, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} \n output io : { flip bypass : UInt<1>, pending : UInt<1>} \n\n\n wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} \n invalidate nodeIn.d.bits.corrupt \n invalidate nodeIn.d.bits.data \n invalidate nodeIn.d.bits.denied \n invalidate nodeIn.d.bits.sink \n invalidate nodeIn.d.bits.source \n invalidate nodeIn.d.bits.size \n invalidate nodeIn.d.bits.param \n invalidate nodeIn.d.bits.opcode \n invalidate nodeIn.d.valid \n invalidate nodeIn.d.ready \n invalidate nodeIn.a.bits.corrupt \n invalidate nodeIn.a.bits.data \n invalidate nodeIn.a.bits.mask \n invalidate nodeIn.a.bits.address \n invalidate nodeIn.a.bits.source \n invalidate nodeIn.a.bits.size \n invalidate nodeIn.a.bits.param \n invalidate nodeIn.a.bits.opcode \n invalidate nodeIn.a.valid \n invalidate nodeIn.a.ready \n inst monitor of TLMonitor_90 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, nodeIn.d.bits.data \n connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink \n connect monitor.io.in.d.bits.source, nodeIn.d.bits.source \n connect monitor.io.in.d.bits.size, nodeIn.d.bits.size \n connect monitor.io.in.d.bits.param, nodeIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode \n connect monitor.io.in.d.valid, nodeIn.d.valid \n connect monitor.io.in.d.ready, nodeIn.d.ready \n connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, nodeIn.a.bits.data \n connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask \n connect monitor.io.in.a.bits.address, nodeIn.a.bits.address \n connect monitor.io.in.a.bits.source, nodeIn.a.bits.source \n connect monitor.io.in.a.bits.size, nodeIn.a.bits.size \n connect monitor.io.in.a.bits.param, nodeIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode \n connect monitor.io.in.a.valid, nodeIn.a.valid \n connect monitor.io.in.a.ready, nodeIn.a.ready \n wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} \n invalidate nodeOut.d.bits.corrupt \n invalidate nodeOut.d.bits.data \n invalidate nodeOut.d.bits.denied \n invalidate nodeOut.d.bits.sink \n invalidate nodeOut.d.bits.source \n invalidate nodeOut.d.bits.size \n invalidate nodeOut.d.bits.param \n invalidate nodeOut.d.bits.opcode \n invalidate nodeOut.d.valid \n invalidate nodeOut.d.ready \n invalidate nodeOut.a.bits.corrupt \n invalidate nodeOut.a.bits.data \n invalidate nodeOut.a.bits.mask \n invalidate nodeOut.a.bits.address \n invalidate nodeOut.a.bits.source \n invalidate nodeOut.a.bits.size \n invalidate nodeOut.a.bits.param \n invalidate nodeOut.a.bits.opcode \n invalidate nodeOut.a.valid \n invalidate nodeOut.a.ready \n wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} \n invalidate x1_nodeOut.d.bits.corrupt \n invalidate x1_nodeOut.d.bits.data \n invalidate x1_nodeOut.d.bits.denied \n invalidate x1_nodeOut.d.bits.sink \n invalidate x1_nodeOut.d.bits.source \n invalidate x1_nodeOut.d.bits.size \n invalidate x1_nodeOut.d.bits.param \n invalidate x1_nodeOut.d.bits.opcode \n invalidate x1_nodeOut.d.valid \n invalidate x1_nodeOut.d.ready \n invalidate x1_nodeOut.a.bits.corrupt \n invalidate x1_nodeOut.a.bits.data \n invalidate x1_nodeOut.a.bits.mask \n invalidate x1_nodeOut.a.bits.address \n invalidate x1_nodeOut.a.bits.source \n invalidate x1_nodeOut.a.bits.size \n invalidate x1_nodeOut.a.bits.param \n invalidate x1_nodeOut.a.bits.opcode \n invalidate x1_nodeOut.a.valid \n invalidate x1_nodeOut.a.ready \n connect auto.out_0, nodeOut \n connect auto.out_1, x1_nodeOut \n connect nodeIn, auto.in \n regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) \n connect in_reset, UInt<1>(0h0) \n reg bypass_reg : UInt<1>, clock \n node bypass = mux(in_reset, io.bypass, bypass_reg) \n regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) \n node _T = and(nodeIn.a.ready, nodeIn.a.valid) \n node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) \n node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) \n node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) \n node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) \n node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) \n node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) \n node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) \n regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) \n node r_counter1 = tail(_r_counter1_T, 1) \n node a_first = eq(r_counter, UInt<1>(0h0)) \n node _r_last_T = eq(r_counter, UInt<1>(0h1)) \n node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) \n node a_last = or(_r_last_T, _r_last_T_1) \n node r_3 = and(a_last, _T) \n node _r_count_T = not(r_counter1) \n node r_4 = and(r_beats1, _r_count_T) \n when _T : \n node _r_counter_T = mux(a_first, r_beats1, r_counter1) \n connect r_counter, _r_counter_T \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<32>(0h0) \n connect _WIRE.bits.mask, UInt<4>(0h0) \n connect _WIRE.bits.address, UInt<9>(0h0) \n connect _WIRE.bits.source, UInt<1>(0h0) \n connect _WIRE.bits.size, UInt<2>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) \n node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) \n node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) \n node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) \n node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) \n node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) \n node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) \n node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) \n regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) \n node r_counter1_1 = tail(_r_counter1_T_1, 1) \n node b_first = eq(r_counter_1, UInt<1>(0h0)) \n node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) \n node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) \n node b_last = or(_r_last_T_2, _r_last_T_3) \n node r_3_1 = and(b_last, _T_1) \n node _r_count_T_1 = not(r_counter1_1) \n node r_4_1 = and(r_beats1_1, _r_count_T_1) \n when _T_1 : \n node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) \n connect r_counter_1, _r_counter_T_1 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<32>(0h0) \n connect _WIRE_2.bits.address, UInt<9>(0h0) \n connect _WIRE_2.bits.source, UInt<1>(0h0) \n connect _WIRE_2.bits.size, UInt<2>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) \n node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) \n node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) \n node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) \n node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) \n node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) \n node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) \n regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) \n node r_counter1_2 = tail(_r_counter1_T_2, 1) \n node c_first = eq(r_counter_2, UInt<1>(0h0)) \n node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) \n node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) \n node c_last = or(_r_last_T_4, _r_last_T_5) \n node r_3_2 = and(c_last, _T_2) \n node _r_count_T_2 = not(r_counter1_2) \n node r_4_2 = and(r_beats1_2, _r_count_T_2) \n when _T_2 : \n node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) \n connect r_counter_2, _r_counter_T_2 \n node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) \n node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) \n node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) \n node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) \n node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) \n node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) \n node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) \n regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) \n node r_counter1_3 = tail(_r_counter1_T_3, 1) \n node d_first = eq(r_counter_3, UInt<1>(0h0)) \n node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) \n node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) \n node d_last = or(_r_last_T_6, _r_last_T_7) \n node r_3_3 = and(d_last, _T_3) \n node _r_count_T_3 = not(r_counter1_3) \n node r_4_3 = and(r_beats1_3, _r_count_T_3) \n when _T_3 : \n node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) \n connect r_counter_3, _r_counter_T_3 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) \n regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) \n node r_counter1_4 = tail(_r_counter1_T_4, 1) \n node e_first = eq(r_counter_4, UInt<1>(0h0)) \n node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) \n node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node e_last = or(_r_last_T_8, _r_last_T_9) \n node r_3_4 = and(e_last, _T_4) \n node _r_count_T_4 = not(r_counter1_4) \n node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) \n when _T_4 : \n node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) \n connect r_counter_4, _r_counter_T_4 \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<32>(0h0) \n connect _WIRE_6.bits.mask, UInt<4>(0h0) \n connect _WIRE_6.bits.address, UInt<9>(0h0) \n connect _WIRE_6.bits.source, UInt<1>(0h0) \n connect _WIRE_6.bits.size, UInt<2>(0h0) \n connect _WIRE_6.bits.param, UInt<2>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<32>(0h0) \n connect _WIRE_8.bits.mask, UInt<4>(0h0) \n connect _WIRE_8.bits.address, UInt<9>(0h0) \n connect _WIRE_8.bits.source, UInt<1>(0h0) \n connect _WIRE_8.bits.size, UInt<2>(0h0) \n connect _WIRE_8.bits.param, UInt<2>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<32>(0h0) \n connect _WIRE_10.bits.address, UInt<9>(0h0) \n connect _WIRE_10.bits.source, UInt<1>(0h0) \n connect _WIRE_10.bits.size, UInt<2>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) \n node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) \n node c_request = and(_T_5, _T_6) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<32>(0h0) \n connect _WIRE_12.bits.address, UInt<9>(0h0) \n connect _WIRE_12.bits.source, UInt<1>(0h0) \n connect _WIRE_12.bits.size, UInt<2>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_8 = eq(_T_7, UInt<1>(0h0)) \n node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n node c_response = or(_T_8, _T_10) \n node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) \n node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n node d_request = and(_T_11, _T_13) \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_14.bits.sink, UInt<1>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_16.bits.sink, UInt<1>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) \n node _a_inc_T_1 = and(_a_inc_T, a_first) \n node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) \n wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _b_inc_WIRE.bits.data, UInt<32>(0h0) \n connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) \n connect _b_inc_WIRE.bits.address, UInt<9>(0h0) \n connect _b_inc_WIRE.bits.source, UInt<1>(0h0) \n connect _b_inc_WIRE.bits.size, UInt<2>(0h0) \n connect _b_inc_WIRE.bits.param, UInt<2>(0h0) \n connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) \n connect _b_inc_WIRE.valid, UInt<1>(0h0) \n connect _b_inc_WIRE.ready, UInt<1>(0h0) \n wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits \n connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid \n connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready \n node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) \n node _b_inc_T_1 = and(_b_inc_T, b_first) \n node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) \n wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_inc_WIRE.bits.data, UInt<32>(0h0) \n connect _c_inc_WIRE.bits.address, UInt<9>(0h0) \n connect _c_inc_WIRE.bits.source, UInt<1>(0h0) \n connect _c_inc_WIRE.bits.size, UInt<2>(0h0) \n connect _c_inc_WIRE.bits.param, UInt<3>(0h0) \n connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_inc_WIRE.valid, UInt<1>(0h0) \n connect _c_inc_WIRE.ready, UInt<1>(0h0) \n wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits \n connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid \n connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready \n node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) \n node _c_inc_T_1 = and(_c_inc_T, c_first) \n node c_inc = and(_c_inc_T_1, c_request) \n node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) \n node _d_inc_T_1 = and(_d_inc_T, d_first) \n node d_inc = and(_d_inc_T_1, d_request) \n wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) \n connect _e_inc_WIRE.valid, UInt<1>(0h0) \n connect _e_inc_WIRE.ready, UInt<1>(0h0) \n wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits \n connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid \n connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready \n node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) \n node _e_inc_T_1 = and(_e_inc_T, e_first) \n node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) \n node inc = cat(a_inc, d_inc) \n node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) \n node _a_dec_T_1 = and(_a_dec_T, a_last) \n node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) \n wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _b_dec_WIRE.bits.data, UInt<32>(0h0) \n connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) \n connect _b_dec_WIRE.bits.address, UInt<9>(0h0) \n connect _b_dec_WIRE.bits.source, UInt<1>(0h0) \n connect _b_dec_WIRE.bits.size, UInt<2>(0h0) \n connect _b_dec_WIRE.bits.param, UInt<2>(0h0) \n connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) \n connect _b_dec_WIRE.valid, UInt<1>(0h0) \n connect _b_dec_WIRE.ready, UInt<1>(0h0) \n wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits \n connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid \n connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready \n node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) \n node _b_dec_T_1 = and(_b_dec_T, b_last) \n node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) \n wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_dec_WIRE.bits.data, UInt<32>(0h0) \n connect _c_dec_WIRE.bits.address, UInt<9>(0h0) \n connect _c_dec_WIRE.bits.source, UInt<1>(0h0) \n connect _c_dec_WIRE.bits.size, UInt<2>(0h0) \n connect _c_dec_WIRE.bits.param, UInt<3>(0h0) \n connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_dec_WIRE.valid, UInt<1>(0h0) \n connect _c_dec_WIRE.ready, UInt<1>(0h0) \n wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits \n connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid \n connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready \n node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) \n node _c_dec_T_1 = and(_c_dec_T, c_last) \n node c_dec = and(_c_dec_T_1, c_response) \n node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) \n node _d_dec_T_1 = and(_d_dec_T, d_last) \n node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) \n wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) \n connect _e_dec_WIRE.valid, UInt<1>(0h0) \n connect _e_dec_WIRE.ready, UInt<1>(0h0) \n wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits \n connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid \n connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready \n node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) \n node _e_dec_T_1 = and(_e_dec_T, e_last) \n node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) \n node dec = cat(a_dec, d_dec) \n node _next_flight_T = bits(inc, 0, 0) \n node _next_flight_T_1 = bits(inc, 1, 1) \n node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) \n node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) \n node _next_flight_T_4 = add(flight, _next_flight_T_3) \n node _next_flight_T_5 = tail(_next_flight_T_4, 1) \n node _next_flight_T_6 = bits(dec, 0, 0) \n node _next_flight_T_7 = bits(dec, 1, 1) \n node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) \n node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) \n node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) \n node next_flight = tail(_next_flight_T_10, 1) \n connect flight, next_flight \n node _io_pending_T = gt(flight, UInt<1>(0h0)) \n connect io.pending, _io_pending_T \n node _T_14 = eq(next_flight, UInt<1>(0h0)) \n node _T_15 = or(in_reset, _T_14) \n when _T_15 : \n connect bypass_reg, io.bypass \n node _stall_T = neq(bypass, io.bypass) \n node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) \n node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) \n node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) \n node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) \n node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) \n node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) \n node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) \n node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) \n regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) \n node stall_counter1 = tail(_stall_counter1_T, 1) \n node stall_first = eq(stall_counter, UInt<1>(0h0)) \n node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) \n node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) \n node stall_last = or(_stall_last_T, _stall_last_T_1) \n node stall_done = and(stall_last, _stall_T_1) \n node _stall_count_T = not(stall_counter1) \n node stall_count = and(stall_beats1, _stall_count_T) \n when _stall_T_1 : \n node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) \n connect stall_counter, _stall_counter_T \n node stall = and(_stall_T, stall_first) \n node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) \n node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) \n node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) \n connect nodeOut.a.valid, _nodeOut_a_valid_T_2 \n node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) \n node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) \n node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) \n node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) \n connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 \n node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) \n node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) \n node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) \n connect nodeIn.a.ready, _nodeIn_a_ready_T_2 \n connect nodeOut.a.bits, nodeIn.a.bits \n connect x1_nodeOut.a.bits, nodeIn.a.bits \n node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) \n connect nodeOut.d.ready, _nodeOut_d_ready_T \n node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) \n node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) \n connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 \n node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) \n connect nodeIn.d.valid, _nodeIn_d_valid_T \n wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} \n connect nodeIn_d_bits_out, nodeIn.d.bits \n connect nodeIn_d_bits_out, nodeOut.d.bits \n wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} \n connect nodeIn_d_bits_out_1, nodeIn.d.bits \n connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits \n node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) \n connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt \n connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data \n connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied \n connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink \n connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source \n connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size \n connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param \n connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<32>(0h0) \n connect _WIRE_18.bits.mask, UInt<4>(0h0) \n connect _WIRE_18.bits.address, UInt<9>(0h0) \n connect _WIRE_18.bits.source, UInt<1>(0h0) \n connect _WIRE_18.bits.size, UInt<2>(0h0) \n connect _WIRE_18.bits.param, UInt<2>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n connect _WIRE_19.valid, UInt<1>(0h0) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<32>(0h0) \n connect _WIRE_20.bits.address, UInt<9>(0h0) \n connect _WIRE_20.bits.source, UInt<1>(0h0) \n connect _WIRE_20.bits.size, UInt<2>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n connect _WIRE_21.ready, UInt<1>(0h1) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_22.bits.sink, UInt<1>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n connect _WIRE_23.ready, UInt<1>(0h1) \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<32>(0h0) \n connect _WIRE_24.bits.mask, UInt<4>(0h0) \n connect _WIRE_24.bits.address, UInt<128>(0h0) \n connect _WIRE_24.bits.source, UInt<1>(0h0) \n connect _WIRE_24.bits.size, UInt<2>(0h0) \n connect _WIRE_24.bits.param, UInt<2>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n connect _WIRE_25.ready, UInt<1>(0h1) \n wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_26.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_26.bits.data, UInt<32>(0h0) \n connect _WIRE_26.bits.address, UInt<128>(0h0) \n connect _WIRE_26.bits.source, UInt<1>(0h0) \n connect _WIRE_26.bits.size, UInt<2>(0h0) \n connect _WIRE_26.bits.param, UInt<3>(0h0) \n connect _WIRE_26.bits.opcode, UInt<3>(0h0) \n connect _WIRE_26.valid, UInt<1>(0h0) \n connect _WIRE_26.ready, UInt<1>(0h0) \n wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_27.bits, _WIRE_26.bits \n connect _WIRE_27.valid, _WIRE_26.valid \n connect _WIRE_27.ready, _WIRE_26.ready \n connect _WIRE_27.valid, UInt<1>(0h0) \n wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_28.bits.sink, UInt<1>(0h0) \n connect _WIRE_28.valid, UInt<1>(0h0) \n connect _WIRE_28.ready, UInt<1>(0h0) \n wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_29.bits, _WIRE_28.bits \n connect _WIRE_29.valid, _WIRE_28.valid \n connect _WIRE_29.ready, _WIRE_28.ready \n connect _WIRE_29.valid, UInt<1>(0h0) \n wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_30.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_30.bits.data, UInt<32>(0h0) \n connect _WIRE_30.bits.mask, UInt<4>(0h0) \n connect _WIRE_30.bits.address, UInt<9>(0h0) \n connect _WIRE_30.bits.source, UInt<1>(0h0) \n connect _WIRE_30.bits.size, UInt<2>(0h0) \n connect _WIRE_30.bits.param, UInt<2>(0h0) \n connect _WIRE_30.bits.opcode, UInt<3>(0h0) \n connect _WIRE_30.valid, UInt<1>(0h0) \n connect _WIRE_30.ready, UInt<1>(0h0) \n wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_31.bits, _WIRE_30.bits \n connect _WIRE_31.valid, _WIRE_30.valid \n connect _WIRE_31.ready, _WIRE_30.ready \n connect _WIRE_31.ready, UInt<1>(0h1) \n wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_32.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_32.bits.data, UInt<32>(0h0) \n connect _WIRE_32.bits.address, UInt<9>(0h0) \n connect _WIRE_32.bits.source, UInt<1>(0h0) \n connect _WIRE_32.bits.size, UInt<2>(0h0) \n connect _WIRE_32.bits.param, UInt<3>(0h0) \n connect _WIRE_32.bits.opcode, UInt<3>(0h0) \n connect _WIRE_32.valid, UInt<1>(0h0) \n connect _WIRE_32.ready, UInt<1>(0h0) \n wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_33.bits, _WIRE_32.bits \n connect _WIRE_33.valid, _WIRE_32.valid \n connect _WIRE_33.ready, _WIRE_32.ready \n connect _WIRE_33.valid, UInt<1>(0h0) \n wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_34.bits.sink, UInt<1>(0h0) \n connect _WIRE_34.valid, UInt<1>(0h0) \n connect _WIRE_34.ready, UInt<1>(0h0) \n wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_35.bits, _WIRE_34.bits \n connect _WIRE_35.valid, _WIRE_34.valid \n connect _WIRE_35.ready, _WIRE_34.ready \n connect _WIRE_35.valid, UInt<1>(0h0) \n\n\n extmodule plusarg_reader_183 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32\n\n\n\n extmodule plusarg_reader_184 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32"},"response":{"kind":"string","value":"module TLBusBypassBar(\t// @[BusBypass.scala:66:9]\n input clock,\t// @[BusBypass.scala:66:9]\n input reset,\t// @[BusBypass.scala:66:9]\n output auto_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [8:0] auto_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_1_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [8:0] auto_out_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_1_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_1_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_1_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [127:0] auto_out_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_0_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input io_bypass\t// @[BusBypass.scala:67:16]\n);\n\n wire auto_in_a_valid_0 = auto_in_a_valid;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode;\t// @[BusBypass.scala:66:9]\n wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address;\t// @[BusBypass.scala:66:9]\n wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data;\t// @[BusBypass.scala:66:9]\n wire auto_in_d_ready_0 = auto_in_d_ready;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_a_ready_0 = auto_out_1_a_ready;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_d_valid_0 = auto_out_1_d_valid;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode;\t// @[BusBypass.scala:66:9]\n wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param;\t// @[BusBypass.scala:66:9]\n wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied;\t// @[BusBypass.scala:66:9]\n wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_a_ready_0 = auto_out_0_a_ready;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_d_valid_0 = auto_out_0_d_valid;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode;\t// @[BusBypass.scala:66:9]\n wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param;\t// @[BusBypass.scala:66:9]\n wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt;\t// @[BusBypass.scala:66:9]\n wire io_bypass_0 = io_bypass;\t// @[BusBypass.scala:66:9]\n wire [4:0] _r_beats1_decode_T_3 = 5'h3;\t// @[package.scala:243:71]\n wire [4:0] _r_beats1_decode_T_6 = 5'h3;\t// @[package.scala:243:71]\n wire [3:0] _b_inc_WIRE_bits_mask = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _b_dec_WIRE_bits_mask = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0;\t// @[Bundles.scala:264:61]\n wire [8:0] _b_inc_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:264:74]\n wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:264:61]\n wire [8:0] _c_inc_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _b_dec_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:264:74]\n wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:264:61]\n wire [8:0] _c_dec_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _r_beats1_decode_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _stall_beats1_decode_T = 5'hC;\t// @[package.scala:243:71]\n wire [1:0] _r_beats1_decode_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _r_beats1_decode_T_5 = 2'h0;\t// @[package.scala:243:46]\n wire [1:0] _r_beats1_decode_T_8 = 2'h0;\t// @[package.scala:243:46]\n wire [1:0] _b_inc_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _b_inc_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _c_inc_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _b_dec_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _b_dec_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _c_dec_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _stall_beats1_decode_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [31:0] auto_out_0_d_bits_data = 32'h0;\t// @[BusBypass.scala:66:9]\n wire [31:0] nodeOut_d_bits_data = 32'h0;\t// @[MixedNode.scala:542:17]\n wire [31:0] _b_inc_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _c_inc_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _b_dec_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _c_dec_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] nodeIn_d_bits_out_data = 32'h0;\t// @[BusBypass.scala:97:53]\n wire [3:0] auto_in_a_bits_mask = 4'hF;\t// @[Nodes.scala:27:25]\n wire [3:0] auto_out_1_a_bits_mask = 4'hF;\t// @[Nodes.scala:27:25]\n wire [3:0] auto_out_0_a_bits_mask = 4'hF;\t// @[Nodes.scala:27:25]\n wire [3:0] nodeIn_a_bits_mask = 4'hF;\t// @[Nodes.scala:27:25]\n wire [3:0] nodeOut_a_bits_mask = 4'hF;\t// @[Nodes.scala:27:25]\n wire [3:0] x1_nodeOut_a_bits_mask = 4'hF;\t// @[Nodes.scala:27:25]\n wire [1:0] auto_in_a_bits_size = 2'h2;\t// @[Nodes.scala:27:25]\n wire [1:0] auto_out_1_a_bits_size = 2'h2;\t// @[Nodes.scala:27:25]\n wire [1:0] auto_out_0_a_bits_size = 2'h2;\t// @[Nodes.scala:27:25]\n wire [1:0] nodeIn_a_bits_size = 2'h2;\t// @[Nodes.scala:27:25]\n wire [1:0] nodeOut_a_bits_size = 2'h2;\t// @[Nodes.scala:27:25]\n wire [1:0] x1_nodeOut_a_bits_size = 2'h2;\t// @[Nodes.scala:27:25]\n wire [2:0] auto_in_a_bits_param = 3'h0;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_out_1_a_bits_param = 3'h0;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_out_0_a_bits_param = 3'h0;\t// @[BusBypass.scala:66:9]\n wire [2:0] nodeIn_a_bits_param = 3'h0;\t// @[MixedNode.scala:551:17]\n wire [2:0] nodeOut_a_bits_param = 3'h0;\t// @[MixedNode.scala:542:17]\n wire [2:0] x1_nodeOut_a_bits_param = 3'h0;\t// @[MixedNode.scala:542:17]\n wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_inc_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_dec_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _r_beats1_decode_T_2 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _r_beats1_decode_T_4 = 2'h3;\t// @[package.scala:243:76]\n wire [1:0] _r_counter1_T_1 = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] _r_beats1_decode_T_7 = 2'h3;\t// @[package.scala:243:76]\n wire [1:0] _r_counter1_T_2 = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] _r_counter1_T_4 = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] _stall_beats1_decode_T_2 = 2'h3;\t// @[package.scala:243:46]\n wire _r_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_last = 1'h1;\t// @[Edges.scala:232:33]\n wire r_beats1_opdata_1 = 1'h1;\t// @[Edges.scala:97:28]\n wire r_counter1_1 = 1'h1;\t// @[Edges.scala:230:28]\n wire b_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _r_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire b_last = 1'h1;\t// @[Edges.scala:232:33]\n wire r_counter1_2 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _r_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _r_last_T_7 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_last = 1'h1;\t// @[Edges.scala:232:33]\n wire r_counter1_4 = 1'h1;\t// @[Edges.scala:230:28]\n wire e_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _r_last_T_9 = 1'h1;\t// @[Edges.scala:232:43]\n wire e_last = 1'h1;\t// @[Edges.scala:232:33]\n wire c_response = 1'h1;\t// @[Edges.scala:82:41]\n wire _stall_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire stall_last = 1'h1;\t// @[Edges.scala:232:33]\n wire auto_in_a_bits_source = 1'h0;\t// @[BusBypass.scala:66:9]\n wire auto_in_a_bits_corrupt = 1'h0;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_a_bits_source = 1'h0;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_a_bits_corrupt = 1'h0;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_a_bits_source = 1'h0;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_a_bits_corrupt = 1'h0;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_d_bits_source = 1'h0;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_d_bits_sink = 1'h0;\t// @[BusBypass.scala:66:9]\n wire nodeIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_a_bits_source = 1'h0;\t// @[MixedNode.scala:551:17]\n wire nodeIn_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:551:17]\n wire nodeOut_a_bits_source = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_bits_source = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_bits_sink = 1'h0;\t// @[MixedNode.scala:542:17]\n wire x1_nodeOut_a_bits_source = 1'h0;\t// @[MixedNode.scala:542:17]\n wire x1_nodeOut_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire r_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire r_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire r_4 = 1'h0;\t// @[Edges.scala:234:25]\n wire r_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire _r_beats1_opdata_T_1 = 1'h0;\t// @[Edges.scala:97:37]\n wire r_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _r_last_T_2 = 1'h0;\t// @[Edges.scala:232:25]\n wire r_3_1 = 1'h0;\t// @[Edges.scala:233:22]\n wire _r_count_T_1 = 1'h0;\t// @[Edges.scala:234:27]\n wire r_4_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire _r_counter_T_1 = 1'h0;\t// @[Edges.scala:236:21]\n wire r_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire r_beats1_opdata_2 = 1'h0;\t// @[Edges.scala:102:36]\n wire r_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire _r_last_T_4 = 1'h0;\t// @[Edges.scala:232:25]\n wire r_3_2 = 1'h0;\t// @[Edges.scala:233:22]\n wire _r_count_T_2 = 1'h0;\t// @[Edges.scala:234:27]\n wire r_4_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire _r_counter_T_2 = 1'h0;\t// @[Edges.scala:236:21]\n wire r_beats1_decode_3 = 1'h0;\t// @[Edges.scala:220:59]\n wire r_beats1_3 = 1'h0;\t// @[Edges.scala:221:14]\n wire r_4_3 = 1'h0;\t// @[Edges.scala:234:25]\n wire _r_last_T_8 = 1'h0;\t// @[Edges.scala:232:25]\n wire r_3_4 = 1'h0;\t// @[Edges.scala:233:22]\n wire _r_count_T_4 = 1'h0;\t// @[Edges.scala:234:27]\n wire r_4_4 = 1'h0;\t// @[Edges.scala:234:25]\n wire _r_counter_T_4 = 1'h0;\t// @[Edges.scala:236:21]\n wire c_request = 1'h0;\t// @[Edges.scala:68:40]\n wire _b_inc_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_inc_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_inc_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_inc_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_inc_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_inc_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_inc_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_inc_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_inc_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire _b_inc_T_1 = 1'h0;\t// @[Edges.scala:311:26]\n wire b_inc = 1'h0;\t// @[Edges.scala:311:37]\n wire _c_inc_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_inc_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_inc_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_inc_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_inc_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_inc_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_inc_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_inc_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_inc_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire _c_inc_T_1 = 1'h0;\t// @[Edges.scala:312:26]\n wire c_inc = 1'h0;\t// @[Edges.scala:312:37]\n wire _e_inc_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _e_inc_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _e_inc_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _e_inc_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _e_inc_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _e_inc_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire _e_inc_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire _e_inc_T_1 = 1'h0;\t// @[Edges.scala:314:26]\n wire e_inc = 1'h0;\t// @[Edges.scala:314:37]\n wire a_dec = 1'h0;\t// @[Edges.scala:317:36]\n wire _b_dec_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_dec_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_dec_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_dec_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _b_dec_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_dec_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_dec_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_dec_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire _b_dec_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire _b_dec_T_1 = 1'h0;\t// @[Edges.scala:318:26]\n wire b_dec = 1'h0;\t// @[Edges.scala:318:36]\n wire _c_dec_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_dec_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_dec_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_dec_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_dec_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_dec_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_dec_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_dec_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_dec_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire _c_dec_T_1 = 1'h0;\t// @[Edges.scala:319:26]\n wire c_dec = 1'h0;\t// @[Edges.scala:319:36]\n wire _e_dec_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _e_dec_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _e_dec_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _e_dec_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _e_dec_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _e_dec_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire _e_dec_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire _e_dec_T_1 = 1'h0;\t// @[Edges.scala:321:26]\n wire e_dec = 1'h0;\t// @[Edges.scala:321:36]\n wire stall_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire stall_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire stall_count = 1'h0;\t// @[Edges.scala:234:25]\n wire nodeIn_d_bits_out_source = 1'h0;\t// @[BusBypass.scala:97:53]\n wire nodeIn_d_bits_out_sink = 1'h0;\t// @[BusBypass.scala:97:53]\n wire nodeIn_a_valid = auto_in_a_valid_0;\t// @[BusBypass.scala:66:9]\n wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0;\t// @[BusBypass.scala:66:9]\n wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0;\t// @[BusBypass.scala:66:9]\n wire nodeIn_d_ready = auto_in_d_ready_0;\t// @[BusBypass.scala:66:9]\n wire nodeIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] nodeIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [31:0] nodeIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire x1_nodeOut_a_ready = auto_out_1_a_ready_0;\t// @[BusBypass.scala:66:9]\n wire x1_nodeOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] x1_nodeOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [8:0] x1_nodeOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [31:0] x1_nodeOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire x1_nodeOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire x1_nodeOut_d_valid = auto_out_1_d_valid_0;\t// @[BusBypass.scala:66:9]\n wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0;\t// @[BusBypass.scala:66:9]\n wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0;\t// @[BusBypass.scala:66:9]\n wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0;\t// @[BusBypass.scala:66:9]\n wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0;\t// @[BusBypass.scala:66:9]\n wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0;\t// @[BusBypass.scala:66:9]\n wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0;\t// @[BusBypass.scala:66:9]\n wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0;\t// @[BusBypass.scala:66:9]\n wire nodeOut_a_ready = auto_out_0_a_ready_0;\t// @[BusBypass.scala:66:9]\n wire nodeOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [127:0] nodeOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_valid = auto_out_0_d_valid_0;\t// @[BusBypass.scala:66:9]\n wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0;\t// @[BusBypass.scala:66:9]\n wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0;\t// @[BusBypass.scala:66:9]\n wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0;\t// @[BusBypass.scala:66:9]\n wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0;\t// @[BusBypass.scala:66:9]\n wire _io_pending_T;\t// @[BusBypass.scala:84:27]\n wire auto_in_a_ready_0;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_in_d_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n wire [1:0] auto_in_d_bits_param_0;\t// @[BusBypass.scala:66:9]\n wire [1:0] auto_in_d_bits_size_0;\t// @[BusBypass.scala:66:9]\n wire auto_in_d_bits_source_0;\t// @[BusBypass.scala:66:9]\n wire auto_in_d_bits_sink_0;\t// @[BusBypass.scala:66:9]\n wire auto_in_d_bits_denied_0;\t// @[BusBypass.scala:66:9]\n wire [31:0] auto_in_d_bits_data_0;\t// @[BusBypass.scala:66:9]\n wire auto_in_d_bits_corrupt_0;\t// @[BusBypass.scala:66:9]\n wire auto_in_d_valid_0;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_out_1_a_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n wire [8:0] auto_out_1_a_bits_address_0;\t// @[BusBypass.scala:66:9]\n wire [31:0] auto_out_1_a_bits_data_0;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_a_valid_0;\t// @[BusBypass.scala:66:9]\n wire auto_out_1_d_ready_0;\t// @[BusBypass.scala:66:9]\n wire [2:0] auto_out_0_a_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n wire [127:0] auto_out_0_a_bits_address_0;\t// @[BusBypass.scala:66:9]\n wire [31:0] auto_out_0_a_bits_data_0;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_a_valid_0;\t// @[BusBypass.scala:66:9]\n wire auto_out_0_d_ready_0;\t// @[BusBypass.scala:66:9]\n wire io_pending;\t// @[BusBypass.scala:66:9]\n wire _nodeIn_a_ready_T_2;\t// @[BusBypass.scala:90:28]\n assign auto_in_a_ready_0 = nodeIn_a_ready;\t// @[BusBypass.scala:66:9]\n assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n assign nodeOut_a_bits_data = nodeIn_a_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n wire _nodeIn_d_valid_T;\t// @[BusBypass.scala:96:24]\n assign auto_in_d_valid_0 = nodeIn_d_valid;\t// @[BusBypass.scala:66:9]\n wire [2:0] _nodeIn_d_bits_T_opcode;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode;\t// @[BusBypass.scala:66:9]\n wire [1:0] _nodeIn_d_bits_T_param;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_param_0 = nodeIn_d_bits_param;\t// @[BusBypass.scala:66:9]\n wire [1:0] _nodeIn_d_bits_T_size;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_size_0 = nodeIn_d_bits_size;\t// @[BusBypass.scala:66:9]\n wire _nodeIn_d_bits_T_source;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_source_0 = nodeIn_d_bits_source;\t// @[BusBypass.scala:66:9]\n wire _nodeIn_d_bits_T_sink;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink;\t// @[BusBypass.scala:66:9]\n wire _nodeIn_d_bits_T_denied;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied;\t// @[BusBypass.scala:66:9]\n wire [31:0] _nodeIn_d_bits_T_data;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_data_0 = nodeIn_d_bits_data;\t// @[BusBypass.scala:66:9]\n wire _nodeIn_d_bits_T_corrupt;\t// @[BusBypass.scala:98:21]\n assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt;\t// @[BusBypass.scala:66:9]\n wire _nodeOut_a_valid_T_2;\t// @[BusBypass.scala:88:42]\n assign auto_out_0_a_valid_0 = nodeOut_a_valid;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data;\t// @[BusBypass.scala:66:9]\n wire _nodeOut_d_ready_T;\t// @[BusBypass.scala:94:32]\n assign auto_out_0_d_ready_0 = nodeOut_d_ready;\t// @[BusBypass.scala:66:9]\n wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode;\t// @[BusBypass.scala:97:53]\n wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param;\t// @[BusBypass.scala:97:53]\n wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size;\t// @[BusBypass.scala:97:53]\n wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied;\t// @[BusBypass.scala:97:53]\n wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt;\t// @[BusBypass.scala:97:53]\n wire _nodeOut_a_valid_T_6;\t// @[BusBypass.scala:89:42]\n assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data;\t// @[BusBypass.scala:66:9]\n wire _nodeOut_d_ready_T_2;\t// @[BusBypass.scala:95:32]\n assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready;\t// @[BusBypass.scala:66:9]\n wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode;\t// @[BusBypass.scala:97:53]\n wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param;\t// @[BusBypass.scala:97:53]\n wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size;\t// @[BusBypass.scala:97:53]\n wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source;\t// @[BusBypass.scala:97:53]\n wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink;\t// @[BusBypass.scala:97:53]\n wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied;\t// @[BusBypass.scala:97:53]\n wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data;\t// @[BusBypass.scala:97:53]\n wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt;\t// @[BusBypass.scala:97:53]\n reg in_reset;\t// @[BusBypass.scala:79:27]\n reg bypass_reg;\t// @[BusBypass.scala:80:25]\n wire bypass = in_reset ? io_bypass_0 : bypass_reg;\t// @[BusBypass.scala:66:9, :79:27, :80:25, :81:21]\n reg [1:0] flight;\t// @[Edges.scala:295:25]\n wire _T = nodeIn_a_ready & nodeIn_a_valid;\t// @[Decoupled.scala:51:35]\n wire r_3;\t// @[Edges.scala:233:22]\n assign r_3 = _T;\t// @[Decoupled.scala:51:35]\n wire _a_inc_T;\t// @[Decoupled.scala:51:35]\n assign _a_inc_T = _T;\t// @[Decoupled.scala:51:35]\n wire _a_dec_T;\t// @[Decoupled.scala:51:35]\n assign _a_dec_T = _T;\t// @[Decoupled.scala:51:35]\n wire _stall_T_1;\t// @[Decoupled.scala:51:35]\n assign _stall_T_1 = _T;\t// @[Decoupled.scala:51:35]\n wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire r_beats1_opdata = ~_r_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg r_counter;\t// @[Edges.scala:229:27]\n wire _r_last_T = r_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire r_counter1 = _r_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~r_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _r_count_T = ~r_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _r_counter_T = ~a_first & r_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire _T_3 = nodeIn_d_ready & nodeIn_d_valid;\t// @[Decoupled.scala:51:35]\n wire r_3_3;\t// @[Edges.scala:233:22]\n assign r_3_3 = _T_3;\t// @[Decoupled.scala:51:35]\n wire _d_inc_T;\t// @[Decoupled.scala:51:35]\n assign _d_inc_T = _T_3;\t// @[Decoupled.scala:51:35]\n wire _d_dec_T;\t// @[Decoupled.scala:51:35]\n assign _d_dec_T = _T_3;\t// @[Decoupled.scala:51:35]\n wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size;\t// @[package.scala:243:71]\n wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10;\t// @[package.scala:243:{46,76}]\n wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0];\t// @[Edges.scala:106:36]\n reg r_counter_3;\t// @[Edges.scala:229:27]\n wire _r_last_T_6 = r_counter_3;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire r_counter1_3 = _r_counter1_T_3[0];\t// @[Edges.scala:230:28]\n wire d_first = ~r_counter_3;\t// @[Edges.scala:229:27, :231:25]\n wire _r_count_T_3 = ~r_counter1_3;\t// @[Edges.scala:230:28, :234:27]\n wire _r_counter_T_3 = ~d_first & r_counter1_3;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]);\t// @[Edges.scala:71:{36,40,43,52}]\n wire _a_inc_T_1 = _a_inc_T & a_first;\t// @[Decoupled.scala:51:35]\n wire a_inc = _a_inc_T_1;\t// @[Edges.scala:310:{26,37}]\n wire _d_inc_T_1 = _d_inc_T & d_first;\t// @[Decoupled.scala:51:35]\n wire d_inc = _d_inc_T_1 & d_request;\t// @[Edges.scala:71:40, :313:{26,37}]\n wire [1:0] inc = {a_inc, d_inc};\t// @[Edges.scala:310:37, :313:37, :315:18]\n wire _a_dec_T_1 = _a_dec_T;\t// @[Decoupled.scala:51:35]\n wire _d_dec_T_1 = _d_dec_T;\t// @[Decoupled.scala:51:35]\n wire d_dec = _d_dec_T_1;\t// @[Edges.scala:320:{26,36}]\n wire [1:0] dec = {1'h0, d_dec};\t// @[Edges.scala:320:36, :322:18]\n wire _next_flight_T = inc[0];\t// @[Edges.scala:315:18, :324:40]\n wire _next_flight_T_1 = inc[1];\t// @[Edges.scala:315:18, :324:40]\n wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1};\t// @[Edges.scala:324:40]\n wire [1:0] _next_flight_T_3 = _next_flight_T_2;\t// @[Edges.scala:324:40]\n wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3};\t// @[Edges.scala:295:25, :324:{30,40}]\n wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0];\t// @[Edges.scala:324:30]\n wire _next_flight_T_6 = dec[0];\t// @[Edges.scala:322:18, :324:56]\n wire _next_flight_T_7 = dec[1];\t// @[Edges.scala:322:18, :324:56]\n wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7};\t// @[Edges.scala:324:56]\n wire [1:0] _next_flight_T_9 = _next_flight_T_8;\t// @[Edges.scala:324:56]\n wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9};\t// @[Edges.scala:324:{30,46,56}]\n wire [1:0] next_flight = _next_flight_T_10[1:0];\t// @[Edges.scala:324:46]\n assign _io_pending_T = |flight;\t// @[Edges.scala:295:25]\n assign io_pending = _io_pending_T;\t// @[BusBypass.scala:66:9, :84:27]\n wire _stall_T = bypass != io_bypass_0;\t// @[BusBypass.scala:66:9, :81:21, :86:25]\n wire stall_done = _stall_T_1;\t// @[Decoupled.scala:51:35]\n wire stall_beats1_opdata = ~_stall_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg stall_counter;\t// @[Edges.scala:229:27]\n wire _stall_last_T = stall_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire stall_counter1 = _stall_counter1_T[0];\t// @[Edges.scala:230:28]\n wire stall_first = ~stall_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _stall_count_T = ~stall_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _stall_counter_T = ~stall_first & stall_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire stall = _stall_T & stall_first;\t// @[Edges.scala:231:25]\n wire _nodeOut_a_valid_T = ~stall;\t// @[BusBypass.scala:86:40, :88:21]\n wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid;\t// @[BusBypass.scala:88:{21,28}]\n assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass;\t// @[BusBypass.scala:81:21, :88:{28,42}]\n assign nodeOut_a_valid = _nodeOut_a_valid_T_2;\t// @[BusBypass.scala:88:42]\n wire _nodeOut_a_valid_T_3 = ~stall;\t// @[BusBypass.scala:86:40, :88:21, :89:21]\n wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid;\t// @[BusBypass.scala:89:{21,28}]\n wire _nodeOut_a_valid_T_5 = ~bypass;\t// @[BusBypass.scala:81:21, :89:45]\n assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5;\t// @[BusBypass.scala:89:{28,42,45}]\n assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6;\t// @[BusBypass.scala:89:42]\n wire _nodeIn_a_ready_T = ~stall;\t// @[BusBypass.scala:86:40, :88:21, :90:21]\n wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready;\t// @[BusBypass.scala:81:21, :90:34]\n assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1;\t// @[BusBypass.scala:90:{21,28,34}]\n assign nodeIn_a_ready = _nodeIn_a_ready_T_2;\t// @[BusBypass.scala:90:28]\n assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address};\t// @[BusBypass.scala:91:18]\n assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass;\t// @[BusBypass.scala:81:21, :94:32]\n assign nodeOut_d_ready = _nodeOut_d_ready_T;\t// @[BusBypass.scala:94:32]\n wire _nodeOut_d_ready_T_1 = ~bypass;\t// @[BusBypass.scala:81:21, :89:45, :95:35]\n assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1;\t// @[BusBypass.scala:95:{32,35}]\n assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2;\t// @[BusBypass.scala:95:32]\n assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid;\t// @[BusBypass.scala:81:21, :96:24]\n assign nodeIn_d_valid = _nodeIn_d_valid_T;\t// @[BusBypass.scala:96:24]\n assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt;\t// @[BusBypass.scala:81:21, :97:53, :98:21]\n assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode;\t// @[BusBypass.scala:98:21]\n assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param;\t// @[BusBypass.scala:98:21]\n assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size;\t// @[BusBypass.scala:98:21]\n assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source;\t// @[BusBypass.scala:98:21]\n assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink;\t// @[BusBypass.scala:98:21]\n assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied;\t// @[BusBypass.scala:98:21]\n assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data;\t// @[BusBypass.scala:98:21]\n assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt;\t// @[BusBypass.scala:98:21]\n always @(posedge clock) begin\t// @[BusBypass.scala:66:9]\n if (reset) begin\t// @[BusBypass.scala:66:9]\n in_reset <= 1'h1;\t// @[BusBypass.scala:79:27]\n flight <= 2'h0;\t// @[Edges.scala:295:25]\n r_counter <= 1'h0;\t// @[Edges.scala:229:27]\n r_counter_3 <= 1'h0;\t// @[Edges.scala:229:27]\n stall_counter <= 1'h0;\t// @[Edges.scala:229:27]\n end\n else begin\t// @[BusBypass.scala:66:9]\n in_reset <= 1'h0;\t// @[BusBypass.scala:79:27]\n flight <= next_flight;\t// @[Edges.scala:295:25, :324:46]\n if (_T)\t// @[Decoupled.scala:51:35]\n r_counter <= _r_counter_T;\t// @[Edges.scala:229:27, :236:21]\n if (_T_3)\t// @[Decoupled.scala:51:35]\n r_counter_3 <= _r_counter_T_3;\t// @[Edges.scala:229:27, :236:21]\n if (_stall_T_1)\t// @[Decoupled.scala:51:35]\n stall_counter <= _stall_counter_T;\t// @[Edges.scala:229:27, :236:21]\n end\n if (in_reset | next_flight == 2'h0)\t// @[Edges.scala:324:46]\n bypass_reg <= io_bypass_0;\t// @[BusBypass.scala:66:9, :80:25]\n always @(posedge)\n TLMonitor_90 monitor (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (nodeIn_a_ready),\t// @[MixedNode.scala:551:17]\n .io_in_a_valid (nodeIn_a_valid),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_opcode (nodeIn_a_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_address (nodeIn_a_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_data (nodeIn_a_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_ready (nodeIn_d_ready),\t// @[MixedNode.scala:551:17]\n .io_in_d_valid (nodeIn_d_valid),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_opcode (nodeIn_d_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_param (nodeIn_d_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_size (nodeIn_d_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_source (nodeIn_d_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_sink (nodeIn_d_bits_sink),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_denied (nodeIn_d_bits_denied),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_data (nodeIn_d_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt)\t// @[MixedNode.scala:551:17]\n );\t// @[Nodes.scala:27:25]\n assign auto_in_a_ready = auto_in_a_ready_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_valid = auto_in_d_valid_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_param = auto_in_d_bits_param_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_size = auto_in_d_bits_size_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_source = auto_in_d_bits_source_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_sink = auto_in_d_bits_sink_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_denied = auto_in_d_bits_denied_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_data = auto_in_d_bits_data_0;\t// @[BusBypass.scala:66:9]\n assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_a_valid = auto_out_1_a_valid_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_1_d_ready = auto_out_1_d_ready_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_a_valid = auto_out_0_a_valid_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0;\t// @[BusBypass.scala:66:9]\n assign auto_out_0_d_ready = auto_out_0_d_ready_0;\t// @[BusBypass.scala:66:9]\nendmodule"}}},{"rowIdx":32152,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_TLBundleD_a32d64s2k3z4c : \n input clock : Clock \n input reset : Reset \n output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, async : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} \n\n\n wire sink_ready : UInt<1> \n connect sink_ready, UInt<1>(0h1) \n reg mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], clock \n node _widx_T = asAsyncReset(reset) \n node _widx_T_1 = and(io.enq.ready, io.enq.valid) \n node _widx_T_2 = eq(sink_ready, UInt<1>(0h0)) \n wire widx_incremented : UInt<4> \n regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0) \n connect widx_widx_bin, widx_incremented \n node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) \n node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) \n node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1) \n connect widx_incremented, _widx_incremented_T_2 \n node _widx_T_3 = shr(widx_incremented, 1) \n node widx = xor(widx_incremented, _widx_T_3) \n inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_3 \n connect ridx_ridx_gray.clock, clock\n\n connect ridx_ridx_gray.reset, reset\n\n connect ridx_ridx_gray.io.d, io.async.ridx \n wire ridx : UInt<4> \n connect ridx, ridx_ridx_gray.io.q \n node _ready_T = xor(ridx, UInt<4>(0hc)) \n node _ready_T_1 = neq(widx, _ready_T) \n node ready = and(sink_ready, _ready_T_1) \n node _index_T = bits(io.async.widx, 2, 0) \n node _index_T_1 = bits(io.async.widx, 3, 3) \n node _index_T_2 = shl(_index_T_1, 2) \n node index = xor(_index_T, _index_T_2) \n node _T = and(io.enq.ready, io.enq.valid) \n when _T : \n connect mem[index], io.enq.bits \n node _ready_reg_T = asAsyncReset(reset) \n regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0) \n connect ready_reg, ready \n node _io_enq_ready_T = and(ready_reg, sink_ready) \n connect io.enq.ready, _io_enq_ready_T \n node _widx_reg_T = asAsyncReset(reset) \n regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0) \n connect widx_gray, widx \n connect io.async.widx, widx_gray \n connect io.async.mem, mem \n inst source_valid_0 of AsyncValidSync_12 \n inst source_valid_1 of AsyncValidSync_13 \n inst sink_extend of AsyncValidSync_14 \n inst sink_valid of AsyncValidSync_15 \n node _source_valid_0_reset_T = asUInt(reset) \n node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) \n node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) \n node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) \n connect source_valid_0.reset, _source_valid_0_reset_T_3 \n node _source_valid_1_reset_T = asUInt(reset) \n node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) \n node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) \n node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) \n connect source_valid_1.reset, _source_valid_1_reset_T_3 \n node _sink_extend_reset_T = asUInt(reset) \n node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) \n node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) \n node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) \n connect sink_extend.reset, _sink_extend_reset_T_3 \n node _sink_valid_reset_T = asAsyncReset(reset) \n connect sink_valid.reset, _sink_valid_reset_T \n connect source_valid_0.clock, clock \n connect source_valid_1.clock, clock \n connect sink_extend.clock, clock \n connect sink_valid.clock, clock \n connect source_valid_0.io.in, UInt<1>(0h1) \n connect source_valid_1.io.in, source_valid_0.io.out \n connect io.async.safe.widx_valid, source_valid_1.io.out \n connect sink_extend.io.in, io.async.safe.ridx_valid \n connect sink_valid.io.in, sink_extend.io.out \n connect sink_ready, sink_valid.io.out \n node _io_async_safe_source_reset_n_T = asUInt(reset) \n node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0)) \n connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1"},"response":{"kind":"string","value":"module AsyncQueueSource_TLBundleD_a32d64s2k3z4c(\t// @[AsyncQueue.scala:70:7]\n input clock,\t// @[AsyncQueue.scala:70:7]\n input reset,\t// @[AsyncQueue.scala:70:7]\n output io_enq_ready,\t// @[AsyncQueue.scala:73:14]\n input io_enq_valid,\t// @[AsyncQueue.scala:73:14]\n input [2:0] io_enq_bits_opcode,\t// @[AsyncQueue.scala:73:14]\n input [1:0] io_enq_bits_param,\t// @[AsyncQueue.scala:73:14]\n input [3:0] io_enq_bits_size,\t// @[AsyncQueue.scala:73:14]\n input [1:0] io_enq_bits_source,\t// @[AsyncQueue.scala:73:14]\n input [2:0] io_enq_bits_sink,\t// @[AsyncQueue.scala:73:14]\n input io_enq_bits_denied,\t// @[AsyncQueue.scala:73:14]\n input [63:0] io_enq_bits_data,\t// @[AsyncQueue.scala:73:14]\n input io_enq_bits_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_0_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_0_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_0_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_0_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_0_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_0_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_0_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_0_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_1_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_1_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_1_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_1_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_1_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_1_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_1_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_1_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_2_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_2_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_2_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_2_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_2_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_2_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_2_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_2_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_3_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_3_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_3_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_3_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_3_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_3_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_3_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_3_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_4_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_4_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_4_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_4_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_4_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_4_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_4_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_4_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_5_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_5_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_5_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_5_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_5_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_5_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_5_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_5_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_6_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_6_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_6_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_6_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_6_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_6_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_6_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_6_corrupt,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_7_opcode,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_7_param,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_mem_7_size,\t// @[AsyncQueue.scala:73:14]\n output [1:0] io_async_mem_7_source,\t// @[AsyncQueue.scala:73:14]\n output [2:0] io_async_mem_7_sink,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_7_denied,\t// @[AsyncQueue.scala:73:14]\n output [63:0] io_async_mem_7_data,\t// @[AsyncQueue.scala:73:14]\n output io_async_mem_7_corrupt,\t// @[AsyncQueue.scala:73:14]\n input [3:0] io_async_ridx,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_widx,\t// @[AsyncQueue.scala:73:14]\n input io_async_safe_ridx_valid,\t// @[AsyncQueue.scala:73:14]\n output io_async_safe_widx_valid,\t// @[AsyncQueue.scala:73:14]\n output io_async_safe_source_reset_n,\t// @[AsyncQueue.scala:73:14]\n input io_async_safe_sink_reset_n\t// @[AsyncQueue.scala:73:14]\n);\n\n wire _sink_extend_io_out;\t// @[AsyncQueue.scala:105:30]\n wire _source_valid_0_io_out;\t// @[AsyncQueue.scala:102:32]\n wire io_enq_valid_0 = io_enq_valid;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_enq_bits_param_0 = io_enq_bits_param;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_enq_bits_size_0 = io_enq_bits_size;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_enq_bits_source_0 = io_enq_bits_source;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink;\t// @[AsyncQueue.scala:70:7]\n wire io_enq_bits_denied_0 = io_enq_bits_denied;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_enq_bits_data_0 = io_enq_bits_data;\t// @[AsyncQueue.scala:70:7]\n wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_ridx_0 = io_async_ridx;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n;\t// @[AsyncQueue.scala:70:7]\n wire _widx_T = reset;\t// @[AsyncQueue.scala:83:30]\n wire _ready_reg_T = reset;\t// @[AsyncQueue.scala:90:35]\n wire _widx_reg_T = reset;\t// @[AsyncQueue.scala:93:34]\n wire _source_valid_0_reset_T = reset;\t// @[AsyncQueue.scala:107:36]\n wire _source_valid_1_reset_T = reset;\t// @[AsyncQueue.scala:108:36]\n wire _sink_extend_reset_T = reset;\t// @[AsyncQueue.scala:109:36]\n wire _sink_valid_reset_T = reset;\t// @[AsyncQueue.scala:110:35]\n wire _io_async_safe_source_reset_n_T = reset;\t// @[AsyncQueue.scala:123:34]\n wire _io_enq_ready_T;\t// @[AsyncQueue.scala:91:29]\n wire _io_async_safe_source_reset_n_T_1;\t// @[AsyncQueue.scala:123:27]\n wire io_enq_ready_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_0_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_0_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_0_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_0_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_0_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_0_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_0_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_0_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_1_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_1_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_1_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_1_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_1_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_1_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_1_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_1_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_2_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_2_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_2_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_2_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_2_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_2_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_2_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_2_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_3_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_3_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_3_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_3_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_3_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_3_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_3_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_3_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_4_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_4_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_4_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_4_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_4_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_4_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_4_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_4_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_5_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_5_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_5_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_5_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_5_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_5_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_5_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_5_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_6_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_6_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_6_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_6_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_6_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_6_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_6_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_6_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_7_opcode_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_7_param_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_mem_7_size_0;\t// @[AsyncQueue.scala:70:7]\n wire [1:0] io_async_mem_7_source_0;\t// @[AsyncQueue.scala:70:7]\n wire [2:0] io_async_mem_7_sink_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_7_denied_0;\t// @[AsyncQueue.scala:70:7]\n wire [63:0] io_async_mem_7_data_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_mem_7_corrupt_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_widx_valid_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_source_reset_n_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_widx_0;\t// @[AsyncQueue.scala:70:7]\n wire sink_ready;\t// @[AsyncQueue.scala:81:28]\n reg [2:0] mem_0_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_opcode_0 = mem_0_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_0_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_param_0 = mem_0_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_0_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_size_0 = mem_0_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_0_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_source_0 = mem_0_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_0_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_sink_0 = mem_0_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_0_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_denied_0 = mem_0_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_0_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_data_0 = mem_0_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_0_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_corrupt_0 = mem_0_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_1_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_opcode_0 = mem_1_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_1_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_param_0 = mem_1_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_1_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_size_0 = mem_1_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_1_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_source_0 = mem_1_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_1_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_sink_0 = mem_1_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_1_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_denied_0 = mem_1_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_1_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_data_0 = mem_1_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_1_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_corrupt_0 = mem_1_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_2_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_opcode_0 = mem_2_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_2_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_param_0 = mem_2_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_2_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_size_0 = mem_2_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_2_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_source_0 = mem_2_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_2_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_sink_0 = mem_2_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_2_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_denied_0 = mem_2_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_2_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_data_0 = mem_2_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_2_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_corrupt_0 = mem_2_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_3_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_opcode_0 = mem_3_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_3_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_param_0 = mem_3_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_3_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_size_0 = mem_3_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_3_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_source_0 = mem_3_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_3_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_sink_0 = mem_3_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_3_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_denied_0 = mem_3_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_3_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_data_0 = mem_3_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_3_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_corrupt_0 = mem_3_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_4_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_opcode_0 = mem_4_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_4_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_param_0 = mem_4_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_4_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_size_0 = mem_4_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_4_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_source_0 = mem_4_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_4_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_sink_0 = mem_4_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_4_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_denied_0 = mem_4_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_4_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_data_0 = mem_4_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_4_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_corrupt_0 = mem_4_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_5_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_opcode_0 = mem_5_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_5_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_param_0 = mem_5_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_5_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_size_0 = mem_5_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_5_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_source_0 = mem_5_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_5_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_sink_0 = mem_5_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_5_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_denied_0 = mem_5_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_5_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_data_0 = mem_5_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_5_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_corrupt_0 = mem_5_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_6_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_opcode_0 = mem_6_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_6_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_param_0 = mem_6_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_6_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_size_0 = mem_6_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_6_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_source_0 = mem_6_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_6_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_sink_0 = mem_6_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_6_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_denied_0 = mem_6_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_6_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_data_0 = mem_6_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_6_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_corrupt_0 = mem_6_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_7_opcode;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_opcode_0 = mem_7_opcode;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_7_param;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_param_0 = mem_7_param;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [3:0] mem_7_size;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_size_0 = mem_7_size;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [1:0] mem_7_source;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_source_0 = mem_7_source;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [2:0] mem_7_sink;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_sink_0 = mem_7_sink;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_7_denied;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_denied_0 = mem_7_denied;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [63:0] mem_7_data;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_data_0 = mem_7_data;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg mem_7_corrupt;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_corrupt_0 = mem_7_corrupt;\t// @[AsyncQueue.scala:70:7, :82:16]\n wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0;\t// @[Decoupled.scala:51:35]\n wire _widx_T_2 = ~sink_ready;\t// @[AsyncQueue.scala:81:28, :83:77]\n wire [3:0] _widx_incremented_T_2;\t// @[AsyncQueue.scala:53:23]\n wire [3:0] widx_incremented;\t// @[AsyncQueue.scala:51:27]\n reg [3:0] widx_widx_bin;\t// @[AsyncQueue.scala:52:25]\n wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1};\t// @[Decoupled.scala:51:35]\n wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0];\t// @[AsyncQueue.scala:53:43]\n assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1;\t// @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]\n assign widx_incremented = _widx_incremented_T_2;\t// @[AsyncQueue.scala:51:27, :53:23]\n wire [2:0] _widx_T_3 = widx_incremented[3:1];\t// @[AsyncQueue.scala:51:27, :54:32]\n wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3};\t// @[AsyncQueue.scala:51:27, :54:{17,32}]\n wire [3:0] ridx;\t// @[ShiftReg.scala:48:24]\n wire [3:0] _ready_T = ridx ^ 4'hC;\t// @[ShiftReg.scala:48:24]\n wire _ready_T_1 = widx != _ready_T;\t// @[AsyncQueue.scala:54:17, :85:{34,44}]\n wire ready = sink_ready & _ready_T_1;\t// @[AsyncQueue.scala:81:28, :85:{26,34}]\n wire [2:0] _index_T = io_async_widx_0[2:0];\t// @[AsyncQueue.scala:70:7, :87:52]\n wire _index_T_1 = io_async_widx_0[3];\t// @[AsyncQueue.scala:70:7, :87:80]\n wire [2:0] _index_T_2 = {_index_T_1, 2'h0};\t// @[AsyncQueue.scala:87:{80,93}]\n wire [2:0] index = _index_T ^ _index_T_2;\t// @[AsyncQueue.scala:87:{52,64,93}]\n reg ready_reg;\t// @[AsyncQueue.scala:90:56]\n assign _io_enq_ready_T = ready_reg & sink_ready;\t// @[AsyncQueue.scala:81:28, :90:56, :91:29]\n assign io_enq_ready_0 = _io_enq_ready_T;\t// @[AsyncQueue.scala:70:7, :91:29]\n reg [3:0] widx_gray;\t// @[AsyncQueue.scala:93:55]\n assign io_async_widx_0 = widx_gray;\t// @[AsyncQueue.scala:70:7, :93:55]\n wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0;\t// @[AsyncQueue.scala:70:7, :107:46]\n wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1;\t// @[AsyncQueue.scala:107:{36,43,46}]\n wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2;\t// @[AsyncQueue.scala:107:{43,65}]\n wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0;\t// @[AsyncQueue.scala:70:7, :107:46, :108:46]\n wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1;\t// @[AsyncQueue.scala:108:{36,43,46}]\n wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2;\t// @[AsyncQueue.scala:108:{43,65}]\n wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0;\t// @[AsyncQueue.scala:70:7, :107:46, :109:46]\n wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1;\t// @[AsyncQueue.scala:109:{36,43,46}]\n wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2;\t// @[AsyncQueue.scala:109:{43,65}]\n assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T;\t// @[AsyncQueue.scala:123:{27,34}]\n assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1;\t// @[AsyncQueue.scala:70:7, :123:27]\n always @(posedge clock) begin\t// @[AsyncQueue.scala:70:7]\n if (_widx_T_1 & index == 3'h0) begin\t// @[Decoupled.scala:51:35]\n mem_0_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_0_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_0_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_0_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_0_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_0_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_0_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_0_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n if (_widx_T_1 & index == 3'h1) begin\t// @[Decoupled.scala:51:35]\n mem_1_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_1_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_1_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_1_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_1_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_1_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_1_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_1_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n if (_widx_T_1 & index == 3'h2) begin\t// @[Decoupled.scala:51:35]\n mem_2_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_2_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_2_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_2_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_2_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_2_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_2_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_2_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n if (_widx_T_1 & index == 3'h3) begin\t// @[Decoupled.scala:51:35]\n mem_3_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_3_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_3_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_3_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_3_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_3_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_3_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_3_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n if (_widx_T_1 & index == 3'h4) begin\t// @[Decoupled.scala:51:35]\n mem_4_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_4_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_4_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_4_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_4_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_4_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_4_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_4_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n if (_widx_T_1 & index == 3'h5) begin\t// @[Decoupled.scala:51:35]\n mem_5_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_5_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_5_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_5_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_5_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_5_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_5_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_5_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n if (_widx_T_1 & index == 3'h6) begin\t// @[Decoupled.scala:51:35]\n mem_6_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_6_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_6_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_6_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_6_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_6_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_6_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_6_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n if (_widx_T_1 & (&index)) begin\t// @[Decoupled.scala:51:35]\n mem_7_opcode <= io_enq_bits_opcode_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_7_param <= io_enq_bits_param_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_7_size <= io_enq_bits_size_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_7_source <= io_enq_bits_source_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_7_sink <= io_enq_bits_sink_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_7_denied <= io_enq_bits_denied_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_7_data <= io_enq_bits_data_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n mem_7_corrupt <= io_enq_bits_corrupt_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n end\n always @(posedge)\n always @(posedge clock or posedge _widx_T) begin\t// @[AsyncQueue.scala:70:7, :83:30]\n if (_widx_T)\t// @[AsyncQueue.scala:70:7, :83:30]\n widx_widx_bin <= 4'h0;\t// @[AsyncQueue.scala:52:25]\n else\t// @[AsyncQueue.scala:70:7]\n widx_widx_bin <= widx_incremented;\t// @[AsyncQueue.scala:51:27, :52:25]\n always @(posedge, posedge)\n always @(posedge clock or posedge _ready_reg_T) begin\t// @[AsyncQueue.scala:70:7, :90:35]\n if (_ready_reg_T)\t// @[AsyncQueue.scala:70:7, :90:35]\n ready_reg <= 1'h0;\t// @[AsyncQueue.scala:90:56]\n else\t// @[AsyncQueue.scala:70:7]\n ready_reg <= ready;\t// @[AsyncQueue.scala:85:26, :90:56]\n always @(posedge, posedge)\n always @(posedge clock or posedge _widx_reg_T) begin\t// @[AsyncQueue.scala:70:7, :93:34]\n if (_widx_reg_T)\t// @[AsyncQueue.scala:70:7, :93:34]\n widx_gray <= 4'h0;\t// @[AsyncQueue.scala:52:25, :93:55]\n else\t// @[AsyncQueue.scala:70:7]\n widx_gray <= widx;\t// @[AsyncQueue.scala:54:17, :93:55]\n always @(posedge, posedge)"}}},{"rowIdx":32153,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_65 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_65(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":32154,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_23 : \n output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} \n\n\n node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) \n node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) \n node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) \n node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) \n node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) \n node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) \n node _roundMagUp_T = and(roundingMode_min, io.in.sign) \n node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) \n node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) \n node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) \n node adjustedSig = shl(io.in.sig, 0) \n node doShiftSigDown1 = bits(adjustedSig, 26, 26) \n wire common_expOut : UInt<9> \n wire common_fractOut : UInt<23> \n wire common_overflow : UInt<1> \n wire common_totalUnderflow : UInt<1> \n wire common_underflow : UInt<1> \n wire common_inexact : UInt<1> \n node _roundMask_T = bits(io.in.sExp, 8, 0) \n node _roundMask_T_1 = not(_roundMask_T) \n node roundMask_msb = bits(_roundMask_T_1, 8, 8) \n node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) \n node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) \n node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) \n node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) \n node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) \n node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) \n node _roundMask_T_2 = bits(roundMask_shift, 63, 42) \n node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) \n node _roundMask_T_4 = shl(UInt<8>(0hff), 8) \n node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) \n node _roundMask_T_6 = shr(_roundMask_T_3, 8) \n node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) \n node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) \n node _roundMask_T_9 = shl(_roundMask_T_8, 8) \n node _roundMask_T_10 = not(_roundMask_T_5) \n node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) \n node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) \n node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) \n node _roundMask_T_14 = shl(_roundMask_T_13, 4) \n node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) \n node _roundMask_T_16 = shr(_roundMask_T_12, 4) \n node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) \n node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) \n node _roundMask_T_19 = shl(_roundMask_T_18, 4) \n node _roundMask_T_20 = not(_roundMask_T_15) \n node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) \n node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) \n node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) \n node _roundMask_T_24 = shl(_roundMask_T_23, 2) \n node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) \n node _roundMask_T_26 = shr(_roundMask_T_22, 2) \n node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) \n node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) \n node _roundMask_T_29 = shl(_roundMask_T_28, 2) \n node _roundMask_T_30 = not(_roundMask_T_25) \n node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) \n node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) \n node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) \n node _roundMask_T_34 = shl(_roundMask_T_33, 1) \n node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) \n node _roundMask_T_36 = shr(_roundMask_T_32, 1) \n node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) \n node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) \n node _roundMask_T_39 = shl(_roundMask_T_38, 1) \n node _roundMask_T_40 = not(_roundMask_T_35) \n node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) \n node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) \n node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) \n node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) \n node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) \n node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) \n node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) \n node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) \n node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) \n node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) \n node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) \n node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) \n node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) \n node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) \n node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) \n node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) \n node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) \n node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) \n node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) \n node _roundMask_T_60 = not(_roundMask_T_59) \n node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) \n node _roundMask_T_62 = not(_roundMask_T_61) \n node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) \n node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) \n node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) \n node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) \n node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) \n node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) \n node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) \n node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) \n node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) \n node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) \n node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) \n node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) \n node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) \n node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) \n node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) \n node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) \n node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) \n node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) \n node _roundPosMask_T = not(shiftedRoundMask) \n node roundPosMask = and(_roundPosMask_T, roundMask) \n node _roundPosBit_T = and(adjustedSig, roundPosMask) \n node roundPosBit = orr(_roundPosBit_T) \n node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) \n node anyRoundExtra = orr(_anyRoundExtra_T) \n node anyRound = or(roundPosBit, anyRoundExtra) \n node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) \n node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) \n node _roundIncr_T_2 = and(roundMagUp, anyRound) \n node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) \n node _roundedSig_T = or(adjustedSig, roundMask) \n node _roundedSig_T_1 = shr(_roundedSig_T, 2) \n node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) \n node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) \n node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) \n node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) \n node _roundedSig_T_6 = shr(roundMask, 1) \n node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) \n node _roundedSig_T_8 = not(_roundedSig_T_7) \n node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) \n node _roundedSig_T_10 = not(roundMask) \n node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) \n node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) \n node _roundedSig_T_13 = and(roundingMode_odd, anyRound) \n node _roundedSig_T_14 = shr(roundPosMask, 1) \n node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) \n node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) \n node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) \n node _sRoundedExp_T = shr(roundedSig, 24) \n node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) \n node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) \n node _common_expOut_T = bits(sRoundedExp, 8, 0) \n connect common_expOut, _common_expOut_T \n node _common_fractOut_T = bits(roundedSig, 23, 1) \n node _common_fractOut_T_1 = bits(roundedSig, 22, 0) \n node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) \n connect common_fractOut, _common_fractOut_T_2 \n node _common_overflow_T = shr(sRoundedExp, 7) \n node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) \n connect common_overflow, _common_overflow_T_1 \n node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) \n connect common_totalUnderflow, _common_totalUnderflow_T \n node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) \n node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) \n node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) \n node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) \n node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) \n node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) \n node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) \n node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) \n node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) \n node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) \n node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) \n node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) \n node _roundCarry_T = bits(roundedSig, 25, 25) \n node _roundCarry_T_1 = bits(roundedSig, 24, 24) \n node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) \n node _common_underflow_T = shr(io.in.sExp, 8) \n node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) \n node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) \n node _common_underflow_T_3 = bits(roundMask, 3, 3) \n node _common_underflow_T_4 = bits(roundMask, 2, 2) \n node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) \n node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) \n node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) \n node _common_underflow_T_8 = bits(roundMask, 4, 4) \n node _common_underflow_T_9 = bits(roundMask, 3, 3) \n node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) \n node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) \n node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) \n node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) \n node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) \n node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) \n node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) \n node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) \n node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) \n connect common_underflow, _common_underflow_T_18 \n node _common_inexact_T = or(common_totalUnderflow, anyRound) \n connect common_inexact, _common_inexact_T \n node isNaNOut = or(io.invalidExc, io.in.isNaN) \n node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) \n node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) \n node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) \n node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) \n node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) \n node commonCase = and(_commonCase_T_2, _commonCase_T_3) \n node overflow = and(commonCase, common_overflow) \n node underflow = and(commonCase, common_underflow) \n node _inexact_T = and(commonCase, common_inexact) \n node inexact = or(overflow, _inexact_T) \n node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) \n node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) \n node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) \n node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) \n node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) \n node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) \n node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) \n node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) \n node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) \n node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) \n node _expOut_T = or(io.in.isZero, common_totalUnderflow) \n node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) \n node _expOut_T_2 = not(_expOut_T_1) \n node _expOut_T_3 = and(common_expOut, _expOut_T_2) \n node _expOut_T_4 = not(UInt<9>(0h6b)) \n node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) \n node _expOut_T_6 = not(_expOut_T_5) \n node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) \n node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) \n node _expOut_T_9 = not(_expOut_T_8) \n node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) \n node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) \n node _expOut_T_12 = not(_expOut_T_11) \n node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) \n node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) \n node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) \n node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) \n node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) \n node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) \n node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) \n node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) \n node expOut = or(_expOut_T_19, _expOut_T_20) \n node _fractOut_T = or(isNaNOut, io.in.isZero) \n node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) \n node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) \n node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) \n node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) \n node fractOut = or(_fractOut_T_3, _fractOut_T_4) \n node _io_out_T = cat(signOut, expOut) \n node _io_out_T_1 = cat(_io_out_T, fractOut) \n connect io.out, _io_out_T_1 \n node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) \n node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) \n node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) \n node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) \n connect io.exceptionFlags, _io_exceptionFlags_T_3"},"response":{"kind":"string","value":"module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_23(\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n input io_invalidExc,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_isNaN,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_isInf,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_isZero,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input io_in_sign,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input [9:0] io_in_sExp,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n input [26:0] io_in_sig,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n output [32:0] io_out,\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n output [4:0] io_exceptionFlags\t// @[RoundAnyRawFNToRecFN.scala:58:16]\n);\n\n wire io_invalidExc_0 = io_invalidExc;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isNaN_0 = io_in_isNaN;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isInf_0 = io_in_isInf;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isZero_0 = io_in_isZero;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_sign_0 = io_in_sign;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [9:0] io_in_sExp_0 = io_in_sExp;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [26:0] io_in_sig_0 = io_in_sig;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [8:0] _expOut_T_4 = 9'h194;\t// @[RoundAnyRawFNToRecFN.scala:258:19]\n wire [15:0] _roundMask_T_5 = 16'hFF;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_4 = 16'hFF00;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_10 = 16'hFF00;\t// @[primitives.scala:77:20]\n wire [11:0] _roundMask_T_13 = 12'hFF;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_14 = 16'hFF0;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_15 = 16'hF0F;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_20 = 16'hF0F0;\t// @[primitives.scala:77:20]\n wire [13:0] _roundMask_T_23 = 14'hF0F;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_24 = 16'h3C3C;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_25 = 16'h3333;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_30 = 16'hCCCC;\t// @[primitives.scala:77:20]\n wire [14:0] _roundMask_T_33 = 15'h3333;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_34 = 16'h6666;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_35 = 16'h5555;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_40 = 16'hAAAA;\t// @[primitives.scala:77:20]\n wire [25:0] _roundedSig_T_15 = 26'h0;\t// @[RoundAnyRawFNToRecFN.scala:181:24]\n wire [8:0] _expOut_T_6 = 9'h1FF;\t// @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]\n wire [8:0] _expOut_T_9 = 9'h1FF;\t// @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]\n wire [8:0] _expOut_T_5 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:257:18]\n wire [8:0] _expOut_T_8 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:261:18]\n wire [8:0] _expOut_T_14 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:269:16]\n wire [8:0] _expOut_T_16 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:273:16]\n wire [22:0] _fractOut_T_4 = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:284:13]\n wire io_detectTininess = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire roundingMode_near_even = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:90:53]\n wire _roundIncr_T = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:169:38]\n wire _unboundedRange_roundIncr_T = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:207:38]\n wire _common_underflow_T_7 = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:222:49]\n wire _overflow_roundMagUp_T = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:243:32]\n wire overflow_roundMagUp = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:243:60]\n wire [2:0] io_roundingMode = 3'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_infiniteExc = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire roundingMode_minMag = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:91:53]\n wire roundingMode_min = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:92:53]\n wire roundingMode_max = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:93:53]\n wire roundingMode_near_maxMag = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:94:53]\n wire roundingMode_odd = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:95:53]\n wire _roundMagUp_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:98:27]\n wire _roundMagUp_T_2 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:98:63]\n wire roundMagUp = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:98:42]\n wire _roundIncr_T_2 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:171:29]\n wire _roundedSig_T_13 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:181:42]\n wire _unboundedRange_roundIncr_T_2 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:209:29]\n wire _pegMinNonzeroMagOut_T_1 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:245:60]\n wire pegMinNonzeroMagOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:245:45]\n wire _pegMaxFiniteMagOut_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:246:42]\n wire pegMaxFiniteMagOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:246:39]\n wire notNaN_isSpecialInfOut = io_in_isInf_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]\n wire [26:0] adjustedSig = io_in_sig_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]\n wire [32:0] _io_out_T_1;\t// @[RoundAnyRawFNToRecFN.scala:286:33]\n wire [4:0] _io_exceptionFlags_T_3;\t// @[RoundAnyRawFNToRecFN.scala:288:66]\n wire [32:0] io_out_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [4:0] io_exceptionFlags_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire _roundMagUp_T_1 = ~io_in_sign_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]\n wire doShiftSigDown1 = adjustedSig[26];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]\n wire [8:0] _common_expOut_T;\t// @[RoundAnyRawFNToRecFN.scala:187:37]\n wire [8:0] common_expOut;\t// @[RoundAnyRawFNToRecFN.scala:122:31]\n wire [22:0] _common_fractOut_T_2;\t// @[RoundAnyRawFNToRecFN.scala:189:16]\n wire [22:0] common_fractOut;\t// @[RoundAnyRawFNToRecFN.scala:123:31]\n wire _common_overflow_T_1;\t// @[RoundAnyRawFNToRecFN.scala:196:50]\n wire common_overflow;\t// @[RoundAnyRawFNToRecFN.scala:124:37]\n wire _common_totalUnderflow_T;\t// @[RoundAnyRawFNToRecFN.scala:200:31]\n wire common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:125:37]\n wire _common_underflow_T_18;\t// @[RoundAnyRawFNToRecFN.scala:217:40]\n wire common_underflow;\t// @[RoundAnyRawFNToRecFN.scala:126:37]\n wire _common_inexact_T;\t// @[RoundAnyRawFNToRecFN.scala:230:49]\n wire common_inexact;\t// @[RoundAnyRawFNToRecFN.scala:127:37]\n wire [8:0] _roundMask_T = io_in_sExp_0[8:0];\t// @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]\n wire [8:0] _roundMask_T_1 = ~_roundMask_T;\t// @[primitives.scala:52:21]\n wire roundMask_msb = _roundMask_T_1[8];\t// @[primitives.scala:52:21, :58:25]\n wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0];\t// @[primitives.scala:52:21, :59:26]\n wire roundMask_msb_1 = roundMask_lsbs[7];\t// @[primitives.scala:58:25, :59:26]\n wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0];\t// @[primitives.scala:59:26]\n wire roundMask_msb_2 = roundMask_lsbs_1[6];\t// @[primitives.scala:58:25, :59:26]\n wire roundMask_msb_3 = roundMask_lsbs_1[6];\t// @[primitives.scala:58:25, :59:26]\n wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0];\t// @[primitives.scala:59:26]\n wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0];\t// @[primitives.scala:59:26]\n wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2);\t// @[primitives.scala:59:26, :76:56]\n wire [21:0] _roundMask_T_2 = roundMask_shift[63:42];\t// @[primitives.scala:76:56, :78:22]\n wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0];\t// @[primitives.scala:77:20, :78:22]\n wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6};\t// @[primitives.scala:77:20]\n wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11;\t// @[primitives.scala:77:20]\n wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F};\t// @[primitives.scala:77:20]\n wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21;\t// @[primitives.scala:77:20]\n wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333};\t// @[primitives.scala:77:20]\n wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31;\t// @[primitives.scala:77:20]\n wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555};\t// @[primitives.scala:77:20]\n wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0];\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0};\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA;\t// @[primitives.scala:77:20]\n wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41;\t// @[primitives.scala:77:20]\n wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16];\t// @[primitives.scala:77:20, :78:22]\n wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_46 = _roundMask_T_45[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_47 = _roundMask_T_45[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47};\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2];\t// @[primitives.scala:77:20]\n wire _roundMask_T_50 = _roundMask_T_49[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_51 = _roundMask_T_49[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51};\t// @[primitives.scala:77:20]\n wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52};\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4];\t// @[primitives.scala:77:20]\n wire _roundMask_T_55 = _roundMask_T_54[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_56 = _roundMask_T_54[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56};\t// @[primitives.scala:77:20]\n wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57};\t// @[primitives.scala:77:20]\n wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58};\t// @[primitives.scala:77:20]\n wire [21:0] _roundMask_T_60 = ~_roundMask_T_59;\t// @[primitives.scala:73:32, :77:20]\n wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60;\t// @[primitives.scala:58:25, :73:{21,32}]\n wire [21:0] _roundMask_T_62 = ~_roundMask_T_61;\t// @[primitives.scala:73:{17,21}]\n wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7};\t// @[primitives.scala:68:58, :73:17]\n wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3);\t// @[primitives.scala:59:26, :76:56]\n wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0];\t// @[primitives.scala:76:56, :78:22]\n wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0];\t// @[primitives.scala:77:20, :78:22]\n wire _roundMask_T_66 = _roundMask_T_65[0];\t// @[primitives.scala:77:20]\n wire _roundMask_T_67 = _roundMask_T_65[1];\t// @[primitives.scala:77:20]\n wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67};\t// @[primitives.scala:77:20]\n wire _roundMask_T_69 = _roundMask_T_64[2];\t// @[primitives.scala:77:20, :78:22]\n wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69};\t// @[primitives.scala:77:20]\n wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0;\t// @[primitives.scala:58:25, :62:24, :77:20]\n wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71};\t// @[primitives.scala:58:25, :62:24, :67:24, :68:58]\n wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0;\t// @[primitives.scala:58:25, :62:24, :67:24]\n wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1};\t// @[primitives.scala:62:24]\n wire [26:0] roundMask = {_roundMask_T_74, 2'h3};\t// @[RoundAnyRawFNToRecFN.scala:159:{23,42}]\n wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask};\t// @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]\n wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1];\t// @[RoundAnyRawFNToRecFN.scala:162:{41,53}]\n wire [26:0] _roundPosMask_T = ~shiftedRoundMask;\t// @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]\n wire [26:0] roundPosMask = _roundPosMask_T & roundMask;\t// @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]\n wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]\n wire roundPosBit = |_roundPosBit_T;\t// @[RoundAnyRawFNToRecFN.scala:164:{40,56}]\n wire _roundIncr_T_1 = roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]\n wire _roundedSig_T_3 = roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]\n wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]\n wire anyRoundExtra = |_anyRoundExtra_T;\t// @[RoundAnyRawFNToRecFN.scala:165:{42,62}]\n wire anyRound = roundPosBit | anyRoundExtra;\t// @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]\n wire roundIncr = _roundIncr_T_1;\t// @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]\n wire [26:0] _roundedSig_T = adjustedSig | roundMask;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]\n wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2];\t// @[RoundAnyRawFNToRecFN.scala:174:{32,44}]\n wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1;\t// @[RoundAnyRawFNToRecFN.scala:174:{44,49}]\n wire _roundedSig_T_4 = ~anyRoundExtra;\t// @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]\n wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4;\t// @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]\n wire [25:0] _roundedSig_T_6 = roundMask[26:1];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]\n wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0;\t// @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]\n wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7;\t// @[RoundAnyRawFNToRecFN.scala:175:{21,25}]\n wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8;\t// @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]\n wire [26:0] _roundedSig_T_10 = ~roundMask;\t// @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]\n wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10;\t// @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]\n wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2];\t// @[RoundAnyRawFNToRecFN.scala:180:{30,43}]\n wire [25:0] _roundedSig_T_14 = roundPosMask[26:1];\t// @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]\n wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12};\t// @[RoundAnyRawFNToRecFN.scala:180:{43,47}]\n wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16;\t// @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]\n wire [1:0] _sRoundedExp_T = roundedSig[25:24];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]\n wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T};\t// @[RoundAnyRawFNToRecFN.scala:185:{54,76}]\n wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1};\t// @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]\n assign _common_expOut_T = sRoundedExp[8:0];\t// @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]\n assign common_expOut = _common_expOut_T;\t// @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]\n wire [22:0] _common_fractOut_T = roundedSig[23:1];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]\n wire [22:0] _common_fractOut_T_1 = roundedSig[22:0];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]\n assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]\n assign common_fractOut = _common_fractOut_T_2;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]\n wire [3:0] _common_overflow_T = sRoundedExp[10:7];\t// @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]\n assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2;\t// @[RoundAnyRawFNToRecFN.scala:196:{30,50}]\n assign common_overflow = _common_overflow_T_1;\t// @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]\n assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B;\t// @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]\n assign common_totalUnderflow = _common_totalUnderflow_T;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]\n wire _unboundedRange_roundPosBit_T = adjustedSig[2];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]\n wire _unboundedRange_anyRound_T = adjustedSig[2];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]\n wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]\n wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]\n wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]\n wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]\n wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0];\t// @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]\n wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2;\t// @[RoundAnyRawFNToRecFN.scala:205:{63,70}]\n wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3;\t// @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]\n wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1;\t// @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]\n wire _roundCarry_T = roundedSig[25];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]\n wire _roundCarry_T_1 = roundedSig[24];\t// @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]\n wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]\n wire [1:0] _common_underflow_T = io_in_sExp_0[9:8];\t// @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]\n wire _common_underflow_T_1 = _common_underflow_T != 2'h1;\t// @[RoundAnyRawFNToRecFN.scala:220:{49,64}]\n wire _common_underflow_T_2 = anyRound & _common_underflow_T_1;\t// @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]\n wire _common_underflow_T_3 = roundMask[3];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]\n wire _common_underflow_T_9 = roundMask[3];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]\n wire _common_underflow_T_4 = roundMask[2];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]\n wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]\n wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5;\t// @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]\n wire _common_underflow_T_8 = roundMask[4];\t// @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]\n wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9;\t// @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]\n wire _common_underflow_T_11 = ~_common_underflow_T_10;\t// @[RoundAnyRawFNToRecFN.scala:223:{34,39}]\n wire _common_underflow_T_12 = _common_underflow_T_11;\t// @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]\n wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry;\t// @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]\n wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit;\t// @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]\n wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr;\t// @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]\n wire _common_underflow_T_16 = ~_common_underflow_T_15;\t// @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]\n wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16;\t// @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]\n assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]\n assign common_underflow = _common_underflow_T_18;\t// @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]\n assign _common_inexact_T = common_totalUnderflow | anyRound;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]\n assign common_inexact = _common_inexact_T;\t// @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]\n wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]\n wire _commonCase_T = ~isNaNOut;\t// @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]\n wire _commonCase_T_1 = ~notNaN_isSpecialInfOut;\t// @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]\n wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1;\t// @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]\n wire _commonCase_T_3 = ~io_in_isZero_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]\n wire commonCase = _commonCase_T_2 & _commonCase_T_3;\t// @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]\n wire overflow = commonCase & common_overflow;\t// @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]\n wire _notNaN_isInfOut_T = overflow;\t// @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]\n wire underflow = commonCase & common_underflow;\t// @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]\n wire _inexact_T = commonCase & common_inexact;\t// @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]\n wire inexact = overflow | _inexact_T;\t// @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]\n wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]\n wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T;\t// @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]\n wire signOut = ~isNaNOut & io_in_sign_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]\n wire _expOut_T = io_in_isZero_0 | common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]\n wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:{18,32}]\n wire [8:0] _expOut_T_2 = ~_expOut_T_1;\t// @[RoundAnyRawFNToRecFN.scala:253:{14,18}]\n wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2;\t// @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]\n wire [8:0] _expOut_T_7 = _expOut_T_3;\t// @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]\n wire [8:0] _expOut_T_10 = _expOut_T_7;\t// @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]\n wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0};\t// @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]\n wire [8:0] _expOut_T_12 = ~_expOut_T_11;\t// @[RoundAnyRawFNToRecFN.scala:265:{14,18}]\n wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12;\t// @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]\n wire [8:0] _expOut_T_15 = _expOut_T_13;\t// @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]\n wire [8:0] _expOut_T_17 = _expOut_T_15;\t// @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]\n wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]\n wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18;\t// @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]\n wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]\n wire [8:0] expOut = _expOut_T_19 | _expOut_T_20;\t// @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]\n wire _fractOut_T = isNaNOut | io_in_isZero_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]\n wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow;\t// @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]\n wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0};\t// @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]\n wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]\n wire [22:0] fractOut = _fractOut_T_3;\t// @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]\n wire [9:0] _io_out_T = {signOut, expOut};\t// @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]\n assign _io_out_T_1 = {_io_out_T, fractOut};\t// @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]\n assign io_out_0 = _io_out_T_1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]\n wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0};\t// @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]\n wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow};\t// @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]\n wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow};\t// @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]\n assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact};\t// @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]\n assign io_exceptionFlags_0 = _io_exceptionFlags_T_3;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]\n assign io_out = io_out_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n assign io_exceptionFlags = io_exceptionFlags_0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\nendmodule"}}},{"rowIdx":32155,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_5 : \n input clock : Clock \n input reset : Reset \n output auto : { } \n\n\n skip"},"response":{"kind":"string","value":"module TLBuffer_5(\t// @[Buffer.scala:40:9]\n input clock,\t// @[Buffer.scala:40:9]\n input reset\t// @[Buffer.scala:40:9]\n);\n\nendmodule"}}},{"rowIdx":32156,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_12 : \n output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} \n\n\n node _intAsRawFloat_sign_T = bits(io.in, 0, 0) \n node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) \n node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) \n node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) \n node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) \n node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) \n node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) \n node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) \n node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) \n node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) \n node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) \n node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) \n wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} \n connect intAsRawFloat.isNaN, UInt<1>(0h0) \n connect intAsRawFloat.isInf, UInt<1>(0h0) \n node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) \n node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) \n connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 \n connect intAsRawFloat.sign, intAsRawFloat_sign \n node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) \n node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) \n node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) \n node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) \n connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 \n connect intAsRawFloat.sig, intAsRawFloat_sig \n inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_12 \n connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig \n connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp \n connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign \n connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero \n connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf \n connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN \n connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode \n connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess \n connect io.out, roundAnyRawFNToRecFN.io.out \n connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags"},"response":{"kind":"string","value":"module INToRecFN_i1_e8_s24_12();\t// @[INToRecFN.scala:43:7]\n wire [1:0] _intAsRawFloat_absIn_T = 2'h3;\t// @[rawFloatFromIN.scala:52:31]\n wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1;\t// @[rawFloatFromIN.scala:53:44]\n wire [2:0] _intAsRawFloat_sig_T = 3'h2;\t// @[rawFloatFromIN.scala:56:22]\n wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4;\t// @[rawFloatFromIN.scala:64:33]\n wire [3:0] intAsRawFloat_sExp = 4'h4;\t// @[rawFloatFromIN.scala:59:23, :64:72]\n wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4;\t// @[rawFloatFromIN.scala:59:23, :64:72]\n wire [1:0] intAsRawFloat_extAbsIn = 2'h1;\t// @[rawFloatFromIN.scala:53:53, :59:23, :65:20]\n wire [1:0] intAsRawFloat_sig = 2'h1;\t// @[rawFloatFromIN.scala:53:53, :59:23, :65:20]\n wire [4:0] io_exceptionFlags = 5'h0;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire [32:0] io_out = 33'h80000000;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire [2:0] io_roundingMode = 3'h0;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire io_in = 1'h1;\t// @[Mux.scala:50:70]\n wire io_detectTininess = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_sign_T = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_absIn_T_1 = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_absIn = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_adjustedNormDist_T = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_adjustedNormDist = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_sig_0 = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_out_isZero_T = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_out_sExp_T = 1'h1;\t// @[Mux.scala:50:70]\n wire io_signedIn = 1'h0;\t// @[INToRecFN.scala:43:7]\n wire intAsRawFloat_sign = 1'h0;\t// @[rawFloatFromIN.scala:51:29]\n wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0;\t// @[primitives.scala:91:52]\n wire intAsRawFloat_isNaN = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_isInf = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_isZero = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_sign_0 = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire _intAsRawFloat_out_isZero_T_1 = 1'h0;\t// @[rawFloatFromIN.scala:62:23]\n wire _intAsRawFloat_out_sExp_T_1 = 1'h0;\t// @[rawFloatFromIN.scala:64:36]\n RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_12 roundAnyRawFNToRecFN ();\t// @[INToRecFN.scala:60:15]\nendmodule"}}},{"rowIdx":32157,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_10 : \n input clock : Clock \n input reset : Reset \n output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} \n\n\n inst q of Queue1_TLBundleC_a32d128s7k6z4c_10 \n connect q.clock, clock\n\n connect q.reset, reset\n\n wire has_body : UInt<1> \n node _head_T = and(q.io.deq.ready, q.io.deq.valid) \n node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) \n node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) \n node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) \n node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) \n node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) \n node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) \n regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0) \n node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) \n node head_counter1 = tail(_head_counter1_T, 1) \n node head = eq(head_counter, UInt<1>(0h0)) \n node _head_last_T = eq(head_counter, UInt<1>(0h1)) \n node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) \n node head_last = or(_head_last_T, _head_last_T_1) \n node head_done = and(head_last, _head_T) \n node _head_count_T = not(head_counter1) \n node head_count = and(head_beats1, _head_count_T) \n when _head_T : \n node _head_counter_T = mux(head, head_beats1, head_counter1) \n connect head_counter, _head_counter_T \n node _tail_T = and(q.io.deq.ready, q.io.deq.valid) \n node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) \n node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) \n node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) \n node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) \n node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) \n node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) \n regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0) \n node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) \n node tail_counter1 = tail(_tail_counter1_T, 1) \n node tail_first = eq(tail_counter, UInt<1>(0h0)) \n node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) \n node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) \n node tail = or(_tail_last_T, _tail_last_T_1) \n node tail_done = and(tail, _tail_T) \n node _tail_count_T = not(tail_counter1) \n node tail_count = and(tail_beats1, _tail_count_T) \n when _tail_T : \n node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) \n connect tail_counter, _tail_counter_T \n node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) \n node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) \n node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) \n node const_hi = cat(const_hi_hi, q.io.deq.bits.size) \n node const = cat(const_hi, const_lo) \n regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) \n connect io.flit.valid, q.io.deq.valid \n node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) \n node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) \n node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) \n connect q.io.deq.ready, _q_io_deq_ready_T_2 \n node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) \n node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) \n connect io.flit.bits.head, _io_flit_bits_head_T_1 \n node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) \n node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) \n node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) \n connect io.flit.bits.tail, _io_flit_bits_tail_T_2 \n node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) \n node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) \n node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) \n node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) \n node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) \n node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) \n node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) \n node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0))) \n node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) \n node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) \n node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) \n node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40)) \n node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) \n node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0))) \n node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) \n node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) \n node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) \n node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80)) \n node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) \n node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0))) \n node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) \n node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) \n node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) \n node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0)) \n node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) \n node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0))) \n node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) \n node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) \n node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) \n node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) \n node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) \n node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) \n node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) \n wire _io_flit_bits_egress_id_WIRE : UInt<5> \n connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 \n connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE \n node _io_flit_bits_payload_T = mux(is_body, body, const) \n connect io.flit.bits.payload, _io_flit_bits_payload_T \n node _T = and(io.flit.ready, io.flit.valid) \n node _T_1 = and(_T, io.flit.bits.head) \n when _T_1 : \n connect is_body, UInt<1>(0h1) \n node _T_2 = and(io.flit.ready, io.flit.valid) \n node _T_3 = and(_T_2, io.flit.bits.tail) \n when _T_3 : \n connect is_body, UInt<1>(0h0) \n node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) \n connect has_body, has_body_opdata \n connect q.io.enq, io.protocol \n node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h28)) \n connect q.io.enq.bits.source, _q_io_enq_bits_source_T"},"response":{"kind":"string","value":"module TLCToNoC_10(\t// @[TilelinkAdapters.scala:151:7]\n input clock,\t// @[TilelinkAdapters.scala:151:7]\n input reset,\t// @[TilelinkAdapters.scala:151:7]\n output io_protocol_ready,\t// @[TilelinkAdapters.scala:19:14]\n input io_protocol_valid,\t// @[TilelinkAdapters.scala:19:14]\n input [2:0] io_protocol_bits_opcode,\t// @[TilelinkAdapters.scala:19:14]\n input [2:0] io_protocol_bits_param,\t// @[TilelinkAdapters.scala:19:14]\n input [3:0] io_protocol_bits_size,\t// @[TilelinkAdapters.scala:19:14]\n input [6:0] io_protocol_bits_source,\t// @[TilelinkAdapters.scala:19:14]\n input [31:0] io_protocol_bits_address,\t// @[TilelinkAdapters.scala:19:14]\n input [127:0] io_protocol_bits_data,\t// @[TilelinkAdapters.scala:19:14]\n input io_protocol_bits_corrupt,\t// @[TilelinkAdapters.scala:19:14]\n input io_flit_ready,\t// @[TilelinkAdapters.scala:19:14]\n output io_flit_valid,\t// @[TilelinkAdapters.scala:19:14]\n output io_flit_bits_head,\t// @[TilelinkAdapters.scala:19:14]\n output io_flit_bits_tail,\t// @[TilelinkAdapters.scala:19:14]\n output [128:0] io_flit_bits_payload,\t// @[TilelinkAdapters.scala:19:14]\n output [4:0] io_flit_bits_egress_id\t// @[TilelinkAdapters.scala:19:14]\n);\n\n wire _q_io_deq_valid;\t// @[TilelinkAdapters.scala:26:17]\n wire [2:0] _q_io_deq_bits_opcode;\t// @[TilelinkAdapters.scala:26:17]\n wire [2:0] _q_io_deq_bits_param;\t// @[TilelinkAdapters.scala:26:17]\n wire [3:0] _q_io_deq_bits_size;\t// @[TilelinkAdapters.scala:26:17]\n wire [6:0] _q_io_deq_bits_source;\t// @[TilelinkAdapters.scala:26:17]\n wire [31:0] _q_io_deq_bits_address;\t// @[TilelinkAdapters.scala:26:17]\n wire [127:0] _q_io_deq_bits_data;\t// @[TilelinkAdapters.scala:26:17]\n wire _q_io_deq_bits_corrupt;\t// @[TilelinkAdapters.scala:26:17]\n wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size;\t// @[package.scala:243:71]\n reg [7:0] head_counter;\t// @[Edges.scala:229:27]\n wire head = head_counter == 8'h0;\t// @[Edges.scala:229:27, :231:25]\n wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0;\t// @[package.scala:243:{46,71,76}]\n reg [7:0] tail_counter;\t// @[Edges.scala:229:27]\n reg is_body;\t// @[TilelinkAdapters.scala:39:24]\n wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0]));\t// @[Edges.scala:102:36]\n wire io_flit_bits_head_0 = head & ~is_body;\t// @[Edges.scala:231:25]\n wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | ~(_q_io_deq_bits_opcode[0]));\t// @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}]\n wire _GEN = io_flit_ready & _q_io_deq_valid;\t// @[Decoupled.scala:51:35]\n always @(posedge clock) begin\t// @[TilelinkAdapters.scala:151:7]\n if (reset) begin\t// @[TilelinkAdapters.scala:151:7]\n head_counter <= 8'h0;\t// @[Edges.scala:229:27]\n tail_counter <= 8'h0;\t// @[Edges.scala:229:27]\n is_body <= 1'h0;\t// @[TilelinkAdapters.scala:39:24, :151:7]\n end\n else begin\t// @[TilelinkAdapters.scala:151:7]\n if (q_io_deq_ready & _q_io_deq_valid) begin\t// @[Decoupled.scala:51:35]\n head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1;\t// @[package.scala:243:{46,71,76}]\n tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1;\t// @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]\n end\n is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body);\t// @[Decoupled.scala:51:35]\n end\n always @(posedge)"}}},{"rowIdx":32158,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module BoomNonBlockingDCache_1 : \n input clock : Clock \n input reset : Reset \n output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} \n output io : { flip lsu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}}[1]}, s1_kill : UInt<1>[1], flip resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1], flip nack : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}}[1], brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, exception : UInt<1>, rob_pnr_idx : UInt<6>, rob_head_idx : UInt<6>, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, force_order : UInt<1>, flip ordered : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>}}} \n\n\n wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} \n invalidate nodeOut.e.bits.sink \n invalidate nodeOut.e.valid \n invalidate nodeOut.e.ready \n invalidate nodeOut.d.bits.corrupt \n invalidate nodeOut.d.bits.data \n invalidate nodeOut.d.bits.denied \n invalidate nodeOut.d.bits.sink \n invalidate nodeOut.d.bits.source \n invalidate nodeOut.d.bits.size \n invalidate nodeOut.d.bits.param \n invalidate nodeOut.d.bits.opcode \n invalidate nodeOut.d.valid \n invalidate nodeOut.d.ready \n invalidate nodeOut.c.bits.corrupt \n invalidate nodeOut.c.bits.data \n invalidate nodeOut.c.bits.address \n invalidate nodeOut.c.bits.source \n invalidate nodeOut.c.bits.size \n invalidate nodeOut.c.bits.param \n invalidate nodeOut.c.bits.opcode \n invalidate nodeOut.c.valid \n invalidate nodeOut.c.ready \n invalidate nodeOut.b.bits.corrupt \n invalidate nodeOut.b.bits.data \n invalidate nodeOut.b.bits.mask \n invalidate nodeOut.b.bits.address \n invalidate nodeOut.b.bits.source \n invalidate nodeOut.b.bits.size \n invalidate nodeOut.b.bits.param \n invalidate nodeOut.b.bits.opcode \n invalidate nodeOut.b.valid \n invalidate nodeOut.b.ready \n invalidate nodeOut.a.bits.corrupt \n invalidate nodeOut.a.bits.data \n invalidate nodeOut.a.bits.mask \n invalidate nodeOut.a.bits.address \n invalidate nodeOut.a.bits.source \n invalidate nodeOut.a.bits.size \n invalidate nodeOut.a.bits.param \n invalidate nodeOut.a.bits.opcode \n invalidate nodeOut.a.valid \n invalidate nodeOut.a.ready \n connect auto.out, nodeOut \n inst wb of BoomWritebackUnit_1 \n connect wb.clock, clock\n\n connect wb.reset, reset\n\n inst prober of BoomProbeUnit_1 \n connect prober.clock, clock\n\n connect prober.reset, reset\n\n inst mshrs of BoomMSHRFile_1 \n connect mshrs.clock, clock\n\n connect mshrs.reset, reset\n\n connect mshrs.io.clear_all, io.lsu.force_order \n connect mshrs.io.brupdate.b2.target_offset, io.lsu.brupdate.b2.target_offset \n connect mshrs.io.brupdate.b2.jalr_target, io.lsu.brupdate.b2.jalr_target \n connect mshrs.io.brupdate.b2.pc_sel, io.lsu.brupdate.b2.pc_sel \n connect mshrs.io.brupdate.b2.cfi_type, io.lsu.brupdate.b2.cfi_type \n connect mshrs.io.brupdate.b2.taken, io.lsu.brupdate.b2.taken \n connect mshrs.io.brupdate.b2.mispredict, io.lsu.brupdate.b2.mispredict \n connect mshrs.io.brupdate.b2.valid, io.lsu.brupdate.b2.valid \n connect mshrs.io.brupdate.b2.uop.debug_tsrc, io.lsu.brupdate.b2.uop.debug_tsrc \n connect mshrs.io.brupdate.b2.uop.debug_fsrc, io.lsu.brupdate.b2.uop.debug_fsrc \n connect mshrs.io.brupdate.b2.uop.bp_xcpt_if, io.lsu.brupdate.b2.uop.bp_xcpt_if \n connect mshrs.io.brupdate.b2.uop.bp_debug_if, io.lsu.brupdate.b2.uop.bp_debug_if \n connect mshrs.io.brupdate.b2.uop.xcpt_ma_if, io.lsu.brupdate.b2.uop.xcpt_ma_if \n connect mshrs.io.brupdate.b2.uop.xcpt_ae_if, io.lsu.brupdate.b2.uop.xcpt_ae_if \n connect mshrs.io.brupdate.b2.uop.xcpt_pf_if, io.lsu.brupdate.b2.uop.xcpt_pf_if \n connect mshrs.io.brupdate.b2.uop.fp_single, io.lsu.brupdate.b2.uop.fp_single \n connect mshrs.io.brupdate.b2.uop.fp_val, io.lsu.brupdate.b2.uop.fp_val \n connect mshrs.io.brupdate.b2.uop.frs3_en, io.lsu.brupdate.b2.uop.frs3_en \n connect mshrs.io.brupdate.b2.uop.lrs2_rtype, io.lsu.brupdate.b2.uop.lrs2_rtype \n connect mshrs.io.brupdate.b2.uop.lrs1_rtype, io.lsu.brupdate.b2.uop.lrs1_rtype \n connect mshrs.io.brupdate.b2.uop.dst_rtype, io.lsu.brupdate.b2.uop.dst_rtype \n connect mshrs.io.brupdate.b2.uop.ldst_val, io.lsu.brupdate.b2.uop.ldst_val \n connect mshrs.io.brupdate.b2.uop.lrs3, io.lsu.brupdate.b2.uop.lrs3 \n connect mshrs.io.brupdate.b2.uop.lrs2, io.lsu.brupdate.b2.uop.lrs2 \n connect mshrs.io.brupdate.b2.uop.lrs1, io.lsu.brupdate.b2.uop.lrs1 \n connect mshrs.io.brupdate.b2.uop.ldst, io.lsu.brupdate.b2.uop.ldst \n connect mshrs.io.brupdate.b2.uop.ldst_is_rs1, io.lsu.brupdate.b2.uop.ldst_is_rs1 \n connect mshrs.io.brupdate.b2.uop.flush_on_commit, io.lsu.brupdate.b2.uop.flush_on_commit \n connect mshrs.io.brupdate.b2.uop.is_unique, io.lsu.brupdate.b2.uop.is_unique \n connect mshrs.io.brupdate.b2.uop.is_sys_pc2epc, io.lsu.brupdate.b2.uop.is_sys_pc2epc \n connect mshrs.io.brupdate.b2.uop.uses_stq, io.lsu.brupdate.b2.uop.uses_stq \n connect mshrs.io.brupdate.b2.uop.uses_ldq, io.lsu.brupdate.b2.uop.uses_ldq \n connect mshrs.io.brupdate.b2.uop.is_amo, io.lsu.brupdate.b2.uop.is_amo \n connect mshrs.io.brupdate.b2.uop.is_fencei, io.lsu.brupdate.b2.uop.is_fencei \n connect mshrs.io.brupdate.b2.uop.is_fence, io.lsu.brupdate.b2.uop.is_fence \n connect mshrs.io.brupdate.b2.uop.mem_signed, io.lsu.brupdate.b2.uop.mem_signed \n connect mshrs.io.brupdate.b2.uop.mem_size, io.lsu.brupdate.b2.uop.mem_size \n connect mshrs.io.brupdate.b2.uop.mem_cmd, io.lsu.brupdate.b2.uop.mem_cmd \n connect mshrs.io.brupdate.b2.uop.bypassable, io.lsu.brupdate.b2.uop.bypassable \n connect mshrs.io.brupdate.b2.uop.exc_cause, io.lsu.brupdate.b2.uop.exc_cause \n connect mshrs.io.brupdate.b2.uop.exception, io.lsu.brupdate.b2.uop.exception \n connect mshrs.io.brupdate.b2.uop.stale_pdst, io.lsu.brupdate.b2.uop.stale_pdst \n connect mshrs.io.brupdate.b2.uop.ppred_busy, io.lsu.brupdate.b2.uop.ppred_busy \n connect mshrs.io.brupdate.b2.uop.prs3_busy, io.lsu.brupdate.b2.uop.prs3_busy \n connect mshrs.io.brupdate.b2.uop.prs2_busy, io.lsu.brupdate.b2.uop.prs2_busy \n connect mshrs.io.brupdate.b2.uop.prs1_busy, io.lsu.brupdate.b2.uop.prs1_busy \n connect mshrs.io.brupdate.b2.uop.ppred, io.lsu.brupdate.b2.uop.ppred \n connect mshrs.io.brupdate.b2.uop.prs3, io.lsu.brupdate.b2.uop.prs3 \n connect mshrs.io.brupdate.b2.uop.prs2, io.lsu.brupdate.b2.uop.prs2 \n connect mshrs.io.brupdate.b2.uop.prs1, io.lsu.brupdate.b2.uop.prs1 \n connect mshrs.io.brupdate.b2.uop.pdst, io.lsu.brupdate.b2.uop.pdst \n connect mshrs.io.brupdate.b2.uop.rxq_idx, io.lsu.brupdate.b2.uop.rxq_idx \n connect mshrs.io.brupdate.b2.uop.stq_idx, io.lsu.brupdate.b2.uop.stq_idx \n connect mshrs.io.brupdate.b2.uop.ldq_idx, io.lsu.brupdate.b2.uop.ldq_idx \n connect mshrs.io.brupdate.b2.uop.rob_idx, io.lsu.brupdate.b2.uop.rob_idx \n connect mshrs.io.brupdate.b2.uop.csr_addr, io.lsu.brupdate.b2.uop.csr_addr \n connect mshrs.io.brupdate.b2.uop.imm_packed, io.lsu.brupdate.b2.uop.imm_packed \n connect mshrs.io.brupdate.b2.uop.taken, io.lsu.brupdate.b2.uop.taken \n connect mshrs.io.brupdate.b2.uop.pc_lob, io.lsu.brupdate.b2.uop.pc_lob \n connect mshrs.io.brupdate.b2.uop.edge_inst, io.lsu.brupdate.b2.uop.edge_inst \n connect mshrs.io.brupdate.b2.uop.ftq_idx, io.lsu.brupdate.b2.uop.ftq_idx \n connect mshrs.io.brupdate.b2.uop.br_tag, io.lsu.brupdate.b2.uop.br_tag \n connect mshrs.io.brupdate.b2.uop.br_mask, io.lsu.brupdate.b2.uop.br_mask \n connect mshrs.io.brupdate.b2.uop.is_sfb, io.lsu.brupdate.b2.uop.is_sfb \n connect mshrs.io.brupdate.b2.uop.is_jal, io.lsu.brupdate.b2.uop.is_jal \n connect mshrs.io.brupdate.b2.uop.is_jalr, io.lsu.brupdate.b2.uop.is_jalr \n connect mshrs.io.brupdate.b2.uop.is_br, io.lsu.brupdate.b2.uop.is_br \n connect mshrs.io.brupdate.b2.uop.iw_p2_poisoned, io.lsu.brupdate.b2.uop.iw_p2_poisoned \n connect mshrs.io.brupdate.b2.uop.iw_p1_poisoned, io.lsu.brupdate.b2.uop.iw_p1_poisoned \n connect mshrs.io.brupdate.b2.uop.iw_state, io.lsu.brupdate.b2.uop.iw_state \n connect mshrs.io.brupdate.b2.uop.ctrl.is_std, io.lsu.brupdate.b2.uop.ctrl.is_std \n connect mshrs.io.brupdate.b2.uop.ctrl.is_sta, io.lsu.brupdate.b2.uop.ctrl.is_sta \n connect mshrs.io.brupdate.b2.uop.ctrl.is_load, io.lsu.brupdate.b2.uop.ctrl.is_load \n connect mshrs.io.brupdate.b2.uop.ctrl.csr_cmd, io.lsu.brupdate.b2.uop.ctrl.csr_cmd \n connect mshrs.io.brupdate.b2.uop.ctrl.fcn_dw, io.lsu.brupdate.b2.uop.ctrl.fcn_dw \n connect mshrs.io.brupdate.b2.uop.ctrl.op_fcn, io.lsu.brupdate.b2.uop.ctrl.op_fcn \n connect mshrs.io.brupdate.b2.uop.ctrl.imm_sel, io.lsu.brupdate.b2.uop.ctrl.imm_sel \n connect mshrs.io.brupdate.b2.uop.ctrl.op2_sel, io.lsu.brupdate.b2.uop.ctrl.op2_sel \n connect mshrs.io.brupdate.b2.uop.ctrl.op1_sel, io.lsu.brupdate.b2.uop.ctrl.op1_sel \n connect mshrs.io.brupdate.b2.uop.ctrl.br_type, io.lsu.brupdate.b2.uop.ctrl.br_type \n connect mshrs.io.brupdate.b2.uop.fu_code, io.lsu.brupdate.b2.uop.fu_code \n connect mshrs.io.brupdate.b2.uop.iq_type, io.lsu.brupdate.b2.uop.iq_type \n connect mshrs.io.brupdate.b2.uop.debug_pc, io.lsu.brupdate.b2.uop.debug_pc \n connect mshrs.io.brupdate.b2.uop.is_rvc, io.lsu.brupdate.b2.uop.is_rvc \n connect mshrs.io.brupdate.b2.uop.debug_inst, io.lsu.brupdate.b2.uop.debug_inst \n connect mshrs.io.brupdate.b2.uop.inst, io.lsu.brupdate.b2.uop.inst \n connect mshrs.io.brupdate.b2.uop.uopc, io.lsu.brupdate.b2.uop.uopc \n connect mshrs.io.brupdate.b1.mispredict_mask, io.lsu.brupdate.b1.mispredict_mask \n connect mshrs.io.brupdate.b1.resolve_mask, io.lsu.brupdate.b1.resolve_mask \n connect mshrs.io.exception, io.lsu.exception \n connect mshrs.io.rob_pnr_idx, io.lsu.rob_pnr_idx \n connect mshrs.io.rob_head_idx, io.lsu.rob_head_idx \n inst meta_0 of L1MetadataArray_1 \n connect meta_0.clock, clock\n\n connect meta_0.reset, reset\n\n inst metaWriteArb of Arbiter2_L1MetaWriteReq_1 \n connect metaWriteArb.clock, clock\n\n connect metaWriteArb.reset, reset\n\n inst metaReadArb of Arbiter6_BoomL1MetaReadReq_1 \n connect metaReadArb.clock, clock\n\n connect metaReadArb.reset, reset\n\n invalidate metaReadArb.io.in[0].bits.req[0].tag \n invalidate metaReadArb.io.in[0].bits.req[0].way_en \n invalidate metaReadArb.io.in[0].bits.req[0].idx \n invalidate metaReadArb.io.in[0].valid \n invalidate metaReadArb.io.in[0].ready \n invalidate metaReadArb.io.in[1].bits.req[0].tag \n invalidate metaReadArb.io.in[1].bits.req[0].way_en \n invalidate metaReadArb.io.in[1].bits.req[0].idx \n invalidate metaReadArb.io.in[1].valid \n invalidate metaReadArb.io.in[1].ready \n invalidate metaReadArb.io.in[2].bits.req[0].tag \n invalidate metaReadArb.io.in[2].bits.req[0].way_en \n invalidate metaReadArb.io.in[2].bits.req[0].idx \n invalidate metaReadArb.io.in[2].valid \n invalidate metaReadArb.io.in[2].ready \n invalidate metaReadArb.io.in[3].bits.req[0].tag \n invalidate metaReadArb.io.in[3].bits.req[0].way_en \n invalidate metaReadArb.io.in[3].bits.req[0].idx \n invalidate metaReadArb.io.in[3].valid \n invalidate metaReadArb.io.in[3].ready \n invalidate metaReadArb.io.in[4].bits.req[0].tag \n invalidate metaReadArb.io.in[4].bits.req[0].way_en \n invalidate metaReadArb.io.in[4].bits.req[0].idx \n invalidate metaReadArb.io.in[4].valid \n invalidate metaReadArb.io.in[4].ready \n invalidate metaReadArb.io.in[5].bits.req[0].tag \n invalidate metaReadArb.io.in[5].bits.req[0].way_en \n invalidate metaReadArb.io.in[5].bits.req[0].idx \n invalidate metaReadArb.io.in[5].valid \n invalidate metaReadArb.io.in[5].ready \n node _meta_0_io_write_valid_T = and(metaWriteArb.io.out.ready, metaWriteArb.io.out.valid) \n connect meta_0.io.write.valid, _meta_0_io_write_valid_T \n connect meta_0.io.write.bits.data.tag, metaWriteArb.io.out.bits.data.tag \n connect meta_0.io.write.bits.data.coh.state, metaWriteArb.io.out.bits.data.coh.state \n connect meta_0.io.write.bits.tag, metaWriteArb.io.out.bits.tag \n connect meta_0.io.write.bits.way_en, metaWriteArb.io.out.bits.way_en \n connect meta_0.io.write.bits.idx, metaWriteArb.io.out.bits.idx \n connect meta_0.io.read.valid, metaReadArb.io.out.valid \n connect meta_0.io.read.bits.tag, metaReadArb.io.out.bits.req[0].tag \n connect meta_0.io.read.bits.way_en, metaReadArb.io.out.bits.req[0].way_en \n connect meta_0.io.read.bits.idx, metaReadArb.io.out.bits.req[0].idx \n connect metaReadArb.io.out.ready, meta_0.io.read.ready \n connect metaWriteArb.io.out.ready, meta_0.io.write.ready \n inst data of BoomDuplicatedDataArray_1 \n connect data.clock, clock\n\n connect data.reset, reset\n\n inst dataWriteArb of Arbiter2_L1DataWriteReq_1 \n connect dataWriteArb.clock, clock\n\n connect dataWriteArb.reset, reset\n\n inst dataReadArb of Arbiter3_BoomL1DataReadReq_1 \n connect dataReadArb.clock, clock\n\n connect dataReadArb.reset, reset\n\n invalidate dataReadArb.io.in[0].bits.valid[0] \n invalidate dataReadArb.io.in[0].bits.req[0].addr \n invalidate dataReadArb.io.in[0].bits.req[0].way_en \n invalidate dataReadArb.io.in[0].valid \n invalidate dataReadArb.io.in[0].ready \n invalidate dataReadArb.io.in[1].bits.valid[0] \n invalidate dataReadArb.io.in[1].bits.req[0].addr \n invalidate dataReadArb.io.in[1].bits.req[0].way_en \n invalidate dataReadArb.io.in[1].valid \n invalidate dataReadArb.io.in[1].ready \n invalidate dataReadArb.io.in[2].bits.valid[0] \n invalidate dataReadArb.io.in[2].bits.req[0].addr \n invalidate dataReadArb.io.in[2].bits.req[0].way_en \n invalidate dataReadArb.io.in[2].valid \n invalidate dataReadArb.io.in[2].ready \n node _data_io_read_0_valid_T = and(dataReadArb.io.out.bits.valid[0], dataReadArb.io.out.valid) \n connect data.io.read[0].valid, _data_io_read_0_valid_T \n connect data.io.read[0].bits.addr, dataReadArb.io.out.bits.req[0].addr \n connect data.io.read[0].bits.way_en, dataReadArb.io.out.bits.req[0].way_en \n connect dataReadArb.io.out.ready, UInt<1>(0h1) \n node _data_io_write_valid_T = and(dataWriteArb.io.out.ready, dataWriteArb.io.out.valid) \n connect data.io.write.valid, _data_io_write_valid_T \n connect data.io.write.bits.data, dataWriteArb.io.out.bits.data \n connect data.io.write.bits.wmask, dataWriteArb.io.out.bits.wmask \n connect data.io.write.bits.addr, dataWriteArb.io.out.bits.addr \n connect data.io.write.bits.way_en, dataWriteArb.io.out.bits.way_en \n connect dataWriteArb.io.out.ready, UInt<1>(0h1) \n node _io_lsu_req_ready_T = and(metaReadArb.io.in[4].ready, dataReadArb.io.in[2].ready) \n connect io.lsu.req.ready, _io_lsu_req_ready_T \n connect metaReadArb.io.in[4].valid, io.lsu.req.valid \n connect dataReadArb.io.in[2].valid, io.lsu.req.valid \n node _metaReadArb_io_in_4_bits_req_0_idx_T = shr(io.lsu.req.bits[0].bits.addr, 6) \n connect metaReadArb.io.in[4].bits.req[0].idx, _metaReadArb_io_in_4_bits_req_0_idx_T \n invalidate metaReadArb.io.in[4].bits.req[0].way_en \n invalidate metaReadArb.io.in[4].bits.req[0].tag \n connect dataReadArb.io.in[2].bits.valid[0], io.lsu.req.bits[0].valid \n connect dataReadArb.io.in[2].bits.req[0].addr, io.lsu.req.bits[0].bits.addr \n node _dataReadArb_io_in_2_bits_req_0_way_en_T = not(UInt<2>(0h0)) \n connect dataReadArb.io.in[2].bits.req[0].way_en, _dataReadArb_io_in_2_bits_req_0_way_en_T \n wire replay_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1] \n invalidate replay_req[0].is_hella \n invalidate replay_req[0].data \n invalidate replay_req[0].addr \n invalidate replay_req[0].uop.debug_tsrc \n invalidate replay_req[0].uop.debug_fsrc \n invalidate replay_req[0].uop.bp_xcpt_if \n invalidate replay_req[0].uop.bp_debug_if \n invalidate replay_req[0].uop.xcpt_ma_if \n invalidate replay_req[0].uop.xcpt_ae_if \n invalidate replay_req[0].uop.xcpt_pf_if \n invalidate replay_req[0].uop.fp_single \n invalidate replay_req[0].uop.fp_val \n invalidate replay_req[0].uop.frs3_en \n invalidate replay_req[0].uop.lrs2_rtype \n invalidate replay_req[0].uop.lrs1_rtype \n invalidate replay_req[0].uop.dst_rtype \n invalidate replay_req[0].uop.ldst_val \n invalidate replay_req[0].uop.lrs3 \n invalidate replay_req[0].uop.lrs2 \n invalidate replay_req[0].uop.lrs1 \n invalidate replay_req[0].uop.ldst \n invalidate replay_req[0].uop.ldst_is_rs1 \n invalidate replay_req[0].uop.flush_on_commit \n invalidate replay_req[0].uop.is_unique \n invalidate replay_req[0].uop.is_sys_pc2epc \n invalidate replay_req[0].uop.uses_stq \n invalidate replay_req[0].uop.uses_ldq \n invalidate replay_req[0].uop.is_amo \n invalidate replay_req[0].uop.is_fencei \n invalidate replay_req[0].uop.is_fence \n invalidate replay_req[0].uop.mem_signed \n invalidate replay_req[0].uop.mem_size \n invalidate replay_req[0].uop.mem_cmd \n invalidate replay_req[0].uop.bypassable \n invalidate replay_req[0].uop.exc_cause \n invalidate replay_req[0].uop.exception \n invalidate replay_req[0].uop.stale_pdst \n invalidate replay_req[0].uop.ppred_busy \n invalidate replay_req[0].uop.prs3_busy \n invalidate replay_req[0].uop.prs2_busy \n invalidate replay_req[0].uop.prs1_busy \n invalidate replay_req[0].uop.ppred \n invalidate replay_req[0].uop.prs3 \n invalidate replay_req[0].uop.prs2 \n invalidate replay_req[0].uop.prs1 \n invalidate replay_req[0].uop.pdst \n invalidate replay_req[0].uop.rxq_idx \n invalidate replay_req[0].uop.stq_idx \n invalidate replay_req[0].uop.ldq_idx \n invalidate replay_req[0].uop.rob_idx \n invalidate replay_req[0].uop.csr_addr \n invalidate replay_req[0].uop.imm_packed \n invalidate replay_req[0].uop.taken \n invalidate replay_req[0].uop.pc_lob \n invalidate replay_req[0].uop.edge_inst \n invalidate replay_req[0].uop.ftq_idx \n invalidate replay_req[0].uop.br_tag \n invalidate replay_req[0].uop.br_mask \n invalidate replay_req[0].uop.is_sfb \n invalidate replay_req[0].uop.is_jal \n invalidate replay_req[0].uop.is_jalr \n invalidate replay_req[0].uop.is_br \n invalidate replay_req[0].uop.iw_p2_poisoned \n invalidate replay_req[0].uop.iw_p1_poisoned \n invalidate replay_req[0].uop.iw_state \n invalidate replay_req[0].uop.ctrl.is_std \n invalidate replay_req[0].uop.ctrl.is_sta \n invalidate replay_req[0].uop.ctrl.is_load \n invalidate replay_req[0].uop.ctrl.csr_cmd \n invalidate replay_req[0].uop.ctrl.fcn_dw \n invalidate replay_req[0].uop.ctrl.op_fcn \n invalidate replay_req[0].uop.ctrl.imm_sel \n invalidate replay_req[0].uop.ctrl.op2_sel \n invalidate replay_req[0].uop.ctrl.op1_sel \n invalidate replay_req[0].uop.ctrl.br_type \n invalidate replay_req[0].uop.fu_code \n invalidate replay_req[0].uop.iq_type \n invalidate replay_req[0].uop.debug_pc \n invalidate replay_req[0].uop.is_rvc \n invalidate replay_req[0].uop.debug_inst \n invalidate replay_req[0].uop.inst \n invalidate replay_req[0].uop.uopc \n connect replay_req[0].uop, mshrs.io.replay.bits.uop \n connect replay_req[0].addr, mshrs.io.replay.bits.addr \n connect replay_req[0].data, mshrs.io.replay.bits.data \n connect replay_req[0].is_hella, mshrs.io.replay.bits.is_hella \n node _mshrs_io_replay_ready_T = and(metaReadArb.io.in[0].ready, dataReadArb.io.in[0].ready) \n connect mshrs.io.replay.ready, _mshrs_io_replay_ready_T \n connect metaReadArb.io.in[0].valid, mshrs.io.replay.valid \n node _metaReadArb_io_in_0_bits_req_0_idx_T = shr(mshrs.io.replay.bits.addr, 6) \n connect metaReadArb.io.in[0].bits.req[0].idx, _metaReadArb_io_in_0_bits_req_0_idx_T \n invalidate metaReadArb.io.in[0].bits.req[0].way_en \n invalidate metaReadArb.io.in[0].bits.req[0].tag \n connect dataReadArb.io.in[0].valid, mshrs.io.replay.valid \n connect dataReadArb.io.in[0].bits.req[0].addr, mshrs.io.replay.bits.addr \n connect dataReadArb.io.in[0].bits.req[0].way_en, mshrs.io.replay.bits.way_en \n wire _WIRE : UInt<1>[1] \n connect _WIRE[0], UInt<1>(0h1) \n connect dataReadArb.io.in[0].bits.valid[0], _WIRE[0] \n wire mshr_read_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1] \n invalidate mshr_read_req[0].is_hella \n invalidate mshr_read_req[0].data \n invalidate mshr_read_req[0].addr \n invalidate mshr_read_req[0].uop.debug_tsrc \n invalidate mshr_read_req[0].uop.debug_fsrc \n invalidate mshr_read_req[0].uop.bp_xcpt_if \n invalidate mshr_read_req[0].uop.bp_debug_if \n invalidate mshr_read_req[0].uop.xcpt_ma_if \n invalidate mshr_read_req[0].uop.xcpt_ae_if \n invalidate mshr_read_req[0].uop.xcpt_pf_if \n invalidate mshr_read_req[0].uop.fp_single \n invalidate mshr_read_req[0].uop.fp_val \n invalidate mshr_read_req[0].uop.frs3_en \n invalidate mshr_read_req[0].uop.lrs2_rtype \n invalidate mshr_read_req[0].uop.lrs1_rtype \n invalidate mshr_read_req[0].uop.dst_rtype \n invalidate mshr_read_req[0].uop.ldst_val \n invalidate mshr_read_req[0].uop.lrs3 \n invalidate mshr_read_req[0].uop.lrs2 \n invalidate mshr_read_req[0].uop.lrs1 \n invalidate mshr_read_req[0].uop.ldst \n invalidate mshr_read_req[0].uop.ldst_is_rs1 \n invalidate mshr_read_req[0].uop.flush_on_commit \n invalidate mshr_read_req[0].uop.is_unique \n invalidate mshr_read_req[0].uop.is_sys_pc2epc \n invalidate mshr_read_req[0].uop.uses_stq \n invalidate mshr_read_req[0].uop.uses_ldq \n invalidate mshr_read_req[0].uop.is_amo \n invalidate mshr_read_req[0].uop.is_fencei \n invalidate mshr_read_req[0].uop.is_fence \n invalidate mshr_read_req[0].uop.mem_signed \n invalidate mshr_read_req[0].uop.mem_size \n invalidate mshr_read_req[0].uop.mem_cmd \n invalidate mshr_read_req[0].uop.bypassable \n invalidate mshr_read_req[0].uop.exc_cause \n invalidate mshr_read_req[0].uop.exception \n invalidate mshr_read_req[0].uop.stale_pdst \n invalidate mshr_read_req[0].uop.ppred_busy \n invalidate mshr_read_req[0].uop.prs3_busy \n invalidate mshr_read_req[0].uop.prs2_busy \n invalidate mshr_read_req[0].uop.prs1_busy \n invalidate mshr_read_req[0].uop.ppred \n invalidate mshr_read_req[0].uop.prs3 \n invalidate mshr_read_req[0].uop.prs2 \n invalidate mshr_read_req[0].uop.prs1 \n invalidate mshr_read_req[0].uop.pdst \n invalidate mshr_read_req[0].uop.rxq_idx \n invalidate mshr_read_req[0].uop.stq_idx \n invalidate mshr_read_req[0].uop.ldq_idx \n invalidate mshr_read_req[0].uop.rob_idx \n invalidate mshr_read_req[0].uop.csr_addr \n invalidate mshr_read_req[0].uop.imm_packed \n invalidate mshr_read_req[0].uop.taken \n invalidate mshr_read_req[0].uop.pc_lob \n invalidate mshr_read_req[0].uop.edge_inst \n invalidate mshr_read_req[0].uop.ftq_idx \n invalidate mshr_read_req[0].uop.br_tag \n invalidate mshr_read_req[0].uop.br_mask \n invalidate mshr_read_req[0].uop.is_sfb \n invalidate mshr_read_req[0].uop.is_jal \n invalidate mshr_read_req[0].uop.is_jalr \n invalidate mshr_read_req[0].uop.is_br \n invalidate mshr_read_req[0].uop.iw_p2_poisoned \n invalidate mshr_read_req[0].uop.iw_p1_poisoned \n invalidate mshr_read_req[0].uop.iw_state \n invalidate mshr_read_req[0].uop.ctrl.is_std \n invalidate mshr_read_req[0].uop.ctrl.is_sta \n invalidate mshr_read_req[0].uop.ctrl.is_load \n invalidate mshr_read_req[0].uop.ctrl.csr_cmd \n invalidate mshr_read_req[0].uop.ctrl.fcn_dw \n invalidate mshr_read_req[0].uop.ctrl.op_fcn \n invalidate mshr_read_req[0].uop.ctrl.imm_sel \n invalidate mshr_read_req[0].uop.ctrl.op2_sel \n invalidate mshr_read_req[0].uop.ctrl.op1_sel \n invalidate mshr_read_req[0].uop.ctrl.br_type \n invalidate mshr_read_req[0].uop.fu_code \n invalidate mshr_read_req[0].uop.iq_type \n invalidate mshr_read_req[0].uop.debug_pc \n invalidate mshr_read_req[0].uop.is_rvc \n invalidate mshr_read_req[0].uop.debug_inst \n invalidate mshr_read_req[0].uop.inst \n invalidate mshr_read_req[0].uop.uopc \n wire mshr_read_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} \n invalidate mshr_read_req_0_uop_uop.debug_tsrc \n invalidate mshr_read_req_0_uop_uop.debug_fsrc \n invalidate mshr_read_req_0_uop_uop.bp_xcpt_if \n invalidate mshr_read_req_0_uop_uop.bp_debug_if \n invalidate mshr_read_req_0_uop_uop.xcpt_ma_if \n invalidate mshr_read_req_0_uop_uop.xcpt_ae_if \n invalidate mshr_read_req_0_uop_uop.xcpt_pf_if \n invalidate mshr_read_req_0_uop_uop.fp_single \n invalidate mshr_read_req_0_uop_uop.fp_val \n invalidate mshr_read_req_0_uop_uop.frs3_en \n invalidate mshr_read_req_0_uop_uop.lrs2_rtype \n invalidate mshr_read_req_0_uop_uop.lrs1_rtype \n invalidate mshr_read_req_0_uop_uop.dst_rtype \n invalidate mshr_read_req_0_uop_uop.ldst_val \n invalidate mshr_read_req_0_uop_uop.lrs3 \n invalidate mshr_read_req_0_uop_uop.lrs2 \n invalidate mshr_read_req_0_uop_uop.lrs1 \n invalidate mshr_read_req_0_uop_uop.ldst \n invalidate mshr_read_req_0_uop_uop.ldst_is_rs1 \n invalidate mshr_read_req_0_uop_uop.flush_on_commit \n invalidate mshr_read_req_0_uop_uop.is_unique \n invalidate mshr_read_req_0_uop_uop.is_sys_pc2epc \n invalidate mshr_read_req_0_uop_uop.uses_stq \n invalidate mshr_read_req_0_uop_uop.uses_ldq \n invalidate mshr_read_req_0_uop_uop.is_amo \n invalidate mshr_read_req_0_uop_uop.is_fencei \n invalidate mshr_read_req_0_uop_uop.is_fence \n invalidate mshr_read_req_0_uop_uop.mem_signed \n invalidate mshr_read_req_0_uop_uop.mem_size \n invalidate mshr_read_req_0_uop_uop.mem_cmd \n invalidate mshr_read_req_0_uop_uop.bypassable \n invalidate mshr_read_req_0_uop_uop.exc_cause \n invalidate mshr_read_req_0_uop_uop.exception \n invalidate mshr_read_req_0_uop_uop.stale_pdst \n invalidate mshr_read_req_0_uop_uop.ppred_busy \n invalidate mshr_read_req_0_uop_uop.prs3_busy \n invalidate mshr_read_req_0_uop_uop.prs2_busy \n invalidate mshr_read_req_0_uop_uop.prs1_busy \n invalidate mshr_read_req_0_uop_uop.ppred \n invalidate mshr_read_req_0_uop_uop.prs3 \n invalidate mshr_read_req_0_uop_uop.prs2 \n invalidate mshr_read_req_0_uop_uop.prs1 \n invalidate mshr_read_req_0_uop_uop.pdst \n invalidate mshr_read_req_0_uop_uop.rxq_idx \n invalidate mshr_read_req_0_uop_uop.stq_idx \n invalidate mshr_read_req_0_uop_uop.ldq_idx \n invalidate mshr_read_req_0_uop_uop.rob_idx \n invalidate mshr_read_req_0_uop_uop.csr_addr \n invalidate mshr_read_req_0_uop_uop.imm_packed \n invalidate mshr_read_req_0_uop_uop.taken \n invalidate mshr_read_req_0_uop_uop.pc_lob \n invalidate mshr_read_req_0_uop_uop.edge_inst \n invalidate mshr_read_req_0_uop_uop.ftq_idx \n invalidate mshr_read_req_0_uop_uop.br_tag \n invalidate mshr_read_req_0_uop_uop.br_mask \n invalidate mshr_read_req_0_uop_uop.is_sfb \n invalidate mshr_read_req_0_uop_uop.is_jal \n invalidate mshr_read_req_0_uop_uop.is_jalr \n invalidate mshr_read_req_0_uop_uop.is_br \n invalidate mshr_read_req_0_uop_uop.iw_p2_poisoned \n invalidate mshr_read_req_0_uop_uop.iw_p1_poisoned \n invalidate mshr_read_req_0_uop_uop.iw_state \n invalidate mshr_read_req_0_uop_uop.ctrl.is_std \n invalidate mshr_read_req_0_uop_uop.ctrl.is_sta \n invalidate mshr_read_req_0_uop_uop.ctrl.is_load \n invalidate mshr_read_req_0_uop_uop.ctrl.csr_cmd \n invalidate mshr_read_req_0_uop_uop.ctrl.fcn_dw \n invalidate mshr_read_req_0_uop_uop.ctrl.op_fcn \n invalidate mshr_read_req_0_uop_uop.ctrl.imm_sel \n invalidate mshr_read_req_0_uop_uop.ctrl.op2_sel \n invalidate mshr_read_req_0_uop_uop.ctrl.op1_sel \n invalidate mshr_read_req_0_uop_uop.ctrl.br_type \n invalidate mshr_read_req_0_uop_uop.fu_code \n invalidate mshr_read_req_0_uop_uop.iq_type \n invalidate mshr_read_req_0_uop_uop.debug_pc \n invalidate mshr_read_req_0_uop_uop.is_rvc \n invalidate mshr_read_req_0_uop_uop.debug_inst \n invalidate mshr_read_req_0_uop_uop.inst \n invalidate mshr_read_req_0_uop_uop.uopc \n connect mshr_read_req_0_uop_uop.uopc, UInt<7>(0h0) \n connect mshr_read_req_0_uop_uop.bypassable, UInt<1>(0h0) \n connect mshr_read_req_0_uop_uop.fp_val, UInt<1>(0h0) \n connect mshr_read_req_0_uop_uop.uses_stq, UInt<1>(0h0) \n connect mshr_read_req_0_uop_uop.uses_ldq, UInt<1>(0h0) \n connect mshr_read_req_0_uop_uop.pdst, UInt<1>(0h0) \n connect mshr_read_req_0_uop_uop.dst_rtype, UInt<2>(0h2) \n wire mshr_read_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} \n invalidate mshr_read_req_0_uop_cs.is_std \n invalidate mshr_read_req_0_uop_cs.is_sta \n invalidate mshr_read_req_0_uop_cs.is_load \n invalidate mshr_read_req_0_uop_cs.csr_cmd \n invalidate mshr_read_req_0_uop_cs.fcn_dw \n invalidate mshr_read_req_0_uop_cs.op_fcn \n invalidate mshr_read_req_0_uop_cs.imm_sel \n invalidate mshr_read_req_0_uop_cs.op2_sel \n invalidate mshr_read_req_0_uop_cs.op1_sel \n invalidate mshr_read_req_0_uop_cs.br_type \n connect mshr_read_req_0_uop_cs.br_type, UInt<4>(0h0) \n connect mshr_read_req_0_uop_cs.csr_cmd, UInt<3>(0h0) \n connect mshr_read_req_0_uop_cs.is_load, UInt<1>(0h0) \n connect mshr_read_req_0_uop_cs.is_sta, UInt<1>(0h0) \n connect mshr_read_req_0_uop_cs.is_std, UInt<1>(0h0) \n connect mshr_read_req_0_uop_uop.ctrl, mshr_read_req_0_uop_cs \n connect mshr_read_req[0].uop, mshr_read_req_0_uop_uop \n node _mshr_read_req_0_addr_T = cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) \n node _mshr_read_req_0_addr_T_1 = shl(_mshr_read_req_0_addr_T, 6) \n connect mshr_read_req[0].addr, _mshr_read_req_0_addr_T_1 \n invalidate mshr_read_req[0].data \n connect mshr_read_req[0].is_hella, UInt<1>(0h0) \n connect metaReadArb.io.in[3].valid, mshrs.io.meta_read.valid \n connect metaReadArb.io.in[3].bits.req[0].tag, mshrs.io.meta_read.bits.tag \n connect metaReadArb.io.in[3].bits.req[0].way_en, mshrs.io.meta_read.bits.way_en \n connect metaReadArb.io.in[3].bits.req[0].idx, mshrs.io.meta_read.bits.idx \n connect mshrs.io.meta_read.ready, metaReadArb.io.in[3].ready \n node _wb_fire_T = and(wb.io.meta_read.ready, wb.io.meta_read.valid) \n node _wb_fire_T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid) \n node wb_fire = and(_wb_fire_T, _wb_fire_T_1) \n wire wb_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1] \n invalidate wb_req[0].is_hella \n invalidate wb_req[0].data \n invalidate wb_req[0].addr \n invalidate wb_req[0].uop.debug_tsrc \n invalidate wb_req[0].uop.debug_fsrc \n invalidate wb_req[0].uop.bp_xcpt_if \n invalidate wb_req[0].uop.bp_debug_if \n invalidate wb_req[0].uop.xcpt_ma_if \n invalidate wb_req[0].uop.xcpt_ae_if \n invalidate wb_req[0].uop.xcpt_pf_if \n invalidate wb_req[0].uop.fp_single \n invalidate wb_req[0].uop.fp_val \n invalidate wb_req[0].uop.frs3_en \n invalidate wb_req[0].uop.lrs2_rtype \n invalidate wb_req[0].uop.lrs1_rtype \n invalidate wb_req[0].uop.dst_rtype \n invalidate wb_req[0].uop.ldst_val \n invalidate wb_req[0].uop.lrs3 \n invalidate wb_req[0].uop.lrs2 \n invalidate wb_req[0].uop.lrs1 \n invalidate wb_req[0].uop.ldst \n invalidate wb_req[0].uop.ldst_is_rs1 \n invalidate wb_req[0].uop.flush_on_commit \n invalidate wb_req[0].uop.is_unique \n invalidate wb_req[0].uop.is_sys_pc2epc \n invalidate wb_req[0].uop.uses_stq \n invalidate wb_req[0].uop.uses_ldq \n invalidate wb_req[0].uop.is_amo \n invalidate wb_req[0].uop.is_fencei \n invalidate wb_req[0].uop.is_fence \n invalidate wb_req[0].uop.mem_signed \n invalidate wb_req[0].uop.mem_size \n invalidate wb_req[0].uop.mem_cmd \n invalidate wb_req[0].uop.bypassable \n invalidate wb_req[0].uop.exc_cause \n invalidate wb_req[0].uop.exception \n invalidate wb_req[0].uop.stale_pdst \n invalidate wb_req[0].uop.ppred_busy \n invalidate wb_req[0].uop.prs3_busy \n invalidate wb_req[0].uop.prs2_busy \n invalidate wb_req[0].uop.prs1_busy \n invalidate wb_req[0].uop.ppred \n invalidate wb_req[0].uop.prs3 \n invalidate wb_req[0].uop.prs2 \n invalidate wb_req[0].uop.prs1 \n invalidate wb_req[0].uop.pdst \n invalidate wb_req[0].uop.rxq_idx \n invalidate wb_req[0].uop.stq_idx \n invalidate wb_req[0].uop.ldq_idx \n invalidate wb_req[0].uop.rob_idx \n invalidate wb_req[0].uop.csr_addr \n invalidate wb_req[0].uop.imm_packed \n invalidate wb_req[0].uop.taken \n invalidate wb_req[0].uop.pc_lob \n invalidate wb_req[0].uop.edge_inst \n invalidate wb_req[0].uop.ftq_idx \n invalidate wb_req[0].uop.br_tag \n invalidate wb_req[0].uop.br_mask \n invalidate wb_req[0].uop.is_sfb \n invalidate wb_req[0].uop.is_jal \n invalidate wb_req[0].uop.is_jalr \n invalidate wb_req[0].uop.is_br \n invalidate wb_req[0].uop.iw_p2_poisoned \n invalidate wb_req[0].uop.iw_p1_poisoned \n invalidate wb_req[0].uop.iw_state \n invalidate wb_req[0].uop.ctrl.is_std \n invalidate wb_req[0].uop.ctrl.is_sta \n invalidate wb_req[0].uop.ctrl.is_load \n invalidate wb_req[0].uop.ctrl.csr_cmd \n invalidate wb_req[0].uop.ctrl.fcn_dw \n invalidate wb_req[0].uop.ctrl.op_fcn \n invalidate wb_req[0].uop.ctrl.imm_sel \n invalidate wb_req[0].uop.ctrl.op2_sel \n invalidate wb_req[0].uop.ctrl.op1_sel \n invalidate wb_req[0].uop.ctrl.br_type \n invalidate wb_req[0].uop.fu_code \n invalidate wb_req[0].uop.iq_type \n invalidate wb_req[0].uop.debug_pc \n invalidate wb_req[0].uop.is_rvc \n invalidate wb_req[0].uop.debug_inst \n invalidate wb_req[0].uop.inst \n invalidate wb_req[0].uop.uopc \n wire wb_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} \n invalidate wb_req_0_uop_uop.debug_tsrc \n invalidate wb_req_0_uop_uop.debug_fsrc \n invalidate wb_req_0_uop_uop.bp_xcpt_if \n invalidate wb_req_0_uop_uop.bp_debug_if \n invalidate wb_req_0_uop_uop.xcpt_ma_if \n invalidate wb_req_0_uop_uop.xcpt_ae_if \n invalidate wb_req_0_uop_uop.xcpt_pf_if \n invalidate wb_req_0_uop_uop.fp_single \n invalidate wb_req_0_uop_uop.fp_val \n invalidate wb_req_0_uop_uop.frs3_en \n invalidate wb_req_0_uop_uop.lrs2_rtype \n invalidate wb_req_0_uop_uop.lrs1_rtype \n invalidate wb_req_0_uop_uop.dst_rtype \n invalidate wb_req_0_uop_uop.ldst_val \n invalidate wb_req_0_uop_uop.lrs3 \n invalidate wb_req_0_uop_uop.lrs2 \n invalidate wb_req_0_uop_uop.lrs1 \n invalidate wb_req_0_uop_uop.ldst \n invalidate wb_req_0_uop_uop.ldst_is_rs1 \n invalidate wb_req_0_uop_uop.flush_on_commit \n invalidate wb_req_0_uop_uop.is_unique \n invalidate wb_req_0_uop_uop.is_sys_pc2epc \n invalidate wb_req_0_uop_uop.uses_stq \n invalidate wb_req_0_uop_uop.uses_ldq \n invalidate wb_req_0_uop_uop.is_amo \n invalidate wb_req_0_uop_uop.is_fencei \n invalidate wb_req_0_uop_uop.is_fence \n invalidate wb_req_0_uop_uop.mem_signed \n invalidate wb_req_0_uop_uop.mem_size \n invalidate wb_req_0_uop_uop.mem_cmd \n invalidate wb_req_0_uop_uop.bypassable \n invalidate wb_req_0_uop_uop.exc_cause \n invalidate wb_req_0_uop_uop.exception \n invalidate wb_req_0_uop_uop.stale_pdst \n invalidate wb_req_0_uop_uop.ppred_busy \n invalidate wb_req_0_uop_uop.prs3_busy \n invalidate wb_req_0_uop_uop.prs2_busy \n invalidate wb_req_0_uop_uop.prs1_busy \n invalidate wb_req_0_uop_uop.ppred \n invalidate wb_req_0_uop_uop.prs3 \n invalidate wb_req_0_uop_uop.prs2 \n invalidate wb_req_0_uop_uop.prs1 \n invalidate wb_req_0_uop_uop.pdst \n invalidate wb_req_0_uop_uop.rxq_idx \n invalidate wb_req_0_uop_uop.stq_idx \n invalidate wb_req_0_uop_uop.ldq_idx \n invalidate wb_req_0_uop_uop.rob_idx \n invalidate wb_req_0_uop_uop.csr_addr \n invalidate wb_req_0_uop_uop.imm_packed \n invalidate wb_req_0_uop_uop.taken \n invalidate wb_req_0_uop_uop.pc_lob \n invalidate wb_req_0_uop_uop.edge_inst \n invalidate wb_req_0_uop_uop.ftq_idx \n invalidate wb_req_0_uop_uop.br_tag \n invalidate wb_req_0_uop_uop.br_mask \n invalidate wb_req_0_uop_uop.is_sfb \n invalidate wb_req_0_uop_uop.is_jal \n invalidate wb_req_0_uop_uop.is_jalr \n invalidate wb_req_0_uop_uop.is_br \n invalidate wb_req_0_uop_uop.iw_p2_poisoned \n invalidate wb_req_0_uop_uop.iw_p1_poisoned \n invalidate wb_req_0_uop_uop.iw_state \n invalidate wb_req_0_uop_uop.ctrl.is_std \n invalidate wb_req_0_uop_uop.ctrl.is_sta \n invalidate wb_req_0_uop_uop.ctrl.is_load \n invalidate wb_req_0_uop_uop.ctrl.csr_cmd \n invalidate wb_req_0_uop_uop.ctrl.fcn_dw \n invalidate wb_req_0_uop_uop.ctrl.op_fcn \n invalidate wb_req_0_uop_uop.ctrl.imm_sel \n invalidate wb_req_0_uop_uop.ctrl.op2_sel \n invalidate wb_req_0_uop_uop.ctrl.op1_sel \n invalidate wb_req_0_uop_uop.ctrl.br_type \n invalidate wb_req_0_uop_uop.fu_code \n invalidate wb_req_0_uop_uop.iq_type \n invalidate wb_req_0_uop_uop.debug_pc \n invalidate wb_req_0_uop_uop.is_rvc \n invalidate wb_req_0_uop_uop.debug_inst \n invalidate wb_req_0_uop_uop.inst \n invalidate wb_req_0_uop_uop.uopc \n connect wb_req_0_uop_uop.uopc, UInt<7>(0h0) \n connect wb_req_0_uop_uop.bypassable, UInt<1>(0h0) \n connect wb_req_0_uop_uop.fp_val, UInt<1>(0h0) \n connect wb_req_0_uop_uop.uses_stq, UInt<1>(0h0) \n connect wb_req_0_uop_uop.uses_ldq, UInt<1>(0h0) \n connect wb_req_0_uop_uop.pdst, UInt<1>(0h0) \n connect wb_req_0_uop_uop.dst_rtype, UInt<2>(0h2) \n wire wb_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} \n invalidate wb_req_0_uop_cs.is_std \n invalidate wb_req_0_uop_cs.is_sta \n invalidate wb_req_0_uop_cs.is_load \n invalidate wb_req_0_uop_cs.csr_cmd \n invalidate wb_req_0_uop_cs.fcn_dw \n invalidate wb_req_0_uop_cs.op_fcn \n invalidate wb_req_0_uop_cs.imm_sel \n invalidate wb_req_0_uop_cs.op2_sel \n invalidate wb_req_0_uop_cs.op1_sel \n invalidate wb_req_0_uop_cs.br_type \n connect wb_req_0_uop_cs.br_type, UInt<4>(0h0) \n connect wb_req_0_uop_cs.csr_cmd, UInt<3>(0h0) \n connect wb_req_0_uop_cs.is_load, UInt<1>(0h0) \n connect wb_req_0_uop_cs.is_sta, UInt<1>(0h0) \n connect wb_req_0_uop_cs.is_std, UInt<1>(0h0) \n connect wb_req_0_uop_uop.ctrl, wb_req_0_uop_cs \n connect wb_req[0].uop, wb_req_0_uop_uop \n node _wb_req_0_addr_T = cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr) \n connect wb_req[0].addr, _wb_req_0_addr_T \n invalidate wb_req[0].data \n connect wb_req[0].is_hella, UInt<1>(0h0) \n connect metaReadArb.io.in[2].valid, wb.io.meta_read.valid \n connect metaReadArb.io.in[2].bits.req[0].tag, wb.io.meta_read.bits.tag \n connect metaReadArb.io.in[2].bits.req[0].way_en, wb.io.meta_read.bits.way_en \n connect metaReadArb.io.in[2].bits.req[0].idx, wb.io.meta_read.bits.idx \n node _wb_io_meta_read_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready) \n connect wb.io.meta_read.ready, _wb_io_meta_read_ready_T \n connect dataReadArb.io.in[1].valid, wb.io.data_req.valid \n connect dataReadArb.io.in[1].bits.req[0].addr, wb.io.data_req.bits.addr \n connect dataReadArb.io.in[1].bits.req[0].way_en, wb.io.data_req.bits.way_en \n wire _WIRE_1 : UInt<1>[1] \n connect _WIRE_1[0], UInt<1>(0h1) \n connect dataReadArb.io.in[1].bits.valid[0], _WIRE_1[0] \n node _wb_io_data_req_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready) \n connect wb.io.data_req.ready, _wb_io_data_req_ready_T \n node _T = and(wb.io.meta_read.ready, wb.io.meta_read.valid) \n node _T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid) \n node _T_2 = xor(_T, _T_1) \n node _T_3 = eq(_T_2, UInt<1>(0h0)) \n node _T_4 = asUInt(reset) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n when _T_5 : \n node _T_6 = eq(_T_3, UInt<1>(0h0)) \n when _T_6 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at dcache.scala:548 assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))\\n\") : printf \n assert(clock, _T_3, UInt<1>(0h1), \"\") : assert \n node prober_fire = and(prober.io.meta_read.ready, prober.io.meta_read.valid) \n wire prober_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1] \n invalidate prober_req[0].is_hella \n invalidate prober_req[0].data \n invalidate prober_req[0].addr \n invalidate prober_req[0].uop.debug_tsrc \n invalidate prober_req[0].uop.debug_fsrc \n invalidate prober_req[0].uop.bp_xcpt_if \n invalidate prober_req[0].uop.bp_debug_if \n invalidate prober_req[0].uop.xcpt_ma_if \n invalidate prober_req[0].uop.xcpt_ae_if \n invalidate prober_req[0].uop.xcpt_pf_if \n invalidate prober_req[0].uop.fp_single \n invalidate prober_req[0].uop.fp_val \n invalidate prober_req[0].uop.frs3_en \n invalidate prober_req[0].uop.lrs2_rtype \n invalidate prober_req[0].uop.lrs1_rtype \n invalidate prober_req[0].uop.dst_rtype \n invalidate prober_req[0].uop.ldst_val \n invalidate prober_req[0].uop.lrs3 \n invalidate prober_req[0].uop.lrs2 \n invalidate prober_req[0].uop.lrs1 \n invalidate prober_req[0].uop.ldst \n invalidate prober_req[0].uop.ldst_is_rs1 \n invalidate prober_req[0].uop.flush_on_commit \n invalidate prober_req[0].uop.is_unique \n invalidate prober_req[0].uop.is_sys_pc2epc \n invalidate prober_req[0].uop.uses_stq \n invalidate prober_req[0].uop.uses_ldq \n invalidate prober_req[0].uop.is_amo \n invalidate prober_req[0].uop.is_fencei \n invalidate prober_req[0].uop.is_fence \n invalidate prober_req[0].uop.mem_signed \n invalidate prober_req[0].uop.mem_size \n invalidate prober_req[0].uop.mem_cmd \n invalidate prober_req[0].uop.bypassable \n invalidate prober_req[0].uop.exc_cause \n invalidate prober_req[0].uop.exception \n invalidate prober_req[0].uop.stale_pdst \n invalidate prober_req[0].uop.ppred_busy \n invalidate prober_req[0].uop.prs3_busy \n invalidate prober_req[0].uop.prs2_busy \n invalidate prober_req[0].uop.prs1_busy \n invalidate prober_req[0].uop.ppred \n invalidate prober_req[0].uop.prs3 \n invalidate prober_req[0].uop.prs2 \n invalidate prober_req[0].uop.prs1 \n invalidate prober_req[0].uop.pdst \n invalidate prober_req[0].uop.rxq_idx \n invalidate prober_req[0].uop.stq_idx \n invalidate prober_req[0].uop.ldq_idx \n invalidate prober_req[0].uop.rob_idx \n invalidate prober_req[0].uop.csr_addr \n invalidate prober_req[0].uop.imm_packed \n invalidate prober_req[0].uop.taken \n invalidate prober_req[0].uop.pc_lob \n invalidate prober_req[0].uop.edge_inst \n invalidate prober_req[0].uop.ftq_idx \n invalidate prober_req[0].uop.br_tag \n invalidate prober_req[0].uop.br_mask \n invalidate prober_req[0].uop.is_sfb \n invalidate prober_req[0].uop.is_jal \n invalidate prober_req[0].uop.is_jalr \n invalidate prober_req[0].uop.is_br \n invalidate prober_req[0].uop.iw_p2_poisoned \n invalidate prober_req[0].uop.iw_p1_poisoned \n invalidate prober_req[0].uop.iw_state \n invalidate prober_req[0].uop.ctrl.is_std \n invalidate prober_req[0].uop.ctrl.is_sta \n invalidate prober_req[0].uop.ctrl.is_load \n invalidate prober_req[0].uop.ctrl.csr_cmd \n invalidate prober_req[0].uop.ctrl.fcn_dw \n invalidate prober_req[0].uop.ctrl.op_fcn \n invalidate prober_req[0].uop.ctrl.imm_sel \n invalidate prober_req[0].uop.ctrl.op2_sel \n invalidate prober_req[0].uop.ctrl.op1_sel \n invalidate prober_req[0].uop.ctrl.br_type \n invalidate prober_req[0].uop.fu_code \n invalidate prober_req[0].uop.iq_type \n invalidate prober_req[0].uop.debug_pc \n invalidate prober_req[0].uop.is_rvc \n invalidate prober_req[0].uop.debug_inst \n invalidate prober_req[0].uop.inst \n invalidate prober_req[0].uop.uopc \n wire prober_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} \n invalidate prober_req_0_uop_uop.debug_tsrc \n invalidate prober_req_0_uop_uop.debug_fsrc \n invalidate prober_req_0_uop_uop.bp_xcpt_if \n invalidate prober_req_0_uop_uop.bp_debug_if \n invalidate prober_req_0_uop_uop.xcpt_ma_if \n invalidate prober_req_0_uop_uop.xcpt_ae_if \n invalidate prober_req_0_uop_uop.xcpt_pf_if \n invalidate prober_req_0_uop_uop.fp_single \n invalidate prober_req_0_uop_uop.fp_val \n invalidate prober_req_0_uop_uop.frs3_en \n invalidate prober_req_0_uop_uop.lrs2_rtype \n invalidate prober_req_0_uop_uop.lrs1_rtype \n invalidate prober_req_0_uop_uop.dst_rtype \n invalidate prober_req_0_uop_uop.ldst_val \n invalidate prober_req_0_uop_uop.lrs3 \n invalidate prober_req_0_uop_uop.lrs2 \n invalidate prober_req_0_uop_uop.lrs1 \n invalidate prober_req_0_uop_uop.ldst \n invalidate prober_req_0_uop_uop.ldst_is_rs1 \n invalidate prober_req_0_uop_uop.flush_on_commit \n invalidate prober_req_0_uop_uop.is_unique \n invalidate prober_req_0_uop_uop.is_sys_pc2epc \n invalidate prober_req_0_uop_uop.uses_stq \n invalidate prober_req_0_uop_uop.uses_ldq \n invalidate prober_req_0_uop_uop.is_amo \n invalidate prober_req_0_uop_uop.is_fencei \n invalidate prober_req_0_uop_uop.is_fence \n invalidate prober_req_0_uop_uop.mem_signed \n invalidate prober_req_0_uop_uop.mem_size \n invalidate prober_req_0_uop_uop.mem_cmd \n invalidate prober_req_0_uop_uop.bypassable \n invalidate prober_req_0_uop_uop.exc_cause \n invalidate prober_req_0_uop_uop.exception \n invalidate prober_req_0_uop_uop.stale_pdst \n invalidate prober_req_0_uop_uop.ppred_busy \n invalidate prober_req_0_uop_uop.prs3_busy \n invalidate prober_req_0_uop_uop.prs2_busy \n invalidate prober_req_0_uop_uop.prs1_busy \n invalidate prober_req_0_uop_uop.ppred \n invalidate prober_req_0_uop_uop.prs3 \n invalidate prober_req_0_uop_uop.prs2 \n invalidate prober_req_0_uop_uop.prs1 \n invalidate prober_req_0_uop_uop.pdst \n invalidate prober_req_0_uop_uop.rxq_idx \n invalidate prober_req_0_uop_uop.stq_idx \n invalidate prober_req_0_uop_uop.ldq_idx \n invalidate prober_req_0_uop_uop.rob_idx \n invalidate prober_req_0_uop_uop.csr_addr \n invalidate prober_req_0_uop_uop.imm_packed \n invalidate prober_req_0_uop_uop.taken \n invalidate prober_req_0_uop_uop.pc_lob \n invalidate prober_req_0_uop_uop.edge_inst \n invalidate prober_req_0_uop_uop.ftq_idx \n invalidate prober_req_0_uop_uop.br_tag \n invalidate prober_req_0_uop_uop.br_mask \n invalidate prober_req_0_uop_uop.is_sfb \n invalidate prober_req_0_uop_uop.is_jal \n invalidate prober_req_0_uop_uop.is_jalr \n invalidate prober_req_0_uop_uop.is_br \n invalidate prober_req_0_uop_uop.iw_p2_poisoned \n invalidate prober_req_0_uop_uop.iw_p1_poisoned \n invalidate prober_req_0_uop_uop.iw_state \n invalidate prober_req_0_uop_uop.ctrl.is_std \n invalidate prober_req_0_uop_uop.ctrl.is_sta \n invalidate prober_req_0_uop_uop.ctrl.is_load \n invalidate prober_req_0_uop_uop.ctrl.csr_cmd \n invalidate prober_req_0_uop_uop.ctrl.fcn_dw \n invalidate prober_req_0_uop_uop.ctrl.op_fcn \n invalidate prober_req_0_uop_uop.ctrl.imm_sel \n invalidate prober_req_0_uop_uop.ctrl.op2_sel \n invalidate prober_req_0_uop_uop.ctrl.op1_sel \n invalidate prober_req_0_uop_uop.ctrl.br_type \n invalidate prober_req_0_uop_uop.fu_code \n invalidate prober_req_0_uop_uop.iq_type \n invalidate prober_req_0_uop_uop.debug_pc \n invalidate prober_req_0_uop_uop.is_rvc \n invalidate prober_req_0_uop_uop.debug_inst \n invalidate prober_req_0_uop_uop.inst \n invalidate prober_req_0_uop_uop.uopc \n connect prober_req_0_uop_uop.uopc, UInt<7>(0h0) \n connect prober_req_0_uop_uop.bypassable, UInt<1>(0h0) \n connect prober_req_0_uop_uop.fp_val, UInt<1>(0h0) \n connect prober_req_0_uop_uop.uses_stq, UInt<1>(0h0) \n connect prober_req_0_uop_uop.uses_ldq, UInt<1>(0h0) \n connect prober_req_0_uop_uop.pdst, UInt<1>(0h0) \n connect prober_req_0_uop_uop.dst_rtype, UInt<2>(0h2) \n wire prober_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} \n invalidate prober_req_0_uop_cs.is_std \n invalidate prober_req_0_uop_cs.is_sta \n invalidate prober_req_0_uop_cs.is_load \n invalidate prober_req_0_uop_cs.csr_cmd \n invalidate prober_req_0_uop_cs.fcn_dw \n invalidate prober_req_0_uop_cs.op_fcn \n invalidate prober_req_0_uop_cs.imm_sel \n invalidate prober_req_0_uop_cs.op2_sel \n invalidate prober_req_0_uop_cs.op1_sel \n invalidate prober_req_0_uop_cs.br_type \n connect prober_req_0_uop_cs.br_type, UInt<4>(0h0) \n connect prober_req_0_uop_cs.csr_cmd, UInt<3>(0h0) \n connect prober_req_0_uop_cs.is_load, UInt<1>(0h0) \n connect prober_req_0_uop_cs.is_sta, UInt<1>(0h0) \n connect prober_req_0_uop_cs.is_std, UInt<1>(0h0) \n connect prober_req_0_uop_uop.ctrl, prober_req_0_uop_cs \n connect prober_req[0].uop, prober_req_0_uop_uop \n node _prober_req_0_addr_T = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) \n node _prober_req_0_addr_T_1 = shl(_prober_req_0_addr_T, 6) \n connect prober_req[0].addr, _prober_req_0_addr_T_1 \n invalidate prober_req[0].data \n connect prober_req[0].is_hella, UInt<1>(0h0) \n connect metaReadArb.io.in[1].valid, prober.io.meta_read.valid \n connect metaReadArb.io.in[1].bits.req[0].tag, prober.io.meta_read.bits.tag \n connect metaReadArb.io.in[1].bits.req[0].way_en, prober.io.meta_read.bits.way_en \n connect metaReadArb.io.in[1].bits.req[0].idx, prober.io.meta_read.bits.idx \n connect prober.io.meta_read.ready, metaReadArb.io.in[1].ready \n node prefetch_fire = and(mshrs.io.prefetch.ready, mshrs.io.prefetch.valid) \n wire prefetch_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1] \n invalidate prefetch_req[0].is_hella \n invalidate prefetch_req[0].data \n invalidate prefetch_req[0].addr \n invalidate prefetch_req[0].uop.debug_tsrc \n invalidate prefetch_req[0].uop.debug_fsrc \n invalidate prefetch_req[0].uop.bp_xcpt_if \n invalidate prefetch_req[0].uop.bp_debug_if \n invalidate prefetch_req[0].uop.xcpt_ma_if \n invalidate prefetch_req[0].uop.xcpt_ae_if \n invalidate prefetch_req[0].uop.xcpt_pf_if \n invalidate prefetch_req[0].uop.fp_single \n invalidate prefetch_req[0].uop.fp_val \n invalidate prefetch_req[0].uop.frs3_en \n invalidate prefetch_req[0].uop.lrs2_rtype \n invalidate prefetch_req[0].uop.lrs1_rtype \n invalidate prefetch_req[0].uop.dst_rtype \n invalidate prefetch_req[0].uop.ldst_val \n invalidate prefetch_req[0].uop.lrs3 \n invalidate prefetch_req[0].uop.lrs2 \n invalidate prefetch_req[0].uop.lrs1 \n invalidate prefetch_req[0].uop.ldst \n invalidate prefetch_req[0].uop.ldst_is_rs1 \n invalidate prefetch_req[0].uop.flush_on_commit \n invalidate prefetch_req[0].uop.is_unique \n invalidate prefetch_req[0].uop.is_sys_pc2epc \n invalidate prefetch_req[0].uop.uses_stq \n invalidate prefetch_req[0].uop.uses_ldq \n invalidate prefetch_req[0].uop.is_amo \n invalidate prefetch_req[0].uop.is_fencei \n invalidate prefetch_req[0].uop.is_fence \n invalidate prefetch_req[0].uop.mem_signed \n invalidate prefetch_req[0].uop.mem_size \n invalidate prefetch_req[0].uop.mem_cmd \n invalidate prefetch_req[0].uop.bypassable \n invalidate prefetch_req[0].uop.exc_cause \n invalidate prefetch_req[0].uop.exception \n invalidate prefetch_req[0].uop.stale_pdst \n invalidate prefetch_req[0].uop.ppred_busy \n invalidate prefetch_req[0].uop.prs3_busy \n invalidate prefetch_req[0].uop.prs2_busy \n invalidate prefetch_req[0].uop.prs1_busy \n invalidate prefetch_req[0].uop.ppred \n invalidate prefetch_req[0].uop.prs3 \n invalidate prefetch_req[0].uop.prs2 \n invalidate prefetch_req[0].uop.prs1 \n invalidate prefetch_req[0].uop.pdst \n invalidate prefetch_req[0].uop.rxq_idx \n invalidate prefetch_req[0].uop.stq_idx \n invalidate prefetch_req[0].uop.ldq_idx \n invalidate prefetch_req[0].uop.rob_idx \n invalidate prefetch_req[0].uop.csr_addr \n invalidate prefetch_req[0].uop.imm_packed \n invalidate prefetch_req[0].uop.taken \n invalidate prefetch_req[0].uop.pc_lob \n invalidate prefetch_req[0].uop.edge_inst \n invalidate prefetch_req[0].uop.ftq_idx \n invalidate prefetch_req[0].uop.br_tag \n invalidate prefetch_req[0].uop.br_mask \n invalidate prefetch_req[0].uop.is_sfb \n invalidate prefetch_req[0].uop.is_jal \n invalidate prefetch_req[0].uop.is_jalr \n invalidate prefetch_req[0].uop.is_br \n invalidate prefetch_req[0].uop.iw_p2_poisoned \n invalidate prefetch_req[0].uop.iw_p1_poisoned \n invalidate prefetch_req[0].uop.iw_state \n invalidate prefetch_req[0].uop.ctrl.is_std \n invalidate prefetch_req[0].uop.ctrl.is_sta \n invalidate prefetch_req[0].uop.ctrl.is_load \n invalidate prefetch_req[0].uop.ctrl.csr_cmd \n invalidate prefetch_req[0].uop.ctrl.fcn_dw \n invalidate prefetch_req[0].uop.ctrl.op_fcn \n invalidate prefetch_req[0].uop.ctrl.imm_sel \n invalidate prefetch_req[0].uop.ctrl.op2_sel \n invalidate prefetch_req[0].uop.ctrl.op1_sel \n invalidate prefetch_req[0].uop.ctrl.br_type \n invalidate prefetch_req[0].uop.fu_code \n invalidate prefetch_req[0].uop.iq_type \n invalidate prefetch_req[0].uop.debug_pc \n invalidate prefetch_req[0].uop.is_rvc \n invalidate prefetch_req[0].uop.debug_inst \n invalidate prefetch_req[0].uop.inst \n invalidate prefetch_req[0].uop.uopc \n connect prefetch_req[0], mshrs.io.prefetch.bits \n connect metaReadArb.io.in[5].valid, mshrs.io.prefetch.valid \n node _metaReadArb_io_in_5_bits_req_0_idx_T = shr(mshrs.io.prefetch.bits.addr, 6) \n connect metaReadArb.io.in[5].bits.req[0].idx, _metaReadArb_io_in_5_bits_req_0_idx_T \n invalidate metaReadArb.io.in[5].bits.req[0].way_en \n invalidate metaReadArb.io.in[5].bits.req[0].tag \n connect mshrs.io.prefetch.ready, metaReadArb.io.in[5].ready \n node _s0_valid_T = and(io.lsu.req.ready, io.lsu.req.valid) \n wire _s0_valid_WIRE : UInt<1>[1] \n connect _s0_valid_WIRE[0], io.lsu.req.bits[0].valid \n node _s0_valid_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid) \n node _s0_valid_T_2 = or(_s0_valid_T_1, wb_fire) \n node _s0_valid_T_3 = or(_s0_valid_T_2, prober_fire) \n node _s0_valid_T_4 = or(_s0_valid_T_3, prefetch_fire) \n node _s0_valid_T_5 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid) \n node _s0_valid_T_6 = or(_s0_valid_T_4, _s0_valid_T_5) \n wire _s0_valid_WIRE_1 : UInt<1>[1] \n connect _s0_valid_WIRE_1[0], UInt<1>(0h1) \n wire _s0_valid_WIRE_2 : UInt<1>[1] \n connect _s0_valid_WIRE_2[0], UInt<1>(0h0) \n node _s0_valid_T_7 = mux(_s0_valid_T_6, _s0_valid_WIRE_1, _s0_valid_WIRE_2) \n node s0_valid = mux(_s0_valid_T, _s0_valid_WIRE, _s0_valid_T_7) \n node _s0_req_T = and(io.lsu.req.ready, io.lsu.req.valid) \n wire _s0_req_WIRE : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1] \n connect _s0_req_WIRE[0], io.lsu.req.bits[0].bits \n node _s0_req_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid) \n node _s0_req_T_2 = mux(_s0_req_T_1, mshr_read_req, replay_req) \n node _s0_req_T_3 = mux(prefetch_fire, prefetch_req, _s0_req_T_2) \n node _s0_req_T_4 = mux(prober_fire, prober_req, _s0_req_T_3) \n node _s0_req_T_5 = mux(wb_fire, wb_req, _s0_req_T_4) \n node s0_req = mux(_s0_req_T, _s0_req_WIRE, _s0_req_T_5) \n node _s0_type_T = and(io.lsu.req.ready, io.lsu.req.valid) \n node _s0_type_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid) \n node _s0_type_T_2 = mux(_s0_type_T_1, UInt<3>(0h3), UInt<3>(0h0)) \n node _s0_type_T_3 = mux(prefetch_fire, UInt<3>(0h5), _s0_type_T_2) \n node _s0_type_T_4 = mux(prober_fire, UInt<3>(0h1), _s0_type_T_3) \n node _s0_type_T_5 = mux(wb_fire, UInt<3>(0h2), _s0_type_T_4) \n node s0_type = mux(_s0_type_T, UInt<3>(0h4), _s0_type_T_5) \n node _s0_send_resp_or_nack_T = and(io.lsu.req.ready, io.lsu.req.valid) \n node _s0_send_resp_or_nack_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid) \n node _s0_send_resp_or_nack_T_2 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<1>(0h0)) \n node _s0_send_resp_or_nack_T_3 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<5>(0h10)) \n node _s0_send_resp_or_nack_T_4 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h6)) \n node _s0_send_resp_or_nack_T_5 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h7)) \n node _s0_send_resp_or_nack_T_6 = or(_s0_send_resp_or_nack_T_2, _s0_send_resp_or_nack_T_3) \n node _s0_send_resp_or_nack_T_7 = or(_s0_send_resp_or_nack_T_6, _s0_send_resp_or_nack_T_4) \n node _s0_send_resp_or_nack_T_8 = or(_s0_send_resp_or_nack_T_7, _s0_send_resp_or_nack_T_5) \n node _s0_send_resp_or_nack_T_9 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h4)) \n node _s0_send_resp_or_nack_T_10 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h9)) \n node _s0_send_resp_or_nack_T_11 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0ha)) \n node _s0_send_resp_or_nack_T_12 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hb)) \n node _s0_send_resp_or_nack_T_13 = or(_s0_send_resp_or_nack_T_9, _s0_send_resp_or_nack_T_10) \n node _s0_send_resp_or_nack_T_14 = or(_s0_send_resp_or_nack_T_13, _s0_send_resp_or_nack_T_11) \n node _s0_send_resp_or_nack_T_15 = or(_s0_send_resp_or_nack_T_14, _s0_send_resp_or_nack_T_12) \n node _s0_send_resp_or_nack_T_16 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h8)) \n node _s0_send_resp_or_nack_T_17 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hc)) \n node _s0_send_resp_or_nack_T_18 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hd)) \n node _s0_send_resp_or_nack_T_19 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0he)) \n node _s0_send_resp_or_nack_T_20 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hf)) \n node _s0_send_resp_or_nack_T_21 = or(_s0_send_resp_or_nack_T_16, _s0_send_resp_or_nack_T_17) \n node _s0_send_resp_or_nack_T_22 = or(_s0_send_resp_or_nack_T_21, _s0_send_resp_or_nack_T_18) \n node _s0_send_resp_or_nack_T_23 = or(_s0_send_resp_or_nack_T_22, _s0_send_resp_or_nack_T_19) \n node _s0_send_resp_or_nack_T_24 = or(_s0_send_resp_or_nack_T_23, _s0_send_resp_or_nack_T_20) \n node _s0_send_resp_or_nack_T_25 = or(_s0_send_resp_or_nack_T_15, _s0_send_resp_or_nack_T_24) \n node _s0_send_resp_or_nack_T_26 = or(_s0_send_resp_or_nack_T_8, _s0_send_resp_or_nack_T_25) \n node _s0_send_resp_or_nack_T_27 = and(_s0_send_resp_or_nack_T_1, _s0_send_resp_or_nack_T_26) \n node _s0_send_resp_or_nack_T_28 = mux(_s0_send_resp_or_nack_T_27, UInt<1>(0h1), UInt<1>(0h0)) \n node _s0_send_resp_or_nack_T_29 = bits(_s0_send_resp_or_nack_T_28, 0, 0) \n wire _s0_send_resp_or_nack_WIRE : UInt<1>[1] \n connect _s0_send_resp_or_nack_WIRE[0], _s0_send_resp_or_nack_T_29 \n node s0_send_resp_or_nack = mux(_s0_send_resp_or_nack_T, s0_valid, _s0_send_resp_or_nack_WIRE) \n reg s1_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1], clock \n connect s1_req, s0_req \n node _s1_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask) \n node _s1_req_0_uop_br_mask_T_1 = and(s0_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T) \n connect s1_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T_1 \n wire s2_store_failed : UInt<1> \n node _s1_valid_T = and(io.lsu.brupdate.b1.mispredict_mask, s0_req[0].uop.br_mask) \n node _s1_valid_T_1 = neq(_s1_valid_T, UInt<1>(0h0)) \n node _s1_valid_T_2 = eq(_s1_valid_T_1, UInt<1>(0h0)) \n node _s1_valid_T_3 = and(s0_valid[0], _s1_valid_T_2) \n node _s1_valid_T_4 = and(io.lsu.exception, s0_req[0].uop.uses_ldq) \n node _s1_valid_T_5 = eq(_s1_valid_T_4, UInt<1>(0h0)) \n node _s1_valid_T_6 = and(_s1_valid_T_3, _s1_valid_T_5) \n node _s1_valid_T_7 = and(io.lsu.req.ready, io.lsu.req.valid) \n node _s1_valid_T_8 = and(s2_store_failed, _s1_valid_T_7) \n node _s1_valid_T_9 = and(_s1_valid_T_8, s0_req[0].uop.uses_stq) \n node _s1_valid_T_10 = eq(_s1_valid_T_9, UInt<1>(0h0)) \n node _s1_valid_T_11 = and(_s1_valid_T_6, _s1_valid_T_10) \n regreset s1_valid_REG : UInt<1>, clock, reset, UInt<1>(0h0) \n connect s1_valid_REG, _s1_valid_T_11 \n wire s1_valid : UInt<1>[1] \n connect s1_valid[0], s1_valid_REG \n node _T_7 = and(io.lsu.req.ready, io.lsu.req.valid) \n reg REG : UInt<1>, clock \n connect REG, _T_7 \n node _T_8 = eq(REG, UInt<1>(0h0)) \n node _T_9 = and(io.lsu.s1_kill[0], _T_8) \n reg REG_1 : UInt<1>, clock \n connect REG_1, io.lsu.req.bits[0].valid \n node _T_10 = eq(REG_1, UInt<1>(0h0)) \n node _T_11 = and(_T_9, _T_10) \n node _T_12 = eq(_T_11, UInt<1>(0h0)) \n node _T_13 = asUInt(reset) \n node _T_14 = eq(_T_13, UInt<1>(0h0)) \n when _T_14 : \n node _T_15 = eq(_T_12, UInt<1>(0h0)) \n when _T_15 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at dcache.scala:611 assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))\\n\") : printf_1 \n assert(clock, _T_12, UInt<1>(0h1), \"\") : assert_1 \n node _s1_nack_T = bits(s1_req[0].addr, 9, 6) \n node _s1_nack_T_1 = eq(_s1_nack_T, prober.io.meta_write.bits.idx) \n node _s1_nack_T_2 = eq(prober.io.req.ready, UInt<1>(0h0)) \n node s1_nack_0 = and(_s1_nack_T_1, _s1_nack_T_2) \n reg s1_send_resp_or_nack : UInt<1>[1], clock \n connect s1_send_resp_or_nack, s0_send_resp_or_nack \n reg s1_type : UInt, clock \n connect s1_type, s0_type \n reg s1_mshr_meta_read_way_en : UInt, clock \n connect s1_mshr_meta_read_way_en, mshrs.io.meta_read.bits.way_en \n reg s1_replay_way_en : UInt, clock \n connect s1_replay_way_en, mshrs.io.replay.bits.way_en \n reg s1_wb_way_en : UInt, clock \n connect s1_wb_way_en, wb.io.data_req.bits.way_en \n node _s1_tag_eq_way_T = shr(s1_req[0].addr, 10) \n node _s1_tag_eq_way_T_1 = eq(meta_0.io.resp[0].tag, _s1_tag_eq_way_T) \n node _s1_tag_eq_way_T_2 = shr(s1_req[0].addr, 10) \n node _s1_tag_eq_way_T_3 = eq(meta_0.io.resp[1].tag, _s1_tag_eq_way_T_2) \n wire _s1_tag_eq_way_WIRE : UInt<1>[2] \n connect _s1_tag_eq_way_WIRE[0], _s1_tag_eq_way_T_1 \n connect _s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_T_3 \n node _s1_tag_eq_way_T_4 = cat(_s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_WIRE[0]) \n wire s1_tag_eq_way : UInt<2>[1] \n connect s1_tag_eq_way[0], _s1_tag_eq_way_T_4 \n node _s1_tag_match_way_T = eq(s1_type, UInt<3>(0h0)) \n node _s1_tag_match_way_T_1 = eq(s1_type, UInt<3>(0h2)) \n node _s1_tag_match_way_T_2 = eq(s1_type, UInt<3>(0h3)) \n node _s1_tag_match_way_T_3 = bits(s1_tag_eq_way[0], 0, 0) \n node _s1_tag_match_way_T_4 = gt(meta_0.io.resp[0].coh.state, UInt<2>(0h0)) \n node _s1_tag_match_way_T_5 = and(_s1_tag_match_way_T_3, _s1_tag_match_way_T_4) \n node _s1_tag_match_way_T_6 = bits(s1_tag_eq_way[0], 1, 1) \n node _s1_tag_match_way_T_7 = gt(meta_0.io.resp[1].coh.state, UInt<2>(0h0)) \n node _s1_tag_match_way_T_8 = and(_s1_tag_match_way_T_6, _s1_tag_match_way_T_7) \n wire _s1_tag_match_way_WIRE : UInt<1>[2] \n connect _s1_tag_match_way_WIRE[0], _s1_tag_match_way_T_5 \n connect _s1_tag_match_way_WIRE[1], _s1_tag_match_way_T_8 \n node _s1_tag_match_way_T_9 = cat(_s1_tag_match_way_WIRE[1], _s1_tag_match_way_WIRE[0]) \n node _s1_tag_match_way_T_10 = mux(_s1_tag_match_way_T_2, s1_mshr_meta_read_way_en, _s1_tag_match_way_T_9) \n node _s1_tag_match_way_T_11 = mux(_s1_tag_match_way_T_1, s1_wb_way_en, _s1_tag_match_way_T_10) \n node _s1_tag_match_way_T_12 = mux(_s1_tag_match_way_T, s1_replay_way_en, _s1_tag_match_way_T_11) \n wire s1_tag_match_way : UInt[1] \n connect s1_tag_match_way[0], _s1_tag_match_way_T_12 \n node _s1_wb_idx_matches_T = bits(s1_req[0].addr, 9, 6) \n node _s1_wb_idx_matches_T_1 = eq(_s1_wb_idx_matches_T, wb.io.idx.bits) \n node _s1_wb_idx_matches_T_2 = and(_s1_wb_idx_matches_T_1, wb.io.idx.valid) \n wire s1_wb_idx_matches : UInt<1>[1] \n connect s1_wb_idx_matches[0], _s1_wb_idx_matches_T_2 \n reg s2_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1], clock \n connect s2_req, s1_req \n reg s2_type : UInt, clock \n connect s2_type, s1_type \n node _s2_valid_T = eq(io.lsu.s1_kill[0], UInt<1>(0h0)) \n node _s2_valid_T_1 = and(s1_valid[0], _s2_valid_T) \n node _s2_valid_T_2 = and(io.lsu.brupdate.b1.mispredict_mask, s1_req[0].uop.br_mask) \n node _s2_valid_T_3 = neq(_s2_valid_T_2, UInt<1>(0h0)) \n node _s2_valid_T_4 = eq(_s2_valid_T_3, UInt<1>(0h0)) \n node _s2_valid_T_5 = and(_s2_valid_T_1, _s2_valid_T_4) \n node _s2_valid_T_6 = and(io.lsu.exception, s1_req[0].uop.uses_ldq) \n node _s2_valid_T_7 = eq(_s2_valid_T_6, UInt<1>(0h0)) \n node _s2_valid_T_8 = and(_s2_valid_T_5, _s2_valid_T_7) \n node _s2_valid_T_9 = eq(s1_type, UInt<3>(0h4)) \n node _s2_valid_T_10 = and(s2_store_failed, _s2_valid_T_9) \n node _s2_valid_T_11 = and(_s2_valid_T_10, s1_req[0].uop.uses_stq) \n node _s2_valid_T_12 = eq(_s2_valid_T_11, UInt<1>(0h0)) \n node _s2_valid_T_13 = and(_s2_valid_T_8, _s2_valid_T_12) \n reg s2_valid_REG : UInt<1>, clock \n connect s2_valid_REG, _s2_valid_T_13 \n wire s2_valid : UInt<1>[1] \n connect s2_valid[0], s2_valid_REG \n node _s2_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask) \n node _s2_req_0_uop_br_mask_T_1 = and(s1_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T) \n connect s2_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T_1 \n reg s2_tag_match_way : UInt[1], clock \n connect s2_tag_match_way, s1_tag_match_way \n node s2_tag_match_0 = orr(s2_tag_match_way[0]) \n reg s2_hit_state_REG : { state : UInt<2>}, clock \n connect s2_hit_state_REG, meta_0.io.resp[0].coh \n reg s2_hit_state_REG_1 : { state : UInt<2>}, clock \n connect s2_hit_state_REG_1, meta_0.io.resp[1].coh \n wire _s2_hit_state_WIRE : { state : UInt<2>}[2] \n connect _s2_hit_state_WIRE[0], s2_hit_state_REG \n connect _s2_hit_state_WIRE[1], s2_hit_state_REG_1 \n node _s2_hit_state_T = bits(s2_tag_match_way[0], 0, 0) \n node _s2_hit_state_T_1 = bits(s2_tag_match_way[0], 1, 1) \n wire _s2_hit_state_WIRE_1 : { state : UInt<2>} \n node _s2_hit_state_T_2 = mux(_s2_hit_state_T, _s2_hit_state_WIRE[0].state, UInt<1>(0h0)) \n node _s2_hit_state_T_3 = mux(_s2_hit_state_T_1, _s2_hit_state_WIRE[1].state, UInt<1>(0h0)) \n node _s2_hit_state_T_4 = or(_s2_hit_state_T_2, _s2_hit_state_T_3) \n wire _s2_hit_state_WIRE_2 : UInt<2> \n connect _s2_hit_state_WIRE_2, _s2_hit_state_T_4 \n connect _s2_hit_state_WIRE_1.state, _s2_hit_state_WIRE_2 \n wire s2_hit_state : { state : UInt<2>}[1] \n connect s2_hit_state[0], _s2_hit_state_WIRE_1 \n node _s2_has_permission_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1)) \n node _s2_has_permission_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11)) \n node _s2_has_permission_r_c_cat_T_2 = or(_s2_has_permission_r_c_cat_T, _s2_has_permission_r_c_cat_T_1) \n node _s2_has_permission_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _s2_has_permission_r_c_cat_T_4 = or(_s2_has_permission_r_c_cat_T_2, _s2_has_permission_r_c_cat_T_3) \n node _s2_has_permission_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _s2_has_permission_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _s2_has_permission_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _s2_has_permission_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _s2_has_permission_r_c_cat_T_9 = or(_s2_has_permission_r_c_cat_T_5, _s2_has_permission_r_c_cat_T_6) \n node _s2_has_permission_r_c_cat_T_10 = or(_s2_has_permission_r_c_cat_T_9, _s2_has_permission_r_c_cat_T_7) \n node _s2_has_permission_r_c_cat_T_11 = or(_s2_has_permission_r_c_cat_T_10, _s2_has_permission_r_c_cat_T_8) \n node _s2_has_permission_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _s2_has_permission_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _s2_has_permission_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _s2_has_permission_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _s2_has_permission_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _s2_has_permission_r_c_cat_T_17 = or(_s2_has_permission_r_c_cat_T_12, _s2_has_permission_r_c_cat_T_13) \n node _s2_has_permission_r_c_cat_T_18 = or(_s2_has_permission_r_c_cat_T_17, _s2_has_permission_r_c_cat_T_14) \n node _s2_has_permission_r_c_cat_T_19 = or(_s2_has_permission_r_c_cat_T_18, _s2_has_permission_r_c_cat_T_15) \n node _s2_has_permission_r_c_cat_T_20 = or(_s2_has_permission_r_c_cat_T_19, _s2_has_permission_r_c_cat_T_16) \n node _s2_has_permission_r_c_cat_T_21 = or(_s2_has_permission_r_c_cat_T_11, _s2_has_permission_r_c_cat_T_20) \n node _s2_has_permission_r_c_cat_T_22 = or(_s2_has_permission_r_c_cat_T_4, _s2_has_permission_r_c_cat_T_21) \n node _s2_has_permission_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1)) \n node _s2_has_permission_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11)) \n node _s2_has_permission_r_c_cat_T_25 = or(_s2_has_permission_r_c_cat_T_23, _s2_has_permission_r_c_cat_T_24) \n node _s2_has_permission_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _s2_has_permission_r_c_cat_T_27 = or(_s2_has_permission_r_c_cat_T_25, _s2_has_permission_r_c_cat_T_26) \n node _s2_has_permission_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _s2_has_permission_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _s2_has_permission_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _s2_has_permission_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _s2_has_permission_r_c_cat_T_32 = or(_s2_has_permission_r_c_cat_T_28, _s2_has_permission_r_c_cat_T_29) \n node _s2_has_permission_r_c_cat_T_33 = or(_s2_has_permission_r_c_cat_T_32, _s2_has_permission_r_c_cat_T_30) \n node _s2_has_permission_r_c_cat_T_34 = or(_s2_has_permission_r_c_cat_T_33, _s2_has_permission_r_c_cat_T_31) \n node _s2_has_permission_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _s2_has_permission_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _s2_has_permission_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _s2_has_permission_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _s2_has_permission_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _s2_has_permission_r_c_cat_T_40 = or(_s2_has_permission_r_c_cat_T_35, _s2_has_permission_r_c_cat_T_36) \n node _s2_has_permission_r_c_cat_T_41 = or(_s2_has_permission_r_c_cat_T_40, _s2_has_permission_r_c_cat_T_37) \n node _s2_has_permission_r_c_cat_T_42 = or(_s2_has_permission_r_c_cat_T_41, _s2_has_permission_r_c_cat_T_38) \n node _s2_has_permission_r_c_cat_T_43 = or(_s2_has_permission_r_c_cat_T_42, _s2_has_permission_r_c_cat_T_39) \n node _s2_has_permission_r_c_cat_T_44 = or(_s2_has_permission_r_c_cat_T_34, _s2_has_permission_r_c_cat_T_43) \n node _s2_has_permission_r_c_cat_T_45 = or(_s2_has_permission_r_c_cat_T_27, _s2_has_permission_r_c_cat_T_44) \n node _s2_has_permission_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3)) \n node _s2_has_permission_r_c_cat_T_47 = or(_s2_has_permission_r_c_cat_T_45, _s2_has_permission_r_c_cat_T_46) \n node _s2_has_permission_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6)) \n node _s2_has_permission_r_c_cat_T_49 = or(_s2_has_permission_r_c_cat_T_47, _s2_has_permission_r_c_cat_T_48) \n node s2_has_permission_r_c = cat(_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49) \n node _s2_has_permission_r_T = cat(s2_has_permission_r_c, s2_hit_state[0].state) \n node _s2_has_permission_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_has_permission_r_T_2 = cat(_s2_has_permission_r_T_1, UInt<2>(0h3)) \n node _s2_has_permission_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_has_permission_r_T_4 = cat(_s2_has_permission_r_T_3, UInt<2>(0h2)) \n node _s2_has_permission_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_has_permission_r_T_6 = cat(_s2_has_permission_r_T_5, UInt<2>(0h1)) \n node _s2_has_permission_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_has_permission_r_T_8 = cat(_s2_has_permission_r_T_7, UInt<2>(0h3)) \n node _s2_has_permission_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_has_permission_r_T_10 = cat(_s2_has_permission_r_T_9, UInt<2>(0h2)) \n node _s2_has_permission_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_has_permission_r_T_12 = cat(_s2_has_permission_r_T_11, UInt<2>(0h3)) \n node _s2_has_permission_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_has_permission_r_T_14 = cat(_s2_has_permission_r_T_13, UInt<2>(0h2)) \n node _s2_has_permission_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_has_permission_r_T_16 = cat(_s2_has_permission_r_T_15, UInt<2>(0h0)) \n node _s2_has_permission_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_has_permission_r_T_18 = cat(_s2_has_permission_r_T_17, UInt<2>(0h1)) \n node _s2_has_permission_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_has_permission_r_T_20 = cat(_s2_has_permission_r_T_19, UInt<2>(0h0)) \n node _s2_has_permission_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_has_permission_r_T_22 = cat(_s2_has_permission_r_T_21, UInt<2>(0h1)) \n node _s2_has_permission_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_has_permission_r_T_24 = cat(_s2_has_permission_r_T_23, UInt<2>(0h0)) \n node _s2_has_permission_r_T_25 = eq(_s2_has_permission_r_T_24, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_26 = mux(_s2_has_permission_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_has_permission_r_T_27 = mux(_s2_has_permission_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) \n node _s2_has_permission_r_T_28 = eq(_s2_has_permission_r_T_22, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_29 = mux(_s2_has_permission_r_T_28, UInt<1>(0h0), _s2_has_permission_r_T_26) \n node _s2_has_permission_r_T_30 = mux(_s2_has_permission_r_T_28, UInt<2>(0h2), _s2_has_permission_r_T_27) \n node _s2_has_permission_r_T_31 = eq(_s2_has_permission_r_T_20, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_32 = mux(_s2_has_permission_r_T_31, UInt<1>(0h0), _s2_has_permission_r_T_29) \n node _s2_has_permission_r_T_33 = mux(_s2_has_permission_r_T_31, UInt<2>(0h1), _s2_has_permission_r_T_30) \n node _s2_has_permission_r_T_34 = eq(_s2_has_permission_r_T_18, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_35 = mux(_s2_has_permission_r_T_34, UInt<1>(0h0), _s2_has_permission_r_T_32) \n node _s2_has_permission_r_T_36 = mux(_s2_has_permission_r_T_34, UInt<2>(0h2), _s2_has_permission_r_T_33) \n node _s2_has_permission_r_T_37 = eq(_s2_has_permission_r_T_16, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_38 = mux(_s2_has_permission_r_T_37, UInt<1>(0h0), _s2_has_permission_r_T_35) \n node _s2_has_permission_r_T_39 = mux(_s2_has_permission_r_T_37, UInt<2>(0h0), _s2_has_permission_r_T_36) \n node _s2_has_permission_r_T_40 = eq(_s2_has_permission_r_T_14, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_41 = mux(_s2_has_permission_r_T_40, UInt<1>(0h1), _s2_has_permission_r_T_38) \n node _s2_has_permission_r_T_42 = mux(_s2_has_permission_r_T_40, UInt<2>(0h3), _s2_has_permission_r_T_39) \n node _s2_has_permission_r_T_43 = eq(_s2_has_permission_r_T_12, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_44 = mux(_s2_has_permission_r_T_43, UInt<1>(0h1), _s2_has_permission_r_T_41) \n node _s2_has_permission_r_T_45 = mux(_s2_has_permission_r_T_43, UInt<2>(0h3), _s2_has_permission_r_T_42) \n node _s2_has_permission_r_T_46 = eq(_s2_has_permission_r_T_10, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_47 = mux(_s2_has_permission_r_T_46, UInt<1>(0h1), _s2_has_permission_r_T_44) \n node _s2_has_permission_r_T_48 = mux(_s2_has_permission_r_T_46, UInt<2>(0h2), _s2_has_permission_r_T_45) \n node _s2_has_permission_r_T_49 = eq(_s2_has_permission_r_T_8, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_50 = mux(_s2_has_permission_r_T_49, UInt<1>(0h1), _s2_has_permission_r_T_47) \n node _s2_has_permission_r_T_51 = mux(_s2_has_permission_r_T_49, UInt<2>(0h3), _s2_has_permission_r_T_48) \n node _s2_has_permission_r_T_52 = eq(_s2_has_permission_r_T_6, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_53 = mux(_s2_has_permission_r_T_52, UInt<1>(0h1), _s2_has_permission_r_T_50) \n node _s2_has_permission_r_T_54 = mux(_s2_has_permission_r_T_52, UInt<2>(0h1), _s2_has_permission_r_T_51) \n node _s2_has_permission_r_T_55 = eq(_s2_has_permission_r_T_4, _s2_has_permission_r_T) \n node _s2_has_permission_r_T_56 = mux(_s2_has_permission_r_T_55, UInt<1>(0h1), _s2_has_permission_r_T_53) \n node _s2_has_permission_r_T_57 = mux(_s2_has_permission_r_T_55, UInt<2>(0h2), _s2_has_permission_r_T_54) \n node _s2_has_permission_r_T_58 = eq(_s2_has_permission_r_T_2, _s2_has_permission_r_T) \n node s2_has_permission_r_1 = mux(_s2_has_permission_r_T_58, UInt<1>(0h1), _s2_has_permission_r_T_56) \n node s2_has_permission_r_2 = mux(_s2_has_permission_r_T_58, UInt<2>(0h3), _s2_has_permission_r_T_57) \n wire s2_has_permission_meta : { state : UInt<2>} \n connect s2_has_permission_meta.state, s2_has_permission_r_2 \n wire s2_has_permission : UInt<1>[1] \n connect s2_has_permission[0], s2_has_permission_r_1 \n node _s2_new_hit_state_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1)) \n node _s2_new_hit_state_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11)) \n node _s2_new_hit_state_r_c_cat_T_2 = or(_s2_new_hit_state_r_c_cat_T, _s2_new_hit_state_r_c_cat_T_1) \n node _s2_new_hit_state_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _s2_new_hit_state_r_c_cat_T_4 = or(_s2_new_hit_state_r_c_cat_T_2, _s2_new_hit_state_r_c_cat_T_3) \n node _s2_new_hit_state_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _s2_new_hit_state_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _s2_new_hit_state_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _s2_new_hit_state_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _s2_new_hit_state_r_c_cat_T_9 = or(_s2_new_hit_state_r_c_cat_T_5, _s2_new_hit_state_r_c_cat_T_6) \n node _s2_new_hit_state_r_c_cat_T_10 = or(_s2_new_hit_state_r_c_cat_T_9, _s2_new_hit_state_r_c_cat_T_7) \n node _s2_new_hit_state_r_c_cat_T_11 = or(_s2_new_hit_state_r_c_cat_T_10, _s2_new_hit_state_r_c_cat_T_8) \n node _s2_new_hit_state_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _s2_new_hit_state_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _s2_new_hit_state_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _s2_new_hit_state_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _s2_new_hit_state_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _s2_new_hit_state_r_c_cat_T_17 = or(_s2_new_hit_state_r_c_cat_T_12, _s2_new_hit_state_r_c_cat_T_13) \n node _s2_new_hit_state_r_c_cat_T_18 = or(_s2_new_hit_state_r_c_cat_T_17, _s2_new_hit_state_r_c_cat_T_14) \n node _s2_new_hit_state_r_c_cat_T_19 = or(_s2_new_hit_state_r_c_cat_T_18, _s2_new_hit_state_r_c_cat_T_15) \n node _s2_new_hit_state_r_c_cat_T_20 = or(_s2_new_hit_state_r_c_cat_T_19, _s2_new_hit_state_r_c_cat_T_16) \n node _s2_new_hit_state_r_c_cat_T_21 = or(_s2_new_hit_state_r_c_cat_T_11, _s2_new_hit_state_r_c_cat_T_20) \n node _s2_new_hit_state_r_c_cat_T_22 = or(_s2_new_hit_state_r_c_cat_T_4, _s2_new_hit_state_r_c_cat_T_21) \n node _s2_new_hit_state_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1)) \n node _s2_new_hit_state_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11)) \n node _s2_new_hit_state_r_c_cat_T_25 = or(_s2_new_hit_state_r_c_cat_T_23, _s2_new_hit_state_r_c_cat_T_24) \n node _s2_new_hit_state_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _s2_new_hit_state_r_c_cat_T_27 = or(_s2_new_hit_state_r_c_cat_T_25, _s2_new_hit_state_r_c_cat_T_26) \n node _s2_new_hit_state_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _s2_new_hit_state_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _s2_new_hit_state_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _s2_new_hit_state_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _s2_new_hit_state_r_c_cat_T_32 = or(_s2_new_hit_state_r_c_cat_T_28, _s2_new_hit_state_r_c_cat_T_29) \n node _s2_new_hit_state_r_c_cat_T_33 = or(_s2_new_hit_state_r_c_cat_T_32, _s2_new_hit_state_r_c_cat_T_30) \n node _s2_new_hit_state_r_c_cat_T_34 = or(_s2_new_hit_state_r_c_cat_T_33, _s2_new_hit_state_r_c_cat_T_31) \n node _s2_new_hit_state_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _s2_new_hit_state_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _s2_new_hit_state_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _s2_new_hit_state_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _s2_new_hit_state_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _s2_new_hit_state_r_c_cat_T_40 = or(_s2_new_hit_state_r_c_cat_T_35, _s2_new_hit_state_r_c_cat_T_36) \n node _s2_new_hit_state_r_c_cat_T_41 = or(_s2_new_hit_state_r_c_cat_T_40, _s2_new_hit_state_r_c_cat_T_37) \n node _s2_new_hit_state_r_c_cat_T_42 = or(_s2_new_hit_state_r_c_cat_T_41, _s2_new_hit_state_r_c_cat_T_38) \n node _s2_new_hit_state_r_c_cat_T_43 = or(_s2_new_hit_state_r_c_cat_T_42, _s2_new_hit_state_r_c_cat_T_39) \n node _s2_new_hit_state_r_c_cat_T_44 = or(_s2_new_hit_state_r_c_cat_T_34, _s2_new_hit_state_r_c_cat_T_43) \n node _s2_new_hit_state_r_c_cat_T_45 = or(_s2_new_hit_state_r_c_cat_T_27, _s2_new_hit_state_r_c_cat_T_44) \n node _s2_new_hit_state_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3)) \n node _s2_new_hit_state_r_c_cat_T_47 = or(_s2_new_hit_state_r_c_cat_T_45, _s2_new_hit_state_r_c_cat_T_46) \n node _s2_new_hit_state_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6)) \n node _s2_new_hit_state_r_c_cat_T_49 = or(_s2_new_hit_state_r_c_cat_T_47, _s2_new_hit_state_r_c_cat_T_48) \n node s2_new_hit_state_r_c = cat(_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49) \n node _s2_new_hit_state_r_T = cat(s2_new_hit_state_r_c, s2_hit_state[0].state) \n node _s2_new_hit_state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_new_hit_state_r_T_2 = cat(_s2_new_hit_state_r_T_1, UInt<2>(0h3)) \n node _s2_new_hit_state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_new_hit_state_r_T_4 = cat(_s2_new_hit_state_r_T_3, UInt<2>(0h2)) \n node _s2_new_hit_state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_new_hit_state_r_T_6 = cat(_s2_new_hit_state_r_T_5, UInt<2>(0h1)) \n node _s2_new_hit_state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_8 = cat(_s2_new_hit_state_r_T_7, UInt<2>(0h3)) \n node _s2_new_hit_state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_10 = cat(_s2_new_hit_state_r_T_9, UInt<2>(0h2)) \n node _s2_new_hit_state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_12 = cat(_s2_new_hit_state_r_T_11, UInt<2>(0h3)) \n node _s2_new_hit_state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_14 = cat(_s2_new_hit_state_r_T_13, UInt<2>(0h2)) \n node _s2_new_hit_state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_new_hit_state_r_T_16 = cat(_s2_new_hit_state_r_T_15, UInt<2>(0h0)) \n node _s2_new_hit_state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_18 = cat(_s2_new_hit_state_r_T_17, UInt<2>(0h1)) \n node _s2_new_hit_state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_20 = cat(_s2_new_hit_state_r_T_19, UInt<2>(0h0)) \n node _s2_new_hit_state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_22 = cat(_s2_new_hit_state_r_T_21, UInt<2>(0h1)) \n node _s2_new_hit_state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) \n node _s2_new_hit_state_r_T_24 = cat(_s2_new_hit_state_r_T_23, UInt<2>(0h0)) \n node _s2_new_hit_state_r_T_25 = eq(_s2_new_hit_state_r_T_24, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_26 = mux(_s2_new_hit_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) \n node _s2_new_hit_state_r_T_27 = mux(_s2_new_hit_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) \n node _s2_new_hit_state_r_T_28 = eq(_s2_new_hit_state_r_T_22, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_29 = mux(_s2_new_hit_state_r_T_28, UInt<1>(0h0), _s2_new_hit_state_r_T_26) \n node _s2_new_hit_state_r_T_30 = mux(_s2_new_hit_state_r_T_28, UInt<2>(0h2), _s2_new_hit_state_r_T_27) \n node _s2_new_hit_state_r_T_31 = eq(_s2_new_hit_state_r_T_20, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_32 = mux(_s2_new_hit_state_r_T_31, UInt<1>(0h0), _s2_new_hit_state_r_T_29) \n node _s2_new_hit_state_r_T_33 = mux(_s2_new_hit_state_r_T_31, UInt<2>(0h1), _s2_new_hit_state_r_T_30) \n node _s2_new_hit_state_r_T_34 = eq(_s2_new_hit_state_r_T_18, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_35 = mux(_s2_new_hit_state_r_T_34, UInt<1>(0h0), _s2_new_hit_state_r_T_32) \n node _s2_new_hit_state_r_T_36 = mux(_s2_new_hit_state_r_T_34, UInt<2>(0h2), _s2_new_hit_state_r_T_33) \n node _s2_new_hit_state_r_T_37 = eq(_s2_new_hit_state_r_T_16, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_38 = mux(_s2_new_hit_state_r_T_37, UInt<1>(0h0), _s2_new_hit_state_r_T_35) \n node _s2_new_hit_state_r_T_39 = mux(_s2_new_hit_state_r_T_37, UInt<2>(0h0), _s2_new_hit_state_r_T_36) \n node _s2_new_hit_state_r_T_40 = eq(_s2_new_hit_state_r_T_14, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_41 = mux(_s2_new_hit_state_r_T_40, UInt<1>(0h1), _s2_new_hit_state_r_T_38) \n node _s2_new_hit_state_r_T_42 = mux(_s2_new_hit_state_r_T_40, UInt<2>(0h3), _s2_new_hit_state_r_T_39) \n node _s2_new_hit_state_r_T_43 = eq(_s2_new_hit_state_r_T_12, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_44 = mux(_s2_new_hit_state_r_T_43, UInt<1>(0h1), _s2_new_hit_state_r_T_41) \n node _s2_new_hit_state_r_T_45 = mux(_s2_new_hit_state_r_T_43, UInt<2>(0h3), _s2_new_hit_state_r_T_42) \n node _s2_new_hit_state_r_T_46 = eq(_s2_new_hit_state_r_T_10, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_47 = mux(_s2_new_hit_state_r_T_46, UInt<1>(0h1), _s2_new_hit_state_r_T_44) \n node _s2_new_hit_state_r_T_48 = mux(_s2_new_hit_state_r_T_46, UInt<2>(0h2), _s2_new_hit_state_r_T_45) \n node _s2_new_hit_state_r_T_49 = eq(_s2_new_hit_state_r_T_8, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_50 = mux(_s2_new_hit_state_r_T_49, UInt<1>(0h1), _s2_new_hit_state_r_T_47) \n node _s2_new_hit_state_r_T_51 = mux(_s2_new_hit_state_r_T_49, UInt<2>(0h3), _s2_new_hit_state_r_T_48) \n node _s2_new_hit_state_r_T_52 = eq(_s2_new_hit_state_r_T_6, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_53 = mux(_s2_new_hit_state_r_T_52, UInt<1>(0h1), _s2_new_hit_state_r_T_50) \n node _s2_new_hit_state_r_T_54 = mux(_s2_new_hit_state_r_T_52, UInt<2>(0h1), _s2_new_hit_state_r_T_51) \n node _s2_new_hit_state_r_T_55 = eq(_s2_new_hit_state_r_T_4, _s2_new_hit_state_r_T) \n node _s2_new_hit_state_r_T_56 = mux(_s2_new_hit_state_r_T_55, UInt<1>(0h1), _s2_new_hit_state_r_T_53) \n node _s2_new_hit_state_r_T_57 = mux(_s2_new_hit_state_r_T_55, UInt<2>(0h2), _s2_new_hit_state_r_T_54) \n node _s2_new_hit_state_r_T_58 = eq(_s2_new_hit_state_r_T_2, _s2_new_hit_state_r_T) \n node s2_new_hit_state_r_1 = mux(_s2_new_hit_state_r_T_58, UInt<1>(0h1), _s2_new_hit_state_r_T_56) \n node s2_new_hit_state_r_2 = mux(_s2_new_hit_state_r_T_58, UInt<2>(0h3), _s2_new_hit_state_r_T_57) \n wire s2_new_hit_state_meta : { state : UInt<2>} \n connect s2_new_hit_state_meta.state, s2_new_hit_state_r_2 \n wire s2_new_hit_state : { state : UInt<2>}[1] \n connect s2_new_hit_state[0], s2_new_hit_state_meta \n node _s2_hit_T = and(s2_tag_match_0, s2_has_permission[0]) \n node _s2_hit_T_1 = eq(s2_hit_state[0].state, s2_new_hit_state[0].state) \n node _s2_hit_T_2 = and(_s2_hit_T, _s2_hit_T_1) \n node _s2_hit_T_3 = eq(mshrs.io.block_hit[0], UInt<1>(0h0)) \n node _s2_hit_T_4 = and(_s2_hit_T_2, _s2_hit_T_3) \n node _s2_hit_T_5 = eq(s2_type, UInt<3>(0h0)) \n node _s2_hit_T_6 = eq(s2_type, UInt<3>(0h2)) \n node _s2_hit_T_7 = or(_s2_hit_T_5, _s2_hit_T_6) \n node _s2_hit_T_8 = or(_s2_hit_T_4, _s2_hit_T_7) \n wire s2_hit : UInt<1>[1] \n connect s2_hit[0], _s2_hit_T_8 \n wire s2_nack : UInt<1>[1] \n node _T_16 = eq(s2_type, UInt<3>(0h0)) \n node _T_17 = eq(s2_hit[0], UInt<1>(0h0)) \n node _T_18 = and(_T_16, _T_17) \n node _T_19 = eq(_T_18, UInt<1>(0h0)) \n node _T_20 = asUInt(reset) \n node _T_21 = eq(_T_20, UInt<1>(0h0)) \n when _T_21 : \n node _T_22 = eq(_T_19, UInt<1>(0h0)) \n when _T_22 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Replays should always hit\\n at dcache.scala:651 assert(!(s2_type === t_replay && !s2_hit(0)), \\\"Replays should always hit\\\")\\n\") : printf_2 \n assert(clock, _T_19, UInt<1>(0h1), \"\") : assert_2 \n node _T_23 = eq(s2_type, UInt<3>(0h2)) \n node _T_24 = eq(s2_hit[0], UInt<1>(0h0)) \n node _T_25 = and(_T_23, _T_24) \n node _T_26 = eq(_T_25, UInt<1>(0h0)) \n node _T_27 = asUInt(reset) \n node _T_28 = eq(_T_27, UInt<1>(0h0)) \n when _T_28 : \n node _T_29 = eq(_T_26, UInt<1>(0h0)) \n when _T_29 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Writeback should always see data hit\\n at dcache.scala:652 assert(!(s2_type === t_wb && !s2_hit(0)), \\\"Writeback should always see data hit\\\")\\n\") : printf_3 \n assert(clock, _T_26, UInt<1>(0h1), \"\") : assert_3 \n reg s2_wb_idx_matches : UInt<1>[1], clock \n connect s2_wb_idx_matches, s1_wb_idx_matches \n regreset debug_sc_fail_addr : UInt, clock, reset, UInt<1>(0h0) \n regreset debug_sc_fail_cnt : UInt<8>, clock, reset, UInt<8>(0h0) \n regreset lrsc_count : UInt<7>, clock, reset, UInt<7>(0h0) \n node lrsc_valid = gt(lrsc_count, UInt<2>(0h3)) \n reg lrsc_addr : UInt, clock \n node _s2_lr_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6)) \n reg s2_lr_REG : UInt<1>, clock \n connect s2_lr_REG, s1_nack_0 \n node _s2_lr_T_1 = eq(s2_lr_REG, UInt<1>(0h0)) \n node _s2_lr_T_2 = eq(s2_type, UInt<3>(0h0)) \n node _s2_lr_T_3 = or(_s2_lr_T_1, _s2_lr_T_2) \n node s2_lr = and(_s2_lr_T, _s2_lr_T_3) \n node _s2_sc_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n reg s2_sc_REG : UInt<1>, clock \n connect s2_sc_REG, s1_nack_0 \n node _s2_sc_T_1 = eq(s2_sc_REG, UInt<1>(0h0)) \n node _s2_sc_T_2 = eq(s2_type, UInt<3>(0h0)) \n node _s2_sc_T_3 = or(_s2_sc_T_1, _s2_sc_T_2) \n node s2_sc = and(_s2_sc_T, _s2_sc_T_3) \n node _s2_lrsc_addr_match_T = shr(s2_req[0].addr, 6) \n node _s2_lrsc_addr_match_T_1 = eq(lrsc_addr, _s2_lrsc_addr_match_T) \n node _s2_lrsc_addr_match_T_2 = and(lrsc_valid, _s2_lrsc_addr_match_T_1) \n wire s2_lrsc_addr_match : UInt<1>[1] \n connect s2_lrsc_addr_match[0], _s2_lrsc_addr_match_T_2 \n node _s2_sc_fail_T = eq(s2_lrsc_addr_match[0], UInt<1>(0h0)) \n node s2_sc_fail = and(s2_sc, _s2_sc_fail_T) \n node _T_30 = gt(lrsc_count, UInt<1>(0h0)) \n when _T_30 : \n node _lrsc_count_T = sub(lrsc_count, UInt<1>(0h1)) \n node _lrsc_count_T_1 = tail(_lrsc_count_T, 1) \n connect lrsc_count, _lrsc_count_T_1 \n node _T_31 = eq(s2_type, UInt<3>(0h4)) \n node _T_32 = and(_T_31, s2_hit[0]) \n node _T_33 = eq(s2_nack[0], UInt<1>(0h0)) \n node _T_34 = and(_T_32, _T_33) \n node _T_35 = eq(s2_type, UInt<3>(0h0)) \n node _T_36 = neq(s2_req[0].uop.mem_cmd, UInt<3>(0h5)) \n node _T_37 = and(_T_35, _T_36) \n node _T_38 = or(_T_34, _T_37) \n node _T_39 = and(s2_valid[0], _T_38) \n when _T_39 : \n when s2_lr : \n connect lrsc_count, UInt<7>(0h4f) \n node _lrsc_addr_T = shr(s2_req[0].addr, 6) \n connect lrsc_addr, _lrsc_addr_T \n node _T_40 = gt(lrsc_count, UInt<1>(0h0)) \n when _T_40 : \n connect lrsc_count, UInt<1>(0h0) \n node _T_41 = eq(s2_type, UInt<3>(0h4)) \n node _T_42 = and(s2_valid[0], _T_41) \n node _T_43 = eq(s2_hit[0], UInt<1>(0h0)) \n node _T_44 = and(_T_42, _T_43) \n node _T_45 = and(s2_has_permission[0], s2_tag_match_0) \n node _T_46 = eq(_T_45, UInt<1>(0h0)) \n node _T_47 = and(_T_44, _T_46) \n node _T_48 = and(_T_47, s2_lrsc_addr_match[0]) \n node _T_49 = eq(s2_nack[0], UInt<1>(0h0)) \n node _T_50 = and(_T_48, _T_49) \n when _T_50 : \n connect lrsc_count, UInt<1>(0h0) \n when s2_valid[0] : \n node _T_51 = eq(s2_req[0].addr, debug_sc_fail_addr) \n when _T_51 : \n when s2_sc_fail : \n node _debug_sc_fail_cnt_T = add(debug_sc_fail_cnt, UInt<1>(0h1)) \n node _debug_sc_fail_cnt_T_1 = tail(_debug_sc_fail_cnt_T, 1) \n connect debug_sc_fail_cnt, _debug_sc_fail_cnt_T_1 \n else :\n\n when s2_sc : \n connect debug_sc_fail_cnt, UInt<1>(0h0) \n else :\n\n when s2_sc_fail : \n connect debug_sc_fail_addr, s2_req[0].addr \n connect debug_sc_fail_cnt, UInt<1>(0h1) \n node _T_52 = lt(debug_sc_fail_cnt, UInt<7>(0h64)) \n node _T_53 = asUInt(reset) \n node _T_54 = eq(_T_53, UInt<1>(0h0)) \n when _T_54 : \n node _T_55 = eq(_T_52, UInt<1>(0h0)) \n when _T_55 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: L1DCache failed too many SCs in a row\\n at dcache.scala:703 assert(debug_sc_fail_cnt < 100.U, \\\"L1DCache failed too many SCs in a row\\\")\\n\") : printf_4 \n assert(clock, _T_52, UInt<1>(0h1), \"\") : assert_4 \n wire s2_data : UInt<64>[2][1] \n connect s2_data[0][0], data.io.resp[0][0] \n connect s2_data[0][1], data.io.resp[0][1] \n node _s2_data_muxed_T = bits(s2_tag_match_way[0], 0, 0) \n node _s2_data_muxed_T_1 = bits(s2_tag_match_way[0], 1, 1) \n node _s2_data_muxed_T_2 = mux(_s2_data_muxed_T, s2_data[0][0], UInt<1>(0h0)) \n node _s2_data_muxed_T_3 = mux(_s2_data_muxed_T_1, s2_data[0][1], UInt<1>(0h0)) \n node _s2_data_muxed_T_4 = or(_s2_data_muxed_T_2, _s2_data_muxed_T_3) \n wire _s2_data_muxed_WIRE : UInt<64> \n connect _s2_data_muxed_WIRE, _s2_data_muxed_T_4 \n wire s2_data_muxed : UInt<64>[1] \n connect s2_data_muxed[0], _s2_data_muxed_WIRE \n wire s2_word_idx : UInt<1>[1] \n connect s2_word_idx[0], UInt<1>(0h0) \n wire replace : UInt<1> \n connect replace, UInt<1>(0h0) \n inst lfsr_prng of MaxPeriodFibonacciLFSR_2 \n connect lfsr_prng.clock, clock\n\n connect lfsr_prng.reset, reset\n\n connect lfsr_prng.io.seed.valid, UInt<1>(0h0) \n invalidate lfsr_prng.io.seed.bits[0] \n invalidate lfsr_prng.io.seed.bits[1] \n invalidate lfsr_prng.io.seed.bits[2] \n invalidate lfsr_prng.io.seed.bits[3] \n invalidate lfsr_prng.io.seed.bits[4] \n invalidate lfsr_prng.io.seed.bits[5] \n invalidate lfsr_prng.io.seed.bits[6] \n invalidate lfsr_prng.io.seed.bits[7] \n invalidate lfsr_prng.io.seed.bits[8] \n invalidate lfsr_prng.io.seed.bits[9] \n invalidate lfsr_prng.io.seed.bits[10] \n invalidate lfsr_prng.io.seed.bits[11] \n invalidate lfsr_prng.io.seed.bits[12] \n invalidate lfsr_prng.io.seed.bits[13] \n invalidate lfsr_prng.io.seed.bits[14] \n invalidate lfsr_prng.io.seed.bits[15] \n connect lfsr_prng.io.increment, replace \n node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0]) \n node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2]) \n node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo) \n node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4]) \n node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6]) \n node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo) \n node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo) \n node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8]) \n node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10]) \n node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo) \n node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12]) \n node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14]) \n node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo) \n node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo) \n node lfsr = cat(lfsr_hi, lfsr_lo) \n node _s1_replaced_way_en_T = bits(lfsr, 0, 0) \n node s1_replaced_way_en = dshl(UInt<1>(0h1), _s1_replaced_way_en_T) \n node _s2_replaced_way_en_T = bits(lfsr, 0, 0) \n reg s2_replaced_way_en_REG : UInt, clock \n connect s2_replaced_way_en_REG, _s2_replaced_way_en_T \n node s2_replaced_way_en = dshl(UInt<1>(0h1), s2_replaced_way_en_REG) \n reg s2_repl_meta_REG : { coh : { state : UInt<2>}, tag : UInt<22>}, clock \n connect s2_repl_meta_REG, meta_0.io.resp[0] \n reg s2_repl_meta_REG_1 : { coh : { state : UInt<2>}, tag : UInt<22>}, clock \n connect s2_repl_meta_REG_1, meta_0.io.resp[1] \n wire _s2_repl_meta_WIRE : { coh : { state : UInt<2>}, tag : UInt<22>}[2] \n connect _s2_repl_meta_WIRE[0], s2_repl_meta_REG \n connect _s2_repl_meta_WIRE[1], s2_repl_meta_REG_1 \n node _s2_repl_meta_T = bits(s2_replaced_way_en, 0, 0) \n node _s2_repl_meta_T_1 = bits(s2_replaced_way_en, 1, 1) \n wire _s2_repl_meta_WIRE_1 : { coh : { state : UInt<2>}, tag : UInt<22>} \n node _s2_repl_meta_T_2 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].tag, UInt<1>(0h0)) \n node _s2_repl_meta_T_3 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].tag, UInt<1>(0h0)) \n node _s2_repl_meta_T_4 = or(_s2_repl_meta_T_2, _s2_repl_meta_T_3) \n wire _s2_repl_meta_WIRE_2 : UInt<22> \n connect _s2_repl_meta_WIRE_2, _s2_repl_meta_T_4 \n connect _s2_repl_meta_WIRE_1.tag, _s2_repl_meta_WIRE_2 \n wire _s2_repl_meta_WIRE_3 : { state : UInt<2>} \n node _s2_repl_meta_T_5 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].coh.state, UInt<1>(0h0)) \n node _s2_repl_meta_T_6 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].coh.state, UInt<1>(0h0)) \n node _s2_repl_meta_T_7 = or(_s2_repl_meta_T_5, _s2_repl_meta_T_6) \n wire _s2_repl_meta_WIRE_4 : UInt<2> \n connect _s2_repl_meta_WIRE_4, _s2_repl_meta_T_7 \n connect _s2_repl_meta_WIRE_3.state, _s2_repl_meta_WIRE_4 \n connect _s2_repl_meta_WIRE_1.coh, _s2_repl_meta_WIRE_3 \n wire s2_repl_meta : { coh : { state : UInt<2>}, tag : UInt<22>}[1] \n connect s2_repl_meta[0], _s2_repl_meta_WIRE_1 \n wire _s2_nack_hit_WIRE : UInt<1>[1] \n connect _s2_nack_hit_WIRE[0], s1_nack_0 \n reg s2_nack_hit : UInt<1>[1], clock \n connect s2_nack_hit, _s2_nack_hit_WIRE \n node _s2_nack_victim_T = and(s2_valid[0], s2_hit[0]) \n node _s2_nack_victim_T_1 = and(_s2_nack_victim_T, mshrs.io.secondary_miss[0]) \n wire s2_nack_victim : UInt<1>[1] \n connect s2_nack_victim[0], _s2_nack_victim_T_1 \n node _s2_nack_miss_T = eq(s2_hit[0], UInt<1>(0h0)) \n node _s2_nack_miss_T_1 = and(s2_valid[0], _s2_nack_miss_T) \n node _s2_nack_miss_T_2 = eq(mshrs.io.req[0].ready, UInt<1>(0h0)) \n node _s2_nack_miss_T_3 = and(_s2_nack_miss_T_1, _s2_nack_miss_T_2) \n wire s2_nack_miss : UInt<1>[1] \n connect s2_nack_miss[0], _s2_nack_miss_T_3 \n wire s2_nack_data : UInt<1>[1] \n connect s2_nack_data[0], data.io.nacks[0] \n node _s2_nack_wb_T = eq(s2_hit[0], UInt<1>(0h0)) \n node _s2_nack_wb_T_1 = and(s2_valid[0], _s2_nack_wb_T) \n node _s2_nack_wb_T_2 = and(_s2_nack_wb_T_1, s2_wb_idx_matches[0]) \n wire s2_nack_wb : UInt<1>[1] \n connect s2_nack_wb[0], _s2_nack_wb_T_2 \n node _T_56 = or(s2_nack_miss[0], s2_nack_hit[0]) \n node _T_57 = or(_T_56, s2_nack_victim[0]) \n node _T_58 = or(_T_57, s2_nack_data[0]) \n node _T_59 = or(_T_58, s2_nack_wb[0]) \n node _T_60 = neq(s2_type, UInt<3>(0h0)) \n node _T_61 = and(_T_59, _T_60) \n wire _WIRE_2 : UInt<1>[1] \n connect _WIRE_2[0], _T_61 \n connect s2_nack, _WIRE_2 \n reg s2_send_resp_REG : UInt<1>, clock \n connect s2_send_resp_REG, s1_send_resp_or_nack[0] \n node _s2_send_resp_T = eq(s2_nack[0], UInt<1>(0h0)) \n node _s2_send_resp_T_1 = and(s2_send_resp_REG, _s2_send_resp_T) \n node _s2_send_resp_T_2 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid) \n node _s2_send_resp_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1)) \n node _s2_send_resp_T_4 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11)) \n node _s2_send_resp_T_5 = or(_s2_send_resp_T_3, _s2_send_resp_T_4) \n node _s2_send_resp_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _s2_send_resp_T_7 = or(_s2_send_resp_T_5, _s2_send_resp_T_6) \n node _s2_send_resp_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _s2_send_resp_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _s2_send_resp_T_10 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _s2_send_resp_T_11 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _s2_send_resp_T_12 = or(_s2_send_resp_T_8, _s2_send_resp_T_9) \n node _s2_send_resp_T_13 = or(_s2_send_resp_T_12, _s2_send_resp_T_10) \n node _s2_send_resp_T_14 = or(_s2_send_resp_T_13, _s2_send_resp_T_11) \n node _s2_send_resp_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _s2_send_resp_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _s2_send_resp_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _s2_send_resp_T_18 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _s2_send_resp_T_19 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _s2_send_resp_T_20 = or(_s2_send_resp_T_15, _s2_send_resp_T_16) \n node _s2_send_resp_T_21 = or(_s2_send_resp_T_20, _s2_send_resp_T_17) \n node _s2_send_resp_T_22 = or(_s2_send_resp_T_21, _s2_send_resp_T_18) \n node _s2_send_resp_T_23 = or(_s2_send_resp_T_22, _s2_send_resp_T_19) \n node _s2_send_resp_T_24 = or(_s2_send_resp_T_14, _s2_send_resp_T_23) \n node _s2_send_resp_T_25 = or(_s2_send_resp_T_7, _s2_send_resp_T_24) \n node _s2_send_resp_T_26 = and(_s2_send_resp_T_2, _s2_send_resp_T_25) \n node _s2_send_resp_T_27 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0)) \n node _s2_send_resp_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10)) \n node _s2_send_resp_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6)) \n node _s2_send_resp_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _s2_send_resp_T_31 = or(_s2_send_resp_T_27, _s2_send_resp_T_28) \n node _s2_send_resp_T_32 = or(_s2_send_resp_T_31, _s2_send_resp_T_29) \n node _s2_send_resp_T_33 = or(_s2_send_resp_T_32, _s2_send_resp_T_30) \n node _s2_send_resp_T_34 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _s2_send_resp_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _s2_send_resp_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _s2_send_resp_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _s2_send_resp_T_38 = or(_s2_send_resp_T_34, _s2_send_resp_T_35) \n node _s2_send_resp_T_39 = or(_s2_send_resp_T_38, _s2_send_resp_T_36) \n node _s2_send_resp_T_40 = or(_s2_send_resp_T_39, _s2_send_resp_T_37) \n node _s2_send_resp_T_41 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _s2_send_resp_T_42 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _s2_send_resp_T_43 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _s2_send_resp_T_44 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _s2_send_resp_T_45 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _s2_send_resp_T_46 = or(_s2_send_resp_T_41, _s2_send_resp_T_42) \n node _s2_send_resp_T_47 = or(_s2_send_resp_T_46, _s2_send_resp_T_43) \n node _s2_send_resp_T_48 = or(_s2_send_resp_T_47, _s2_send_resp_T_44) \n node _s2_send_resp_T_49 = or(_s2_send_resp_T_48, _s2_send_resp_T_45) \n node _s2_send_resp_T_50 = or(_s2_send_resp_T_40, _s2_send_resp_T_49) \n node _s2_send_resp_T_51 = or(_s2_send_resp_T_33, _s2_send_resp_T_50) \n node _s2_send_resp_T_52 = eq(_s2_send_resp_T_51, UInt<1>(0h0)) \n node _s2_send_resp_T_53 = and(_s2_send_resp_T_26, _s2_send_resp_T_52) \n node _s2_send_resp_T_54 = or(s2_hit[0], _s2_send_resp_T_53) \n node _s2_send_resp_T_55 = and(_s2_send_resp_T_1, _s2_send_resp_T_54) \n wire s2_send_resp : UInt<1>[1] \n connect s2_send_resp[0], _s2_send_resp_T_55 \n reg s2_send_nack_REG : UInt<1>, clock \n connect s2_send_nack_REG, s1_send_resp_or_nack[0] \n node _s2_send_nack_T = and(s2_send_nack_REG, s2_nack[0]) \n wire s2_send_nack : UInt<1>[1] \n connect s2_send_nack[0], _s2_send_nack_T \n node _T_62 = and(s2_send_resp[0], s2_send_nack[0]) \n node _T_63 = eq(_T_62, UInt<1>(0h0)) \n node _T_64 = asUInt(reset) \n node _T_65 = eq(_T_64, UInt<1>(0h0)) \n when _T_65 : \n node _T_66 = eq(_T_63, UInt<1>(0h0)) \n when _T_66 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at dcache.scala:737 assert(!(s2_send_resp(w) && s2_send_nack(w)))\\n\") : printf_5 \n assert(clock, _T_63, UInt<1>(0h1), \"\") : assert_5 \n node _s2_store_failed_T = and(s2_valid[0], s2_nack[0]) \n node _s2_store_failed_T_1 = and(_s2_store_failed_T, s2_send_nack[0]) \n node _s2_store_failed_T_2 = and(_s2_store_failed_T_1, s2_req[0].uop.uses_stq) \n connect s2_store_failed, _s2_store_failed_T_2 \n node _mshrs_io_req_0_valid_T = eq(s2_hit[0], UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_1 = and(s2_valid[0], _mshrs_io_req_0_valid_T) \n node _mshrs_io_req_0_valid_T_2 = eq(s2_nack_hit[0], UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_3 = and(_mshrs_io_req_0_valid_T_1, _mshrs_io_req_0_valid_T_2) \n node _mshrs_io_req_0_valid_T_4 = eq(s2_nack_victim[0], UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_5 = and(_mshrs_io_req_0_valid_T_3, _mshrs_io_req_0_valid_T_4) \n node _mshrs_io_req_0_valid_T_6 = eq(s2_nack_data[0], UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_7 = and(_mshrs_io_req_0_valid_T_5, _mshrs_io_req_0_valid_T_6) \n node _mshrs_io_req_0_valid_T_8 = eq(s2_nack_wb[0], UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_9 = and(_mshrs_io_req_0_valid_T_7, _mshrs_io_req_0_valid_T_8) \n node _mshrs_io_req_0_valid_T_10 = eq(s2_type, UInt<3>(0h4)) \n node _mshrs_io_req_0_valid_T_11 = eq(s2_type, UInt<3>(0h5)) \n node _mshrs_io_req_0_valid_T_12 = or(_mshrs_io_req_0_valid_T_10, _mshrs_io_req_0_valid_T_11) \n node _mshrs_io_req_0_valid_T_13 = and(_mshrs_io_req_0_valid_T_9, _mshrs_io_req_0_valid_T_12) \n node _mshrs_io_req_0_valid_T_14 = and(io.lsu.brupdate.b1.mispredict_mask, s2_req[0].uop.br_mask) \n node _mshrs_io_req_0_valid_T_15 = neq(_mshrs_io_req_0_valid_T_14, UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_16 = eq(_mshrs_io_req_0_valid_T_15, UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_17 = and(_mshrs_io_req_0_valid_T_13, _mshrs_io_req_0_valid_T_16) \n node _mshrs_io_req_0_valid_T_18 = and(io.lsu.exception, s2_req[0].uop.uses_ldq) \n node _mshrs_io_req_0_valid_T_19 = eq(_mshrs_io_req_0_valid_T_18, UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_20 = and(_mshrs_io_req_0_valid_T_17, _mshrs_io_req_0_valid_T_19) \n node _mshrs_io_req_0_valid_T_21 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h2)) \n node _mshrs_io_req_0_valid_T_22 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3)) \n node _mshrs_io_req_0_valid_T_23 = or(_mshrs_io_req_0_valid_T_21, _mshrs_io_req_0_valid_T_22) \n node _mshrs_io_req_0_valid_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0)) \n node _mshrs_io_req_0_valid_T_25 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10)) \n node _mshrs_io_req_0_valid_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6)) \n node _mshrs_io_req_0_valid_T_27 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _mshrs_io_req_0_valid_T_28 = or(_mshrs_io_req_0_valid_T_24, _mshrs_io_req_0_valid_T_25) \n node _mshrs_io_req_0_valid_T_29 = or(_mshrs_io_req_0_valid_T_28, _mshrs_io_req_0_valid_T_26) \n node _mshrs_io_req_0_valid_T_30 = or(_mshrs_io_req_0_valid_T_29, _mshrs_io_req_0_valid_T_27) \n node _mshrs_io_req_0_valid_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _mshrs_io_req_0_valid_T_32 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _mshrs_io_req_0_valid_T_33 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _mshrs_io_req_0_valid_T_34 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _mshrs_io_req_0_valid_T_35 = or(_mshrs_io_req_0_valid_T_31, _mshrs_io_req_0_valid_T_32) \n node _mshrs_io_req_0_valid_T_36 = or(_mshrs_io_req_0_valid_T_35, _mshrs_io_req_0_valid_T_33) \n node _mshrs_io_req_0_valid_T_37 = or(_mshrs_io_req_0_valid_T_36, _mshrs_io_req_0_valid_T_34) \n node _mshrs_io_req_0_valid_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _mshrs_io_req_0_valid_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _mshrs_io_req_0_valid_T_40 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _mshrs_io_req_0_valid_T_41 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _mshrs_io_req_0_valid_T_42 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _mshrs_io_req_0_valid_T_43 = or(_mshrs_io_req_0_valid_T_38, _mshrs_io_req_0_valid_T_39) \n node _mshrs_io_req_0_valid_T_44 = or(_mshrs_io_req_0_valid_T_43, _mshrs_io_req_0_valid_T_40) \n node _mshrs_io_req_0_valid_T_45 = or(_mshrs_io_req_0_valid_T_44, _mshrs_io_req_0_valid_T_41) \n node _mshrs_io_req_0_valid_T_46 = or(_mshrs_io_req_0_valid_T_45, _mshrs_io_req_0_valid_T_42) \n node _mshrs_io_req_0_valid_T_47 = or(_mshrs_io_req_0_valid_T_37, _mshrs_io_req_0_valid_T_46) \n node _mshrs_io_req_0_valid_T_48 = or(_mshrs_io_req_0_valid_T_30, _mshrs_io_req_0_valid_T_47) \n node _mshrs_io_req_0_valid_T_49 = or(_mshrs_io_req_0_valid_T_23, _mshrs_io_req_0_valid_T_48) \n node _mshrs_io_req_0_valid_T_50 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1)) \n node _mshrs_io_req_0_valid_T_51 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11)) \n node _mshrs_io_req_0_valid_T_52 = or(_mshrs_io_req_0_valid_T_50, _mshrs_io_req_0_valid_T_51) \n node _mshrs_io_req_0_valid_T_53 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _mshrs_io_req_0_valid_T_54 = or(_mshrs_io_req_0_valid_T_52, _mshrs_io_req_0_valid_T_53) \n node _mshrs_io_req_0_valid_T_55 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _mshrs_io_req_0_valid_T_56 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _mshrs_io_req_0_valid_T_57 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _mshrs_io_req_0_valid_T_58 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _mshrs_io_req_0_valid_T_59 = or(_mshrs_io_req_0_valid_T_55, _mshrs_io_req_0_valid_T_56) \n node _mshrs_io_req_0_valid_T_60 = or(_mshrs_io_req_0_valid_T_59, _mshrs_io_req_0_valid_T_57) \n node _mshrs_io_req_0_valid_T_61 = or(_mshrs_io_req_0_valid_T_60, _mshrs_io_req_0_valid_T_58) \n node _mshrs_io_req_0_valid_T_62 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _mshrs_io_req_0_valid_T_63 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _mshrs_io_req_0_valid_T_64 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _mshrs_io_req_0_valid_T_65 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _mshrs_io_req_0_valid_T_66 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _mshrs_io_req_0_valid_T_67 = or(_mshrs_io_req_0_valid_T_62, _mshrs_io_req_0_valid_T_63) \n node _mshrs_io_req_0_valid_T_68 = or(_mshrs_io_req_0_valid_T_67, _mshrs_io_req_0_valid_T_64) \n node _mshrs_io_req_0_valid_T_69 = or(_mshrs_io_req_0_valid_T_68, _mshrs_io_req_0_valid_T_65) \n node _mshrs_io_req_0_valid_T_70 = or(_mshrs_io_req_0_valid_T_69, _mshrs_io_req_0_valid_T_66) \n node _mshrs_io_req_0_valid_T_71 = or(_mshrs_io_req_0_valid_T_61, _mshrs_io_req_0_valid_T_70) \n node _mshrs_io_req_0_valid_T_72 = or(_mshrs_io_req_0_valid_T_54, _mshrs_io_req_0_valid_T_71) \n node _mshrs_io_req_0_valid_T_73 = or(_mshrs_io_req_0_valid_T_49, _mshrs_io_req_0_valid_T_72) \n node _mshrs_io_req_0_valid_T_74 = and(_mshrs_io_req_0_valid_T_20, _mshrs_io_req_0_valid_T_73) \n connect mshrs.io.req[0].valid, _mshrs_io_req_0_valid_T_74 \n node _T_67 = eq(s2_type, UInt<3>(0h0)) \n node _T_68 = and(mshrs.io.req[0].valid, _T_67) \n node _T_69 = eq(_T_68, UInt<1>(0h0)) \n node _T_70 = asUInt(reset) \n node _T_71 = eq(_T_70, UInt<1>(0h0)) \n when _T_71 : \n node _T_72 = eq(_T_69, UInt<1>(0h0)) \n when _T_72 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Replays should not need to go back into MSHRs\\n at dcache.scala:758 assert(!(mshrs.io.req(w).valid && s2_type === t_replay), \\\"Replays should not need to go back into MSHRs\\\")\\n\") : printf_6 \n assert(clock, _T_69, UInt<1>(0h1), \"\") : assert_6 \n invalidate mshrs.io.req[0].bits.sdq_id \n invalidate mshrs.io.req[0].bits.way_en \n invalidate mshrs.io.req[0].bits.old_meta.tag \n invalidate mshrs.io.req[0].bits.old_meta.coh.state \n invalidate mshrs.io.req[0].bits.tag_match \n invalidate mshrs.io.req[0].bits.is_hella \n invalidate mshrs.io.req[0].bits.data \n invalidate mshrs.io.req[0].bits.addr \n invalidate mshrs.io.req[0].bits.uop.debug_tsrc \n invalidate mshrs.io.req[0].bits.uop.debug_fsrc \n invalidate mshrs.io.req[0].bits.uop.bp_xcpt_if \n invalidate mshrs.io.req[0].bits.uop.bp_debug_if \n invalidate mshrs.io.req[0].bits.uop.xcpt_ma_if \n invalidate mshrs.io.req[0].bits.uop.xcpt_ae_if \n invalidate mshrs.io.req[0].bits.uop.xcpt_pf_if \n invalidate mshrs.io.req[0].bits.uop.fp_single \n invalidate mshrs.io.req[0].bits.uop.fp_val \n invalidate mshrs.io.req[0].bits.uop.frs3_en \n invalidate mshrs.io.req[0].bits.uop.lrs2_rtype \n invalidate mshrs.io.req[0].bits.uop.lrs1_rtype \n invalidate mshrs.io.req[0].bits.uop.dst_rtype \n invalidate mshrs.io.req[0].bits.uop.ldst_val \n invalidate mshrs.io.req[0].bits.uop.lrs3 \n invalidate mshrs.io.req[0].bits.uop.lrs2 \n invalidate mshrs.io.req[0].bits.uop.lrs1 \n invalidate mshrs.io.req[0].bits.uop.ldst \n invalidate mshrs.io.req[0].bits.uop.ldst_is_rs1 \n invalidate mshrs.io.req[0].bits.uop.flush_on_commit \n invalidate mshrs.io.req[0].bits.uop.is_unique \n invalidate mshrs.io.req[0].bits.uop.is_sys_pc2epc \n invalidate mshrs.io.req[0].bits.uop.uses_stq \n invalidate mshrs.io.req[0].bits.uop.uses_ldq \n invalidate mshrs.io.req[0].bits.uop.is_amo \n invalidate mshrs.io.req[0].bits.uop.is_fencei \n invalidate mshrs.io.req[0].bits.uop.is_fence \n invalidate mshrs.io.req[0].bits.uop.mem_signed \n invalidate mshrs.io.req[0].bits.uop.mem_size \n invalidate mshrs.io.req[0].bits.uop.mem_cmd \n invalidate mshrs.io.req[0].bits.uop.bypassable \n invalidate mshrs.io.req[0].bits.uop.exc_cause \n invalidate mshrs.io.req[0].bits.uop.exception \n invalidate mshrs.io.req[0].bits.uop.stale_pdst \n invalidate mshrs.io.req[0].bits.uop.ppred_busy \n invalidate mshrs.io.req[0].bits.uop.prs3_busy \n invalidate mshrs.io.req[0].bits.uop.prs2_busy \n invalidate mshrs.io.req[0].bits.uop.prs1_busy \n invalidate mshrs.io.req[0].bits.uop.ppred \n invalidate mshrs.io.req[0].bits.uop.prs3 \n invalidate mshrs.io.req[0].bits.uop.prs2 \n invalidate mshrs.io.req[0].bits.uop.prs1 \n invalidate mshrs.io.req[0].bits.uop.pdst \n invalidate mshrs.io.req[0].bits.uop.rxq_idx \n invalidate mshrs.io.req[0].bits.uop.stq_idx \n invalidate mshrs.io.req[0].bits.uop.ldq_idx \n invalidate mshrs.io.req[0].bits.uop.rob_idx \n invalidate mshrs.io.req[0].bits.uop.csr_addr \n invalidate mshrs.io.req[0].bits.uop.imm_packed \n invalidate mshrs.io.req[0].bits.uop.taken \n invalidate mshrs.io.req[0].bits.uop.pc_lob \n invalidate mshrs.io.req[0].bits.uop.edge_inst \n invalidate mshrs.io.req[0].bits.uop.ftq_idx \n invalidate mshrs.io.req[0].bits.uop.br_tag \n invalidate mshrs.io.req[0].bits.uop.br_mask \n invalidate mshrs.io.req[0].bits.uop.is_sfb \n invalidate mshrs.io.req[0].bits.uop.is_jal \n invalidate mshrs.io.req[0].bits.uop.is_jalr \n invalidate mshrs.io.req[0].bits.uop.is_br \n invalidate mshrs.io.req[0].bits.uop.iw_p2_poisoned \n invalidate mshrs.io.req[0].bits.uop.iw_p1_poisoned \n invalidate mshrs.io.req[0].bits.uop.iw_state \n invalidate mshrs.io.req[0].bits.uop.ctrl.is_std \n invalidate mshrs.io.req[0].bits.uop.ctrl.is_sta \n invalidate mshrs.io.req[0].bits.uop.ctrl.is_load \n invalidate mshrs.io.req[0].bits.uop.ctrl.csr_cmd \n invalidate mshrs.io.req[0].bits.uop.ctrl.fcn_dw \n invalidate mshrs.io.req[0].bits.uop.ctrl.op_fcn \n invalidate mshrs.io.req[0].bits.uop.ctrl.imm_sel \n invalidate mshrs.io.req[0].bits.uop.ctrl.op2_sel \n invalidate mshrs.io.req[0].bits.uop.ctrl.op1_sel \n invalidate mshrs.io.req[0].bits.uop.ctrl.br_type \n invalidate mshrs.io.req[0].bits.uop.fu_code \n invalidate mshrs.io.req[0].bits.uop.iq_type \n invalidate mshrs.io.req[0].bits.uop.debug_pc \n invalidate mshrs.io.req[0].bits.uop.is_rvc \n invalidate mshrs.io.req[0].bits.uop.debug_inst \n invalidate mshrs.io.req[0].bits.uop.inst \n invalidate mshrs.io.req[0].bits.uop.uopc \n connect mshrs.io.req[0].bits.uop.debug_tsrc, s2_req[0].uop.debug_tsrc \n connect mshrs.io.req[0].bits.uop.debug_fsrc, s2_req[0].uop.debug_fsrc \n connect mshrs.io.req[0].bits.uop.bp_xcpt_if, s2_req[0].uop.bp_xcpt_if \n connect mshrs.io.req[0].bits.uop.bp_debug_if, s2_req[0].uop.bp_debug_if \n connect mshrs.io.req[0].bits.uop.xcpt_ma_if, s2_req[0].uop.xcpt_ma_if \n connect mshrs.io.req[0].bits.uop.xcpt_ae_if, s2_req[0].uop.xcpt_ae_if \n connect mshrs.io.req[0].bits.uop.xcpt_pf_if, s2_req[0].uop.xcpt_pf_if \n connect mshrs.io.req[0].bits.uop.fp_single, s2_req[0].uop.fp_single \n connect mshrs.io.req[0].bits.uop.fp_val, s2_req[0].uop.fp_val \n connect mshrs.io.req[0].bits.uop.frs3_en, s2_req[0].uop.frs3_en \n connect mshrs.io.req[0].bits.uop.lrs2_rtype, s2_req[0].uop.lrs2_rtype \n connect mshrs.io.req[0].bits.uop.lrs1_rtype, s2_req[0].uop.lrs1_rtype \n connect mshrs.io.req[0].bits.uop.dst_rtype, s2_req[0].uop.dst_rtype \n connect mshrs.io.req[0].bits.uop.ldst_val, s2_req[0].uop.ldst_val \n connect mshrs.io.req[0].bits.uop.lrs3, s2_req[0].uop.lrs3 \n connect mshrs.io.req[0].bits.uop.lrs2, s2_req[0].uop.lrs2 \n connect mshrs.io.req[0].bits.uop.lrs1, s2_req[0].uop.lrs1 \n connect mshrs.io.req[0].bits.uop.ldst, s2_req[0].uop.ldst \n connect mshrs.io.req[0].bits.uop.ldst_is_rs1, s2_req[0].uop.ldst_is_rs1 \n connect mshrs.io.req[0].bits.uop.flush_on_commit, s2_req[0].uop.flush_on_commit \n connect mshrs.io.req[0].bits.uop.is_unique, s2_req[0].uop.is_unique \n connect mshrs.io.req[0].bits.uop.is_sys_pc2epc, s2_req[0].uop.is_sys_pc2epc \n connect mshrs.io.req[0].bits.uop.uses_stq, s2_req[0].uop.uses_stq \n connect mshrs.io.req[0].bits.uop.uses_ldq, s2_req[0].uop.uses_ldq \n connect mshrs.io.req[0].bits.uop.is_amo, s2_req[0].uop.is_amo \n connect mshrs.io.req[0].bits.uop.is_fencei, s2_req[0].uop.is_fencei \n connect mshrs.io.req[0].bits.uop.is_fence, s2_req[0].uop.is_fence \n connect mshrs.io.req[0].bits.uop.mem_signed, s2_req[0].uop.mem_signed \n connect mshrs.io.req[0].bits.uop.mem_size, s2_req[0].uop.mem_size \n connect mshrs.io.req[0].bits.uop.mem_cmd, s2_req[0].uop.mem_cmd \n connect mshrs.io.req[0].bits.uop.bypassable, s2_req[0].uop.bypassable \n connect mshrs.io.req[0].bits.uop.exc_cause, s2_req[0].uop.exc_cause \n connect mshrs.io.req[0].bits.uop.exception, s2_req[0].uop.exception \n connect mshrs.io.req[0].bits.uop.stale_pdst, s2_req[0].uop.stale_pdst \n connect mshrs.io.req[0].bits.uop.ppred_busy, s2_req[0].uop.ppred_busy \n connect mshrs.io.req[0].bits.uop.prs3_busy, s2_req[0].uop.prs3_busy \n connect mshrs.io.req[0].bits.uop.prs2_busy, s2_req[0].uop.prs2_busy \n connect mshrs.io.req[0].bits.uop.prs1_busy, s2_req[0].uop.prs1_busy \n connect mshrs.io.req[0].bits.uop.ppred, s2_req[0].uop.ppred \n connect mshrs.io.req[0].bits.uop.prs3, s2_req[0].uop.prs3 \n connect mshrs.io.req[0].bits.uop.prs2, s2_req[0].uop.prs2 \n connect mshrs.io.req[0].bits.uop.prs1, s2_req[0].uop.prs1 \n connect mshrs.io.req[0].bits.uop.pdst, s2_req[0].uop.pdst \n connect mshrs.io.req[0].bits.uop.rxq_idx, s2_req[0].uop.rxq_idx \n connect mshrs.io.req[0].bits.uop.stq_idx, s2_req[0].uop.stq_idx \n connect mshrs.io.req[0].bits.uop.ldq_idx, s2_req[0].uop.ldq_idx \n connect mshrs.io.req[0].bits.uop.rob_idx, s2_req[0].uop.rob_idx \n connect mshrs.io.req[0].bits.uop.csr_addr, s2_req[0].uop.csr_addr \n connect mshrs.io.req[0].bits.uop.imm_packed, s2_req[0].uop.imm_packed \n connect mshrs.io.req[0].bits.uop.taken, s2_req[0].uop.taken \n connect mshrs.io.req[0].bits.uop.pc_lob, s2_req[0].uop.pc_lob \n connect mshrs.io.req[0].bits.uop.edge_inst, s2_req[0].uop.edge_inst \n connect mshrs.io.req[0].bits.uop.ftq_idx, s2_req[0].uop.ftq_idx \n connect mshrs.io.req[0].bits.uop.br_tag, s2_req[0].uop.br_tag \n connect mshrs.io.req[0].bits.uop.br_mask, s2_req[0].uop.br_mask \n connect mshrs.io.req[0].bits.uop.is_sfb, s2_req[0].uop.is_sfb \n connect mshrs.io.req[0].bits.uop.is_jal, s2_req[0].uop.is_jal \n connect mshrs.io.req[0].bits.uop.is_jalr, s2_req[0].uop.is_jalr \n connect mshrs.io.req[0].bits.uop.is_br, s2_req[0].uop.is_br \n connect mshrs.io.req[0].bits.uop.iw_p2_poisoned, s2_req[0].uop.iw_p2_poisoned \n connect mshrs.io.req[0].bits.uop.iw_p1_poisoned, s2_req[0].uop.iw_p1_poisoned \n connect mshrs.io.req[0].bits.uop.iw_state, s2_req[0].uop.iw_state \n connect mshrs.io.req[0].bits.uop.ctrl.is_std, s2_req[0].uop.ctrl.is_std \n connect mshrs.io.req[0].bits.uop.ctrl.is_sta, s2_req[0].uop.ctrl.is_sta \n connect mshrs.io.req[0].bits.uop.ctrl.is_load, s2_req[0].uop.ctrl.is_load \n connect mshrs.io.req[0].bits.uop.ctrl.csr_cmd, s2_req[0].uop.ctrl.csr_cmd \n connect mshrs.io.req[0].bits.uop.ctrl.fcn_dw, s2_req[0].uop.ctrl.fcn_dw \n connect mshrs.io.req[0].bits.uop.ctrl.op_fcn, s2_req[0].uop.ctrl.op_fcn \n connect mshrs.io.req[0].bits.uop.ctrl.imm_sel, s2_req[0].uop.ctrl.imm_sel \n connect mshrs.io.req[0].bits.uop.ctrl.op2_sel, s2_req[0].uop.ctrl.op2_sel \n connect mshrs.io.req[0].bits.uop.ctrl.op1_sel, s2_req[0].uop.ctrl.op1_sel \n connect mshrs.io.req[0].bits.uop.ctrl.br_type, s2_req[0].uop.ctrl.br_type \n connect mshrs.io.req[0].bits.uop.fu_code, s2_req[0].uop.fu_code \n connect mshrs.io.req[0].bits.uop.iq_type, s2_req[0].uop.iq_type \n connect mshrs.io.req[0].bits.uop.debug_pc, s2_req[0].uop.debug_pc \n connect mshrs.io.req[0].bits.uop.is_rvc, s2_req[0].uop.is_rvc \n connect mshrs.io.req[0].bits.uop.debug_inst, s2_req[0].uop.debug_inst \n connect mshrs.io.req[0].bits.uop.inst, s2_req[0].uop.inst \n connect mshrs.io.req[0].bits.uop.uopc, s2_req[0].uop.uopc \n node _mshrs_io_req_0_bits_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask) \n node _mshrs_io_req_0_bits_uop_br_mask_T_1 = and(s2_req[0].uop.br_mask, _mshrs_io_req_0_bits_uop_br_mask_T) \n connect mshrs.io.req[0].bits.uop.br_mask, _mshrs_io_req_0_bits_uop_br_mask_T_1 \n connect mshrs.io.req[0].bits.addr, s2_req[0].addr \n connect mshrs.io.req[0].bits.tag_match, s2_tag_match_0 \n wire mshrs_io_req_0_bits_old_meta_meta : { coh : { state : UInt<2>}, tag : UInt<22>} \n connect mshrs_io_req_0_bits_old_meta_meta.tag, s2_repl_meta[0].tag \n connect mshrs_io_req_0_bits_old_meta_meta.coh, s2_hit_state[0] \n node _mshrs_io_req_0_bits_old_meta_T = mux(s2_tag_match_0, mshrs_io_req_0_bits_old_meta_meta, s2_repl_meta[0]) \n connect mshrs.io.req[0].bits.old_meta.tag, _mshrs_io_req_0_bits_old_meta_T.tag \n connect mshrs.io.req[0].bits.old_meta.coh.state, _mshrs_io_req_0_bits_old_meta_T.coh.state \n node _mshrs_io_req_0_bits_way_en_T = mux(s2_tag_match_0, s2_tag_match_way[0], s2_replaced_way_en) \n connect mshrs.io.req[0].bits.way_en, _mshrs_io_req_0_bits_way_en_T \n connect mshrs.io.req[0].bits.data, s2_req[0].data \n connect mshrs.io.req[0].bits.is_hella, s2_req[0].is_hella \n node _mshrs_io_req_is_probe_0_T = eq(s2_type, UInt<3>(0h1)) \n node _mshrs_io_req_is_probe_0_T_1 = and(_mshrs_io_req_is_probe_0_T, s2_valid[0]) \n connect mshrs.io.req_is_probe[0], _mshrs_io_req_is_probe_0_T_1 \n node _mshrs_io_meta_resp_valid_T = eq(s2_nack_hit[0], UInt<1>(0h0)) \n node _mshrs_io_meta_resp_valid_T_1 = or(_mshrs_io_meta_resp_valid_T, prober.io.mshr_wb_rdy) \n connect mshrs.io.meta_resp.valid, _mshrs_io_meta_resp_valid_T_1 \n reg mshrs_io_meta_resp_bits_REG : { coh : { state : UInt<2>}, tag : UInt<22>}[2], clock \n connect mshrs_io_meta_resp_bits_REG, meta_0.io.resp \n node _mshrs_io_meta_resp_bits_T = bits(s2_tag_match_way[0], 0, 0) \n node _mshrs_io_meta_resp_bits_T_1 = bits(s2_tag_match_way[0], 1, 1) \n wire _mshrs_io_meta_resp_bits_WIRE : { coh : { state : UInt<2>}, tag : UInt<22>} \n node _mshrs_io_meta_resp_bits_T_2 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].tag, UInt<1>(0h0)) \n node _mshrs_io_meta_resp_bits_T_3 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].tag, UInt<1>(0h0)) \n node _mshrs_io_meta_resp_bits_T_4 = or(_mshrs_io_meta_resp_bits_T_2, _mshrs_io_meta_resp_bits_T_3) \n wire _mshrs_io_meta_resp_bits_WIRE_1 : UInt<22> \n connect _mshrs_io_meta_resp_bits_WIRE_1, _mshrs_io_meta_resp_bits_T_4 \n connect _mshrs_io_meta_resp_bits_WIRE.tag, _mshrs_io_meta_resp_bits_WIRE_1 \n wire _mshrs_io_meta_resp_bits_WIRE_2 : { state : UInt<2>} \n node _mshrs_io_meta_resp_bits_T_5 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].coh.state, UInt<1>(0h0)) \n node _mshrs_io_meta_resp_bits_T_6 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].coh.state, UInt<1>(0h0)) \n node _mshrs_io_meta_resp_bits_T_7 = or(_mshrs_io_meta_resp_bits_T_5, _mshrs_io_meta_resp_bits_T_6) \n wire _mshrs_io_meta_resp_bits_WIRE_3 : UInt<2> \n connect _mshrs_io_meta_resp_bits_WIRE_3, _mshrs_io_meta_resp_bits_T_7 \n connect _mshrs_io_meta_resp_bits_WIRE_2.state, _mshrs_io_meta_resp_bits_WIRE_3 \n connect _mshrs_io_meta_resp_bits_WIRE.coh, _mshrs_io_meta_resp_bits_WIRE_2 \n connect mshrs.io.meta_resp.bits.tag, _mshrs_io_meta_resp_bits_WIRE.tag \n connect mshrs.io.meta_resp.bits.coh.state, _mshrs_io_meta_resp_bits_WIRE.coh.state \n node _T_73 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid) \n when _T_73 : \n connect replace, UInt<1>(0h1) \n connect nodeOut.a.bits, mshrs.io.mem_acquire.bits \n connect nodeOut.a.valid, mshrs.io.mem_acquire.valid \n connect mshrs.io.mem_acquire.ready, nodeOut.a.ready \n node _prober_io_req_valid_T = eq(lrsc_valid, UInt<1>(0h0)) \n node _prober_io_req_valid_T_1 = and(nodeOut.b.valid, _prober_io_req_valid_T) \n connect prober.io.req.valid, _prober_io_req_valid_T_1 \n node _nodeOut_b_ready_T = eq(lrsc_valid, UInt<1>(0h0)) \n node _nodeOut_b_ready_T_1 = and(prober.io.req.ready, _nodeOut_b_ready_T) \n connect nodeOut.b.ready, _nodeOut_b_ready_T_1 \n connect prober.io.req.bits.corrupt, nodeOut.b.bits.corrupt \n connect prober.io.req.bits.data, nodeOut.b.bits.data \n connect prober.io.req.bits.mask, nodeOut.b.bits.mask \n connect prober.io.req.bits.address, nodeOut.b.bits.address \n connect prober.io.req.bits.source, nodeOut.b.bits.source \n connect prober.io.req.bits.size, nodeOut.b.bits.size \n connect prober.io.req.bits.param, nodeOut.b.bits.param \n connect prober.io.req.bits.opcode, nodeOut.b.bits.opcode \n connect prober.io.way_en, s2_tag_match_way[0] \n connect prober.io.block_state.state, s2_hit_state[0].state \n connect metaWriteArb.io.in[1], prober.io.meta_write \n connect prober.io.mshr_rdy, mshrs.io.probe_rdy \n node _prober_io_wb_rdy_T = neq(prober.io.meta_write.bits.idx, wb.io.idx.bits) \n node _prober_io_wb_rdy_T_1 = eq(wb.io.idx.valid, UInt<1>(0h0)) \n node _prober_io_wb_rdy_T_2 = or(_prober_io_wb_rdy_T, _prober_io_wb_rdy_T_1) \n connect prober.io.wb_rdy, _prober_io_wb_rdy_T_2 \n connect mshrs.io.prober_state.bits, prober.io.state.bits \n connect mshrs.io.prober_state.valid, prober.io.state.valid \n node _T_74 = eq(nodeOut.d.bits.source, UInt<4>(0h8)) \n when _T_74 : \n connect nodeOut.d.ready, UInt<1>(0h1) \n connect mshrs.io.mem_grant.valid, UInt<1>(0h0) \n invalidate mshrs.io.mem_grant.bits.corrupt \n invalidate mshrs.io.mem_grant.bits.data \n invalidate mshrs.io.mem_grant.bits.denied \n invalidate mshrs.io.mem_grant.bits.sink \n invalidate mshrs.io.mem_grant.bits.source \n invalidate mshrs.io.mem_grant.bits.size \n invalidate mshrs.io.mem_grant.bits.param \n invalidate mshrs.io.mem_grant.bits.opcode \n else :\n\n connect mshrs.io.mem_grant, nodeOut.d \n connect dataWriteArb.io.in[1], mshrs.io.refill \n connect metaWriteArb.io.in[0], mshrs.io.meta_write \n connect nodeOut.e.bits, mshrs.io.mem_finish.bits \n connect nodeOut.e.valid, mshrs.io.mem_finish.valid \n connect mshrs.io.mem_finish.ready, nodeOut.e.ready \n inst wbArb of Arbiter2_WritebackReq_1 \n connect wbArb.clock, clock\n\n connect wbArb.reset, reset\n\n connect wbArb.io.in[0], prober.io.wb_req \n connect wbArb.io.in[1], mshrs.io.wb_req \n connect wb.io.req, wbArb.io.out \n connect wb.io.data_resp, s2_data_muxed[0] \n connect mshrs.io.wb_resp, wb.io.resp \n node _wb_io_mem_grant_T = and(nodeOut.d.ready, nodeOut.d.valid) \n node _wb_io_mem_grant_T_1 = eq(nodeOut.d.bits.source, UInt<4>(0h8)) \n node _wb_io_mem_grant_T_2 = and(_wb_io_mem_grant_T, _wb_io_mem_grant_T_1) \n connect wb.io.mem_grant, _wb_io_mem_grant_T_2 \n inst lsu_release_arb of Arbiter2_TLBundleC_a32d64s4k3z4c_1 \n connect lsu_release_arb.clock, clock\n\n connect lsu_release_arb.reset, reset\n\n connect io.lsu.release.bits, lsu_release_arb.io.out.bits \n connect io.lsu.release.valid, lsu_release_arb.io.out.valid \n connect lsu_release_arb.io.out.ready, io.lsu.release.ready \n connect lsu_release_arb.io.in[0], wb.io.lsu_release \n connect lsu_release_arb.io.in[1], prober.io.lsu_release \n node _decode_T = dshl(UInt<12>(0hfff), wb.io.release.bits.size) \n node _decode_T_1 = bits(_decode_T, 11, 0) \n node _decode_T_2 = not(_decode_T_1) \n node decode = shr(_decode_T_2, 3) \n node opdata = bits(wb.io.release.bits.opcode, 0, 0) \n node _T_75 = mux(opdata, decode, UInt<1>(0h0)) \n node _decode_T_3 = dshl(UInt<12>(0hfff), prober.io.rep.bits.size) \n node _decode_T_4 = bits(_decode_T_3, 11, 0) \n node _decode_T_5 = not(_decode_T_4) \n node decode_1 = shr(_decode_T_5, 3) \n node opdata_1 = bits(prober.io.rep.bits.opcode, 0, 0) \n node _T_76 = mux(opdata_1, decode_1, UInt<1>(0h0)) \n regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) \n node idle = eq(beatsLeft, UInt<1>(0h0)) \n node latch = and(idle, nodeOut.c.ready) \n node _readys_T = cat(prober.io.rep.valid, wb.io.release.valid) \n node _readys_T_1 = shl(_readys_T, 1) \n node _readys_T_2 = bits(_readys_T_1, 1, 0) \n node _readys_T_3 = or(_readys_T, _readys_T_2) \n node _readys_T_4 = bits(_readys_T_3, 1, 0) \n node _readys_T_5 = shl(_readys_T_4, 1) \n node _readys_T_6 = bits(_readys_T_5, 1, 0) \n node _readys_T_7 = not(_readys_T_6) \n node _readys_T_8 = bits(_readys_T_7, 0, 0) \n node _readys_T_9 = bits(_readys_T_7, 1, 1) \n wire readys : UInt<1>[2] \n connect readys[0], _readys_T_8 \n connect readys[1], _readys_T_9 \n node _winner_T = and(readys[0], wb.io.release.valid) \n node _winner_T_1 = and(readys[1], prober.io.rep.valid) \n wire winner : UInt<1>[2] \n connect winner[0], _winner_T \n connect winner[1], _winner_T_1 \n node prefixOR_1 = or(UInt<1>(0h0), winner[0]) \n node _prefixOR_T = or(prefixOR_1, winner[1]) \n node _T_77 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_78 = eq(winner[0], UInt<1>(0h0)) \n node _T_79 = or(_T_77, _T_78) \n node _T_80 = eq(prefixOR_1, UInt<1>(0h0)) \n node _T_81 = eq(winner[1], UInt<1>(0h0)) \n node _T_82 = or(_T_80, _T_81) \n node _T_83 = and(_T_79, _T_82) \n node _T_84 = asUInt(reset) \n node _T_85 = eq(_T_84, UInt<1>(0h0)) \n when _T_85 : \n node _T_86 = eq(_T_83, UInt<1>(0h0)) \n when _T_86 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\\n\") : printf_7 \n assert(clock, _T_83, UInt<1>(0h1), \"\") : assert_7 \n node _T_87 = or(wb.io.release.valid, prober.io.rep.valid) \n node _T_88 = eq(_T_87, UInt<1>(0h0)) \n node _T_89 = or(winner[0], winner[1]) \n node _T_90 = or(_T_88, _T_89) \n node _T_91 = asUInt(reset) \n node _T_92 = eq(_T_91, UInt<1>(0h0)) \n when _T_92 : \n node _T_93 = eq(_T_90, UInt<1>(0h0)) \n when _T_93 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\\n\") : printf_8 \n assert(clock, _T_90, UInt<1>(0h1), \"\") : assert_8 \n node maskedBeats_0 = mux(winner[0], _T_75, UInt<1>(0h0)) \n node maskedBeats_1 = mux(winner[1], _T_76, UInt<1>(0h0)) \n node initBeats = or(maskedBeats_0, maskedBeats_1) \n node _beatsLeft_T = and(nodeOut.c.ready, nodeOut.c.valid) \n node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) \n node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) \n node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) \n connect beatsLeft, _beatsLeft_T_3 \n wire _state_WIRE : UInt<1>[2] \n connect _state_WIRE[0], UInt<1>(0h0) \n connect _state_WIRE[1], UInt<1>(0h0) \n regreset state : UInt<1>[2], clock, reset, _state_WIRE \n node muxState = mux(idle, winner, state) \n connect state, muxState \n node allowed = mux(idle, readys, state) \n node _wb_io_release_ready_T = and(nodeOut.c.ready, allowed[0]) \n connect wb.io.release.ready, _wb_io_release_ready_T \n node _prober_io_rep_ready_T = and(nodeOut.c.ready, allowed[1]) \n connect prober.io.rep.ready, _prober_io_rep_ready_T \n node _nodeOut_c_valid_T = or(wb.io.release.valid, prober.io.rep.valid) \n node _nodeOut_c_valid_T_1 = mux(state[0], wb.io.release.valid, UInt<1>(0h0)) \n node _nodeOut_c_valid_T_2 = mux(state[1], prober.io.rep.valid, UInt<1>(0h0)) \n node _nodeOut_c_valid_T_3 = or(_nodeOut_c_valid_T_1, _nodeOut_c_valid_T_2) \n wire _nodeOut_c_valid_WIRE : UInt<1> \n connect _nodeOut_c_valid_WIRE, _nodeOut_c_valid_T_3 \n node _nodeOut_c_valid_T_4 = mux(idle, _nodeOut_c_valid_T, _nodeOut_c_valid_WIRE) \n connect nodeOut.c.valid, _nodeOut_c_valid_T_4 \n wire _nodeOut_c_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} \n node _nodeOut_c_bits_T = mux(muxState[0], wb.io.release.bits.corrupt, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_1 = mux(muxState[1], prober.io.rep.bits.corrupt, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_2 = or(_nodeOut_c_bits_T, _nodeOut_c_bits_T_1) \n wire _nodeOut_c_bits_WIRE_1 : UInt<1> \n connect _nodeOut_c_bits_WIRE_1, _nodeOut_c_bits_T_2 \n connect _nodeOut_c_bits_WIRE.corrupt, _nodeOut_c_bits_WIRE_1 \n node _nodeOut_c_bits_T_3 = mux(muxState[0], wb.io.release.bits.data, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_4 = mux(muxState[1], prober.io.rep.bits.data, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_5 = or(_nodeOut_c_bits_T_3, _nodeOut_c_bits_T_4) \n wire _nodeOut_c_bits_WIRE_2 : UInt<64> \n connect _nodeOut_c_bits_WIRE_2, _nodeOut_c_bits_T_5 \n connect _nodeOut_c_bits_WIRE.data, _nodeOut_c_bits_WIRE_2 \n wire _nodeOut_c_bits_WIRE_3 : { } \n connect _nodeOut_c_bits_WIRE.echo, _nodeOut_c_bits_WIRE_3 \n wire _nodeOut_c_bits_WIRE_4 : { } \n connect _nodeOut_c_bits_WIRE.user, _nodeOut_c_bits_WIRE_4 \n node _nodeOut_c_bits_T_6 = mux(muxState[0], wb.io.release.bits.address, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_7 = mux(muxState[1], prober.io.rep.bits.address, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_8 = or(_nodeOut_c_bits_T_6, _nodeOut_c_bits_T_7) \n wire _nodeOut_c_bits_WIRE_5 : UInt<32> \n connect _nodeOut_c_bits_WIRE_5, _nodeOut_c_bits_T_8 \n connect _nodeOut_c_bits_WIRE.address, _nodeOut_c_bits_WIRE_5 \n node _nodeOut_c_bits_T_9 = mux(muxState[0], wb.io.release.bits.source, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_10 = mux(muxState[1], prober.io.rep.bits.source, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_11 = or(_nodeOut_c_bits_T_9, _nodeOut_c_bits_T_10) \n wire _nodeOut_c_bits_WIRE_6 : UInt<4> \n connect _nodeOut_c_bits_WIRE_6, _nodeOut_c_bits_T_11 \n connect _nodeOut_c_bits_WIRE.source, _nodeOut_c_bits_WIRE_6 \n node _nodeOut_c_bits_T_12 = mux(muxState[0], wb.io.release.bits.size, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_13 = mux(muxState[1], prober.io.rep.bits.size, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_14 = or(_nodeOut_c_bits_T_12, _nodeOut_c_bits_T_13) \n wire _nodeOut_c_bits_WIRE_7 : UInt<4> \n connect _nodeOut_c_bits_WIRE_7, _nodeOut_c_bits_T_14 \n connect _nodeOut_c_bits_WIRE.size, _nodeOut_c_bits_WIRE_7 \n node _nodeOut_c_bits_T_15 = mux(muxState[0], wb.io.release.bits.param, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_16 = mux(muxState[1], prober.io.rep.bits.param, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_17 = or(_nodeOut_c_bits_T_15, _nodeOut_c_bits_T_16) \n wire _nodeOut_c_bits_WIRE_8 : UInt<3> \n connect _nodeOut_c_bits_WIRE_8, _nodeOut_c_bits_T_17 \n connect _nodeOut_c_bits_WIRE.param, _nodeOut_c_bits_WIRE_8 \n node _nodeOut_c_bits_T_18 = mux(muxState[0], wb.io.release.bits.opcode, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_19 = mux(muxState[1], prober.io.rep.bits.opcode, UInt<1>(0h0)) \n node _nodeOut_c_bits_T_20 = or(_nodeOut_c_bits_T_18, _nodeOut_c_bits_T_19) \n wire _nodeOut_c_bits_WIRE_9 : UInt<3> \n connect _nodeOut_c_bits_WIRE_9, _nodeOut_c_bits_T_20 \n connect _nodeOut_c_bits_WIRE.opcode, _nodeOut_c_bits_WIRE_9 \n connect nodeOut.c.bits.corrupt, _nodeOut_c_bits_WIRE.corrupt \n connect nodeOut.c.bits.data, _nodeOut_c_bits_WIRE.data \n connect nodeOut.c.bits.address, _nodeOut_c_bits_WIRE.address \n connect nodeOut.c.bits.source, _nodeOut_c_bits_WIRE.source \n connect nodeOut.c.bits.size, _nodeOut_c_bits_WIRE.size \n connect nodeOut.c.bits.param, _nodeOut_c_bits_WIRE.param \n connect nodeOut.c.bits.opcode, _nodeOut_c_bits_WIRE.opcode \n node _io_lsu_perf_release_T = and(nodeOut.c.ready, nodeOut.c.valid) \n node _io_lsu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.c.bits.size) \n node _io_lsu_perf_release_beats1_decode_T_1 = bits(_io_lsu_perf_release_beats1_decode_T, 11, 0) \n node _io_lsu_perf_release_beats1_decode_T_2 = not(_io_lsu_perf_release_beats1_decode_T_1) \n node io_lsu_perf_release_beats1_decode = shr(_io_lsu_perf_release_beats1_decode_T_2, 3) \n node io_lsu_perf_release_beats1_opdata = bits(nodeOut.c.bits.opcode, 0, 0) \n node io_lsu_perf_release_beats1 = mux(io_lsu_perf_release_beats1_opdata, io_lsu_perf_release_beats1_decode, UInt<1>(0h0)) \n regreset io_lsu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _io_lsu_perf_release_counter1_T = sub(io_lsu_perf_release_counter, UInt<1>(0h1)) \n node io_lsu_perf_release_counter1 = tail(_io_lsu_perf_release_counter1_T, 1) \n node io_lsu_perf_release_first = eq(io_lsu_perf_release_counter, UInt<1>(0h0)) \n node _io_lsu_perf_release_last_T = eq(io_lsu_perf_release_counter, UInt<1>(0h1)) \n node _io_lsu_perf_release_last_T_1 = eq(io_lsu_perf_release_beats1, UInt<1>(0h0)) \n node io_lsu_perf_release_last = or(_io_lsu_perf_release_last_T, _io_lsu_perf_release_last_T_1) \n node io_lsu_perf_release_done = and(io_lsu_perf_release_last, _io_lsu_perf_release_T) \n node _io_lsu_perf_release_count_T = not(io_lsu_perf_release_counter1) \n node io_lsu_perf_release_count = and(io_lsu_perf_release_beats1, _io_lsu_perf_release_count_T) \n when _io_lsu_perf_release_T : \n node _io_lsu_perf_release_counter_T = mux(io_lsu_perf_release_first, io_lsu_perf_release_beats1, io_lsu_perf_release_counter1) \n connect io_lsu_perf_release_counter, _io_lsu_perf_release_counter_T \n connect io.lsu.perf.release, io_lsu_perf_release_done \n node _io_lsu_perf_acquire_T = and(nodeOut.a.ready, nodeOut.a.valid) \n node _io_lsu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.a.bits.size) \n node _io_lsu_perf_acquire_beats1_decode_T_1 = bits(_io_lsu_perf_acquire_beats1_decode_T, 11, 0) \n node _io_lsu_perf_acquire_beats1_decode_T_2 = not(_io_lsu_perf_acquire_beats1_decode_T_1) \n node io_lsu_perf_acquire_beats1_decode = shr(_io_lsu_perf_acquire_beats1_decode_T_2, 3) \n node _io_lsu_perf_acquire_beats1_opdata_T = bits(nodeOut.a.bits.opcode, 2, 2) \n node io_lsu_perf_acquire_beats1_opdata = eq(_io_lsu_perf_acquire_beats1_opdata_T, UInt<1>(0h0)) \n node io_lsu_perf_acquire_beats1 = mux(io_lsu_perf_acquire_beats1_opdata, io_lsu_perf_acquire_beats1_decode, UInt<1>(0h0)) \n regreset io_lsu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _io_lsu_perf_acquire_counter1_T = sub(io_lsu_perf_acquire_counter, UInt<1>(0h1)) \n node io_lsu_perf_acquire_counter1 = tail(_io_lsu_perf_acquire_counter1_T, 1) \n node io_lsu_perf_acquire_first = eq(io_lsu_perf_acquire_counter, UInt<1>(0h0)) \n node _io_lsu_perf_acquire_last_T = eq(io_lsu_perf_acquire_counter, UInt<1>(0h1)) \n node _io_lsu_perf_acquire_last_T_1 = eq(io_lsu_perf_acquire_beats1, UInt<1>(0h0)) \n node io_lsu_perf_acquire_last = or(_io_lsu_perf_acquire_last_T, _io_lsu_perf_acquire_last_T_1) \n node io_lsu_perf_acquire_done = and(io_lsu_perf_acquire_last, _io_lsu_perf_acquire_T) \n node _io_lsu_perf_acquire_count_T = not(io_lsu_perf_acquire_counter1) \n node io_lsu_perf_acquire_count = and(io_lsu_perf_acquire_beats1, _io_lsu_perf_acquire_count_T) \n when _io_lsu_perf_acquire_T : \n node _io_lsu_perf_acquire_counter_T = mux(io_lsu_perf_acquire_first, io_lsu_perf_acquire_beats1, io_lsu_perf_acquire_counter1) \n connect io_lsu_perf_acquire_counter, _io_lsu_perf_acquire_counter_T \n connect io.lsu.perf.acquire, io_lsu_perf_acquire_done \n node _s2_data_word_prebypass_T = cat(s2_word_idx[0], UInt<6>(0h0)) \n node _s2_data_word_prebypass_T_1 = dshr(s2_data_muxed[0], _s2_data_word_prebypass_T) \n wire s2_data_word_prebypass : UInt<64>[1] \n connect s2_data_word_prebypass[0], _s2_data_word_prebypass_T_1 \n wire s2_data_word : UInt[1] \n node _T_94 = and(s2_sc, UInt<1>(0h1)) \n wire size : UInt<2> \n connect size, s2_req[0].uop.mem_size \n node size_dat_padded = pad(s2_data_word[0], 64) \n wire cache_resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1] \n node _cache_resp_0_valid_T = and(s2_valid[0], s2_send_resp[0]) \n connect cache_resp[0].valid, _cache_resp_0_valid_T \n connect cache_resp[0].bits.uop, s2_req[0].uop \n node _cache_resp_0_bits_data_shifted_T = bits(s2_req[0].addr, 2, 2) \n node _cache_resp_0_bits_data_shifted_T_1 = bits(s2_data_word[0], 63, 32) \n node _cache_resp_0_bits_data_shifted_T_2 = bits(s2_data_word[0], 31, 0) \n node cache_resp_0_bits_data_shifted = mux(_cache_resp_0_bits_data_shifted_T, _cache_resp_0_bits_data_shifted_T_1, _cache_resp_0_bits_data_shifted_T_2) \n node cache_resp_0_bits_data_doZero = and(UInt<1>(0h0), _T_94) \n node cache_resp_0_bits_data_zeroed = mux(cache_resp_0_bits_data_doZero, UInt<1>(0h0), cache_resp_0_bits_data_shifted) \n node _cache_resp_0_bits_data_T = eq(size, UInt<2>(0h2)) \n node _cache_resp_0_bits_data_T_1 = or(_cache_resp_0_bits_data_T, cache_resp_0_bits_data_doZero) \n node _cache_resp_0_bits_data_T_2 = bits(cache_resp_0_bits_data_zeroed, 31, 31) \n node _cache_resp_0_bits_data_T_3 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_2) \n node _cache_resp_0_bits_data_T_4 = mux(_cache_resp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) \n node _cache_resp_0_bits_data_T_5 = bits(s2_data_word[0], 63, 32) \n node _cache_resp_0_bits_data_T_6 = mux(_cache_resp_0_bits_data_T_1, _cache_resp_0_bits_data_T_4, _cache_resp_0_bits_data_T_5) \n node _cache_resp_0_bits_data_T_7 = cat(_cache_resp_0_bits_data_T_6, cache_resp_0_bits_data_zeroed) \n node _cache_resp_0_bits_data_shifted_T_3 = bits(s2_req[0].addr, 1, 1) \n node _cache_resp_0_bits_data_shifted_T_4 = bits(_cache_resp_0_bits_data_T_7, 31, 16) \n node _cache_resp_0_bits_data_shifted_T_5 = bits(_cache_resp_0_bits_data_T_7, 15, 0) \n node cache_resp_0_bits_data_shifted_1 = mux(_cache_resp_0_bits_data_shifted_T_3, _cache_resp_0_bits_data_shifted_T_4, _cache_resp_0_bits_data_shifted_T_5) \n node cache_resp_0_bits_data_doZero_1 = and(UInt<1>(0h0), _T_94) \n node cache_resp_0_bits_data_zeroed_1 = mux(cache_resp_0_bits_data_doZero_1, UInt<1>(0h0), cache_resp_0_bits_data_shifted_1) \n node _cache_resp_0_bits_data_T_8 = eq(size, UInt<1>(0h1)) \n node _cache_resp_0_bits_data_T_9 = or(_cache_resp_0_bits_data_T_8, cache_resp_0_bits_data_doZero_1) \n node _cache_resp_0_bits_data_T_10 = bits(cache_resp_0_bits_data_zeroed_1, 15, 15) \n node _cache_resp_0_bits_data_T_11 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_10) \n node _cache_resp_0_bits_data_T_12 = mux(_cache_resp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) \n node _cache_resp_0_bits_data_T_13 = bits(_cache_resp_0_bits_data_T_7, 63, 16) \n node _cache_resp_0_bits_data_T_14 = mux(_cache_resp_0_bits_data_T_9, _cache_resp_0_bits_data_T_12, _cache_resp_0_bits_data_T_13) \n node _cache_resp_0_bits_data_T_15 = cat(_cache_resp_0_bits_data_T_14, cache_resp_0_bits_data_zeroed_1) \n node _cache_resp_0_bits_data_shifted_T_6 = bits(s2_req[0].addr, 0, 0) \n node _cache_resp_0_bits_data_shifted_T_7 = bits(_cache_resp_0_bits_data_T_15, 15, 8) \n node _cache_resp_0_bits_data_shifted_T_8 = bits(_cache_resp_0_bits_data_T_15, 7, 0) \n node cache_resp_0_bits_data_shifted_2 = mux(_cache_resp_0_bits_data_shifted_T_6, _cache_resp_0_bits_data_shifted_T_7, _cache_resp_0_bits_data_shifted_T_8) \n node cache_resp_0_bits_data_doZero_2 = and(UInt<1>(0h1), _T_94) \n node cache_resp_0_bits_data_zeroed_2 = mux(cache_resp_0_bits_data_doZero_2, UInt<1>(0h0), cache_resp_0_bits_data_shifted_2) \n node _cache_resp_0_bits_data_T_16 = eq(size, UInt<1>(0h0)) \n node _cache_resp_0_bits_data_T_17 = or(_cache_resp_0_bits_data_T_16, cache_resp_0_bits_data_doZero_2) \n node _cache_resp_0_bits_data_T_18 = bits(cache_resp_0_bits_data_zeroed_2, 7, 7) \n node _cache_resp_0_bits_data_T_19 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_18) \n node _cache_resp_0_bits_data_T_20 = mux(_cache_resp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) \n node _cache_resp_0_bits_data_T_21 = bits(_cache_resp_0_bits_data_T_15, 63, 8) \n node _cache_resp_0_bits_data_T_22 = mux(_cache_resp_0_bits_data_T_17, _cache_resp_0_bits_data_T_20, _cache_resp_0_bits_data_T_21) \n node _cache_resp_0_bits_data_T_23 = cat(_cache_resp_0_bits_data_T_22, cache_resp_0_bits_data_zeroed_2) \n node _cache_resp_0_bits_data_T_24 = or(_cache_resp_0_bits_data_T_23, s2_sc_fail) \n connect cache_resp[0].bits.data, _cache_resp_0_bits_data_T_24 \n connect cache_resp[0].bits.is_hella, s2_req[0].is_hella \n wire uncache_resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}} \n connect uncache_resp.bits, mshrs.io.resp.bits \n connect uncache_resp.valid, mshrs.io.resp.valid \n node _mshrs_io_resp_ready_T = eq(cache_resp[0].valid, UInt<1>(0h0)) \n connect mshrs.io.resp.ready, _mshrs_io_resp_ready_T \n wire resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1] \n connect resp, cache_resp \n node _uncache_respond_T = eq(cache_resp[0].valid, UInt<1>(0h0)) \n node _uncache_respond_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node uncache_respond = and(_uncache_respond_T, _uncache_respond_T_1) \n when uncache_respond : \n connect resp[0], uncache_resp \n node _T_95 = or(UInt<1>(0h0), uncache_respond) \n node _io_lsu_resp_0_valid_T = and(io.lsu.exception, resp[0].bits.uop.uses_ldq) \n node _io_lsu_resp_0_valid_T_1 = eq(_io_lsu_resp_0_valid_T, UInt<1>(0h0)) \n node _io_lsu_resp_0_valid_T_2 = and(resp[0].valid, _io_lsu_resp_0_valid_T_1) \n node _io_lsu_resp_0_valid_T_3 = and(io.lsu.brupdate.b1.mispredict_mask, resp[0].bits.uop.br_mask) \n node _io_lsu_resp_0_valid_T_4 = neq(_io_lsu_resp_0_valid_T_3, UInt<1>(0h0)) \n node _io_lsu_resp_0_valid_T_5 = eq(_io_lsu_resp_0_valid_T_4, UInt<1>(0h0)) \n node _io_lsu_resp_0_valid_T_6 = and(_io_lsu_resp_0_valid_T_2, _io_lsu_resp_0_valid_T_5) \n connect io.lsu.resp[0].valid, _io_lsu_resp_0_valid_T_6 \n wire io_lsu_resp_0_bits_out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>} \n connect io_lsu_resp_0_bits_out, resp[0].bits \n node _io_lsu_resp_0_bits_out_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask) \n node _io_lsu_resp_0_bits_out_uop_br_mask_T_1 = and(resp[0].bits.uop.br_mask, _io_lsu_resp_0_bits_out_uop_br_mask_T) \n connect io_lsu_resp_0_bits_out.uop.br_mask, _io_lsu_resp_0_bits_out_uop_br_mask_T_1 \n connect io.lsu.resp[0].bits, io_lsu_resp_0_bits_out \n node _io_lsu_nack_0_valid_T = and(s2_valid[0], s2_send_nack[0]) \n node _io_lsu_nack_0_valid_T_1 = and(io.lsu.exception, s2_req[0].uop.uses_ldq) \n node _io_lsu_nack_0_valid_T_2 = eq(_io_lsu_nack_0_valid_T_1, UInt<1>(0h0)) \n node _io_lsu_nack_0_valid_T_3 = and(_io_lsu_nack_0_valid_T, _io_lsu_nack_0_valid_T_2) \n node _io_lsu_nack_0_valid_T_4 = and(io.lsu.brupdate.b1.mispredict_mask, s2_req[0].uop.br_mask) \n node _io_lsu_nack_0_valid_T_5 = neq(_io_lsu_nack_0_valid_T_4, UInt<1>(0h0)) \n node _io_lsu_nack_0_valid_T_6 = eq(_io_lsu_nack_0_valid_T_5, UInt<1>(0h0)) \n node _io_lsu_nack_0_valid_T_7 = and(_io_lsu_nack_0_valid_T_3, _io_lsu_nack_0_valid_T_6) \n connect io.lsu.nack[0].valid, _io_lsu_nack_0_valid_T_7 \n wire io_lsu_nack_0_bits_out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>} \n connect io_lsu_nack_0_bits_out, s2_req[0] \n node _io_lsu_nack_0_bits_out_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask) \n node _io_lsu_nack_0_bits_out_uop_br_mask_T_1 = and(s2_req[0].uop.br_mask, _io_lsu_nack_0_bits_out_uop_br_mask_T) \n connect io_lsu_nack_0_bits_out.uop.br_mask, _io_lsu_nack_0_bits_out_uop_br_mask_T_1 \n connect io.lsu.nack[0].bits, io_lsu_nack_0_bits_out \n node _T_96 = neq(s2_type, UInt<3>(0h4)) \n node _T_97 = and(io.lsu.nack[0].valid, _T_96) \n node _T_98 = eq(_T_97, UInt<1>(0h0)) \n node _T_99 = asUInt(reset) \n node _T_100 = eq(_T_99, UInt<1>(0h0)) \n when _T_100 : \n node _T_101 = eq(_T_98, UInt<1>(0h0)) \n when _T_101 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at dcache.scala:866 assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))\\n\") : printf_9 \n assert(clock, _T_98, UInt<1>(0h1), \"\") : assert_9 \n reg s3_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}, clock \n connect s3_req, s2_req[0] \n node _s3_valid_T = and(s2_valid[0], s2_hit[0]) \n node _s3_valid_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1)) \n node _s3_valid_T_2 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11)) \n node _s3_valid_T_3 = or(_s3_valid_T_1, _s3_valid_T_2) \n node _s3_valid_T_4 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7)) \n node _s3_valid_T_5 = or(_s3_valid_T_3, _s3_valid_T_4) \n node _s3_valid_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4)) \n node _s3_valid_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9)) \n node _s3_valid_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha)) \n node _s3_valid_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb)) \n node _s3_valid_T_10 = or(_s3_valid_T_6, _s3_valid_T_7) \n node _s3_valid_T_11 = or(_s3_valid_T_10, _s3_valid_T_8) \n node _s3_valid_T_12 = or(_s3_valid_T_11, _s3_valid_T_9) \n node _s3_valid_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8)) \n node _s3_valid_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc)) \n node _s3_valid_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd)) \n node _s3_valid_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he)) \n node _s3_valid_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf)) \n node _s3_valid_T_18 = or(_s3_valid_T_13, _s3_valid_T_14) \n node _s3_valid_T_19 = or(_s3_valid_T_18, _s3_valid_T_15) \n node _s3_valid_T_20 = or(_s3_valid_T_19, _s3_valid_T_16) \n node _s3_valid_T_21 = or(_s3_valid_T_20, _s3_valid_T_17) \n node _s3_valid_T_22 = or(_s3_valid_T_12, _s3_valid_T_21) \n node _s3_valid_T_23 = or(_s3_valid_T_5, _s3_valid_T_22) \n node _s3_valid_T_24 = and(_s3_valid_T, _s3_valid_T_23) \n node _s3_valid_T_25 = eq(s2_sc_fail, UInt<1>(0h0)) \n node _s3_valid_T_26 = and(_s3_valid_T_24, _s3_valid_T_25) \n node _s3_valid_T_27 = and(s2_send_nack[0], s2_nack[0]) \n node _s3_valid_T_28 = eq(_s3_valid_T_27, UInt<1>(0h0)) \n node _s3_valid_T_29 = and(_s3_valid_T_26, _s3_valid_T_28) \n reg s3_valid : UInt<1>, clock \n connect s3_valid, _s3_valid_T_29 \n reg s4_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}, clock \n connect s4_req, s3_req \n reg s4_valid : UInt<1>, clock \n connect s4_valid, s3_valid \n reg s5_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}, clock \n connect s5_req, s4_req \n reg s5_valid : UInt<1>, clock \n connect s5_valid, s4_valid \n node _s3_bypass_T = shr(s2_req[0].addr, 3) \n node _s3_bypass_T_1 = shr(s3_req.addr, 3) \n node _s3_bypass_T_2 = eq(_s3_bypass_T, _s3_bypass_T_1) \n node _s3_bypass_T_3 = and(s3_valid, _s3_bypass_T_2) \n wire s3_bypass : UInt<1>[1] \n connect s3_bypass[0], _s3_bypass_T_3 \n node _s4_bypass_T = shr(s2_req[0].addr, 3) \n node _s4_bypass_T_1 = shr(s4_req.addr, 3) \n node _s4_bypass_T_2 = eq(_s4_bypass_T, _s4_bypass_T_1) \n node _s4_bypass_T_3 = and(s4_valid, _s4_bypass_T_2) \n wire s4_bypass : UInt<1>[1] \n connect s4_bypass[0], _s4_bypass_T_3 \n node _s5_bypass_T = shr(s2_req[0].addr, 3) \n node _s5_bypass_T_1 = shr(s5_req.addr, 3) \n node _s5_bypass_T_2 = eq(_s5_bypass_T, _s5_bypass_T_1) \n node _s5_bypass_T_3 = and(s5_valid, _s5_bypass_T_2) \n wire s5_bypass : UInt<1>[1] \n connect s5_bypass[0], _s5_bypass_T_3 \n node _s2_data_word_0_T = mux(s5_bypass[0], s5_req.data, s2_data_word_prebypass[0]) \n node _s2_data_word_0_T_1 = mux(s4_bypass[0], s4_req.data, _s2_data_word_0_T) \n node _s2_data_word_0_T_2 = mux(s3_bypass[0], s3_req.data, _s2_data_word_0_T_1) \n connect s2_data_word[0], _s2_data_word_0_T_2 \n inst amoalu of AMOALU_1 \n connect amoalu.clock, clock\n\n connect amoalu.reset, reset\n\n wire amoalu_io_mask_size : UInt<2> \n connect amoalu_io_mask_size, s2_req[0].uop.mem_size \n node _amoalu_io_mask_upper_T = bits(s2_req[0].addr, 0, 0) \n node _amoalu_io_mask_upper_T_1 = mux(_amoalu_io_mask_upper_T, UInt<1>(0h1), UInt<1>(0h0)) \n node _amoalu_io_mask_upper_T_2 = geq(amoalu_io_mask_size, UInt<1>(0h1)) \n node _amoalu_io_mask_upper_T_3 = mux(_amoalu_io_mask_upper_T_2, UInt<1>(0h1), UInt<1>(0h0)) \n node amoalu_io_mask_upper = or(_amoalu_io_mask_upper_T_1, _amoalu_io_mask_upper_T_3) \n node _amoalu_io_mask_lower_T = bits(s2_req[0].addr, 0, 0) \n node amoalu_io_mask_lower = mux(_amoalu_io_mask_lower_T, UInt<1>(0h0), UInt<1>(0h1)) \n node _amoalu_io_mask_T = cat(amoalu_io_mask_upper, amoalu_io_mask_lower) \n node _amoalu_io_mask_upper_T_4 = bits(s2_req[0].addr, 1, 1) \n node _amoalu_io_mask_upper_T_5 = mux(_amoalu_io_mask_upper_T_4, _amoalu_io_mask_T, UInt<1>(0h0)) \n node _amoalu_io_mask_upper_T_6 = geq(amoalu_io_mask_size, UInt<2>(0h2)) \n node _amoalu_io_mask_upper_T_7 = mux(_amoalu_io_mask_upper_T_6, UInt<2>(0h3), UInt<1>(0h0)) \n node amoalu_io_mask_upper_1 = or(_amoalu_io_mask_upper_T_5, _amoalu_io_mask_upper_T_7) \n node _amoalu_io_mask_lower_T_1 = bits(s2_req[0].addr, 1, 1) \n node amoalu_io_mask_lower_1 = mux(_amoalu_io_mask_lower_T_1, UInt<1>(0h0), _amoalu_io_mask_T) \n node _amoalu_io_mask_T_1 = cat(amoalu_io_mask_upper_1, amoalu_io_mask_lower_1) \n node _amoalu_io_mask_upper_T_8 = bits(s2_req[0].addr, 2, 2) \n node _amoalu_io_mask_upper_T_9 = mux(_amoalu_io_mask_upper_T_8, _amoalu_io_mask_T_1, UInt<1>(0h0)) \n node _amoalu_io_mask_upper_T_10 = geq(amoalu_io_mask_size, UInt<2>(0h3)) \n node _amoalu_io_mask_upper_T_11 = mux(_amoalu_io_mask_upper_T_10, UInt<4>(0hf), UInt<1>(0h0)) \n node amoalu_io_mask_upper_2 = or(_amoalu_io_mask_upper_T_9, _amoalu_io_mask_upper_T_11) \n node _amoalu_io_mask_lower_T_2 = bits(s2_req[0].addr, 2, 2) \n node amoalu_io_mask_lower_2 = mux(_amoalu_io_mask_lower_T_2, UInt<1>(0h0), _amoalu_io_mask_T_1) \n node _amoalu_io_mask_T_2 = cat(amoalu_io_mask_upper_2, amoalu_io_mask_lower_2) \n connect amoalu.io.mask, _amoalu_io_mask_T_2 \n connect amoalu.io.cmd, s2_req[0].uop.mem_cmd \n connect amoalu.io.lhs, s2_data_word[0] \n connect amoalu.io.rhs, s2_req[0].data \n connect s3_req.data, amoalu.io.out \n reg s3_way : UInt, clock \n connect s3_way, s2_tag_match_way[0] \n connect dataWriteArb.io.in[0].valid, s3_valid \n connect dataWriteArb.io.in[0].bits.addr, s3_req.addr \n node _dataWriteArb_io_in_0_bits_wmask_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) \n connect dataWriteArb.io.in[0].bits.wmask, _dataWriteArb_io_in_0_bits_wmask_T \n connect dataWriteArb.io.in[0].bits.data, s3_req.data \n connect dataWriteArb.io.in[0].bits.way_en, s3_way \n node _io_lsu_ordered_T = eq(s1_valid[0], UInt<1>(0h0)) \n node _io_lsu_ordered_T_1 = and(mshrs.io.fence_rdy, _io_lsu_ordered_T) \n node _io_lsu_ordered_T_2 = eq(s2_valid[0], UInt<1>(0h0)) \n node _io_lsu_ordered_T_3 = and(_io_lsu_ordered_T_1, _io_lsu_ordered_T_2) \n connect io.lsu.ordered, _io_lsu_ordered_T_3"},"response":{"kind":"string","value":"module BoomNonBlockingDCache_1(\t// @[dcache.scala:413:7]\n input clock,\t// @[dcache.scala:413:7]\n input reset,\t// @[dcache.scala:413:7]\n input auto_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_out_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_e_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output io_lsu_req_ready,\t// @[dcache.scala:419:14]\n input io_lsu_req_valid,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_valid,\t// @[dcache.scala:419:14]\n input [6:0] io_lsu_req_bits_0_bits_uop_uopc,\t// @[dcache.scala:419:14]\n input [31:0] io_lsu_req_bits_0_bits_uop_inst,\t// @[dcache.scala:419:14]\n input [31:0] io_lsu_req_bits_0_bits_uop_debug_inst,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_rvc,\t// @[dcache.scala:419:14]\n input [33:0] io_lsu_req_bits_0_bits_uop_debug_pc,\t// @[dcache.scala:419:14]\n input [2:0] io_lsu_req_bits_0_bits_uop_iq_type,\t// @[dcache.scala:419:14]\n input [9:0] io_lsu_req_bits_0_bits_uop_fu_code,\t// @[dcache.scala:419:14]\n input [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel,\t// @[dcache.scala:419:14]\n input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel,\t// @[dcache.scala:419:14]\n input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel,\t// @[dcache.scala:419:14]\n input [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw,\t// @[dcache.scala:419:14]\n input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_ctrl_is_load,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_ctrl_is_sta,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_ctrl_is_std,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_iw_state,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_iw_p1_poisoned,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_iw_p2_poisoned,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_br,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_jalr,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_jal,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_sfb,\t// @[dcache.scala:419:14]\n input [3:0] io_lsu_req_bits_0_bits_uop_br_mask,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_br_tag,\t// @[dcache.scala:419:14]\n input [3:0] io_lsu_req_bits_0_bits_uop_ftq_idx,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_edge_inst,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_req_bits_0_bits_uop_pc_lob,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_taken,\t// @[dcache.scala:419:14]\n input [19:0] io_lsu_req_bits_0_bits_uop_imm_packed,\t// @[dcache.scala:419:14]\n input [11:0] io_lsu_req_bits_0_bits_uop_csr_addr,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_req_bits_0_bits_uop_rob_idx,\t// @[dcache.scala:419:14]\n input [3:0] io_lsu_req_bits_0_bits_uop_ldq_idx,\t// @[dcache.scala:419:14]\n input [3:0] io_lsu_req_bits_0_bits_uop_stq_idx,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx,\t// @[dcache.scala:419:14]\n input [6:0] io_lsu_req_bits_0_bits_uop_pdst,\t// @[dcache.scala:419:14]\n input [6:0] io_lsu_req_bits_0_bits_uop_prs1,\t// @[dcache.scala:419:14]\n input [6:0] io_lsu_req_bits_0_bits_uop_prs2,\t// @[dcache.scala:419:14]\n input [6:0] io_lsu_req_bits_0_bits_uop_prs3,\t// @[dcache.scala:419:14]\n input [3:0] io_lsu_req_bits_0_bits_uop_ppred,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_prs1_busy,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_prs2_busy,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_prs3_busy,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_ppred_busy,\t// @[dcache.scala:419:14]\n input [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_exception,\t// @[dcache.scala:419:14]\n input [63:0] io_lsu_req_bits_0_bits_uop_exc_cause,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_bypassable,\t// @[dcache.scala:419:14]\n input [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_mem_size,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_mem_signed,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_fence,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_fencei,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_amo,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_uses_ldq,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_uses_stq,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_sys_pc2epc,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_is_unique,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_flush_on_commit,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_ldst_is_rs1,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_req_bits_0_bits_uop_ldst,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_req_bits_0_bits_uop_lrs1,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_req_bits_0_bits_uop_lrs2,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_req_bits_0_bits_uop_lrs3,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_ldst_val,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_frs3_en,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_fp_val,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_fp_single,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_xcpt_pf_if,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_xcpt_ae_if,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_xcpt_ma_if,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_bp_debug_if,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_uop_bp_xcpt_if,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc,\t// @[dcache.scala:419:14]\n input [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc,\t// @[dcache.scala:419:14]\n input [33:0] io_lsu_req_bits_0_bits_addr,\t// @[dcache.scala:419:14]\n input [63:0] io_lsu_req_bits_0_bits_data,\t// @[dcache.scala:419:14]\n input io_lsu_req_bits_0_bits_is_hella,\t// @[dcache.scala:419:14]\n input io_lsu_s1_kill_0,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_valid,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_resp_0_bits_uop_uopc,\t// @[dcache.scala:419:14]\n output [31:0] io_lsu_resp_0_bits_uop_inst,\t// @[dcache.scala:419:14]\n output [31:0] io_lsu_resp_0_bits_uop_debug_inst,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_rvc,\t// @[dcache.scala:419:14]\n output [33:0] io_lsu_resp_0_bits_uop_debug_pc,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_resp_0_bits_uop_iq_type,\t// @[dcache.scala:419:14]\n output [9:0] io_lsu_resp_0_bits_uop_fu_code,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel,\t// @[dcache.scala:419:14]\n output [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_ctrl_fcn_dw,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_ctrl_is_load,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_ctrl_is_sta,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_ctrl_is_std,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_iw_state,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_iw_p1_poisoned,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_iw_p2_poisoned,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_br,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_jalr,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_jal,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_sfb,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_resp_0_bits_uop_br_mask,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_br_tag,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_resp_0_bits_uop_ftq_idx,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_edge_inst,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_resp_0_bits_uop_pc_lob,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_taken,\t// @[dcache.scala:419:14]\n output [19:0] io_lsu_resp_0_bits_uop_imm_packed,\t// @[dcache.scala:419:14]\n output [11:0] io_lsu_resp_0_bits_uop_csr_addr,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_resp_0_bits_uop_rob_idx,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_resp_0_bits_uop_ldq_idx,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_resp_0_bits_uop_stq_idx,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_rxq_idx,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_resp_0_bits_uop_pdst,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_resp_0_bits_uop_prs1,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_resp_0_bits_uop_prs2,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_resp_0_bits_uop_prs3,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_resp_0_bits_uop_ppred,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_prs1_busy,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_prs2_busy,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_prs3_busy,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_ppred_busy,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_resp_0_bits_uop_stale_pdst,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_exception,\t// @[dcache.scala:419:14]\n output [63:0] io_lsu_resp_0_bits_uop_exc_cause,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_bypassable,\t// @[dcache.scala:419:14]\n output [4:0] io_lsu_resp_0_bits_uop_mem_cmd,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_mem_size,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_mem_signed,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_fence,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_fencei,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_amo,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_uses_ldq,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_uses_stq,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_sys_pc2epc,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_is_unique,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_flush_on_commit,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_ldst_is_rs1,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_resp_0_bits_uop_ldst,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_resp_0_bits_uop_lrs1,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_resp_0_bits_uop_lrs2,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_resp_0_bits_uop_lrs3,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_ldst_val,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_dst_rtype,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_frs3_en,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_fp_val,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_fp_single,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_xcpt_pf_if,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_xcpt_ae_if,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_xcpt_ma_if,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_bp_debug_if,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_uop_bp_xcpt_if,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_debug_fsrc,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_resp_0_bits_uop_debug_tsrc,\t// @[dcache.scala:419:14]\n output [63:0] io_lsu_resp_0_bits_data,\t// @[dcache.scala:419:14]\n output io_lsu_resp_0_bits_is_hella,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_valid,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_nack_0_bits_uop_uopc,\t// @[dcache.scala:419:14]\n output [31:0] io_lsu_nack_0_bits_uop_inst,\t// @[dcache.scala:419:14]\n output [31:0] io_lsu_nack_0_bits_uop_debug_inst,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_rvc,\t// @[dcache.scala:419:14]\n output [33:0] io_lsu_nack_0_bits_uop_debug_pc,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_nack_0_bits_uop_iq_type,\t// @[dcache.scala:419:14]\n output [9:0] io_lsu_nack_0_bits_uop_fu_code,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel,\t// @[dcache.scala:419:14]\n output [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_ctrl_fcn_dw,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_ctrl_is_load,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_ctrl_is_sta,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_ctrl_is_std,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_iw_state,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_iw_p1_poisoned,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_iw_p2_poisoned,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_br,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_jalr,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_jal,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_sfb,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_nack_0_bits_uop_br_mask,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_br_tag,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_nack_0_bits_uop_ftq_idx,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_edge_inst,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_nack_0_bits_uop_pc_lob,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_taken,\t// @[dcache.scala:419:14]\n output [19:0] io_lsu_nack_0_bits_uop_imm_packed,\t// @[dcache.scala:419:14]\n output [11:0] io_lsu_nack_0_bits_uop_csr_addr,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_nack_0_bits_uop_rob_idx,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_nack_0_bits_uop_ldq_idx,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_nack_0_bits_uop_stq_idx,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_rxq_idx,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_nack_0_bits_uop_pdst,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_nack_0_bits_uop_prs1,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_nack_0_bits_uop_prs2,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_nack_0_bits_uop_prs3,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_nack_0_bits_uop_ppred,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_prs1_busy,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_prs2_busy,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_prs3_busy,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_ppred_busy,\t// @[dcache.scala:419:14]\n output [6:0] io_lsu_nack_0_bits_uop_stale_pdst,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_exception,\t// @[dcache.scala:419:14]\n output [63:0] io_lsu_nack_0_bits_uop_exc_cause,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_bypassable,\t// @[dcache.scala:419:14]\n output [4:0] io_lsu_nack_0_bits_uop_mem_cmd,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_mem_size,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_mem_signed,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_fence,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_fencei,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_amo,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_uses_ldq,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_uses_stq,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_sys_pc2epc,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_is_unique,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_flush_on_commit,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_ldst_is_rs1,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_nack_0_bits_uop_ldst,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_nack_0_bits_uop_lrs1,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_nack_0_bits_uop_lrs2,\t// @[dcache.scala:419:14]\n output [5:0] io_lsu_nack_0_bits_uop_lrs3,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_ldst_val,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_dst_rtype,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_frs3_en,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_fp_val,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_fp_single,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_xcpt_pf_if,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_xcpt_ae_if,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_xcpt_ma_if,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_bp_debug_if,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_uop_bp_xcpt_if,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_debug_fsrc,\t// @[dcache.scala:419:14]\n output [1:0] io_lsu_nack_0_bits_uop_debug_tsrc,\t// @[dcache.scala:419:14]\n output [33:0] io_lsu_nack_0_bits_addr,\t// @[dcache.scala:419:14]\n output [63:0] io_lsu_nack_0_bits_data,\t// @[dcache.scala:419:14]\n output io_lsu_nack_0_bits_is_hella,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_rob_pnr_idx,\t// @[dcache.scala:419:14]\n input [5:0] io_lsu_rob_head_idx,\t// @[dcache.scala:419:14]\n input io_lsu_release_ready,\t// @[dcache.scala:419:14]\n output io_lsu_release_valid,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_release_bits_opcode,\t// @[dcache.scala:419:14]\n output [2:0] io_lsu_release_bits_param,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_release_bits_size,\t// @[dcache.scala:419:14]\n output [3:0] io_lsu_release_bits_source,\t// @[dcache.scala:419:14]\n output [31:0] io_lsu_release_bits_address,\t// @[dcache.scala:419:14]\n output [63:0] io_lsu_release_bits_data,\t// @[dcache.scala:419:14]\n input io_lsu_force_order,\t// @[dcache.scala:419:14]\n output io_lsu_ordered,\t// @[dcache.scala:419:14]\n output io_lsu_perf_acquire,\t// @[dcache.scala:419:14]\n output io_lsu_perf_release\t// @[dcache.scala:419:14]\n);\n\n wire resp_0_valid;\t// @[dcache.scala:846:22]\n wire resp_0_bits_is_hella;\t// @[dcache.scala:846:22]\n wire [63:0] resp_0_bits_data;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_debug_tsrc;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_debug_fsrc;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_bp_xcpt_if;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_bp_debug_if;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_xcpt_ma_if;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_xcpt_ae_if;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_xcpt_pf_if;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_fp_single;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_fp_val;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_frs3_en;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_lrs2_rtype;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_lrs1_rtype;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_dst_rtype;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_ldst_val;\t// @[dcache.scala:846:22]\n wire [5:0] resp_0_bits_uop_lrs3;\t// @[dcache.scala:846:22]\n wire [5:0] resp_0_bits_uop_lrs2;\t// @[dcache.scala:846:22]\n wire [5:0] resp_0_bits_uop_lrs1;\t// @[dcache.scala:846:22]\n wire [5:0] resp_0_bits_uop_ldst;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_ldst_is_rs1;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_flush_on_commit;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_unique;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_sys_pc2epc;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_uses_stq;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_uses_ldq;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_amo;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_fencei;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_fence;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_mem_signed;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_mem_size;\t// @[dcache.scala:846:22]\n wire [4:0] resp_0_bits_uop_mem_cmd;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_bypassable;\t// @[dcache.scala:846:22]\n wire [63:0] resp_0_bits_uop_exc_cause;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_exception;\t// @[dcache.scala:846:22]\n wire [6:0] resp_0_bits_uop_stale_pdst;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_ppred_busy;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_prs3_busy;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_prs2_busy;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_prs1_busy;\t// @[dcache.scala:846:22]\n wire [3:0] resp_0_bits_uop_ppred;\t// @[dcache.scala:846:22]\n wire [6:0] resp_0_bits_uop_prs3;\t// @[dcache.scala:846:22]\n wire [6:0] resp_0_bits_uop_prs2;\t// @[dcache.scala:846:22]\n wire [6:0] resp_0_bits_uop_prs1;\t// @[dcache.scala:846:22]\n wire [6:0] resp_0_bits_uop_pdst;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_rxq_idx;\t// @[dcache.scala:846:22]\n wire [3:0] resp_0_bits_uop_stq_idx;\t// @[dcache.scala:846:22]\n wire [3:0] resp_0_bits_uop_ldq_idx;\t// @[dcache.scala:846:22]\n wire [5:0] resp_0_bits_uop_rob_idx;\t// @[dcache.scala:846:22]\n wire [11:0] resp_0_bits_uop_csr_addr;\t// @[dcache.scala:846:22]\n wire [19:0] resp_0_bits_uop_imm_packed;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_taken;\t// @[dcache.scala:846:22]\n wire [5:0] resp_0_bits_uop_pc_lob;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_edge_inst;\t// @[dcache.scala:846:22]\n wire [3:0] resp_0_bits_uop_ftq_idx;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_br_tag;\t// @[dcache.scala:846:22]\n wire [3:0] resp_0_bits_uop_br_mask;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_sfb;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_jal;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_jalr;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_br;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_iw_p2_poisoned;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_iw_p1_poisoned;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_iw_state;\t// @[dcache.scala:846:22]\n wire [9:0] resp_0_bits_uop_fu_code;\t// @[dcache.scala:846:22]\n wire [2:0] resp_0_bits_uop_iq_type;\t// @[dcache.scala:846:22]\n wire [33:0] resp_0_bits_uop_debug_pc;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_is_rvc;\t// @[dcache.scala:846:22]\n wire [31:0] resp_0_bits_uop_debug_inst;\t// @[dcache.scala:846:22]\n wire [31:0] resp_0_bits_uop_inst;\t// @[dcache.scala:846:22]\n wire [6:0] resp_0_bits_uop_uopc;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_ctrl_is_std;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_ctrl_is_sta;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_ctrl_is_load;\t// @[dcache.scala:846:22]\n wire [2:0] resp_0_bits_uop_ctrl_csr_cmd;\t// @[dcache.scala:846:22]\n wire resp_0_bits_uop_ctrl_fcn_dw;\t// @[dcache.scala:846:22]\n wire [4:0] resp_0_bits_uop_ctrl_op_fcn;\t// @[dcache.scala:846:22]\n wire [2:0] resp_0_bits_uop_ctrl_imm_sel;\t// @[dcache.scala:846:22]\n wire [2:0] resp_0_bits_uop_ctrl_op2_sel;\t// @[dcache.scala:846:22]\n wire [1:0] resp_0_bits_uop_ctrl_op1_sel;\t// @[dcache.scala:846:22]\n wire [3:0] resp_0_bits_uop_ctrl_br_type;\t// @[dcache.scala:846:22]\n wire [1:0] _s2_repl_meta_WIRE_1_coh_state;\t// @[Mux.scala:30:73]\n wire [21:0] _s2_repl_meta_WIRE_1_tag;\t// @[Mux.scala:30:73]\n wire [1:0] _s2_hit_state_WIRE_1_state;\t// @[Mux.scala:30:73]\n wire [63:0] _amoalu_io_out;\t// @[dcache.scala:896:24]\n wire _lsu_release_arb_io_in_0_ready;\t// @[dcache.scala:814:31]\n wire _lsu_release_arb_io_in_1_ready;\t// @[dcache.scala:814:31]\n wire _wbArb_io_in_0_ready;\t// @[dcache.scala:805:21]\n wire _wbArb_io_in_1_ready;\t// @[dcache.scala:805:21]\n wire _wbArb_io_out_valid;\t// @[dcache.scala:805:21]\n wire [21:0] _wbArb_io_out_bits_tag;\t// @[dcache.scala:805:21]\n wire [3:0] _wbArb_io_out_bits_idx;\t// @[dcache.scala:805:21]\n wire [3:0] _wbArb_io_out_bits_source;\t// @[dcache.scala:805:21]\n wire [2:0] _wbArb_io_out_bits_param;\t// @[dcache.scala:805:21]\n wire [1:0] _wbArb_io_out_bits_way_en;\t// @[dcache.scala:805:21]\n wire _wbArb_io_out_bits_voluntary;\t// @[dcache.scala:805:21]\n wire _lfsr_prng_io_out_0;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_1;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_2;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_3;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_4;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_5;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_6;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_7;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_8;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_9;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_10;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_11;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_12;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_13;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_14;\t// @[PRNG.scala:91:22]\n wire _lfsr_prng_io_out_15;\t// @[PRNG.scala:91:22]\n wire _dataReadArb_io_in_1_ready;\t// @[dcache.scala:463:27]\n wire _dataReadArb_io_in_2_ready;\t// @[dcache.scala:463:27]\n wire _dataReadArb_io_out_valid;\t// @[dcache.scala:463:27]\n wire [1:0] _dataReadArb_io_out_bits_req_0_way_en;\t// @[dcache.scala:463:27]\n wire [9:0] _dataReadArb_io_out_bits_req_0_addr;\t// @[dcache.scala:463:27]\n wire _dataReadArb_io_out_bits_valid_0;\t// @[dcache.scala:463:27]\n wire _dataWriteArb_io_in_1_ready;\t// @[dcache.scala:461:28]\n wire [1:0] _dataWriteArb_io_out_bits_way_en;\t// @[dcache.scala:461:28]\n wire [9:0] _dataWriteArb_io_out_bits_addr;\t// @[dcache.scala:461:28]\n wire [63:0] _dataWriteArb_io_out_bits_data;\t// @[dcache.scala:461:28]\n wire _metaReadArb_io_in_1_ready;\t// @[dcache.scala:445:27]\n wire _metaReadArb_io_in_2_ready;\t// @[dcache.scala:445:27]\n wire _metaReadArb_io_in_3_ready;\t// @[dcache.scala:445:27]\n wire _metaReadArb_io_in_4_ready;\t// @[dcache.scala:445:27]\n wire _metaReadArb_io_in_5_ready;\t// @[dcache.scala:445:27]\n wire _metaReadArb_io_out_valid;\t// @[dcache.scala:445:27]\n wire [3:0] _metaReadArb_io_out_bits_req_0_idx;\t// @[dcache.scala:445:27]\n wire [1:0] _metaReadArb_io_out_bits_req_0_way_en;\t// @[dcache.scala:445:27]\n wire [21:0] _metaReadArb_io_out_bits_req_0_tag;\t// @[dcache.scala:445:27]\n wire _metaWriteArb_io_in_0_ready;\t// @[dcache.scala:443:28]\n wire _metaWriteArb_io_in_1_ready;\t// @[dcache.scala:443:28]\n wire _metaWriteArb_io_out_valid;\t// @[dcache.scala:443:28]\n wire [3:0] _metaWriteArb_io_out_bits_idx;\t// @[dcache.scala:443:28]\n wire [1:0] _metaWriteArb_io_out_bits_way_en;\t// @[dcache.scala:443:28]\n wire [21:0] _metaWriteArb_io_out_bits_tag;\t// @[dcache.scala:443:28]\n wire [1:0] _metaWriteArb_io_out_bits_data_coh_state;\t// @[dcache.scala:443:28]\n wire [21:0] _metaWriteArb_io_out_bits_data_tag;\t// @[dcache.scala:443:28]\n wire _meta_0_io_read_ready;\t// @[dcache.scala:442:41]\n wire _meta_0_io_write_ready;\t// @[dcache.scala:442:41]\n wire [1:0] _meta_0_io_resp_0_coh_state;\t// @[dcache.scala:442:41]\n wire [21:0] _meta_0_io_resp_0_tag;\t// @[dcache.scala:442:41]\n wire [1:0] _meta_0_io_resp_1_coh_state;\t// @[dcache.scala:442:41]\n wire [21:0] _meta_0_io_resp_1_tag;\t// @[dcache.scala:442:41]\n wire _mshrs_io_req_0_ready;\t// @[dcache.scala:433:21]\n wire _mshrs_io_secondary_miss_0;\t// @[dcache.scala:433:21]\n wire _mshrs_io_block_hit_0;\t// @[dcache.scala:433:21]\n wire _mshrs_io_mem_grant_ready;\t// @[dcache.scala:433:21]\n wire _mshrs_io_refill_valid;\t// @[dcache.scala:433:21]\n wire [1:0] _mshrs_io_refill_bits_way_en;\t// @[dcache.scala:433:21]\n wire [9:0] _mshrs_io_refill_bits_addr;\t// @[dcache.scala:433:21]\n wire [63:0] _mshrs_io_refill_bits_data;\t// @[dcache.scala:433:21]\n wire _mshrs_io_meta_write_valid;\t// @[dcache.scala:433:21]\n wire [3:0] _mshrs_io_meta_write_bits_idx;\t// @[dcache.scala:433:21]\n wire [1:0] _mshrs_io_meta_write_bits_way_en;\t// @[dcache.scala:433:21]\n wire [1:0] _mshrs_io_meta_write_bits_data_coh_state;\t// @[dcache.scala:433:21]\n wire [21:0] _mshrs_io_meta_write_bits_data_tag;\t// @[dcache.scala:433:21]\n wire _mshrs_io_meta_read_valid;\t// @[dcache.scala:433:21]\n wire [3:0] _mshrs_io_meta_read_bits_idx;\t// @[dcache.scala:433:21]\n wire [1:0] _mshrs_io_meta_read_bits_way_en;\t// @[dcache.scala:433:21]\n wire [21:0] _mshrs_io_meta_read_bits_tag;\t// @[dcache.scala:433:21]\n wire _mshrs_io_replay_valid;\t// @[dcache.scala:433:21]\n wire [4:0] _mshrs_io_replay_bits_uop_mem_cmd;\t// @[dcache.scala:433:21]\n wire [33:0] _mshrs_io_replay_bits_addr;\t// @[dcache.scala:433:21]\n wire [1:0] _mshrs_io_replay_bits_way_en;\t// @[dcache.scala:433:21]\n wire _mshrs_io_wb_req_valid;\t// @[dcache.scala:433:21]\n wire [21:0] _mshrs_io_wb_req_bits_tag;\t// @[dcache.scala:433:21]\n wire [3:0] _mshrs_io_wb_req_bits_idx;\t// @[dcache.scala:433:21]\n wire [3:0] _mshrs_io_wb_req_bits_source;\t// @[dcache.scala:433:21]\n wire [2:0] _mshrs_io_wb_req_bits_param;\t// @[dcache.scala:433:21]\n wire [1:0] _mshrs_io_wb_req_bits_way_en;\t// @[dcache.scala:433:21]\n wire _mshrs_io_fence_rdy;\t// @[dcache.scala:433:21]\n wire _mshrs_io_probe_rdy;\t// @[dcache.scala:433:21]\n wire _prober_io_req_ready;\t// @[dcache.scala:432:22]\n wire _prober_io_rep_valid;\t// @[dcache.scala:432:22]\n wire [2:0] _prober_io_rep_bits_param;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_rep_bits_size;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_rep_bits_source;\t// @[dcache.scala:432:22]\n wire [31:0] _prober_io_rep_bits_address;\t// @[dcache.scala:432:22]\n wire _prober_io_meta_read_valid;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_meta_read_bits_idx;\t// @[dcache.scala:432:22]\n wire [21:0] _prober_io_meta_read_bits_tag;\t// @[dcache.scala:432:22]\n wire _prober_io_meta_write_valid;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_meta_write_bits_idx;\t// @[dcache.scala:432:22]\n wire [1:0] _prober_io_meta_write_bits_way_en;\t// @[dcache.scala:432:22]\n wire [21:0] _prober_io_meta_write_bits_tag;\t// @[dcache.scala:432:22]\n wire [1:0] _prober_io_meta_write_bits_data_coh_state;\t// @[dcache.scala:432:22]\n wire [21:0] _prober_io_meta_write_bits_data_tag;\t// @[dcache.scala:432:22]\n wire _prober_io_wb_req_valid;\t// @[dcache.scala:432:22]\n wire [21:0] _prober_io_wb_req_bits_tag;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_wb_req_bits_idx;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_wb_req_bits_source;\t// @[dcache.scala:432:22]\n wire [2:0] _prober_io_wb_req_bits_param;\t// @[dcache.scala:432:22]\n wire [1:0] _prober_io_wb_req_bits_way_en;\t// @[dcache.scala:432:22]\n wire _prober_io_mshr_wb_rdy;\t// @[dcache.scala:432:22]\n wire _prober_io_lsu_release_valid;\t// @[dcache.scala:432:22]\n wire [2:0] _prober_io_lsu_release_bits_param;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_lsu_release_bits_size;\t// @[dcache.scala:432:22]\n wire [3:0] _prober_io_lsu_release_bits_source;\t// @[dcache.scala:432:22]\n wire [31:0] _prober_io_lsu_release_bits_address;\t// @[dcache.scala:432:22]\n wire _prober_io_state_valid;\t// @[dcache.scala:432:22]\n wire [33:0] _prober_io_state_bits;\t// @[dcache.scala:432:22]\n wire _wb_io_req_ready;\t// @[dcache.scala:431:18]\n wire _wb_io_meta_read_valid;\t// @[dcache.scala:431:18]\n wire [3:0] _wb_io_meta_read_bits_idx;\t// @[dcache.scala:431:18]\n wire [21:0] _wb_io_meta_read_bits_tag;\t// @[dcache.scala:431:18]\n wire _wb_io_resp;\t// @[dcache.scala:431:18]\n wire _wb_io_idx_valid;\t// @[dcache.scala:431:18]\n wire [3:0] _wb_io_idx_bits;\t// @[dcache.scala:431:18]\n wire _wb_io_data_req_valid;\t// @[dcache.scala:431:18]\n wire [1:0] _wb_io_data_req_bits_way_en;\t// @[dcache.scala:431:18]\n wire [9:0] _wb_io_data_req_bits_addr;\t// @[dcache.scala:431:18]\n wire _wb_io_release_valid;\t// @[dcache.scala:431:18]\n wire [2:0] _wb_io_release_bits_opcode;\t// @[dcache.scala:431:18]\n wire [2:0] _wb_io_release_bits_param;\t// @[dcache.scala:431:18]\n wire [31:0] _wb_io_release_bits_address;\t// @[dcache.scala:431:18]\n wire [63:0] _wb_io_release_bits_data;\t// @[dcache.scala:431:18]\n wire _wb_io_lsu_release_valid;\t// @[dcache.scala:431:18]\n wire [2:0] _wb_io_lsu_release_bits_param;\t// @[dcache.scala:431:18]\n wire [31:0] _wb_io_lsu_release_bits_address;\t// @[dcache.scala:431:18]\n wire [63:0] _wb_io_lsu_release_bits_data;\t// @[dcache.scala:431:18]\n wire auto_out_a_ready_0 = auto_out_a_ready;\t// @[dcache.scala:413:7]\n wire auto_out_b_valid_0 = auto_out_b_valid;\t// @[dcache.scala:413:7]\n wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode;\t// @[dcache.scala:413:7]\n wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_b_bits_source_0 = auto_out_b_bits_source;\t// @[dcache.scala:413:7]\n wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address;\t// @[dcache.scala:413:7]\n wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask;\t// @[dcache.scala:413:7]\n wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data;\t// @[dcache.scala:413:7]\n wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt;\t// @[dcache.scala:413:7]\n wire auto_out_c_ready_0 = auto_out_c_ready;\t// @[dcache.scala:413:7]\n wire auto_out_d_valid_0 = auto_out_d_valid;\t// @[dcache.scala:413:7]\n wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode;\t// @[dcache.scala:413:7]\n wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source;\t// @[dcache.scala:413:7]\n wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink;\t// @[dcache.scala:413:7]\n wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied;\t// @[dcache.scala:413:7]\n wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data;\t// @[dcache.scala:413:7]\n wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt;\t// @[dcache.scala:413:7]\n wire auto_out_e_ready_0 = auto_out_e_ready;\t// @[dcache.scala:413:7]\n wire io_lsu_req_valid_0 = io_lsu_req_valid;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_valid_0 = io_lsu_req_bits_0_valid;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_req_bits_0_bits_uop_uopc_0 = io_lsu_req_bits_0_bits_uop_uopc;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_req_bits_0_bits_uop_inst_0 = io_lsu_req_bits_0_bits_uop_inst;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_req_bits_0_bits_uop_debug_inst_0 = io_lsu_req_bits_0_bits_uop_debug_inst;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_rvc_0 = io_lsu_req_bits_0_bits_uop_is_rvc;\t// @[dcache.scala:413:7]\n wire [33:0] io_lsu_req_bits_0_bits_uop_debug_pc_0 = io_lsu_req_bits_0_bits_uop_debug_pc;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_req_bits_0_bits_uop_iq_type_0 = io_lsu_req_bits_0_bits_uop_iq_type;\t// @[dcache.scala:413:7]\n wire [9:0] io_lsu_req_bits_0_bits_uop_fu_code_0 = io_lsu_req_bits_0_bits_uop_fu_code;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type_0 = io_lsu_req_bits_0_bits_uop_ctrl_br_type;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel;\t// @[dcache.scala:413:7]\n wire [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0 = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_ctrl_is_load_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_load;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_sta;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_ctrl_is_std_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_std;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_iw_state_0 = io_lsu_req_bits_0_bits_uop_iw_state;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_br_0 = io_lsu_req_bits_0_bits_uop_is_br;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_jalr_0 = io_lsu_req_bits_0_bits_uop_is_jalr;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_jal_0 = io_lsu_req_bits_0_bits_uop_is_jal;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_sfb_0 = io_lsu_req_bits_0_bits_uop_is_sfb;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_req_bits_0_bits_uop_br_mask_0 = io_lsu_req_bits_0_bits_uop_br_mask;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_br_tag_0 = io_lsu_req_bits_0_bits_uop_br_tag;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_req_bits_0_bits_uop_ftq_idx_0 = io_lsu_req_bits_0_bits_uop_ftq_idx;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_edge_inst_0 = io_lsu_req_bits_0_bits_uop_edge_inst;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_req_bits_0_bits_uop_pc_lob_0 = io_lsu_req_bits_0_bits_uop_pc_lob;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_taken_0 = io_lsu_req_bits_0_bits_uop_taken;\t// @[dcache.scala:413:7]\n wire [19:0] io_lsu_req_bits_0_bits_uop_imm_packed_0 = io_lsu_req_bits_0_bits_uop_imm_packed;\t// @[dcache.scala:413:7]\n wire [11:0] io_lsu_req_bits_0_bits_uop_csr_addr_0 = io_lsu_req_bits_0_bits_uop_csr_addr;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_req_bits_0_bits_uop_rob_idx_0 = io_lsu_req_bits_0_bits_uop_rob_idx;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_req_bits_0_bits_uop_ldq_idx_0 = io_lsu_req_bits_0_bits_uop_ldq_idx;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_req_bits_0_bits_uop_stq_idx_0 = io_lsu_req_bits_0_bits_uop_stq_idx;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx_0 = io_lsu_req_bits_0_bits_uop_rxq_idx;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_req_bits_0_bits_uop_pdst_0 = io_lsu_req_bits_0_bits_uop_pdst;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_req_bits_0_bits_uop_prs1_0 = io_lsu_req_bits_0_bits_uop_prs1;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_req_bits_0_bits_uop_prs2_0 = io_lsu_req_bits_0_bits_uop_prs2;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_req_bits_0_bits_uop_prs3_0 = io_lsu_req_bits_0_bits_uop_prs3;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_req_bits_0_bits_uop_ppred_0 = io_lsu_req_bits_0_bits_uop_ppred;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_prs1_busy_0 = io_lsu_req_bits_0_bits_uop_prs1_busy;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_prs2_busy_0 = io_lsu_req_bits_0_bits_uop_prs2_busy;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_prs3_busy_0 = io_lsu_req_bits_0_bits_uop_prs3_busy;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_ppred_busy_0 = io_lsu_req_bits_0_bits_uop_ppred_busy;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst_0 = io_lsu_req_bits_0_bits_uop_stale_pdst;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_exception_0 = io_lsu_req_bits_0_bits_uop_exception;\t// @[dcache.scala:413:7]\n wire [63:0] io_lsu_req_bits_0_bits_uop_exc_cause_0 = io_lsu_req_bits_0_bits_uop_exc_cause;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_bypassable_0 = io_lsu_req_bits_0_bits_uop_bypassable;\t// @[dcache.scala:413:7]\n wire [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd_0 = io_lsu_req_bits_0_bits_uop_mem_cmd;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_mem_size_0 = io_lsu_req_bits_0_bits_uop_mem_size;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_mem_signed_0 = io_lsu_req_bits_0_bits_uop_mem_signed;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_fence_0 = io_lsu_req_bits_0_bits_uop_is_fence;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_fencei_0 = io_lsu_req_bits_0_bits_uop_is_fencei;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_amo_0 = io_lsu_req_bits_0_bits_uop_is_amo;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_uses_ldq_0 = io_lsu_req_bits_0_bits_uop_uses_ldq;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_uses_stq_0 = io_lsu_req_bits_0_bits_uop_uses_stq;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0 = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_is_unique_0 = io_lsu_req_bits_0_bits_uop_is_unique;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_flush_on_commit_0 = io_lsu_req_bits_0_bits_uop_flush_on_commit;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_req_bits_0_bits_uop_ldst_0 = io_lsu_req_bits_0_bits_uop_ldst;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_req_bits_0_bits_uop_lrs1_0 = io_lsu_req_bits_0_bits_uop_lrs1;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_req_bits_0_bits_uop_lrs2_0 = io_lsu_req_bits_0_bits_uop_lrs2;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_req_bits_0_bits_uop_lrs3_0 = io_lsu_req_bits_0_bits_uop_lrs3;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_ldst_val_0 = io_lsu_req_bits_0_bits_uop_ldst_val;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype_0 = io_lsu_req_bits_0_bits_uop_dst_rtype;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs1_rtype;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs2_rtype;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_frs3_en_0 = io_lsu_req_bits_0_bits_uop_frs3_en;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_fp_val_0 = io_lsu_req_bits_0_bits_uop_fp_val;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_fp_single_0 = io_lsu_req_bits_0_bits_uop_fp_single;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_pf_if;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ae_if;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ma_if;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_bp_debug_if_0 = io_lsu_req_bits_0_bits_uop_bp_debug_if;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0 = io_lsu_req_bits_0_bits_uop_bp_xcpt_if;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc_0 = io_lsu_req_bits_0_bits_uop_debug_fsrc;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc_0 = io_lsu_req_bits_0_bits_uop_debug_tsrc;\t// @[dcache.scala:413:7]\n wire [33:0] io_lsu_req_bits_0_bits_addr_0 = io_lsu_req_bits_0_bits_addr;\t// @[dcache.scala:413:7]\n wire [63:0] io_lsu_req_bits_0_bits_data_0 = io_lsu_req_bits_0_bits_data;\t// @[dcache.scala:413:7]\n wire io_lsu_req_bits_0_bits_is_hella_0 = io_lsu_req_bits_0_bits_is_hella;\t// @[dcache.scala:413:7]\n wire io_lsu_s1_kill_0_0 = io_lsu_s1_kill_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_rob_pnr_idx_0 = io_lsu_rob_pnr_idx;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_rob_head_idx_0 = io_lsu_rob_head_idx;\t// @[dcache.scala:413:7]\n wire io_lsu_release_ready_0 = io_lsu_release_ready;\t// @[dcache.scala:413:7]\n wire io_lsu_force_order_0 = io_lsu_force_order;\t// @[dcache.scala:413:7]\n wire auto_out_a_bits_corrupt = 1'h0;\t// @[dcache.scala:413:7]\n wire auto_out_c_bits_corrupt = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_ctrl_is_load = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_ctrl_is_sta = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_ctrl_is_std = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_iw_p1_poisoned = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_iw_p2_poisoned = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_br = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_jalr = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_jal = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_taken = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_exception = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_bypassable = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_fence = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_amo = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_is_unique = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_ldst_val = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_fp_val = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_fp_single = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_valid = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_mispredict = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_brupdate_b2_taken = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_exception = 1'h0;\t// @[dcache.scala:413:7]\n wire io_lsu_release_bits_corrupt = 1'h0;\t// @[dcache.scala:413:7]\n wire nodeOut_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_bits_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire mshr_read_req_0_uop_is_rvc = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_ctrl_fcn_dw = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_ctrl_is_load = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_ctrl_is_sta = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_ctrl_is_std = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_iw_p1_poisoned = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_iw_p2_poisoned = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_br = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_jalr = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_jal = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_sfb = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_edge_inst = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_taken = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_prs1_busy = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_prs2_busy = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_prs3_busy = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_ppred_busy = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_exception = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_bypassable = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_mem_signed = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_fence = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_fencei = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_amo = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_uses_ldq = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_uses_stq = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_sys_pc2epc = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_is_unique = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_flush_on_commit = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_ldst_is_rs1 = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_ldst_val = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_frs3_en = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_fp_val = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_fp_single = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_xcpt_pf_if = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_xcpt_ae_if = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_xcpt_ma_if = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_bp_debug_if = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_bp_xcpt_if = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_is_hella = 1'h0;\t// @[dcache.scala:517:27]\n wire mshr_read_req_0_uop_uop_is_rvc = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_ctrl_fcn_dw = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_ctrl_is_load = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_ctrl_is_sta = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_ctrl_is_std = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_iw_p1_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_iw_p2_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_br = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_jalr = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_jal = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_sfb = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_edge_inst = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_taken = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_prs1_busy = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_prs2_busy = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_prs3_busy = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_ppred_busy = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_exception = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_bypassable = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_mem_signed = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_fence = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_fencei = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_amo = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_uses_ldq = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_uses_stq = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_sys_pc2epc = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_is_unique = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_flush_on_commit = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_ldst_is_rs1 = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_ldst_val = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_frs3_en = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_fp_val = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_fp_single = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_xcpt_pf_if = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_xcpt_ae_if = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_xcpt_ma_if = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_bp_debug_if = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_uop_bp_xcpt_if = 1'h0;\t// @[consts.scala:269:19]\n wire mshr_read_req_0_uop_cs_fcn_dw = 1'h0;\t// @[consts.scala:279:18]\n wire mshr_read_req_0_uop_cs_is_load = 1'h0;\t// @[consts.scala:279:18]\n wire mshr_read_req_0_uop_cs_is_sta = 1'h0;\t// @[consts.scala:279:18]\n wire mshr_read_req_0_uop_cs_is_std = 1'h0;\t// @[consts.scala:279:18]\n wire wb_req_0_uop_is_rvc = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_ctrl_fcn_dw = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_ctrl_is_load = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_ctrl_is_sta = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_ctrl_is_std = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_iw_p1_poisoned = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_iw_p2_poisoned = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_br = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_jalr = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_jal = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_sfb = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_edge_inst = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_taken = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_prs1_busy = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_prs2_busy = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_prs3_busy = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_ppred_busy = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_exception = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_bypassable = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_mem_signed = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_fence = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_fencei = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_amo = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_uses_ldq = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_uses_stq = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_sys_pc2epc = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_is_unique = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_flush_on_commit = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_ldst_is_rs1 = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_ldst_val = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_frs3_en = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_fp_val = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_fp_single = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_xcpt_pf_if = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_xcpt_ae_if = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_xcpt_ma_if = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_bp_debug_if = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_bp_xcpt_if = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_is_hella = 1'h0;\t// @[dcache.scala:532:20]\n wire wb_req_0_uop_uop_is_rvc = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_ctrl_fcn_dw = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_ctrl_is_load = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_ctrl_is_sta = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_ctrl_is_std = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_iw_p1_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_iw_p2_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_br = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_jalr = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_jal = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_sfb = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_edge_inst = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_taken = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_prs1_busy = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_prs2_busy = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_prs3_busy = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_ppred_busy = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_exception = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_bypassable = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_mem_signed = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_fence = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_fencei = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_amo = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_uses_ldq = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_uses_stq = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_sys_pc2epc = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_is_unique = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_flush_on_commit = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_ldst_is_rs1 = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_ldst_val = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_frs3_en = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_fp_val = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_fp_single = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_xcpt_pf_if = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_xcpt_ae_if = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_xcpt_ma_if = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_bp_debug_if = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_uop_bp_xcpt_if = 1'h0;\t// @[consts.scala:269:19]\n wire wb_req_0_uop_cs_fcn_dw = 1'h0;\t// @[consts.scala:279:18]\n wire wb_req_0_uop_cs_is_load = 1'h0;\t// @[consts.scala:279:18]\n wire wb_req_0_uop_cs_is_sta = 1'h0;\t// @[consts.scala:279:18]\n wire wb_req_0_uop_cs_is_std = 1'h0;\t// @[consts.scala:279:18]\n wire prober_req_0_uop_is_rvc = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_ctrl_fcn_dw = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_ctrl_is_load = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_ctrl_is_sta = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_ctrl_is_std = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_iw_p1_poisoned = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_iw_p2_poisoned = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_br = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_jalr = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_jal = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_sfb = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_edge_inst = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_taken = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_prs1_busy = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_prs2_busy = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_prs3_busy = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_ppred_busy = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_exception = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_bypassable = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_mem_signed = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_fence = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_fencei = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_amo = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_uses_ldq = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_uses_stq = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_sys_pc2epc = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_is_unique = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_flush_on_commit = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_ldst_is_rs1 = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_ldst_val = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_frs3_en = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_fp_val = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_fp_single = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_xcpt_pf_if = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_xcpt_ae_if = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_xcpt_ma_if = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_bp_debug_if = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_bp_xcpt_if = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_is_hella = 1'h0;\t// @[dcache.scala:553:26]\n wire prober_req_0_uop_uop_is_rvc = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_ctrl_fcn_dw = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_ctrl_is_load = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_ctrl_is_sta = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_ctrl_is_std = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_iw_p1_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_iw_p2_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_br = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_jalr = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_jal = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_sfb = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_edge_inst = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_taken = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_prs1_busy = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_prs2_busy = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_prs3_busy = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_ppred_busy = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_exception = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_bypassable = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_mem_signed = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_fence = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_fencei = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_amo = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_uses_ldq = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_uses_stq = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_sys_pc2epc = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_is_unique = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_flush_on_commit = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_ldst_is_rs1 = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_ldst_val = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_frs3_en = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_fp_val = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_fp_single = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_xcpt_pf_if = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_xcpt_ae_if = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_xcpt_ma_if = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_bp_debug_if = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_uop_bp_xcpt_if = 1'h0;\t// @[consts.scala:269:19]\n wire prober_req_0_uop_cs_fcn_dw = 1'h0;\t// @[consts.scala:279:18]\n wire prober_req_0_uop_cs_is_load = 1'h0;\t// @[consts.scala:279:18]\n wire prober_req_0_uop_cs_is_sta = 1'h0;\t// @[consts.scala:279:18]\n wire prober_req_0_uop_cs_is_std = 1'h0;\t// @[consts.scala:279:18]\n wire prefetch_fire = 1'h0;\t// @[Decoupled.scala:51:35]\n wire prefetch_req_0_uop_is_rvc = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_ctrl_fcn_dw = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_ctrl_is_load = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_ctrl_is_sta = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_ctrl_is_std = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_iw_p1_poisoned = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_iw_p2_poisoned = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_br = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_jalr = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_jal = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_sfb = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_edge_inst = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_taken = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_prs1_busy = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_prs2_busy = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_prs3_busy = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_ppred_busy = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_exception = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_bypassable = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_mem_signed = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_fence = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_fencei = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_amo = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_uses_ldq = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_uses_stq = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_sys_pc2epc = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_is_unique = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_flush_on_commit = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_ldst_is_rs1 = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_ldst_val = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_frs3_en = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_fp_val = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_fp_single = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_xcpt_pf_if = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_xcpt_ae_if = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_xcpt_ma_if = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_bp_debug_if = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_uop_bp_xcpt_if = 1'h0;\t// @[dcache.scala:568:27]\n wire prefetch_req_0_is_hella = 1'h0;\t// @[dcache.scala:568:27]\n wire _s0_valid_WIRE_2_0 = 1'h0;\t// @[dcache.scala:581:82]\n wire _s1_valid_T_1 = 1'h0;\t// @[util.scala:118:59]\n wire _s1_valid_T_4 = 1'h0;\t// @[dcache.scala:607:45]\n wire _s2_valid_T_3 = 1'h0;\t// @[util.scala:118:59]\n wire _s2_valid_T_6 = 1'h0;\t// @[dcache.scala:638:45]\n wire _s2_has_permission_r_T_26 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_has_permission_r_T_29 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_has_permission_r_T_32 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_has_permission_r_T_35 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_has_permission_r_T_38 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_new_hit_state_r_T_26 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_new_hit_state_r_T_29 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_new_hit_state_r_T_32 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_new_hit_state_r_T_35 = 1'h0;\t// @[Misc.scala:35:9]\n wire _s2_new_hit_state_r_T_38 = 1'h0;\t// @[Misc.scala:35:9]\n wire s2_word_idx_0 = 1'h0;\t// @[dcache.scala:427:49]\n wire s2_nack_data_0 = 1'h0;\t// @[dcache.scala:427:49]\n wire _mshrs_io_req_0_valid_T_15 = 1'h0;\t// @[util.scala:118:59]\n wire _mshrs_io_req_0_valid_T_18 = 1'h0;\t// @[dcache.scala:754:48]\n wire opdata_1 = 1'h0;\t// @[Edges.scala:102:36]\n wire _state_WIRE_0 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _state_WIRE_1 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _nodeOut_c_bits_WIRE_corrupt = 1'h0;\t// @[Mux.scala:30:73]\n wire _nodeOut_c_bits_T = 1'h0;\t// @[Mux.scala:30:73]\n wire _nodeOut_c_bits_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire _nodeOut_c_bits_T_2 = 1'h0;\t// @[Mux.scala:30:73]\n wire _nodeOut_c_bits_WIRE_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire cache_resp_0_bits_data_doZero = 1'h0;\t// @[AMOALU.scala:43:31]\n wire cache_resp_0_bits_data_doZero_1 = 1'h0;\t// @[AMOALU.scala:43:31]\n wire _io_lsu_resp_0_valid_T = 1'h0;\t// @[dcache.scala:858:48]\n wire _io_lsu_resp_0_valid_T_4 = 1'h0;\t// @[util.scala:118:59]\n wire _io_lsu_nack_0_valid_T_1 = 1'h0;\t// @[dcache.scala:863:48]\n wire _io_lsu_nack_0_valid_T_5 = 1'h0;\t// @[util.scala:118:59]\n wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0;\t// @[dcache.scala:413:7]\n wire [3:0] mshr_read_req_0_uop_ctrl_br_type = 4'h0;\t// @[dcache.scala:517:27]\n wire [3:0] mshr_read_req_0_uop_br_mask = 4'h0;\t// @[dcache.scala:517:27]\n wire [3:0] mshr_read_req_0_uop_ftq_idx = 4'h0;\t// @[dcache.scala:517:27]\n wire [3:0] mshr_read_req_0_uop_ldq_idx = 4'h0;\t// @[dcache.scala:517:27]\n wire [3:0] mshr_read_req_0_uop_stq_idx = 4'h0;\t// @[dcache.scala:517:27]\n wire [3:0] mshr_read_req_0_uop_ppred = 4'h0;\t// @[dcache.scala:517:27]\n wire [3:0] mshr_read_req_0_uop_uop_ctrl_br_type = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] mshr_read_req_0_uop_uop_br_mask = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] mshr_read_req_0_uop_uop_ftq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] mshr_read_req_0_uop_uop_ldq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] mshr_read_req_0_uop_uop_stq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] mshr_read_req_0_uop_uop_ppred = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] mshr_read_req_0_uop_cs_br_type = 4'h0;\t// @[consts.scala:279:18]\n wire [3:0] wb_req_0_uop_ctrl_br_type = 4'h0;\t// @[dcache.scala:532:20]\n wire [3:0] wb_req_0_uop_br_mask = 4'h0;\t// @[dcache.scala:532:20]\n wire [3:0] wb_req_0_uop_ftq_idx = 4'h0;\t// @[dcache.scala:532:20]\n wire [3:0] wb_req_0_uop_ldq_idx = 4'h0;\t// @[dcache.scala:532:20]\n wire [3:0] wb_req_0_uop_stq_idx = 4'h0;\t// @[dcache.scala:532:20]\n wire [3:0] wb_req_0_uop_ppred = 4'h0;\t// @[dcache.scala:532:20]\n wire [3:0] wb_req_0_uop_uop_ctrl_br_type = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] wb_req_0_uop_uop_br_mask = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] wb_req_0_uop_uop_ftq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] wb_req_0_uop_uop_ldq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] wb_req_0_uop_uop_stq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] wb_req_0_uop_uop_ppred = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] wb_req_0_uop_cs_br_type = 4'h0;\t// @[consts.scala:279:18]\n wire [3:0] prober_req_0_uop_ctrl_br_type = 4'h0;\t// @[dcache.scala:553:26]\n wire [3:0] prober_req_0_uop_br_mask = 4'h0;\t// @[dcache.scala:553:26]\n wire [3:0] prober_req_0_uop_ftq_idx = 4'h0;\t// @[dcache.scala:553:26]\n wire [3:0] prober_req_0_uop_ldq_idx = 4'h0;\t// @[dcache.scala:553:26]\n wire [3:0] prober_req_0_uop_stq_idx = 4'h0;\t// @[dcache.scala:553:26]\n wire [3:0] prober_req_0_uop_ppred = 4'h0;\t// @[dcache.scala:553:26]\n wire [3:0] prober_req_0_uop_uop_ctrl_br_type = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] prober_req_0_uop_uop_br_mask = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] prober_req_0_uop_uop_ftq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] prober_req_0_uop_uop_ldq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] prober_req_0_uop_uop_stq_idx = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] prober_req_0_uop_uop_ppred = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] prober_req_0_uop_cs_br_type = 4'h0;\t// @[consts.scala:279:18]\n wire [3:0] prefetch_req_0_uop_ctrl_br_type = 4'h0;\t// @[dcache.scala:568:27]\n wire [3:0] prefetch_req_0_uop_br_mask = 4'h0;\t// @[dcache.scala:568:27]\n wire [3:0] prefetch_req_0_uop_ftq_idx = 4'h0;\t// @[dcache.scala:568:27]\n wire [3:0] prefetch_req_0_uop_ldq_idx = 4'h0;\t// @[dcache.scala:568:27]\n wire [3:0] prefetch_req_0_uop_stq_idx = 4'h0;\t// @[dcache.scala:568:27]\n wire [3:0] prefetch_req_0_uop_ppred = 4'h0;\t// @[dcache.scala:568:27]\n wire [3:0] _s1_valid_T = 4'h0;\t// @[util.scala:118:51]\n wire [3:0] _s2_valid_T_2 = 4'h0;\t// @[util.scala:118:51]\n wire [3:0] _s2_has_permission_r_T_16 = 4'h0;\t// @[Metadata.scala:68:10]\n wire [3:0] _s2_new_hit_state_r_T_16 = 4'h0;\t// @[Metadata.scala:68:10]\n wire [3:0] _mshrs_io_req_0_valid_T_14 = 4'h0;\t// @[util.scala:118:51]\n wire [3:0] _io_lsu_resp_0_valid_T_3 = 4'h0;\t// @[util.scala:118:51]\n wire [3:0] _io_lsu_nack_0_valid_T_4 = 4'h0;\t// @[util.scala:118:51]\n wire [6:0] io_lsu_brupdate_b2_uop_uopc = 7'h0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_brupdate_b2_uop_pdst = 7'h0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_brupdate_b2_uop_prs1 = 7'h0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_brupdate_b2_uop_prs2 = 7'h0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_brupdate_b2_uop_prs3 = 7'h0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst = 7'h0;\t// @[dcache.scala:413:7]\n wire [6:0] mshr_read_req_0_uop_uopc = 7'h0;\t// @[dcache.scala:517:27]\n wire [6:0] mshr_read_req_0_uop_pdst = 7'h0;\t// @[dcache.scala:517:27]\n wire [6:0] mshr_read_req_0_uop_prs1 = 7'h0;\t// @[dcache.scala:517:27]\n wire [6:0] mshr_read_req_0_uop_prs2 = 7'h0;\t// @[dcache.scala:517:27]\n wire [6:0] mshr_read_req_0_uop_prs3 = 7'h0;\t// @[dcache.scala:517:27]\n wire [6:0] mshr_read_req_0_uop_stale_pdst = 7'h0;\t// @[dcache.scala:517:27]\n wire [6:0] mshr_read_req_0_uop_uop_uopc = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] mshr_read_req_0_uop_uop_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] mshr_read_req_0_uop_uop_prs1 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] mshr_read_req_0_uop_uop_prs2 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] mshr_read_req_0_uop_uop_prs3 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] mshr_read_req_0_uop_uop_stale_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] wb_req_0_uop_uopc = 7'h0;\t// @[dcache.scala:532:20]\n wire [6:0] wb_req_0_uop_pdst = 7'h0;\t// @[dcache.scala:532:20]\n wire [6:0] wb_req_0_uop_prs1 = 7'h0;\t// @[dcache.scala:532:20]\n wire [6:0] wb_req_0_uop_prs2 = 7'h0;\t// @[dcache.scala:532:20]\n wire [6:0] wb_req_0_uop_prs3 = 7'h0;\t// @[dcache.scala:532:20]\n wire [6:0] wb_req_0_uop_stale_pdst = 7'h0;\t// @[dcache.scala:532:20]\n wire [6:0] wb_req_0_uop_uop_uopc = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] wb_req_0_uop_uop_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] wb_req_0_uop_uop_prs1 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] wb_req_0_uop_uop_prs2 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] wb_req_0_uop_uop_prs3 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] wb_req_0_uop_uop_stale_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] prober_req_0_uop_uopc = 7'h0;\t// @[dcache.scala:553:26]\n wire [6:0] prober_req_0_uop_pdst = 7'h0;\t// @[dcache.scala:553:26]\n wire [6:0] prober_req_0_uop_prs1 = 7'h0;\t// @[dcache.scala:553:26]\n wire [6:0] prober_req_0_uop_prs2 = 7'h0;\t// @[dcache.scala:553:26]\n wire [6:0] prober_req_0_uop_prs3 = 7'h0;\t// @[dcache.scala:553:26]\n wire [6:0] prober_req_0_uop_stale_pdst = 7'h0;\t// @[dcache.scala:553:26]\n wire [6:0] prober_req_0_uop_uop_uopc = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] prober_req_0_uop_uop_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] prober_req_0_uop_uop_prs1 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] prober_req_0_uop_uop_prs2 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] prober_req_0_uop_uop_prs3 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] prober_req_0_uop_uop_stale_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] prefetch_req_0_uop_uopc = 7'h0;\t// @[dcache.scala:568:27]\n wire [6:0] prefetch_req_0_uop_pdst = 7'h0;\t// @[dcache.scala:568:27]\n wire [6:0] prefetch_req_0_uop_prs1 = 7'h0;\t// @[dcache.scala:568:27]\n wire [6:0] prefetch_req_0_uop_prs2 = 7'h0;\t// @[dcache.scala:568:27]\n wire [6:0] prefetch_req_0_uop_prs3 = 7'h0;\t// @[dcache.scala:568:27]\n wire [6:0] prefetch_req_0_uop_stale_pdst = 7'h0;\t// @[dcache.scala:568:27]\n wire [6:0] _s2_data_word_prebypass_T = 7'h0;\t// @[dcache.scala:825:69]\n wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0;\t// @[dcache.scala:413:7]\n wire [31:0] mshr_read_req_0_uop_inst = 32'h0;\t// @[dcache.scala:517:27]\n wire [31:0] mshr_read_req_0_uop_debug_inst = 32'h0;\t// @[dcache.scala:517:27]\n wire [31:0] mshr_read_req_0_uop_uop_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] mshr_read_req_0_uop_uop_debug_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] wb_req_0_uop_inst = 32'h0;\t// @[dcache.scala:532:20]\n wire [31:0] wb_req_0_uop_debug_inst = 32'h0;\t// @[dcache.scala:532:20]\n wire [31:0] wb_req_0_uop_uop_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] wb_req_0_uop_uop_debug_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] prober_req_0_uop_inst = 32'h0;\t// @[dcache.scala:553:26]\n wire [31:0] prober_req_0_uop_debug_inst = 32'h0;\t// @[dcache.scala:553:26]\n wire [31:0] prober_req_0_uop_uop_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] prober_req_0_uop_uop_debug_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] prefetch_req_0_uop_inst = 32'h0;\t// @[dcache.scala:568:27]\n wire [31:0] prefetch_req_0_uop_debug_inst = 32'h0;\t// @[dcache.scala:568:27]\n wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0;\t// @[dcache.scala:413:7]\n wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0;\t// @[dcache.scala:413:7]\n wire [33:0] mshr_read_req_0_uop_debug_pc = 34'h0;\t// @[dcache.scala:517:27]\n wire [33:0] mshr_read_req_0_uop_uop_debug_pc = 34'h0;\t// @[consts.scala:269:19]\n wire [33:0] wb_req_0_uop_debug_pc = 34'h0;\t// @[dcache.scala:532:20]\n wire [33:0] wb_req_0_uop_uop_debug_pc = 34'h0;\t// @[consts.scala:269:19]\n wire [33:0] prober_req_0_uop_debug_pc = 34'h0;\t// @[dcache.scala:553:26]\n wire [33:0] prober_req_0_uop_uop_debug_pc = 34'h0;\t// @[consts.scala:269:19]\n wire [33:0] prefetch_req_0_uop_debug_pc = 34'h0;\t// @[dcache.scala:568:27]\n wire [33:0] prefetch_req_0_addr = 34'h0;\t// @[dcache.scala:568:27]\n wire [2:0] io_lsu_brupdate_b2_uop_iq_type = 3'h0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel = 3'h0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel = 3'h0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd = 3'h0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0;\t// @[dcache.scala:413:7]\n wire [2:0] mshr_read_req_0_uop_iq_type = 3'h0;\t// @[dcache.scala:517:27]\n wire [2:0] mshr_read_req_0_uop_ctrl_op2_sel = 3'h0;\t// @[dcache.scala:517:27]\n wire [2:0] mshr_read_req_0_uop_ctrl_imm_sel = 3'h0;\t// @[dcache.scala:517:27]\n wire [2:0] mshr_read_req_0_uop_ctrl_csr_cmd = 3'h0;\t// @[dcache.scala:517:27]\n wire [2:0] mshr_read_req_0_uop_uop_iq_type = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] mshr_read_req_0_uop_uop_ctrl_op2_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] mshr_read_req_0_uop_uop_ctrl_imm_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] mshr_read_req_0_uop_uop_ctrl_csr_cmd = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] mshr_read_req_0_uop_cs_op2_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] mshr_read_req_0_uop_cs_imm_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] mshr_read_req_0_uop_cs_csr_cmd = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] wb_req_0_uop_iq_type = 3'h0;\t// @[dcache.scala:532:20]\n wire [2:0] wb_req_0_uop_ctrl_op2_sel = 3'h0;\t// @[dcache.scala:532:20]\n wire [2:0] wb_req_0_uop_ctrl_imm_sel = 3'h0;\t// @[dcache.scala:532:20]\n wire [2:0] wb_req_0_uop_ctrl_csr_cmd = 3'h0;\t// @[dcache.scala:532:20]\n wire [2:0] wb_req_0_uop_uop_iq_type = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] wb_req_0_uop_uop_ctrl_op2_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] wb_req_0_uop_uop_ctrl_imm_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] wb_req_0_uop_uop_ctrl_csr_cmd = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] wb_req_0_uop_cs_op2_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] wb_req_0_uop_cs_imm_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] wb_req_0_uop_cs_csr_cmd = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] prober_req_0_uop_iq_type = 3'h0;\t// @[dcache.scala:553:26]\n wire [2:0] prober_req_0_uop_ctrl_op2_sel = 3'h0;\t// @[dcache.scala:553:26]\n wire [2:0] prober_req_0_uop_ctrl_imm_sel = 3'h0;\t// @[dcache.scala:553:26]\n wire [2:0] prober_req_0_uop_ctrl_csr_cmd = 3'h0;\t// @[dcache.scala:553:26]\n wire [2:0] prober_req_0_uop_uop_iq_type = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] prober_req_0_uop_uop_ctrl_op2_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] prober_req_0_uop_uop_ctrl_imm_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] prober_req_0_uop_uop_ctrl_csr_cmd = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] prober_req_0_uop_cs_op2_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] prober_req_0_uop_cs_imm_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] prober_req_0_uop_cs_csr_cmd = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] prefetch_req_0_uop_iq_type = 3'h0;\t// @[dcache.scala:568:27]\n wire [2:0] prefetch_req_0_uop_ctrl_op2_sel = 3'h0;\t// @[dcache.scala:568:27]\n wire [2:0] prefetch_req_0_uop_ctrl_imm_sel = 3'h0;\t// @[dcache.scala:568:27]\n wire [2:0] prefetch_req_0_uop_ctrl_csr_cmd = 3'h0;\t// @[dcache.scala:568:27]\n wire [9:0] io_lsu_brupdate_b2_uop_fu_code = 10'h0;\t// @[dcache.scala:413:7]\n wire [9:0] mshr_read_req_0_uop_fu_code = 10'h0;\t// @[dcache.scala:517:27]\n wire [9:0] mshr_read_req_0_uop_uop_fu_code = 10'h0;\t// @[consts.scala:269:19]\n wire [9:0] wb_req_0_uop_fu_code = 10'h0;\t// @[dcache.scala:532:20]\n wire [9:0] wb_req_0_uop_uop_fu_code = 10'h0;\t// @[consts.scala:269:19]\n wire [9:0] prober_req_0_uop_fu_code = 10'h0;\t// @[dcache.scala:553:26]\n wire [9:0] prober_req_0_uop_uop_fu_code = 10'h0;\t// @[consts.scala:269:19]\n wire [9:0] prefetch_req_0_uop_fu_code = 10'h0;\t// @[dcache.scala:568:27]\n wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_iw_state = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_brupdate_b2_target_offset = 2'h0;\t// @[dcache.scala:413:7]\n wire [1:0] mshr_read_req_0_uop_ctrl_op1_sel = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_iw_state = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_br_tag = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_rxq_idx = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_mem_size = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_lrs1_rtype = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_lrs2_rtype = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_debug_fsrc = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_debug_tsrc = 2'h0;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_uop_ctrl_op1_sel = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_iw_state = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_br_tag = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_rxq_idx = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_mem_size = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_lrs1_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_lrs2_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_debug_fsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_uop_debug_tsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] mshr_read_req_0_uop_cs_op1_sel = 2'h0;\t// @[consts.scala:279:18]\n wire [1:0] wb_req_0_uop_ctrl_op1_sel = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_iw_state = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_br_tag = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_rxq_idx = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_mem_size = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_lrs1_rtype = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_lrs2_rtype = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_debug_fsrc = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_debug_tsrc = 2'h0;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_uop_ctrl_op1_sel = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_iw_state = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_br_tag = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_rxq_idx = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_mem_size = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_lrs1_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_lrs2_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_debug_fsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_uop_debug_tsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_cs_op1_sel = 2'h0;\t// @[consts.scala:279:18]\n wire [1:0] prober_req_0_uop_ctrl_op1_sel = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_iw_state = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_br_tag = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_rxq_idx = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_mem_size = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_lrs1_rtype = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_lrs2_rtype = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_debug_fsrc = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_debug_tsrc = 2'h0;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_uop_ctrl_op1_sel = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_iw_state = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_br_tag = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_rxq_idx = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_mem_size = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_lrs1_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_lrs2_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_debug_fsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_uop_debug_tsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_cs_op1_sel = 2'h0;\t// @[consts.scala:279:18]\n wire [1:0] prefetch_req_0_uop_ctrl_op1_sel = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_iw_state = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_br_tag = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_rxq_idx = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_mem_size = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_dst_rtype = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_lrs1_rtype = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_lrs2_rtype = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_debug_fsrc = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] prefetch_req_0_uop_debug_tsrc = 2'h0;\t// @[dcache.scala:568:27]\n wire [1:0] _s2_has_permission_r_T_1 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [1:0] _s2_has_permission_r_T_3 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [1:0] _s2_has_permission_r_T_5 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [1:0] _s2_has_permission_r_T_15 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [1:0] _s2_new_hit_state_r_T_1 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [1:0] _s2_new_hit_state_r_T_3 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [1:0] _s2_new_hit_state_r_T_5 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [1:0] _s2_new_hit_state_r_T_15 = 2'h0;\t// @[Metadata.scala:26:15]\n wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn = 5'h0;\t// @[dcache.scala:413:7]\n wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0;\t// @[dcache.scala:413:7]\n wire [4:0] mshr_read_req_0_uop_ctrl_op_fcn = 5'h0;\t// @[dcache.scala:517:27]\n wire [4:0] mshr_read_req_0_uop_mem_cmd = 5'h0;\t// @[dcache.scala:517:27]\n wire [4:0] mshr_read_req_0_uop_uop_ctrl_op_fcn = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] mshr_read_req_0_uop_uop_mem_cmd = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] mshr_read_req_0_uop_cs_op_fcn = 5'h0;\t// @[consts.scala:279:18]\n wire [4:0] wb_req_0_uop_ctrl_op_fcn = 5'h0;\t// @[dcache.scala:532:20]\n wire [4:0] wb_req_0_uop_mem_cmd = 5'h0;\t// @[dcache.scala:532:20]\n wire [4:0] wb_req_0_uop_uop_ctrl_op_fcn = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] wb_req_0_uop_uop_mem_cmd = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] wb_req_0_uop_cs_op_fcn = 5'h0;\t// @[consts.scala:279:18]\n wire [4:0] prober_req_0_uop_ctrl_op_fcn = 5'h0;\t// @[dcache.scala:553:26]\n wire [4:0] prober_req_0_uop_mem_cmd = 5'h0;\t// @[dcache.scala:553:26]\n wire [4:0] prober_req_0_uop_uop_ctrl_op_fcn = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] prober_req_0_uop_uop_mem_cmd = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] prober_req_0_uop_cs_op_fcn = 5'h0;\t// @[consts.scala:279:18]\n wire [4:0] prefetch_req_0_uop_ctrl_op_fcn = 5'h0;\t// @[dcache.scala:568:27]\n wire [4:0] prefetch_req_0_uop_mem_cmd = 5'h0;\t// @[dcache.scala:568:27]\n wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_brupdate_b2_uop_rob_idx = 6'h0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0;\t// @[dcache.scala:413:7]\n wire [5:0] mshr_read_req_0_uop_pc_lob = 6'h0;\t// @[dcache.scala:517:27]\n wire [5:0] mshr_read_req_0_uop_rob_idx = 6'h0;\t// @[dcache.scala:517:27]\n wire [5:0] mshr_read_req_0_uop_ldst = 6'h0;\t// @[dcache.scala:517:27]\n wire [5:0] mshr_read_req_0_uop_lrs1 = 6'h0;\t// @[dcache.scala:517:27]\n wire [5:0] mshr_read_req_0_uop_lrs2 = 6'h0;\t// @[dcache.scala:517:27]\n wire [5:0] mshr_read_req_0_uop_lrs3 = 6'h0;\t// @[dcache.scala:517:27]\n wire [5:0] mshr_read_req_0_uop_uop_pc_lob = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] mshr_read_req_0_uop_uop_rob_idx = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] mshr_read_req_0_uop_uop_ldst = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] mshr_read_req_0_uop_uop_lrs1 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] mshr_read_req_0_uop_uop_lrs2 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] mshr_read_req_0_uop_uop_lrs3 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] wb_req_0_uop_pc_lob = 6'h0;\t// @[dcache.scala:532:20]\n wire [5:0] wb_req_0_uop_rob_idx = 6'h0;\t// @[dcache.scala:532:20]\n wire [5:0] wb_req_0_uop_ldst = 6'h0;\t// @[dcache.scala:532:20]\n wire [5:0] wb_req_0_uop_lrs1 = 6'h0;\t// @[dcache.scala:532:20]\n wire [5:0] wb_req_0_uop_lrs2 = 6'h0;\t// @[dcache.scala:532:20]\n wire [5:0] wb_req_0_uop_lrs3 = 6'h0;\t// @[dcache.scala:532:20]\n wire [5:0] wb_req_0_uop_uop_pc_lob = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] wb_req_0_uop_uop_rob_idx = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] wb_req_0_uop_uop_ldst = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] wb_req_0_uop_uop_lrs1 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] wb_req_0_uop_uop_lrs2 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] wb_req_0_uop_uop_lrs3 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] prober_req_0_uop_pc_lob = 6'h0;\t// @[dcache.scala:553:26]\n wire [5:0] prober_req_0_uop_rob_idx = 6'h0;\t// @[dcache.scala:553:26]\n wire [5:0] prober_req_0_uop_ldst = 6'h0;\t// @[dcache.scala:553:26]\n wire [5:0] prober_req_0_uop_lrs1 = 6'h0;\t// @[dcache.scala:553:26]\n wire [5:0] prober_req_0_uop_lrs2 = 6'h0;\t// @[dcache.scala:553:26]\n wire [5:0] prober_req_0_uop_lrs3 = 6'h0;\t// @[dcache.scala:553:26]\n wire [5:0] prober_req_0_uop_uop_pc_lob = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] prober_req_0_uop_uop_rob_idx = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] prober_req_0_uop_uop_ldst = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] prober_req_0_uop_uop_lrs1 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] prober_req_0_uop_uop_lrs2 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] prober_req_0_uop_uop_lrs3 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] prefetch_req_0_uop_pc_lob = 6'h0;\t// @[dcache.scala:568:27]\n wire [5:0] prefetch_req_0_uop_rob_idx = 6'h0;\t// @[dcache.scala:568:27]\n wire [5:0] prefetch_req_0_uop_ldst = 6'h0;\t// @[dcache.scala:568:27]\n wire [5:0] prefetch_req_0_uop_lrs1 = 6'h0;\t// @[dcache.scala:568:27]\n wire [5:0] prefetch_req_0_uop_lrs2 = 6'h0;\t// @[dcache.scala:568:27]\n wire [5:0] prefetch_req_0_uop_lrs3 = 6'h0;\t// @[dcache.scala:568:27]\n wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0;\t// @[dcache.scala:413:7]\n wire [19:0] mshr_read_req_0_uop_imm_packed = 20'h0;\t// @[dcache.scala:517:27]\n wire [19:0] mshr_read_req_0_uop_uop_imm_packed = 20'h0;\t// @[consts.scala:269:19]\n wire [19:0] wb_req_0_uop_imm_packed = 20'h0;\t// @[dcache.scala:532:20]\n wire [19:0] wb_req_0_uop_uop_imm_packed = 20'h0;\t// @[consts.scala:269:19]\n wire [19:0] prober_req_0_uop_imm_packed = 20'h0;\t// @[dcache.scala:553:26]\n wire [19:0] prober_req_0_uop_uop_imm_packed = 20'h0;\t// @[consts.scala:269:19]\n wire [19:0] prefetch_req_0_uop_imm_packed = 20'h0;\t// @[dcache.scala:568:27]\n wire [11:0] io_lsu_brupdate_b2_uop_csr_addr = 12'h0;\t// @[dcache.scala:413:7]\n wire [11:0] mshr_read_req_0_uop_csr_addr = 12'h0;\t// @[dcache.scala:517:27]\n wire [11:0] mshr_read_req_0_uop_uop_csr_addr = 12'h0;\t// @[consts.scala:269:19]\n wire [11:0] wb_req_0_uop_csr_addr = 12'h0;\t// @[dcache.scala:532:20]\n wire [11:0] wb_req_0_uop_uop_csr_addr = 12'h0;\t// @[consts.scala:269:19]\n wire [11:0] prober_req_0_uop_csr_addr = 12'h0;\t// @[dcache.scala:553:26]\n wire [11:0] prober_req_0_uop_uop_csr_addr = 12'h0;\t// @[consts.scala:269:19]\n wire [11:0] prefetch_req_0_uop_csr_addr = 12'h0;\t// @[dcache.scala:568:27]\n wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0;\t// @[dcache.scala:413:7]\n wire [63:0] mshr_read_req_0_uop_exc_cause = 64'h0;\t// @[dcache.scala:517:27]\n wire [63:0] mshr_read_req_0_data = 64'h0;\t// @[dcache.scala:517:27]\n wire [63:0] mshr_read_req_0_uop_uop_exc_cause = 64'h0;\t// @[consts.scala:269:19]\n wire [63:0] wb_req_0_uop_exc_cause = 64'h0;\t// @[dcache.scala:532:20]\n wire [63:0] wb_req_0_data = 64'h0;\t// @[dcache.scala:532:20]\n wire [63:0] wb_req_0_uop_uop_exc_cause = 64'h0;\t// @[consts.scala:269:19]\n wire [63:0] prober_req_0_uop_exc_cause = 64'h0;\t// @[dcache.scala:553:26]\n wire [63:0] prober_req_0_data = 64'h0;\t// @[dcache.scala:553:26]\n wire [63:0] prober_req_0_uop_uop_exc_cause = 64'h0;\t// @[consts.scala:269:19]\n wire [63:0] prefetch_req_0_uop_exc_cause = 64'h0;\t// @[dcache.scala:568:27]\n wire [63:0] prefetch_req_0_data = 64'h0;\t// @[dcache.scala:568:27]\n wire [63:0] _nodeOut_c_bits_T_4 = 64'h0;\t// @[Mux.scala:30:73]\n wire [3:0] _s1_req_0_uop_br_mask_T = 4'hF;\t// @[util.scala:85:27]\n wire [3:0] _s2_req_0_uop_br_mask_T = 4'hF;\t// @[util.scala:85:27]\n wire [3:0] _s2_has_permission_r_T_12 = 4'hF;\t// @[Metadata.scala:65:10]\n wire [3:0] _s2_new_hit_state_r_T_12 = 4'hF;\t// @[Metadata.scala:65:10]\n wire [3:0] _mshrs_io_req_0_bits_uop_br_mask_T = 4'hF;\t// @[util.scala:85:27]\n wire [3:0] _io_lsu_resp_0_bits_out_uop_br_mask_T = 4'hF;\t// @[util.scala:89:23]\n wire [3:0] _io_lsu_nack_0_bits_out_uop_br_mask_T = 4'hF;\t// @[util.scala:89:23]\n wire _s0_valid_WIRE_1_0 = 1'h1;\t// @[dcache.scala:581:48]\n wire _s1_valid_T_2 = 1'h1;\t// @[dcache.scala:606:26]\n wire _s1_valid_T_5 = 1'h1;\t// @[dcache.scala:607:26]\n wire _s2_valid_T_4 = 1'h1;\t// @[dcache.scala:637:26]\n wire _s2_valid_T_7 = 1'h1;\t// @[dcache.scala:638:26]\n wire _mshrs_io_req_0_valid_T_6 = 1'h1;\t// @[dcache.scala:750:29]\n wire _mshrs_io_req_0_valid_T_16 = 1'h1;\t// @[dcache.scala:753:29]\n wire _mshrs_io_req_0_valid_T_19 = 1'h1;\t// @[dcache.scala:754:29]\n wire _uncache_respond_T_1 = 1'h1;\t// @[dcache.scala:849:51]\n wire _io_lsu_resp_0_valid_T_1 = 1'h1;\t// @[dcache.scala:858:29]\n wire _io_lsu_resp_0_valid_T_5 = 1'h1;\t// @[dcache.scala:859:29]\n wire _io_lsu_nack_0_valid_T_2 = 1'h1;\t// @[dcache.scala:863:29]\n wire _io_lsu_nack_0_valid_T_6 = 1'h1;\t// @[dcache.scala:864:29]\n wire [8:0] maskedBeats_1 = 9'h0;\t// @[Arbiter.scala:82:69]\n wire [8:0] decode = 9'h7;\t// @[Edges.scala:220:59]\n wire [11:0] _decode_T_2 = 12'h3F;\t// @[package.scala:243:46]\n wire [11:0] _decode_T_1 = 12'hFC0;\t// @[package.scala:243:76]\n wire [26:0] _decode_T = 27'h3FFC0;\t// @[package.scala:243:71]\n wire [3:0] _s2_has_permission_r_T_10 = 4'h6;\t// @[Metadata.scala:64:10]\n wire [3:0] _s2_new_hit_state_r_T_10 = 4'h6;\t// @[Metadata.scala:64:10]\n wire [3:0] _s2_has_permission_r_T_24 = 4'hC;\t// @[Metadata.scala:72:10]\n wire [3:0] _s2_new_hit_state_r_T_24 = 4'hC;\t// @[Metadata.scala:72:10]\n wire [3:0] _s2_has_permission_r_T_22 = 4'hD;\t// @[Metadata.scala:71:10]\n wire [3:0] _s2_new_hit_state_r_T_22 = 4'hD;\t// @[Metadata.scala:71:10]\n wire [3:0] _s2_has_permission_r_T_20 = 4'h4;\t// @[Metadata.scala:70:10]\n wire [3:0] _s2_new_hit_state_r_T_20 = 4'h4;\t// @[Metadata.scala:70:10]\n wire [3:0] _s2_has_permission_r_T_18 = 4'h5;\t// @[Metadata.scala:69:10]\n wire [3:0] _s2_new_hit_state_r_T_18 = 4'h5;\t// @[Metadata.scala:69:10]\n wire [3:0] _s2_has_permission_r_T_14 = 4'hE;\t// @[Metadata.scala:66:10]\n wire [3:0] _s2_new_hit_state_r_T_14 = 4'hE;\t// @[Metadata.scala:66:10]\n wire [3:0] _s2_has_permission_r_T_8 = 4'h7;\t// @[Metadata.scala:63:10]\n wire [3:0] _s2_new_hit_state_r_T_8 = 4'h7;\t// @[Metadata.scala:63:10]\n wire [3:0] _s2_has_permission_r_T_6 = 4'h1;\t// @[Metadata.scala:62:10]\n wire [3:0] _s2_new_hit_state_r_T_6 = 4'h1;\t// @[Metadata.scala:62:10]\n wire [3:0] _s2_has_permission_r_T_4 = 4'h2;\t// @[Metadata.scala:61:10]\n wire [3:0] _s2_new_hit_state_r_T_4 = 4'h2;\t// @[Metadata.scala:61:10]\n wire [3:0] _s2_has_permission_r_T_2 = 4'h3;\t// @[Metadata.scala:60:10]\n wire [3:0] _s2_new_hit_state_r_T_2 = 4'h3;\t// @[Metadata.scala:60:10]\n wire [27:0] _metaReadArb_io_in_5_bits_req_0_idx_T = 28'h0;\t// @[dcache.scala:573:74]\n wire [1:0] mshr_read_req_0_uop_dst_rtype = 2'h2;\t// @[dcache.scala:517:27]\n wire [1:0] mshr_read_req_0_uop_uop_dst_rtype = 2'h2;\t// @[consts.scala:269:19]\n wire [1:0] wb_req_0_uop_dst_rtype = 2'h2;\t// @[dcache.scala:532:20]\n wire [1:0] wb_req_0_uop_uop_dst_rtype = 2'h2;\t// @[consts.scala:269:19]\n wire [1:0] prober_req_0_uop_dst_rtype = 2'h2;\t// @[dcache.scala:553:26]\n wire [1:0] prober_req_0_uop_uop_dst_rtype = 2'h2;\t// @[consts.scala:269:19]\n wire [1:0] _s2_has_permission_r_T_7 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _s2_has_permission_r_T_9 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _s2_has_permission_r_T_17 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _s2_has_permission_r_T_19 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _s2_new_hit_state_r_T_7 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _s2_new_hit_state_r_T_9 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _s2_new_hit_state_r_T_17 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _s2_new_hit_state_r_T_19 = 2'h1;\t// @[Metadata.scala:25:15]\n wire [1:0] _dataWriteArb_io_in_0_bits_wmask_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _dataReadArb_io_in_2_bits_req_0_way_en_T = 2'h3;\t// @[dcache.scala:491:48]\n wire [1:0] _s2_has_permission_r_T_11 = 2'h3;\t// @[Metadata.scala:24:15]\n wire [1:0] _s2_has_permission_r_T_13 = 2'h3;\t// @[Metadata.scala:24:15]\n wire [1:0] _s2_has_permission_r_T_21 = 2'h3;\t// @[Metadata.scala:24:15]\n wire [1:0] _s2_has_permission_r_T_23 = 2'h3;\t// @[Metadata.scala:24:15]\n wire [1:0] _s2_new_hit_state_r_T_11 = 2'h3;\t// @[Metadata.scala:24:15]\n wire [1:0] _s2_new_hit_state_r_T_13 = 2'h3;\t// @[Metadata.scala:24:15]\n wire [1:0] _s2_new_hit_state_r_T_21 = 2'h3;\t// @[Metadata.scala:24:15]\n wire [1:0] _s2_new_hit_state_r_T_23 = 2'h3;\t// @[Metadata.scala:24:15]\n wire nodeOut_a_ready = auto_out_a_ready_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_ready;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_valid = auto_out_b_valid_0;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_b_bits_source = auto_out_b_bits_source_0;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_ready = auto_out_c_ready_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_bits_size;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_bits_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_bits_data;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_valid = auto_out_d_valid_0;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_e_ready = auto_out_e_ready_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_e_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_bits_sink;\t// @[MixedNode.scala:542:17]\n wire _io_lsu_req_ready_T;\t// @[dcache.scala:480:50]\n wire _s0_valid_WIRE_0 = io_lsu_req_bits_0_valid_0;\t// @[dcache.scala:413:7, :579:46]\n wire [6:0] _s0_req_WIRE_0_uop_uopc = io_lsu_req_bits_0_bits_uop_uopc_0;\t// @[dcache.scala:413:7, :582:54]\n wire [31:0] _s0_req_WIRE_0_uop_inst = io_lsu_req_bits_0_bits_uop_inst_0;\t// @[dcache.scala:413:7, :582:54]\n wire [31:0] _s0_req_WIRE_0_uop_debug_inst = io_lsu_req_bits_0_bits_uop_debug_inst_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_rvc = io_lsu_req_bits_0_bits_uop_is_rvc_0;\t// @[dcache.scala:413:7, :582:54]\n wire [33:0] _s0_req_WIRE_0_uop_debug_pc = io_lsu_req_bits_0_bits_uop_debug_pc_0;\t// @[dcache.scala:413:7, :582:54]\n wire [2:0] _s0_req_WIRE_0_uop_iq_type = io_lsu_req_bits_0_bits_uop_iq_type_0;\t// @[dcache.scala:413:7, :582:54]\n wire [9:0] _s0_req_WIRE_0_uop_fu_code = io_lsu_req_bits_0_bits_uop_fu_code_0;\t// @[dcache.scala:413:7, :582:54]\n wire [3:0] _s0_req_WIRE_0_uop_ctrl_br_type = io_lsu_req_bits_0_bits_uop_ctrl_br_type_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_ctrl_op1_sel = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0;\t// @[dcache.scala:413:7, :582:54]\n wire [2:0] _s0_req_WIRE_0_uop_ctrl_op2_sel = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0;\t// @[dcache.scala:413:7, :582:54]\n wire [2:0] _s0_req_WIRE_0_uop_ctrl_imm_sel = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0;\t// @[dcache.scala:413:7, :582:54]\n wire [4:0] _s0_req_WIRE_0_uop_ctrl_op_fcn = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_ctrl_fcn_dw = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0;\t// @[dcache.scala:413:7, :582:54]\n wire [2:0] _s0_req_WIRE_0_uop_ctrl_csr_cmd = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_ctrl_is_load = io_lsu_req_bits_0_bits_uop_ctrl_is_load_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_ctrl_is_sta = io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_ctrl_is_std = io_lsu_req_bits_0_bits_uop_ctrl_is_std_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_iw_state = io_lsu_req_bits_0_bits_uop_iw_state_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_iw_p1_poisoned = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_iw_p2_poisoned = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_br = io_lsu_req_bits_0_bits_uop_is_br_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_jalr = io_lsu_req_bits_0_bits_uop_is_jalr_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_jal = io_lsu_req_bits_0_bits_uop_is_jal_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_sfb = io_lsu_req_bits_0_bits_uop_is_sfb_0;\t// @[dcache.scala:413:7, :582:54]\n wire [3:0] _s0_req_WIRE_0_uop_br_mask = io_lsu_req_bits_0_bits_uop_br_mask_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_br_tag = io_lsu_req_bits_0_bits_uop_br_tag_0;\t// @[dcache.scala:413:7, :582:54]\n wire [3:0] _s0_req_WIRE_0_uop_ftq_idx = io_lsu_req_bits_0_bits_uop_ftq_idx_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_edge_inst = io_lsu_req_bits_0_bits_uop_edge_inst_0;\t// @[dcache.scala:413:7, :582:54]\n wire [5:0] _s0_req_WIRE_0_uop_pc_lob = io_lsu_req_bits_0_bits_uop_pc_lob_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_taken = io_lsu_req_bits_0_bits_uop_taken_0;\t// @[dcache.scala:413:7, :582:54]\n wire [19:0] _s0_req_WIRE_0_uop_imm_packed = io_lsu_req_bits_0_bits_uop_imm_packed_0;\t// @[dcache.scala:413:7, :582:54]\n wire [11:0] _s0_req_WIRE_0_uop_csr_addr = io_lsu_req_bits_0_bits_uop_csr_addr_0;\t// @[dcache.scala:413:7, :582:54]\n wire [5:0] _s0_req_WIRE_0_uop_rob_idx = io_lsu_req_bits_0_bits_uop_rob_idx_0;\t// @[dcache.scala:413:7, :582:54]\n wire [3:0] _s0_req_WIRE_0_uop_ldq_idx = io_lsu_req_bits_0_bits_uop_ldq_idx_0;\t// @[dcache.scala:413:7, :582:54]\n wire [3:0] _s0_req_WIRE_0_uop_stq_idx = io_lsu_req_bits_0_bits_uop_stq_idx_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_rxq_idx = io_lsu_req_bits_0_bits_uop_rxq_idx_0;\t// @[dcache.scala:413:7, :582:54]\n wire [6:0] _s0_req_WIRE_0_uop_pdst = io_lsu_req_bits_0_bits_uop_pdst_0;\t// @[dcache.scala:413:7, :582:54]\n wire [6:0] _s0_req_WIRE_0_uop_prs1 = io_lsu_req_bits_0_bits_uop_prs1_0;\t// @[dcache.scala:413:7, :582:54]\n wire [6:0] _s0_req_WIRE_0_uop_prs2 = io_lsu_req_bits_0_bits_uop_prs2_0;\t// @[dcache.scala:413:7, :582:54]\n wire [6:0] _s0_req_WIRE_0_uop_prs3 = io_lsu_req_bits_0_bits_uop_prs3_0;\t// @[dcache.scala:413:7, :582:54]\n wire [3:0] _s0_req_WIRE_0_uop_ppred = io_lsu_req_bits_0_bits_uop_ppred_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_prs1_busy = io_lsu_req_bits_0_bits_uop_prs1_busy_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_prs2_busy = io_lsu_req_bits_0_bits_uop_prs2_busy_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_prs3_busy = io_lsu_req_bits_0_bits_uop_prs3_busy_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_ppred_busy = io_lsu_req_bits_0_bits_uop_ppred_busy_0;\t// @[dcache.scala:413:7, :582:54]\n wire [6:0] _s0_req_WIRE_0_uop_stale_pdst = io_lsu_req_bits_0_bits_uop_stale_pdst_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_exception = io_lsu_req_bits_0_bits_uop_exception_0;\t// @[dcache.scala:413:7, :582:54]\n wire [63:0] _s0_req_WIRE_0_uop_exc_cause = io_lsu_req_bits_0_bits_uop_exc_cause_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_bypassable = io_lsu_req_bits_0_bits_uop_bypassable_0;\t// @[dcache.scala:413:7, :582:54]\n wire [4:0] _s0_req_WIRE_0_uop_mem_cmd = io_lsu_req_bits_0_bits_uop_mem_cmd_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_mem_size = io_lsu_req_bits_0_bits_uop_mem_size_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_mem_signed = io_lsu_req_bits_0_bits_uop_mem_signed_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_fence = io_lsu_req_bits_0_bits_uop_is_fence_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_fencei = io_lsu_req_bits_0_bits_uop_is_fencei_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_amo = io_lsu_req_bits_0_bits_uop_is_amo_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_uses_ldq = io_lsu_req_bits_0_bits_uop_uses_ldq_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_uses_stq = io_lsu_req_bits_0_bits_uop_uses_stq_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_sys_pc2epc = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_is_unique = io_lsu_req_bits_0_bits_uop_is_unique_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_flush_on_commit = io_lsu_req_bits_0_bits_uop_flush_on_commit_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_ldst_is_rs1 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0;\t// @[dcache.scala:413:7, :582:54]\n wire [5:0] _s0_req_WIRE_0_uop_ldst = io_lsu_req_bits_0_bits_uop_ldst_0;\t// @[dcache.scala:413:7, :582:54]\n wire [5:0] _s0_req_WIRE_0_uop_lrs1 = io_lsu_req_bits_0_bits_uop_lrs1_0;\t// @[dcache.scala:413:7, :582:54]\n wire [5:0] _s0_req_WIRE_0_uop_lrs2 = io_lsu_req_bits_0_bits_uop_lrs2_0;\t// @[dcache.scala:413:7, :582:54]\n wire [5:0] _s0_req_WIRE_0_uop_lrs3 = io_lsu_req_bits_0_bits_uop_lrs3_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_ldst_val = io_lsu_req_bits_0_bits_uop_ldst_val_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_dst_rtype = io_lsu_req_bits_0_bits_uop_dst_rtype_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_lrs1_rtype = io_lsu_req_bits_0_bits_uop_lrs1_rtype_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_lrs2_rtype = io_lsu_req_bits_0_bits_uop_lrs2_rtype_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_frs3_en = io_lsu_req_bits_0_bits_uop_frs3_en_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_fp_val = io_lsu_req_bits_0_bits_uop_fp_val_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_fp_single = io_lsu_req_bits_0_bits_uop_fp_single_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_xcpt_pf_if = io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_xcpt_ae_if = io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_xcpt_ma_if = io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_bp_debug_if = io_lsu_req_bits_0_bits_uop_bp_debug_if_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_uop_bp_xcpt_if = io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_debug_fsrc = io_lsu_req_bits_0_bits_uop_debug_fsrc_0;\t// @[dcache.scala:413:7, :582:54]\n wire [1:0] _s0_req_WIRE_0_uop_debug_tsrc = io_lsu_req_bits_0_bits_uop_debug_tsrc_0;\t// @[dcache.scala:413:7, :582:54]\n wire [33:0] _s0_req_WIRE_0_addr = io_lsu_req_bits_0_bits_addr_0;\t// @[dcache.scala:413:7, :582:54]\n wire [63:0] _s0_req_WIRE_0_data = io_lsu_req_bits_0_bits_data_0;\t// @[dcache.scala:413:7, :582:54]\n wire _s0_req_WIRE_0_is_hella = io_lsu_req_bits_0_bits_is_hella_0;\t// @[dcache.scala:413:7, :582:54]\n wire _io_lsu_resp_0_valid_T_6;\t// @[dcache.scala:858:78]\n wire [6:0] io_lsu_resp_0_bits_out_uop_uopc;\t// @[util.scala:101:23]\n wire [31:0] io_lsu_resp_0_bits_out_uop_inst;\t// @[util.scala:101:23]\n wire [31:0] io_lsu_resp_0_bits_out_uop_debug_inst;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_rvc;\t// @[util.scala:101:23]\n wire [33:0] io_lsu_resp_0_bits_out_uop_debug_pc;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_resp_0_bits_out_uop_iq_type;\t// @[util.scala:101:23]\n wire [9:0] io_lsu_resp_0_bits_out_uop_fu_code;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_resp_0_bits_out_uop_ctrl_br_type;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_ctrl_op1_sel;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_op2_sel;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_imm_sel;\t// @[util.scala:101:23]\n wire [4:0] io_lsu_resp_0_bits_out_uop_ctrl_op_fcn;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_ctrl_is_load;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_ctrl_is_sta;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_ctrl_is_std;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_iw_state;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_iw_p1_poisoned;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_iw_p2_poisoned;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_br;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_jalr;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_jal;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_sfb;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_resp_0_bits_out_uop_br_mask;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_br_tag;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_resp_0_bits_out_uop_ftq_idx;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_edge_inst;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_resp_0_bits_out_uop_pc_lob;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_taken;\t// @[util.scala:101:23]\n wire [19:0] io_lsu_resp_0_bits_out_uop_imm_packed;\t// @[util.scala:101:23]\n wire [11:0] io_lsu_resp_0_bits_out_uop_csr_addr;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_resp_0_bits_out_uop_rob_idx;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_resp_0_bits_out_uop_ldq_idx;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_resp_0_bits_out_uop_stq_idx;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_rxq_idx;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_resp_0_bits_out_uop_pdst;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_resp_0_bits_out_uop_prs1;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_resp_0_bits_out_uop_prs2;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_resp_0_bits_out_uop_prs3;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_resp_0_bits_out_uop_ppred;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_prs1_busy;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_prs2_busy;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_prs3_busy;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_ppred_busy;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_resp_0_bits_out_uop_stale_pdst;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_exception;\t// @[util.scala:101:23]\n wire [63:0] io_lsu_resp_0_bits_out_uop_exc_cause;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_bypassable;\t// @[util.scala:101:23]\n wire [4:0] io_lsu_resp_0_bits_out_uop_mem_cmd;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_mem_size;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_mem_signed;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_fence;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_fencei;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_amo;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_uses_ldq;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_uses_stq;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_sys_pc2epc;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_is_unique;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_flush_on_commit;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_ldst_is_rs1;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_resp_0_bits_out_uop_ldst;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_resp_0_bits_out_uop_lrs1;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_resp_0_bits_out_uop_lrs2;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_resp_0_bits_out_uop_lrs3;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_ldst_val;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_dst_rtype;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_lrs1_rtype;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_lrs2_rtype;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_frs3_en;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_fp_val;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_fp_single;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_xcpt_pf_if;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_xcpt_ae_if;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_xcpt_ma_if;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_bp_debug_if;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_uop_bp_xcpt_if;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_debug_fsrc;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_resp_0_bits_out_uop_debug_tsrc;\t// @[util.scala:101:23]\n wire [63:0] io_lsu_resp_0_bits_out_data;\t// @[util.scala:101:23]\n wire io_lsu_resp_0_bits_out_is_hella;\t// @[util.scala:101:23]\n wire _io_lsu_nack_0_valid_T_7;\t// @[dcache.scala:863:75]\n wire [6:0] io_lsu_nack_0_bits_out_uop_uopc;\t// @[util.scala:101:23]\n wire [31:0] io_lsu_nack_0_bits_out_uop_inst;\t// @[util.scala:101:23]\n wire [31:0] io_lsu_nack_0_bits_out_uop_debug_inst;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_rvc;\t// @[util.scala:101:23]\n wire [33:0] io_lsu_nack_0_bits_out_uop_debug_pc;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_nack_0_bits_out_uop_iq_type;\t// @[util.scala:101:23]\n wire [9:0] io_lsu_nack_0_bits_out_uop_fu_code;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_nack_0_bits_out_uop_ctrl_br_type;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_ctrl_op1_sel;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_op2_sel;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_imm_sel;\t// @[util.scala:101:23]\n wire [4:0] io_lsu_nack_0_bits_out_uop_ctrl_op_fcn;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw;\t// @[util.scala:101:23]\n wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_ctrl_is_load;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_ctrl_is_sta;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_ctrl_is_std;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_iw_state;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_iw_p1_poisoned;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_iw_p2_poisoned;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_br;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_jalr;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_jal;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_sfb;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_nack_0_bits_out_uop_br_mask;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_br_tag;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_nack_0_bits_out_uop_ftq_idx;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_edge_inst;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_nack_0_bits_out_uop_pc_lob;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_taken;\t// @[util.scala:101:23]\n wire [19:0] io_lsu_nack_0_bits_out_uop_imm_packed;\t// @[util.scala:101:23]\n wire [11:0] io_lsu_nack_0_bits_out_uop_csr_addr;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_nack_0_bits_out_uop_rob_idx;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_nack_0_bits_out_uop_ldq_idx;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_nack_0_bits_out_uop_stq_idx;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_rxq_idx;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_nack_0_bits_out_uop_pdst;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_nack_0_bits_out_uop_prs1;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_nack_0_bits_out_uop_prs2;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_nack_0_bits_out_uop_prs3;\t// @[util.scala:101:23]\n wire [3:0] io_lsu_nack_0_bits_out_uop_ppred;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_prs1_busy;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_prs2_busy;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_prs3_busy;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_ppred_busy;\t// @[util.scala:101:23]\n wire [6:0] io_lsu_nack_0_bits_out_uop_stale_pdst;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_exception;\t// @[util.scala:101:23]\n wire [63:0] io_lsu_nack_0_bits_out_uop_exc_cause;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_bypassable;\t// @[util.scala:101:23]\n wire [4:0] io_lsu_nack_0_bits_out_uop_mem_cmd;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_mem_size;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_mem_signed;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_fence;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_fencei;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_amo;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_uses_ldq;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_uses_stq;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_sys_pc2epc;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_is_unique;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_flush_on_commit;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_ldst_is_rs1;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_nack_0_bits_out_uop_ldst;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_nack_0_bits_out_uop_lrs1;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_nack_0_bits_out_uop_lrs2;\t// @[util.scala:101:23]\n wire [5:0] io_lsu_nack_0_bits_out_uop_lrs3;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_ldst_val;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_dst_rtype;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_lrs1_rtype;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_lrs2_rtype;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_frs3_en;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_fp_val;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_fp_single;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_xcpt_pf_if;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_xcpt_ae_if;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_xcpt_ma_if;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_bp_debug_if;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_uop_bp_xcpt_if;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_debug_fsrc;\t// @[util.scala:101:23]\n wire [1:0] io_lsu_nack_0_bits_out_uop_debug_tsrc;\t// @[util.scala:101:23]\n wire [33:0] io_lsu_nack_0_bits_out_addr;\t// @[util.scala:101:23]\n wire [63:0] io_lsu_nack_0_bits_out_data;\t// @[util.scala:101:23]\n wire io_lsu_nack_0_bits_out_is_hella;\t// @[util.scala:101:23]\n wire _io_lsu_ordered_T_3;\t// @[dcache.scala:913:66]\n wire io_lsu_perf_acquire_done;\t// @[Edges.scala:233:22]\n wire io_lsu_perf_release_done;\t// @[Edges.scala:233:22]\n wire [2:0] auto_out_a_bits_opcode_0;\t// @[dcache.scala:413:7]\n wire [2:0] auto_out_a_bits_param_0;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_a_bits_size_0;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_a_bits_source_0;\t// @[dcache.scala:413:7]\n wire [31:0] auto_out_a_bits_address_0;\t// @[dcache.scala:413:7]\n wire [7:0] auto_out_a_bits_mask_0;\t// @[dcache.scala:413:7]\n wire [63:0] auto_out_a_bits_data_0;\t// @[dcache.scala:413:7]\n wire auto_out_a_valid_0;\t// @[dcache.scala:413:7]\n wire auto_out_b_ready_0;\t// @[dcache.scala:413:7]\n wire [2:0] auto_out_c_bits_opcode_0;\t// @[dcache.scala:413:7]\n wire [2:0] auto_out_c_bits_param_0;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_c_bits_size_0;\t// @[dcache.scala:413:7]\n wire [3:0] auto_out_c_bits_source_0;\t// @[dcache.scala:413:7]\n wire [31:0] auto_out_c_bits_address_0;\t// @[dcache.scala:413:7]\n wire [63:0] auto_out_c_bits_data_0;\t// @[dcache.scala:413:7]\n wire auto_out_c_valid_0;\t// @[dcache.scala:413:7]\n wire auto_out_d_ready_0;\t// @[dcache.scala:413:7]\n wire [2:0] auto_out_e_bits_sink_0;\t// @[dcache.scala:413:7]\n wire auto_out_e_valid_0;\t// @[dcache.scala:413:7]\n wire io_lsu_req_ready_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel_0;\t// @[dcache.scala:413:7]\n wire [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_ctrl_is_load_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_ctrl_is_sta_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_ctrl_is_std_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_resp_0_bits_uop_uopc_0;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_resp_0_bits_uop_inst_0;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_resp_0_bits_uop_debug_inst_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_rvc_0;\t// @[dcache.scala:413:7]\n wire [33:0] io_lsu_resp_0_bits_uop_debug_pc_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_resp_0_bits_uop_iq_type_0;\t// @[dcache.scala:413:7]\n wire [9:0] io_lsu_resp_0_bits_uop_fu_code_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_iw_state_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_iw_p1_poisoned_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_iw_p2_poisoned_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_br_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_jalr_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_jal_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_sfb_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_resp_0_bits_uop_br_mask_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_br_tag_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_resp_0_bits_uop_ftq_idx_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_edge_inst_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_resp_0_bits_uop_pc_lob_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_taken_0;\t// @[dcache.scala:413:7]\n wire [19:0] io_lsu_resp_0_bits_uop_imm_packed_0;\t// @[dcache.scala:413:7]\n wire [11:0] io_lsu_resp_0_bits_uop_csr_addr_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_resp_0_bits_uop_rob_idx_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_resp_0_bits_uop_ldq_idx_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_resp_0_bits_uop_stq_idx_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_rxq_idx_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_resp_0_bits_uop_pdst_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_resp_0_bits_uop_prs1_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_resp_0_bits_uop_prs2_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_resp_0_bits_uop_prs3_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_resp_0_bits_uop_ppred_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_prs1_busy_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_prs2_busy_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_prs3_busy_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_ppred_busy_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_resp_0_bits_uop_stale_pdst_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_exception_0;\t// @[dcache.scala:413:7]\n wire [63:0] io_lsu_resp_0_bits_uop_exc_cause_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_bypassable_0;\t// @[dcache.scala:413:7]\n wire [4:0] io_lsu_resp_0_bits_uop_mem_cmd_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_mem_size_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_mem_signed_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_fence_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_fencei_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_amo_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_uses_ldq_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_uses_stq_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_sys_pc2epc_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_is_unique_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_flush_on_commit_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_ldst_is_rs1_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_resp_0_bits_uop_ldst_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_resp_0_bits_uop_lrs1_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_resp_0_bits_uop_lrs2_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_resp_0_bits_uop_lrs3_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_ldst_val_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_dst_rtype_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_frs3_en_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_fp_val_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_fp_single_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_xcpt_pf_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_xcpt_ae_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_xcpt_ma_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_bp_debug_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_uop_bp_xcpt_if_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_debug_fsrc_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_resp_0_bits_uop_debug_tsrc_0;\t// @[dcache.scala:413:7]\n wire [63:0] io_lsu_resp_0_bits_data_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_bits_is_hella_0;\t// @[dcache.scala:413:7]\n wire io_lsu_resp_0_valid_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel_0;\t// @[dcache.scala:413:7]\n wire [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_ctrl_is_load_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_ctrl_is_sta_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_ctrl_is_std_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_nack_0_bits_uop_uopc_0;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_nack_0_bits_uop_inst_0;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_nack_0_bits_uop_debug_inst_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_rvc_0;\t// @[dcache.scala:413:7]\n wire [33:0] io_lsu_nack_0_bits_uop_debug_pc_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_nack_0_bits_uop_iq_type_0;\t// @[dcache.scala:413:7]\n wire [9:0] io_lsu_nack_0_bits_uop_fu_code_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_iw_state_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_iw_p1_poisoned_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_iw_p2_poisoned_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_br_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_jalr_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_jal_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_sfb_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_nack_0_bits_uop_br_mask_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_br_tag_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_nack_0_bits_uop_ftq_idx_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_edge_inst_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_nack_0_bits_uop_pc_lob_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_taken_0;\t// @[dcache.scala:413:7]\n wire [19:0] io_lsu_nack_0_bits_uop_imm_packed_0;\t// @[dcache.scala:413:7]\n wire [11:0] io_lsu_nack_0_bits_uop_csr_addr_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_nack_0_bits_uop_rob_idx_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_nack_0_bits_uop_ldq_idx_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_nack_0_bits_uop_stq_idx_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_rxq_idx_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_nack_0_bits_uop_pdst_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_nack_0_bits_uop_prs1_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_nack_0_bits_uop_prs2_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_nack_0_bits_uop_prs3_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_nack_0_bits_uop_ppred_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_prs1_busy_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_prs2_busy_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_prs3_busy_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_ppred_busy_0;\t// @[dcache.scala:413:7]\n wire [6:0] io_lsu_nack_0_bits_uop_stale_pdst_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_exception_0;\t// @[dcache.scala:413:7]\n wire [63:0] io_lsu_nack_0_bits_uop_exc_cause_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_bypassable_0;\t// @[dcache.scala:413:7]\n wire [4:0] io_lsu_nack_0_bits_uop_mem_cmd_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_mem_size_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_mem_signed_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_fence_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_fencei_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_amo_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_uses_ldq_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_uses_stq_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_sys_pc2epc_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_is_unique_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_flush_on_commit_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_ldst_is_rs1_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_nack_0_bits_uop_ldst_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_nack_0_bits_uop_lrs1_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_nack_0_bits_uop_lrs2_0;\t// @[dcache.scala:413:7]\n wire [5:0] io_lsu_nack_0_bits_uop_lrs3_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_ldst_val_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_dst_rtype_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_frs3_en_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_fp_val_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_fp_single_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_xcpt_pf_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_xcpt_ae_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_xcpt_ma_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_bp_debug_if_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_uop_bp_xcpt_if_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_debug_fsrc_0;\t// @[dcache.scala:413:7]\n wire [1:0] io_lsu_nack_0_bits_uop_debug_tsrc_0;\t// @[dcache.scala:413:7]\n wire [33:0] io_lsu_nack_0_bits_addr_0;\t// @[dcache.scala:413:7]\n wire [63:0] io_lsu_nack_0_bits_data_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_bits_is_hella_0;\t// @[dcache.scala:413:7]\n wire io_lsu_nack_0_valid_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_release_bits_opcode_0;\t// @[dcache.scala:413:7]\n wire [2:0] io_lsu_release_bits_param_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_release_bits_size_0;\t// @[dcache.scala:413:7]\n wire [3:0] io_lsu_release_bits_source_0;\t// @[dcache.scala:413:7]\n wire [31:0] io_lsu_release_bits_address_0;\t// @[dcache.scala:413:7]\n wire [63:0] io_lsu_release_bits_data_0;\t// @[dcache.scala:413:7]\n wire io_lsu_release_valid_0;\t// @[dcache.scala:413:7]\n wire io_lsu_perf_acquire_0;\t// @[dcache.scala:413:7]\n wire io_lsu_perf_release_0;\t// @[dcache.scala:413:7]\n wire io_lsu_ordered_0;\t// @[dcache.scala:413:7]\n assign auto_out_a_valid_0 = nodeOut_a_valid;\t// @[MixedNode.scala:542:17]\n assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n assign auto_out_a_bits_param_0 = nodeOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n assign auto_out_a_bits_size_0 = nodeOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n assign auto_out_a_bits_source_0 = nodeOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n assign auto_out_a_bits_address_0 = nodeOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n assign auto_out_a_bits_data_0 = nodeOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire _nodeOut_b_ready_T_1;\t// @[dcache.scala:779:48]\n assign auto_out_b_ready_0 = nodeOut_b_ready;\t// @[MixedNode.scala:542:17]\n wire _nodeOut_c_valid_T_4;\t// @[Arbiter.scala:96:24]\n assign auto_out_c_valid_0 = nodeOut_c_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] _nodeOut_c_bits_WIRE_opcode;\t// @[Mux.scala:30:73]\n assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] _nodeOut_c_bits_WIRE_param;\t// @[Mux.scala:30:73]\n assign auto_out_c_bits_param_0 = nodeOut_c_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] _nodeOut_c_bits_WIRE_size;\t// @[Mux.scala:30:73]\n assign auto_out_c_bits_size_0 = nodeOut_c_bits_size;\t// @[MixedNode.scala:542:17]\n wire [3:0] _nodeOut_c_bits_WIRE_source;\t// @[Mux.scala:30:73]\n assign auto_out_c_bits_source_0 = nodeOut_c_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] _nodeOut_c_bits_WIRE_address;\t// @[Mux.scala:30:73]\n assign auto_out_c_bits_address_0 = nodeOut_c_bits_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] _nodeOut_c_bits_WIRE_data;\t// @[Mux.scala:30:73]\n assign auto_out_c_bits_data_0 = nodeOut_c_bits_data;\t// @[MixedNode.scala:542:17]\n assign auto_out_d_ready_0 = nodeOut_d_ready;\t// @[MixedNode.scala:542:17]\n assign auto_out_e_valid_0 = nodeOut_e_valid;\t// @[MixedNode.scala:542:17]\n assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink;\t// @[MixedNode.scala:542:17]\n wire _meta_0_io_write_valid_T = _meta_0_io_write_ready & _metaWriteArb_io_out_valid;\t// @[Decoupled.scala:51:35]\n wire _data_io_read_0_valid_T = _dataReadArb_io_out_bits_valid_0 & _dataReadArb_io_out_valid;\t// @[dcache.scala:463:27, :468:63]\n assign _io_lsu_req_ready_T = _metaReadArb_io_in_4_ready & _dataReadArb_io_in_2_ready;\t// @[dcache.scala:445:27, :463:27, :480:50]\n assign io_lsu_req_ready_0 = _io_lsu_req_ready_T;\t// @[dcache.scala:413:7, :480:50]\n wire [27:0] _metaReadArb_io_in_4_bits_req_0_idx_T = io_lsu_req_bits_0_bits_addr_0[33:6];\t// @[dcache.scala:413:7, :485:77]\n wire [3:0] replay_req_0_uop_ctrl_br_type;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_ctrl_op1_sel;\t// @[dcache.scala:496:24]\n wire [2:0] replay_req_0_uop_ctrl_op2_sel;\t// @[dcache.scala:496:24]\n wire [2:0] replay_req_0_uop_ctrl_imm_sel;\t// @[dcache.scala:496:24]\n wire [4:0] replay_req_0_uop_ctrl_op_fcn;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_ctrl_fcn_dw;\t// @[dcache.scala:496:24]\n wire [2:0] replay_req_0_uop_ctrl_csr_cmd;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_ctrl_is_load;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_ctrl_is_sta;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_ctrl_is_std;\t// @[dcache.scala:496:24]\n wire [6:0] replay_req_0_uop_uopc;\t// @[dcache.scala:496:24]\n wire [31:0] replay_req_0_uop_inst;\t// @[dcache.scala:496:24]\n wire [31:0] replay_req_0_uop_debug_inst;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_rvc;\t// @[dcache.scala:496:24]\n wire [33:0] replay_req_0_uop_debug_pc;\t// @[dcache.scala:496:24]\n wire [2:0] replay_req_0_uop_iq_type;\t// @[dcache.scala:496:24]\n wire [9:0] replay_req_0_uop_fu_code;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_iw_state;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_iw_p1_poisoned;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_iw_p2_poisoned;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_br;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_jalr;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_jal;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_sfb;\t// @[dcache.scala:496:24]\n wire [3:0] replay_req_0_uop_br_mask;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_br_tag;\t// @[dcache.scala:496:24]\n wire [3:0] replay_req_0_uop_ftq_idx;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_edge_inst;\t// @[dcache.scala:496:24]\n wire [5:0] replay_req_0_uop_pc_lob;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_taken;\t// @[dcache.scala:496:24]\n wire [19:0] replay_req_0_uop_imm_packed;\t// @[dcache.scala:496:24]\n wire [11:0] replay_req_0_uop_csr_addr;\t// @[dcache.scala:496:24]\n wire [5:0] replay_req_0_uop_rob_idx;\t// @[dcache.scala:496:24]\n wire [3:0] replay_req_0_uop_ldq_idx;\t// @[dcache.scala:496:24]\n wire [3:0] replay_req_0_uop_stq_idx;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_rxq_idx;\t// @[dcache.scala:496:24]\n wire [6:0] replay_req_0_uop_pdst;\t// @[dcache.scala:496:24]\n wire [6:0] replay_req_0_uop_prs1;\t// @[dcache.scala:496:24]\n wire [6:0] replay_req_0_uop_prs2;\t// @[dcache.scala:496:24]\n wire [6:0] replay_req_0_uop_prs3;\t// @[dcache.scala:496:24]\n wire [3:0] replay_req_0_uop_ppred;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_prs1_busy;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_prs2_busy;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_prs3_busy;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_ppred_busy;\t// @[dcache.scala:496:24]\n wire [6:0] replay_req_0_uop_stale_pdst;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_exception;\t// @[dcache.scala:496:24]\n wire [63:0] replay_req_0_uop_exc_cause;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_bypassable;\t// @[dcache.scala:496:24]\n wire [4:0] replay_req_0_uop_mem_cmd;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_mem_size;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_mem_signed;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_fence;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_fencei;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_amo;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_uses_ldq;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_uses_stq;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_sys_pc2epc;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_is_unique;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_flush_on_commit;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_ldst_is_rs1;\t// @[dcache.scala:496:24]\n wire [5:0] replay_req_0_uop_ldst;\t// @[dcache.scala:496:24]\n wire [5:0] replay_req_0_uop_lrs1;\t// @[dcache.scala:496:24]\n wire [5:0] replay_req_0_uop_lrs2;\t// @[dcache.scala:496:24]\n wire [5:0] replay_req_0_uop_lrs3;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_ldst_val;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_dst_rtype;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_lrs1_rtype;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_lrs2_rtype;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_frs3_en;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_fp_val;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_fp_single;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_xcpt_pf_if;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_xcpt_ae_if;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_xcpt_ma_if;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_bp_debug_if;\t// @[dcache.scala:496:24]\n wire replay_req_0_uop_bp_xcpt_if;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_debug_fsrc;\t// @[dcache.scala:496:24]\n wire [1:0] replay_req_0_uop_debug_tsrc;\t// @[dcache.scala:496:24]\n wire [33:0] replay_req_0_addr;\t// @[dcache.scala:496:24]\n wire [63:0] replay_req_0_data;\t// @[dcache.scala:496:24]\n wire replay_req_0_is_hella;\t// @[dcache.scala:496:24]\n wire [27:0] _metaReadArb_io_in_0_bits_req_0_idx_T = _mshrs_io_replay_bits_addr[33:6];\t// @[dcache.scala:433:21, :506:72]\n wire [33:0] mshr_read_req_0_addr;\t// @[dcache.scala:517:27]\n wire [25:0] _mshr_read_req_0_addr_T = {_mshrs_io_meta_read_bits_tag, _mshrs_io_meta_read_bits_idx};\t// @[dcache.scala:433:21, :520:35]\n wire [31:0] _mshr_read_req_0_addr_T_1 = {_mshr_read_req_0_addr_T, 6'h0};\t// @[dcache.scala:520:{35,94}]\n assign mshr_read_req_0_addr = {2'h0, _mshr_read_req_0_addr_T_1};\t// @[dcache.scala:517:27, :520:{29,94}]\n wire _wb_io_meta_read_ready_T;\t// @[dcache.scala:542:55]\n wire _wb_fire_T = _wb_io_meta_read_ready_T & _wb_io_meta_read_valid;\t// @[Decoupled.scala:51:35]\n wire _wb_io_data_req_ready_T;\t// @[dcache.scala:547:55]\n wire _wb_fire_T_1 = _wb_io_data_req_ready_T & _wb_io_data_req_valid;\t// @[Decoupled.scala:51:35]\n wire wb_fire = _wb_fire_T & _wb_fire_T_1;\t// @[Decoupled.scala:51:35]\n wire [33:0] wb_req_0_addr;\t// @[dcache.scala:532:20]\n wire [31:0] _wb_req_0_addr_T = {_wb_io_meta_read_bits_tag, _wb_io_data_req_bits_addr};\t// @[dcache.scala:431:18, :535:28]\n assign wb_req_0_addr = {2'h0, _wb_req_0_addr_T};\t// @[dcache.scala:532:20, :535:{22,28}]\n wire _GEN = _metaReadArb_io_in_2_ready & _dataReadArb_io_in_1_ready;\t// @[dcache.scala:445:27, :463:27, :542:55]\n assign _wb_io_meta_read_ready_T = _GEN;\t// @[dcache.scala:542:55]\n assign _wb_io_data_req_ready_T = _GEN;\t// @[dcache.scala:542:55, :547:55]\n wire prober_fire = _metaReadArb_io_in_1_ready & _prober_io_meta_read_valid;\t// @[Decoupled.scala:51:35]\n wire [33:0] prober_req_0_addr;\t// @[dcache.scala:553:26]\n wire [25:0] _prober_req_0_addr_T = {_prober_io_meta_read_bits_tag, _prober_io_meta_read_bits_idx};\t// @[dcache.scala:432:22, :556:32]\n wire [31:0] _prober_req_0_addr_T_1 = {_prober_req_0_addr_T, 6'h0};\t// @[dcache.scala:556:{32,93}]\n assign prober_req_0_addr = {2'h0, _prober_req_0_addr_T_1};\t// @[dcache.scala:553:26, :556:{26,93}]\n wire _T_7 = io_lsu_req_ready_0 & io_lsu_req_valid_0;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T;\t// @[Decoupled.scala:51:35]\n assign _s0_valid_T = _T_7;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T;\t// @[Decoupled.scala:51:35]\n assign _s0_req_T = _T_7;\t// @[Decoupled.scala:51:35]\n wire _s0_type_T;\t// @[Decoupled.scala:51:35]\n assign _s0_type_T = _T_7;\t// @[Decoupled.scala:51:35]\n wire _s0_send_resp_or_nack_T;\t// @[Decoupled.scala:51:35]\n assign _s0_send_resp_or_nack_T = _T_7;\t// @[Decoupled.scala:51:35]\n wire _s1_valid_T_7;\t// @[Decoupled.scala:51:35]\n assign _s1_valid_T_7 = _T_7;\t// @[Decoupled.scala:51:35]\n wire _mshrs_io_replay_ready_T;\t// @[dcache.scala:502:58]\n wire _GEN_0 = _mshrs_io_replay_ready_T & _mshrs_io_replay_valid;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T_1;\t// @[Decoupled.scala:51:35]\n assign _s0_valid_T_1 = _GEN_0;\t// @[Decoupled.scala:51:35]\n wire _s0_send_resp_or_nack_T_1;\t// @[Decoupled.scala:51:35]\n assign _s0_send_resp_or_nack_T_1 = _GEN_0;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T_2 = _s0_valid_T_1 | wb_fire;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T_3 = _s0_valid_T_2 | prober_fire;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T_4 = _s0_valid_T_3;\t// @[dcache.scala:580:{54,69}]\n wire _GEN_1 = _metaReadArb_io_in_3_ready & _mshrs_io_meta_read_valid;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T_5;\t// @[Decoupled.scala:51:35]\n assign _s0_valid_T_5 = _GEN_1;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_1;\t// @[Decoupled.scala:51:35]\n assign _s0_req_T_1 = _GEN_1;\t// @[Decoupled.scala:51:35]\n wire _s0_type_T_1;\t// @[Decoupled.scala:51:35]\n assign _s0_type_T_1 = _GEN_1;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T_6 = _s0_valid_T_4 | _s0_valid_T_5;\t// @[Decoupled.scala:51:35]\n wire _s0_valid_T_7_0 = _s0_valid_T_6;\t// @[dcache.scala:580:{21,86}]\n wire s0_valid_0 = _s0_valid_T ? _s0_valid_WIRE_0 : _s0_valid_T_7_0;\t// @[Decoupled.scala:51:35]\n wire _s1_valid_T_3 = s0_valid_0;\t// @[dcache.scala:579:21, :605:74]\n wire [6:0] _s0_req_T_2_0_uop_uopc = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_uopc;\t// @[Decoupled.scala:51:35]\n wire [31:0] _s0_req_T_2_0_uop_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_inst;\t// @[Decoupled.scala:51:35]\n wire [31:0] _s0_req_T_2_0_uop_debug_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_debug_inst;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_rvc = ~_s0_req_T_1 & replay_req_0_uop_is_rvc;\t// @[Decoupled.scala:51:35]\n wire [33:0] _s0_req_T_2_0_uop_debug_pc = _s0_req_T_1 ? 34'h0 : replay_req_0_uop_debug_pc;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_2_0_uop_iq_type = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_iq_type;\t// @[Decoupled.scala:51:35]\n wire [9:0] _s0_req_T_2_0_uop_fu_code = _s0_req_T_1 ? 10'h0 : replay_req_0_uop_fu_code;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_2_0_uop_ctrl_br_type = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ctrl_br_type;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_ctrl_op1_sel = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_ctrl_op1_sel;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_2_0_uop_ctrl_op2_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_op2_sel;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_2_0_uop_ctrl_imm_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_imm_sel;\t// @[Decoupled.scala:51:35]\n wire [4:0] _s0_req_T_2_0_uop_ctrl_op_fcn = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ctrl_op_fcn;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_ctrl_fcn_dw = ~_s0_req_T_1 & replay_req_0_uop_ctrl_fcn_dw;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_2_0_uop_ctrl_csr_cmd = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_csr_cmd;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_ctrl_is_load = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_load;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_ctrl_is_sta = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_sta;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_ctrl_is_std = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_std;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_iw_state = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_iw_state;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_iw_p1_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p1_poisoned;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_iw_p2_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p2_poisoned;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_br = ~_s0_req_T_1 & replay_req_0_uop_is_br;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_jalr = ~_s0_req_T_1 & replay_req_0_uop_is_jalr;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_jal = ~_s0_req_T_1 & replay_req_0_uop_is_jal;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_sfb = ~_s0_req_T_1 & replay_req_0_uop_is_sfb;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_2_0_uop_br_mask = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_br_mask;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_br_tag = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_br_tag;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_2_0_uop_ftq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ftq_idx;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_edge_inst = ~_s0_req_T_1 & replay_req_0_uop_edge_inst;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_2_0_uop_pc_lob = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_pc_lob;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_taken = ~_s0_req_T_1 & replay_req_0_uop_taken;\t// @[Decoupled.scala:51:35]\n wire [19:0] _s0_req_T_2_0_uop_imm_packed = _s0_req_T_1 ? 20'h0 : replay_req_0_uop_imm_packed;\t// @[Decoupled.scala:51:35]\n wire [11:0] _s0_req_T_2_0_uop_csr_addr = _s0_req_T_1 ? 12'h0 : replay_req_0_uop_csr_addr;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_2_0_uop_rob_idx = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_rob_idx;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_2_0_uop_ldq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ldq_idx;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_2_0_uop_stq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_stq_idx;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_rxq_idx = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_rxq_idx;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_2_0_uop_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_pdst;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_2_0_uop_prs1 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs1;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_2_0_uop_prs2 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs2;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_2_0_uop_prs3 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs3;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_2_0_uop_ppred = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ppred;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_prs1_busy = ~_s0_req_T_1 & replay_req_0_uop_prs1_busy;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_prs2_busy = ~_s0_req_T_1 & replay_req_0_uop_prs2_busy;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_prs3_busy = ~_s0_req_T_1 & replay_req_0_uop_prs3_busy;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_ppred_busy = ~_s0_req_T_1 & replay_req_0_uop_ppred_busy;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_2_0_uop_stale_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_stale_pdst;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_exception = ~_s0_req_T_1 & replay_req_0_uop_exception;\t// @[Decoupled.scala:51:35]\n wire [63:0] _s0_req_T_2_0_uop_exc_cause = _s0_req_T_1 ? 64'h0 : replay_req_0_uop_exc_cause;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_bypassable = ~_s0_req_T_1 & replay_req_0_uop_bypassable;\t// @[Decoupled.scala:51:35]\n wire [4:0] _s0_req_T_2_0_uop_mem_cmd = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_mem_cmd;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_mem_size = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_mem_size;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_mem_signed = ~_s0_req_T_1 & replay_req_0_uop_mem_signed;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_fence = ~_s0_req_T_1 & replay_req_0_uop_is_fence;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_fencei = ~_s0_req_T_1 & replay_req_0_uop_is_fencei;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_amo = ~_s0_req_T_1 & replay_req_0_uop_is_amo;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_uses_ldq = ~_s0_req_T_1 & replay_req_0_uop_uses_ldq;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_uses_stq = ~_s0_req_T_1 & replay_req_0_uop_uses_stq;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_sys_pc2epc = ~_s0_req_T_1 & replay_req_0_uop_is_sys_pc2epc;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_is_unique = ~_s0_req_T_1 & replay_req_0_uop_is_unique;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_flush_on_commit = ~_s0_req_T_1 & replay_req_0_uop_flush_on_commit;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_ldst_is_rs1 = ~_s0_req_T_1 & replay_req_0_uop_ldst_is_rs1;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_2_0_uop_ldst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_ldst;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_2_0_uop_lrs1 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs1;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_2_0_uop_lrs2 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs2;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_2_0_uop_lrs3 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs3;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_ldst_val = ~_s0_req_T_1 & replay_req_0_uop_ldst_val;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_dst_rtype = _s0_req_T_1 ? 2'h2 : replay_req_0_uop_dst_rtype;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_lrs1_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs1_rtype;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_lrs2_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs2_rtype;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_frs3_en = ~_s0_req_T_1 & replay_req_0_uop_frs3_en;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_fp_val = ~_s0_req_T_1 & replay_req_0_uop_fp_val;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_fp_single = ~_s0_req_T_1 & replay_req_0_uop_fp_single;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_xcpt_pf_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_pf_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_xcpt_ae_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ae_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_xcpt_ma_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ma_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_bp_debug_if = ~_s0_req_T_1 & replay_req_0_uop_bp_debug_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_uop_bp_xcpt_if = ~_s0_req_T_1 & replay_req_0_uop_bp_xcpt_if;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_debug_fsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_fsrc;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_2_0_uop_debug_tsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_tsrc;\t// @[Decoupled.scala:51:35]\n wire [33:0] _s0_req_T_2_0_addr = _s0_req_T_1 ? mshr_read_req_0_addr : replay_req_0_addr;\t// @[Decoupled.scala:51:35]\n wire [63:0] _s0_req_T_2_0_data = _s0_req_T_1 ? 64'h0 : replay_req_0_data;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_2_0_is_hella = ~_s0_req_T_1 & replay_req_0_is_hella;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_3_0_uop_uopc = _s0_req_T_2_0_uop_uopc;\t// @[dcache.scala:585:21, :586:21]\n wire [31:0] _s0_req_T_3_0_uop_inst = _s0_req_T_2_0_uop_inst;\t// @[dcache.scala:585:21, :586:21]\n wire [31:0] _s0_req_T_3_0_uop_debug_inst = _s0_req_T_2_0_uop_debug_inst;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_rvc = _s0_req_T_2_0_uop_is_rvc;\t// @[dcache.scala:585:21, :586:21]\n wire [33:0] _s0_req_T_3_0_uop_debug_pc = _s0_req_T_2_0_uop_debug_pc;\t// @[dcache.scala:585:21, :586:21]\n wire [2:0] _s0_req_T_3_0_uop_iq_type = _s0_req_T_2_0_uop_iq_type;\t// @[dcache.scala:585:21, :586:21]\n wire [9:0] _s0_req_T_3_0_uop_fu_code = _s0_req_T_2_0_uop_fu_code;\t// @[dcache.scala:585:21, :586:21]\n wire [3:0] _s0_req_T_3_0_uop_ctrl_br_type = _s0_req_T_2_0_uop_ctrl_br_type;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_ctrl_op1_sel = _s0_req_T_2_0_uop_ctrl_op1_sel;\t// @[dcache.scala:585:21, :586:21]\n wire [2:0] _s0_req_T_3_0_uop_ctrl_op2_sel = _s0_req_T_2_0_uop_ctrl_op2_sel;\t// @[dcache.scala:585:21, :586:21]\n wire [2:0] _s0_req_T_3_0_uop_ctrl_imm_sel = _s0_req_T_2_0_uop_ctrl_imm_sel;\t// @[dcache.scala:585:21, :586:21]\n wire [4:0] _s0_req_T_3_0_uop_ctrl_op_fcn = _s0_req_T_2_0_uop_ctrl_op_fcn;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_ctrl_fcn_dw = _s0_req_T_2_0_uop_ctrl_fcn_dw;\t// @[dcache.scala:585:21, :586:21]\n wire [2:0] _s0_req_T_3_0_uop_ctrl_csr_cmd = _s0_req_T_2_0_uop_ctrl_csr_cmd;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_ctrl_is_load = _s0_req_T_2_0_uop_ctrl_is_load;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_ctrl_is_sta = _s0_req_T_2_0_uop_ctrl_is_sta;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_ctrl_is_std = _s0_req_T_2_0_uop_ctrl_is_std;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_iw_state = _s0_req_T_2_0_uop_iw_state;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_iw_p1_poisoned = _s0_req_T_2_0_uop_iw_p1_poisoned;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_iw_p2_poisoned = _s0_req_T_2_0_uop_iw_p2_poisoned;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_br = _s0_req_T_2_0_uop_is_br;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_jalr = _s0_req_T_2_0_uop_is_jalr;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_jal = _s0_req_T_2_0_uop_is_jal;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_sfb = _s0_req_T_2_0_uop_is_sfb;\t// @[dcache.scala:585:21, :586:21]\n wire [3:0] _s0_req_T_3_0_uop_br_mask = _s0_req_T_2_0_uop_br_mask;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_br_tag = _s0_req_T_2_0_uop_br_tag;\t// @[dcache.scala:585:21, :586:21]\n wire [3:0] _s0_req_T_3_0_uop_ftq_idx = _s0_req_T_2_0_uop_ftq_idx;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_edge_inst = _s0_req_T_2_0_uop_edge_inst;\t// @[dcache.scala:585:21, :586:21]\n wire [5:0] _s0_req_T_3_0_uop_pc_lob = _s0_req_T_2_0_uop_pc_lob;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_taken = _s0_req_T_2_0_uop_taken;\t// @[dcache.scala:585:21, :586:21]\n wire [19:0] _s0_req_T_3_0_uop_imm_packed = _s0_req_T_2_0_uop_imm_packed;\t// @[dcache.scala:585:21, :586:21]\n wire [11:0] _s0_req_T_3_0_uop_csr_addr = _s0_req_T_2_0_uop_csr_addr;\t// @[dcache.scala:585:21, :586:21]\n wire [5:0] _s0_req_T_3_0_uop_rob_idx = _s0_req_T_2_0_uop_rob_idx;\t// @[dcache.scala:585:21, :586:21]\n wire [3:0] _s0_req_T_3_0_uop_ldq_idx = _s0_req_T_2_0_uop_ldq_idx;\t// @[dcache.scala:585:21, :586:21]\n wire [3:0] _s0_req_T_3_0_uop_stq_idx = _s0_req_T_2_0_uop_stq_idx;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_rxq_idx = _s0_req_T_2_0_uop_rxq_idx;\t// @[dcache.scala:585:21, :586:21]\n wire [6:0] _s0_req_T_3_0_uop_pdst = _s0_req_T_2_0_uop_pdst;\t// @[dcache.scala:585:21, :586:21]\n wire [6:0] _s0_req_T_3_0_uop_prs1 = _s0_req_T_2_0_uop_prs1;\t// @[dcache.scala:585:21, :586:21]\n wire [6:0] _s0_req_T_3_0_uop_prs2 = _s0_req_T_2_0_uop_prs2;\t// @[dcache.scala:585:21, :586:21]\n wire [6:0] _s0_req_T_3_0_uop_prs3 = _s0_req_T_2_0_uop_prs3;\t// @[dcache.scala:585:21, :586:21]\n wire [3:0] _s0_req_T_3_0_uop_ppred = _s0_req_T_2_0_uop_ppred;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_prs1_busy = _s0_req_T_2_0_uop_prs1_busy;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_prs2_busy = _s0_req_T_2_0_uop_prs2_busy;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_prs3_busy = _s0_req_T_2_0_uop_prs3_busy;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_ppred_busy = _s0_req_T_2_0_uop_ppred_busy;\t// @[dcache.scala:585:21, :586:21]\n wire [6:0] _s0_req_T_3_0_uop_stale_pdst = _s0_req_T_2_0_uop_stale_pdst;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_exception = _s0_req_T_2_0_uop_exception;\t// @[dcache.scala:585:21, :586:21]\n wire [63:0] _s0_req_T_3_0_uop_exc_cause = _s0_req_T_2_0_uop_exc_cause;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_bypassable = _s0_req_T_2_0_uop_bypassable;\t// @[dcache.scala:585:21, :586:21]\n wire [4:0] _s0_req_T_3_0_uop_mem_cmd = _s0_req_T_2_0_uop_mem_cmd;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_mem_size = _s0_req_T_2_0_uop_mem_size;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_mem_signed = _s0_req_T_2_0_uop_mem_signed;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_fence = _s0_req_T_2_0_uop_is_fence;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_fencei = _s0_req_T_2_0_uop_is_fencei;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_amo = _s0_req_T_2_0_uop_is_amo;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_uses_ldq = _s0_req_T_2_0_uop_uses_ldq;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_uses_stq = _s0_req_T_2_0_uop_uses_stq;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_sys_pc2epc = _s0_req_T_2_0_uop_is_sys_pc2epc;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_is_unique = _s0_req_T_2_0_uop_is_unique;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_flush_on_commit = _s0_req_T_2_0_uop_flush_on_commit;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_ldst_is_rs1 = _s0_req_T_2_0_uop_ldst_is_rs1;\t// @[dcache.scala:585:21, :586:21]\n wire [5:0] _s0_req_T_3_0_uop_ldst = _s0_req_T_2_0_uop_ldst;\t// @[dcache.scala:585:21, :586:21]\n wire [5:0] _s0_req_T_3_0_uop_lrs1 = _s0_req_T_2_0_uop_lrs1;\t// @[dcache.scala:585:21, :586:21]\n wire [5:0] _s0_req_T_3_0_uop_lrs2 = _s0_req_T_2_0_uop_lrs2;\t// @[dcache.scala:585:21, :586:21]\n wire [5:0] _s0_req_T_3_0_uop_lrs3 = _s0_req_T_2_0_uop_lrs3;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_ldst_val = _s0_req_T_2_0_uop_ldst_val;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_dst_rtype = _s0_req_T_2_0_uop_dst_rtype;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_lrs1_rtype = _s0_req_T_2_0_uop_lrs1_rtype;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_lrs2_rtype = _s0_req_T_2_0_uop_lrs2_rtype;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_frs3_en = _s0_req_T_2_0_uop_frs3_en;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_fp_val = _s0_req_T_2_0_uop_fp_val;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_fp_single = _s0_req_T_2_0_uop_fp_single;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_xcpt_pf_if = _s0_req_T_2_0_uop_xcpt_pf_if;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_xcpt_ae_if = _s0_req_T_2_0_uop_xcpt_ae_if;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_xcpt_ma_if = _s0_req_T_2_0_uop_xcpt_ma_if;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_bp_debug_if = _s0_req_T_2_0_uop_bp_debug_if;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_uop_bp_xcpt_if = _s0_req_T_2_0_uop_bp_xcpt_if;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_debug_fsrc = _s0_req_T_2_0_uop_debug_fsrc;\t// @[dcache.scala:585:21, :586:21]\n wire [1:0] _s0_req_T_3_0_uop_debug_tsrc = _s0_req_T_2_0_uop_debug_tsrc;\t// @[dcache.scala:585:21, :586:21]\n wire [33:0] _s0_req_T_3_0_addr = _s0_req_T_2_0_addr;\t// @[dcache.scala:585:21, :586:21]\n wire [63:0] _s0_req_T_3_0_data = _s0_req_T_2_0_data;\t// @[dcache.scala:585:21, :586:21]\n wire _s0_req_T_3_0_is_hella = _s0_req_T_2_0_is_hella;\t// @[dcache.scala:585:21, :586:21]\n wire [6:0] _s0_req_T_4_0_uop_uopc = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_uopc;\t// @[Decoupled.scala:51:35]\n wire [31:0] _s0_req_T_4_0_uop_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_inst;\t// @[Decoupled.scala:51:35]\n wire [31:0] _s0_req_T_4_0_uop_debug_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_debug_inst;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_rvc = ~prober_fire & _s0_req_T_3_0_uop_is_rvc;\t// @[Decoupled.scala:51:35]\n wire [33:0] _s0_req_T_4_0_uop_debug_pc = prober_fire ? 34'h0 : _s0_req_T_3_0_uop_debug_pc;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_4_0_uop_iq_type = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_iq_type;\t// @[Decoupled.scala:51:35]\n wire [9:0] _s0_req_T_4_0_uop_fu_code = prober_fire ? 10'h0 : _s0_req_T_3_0_uop_fu_code;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_4_0_uop_ctrl_br_type = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ctrl_br_type;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_ctrl_op1_sel = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_ctrl_op1_sel;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_4_0_uop_ctrl_op2_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_op2_sel;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_4_0_uop_ctrl_imm_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_imm_sel;\t// @[Decoupled.scala:51:35]\n wire [4:0] _s0_req_T_4_0_uop_ctrl_op_fcn = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ctrl_op_fcn;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_ctrl_fcn_dw = ~prober_fire & _s0_req_T_3_0_uop_ctrl_fcn_dw;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_req_T_4_0_uop_ctrl_csr_cmd = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_csr_cmd;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_ctrl_is_load = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_load;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_ctrl_is_sta = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_sta;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_ctrl_is_std = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_std;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_iw_state = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_iw_state;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_iw_p1_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p1_poisoned;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_iw_p2_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p2_poisoned;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_br = ~prober_fire & _s0_req_T_3_0_uop_is_br;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_jalr = ~prober_fire & _s0_req_T_3_0_uop_is_jalr;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_jal = ~prober_fire & _s0_req_T_3_0_uop_is_jal;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_sfb = ~prober_fire & _s0_req_T_3_0_uop_is_sfb;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_4_0_uop_br_mask = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_br_mask;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_br_tag = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_br_tag;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_4_0_uop_ftq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ftq_idx;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_edge_inst = ~prober_fire & _s0_req_T_3_0_uop_edge_inst;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_4_0_uop_pc_lob = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_pc_lob;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_taken = ~prober_fire & _s0_req_T_3_0_uop_taken;\t// @[Decoupled.scala:51:35]\n wire [19:0] _s0_req_T_4_0_uop_imm_packed = prober_fire ? 20'h0 : _s0_req_T_3_0_uop_imm_packed;\t// @[Decoupled.scala:51:35]\n wire [11:0] _s0_req_T_4_0_uop_csr_addr = prober_fire ? 12'h0 : _s0_req_T_3_0_uop_csr_addr;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_4_0_uop_rob_idx = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_rob_idx;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_4_0_uop_ldq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ldq_idx;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_4_0_uop_stq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_stq_idx;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_rxq_idx = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_rxq_idx;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_4_0_uop_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_pdst;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_4_0_uop_prs1 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs1;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_4_0_uop_prs2 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs2;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_4_0_uop_prs3 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs3;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s0_req_T_4_0_uop_ppred = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ppred;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_prs1_busy = ~prober_fire & _s0_req_T_3_0_uop_prs1_busy;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_prs2_busy = ~prober_fire & _s0_req_T_3_0_uop_prs2_busy;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_prs3_busy = ~prober_fire & _s0_req_T_3_0_uop_prs3_busy;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_ppred_busy = ~prober_fire & _s0_req_T_3_0_uop_ppred_busy;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_4_0_uop_stale_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_stale_pdst;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_exception = ~prober_fire & _s0_req_T_3_0_uop_exception;\t// @[Decoupled.scala:51:35]\n wire [63:0] _s0_req_T_4_0_uop_exc_cause = prober_fire ? 64'h0 : _s0_req_T_3_0_uop_exc_cause;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_bypassable = ~prober_fire & _s0_req_T_3_0_uop_bypassable;\t// @[Decoupled.scala:51:35]\n wire [4:0] _s0_req_T_4_0_uop_mem_cmd = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_mem_cmd;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_mem_size = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_mem_size;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_mem_signed = ~prober_fire & _s0_req_T_3_0_uop_mem_signed;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_fence = ~prober_fire & _s0_req_T_3_0_uop_is_fence;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_fencei = ~prober_fire & _s0_req_T_3_0_uop_is_fencei;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_amo = ~prober_fire & _s0_req_T_3_0_uop_is_amo;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_uses_ldq = ~prober_fire & _s0_req_T_3_0_uop_uses_ldq;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_uses_stq = ~prober_fire & _s0_req_T_3_0_uop_uses_stq;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_sys_pc2epc = ~prober_fire & _s0_req_T_3_0_uop_is_sys_pc2epc;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_is_unique = ~prober_fire & _s0_req_T_3_0_uop_is_unique;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_flush_on_commit = ~prober_fire & _s0_req_T_3_0_uop_flush_on_commit;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_ldst_is_rs1 = ~prober_fire & _s0_req_T_3_0_uop_ldst_is_rs1;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_4_0_uop_ldst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_ldst;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_4_0_uop_lrs1 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs1;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_4_0_uop_lrs2 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs2;\t// @[Decoupled.scala:51:35]\n wire [5:0] _s0_req_T_4_0_uop_lrs3 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs3;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_ldst_val = ~prober_fire & _s0_req_T_3_0_uop_ldst_val;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_dst_rtype = prober_fire ? 2'h2 : _s0_req_T_3_0_uop_dst_rtype;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_lrs1_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs1_rtype;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_lrs2_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs2_rtype;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_frs3_en = ~prober_fire & _s0_req_T_3_0_uop_frs3_en;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_fp_val = ~prober_fire & _s0_req_T_3_0_uop_fp_val;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_fp_single = ~prober_fire & _s0_req_T_3_0_uop_fp_single;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_xcpt_pf_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_pf_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_xcpt_ae_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ae_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_xcpt_ma_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ma_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_bp_debug_if = ~prober_fire & _s0_req_T_3_0_uop_bp_debug_if;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_uop_bp_xcpt_if = ~prober_fire & _s0_req_T_3_0_uop_bp_xcpt_if;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_debug_fsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_fsrc;\t// @[Decoupled.scala:51:35]\n wire [1:0] _s0_req_T_4_0_uop_debug_tsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_tsrc;\t// @[Decoupled.scala:51:35]\n wire [33:0] _s0_req_T_4_0_addr = prober_fire ? prober_req_0_addr : _s0_req_T_3_0_addr;\t// @[Decoupled.scala:51:35]\n wire [63:0] _s0_req_T_4_0_data = prober_fire ? 64'h0 : _s0_req_T_3_0_data;\t// @[Decoupled.scala:51:35]\n wire _s0_req_T_4_0_is_hella = ~prober_fire & _s0_req_T_3_0_is_hella;\t// @[Decoupled.scala:51:35]\n wire [6:0] _s0_req_T_5_0_uop_uopc = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_uopc;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [31:0] _s0_req_T_5_0_uop_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_inst;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [31:0] _s0_req_T_5_0_uop_debug_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_debug_inst;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_rvc = ~wb_fire & _s0_req_T_4_0_uop_is_rvc;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [33:0] _s0_req_T_5_0_uop_debug_pc = wb_fire ? 34'h0 : _s0_req_T_4_0_uop_debug_pc;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [2:0] _s0_req_T_5_0_uop_iq_type = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_iq_type;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [9:0] _s0_req_T_5_0_uop_fu_code = wb_fire ? 10'h0 : _s0_req_T_4_0_uop_fu_code;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [3:0] _s0_req_T_5_0_uop_ctrl_br_type = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ctrl_br_type;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_ctrl_op1_sel = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_ctrl_op1_sel;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [2:0] _s0_req_T_5_0_uop_ctrl_op2_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_op2_sel;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [2:0] _s0_req_T_5_0_uop_ctrl_imm_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_imm_sel;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [4:0] _s0_req_T_5_0_uop_ctrl_op_fcn = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ctrl_op_fcn;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_ctrl_fcn_dw = ~wb_fire & _s0_req_T_4_0_uop_ctrl_fcn_dw;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [2:0] _s0_req_T_5_0_uop_ctrl_csr_cmd = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_csr_cmd;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_ctrl_is_load = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_load;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_ctrl_is_sta = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_sta;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_ctrl_is_std = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_std;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_iw_state = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_iw_state;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_iw_p1_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p1_poisoned;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_iw_p2_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p2_poisoned;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_br = ~wb_fire & _s0_req_T_4_0_uop_is_br;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_jalr = ~wb_fire & _s0_req_T_4_0_uop_is_jalr;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_jal = ~wb_fire & _s0_req_T_4_0_uop_is_jal;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_sfb = ~wb_fire & _s0_req_T_4_0_uop_is_sfb;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [3:0] _s0_req_T_5_0_uop_br_mask = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_br_mask;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_br_tag = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_br_tag;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [3:0] _s0_req_T_5_0_uop_ftq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ftq_idx;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_edge_inst = ~wb_fire & _s0_req_T_4_0_uop_edge_inst;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [5:0] _s0_req_T_5_0_uop_pc_lob = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_pc_lob;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_taken = ~wb_fire & _s0_req_T_4_0_uop_taken;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [19:0] _s0_req_T_5_0_uop_imm_packed = wb_fire ? 20'h0 : _s0_req_T_4_0_uop_imm_packed;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [11:0] _s0_req_T_5_0_uop_csr_addr = wb_fire ? 12'h0 : _s0_req_T_4_0_uop_csr_addr;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [5:0] _s0_req_T_5_0_uop_rob_idx = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_rob_idx;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [3:0] _s0_req_T_5_0_uop_ldq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ldq_idx;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [3:0] _s0_req_T_5_0_uop_stq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_stq_idx;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_rxq_idx = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_rxq_idx;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [6:0] _s0_req_T_5_0_uop_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_pdst;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [6:0] _s0_req_T_5_0_uop_prs1 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs1;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [6:0] _s0_req_T_5_0_uop_prs2 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs2;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [6:0] _s0_req_T_5_0_uop_prs3 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs3;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [3:0] _s0_req_T_5_0_uop_ppred = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ppred;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_prs1_busy = ~wb_fire & _s0_req_T_4_0_uop_prs1_busy;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_prs2_busy = ~wb_fire & _s0_req_T_4_0_uop_prs2_busy;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_prs3_busy = ~wb_fire & _s0_req_T_4_0_uop_prs3_busy;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_ppred_busy = ~wb_fire & _s0_req_T_4_0_uop_ppred_busy;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [6:0] _s0_req_T_5_0_uop_stale_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_stale_pdst;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_exception = ~wb_fire & _s0_req_T_4_0_uop_exception;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [63:0] _s0_req_T_5_0_uop_exc_cause = wb_fire ? 64'h0 : _s0_req_T_4_0_uop_exc_cause;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_bypassable = ~wb_fire & _s0_req_T_4_0_uop_bypassable;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [4:0] _s0_req_T_5_0_uop_mem_cmd = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_mem_cmd;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_mem_size = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_mem_size;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_mem_signed = ~wb_fire & _s0_req_T_4_0_uop_mem_signed;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_fence = ~wb_fire & _s0_req_T_4_0_uop_is_fence;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_fencei = ~wb_fire & _s0_req_T_4_0_uop_is_fencei;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_amo = ~wb_fire & _s0_req_T_4_0_uop_is_amo;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_uses_ldq = ~wb_fire & _s0_req_T_4_0_uop_uses_ldq;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_uses_stq = ~wb_fire & _s0_req_T_4_0_uop_uses_stq;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_sys_pc2epc = ~wb_fire & _s0_req_T_4_0_uop_is_sys_pc2epc;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_is_unique = ~wb_fire & _s0_req_T_4_0_uop_is_unique;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_flush_on_commit = ~wb_fire & _s0_req_T_4_0_uop_flush_on_commit;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_ldst_is_rs1 = ~wb_fire & _s0_req_T_4_0_uop_ldst_is_rs1;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [5:0] _s0_req_T_5_0_uop_ldst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_ldst;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [5:0] _s0_req_T_5_0_uop_lrs1 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs1;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [5:0] _s0_req_T_5_0_uop_lrs2 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs2;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [5:0] _s0_req_T_5_0_uop_lrs3 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs3;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_ldst_val = ~wb_fire & _s0_req_T_4_0_uop_ldst_val;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_dst_rtype = wb_fire ? 2'h2 : _s0_req_T_4_0_uop_dst_rtype;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_lrs1_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs1_rtype;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_lrs2_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs2_rtype;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_frs3_en = ~wb_fire & _s0_req_T_4_0_uop_frs3_en;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_fp_val = ~wb_fire & _s0_req_T_4_0_uop_fp_val;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_fp_single = ~wb_fire & _s0_req_T_4_0_uop_fp_single;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_xcpt_pf_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_pf_if;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_xcpt_ae_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ae_if;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_xcpt_ma_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ma_if;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_bp_debug_if = ~wb_fire & _s0_req_T_4_0_uop_bp_debug_if;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_uop_bp_xcpt_if = ~wb_fire & _s0_req_T_4_0_uop_bp_xcpt_if;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_debug_fsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_fsrc;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [1:0] _s0_req_T_5_0_uop_debug_tsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_tsrc;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [33:0] _s0_req_T_5_0_addr = wb_fire ? wb_req_0_addr : _s0_req_T_4_0_addr;\t// @[dcache.scala:531:38, :532:20, :583:21, :584:21]\n wire [63:0] _s0_req_T_5_0_data = wb_fire ? 64'h0 : _s0_req_T_4_0_data;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire _s0_req_T_5_0_is_hella = ~wb_fire & _s0_req_T_4_0_is_hella;\t// @[dcache.scala:531:38, :583:21, :584:21]\n wire [6:0] s0_req_0_uop_uopc = _s0_req_T ? _s0_req_WIRE_0_uop_uopc : _s0_req_T_5_0_uop_uopc;\t// @[Decoupled.scala:51:35]\n wire [31:0] s0_req_0_uop_inst = _s0_req_T ? _s0_req_WIRE_0_uop_inst : _s0_req_T_5_0_uop_inst;\t// @[Decoupled.scala:51:35]\n wire [31:0] s0_req_0_uop_debug_inst = _s0_req_T ? _s0_req_WIRE_0_uop_debug_inst : _s0_req_T_5_0_uop_debug_inst;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_rvc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rvc : _s0_req_T_5_0_uop_is_rvc;\t// @[Decoupled.scala:51:35]\n wire [33:0] s0_req_0_uop_debug_pc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_pc : _s0_req_T_5_0_uop_debug_pc;\t// @[Decoupled.scala:51:35]\n wire [2:0] s0_req_0_uop_iq_type = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type : _s0_req_T_5_0_uop_iq_type;\t// @[Decoupled.scala:51:35]\n wire [9:0] s0_req_0_uop_fu_code = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code : _s0_req_T_5_0_uop_fu_code;\t// @[Decoupled.scala:51:35]\n wire [3:0] s0_req_0_uop_ctrl_br_type = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_br_type : _s0_req_T_5_0_uop_ctrl_br_type;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_ctrl_op1_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op1_sel : _s0_req_T_5_0_uop_ctrl_op1_sel;\t// @[Decoupled.scala:51:35]\n wire [2:0] s0_req_0_uop_ctrl_op2_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op2_sel : _s0_req_T_5_0_uop_ctrl_op2_sel;\t// @[Decoupled.scala:51:35]\n wire [2:0] s0_req_0_uop_ctrl_imm_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_imm_sel : _s0_req_T_5_0_uop_ctrl_imm_sel;\t// @[Decoupled.scala:51:35]\n wire [4:0] s0_req_0_uop_ctrl_op_fcn = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op_fcn : _s0_req_T_5_0_uop_ctrl_op_fcn;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_ctrl_fcn_dw = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_fcn_dw : _s0_req_T_5_0_uop_ctrl_fcn_dw;\t// @[Decoupled.scala:51:35]\n wire [2:0] s0_req_0_uop_ctrl_csr_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_csr_cmd : _s0_req_T_5_0_uop_ctrl_csr_cmd;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_ctrl_is_load = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_load : _s0_req_T_5_0_uop_ctrl_is_load;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_ctrl_is_sta = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_sta : _s0_req_T_5_0_uop_ctrl_is_sta;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_ctrl_is_std = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_std : _s0_req_T_5_0_uop_ctrl_is_std;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_iw_state = _s0_req_T ? _s0_req_WIRE_0_uop_iw_state : _s0_req_T_5_0_uop_iw_state;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_iw_p1_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_poisoned : _s0_req_T_5_0_uop_iw_p1_poisoned;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_iw_p2_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_poisoned : _s0_req_T_5_0_uop_iw_p2_poisoned;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_br = _s0_req_T ? _s0_req_WIRE_0_uop_is_br : _s0_req_T_5_0_uop_is_br;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_jalr = _s0_req_T ? _s0_req_WIRE_0_uop_is_jalr : _s0_req_T_5_0_uop_is_jalr;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_jal = _s0_req_T ? _s0_req_WIRE_0_uop_is_jal : _s0_req_T_5_0_uop_is_jal;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_sfb = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfb : _s0_req_T_5_0_uop_is_sfb;\t// @[Decoupled.scala:51:35]\n wire [3:0] s0_req_0_uop_br_mask = _s0_req_T ? _s0_req_WIRE_0_uop_br_mask : _s0_req_T_5_0_uop_br_mask;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_br_tag = _s0_req_T ? _s0_req_WIRE_0_uop_br_tag : _s0_req_T_5_0_uop_br_tag;\t// @[Decoupled.scala:51:35]\n wire [3:0] s0_req_0_uop_ftq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ftq_idx : _s0_req_T_5_0_uop_ftq_idx;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_edge_inst = _s0_req_T ? _s0_req_WIRE_0_uop_edge_inst : _s0_req_T_5_0_uop_edge_inst;\t// @[Decoupled.scala:51:35]\n wire [5:0] s0_req_0_uop_pc_lob = _s0_req_T ? _s0_req_WIRE_0_uop_pc_lob : _s0_req_T_5_0_uop_pc_lob;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_taken = _s0_req_T ? _s0_req_WIRE_0_uop_taken : _s0_req_T_5_0_uop_taken;\t// @[Decoupled.scala:51:35]\n wire [19:0] s0_req_0_uop_imm_packed = _s0_req_T ? _s0_req_WIRE_0_uop_imm_packed : _s0_req_T_5_0_uop_imm_packed;\t// @[Decoupled.scala:51:35]\n wire [11:0] s0_req_0_uop_csr_addr = _s0_req_T ? _s0_req_WIRE_0_uop_csr_addr : _s0_req_T_5_0_uop_csr_addr;\t// @[Decoupled.scala:51:35]\n wire [5:0] s0_req_0_uop_rob_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rob_idx : _s0_req_T_5_0_uop_rob_idx;\t// @[Decoupled.scala:51:35]\n wire [3:0] s0_req_0_uop_ldq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ldq_idx : _s0_req_T_5_0_uop_ldq_idx;\t// @[Decoupled.scala:51:35]\n wire [3:0] s0_req_0_uop_stq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_stq_idx : _s0_req_T_5_0_uop_stq_idx;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_rxq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rxq_idx : _s0_req_T_5_0_uop_rxq_idx;\t// @[Decoupled.scala:51:35]\n wire [6:0] s0_req_0_uop_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_pdst : _s0_req_T_5_0_uop_pdst;\t// @[Decoupled.scala:51:35]\n wire [6:0] s0_req_0_uop_prs1 = _s0_req_T ? _s0_req_WIRE_0_uop_prs1 : _s0_req_T_5_0_uop_prs1;\t// @[Decoupled.scala:51:35]\n wire [6:0] s0_req_0_uop_prs2 = _s0_req_T ? _s0_req_WIRE_0_uop_prs2 : _s0_req_T_5_0_uop_prs2;\t// @[Decoupled.scala:51:35]\n wire [6:0] s0_req_0_uop_prs3 = _s0_req_T ? _s0_req_WIRE_0_uop_prs3 : _s0_req_T_5_0_uop_prs3;\t// @[Decoupled.scala:51:35]\n wire [3:0] s0_req_0_uop_ppred = _s0_req_T ? _s0_req_WIRE_0_uop_ppred : _s0_req_T_5_0_uop_ppred;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_prs1_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs1_busy : _s0_req_T_5_0_uop_prs1_busy;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_prs2_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs2_busy : _s0_req_T_5_0_uop_prs2_busy;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_prs3_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs3_busy : _s0_req_T_5_0_uop_prs3_busy;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_ppred_busy = _s0_req_T ? _s0_req_WIRE_0_uop_ppred_busy : _s0_req_T_5_0_uop_ppred_busy;\t// @[Decoupled.scala:51:35]\n wire [6:0] s0_req_0_uop_stale_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_stale_pdst : _s0_req_T_5_0_uop_stale_pdst;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_exception = _s0_req_T ? _s0_req_WIRE_0_uop_exception : _s0_req_T_5_0_uop_exception;\t// @[Decoupled.scala:51:35]\n wire [63:0] s0_req_0_uop_exc_cause = _s0_req_T ? _s0_req_WIRE_0_uop_exc_cause : _s0_req_T_5_0_uop_exc_cause;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_bypassable = _s0_req_T ? _s0_req_WIRE_0_uop_bypassable : _s0_req_T_5_0_uop_bypassable;\t// @[Decoupled.scala:51:35]\n wire [4:0] s0_req_0_uop_mem_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_mem_cmd : _s0_req_T_5_0_uop_mem_cmd;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_mem_size = _s0_req_T ? _s0_req_WIRE_0_uop_mem_size : _s0_req_T_5_0_uop_mem_size;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_mem_signed = _s0_req_T ? _s0_req_WIRE_0_uop_mem_signed : _s0_req_T_5_0_uop_mem_signed;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_fence = _s0_req_T ? _s0_req_WIRE_0_uop_is_fence : _s0_req_T_5_0_uop_is_fence;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_fencei = _s0_req_T ? _s0_req_WIRE_0_uop_is_fencei : _s0_req_T_5_0_uop_is_fencei;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_amo = _s0_req_T ? _s0_req_WIRE_0_uop_is_amo : _s0_req_T_5_0_uop_is_amo;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_uses_ldq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_ldq : _s0_req_T_5_0_uop_uses_ldq;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_uses_stq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_stq : _s0_req_T_5_0_uop_uses_stq;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_sys_pc2epc = _s0_req_T ? _s0_req_WIRE_0_uop_is_sys_pc2epc : _s0_req_T_5_0_uop_is_sys_pc2epc;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_is_unique = _s0_req_T ? _s0_req_WIRE_0_uop_is_unique : _s0_req_T_5_0_uop_is_unique;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_flush_on_commit = _s0_req_T ? _s0_req_WIRE_0_uop_flush_on_commit : _s0_req_T_5_0_uop_flush_on_commit;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_ldst_is_rs1 = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_is_rs1 : _s0_req_T_5_0_uop_ldst_is_rs1;\t// @[Decoupled.scala:51:35]\n wire [5:0] s0_req_0_uop_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_ldst : _s0_req_T_5_0_uop_ldst;\t// @[Decoupled.scala:51:35]\n wire [5:0] s0_req_0_uop_lrs1 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1 : _s0_req_T_5_0_uop_lrs1;\t// @[Decoupled.scala:51:35]\n wire [5:0] s0_req_0_uop_lrs2 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2 : _s0_req_T_5_0_uop_lrs2;\t// @[Decoupled.scala:51:35]\n wire [5:0] s0_req_0_uop_lrs3 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs3 : _s0_req_T_5_0_uop_lrs3;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_ldst_val = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_val : _s0_req_T_5_0_uop_ldst_val;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_dst_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_dst_rtype : _s0_req_T_5_0_uop_dst_rtype;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_lrs1_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1_rtype : _s0_req_T_5_0_uop_lrs1_rtype;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_lrs2_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2_rtype : _s0_req_T_5_0_uop_lrs2_rtype;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_frs3_en = _s0_req_T ? _s0_req_WIRE_0_uop_frs3_en : _s0_req_T_5_0_uop_frs3_en;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_fp_val = _s0_req_T ? _s0_req_WIRE_0_uop_fp_val : _s0_req_T_5_0_uop_fp_val;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_fp_single = _s0_req_T ? _s0_req_WIRE_0_uop_fp_single : _s0_req_T_5_0_uop_fp_single;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_xcpt_pf_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_pf_if : _s0_req_T_5_0_uop_xcpt_pf_if;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_xcpt_ae_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ae_if : _s0_req_T_5_0_uop_xcpt_ae_if;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_xcpt_ma_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ma_if : _s0_req_T_5_0_uop_xcpt_ma_if;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_bp_debug_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_debug_if : _s0_req_T_5_0_uop_bp_debug_if;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_uop_bp_xcpt_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_xcpt_if : _s0_req_T_5_0_uop_bp_xcpt_if;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_debug_fsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_fsrc : _s0_req_T_5_0_uop_debug_fsrc;\t// @[Decoupled.scala:51:35]\n wire [1:0] s0_req_0_uop_debug_tsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_tsrc : _s0_req_T_5_0_uop_debug_tsrc;\t// @[Decoupled.scala:51:35]\n wire [33:0] s0_req_0_addr = _s0_req_T ? _s0_req_WIRE_0_addr : _s0_req_T_5_0_addr;\t// @[Decoupled.scala:51:35]\n wire [63:0] s0_req_0_data = _s0_req_T ? _s0_req_WIRE_0_data : _s0_req_T_5_0_data;\t// @[Decoupled.scala:51:35]\n wire s0_req_0_is_hella = _s0_req_T ? _s0_req_WIRE_0_is_hella : _s0_req_T_5_0_is_hella;\t// @[Decoupled.scala:51:35]\n wire [3:0] _s1_req_0_uop_br_mask_T_1 = s0_req_0_uop_br_mask;\t// @[util.scala:85:25]\n wire [2:0] _s0_type_T_2 = _s0_type_T_1 ? 3'h3 : 3'h0;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_type_T_3 = _s0_type_T_2;\t// @[dcache.scala:591:21, :592:21]\n wire [2:0] _s0_type_T_4 = prober_fire ? 3'h1 : _s0_type_T_3;\t// @[Decoupled.scala:51:35]\n wire [2:0] _s0_type_T_5 = wb_fire ? 3'h2 : _s0_type_T_4;\t// @[dcache.scala:531:38, :589:21, :590:21]\n wire [2:0] s0_type = _s0_type_T ? 3'h4 : _s0_type_T_5;\t// @[Decoupled.scala:51:35]\n wire _s0_send_resp_or_nack_T_2 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h0;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_3 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h10;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_4 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h6;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_5 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h7;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_6 = _s0_send_resp_or_nack_T_2 | _s0_send_resp_or_nack_T_3;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_7 = _s0_send_resp_or_nack_T_6 | _s0_send_resp_or_nack_T_4;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_8 = _s0_send_resp_or_nack_T_7 | _s0_send_resp_or_nack_T_5;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_9 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h4;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_10 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h9;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_11 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hA;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_12 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hB;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_13 = _s0_send_resp_or_nack_T_9 | _s0_send_resp_or_nack_T_10;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_14 = _s0_send_resp_or_nack_T_13 | _s0_send_resp_or_nack_T_11;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_15 = _s0_send_resp_or_nack_T_14 | _s0_send_resp_or_nack_T_12;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_16 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h8;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_17 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hC;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_18 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hD;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_19 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hE;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_20 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hF;\t// @[package.scala:16:47]\n wire _s0_send_resp_or_nack_T_21 = _s0_send_resp_or_nack_T_16 | _s0_send_resp_or_nack_T_17;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_22 = _s0_send_resp_or_nack_T_21 | _s0_send_resp_or_nack_T_18;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_23 = _s0_send_resp_or_nack_T_22 | _s0_send_resp_or_nack_T_19;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_24 = _s0_send_resp_or_nack_T_23 | _s0_send_resp_or_nack_T_20;\t// @[package.scala:16:47, :81:59]\n wire _s0_send_resp_or_nack_T_25 = _s0_send_resp_or_nack_T_15 | _s0_send_resp_or_nack_T_24;\t// @[package.scala:81:59]\n wire _s0_send_resp_or_nack_T_26 = _s0_send_resp_or_nack_T_8 | _s0_send_resp_or_nack_T_25;\t// @[package.scala:81:59]\n wire _s0_send_resp_or_nack_T_27 = _s0_send_resp_or_nack_T_1 & _s0_send_resp_or_nack_T_26;\t// @[Decoupled.scala:51:35]\n wire _s0_send_resp_or_nack_T_28 = _s0_send_resp_or_nack_T_27;\t// @[dcache.scala:597:{16,38}]\n wire _s0_send_resp_or_nack_T_29 = _s0_send_resp_or_nack_T_28;\t// @[dcache.scala:597:{16,117}]\n wire _s0_send_resp_or_nack_WIRE_0 = _s0_send_resp_or_nack_T_29;\t// @[dcache.scala:597:{12,117}]\n wire s0_send_resp_or_nack_0 = _s0_send_resp_or_nack_T ? s0_valid_0 : _s0_send_resp_or_nack_WIRE_0;\t// @[Decoupled.scala:51:35]\n reg [6:0] s1_req_0_uop_uopc;\t// @[dcache.scala:600:32]\n reg [31:0] s1_req_0_uop_inst;\t// @[dcache.scala:600:32]\n reg [31:0] s1_req_0_uop_debug_inst;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_rvc;\t// @[dcache.scala:600:32]\n reg [33:0] s1_req_0_uop_debug_pc;\t// @[dcache.scala:600:32]\n reg [2:0] s1_req_0_uop_iq_type;\t// @[dcache.scala:600:32]\n reg [9:0] s1_req_0_uop_fu_code;\t// @[dcache.scala:600:32]\n reg [3:0] s1_req_0_uop_ctrl_br_type;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_ctrl_op1_sel;\t// @[dcache.scala:600:32]\n reg [2:0] s1_req_0_uop_ctrl_op2_sel;\t// @[dcache.scala:600:32]\n reg [2:0] s1_req_0_uop_ctrl_imm_sel;\t// @[dcache.scala:600:32]\n reg [4:0] s1_req_0_uop_ctrl_op_fcn;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_ctrl_fcn_dw;\t// @[dcache.scala:600:32]\n reg [2:0] s1_req_0_uop_ctrl_csr_cmd;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_ctrl_is_load;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_ctrl_is_sta;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_ctrl_is_std;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_iw_state;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_iw_p1_poisoned;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_iw_p2_poisoned;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_br;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_jalr;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_jal;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_sfb;\t// @[dcache.scala:600:32]\n reg [3:0] s1_req_0_uop_br_mask;\t// @[dcache.scala:600:32]\n wire [3:0] _s2_req_0_uop_br_mask_T_1 = s1_req_0_uop_br_mask;\t// @[util.scala:85:25]\n reg [1:0] s1_req_0_uop_br_tag;\t// @[dcache.scala:600:32]\n reg [3:0] s1_req_0_uop_ftq_idx;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_edge_inst;\t// @[dcache.scala:600:32]\n reg [5:0] s1_req_0_uop_pc_lob;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_taken;\t// @[dcache.scala:600:32]\n reg [19:0] s1_req_0_uop_imm_packed;\t// @[dcache.scala:600:32]\n reg [11:0] s1_req_0_uop_csr_addr;\t// @[dcache.scala:600:32]\n reg [5:0] s1_req_0_uop_rob_idx;\t// @[dcache.scala:600:32]\n reg [3:0] s1_req_0_uop_ldq_idx;\t// @[dcache.scala:600:32]\n reg [3:0] s1_req_0_uop_stq_idx;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_rxq_idx;\t// @[dcache.scala:600:32]\n reg [6:0] s1_req_0_uop_pdst;\t// @[dcache.scala:600:32]\n reg [6:0] s1_req_0_uop_prs1;\t// @[dcache.scala:600:32]\n reg [6:0] s1_req_0_uop_prs2;\t// @[dcache.scala:600:32]\n reg [6:0] s1_req_0_uop_prs3;\t// @[dcache.scala:600:32]\n reg [3:0] s1_req_0_uop_ppred;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_prs1_busy;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_prs2_busy;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_prs3_busy;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_ppred_busy;\t// @[dcache.scala:600:32]\n reg [6:0] s1_req_0_uop_stale_pdst;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_exception;\t// @[dcache.scala:600:32]\n reg [63:0] s1_req_0_uop_exc_cause;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_bypassable;\t// @[dcache.scala:600:32]\n reg [4:0] s1_req_0_uop_mem_cmd;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_mem_size;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_mem_signed;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_fence;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_fencei;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_amo;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_uses_ldq;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_uses_stq;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_sys_pc2epc;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_is_unique;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_flush_on_commit;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_ldst_is_rs1;\t// @[dcache.scala:600:32]\n reg [5:0] s1_req_0_uop_ldst;\t// @[dcache.scala:600:32]\n reg [5:0] s1_req_0_uop_lrs1;\t// @[dcache.scala:600:32]\n reg [5:0] s1_req_0_uop_lrs2;\t// @[dcache.scala:600:32]\n reg [5:0] s1_req_0_uop_lrs3;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_ldst_val;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_dst_rtype;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_lrs1_rtype;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_lrs2_rtype;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_frs3_en;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_fp_val;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_fp_single;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_xcpt_pf_if;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_xcpt_ae_if;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_xcpt_ma_if;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_bp_debug_if;\t// @[dcache.scala:600:32]\n reg s1_req_0_uop_bp_xcpt_if;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_debug_fsrc;\t// @[dcache.scala:600:32]\n reg [1:0] s1_req_0_uop_debug_tsrc;\t// @[dcache.scala:600:32]\n reg [33:0] s1_req_0_addr;\t// @[dcache.scala:600:32]\n reg [63:0] s1_req_0_data;\t// @[dcache.scala:600:32]\n reg s1_req_0_is_hella;\t// @[dcache.scala:600:32]\n wire _s2_store_failed_T_2;\t// @[dcache.scala:742:67]\n wire s2_store_failed;\t// @[dcache.scala:603:29]\n wire _s1_valid_T_6 = _s1_valid_T_3;\t// @[dcache.scala:605:74, :606:76]\n wire _s1_valid_T_8 = s2_store_failed & _s1_valid_T_7;\t// @[Decoupled.scala:51:35]\n wire _s1_valid_T_9 = _s1_valid_T_8 & s0_req_0_uop_uses_stq;\t// @[dcache.scala:582:21, :608:{44,63}]\n wire _s1_valid_T_10 = ~_s1_valid_T_9;\t// @[dcache.scala:608:{26,63}]\n wire _s1_valid_T_11 = _s1_valid_T_6 & _s1_valid_T_10;\t// @[dcache.scala:606:76, :607:74, :608:26]\n reg s1_valid_REG;\t// @[dcache.scala:605:25]\n wire s1_valid_0 = s1_valid_REG;\t// @[dcache.scala:427:49, :605:25]\n reg REG;\t// @[dcache.scala:611:43]\n reg REG_1;\t// @[dcache.scala:611:72]\n wire [3:0] _s1_nack_T = s1_req_0_addr[9:6];\t// @[dcache.scala:600:32, :613:43]\n wire [3:0] _s1_wb_idx_matches_T = s1_req_0_addr[9:6];\t// @[dcache.scala:600:32, :613:43, :630:52]\n wire _s1_nack_T_1 = _s1_nack_T == _prober_io_meta_write_bits_idx;\t// @[dcache.scala:432:22, :613:{43,59}]\n wire _s1_nack_T_2 = ~_prober_io_req_ready;\t// @[dcache.scala:432:22, :613:96]\n wire s1_nack_0 = _s1_nack_T_1 & _s1_nack_T_2;\t// @[dcache.scala:613:{59,93,96}]\n wire _s2_nack_hit_WIRE_0 = s1_nack_0;\t// @[dcache.scala:613:93, :722:39]\n reg s1_send_resp_or_nack_0;\t// @[dcache.scala:614:37]\n reg [2:0] s1_type;\t// @[dcache.scala:615:32]\n reg [1:0] s1_mshr_meta_read_way_en;\t// @[dcache.scala:617:41]\n reg [1:0] s1_replay_way_en;\t// @[dcache.scala:618:41]\n reg [1:0] s1_wb_way_en;\t// @[dcache.scala:619:41]\n wire [23:0] _s1_tag_eq_way_T = s1_req_0_addr[33:10];\t// @[dcache.scala:600:32, :623:95]\n wire [23:0] _s1_tag_eq_way_T_2 = s1_req_0_addr[33:10];\t// @[dcache.scala:600:32, :623:95]\n wire _s1_tag_eq_way_T_1 = {2'h0, _meta_0_io_resp_0_tag} == _s1_tag_eq_way_T;\t// @[dcache.scala:442:41, :623:{79,95}]\n wire _s1_tag_eq_way_WIRE_0 = _s1_tag_eq_way_T_1;\t// @[dcache.scala:622:47, :623:79]\n wire _s1_tag_eq_way_T_3 = {2'h0, _meta_0_io_resp_1_tag} == _s1_tag_eq_way_T_2;\t// @[dcache.scala:442:41, :623:{79,95}]\n wire _s1_tag_eq_way_WIRE_1 = _s1_tag_eq_way_T_3;\t// @[dcache.scala:622:47, :623:79]\n wire [1:0] _s1_tag_eq_way_T_4 = {_s1_tag_eq_way_WIRE_1, _s1_tag_eq_way_WIRE_0};\t// @[dcache.scala:622:47, :623:110]\n wire [1:0] s1_tag_eq_way_0 = _s1_tag_eq_way_T_4;\t// @[dcache.scala:427:49, :623:110]\n wire _s1_tag_match_way_T = s1_type == 3'h0;\t// @[dcache.scala:615:32, :625:38]\n wire _s1_tag_match_way_T_1 = s1_type == 3'h2;\t// @[dcache.scala:615:32, :626:38]\n wire _s1_tag_match_way_T_2 = s1_type == 3'h3;\t// @[dcache.scala:615:32, :627:38]\n wire _s1_tag_match_way_T_3 = s1_tag_eq_way_0[0];\t// @[dcache.scala:427:49, :628:63]\n wire _s1_tag_match_way_T_4 = |_meta_0_io_resp_0_coh_state;\t// @[Metadata.scala:50:45]\n wire _s1_tag_match_way_T_5 = _s1_tag_match_way_T_3 & _s1_tag_match_way_T_4;\t// @[Metadata.scala:50:45]\n wire _s1_tag_match_way_WIRE_0 = _s1_tag_match_way_T_5;\t// @[dcache.scala:622:47, :628:67]\n wire _s1_tag_match_way_T_6 = s1_tag_eq_way_0[1];\t// @[dcache.scala:427:49, :628:63]\n wire _s1_tag_match_way_T_7 = |_meta_0_io_resp_1_coh_state;\t// @[Metadata.scala:50:45]\n wire _s1_tag_match_way_T_8 = _s1_tag_match_way_T_6 & _s1_tag_match_way_T_7;\t// @[Metadata.scala:50:45]\n wire _s1_tag_match_way_WIRE_1 = _s1_tag_match_way_T_8;\t// @[dcache.scala:622:47, :628:67]\n wire [1:0] _s1_tag_match_way_T_9 = {_s1_tag_match_way_WIRE_1, _s1_tag_match_way_WIRE_0};\t// @[dcache.scala:622:47, :628:104]\n wire [1:0] _s1_tag_match_way_T_10 = _s1_tag_match_way_T_2 ? s1_mshr_meta_read_way_en : _s1_tag_match_way_T_9;\t// @[dcache.scala:617:41, :627:{29,38}, :628:104]\n wire [1:0] _s1_tag_match_way_T_11 = _s1_tag_match_way_T_1 ? s1_wb_way_en : _s1_tag_match_way_T_10;\t// @[dcache.scala:619:41, :626:{29,38}, :627:29]\n wire [1:0] _s1_tag_match_way_T_12 = _s1_tag_match_way_T ? s1_replay_way_en : _s1_tag_match_way_T_11;\t// @[dcache.scala:618:41, :625:{29,38}, :626:29]\n wire [1:0] s1_tag_match_way_0 = _s1_tag_match_way_T_12;\t// @[dcache.scala:427:49, :625:29]\n wire _s1_wb_idx_matches_T_1 = _s1_wb_idx_matches_T == _wb_io_idx_bits;\t// @[dcache.scala:431:18, :630:{52,79}]\n wire _s1_wb_idx_matches_T_2 = _s1_wb_idx_matches_T_1 & _wb_io_idx_valid;\t// @[dcache.scala:431:18, :630:{79,99}]\n wire s1_wb_idx_matches_0 = _s1_wb_idx_matches_T_2;\t// @[dcache.scala:427:49, :630:99]\n reg [6:0] s2_req_0_uop_uopc;\t// @[dcache.scala:632:25]\n wire [6:0] cache_resp_0_bits_uop_uopc = s2_req_0_uop_uopc;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_uopc = s2_req_0_uop_uopc;\t// @[util.scala:101:23]\n reg [31:0] s2_req_0_uop_inst;\t// @[dcache.scala:632:25]\n wire [31:0] cache_resp_0_bits_uop_inst = s2_req_0_uop_inst;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_inst = s2_req_0_uop_inst;\t// @[util.scala:101:23]\n reg [31:0] s2_req_0_uop_debug_inst;\t// @[dcache.scala:632:25]\n wire [31:0] cache_resp_0_bits_uop_debug_inst = s2_req_0_uop_debug_inst;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_debug_inst = s2_req_0_uop_debug_inst;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_rvc;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_rvc = s2_req_0_uop_is_rvc;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_rvc = s2_req_0_uop_is_rvc;\t// @[util.scala:101:23]\n reg [33:0] s2_req_0_uop_debug_pc;\t// @[dcache.scala:632:25]\n wire [33:0] cache_resp_0_bits_uop_debug_pc = s2_req_0_uop_debug_pc;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_debug_pc = s2_req_0_uop_debug_pc;\t// @[util.scala:101:23]\n reg [2:0] s2_req_0_uop_iq_type;\t// @[dcache.scala:632:25]\n wire [2:0] cache_resp_0_bits_uop_iq_type = s2_req_0_uop_iq_type;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_iq_type = s2_req_0_uop_iq_type;\t// @[util.scala:101:23]\n reg [9:0] s2_req_0_uop_fu_code;\t// @[dcache.scala:632:25]\n wire [9:0] cache_resp_0_bits_uop_fu_code = s2_req_0_uop_fu_code;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_fu_code = s2_req_0_uop_fu_code;\t// @[util.scala:101:23]\n reg [3:0] s2_req_0_uop_ctrl_br_type;\t// @[dcache.scala:632:25]\n wire [3:0] cache_resp_0_bits_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_ctrl_op1_sel;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel;\t// @[util.scala:101:23]\n reg [2:0] s2_req_0_uop_ctrl_op2_sel;\t// @[dcache.scala:632:25]\n wire [2:0] cache_resp_0_bits_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel;\t// @[util.scala:101:23]\n reg [2:0] s2_req_0_uop_ctrl_imm_sel;\t// @[dcache.scala:632:25]\n wire [2:0] cache_resp_0_bits_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel;\t// @[util.scala:101:23]\n reg [4:0] s2_req_0_uop_ctrl_op_fcn;\t// @[dcache.scala:632:25]\n wire [4:0] cache_resp_0_bits_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn;\t// @[util.scala:101:23]\n reg s2_req_0_uop_ctrl_fcn_dw;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw;\t// @[util.scala:101:23]\n reg [2:0] s2_req_0_uop_ctrl_csr_cmd;\t// @[dcache.scala:632:25]\n wire [2:0] cache_resp_0_bits_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd;\t// @[util.scala:101:23]\n reg s2_req_0_uop_ctrl_is_load;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load;\t// @[util.scala:101:23]\n reg s2_req_0_uop_ctrl_is_sta;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta;\t// @[util.scala:101:23]\n reg s2_req_0_uop_ctrl_is_std;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_iw_state;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_iw_state = s2_req_0_uop_iw_state;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_iw_state = s2_req_0_uop_iw_state;\t// @[util.scala:101:23]\n reg s2_req_0_uop_iw_p1_poisoned;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned;\t// @[util.scala:101:23]\n reg s2_req_0_uop_iw_p2_poisoned;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_br;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_br = s2_req_0_uop_is_br;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_br = s2_req_0_uop_is_br;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_jalr;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_jalr = s2_req_0_uop_is_jalr;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_jalr = s2_req_0_uop_is_jalr;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_jal;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_jal = s2_req_0_uop_is_jal;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_jal = s2_req_0_uop_is_jal;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_sfb;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_sfb = s2_req_0_uop_is_sfb;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_sfb = s2_req_0_uop_is_sfb;\t// @[util.scala:101:23]\n reg [3:0] s2_req_0_uop_br_mask;\t// @[dcache.scala:632:25]\n wire [3:0] _mshrs_io_req_0_bits_uop_br_mask_T_1 = s2_req_0_uop_br_mask;\t// @[util.scala:85:25]\n wire [3:0] cache_resp_0_bits_uop_br_mask = s2_req_0_uop_br_mask;\t// @[dcache.scala:632:25, :833:26]\n wire [3:0] _io_lsu_nack_0_bits_out_uop_br_mask_T_1 = s2_req_0_uop_br_mask;\t// @[util.scala:89:21]\n reg [1:0] s2_req_0_uop_br_tag;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_br_tag = s2_req_0_uop_br_tag;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_br_tag = s2_req_0_uop_br_tag;\t// @[util.scala:101:23]\n reg [3:0] s2_req_0_uop_ftq_idx;\t// @[dcache.scala:632:25]\n wire [3:0] cache_resp_0_bits_uop_ftq_idx = s2_req_0_uop_ftq_idx;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ftq_idx = s2_req_0_uop_ftq_idx;\t// @[util.scala:101:23]\n reg s2_req_0_uop_edge_inst;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_edge_inst = s2_req_0_uop_edge_inst;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_edge_inst = s2_req_0_uop_edge_inst;\t// @[util.scala:101:23]\n reg [5:0] s2_req_0_uop_pc_lob;\t// @[dcache.scala:632:25]\n wire [5:0] cache_resp_0_bits_uop_pc_lob = s2_req_0_uop_pc_lob;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_pc_lob = s2_req_0_uop_pc_lob;\t// @[util.scala:101:23]\n reg s2_req_0_uop_taken;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_taken = s2_req_0_uop_taken;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_taken = s2_req_0_uop_taken;\t// @[util.scala:101:23]\n reg [19:0] s2_req_0_uop_imm_packed;\t// @[dcache.scala:632:25]\n wire [19:0] cache_resp_0_bits_uop_imm_packed = s2_req_0_uop_imm_packed;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_imm_packed = s2_req_0_uop_imm_packed;\t// @[util.scala:101:23]\n reg [11:0] s2_req_0_uop_csr_addr;\t// @[dcache.scala:632:25]\n wire [11:0] cache_resp_0_bits_uop_csr_addr = s2_req_0_uop_csr_addr;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_csr_addr = s2_req_0_uop_csr_addr;\t// @[util.scala:101:23]\n reg [5:0] s2_req_0_uop_rob_idx;\t// @[dcache.scala:632:25]\n wire [5:0] cache_resp_0_bits_uop_rob_idx = s2_req_0_uop_rob_idx;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_rob_idx = s2_req_0_uop_rob_idx;\t// @[util.scala:101:23]\n reg [3:0] s2_req_0_uop_ldq_idx;\t// @[dcache.scala:632:25]\n wire [3:0] cache_resp_0_bits_uop_ldq_idx = s2_req_0_uop_ldq_idx;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ldq_idx = s2_req_0_uop_ldq_idx;\t// @[util.scala:101:23]\n reg [3:0] s2_req_0_uop_stq_idx;\t// @[dcache.scala:632:25]\n wire [3:0] cache_resp_0_bits_uop_stq_idx = s2_req_0_uop_stq_idx;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_stq_idx = s2_req_0_uop_stq_idx;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_rxq_idx;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_rxq_idx = s2_req_0_uop_rxq_idx;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_rxq_idx = s2_req_0_uop_rxq_idx;\t// @[util.scala:101:23]\n reg [6:0] s2_req_0_uop_pdst;\t// @[dcache.scala:632:25]\n wire [6:0] cache_resp_0_bits_uop_pdst = s2_req_0_uop_pdst;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_pdst = s2_req_0_uop_pdst;\t// @[util.scala:101:23]\n reg [6:0] s2_req_0_uop_prs1;\t// @[dcache.scala:632:25]\n wire [6:0] cache_resp_0_bits_uop_prs1 = s2_req_0_uop_prs1;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_prs1 = s2_req_0_uop_prs1;\t// @[util.scala:101:23]\n reg [6:0] s2_req_0_uop_prs2;\t// @[dcache.scala:632:25]\n wire [6:0] cache_resp_0_bits_uop_prs2 = s2_req_0_uop_prs2;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_prs2 = s2_req_0_uop_prs2;\t// @[util.scala:101:23]\n reg [6:0] s2_req_0_uop_prs3;\t// @[dcache.scala:632:25]\n wire [6:0] cache_resp_0_bits_uop_prs3 = s2_req_0_uop_prs3;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_prs3 = s2_req_0_uop_prs3;\t// @[util.scala:101:23]\n reg [3:0] s2_req_0_uop_ppred;\t// @[dcache.scala:632:25]\n wire [3:0] cache_resp_0_bits_uop_ppred = s2_req_0_uop_ppred;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ppred = s2_req_0_uop_ppred;\t// @[util.scala:101:23]\n reg s2_req_0_uop_prs1_busy;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_prs1_busy = s2_req_0_uop_prs1_busy;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_prs1_busy = s2_req_0_uop_prs1_busy;\t// @[util.scala:101:23]\n reg s2_req_0_uop_prs2_busy;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_prs2_busy = s2_req_0_uop_prs2_busy;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_prs2_busy = s2_req_0_uop_prs2_busy;\t// @[util.scala:101:23]\n reg s2_req_0_uop_prs3_busy;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_prs3_busy = s2_req_0_uop_prs3_busy;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_prs3_busy = s2_req_0_uop_prs3_busy;\t// @[util.scala:101:23]\n reg s2_req_0_uop_ppred_busy;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_ppred_busy = s2_req_0_uop_ppred_busy;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ppred_busy = s2_req_0_uop_ppred_busy;\t// @[util.scala:101:23]\n reg [6:0] s2_req_0_uop_stale_pdst;\t// @[dcache.scala:632:25]\n wire [6:0] cache_resp_0_bits_uop_stale_pdst = s2_req_0_uop_stale_pdst;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_stale_pdst = s2_req_0_uop_stale_pdst;\t// @[util.scala:101:23]\n reg s2_req_0_uop_exception;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_exception = s2_req_0_uop_exception;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_exception = s2_req_0_uop_exception;\t// @[util.scala:101:23]\n reg [63:0] s2_req_0_uop_exc_cause;\t// @[dcache.scala:632:25]\n wire [63:0] cache_resp_0_bits_uop_exc_cause = s2_req_0_uop_exc_cause;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_exc_cause = s2_req_0_uop_exc_cause;\t// @[util.scala:101:23]\n reg s2_req_0_uop_bypassable;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_bypassable = s2_req_0_uop_bypassable;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_bypassable = s2_req_0_uop_bypassable;\t// @[util.scala:101:23]\n reg [4:0] s2_req_0_uop_mem_cmd;\t// @[dcache.scala:632:25]\n wire [4:0] cache_resp_0_bits_uop_mem_cmd = s2_req_0_uop_mem_cmd;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_mem_cmd = s2_req_0_uop_mem_cmd;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_mem_size;\t// @[dcache.scala:632:25]\n wire [1:0] size = s2_req_0_uop_mem_size;\t// @[AMOALU.scala:11:18]\n wire [1:0] cache_resp_0_bits_uop_mem_size = s2_req_0_uop_mem_size;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_mem_size = s2_req_0_uop_mem_size;\t// @[util.scala:101:23]\n wire [1:0] amoalu_io_mask_size = s2_req_0_uop_mem_size;\t// @[AMOALU.scala:11:18]\n reg s2_req_0_uop_mem_signed;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_mem_signed = s2_req_0_uop_mem_signed;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_mem_signed = s2_req_0_uop_mem_signed;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_fence;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_fence = s2_req_0_uop_is_fence;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_fence = s2_req_0_uop_is_fence;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_fencei;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_fencei = s2_req_0_uop_is_fencei;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_fencei = s2_req_0_uop_is_fencei;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_amo;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_amo = s2_req_0_uop_is_amo;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_amo = s2_req_0_uop_is_amo;\t// @[util.scala:101:23]\n reg s2_req_0_uop_uses_ldq;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_uses_ldq = s2_req_0_uop_uses_ldq;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_uses_ldq = s2_req_0_uop_uses_ldq;\t// @[util.scala:101:23]\n reg s2_req_0_uop_uses_stq;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_uses_stq = s2_req_0_uop_uses_stq;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_uses_stq = s2_req_0_uop_uses_stq;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_sys_pc2epc;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc;\t// @[util.scala:101:23]\n reg s2_req_0_uop_is_unique;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_is_unique = s2_req_0_uop_is_unique;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_is_unique = s2_req_0_uop_is_unique;\t// @[util.scala:101:23]\n reg s2_req_0_uop_flush_on_commit;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_flush_on_commit = s2_req_0_uop_flush_on_commit;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_flush_on_commit = s2_req_0_uop_flush_on_commit;\t// @[util.scala:101:23]\n reg s2_req_0_uop_ldst_is_rs1;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1;\t// @[util.scala:101:23]\n reg [5:0] s2_req_0_uop_ldst;\t// @[dcache.scala:632:25]\n wire [5:0] cache_resp_0_bits_uop_ldst = s2_req_0_uop_ldst;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ldst = s2_req_0_uop_ldst;\t// @[util.scala:101:23]\n reg [5:0] s2_req_0_uop_lrs1;\t// @[dcache.scala:632:25]\n wire [5:0] cache_resp_0_bits_uop_lrs1 = s2_req_0_uop_lrs1;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_lrs1 = s2_req_0_uop_lrs1;\t// @[util.scala:101:23]\n reg [5:0] s2_req_0_uop_lrs2;\t// @[dcache.scala:632:25]\n wire [5:0] cache_resp_0_bits_uop_lrs2 = s2_req_0_uop_lrs2;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_lrs2 = s2_req_0_uop_lrs2;\t// @[util.scala:101:23]\n reg [5:0] s2_req_0_uop_lrs3;\t// @[dcache.scala:632:25]\n wire [5:0] cache_resp_0_bits_uop_lrs3 = s2_req_0_uop_lrs3;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_lrs3 = s2_req_0_uop_lrs3;\t// @[util.scala:101:23]\n reg s2_req_0_uop_ldst_val;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_ldst_val = s2_req_0_uop_ldst_val;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_ldst_val = s2_req_0_uop_ldst_val;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_dst_rtype;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_dst_rtype = s2_req_0_uop_dst_rtype;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_dst_rtype = s2_req_0_uop_dst_rtype;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_lrs1_rtype;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_lrs2_rtype;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype;\t// @[util.scala:101:23]\n reg s2_req_0_uop_frs3_en;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_frs3_en = s2_req_0_uop_frs3_en;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_frs3_en = s2_req_0_uop_frs3_en;\t// @[util.scala:101:23]\n reg s2_req_0_uop_fp_val;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_fp_val = s2_req_0_uop_fp_val;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_fp_val = s2_req_0_uop_fp_val;\t// @[util.scala:101:23]\n reg s2_req_0_uop_fp_single;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_fp_single = s2_req_0_uop_fp_single;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_fp_single = s2_req_0_uop_fp_single;\t// @[util.scala:101:23]\n reg s2_req_0_uop_xcpt_pf_if;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if;\t// @[util.scala:101:23]\n reg s2_req_0_uop_xcpt_ae_if;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if;\t// @[util.scala:101:23]\n reg s2_req_0_uop_xcpt_ma_if;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if;\t// @[util.scala:101:23]\n reg s2_req_0_uop_bp_debug_if;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_bp_debug_if = s2_req_0_uop_bp_debug_if;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_bp_debug_if = s2_req_0_uop_bp_debug_if;\t// @[util.scala:101:23]\n reg s2_req_0_uop_bp_xcpt_if;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_debug_fsrc;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_debug_fsrc = s2_req_0_uop_debug_fsrc;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_debug_fsrc = s2_req_0_uop_debug_fsrc;\t// @[util.scala:101:23]\n reg [1:0] s2_req_0_uop_debug_tsrc;\t// @[dcache.scala:632:25]\n wire [1:0] cache_resp_0_bits_uop_debug_tsrc = s2_req_0_uop_debug_tsrc;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_uop_debug_tsrc = s2_req_0_uop_debug_tsrc;\t// @[util.scala:101:23]\n reg [33:0] s2_req_0_addr;\t// @[dcache.scala:632:25]\n assign io_lsu_nack_0_bits_out_addr = s2_req_0_addr;\t// @[util.scala:101:23]\n reg [63:0] s2_req_0_data;\t// @[dcache.scala:632:25]\n assign io_lsu_nack_0_bits_out_data = s2_req_0_data;\t// @[util.scala:101:23]\n reg s2_req_0_is_hella;\t// @[dcache.scala:632:25]\n wire cache_resp_0_bits_is_hella = s2_req_0_is_hella;\t// @[dcache.scala:632:25, :833:26]\n assign io_lsu_nack_0_bits_out_is_hella = s2_req_0_is_hella;\t// @[util.scala:101:23]\n reg [2:0] s2_type;\t// @[dcache.scala:633:25]\n wire _s2_valid_T = ~io_lsu_s1_kill_0_0;\t// @[dcache.scala:413:7, :636:26]\n wire _s2_valid_T_1 = s1_valid_0 & _s2_valid_T;\t// @[dcache.scala:427:49, :635:39, :636:26]\n wire _s2_valid_T_5 = _s2_valid_T_1;\t// @[dcache.scala:635:39, :636:45]\n wire _s2_valid_T_8 = _s2_valid_T_5;\t// @[dcache.scala:636:45, :637:76]\n wire _s2_valid_T_9 = s1_type == 3'h4;\t// @[dcache.scala:615:32, :639:56]\n wire _s2_valid_T_10 = s2_store_failed & _s2_valid_T_9;\t// @[dcache.scala:603:29, :639:{44,56}]\n wire _s2_valid_T_11 = _s2_valid_T_10 & s1_req_0_uop_uses_stq;\t// @[dcache.scala:600:32, :639:{44,67}]\n wire _s2_valid_T_12 = ~_s2_valid_T_11;\t// @[dcache.scala:639:{26,67}]\n wire _s2_valid_T_13 = _s2_valid_T_8 & _s2_valid_T_12;\t// @[dcache.scala:637:76, :638:72, :639:26]\n reg s2_valid_REG;\t// @[dcache.scala:635:26]\n wire s2_valid_0 = s2_valid_REG;\t// @[dcache.scala:427:49, :635:26]\n reg [1:0] s2_tag_match_way_0;\t// @[dcache.scala:643:33]\n wire s2_tag_match_0 = |s2_tag_match_way_0;\t// @[dcache.scala:643:33, :644:49]\n reg [1:0] s2_hit_state_REG_state;\t// @[dcache.scala:645:93]\n wire [1:0] _s2_hit_state_WIRE_0_state = s2_hit_state_REG_state;\t// @[dcache.scala:622:47, :645:93]\n reg [1:0] s2_hit_state_REG_1_state;\t// @[dcache.scala:645:93]\n wire [1:0] _s2_hit_state_WIRE_1_state_0 = s2_hit_state_REG_1_state;\t// @[dcache.scala:622:47, :645:93]\n wire _s2_hit_state_T = s2_tag_match_way_0[0];\t// @[Mux.scala:32:36]\n wire _s2_data_muxed_T = s2_tag_match_way_0[0];\t// @[Mux.scala:32:36]\n wire _mshrs_io_meta_resp_bits_T = s2_tag_match_way_0[0];\t// @[Mux.scala:32:36]\n wire _s2_hit_state_T_1 = s2_tag_match_way_0[1];\t// @[Mux.scala:32:36]\n wire _s2_data_muxed_T_1 = s2_tag_match_way_0[1];\t// @[Mux.scala:32:36]\n wire _mshrs_io_meta_resp_bits_T_1 = s2_tag_match_way_0[1];\t// @[Mux.scala:32:36]\n wire [1:0] _s2_hit_state_WIRE_2;\t// @[Mux.scala:30:73]\n wire [1:0] s2_hit_state_0_state = _s2_hit_state_WIRE_1_state;\t// @[Mux.scala:30:73]\n wire [1:0] _s2_hit_state_T_2 = _s2_hit_state_T ? _s2_hit_state_WIRE_0_state : 2'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [1:0] _s2_hit_state_T_3 = _s2_hit_state_T_1 ? _s2_hit_state_WIRE_1_state_0 : 2'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [1:0] _s2_hit_state_T_4 = _s2_hit_state_T_2 | _s2_hit_state_T_3;\t// @[Mux.scala:30:73]\n assign _s2_hit_state_WIRE_2 = _s2_hit_state_T_4;\t// @[Mux.scala:30:73]\n assign _s2_hit_state_WIRE_1_state = _s2_hit_state_WIRE_2;\t// @[Mux.scala:30:73]\n wire [1:0] mshrs_io_req_0_bits_old_meta_meta_coh_state = s2_hit_state_0_state;\t// @[HellaCache.scala:305:20]\n wire _GEN_2 = s2_req_0_uop_mem_cmd == 5'h1;\t// @[Consts.scala:90:32]\n wire _s2_has_permission_r_c_cat_T;\t// @[Consts.scala:90:32]\n assign _s2_has_permission_r_c_cat_T = _GEN_2;\t// @[Consts.scala:90:32]\n wire _s2_has_permission_r_c_cat_T_23;\t// @[Consts.scala:90:32]\n assign _s2_has_permission_r_c_cat_T_23 = _GEN_2;\t// @[Consts.scala:90:32]\n wire _s2_new_hit_state_r_c_cat_T;\t// @[Consts.scala:90:32]\n assign _s2_new_hit_state_r_c_cat_T = _GEN_2;\t// @[Consts.scala:90:32]\n wire _s2_new_hit_state_r_c_cat_T_23;\t// @[Consts.scala:90:32]\n assign _s2_new_hit_state_r_c_cat_T_23 = _GEN_2;\t// @[Consts.scala:90:32]\n wire _s2_send_resp_T_3;\t// @[Consts.scala:90:32]\n assign _s2_send_resp_T_3 = _GEN_2;\t// @[Consts.scala:90:32]\n wire _mshrs_io_req_0_valid_T_50;\t// @[Consts.scala:90:32]\n assign _mshrs_io_req_0_valid_T_50 = _GEN_2;\t// @[Consts.scala:90:32]\n wire _s3_valid_T_1;\t// @[Consts.scala:90:32]\n assign _s3_valid_T_1 = _GEN_2;\t// @[Consts.scala:90:32]\n wire _GEN_3 = s2_req_0_uop_mem_cmd == 5'h11;\t// @[Consts.scala:90:49]\n wire _s2_has_permission_r_c_cat_T_1;\t// @[Consts.scala:90:49]\n assign _s2_has_permission_r_c_cat_T_1 = _GEN_3;\t// @[Consts.scala:90:49]\n wire _s2_has_permission_r_c_cat_T_24;\t// @[Consts.scala:90:49]\n assign _s2_has_permission_r_c_cat_T_24 = _GEN_3;\t// @[Consts.scala:90:49]\n wire _s2_new_hit_state_r_c_cat_T_1;\t// @[Consts.scala:90:49]\n assign _s2_new_hit_state_r_c_cat_T_1 = _GEN_3;\t// @[Consts.scala:90:49]\n wire _s2_new_hit_state_r_c_cat_T_24;\t// @[Consts.scala:90:49]\n assign _s2_new_hit_state_r_c_cat_T_24 = _GEN_3;\t// @[Consts.scala:90:49]\n wire _s2_send_resp_T_4;\t// @[Consts.scala:90:49]\n assign _s2_send_resp_T_4 = _GEN_3;\t// @[Consts.scala:90:49]\n wire _mshrs_io_req_0_valid_T_51;\t// @[Consts.scala:90:49]\n assign _mshrs_io_req_0_valid_T_51 = _GEN_3;\t// @[Consts.scala:90:49]\n wire _s3_valid_T_2;\t// @[Consts.scala:90:49]\n assign _s3_valid_T_2 = _GEN_3;\t// @[Consts.scala:90:49]\n wire _s2_has_permission_r_c_cat_T_2 = _s2_has_permission_r_c_cat_T | _s2_has_permission_r_c_cat_T_1;\t// @[Consts.scala:90:{32,42,49}]\n wire _GEN_4 = s2_req_0_uop_mem_cmd == 5'h7;\t// @[Consts.scala:90:66]\n wire _s2_has_permission_r_c_cat_T_3;\t// @[Consts.scala:90:66]\n assign _s2_has_permission_r_c_cat_T_3 = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s2_has_permission_r_c_cat_T_26;\t// @[Consts.scala:90:66]\n assign _s2_has_permission_r_c_cat_T_26 = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s2_new_hit_state_r_c_cat_T_3;\t// @[Consts.scala:90:66]\n assign _s2_new_hit_state_r_c_cat_T_3 = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s2_new_hit_state_r_c_cat_T_26;\t// @[Consts.scala:90:66]\n assign _s2_new_hit_state_r_c_cat_T_26 = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s2_sc_T;\t// @[dcache.scala:664:37]\n assign _s2_sc_T = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s2_send_resp_T_6;\t// @[Consts.scala:90:66]\n assign _s2_send_resp_T_6 = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s2_send_resp_T_30;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_30 = _GEN_4;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_27;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_27 = _GEN_4;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_53;\t// @[Consts.scala:90:66]\n assign _mshrs_io_req_0_valid_T_53 = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s3_valid_T_4;\t// @[Consts.scala:90:66]\n assign _s3_valid_T_4 = _GEN_4;\t// @[Consts.scala:90:66]\n wire _s2_has_permission_r_c_cat_T_4 = _s2_has_permission_r_c_cat_T_2 | _s2_has_permission_r_c_cat_T_3;\t// @[Consts.scala:90:{42,59,66}]\n wire _GEN_5 = s2_req_0_uop_mem_cmd == 5'h4;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_5;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_5 = _GEN_5;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_28;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_28 = _GEN_5;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_5;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_5 = _GEN_5;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_28;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_28 = _GEN_5;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_8;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_8 = _GEN_5;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_34;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_34 = _GEN_5;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_31;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_31 = _GEN_5;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_55;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_55 = _GEN_5;\t// @[package.scala:16:47]\n wire _s3_valid_T_6;\t// @[package.scala:16:47]\n assign _s3_valid_T_6 = _GEN_5;\t// @[package.scala:16:47]\n wire _GEN_6 = s2_req_0_uop_mem_cmd == 5'h9;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_6;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_6 = _GEN_6;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_29;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_29 = _GEN_6;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_6;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_6 = _GEN_6;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_29;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_29 = _GEN_6;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_9;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_9 = _GEN_6;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_35;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_35 = _GEN_6;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_32;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_32 = _GEN_6;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_56;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_56 = _GEN_6;\t// @[package.scala:16:47]\n wire _s3_valid_T_7;\t// @[package.scala:16:47]\n assign _s3_valid_T_7 = _GEN_6;\t// @[package.scala:16:47]\n wire _GEN_7 = s2_req_0_uop_mem_cmd == 5'hA;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_7;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_7 = _GEN_7;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_30;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_30 = _GEN_7;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_7;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_7 = _GEN_7;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_30;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_30 = _GEN_7;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_10;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_10 = _GEN_7;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_36;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_36 = _GEN_7;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_33;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_33 = _GEN_7;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_57;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_57 = _GEN_7;\t// @[package.scala:16:47]\n wire _s3_valid_T_8;\t// @[package.scala:16:47]\n assign _s3_valid_T_8 = _GEN_7;\t// @[package.scala:16:47]\n wire _GEN_8 = s2_req_0_uop_mem_cmd == 5'hB;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_8;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_8 = _GEN_8;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_31;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_31 = _GEN_8;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_8;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_8 = _GEN_8;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_31;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_31 = _GEN_8;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_11;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_11 = _GEN_8;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_37;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_37 = _GEN_8;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_34;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_34 = _GEN_8;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_58;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_58 = _GEN_8;\t// @[package.scala:16:47]\n wire _s3_valid_T_9;\t// @[package.scala:16:47]\n assign _s3_valid_T_9 = _GEN_8;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_9 = _s2_has_permission_r_c_cat_T_5 | _s2_has_permission_r_c_cat_T_6;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_10 = _s2_has_permission_r_c_cat_T_9 | _s2_has_permission_r_c_cat_T_7;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_11 = _s2_has_permission_r_c_cat_T_10 | _s2_has_permission_r_c_cat_T_8;\t// @[package.scala:16:47, :81:59]\n wire _GEN_9 = s2_req_0_uop_mem_cmd == 5'h8;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_12;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_12 = _GEN_9;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_35;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_35 = _GEN_9;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_12;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_12 = _GEN_9;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_35;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_35 = _GEN_9;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_15;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_15 = _GEN_9;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_41;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_41 = _GEN_9;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_38;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_38 = _GEN_9;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_62;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_62 = _GEN_9;\t// @[package.scala:16:47]\n wire _s3_valid_T_13;\t// @[package.scala:16:47]\n assign _s3_valid_T_13 = _GEN_9;\t// @[package.scala:16:47]\n wire _GEN_10 = s2_req_0_uop_mem_cmd == 5'hC;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_13;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_13 = _GEN_10;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_36;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_36 = _GEN_10;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_13;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_13 = _GEN_10;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_36;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_36 = _GEN_10;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_16;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_16 = _GEN_10;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_42;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_42 = _GEN_10;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_39;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_39 = _GEN_10;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_63;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_63 = _GEN_10;\t// @[package.scala:16:47]\n wire _s3_valid_T_14;\t// @[package.scala:16:47]\n assign _s3_valid_T_14 = _GEN_10;\t// @[package.scala:16:47]\n wire _GEN_11 = s2_req_0_uop_mem_cmd == 5'hD;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_14;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_14 = _GEN_11;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_37;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_37 = _GEN_11;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_14;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_14 = _GEN_11;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_37;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_37 = _GEN_11;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_17;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_17 = _GEN_11;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_43;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_43 = _GEN_11;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_40;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_40 = _GEN_11;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_64;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_64 = _GEN_11;\t// @[package.scala:16:47]\n wire _s3_valid_T_15;\t// @[package.scala:16:47]\n assign _s3_valid_T_15 = _GEN_11;\t// @[package.scala:16:47]\n wire _GEN_12 = s2_req_0_uop_mem_cmd == 5'hE;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_15;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_15 = _GEN_12;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_38;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_38 = _GEN_12;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_15;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_15 = _GEN_12;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_38;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_38 = _GEN_12;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_18;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_18 = _GEN_12;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_44;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_44 = _GEN_12;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_41;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_41 = _GEN_12;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_65;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_65 = _GEN_12;\t// @[package.scala:16:47]\n wire _s3_valid_T_16;\t// @[package.scala:16:47]\n assign _s3_valid_T_16 = _GEN_12;\t// @[package.scala:16:47]\n wire _GEN_13 = s2_req_0_uop_mem_cmd == 5'hF;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_16;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_16 = _GEN_13;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_39;\t// @[package.scala:16:47]\n assign _s2_has_permission_r_c_cat_T_39 = _GEN_13;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_16;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_16 = _GEN_13;\t// @[package.scala:16:47]\n wire _s2_new_hit_state_r_c_cat_T_39;\t// @[package.scala:16:47]\n assign _s2_new_hit_state_r_c_cat_T_39 = _GEN_13;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_19;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_19 = _GEN_13;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_45;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_45 = _GEN_13;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_42;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_42 = _GEN_13;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_66;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_66 = _GEN_13;\t// @[package.scala:16:47]\n wire _s3_valid_T_17;\t// @[package.scala:16:47]\n assign _s3_valid_T_17 = _GEN_13;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_17 = _s2_has_permission_r_c_cat_T_12 | _s2_has_permission_r_c_cat_T_13;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_18 = _s2_has_permission_r_c_cat_T_17 | _s2_has_permission_r_c_cat_T_14;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_19 = _s2_has_permission_r_c_cat_T_18 | _s2_has_permission_r_c_cat_T_15;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_20 = _s2_has_permission_r_c_cat_T_19 | _s2_has_permission_r_c_cat_T_16;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_21 = _s2_has_permission_r_c_cat_T_11 | _s2_has_permission_r_c_cat_T_20;\t// @[package.scala:81:59]\n wire _s2_has_permission_r_c_cat_T_22 = _s2_has_permission_r_c_cat_T_4 | _s2_has_permission_r_c_cat_T_21;\t// @[Consts.scala:87:44, :90:{59,76}]\n wire _s2_has_permission_r_c_cat_T_25 = _s2_has_permission_r_c_cat_T_23 | _s2_has_permission_r_c_cat_T_24;\t// @[Consts.scala:90:{32,42,49}]\n wire _s2_has_permission_r_c_cat_T_27 = _s2_has_permission_r_c_cat_T_25 | _s2_has_permission_r_c_cat_T_26;\t// @[Consts.scala:90:{42,59,66}]\n wire _s2_has_permission_r_c_cat_T_32 = _s2_has_permission_r_c_cat_T_28 | _s2_has_permission_r_c_cat_T_29;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_33 = _s2_has_permission_r_c_cat_T_32 | _s2_has_permission_r_c_cat_T_30;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_34 = _s2_has_permission_r_c_cat_T_33 | _s2_has_permission_r_c_cat_T_31;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_40 = _s2_has_permission_r_c_cat_T_35 | _s2_has_permission_r_c_cat_T_36;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_41 = _s2_has_permission_r_c_cat_T_40 | _s2_has_permission_r_c_cat_T_37;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_42 = _s2_has_permission_r_c_cat_T_41 | _s2_has_permission_r_c_cat_T_38;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_43 = _s2_has_permission_r_c_cat_T_42 | _s2_has_permission_r_c_cat_T_39;\t// @[package.scala:16:47, :81:59]\n wire _s2_has_permission_r_c_cat_T_44 = _s2_has_permission_r_c_cat_T_34 | _s2_has_permission_r_c_cat_T_43;\t// @[package.scala:81:59]\n wire _s2_has_permission_r_c_cat_T_45 = _s2_has_permission_r_c_cat_T_27 | _s2_has_permission_r_c_cat_T_44;\t// @[Consts.scala:87:44, :90:{59,76}]\n wire _GEN_14 = s2_req_0_uop_mem_cmd == 5'h3;\t// @[Consts.scala:91:54]\n wire _s2_has_permission_r_c_cat_T_46;\t// @[Consts.scala:91:54]\n assign _s2_has_permission_r_c_cat_T_46 = _GEN_14;\t// @[Consts.scala:91:54]\n wire _s2_new_hit_state_r_c_cat_T_46;\t// @[Consts.scala:91:54]\n assign _s2_new_hit_state_r_c_cat_T_46 = _GEN_14;\t// @[Consts.scala:91:54]\n wire _mshrs_io_req_0_valid_T_22;\t// @[Consts.scala:88:52]\n assign _mshrs_io_req_0_valid_T_22 = _GEN_14;\t// @[Consts.scala:88:52, :91:54]\n wire _s2_has_permission_r_c_cat_T_47 = _s2_has_permission_r_c_cat_T_45 | _s2_has_permission_r_c_cat_T_46;\t// @[Consts.scala:90:76, :91:{47,54}]\n wire _GEN_15 = s2_req_0_uop_mem_cmd == 5'h6;\t// @[Consts.scala:91:71]\n wire _s2_has_permission_r_c_cat_T_48;\t// @[Consts.scala:91:71]\n assign _s2_has_permission_r_c_cat_T_48 = _GEN_15;\t// @[Consts.scala:91:71]\n wire _s2_new_hit_state_r_c_cat_T_48;\t// @[Consts.scala:91:71]\n assign _s2_new_hit_state_r_c_cat_T_48 = _GEN_15;\t// @[Consts.scala:91:71]\n wire _s2_lr_T;\t// @[dcache.scala:663:37]\n assign _s2_lr_T = _GEN_15;\t// @[Consts.scala:91:71]\n wire _s2_send_resp_T_29;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_29 = _GEN_15;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_26;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_26 = _GEN_15;\t// @[package.scala:16:47]\n wire _s2_has_permission_r_c_cat_T_49 = _s2_has_permission_r_c_cat_T_47 | _s2_has_permission_r_c_cat_T_48;\t// @[Consts.scala:91:{47,64,71}]\n wire [1:0] s2_has_permission_r_c = {_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49};\t// @[Metadata.scala:29:18]\n wire [3:0] _s2_has_permission_r_T = {s2_has_permission_r_c, s2_hit_state_0_state};\t// @[Metadata.scala:29:18, :58:19]\n wire _s2_has_permission_r_T_25 = _s2_has_permission_r_T == 4'hC;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_has_permission_r_T_27 = {1'h0, _s2_has_permission_r_T_25};\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_28 = _s2_has_permission_r_T == 4'hD;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_has_permission_r_T_30 = _s2_has_permission_r_T_28 ? 2'h2 : _s2_has_permission_r_T_27;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_31 = _s2_has_permission_r_T == 4'h4;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_has_permission_r_T_33 = _s2_has_permission_r_T_31 ? 2'h1 : _s2_has_permission_r_T_30;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_34 = _s2_has_permission_r_T == 4'h5;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_has_permission_r_T_36 = _s2_has_permission_r_T_34 ? 2'h2 : _s2_has_permission_r_T_33;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_37 = _s2_has_permission_r_T == 4'h0;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_has_permission_r_T_39 = _s2_has_permission_r_T_37 ? 2'h0 : _s2_has_permission_r_T_36;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_40 = _s2_has_permission_r_T == 4'hE;\t// @[Misc.scala:49:20]\n wire _s2_has_permission_r_T_41 = _s2_has_permission_r_T_40;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_has_permission_r_T_42 = _s2_has_permission_r_T_40 ? 2'h3 : _s2_has_permission_r_T_39;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_43 = &_s2_has_permission_r_T;\t// @[Misc.scala:49:20]\n wire _s2_has_permission_r_T_44 = _s2_has_permission_r_T_43 | _s2_has_permission_r_T_41;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_has_permission_r_T_45 = _s2_has_permission_r_T_43 ? 2'h3 : _s2_has_permission_r_T_42;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_46 = _s2_has_permission_r_T == 4'h6;\t// @[Misc.scala:49:20]\n wire _s2_has_permission_r_T_47 = _s2_has_permission_r_T_46 | _s2_has_permission_r_T_44;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_has_permission_r_T_48 = _s2_has_permission_r_T_46 ? 2'h2 : _s2_has_permission_r_T_45;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_49 = _s2_has_permission_r_T == 4'h7;\t// @[Misc.scala:49:20]\n wire _s2_has_permission_r_T_50 = _s2_has_permission_r_T_49 | _s2_has_permission_r_T_47;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_has_permission_r_T_51 = _s2_has_permission_r_T_49 ? 2'h3 : _s2_has_permission_r_T_48;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_52 = _s2_has_permission_r_T == 4'h1;\t// @[Misc.scala:49:20]\n wire _s2_has_permission_r_T_53 = _s2_has_permission_r_T_52 | _s2_has_permission_r_T_50;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_has_permission_r_T_54 = _s2_has_permission_r_T_52 ? 2'h1 : _s2_has_permission_r_T_51;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_55 = _s2_has_permission_r_T == 4'h2;\t// @[Misc.scala:49:20]\n wire _s2_has_permission_r_T_56 = _s2_has_permission_r_T_55 | _s2_has_permission_r_T_53;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_has_permission_r_T_57 = _s2_has_permission_r_T_55 ? 2'h2 : _s2_has_permission_r_T_54;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_has_permission_r_T_58 = _s2_has_permission_r_T == 4'h3;\t// @[Misc.scala:49:20]\n wire s2_has_permission_r_1 = _s2_has_permission_r_T_58 | _s2_has_permission_r_T_56;\t// @[Misc.scala:35:9, :49:20]\n wire s2_has_permission_0 = s2_has_permission_r_1;\t// @[Misc.scala:35:9]\n wire [1:0] s2_has_permission_r_2 = _s2_has_permission_r_T_58 ? 2'h3 : _s2_has_permission_r_T_57;\t// @[Misc.scala:35:36, :49:20]\n wire [1:0] s2_has_permission_meta_state = s2_has_permission_r_2;\t// @[Misc.scala:35:36]\n wire _s2_new_hit_state_r_c_cat_T_2 = _s2_new_hit_state_r_c_cat_T | _s2_new_hit_state_r_c_cat_T_1;\t// @[Consts.scala:90:{32,42,49}]\n wire _s2_new_hit_state_r_c_cat_T_4 = _s2_new_hit_state_r_c_cat_T_2 | _s2_new_hit_state_r_c_cat_T_3;\t// @[Consts.scala:90:{42,59,66}]\n wire _s2_new_hit_state_r_c_cat_T_9 = _s2_new_hit_state_r_c_cat_T_5 | _s2_new_hit_state_r_c_cat_T_6;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_10 = _s2_new_hit_state_r_c_cat_T_9 | _s2_new_hit_state_r_c_cat_T_7;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_11 = _s2_new_hit_state_r_c_cat_T_10 | _s2_new_hit_state_r_c_cat_T_8;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_17 = _s2_new_hit_state_r_c_cat_T_12 | _s2_new_hit_state_r_c_cat_T_13;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_18 = _s2_new_hit_state_r_c_cat_T_17 | _s2_new_hit_state_r_c_cat_T_14;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_19 = _s2_new_hit_state_r_c_cat_T_18 | _s2_new_hit_state_r_c_cat_T_15;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_20 = _s2_new_hit_state_r_c_cat_T_19 | _s2_new_hit_state_r_c_cat_T_16;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_21 = _s2_new_hit_state_r_c_cat_T_11 | _s2_new_hit_state_r_c_cat_T_20;\t// @[package.scala:81:59]\n wire _s2_new_hit_state_r_c_cat_T_22 = _s2_new_hit_state_r_c_cat_T_4 | _s2_new_hit_state_r_c_cat_T_21;\t// @[Consts.scala:87:44, :90:{59,76}]\n wire _s2_new_hit_state_r_c_cat_T_25 = _s2_new_hit_state_r_c_cat_T_23 | _s2_new_hit_state_r_c_cat_T_24;\t// @[Consts.scala:90:{32,42,49}]\n wire _s2_new_hit_state_r_c_cat_T_27 = _s2_new_hit_state_r_c_cat_T_25 | _s2_new_hit_state_r_c_cat_T_26;\t// @[Consts.scala:90:{42,59,66}]\n wire _s2_new_hit_state_r_c_cat_T_32 = _s2_new_hit_state_r_c_cat_T_28 | _s2_new_hit_state_r_c_cat_T_29;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_33 = _s2_new_hit_state_r_c_cat_T_32 | _s2_new_hit_state_r_c_cat_T_30;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_34 = _s2_new_hit_state_r_c_cat_T_33 | _s2_new_hit_state_r_c_cat_T_31;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_40 = _s2_new_hit_state_r_c_cat_T_35 | _s2_new_hit_state_r_c_cat_T_36;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_41 = _s2_new_hit_state_r_c_cat_T_40 | _s2_new_hit_state_r_c_cat_T_37;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_42 = _s2_new_hit_state_r_c_cat_T_41 | _s2_new_hit_state_r_c_cat_T_38;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_43 = _s2_new_hit_state_r_c_cat_T_42 | _s2_new_hit_state_r_c_cat_T_39;\t// @[package.scala:16:47, :81:59]\n wire _s2_new_hit_state_r_c_cat_T_44 = _s2_new_hit_state_r_c_cat_T_34 | _s2_new_hit_state_r_c_cat_T_43;\t// @[package.scala:81:59]\n wire _s2_new_hit_state_r_c_cat_T_45 = _s2_new_hit_state_r_c_cat_T_27 | _s2_new_hit_state_r_c_cat_T_44;\t// @[Consts.scala:87:44, :90:{59,76}]\n wire _s2_new_hit_state_r_c_cat_T_47 = _s2_new_hit_state_r_c_cat_T_45 | _s2_new_hit_state_r_c_cat_T_46;\t// @[Consts.scala:90:76, :91:{47,54}]\n wire _s2_new_hit_state_r_c_cat_T_49 = _s2_new_hit_state_r_c_cat_T_47 | _s2_new_hit_state_r_c_cat_T_48;\t// @[Consts.scala:91:{47,64,71}]\n wire [1:0] s2_new_hit_state_r_c = {_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49};\t// @[Metadata.scala:29:18]\n wire [3:0] _s2_new_hit_state_r_T = {s2_new_hit_state_r_c, s2_hit_state_0_state};\t// @[Metadata.scala:29:18, :58:19]\n wire _s2_new_hit_state_r_T_25 = _s2_new_hit_state_r_T == 4'hC;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_new_hit_state_r_T_27 = {1'h0, _s2_new_hit_state_r_T_25};\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_28 = _s2_new_hit_state_r_T == 4'hD;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_new_hit_state_r_T_30 = _s2_new_hit_state_r_T_28 ? 2'h2 : _s2_new_hit_state_r_T_27;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_31 = _s2_new_hit_state_r_T == 4'h4;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_new_hit_state_r_T_33 = _s2_new_hit_state_r_T_31 ? 2'h1 : _s2_new_hit_state_r_T_30;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_34 = _s2_new_hit_state_r_T == 4'h5;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_new_hit_state_r_T_36 = _s2_new_hit_state_r_T_34 ? 2'h2 : _s2_new_hit_state_r_T_33;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_37 = _s2_new_hit_state_r_T == 4'h0;\t// @[Misc.scala:49:20]\n wire [1:0] _s2_new_hit_state_r_T_39 = _s2_new_hit_state_r_T_37 ? 2'h0 : _s2_new_hit_state_r_T_36;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_40 = _s2_new_hit_state_r_T == 4'hE;\t// @[Misc.scala:49:20]\n wire _s2_new_hit_state_r_T_41 = _s2_new_hit_state_r_T_40;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_new_hit_state_r_T_42 = _s2_new_hit_state_r_T_40 ? 2'h3 : _s2_new_hit_state_r_T_39;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_43 = &_s2_new_hit_state_r_T;\t// @[Misc.scala:49:20]\n wire _s2_new_hit_state_r_T_44 = _s2_new_hit_state_r_T_43 | _s2_new_hit_state_r_T_41;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_new_hit_state_r_T_45 = _s2_new_hit_state_r_T_43 ? 2'h3 : _s2_new_hit_state_r_T_42;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_46 = _s2_new_hit_state_r_T == 4'h6;\t// @[Misc.scala:49:20]\n wire _s2_new_hit_state_r_T_47 = _s2_new_hit_state_r_T_46 | _s2_new_hit_state_r_T_44;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_new_hit_state_r_T_48 = _s2_new_hit_state_r_T_46 ? 2'h2 : _s2_new_hit_state_r_T_45;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_49 = _s2_new_hit_state_r_T == 4'h7;\t// @[Misc.scala:49:20]\n wire _s2_new_hit_state_r_T_50 = _s2_new_hit_state_r_T_49 | _s2_new_hit_state_r_T_47;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_new_hit_state_r_T_51 = _s2_new_hit_state_r_T_49 ? 2'h3 : _s2_new_hit_state_r_T_48;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_52 = _s2_new_hit_state_r_T == 4'h1;\t// @[Misc.scala:49:20]\n wire _s2_new_hit_state_r_T_53 = _s2_new_hit_state_r_T_52 | _s2_new_hit_state_r_T_50;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_new_hit_state_r_T_54 = _s2_new_hit_state_r_T_52 ? 2'h1 : _s2_new_hit_state_r_T_51;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_55 = _s2_new_hit_state_r_T == 4'h2;\t// @[Misc.scala:49:20]\n wire _s2_new_hit_state_r_T_56 = _s2_new_hit_state_r_T_55 | _s2_new_hit_state_r_T_53;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] _s2_new_hit_state_r_T_57 = _s2_new_hit_state_r_T_55 ? 2'h2 : _s2_new_hit_state_r_T_54;\t// @[Misc.scala:35:36, :49:20]\n wire _s2_new_hit_state_r_T_58 = _s2_new_hit_state_r_T == 4'h3;\t// @[Misc.scala:49:20]\n wire s2_new_hit_state_r_1 = _s2_new_hit_state_r_T_58 | _s2_new_hit_state_r_T_56;\t// @[Misc.scala:35:9, :49:20]\n wire [1:0] s2_new_hit_state_r_2 = _s2_new_hit_state_r_T_58 ? 2'h3 : _s2_new_hit_state_r_T_57;\t// @[Misc.scala:35:36, :49:20]\n wire [1:0] s2_new_hit_state_meta_state = s2_new_hit_state_r_2;\t// @[Misc.scala:35:36]\n wire [1:0] s2_new_hit_state_0_state = s2_new_hit_state_meta_state;\t// @[Metadata.scala:160:20]\n wire _s2_hit_T = s2_tag_match_0 & s2_has_permission_0;\t// @[dcache.scala:427:49, :644:49, :649:47]\n wire _s2_hit_T_1 = s2_hit_state_0_state == s2_new_hit_state_0_state;\t// @[Metadata.scala:46:46]\n wire _s2_hit_T_2 = _s2_hit_T & _s2_hit_T_1;\t// @[Metadata.scala:46:46]\n wire _s2_hit_T_3 = ~_mshrs_io_block_hit_0;\t// @[dcache.scala:433:21, :649:117]\n wire _s2_hit_T_4 = _s2_hit_T_2 & _s2_hit_T_3;\t// @[dcache.scala:649:{71,114,117}]\n wire _T_67 = s2_type == 3'h0;\t// @[package.scala:16:47]\n wire _s2_hit_T_5;\t// @[package.scala:16:47]\n assign _s2_hit_T_5 = _T_67;\t// @[package.scala:16:47]\n wire _s2_lr_T_2;\t// @[dcache.scala:663:83]\n assign _s2_lr_T_2 = _T_67;\t// @[package.scala:16:47]\n wire _s2_sc_T_2;\t// @[dcache.scala:664:83]\n assign _s2_sc_T_2 = _T_67;\t// @[package.scala:16:47]\n wire _s2_hit_T_6 = s2_type == 3'h2;\t// @[package.scala:16:47]\n wire _s2_hit_T_7 = _s2_hit_T_5 | _s2_hit_T_6;\t// @[package.scala:16:47, :81:59]\n wire _s2_hit_T_8 = _s2_hit_T_4 | _s2_hit_T_7;\t// @[package.scala:81:59]\n wire s2_hit_0 = _s2_hit_T_8;\t// @[dcache.scala:427:49, :649:141]\n wire s2_nack_0;\t// @[dcache.scala:650:21]\n reg s2_wb_idx_matches_0;\t// @[dcache.scala:654:34]\n reg [33:0] debug_sc_fail_addr;\t// @[dcache.scala:657:35]\n reg [7:0] debug_sc_fail_cnt;\t// @[dcache.scala:658:35]\n reg [6:0] lrsc_count;\t// @[dcache.scala:660:27]\n wire lrsc_valid = |(lrsc_count[6:2]);\t// @[dcache.scala:660:27, :661:31]\n reg [27:0] lrsc_addr;\t// @[dcache.scala:662:23]\n reg s2_lr_REG;\t// @[dcache.scala:663:59]\n wire _s2_lr_T_1 = ~s2_lr_REG;\t// @[dcache.scala:663:{51,59}]\n wire _s2_lr_T_3 = _s2_lr_T_1 | _s2_lr_T_2;\t// @[dcache.scala:663:{51,72,83}]\n wire s2_lr = _s2_lr_T & _s2_lr_T_3;\t// @[dcache.scala:663:{37,47,72}]\n reg s2_sc_REG;\t// @[dcache.scala:664:59]\n wire _s2_sc_T_1 = ~s2_sc_REG;\t// @[dcache.scala:664:{51,59}]\n wire _s2_sc_T_3 = _s2_sc_T_1 | _s2_sc_T_2;\t// @[dcache.scala:664:{51,72,83}]\n wire s2_sc = _s2_sc_T & _s2_sc_T_3;\t// @[dcache.scala:664:{37,47,72}]\n wire cache_resp_0_bits_data_doZero_2 = s2_sc;\t// @[AMOALU.scala:43:31]\n wire [27:0] _s2_lrsc_addr_match_T = s2_req_0_addr[33:6];\t// @[dcache.scala:632:25, :665:86]\n wire [27:0] _lrsc_addr_T = s2_req_0_addr[33:6];\t// @[dcache.scala:632:25, :665:86, :672:35]\n wire _s2_lrsc_addr_match_T_1 = lrsc_addr == _s2_lrsc_addr_match_T;\t// @[dcache.scala:662:23, :665:{66,86}]\n wire _s2_lrsc_addr_match_T_2 = lrsc_valid & _s2_lrsc_addr_match_T_1;\t// @[dcache.scala:661:31, :665:{53,66}]\n wire s2_lrsc_addr_match_0 = _s2_lrsc_addr_match_T_2;\t// @[dcache.scala:427:49, :665:53]\n wire _s2_sc_fail_T = ~s2_lrsc_addr_match_0;\t// @[dcache.scala:427:49, :666:29]\n wire s2_sc_fail = s2_sc & _s2_sc_fail_T;\t// @[dcache.scala:664:47, :666:{26,29}]\n wire [7:0] _lrsc_count_T = {1'h0, lrsc_count} - 8'h1;\t// @[dcache.scala:660:27, :667:54]\n wire [6:0] _lrsc_count_T_1 = _lrsc_count_T[6:0];\t// @[dcache.scala:667:54]\n wire _mshrs_io_req_0_valid_T_10 = s2_type == 3'h4;\t// @[package.scala:16:47]\n wire [8:0] _debug_sc_fail_cnt_T = {1'h0, debug_sc_fail_cnt} + 9'h1;\t// @[dcache.scala:658:35, :692:48]\n wire [7:0] _debug_sc_fail_cnt_T_1 = _debug_sc_fail_cnt_T[7:0];\t// @[dcache.scala:692:48]\n wire [63:0] s2_data_0_0;\t// @[dcache.scala:705:21]\n wire [63:0] s2_data_0_1;\t// @[dcache.scala:705:21]\n wire [63:0] _s2_data_muxed_T_2 = _s2_data_muxed_T ? s2_data_0_0 : 64'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [63:0] _s2_data_muxed_T_3 = _s2_data_muxed_T_1 ? s2_data_0_1 : 64'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [63:0] _s2_data_muxed_T_4 = _s2_data_muxed_T_2 | _s2_data_muxed_T_3;\t// @[Mux.scala:30:73]\n wire [63:0] _s2_data_muxed_WIRE = _s2_data_muxed_T_4;\t// @[Mux.scala:30:73]\n wire [63:0] s2_data_muxed_0 = _s2_data_muxed_WIRE;\t// @[Mux.scala:30:73]\n wire [63:0] _s2_data_word_prebypass_T_1 = s2_data_muxed_0;\t// @[dcache.scala:427:49, :825:63]\n wire replace;\t// @[Replacement.scala:37:29]\n wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0};\t// @[PRNG.scala:91:22, :95:17]\n wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2};\t// @[PRNG.scala:91:22, :95:17]\n wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo};\t// @[PRNG.scala:95:17]\n wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4};\t// @[PRNG.scala:91:22, :95:17]\n wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6};\t// @[PRNG.scala:91:22, :95:17]\n wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo};\t// @[PRNG.scala:95:17]\n wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo};\t// @[PRNG.scala:95:17]\n wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8};\t// @[PRNG.scala:91:22, :95:17]\n wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10};\t// @[PRNG.scala:91:22, :95:17]\n wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo};\t// @[PRNG.scala:95:17]\n wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12};\t// @[PRNG.scala:91:22, :95:17]\n wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14};\t// @[PRNG.scala:91:22, :95:17]\n wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo};\t// @[PRNG.scala:95:17]\n wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo};\t// @[PRNG.scala:95:17]\n wire [15:0] lfsr = {lfsr_hi, lfsr_lo};\t// @[PRNG.scala:95:17]\n wire _s1_replaced_way_en_T = lfsr[0];\t// @[PRNG.scala:95:17]\n wire _s2_replaced_way_en_T = lfsr[0];\t// @[PRNG.scala:95:17]\n wire [1:0] s1_replaced_way_en = 2'h1 << _s1_replaced_way_en_T;\t// @[OneHot.scala:58:35]\n reg s2_replaced_way_en_REG;\t// @[dcache.scala:718:44]\n wire [1:0] s2_replaced_way_en = 2'h1 << s2_replaced_way_en_REG;\t// @[OneHot.scala:58:35]\n reg [1:0] s2_repl_meta_REG_coh_state;\t// @[dcache.scala:719:88]\n wire [1:0] _s2_repl_meta_WIRE_0_coh_state = s2_repl_meta_REG_coh_state;\t// @[dcache.scala:622:47, :719:88]\n reg [21:0] s2_repl_meta_REG_tag;\t// @[dcache.scala:719:88]\n wire [21:0] _s2_repl_meta_WIRE_0_tag = s2_repl_meta_REG_tag;\t// @[dcache.scala:622:47, :719:88]\n reg [1:0] s2_repl_meta_REG_1_coh_state;\t// @[dcache.scala:719:88]\n wire [1:0] _s2_repl_meta_WIRE_1_coh_state_0 = s2_repl_meta_REG_1_coh_state;\t// @[dcache.scala:622:47, :719:88]\n reg [21:0] s2_repl_meta_REG_1_tag;\t// @[dcache.scala:719:88]\n wire [21:0] _s2_repl_meta_WIRE_1_tag_0 = s2_repl_meta_REG_1_tag;\t// @[dcache.scala:622:47, :719:88]\n wire _s2_repl_meta_T = s2_replaced_way_en[0];\t// @[OneHot.scala:58:35]\n wire _s2_repl_meta_T_1 = s2_replaced_way_en[1];\t// @[OneHot.scala:58:35]\n wire [1:0] _s2_repl_meta_WIRE_3_state;\t// @[Mux.scala:30:73]\n wire [21:0] _s2_repl_meta_WIRE_2;\t// @[Mux.scala:30:73]\n wire [1:0] s2_repl_meta_0_coh_state = _s2_repl_meta_WIRE_1_coh_state;\t// @[Mux.scala:30:73]\n wire [21:0] s2_repl_meta_0_tag = _s2_repl_meta_WIRE_1_tag;\t// @[Mux.scala:30:73]\n wire [21:0] _s2_repl_meta_T_2 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_tag : 22'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [21:0] _s2_repl_meta_T_3 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_tag_0 : 22'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [21:0] _s2_repl_meta_T_4 = _s2_repl_meta_T_2 | _s2_repl_meta_T_3;\t// @[Mux.scala:30:73]\n assign _s2_repl_meta_WIRE_2 = _s2_repl_meta_T_4;\t// @[Mux.scala:30:73]\n assign _s2_repl_meta_WIRE_1_tag = _s2_repl_meta_WIRE_2;\t// @[Mux.scala:30:73]\n wire [1:0] _s2_repl_meta_WIRE_4;\t// @[Mux.scala:30:73]\n assign _s2_repl_meta_WIRE_1_coh_state = _s2_repl_meta_WIRE_3_state;\t// @[Mux.scala:30:73]\n wire [1:0] _s2_repl_meta_T_5 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_coh_state : 2'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [1:0] _s2_repl_meta_T_6 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_coh_state_0 : 2'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [1:0] _s2_repl_meta_T_7 = _s2_repl_meta_T_5 | _s2_repl_meta_T_6;\t// @[Mux.scala:30:73]\n assign _s2_repl_meta_WIRE_4 = _s2_repl_meta_T_7;\t// @[Mux.scala:30:73]\n assign _s2_repl_meta_WIRE_3_state = _s2_repl_meta_WIRE_4;\t// @[Mux.scala:30:73]\n wire [21:0] mshrs_io_req_0_bits_old_meta_meta_tag = s2_repl_meta_0_tag;\t// @[HellaCache.scala:305:20]\n reg s2_nack_hit_0;\t// @[dcache.scala:722:31]\n wire _GEN_16 = s2_valid_0 & s2_hit_0;\t// @[dcache.scala:427:49, :724:50]\n wire _s2_nack_victim_T;\t// @[dcache.scala:724:50]\n assign _s2_nack_victim_T = _GEN_16;\t// @[dcache.scala:724:50]\n wire _s3_valid_T;\t// @[dcache.scala:871:38]\n assign _s3_valid_T = _GEN_16;\t// @[dcache.scala:724:50, :871:38]\n wire _s2_nack_victim_T_1 = _s2_nack_victim_T & _mshrs_io_secondary_miss_0;\t// @[dcache.scala:433:21, :724:{50,64}]\n wire s2_nack_victim_0 = _s2_nack_victim_T_1;\t// @[dcache.scala:427:49, :724:64]\n wire _s2_nack_miss_T = ~s2_hit_0;\t// @[dcache.scala:427:49, :651:36, :726:53]\n wire _s2_nack_miss_T_1 = s2_valid_0 & _s2_nack_miss_T;\t// @[dcache.scala:427:49, :726:{50,53}]\n wire _s2_nack_miss_T_2 = ~_mshrs_io_req_0_ready;\t// @[dcache.scala:433:21, :726:67]\n wire _s2_nack_miss_T_3 = _s2_nack_miss_T_1 & _s2_nack_miss_T_2;\t// @[dcache.scala:726:{50,64,67}]\n wire s2_nack_miss_0 = _s2_nack_miss_T_3;\t// @[dcache.scala:427:49, :726:64]\n wire _s2_nack_wb_T = ~s2_hit_0;\t// @[dcache.scala:427:49, :651:36, :730:53]\n wire _s2_nack_wb_T_1 = s2_valid_0 & _s2_nack_wb_T;\t// @[dcache.scala:427:49, :730:{50,53}]\n wire _s2_nack_wb_T_2 = _s2_nack_wb_T_1 & s2_wb_idx_matches_0;\t// @[dcache.scala:654:34, :730:{50,64}]\n wire s2_nack_wb_0 = _s2_nack_wb_T_2;\t// @[dcache.scala:427:49, :730:64]\n assign s2_nack_0 = (s2_nack_miss_0 | s2_nack_hit_0 | s2_nack_victim_0 | s2_nack_wb_0) & (|s2_type);\t// @[dcache.scala:427:49, :633:25, :650:21, :722:31, :732:{55,73,113,131,142}]\n reg s2_send_resp_REG;\t// @[dcache.scala:733:44]\n wire _s2_send_resp_T = ~s2_nack_0;\t// @[dcache.scala:650:21, :668:60, :733:73]\n wire _s2_send_resp_T_1 = s2_send_resp_REG & _s2_send_resp_T;\t// @[dcache.scala:733:{44,70,73}]\n wire _mshrs_io_req_0_valid_T_74;\t// @[dcache.scala:754:77]\n wire _T_73 = _mshrs_io_req_0_ready & _mshrs_io_req_0_valid_T_74;\t// @[Decoupled.scala:51:35]\n assign replace = _T_73;\t// @[Decoupled.scala:51:35]\n wire _s2_send_resp_T_2;\t// @[Decoupled.scala:51:35]\n assign _s2_send_resp_T_2 = _T_73;\t// @[Decoupled.scala:51:35]\n wire _s2_send_resp_T_5 = _s2_send_resp_T_3 | _s2_send_resp_T_4;\t// @[Consts.scala:90:{32,42,49}]\n wire _s2_send_resp_T_7 = _s2_send_resp_T_5 | _s2_send_resp_T_6;\t// @[Consts.scala:90:{42,59,66}]\n wire _s2_send_resp_T_12 = _s2_send_resp_T_8 | _s2_send_resp_T_9;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_13 = _s2_send_resp_T_12 | _s2_send_resp_T_10;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_14 = _s2_send_resp_T_13 | _s2_send_resp_T_11;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_20 = _s2_send_resp_T_15 | _s2_send_resp_T_16;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_21 = _s2_send_resp_T_20 | _s2_send_resp_T_17;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_22 = _s2_send_resp_T_21 | _s2_send_resp_T_18;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_23 = _s2_send_resp_T_22 | _s2_send_resp_T_19;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_24 = _s2_send_resp_T_14 | _s2_send_resp_T_23;\t// @[package.scala:81:59]\n wire _s2_send_resp_T_25 = _s2_send_resp_T_7 | _s2_send_resp_T_24;\t// @[Consts.scala:87:44, :90:{59,76}]\n wire _s2_send_resp_T_26 = _s2_send_resp_T_2 & _s2_send_resp_T_25;\t// @[Decoupled.scala:51:35]\n wire _GEN_17 = s2_req_0_uop_mem_cmd == 5'h0;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_27;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_27 = _GEN_17;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_24;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_24 = _GEN_17;\t// @[package.scala:16:47]\n wire _GEN_18 = s2_req_0_uop_mem_cmd == 5'h10;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_28;\t// @[package.scala:16:47]\n assign _s2_send_resp_T_28 = _GEN_18;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_25;\t// @[package.scala:16:47]\n assign _mshrs_io_req_0_valid_T_25 = _GEN_18;\t// @[package.scala:16:47]\n wire _s2_send_resp_T_31 = _s2_send_resp_T_27 | _s2_send_resp_T_28;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_32 = _s2_send_resp_T_31 | _s2_send_resp_T_29;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_33 = _s2_send_resp_T_32 | _s2_send_resp_T_30;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_38 = _s2_send_resp_T_34 | _s2_send_resp_T_35;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_39 = _s2_send_resp_T_38 | _s2_send_resp_T_36;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_40 = _s2_send_resp_T_39 | _s2_send_resp_T_37;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_46 = _s2_send_resp_T_41 | _s2_send_resp_T_42;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_47 = _s2_send_resp_T_46 | _s2_send_resp_T_43;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_48 = _s2_send_resp_T_47 | _s2_send_resp_T_44;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_49 = _s2_send_resp_T_48 | _s2_send_resp_T_45;\t// @[package.scala:16:47, :81:59]\n wire _s2_send_resp_T_50 = _s2_send_resp_T_40 | _s2_send_resp_T_49;\t// @[package.scala:81:59]\n wire _s2_send_resp_T_51 = _s2_send_resp_T_33 | _s2_send_resp_T_50;\t// @[package.scala:81:59]\n wire _s2_send_resp_T_52 = ~_s2_send_resp_T_51;\t// @[Consts.scala:89:68]\n wire _s2_send_resp_T_53 = _s2_send_resp_T_26 & _s2_send_resp_T_52;\t// @[dcache.scala:734:{59,93,96}]\n wire _s2_send_resp_T_54 = s2_hit_0 | _s2_send_resp_T_53;\t// @[dcache.scala:427:49, :734:{34,93}]\n wire _s2_send_resp_T_55 = _s2_send_resp_T_1 & _s2_send_resp_T_54;\t// @[dcache.scala:733:{70,85}, :734:34]\n wire s2_send_resp_0 = _s2_send_resp_T_55;\t// @[dcache.scala:427:49, :733:85]\n reg s2_send_nack_REG;\t// @[dcache.scala:735:44]\n wire _s2_send_nack_T = s2_send_nack_REG & s2_nack_0;\t// @[dcache.scala:650:21, :735:{44,70}]\n wire s2_send_nack_0 = _s2_send_nack_T;\t// @[dcache.scala:427:49, :735:70]\n wire _s2_store_failed_T = s2_valid_0 & s2_nack_0;\t// @[dcache.scala:427:49, :650:21, :742:34]\n wire _s2_store_failed_T_1 = _s2_store_failed_T & s2_send_nack_0;\t// @[dcache.scala:427:49, :742:{34,48}]\n assign _s2_store_failed_T_2 = _s2_store_failed_T_1 & s2_req_0_uop_uses_stq;\t// @[dcache.scala:632:25, :742:{48,67}]\n assign s2_store_failed = _s2_store_failed_T_2;\t// @[dcache.scala:603:29, :742:67]\n wire _mshrs_io_req_0_valid_T = ~s2_hit_0;\t// @[dcache.scala:427:49, :651:36, :747:29]\n wire _mshrs_io_req_0_valid_T_1 = s2_valid_0 & _mshrs_io_req_0_valid_T;\t// @[dcache.scala:427:49, :746:51, :747:29]\n wire _mshrs_io_req_0_valid_T_2 = ~s2_nack_hit_0;\t// @[dcache.scala:722:31, :748:29]\n wire _mshrs_io_req_0_valid_T_3 = _mshrs_io_req_0_valid_T_1 & _mshrs_io_req_0_valid_T_2;\t// @[dcache.scala:746:51, :747:51, :748:29]\n wire _mshrs_io_req_0_valid_T_4 = ~s2_nack_victim_0;\t// @[dcache.scala:427:49, :749:29]\n wire _mshrs_io_req_0_valid_T_5 = _mshrs_io_req_0_valid_T_3 & _mshrs_io_req_0_valid_T_4;\t// @[dcache.scala:747:51, :748:51, :749:29]\n wire _mshrs_io_req_0_valid_T_7 = _mshrs_io_req_0_valid_T_5;\t// @[dcache.scala:748:51, :749:51]\n wire _mshrs_io_req_0_valid_T_8 = ~s2_nack_wb_0;\t// @[dcache.scala:427:49, :751:29]\n wire _mshrs_io_req_0_valid_T_9 = _mshrs_io_req_0_valid_T_7 & _mshrs_io_req_0_valid_T_8;\t// @[dcache.scala:749:51, :750:51, :751:29]\n wire _mshrs_io_req_0_valid_T_11 = s2_type == 3'h5;\t// @[package.scala:16:47]\n wire _mshrs_io_req_0_valid_T_12 = _mshrs_io_req_0_valid_T_10 | _mshrs_io_req_0_valid_T_11;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_13 = _mshrs_io_req_0_valid_T_9 & _mshrs_io_req_0_valid_T_12;\t// @[package.scala:81:59]\n wire _mshrs_io_req_0_valid_T_17 = _mshrs_io_req_0_valid_T_13;\t// @[dcache.scala:751:51, :752:77]\n wire _mshrs_io_req_0_valid_T_20 = _mshrs_io_req_0_valid_T_17;\t// @[dcache.scala:752:77, :753:79]\n wire _mshrs_io_req_0_valid_T_21 = s2_req_0_uop_mem_cmd == 5'h2;\t// @[Consts.scala:88:35]\n wire _mshrs_io_req_0_valid_T_23 = _mshrs_io_req_0_valid_T_21 | _mshrs_io_req_0_valid_T_22;\t// @[Consts.scala:88:{35,45,52}]\n wire _mshrs_io_req_0_valid_T_28 = _mshrs_io_req_0_valid_T_24 | _mshrs_io_req_0_valid_T_25;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_29 = _mshrs_io_req_0_valid_T_28 | _mshrs_io_req_0_valid_T_26;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_30 = _mshrs_io_req_0_valid_T_29 | _mshrs_io_req_0_valid_T_27;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_35 = _mshrs_io_req_0_valid_T_31 | _mshrs_io_req_0_valid_T_32;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_36 = _mshrs_io_req_0_valid_T_35 | _mshrs_io_req_0_valid_T_33;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_37 = _mshrs_io_req_0_valid_T_36 | _mshrs_io_req_0_valid_T_34;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_43 = _mshrs_io_req_0_valid_T_38 | _mshrs_io_req_0_valid_T_39;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_44 = _mshrs_io_req_0_valid_T_43 | _mshrs_io_req_0_valid_T_40;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_45 = _mshrs_io_req_0_valid_T_44 | _mshrs_io_req_0_valid_T_41;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_46 = _mshrs_io_req_0_valid_T_45 | _mshrs_io_req_0_valid_T_42;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_47 = _mshrs_io_req_0_valid_T_37 | _mshrs_io_req_0_valid_T_46;\t// @[package.scala:81:59]\n wire _mshrs_io_req_0_valid_T_48 = _mshrs_io_req_0_valid_T_30 | _mshrs_io_req_0_valid_T_47;\t// @[package.scala:81:59]\n wire _mshrs_io_req_0_valid_T_49 = _mshrs_io_req_0_valid_T_23 | _mshrs_io_req_0_valid_T_48;\t// @[Consts.scala:88:45, :89:68]\n wire _mshrs_io_req_0_valid_T_52 = _mshrs_io_req_0_valid_T_50 | _mshrs_io_req_0_valid_T_51;\t// @[Consts.scala:90:{32,42,49}]\n wire _mshrs_io_req_0_valid_T_54 = _mshrs_io_req_0_valid_T_52 | _mshrs_io_req_0_valid_T_53;\t// @[Consts.scala:90:{42,59,66}]\n wire _mshrs_io_req_0_valid_T_59 = _mshrs_io_req_0_valid_T_55 | _mshrs_io_req_0_valid_T_56;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_60 = _mshrs_io_req_0_valid_T_59 | _mshrs_io_req_0_valid_T_57;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_61 = _mshrs_io_req_0_valid_T_60 | _mshrs_io_req_0_valid_T_58;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_67 = _mshrs_io_req_0_valid_T_62 | _mshrs_io_req_0_valid_T_63;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_68 = _mshrs_io_req_0_valid_T_67 | _mshrs_io_req_0_valid_T_64;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_69 = _mshrs_io_req_0_valid_T_68 | _mshrs_io_req_0_valid_T_65;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_70 = _mshrs_io_req_0_valid_T_69 | _mshrs_io_req_0_valid_T_66;\t// @[package.scala:16:47, :81:59]\n wire _mshrs_io_req_0_valid_T_71 = _mshrs_io_req_0_valid_T_61 | _mshrs_io_req_0_valid_T_70;\t// @[package.scala:81:59]\n wire _mshrs_io_req_0_valid_T_72 = _mshrs_io_req_0_valid_T_54 | _mshrs_io_req_0_valid_T_71;\t// @[Consts.scala:87:44, :90:{59,76}]\n wire _mshrs_io_req_0_valid_T_73 = _mshrs_io_req_0_valid_T_49 | _mshrs_io_req_0_valid_T_72;\t// @[Consts.scala:90:76]\n assign _mshrs_io_req_0_valid_T_74 = _mshrs_io_req_0_valid_T_20 & _mshrs_io_req_0_valid_T_73;\t// @[dcache.scala:753:79, :754:77, :756:65]\n wire [1:0] _mshrs_io_req_0_bits_old_meta_T_coh_state = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_coh_state : s2_repl_meta_0_coh_state;\t// @[HellaCache.scala:305:20]\n wire [21:0] _mshrs_io_req_0_bits_old_meta_T_tag = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_tag : s2_repl_meta_0_tag;\t// @[HellaCache.scala:305:20]\n wire [1:0] _mshrs_io_req_0_bits_way_en_T = s2_tag_match_0 ? s2_tag_match_way_0 : s2_replaced_way_en;\t// @[OneHot.scala:58:35]\n wire _mshrs_io_req_is_probe_0_T = s2_type == 3'h1;\t// @[dcache.scala:633:25, :769:49]\n wire _mshrs_io_req_is_probe_0_T_1 = _mshrs_io_req_is_probe_0_T & s2_valid_0;\t// @[dcache.scala:427:49, :769:{49,61}]\n wire _mshrs_io_meta_resp_valid_T = ~s2_nack_hit_0;\t// @[dcache.scala:722:31, :748:29, :772:36]\n wire _mshrs_io_meta_resp_valid_T_1 = _mshrs_io_meta_resp_valid_T | _prober_io_mshr_wb_rdy;\t// @[dcache.scala:432:22, :772:{36,52}]\n reg [1:0] mshrs_io_meta_resp_bits_REG_0_coh_state;\t// @[dcache.scala:773:70]\n reg [21:0] mshrs_io_meta_resp_bits_REG_0_tag;\t// @[dcache.scala:773:70]\n reg [1:0] mshrs_io_meta_resp_bits_REG_1_coh_state;\t// @[dcache.scala:773:70]\n reg [21:0] mshrs_io_meta_resp_bits_REG_1_tag;\t// @[dcache.scala:773:70]\n wire [1:0] _mshrs_io_meta_resp_bits_WIRE_2_state;\t// @[Mux.scala:30:73]\n wire [21:0] _mshrs_io_meta_resp_bits_WIRE_1;\t// @[Mux.scala:30:73]\n wire [21:0] _mshrs_io_meta_resp_bits_T_2 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_tag : 22'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [21:0] _mshrs_io_meta_resp_bits_T_3 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_tag : 22'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [21:0] _mshrs_io_meta_resp_bits_T_4 = _mshrs_io_meta_resp_bits_T_2 | _mshrs_io_meta_resp_bits_T_3;\t// @[Mux.scala:30:73]\n assign _mshrs_io_meta_resp_bits_WIRE_1 = _mshrs_io_meta_resp_bits_T_4;\t// @[Mux.scala:30:73]\n wire [21:0] _mshrs_io_meta_resp_bits_WIRE_tag = _mshrs_io_meta_resp_bits_WIRE_1;\t// @[Mux.scala:30:73]\n wire [1:0] _mshrs_io_meta_resp_bits_WIRE_3;\t// @[Mux.scala:30:73]\n wire [1:0] _mshrs_io_meta_resp_bits_WIRE_coh_state = _mshrs_io_meta_resp_bits_WIRE_2_state;\t// @[Mux.scala:30:73]\n wire [1:0] _mshrs_io_meta_resp_bits_T_5 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_coh_state : 2'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [1:0] _mshrs_io_meta_resp_bits_T_6 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_coh_state : 2'h0;\t// @[Mux.scala:30:73, :32:36]\n wire [1:0] _mshrs_io_meta_resp_bits_T_7 = _mshrs_io_meta_resp_bits_T_5 | _mshrs_io_meta_resp_bits_T_6;\t// @[Mux.scala:30:73]\n assign _mshrs_io_meta_resp_bits_WIRE_3 = _mshrs_io_meta_resp_bits_T_7;\t// @[Mux.scala:30:73]\n assign _mshrs_io_meta_resp_bits_WIRE_2_state = _mshrs_io_meta_resp_bits_WIRE_3;\t// @[Mux.scala:30:73]\n wire _prober_io_req_valid_T = ~lrsc_valid;\t// @[dcache.scala:661:31, :778:46]\n wire _prober_io_req_valid_T_1 = nodeOut_b_valid & _prober_io_req_valid_T;\t// @[MixedNode.scala:542:17]\n wire _nodeOut_b_ready_T = ~lrsc_valid;\t// @[dcache.scala:661:31, :778:46, :779:51]\n assign _nodeOut_b_ready_T_1 = _prober_io_req_ready & _nodeOut_b_ready_T;\t// @[dcache.scala:432:22, :779:{48,51}]\n assign nodeOut_b_ready = _nodeOut_b_ready_T_1;\t// @[MixedNode.scala:542:17]\n wire _prober_io_wb_rdy_T = _prober_io_meta_write_bits_idx != _wb_io_idx_bits;\t// @[dcache.scala:431:18, :432:22, :785:59]\n wire _prober_io_wb_rdy_T_1 = ~_wb_io_idx_valid;\t// @[dcache.scala:431:18, :785:82]\n wire _prober_io_wb_rdy_T_2 = _prober_io_wb_rdy_T | _prober_io_wb_rdy_T_1;\t// @[dcache.scala:785:{59,79,82}]\n wire _wb_io_mem_grant_T_1 = nodeOut_d_bits_source == 4'h8;\t// @[MixedNode.scala:542:17]\n assign nodeOut_d_ready = _wb_io_mem_grant_T_1 | _mshrs_io_mem_grant_ready;\t// @[MixedNode.scala:542:17]\n wire _wb_io_mem_grant_T = nodeOut_d_ready & nodeOut_d_valid;\t// @[Decoupled.scala:51:35]\n wire _wb_io_mem_grant_T_2 = _wb_io_mem_grant_T & _wb_io_mem_grant_T_1;\t// @[Decoupled.scala:51:35]\n wire opdata = _wb_io_release_bits_opcode[0];\t// @[Edges.scala:102:36]\n wire [26:0] _decode_T_3 = 27'hFFF << _prober_io_rep_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _decode_T_4 = _decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _decode_T_5 = ~_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] decode_1 = _decode_T_5[11:3];\t// @[package.scala:243:46]\n reg [8:0] beatsLeft;\t// @[Arbiter.scala:60:30]\n wire idle = beatsLeft == 9'h0;\t// @[Arbiter.scala:60:30, :61:28]\n wire latch = idle & nodeOut_c_ready;\t// @[Arbiter.scala:61:28, :62:24]\n wire [1:0] _readys_T = {_prober_io_rep_valid, _wb_io_release_valid};\t// @[Arbiter.scala:68:51]\n wire [2:0] _readys_T_1 = {_readys_T, 1'h0};\t// @[package.scala:253:48]\n wire [1:0] _readys_T_2 = _readys_T_1[1:0];\t// @[package.scala:253:{48,53}]\n wire [1:0] _readys_T_3 = _readys_T | _readys_T_2;\t// @[package.scala:253:{43,53}]\n wire [1:0] _readys_T_4 = _readys_T_3;\t// @[package.scala:253:43, :254:17]\n wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0};\t// @[package.scala:254:17]\n wire [1:0] _readys_T_6 = _readys_T_5[1:0];\t// @[Arbiter.scala:16:{78,83}]\n wire [1:0] _readys_T_7 = ~_readys_T_6;\t// @[Arbiter.scala:16:{61,83}]\n wire _readys_T_8 = _readys_T_7[0];\t// @[Arbiter.scala:16:61, :68:76]\n wire readys_0 = _readys_T_8;\t// @[Arbiter.scala:68:{27,76}]\n wire _readys_T_9 = _readys_T_7[1];\t// @[Arbiter.scala:16:61, :68:76]\n wire readys_1 = _readys_T_9;\t// @[Arbiter.scala:68:{27,76}]\n wire _winner_T = readys_0 & _wb_io_release_valid;\t// @[Arbiter.scala:68:27, :71:69]\n wire winner_0 = _winner_T;\t// @[Arbiter.scala:71:{27,69}]\n wire _winner_T_1 = readys_1 & _prober_io_rep_valid;\t// @[Arbiter.scala:68:27, :71:69]\n wire winner_1 = _winner_T_1;\t// @[Arbiter.scala:71:{27,69}]\n wire prefixOR_1 = winner_0;\t// @[Arbiter.scala:71:27, :76:48]\n wire _prefixOR_T = prefixOR_1 | winner_1;\t// @[Arbiter.scala:71:27, :76:48]\n wire _nodeOut_c_valid_T = _wb_io_release_valid | _prober_io_rep_valid;\t// @[Arbiter.scala:79:31, :96:46]\n wire [8:0] maskedBeats_0 = winner_0 & opdata ? 9'h7 : 9'h0;\t// @[Edges.scala:102:36, :221:14]\n wire [8:0] initBeats = maskedBeats_0;\t// @[Arbiter.scala:82:69, :84:44]\n wire _GEN_19 = nodeOut_c_ready & nodeOut_c_valid;\t// @[Decoupled.scala:51:35]\n wire _beatsLeft_T;\t// @[Decoupled.scala:51:35]\n assign _beatsLeft_T = _GEN_19;\t// @[Decoupled.scala:51:35]\n wire _io_lsu_perf_release_T;\t// @[Decoupled.scala:51:35]\n assign _io_lsu_perf_release_T = _GEN_19;\t// @[Decoupled.scala:51:35]\n wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T};\t// @[Decoupled.scala:51:35]\n wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0];\t// @[Arbiter.scala:85:52]\n wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2;\t// @[Arbiter.scala:62:24, :84:44, :85:{23,52}]\n reg state_0;\t// @[Arbiter.scala:88:26]\n reg state_1;\t// @[Arbiter.scala:88:26]\n wire muxState_0 = idle ? winner_0 : state_0;\t// @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]\n wire muxState_1 = idle ? winner_1 : state_1;\t// @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]\n wire allowed_0 = idle ? readys_0 : state_0;\t// @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]\n wire allowed_1 = idle ? readys_1 : state_1;\t// @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]\n wire _wb_io_release_ready_T = nodeOut_c_ready & allowed_0;\t// @[Arbiter.scala:92:24, :94:31]\n wire _prober_io_rep_ready_T = nodeOut_c_ready & allowed_1;\t// @[Arbiter.scala:92:24, :94:31]\n wire _nodeOut_c_valid_T_1 = state_0 & _wb_io_release_valid;\t// @[Mux.scala:30:73]\n wire _nodeOut_c_valid_T_2 = state_1 & _prober_io_rep_valid;\t// @[Mux.scala:30:73]\n wire _nodeOut_c_valid_T_3 = _nodeOut_c_valid_T_1 | _nodeOut_c_valid_T_2;\t// @[Mux.scala:30:73]\n wire _nodeOut_c_valid_WIRE = _nodeOut_c_valid_T_3;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_valid_T_4 = idle ? _nodeOut_c_valid_T : _nodeOut_c_valid_WIRE;\t// @[Mux.scala:30:73]\n assign nodeOut_c_valid = _nodeOut_c_valid_T_4;\t// @[Arbiter.scala:96:24]\n wire [2:0] _nodeOut_c_bits_WIRE_9;\t// @[Mux.scala:30:73]\n assign nodeOut_c_bits_opcode = _nodeOut_c_bits_WIRE_opcode;\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_c_bits_WIRE_8;\t// @[Mux.scala:30:73]\n assign nodeOut_c_bits_param = _nodeOut_c_bits_WIRE_param;\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_WIRE_7;\t// @[Mux.scala:30:73]\n assign nodeOut_c_bits_size = _nodeOut_c_bits_WIRE_size;\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_WIRE_6;\t// @[Mux.scala:30:73]\n assign nodeOut_c_bits_source = _nodeOut_c_bits_WIRE_source;\t// @[Mux.scala:30:73]\n wire [31:0] _nodeOut_c_bits_WIRE_5;\t// @[Mux.scala:30:73]\n assign nodeOut_c_bits_address = _nodeOut_c_bits_WIRE_address;\t// @[Mux.scala:30:73]\n wire [63:0] _nodeOut_c_bits_WIRE_2;\t// @[Mux.scala:30:73]\n assign nodeOut_c_bits_data = _nodeOut_c_bits_WIRE_data;\t// @[Mux.scala:30:73]\n wire [63:0] _nodeOut_c_bits_T_3 = muxState_0 ? _wb_io_release_bits_data : 64'h0;\t// @[Mux.scala:30:73]\n wire [63:0] _nodeOut_c_bits_T_5 = _nodeOut_c_bits_T_3;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_2 = _nodeOut_c_bits_T_5;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_data = _nodeOut_c_bits_WIRE_2;\t// @[Mux.scala:30:73]\n wire [31:0] _nodeOut_c_bits_T_6 = muxState_0 ? _wb_io_release_bits_address : 32'h0;\t// @[Mux.scala:30:73]\n wire [31:0] _nodeOut_c_bits_T_7 = muxState_1 ? _prober_io_rep_bits_address : 32'h0;\t// @[Mux.scala:30:73]\n wire [31:0] _nodeOut_c_bits_T_8 = _nodeOut_c_bits_T_6 | _nodeOut_c_bits_T_7;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_5 = _nodeOut_c_bits_T_8;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_address = _nodeOut_c_bits_WIRE_5;\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_T_9 = {muxState_0, 3'h0};\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_T_10 = muxState_1 ? _prober_io_rep_bits_source : 4'h0;\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_T_11 = _nodeOut_c_bits_T_9 | _nodeOut_c_bits_T_10;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_6 = _nodeOut_c_bits_T_11;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_source = _nodeOut_c_bits_WIRE_6;\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_T_12 = muxState_0 ? 4'h6 : 4'h0;\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_T_13 = muxState_1 ? _prober_io_rep_bits_size : 4'h0;\t// @[Mux.scala:30:73]\n wire [3:0] _nodeOut_c_bits_T_14 = _nodeOut_c_bits_T_12 | _nodeOut_c_bits_T_13;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_7 = _nodeOut_c_bits_T_14;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_size = _nodeOut_c_bits_WIRE_7;\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_c_bits_T_15 = muxState_0 ? _wb_io_release_bits_param : 3'h0;\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_c_bits_T_16 = muxState_1 ? _prober_io_rep_bits_param : 3'h0;\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_c_bits_T_17 = _nodeOut_c_bits_T_15 | _nodeOut_c_bits_T_16;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_8 = _nodeOut_c_bits_T_17;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_param = _nodeOut_c_bits_WIRE_8;\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_c_bits_T_18 = muxState_0 ? _wb_io_release_bits_opcode : 3'h0;\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_c_bits_T_19 = {muxState_1, 2'h0};\t// @[Mux.scala:30:73]\n wire [2:0] _nodeOut_c_bits_T_20 = _nodeOut_c_bits_T_18 | _nodeOut_c_bits_T_19;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_9 = _nodeOut_c_bits_T_20;\t// @[Mux.scala:30:73]\n assign _nodeOut_c_bits_WIRE_opcode = _nodeOut_c_bits_WIRE_9;\t// @[Mux.scala:30:73]\n wire [26:0] _io_lsu_perf_release_beats1_decode_T = 27'hFFF << nodeOut_c_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _io_lsu_perf_release_beats1_decode_T_1 = _io_lsu_perf_release_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _io_lsu_perf_release_beats1_decode_T_2 = ~_io_lsu_perf_release_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] io_lsu_perf_release_beats1_decode = _io_lsu_perf_release_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire io_lsu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0];\t// @[Edges.scala:102:36]\n wire [8:0] io_lsu_perf_release_beats1 = io_lsu_perf_release_beats1_opdata ? io_lsu_perf_release_beats1_decode : 9'h0;\t// @[Edges.scala:102:36, :220:59, :221:14]\n reg [8:0] io_lsu_perf_release_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _io_lsu_perf_release_counter1_T = {1'h0, io_lsu_perf_release_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] io_lsu_perf_release_counter1 = _io_lsu_perf_release_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire io_lsu_perf_release_first = io_lsu_perf_release_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _io_lsu_perf_release_last_T = io_lsu_perf_release_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _io_lsu_perf_release_last_T_1 = io_lsu_perf_release_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire io_lsu_perf_release_last = _io_lsu_perf_release_last_T | _io_lsu_perf_release_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n assign io_lsu_perf_release_done = io_lsu_perf_release_last & _io_lsu_perf_release_T;\t// @[Decoupled.scala:51:35]\n assign io_lsu_perf_release_0 = io_lsu_perf_release_done;\t// @[Edges.scala:233:22]\n wire [8:0] _io_lsu_perf_release_count_T = ~io_lsu_perf_release_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] io_lsu_perf_release_count = io_lsu_perf_release_beats1 & _io_lsu_perf_release_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _io_lsu_perf_release_counter_T = io_lsu_perf_release_first ? io_lsu_perf_release_beats1 : io_lsu_perf_release_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _io_lsu_perf_acquire_T = nodeOut_a_ready & nodeOut_a_valid;\t// @[Decoupled.scala:51:35]\n wire [26:0] _io_lsu_perf_acquire_beats1_decode_T = 27'hFFF << nodeOut_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_1 = _io_lsu_perf_acquire_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_2 = ~_io_lsu_perf_acquire_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] io_lsu_perf_acquire_beats1_decode = _io_lsu_perf_acquire_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _io_lsu_perf_acquire_beats1_opdata_T = nodeOut_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire io_lsu_perf_acquire_beats1_opdata = ~_io_lsu_perf_acquire_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] io_lsu_perf_acquire_beats1 = io_lsu_perf_acquire_beats1_opdata ? io_lsu_perf_acquire_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] io_lsu_perf_acquire_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _io_lsu_perf_acquire_counter1_T = {1'h0, io_lsu_perf_acquire_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] io_lsu_perf_acquire_counter1 = _io_lsu_perf_acquire_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire io_lsu_perf_acquire_first = io_lsu_perf_acquire_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _io_lsu_perf_acquire_last_T = io_lsu_perf_acquire_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _io_lsu_perf_acquire_last_T_1 = io_lsu_perf_acquire_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire io_lsu_perf_acquire_last = _io_lsu_perf_acquire_last_T | _io_lsu_perf_acquire_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n assign io_lsu_perf_acquire_done = io_lsu_perf_acquire_last & _io_lsu_perf_acquire_T;\t// @[Decoupled.scala:51:35]\n assign io_lsu_perf_acquire_0 = io_lsu_perf_acquire_done;\t// @[Edges.scala:233:22]\n wire [8:0] _io_lsu_perf_acquire_count_T = ~io_lsu_perf_acquire_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] io_lsu_perf_acquire_count = io_lsu_perf_acquire_beats1 & _io_lsu_perf_acquire_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _io_lsu_perf_acquire_counter_T = io_lsu_perf_acquire_first ? io_lsu_perf_acquire_beats1 : io_lsu_perf_acquire_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [63:0] s2_data_word_prebypass_0 = _s2_data_word_prebypass_T_1;\t// @[dcache.scala:427:49, :825:63]\n wire [63:0] _s2_data_word_0_T_2;\t// @[dcache.scala:891:27]\n wire [63:0] s2_data_word_0;\t// @[dcache.scala:826:26]\n wire [63:0] size_dat_padded = s2_data_word_0;\t// @[AMOALU.scala:13:27]\n wire _cache_resp_0_valid_T;\t// @[dcache.scala:835:48]\n wire [63:0] _cache_resp_0_bits_data_T_24;\t// @[dcache.scala:837:52]\n wire [63:0] cache_resp_0_bits_data;\t// @[dcache.scala:833:26]\n wire cache_resp_0_valid;\t// @[dcache.scala:833:26]\n assign _cache_resp_0_valid_T = s2_valid_0 & s2_send_resp_0;\t// @[dcache.scala:427:49, :835:48]\n assign cache_resp_0_valid = _cache_resp_0_valid_T;\t// @[dcache.scala:833:26, :835:48]\n wire _cache_resp_0_bits_data_shifted_T = s2_req_0_addr[2];\t// @[AMOALU.scala:42:29]\n wire _amoalu_io_mask_upper_T_8 = s2_req_0_addr[2];\t// @[AMOALU.scala:20:27, :42:29]\n wire _amoalu_io_mask_lower_T_2 = s2_req_0_addr[2];\t// @[AMOALU.scala:21:27, :42:29]\n wire [31:0] _cache_resp_0_bits_data_shifted_T_1 = s2_data_word_0[63:32];\t// @[AMOALU.scala:42:37]\n wire [31:0] _cache_resp_0_bits_data_T_5 = s2_data_word_0[63:32];\t// @[AMOALU.scala:42:37, :45:94]\n wire [31:0] _cache_resp_0_bits_data_shifted_T_2 = s2_data_word_0[31:0];\t// @[AMOALU.scala:42:55]\n wire [31:0] cache_resp_0_bits_data_shifted = _cache_resp_0_bits_data_shifted_T ? _cache_resp_0_bits_data_shifted_T_1 : _cache_resp_0_bits_data_shifted_T_2;\t// @[AMOALU.scala:42:{24,29,37,55}]\n wire [31:0] cache_resp_0_bits_data_zeroed = cache_resp_0_bits_data_shifted;\t// @[AMOALU.scala:42:24, :44:23]\n wire _cache_resp_0_bits_data_T = size == 2'h2;\t// @[AMOALU.scala:11:18, :45:26]\n wire _cache_resp_0_bits_data_T_1 = _cache_resp_0_bits_data_T;\t// @[AMOALU.scala:45:{26,34}]\n wire _cache_resp_0_bits_data_T_2 = cache_resp_0_bits_data_zeroed[31];\t// @[AMOALU.scala:44:23, :45:81]\n wire _cache_resp_0_bits_data_T_3 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_2;\t// @[AMOALU.scala:45:{72,81}]\n wire [31:0] _cache_resp_0_bits_data_T_4 = {32{_cache_resp_0_bits_data_T_3}};\t// @[AMOALU.scala:45:{49,72}]\n wire [31:0] _cache_resp_0_bits_data_T_6 = _cache_resp_0_bits_data_T_1 ? _cache_resp_0_bits_data_T_4 : _cache_resp_0_bits_data_T_5;\t// @[AMOALU.scala:45:{20,34,49,94}]\n wire [63:0] _cache_resp_0_bits_data_T_7 = {_cache_resp_0_bits_data_T_6, cache_resp_0_bits_data_zeroed};\t// @[AMOALU.scala:44:23, :45:{16,20}]\n wire _cache_resp_0_bits_data_shifted_T_3 = s2_req_0_addr[1];\t// @[AMOALU.scala:42:29]\n wire _amoalu_io_mask_upper_T_4 = s2_req_0_addr[1];\t// @[AMOALU.scala:20:27, :42:29]\n wire _amoalu_io_mask_lower_T_1 = s2_req_0_addr[1];\t// @[AMOALU.scala:21:27, :42:29]\n wire [15:0] _cache_resp_0_bits_data_shifted_T_4 = _cache_resp_0_bits_data_T_7[31:16];\t// @[AMOALU.scala:42:37, :45:16]\n wire [15:0] _cache_resp_0_bits_data_shifted_T_5 = _cache_resp_0_bits_data_T_7[15:0];\t// @[AMOALU.scala:42:55, :45:16]\n wire [15:0] cache_resp_0_bits_data_shifted_1 = _cache_resp_0_bits_data_shifted_T_3 ? _cache_resp_0_bits_data_shifted_T_4 : _cache_resp_0_bits_data_shifted_T_5;\t// @[AMOALU.scala:42:{24,29,37,55}]\n wire [15:0] cache_resp_0_bits_data_zeroed_1 = cache_resp_0_bits_data_shifted_1;\t// @[AMOALU.scala:42:24, :44:23]\n wire _cache_resp_0_bits_data_T_8 = size == 2'h1;\t// @[AMOALU.scala:11:18, :45:26]\n wire _cache_resp_0_bits_data_T_9 = _cache_resp_0_bits_data_T_8;\t// @[AMOALU.scala:45:{26,34}]\n wire _cache_resp_0_bits_data_T_10 = cache_resp_0_bits_data_zeroed_1[15];\t// @[AMOALU.scala:44:23, :45:81]\n wire _cache_resp_0_bits_data_T_11 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_10;\t// @[AMOALU.scala:45:{72,81}]\n wire [47:0] _cache_resp_0_bits_data_T_12 = {48{_cache_resp_0_bits_data_T_11}};\t// @[AMOALU.scala:45:{49,72}]\n wire [47:0] _cache_resp_0_bits_data_T_13 = _cache_resp_0_bits_data_T_7[63:16];\t// @[AMOALU.scala:45:{16,94}]\n wire [47:0] _cache_resp_0_bits_data_T_14 = _cache_resp_0_bits_data_T_9 ? _cache_resp_0_bits_data_T_12 : _cache_resp_0_bits_data_T_13;\t// @[AMOALU.scala:45:{20,34,49,94}]\n wire [63:0] _cache_resp_0_bits_data_T_15 = {_cache_resp_0_bits_data_T_14, cache_resp_0_bits_data_zeroed_1};\t// @[AMOALU.scala:44:23, :45:{16,20}]\n wire _cache_resp_0_bits_data_shifted_T_6 = s2_req_0_addr[0];\t// @[AMOALU.scala:42:29]\n wire _amoalu_io_mask_upper_T = s2_req_0_addr[0];\t// @[AMOALU.scala:20:27, :42:29]\n wire _amoalu_io_mask_lower_T = s2_req_0_addr[0];\t// @[AMOALU.scala:21:27, :42:29]\n wire [7:0] _cache_resp_0_bits_data_shifted_T_7 = _cache_resp_0_bits_data_T_15[15:8];\t// @[AMOALU.scala:42:37, :45:16]\n wire [7:0] _cache_resp_0_bits_data_shifted_T_8 = _cache_resp_0_bits_data_T_15[7:0];\t// @[AMOALU.scala:42:55, :45:16]\n wire [7:0] cache_resp_0_bits_data_shifted_2 = _cache_resp_0_bits_data_shifted_T_6 ? _cache_resp_0_bits_data_shifted_T_7 : _cache_resp_0_bits_data_shifted_T_8;\t// @[AMOALU.scala:42:{24,29,37,55}]\n wire [7:0] cache_resp_0_bits_data_zeroed_2 = cache_resp_0_bits_data_doZero_2 ? 8'h0 : cache_resp_0_bits_data_shifted_2;\t// @[AMOALU.scala:42:24, :43:31, :44:23]\n wire _cache_resp_0_bits_data_T_16 = size == 2'h0;\t// @[AMOALU.scala:11:18, :45:26]\n wire _cache_resp_0_bits_data_T_17 = _cache_resp_0_bits_data_T_16 | cache_resp_0_bits_data_doZero_2;\t// @[AMOALU.scala:43:31, :45:{26,34}]\n wire _cache_resp_0_bits_data_T_18 = cache_resp_0_bits_data_zeroed_2[7];\t// @[AMOALU.scala:44:23, :45:81]\n wire _cache_resp_0_bits_data_T_19 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_18;\t// @[AMOALU.scala:45:{72,81}]\n wire [55:0] _cache_resp_0_bits_data_T_20 = {56{_cache_resp_0_bits_data_T_19}};\t// @[AMOALU.scala:45:{49,72}]\n wire [55:0] _cache_resp_0_bits_data_T_21 = _cache_resp_0_bits_data_T_15[63:8];\t// @[AMOALU.scala:45:{16,94}]\n wire [55:0] _cache_resp_0_bits_data_T_22 = _cache_resp_0_bits_data_T_17 ? _cache_resp_0_bits_data_T_20 : _cache_resp_0_bits_data_T_21;\t// @[AMOALU.scala:45:{20,34,49,94}]\n wire [63:0] _cache_resp_0_bits_data_T_23 = {_cache_resp_0_bits_data_T_22, cache_resp_0_bits_data_zeroed_2};\t// @[AMOALU.scala:44:23, :45:{16,20}]\n assign _cache_resp_0_bits_data_T_24 = {_cache_resp_0_bits_data_T_23[63:1], _cache_resp_0_bits_data_T_23[0] | s2_sc_fail};\t// @[AMOALU.scala:45:16]\n assign cache_resp_0_bits_data = _cache_resp_0_bits_data_T_24;\t// @[dcache.scala:833:26, :837:52]\n wire [3:0] uncache_resp_bits_uop_ctrl_br_type;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_ctrl_op1_sel;\t// @[dcache.scala:841:26]\n wire [2:0] uncache_resp_bits_uop_ctrl_op2_sel;\t// @[dcache.scala:841:26]\n wire [2:0] uncache_resp_bits_uop_ctrl_imm_sel;\t// @[dcache.scala:841:26]\n wire [4:0] uncache_resp_bits_uop_ctrl_op_fcn;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_ctrl_fcn_dw;\t// @[dcache.scala:841:26]\n wire [2:0] uncache_resp_bits_uop_ctrl_csr_cmd;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_ctrl_is_load;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_ctrl_is_sta;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_ctrl_is_std;\t// @[dcache.scala:841:26]\n wire [6:0] uncache_resp_bits_uop_uopc;\t// @[dcache.scala:841:26]\n wire [31:0] uncache_resp_bits_uop_inst;\t// @[dcache.scala:841:26]\n wire [31:0] uncache_resp_bits_uop_debug_inst;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_rvc;\t// @[dcache.scala:841:26]\n wire [33:0] uncache_resp_bits_uop_debug_pc;\t// @[dcache.scala:841:26]\n wire [2:0] uncache_resp_bits_uop_iq_type;\t// @[dcache.scala:841:26]\n wire [9:0] uncache_resp_bits_uop_fu_code;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_iw_state;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_iw_p1_poisoned;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_iw_p2_poisoned;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_br;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_jalr;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_jal;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_sfb;\t// @[dcache.scala:841:26]\n wire [3:0] uncache_resp_bits_uop_br_mask;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_br_tag;\t// @[dcache.scala:841:26]\n wire [3:0] uncache_resp_bits_uop_ftq_idx;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_edge_inst;\t// @[dcache.scala:841:26]\n wire [5:0] uncache_resp_bits_uop_pc_lob;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_taken;\t// @[dcache.scala:841:26]\n wire [19:0] uncache_resp_bits_uop_imm_packed;\t// @[dcache.scala:841:26]\n wire [11:0] uncache_resp_bits_uop_csr_addr;\t// @[dcache.scala:841:26]\n wire [5:0] uncache_resp_bits_uop_rob_idx;\t// @[dcache.scala:841:26]\n wire [3:0] uncache_resp_bits_uop_ldq_idx;\t// @[dcache.scala:841:26]\n wire [3:0] uncache_resp_bits_uop_stq_idx;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_rxq_idx;\t// @[dcache.scala:841:26]\n wire [6:0] uncache_resp_bits_uop_pdst;\t// @[dcache.scala:841:26]\n wire [6:0] uncache_resp_bits_uop_prs1;\t// @[dcache.scala:841:26]\n wire [6:0] uncache_resp_bits_uop_prs2;\t// @[dcache.scala:841:26]\n wire [6:0] uncache_resp_bits_uop_prs3;\t// @[dcache.scala:841:26]\n wire [3:0] uncache_resp_bits_uop_ppred;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_prs1_busy;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_prs2_busy;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_prs3_busy;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_ppred_busy;\t// @[dcache.scala:841:26]\n wire [6:0] uncache_resp_bits_uop_stale_pdst;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_exception;\t// @[dcache.scala:841:26]\n wire [63:0] uncache_resp_bits_uop_exc_cause;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_bypassable;\t// @[dcache.scala:841:26]\n wire [4:0] uncache_resp_bits_uop_mem_cmd;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_mem_size;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_mem_signed;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_fence;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_fencei;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_amo;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_uses_ldq;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_uses_stq;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_sys_pc2epc;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_is_unique;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_flush_on_commit;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_ldst_is_rs1;\t// @[dcache.scala:841:26]\n wire [5:0] uncache_resp_bits_uop_ldst;\t// @[dcache.scala:841:26]\n wire [5:0] uncache_resp_bits_uop_lrs1;\t// @[dcache.scala:841:26]\n wire [5:0] uncache_resp_bits_uop_lrs2;\t// @[dcache.scala:841:26]\n wire [5:0] uncache_resp_bits_uop_lrs3;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_ldst_val;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_dst_rtype;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_lrs1_rtype;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_lrs2_rtype;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_frs3_en;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_fp_val;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_fp_single;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_xcpt_pf_if;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_xcpt_ae_if;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_xcpt_ma_if;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_bp_debug_if;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_uop_bp_xcpt_if;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_debug_fsrc;\t// @[dcache.scala:841:26]\n wire [1:0] uncache_resp_bits_uop_debug_tsrc;\t// @[dcache.scala:841:26]\n wire [63:0] uncache_resp_bits_data;\t// @[dcache.scala:841:26]\n wire uncache_resp_bits_is_hella;\t// @[dcache.scala:841:26]\n wire uncache_resp_valid;\t// @[dcache.scala:841:26]\n wire _mshrs_io_resp_ready_T = ~cache_resp_0_valid;\t// @[dcache.scala:833:26, :844:26]\n wire _io_lsu_resp_0_valid_T_2 = resp_0_valid;\t// @[dcache.scala:846:22, :857:43]\n assign io_lsu_resp_0_bits_out_uop_uopc = resp_0_bits_uop_uopc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_inst = resp_0_bits_uop_inst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_debug_inst = resp_0_bits_uop_debug_inst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_rvc = resp_0_bits_uop_is_rvc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_debug_pc = resp_0_bits_uop_debug_pc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_iq_type = resp_0_bits_uop_iq_type;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_fu_code = resp_0_bits_uop_fu_code;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_br_type = resp_0_bits_uop_ctrl_br_type;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_op1_sel = resp_0_bits_uop_ctrl_op1_sel;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_op2_sel = resp_0_bits_uop_ctrl_op2_sel;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_imm_sel = resp_0_bits_uop_ctrl_imm_sel;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_op_fcn = resp_0_bits_uop_ctrl_op_fcn;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw = resp_0_bits_uop_ctrl_fcn_dw;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd = resp_0_bits_uop_ctrl_csr_cmd;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_is_load = resp_0_bits_uop_ctrl_is_load;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_is_sta = resp_0_bits_uop_ctrl_is_sta;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ctrl_is_std = resp_0_bits_uop_ctrl_is_std;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_iw_state = resp_0_bits_uop_iw_state;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_iw_p1_poisoned = resp_0_bits_uop_iw_p1_poisoned;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_iw_p2_poisoned = resp_0_bits_uop_iw_p2_poisoned;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_br = resp_0_bits_uop_is_br;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_jalr = resp_0_bits_uop_is_jalr;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_jal = resp_0_bits_uop_is_jal;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_sfb = resp_0_bits_uop_is_sfb;\t// @[util.scala:101:23]\n wire [3:0] _io_lsu_resp_0_bits_out_uop_br_mask_T_1 = resp_0_bits_uop_br_mask;\t// @[util.scala:89:21]\n assign io_lsu_resp_0_bits_out_uop_br_tag = resp_0_bits_uop_br_tag;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ftq_idx = resp_0_bits_uop_ftq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_edge_inst = resp_0_bits_uop_edge_inst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_pc_lob = resp_0_bits_uop_pc_lob;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_taken = resp_0_bits_uop_taken;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_imm_packed = resp_0_bits_uop_imm_packed;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_csr_addr = resp_0_bits_uop_csr_addr;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_rob_idx = resp_0_bits_uop_rob_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ldq_idx = resp_0_bits_uop_ldq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_stq_idx = resp_0_bits_uop_stq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_rxq_idx = resp_0_bits_uop_rxq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_pdst = resp_0_bits_uop_pdst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_prs1 = resp_0_bits_uop_prs1;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_prs2 = resp_0_bits_uop_prs2;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_prs3 = resp_0_bits_uop_prs3;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ppred = resp_0_bits_uop_ppred;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_prs1_busy = resp_0_bits_uop_prs1_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_prs2_busy = resp_0_bits_uop_prs2_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_prs3_busy = resp_0_bits_uop_prs3_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ppred_busy = resp_0_bits_uop_ppred_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_stale_pdst = resp_0_bits_uop_stale_pdst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_exception = resp_0_bits_uop_exception;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_exc_cause = resp_0_bits_uop_exc_cause;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_bypassable = resp_0_bits_uop_bypassable;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_mem_cmd = resp_0_bits_uop_mem_cmd;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_mem_size = resp_0_bits_uop_mem_size;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_mem_signed = resp_0_bits_uop_mem_signed;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_fence = resp_0_bits_uop_is_fence;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_fencei = resp_0_bits_uop_is_fencei;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_amo = resp_0_bits_uop_is_amo;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_uses_ldq = resp_0_bits_uop_uses_ldq;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_uses_stq = resp_0_bits_uop_uses_stq;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_sys_pc2epc = resp_0_bits_uop_is_sys_pc2epc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_is_unique = resp_0_bits_uop_is_unique;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_flush_on_commit = resp_0_bits_uop_flush_on_commit;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ldst_is_rs1 = resp_0_bits_uop_ldst_is_rs1;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ldst = resp_0_bits_uop_ldst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_lrs1 = resp_0_bits_uop_lrs1;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_lrs2 = resp_0_bits_uop_lrs2;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_lrs3 = resp_0_bits_uop_lrs3;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_ldst_val = resp_0_bits_uop_ldst_val;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_dst_rtype = resp_0_bits_uop_dst_rtype;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_lrs1_rtype = resp_0_bits_uop_lrs1_rtype;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_lrs2_rtype = resp_0_bits_uop_lrs2_rtype;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_frs3_en = resp_0_bits_uop_frs3_en;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_fp_val = resp_0_bits_uop_fp_val;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_fp_single = resp_0_bits_uop_fp_single;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_xcpt_pf_if = resp_0_bits_uop_xcpt_pf_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_xcpt_ae_if = resp_0_bits_uop_xcpt_ae_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_xcpt_ma_if = resp_0_bits_uop_xcpt_ma_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_bp_debug_if = resp_0_bits_uop_bp_debug_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_bp_xcpt_if = resp_0_bits_uop_bp_xcpt_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_debug_fsrc = resp_0_bits_uop_debug_fsrc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_debug_tsrc = resp_0_bits_uop_debug_tsrc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_data = resp_0_bits_data;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_is_hella = resp_0_bits_is_hella;\t// @[util.scala:101:23]\n wire _uncache_respond_T = ~cache_resp_0_valid;\t// @[dcache.scala:833:26, :844:26, :849:27]\n wire uncache_respond = _uncache_respond_T;\t// @[dcache.scala:849:{27,48}]\n assign resp_0_valid = uncache_respond ? uncache_resp_valid : cache_resp_0_valid;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_uopc = uncache_respond ? uncache_resp_bits_uop_uopc : cache_resp_0_bits_uop_uopc;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_inst = uncache_respond ? uncache_resp_bits_uop_inst : cache_resp_0_bits_uop_inst;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_debug_inst = uncache_respond ? uncache_resp_bits_uop_debug_inst : cache_resp_0_bits_uop_debug_inst;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_rvc = uncache_respond ? uncache_resp_bits_uop_is_rvc : cache_resp_0_bits_uop_is_rvc;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_debug_pc = uncache_respond ? uncache_resp_bits_uop_debug_pc : cache_resp_0_bits_uop_debug_pc;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_iq_type = uncache_respond ? uncache_resp_bits_uop_iq_type : cache_resp_0_bits_uop_iq_type;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_fu_code = uncache_respond ? uncache_resp_bits_uop_fu_code : cache_resp_0_bits_uop_fu_code;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_br_type = uncache_respond ? uncache_resp_bits_uop_ctrl_br_type : cache_resp_0_bits_uop_ctrl_br_type;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_op1_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op1_sel : cache_resp_0_bits_uop_ctrl_op1_sel;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_op2_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op2_sel : cache_resp_0_bits_uop_ctrl_op2_sel;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_imm_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_imm_sel : cache_resp_0_bits_uop_ctrl_imm_sel;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_op_fcn = uncache_respond ? uncache_resp_bits_uop_ctrl_op_fcn : cache_resp_0_bits_uop_ctrl_op_fcn;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_fcn_dw = uncache_respond ? uncache_resp_bits_uop_ctrl_fcn_dw : cache_resp_0_bits_uop_ctrl_fcn_dw;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_csr_cmd = uncache_respond ? uncache_resp_bits_uop_ctrl_csr_cmd : cache_resp_0_bits_uop_ctrl_csr_cmd;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_is_load = uncache_respond ? uncache_resp_bits_uop_ctrl_is_load : cache_resp_0_bits_uop_ctrl_is_load;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_is_sta = uncache_respond ? uncache_resp_bits_uop_ctrl_is_sta : cache_resp_0_bits_uop_ctrl_is_sta;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ctrl_is_std = uncache_respond ? uncache_resp_bits_uop_ctrl_is_std : cache_resp_0_bits_uop_ctrl_is_std;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_iw_state = uncache_respond ? uncache_resp_bits_uop_iw_state : cache_resp_0_bits_uop_iw_state;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_iw_p1_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p1_poisoned : cache_resp_0_bits_uop_iw_p1_poisoned;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_iw_p2_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p2_poisoned : cache_resp_0_bits_uop_iw_p2_poisoned;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_br = uncache_respond ? uncache_resp_bits_uop_is_br : cache_resp_0_bits_uop_is_br;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_jalr = uncache_respond ? uncache_resp_bits_uop_is_jalr : cache_resp_0_bits_uop_is_jalr;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_jal = uncache_respond ? uncache_resp_bits_uop_is_jal : cache_resp_0_bits_uop_is_jal;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_sfb = uncache_respond ? uncache_resp_bits_uop_is_sfb : cache_resp_0_bits_uop_is_sfb;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_br_mask = uncache_respond ? uncache_resp_bits_uop_br_mask : cache_resp_0_bits_uop_br_mask;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_br_tag = uncache_respond ? uncache_resp_bits_uop_br_tag : cache_resp_0_bits_uop_br_tag;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ftq_idx = uncache_respond ? uncache_resp_bits_uop_ftq_idx : cache_resp_0_bits_uop_ftq_idx;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_edge_inst = uncache_respond ? uncache_resp_bits_uop_edge_inst : cache_resp_0_bits_uop_edge_inst;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_pc_lob = uncache_respond ? uncache_resp_bits_uop_pc_lob : cache_resp_0_bits_uop_pc_lob;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_taken = uncache_respond ? uncache_resp_bits_uop_taken : cache_resp_0_bits_uop_taken;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_imm_packed = uncache_respond ? uncache_resp_bits_uop_imm_packed : cache_resp_0_bits_uop_imm_packed;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_csr_addr = uncache_respond ? uncache_resp_bits_uop_csr_addr : cache_resp_0_bits_uop_csr_addr;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_rob_idx = uncache_respond ? uncache_resp_bits_uop_rob_idx : cache_resp_0_bits_uop_rob_idx;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ldq_idx = uncache_respond ? uncache_resp_bits_uop_ldq_idx : cache_resp_0_bits_uop_ldq_idx;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_stq_idx = uncache_respond ? uncache_resp_bits_uop_stq_idx : cache_resp_0_bits_uop_stq_idx;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_rxq_idx = uncache_respond ? uncache_resp_bits_uop_rxq_idx : cache_resp_0_bits_uop_rxq_idx;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_pdst = uncache_respond ? uncache_resp_bits_uop_pdst : cache_resp_0_bits_uop_pdst;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_prs1 = uncache_respond ? uncache_resp_bits_uop_prs1 : cache_resp_0_bits_uop_prs1;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_prs2 = uncache_respond ? uncache_resp_bits_uop_prs2 : cache_resp_0_bits_uop_prs2;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_prs3 = uncache_respond ? uncache_resp_bits_uop_prs3 : cache_resp_0_bits_uop_prs3;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ppred = uncache_respond ? uncache_resp_bits_uop_ppred : cache_resp_0_bits_uop_ppred;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_prs1_busy = uncache_respond ? uncache_resp_bits_uop_prs1_busy : cache_resp_0_bits_uop_prs1_busy;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_prs2_busy = uncache_respond ? uncache_resp_bits_uop_prs2_busy : cache_resp_0_bits_uop_prs2_busy;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_prs3_busy = uncache_respond ? uncache_resp_bits_uop_prs3_busy : cache_resp_0_bits_uop_prs3_busy;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ppred_busy = uncache_respond ? uncache_resp_bits_uop_ppred_busy : cache_resp_0_bits_uop_ppred_busy;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_stale_pdst = uncache_respond ? uncache_resp_bits_uop_stale_pdst : cache_resp_0_bits_uop_stale_pdst;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_exception = uncache_respond ? uncache_resp_bits_uop_exception : cache_resp_0_bits_uop_exception;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_exc_cause = uncache_respond ? uncache_resp_bits_uop_exc_cause : cache_resp_0_bits_uop_exc_cause;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_bypassable = uncache_respond ? uncache_resp_bits_uop_bypassable : cache_resp_0_bits_uop_bypassable;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_mem_cmd = uncache_respond ? uncache_resp_bits_uop_mem_cmd : cache_resp_0_bits_uop_mem_cmd;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_mem_size = uncache_respond ? uncache_resp_bits_uop_mem_size : cache_resp_0_bits_uop_mem_size;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_mem_signed = uncache_respond ? uncache_resp_bits_uop_mem_signed : cache_resp_0_bits_uop_mem_signed;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_fence = uncache_respond ? uncache_resp_bits_uop_is_fence : cache_resp_0_bits_uop_is_fence;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_fencei = uncache_respond ? uncache_resp_bits_uop_is_fencei : cache_resp_0_bits_uop_is_fencei;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_amo = uncache_respond ? uncache_resp_bits_uop_is_amo : cache_resp_0_bits_uop_is_amo;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_uses_ldq = uncache_respond ? uncache_resp_bits_uop_uses_ldq : cache_resp_0_bits_uop_uses_ldq;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_uses_stq = uncache_respond ? uncache_resp_bits_uop_uses_stq : cache_resp_0_bits_uop_uses_stq;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_sys_pc2epc = uncache_respond ? uncache_resp_bits_uop_is_sys_pc2epc : cache_resp_0_bits_uop_is_sys_pc2epc;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_is_unique = uncache_respond ? uncache_resp_bits_uop_is_unique : cache_resp_0_bits_uop_is_unique;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_flush_on_commit = uncache_respond ? uncache_resp_bits_uop_flush_on_commit : cache_resp_0_bits_uop_flush_on_commit;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ldst_is_rs1 = uncache_respond ? uncache_resp_bits_uop_ldst_is_rs1 : cache_resp_0_bits_uop_ldst_is_rs1;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ldst = uncache_respond ? uncache_resp_bits_uop_ldst : cache_resp_0_bits_uop_ldst;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_lrs1 = uncache_respond ? uncache_resp_bits_uop_lrs1 : cache_resp_0_bits_uop_lrs1;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_lrs2 = uncache_respond ? uncache_resp_bits_uop_lrs2 : cache_resp_0_bits_uop_lrs2;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_lrs3 = uncache_respond ? uncache_resp_bits_uop_lrs3 : cache_resp_0_bits_uop_lrs3;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_ldst_val = uncache_respond ? uncache_resp_bits_uop_ldst_val : cache_resp_0_bits_uop_ldst_val;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_dst_rtype = uncache_respond ? uncache_resp_bits_uop_dst_rtype : cache_resp_0_bits_uop_dst_rtype;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_lrs1_rtype = uncache_respond ? uncache_resp_bits_uop_lrs1_rtype : cache_resp_0_bits_uop_lrs1_rtype;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_lrs2_rtype = uncache_respond ? uncache_resp_bits_uop_lrs2_rtype : cache_resp_0_bits_uop_lrs2_rtype;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_frs3_en = uncache_respond ? uncache_resp_bits_uop_frs3_en : cache_resp_0_bits_uop_frs3_en;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_fp_val = uncache_respond ? uncache_resp_bits_uop_fp_val : cache_resp_0_bits_uop_fp_val;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_fp_single = uncache_respond ? uncache_resp_bits_uop_fp_single : cache_resp_0_bits_uop_fp_single;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_xcpt_pf_if = uncache_respond ? uncache_resp_bits_uop_xcpt_pf_if : cache_resp_0_bits_uop_xcpt_pf_if;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_xcpt_ae_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ae_if : cache_resp_0_bits_uop_xcpt_ae_if;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_xcpt_ma_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ma_if : cache_resp_0_bits_uop_xcpt_ma_if;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_bp_debug_if = uncache_respond ? uncache_resp_bits_uop_bp_debug_if : cache_resp_0_bits_uop_bp_debug_if;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_bp_xcpt_if = uncache_respond ? uncache_resp_bits_uop_bp_xcpt_if : cache_resp_0_bits_uop_bp_xcpt_if;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_debug_fsrc = uncache_respond ? uncache_resp_bits_uop_debug_fsrc : cache_resp_0_bits_uop_debug_fsrc;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_uop_debug_tsrc = uncache_respond ? uncache_resp_bits_uop_debug_tsrc : cache_resp_0_bits_uop_debug_tsrc;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_data = uncache_respond ? uncache_resp_bits_data : cache_resp_0_bits_data;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign resp_0_bits_is_hella = uncache_respond ? uncache_resp_bits_is_hella : cache_resp_0_bits_is_hella;\t// @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]\n assign _io_lsu_resp_0_valid_T_6 = _io_lsu_resp_0_valid_T_2;\t// @[dcache.scala:857:43, :858:78]\n assign io_lsu_resp_0_valid_0 = _io_lsu_resp_0_valid_T_6;\t// @[dcache.scala:413:7, :858:78]\n assign io_lsu_resp_0_bits_uop_uopc_0 = io_lsu_resp_0_bits_out_uop_uopc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_inst_0 = io_lsu_resp_0_bits_out_uop_inst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_debug_inst_0 = io_lsu_resp_0_bits_out_uop_debug_inst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_rvc_0 = io_lsu_resp_0_bits_out_uop_is_rvc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_debug_pc_0 = io_lsu_resp_0_bits_out_uop_debug_pc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_iq_type_0 = io_lsu_resp_0_bits_out_uop_iq_type;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_fu_code_0 = io_lsu_resp_0_bits_out_uop_fu_code;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_br_type_0 = io_lsu_resp_0_bits_out_uop_ctrl_br_type;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_op1_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op1_sel;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_op2_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op2_sel;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_imm_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_imm_sel;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_op_fcn_0 = io_lsu_resp_0_bits_out_uop_ctrl_op_fcn;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_is_load_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_load;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_is_sta_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_sta;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ctrl_is_std_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_std;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_iw_state_0 = io_lsu_resp_0_bits_out_uop_iw_state;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_iw_p1_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p1_poisoned;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_iw_p2_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p2_poisoned;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_br_0 = io_lsu_resp_0_bits_out_uop_is_br;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_jalr_0 = io_lsu_resp_0_bits_out_uop_is_jalr;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_jal_0 = io_lsu_resp_0_bits_out_uop_is_jal;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_sfb_0 = io_lsu_resp_0_bits_out_uop_is_sfb;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_br_mask_0 = io_lsu_resp_0_bits_out_uop_br_mask;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_br_tag_0 = io_lsu_resp_0_bits_out_uop_br_tag;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ftq_idx_0 = io_lsu_resp_0_bits_out_uop_ftq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_edge_inst_0 = io_lsu_resp_0_bits_out_uop_edge_inst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_pc_lob_0 = io_lsu_resp_0_bits_out_uop_pc_lob;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_taken_0 = io_lsu_resp_0_bits_out_uop_taken;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_imm_packed_0 = io_lsu_resp_0_bits_out_uop_imm_packed;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_csr_addr_0 = io_lsu_resp_0_bits_out_uop_csr_addr;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_rob_idx_0 = io_lsu_resp_0_bits_out_uop_rob_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ldq_idx_0 = io_lsu_resp_0_bits_out_uop_ldq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_stq_idx_0 = io_lsu_resp_0_bits_out_uop_stq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_rxq_idx_0 = io_lsu_resp_0_bits_out_uop_rxq_idx;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_pdst_0 = io_lsu_resp_0_bits_out_uop_pdst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_prs1_0 = io_lsu_resp_0_bits_out_uop_prs1;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_prs2_0 = io_lsu_resp_0_bits_out_uop_prs2;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_prs3_0 = io_lsu_resp_0_bits_out_uop_prs3;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ppred_0 = io_lsu_resp_0_bits_out_uop_ppred;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_prs1_busy_0 = io_lsu_resp_0_bits_out_uop_prs1_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_prs2_busy_0 = io_lsu_resp_0_bits_out_uop_prs2_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_prs3_busy_0 = io_lsu_resp_0_bits_out_uop_prs3_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ppred_busy_0 = io_lsu_resp_0_bits_out_uop_ppred_busy;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_stale_pdst_0 = io_lsu_resp_0_bits_out_uop_stale_pdst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_exception_0 = io_lsu_resp_0_bits_out_uop_exception;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_exc_cause_0 = io_lsu_resp_0_bits_out_uop_exc_cause;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_bypassable_0 = io_lsu_resp_0_bits_out_uop_bypassable;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_mem_cmd_0 = io_lsu_resp_0_bits_out_uop_mem_cmd;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_mem_size_0 = io_lsu_resp_0_bits_out_uop_mem_size;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_mem_signed_0 = io_lsu_resp_0_bits_out_uop_mem_signed;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_fence_0 = io_lsu_resp_0_bits_out_uop_is_fence;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_fencei_0 = io_lsu_resp_0_bits_out_uop_is_fencei;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_amo_0 = io_lsu_resp_0_bits_out_uop_is_amo;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_uses_ldq_0 = io_lsu_resp_0_bits_out_uop_uses_ldq;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_uses_stq_0 = io_lsu_resp_0_bits_out_uop_uses_stq;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_resp_0_bits_out_uop_is_sys_pc2epc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_is_unique_0 = io_lsu_resp_0_bits_out_uop_is_unique;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_flush_on_commit_0 = io_lsu_resp_0_bits_out_uop_flush_on_commit;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ldst_is_rs1_0 = io_lsu_resp_0_bits_out_uop_ldst_is_rs1;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ldst_0 = io_lsu_resp_0_bits_out_uop_ldst;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_lrs1_0 = io_lsu_resp_0_bits_out_uop_lrs1;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_lrs2_0 = io_lsu_resp_0_bits_out_uop_lrs2;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_lrs3_0 = io_lsu_resp_0_bits_out_uop_lrs3;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_ldst_val_0 = io_lsu_resp_0_bits_out_uop_ldst_val;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_dst_rtype_0 = io_lsu_resp_0_bits_out_uop_dst_rtype;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_lrs1_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs1_rtype;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_lrs2_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs2_rtype;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_frs3_en_0 = io_lsu_resp_0_bits_out_uop_frs3_en;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_fp_val_0 = io_lsu_resp_0_bits_out_uop_fp_val;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_fp_single_0 = io_lsu_resp_0_bits_out_uop_fp_single;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_xcpt_pf_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_pf_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_xcpt_ae_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ae_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_xcpt_ma_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ma_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_bp_debug_if_0 = io_lsu_resp_0_bits_out_uop_bp_debug_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_bp_xcpt_if_0 = io_lsu_resp_0_bits_out_uop_bp_xcpt_if;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_debug_fsrc_0 = io_lsu_resp_0_bits_out_uop_debug_fsrc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_uop_debug_tsrc_0 = io_lsu_resp_0_bits_out_uop_debug_tsrc;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_data_0 = io_lsu_resp_0_bits_out_data;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_is_hella_0 = io_lsu_resp_0_bits_out_is_hella;\t// @[util.scala:101:23]\n assign io_lsu_resp_0_bits_out_uop_br_mask = _io_lsu_resp_0_bits_out_uop_br_mask_T_1;\t// @[util.scala:89:21, :101:23]\n wire _io_lsu_nack_0_valid_T = s2_valid_0 & s2_send_nack_0;\t// @[dcache.scala:427:49, :862:41]\n wire _io_lsu_nack_0_valid_T_3 = _io_lsu_nack_0_valid_T;\t// @[dcache.scala:862:{41,60}]\n assign _io_lsu_nack_0_valid_T_7 = _io_lsu_nack_0_valid_T_3;\t// @[dcache.scala:862:60, :863:75]\n assign io_lsu_nack_0_valid_0 = _io_lsu_nack_0_valid_T_7;\t// @[dcache.scala:413:7, :863:75]\n assign io_lsu_nack_0_bits_uop_uopc_0 = io_lsu_nack_0_bits_out_uop_uopc;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_inst_0 = io_lsu_nack_0_bits_out_uop_inst;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_debug_inst_0 = io_lsu_nack_0_bits_out_uop_debug_inst;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_rvc_0 = io_lsu_nack_0_bits_out_uop_is_rvc;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_debug_pc_0 = io_lsu_nack_0_bits_out_uop_debug_pc;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_iq_type_0 = io_lsu_nack_0_bits_out_uop_iq_type;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_fu_code_0 = io_lsu_nack_0_bits_out_uop_fu_code;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_br_type_0 = io_lsu_nack_0_bits_out_uop_ctrl_br_type;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_op1_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op1_sel;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_op2_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op2_sel;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_imm_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_imm_sel;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_op_fcn_0 = io_lsu_nack_0_bits_out_uop_ctrl_op_fcn;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_is_load_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_load;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_is_sta_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_sta;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ctrl_is_std_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_std;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_iw_state_0 = io_lsu_nack_0_bits_out_uop_iw_state;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_iw_p1_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p1_poisoned;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_iw_p2_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p2_poisoned;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_br_0 = io_lsu_nack_0_bits_out_uop_is_br;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_jalr_0 = io_lsu_nack_0_bits_out_uop_is_jalr;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_jal_0 = io_lsu_nack_0_bits_out_uop_is_jal;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_sfb_0 = io_lsu_nack_0_bits_out_uop_is_sfb;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_br_mask_0 = io_lsu_nack_0_bits_out_uop_br_mask;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_br_tag_0 = io_lsu_nack_0_bits_out_uop_br_tag;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ftq_idx_0 = io_lsu_nack_0_bits_out_uop_ftq_idx;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_edge_inst_0 = io_lsu_nack_0_bits_out_uop_edge_inst;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_pc_lob_0 = io_lsu_nack_0_bits_out_uop_pc_lob;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_taken_0 = io_lsu_nack_0_bits_out_uop_taken;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_imm_packed_0 = io_lsu_nack_0_bits_out_uop_imm_packed;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_csr_addr_0 = io_lsu_nack_0_bits_out_uop_csr_addr;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_rob_idx_0 = io_lsu_nack_0_bits_out_uop_rob_idx;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ldq_idx_0 = io_lsu_nack_0_bits_out_uop_ldq_idx;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_stq_idx_0 = io_lsu_nack_0_bits_out_uop_stq_idx;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_rxq_idx_0 = io_lsu_nack_0_bits_out_uop_rxq_idx;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_pdst_0 = io_lsu_nack_0_bits_out_uop_pdst;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_prs1_0 = io_lsu_nack_0_bits_out_uop_prs1;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_prs2_0 = io_lsu_nack_0_bits_out_uop_prs2;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_prs3_0 = io_lsu_nack_0_bits_out_uop_prs3;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ppred_0 = io_lsu_nack_0_bits_out_uop_ppred;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_prs1_busy_0 = io_lsu_nack_0_bits_out_uop_prs1_busy;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_prs2_busy_0 = io_lsu_nack_0_bits_out_uop_prs2_busy;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_prs3_busy_0 = io_lsu_nack_0_bits_out_uop_prs3_busy;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ppred_busy_0 = io_lsu_nack_0_bits_out_uop_ppred_busy;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_stale_pdst_0 = io_lsu_nack_0_bits_out_uop_stale_pdst;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_exception_0 = io_lsu_nack_0_bits_out_uop_exception;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_exc_cause_0 = io_lsu_nack_0_bits_out_uop_exc_cause;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_bypassable_0 = io_lsu_nack_0_bits_out_uop_bypassable;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_mem_cmd_0 = io_lsu_nack_0_bits_out_uop_mem_cmd;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_mem_size_0 = io_lsu_nack_0_bits_out_uop_mem_size;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_mem_signed_0 = io_lsu_nack_0_bits_out_uop_mem_signed;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_fence_0 = io_lsu_nack_0_bits_out_uop_is_fence;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_fencei_0 = io_lsu_nack_0_bits_out_uop_is_fencei;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_amo_0 = io_lsu_nack_0_bits_out_uop_is_amo;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_uses_ldq_0 = io_lsu_nack_0_bits_out_uop_uses_ldq;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_uses_stq_0 = io_lsu_nack_0_bits_out_uop_uses_stq;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_sys_pc2epc_0 = io_lsu_nack_0_bits_out_uop_is_sys_pc2epc;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_is_unique_0 = io_lsu_nack_0_bits_out_uop_is_unique;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_flush_on_commit_0 = io_lsu_nack_0_bits_out_uop_flush_on_commit;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ldst_is_rs1_0 = io_lsu_nack_0_bits_out_uop_ldst_is_rs1;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ldst_0 = io_lsu_nack_0_bits_out_uop_ldst;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_lrs1_0 = io_lsu_nack_0_bits_out_uop_lrs1;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_lrs2_0 = io_lsu_nack_0_bits_out_uop_lrs2;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_lrs3_0 = io_lsu_nack_0_bits_out_uop_lrs3;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_ldst_val_0 = io_lsu_nack_0_bits_out_uop_ldst_val;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_dst_rtype_0 = io_lsu_nack_0_bits_out_uop_dst_rtype;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_lrs1_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs1_rtype;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_lrs2_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs2_rtype;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_frs3_en_0 = io_lsu_nack_0_bits_out_uop_frs3_en;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_fp_val_0 = io_lsu_nack_0_bits_out_uop_fp_val;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_fp_single_0 = io_lsu_nack_0_bits_out_uop_fp_single;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_xcpt_pf_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_pf_if;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_xcpt_ae_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ae_if;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_xcpt_ma_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ma_if;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_bp_debug_if_0 = io_lsu_nack_0_bits_out_uop_bp_debug_if;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_bp_xcpt_if_0 = io_lsu_nack_0_bits_out_uop_bp_xcpt_if;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_debug_fsrc_0 = io_lsu_nack_0_bits_out_uop_debug_fsrc;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_uop_debug_tsrc_0 = io_lsu_nack_0_bits_out_uop_debug_tsrc;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_addr_0 = io_lsu_nack_0_bits_out_addr;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_data_0 = io_lsu_nack_0_bits_out_data;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_is_hella_0 = io_lsu_nack_0_bits_out_is_hella;\t// @[util.scala:101:23]\n assign io_lsu_nack_0_bits_out_uop_br_mask = _io_lsu_nack_0_bits_out_uop_br_mask_T_1;\t// @[util.scala:89:21, :101:23]"}}},{"rowIdx":32159,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module Rob : \n input clock : Clock \n input reset : Reset \n output io : { flip enq_valids : UInt<1>[1], flip enq_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip enq_partial_stall : UInt<1>, flip xcpt_fetch_pc : UInt<40>, rob_tail_idx : UInt<5>, rob_pnr_idx : UInt<5>, rob_head_idx : UInt<5>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip wb_resps : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[4], flip lsu_clr_bsy : { valid : UInt<1>, bits : UInt<5>}[2], flip lsu_clr_unsafe : { valid : UInt<1>, bits : UInt<5>}[1], flip debug_wb_valids : UInt<1>[4], flip debug_wb_wdata : UInt<64>[4], flip fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}[2], flip lxcpt : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<40>}}, flip csr_replay : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<40>}}, commit : { valids : UInt<1>[1], arch_valids : UInt<1>[1], uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[1], rbk_valids : UInt<1>[1], rollback : UInt<1>, debug_wdata : UInt<64>[1]}, com_load_is_at_rob_head : UInt<1>, com_xcpt : { valid : UInt<1>, bits : { ftq_idx : UInt<4>, edge_inst : UInt<1>, is_rvc : UInt<1>, pc_lob : UInt<6>, cause : UInt<64>, badvaddr : UInt<64>, flush_typ : UInt<3>}}, flip csr_stall : UInt<1>, flush : { valid : UInt<1>, bits : { ftq_idx : UInt<4>, edge_inst : UInt<1>, is_rvc : UInt<1>, pc_lob : UInt<6>, cause : UInt<64>, badvaddr : UInt<64>, flush_typ : UInt<3>}}, empty : UInt<1>, ready : UInt<1>, flush_frontend : UInt<1>, flip debug_tsc : UInt<64>} \n\n\n regreset rob_state : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset rob_head : UInt<5>, clock, reset, UInt<5>(0h0) \n regreset rob_head_lsb : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset rob_tail : UInt<5>, clock, reset, UInt<5>(0h0) \n regreset rob_tail_lsb : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset rob_pnr : UInt<5>, clock, reset, UInt<5>(0h0) \n regreset rob_pnr_lsb : UInt<1>, clock, reset, UInt<1>(0h0) \n node _com_idx_T = eq(rob_state, UInt<2>(0h2)) \n node com_idx = mux(_com_idx_T, rob_tail, rob_head) \n regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) \n wire full : UInt<1> \n wire empty : UInt<1> \n wire will_commit : UInt<1>[1] \n wire can_commit : UInt<1>[1] \n wire can_throw_exception : UInt<1>[1] \n wire rob_pnr_unsafe : UInt<1>[1] \n wire rob_head_vals : UInt<1>[1] \n wire rob_tail_vals : UInt<1>[1] \n wire rob_head_uses_stq : UInt<1>[1] \n wire rob_head_uses_ldq : UInt<1>[1] \n wire rob_head_fflags : UInt<5>[1] \n wire exception_thrown : UInt<1> \n regreset r_xcpt_val : UInt<1>, clock, reset, UInt<1>(0h0) \n reg r_xcpt_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock \n reg r_xcpt_badvaddr : UInt<40>, clock \n connect io.flush_frontend, r_xcpt_val \n wire debug_entry : { valid : UInt<1>, busy : UInt<1>, unsafe : UInt<1>, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, exception : UInt<1>}[32] \n invalidate debug_entry[0].exception \n invalidate debug_entry[0].uop.debug_tsrc \n invalidate debug_entry[0].uop.debug_fsrc \n invalidate debug_entry[0].uop.bp_xcpt_if \n invalidate debug_entry[0].uop.bp_debug_if \n invalidate debug_entry[0].uop.xcpt_ma_if \n invalidate debug_entry[0].uop.xcpt_ae_if \n invalidate debug_entry[0].uop.xcpt_pf_if \n invalidate debug_entry[0].uop.fp_single \n invalidate debug_entry[0].uop.fp_val \n invalidate debug_entry[0].uop.frs3_en \n invalidate debug_entry[0].uop.lrs2_rtype \n invalidate debug_entry[0].uop.lrs1_rtype \n invalidate debug_entry[0].uop.dst_rtype \n invalidate debug_entry[0].uop.ldst_val \n invalidate debug_entry[0].uop.lrs3 \n invalidate debug_entry[0].uop.lrs2 \n invalidate debug_entry[0].uop.lrs1 \n invalidate debug_entry[0].uop.ldst \n invalidate debug_entry[0].uop.ldst_is_rs1 \n invalidate debug_entry[0].uop.flush_on_commit \n invalidate debug_entry[0].uop.is_unique \n invalidate debug_entry[0].uop.is_sys_pc2epc \n invalidate debug_entry[0].uop.uses_stq \n invalidate debug_entry[0].uop.uses_ldq \n invalidate debug_entry[0].uop.is_amo \n invalidate debug_entry[0].uop.is_fencei \n invalidate debug_entry[0].uop.is_fence \n invalidate debug_entry[0].uop.mem_signed \n invalidate debug_entry[0].uop.mem_size \n invalidate debug_entry[0].uop.mem_cmd \n invalidate debug_entry[0].uop.bypassable \n invalidate debug_entry[0].uop.exc_cause \n invalidate debug_entry[0].uop.exception \n invalidate debug_entry[0].uop.stale_pdst \n invalidate debug_entry[0].uop.ppred_busy \n invalidate debug_entry[0].uop.prs3_busy \n invalidate debug_entry[0].uop.prs2_busy \n invalidate debug_entry[0].uop.prs1_busy \n invalidate debug_entry[0].uop.ppred \n invalidate debug_entry[0].uop.prs3 \n invalidate debug_entry[0].uop.prs2 \n invalidate debug_entry[0].uop.prs1 \n invalidate debug_entry[0].uop.pdst \n invalidate debug_entry[0].uop.rxq_idx \n invalidate debug_entry[0].uop.stq_idx \n invalidate debug_entry[0].uop.ldq_idx \n invalidate debug_entry[0].uop.rob_idx \n invalidate debug_entry[0].uop.csr_addr \n invalidate debug_entry[0].uop.imm_packed \n invalidate debug_entry[0].uop.taken \n invalidate debug_entry[0].uop.pc_lob \n invalidate debug_entry[0].uop.edge_inst \n invalidate debug_entry[0].uop.ftq_idx \n invalidate debug_entry[0].uop.br_tag \n invalidate debug_entry[0].uop.br_mask \n invalidate debug_entry[0].uop.is_sfb \n invalidate debug_entry[0].uop.is_jal \n invalidate debug_entry[0].uop.is_jalr \n invalidate debug_entry[0].uop.is_br \n invalidate debug_entry[0].uop.iw_p2_poisoned \n invalidate debug_entry[0].uop.iw_p1_poisoned \n invalidate debug_entry[0].uop.iw_state \n invalidate debug_entry[0].uop.ctrl.is_std \n invalidate debug_entry[0].uop.ctrl.is_sta \n invalidate debug_entry[0].uop.ctrl.is_load \n invalidate debug_entry[0].uop.ctrl.csr_cmd \n invalidate debug_entry[0].uop.ctrl.fcn_dw \n invalidate debug_entry[0].uop.ctrl.op_fcn \n invalidate debug_entry[0].uop.ctrl.imm_sel \n invalidate debug_entry[0].uop.ctrl.op2_sel \n invalidate debug_entry[0].uop.ctrl.op1_sel \n invalidate debug_entry[0].uop.ctrl.br_type \n invalidate debug_entry[0].uop.fu_code \n invalidate debug_entry[0].uop.iq_type \n invalidate debug_entry[0].uop.debug_pc \n invalidate debug_entry[0].uop.is_rvc \n invalidate debug_entry[0].uop.debug_inst \n invalidate debug_entry[0].uop.inst \n invalidate debug_entry[0].uop.uopc \n invalidate debug_entry[0].unsafe \n invalidate debug_entry[0].busy \n invalidate debug_entry[0].valid \n invalidate debug_entry[1].exception \n invalidate debug_entry[1].uop.debug_tsrc \n invalidate debug_entry[1].uop.debug_fsrc \n invalidate debug_entry[1].uop.bp_xcpt_if \n invalidate debug_entry[1].uop.bp_debug_if \n invalidate debug_entry[1].uop.xcpt_ma_if \n invalidate debug_entry[1].uop.xcpt_ae_if \n invalidate debug_entry[1].uop.xcpt_pf_if \n invalidate debug_entry[1].uop.fp_single \n invalidate debug_entry[1].uop.fp_val \n invalidate debug_entry[1].uop.frs3_en \n invalidate debug_entry[1].uop.lrs2_rtype \n invalidate debug_entry[1].uop.lrs1_rtype \n invalidate debug_entry[1].uop.dst_rtype \n invalidate debug_entry[1].uop.ldst_val \n invalidate debug_entry[1].uop.lrs3 \n invalidate debug_entry[1].uop.lrs2 \n invalidate debug_entry[1].uop.lrs1 \n invalidate debug_entry[1].uop.ldst \n invalidate debug_entry[1].uop.ldst_is_rs1 \n invalidate debug_entry[1].uop.flush_on_commit \n invalidate debug_entry[1].uop.is_unique \n invalidate debug_entry[1].uop.is_sys_pc2epc \n invalidate debug_entry[1].uop.uses_stq \n invalidate debug_entry[1].uop.uses_ldq \n invalidate debug_entry[1].uop.is_amo \n invalidate debug_entry[1].uop.is_fencei \n invalidate debug_entry[1].uop.is_fence \n invalidate debug_entry[1].uop.mem_signed \n invalidate debug_entry[1].uop.mem_size \n invalidate debug_entry[1].uop.mem_cmd \n invalidate debug_entry[1].uop.bypassable \n invalidate debug_entry[1].uop.exc_cause \n invalidate debug_entry[1].uop.exception \n invalidate debug_entry[1].uop.stale_pdst \n invalidate debug_entry[1].uop.ppred_busy \n invalidate debug_entry[1].uop.prs3_busy \n invalidate debug_entry[1].uop.prs2_busy \n invalidate debug_entry[1].uop.prs1_busy \n invalidate debug_entry[1].uop.ppred \n invalidate debug_entry[1].uop.prs3 \n invalidate debug_entry[1].uop.prs2 \n invalidate debug_entry[1].uop.prs1 \n invalidate debug_entry[1].uop.pdst \n invalidate debug_entry[1].uop.rxq_idx \n invalidate debug_entry[1].uop.stq_idx \n invalidate debug_entry[1].uop.ldq_idx \n invalidate debug_entry[1].uop.rob_idx \n invalidate debug_entry[1].uop.csr_addr \n invalidate debug_entry[1].uop.imm_packed \n invalidate debug_entry[1].uop.taken \n invalidate debug_entry[1].uop.pc_lob \n invalidate debug_entry[1].uop.edge_inst \n invalidate debug_entry[1].uop.ftq_idx \n invalidate debug_entry[1].uop.br_tag \n invalidate debug_entry[1].uop.br_mask \n invalidate debug_entry[1].uop.is_sfb \n invalidate debug_entry[1].uop.is_jal \n invalidate debug_entry[1].uop.is_jalr \n invalidate debug_entry[1].uop.is_br \n invalidate debug_entry[1].uop.iw_p2_poisoned \n invalidate debug_entry[1].uop.iw_p1_poisoned \n invalidate debug_entry[1].uop.iw_state \n invalidate debug_entry[1].uop.ctrl.is_std \n invalidate debug_entry[1].uop.ctrl.is_sta \n invalidate debug_entry[1].uop.ctrl.is_load \n invalidate debug_entry[1].uop.ctrl.csr_cmd \n invalidate debug_entry[1].uop.ctrl.fcn_dw \n invalidate debug_entry[1].uop.ctrl.op_fcn \n invalidate debug_entry[1].uop.ctrl.imm_sel \n invalidate debug_entry[1].uop.ctrl.op2_sel \n invalidate debug_entry[1].uop.ctrl.op1_sel \n invalidate debug_entry[1].uop.ctrl.br_type \n invalidate debug_entry[1].uop.fu_code \n invalidate debug_entry[1].uop.iq_type \n invalidate debug_entry[1].uop.debug_pc \n invalidate debug_entry[1].uop.is_rvc \n invalidate debug_entry[1].uop.debug_inst \n invalidate debug_entry[1].uop.inst \n invalidate debug_entry[1].uop.uopc \n invalidate debug_entry[1].unsafe \n invalidate debug_entry[1].busy \n invalidate debug_entry[1].valid \n invalidate debug_entry[2].exception \n invalidate debug_entry[2].uop.debug_tsrc \n invalidate debug_entry[2].uop.debug_fsrc \n invalidate debug_entry[2].uop.bp_xcpt_if \n invalidate debug_entry[2].uop.bp_debug_if \n invalidate debug_entry[2].uop.xcpt_ma_if \n invalidate debug_entry[2].uop.xcpt_ae_if \n invalidate debug_entry[2].uop.xcpt_pf_if \n invalidate debug_entry[2].uop.fp_single \n invalidate debug_entry[2].uop.fp_val \n invalidate debug_entry[2].uop.frs3_en \n invalidate debug_entry[2].uop.lrs2_rtype \n invalidate debug_entry[2].uop.lrs1_rtype \n invalidate debug_entry[2].uop.dst_rtype \n invalidate debug_entry[2].uop.ldst_val \n invalidate debug_entry[2].uop.lrs3 \n invalidate debug_entry[2].uop.lrs2 \n invalidate debug_entry[2].uop.lrs1 \n invalidate debug_entry[2].uop.ldst \n invalidate debug_entry[2].uop.ldst_is_rs1 \n invalidate debug_entry[2].uop.flush_on_commit \n invalidate debug_entry[2].uop.is_unique \n invalidate debug_entry[2].uop.is_sys_pc2epc \n invalidate debug_entry[2].uop.uses_stq \n invalidate debug_entry[2].uop.uses_ldq \n invalidate debug_entry[2].uop.is_amo \n invalidate debug_entry[2].uop.is_fencei \n invalidate debug_entry[2].uop.is_fence \n invalidate debug_entry[2].uop.mem_signed \n invalidate debug_entry[2].uop.mem_size \n invalidate debug_entry[2].uop.mem_cmd \n invalidate debug_entry[2].uop.bypassable \n invalidate debug_entry[2].uop.exc_cause \n invalidate debug_entry[2].uop.exception \n invalidate debug_entry[2].uop.stale_pdst \n invalidate debug_entry[2].uop.ppred_busy \n invalidate debug_entry[2].uop.prs3_busy \n invalidate debug_entry[2].uop.prs2_busy \n invalidate debug_entry[2].uop.prs1_busy \n invalidate debug_entry[2].uop.ppred \n invalidate debug_entry[2].uop.prs3 \n invalidate debug_entry[2].uop.prs2 \n invalidate debug_entry[2].uop.prs1 \n invalidate debug_entry[2].uop.pdst \n invalidate debug_entry[2].uop.rxq_idx \n invalidate debug_entry[2].uop.stq_idx \n invalidate debug_entry[2].uop.ldq_idx \n invalidate debug_entry[2].uop.rob_idx \n invalidate debug_entry[2].uop.csr_addr \n invalidate debug_entry[2].uop.imm_packed \n invalidate debug_entry[2].uop.taken \n invalidate debug_entry[2].uop.pc_lob \n invalidate debug_entry[2].uop.edge_inst \n invalidate debug_entry[2].uop.ftq_idx \n invalidate debug_entry[2].uop.br_tag \n invalidate debug_entry[2].uop.br_mask \n invalidate debug_entry[2].uop.is_sfb \n invalidate debug_entry[2].uop.is_jal \n invalidate debug_entry[2].uop.is_jalr \n invalidate debug_entry[2].uop.is_br \n invalidate debug_entry[2].uop.iw_p2_poisoned \n invalidate debug_entry[2].uop.iw_p1_poisoned \n invalidate debug_entry[2].uop.iw_state \n invalidate debug_entry[2].uop.ctrl.is_std \n invalidate debug_entry[2].uop.ctrl.is_sta \n invalidate debug_entry[2].uop.ctrl.is_load \n invalidate debug_entry[2].uop.ctrl.csr_cmd \n invalidate debug_entry[2].uop.ctrl.fcn_dw \n invalidate debug_entry[2].uop.ctrl.op_fcn \n invalidate debug_entry[2].uop.ctrl.imm_sel \n invalidate debug_entry[2].uop.ctrl.op2_sel \n invalidate debug_entry[2].uop.ctrl.op1_sel \n invalidate debug_entry[2].uop.ctrl.br_type \n invalidate debug_entry[2].uop.fu_code \n invalidate debug_entry[2].uop.iq_type \n invalidate debug_entry[2].uop.debug_pc \n invalidate debug_entry[2].uop.is_rvc \n invalidate debug_entry[2].uop.debug_inst \n invalidate debug_entry[2].uop.inst \n invalidate debug_entry[2].uop.uopc \n invalidate debug_entry[2].unsafe \n invalidate debug_entry[2].busy \n invalidate debug_entry[2].valid \n invalidate debug_entry[3].exception \n invalidate debug_entry[3].uop.debug_tsrc \n invalidate debug_entry[3].uop.debug_fsrc \n invalidate debug_entry[3].uop.bp_xcpt_if \n invalidate debug_entry[3].uop.bp_debug_if \n invalidate debug_entry[3].uop.xcpt_ma_if \n invalidate debug_entry[3].uop.xcpt_ae_if \n invalidate debug_entry[3].uop.xcpt_pf_if \n invalidate debug_entry[3].uop.fp_single \n invalidate debug_entry[3].uop.fp_val \n invalidate debug_entry[3].uop.frs3_en \n invalidate debug_entry[3].uop.lrs2_rtype \n invalidate debug_entry[3].uop.lrs1_rtype \n invalidate debug_entry[3].uop.dst_rtype \n invalidate debug_entry[3].uop.ldst_val \n invalidate debug_entry[3].uop.lrs3 \n invalidate debug_entry[3].uop.lrs2 \n invalidate debug_entry[3].uop.lrs1 \n invalidate debug_entry[3].uop.ldst \n invalidate debug_entry[3].uop.ldst_is_rs1 \n invalidate debug_entry[3].uop.flush_on_commit \n invalidate debug_entry[3].uop.is_unique \n invalidate debug_entry[3].uop.is_sys_pc2epc \n invalidate debug_entry[3].uop.uses_stq \n invalidate debug_entry[3].uop.uses_ldq \n invalidate debug_entry[3].uop.is_amo \n invalidate debug_entry[3].uop.is_fencei \n invalidate debug_entry[3].uop.is_fence \n invalidate debug_entry[3].uop.mem_signed \n invalidate debug_entry[3].uop.mem_size \n invalidate debug_entry[3].uop.mem_cmd \n invalidate debug_entry[3].uop.bypassable \n invalidate debug_entry[3].uop.exc_cause \n invalidate debug_entry[3].uop.exception \n invalidate debug_entry[3].uop.stale_pdst \n invalidate debug_entry[3].uop.ppred_busy \n invalidate debug_entry[3].uop.prs3_busy \n invalidate debug_entry[3].uop.prs2_busy \n invalidate debug_entry[3].uop.prs1_busy \n invalidate debug_entry[3].uop.ppred \n invalidate debug_entry[3].uop.prs3 \n invalidate debug_entry[3].uop.prs2 \n invalidate debug_entry[3].uop.prs1 \n invalidate debug_entry[3].uop.pdst \n invalidate debug_entry[3].uop.rxq_idx \n invalidate debug_entry[3].uop.stq_idx \n invalidate debug_entry[3].uop.ldq_idx \n invalidate debug_entry[3].uop.rob_idx \n invalidate debug_entry[3].uop.csr_addr \n invalidate debug_entry[3].uop.imm_packed \n invalidate debug_entry[3].uop.taken \n invalidate debug_entry[3].uop.pc_lob \n invalidate debug_entry[3].uop.edge_inst \n invalidate debug_entry[3].uop.ftq_idx \n invalidate debug_entry[3].uop.br_tag \n invalidate debug_entry[3].uop.br_mask \n invalidate debug_entry[3].uop.is_sfb \n invalidate debug_entry[3].uop.is_jal \n invalidate debug_entry[3].uop.is_jalr \n invalidate debug_entry[3].uop.is_br \n invalidate debug_entry[3].uop.iw_p2_poisoned \n invalidate debug_entry[3].uop.iw_p1_poisoned \n invalidate debug_entry[3].uop.iw_state \n invalidate debug_entry[3].uop.ctrl.is_std \n invalidate debug_entry[3].uop.ctrl.is_sta \n invalidate debug_entry[3].uop.ctrl.is_load \n invalidate debug_entry[3].uop.ctrl.csr_cmd \n invalidate debug_entry[3].uop.ctrl.fcn_dw \n invalidate debug_entry[3].uop.ctrl.op_fcn \n invalidate debug_entry[3].uop.ctrl.imm_sel \n invalidate debug_entry[3].uop.ctrl.op2_sel \n invalidate debug_entry[3].uop.ctrl.op1_sel \n invalidate debug_entry[3].uop.ctrl.br_type \n invalidate debug_entry[3].uop.fu_code \n invalidate debug_entry[3].uop.iq_type \n invalidate debug_entry[3].uop.debug_pc \n invalidate debug_entry[3].uop.is_rvc \n invalidate debug_entry[3].uop.debug_inst \n invalidate debug_entry[3].uop.inst \n invalidate debug_entry[3].uop.uopc \n invalidate debug_entry[3].unsafe \n invalidate debug_entry[3].busy \n invalidate debug_entry[3].valid \n invalidate debug_entry[4].exception \n invalidate debug_entry[4].uop.debug_tsrc \n invalidate debug_entry[4].uop.debug_fsrc \n invalidate debug_entry[4].uop.bp_xcpt_if \n invalidate debug_entry[4].uop.bp_debug_if \n invalidate debug_entry[4].uop.xcpt_ma_if \n invalidate debug_entry[4].uop.xcpt_ae_if \n invalidate debug_entry[4].uop.xcpt_pf_if \n invalidate debug_entry[4].uop.fp_single \n invalidate debug_entry[4].uop.fp_val \n invalidate debug_entry[4].uop.frs3_en \n invalidate debug_entry[4].uop.lrs2_rtype \n invalidate debug_entry[4].uop.lrs1_rtype \n invalidate debug_entry[4].uop.dst_rtype \n invalidate debug_entry[4].uop.ldst_val \n invalidate debug_entry[4].uop.lrs3 \n invalidate debug_entry[4].uop.lrs2 \n invalidate debug_entry[4].uop.lrs1 \n invalidate debug_entry[4].uop.ldst \n invalidate debug_entry[4].uop.ldst_is_rs1 \n invalidate debug_entry[4].uop.flush_on_commit \n invalidate debug_entry[4].uop.is_unique \n invalidate debug_entry[4].uop.is_sys_pc2epc \n invalidate debug_entry[4].uop.uses_stq \n invalidate debug_entry[4].uop.uses_ldq \n invalidate debug_entry[4].uop.is_amo \n invalidate debug_entry[4].uop.is_fencei \n invalidate debug_entry[4].uop.is_fence \n invalidate debug_entry[4].uop.mem_signed \n invalidate debug_entry[4].uop.mem_size \n invalidate debug_entry[4].uop.mem_cmd \n invalidate debug_entry[4].uop.bypassable \n invalidate debug_entry[4].uop.exc_cause \n invalidate debug_entry[4].uop.exception \n invalidate debug_entry[4].uop.stale_pdst \n invalidate debug_entry[4].uop.ppred_busy \n invalidate debug_entry[4].uop.prs3_busy \n invalidate debug_entry[4].uop.prs2_busy \n invalidate debug_entry[4].uop.prs1_busy \n invalidate debug_entry[4].uop.ppred \n invalidate debug_entry[4].uop.prs3 \n invalidate debug_entry[4].uop.prs2 \n invalidate debug_entry[4].uop.prs1 \n invalidate debug_entry[4].uop.pdst \n invalidate debug_entry[4].uop.rxq_idx \n invalidate debug_entry[4].uop.stq_idx \n invalidate debug_entry[4].uop.ldq_idx \n invalidate debug_entry[4].uop.rob_idx \n invalidate debug_entry[4].uop.csr_addr \n invalidate debug_entry[4].uop.imm_packed \n invalidate debug_entry[4].uop.taken \n invalidate debug_entry[4].uop.pc_lob \n invalidate debug_entry[4].uop.edge_inst \n invalidate debug_entry[4].uop.ftq_idx \n invalidate debug_entry[4].uop.br_tag \n invalidate debug_entry[4].uop.br_mask \n invalidate debug_entry[4].uop.is_sfb \n invalidate debug_entry[4].uop.is_jal \n invalidate debug_entry[4].uop.is_jalr \n invalidate debug_entry[4].uop.is_br \n invalidate debug_entry[4].uop.iw_p2_poisoned \n invalidate debug_entry[4].uop.iw_p1_poisoned \n invalidate debug_entry[4].uop.iw_state \n invalidate debug_entry[4].uop.ctrl.is_std \n invalidate debug_entry[4].uop.ctrl.is_sta \n invalidate debug_entry[4].uop.ctrl.is_load \n invalidate debug_entry[4].uop.ctrl.csr_cmd \n invalidate debug_entry[4].uop.ctrl.fcn_dw \n invalidate debug_entry[4].uop.ctrl.op_fcn \n invalidate debug_entry[4].uop.ctrl.imm_sel \n invalidate debug_entry[4].uop.ctrl.op2_sel \n invalidate debug_entry[4].uop.ctrl.op1_sel \n invalidate debug_entry[4].uop.ctrl.br_type \n invalidate debug_entry[4].uop.fu_code \n invalidate debug_entry[4].uop.iq_type \n invalidate debug_entry[4].uop.debug_pc \n invalidate debug_entry[4].uop.is_rvc \n invalidate debug_entry[4].uop.debug_inst \n invalidate debug_entry[4].uop.inst \n invalidate debug_entry[4].uop.uopc \n invalidate debug_entry[4].unsafe \n invalidate debug_entry[4].busy \n invalidate debug_entry[4].valid \n invalidate debug_entry[5].exception \n invalidate debug_entry[5].uop.debug_tsrc \n invalidate debug_entry[5].uop.debug_fsrc \n invalidate debug_entry[5].uop.bp_xcpt_if \n invalidate debug_entry[5].uop.bp_debug_if \n invalidate debug_entry[5].uop.xcpt_ma_if \n invalidate debug_entry[5].uop.xcpt_ae_if \n invalidate debug_entry[5].uop.xcpt_pf_if \n invalidate debug_entry[5].uop.fp_single \n invalidate debug_entry[5].uop.fp_val \n invalidate debug_entry[5].uop.frs3_en \n invalidate debug_entry[5].uop.lrs2_rtype \n invalidate debug_entry[5].uop.lrs1_rtype \n invalidate debug_entry[5].uop.dst_rtype \n invalidate debug_entry[5].uop.ldst_val \n invalidate debug_entry[5].uop.lrs3 \n invalidate debug_entry[5].uop.lrs2 \n invalidate debug_entry[5].uop.lrs1 \n invalidate debug_entry[5].uop.ldst \n invalidate debug_entry[5].uop.ldst_is_rs1 \n invalidate debug_entry[5].uop.flush_on_commit \n invalidate debug_entry[5].uop.is_unique \n invalidate debug_entry[5].uop.is_sys_pc2epc \n invalidate debug_entry[5].uop.uses_stq \n invalidate debug_entry[5].uop.uses_ldq \n invalidate debug_entry[5].uop.is_amo \n invalidate debug_entry[5].uop.is_fencei \n invalidate debug_entry[5].uop.is_fence \n invalidate debug_entry[5].uop.mem_signed \n invalidate debug_entry[5].uop.mem_size \n invalidate debug_entry[5].uop.mem_cmd \n invalidate debug_entry[5].uop.bypassable \n invalidate debug_entry[5].uop.exc_cause \n invalidate debug_entry[5].uop.exception \n invalidate debug_entry[5].uop.stale_pdst \n invalidate debug_entry[5].uop.ppred_busy \n invalidate debug_entry[5].uop.prs3_busy \n invalidate debug_entry[5].uop.prs2_busy \n invalidate debug_entry[5].uop.prs1_busy \n invalidate debug_entry[5].uop.ppred \n invalidate debug_entry[5].uop.prs3 \n invalidate debug_entry[5].uop.prs2 \n invalidate debug_entry[5].uop.prs1 \n invalidate debug_entry[5].uop.pdst \n invalidate debug_entry[5].uop.rxq_idx \n invalidate debug_entry[5].uop.stq_idx \n invalidate debug_entry[5].uop.ldq_idx \n invalidate debug_entry[5].uop.rob_idx \n invalidate debug_entry[5].uop.csr_addr \n invalidate debug_entry[5].uop.imm_packed \n invalidate debug_entry[5].uop.taken \n invalidate debug_entry[5].uop.pc_lob \n invalidate debug_entry[5].uop.edge_inst \n invalidate debug_entry[5].uop.ftq_idx \n invalidate debug_entry[5].uop.br_tag \n invalidate debug_entry[5].uop.br_mask \n invalidate debug_entry[5].uop.is_sfb \n invalidate debug_entry[5].uop.is_jal \n invalidate debug_entry[5].uop.is_jalr \n invalidate debug_entry[5].uop.is_br \n invalidate debug_entry[5].uop.iw_p2_poisoned \n invalidate debug_entry[5].uop.iw_p1_poisoned \n invalidate debug_entry[5].uop.iw_state \n invalidate debug_entry[5].uop.ctrl.is_std \n invalidate debug_entry[5].uop.ctrl.is_sta \n invalidate debug_entry[5].uop.ctrl.is_load \n invalidate debug_entry[5].uop.ctrl.csr_cmd \n invalidate debug_entry[5].uop.ctrl.fcn_dw \n invalidate debug_entry[5].uop.ctrl.op_fcn \n invalidate debug_entry[5].uop.ctrl.imm_sel \n invalidate debug_entry[5].uop.ctrl.op2_sel \n invalidate debug_entry[5].uop.ctrl.op1_sel \n invalidate debug_entry[5].uop.ctrl.br_type \n invalidate debug_entry[5].uop.fu_code \n invalidate debug_entry[5].uop.iq_type \n invalidate debug_entry[5].uop.debug_pc \n invalidate debug_entry[5].uop.is_rvc \n invalidate debug_entry[5].uop.debug_inst \n invalidate debug_entry[5].uop.inst \n invalidate debug_entry[5].uop.uopc \n invalidate debug_entry[5].unsafe \n invalidate debug_entry[5].busy \n invalidate debug_entry[5].valid \n invalidate debug_entry[6].exception \n invalidate debug_entry[6].uop.debug_tsrc \n invalidate debug_entry[6].uop.debug_fsrc \n invalidate debug_entry[6].uop.bp_xcpt_if \n invalidate debug_entry[6].uop.bp_debug_if \n invalidate debug_entry[6].uop.xcpt_ma_if \n invalidate debug_entry[6].uop.xcpt_ae_if \n invalidate debug_entry[6].uop.xcpt_pf_if \n invalidate debug_entry[6].uop.fp_single \n invalidate debug_entry[6].uop.fp_val \n invalidate debug_entry[6].uop.frs3_en \n invalidate debug_entry[6].uop.lrs2_rtype \n invalidate debug_entry[6].uop.lrs1_rtype \n invalidate debug_entry[6].uop.dst_rtype \n invalidate debug_entry[6].uop.ldst_val \n invalidate debug_entry[6].uop.lrs3 \n invalidate debug_entry[6].uop.lrs2 \n invalidate debug_entry[6].uop.lrs1 \n invalidate debug_entry[6].uop.ldst \n invalidate debug_entry[6].uop.ldst_is_rs1 \n invalidate debug_entry[6].uop.flush_on_commit \n invalidate debug_entry[6].uop.is_unique \n invalidate debug_entry[6].uop.is_sys_pc2epc \n invalidate debug_entry[6].uop.uses_stq \n invalidate debug_entry[6].uop.uses_ldq \n invalidate debug_entry[6].uop.is_amo \n invalidate debug_entry[6].uop.is_fencei \n invalidate debug_entry[6].uop.is_fence \n invalidate debug_entry[6].uop.mem_signed \n invalidate debug_entry[6].uop.mem_size \n invalidate debug_entry[6].uop.mem_cmd \n invalidate debug_entry[6].uop.bypassable \n invalidate debug_entry[6].uop.exc_cause \n invalidate debug_entry[6].uop.exception \n invalidate debug_entry[6].uop.stale_pdst \n invalidate debug_entry[6].uop.ppred_busy \n invalidate debug_entry[6].uop.prs3_busy \n invalidate debug_entry[6].uop.prs2_busy \n invalidate debug_entry[6].uop.prs1_busy \n invalidate debug_entry[6].uop.ppred \n invalidate debug_entry[6].uop.prs3 \n invalidate debug_entry[6].uop.prs2 \n invalidate debug_entry[6].uop.prs1 \n invalidate debug_entry[6].uop.pdst \n invalidate debug_entry[6].uop.rxq_idx \n invalidate debug_entry[6].uop.stq_idx \n invalidate debug_entry[6].uop.ldq_idx \n invalidate debug_entry[6].uop.rob_idx \n invalidate debug_entry[6].uop.csr_addr \n invalidate debug_entry[6].uop.imm_packed \n invalidate debug_entry[6].uop.taken \n invalidate debug_entry[6].uop.pc_lob \n invalidate debug_entry[6].uop.edge_inst \n invalidate debug_entry[6].uop.ftq_idx \n invalidate debug_entry[6].uop.br_tag \n invalidate debug_entry[6].uop.br_mask \n invalidate debug_entry[6].uop.is_sfb \n invalidate debug_entry[6].uop.is_jal \n invalidate debug_entry[6].uop.is_jalr \n invalidate debug_entry[6].uop.is_br \n invalidate debug_entry[6].uop.iw_p2_poisoned \n invalidate debug_entry[6].uop.iw_p1_poisoned \n invalidate debug_entry[6].uop.iw_state \n invalidate debug_entry[6].uop.ctrl.is_std \n invalidate debug_entry[6].uop.ctrl.is_sta \n invalidate debug_entry[6].uop.ctrl.is_load \n invalidate debug_entry[6].uop.ctrl.csr_cmd \n invalidate debug_entry[6].uop.ctrl.fcn_dw \n invalidate debug_entry[6].uop.ctrl.op_fcn \n invalidate debug_entry[6].uop.ctrl.imm_sel \n invalidate debug_entry[6].uop.ctrl.op2_sel \n invalidate debug_entry[6].uop.ctrl.op1_sel \n invalidate debug_entry[6].uop.ctrl.br_type \n invalidate debug_entry[6].uop.fu_code \n invalidate debug_entry[6].uop.iq_type \n invalidate debug_entry[6].uop.debug_pc \n invalidate debug_entry[6].uop.is_rvc \n invalidate debug_entry[6].uop.debug_inst \n invalidate debug_entry[6].uop.inst \n invalidate debug_entry[6].uop.uopc \n invalidate debug_entry[6].unsafe \n invalidate debug_entry[6].busy \n invalidate debug_entry[6].valid \n invalidate debug_entry[7].exception \n invalidate debug_entry[7].uop.debug_tsrc \n invalidate debug_entry[7].uop.debug_fsrc \n invalidate debug_entry[7].uop.bp_xcpt_if \n invalidate debug_entry[7].uop.bp_debug_if \n invalidate debug_entry[7].uop.xcpt_ma_if \n invalidate debug_entry[7].uop.xcpt_ae_if \n invalidate debug_entry[7].uop.xcpt_pf_if \n invalidate debug_entry[7].uop.fp_single \n invalidate debug_entry[7].uop.fp_val \n invalidate debug_entry[7].uop.frs3_en \n invalidate debug_entry[7].uop.lrs2_rtype \n invalidate debug_entry[7].uop.lrs1_rtype \n invalidate debug_entry[7].uop.dst_rtype \n invalidate debug_entry[7].uop.ldst_val \n invalidate debug_entry[7].uop.lrs3 \n invalidate debug_entry[7].uop.lrs2 \n invalidate debug_entry[7].uop.lrs1 \n invalidate debug_entry[7].uop.ldst \n invalidate debug_entry[7].uop.ldst_is_rs1 \n invalidate debug_entry[7].uop.flush_on_commit \n invalidate debug_entry[7].uop.is_unique \n invalidate debug_entry[7].uop.is_sys_pc2epc \n invalidate debug_entry[7].uop.uses_stq \n invalidate debug_entry[7].uop.uses_ldq \n invalidate debug_entry[7].uop.is_amo \n invalidate debug_entry[7].uop.is_fencei \n invalidate debug_entry[7].uop.is_fence \n invalidate debug_entry[7].uop.mem_signed \n invalidate debug_entry[7].uop.mem_size \n invalidate debug_entry[7].uop.mem_cmd \n invalidate debug_entry[7].uop.bypassable \n invalidate debug_entry[7].uop.exc_cause \n invalidate debug_entry[7].uop.exception \n invalidate debug_entry[7].uop.stale_pdst \n invalidate debug_entry[7].uop.ppred_busy \n invalidate debug_entry[7].uop.prs3_busy \n invalidate debug_entry[7].uop.prs2_busy \n invalidate debug_entry[7].uop.prs1_busy \n invalidate debug_entry[7].uop.ppred \n invalidate debug_entry[7].uop.prs3 \n invalidate debug_entry[7].uop.prs2 \n invalidate debug_entry[7].uop.prs1 \n invalidate debug_entry[7].uop.pdst \n invalidate debug_entry[7].uop.rxq_idx \n invalidate debug_entry[7].uop.stq_idx \n invalidate debug_entry[7].uop.ldq_idx \n invalidate debug_entry[7].uop.rob_idx \n invalidate debug_entry[7].uop.csr_addr \n invalidate debug_entry[7].uop.imm_packed \n invalidate debug_entry[7].uop.taken \n invalidate debug_entry[7].uop.pc_lob \n invalidate debug_entry[7].uop.edge_inst \n invalidate debug_entry[7].uop.ftq_idx \n invalidate debug_entry[7].uop.br_tag \n invalidate debug_entry[7].uop.br_mask \n invalidate debug_entry[7].uop.is_sfb \n invalidate debug_entry[7].uop.is_jal \n invalidate debug_entry[7].uop.is_jalr \n invalidate debug_entry[7].uop.is_br \n invalidate debug_entry[7].uop.iw_p2_poisoned \n invalidate debug_entry[7].uop.iw_p1_poisoned \n invalidate debug_entry[7].uop.iw_state \n invalidate debug_entry[7].uop.ctrl.is_std \n invalidate debug_entry[7].uop.ctrl.is_sta \n invalidate debug_entry[7].uop.ctrl.is_load \n invalidate debug_entry[7].uop.ctrl.csr_cmd \n invalidate debug_entry[7].uop.ctrl.fcn_dw \n invalidate debug_entry[7].uop.ctrl.op_fcn \n invalidate debug_entry[7].uop.ctrl.imm_sel \n invalidate debug_entry[7].uop.ctrl.op2_sel \n invalidate debug_entry[7].uop.ctrl.op1_sel \n invalidate debug_entry[7].uop.ctrl.br_type \n invalidate debug_entry[7].uop.fu_code \n invalidate debug_entry[7].uop.iq_type \n invalidate debug_entry[7].uop.debug_pc \n invalidate debug_entry[7].uop.is_rvc \n invalidate debug_entry[7].uop.debug_inst \n invalidate debug_entry[7].uop.inst \n invalidate debug_entry[7].uop.uopc \n invalidate debug_entry[7].unsafe \n invalidate debug_entry[7].busy \n invalidate debug_entry[7].valid \n invalidate debug_entry[8].exception \n invalidate debug_entry[8].uop.debug_tsrc \n invalidate debug_entry[8].uop.debug_fsrc \n invalidate debug_entry[8].uop.bp_xcpt_if \n invalidate debug_entry[8].uop.bp_debug_if \n invalidate debug_entry[8].uop.xcpt_ma_if \n invalidate debug_entry[8].uop.xcpt_ae_if \n invalidate debug_entry[8].uop.xcpt_pf_if \n invalidate debug_entry[8].uop.fp_single \n invalidate debug_entry[8].uop.fp_val \n invalidate debug_entry[8].uop.frs3_en \n invalidate debug_entry[8].uop.lrs2_rtype \n invalidate debug_entry[8].uop.lrs1_rtype \n invalidate debug_entry[8].uop.dst_rtype \n invalidate debug_entry[8].uop.ldst_val \n invalidate debug_entry[8].uop.lrs3 \n invalidate debug_entry[8].uop.lrs2 \n invalidate debug_entry[8].uop.lrs1 \n invalidate debug_entry[8].uop.ldst \n invalidate debug_entry[8].uop.ldst_is_rs1 \n invalidate debug_entry[8].uop.flush_on_commit \n invalidate debug_entry[8].uop.is_unique \n invalidate debug_entry[8].uop.is_sys_pc2epc \n invalidate debug_entry[8].uop.uses_stq \n invalidate debug_entry[8].uop.uses_ldq \n invalidate debug_entry[8].uop.is_amo \n invalidate debug_entry[8].uop.is_fencei \n invalidate debug_entry[8].uop.is_fence \n invalidate debug_entry[8].uop.mem_signed \n invalidate debug_entry[8].uop.mem_size \n invalidate debug_entry[8].uop.mem_cmd \n invalidate debug_entry[8].uop.bypassable \n invalidate debug_entry[8].uop.exc_cause \n invalidate debug_entry[8].uop.exception \n invalidate debug_entry[8].uop.stale_pdst \n invalidate debug_entry[8].uop.ppred_busy \n invalidate debug_entry[8].uop.prs3_busy \n invalidate debug_entry[8].uop.prs2_busy \n invalidate debug_entry[8].uop.prs1_busy \n invalidate debug_entry[8].uop.ppred \n invalidate debug_entry[8].uop.prs3 \n invalidate debug_entry[8].uop.prs2 \n invalidate debug_entry[8].uop.prs1 \n invalidate debug_entry[8].uop.pdst \n invalidate debug_entry[8].uop.rxq_idx \n invalidate debug_entry[8].uop.stq_idx \n invalidate debug_entry[8].uop.ldq_idx \n invalidate debug_entry[8].uop.rob_idx \n invalidate debug_entry[8].uop.csr_addr \n invalidate debug_entry[8].uop.imm_packed \n invalidate debug_entry[8].uop.taken \n invalidate debug_entry[8].uop.pc_lob \n invalidate debug_entry[8].uop.edge_inst \n invalidate debug_entry[8].uop.ftq_idx \n invalidate debug_entry[8].uop.br_tag \n invalidate debug_entry[8].uop.br_mask \n invalidate debug_entry[8].uop.is_sfb \n invalidate debug_entry[8].uop.is_jal \n invalidate debug_entry[8].uop.is_jalr \n invalidate debug_entry[8].uop.is_br \n invalidate debug_entry[8].uop.iw_p2_poisoned \n invalidate debug_entry[8].uop.iw_p1_poisoned \n invalidate debug_entry[8].uop.iw_state \n invalidate debug_entry[8].uop.ctrl.is_std \n invalidate debug_entry[8].uop.ctrl.is_sta \n invalidate debug_entry[8].uop.ctrl.is_load \n invalidate debug_entry[8].uop.ctrl.csr_cmd \n invalidate debug_entry[8].uop.ctrl.fcn_dw \n invalidate debug_entry[8].uop.ctrl.op_fcn \n invalidate debug_entry[8].uop.ctrl.imm_sel \n invalidate debug_entry[8].uop.ctrl.op2_sel \n invalidate debug_entry[8].uop.ctrl.op1_sel \n invalidate debug_entry[8].uop.ctrl.br_type \n invalidate debug_entry[8].uop.fu_code \n invalidate debug_entry[8].uop.iq_type \n invalidate debug_entry[8].uop.debug_pc \n invalidate debug_entry[8].uop.is_rvc \n invalidate debug_entry[8].uop.debug_inst \n invalidate debug_entry[8].uop.inst \n invalidate debug_entry[8].uop.uopc \n invalidate debug_entry[8].unsafe \n invalidate debug_entry[8].busy \n invalidate debug_entry[8].valid \n invalidate debug_entry[9].exception \n invalidate debug_entry[9].uop.debug_tsrc \n invalidate debug_entry[9].uop.debug_fsrc \n invalidate debug_entry[9].uop.bp_xcpt_if \n invalidate debug_entry[9].uop.bp_debug_if \n invalidate debug_entry[9].uop.xcpt_ma_if \n invalidate debug_entry[9].uop.xcpt_ae_if \n invalidate debug_entry[9].uop.xcpt_pf_if \n invalidate debug_entry[9].uop.fp_single \n invalidate debug_entry[9].uop.fp_val \n invalidate debug_entry[9].uop.frs3_en \n invalidate debug_entry[9].uop.lrs2_rtype \n invalidate debug_entry[9].uop.lrs1_rtype \n invalidate debug_entry[9].uop.dst_rtype \n invalidate debug_entry[9].uop.ldst_val \n invalidate debug_entry[9].uop.lrs3 \n invalidate debug_entry[9].uop.lrs2 \n invalidate debug_entry[9].uop.lrs1 \n invalidate debug_entry[9].uop.ldst \n invalidate debug_entry[9].uop.ldst_is_rs1 \n invalidate debug_entry[9].uop.flush_on_commit \n invalidate debug_entry[9].uop.is_unique \n invalidate debug_entry[9].uop.is_sys_pc2epc \n invalidate debug_entry[9].uop.uses_stq \n invalidate debug_entry[9].uop.uses_ldq \n invalidate debug_entry[9].uop.is_amo \n invalidate debug_entry[9].uop.is_fencei \n invalidate debug_entry[9].uop.is_fence \n invalidate debug_entry[9].uop.mem_signed \n invalidate debug_entry[9].uop.mem_size \n invalidate debug_entry[9].uop.mem_cmd \n invalidate debug_entry[9].uop.bypassable \n invalidate debug_entry[9].uop.exc_cause \n invalidate debug_entry[9].uop.exception \n invalidate debug_entry[9].uop.stale_pdst \n invalidate debug_entry[9].uop.ppred_busy \n invalidate debug_entry[9].uop.prs3_busy \n invalidate debug_entry[9].uop.prs2_busy \n invalidate debug_entry[9].uop.prs1_busy \n invalidate debug_entry[9].uop.ppred \n invalidate debug_entry[9].uop.prs3 \n invalidate debug_entry[9].uop.prs2 \n invalidate debug_entry[9].uop.prs1 \n invalidate debug_entry[9].uop.pdst \n invalidate debug_entry[9].uop.rxq_idx \n invalidate debug_entry[9].uop.stq_idx \n invalidate debug_entry[9].uop.ldq_idx \n invalidate debug_entry[9].uop.rob_idx \n invalidate debug_entry[9].uop.csr_addr \n invalidate debug_entry[9].uop.imm_packed \n invalidate debug_entry[9].uop.taken \n invalidate debug_entry[9].uop.pc_lob \n invalidate debug_entry[9].uop.edge_inst \n invalidate debug_entry[9].uop.ftq_idx \n invalidate debug_entry[9].uop.br_tag \n invalidate debug_entry[9].uop.br_mask \n invalidate debug_entry[9].uop.is_sfb \n invalidate debug_entry[9].uop.is_jal \n invalidate debug_entry[9].uop.is_jalr \n invalidate debug_entry[9].uop.is_br \n invalidate debug_entry[9].uop.iw_p2_poisoned \n invalidate debug_entry[9].uop.iw_p1_poisoned \n invalidate debug_entry[9].uop.iw_state \n invalidate debug_entry[9].uop.ctrl.is_std \n invalidate debug_entry[9].uop.ctrl.is_sta \n invalidate debug_entry[9].uop.ctrl.is_load \n invalidate debug_entry[9].uop.ctrl.csr_cmd \n invalidate debug_entry[9].uop.ctrl.fcn_dw \n invalidate debug_entry[9].uop.ctrl.op_fcn \n invalidate debug_entry[9].uop.ctrl.imm_sel \n invalidate debug_entry[9].uop.ctrl.op2_sel \n invalidate debug_entry[9].uop.ctrl.op1_sel \n invalidate debug_entry[9].uop.ctrl.br_type \n invalidate debug_entry[9].uop.fu_code \n invalidate debug_entry[9].uop.iq_type \n invalidate debug_entry[9].uop.debug_pc \n invalidate debug_entry[9].uop.is_rvc \n invalidate debug_entry[9].uop.debug_inst \n invalidate debug_entry[9].uop.inst \n invalidate debug_entry[9].uop.uopc \n invalidate debug_entry[9].unsafe \n invalidate debug_entry[9].busy \n invalidate debug_entry[9].valid \n invalidate debug_entry[10].exception \n invalidate debug_entry[10].uop.debug_tsrc \n invalidate debug_entry[10].uop.debug_fsrc \n invalidate debug_entry[10].uop.bp_xcpt_if \n invalidate debug_entry[10].uop.bp_debug_if \n invalidate debug_entry[10].uop.xcpt_ma_if \n invalidate debug_entry[10].uop.xcpt_ae_if \n invalidate debug_entry[10].uop.xcpt_pf_if \n invalidate debug_entry[10].uop.fp_single \n invalidate debug_entry[10].uop.fp_val \n invalidate debug_entry[10].uop.frs3_en \n invalidate debug_entry[10].uop.lrs2_rtype \n invalidate debug_entry[10].uop.lrs1_rtype \n invalidate debug_entry[10].uop.dst_rtype \n invalidate debug_entry[10].uop.ldst_val \n invalidate debug_entry[10].uop.lrs3 \n invalidate debug_entry[10].uop.lrs2 \n invalidate debug_entry[10].uop.lrs1 \n invalidate debug_entry[10].uop.ldst \n invalidate debug_entry[10].uop.ldst_is_rs1 \n invalidate debug_entry[10].uop.flush_on_commit \n invalidate debug_entry[10].uop.is_unique \n invalidate debug_entry[10].uop.is_sys_pc2epc \n invalidate debug_entry[10].uop.uses_stq \n invalidate debug_entry[10].uop.uses_ldq \n invalidate debug_entry[10].uop.is_amo \n invalidate debug_entry[10].uop.is_fencei \n invalidate debug_entry[10].uop.is_fence \n invalidate debug_entry[10].uop.mem_signed \n invalidate debug_entry[10].uop.mem_size \n invalidate debug_entry[10].uop.mem_cmd \n invalidate debug_entry[10].uop.bypassable \n invalidate debug_entry[10].uop.exc_cause \n invalidate debug_entry[10].uop.exception \n invalidate debug_entry[10].uop.stale_pdst \n invalidate debug_entry[10].uop.ppred_busy \n invalidate debug_entry[10].uop.prs3_busy \n invalidate debug_entry[10].uop.prs2_busy \n invalidate debug_entry[10].uop.prs1_busy \n invalidate debug_entry[10].uop.ppred \n invalidate debug_entry[10].uop.prs3 \n invalidate debug_entry[10].uop.prs2 \n invalidate debug_entry[10].uop.prs1 \n invalidate debug_entry[10].uop.pdst \n invalidate debug_entry[10].uop.rxq_idx \n invalidate debug_entry[10].uop.stq_idx \n invalidate debug_entry[10].uop.ldq_idx \n invalidate debug_entry[10].uop.rob_idx \n invalidate debug_entry[10].uop.csr_addr \n invalidate debug_entry[10].uop.imm_packed \n invalidate debug_entry[10].uop.taken \n invalidate debug_entry[10].uop.pc_lob \n invalidate debug_entry[10].uop.edge_inst \n invalidate debug_entry[10].uop.ftq_idx \n invalidate debug_entry[10].uop.br_tag \n invalidate debug_entry[10].uop.br_mask \n invalidate debug_entry[10].uop.is_sfb \n invalidate debug_entry[10].uop.is_jal \n invalidate debug_entry[10].uop.is_jalr \n invalidate debug_entry[10].uop.is_br \n invalidate debug_entry[10].uop.iw_p2_poisoned \n invalidate debug_entry[10].uop.iw_p1_poisoned \n invalidate debug_entry[10].uop.iw_state \n invalidate debug_entry[10].uop.ctrl.is_std \n invalidate debug_entry[10].uop.ctrl.is_sta \n invalidate debug_entry[10].uop.ctrl.is_load \n invalidate debug_entry[10].uop.ctrl.csr_cmd \n invalidate debug_entry[10].uop.ctrl.fcn_dw \n invalidate debug_entry[10].uop.ctrl.op_fcn \n invalidate debug_entry[10].uop.ctrl.imm_sel \n invalidate debug_entry[10].uop.ctrl.op2_sel \n invalidate debug_entry[10].uop.ctrl.op1_sel \n invalidate debug_entry[10].uop.ctrl.br_type \n invalidate debug_entry[10].uop.fu_code \n invalidate debug_entry[10].uop.iq_type \n invalidate debug_entry[10].uop.debug_pc \n invalidate debug_entry[10].uop.is_rvc \n invalidate debug_entry[10].uop.debug_inst \n invalidate debug_entry[10].uop.inst \n invalidate debug_entry[10].uop.uopc \n invalidate debug_entry[10].unsafe \n invalidate debug_entry[10].busy \n invalidate debug_entry[10].valid \n invalidate debug_entry[11].exception \n invalidate debug_entry[11].uop.debug_tsrc \n invalidate debug_entry[11].uop.debug_fsrc \n invalidate debug_entry[11].uop.bp_xcpt_if \n invalidate debug_entry[11].uop.bp_debug_if \n invalidate debug_entry[11].uop.xcpt_ma_if \n invalidate debug_entry[11].uop.xcpt_ae_if \n invalidate debug_entry[11].uop.xcpt_pf_if \n invalidate debug_entry[11].uop.fp_single \n invalidate debug_entry[11].uop.fp_val \n invalidate debug_entry[11].uop.frs3_en \n invalidate debug_entry[11].uop.lrs2_rtype \n invalidate debug_entry[11].uop.lrs1_rtype \n invalidate debug_entry[11].uop.dst_rtype \n invalidate debug_entry[11].uop.ldst_val \n invalidate debug_entry[11].uop.lrs3 \n invalidate debug_entry[11].uop.lrs2 \n invalidate debug_entry[11].uop.lrs1 \n invalidate debug_entry[11].uop.ldst \n invalidate debug_entry[11].uop.ldst_is_rs1 \n invalidate debug_entry[11].uop.flush_on_commit \n invalidate debug_entry[11].uop.is_unique \n invalidate debug_entry[11].uop.is_sys_pc2epc \n invalidate debug_entry[11].uop.uses_stq \n invalidate debug_entry[11].uop.uses_ldq \n invalidate debug_entry[11].uop.is_amo \n invalidate debug_entry[11].uop.is_fencei \n invalidate debug_entry[11].uop.is_fence \n invalidate debug_entry[11].uop.mem_signed \n invalidate debug_entry[11].uop.mem_size \n invalidate debug_entry[11].uop.mem_cmd \n invalidate debug_entry[11].uop.bypassable \n invalidate debug_entry[11].uop.exc_cause \n invalidate debug_entry[11].uop.exception \n invalidate debug_entry[11].uop.stale_pdst \n invalidate debug_entry[11].uop.ppred_busy \n invalidate debug_entry[11].uop.prs3_busy \n invalidate debug_entry[11].uop.prs2_busy \n invalidate debug_entry[11].uop.prs1_busy \n invalidate debug_entry[11].uop.ppred \n invalidate debug_entry[11].uop.prs3 \n invalidate debug_entry[11].uop.prs2 \n invalidate debug_entry[11].uop.prs1 \n invalidate debug_entry[11].uop.pdst \n invalidate debug_entry[11].uop.rxq_idx \n invalidate debug_entry[11].uop.stq_idx \n invalidate debug_entry[11].uop.ldq_idx \n invalidate debug_entry[11].uop.rob_idx \n invalidate debug_entry[11].uop.csr_addr \n invalidate debug_entry[11].uop.imm_packed \n invalidate debug_entry[11].uop.taken \n invalidate debug_entry[11].uop.pc_lob \n invalidate debug_entry[11].uop.edge_inst \n invalidate debug_entry[11].uop.ftq_idx \n invalidate debug_entry[11].uop.br_tag \n invalidate debug_entry[11].uop.br_mask \n invalidate debug_entry[11].uop.is_sfb \n invalidate debug_entry[11].uop.is_jal \n invalidate debug_entry[11].uop.is_jalr \n invalidate debug_entry[11].uop.is_br \n invalidate debug_entry[11].uop.iw_p2_poisoned \n invalidate debug_entry[11].uop.iw_p1_poisoned \n invalidate debug_entry[11].uop.iw_state \n invalidate debug_entry[11].uop.ctrl.is_std \n invalidate debug_entry[11].uop.ctrl.is_sta \n invalidate debug_entry[11].uop.ctrl.is_load \n invalidate debug_entry[11].uop.ctrl.csr_cmd \n invalidate debug_entry[11].uop.ctrl.fcn_dw \n invalidate debug_entry[11].uop.ctrl.op_fcn \n invalidate debug_entry[11].uop.ctrl.imm_sel \n invalidate debug_entry[11].uop.ctrl.op2_sel \n invalidate debug_entry[11].uop.ctrl.op1_sel \n invalidate debug_entry[11].uop.ctrl.br_type \n invalidate debug_entry[11].uop.fu_code \n invalidate debug_entry[11].uop.iq_type \n invalidate debug_entry[11].uop.debug_pc \n invalidate debug_entry[11].uop.is_rvc \n invalidate debug_entry[11].uop.debug_inst \n invalidate debug_entry[11].uop.inst \n invalidate debug_entry[11].uop.uopc \n invalidate debug_entry[11].unsafe \n invalidate debug_entry[11].busy \n invalidate debug_entry[11].valid \n invalidate debug_entry[12].exception \n invalidate debug_entry[12].uop.debug_tsrc \n invalidate debug_entry[12].uop.debug_fsrc \n invalidate debug_entry[12].uop.bp_xcpt_if \n invalidate debug_entry[12].uop.bp_debug_if \n invalidate debug_entry[12].uop.xcpt_ma_if \n invalidate debug_entry[12].uop.xcpt_ae_if \n invalidate debug_entry[12].uop.xcpt_pf_if \n invalidate debug_entry[12].uop.fp_single \n invalidate debug_entry[12].uop.fp_val \n invalidate debug_entry[12].uop.frs3_en \n invalidate debug_entry[12].uop.lrs2_rtype \n invalidate debug_entry[12].uop.lrs1_rtype \n invalidate debug_entry[12].uop.dst_rtype \n invalidate debug_entry[12].uop.ldst_val \n invalidate debug_entry[12].uop.lrs3 \n invalidate debug_entry[12].uop.lrs2 \n invalidate debug_entry[12].uop.lrs1 \n invalidate debug_entry[12].uop.ldst \n invalidate debug_entry[12].uop.ldst_is_rs1 \n invalidate debug_entry[12].uop.flush_on_commit \n invalidate debug_entry[12].uop.is_unique \n invalidate debug_entry[12].uop.is_sys_pc2epc \n invalidate debug_entry[12].uop.uses_stq \n invalidate debug_entry[12].uop.uses_ldq \n invalidate debug_entry[12].uop.is_amo \n invalidate debug_entry[12].uop.is_fencei \n invalidate debug_entry[12].uop.is_fence \n invalidate debug_entry[12].uop.mem_signed \n invalidate debug_entry[12].uop.mem_size \n invalidate debug_entry[12].uop.mem_cmd \n invalidate debug_entry[12].uop.bypassable \n invalidate debug_entry[12].uop.exc_cause \n invalidate debug_entry[12].uop.exception \n invalidate debug_entry[12].uop.stale_pdst \n invalidate debug_entry[12].uop.ppred_busy \n invalidate debug_entry[12].uop.prs3_busy \n invalidate debug_entry[12].uop.prs2_busy \n invalidate debug_entry[12].uop.prs1_busy \n invalidate debug_entry[12].uop.ppred \n invalidate debug_entry[12].uop.prs3 \n invalidate debug_entry[12].uop.prs2 \n invalidate debug_entry[12].uop.prs1 \n invalidate debug_entry[12].uop.pdst \n invalidate debug_entry[12].uop.rxq_idx \n invalidate debug_entry[12].uop.stq_idx \n invalidate debug_entry[12].uop.ldq_idx \n invalidate debug_entry[12].uop.rob_idx \n invalidate debug_entry[12].uop.csr_addr \n invalidate debug_entry[12].uop.imm_packed \n invalidate debug_entry[12].uop.taken \n invalidate debug_entry[12].uop.pc_lob \n invalidate debug_entry[12].uop.edge_inst \n invalidate debug_entry[12].uop.ftq_idx \n invalidate debug_entry[12].uop.br_tag \n invalidate debug_entry[12].uop.br_mask \n invalidate debug_entry[12].uop.is_sfb \n invalidate debug_entry[12].uop.is_jal \n invalidate debug_entry[12].uop.is_jalr \n invalidate debug_entry[12].uop.is_br \n invalidate debug_entry[12].uop.iw_p2_poisoned \n invalidate debug_entry[12].uop.iw_p1_poisoned \n invalidate debug_entry[12].uop.iw_state \n invalidate debug_entry[12].uop.ctrl.is_std \n invalidate debug_entry[12].uop.ctrl.is_sta \n invalidate debug_entry[12].uop.ctrl.is_load \n invalidate debug_entry[12].uop.ctrl.csr_cmd \n invalidate debug_entry[12].uop.ctrl.fcn_dw \n invalidate debug_entry[12].uop.ctrl.op_fcn \n invalidate debug_entry[12].uop.ctrl.imm_sel \n invalidate debug_entry[12].uop.ctrl.op2_sel \n invalidate debug_entry[12].uop.ctrl.op1_sel \n invalidate debug_entry[12].uop.ctrl.br_type \n invalidate debug_entry[12].uop.fu_code \n invalidate debug_entry[12].uop.iq_type \n invalidate debug_entry[12].uop.debug_pc \n invalidate debug_entry[12].uop.is_rvc \n invalidate debug_entry[12].uop.debug_inst \n invalidate debug_entry[12].uop.inst \n invalidate debug_entry[12].uop.uopc \n invalidate debug_entry[12].unsafe \n invalidate debug_entry[12].busy \n invalidate debug_entry[12].valid \n invalidate debug_entry[13].exception \n invalidate debug_entry[13].uop.debug_tsrc \n invalidate debug_entry[13].uop.debug_fsrc \n invalidate debug_entry[13].uop.bp_xcpt_if \n invalidate debug_entry[13].uop.bp_debug_if \n invalidate debug_entry[13].uop.xcpt_ma_if \n invalidate debug_entry[13].uop.xcpt_ae_if \n invalidate debug_entry[13].uop.xcpt_pf_if \n invalidate debug_entry[13].uop.fp_single \n invalidate debug_entry[13].uop.fp_val \n invalidate debug_entry[13].uop.frs3_en \n invalidate debug_entry[13].uop.lrs2_rtype \n invalidate debug_entry[13].uop.lrs1_rtype \n invalidate debug_entry[13].uop.dst_rtype \n invalidate debug_entry[13].uop.ldst_val \n invalidate debug_entry[13].uop.lrs3 \n invalidate debug_entry[13].uop.lrs2 \n invalidate debug_entry[13].uop.lrs1 \n invalidate debug_entry[13].uop.ldst \n invalidate debug_entry[13].uop.ldst_is_rs1 \n invalidate debug_entry[13].uop.flush_on_commit \n invalidate debug_entry[13].uop.is_unique \n invalidate debug_entry[13].uop.is_sys_pc2epc \n invalidate debug_entry[13].uop.uses_stq \n invalidate debug_entry[13].uop.uses_ldq \n invalidate debug_entry[13].uop.is_amo \n invalidate debug_entry[13].uop.is_fencei \n invalidate debug_entry[13].uop.is_fence \n invalidate debug_entry[13].uop.mem_signed \n invalidate debug_entry[13].uop.mem_size \n invalidate debug_entry[13].uop.mem_cmd \n invalidate debug_entry[13].uop.bypassable \n invalidate debug_entry[13].uop.exc_cause \n invalidate debug_entry[13].uop.exception \n invalidate debug_entry[13].uop.stale_pdst \n invalidate debug_entry[13].uop.ppred_busy \n invalidate debug_entry[13].uop.prs3_busy \n invalidate debug_entry[13].uop.prs2_busy \n invalidate debug_entry[13].uop.prs1_busy \n invalidate debug_entry[13].uop.ppred \n invalidate debug_entry[13].uop.prs3 \n invalidate debug_entry[13].uop.prs2 \n invalidate debug_entry[13].uop.prs1 \n invalidate debug_entry[13].uop.pdst \n invalidate debug_entry[13].uop.rxq_idx \n invalidate debug_entry[13].uop.stq_idx \n invalidate debug_entry[13].uop.ldq_idx \n invalidate debug_entry[13].uop.rob_idx \n invalidate debug_entry[13].uop.csr_addr \n invalidate debug_entry[13].uop.imm_packed \n invalidate debug_entry[13].uop.taken \n invalidate debug_entry[13].uop.pc_lob \n invalidate debug_entry[13].uop.edge_inst \n invalidate debug_entry[13].uop.ftq_idx \n invalidate debug_entry[13].uop.br_tag \n invalidate debug_entry[13].uop.br_mask \n invalidate debug_entry[13].uop.is_sfb \n invalidate debug_entry[13].uop.is_jal \n invalidate debug_entry[13].uop.is_jalr \n invalidate debug_entry[13].uop.is_br \n invalidate debug_entry[13].uop.iw_p2_poisoned \n invalidate debug_entry[13].uop.iw_p1_poisoned \n invalidate debug_entry[13].uop.iw_state \n invalidate debug_entry[13].uop.ctrl.is_std \n invalidate debug_entry[13].uop.ctrl.is_sta \n invalidate debug_entry[13].uop.ctrl.is_load \n invalidate debug_entry[13].uop.ctrl.csr_cmd \n invalidate debug_entry[13].uop.ctrl.fcn_dw \n invalidate debug_entry[13].uop.ctrl.op_fcn \n invalidate debug_entry[13].uop.ctrl.imm_sel \n invalidate debug_entry[13].uop.ctrl.op2_sel \n invalidate debug_entry[13].uop.ctrl.op1_sel \n invalidate debug_entry[13].uop.ctrl.br_type \n invalidate debug_entry[13].uop.fu_code \n invalidate debug_entry[13].uop.iq_type \n invalidate debug_entry[13].uop.debug_pc \n invalidate debug_entry[13].uop.is_rvc \n invalidate debug_entry[13].uop.debug_inst \n invalidate debug_entry[13].uop.inst \n invalidate debug_entry[13].uop.uopc \n invalidate debug_entry[13].unsafe \n invalidate debug_entry[13].busy \n invalidate debug_entry[13].valid \n invalidate debug_entry[14].exception \n invalidate debug_entry[14].uop.debug_tsrc \n invalidate debug_entry[14].uop.debug_fsrc \n invalidate debug_entry[14].uop.bp_xcpt_if \n invalidate debug_entry[14].uop.bp_debug_if \n invalidate debug_entry[14].uop.xcpt_ma_if \n invalidate debug_entry[14].uop.xcpt_ae_if \n invalidate debug_entry[14].uop.xcpt_pf_if \n invalidate debug_entry[14].uop.fp_single \n invalidate debug_entry[14].uop.fp_val \n invalidate debug_entry[14].uop.frs3_en \n invalidate debug_entry[14].uop.lrs2_rtype \n invalidate debug_entry[14].uop.lrs1_rtype \n invalidate debug_entry[14].uop.dst_rtype \n invalidate debug_entry[14].uop.ldst_val \n invalidate debug_entry[14].uop.lrs3 \n invalidate debug_entry[14].uop.lrs2 \n invalidate debug_entry[14].uop.lrs1 \n invalidate debug_entry[14].uop.ldst \n invalidate debug_entry[14].uop.ldst_is_rs1 \n invalidate debug_entry[14].uop.flush_on_commit \n invalidate debug_entry[14].uop.is_unique \n invalidate debug_entry[14].uop.is_sys_pc2epc \n invalidate debug_entry[14].uop.uses_stq \n invalidate debug_entry[14].uop.uses_ldq \n invalidate debug_entry[14].uop.is_amo \n invalidate debug_entry[14].uop.is_fencei \n invalidate debug_entry[14].uop.is_fence \n invalidate debug_entry[14].uop.mem_signed \n invalidate debug_entry[14].uop.mem_size \n invalidate debug_entry[14].uop.mem_cmd \n invalidate debug_entry[14].uop.bypassable \n invalidate debug_entry[14].uop.exc_cause \n invalidate debug_entry[14].uop.exception \n invalidate debug_entry[14].uop.stale_pdst \n invalidate debug_entry[14].uop.ppred_busy \n invalidate debug_entry[14].uop.prs3_busy \n invalidate debug_entry[14].uop.prs2_busy \n invalidate debug_entry[14].uop.prs1_busy \n invalidate debug_entry[14].uop.ppred \n invalidate debug_entry[14].uop.prs3 \n invalidate debug_entry[14].uop.prs2 \n invalidate debug_entry[14].uop.prs1 \n invalidate debug_entry[14].uop.pdst \n invalidate debug_entry[14].uop.rxq_idx \n invalidate debug_entry[14].uop.stq_idx \n invalidate debug_entry[14].uop.ldq_idx \n invalidate debug_entry[14].uop.rob_idx \n invalidate debug_entry[14].uop.csr_addr \n invalidate debug_entry[14].uop.imm_packed \n invalidate debug_entry[14].uop.taken \n invalidate debug_entry[14].uop.pc_lob \n invalidate debug_entry[14].uop.edge_inst \n invalidate debug_entry[14].uop.ftq_idx \n invalidate debug_entry[14].uop.br_tag \n invalidate debug_entry[14].uop.br_mask \n invalidate debug_entry[14].uop.is_sfb \n invalidate debug_entry[14].uop.is_jal \n invalidate debug_entry[14].uop.is_jalr \n invalidate debug_entry[14].uop.is_br \n invalidate debug_entry[14].uop.iw_p2_poisoned \n invalidate debug_entry[14].uop.iw_p1_poisoned \n invalidate debug_entry[14].uop.iw_state \n invalidate debug_entry[14].uop.ctrl.is_std \n invalidate debug_entry[14].uop.ctrl.is_sta \n invalidate debug_entry[14].uop.ctrl.is_load \n invalidate debug_entry[14].uop.ctrl.csr_cmd \n invalidate debug_entry[14].uop.ctrl.fcn_dw \n invalidate debug_entry[14].uop.ctrl.op_fcn \n invalidate debug_entry[14].uop.ctrl.imm_sel \n invalidate debug_entry[14].uop.ctrl.op2_sel \n invalidate debug_entry[14].uop.ctrl.op1_sel \n invalidate debug_entry[14].uop.ctrl.br_type \n invalidate debug_entry[14].uop.fu_code \n invalidate debug_entry[14].uop.iq_type \n invalidate debug_entry[14].uop.debug_pc \n invalidate debug_entry[14].uop.is_rvc \n invalidate debug_entry[14].uop.debug_inst \n invalidate debug_entry[14].uop.inst \n invalidate debug_entry[14].uop.uopc \n invalidate debug_entry[14].unsafe \n invalidate debug_entry[14].busy \n invalidate debug_entry[14].valid \n invalidate debug_entry[15].exception \n invalidate debug_entry[15].uop.debug_tsrc \n invalidate debug_entry[15].uop.debug_fsrc \n invalidate debug_entry[15].uop.bp_xcpt_if \n invalidate debug_entry[15].uop.bp_debug_if \n invalidate debug_entry[15].uop.xcpt_ma_if \n invalidate debug_entry[15].uop.xcpt_ae_if \n invalidate debug_entry[15].uop.xcpt_pf_if \n invalidate debug_entry[15].uop.fp_single \n invalidate debug_entry[15].uop.fp_val \n invalidate debug_entry[15].uop.frs3_en \n invalidate debug_entry[15].uop.lrs2_rtype \n invalidate debug_entry[15].uop.lrs1_rtype \n invalidate debug_entry[15].uop.dst_rtype \n invalidate debug_entry[15].uop.ldst_val \n invalidate debug_entry[15].uop.lrs3 \n invalidate debug_entry[15].uop.lrs2 \n invalidate debug_entry[15].uop.lrs1 \n invalidate debug_entry[15].uop.ldst \n invalidate debug_entry[15].uop.ldst_is_rs1 \n invalidate debug_entry[15].uop.flush_on_commit \n invalidate debug_entry[15].uop.is_unique \n invalidate debug_entry[15].uop.is_sys_pc2epc \n invalidate debug_entry[15].uop.uses_stq \n invalidate debug_entry[15].uop.uses_ldq \n invalidate debug_entry[15].uop.is_amo \n invalidate debug_entry[15].uop.is_fencei \n invalidate debug_entry[15].uop.is_fence \n invalidate debug_entry[15].uop.mem_signed \n invalidate debug_entry[15].uop.mem_size \n invalidate debug_entry[15].uop.mem_cmd \n invalidate debug_entry[15].uop.bypassable \n invalidate debug_entry[15].uop.exc_cause \n invalidate debug_entry[15].uop.exception \n invalidate debug_entry[15].uop.stale_pdst \n invalidate debug_entry[15].uop.ppred_busy \n invalidate debug_entry[15].uop.prs3_busy \n invalidate debug_entry[15].uop.prs2_busy \n invalidate debug_entry[15].uop.prs1_busy \n invalidate debug_entry[15].uop.ppred \n invalidate debug_entry[15].uop.prs3 \n invalidate debug_entry[15].uop.prs2 \n invalidate debug_entry[15].uop.prs1 \n invalidate debug_entry[15].uop.pdst \n invalidate debug_entry[15].uop.rxq_idx \n invalidate debug_entry[15].uop.stq_idx \n invalidate debug_entry[15].uop.ldq_idx \n invalidate debug_entry[15].uop.rob_idx \n invalidate debug_entry[15].uop.csr_addr \n invalidate debug_entry[15].uop.imm_packed \n invalidate debug_entry[15].uop.taken \n invalidate debug_entry[15].uop.pc_lob \n invalidate debug_entry[15].uop.edge_inst \n invalidate debug_entry[15].uop.ftq_idx \n invalidate debug_entry[15].uop.br_tag \n invalidate debug_entry[15].uop.br_mask \n invalidate debug_entry[15].uop.is_sfb \n invalidate debug_entry[15].uop.is_jal \n invalidate debug_entry[15].uop.is_jalr \n invalidate debug_entry[15].uop.is_br \n invalidate debug_entry[15].uop.iw_p2_poisoned \n invalidate debug_entry[15].uop.iw_p1_poisoned \n invalidate debug_entry[15].uop.iw_state \n invalidate debug_entry[15].uop.ctrl.is_std \n invalidate debug_entry[15].uop.ctrl.is_sta \n invalidate debug_entry[15].uop.ctrl.is_load \n invalidate debug_entry[15].uop.ctrl.csr_cmd \n invalidate debug_entry[15].uop.ctrl.fcn_dw \n invalidate debug_entry[15].uop.ctrl.op_fcn \n invalidate debug_entry[15].uop.ctrl.imm_sel \n invalidate debug_entry[15].uop.ctrl.op2_sel \n invalidate debug_entry[15].uop.ctrl.op1_sel \n invalidate debug_entry[15].uop.ctrl.br_type \n invalidate debug_entry[15].uop.fu_code \n invalidate debug_entry[15].uop.iq_type \n invalidate debug_entry[15].uop.debug_pc \n invalidate debug_entry[15].uop.is_rvc \n invalidate debug_entry[15].uop.debug_inst \n invalidate debug_entry[15].uop.inst \n invalidate debug_entry[15].uop.uopc \n invalidate debug_entry[15].unsafe \n invalidate debug_entry[15].busy \n invalidate debug_entry[15].valid \n invalidate debug_entry[16].exception \n invalidate debug_entry[16].uop.debug_tsrc \n invalidate debug_entry[16].uop.debug_fsrc \n invalidate debug_entry[16].uop.bp_xcpt_if \n invalidate debug_entry[16].uop.bp_debug_if \n invalidate debug_entry[16].uop.xcpt_ma_if \n invalidate debug_entry[16].uop.xcpt_ae_if \n invalidate debug_entry[16].uop.xcpt_pf_if \n invalidate debug_entry[16].uop.fp_single \n invalidate debug_entry[16].uop.fp_val \n invalidate debug_entry[16].uop.frs3_en \n invalidate debug_entry[16].uop.lrs2_rtype \n invalidate debug_entry[16].uop.lrs1_rtype \n invalidate debug_entry[16].uop.dst_rtype \n invalidate debug_entry[16].uop.ldst_val \n invalidate debug_entry[16].uop.lrs3 \n invalidate debug_entry[16].uop.lrs2 \n invalidate debug_entry[16].uop.lrs1 \n invalidate debug_entry[16].uop.ldst \n invalidate debug_entry[16].uop.ldst_is_rs1 \n invalidate debug_entry[16].uop.flush_on_commit \n invalidate debug_entry[16].uop.is_unique \n invalidate debug_entry[16].uop.is_sys_pc2epc \n invalidate debug_entry[16].uop.uses_stq \n invalidate debug_entry[16].uop.uses_ldq \n invalidate debug_entry[16].uop.is_amo \n invalidate debug_entry[16].uop.is_fencei \n invalidate debug_entry[16].uop.is_fence \n invalidate debug_entry[16].uop.mem_signed \n invalidate debug_entry[16].uop.mem_size \n invalidate debug_entry[16].uop.mem_cmd \n invalidate debug_entry[16].uop.bypassable \n invalidate debug_entry[16].uop.exc_cause \n invalidate debug_entry[16].uop.exception \n invalidate debug_entry[16].uop.stale_pdst \n invalidate debug_entry[16].uop.ppred_busy \n invalidate debug_entry[16].uop.prs3_busy \n invalidate debug_entry[16].uop.prs2_busy \n invalidate debug_entry[16].uop.prs1_busy \n invalidate debug_entry[16].uop.ppred \n invalidate debug_entry[16].uop.prs3 \n invalidate debug_entry[16].uop.prs2 \n invalidate debug_entry[16].uop.prs1 \n invalidate debug_entry[16].uop.pdst \n invalidate debug_entry[16].uop.rxq_idx \n invalidate debug_entry[16].uop.stq_idx \n invalidate debug_entry[16].uop.ldq_idx \n invalidate debug_entry[16].uop.rob_idx \n invalidate debug_entry[16].uop.csr_addr \n invalidate debug_entry[16].uop.imm_packed \n invalidate debug_entry[16].uop.taken \n invalidate debug_entry[16].uop.pc_lob \n invalidate debug_entry[16].uop.edge_inst \n invalidate debug_entry[16].uop.ftq_idx \n invalidate debug_entry[16].uop.br_tag \n invalidate debug_entry[16].uop.br_mask \n invalidate debug_entry[16].uop.is_sfb \n invalidate debug_entry[16].uop.is_jal \n invalidate debug_entry[16].uop.is_jalr \n invalidate debug_entry[16].uop.is_br \n invalidate debug_entry[16].uop.iw_p2_poisoned \n invalidate debug_entry[16].uop.iw_p1_poisoned \n invalidate debug_entry[16].uop.iw_state \n invalidate debug_entry[16].uop.ctrl.is_std \n invalidate debug_entry[16].uop.ctrl.is_sta \n invalidate debug_entry[16].uop.ctrl.is_load \n invalidate debug_entry[16].uop.ctrl.csr_cmd \n invalidate debug_entry[16].uop.ctrl.fcn_dw \n invalidate debug_entry[16].uop.ctrl.op_fcn \n invalidate debug_entry[16].uop.ctrl.imm_sel \n invalidate debug_entry[16].uop.ctrl.op2_sel \n invalidate debug_entry[16].uop.ctrl.op1_sel \n invalidate debug_entry[16].uop.ctrl.br_type \n invalidate debug_entry[16].uop.fu_code \n invalidate debug_entry[16].uop.iq_type \n invalidate debug_entry[16].uop.debug_pc \n invalidate debug_entry[16].uop.is_rvc \n invalidate debug_entry[16].uop.debug_inst \n invalidate debug_entry[16].uop.inst \n invalidate debug_entry[16].uop.uopc \n invalidate debug_entry[16].unsafe \n invalidate debug_entry[16].busy \n invalidate debug_entry[16].valid \n invalidate debug_entry[17].exception \n invalidate debug_entry[17].uop.debug_tsrc \n invalidate debug_entry[17].uop.debug_fsrc \n invalidate debug_entry[17].uop.bp_xcpt_if \n invalidate debug_entry[17].uop.bp_debug_if \n invalidate debug_entry[17].uop.xcpt_ma_if \n invalidate debug_entry[17].uop.xcpt_ae_if \n invalidate debug_entry[17].uop.xcpt_pf_if \n invalidate debug_entry[17].uop.fp_single \n invalidate debug_entry[17].uop.fp_val \n invalidate debug_entry[17].uop.frs3_en \n invalidate debug_entry[17].uop.lrs2_rtype \n invalidate debug_entry[17].uop.lrs1_rtype \n invalidate debug_entry[17].uop.dst_rtype \n invalidate debug_entry[17].uop.ldst_val \n invalidate debug_entry[17].uop.lrs3 \n invalidate debug_entry[17].uop.lrs2 \n invalidate debug_entry[17].uop.lrs1 \n invalidate debug_entry[17].uop.ldst \n invalidate debug_entry[17].uop.ldst_is_rs1 \n invalidate debug_entry[17].uop.flush_on_commit \n invalidate debug_entry[17].uop.is_unique \n invalidate debug_entry[17].uop.is_sys_pc2epc \n invalidate debug_entry[17].uop.uses_stq \n invalidate debug_entry[17].uop.uses_ldq \n invalidate debug_entry[17].uop.is_amo \n invalidate debug_entry[17].uop.is_fencei \n invalidate debug_entry[17].uop.is_fence \n invalidate debug_entry[17].uop.mem_signed \n invalidate debug_entry[17].uop.mem_size \n invalidate debug_entry[17].uop.mem_cmd \n invalidate debug_entry[17].uop.bypassable \n invalidate debug_entry[17].uop.exc_cause \n invalidate debug_entry[17].uop.exception \n invalidate debug_entry[17].uop.stale_pdst \n invalidate debug_entry[17].uop.ppred_busy \n invalidate debug_entry[17].uop.prs3_busy \n invalidate debug_entry[17].uop.prs2_busy \n invalidate debug_entry[17].uop.prs1_busy \n invalidate debug_entry[17].uop.ppred \n invalidate debug_entry[17].uop.prs3 \n invalidate debug_entry[17].uop.prs2 \n invalidate debug_entry[17].uop.prs1 \n invalidate debug_entry[17].uop.pdst \n invalidate debug_entry[17].uop.rxq_idx \n invalidate debug_entry[17].uop.stq_idx \n invalidate debug_entry[17].uop.ldq_idx \n invalidate debug_entry[17].uop.rob_idx \n invalidate debug_entry[17].uop.csr_addr \n invalidate debug_entry[17].uop.imm_packed \n invalidate debug_entry[17].uop.taken \n invalidate debug_entry[17].uop.pc_lob \n invalidate debug_entry[17].uop.edge_inst \n invalidate debug_entry[17].uop.ftq_idx \n invalidate debug_entry[17].uop.br_tag \n invalidate debug_entry[17].uop.br_mask \n invalidate debug_entry[17].uop.is_sfb \n invalidate debug_entry[17].uop.is_jal \n invalidate debug_entry[17].uop.is_jalr \n invalidate debug_entry[17].uop.is_br \n invalidate debug_entry[17].uop.iw_p2_poisoned \n invalidate debug_entry[17].uop.iw_p1_poisoned \n invalidate debug_entry[17].uop.iw_state \n invalidate debug_entry[17].uop.ctrl.is_std \n invalidate debug_entry[17].uop.ctrl.is_sta \n invalidate debug_entry[17].uop.ctrl.is_load \n invalidate debug_entry[17].uop.ctrl.csr_cmd \n invalidate debug_entry[17].uop.ctrl.fcn_dw \n invalidate debug_entry[17].uop.ctrl.op_fcn \n invalidate debug_entry[17].uop.ctrl.imm_sel \n invalidate debug_entry[17].uop.ctrl.op2_sel \n invalidate debug_entry[17].uop.ctrl.op1_sel \n invalidate debug_entry[17].uop.ctrl.br_type \n invalidate debug_entry[17].uop.fu_code \n invalidate debug_entry[17].uop.iq_type \n invalidate debug_entry[17].uop.debug_pc \n invalidate debug_entry[17].uop.is_rvc \n invalidate debug_entry[17].uop.debug_inst \n invalidate debug_entry[17].uop.inst \n invalidate debug_entry[17].uop.uopc \n invalidate debug_entry[17].unsafe \n invalidate debug_entry[17].busy \n invalidate debug_entry[17].valid \n invalidate debug_entry[18].exception \n invalidate debug_entry[18].uop.debug_tsrc \n invalidate debug_entry[18].uop.debug_fsrc \n invalidate debug_entry[18].uop.bp_xcpt_if \n invalidate debug_entry[18].uop.bp_debug_if \n invalidate debug_entry[18].uop.xcpt_ma_if \n invalidate debug_entry[18].uop.xcpt_ae_if \n invalidate debug_entry[18].uop.xcpt_pf_if \n invalidate debug_entry[18].uop.fp_single \n invalidate debug_entry[18].uop.fp_val \n invalidate debug_entry[18].uop.frs3_en \n invalidate debug_entry[18].uop.lrs2_rtype \n invalidate debug_entry[18].uop.lrs1_rtype \n invalidate debug_entry[18].uop.dst_rtype \n invalidate debug_entry[18].uop.ldst_val \n invalidate debug_entry[18].uop.lrs3 \n invalidate debug_entry[18].uop.lrs2 \n invalidate debug_entry[18].uop.lrs1 \n invalidate debug_entry[18].uop.ldst \n invalidate debug_entry[18].uop.ldst_is_rs1 \n invalidate debug_entry[18].uop.flush_on_commit \n invalidate debug_entry[18].uop.is_unique \n invalidate debug_entry[18].uop.is_sys_pc2epc \n invalidate debug_entry[18].uop.uses_stq \n invalidate debug_entry[18].uop.uses_ldq \n invalidate debug_entry[18].uop.is_amo \n invalidate debug_entry[18].uop.is_fencei \n invalidate debug_entry[18].uop.is_fence \n invalidate debug_entry[18].uop.mem_signed \n invalidate debug_entry[18].uop.mem_size \n invalidate debug_entry[18].uop.mem_cmd \n invalidate debug_entry[18].uop.bypassable \n invalidate debug_entry[18].uop.exc_cause \n invalidate debug_entry[18].uop.exception \n invalidate debug_entry[18].uop.stale_pdst \n invalidate debug_entry[18].uop.ppred_busy \n invalidate debug_entry[18].uop.prs3_busy \n invalidate debug_entry[18].uop.prs2_busy \n invalidate debug_entry[18].uop.prs1_busy \n invalidate debug_entry[18].uop.ppred \n invalidate debug_entry[18].uop.prs3 \n invalidate debug_entry[18].uop.prs2 \n invalidate debug_entry[18].uop.prs1 \n invalidate debug_entry[18].uop.pdst \n invalidate debug_entry[18].uop.rxq_idx \n invalidate debug_entry[18].uop.stq_idx \n invalidate debug_entry[18].uop.ldq_idx \n invalidate debug_entry[18].uop.rob_idx \n invalidate debug_entry[18].uop.csr_addr \n invalidate debug_entry[18].uop.imm_packed \n invalidate debug_entry[18].uop.taken \n invalidate debug_entry[18].uop.pc_lob \n invalidate debug_entry[18].uop.edge_inst \n invalidate debug_entry[18].uop.ftq_idx \n invalidate debug_entry[18].uop.br_tag \n invalidate debug_entry[18].uop.br_mask \n invalidate debug_entry[18].uop.is_sfb \n invalidate debug_entry[18].uop.is_jal \n invalidate debug_entry[18].uop.is_jalr \n invalidate debug_entry[18].uop.is_br \n invalidate debug_entry[18].uop.iw_p2_poisoned \n invalidate debug_entry[18].uop.iw_p1_poisoned \n invalidate debug_entry[18].uop.iw_state \n invalidate debug_entry[18].uop.ctrl.is_std \n invalidate debug_entry[18].uop.ctrl.is_sta \n invalidate debug_entry[18].uop.ctrl.is_load \n invalidate debug_entry[18].uop.ctrl.csr_cmd \n invalidate debug_entry[18].uop.ctrl.fcn_dw \n invalidate debug_entry[18].uop.ctrl.op_fcn \n invalidate debug_entry[18].uop.ctrl.imm_sel \n invalidate debug_entry[18].uop.ctrl.op2_sel \n invalidate debug_entry[18].uop.ctrl.op1_sel \n invalidate debug_entry[18].uop.ctrl.br_type \n invalidate debug_entry[18].uop.fu_code \n invalidate debug_entry[18].uop.iq_type \n invalidate debug_entry[18].uop.debug_pc \n invalidate debug_entry[18].uop.is_rvc \n invalidate debug_entry[18].uop.debug_inst \n invalidate debug_entry[18].uop.inst \n invalidate debug_entry[18].uop.uopc \n invalidate debug_entry[18].unsafe \n invalidate debug_entry[18].busy \n invalidate debug_entry[18].valid \n invalidate debug_entry[19].exception \n invalidate debug_entry[19].uop.debug_tsrc \n invalidate debug_entry[19].uop.debug_fsrc \n invalidate debug_entry[19].uop.bp_xcpt_if \n invalidate debug_entry[19].uop.bp_debug_if \n invalidate debug_entry[19].uop.xcpt_ma_if \n invalidate debug_entry[19].uop.xcpt_ae_if \n invalidate debug_entry[19].uop.xcpt_pf_if \n invalidate debug_entry[19].uop.fp_single \n invalidate debug_entry[19].uop.fp_val \n invalidate debug_entry[19].uop.frs3_en \n invalidate debug_entry[19].uop.lrs2_rtype \n invalidate debug_entry[19].uop.lrs1_rtype \n invalidate debug_entry[19].uop.dst_rtype \n invalidate debug_entry[19].uop.ldst_val \n invalidate debug_entry[19].uop.lrs3 \n invalidate debug_entry[19].uop.lrs2 \n invalidate debug_entry[19].uop.lrs1 \n invalidate debug_entry[19].uop.ldst \n invalidate debug_entry[19].uop.ldst_is_rs1 \n invalidate debug_entry[19].uop.flush_on_commit \n invalidate debug_entry[19].uop.is_unique \n invalidate debug_entry[19].uop.is_sys_pc2epc \n invalidate debug_entry[19].uop.uses_stq \n invalidate debug_entry[19].uop.uses_ldq \n invalidate debug_entry[19].uop.is_amo \n invalidate debug_entry[19].uop.is_fencei \n invalidate debug_entry[19].uop.is_fence \n invalidate debug_entry[19].uop.mem_signed \n invalidate debug_entry[19].uop.mem_size \n invalidate debug_entry[19].uop.mem_cmd \n invalidate debug_entry[19].uop.bypassable \n invalidate debug_entry[19].uop.exc_cause \n invalidate debug_entry[19].uop.exception \n invalidate debug_entry[19].uop.stale_pdst \n invalidate debug_entry[19].uop.ppred_busy \n invalidate debug_entry[19].uop.prs3_busy \n invalidate debug_entry[19].uop.prs2_busy \n invalidate debug_entry[19].uop.prs1_busy \n invalidate debug_entry[19].uop.ppred \n invalidate debug_entry[19].uop.prs3 \n invalidate debug_entry[19].uop.prs2 \n invalidate debug_entry[19].uop.prs1 \n invalidate debug_entry[19].uop.pdst \n invalidate debug_entry[19].uop.rxq_idx \n invalidate debug_entry[19].uop.stq_idx \n invalidate debug_entry[19].uop.ldq_idx \n invalidate debug_entry[19].uop.rob_idx \n invalidate debug_entry[19].uop.csr_addr \n invalidate debug_entry[19].uop.imm_packed \n invalidate debug_entry[19].uop.taken \n invalidate debug_entry[19].uop.pc_lob \n invalidate debug_entry[19].uop.edge_inst \n invalidate debug_entry[19].uop.ftq_idx \n invalidate debug_entry[19].uop.br_tag \n invalidate debug_entry[19].uop.br_mask \n invalidate debug_entry[19].uop.is_sfb \n invalidate debug_entry[19].uop.is_jal \n invalidate debug_entry[19].uop.is_jalr \n invalidate debug_entry[19].uop.is_br \n invalidate debug_entry[19].uop.iw_p2_poisoned \n invalidate debug_entry[19].uop.iw_p1_poisoned \n invalidate debug_entry[19].uop.iw_state \n invalidate debug_entry[19].uop.ctrl.is_std \n invalidate debug_entry[19].uop.ctrl.is_sta \n invalidate debug_entry[19].uop.ctrl.is_load \n invalidate debug_entry[19].uop.ctrl.csr_cmd \n invalidate debug_entry[19].uop.ctrl.fcn_dw \n invalidate debug_entry[19].uop.ctrl.op_fcn \n invalidate debug_entry[19].uop.ctrl.imm_sel \n invalidate debug_entry[19].uop.ctrl.op2_sel \n invalidate debug_entry[19].uop.ctrl.op1_sel \n invalidate debug_entry[19].uop.ctrl.br_type \n invalidate debug_entry[19].uop.fu_code \n invalidate debug_entry[19].uop.iq_type \n invalidate debug_entry[19].uop.debug_pc \n invalidate debug_entry[19].uop.is_rvc \n invalidate debug_entry[19].uop.debug_inst \n invalidate debug_entry[19].uop.inst \n invalidate debug_entry[19].uop.uopc \n invalidate debug_entry[19].unsafe \n invalidate debug_entry[19].busy \n invalidate debug_entry[19].valid \n invalidate debug_entry[20].exception \n invalidate debug_entry[20].uop.debug_tsrc \n invalidate debug_entry[20].uop.debug_fsrc \n invalidate debug_entry[20].uop.bp_xcpt_if \n invalidate debug_entry[20].uop.bp_debug_if \n invalidate debug_entry[20].uop.xcpt_ma_if \n invalidate debug_entry[20].uop.xcpt_ae_if \n invalidate debug_entry[20].uop.xcpt_pf_if \n invalidate debug_entry[20].uop.fp_single \n invalidate debug_entry[20].uop.fp_val \n invalidate debug_entry[20].uop.frs3_en \n invalidate debug_entry[20].uop.lrs2_rtype \n invalidate debug_entry[20].uop.lrs1_rtype \n invalidate debug_entry[20].uop.dst_rtype \n invalidate debug_entry[20].uop.ldst_val \n invalidate debug_entry[20].uop.lrs3 \n invalidate debug_entry[20].uop.lrs2 \n invalidate debug_entry[20].uop.lrs1 \n invalidate debug_entry[20].uop.ldst \n invalidate debug_entry[20].uop.ldst_is_rs1 \n invalidate debug_entry[20].uop.flush_on_commit \n invalidate debug_entry[20].uop.is_unique \n invalidate debug_entry[20].uop.is_sys_pc2epc \n invalidate debug_entry[20].uop.uses_stq \n invalidate debug_entry[20].uop.uses_ldq \n invalidate debug_entry[20].uop.is_amo \n invalidate debug_entry[20].uop.is_fencei \n invalidate debug_entry[20].uop.is_fence \n invalidate debug_entry[20].uop.mem_signed \n invalidate debug_entry[20].uop.mem_size \n invalidate debug_entry[20].uop.mem_cmd \n invalidate debug_entry[20].uop.bypassable \n invalidate debug_entry[20].uop.exc_cause \n invalidate debug_entry[20].uop.exception \n invalidate debug_entry[20].uop.stale_pdst \n invalidate debug_entry[20].uop.ppred_busy \n invalidate debug_entry[20].uop.prs3_busy \n invalidate debug_entry[20].uop.prs2_busy \n invalidate debug_entry[20].uop.prs1_busy \n invalidate debug_entry[20].uop.ppred \n invalidate debug_entry[20].uop.prs3 \n invalidate debug_entry[20].uop.prs2 \n invalidate debug_entry[20].uop.prs1 \n invalidate debug_entry[20].uop.pdst \n invalidate debug_entry[20].uop.rxq_idx \n invalidate debug_entry[20].uop.stq_idx \n invalidate debug_entry[20].uop.ldq_idx \n invalidate debug_entry[20].uop.rob_idx \n invalidate debug_entry[20].uop.csr_addr \n invalidate debug_entry[20].uop.imm_packed \n invalidate debug_entry[20].uop.taken \n invalidate debug_entry[20].uop.pc_lob \n invalidate debug_entry[20].uop.edge_inst \n invalidate debug_entry[20].uop.ftq_idx \n invalidate debug_entry[20].uop.br_tag \n invalidate debug_entry[20].uop.br_mask \n invalidate debug_entry[20].uop.is_sfb \n invalidate debug_entry[20].uop.is_jal \n invalidate debug_entry[20].uop.is_jalr \n invalidate debug_entry[20].uop.is_br \n invalidate debug_entry[20].uop.iw_p2_poisoned \n invalidate debug_entry[20].uop.iw_p1_poisoned \n invalidate debug_entry[20].uop.iw_state \n invalidate debug_entry[20].uop.ctrl.is_std \n invalidate debug_entry[20].uop.ctrl.is_sta \n invalidate debug_entry[20].uop.ctrl.is_load \n invalidate debug_entry[20].uop.ctrl.csr_cmd \n invalidate debug_entry[20].uop.ctrl.fcn_dw \n invalidate debug_entry[20].uop.ctrl.op_fcn \n invalidate debug_entry[20].uop.ctrl.imm_sel \n invalidate debug_entry[20].uop.ctrl.op2_sel \n invalidate debug_entry[20].uop.ctrl.op1_sel \n invalidate debug_entry[20].uop.ctrl.br_type \n invalidate debug_entry[20].uop.fu_code \n invalidate debug_entry[20].uop.iq_type \n invalidate debug_entry[20].uop.debug_pc \n invalidate debug_entry[20].uop.is_rvc \n invalidate debug_entry[20].uop.debug_inst \n invalidate debug_entry[20].uop.inst \n invalidate debug_entry[20].uop.uopc \n invalidate debug_entry[20].unsafe \n invalidate debug_entry[20].busy \n invalidate debug_entry[20].valid \n invalidate debug_entry[21].exception \n invalidate debug_entry[21].uop.debug_tsrc \n invalidate debug_entry[21].uop.debug_fsrc \n invalidate debug_entry[21].uop.bp_xcpt_if \n invalidate debug_entry[21].uop.bp_debug_if \n invalidate debug_entry[21].uop.xcpt_ma_if \n invalidate debug_entry[21].uop.xcpt_ae_if \n invalidate debug_entry[21].uop.xcpt_pf_if \n invalidate debug_entry[21].uop.fp_single \n invalidate debug_entry[21].uop.fp_val \n invalidate debug_entry[21].uop.frs3_en \n invalidate debug_entry[21].uop.lrs2_rtype \n invalidate debug_entry[21].uop.lrs1_rtype \n invalidate debug_entry[21].uop.dst_rtype \n invalidate debug_entry[21].uop.ldst_val \n invalidate debug_entry[21].uop.lrs3 \n invalidate debug_entry[21].uop.lrs2 \n invalidate debug_entry[21].uop.lrs1 \n invalidate debug_entry[21].uop.ldst \n invalidate debug_entry[21].uop.ldst_is_rs1 \n invalidate debug_entry[21].uop.flush_on_commit \n invalidate debug_entry[21].uop.is_unique \n invalidate debug_entry[21].uop.is_sys_pc2epc \n invalidate debug_entry[21].uop.uses_stq \n invalidate debug_entry[21].uop.uses_ldq \n invalidate debug_entry[21].uop.is_amo \n invalidate debug_entry[21].uop.is_fencei \n invalidate debug_entry[21].uop.is_fence \n invalidate debug_entry[21].uop.mem_signed \n invalidate debug_entry[21].uop.mem_size \n invalidate debug_entry[21].uop.mem_cmd \n invalidate debug_entry[21].uop.bypassable \n invalidate debug_entry[21].uop.exc_cause \n invalidate debug_entry[21].uop.exception \n invalidate debug_entry[21].uop.stale_pdst \n invalidate debug_entry[21].uop.ppred_busy \n invalidate debug_entry[21].uop.prs3_busy \n invalidate debug_entry[21].uop.prs2_busy \n invalidate debug_entry[21].uop.prs1_busy \n invalidate debug_entry[21].uop.ppred \n invalidate debug_entry[21].uop.prs3 \n invalidate debug_entry[21].uop.prs2 \n invalidate debug_entry[21].uop.prs1 \n invalidate debug_entry[21].uop.pdst \n invalidate debug_entry[21].uop.rxq_idx \n invalidate debug_entry[21].uop.stq_idx \n invalidate debug_entry[21].uop.ldq_idx \n invalidate debug_entry[21].uop.rob_idx \n invalidate debug_entry[21].uop.csr_addr \n invalidate debug_entry[21].uop.imm_packed \n invalidate debug_entry[21].uop.taken \n invalidate debug_entry[21].uop.pc_lob \n invalidate debug_entry[21].uop.edge_inst \n invalidate debug_entry[21].uop.ftq_idx \n invalidate debug_entry[21].uop.br_tag \n invalidate debug_entry[21].uop.br_mask \n invalidate debug_entry[21].uop.is_sfb \n invalidate debug_entry[21].uop.is_jal \n invalidate debug_entry[21].uop.is_jalr \n invalidate debug_entry[21].uop.is_br \n invalidate debug_entry[21].uop.iw_p2_poisoned \n invalidate debug_entry[21].uop.iw_p1_poisoned \n invalidate debug_entry[21].uop.iw_state \n invalidate debug_entry[21].uop.ctrl.is_std \n invalidate debug_entry[21].uop.ctrl.is_sta \n invalidate debug_entry[21].uop.ctrl.is_load \n invalidate debug_entry[21].uop.ctrl.csr_cmd \n invalidate debug_entry[21].uop.ctrl.fcn_dw \n invalidate debug_entry[21].uop.ctrl.op_fcn \n invalidate debug_entry[21].uop.ctrl.imm_sel \n invalidate debug_entry[21].uop.ctrl.op2_sel \n invalidate debug_entry[21].uop.ctrl.op1_sel \n invalidate debug_entry[21].uop.ctrl.br_type \n invalidate debug_entry[21].uop.fu_code \n invalidate debug_entry[21].uop.iq_type \n invalidate debug_entry[21].uop.debug_pc \n invalidate debug_entry[21].uop.is_rvc \n invalidate debug_entry[21].uop.debug_inst \n invalidate debug_entry[21].uop.inst \n invalidate debug_entry[21].uop.uopc \n invalidate debug_entry[21].unsafe \n invalidate debug_entry[21].busy \n invalidate debug_entry[21].valid \n invalidate debug_entry[22].exception \n invalidate debug_entry[22].uop.debug_tsrc \n invalidate debug_entry[22].uop.debug_fsrc \n invalidate debug_entry[22].uop.bp_xcpt_if \n invalidate debug_entry[22].uop.bp_debug_if \n invalidate debug_entry[22].uop.xcpt_ma_if \n invalidate debug_entry[22].uop.xcpt_ae_if \n invalidate debug_entry[22].uop.xcpt_pf_if \n invalidate debug_entry[22].uop.fp_single \n invalidate debug_entry[22].uop.fp_val \n invalidate debug_entry[22].uop.frs3_en \n invalidate debug_entry[22].uop.lrs2_rtype \n invalidate debug_entry[22].uop.lrs1_rtype \n invalidate debug_entry[22].uop.dst_rtype \n invalidate debug_entry[22].uop.ldst_val \n invalidate debug_entry[22].uop.lrs3 \n invalidate debug_entry[22].uop.lrs2 \n invalidate debug_entry[22].uop.lrs1 \n invalidate debug_entry[22].uop.ldst \n invalidate debug_entry[22].uop.ldst_is_rs1 \n invalidate debug_entry[22].uop.flush_on_commit \n invalidate debug_entry[22].uop.is_unique \n invalidate debug_entry[22].uop.is_sys_pc2epc \n invalidate debug_entry[22].uop.uses_stq \n invalidate debug_entry[22].uop.uses_ldq \n invalidate debug_entry[22].uop.is_amo \n invalidate debug_entry[22].uop.is_fencei \n invalidate debug_entry[22].uop.is_fence \n invalidate debug_entry[22].uop.mem_signed \n invalidate debug_entry[22].uop.mem_size \n invalidate debug_entry[22].uop.mem_cmd \n invalidate debug_entry[22].uop.bypassable \n invalidate debug_entry[22].uop.exc_cause \n invalidate debug_entry[22].uop.exception \n invalidate debug_entry[22].uop.stale_pdst \n invalidate debug_entry[22].uop.ppred_busy \n invalidate debug_entry[22].uop.prs3_busy \n invalidate debug_entry[22].uop.prs2_busy \n invalidate debug_entry[22].uop.prs1_busy \n invalidate debug_entry[22].uop.ppred \n invalidate debug_entry[22].uop.prs3 \n invalidate debug_entry[22].uop.prs2 \n invalidate debug_entry[22].uop.prs1 \n invalidate debug_entry[22].uop.pdst \n invalidate debug_entry[22].uop.rxq_idx \n invalidate debug_entry[22].uop.stq_idx \n invalidate debug_entry[22].uop.ldq_idx \n invalidate debug_entry[22].uop.rob_idx \n invalidate debug_entry[22].uop.csr_addr \n invalidate debug_entry[22].uop.imm_packed \n invalidate debug_entry[22].uop.taken \n invalidate debug_entry[22].uop.pc_lob \n invalidate debug_entry[22].uop.edge_inst \n invalidate debug_entry[22].uop.ftq_idx \n invalidate debug_entry[22].uop.br_tag \n invalidate debug_entry[22].uop.br_mask \n invalidate debug_entry[22].uop.is_sfb \n invalidate debug_entry[22].uop.is_jal \n invalidate debug_entry[22].uop.is_jalr \n invalidate debug_entry[22].uop.is_br \n invalidate debug_entry[22].uop.iw_p2_poisoned \n invalidate debug_entry[22].uop.iw_p1_poisoned \n invalidate debug_entry[22].uop.iw_state \n invalidate debug_entry[22].uop.ctrl.is_std \n invalidate debug_entry[22].uop.ctrl.is_sta \n invalidate debug_entry[22].uop.ctrl.is_load \n invalidate debug_entry[22].uop.ctrl.csr_cmd \n invalidate debug_entry[22].uop.ctrl.fcn_dw \n invalidate debug_entry[22].uop.ctrl.op_fcn \n invalidate debug_entry[22].uop.ctrl.imm_sel \n invalidate debug_entry[22].uop.ctrl.op2_sel \n invalidate debug_entry[22].uop.ctrl.op1_sel \n invalidate debug_entry[22].uop.ctrl.br_type \n invalidate debug_entry[22].uop.fu_code \n invalidate debug_entry[22].uop.iq_type \n invalidate debug_entry[22].uop.debug_pc \n invalidate debug_entry[22].uop.is_rvc \n invalidate debug_entry[22].uop.debug_inst \n invalidate debug_entry[22].uop.inst \n invalidate debug_entry[22].uop.uopc \n invalidate debug_entry[22].unsafe \n invalidate debug_entry[22].busy \n invalidate debug_entry[22].valid \n invalidate debug_entry[23].exception \n invalidate debug_entry[23].uop.debug_tsrc \n invalidate debug_entry[23].uop.debug_fsrc \n invalidate debug_entry[23].uop.bp_xcpt_if \n invalidate debug_entry[23].uop.bp_debug_if \n invalidate debug_entry[23].uop.xcpt_ma_if \n invalidate debug_entry[23].uop.xcpt_ae_if \n invalidate debug_entry[23].uop.xcpt_pf_if \n invalidate debug_entry[23].uop.fp_single \n invalidate debug_entry[23].uop.fp_val \n invalidate debug_entry[23].uop.frs3_en \n invalidate debug_entry[23].uop.lrs2_rtype \n invalidate debug_entry[23].uop.lrs1_rtype \n invalidate debug_entry[23].uop.dst_rtype \n invalidate debug_entry[23].uop.ldst_val \n invalidate debug_entry[23].uop.lrs3 \n invalidate debug_entry[23].uop.lrs2 \n invalidate debug_entry[23].uop.lrs1 \n invalidate debug_entry[23].uop.ldst \n invalidate debug_entry[23].uop.ldst_is_rs1 \n invalidate debug_entry[23].uop.flush_on_commit \n invalidate debug_entry[23].uop.is_unique \n invalidate debug_entry[23].uop.is_sys_pc2epc \n invalidate debug_entry[23].uop.uses_stq \n invalidate debug_entry[23].uop.uses_ldq \n invalidate debug_entry[23].uop.is_amo \n invalidate debug_entry[23].uop.is_fencei \n invalidate debug_entry[23].uop.is_fence \n invalidate debug_entry[23].uop.mem_signed \n invalidate debug_entry[23].uop.mem_size \n invalidate debug_entry[23].uop.mem_cmd \n invalidate debug_entry[23].uop.bypassable \n invalidate debug_entry[23].uop.exc_cause \n invalidate debug_entry[23].uop.exception \n invalidate debug_entry[23].uop.stale_pdst \n invalidate debug_entry[23].uop.ppred_busy \n invalidate debug_entry[23].uop.prs3_busy \n invalidate debug_entry[23].uop.prs2_busy \n invalidate debug_entry[23].uop.prs1_busy \n invalidate debug_entry[23].uop.ppred \n invalidate debug_entry[23].uop.prs3 \n invalidate debug_entry[23].uop.prs2 \n invalidate debug_entry[23].uop.prs1 \n invalidate debug_entry[23].uop.pdst \n invalidate debug_entry[23].uop.rxq_idx \n invalidate debug_entry[23].uop.stq_idx \n invalidate debug_entry[23].uop.ldq_idx \n invalidate debug_entry[23].uop.rob_idx \n invalidate debug_entry[23].uop.csr_addr \n invalidate debug_entry[23].uop.imm_packed \n invalidate debug_entry[23].uop.taken \n invalidate debug_entry[23].uop.pc_lob \n invalidate debug_entry[23].uop.edge_inst \n invalidate debug_entry[23].uop.ftq_idx \n invalidate debug_entry[23].uop.br_tag \n invalidate debug_entry[23].uop.br_mask \n invalidate debug_entry[23].uop.is_sfb \n invalidate debug_entry[23].uop.is_jal \n invalidate debug_entry[23].uop.is_jalr \n invalidate debug_entry[23].uop.is_br \n invalidate debug_entry[23].uop.iw_p2_poisoned \n invalidate debug_entry[23].uop.iw_p1_poisoned \n invalidate debug_entry[23].uop.iw_state \n invalidate debug_entry[23].uop.ctrl.is_std \n invalidate debug_entry[23].uop.ctrl.is_sta \n invalidate debug_entry[23].uop.ctrl.is_load \n invalidate debug_entry[23].uop.ctrl.csr_cmd \n invalidate debug_entry[23].uop.ctrl.fcn_dw \n invalidate debug_entry[23].uop.ctrl.op_fcn \n invalidate debug_entry[23].uop.ctrl.imm_sel \n invalidate debug_entry[23].uop.ctrl.op2_sel \n invalidate debug_entry[23].uop.ctrl.op1_sel \n invalidate debug_entry[23].uop.ctrl.br_type \n invalidate debug_entry[23].uop.fu_code \n invalidate debug_entry[23].uop.iq_type \n invalidate debug_entry[23].uop.debug_pc \n invalidate debug_entry[23].uop.is_rvc \n invalidate debug_entry[23].uop.debug_inst \n invalidate debug_entry[23].uop.inst \n invalidate debug_entry[23].uop.uopc \n invalidate debug_entry[23].unsafe \n invalidate debug_entry[23].busy \n invalidate debug_entry[23].valid \n invalidate debug_entry[24].exception \n invalidate debug_entry[24].uop.debug_tsrc \n invalidate debug_entry[24].uop.debug_fsrc \n invalidate debug_entry[24].uop.bp_xcpt_if \n invalidate debug_entry[24].uop.bp_debug_if \n invalidate debug_entry[24].uop.xcpt_ma_if \n invalidate debug_entry[24].uop.xcpt_ae_if \n invalidate debug_entry[24].uop.xcpt_pf_if \n invalidate debug_entry[24].uop.fp_single \n invalidate debug_entry[24].uop.fp_val \n invalidate debug_entry[24].uop.frs3_en \n invalidate debug_entry[24].uop.lrs2_rtype \n invalidate debug_entry[24].uop.lrs1_rtype \n invalidate debug_entry[24].uop.dst_rtype \n invalidate debug_entry[24].uop.ldst_val \n invalidate debug_entry[24].uop.lrs3 \n invalidate debug_entry[24].uop.lrs2 \n invalidate debug_entry[24].uop.lrs1 \n invalidate debug_entry[24].uop.ldst \n invalidate debug_entry[24].uop.ldst_is_rs1 \n invalidate debug_entry[24].uop.flush_on_commit \n invalidate debug_entry[24].uop.is_unique \n invalidate debug_entry[24].uop.is_sys_pc2epc \n invalidate debug_entry[24].uop.uses_stq \n invalidate debug_entry[24].uop.uses_ldq \n invalidate debug_entry[24].uop.is_amo \n invalidate debug_entry[24].uop.is_fencei \n invalidate debug_entry[24].uop.is_fence \n invalidate debug_entry[24].uop.mem_signed \n invalidate debug_entry[24].uop.mem_size \n invalidate debug_entry[24].uop.mem_cmd \n invalidate debug_entry[24].uop.bypassable \n invalidate debug_entry[24].uop.exc_cause \n invalidate debug_entry[24].uop.exception \n invalidate debug_entry[24].uop.stale_pdst \n invalidate debug_entry[24].uop.ppred_busy \n invalidate debug_entry[24].uop.prs3_busy \n invalidate debug_entry[24].uop.prs2_busy \n invalidate debug_entry[24].uop.prs1_busy \n invalidate debug_entry[24].uop.ppred \n invalidate debug_entry[24].uop.prs3 \n invalidate debug_entry[24].uop.prs2 \n invalidate debug_entry[24].uop.prs1 \n invalidate debug_entry[24].uop.pdst \n invalidate debug_entry[24].uop.rxq_idx \n invalidate debug_entry[24].uop.stq_idx \n invalidate debug_entry[24].uop.ldq_idx \n invalidate debug_entry[24].uop.rob_idx \n invalidate debug_entry[24].uop.csr_addr \n invalidate debug_entry[24].uop.imm_packed \n invalidate debug_entry[24].uop.taken \n invalidate debug_entry[24].uop.pc_lob \n invalidate debug_entry[24].uop.edge_inst \n invalidate debug_entry[24].uop.ftq_idx \n invalidate debug_entry[24].uop.br_tag \n invalidate debug_entry[24].uop.br_mask \n invalidate debug_entry[24].uop.is_sfb \n invalidate debug_entry[24].uop.is_jal \n invalidate debug_entry[24].uop.is_jalr \n invalidate debug_entry[24].uop.is_br \n invalidate debug_entry[24].uop.iw_p2_poisoned \n invalidate debug_entry[24].uop.iw_p1_poisoned \n invalidate debug_entry[24].uop.iw_state \n invalidate debug_entry[24].uop.ctrl.is_std \n invalidate debug_entry[24].uop.ctrl.is_sta \n invalidate debug_entry[24].uop.ctrl.is_load \n invalidate debug_entry[24].uop.ctrl.csr_cmd \n invalidate debug_entry[24].uop.ctrl.fcn_dw \n invalidate debug_entry[24].uop.ctrl.op_fcn \n invalidate debug_entry[24].uop.ctrl.imm_sel \n invalidate debug_entry[24].uop.ctrl.op2_sel \n invalidate debug_entry[24].uop.ctrl.op1_sel \n invalidate debug_entry[24].uop.ctrl.br_type \n invalidate debug_entry[24].uop.fu_code \n invalidate debug_entry[24].uop.iq_type \n invalidate debug_entry[24].uop.debug_pc \n invalidate debug_entry[24].uop.is_rvc \n invalidate debug_entry[24].uop.debug_inst \n invalidate debug_entry[24].uop.inst \n invalidate debug_entry[24].uop.uopc \n invalidate debug_entry[24].unsafe \n invalidate debug_entry[24].busy \n invalidate debug_entry[24].valid \n invalidate debug_entry[25].exception \n invalidate debug_entry[25].uop.debug_tsrc \n invalidate debug_entry[25].uop.debug_fsrc \n invalidate debug_entry[25].uop.bp_xcpt_if \n invalidate debug_entry[25].uop.bp_debug_if \n invalidate debug_entry[25].uop.xcpt_ma_if \n invalidate debug_entry[25].uop.xcpt_ae_if \n invalidate debug_entry[25].uop.xcpt_pf_if \n invalidate debug_entry[25].uop.fp_single \n invalidate debug_entry[25].uop.fp_val \n invalidate debug_entry[25].uop.frs3_en \n invalidate debug_entry[25].uop.lrs2_rtype \n invalidate debug_entry[25].uop.lrs1_rtype \n invalidate debug_entry[25].uop.dst_rtype \n invalidate debug_entry[25].uop.ldst_val \n invalidate debug_entry[25].uop.lrs3 \n invalidate debug_entry[25].uop.lrs2 \n invalidate debug_entry[25].uop.lrs1 \n invalidate debug_entry[25].uop.ldst \n invalidate debug_entry[25].uop.ldst_is_rs1 \n invalidate debug_entry[25].uop.flush_on_commit \n invalidate debug_entry[25].uop.is_unique \n invalidate debug_entry[25].uop.is_sys_pc2epc \n invalidate debug_entry[25].uop.uses_stq \n invalidate debug_entry[25].uop.uses_ldq \n invalidate debug_entry[25].uop.is_amo \n invalidate debug_entry[25].uop.is_fencei \n invalidate debug_entry[25].uop.is_fence \n invalidate debug_entry[25].uop.mem_signed \n invalidate debug_entry[25].uop.mem_size \n invalidate debug_entry[25].uop.mem_cmd \n invalidate debug_entry[25].uop.bypassable \n invalidate debug_entry[25].uop.exc_cause \n invalidate debug_entry[25].uop.exception \n invalidate debug_entry[25].uop.stale_pdst \n invalidate debug_entry[25].uop.ppred_busy \n invalidate debug_entry[25].uop.prs3_busy \n invalidate debug_entry[25].uop.prs2_busy \n invalidate debug_entry[25].uop.prs1_busy \n invalidate debug_entry[25].uop.ppred \n invalidate debug_entry[25].uop.prs3 \n invalidate debug_entry[25].uop.prs2 \n invalidate debug_entry[25].uop.prs1 \n invalidate debug_entry[25].uop.pdst \n invalidate debug_entry[25].uop.rxq_idx \n invalidate debug_entry[25].uop.stq_idx \n invalidate debug_entry[25].uop.ldq_idx \n invalidate debug_entry[25].uop.rob_idx \n invalidate debug_entry[25].uop.csr_addr \n invalidate debug_entry[25].uop.imm_packed \n invalidate debug_entry[25].uop.taken \n invalidate debug_entry[25].uop.pc_lob \n invalidate debug_entry[25].uop.edge_inst \n invalidate debug_entry[25].uop.ftq_idx \n invalidate debug_entry[25].uop.br_tag \n invalidate debug_entry[25].uop.br_mask \n invalidate debug_entry[25].uop.is_sfb \n invalidate debug_entry[25].uop.is_jal \n invalidate debug_entry[25].uop.is_jalr \n invalidate debug_entry[25].uop.is_br \n invalidate debug_entry[25].uop.iw_p2_poisoned \n invalidate debug_entry[25].uop.iw_p1_poisoned \n invalidate debug_entry[25].uop.iw_state \n invalidate debug_entry[25].uop.ctrl.is_std \n invalidate debug_entry[25].uop.ctrl.is_sta \n invalidate debug_entry[25].uop.ctrl.is_load \n invalidate debug_entry[25].uop.ctrl.csr_cmd \n invalidate debug_entry[25].uop.ctrl.fcn_dw \n invalidate debug_entry[25].uop.ctrl.op_fcn \n invalidate debug_entry[25].uop.ctrl.imm_sel \n invalidate debug_entry[25].uop.ctrl.op2_sel \n invalidate debug_entry[25].uop.ctrl.op1_sel \n invalidate debug_entry[25].uop.ctrl.br_type \n invalidate debug_entry[25].uop.fu_code \n invalidate debug_entry[25].uop.iq_type \n invalidate debug_entry[25].uop.debug_pc \n invalidate debug_entry[25].uop.is_rvc \n invalidate debug_entry[25].uop.debug_inst \n invalidate debug_entry[25].uop.inst \n invalidate debug_entry[25].uop.uopc \n invalidate debug_entry[25].unsafe \n invalidate debug_entry[25].busy \n invalidate debug_entry[25].valid \n invalidate debug_entry[26].exception \n invalidate debug_entry[26].uop.debug_tsrc \n invalidate debug_entry[26].uop.debug_fsrc \n invalidate debug_entry[26].uop.bp_xcpt_if \n invalidate debug_entry[26].uop.bp_debug_if \n invalidate debug_entry[26].uop.xcpt_ma_if \n invalidate debug_entry[26].uop.xcpt_ae_if \n invalidate debug_entry[26].uop.xcpt_pf_if \n invalidate debug_entry[26].uop.fp_single \n invalidate debug_entry[26].uop.fp_val \n invalidate debug_entry[26].uop.frs3_en \n invalidate debug_entry[26].uop.lrs2_rtype \n invalidate debug_entry[26].uop.lrs1_rtype \n invalidate debug_entry[26].uop.dst_rtype \n invalidate debug_entry[26].uop.ldst_val \n invalidate debug_entry[26].uop.lrs3 \n invalidate debug_entry[26].uop.lrs2 \n invalidate debug_entry[26].uop.lrs1 \n invalidate debug_entry[26].uop.ldst \n invalidate debug_entry[26].uop.ldst_is_rs1 \n invalidate debug_entry[26].uop.flush_on_commit \n invalidate debug_entry[26].uop.is_unique \n invalidate debug_entry[26].uop.is_sys_pc2epc \n invalidate debug_entry[26].uop.uses_stq \n invalidate debug_entry[26].uop.uses_ldq \n invalidate debug_entry[26].uop.is_amo \n invalidate debug_entry[26].uop.is_fencei \n invalidate debug_entry[26].uop.is_fence \n invalidate debug_entry[26].uop.mem_signed \n invalidate debug_entry[26].uop.mem_size \n invalidate debug_entry[26].uop.mem_cmd \n invalidate debug_entry[26].uop.bypassable \n invalidate debug_entry[26].uop.exc_cause \n invalidate debug_entry[26].uop.exception \n invalidate debug_entry[26].uop.stale_pdst \n invalidate debug_entry[26].uop.ppred_busy \n invalidate debug_entry[26].uop.prs3_busy \n invalidate debug_entry[26].uop.prs2_busy \n invalidate debug_entry[26].uop.prs1_busy \n invalidate debug_entry[26].uop.ppred \n invalidate debug_entry[26].uop.prs3 \n invalidate debug_entry[26].uop.prs2 \n invalidate debug_entry[26].uop.prs1 \n invalidate debug_entry[26].uop.pdst \n invalidate debug_entry[26].uop.rxq_idx \n invalidate debug_entry[26].uop.stq_idx \n invalidate debug_entry[26].uop.ldq_idx \n invalidate debug_entry[26].uop.rob_idx \n invalidate debug_entry[26].uop.csr_addr \n invalidate debug_entry[26].uop.imm_packed \n invalidate debug_entry[26].uop.taken \n invalidate debug_entry[26].uop.pc_lob \n invalidate debug_entry[26].uop.edge_inst \n invalidate debug_entry[26].uop.ftq_idx \n invalidate debug_entry[26].uop.br_tag \n invalidate debug_entry[26].uop.br_mask \n invalidate debug_entry[26].uop.is_sfb \n invalidate debug_entry[26].uop.is_jal \n invalidate debug_entry[26].uop.is_jalr \n invalidate debug_entry[26].uop.is_br \n invalidate debug_entry[26].uop.iw_p2_poisoned \n invalidate debug_entry[26].uop.iw_p1_poisoned \n invalidate debug_entry[26].uop.iw_state \n invalidate debug_entry[26].uop.ctrl.is_std \n invalidate debug_entry[26].uop.ctrl.is_sta \n invalidate debug_entry[26].uop.ctrl.is_load \n invalidate debug_entry[26].uop.ctrl.csr_cmd \n invalidate debug_entry[26].uop.ctrl.fcn_dw \n invalidate debug_entry[26].uop.ctrl.op_fcn \n invalidate debug_entry[26].uop.ctrl.imm_sel \n invalidate debug_entry[26].uop.ctrl.op2_sel \n invalidate debug_entry[26].uop.ctrl.op1_sel \n invalidate debug_entry[26].uop.ctrl.br_type \n invalidate debug_entry[26].uop.fu_code \n invalidate debug_entry[26].uop.iq_type \n invalidate debug_entry[26].uop.debug_pc \n invalidate debug_entry[26].uop.is_rvc \n invalidate debug_entry[26].uop.debug_inst \n invalidate debug_entry[26].uop.inst \n invalidate debug_entry[26].uop.uopc \n invalidate debug_entry[26].unsafe \n invalidate debug_entry[26].busy \n invalidate debug_entry[26].valid \n invalidate debug_entry[27].exception \n invalidate debug_entry[27].uop.debug_tsrc \n invalidate debug_entry[27].uop.debug_fsrc \n invalidate debug_entry[27].uop.bp_xcpt_if \n invalidate debug_entry[27].uop.bp_debug_if \n invalidate debug_entry[27].uop.xcpt_ma_if \n invalidate debug_entry[27].uop.xcpt_ae_if \n invalidate debug_entry[27].uop.xcpt_pf_if \n invalidate debug_entry[27].uop.fp_single \n invalidate debug_entry[27].uop.fp_val \n invalidate debug_entry[27].uop.frs3_en \n invalidate debug_entry[27].uop.lrs2_rtype \n invalidate debug_entry[27].uop.lrs1_rtype \n invalidate debug_entry[27].uop.dst_rtype \n invalidate debug_entry[27].uop.ldst_val \n invalidate debug_entry[27].uop.lrs3 \n invalidate debug_entry[27].uop.lrs2 \n invalidate debug_entry[27].uop.lrs1 \n invalidate debug_entry[27].uop.ldst \n invalidate debug_entry[27].uop.ldst_is_rs1 \n invalidate debug_entry[27].uop.flush_on_commit \n invalidate debug_entry[27].uop.is_unique \n invalidate debug_entry[27].uop.is_sys_pc2epc \n invalidate debug_entry[27].uop.uses_stq \n invalidate debug_entry[27].uop.uses_ldq \n invalidate debug_entry[27].uop.is_amo \n invalidate debug_entry[27].uop.is_fencei \n invalidate debug_entry[27].uop.is_fence \n invalidate debug_entry[27].uop.mem_signed \n invalidate debug_entry[27].uop.mem_size \n invalidate debug_entry[27].uop.mem_cmd \n invalidate debug_entry[27].uop.bypassable \n invalidate debug_entry[27].uop.exc_cause \n invalidate debug_entry[27].uop.exception \n invalidate debug_entry[27].uop.stale_pdst \n invalidate debug_entry[27].uop.ppred_busy \n invalidate debug_entry[27].uop.prs3_busy \n invalidate debug_entry[27].uop.prs2_busy \n invalidate debug_entry[27].uop.prs1_busy \n invalidate debug_entry[27].uop.ppred \n invalidate debug_entry[27].uop.prs3 \n invalidate debug_entry[27].uop.prs2 \n invalidate debug_entry[27].uop.prs1 \n invalidate debug_entry[27].uop.pdst \n invalidate debug_entry[27].uop.rxq_idx \n invalidate debug_entry[27].uop.stq_idx \n invalidate debug_entry[27].uop.ldq_idx \n invalidate debug_entry[27].uop.rob_idx \n invalidate debug_entry[27].uop.csr_addr \n invalidate debug_entry[27].uop.imm_packed \n invalidate debug_entry[27].uop.taken \n invalidate debug_entry[27].uop.pc_lob \n invalidate debug_entry[27].uop.edge_inst \n invalidate debug_entry[27].uop.ftq_idx \n invalidate debug_entry[27].uop.br_tag \n invalidate debug_entry[27].uop.br_mask \n invalidate debug_entry[27].uop.is_sfb \n invalidate debug_entry[27].uop.is_jal \n invalidate debug_entry[27].uop.is_jalr \n invalidate debug_entry[27].uop.is_br \n invalidate debug_entry[27].uop.iw_p2_poisoned \n invalidate debug_entry[27].uop.iw_p1_poisoned \n invalidate debug_entry[27].uop.iw_state \n invalidate debug_entry[27].uop.ctrl.is_std \n invalidate debug_entry[27].uop.ctrl.is_sta \n invalidate debug_entry[27].uop.ctrl.is_load \n invalidate debug_entry[27].uop.ctrl.csr_cmd \n invalidate debug_entry[27].uop.ctrl.fcn_dw \n invalidate debug_entry[27].uop.ctrl.op_fcn \n invalidate debug_entry[27].uop.ctrl.imm_sel \n invalidate debug_entry[27].uop.ctrl.op2_sel \n invalidate debug_entry[27].uop.ctrl.op1_sel \n invalidate debug_entry[27].uop.ctrl.br_type \n invalidate debug_entry[27].uop.fu_code \n invalidate debug_entry[27].uop.iq_type \n invalidate debug_entry[27].uop.debug_pc \n invalidate debug_entry[27].uop.is_rvc \n invalidate debug_entry[27].uop.debug_inst \n invalidate debug_entry[27].uop.inst \n invalidate debug_entry[27].uop.uopc \n invalidate debug_entry[27].unsafe \n invalidate debug_entry[27].busy \n invalidate debug_entry[27].valid \n invalidate debug_entry[28].exception \n invalidate debug_entry[28].uop.debug_tsrc \n invalidate debug_entry[28].uop.debug_fsrc \n invalidate debug_entry[28].uop.bp_xcpt_if \n invalidate debug_entry[28].uop.bp_debug_if \n invalidate debug_entry[28].uop.xcpt_ma_if \n invalidate debug_entry[28].uop.xcpt_ae_if \n invalidate debug_entry[28].uop.xcpt_pf_if \n invalidate debug_entry[28].uop.fp_single \n invalidate debug_entry[28].uop.fp_val \n invalidate debug_entry[28].uop.frs3_en \n invalidate debug_entry[28].uop.lrs2_rtype \n invalidate debug_entry[28].uop.lrs1_rtype \n invalidate debug_entry[28].uop.dst_rtype \n invalidate debug_entry[28].uop.ldst_val \n invalidate debug_entry[28].uop.lrs3 \n invalidate debug_entry[28].uop.lrs2 \n invalidate debug_entry[28].uop.lrs1 \n invalidate debug_entry[28].uop.ldst \n invalidate debug_entry[28].uop.ldst_is_rs1 \n invalidate debug_entry[28].uop.flush_on_commit \n invalidate debug_entry[28].uop.is_unique \n invalidate debug_entry[28].uop.is_sys_pc2epc \n invalidate debug_entry[28].uop.uses_stq \n invalidate debug_entry[28].uop.uses_ldq \n invalidate debug_entry[28].uop.is_amo \n invalidate debug_entry[28].uop.is_fencei \n invalidate debug_entry[28].uop.is_fence \n invalidate debug_entry[28].uop.mem_signed \n invalidate debug_entry[28].uop.mem_size \n invalidate debug_entry[28].uop.mem_cmd \n invalidate debug_entry[28].uop.bypassable \n invalidate debug_entry[28].uop.exc_cause \n invalidate debug_entry[28].uop.exception \n invalidate debug_entry[28].uop.stale_pdst \n invalidate debug_entry[28].uop.ppred_busy \n invalidate debug_entry[28].uop.prs3_busy \n invalidate debug_entry[28].uop.prs2_busy \n invalidate debug_entry[28].uop.prs1_busy \n invalidate debug_entry[28].uop.ppred \n invalidate debug_entry[28].uop.prs3 \n invalidate debug_entry[28].uop.prs2 \n invalidate debug_entry[28].uop.prs1 \n invalidate debug_entry[28].uop.pdst \n invalidate debug_entry[28].uop.rxq_idx \n invalidate debug_entry[28].uop.stq_idx \n invalidate debug_entry[28].uop.ldq_idx \n invalidate debug_entry[28].uop.rob_idx \n invalidate debug_entry[28].uop.csr_addr \n invalidate debug_entry[28].uop.imm_packed \n invalidate debug_entry[28].uop.taken \n invalidate debug_entry[28].uop.pc_lob \n invalidate debug_entry[28].uop.edge_inst \n invalidate debug_entry[28].uop.ftq_idx \n invalidate debug_entry[28].uop.br_tag \n invalidate debug_entry[28].uop.br_mask \n invalidate debug_entry[28].uop.is_sfb \n invalidate debug_entry[28].uop.is_jal \n invalidate debug_entry[28].uop.is_jalr \n invalidate debug_entry[28].uop.is_br \n invalidate debug_entry[28].uop.iw_p2_poisoned \n invalidate debug_entry[28].uop.iw_p1_poisoned \n invalidate debug_entry[28].uop.iw_state \n invalidate debug_entry[28].uop.ctrl.is_std \n invalidate debug_entry[28].uop.ctrl.is_sta \n invalidate debug_entry[28].uop.ctrl.is_load \n invalidate debug_entry[28].uop.ctrl.csr_cmd \n invalidate debug_entry[28].uop.ctrl.fcn_dw \n invalidate debug_entry[28].uop.ctrl.op_fcn \n invalidate debug_entry[28].uop.ctrl.imm_sel \n invalidate debug_entry[28].uop.ctrl.op2_sel \n invalidate debug_entry[28].uop.ctrl.op1_sel \n invalidate debug_entry[28].uop.ctrl.br_type \n invalidate debug_entry[28].uop.fu_code \n invalidate debug_entry[28].uop.iq_type \n invalidate debug_entry[28].uop.debug_pc \n invalidate debug_entry[28].uop.is_rvc \n invalidate debug_entry[28].uop.debug_inst \n invalidate debug_entry[28].uop.inst \n invalidate debug_entry[28].uop.uopc \n invalidate debug_entry[28].unsafe \n invalidate debug_entry[28].busy \n invalidate debug_entry[28].valid \n invalidate debug_entry[29].exception \n invalidate debug_entry[29].uop.debug_tsrc \n invalidate debug_entry[29].uop.debug_fsrc \n invalidate debug_entry[29].uop.bp_xcpt_if \n invalidate debug_entry[29].uop.bp_debug_if \n invalidate debug_entry[29].uop.xcpt_ma_if \n invalidate debug_entry[29].uop.xcpt_ae_if \n invalidate debug_entry[29].uop.xcpt_pf_if \n invalidate debug_entry[29].uop.fp_single \n invalidate debug_entry[29].uop.fp_val \n invalidate debug_entry[29].uop.frs3_en \n invalidate debug_entry[29].uop.lrs2_rtype \n invalidate debug_entry[29].uop.lrs1_rtype \n invalidate debug_entry[29].uop.dst_rtype \n invalidate debug_entry[29].uop.ldst_val \n invalidate debug_entry[29].uop.lrs3 \n invalidate debug_entry[29].uop.lrs2 \n invalidate debug_entry[29].uop.lrs1 \n invalidate debug_entry[29].uop.ldst \n invalidate debug_entry[29].uop.ldst_is_rs1 \n invalidate debug_entry[29].uop.flush_on_commit \n invalidate debug_entry[29].uop.is_unique \n invalidate debug_entry[29].uop.is_sys_pc2epc \n invalidate debug_entry[29].uop.uses_stq \n invalidate debug_entry[29].uop.uses_ldq \n invalidate debug_entry[29].uop.is_amo \n invalidate debug_entry[29].uop.is_fencei \n invalidate debug_entry[29].uop.is_fence \n invalidate debug_entry[29].uop.mem_signed \n invalidate debug_entry[29].uop.mem_size \n invalidate debug_entry[29].uop.mem_cmd \n invalidate debug_entry[29].uop.bypassable \n invalidate debug_entry[29].uop.exc_cause \n invalidate debug_entry[29].uop.exception \n invalidate debug_entry[29].uop.stale_pdst \n invalidate debug_entry[29].uop.ppred_busy \n invalidate debug_entry[29].uop.prs3_busy \n invalidate debug_entry[29].uop.prs2_busy \n invalidate debug_entry[29].uop.prs1_busy \n invalidate debug_entry[29].uop.ppred \n invalidate debug_entry[29].uop.prs3 \n invalidate debug_entry[29].uop.prs2 \n invalidate debug_entry[29].uop.prs1 \n invalidate debug_entry[29].uop.pdst \n invalidate debug_entry[29].uop.rxq_idx \n invalidate debug_entry[29].uop.stq_idx \n invalidate debug_entry[29].uop.ldq_idx \n invalidate debug_entry[29].uop.rob_idx \n invalidate debug_entry[29].uop.csr_addr \n invalidate debug_entry[29].uop.imm_packed \n invalidate debug_entry[29].uop.taken \n invalidate debug_entry[29].uop.pc_lob \n invalidate debug_entry[29].uop.edge_inst \n invalidate debug_entry[29].uop.ftq_idx \n invalidate debug_entry[29].uop.br_tag \n invalidate debug_entry[29].uop.br_mask \n invalidate debug_entry[29].uop.is_sfb \n invalidate debug_entry[29].uop.is_jal \n invalidate debug_entry[29].uop.is_jalr \n invalidate debug_entry[29].uop.is_br \n invalidate debug_entry[29].uop.iw_p2_poisoned \n invalidate debug_entry[29].uop.iw_p1_poisoned \n invalidate debug_entry[29].uop.iw_state \n invalidate debug_entry[29].uop.ctrl.is_std \n invalidate debug_entry[29].uop.ctrl.is_sta \n invalidate debug_entry[29].uop.ctrl.is_load \n invalidate debug_entry[29].uop.ctrl.csr_cmd \n invalidate debug_entry[29].uop.ctrl.fcn_dw \n invalidate debug_entry[29].uop.ctrl.op_fcn \n invalidate debug_entry[29].uop.ctrl.imm_sel \n invalidate debug_entry[29].uop.ctrl.op2_sel \n invalidate debug_entry[29].uop.ctrl.op1_sel \n invalidate debug_entry[29].uop.ctrl.br_type \n invalidate debug_entry[29].uop.fu_code \n invalidate debug_entry[29].uop.iq_type \n invalidate debug_entry[29].uop.debug_pc \n invalidate debug_entry[29].uop.is_rvc \n invalidate debug_entry[29].uop.debug_inst \n invalidate debug_entry[29].uop.inst \n invalidate debug_entry[29].uop.uopc \n invalidate debug_entry[29].unsafe \n invalidate debug_entry[29].busy \n invalidate debug_entry[29].valid \n invalidate debug_entry[30].exception \n invalidate debug_entry[30].uop.debug_tsrc \n invalidate debug_entry[30].uop.debug_fsrc \n invalidate debug_entry[30].uop.bp_xcpt_if \n invalidate debug_entry[30].uop.bp_debug_if \n invalidate debug_entry[30].uop.xcpt_ma_if \n invalidate debug_entry[30].uop.xcpt_ae_if \n invalidate debug_entry[30].uop.xcpt_pf_if \n invalidate debug_entry[30].uop.fp_single \n invalidate debug_entry[30].uop.fp_val \n invalidate debug_entry[30].uop.frs3_en \n invalidate debug_entry[30].uop.lrs2_rtype \n invalidate debug_entry[30].uop.lrs1_rtype \n invalidate debug_entry[30].uop.dst_rtype \n invalidate debug_entry[30].uop.ldst_val \n invalidate debug_entry[30].uop.lrs3 \n invalidate debug_entry[30].uop.lrs2 \n invalidate debug_entry[30].uop.lrs1 \n invalidate debug_entry[30].uop.ldst \n invalidate debug_entry[30].uop.ldst_is_rs1 \n invalidate debug_entry[30].uop.flush_on_commit \n invalidate debug_entry[30].uop.is_unique \n invalidate debug_entry[30].uop.is_sys_pc2epc \n invalidate debug_entry[30].uop.uses_stq \n invalidate debug_entry[30].uop.uses_ldq \n invalidate debug_entry[30].uop.is_amo \n invalidate debug_entry[30].uop.is_fencei \n invalidate debug_entry[30].uop.is_fence \n invalidate debug_entry[30].uop.mem_signed \n invalidate debug_entry[30].uop.mem_size \n invalidate debug_entry[30].uop.mem_cmd \n invalidate debug_entry[30].uop.bypassable \n invalidate debug_entry[30].uop.exc_cause \n invalidate debug_entry[30].uop.exception \n invalidate debug_entry[30].uop.stale_pdst \n invalidate debug_entry[30].uop.ppred_busy \n invalidate debug_entry[30].uop.prs3_busy \n invalidate debug_entry[30].uop.prs2_busy \n invalidate debug_entry[30].uop.prs1_busy \n invalidate debug_entry[30].uop.ppred \n invalidate debug_entry[30].uop.prs3 \n invalidate debug_entry[30].uop.prs2 \n invalidate debug_entry[30].uop.prs1 \n invalidate debug_entry[30].uop.pdst \n invalidate debug_entry[30].uop.rxq_idx \n invalidate debug_entry[30].uop.stq_idx \n invalidate debug_entry[30].uop.ldq_idx \n invalidate debug_entry[30].uop.rob_idx \n invalidate debug_entry[30].uop.csr_addr \n invalidate debug_entry[30].uop.imm_packed \n invalidate debug_entry[30].uop.taken \n invalidate debug_entry[30].uop.pc_lob \n invalidate debug_entry[30].uop.edge_inst \n invalidate debug_entry[30].uop.ftq_idx \n invalidate debug_entry[30].uop.br_tag \n invalidate debug_entry[30].uop.br_mask \n invalidate debug_entry[30].uop.is_sfb \n invalidate debug_entry[30].uop.is_jal \n invalidate debug_entry[30].uop.is_jalr \n invalidate debug_entry[30].uop.is_br \n invalidate debug_entry[30].uop.iw_p2_poisoned \n invalidate debug_entry[30].uop.iw_p1_poisoned \n invalidate debug_entry[30].uop.iw_state \n invalidate debug_entry[30].uop.ctrl.is_std \n invalidate debug_entry[30].uop.ctrl.is_sta \n invalidate debug_entry[30].uop.ctrl.is_load \n invalidate debug_entry[30].uop.ctrl.csr_cmd \n invalidate debug_entry[30].uop.ctrl.fcn_dw \n invalidate debug_entry[30].uop.ctrl.op_fcn \n invalidate debug_entry[30].uop.ctrl.imm_sel \n invalidate debug_entry[30].uop.ctrl.op2_sel \n invalidate debug_entry[30].uop.ctrl.op1_sel \n invalidate debug_entry[30].uop.ctrl.br_type \n invalidate debug_entry[30].uop.fu_code \n invalidate debug_entry[30].uop.iq_type \n invalidate debug_entry[30].uop.debug_pc \n invalidate debug_entry[30].uop.is_rvc \n invalidate debug_entry[30].uop.debug_inst \n invalidate debug_entry[30].uop.inst \n invalidate debug_entry[30].uop.uopc \n invalidate debug_entry[30].unsafe \n invalidate debug_entry[30].busy \n invalidate debug_entry[30].valid \n invalidate debug_entry[31].exception \n invalidate debug_entry[31].uop.debug_tsrc \n invalidate debug_entry[31].uop.debug_fsrc \n invalidate debug_entry[31].uop.bp_xcpt_if \n invalidate debug_entry[31].uop.bp_debug_if \n invalidate debug_entry[31].uop.xcpt_ma_if \n invalidate debug_entry[31].uop.xcpt_ae_if \n invalidate debug_entry[31].uop.xcpt_pf_if \n invalidate debug_entry[31].uop.fp_single \n invalidate debug_entry[31].uop.fp_val \n invalidate debug_entry[31].uop.frs3_en \n invalidate debug_entry[31].uop.lrs2_rtype \n invalidate debug_entry[31].uop.lrs1_rtype \n invalidate debug_entry[31].uop.dst_rtype \n invalidate debug_entry[31].uop.ldst_val \n invalidate debug_entry[31].uop.lrs3 \n invalidate debug_entry[31].uop.lrs2 \n invalidate debug_entry[31].uop.lrs1 \n invalidate debug_entry[31].uop.ldst \n invalidate debug_entry[31].uop.ldst_is_rs1 \n invalidate debug_entry[31].uop.flush_on_commit \n invalidate debug_entry[31].uop.is_unique \n invalidate debug_entry[31].uop.is_sys_pc2epc \n invalidate debug_entry[31].uop.uses_stq \n invalidate debug_entry[31].uop.uses_ldq \n invalidate debug_entry[31].uop.is_amo \n invalidate debug_entry[31].uop.is_fencei \n invalidate debug_entry[31].uop.is_fence \n invalidate debug_entry[31].uop.mem_signed \n invalidate debug_entry[31].uop.mem_size \n invalidate debug_entry[31].uop.mem_cmd \n invalidate debug_entry[31].uop.bypassable \n invalidate debug_entry[31].uop.exc_cause \n invalidate debug_entry[31].uop.exception \n invalidate debug_entry[31].uop.stale_pdst \n invalidate debug_entry[31].uop.ppred_busy \n invalidate debug_entry[31].uop.prs3_busy \n invalidate debug_entry[31].uop.prs2_busy \n invalidate debug_entry[31].uop.prs1_busy \n invalidate debug_entry[31].uop.ppred \n invalidate debug_entry[31].uop.prs3 \n invalidate debug_entry[31].uop.prs2 \n invalidate debug_entry[31].uop.prs1 \n invalidate debug_entry[31].uop.pdst \n invalidate debug_entry[31].uop.rxq_idx \n invalidate debug_entry[31].uop.stq_idx \n invalidate debug_entry[31].uop.ldq_idx \n invalidate debug_entry[31].uop.rob_idx \n invalidate debug_entry[31].uop.csr_addr \n invalidate debug_entry[31].uop.imm_packed \n invalidate debug_entry[31].uop.taken \n invalidate debug_entry[31].uop.pc_lob \n invalidate debug_entry[31].uop.edge_inst \n invalidate debug_entry[31].uop.ftq_idx \n invalidate debug_entry[31].uop.br_tag \n invalidate debug_entry[31].uop.br_mask \n invalidate debug_entry[31].uop.is_sfb \n invalidate debug_entry[31].uop.is_jal \n invalidate debug_entry[31].uop.is_jalr \n invalidate debug_entry[31].uop.is_br \n invalidate debug_entry[31].uop.iw_p2_poisoned \n invalidate debug_entry[31].uop.iw_p1_poisoned \n invalidate debug_entry[31].uop.iw_state \n invalidate debug_entry[31].uop.ctrl.is_std \n invalidate debug_entry[31].uop.ctrl.is_sta \n invalidate debug_entry[31].uop.ctrl.is_load \n invalidate debug_entry[31].uop.ctrl.csr_cmd \n invalidate debug_entry[31].uop.ctrl.fcn_dw \n invalidate debug_entry[31].uop.ctrl.op_fcn \n invalidate debug_entry[31].uop.ctrl.imm_sel \n invalidate debug_entry[31].uop.ctrl.op2_sel \n invalidate debug_entry[31].uop.ctrl.op1_sel \n invalidate debug_entry[31].uop.ctrl.br_type \n invalidate debug_entry[31].uop.fu_code \n invalidate debug_entry[31].uop.iq_type \n invalidate debug_entry[31].uop.debug_pc \n invalidate debug_entry[31].uop.is_rvc \n invalidate debug_entry[31].uop.debug_inst \n invalidate debug_entry[31].uop.inst \n invalidate debug_entry[31].uop.uopc \n invalidate debug_entry[31].unsafe \n invalidate debug_entry[31].busy \n invalidate debug_entry[31].valid \n wire _rob_unsafe_masked_WIRE : UInt<1>[32] \n connect _rob_unsafe_masked_WIRE[0], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[1], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[2], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[3], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[4], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[5], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[6], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[7], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[8], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[9], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[10], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[11], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[12], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[13], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[14], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[15], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[16], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[17], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[18], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[19], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[20], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[21], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[22], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[23], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[24], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[25], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[26], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[27], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[28], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[29], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[30], UInt<1>(0h0) \n connect _rob_unsafe_masked_WIRE[31], UInt<1>(0h0) \n wire rob_unsafe_masked : UInt<1>[32] \n connect rob_unsafe_masked, _rob_unsafe_masked_WIRE \n smem rob_debug_inst_mem : UInt<32>[1] [32] \n wire _rob_debug_inst_wmask_WIRE : UInt<1>[1] \n connect _rob_debug_inst_wmask_WIRE[0], UInt<1>(0h0) \n wire rob_debug_inst_wmask : UInt<1>[1] \n connect rob_debug_inst_wmask, _rob_debug_inst_wmask_WIRE \n wire rob_debug_inst_wdata : UInt<32>[1] \n write mport MPORT = rob_debug_inst_mem[rob_tail], clock \n when rob_debug_inst_wmask[0] : \n connect MPORT[0], rob_debug_inst_wdata[0] \n wire _rob_debug_inst_rdata_WIRE : UInt<5> \n invalidate _rob_debug_inst_rdata_WIRE \n when will_commit[0] : \n connect _rob_debug_inst_rdata_WIRE, rob_head \n read mport rob_debug_inst_rdata = rob_debug_inst_mem[_rob_debug_inst_rdata_WIRE], clock \n reg rob_fflags_0 : UInt<5>[32], clock \n wire _rob_val_WIRE : UInt<1>[32] \n connect _rob_val_WIRE[0], UInt<1>(0h0) \n connect _rob_val_WIRE[1], UInt<1>(0h0) \n connect _rob_val_WIRE[2], UInt<1>(0h0) \n connect _rob_val_WIRE[3], UInt<1>(0h0) \n connect _rob_val_WIRE[4], UInt<1>(0h0) \n connect _rob_val_WIRE[5], UInt<1>(0h0) \n connect _rob_val_WIRE[6], UInt<1>(0h0) \n connect _rob_val_WIRE[7], UInt<1>(0h0) \n connect _rob_val_WIRE[8], UInt<1>(0h0) \n connect _rob_val_WIRE[9], UInt<1>(0h0) \n connect _rob_val_WIRE[10], UInt<1>(0h0) \n connect _rob_val_WIRE[11], UInt<1>(0h0) \n connect _rob_val_WIRE[12], UInt<1>(0h0) \n connect _rob_val_WIRE[13], UInt<1>(0h0) \n connect _rob_val_WIRE[14], UInt<1>(0h0) \n connect _rob_val_WIRE[15], UInt<1>(0h0) \n connect _rob_val_WIRE[16], UInt<1>(0h0) \n connect _rob_val_WIRE[17], UInt<1>(0h0) \n connect _rob_val_WIRE[18], UInt<1>(0h0) \n connect _rob_val_WIRE[19], UInt<1>(0h0) \n connect _rob_val_WIRE[20], UInt<1>(0h0) \n connect _rob_val_WIRE[21], UInt<1>(0h0) \n connect _rob_val_WIRE[22], UInt<1>(0h0) \n connect _rob_val_WIRE[23], UInt<1>(0h0) \n connect _rob_val_WIRE[24], UInt<1>(0h0) \n connect _rob_val_WIRE[25], UInt<1>(0h0) \n connect _rob_val_WIRE[26], UInt<1>(0h0) \n connect _rob_val_WIRE[27], UInt<1>(0h0) \n connect _rob_val_WIRE[28], UInt<1>(0h0) \n connect _rob_val_WIRE[29], UInt<1>(0h0) \n connect _rob_val_WIRE[30], UInt<1>(0h0) \n connect _rob_val_WIRE[31], UInt<1>(0h0) \n regreset rob_val : UInt<1>[32], clock, reset, _rob_val_WIRE \n reg rob_bsy : UInt<1>[32], clock \n reg rob_unsafe : UInt<1>[32], clock \n reg rob_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[32], clock \n reg rob_exception : UInt<1>[32], clock \n reg rob_predicated : UInt<1>[32], clock \n cmem rob_debug_wdata : UInt<64> [32] \n connect rob_debug_inst_wmask[0], io.enq_valids[0] \n connect rob_debug_inst_wdata[0], io.enq_uops[0].debug_inst \n when io.enq_valids[0] : \n connect rob_val[rob_tail], UInt<1>(0h1) \n node _rob_bsy_T = or(io.enq_uops[0].is_fence, io.enq_uops[0].is_fencei) \n node _rob_bsy_T_1 = eq(_rob_bsy_T, UInt<1>(0h0)) \n connect rob_bsy[rob_tail], _rob_bsy_T_1 \n node _rob_unsafe_T = eq(io.enq_uops[0].is_fence, UInt<1>(0h0)) \n node _rob_unsafe_T_1 = and(io.enq_uops[0].uses_stq, _rob_unsafe_T) \n node _rob_unsafe_T_2 = or(io.enq_uops[0].uses_ldq, _rob_unsafe_T_1) \n node _rob_unsafe_T_3 = or(_rob_unsafe_T_2, io.enq_uops[0].is_br) \n node _rob_unsafe_T_4 = or(_rob_unsafe_T_3, io.enq_uops[0].is_jalr) \n connect rob_unsafe[rob_tail], _rob_unsafe_T_4 \n connect rob_uop[rob_tail], io.enq_uops[0] \n connect rob_exception[rob_tail], io.enq_uops[0].exception \n connect rob_predicated[rob_tail], UInt<1>(0h0) \n connect rob_fflags_0[rob_tail], UInt<1>(0h0) \n node _T = eq(rob_val[rob_tail], UInt<1>(0h0)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] overwriting a valid entry.\\n at rob.scala:333 assert (rob_val(rob_tail) === false.B, \\\"[rob] overwriting a valid entry.\\\")\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _T_4 = shr(io.enq_uops[0].rob_idx, 0) \n node _T_5 = eq(_T_4, rob_tail) \n node _T_6 = asUInt(reset) \n node _T_7 = eq(_T_6, UInt<1>(0h0)) \n when _T_7 : \n node _T_8 = eq(_T_5, UInt<1>(0h0)) \n when _T_8 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at rob.scala:334 assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)\\n\") : printf_1 \n assert(clock, _T_5, UInt<1>(0h1), \"\") : assert_1 \n else :\n\n node _T_9 = eq(rob_val[rob_tail], UInt<1>(0h0)) \n node _T_10 = and(io.enq_valids[0], _T_9) \n when _T_10 : \n connect rob_uop[rob_tail].debug_inst, UInt<32>(0h4033) \n node _T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_12 = and(io.wb_resps[0].valid, _T_11) \n when _T_12 : \n connect rob_bsy[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_unsafe[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_predicated[io.wb_resps[0].bits.uop.rob_idx], io.wb_resps[0].bits.predicated \n node _T_13 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_14 = and(io.wb_resps[1].valid, _T_13) \n when _T_14 : \n connect rob_bsy[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_unsafe[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_predicated[io.wb_resps[1].bits.uop.rob_idx], io.wb_resps[1].bits.predicated \n node _T_15 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_16 = and(io.wb_resps[2].valid, _T_15) \n when _T_16 : \n connect rob_bsy[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_unsafe[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_predicated[io.wb_resps[2].bits.uop.rob_idx], io.wb_resps[2].bits.predicated \n node _T_17 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_18 = and(io.wb_resps[3].valid, _T_17) \n when _T_18 : \n connect rob_bsy[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_unsafe[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0) \n connect rob_predicated[io.wb_resps[3].bits.uop.rob_idx], io.wb_resps[3].bits.predicated \n node _T_19 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_20 = and(io.lsu_clr_bsy[0].valid, _T_19) \n when _T_20 : \n connect rob_bsy[io.lsu_clr_bsy[0].bits], UInt<1>(0h0) \n connect rob_unsafe[io.lsu_clr_bsy[0].bits], UInt<1>(0h0) \n node _T_21 = eq(rob_val[io.lsu_clr_bsy[0].bits], UInt<1>(0h1)) \n node _T_22 = asUInt(reset) \n node _T_23 = eq(_T_22, UInt<1>(0h0)) \n when _T_23 : \n node _T_24 = eq(_T_21, UInt<1>(0h0)) \n when _T_24 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] store writing back to invalid entry.\\n at rob.scala:365 assert (rob_val(cidx) === true.B, \\\"[rob] store writing back to invalid entry.\\\")\\n\") : printf_2 \n assert(clock, _T_21, UInt<1>(0h1), \"\") : assert_2 \n node _T_25 = eq(rob_bsy[io.lsu_clr_bsy[0].bits], UInt<1>(0h1)) \n node _T_26 = asUInt(reset) \n node _T_27 = eq(_T_26, UInt<1>(0h0)) \n when _T_27 : \n node _T_28 = eq(_T_25, UInt<1>(0h0)) \n when _T_28 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] store writing back to a not-busy entry.\\n at rob.scala:366 assert (rob_bsy(cidx) === true.B, \\\"[rob] store writing back to a not-busy entry.\\\")\\n\") : printf_3 \n assert(clock, _T_25, UInt<1>(0h1), \"\") : assert_3 \n node _T_29 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_30 = and(io.lsu_clr_bsy[1].valid, _T_29) \n when _T_30 : \n connect rob_bsy[io.lsu_clr_bsy[1].bits], UInt<1>(0h0) \n connect rob_unsafe[io.lsu_clr_bsy[1].bits], UInt<1>(0h0) \n node _T_31 = eq(rob_val[io.lsu_clr_bsy[1].bits], UInt<1>(0h1)) \n node _T_32 = asUInt(reset) \n node _T_33 = eq(_T_32, UInt<1>(0h0)) \n when _T_33 : \n node _T_34 = eq(_T_31, UInt<1>(0h0)) \n when _T_34 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] store writing back to invalid entry.\\n at rob.scala:365 assert (rob_val(cidx) === true.B, \\\"[rob] store writing back to invalid entry.\\\")\\n\") : printf_4 \n assert(clock, _T_31, UInt<1>(0h1), \"\") : assert_4 \n node _T_35 = eq(rob_bsy[io.lsu_clr_bsy[1].bits], UInt<1>(0h1)) \n node _T_36 = asUInt(reset) \n node _T_37 = eq(_T_36, UInt<1>(0h0)) \n when _T_37 : \n node _T_38 = eq(_T_35, UInt<1>(0h0)) \n when _T_38 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] store writing back to a not-busy entry.\\n at rob.scala:366 assert (rob_bsy(cidx) === true.B, \\\"[rob] store writing back to a not-busy entry.\\\")\\n\") : printf_5 \n assert(clock, _T_35, UInt<1>(0h1), \"\") : assert_5 \n node _T_39 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_40 = and(io.lsu_clr_unsafe[0].valid, _T_39) \n when _T_40 : \n connect rob_unsafe[io.lsu_clr_unsafe[0].bits], UInt<1>(0h0) \n node _T_41 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_42 = and(io.fflags[0].valid, _T_41) \n when _T_42 : \n connect rob_fflags_0[io.fflags[0].bits.uop.rob_idx], io.fflags[0].bits.flags \n node _T_43 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_44 = and(io.fflags[1].valid, _T_43) \n when _T_44 : \n connect rob_fflags_0[io.fflags[1].bits.uop.rob_idx], io.fflags[1].bits.flags \n node _T_45 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_46 = and(io.lxcpt.valid, _T_45) \n when _T_46 : \n connect rob_exception[io.lxcpt.bits.uop.rob_idx], UInt<1>(0h1) \n node _T_47 = neq(io.lxcpt.bits.cause, UInt<5>(0h10)) \n when _T_47 : \n node _T_48 = asUInt(reset) \n node _T_49 = eq(_T_48, UInt<1>(0h0)) \n when _T_49 : \n node _T_50 = eq(rob_unsafe[io.lxcpt.bits.uop.rob_idx], UInt<1>(0h0)) \n when _T_50 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: An instruction marked as safe is causing an exception\\n at rob.scala:394 assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),\\n\") : printf_6 \n assert(clock, rob_unsafe[io.lxcpt.bits.uop.rob_idx], UInt<1>(0h1), \"\") : assert_6 \n node _T_51 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_52 = and(io.csr_replay.valid, _T_51) \n when _T_52 : \n connect rob_exception[io.csr_replay.bits.uop.rob_idx], UInt<1>(0h1) \n node _can_throw_exception_0_T = and(rob_val[rob_head], rob_exception[rob_head]) \n connect can_throw_exception[0], _can_throw_exception_0_T \n node _can_commit_0_T = eq(rob_bsy[rob_head], UInt<1>(0h0)) \n node _can_commit_0_T_1 = and(rob_val[rob_head], _can_commit_0_T) \n node _can_commit_0_T_2 = eq(io.csr_stall, UInt<1>(0h0)) \n node _can_commit_0_T_3 = and(_can_commit_0_T_1, _can_commit_0_T_2) \n connect can_commit[0], _can_commit_0_T_3 \n connect io.commit.valids[0], will_commit[0] \n node _io_commit_arch_valids_0_T = eq(rob_predicated[com_idx], UInt<1>(0h0)) \n node _io_commit_arch_valids_0_T_1 = and(will_commit[0], _io_commit_arch_valids_0_T) \n connect io.commit.arch_valids[0], _io_commit_arch_valids_0_T_1 \n connect io.commit.uops[0], rob_uop[com_idx] \n connect io.commit.debug_insts[0], rob_debug_inst_rdata[0] \n node _T_53 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_54 = and(io.brupdate.b2.mispredict, _T_53) \n node _T_55 = eq(io.brupdate.b2.uop.rob_idx, com_idx) \n node _T_56 = and(_T_54, _T_55) \n when _T_56 : \n connect io.commit.uops[0].debug_fsrc, UInt<2>(0h3) \n connect io.commit.uops[0].taken, io.brupdate.b2.taken \n node _rbk_row_T = eq(rob_state, UInt<2>(0h2)) \n node _rbk_row_T_1 = eq(full, UInt<1>(0h0)) \n node rbk_row = and(_rbk_row_T, _rbk_row_T_1) \n node _io_commit_rbk_valids_0_T = and(rbk_row, rob_val[com_idx]) \n node _io_commit_rbk_valids_0_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _io_commit_rbk_valids_0_T_2 = and(_io_commit_rbk_valids_0_T, _io_commit_rbk_valids_0_T_1) \n connect io.commit.rbk_valids[0], _io_commit_rbk_valids_0_T_2 \n node _io_commit_rollback_T = eq(rob_state, UInt<2>(0h2)) \n connect io.commit.rollback, _io_commit_rollback_T \n node _T_57 = and(io.commit.valids[0], io.commit.rbk_valids[0]) \n node _T_58 = eq(_T_57, UInt<1>(0h0)) \n node _T_59 = asUInt(reset) \n node _T_60 = eq(_T_59, UInt<1>(0h0)) \n when _T_60 : \n node _T_61 = eq(_T_58, UInt<1>(0h0)) \n when _T_61 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: com_valids and rbk_valids are mutually exclusive\\n at rob.scala:434 assert (!(io.commit.valids.reduce(_||_) && io.commit.rbk_valids.reduce(_||_)),\\n\") : printf_7 \n assert(clock, _T_58, UInt<1>(0h1), \"\") : assert_7 \n when rbk_row : \n connect rob_val[com_idx], UInt<1>(0h0) \n connect rob_exception[com_idx], UInt<1>(0h0) \n node _T_62 = and(io.brupdate.b1.mispredict_mask, rob_uop[0].br_mask) \n node _T_63 = neq(_T_62, UInt<1>(0h0)) \n when _T_63 : \n connect rob_val[0], UInt<1>(0h0) \n connect rob_uop[0].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[0] : \n node _rob_uop_0_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_0_br_mask_T_1 = and(rob_uop[0].br_mask, _rob_uop_0_br_mask_T) \n connect rob_uop[0].br_mask, _rob_uop_0_br_mask_T_1 \n node _T_64 = and(io.brupdate.b1.mispredict_mask, rob_uop[1].br_mask) \n node _T_65 = neq(_T_64, UInt<1>(0h0)) \n when _T_65 : \n connect rob_val[1], UInt<1>(0h0) \n connect rob_uop[1].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[1] : \n node _rob_uop_1_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_1_br_mask_T_1 = and(rob_uop[1].br_mask, _rob_uop_1_br_mask_T) \n connect rob_uop[1].br_mask, _rob_uop_1_br_mask_T_1 \n node _T_66 = and(io.brupdate.b1.mispredict_mask, rob_uop[2].br_mask) \n node _T_67 = neq(_T_66, UInt<1>(0h0)) \n when _T_67 : \n connect rob_val[2], UInt<1>(0h0) \n connect rob_uop[2].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[2] : \n node _rob_uop_2_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_2_br_mask_T_1 = and(rob_uop[2].br_mask, _rob_uop_2_br_mask_T) \n connect rob_uop[2].br_mask, _rob_uop_2_br_mask_T_1 \n node _T_68 = and(io.brupdate.b1.mispredict_mask, rob_uop[3].br_mask) \n node _T_69 = neq(_T_68, UInt<1>(0h0)) \n when _T_69 : \n connect rob_val[3], UInt<1>(0h0) \n connect rob_uop[3].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[3] : \n node _rob_uop_3_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_3_br_mask_T_1 = and(rob_uop[3].br_mask, _rob_uop_3_br_mask_T) \n connect rob_uop[3].br_mask, _rob_uop_3_br_mask_T_1 \n node _T_70 = and(io.brupdate.b1.mispredict_mask, rob_uop[4].br_mask) \n node _T_71 = neq(_T_70, UInt<1>(0h0)) \n when _T_71 : \n connect rob_val[4], UInt<1>(0h0) \n connect rob_uop[4].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[4] : \n node _rob_uop_4_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_4_br_mask_T_1 = and(rob_uop[4].br_mask, _rob_uop_4_br_mask_T) \n connect rob_uop[4].br_mask, _rob_uop_4_br_mask_T_1 \n node _T_72 = and(io.brupdate.b1.mispredict_mask, rob_uop[5].br_mask) \n node _T_73 = neq(_T_72, UInt<1>(0h0)) \n when _T_73 : \n connect rob_val[5], UInt<1>(0h0) \n connect rob_uop[5].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[5] : \n node _rob_uop_5_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_5_br_mask_T_1 = and(rob_uop[5].br_mask, _rob_uop_5_br_mask_T) \n connect rob_uop[5].br_mask, _rob_uop_5_br_mask_T_1 \n node _T_74 = and(io.brupdate.b1.mispredict_mask, rob_uop[6].br_mask) \n node _T_75 = neq(_T_74, UInt<1>(0h0)) \n when _T_75 : \n connect rob_val[6], UInt<1>(0h0) \n connect rob_uop[6].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[6] : \n node _rob_uop_6_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_6_br_mask_T_1 = and(rob_uop[6].br_mask, _rob_uop_6_br_mask_T) \n connect rob_uop[6].br_mask, _rob_uop_6_br_mask_T_1 \n node _T_76 = and(io.brupdate.b1.mispredict_mask, rob_uop[7].br_mask) \n node _T_77 = neq(_T_76, UInt<1>(0h0)) \n when _T_77 : \n connect rob_val[7], UInt<1>(0h0) \n connect rob_uop[7].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[7] : \n node _rob_uop_7_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_7_br_mask_T_1 = and(rob_uop[7].br_mask, _rob_uop_7_br_mask_T) \n connect rob_uop[7].br_mask, _rob_uop_7_br_mask_T_1 \n node _T_78 = and(io.brupdate.b1.mispredict_mask, rob_uop[8].br_mask) \n node _T_79 = neq(_T_78, UInt<1>(0h0)) \n when _T_79 : \n connect rob_val[8], UInt<1>(0h0) \n connect rob_uop[8].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[8] : \n node _rob_uop_8_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_8_br_mask_T_1 = and(rob_uop[8].br_mask, _rob_uop_8_br_mask_T) \n connect rob_uop[8].br_mask, _rob_uop_8_br_mask_T_1 \n node _T_80 = and(io.brupdate.b1.mispredict_mask, rob_uop[9].br_mask) \n node _T_81 = neq(_T_80, UInt<1>(0h0)) \n when _T_81 : \n connect rob_val[9], UInt<1>(0h0) \n connect rob_uop[9].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[9] : \n node _rob_uop_9_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_9_br_mask_T_1 = and(rob_uop[9].br_mask, _rob_uop_9_br_mask_T) \n connect rob_uop[9].br_mask, _rob_uop_9_br_mask_T_1 \n node _T_82 = and(io.brupdate.b1.mispredict_mask, rob_uop[10].br_mask) \n node _T_83 = neq(_T_82, UInt<1>(0h0)) \n when _T_83 : \n connect rob_val[10], UInt<1>(0h0) \n connect rob_uop[10].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[10] : \n node _rob_uop_10_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_10_br_mask_T_1 = and(rob_uop[10].br_mask, _rob_uop_10_br_mask_T) \n connect rob_uop[10].br_mask, _rob_uop_10_br_mask_T_1 \n node _T_84 = and(io.brupdate.b1.mispredict_mask, rob_uop[11].br_mask) \n node _T_85 = neq(_T_84, UInt<1>(0h0)) \n when _T_85 : \n connect rob_val[11], UInt<1>(0h0) \n connect rob_uop[11].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[11] : \n node _rob_uop_11_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_11_br_mask_T_1 = and(rob_uop[11].br_mask, _rob_uop_11_br_mask_T) \n connect rob_uop[11].br_mask, _rob_uop_11_br_mask_T_1 \n node _T_86 = and(io.brupdate.b1.mispredict_mask, rob_uop[12].br_mask) \n node _T_87 = neq(_T_86, UInt<1>(0h0)) \n when _T_87 : \n connect rob_val[12], UInt<1>(0h0) \n connect rob_uop[12].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[12] : \n node _rob_uop_12_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_12_br_mask_T_1 = and(rob_uop[12].br_mask, _rob_uop_12_br_mask_T) \n connect rob_uop[12].br_mask, _rob_uop_12_br_mask_T_1 \n node _T_88 = and(io.brupdate.b1.mispredict_mask, rob_uop[13].br_mask) \n node _T_89 = neq(_T_88, UInt<1>(0h0)) \n when _T_89 : \n connect rob_val[13], UInt<1>(0h0) \n connect rob_uop[13].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[13] : \n node _rob_uop_13_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_13_br_mask_T_1 = and(rob_uop[13].br_mask, _rob_uop_13_br_mask_T) \n connect rob_uop[13].br_mask, _rob_uop_13_br_mask_T_1 \n node _T_90 = and(io.brupdate.b1.mispredict_mask, rob_uop[14].br_mask) \n node _T_91 = neq(_T_90, UInt<1>(0h0)) \n when _T_91 : \n connect rob_val[14], UInt<1>(0h0) \n connect rob_uop[14].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[14] : \n node _rob_uop_14_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_14_br_mask_T_1 = and(rob_uop[14].br_mask, _rob_uop_14_br_mask_T) \n connect rob_uop[14].br_mask, _rob_uop_14_br_mask_T_1 \n node _T_92 = and(io.brupdate.b1.mispredict_mask, rob_uop[15].br_mask) \n node _T_93 = neq(_T_92, UInt<1>(0h0)) \n when _T_93 : \n connect rob_val[15], UInt<1>(0h0) \n connect rob_uop[15].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[15] : \n node _rob_uop_15_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_15_br_mask_T_1 = and(rob_uop[15].br_mask, _rob_uop_15_br_mask_T) \n connect rob_uop[15].br_mask, _rob_uop_15_br_mask_T_1 \n node _T_94 = and(io.brupdate.b1.mispredict_mask, rob_uop[16].br_mask) \n node _T_95 = neq(_T_94, UInt<1>(0h0)) \n when _T_95 : \n connect rob_val[16], UInt<1>(0h0) \n connect rob_uop[16].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[16] : \n node _rob_uop_16_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_16_br_mask_T_1 = and(rob_uop[16].br_mask, _rob_uop_16_br_mask_T) \n connect rob_uop[16].br_mask, _rob_uop_16_br_mask_T_1 \n node _T_96 = and(io.brupdate.b1.mispredict_mask, rob_uop[17].br_mask) \n node _T_97 = neq(_T_96, UInt<1>(0h0)) \n when _T_97 : \n connect rob_val[17], UInt<1>(0h0) \n connect rob_uop[17].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[17] : \n node _rob_uop_17_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_17_br_mask_T_1 = and(rob_uop[17].br_mask, _rob_uop_17_br_mask_T) \n connect rob_uop[17].br_mask, _rob_uop_17_br_mask_T_1 \n node _T_98 = and(io.brupdate.b1.mispredict_mask, rob_uop[18].br_mask) \n node _T_99 = neq(_T_98, UInt<1>(0h0)) \n when _T_99 : \n connect rob_val[18], UInt<1>(0h0) \n connect rob_uop[18].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[18] : \n node _rob_uop_18_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_18_br_mask_T_1 = and(rob_uop[18].br_mask, _rob_uop_18_br_mask_T) \n connect rob_uop[18].br_mask, _rob_uop_18_br_mask_T_1 \n node _T_100 = and(io.brupdate.b1.mispredict_mask, rob_uop[19].br_mask) \n node _T_101 = neq(_T_100, UInt<1>(0h0)) \n when _T_101 : \n connect rob_val[19], UInt<1>(0h0) \n connect rob_uop[19].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[19] : \n node _rob_uop_19_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_19_br_mask_T_1 = and(rob_uop[19].br_mask, _rob_uop_19_br_mask_T) \n connect rob_uop[19].br_mask, _rob_uop_19_br_mask_T_1 \n node _T_102 = and(io.brupdate.b1.mispredict_mask, rob_uop[20].br_mask) \n node _T_103 = neq(_T_102, UInt<1>(0h0)) \n when _T_103 : \n connect rob_val[20], UInt<1>(0h0) \n connect rob_uop[20].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[20] : \n node _rob_uop_20_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_20_br_mask_T_1 = and(rob_uop[20].br_mask, _rob_uop_20_br_mask_T) \n connect rob_uop[20].br_mask, _rob_uop_20_br_mask_T_1 \n node _T_104 = and(io.brupdate.b1.mispredict_mask, rob_uop[21].br_mask) \n node _T_105 = neq(_T_104, UInt<1>(0h0)) \n when _T_105 : \n connect rob_val[21], UInt<1>(0h0) \n connect rob_uop[21].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[21] : \n node _rob_uop_21_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_21_br_mask_T_1 = and(rob_uop[21].br_mask, _rob_uop_21_br_mask_T) \n connect rob_uop[21].br_mask, _rob_uop_21_br_mask_T_1 \n node _T_106 = and(io.brupdate.b1.mispredict_mask, rob_uop[22].br_mask) \n node _T_107 = neq(_T_106, UInt<1>(0h0)) \n when _T_107 : \n connect rob_val[22], UInt<1>(0h0) \n connect rob_uop[22].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[22] : \n node _rob_uop_22_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_22_br_mask_T_1 = and(rob_uop[22].br_mask, _rob_uop_22_br_mask_T) \n connect rob_uop[22].br_mask, _rob_uop_22_br_mask_T_1 \n node _T_108 = and(io.brupdate.b1.mispredict_mask, rob_uop[23].br_mask) \n node _T_109 = neq(_T_108, UInt<1>(0h0)) \n when _T_109 : \n connect rob_val[23], UInt<1>(0h0) \n connect rob_uop[23].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[23] : \n node _rob_uop_23_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_23_br_mask_T_1 = and(rob_uop[23].br_mask, _rob_uop_23_br_mask_T) \n connect rob_uop[23].br_mask, _rob_uop_23_br_mask_T_1 \n node _T_110 = and(io.brupdate.b1.mispredict_mask, rob_uop[24].br_mask) \n node _T_111 = neq(_T_110, UInt<1>(0h0)) \n when _T_111 : \n connect rob_val[24], UInt<1>(0h0) \n connect rob_uop[24].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[24] : \n node _rob_uop_24_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_24_br_mask_T_1 = and(rob_uop[24].br_mask, _rob_uop_24_br_mask_T) \n connect rob_uop[24].br_mask, _rob_uop_24_br_mask_T_1 \n node _T_112 = and(io.brupdate.b1.mispredict_mask, rob_uop[25].br_mask) \n node _T_113 = neq(_T_112, UInt<1>(0h0)) \n when _T_113 : \n connect rob_val[25], UInt<1>(0h0) \n connect rob_uop[25].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[25] : \n node _rob_uop_25_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_25_br_mask_T_1 = and(rob_uop[25].br_mask, _rob_uop_25_br_mask_T) \n connect rob_uop[25].br_mask, _rob_uop_25_br_mask_T_1 \n node _T_114 = and(io.brupdate.b1.mispredict_mask, rob_uop[26].br_mask) \n node _T_115 = neq(_T_114, UInt<1>(0h0)) \n when _T_115 : \n connect rob_val[26], UInt<1>(0h0) \n connect rob_uop[26].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[26] : \n node _rob_uop_26_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_26_br_mask_T_1 = and(rob_uop[26].br_mask, _rob_uop_26_br_mask_T) \n connect rob_uop[26].br_mask, _rob_uop_26_br_mask_T_1 \n node _T_116 = and(io.brupdate.b1.mispredict_mask, rob_uop[27].br_mask) \n node _T_117 = neq(_T_116, UInt<1>(0h0)) \n when _T_117 : \n connect rob_val[27], UInt<1>(0h0) \n connect rob_uop[27].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[27] : \n node _rob_uop_27_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_27_br_mask_T_1 = and(rob_uop[27].br_mask, _rob_uop_27_br_mask_T) \n connect rob_uop[27].br_mask, _rob_uop_27_br_mask_T_1 \n node _T_118 = and(io.brupdate.b1.mispredict_mask, rob_uop[28].br_mask) \n node _T_119 = neq(_T_118, UInt<1>(0h0)) \n when _T_119 : \n connect rob_val[28], UInt<1>(0h0) \n connect rob_uop[28].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[28] : \n node _rob_uop_28_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_28_br_mask_T_1 = and(rob_uop[28].br_mask, _rob_uop_28_br_mask_T) \n connect rob_uop[28].br_mask, _rob_uop_28_br_mask_T_1 \n node _T_120 = and(io.brupdate.b1.mispredict_mask, rob_uop[29].br_mask) \n node _T_121 = neq(_T_120, UInt<1>(0h0)) \n when _T_121 : \n connect rob_val[29], UInt<1>(0h0) \n connect rob_uop[29].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[29] : \n node _rob_uop_29_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_29_br_mask_T_1 = and(rob_uop[29].br_mask, _rob_uop_29_br_mask_T) \n connect rob_uop[29].br_mask, _rob_uop_29_br_mask_T_1 \n node _T_122 = and(io.brupdate.b1.mispredict_mask, rob_uop[30].br_mask) \n node _T_123 = neq(_T_122, UInt<1>(0h0)) \n when _T_123 : \n connect rob_val[30], UInt<1>(0h0) \n connect rob_uop[30].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[30] : \n node _rob_uop_30_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_30_br_mask_T_1 = and(rob_uop[30].br_mask, _rob_uop_30_br_mask_T) \n connect rob_uop[30].br_mask, _rob_uop_30_br_mask_T_1 \n node _T_124 = and(io.brupdate.b1.mispredict_mask, rob_uop[31].br_mask) \n node _T_125 = neq(_T_124, UInt<1>(0h0)) \n when _T_125 : \n connect rob_val[31], UInt<1>(0h0) \n connect rob_uop[31].debug_inst, UInt<32>(0h4033) \n else :\n\n when rob_val[31] : \n node _rob_uop_31_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _rob_uop_31_br_mask_T_1 = and(rob_uop[31].br_mask, _rob_uop_31_br_mask_T) \n connect rob_uop[31].br_mask, _rob_uop_31_br_mask_T_1 \n node _T_126 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_127 = and(io.brupdate.b2.mispredict, _T_126) \n when _T_127 : \n connect rob_uop[io.brupdate.b2.uop.rob_idx].debug_fsrc, UInt<2>(0h3) \n connect rob_uop[io.brupdate.b2.uop.rob_idx].taken, io.brupdate.b2.taken \n when will_commit[0] : \n connect rob_val[rob_head], UInt<1>(0h0) \n connect rob_head_vals[0], rob_val[rob_head] \n connect rob_tail_vals[0], rob_val[rob_tail] \n connect rob_head_fflags[0], rob_fflags_0[rob_head] \n connect rob_head_uses_stq[0], rob_uop[rob_head].uses_stq \n connect rob_head_uses_ldq[0], rob_uop[rob_head].uses_ldq \n node _rob_unsafe_masked_0_T = or(rob_unsafe[0], rob_exception[0]) \n node _rob_unsafe_masked_0_T_1 = and(rob_val[0], _rob_unsafe_masked_0_T) \n connect rob_unsafe_masked[0], _rob_unsafe_masked_0_T_1 \n node _rob_unsafe_masked_1_T = or(rob_unsafe[1], rob_exception[1]) \n node _rob_unsafe_masked_1_T_1 = and(rob_val[1], _rob_unsafe_masked_1_T) \n connect rob_unsafe_masked[1], _rob_unsafe_masked_1_T_1 \n node _rob_unsafe_masked_2_T = or(rob_unsafe[2], rob_exception[2]) \n node _rob_unsafe_masked_2_T_1 = and(rob_val[2], _rob_unsafe_masked_2_T) \n connect rob_unsafe_masked[2], _rob_unsafe_masked_2_T_1 \n node _rob_unsafe_masked_3_T = or(rob_unsafe[3], rob_exception[3]) \n node _rob_unsafe_masked_3_T_1 = and(rob_val[3], _rob_unsafe_masked_3_T) \n connect rob_unsafe_masked[3], _rob_unsafe_masked_3_T_1 \n node _rob_unsafe_masked_4_T = or(rob_unsafe[4], rob_exception[4]) \n node _rob_unsafe_masked_4_T_1 = and(rob_val[4], _rob_unsafe_masked_4_T) \n connect rob_unsafe_masked[4], _rob_unsafe_masked_4_T_1 \n node _rob_unsafe_masked_5_T = or(rob_unsafe[5], rob_exception[5]) \n node _rob_unsafe_masked_5_T_1 = and(rob_val[5], _rob_unsafe_masked_5_T) \n connect rob_unsafe_masked[5], _rob_unsafe_masked_5_T_1 \n node _rob_unsafe_masked_6_T = or(rob_unsafe[6], rob_exception[6]) \n node _rob_unsafe_masked_6_T_1 = and(rob_val[6], _rob_unsafe_masked_6_T) \n connect rob_unsafe_masked[6], _rob_unsafe_masked_6_T_1 \n node _rob_unsafe_masked_7_T = or(rob_unsafe[7], rob_exception[7]) \n node _rob_unsafe_masked_7_T_1 = and(rob_val[7], _rob_unsafe_masked_7_T) \n connect rob_unsafe_masked[7], _rob_unsafe_masked_7_T_1 \n node _rob_unsafe_masked_8_T = or(rob_unsafe[8], rob_exception[8]) \n node _rob_unsafe_masked_8_T_1 = and(rob_val[8], _rob_unsafe_masked_8_T) \n connect rob_unsafe_masked[8], _rob_unsafe_masked_8_T_1 \n node _rob_unsafe_masked_9_T = or(rob_unsafe[9], rob_exception[9]) \n node _rob_unsafe_masked_9_T_1 = and(rob_val[9], _rob_unsafe_masked_9_T) \n connect rob_unsafe_masked[9], _rob_unsafe_masked_9_T_1 \n node _rob_unsafe_masked_10_T = or(rob_unsafe[10], rob_exception[10]) \n node _rob_unsafe_masked_10_T_1 = and(rob_val[10], _rob_unsafe_masked_10_T) \n connect rob_unsafe_masked[10], _rob_unsafe_masked_10_T_1 \n node _rob_unsafe_masked_11_T = or(rob_unsafe[11], rob_exception[11]) \n node _rob_unsafe_masked_11_T_1 = and(rob_val[11], _rob_unsafe_masked_11_T) \n connect rob_unsafe_masked[11], _rob_unsafe_masked_11_T_1 \n node _rob_unsafe_masked_12_T = or(rob_unsafe[12], rob_exception[12]) \n node _rob_unsafe_masked_12_T_1 = and(rob_val[12], _rob_unsafe_masked_12_T) \n connect rob_unsafe_masked[12], _rob_unsafe_masked_12_T_1 \n node _rob_unsafe_masked_13_T = or(rob_unsafe[13], rob_exception[13]) \n node _rob_unsafe_masked_13_T_1 = and(rob_val[13], _rob_unsafe_masked_13_T) \n connect rob_unsafe_masked[13], _rob_unsafe_masked_13_T_1 \n node _rob_unsafe_masked_14_T = or(rob_unsafe[14], rob_exception[14]) \n node _rob_unsafe_masked_14_T_1 = and(rob_val[14], _rob_unsafe_masked_14_T) \n connect rob_unsafe_masked[14], _rob_unsafe_masked_14_T_1 \n node _rob_unsafe_masked_15_T = or(rob_unsafe[15], rob_exception[15]) \n node _rob_unsafe_masked_15_T_1 = and(rob_val[15], _rob_unsafe_masked_15_T) \n connect rob_unsafe_masked[15], _rob_unsafe_masked_15_T_1 \n node _rob_unsafe_masked_16_T = or(rob_unsafe[16], rob_exception[16]) \n node _rob_unsafe_masked_16_T_1 = and(rob_val[16], _rob_unsafe_masked_16_T) \n connect rob_unsafe_masked[16], _rob_unsafe_masked_16_T_1 \n node _rob_unsafe_masked_17_T = or(rob_unsafe[17], rob_exception[17]) \n node _rob_unsafe_masked_17_T_1 = and(rob_val[17], _rob_unsafe_masked_17_T) \n connect rob_unsafe_masked[17], _rob_unsafe_masked_17_T_1 \n node _rob_unsafe_masked_18_T = or(rob_unsafe[18], rob_exception[18]) \n node _rob_unsafe_masked_18_T_1 = and(rob_val[18], _rob_unsafe_masked_18_T) \n connect rob_unsafe_masked[18], _rob_unsafe_masked_18_T_1 \n node _rob_unsafe_masked_19_T = or(rob_unsafe[19], rob_exception[19]) \n node _rob_unsafe_masked_19_T_1 = and(rob_val[19], _rob_unsafe_masked_19_T) \n connect rob_unsafe_masked[19], _rob_unsafe_masked_19_T_1 \n node _rob_unsafe_masked_20_T = or(rob_unsafe[20], rob_exception[20]) \n node _rob_unsafe_masked_20_T_1 = and(rob_val[20], _rob_unsafe_masked_20_T) \n connect rob_unsafe_masked[20], _rob_unsafe_masked_20_T_1 \n node _rob_unsafe_masked_21_T = or(rob_unsafe[21], rob_exception[21]) \n node _rob_unsafe_masked_21_T_1 = and(rob_val[21], _rob_unsafe_masked_21_T) \n connect rob_unsafe_masked[21], _rob_unsafe_masked_21_T_1 \n node _rob_unsafe_masked_22_T = or(rob_unsafe[22], rob_exception[22]) \n node _rob_unsafe_masked_22_T_1 = and(rob_val[22], _rob_unsafe_masked_22_T) \n connect rob_unsafe_masked[22], _rob_unsafe_masked_22_T_1 \n node _rob_unsafe_masked_23_T = or(rob_unsafe[23], rob_exception[23]) \n node _rob_unsafe_masked_23_T_1 = and(rob_val[23], _rob_unsafe_masked_23_T) \n connect rob_unsafe_masked[23], _rob_unsafe_masked_23_T_1 \n node _rob_unsafe_masked_24_T = or(rob_unsafe[24], rob_exception[24]) \n node _rob_unsafe_masked_24_T_1 = and(rob_val[24], _rob_unsafe_masked_24_T) \n connect rob_unsafe_masked[24], _rob_unsafe_masked_24_T_1 \n node _rob_unsafe_masked_25_T = or(rob_unsafe[25], rob_exception[25]) \n node _rob_unsafe_masked_25_T_1 = and(rob_val[25], _rob_unsafe_masked_25_T) \n connect rob_unsafe_masked[25], _rob_unsafe_masked_25_T_1 \n node _rob_unsafe_masked_26_T = or(rob_unsafe[26], rob_exception[26]) \n node _rob_unsafe_masked_26_T_1 = and(rob_val[26], _rob_unsafe_masked_26_T) \n connect rob_unsafe_masked[26], _rob_unsafe_masked_26_T_1 \n node _rob_unsafe_masked_27_T = or(rob_unsafe[27], rob_exception[27]) \n node _rob_unsafe_masked_27_T_1 = and(rob_val[27], _rob_unsafe_masked_27_T) \n connect rob_unsafe_masked[27], _rob_unsafe_masked_27_T_1 \n node _rob_unsafe_masked_28_T = or(rob_unsafe[28], rob_exception[28]) \n node _rob_unsafe_masked_28_T_1 = and(rob_val[28], _rob_unsafe_masked_28_T) \n connect rob_unsafe_masked[28], _rob_unsafe_masked_28_T_1 \n node _rob_unsafe_masked_29_T = or(rob_unsafe[29], rob_exception[29]) \n node _rob_unsafe_masked_29_T_1 = and(rob_val[29], _rob_unsafe_masked_29_T) \n connect rob_unsafe_masked[29], _rob_unsafe_masked_29_T_1 \n node _rob_unsafe_masked_30_T = or(rob_unsafe[30], rob_exception[30]) \n node _rob_unsafe_masked_30_T_1 = and(rob_val[30], _rob_unsafe_masked_30_T) \n connect rob_unsafe_masked[30], _rob_unsafe_masked_30_T_1 \n node _rob_unsafe_masked_31_T = or(rob_unsafe[31], rob_exception[31]) \n node _rob_unsafe_masked_31_T_1 = and(rob_val[31], _rob_unsafe_masked_31_T) \n connect rob_unsafe_masked[31], _rob_unsafe_masked_31_T_1 \n node _rob_pnr_unsafe_0_T = or(rob_unsafe[rob_pnr], rob_exception[rob_pnr]) \n node _rob_pnr_unsafe_0_T_1 = and(rob_val[rob_pnr], _rob_pnr_unsafe_0_T) \n connect rob_pnr_unsafe[0], _rob_pnr_unsafe_0_T_1 \n when will_commit[0] : \n connect rob_uop[rob_head].debug_inst, UInt<32>(0h4033) \n else :\n\n when rbk_row : \n connect rob_uop[rob_tail].debug_inst, UInt<32>(0h4033) \n node _T_128 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_129 = and(io.debug_wb_valids[0], _T_128) \n when _T_129 : \n infer mport MPORT_1 = rob_debug_wdata[io.wb_resps[0].bits.uop.rob_idx], clock \n connect MPORT_1, io.debug_wb_wdata[0] \n node _T_130 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_131 = and(io.wb_resps[0].valid, _T_130) \n node _T_132 = eq(rob_val[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_133 = and(_T_131, _T_132) \n node _T_134 = eq(_T_133, UInt<1>(0h0)) \n node _T_135 = asUInt(reset) \n node _T_136 = eq(_T_135, UInt<1>(0h0)) \n when _T_136 : \n node _T_137 = eq(_T_134, UInt<1>(0h0)) \n when _T_137 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (0) occurred to an invalid ROB entry.\\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_8 \n assert(clock, _T_134, UInt<1>(0h1), \"\") : assert_8 \n node _T_138 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_139 = and(io.wb_resps[0].valid, _T_138) \n node _T_140 = eq(rob_bsy[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_141 = and(_T_139, _T_140) \n node _T_142 = eq(_T_141, UInt<1>(0h0)) \n node _T_143 = asUInt(reset) \n node _T_144 = eq(_T_143, UInt<1>(0h0)) \n when _T_144 : \n node _T_145 = eq(_T_142, UInt<1>(0h0)) \n when _T_145 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (0) occurred to a not-busy ROB entry.\\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_9 \n assert(clock, _T_142, UInt<1>(0h1), \"\") : assert_9 \n node _T_146 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_147 = and(io.wb_resps[0].valid, _T_146) \n node _T_148 = and(_T_147, rob_uop[io.wb_resps[0].bits.uop.rob_idx].ldst_val) \n node _T_149 = neq(rob_uop[io.wb_resps[0].bits.uop.rob_idx].pdst, io.wb_resps[0].bits.uop.pdst) \n node _T_150 = and(_T_148, _T_149) \n node _T_151 = eq(_T_150, UInt<1>(0h0)) \n node _T_152 = asUInt(reset) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n when _T_153 : \n node _T_154 = eq(_T_151, UInt<1>(0h0)) \n when _T_154 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (0) occurred to the wrong pdst.\\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_10 \n assert(clock, _T_151, UInt<1>(0h1), \"\") : assert_10 \n node _T_155 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_156 = and(io.debug_wb_valids[1], _T_155) \n when _T_156 : \n infer mport MPORT_2 = rob_debug_wdata[io.wb_resps[1].bits.uop.rob_idx], clock \n connect MPORT_2, io.debug_wb_wdata[1] \n node _T_157 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_158 = and(io.wb_resps[1].valid, _T_157) \n node _T_159 = eq(rob_val[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_160 = and(_T_158, _T_159) \n node _T_161 = eq(_T_160, UInt<1>(0h0)) \n node _T_162 = asUInt(reset) \n node _T_163 = eq(_T_162, UInt<1>(0h0)) \n when _T_163 : \n node _T_164 = eq(_T_161, UInt<1>(0h0)) \n when _T_164 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (1) occurred to an invalid ROB entry.\\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_11 \n assert(clock, _T_161, UInt<1>(0h1), \"\") : assert_11 \n node _T_165 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_166 = and(io.wb_resps[1].valid, _T_165) \n node _T_167 = eq(rob_bsy[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_168 = and(_T_166, _T_167) \n node _T_169 = eq(_T_168, UInt<1>(0h0)) \n node _T_170 = asUInt(reset) \n node _T_171 = eq(_T_170, UInt<1>(0h0)) \n when _T_171 : \n node _T_172 = eq(_T_169, UInt<1>(0h0)) \n when _T_172 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (1) occurred to a not-busy ROB entry.\\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_12 \n assert(clock, _T_169, UInt<1>(0h1), \"\") : assert_12 \n node _T_173 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_174 = and(io.wb_resps[1].valid, _T_173) \n node _T_175 = and(_T_174, rob_uop[io.wb_resps[1].bits.uop.rob_idx].ldst_val) \n node _T_176 = neq(rob_uop[io.wb_resps[1].bits.uop.rob_idx].pdst, io.wb_resps[1].bits.uop.pdst) \n node _T_177 = and(_T_175, _T_176) \n node _T_178 = eq(_T_177, UInt<1>(0h0)) \n node _T_179 = asUInt(reset) \n node _T_180 = eq(_T_179, UInt<1>(0h0)) \n when _T_180 : \n node _T_181 = eq(_T_178, UInt<1>(0h0)) \n when _T_181 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (1) occurred to the wrong pdst.\\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_13 \n assert(clock, _T_178, UInt<1>(0h1), \"\") : assert_13 \n node _T_182 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_183 = and(io.debug_wb_valids[2], _T_182) \n when _T_183 : \n infer mport MPORT_3 = rob_debug_wdata[io.wb_resps[2].bits.uop.rob_idx], clock \n connect MPORT_3, io.debug_wb_wdata[2] \n node _T_184 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_185 = and(io.wb_resps[2].valid, _T_184) \n node _T_186 = eq(rob_val[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_187 = and(_T_185, _T_186) \n node _T_188 = eq(_T_187, UInt<1>(0h0)) \n node _T_189 = asUInt(reset) \n node _T_190 = eq(_T_189, UInt<1>(0h0)) \n when _T_190 : \n node _T_191 = eq(_T_188, UInt<1>(0h0)) \n when _T_191 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (2) occurred to an invalid ROB entry.\\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_14 \n assert(clock, _T_188, UInt<1>(0h1), \"\") : assert_14 \n node _T_192 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_193 = and(io.wb_resps[2].valid, _T_192) \n node _T_194 = eq(rob_bsy[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_195 = and(_T_193, _T_194) \n node _T_196 = eq(_T_195, UInt<1>(0h0)) \n node _T_197 = asUInt(reset) \n node _T_198 = eq(_T_197, UInt<1>(0h0)) \n when _T_198 : \n node _T_199 = eq(_T_196, UInt<1>(0h0)) \n when _T_199 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (2) occurred to a not-busy ROB entry.\\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_15 \n assert(clock, _T_196, UInt<1>(0h1), \"\") : assert_15 \n node _T_200 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_201 = and(io.wb_resps[2].valid, _T_200) \n node _T_202 = and(_T_201, rob_uop[io.wb_resps[2].bits.uop.rob_idx].ldst_val) \n node _T_203 = neq(rob_uop[io.wb_resps[2].bits.uop.rob_idx].pdst, io.wb_resps[2].bits.uop.pdst) \n node _T_204 = and(_T_202, _T_203) \n node _T_205 = eq(_T_204, UInt<1>(0h0)) \n node _T_206 = asUInt(reset) \n node _T_207 = eq(_T_206, UInt<1>(0h0)) \n when _T_207 : \n node _T_208 = eq(_T_205, UInt<1>(0h0)) \n when _T_208 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (2) occurred to the wrong pdst.\\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_16 \n assert(clock, _T_205, UInt<1>(0h1), \"\") : assert_16 \n node _T_209 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_210 = and(io.debug_wb_valids[3], _T_209) \n when _T_210 : \n infer mport MPORT_4 = rob_debug_wdata[io.wb_resps[3].bits.uop.rob_idx], clock \n connect MPORT_4, io.debug_wb_wdata[3] \n node _T_211 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_212 = and(io.wb_resps[3].valid, _T_211) \n node _T_213 = eq(rob_val[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_214 = and(_T_212, _T_213) \n node _T_215 = eq(_T_214, UInt<1>(0h0)) \n node _T_216 = asUInt(reset) \n node _T_217 = eq(_T_216, UInt<1>(0h0)) \n when _T_217 : \n node _T_218 = eq(_T_215, UInt<1>(0h0)) \n when _T_218 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (3) occurred to an invalid ROB entry.\\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_17 \n assert(clock, _T_215, UInt<1>(0h1), \"\") : assert_17 \n node _T_219 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_220 = and(io.wb_resps[3].valid, _T_219) \n node _T_221 = eq(rob_bsy[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0)) \n node _T_222 = and(_T_220, _T_221) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n node _T_224 = asUInt(reset) \n node _T_225 = eq(_T_224, UInt<1>(0h0)) \n when _T_225 : \n node _T_226 = eq(_T_223, UInt<1>(0h0)) \n when _T_226 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (3) occurred to a not-busy ROB entry.\\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_18 \n assert(clock, _T_223, UInt<1>(0h1), \"\") : assert_18 \n node _T_227 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_228 = and(io.wb_resps[3].valid, _T_227) \n node _T_229 = and(_T_228, rob_uop[io.wb_resps[3].bits.uop.rob_idx].ldst_val) \n node _T_230 = neq(rob_uop[io.wb_resps[3].bits.uop.rob_idx].pdst, io.wb_resps[3].bits.uop.pdst) \n node _T_231 = and(_T_229, _T_230) \n node _T_232 = eq(_T_231, UInt<1>(0h0)) \n node _T_233 = asUInt(reset) \n node _T_234 = eq(_T_233, UInt<1>(0h0)) \n when _T_234 : \n node _T_235 = eq(_T_232, UInt<1>(0h0)) \n when _T_235 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] writeback (3) occurred to the wrong pdst.\\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\\n\") : printf_19 \n assert(clock, _T_232, UInt<1>(0h1), \"\") : assert_19 \n infer mport io_commit_debug_wdata_0_MPORT = rob_debug_wdata[rob_head], clock \n connect io.commit.debug_wdata[0], io_commit_debug_wdata_0_MPORT \n node _block_commit_T = neq(rob_state, UInt<2>(0h1)) \n node _block_commit_T_1 = neq(rob_state, UInt<2>(0h3)) \n node _block_commit_T_2 = and(_block_commit_T, _block_commit_T_1) \n reg block_commit_REG : UInt<1>, clock \n connect block_commit_REG, exception_thrown \n node _block_commit_T_3 = or(_block_commit_T_2, block_commit_REG) \n reg block_commit_REG_1 : UInt<1>, clock \n connect block_commit_REG_1, exception_thrown \n reg block_commit_REG_2 : UInt<1>, clock \n connect block_commit_REG_2, block_commit_REG_1 \n node block_commit = or(_block_commit_T_3, block_commit_REG_2) \n node _T_236 = eq(block_commit, UInt<1>(0h0)) \n node _T_237 = and(can_throw_exception[0], _T_236) \n node _T_238 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_239 = and(_T_237, _T_238) \n node _T_240 = or(_T_239, UInt<1>(0h0)) \n node _will_commit_0_T = eq(can_throw_exception[0], UInt<1>(0h0)) \n node _will_commit_0_T_1 = and(can_commit[0], _will_commit_0_T) \n node _will_commit_0_T_2 = eq(block_commit, UInt<1>(0h0)) \n node _will_commit_0_T_3 = and(_will_commit_0_T_1, _will_commit_0_T_2) \n connect will_commit[0], _will_commit_0_T_3 \n node _T_241 = eq(can_commit[0], UInt<1>(0h0)) \n node _T_242 = or(_T_241, can_throw_exception[0]) \n node _T_243 = and(rob_head_vals[0], _T_242) \n node _T_244 = or(_T_243, block_commit) \n connect exception_thrown, _T_240 \n node _is_mini_exception_T = eq(io.com_xcpt.bits.cause, UInt<5>(0h10)) \n node _is_mini_exception_T_1 = eq(io.com_xcpt.bits.cause, UInt<5>(0h11)) \n node is_mini_exception = or(_is_mini_exception_T, _is_mini_exception_T_1) \n node _io_com_xcpt_valid_T = eq(is_mini_exception, UInt<1>(0h0)) \n node _io_com_xcpt_valid_T_1 = and(exception_thrown, _io_com_xcpt_valid_T) \n connect io.com_xcpt.valid, _io_com_xcpt_valid_T_1 \n invalidate io.com_xcpt.bits.flush_typ \n invalidate io.com_xcpt.bits.badvaddr \n invalidate io.com_xcpt.bits.cause \n invalidate io.com_xcpt.bits.pc_lob \n invalidate io.com_xcpt.bits.is_rvc \n invalidate io.com_xcpt.bits.edge_inst \n invalidate io.com_xcpt.bits.ftq_idx \n connect io.com_xcpt.bits.cause, r_xcpt_uop.exc_cause \n node _io_com_xcpt_bits_badvaddr_T = bits(r_xcpt_badvaddr, 39, 39) \n node _io_com_xcpt_bits_badvaddr_T_1 = mux(_io_com_xcpt_bits_badvaddr_T, UInt<24>(0hffffff), UInt<24>(0h0)) \n node _io_com_xcpt_bits_badvaddr_T_2 = cat(_io_com_xcpt_bits_badvaddr_T_1, r_xcpt_badvaddr) \n connect io.com_xcpt.bits.badvaddr, _io_com_xcpt_bits_badvaddr_T_2 \n node insn_sys_pc2epc = and(rob_head_vals[0], io.commit.uops[0].is_sys_pc2epc) \n node refetch_inst = or(exception_thrown, insn_sys_pc2epc) \n connect io.com_xcpt.bits.ftq_idx, io.commit.uops[0].ftq_idx \n connect io.com_xcpt.bits.edge_inst, io.commit.uops[0].edge_inst \n connect io.com_xcpt.bits.is_rvc, io.commit.uops[0].is_rvc \n connect io.com_xcpt.bits.pc_lob, io.commit.uops[0].pc_lob \n node flush_commit_mask_0 = and(io.commit.valids[0], io.commit.uops[0].flush_on_commit) \n node flush_val = or(exception_thrown, flush_commit_mask_0) \n node _T_245 = gt(flush_commit_mask_0, UInt<1>(0h1)) \n node _T_246 = eq(_T_245, UInt<1>(0h0)) \n node _T_247 = asUInt(reset) \n node _T_248 = eq(_T_247, UInt<1>(0h0)) \n when _T_248 : \n node _T_249 = eq(_T_246, UInt<1>(0h0)) \n when _T_249 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [rob] Can't commit multiple flush_on_commit instructions on one cycle\\n at rob.scala:580 assert(!(PopCount(flush_commit_mask) > 1.U),\\n\") : printf_20 \n assert(clock, _T_246, UInt<1>(0h1), \"\") : assert_20 \n node flush_uop = mux(exception_thrown, io.commit.uops[0], io.commit.uops[0]) \n connect io.flush.valid, flush_val \n invalidate io.flush.bits.flush_typ \n invalidate io.flush.bits.badvaddr \n invalidate io.flush.bits.cause \n invalidate io.flush.bits.pc_lob \n invalidate io.flush.bits.is_rvc \n invalidate io.flush.bits.edge_inst \n invalidate io.flush.bits.ftq_idx \n connect io.flush.bits.ftq_idx, flush_uop.ftq_idx \n connect io.flush.bits.pc_lob, flush_uop.pc_lob \n connect io.flush.bits.edge_inst, flush_uop.edge_inst \n connect io.flush.bits.is_rvc, flush_uop.is_rvc \n node _io_flush_bits_flush_typ_T = eq(is_mini_exception, UInt<1>(0h0)) \n node _io_flush_bits_flush_typ_T_1 = and(exception_thrown, _io_flush_bits_flush_typ_T) \n node _io_flush_bits_flush_typ_T_2 = eq(flush_uop.uopc, UInt<7>(0h6a)) \n node _io_flush_bits_flush_typ_T_3 = and(flush_commit_mask_0, _io_flush_bits_flush_typ_T_2) \n node _io_flush_bits_flush_typ_ret_T = eq(flush_val, UInt<1>(0h0)) \n node _io_flush_bits_flush_typ_ret_T_1 = mux(refetch_inst, UInt<2>(0h2), UInt<3>(0h4)) \n node _io_flush_bits_flush_typ_ret_T_2 = mux(_io_flush_bits_flush_typ_T_1, UInt<1>(0h1), _io_flush_bits_flush_typ_ret_T_1) \n node _io_flush_bits_flush_typ_ret_T_3 = mux(_io_flush_bits_flush_typ_T_3, UInt<2>(0h3), _io_flush_bits_flush_typ_ret_T_2) \n node io_flush_bits_flush_typ_ret = mux(_io_flush_bits_flush_typ_ret_T, UInt<1>(0h0), _io_flush_bits_flush_typ_ret_T_3) \n connect io.flush.bits.flush_typ, io_flush_bits_flush_typ_ret \n wire fflags_val : UInt<1>[1] \n wire fflags : UInt<5>[1] \n node _fflags_val_0_T = and(io.commit.valids[0], io.commit.uops[0].fp_val) \n node _fflags_val_0_T_1 = eq(io.commit.uops[0].uses_stq, UInt<1>(0h0)) \n node _fflags_val_0_T_2 = and(_fflags_val_0_T, _fflags_val_0_T_1) \n connect fflags_val[0], _fflags_val_0_T_2 \n node _fflags_0_T = mux(fflags_val[0], rob_head_fflags[0], UInt<1>(0h0)) \n connect fflags[0], _fflags_0_T \n node _T_250 = eq(io.commit.uops[0].fp_val, UInt<1>(0h0)) \n node _T_251 = and(io.commit.valids[0], _T_250) \n node _T_252 = neq(rob_head_fflags[0], UInt<1>(0h0)) \n node _T_253 = and(_T_251, _T_252) \n node _T_254 = eq(_T_253, UInt<1>(0h0)) \n node _T_255 = asUInt(reset) \n node _T_256 = eq(_T_255, UInt<1>(0h0)) \n when _T_256 : \n node _T_257 = eq(_T_254, UInt<1>(0h0)) \n when _T_257 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Committed non-FP instruction has non-zero fflag bits.\\n at rob.scala:613 assert (!(io.commit.valids(w) &&\\n\") : printf_21 \n assert(clock, _T_254, UInt<1>(0h1), \"\") : assert_21 \n node _T_258 = and(io.commit.valids[0], io.commit.uops[0].fp_val) \n node _T_259 = or(io.commit.uops[0].uses_ldq, io.commit.uops[0].uses_stq) \n node _T_260 = and(_T_258, _T_259) \n node _T_261 = neq(rob_head_fflags[0], UInt<1>(0h0)) \n node _T_262 = and(_T_260, _T_261) \n node _T_263 = eq(_T_262, UInt<1>(0h0)) \n node _T_264 = asUInt(reset) \n node _T_265 = eq(_T_264, UInt<1>(0h0)) \n when _T_265 : \n node _T_266 = eq(_T_263, UInt<1>(0h0)) \n when _T_266 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Committed FP load or store has non-zero fflag bits.\\n at rob.scala:617 assert (!(io.commit.valids(w) &&\\n\") : printf_22 \n assert(clock, _T_263, UInt<1>(0h1), \"\") : assert_22 \n connect io.commit.fflags.valid, fflags_val[0] \n connect io.commit.fflags.bits, fflags[0] \n wire next_xcpt_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} \n connect next_xcpt_uop, r_xcpt_uop \n wire enq_xcpts : UInt<1>[1] \n node _enq_xcpts_0_T = and(io.enq_valids[0], io.enq_uops[0].exception) \n connect enq_xcpts[0], _enq_xcpts_0_T \n node _T_267 = or(io.flush.valid, exception_thrown) \n node _T_268 = eq(_T_267, UInt<1>(0h0)) \n node _T_269 = neq(rob_state, UInt<2>(0h2)) \n node _T_270 = and(_T_268, _T_269) \n when _T_270 : \n node new_xcpt_valid = or(io.lxcpt.valid, io.csr_replay.valid) \n node _lxcpt_older_T = eq(io.csr_replay.valid, UInt<1>(0h0)) \n node _lxcpt_older_T_1 = lt(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx) \n node _lxcpt_older_T_2 = lt(io.lxcpt.bits.uop.rob_idx, rob_head) \n node _lxcpt_older_T_3 = xor(_lxcpt_older_T_1, _lxcpt_older_T_2) \n node _lxcpt_older_T_4 = lt(io.csr_replay.bits.uop.rob_idx, rob_head) \n node _lxcpt_older_T_5 = xor(_lxcpt_older_T_3, _lxcpt_older_T_4) \n node _lxcpt_older_T_6 = and(_lxcpt_older_T_5, io.lxcpt.valid) \n node lxcpt_older = or(_lxcpt_older_T, _lxcpt_older_T_6) \n node new_xcpt = mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits) \n when new_xcpt_valid : \n node _T_271 = eq(r_xcpt_val, UInt<1>(0h0)) \n node _T_272 = lt(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx) \n node _T_273 = lt(new_xcpt.uop.rob_idx, rob_head) \n node _T_274 = xor(_T_272, _T_273) \n node _T_275 = lt(r_xcpt_uop.rob_idx, rob_head) \n node _T_276 = xor(_T_274, _T_275) \n node _T_277 = or(_T_271, _T_276) \n when _T_277 : \n connect r_xcpt_val, UInt<1>(0h1) \n connect next_xcpt_uop, new_xcpt.uop \n connect next_xcpt_uop.exc_cause, new_xcpt.cause \n connect r_xcpt_badvaddr, new_xcpt.badvaddr \n else :\n\n node _T_278 = eq(r_xcpt_val, UInt<1>(0h0)) \n node _T_279 = and(_T_278, enq_xcpts[0]) \n when _T_279 : \n connect r_xcpt_val, UInt<1>(0h1) \n connect next_xcpt_uop, io.enq_uops[0] \n node _r_xcpt_badvaddr_T = not(io.xcpt_fetch_pc) \n node _r_xcpt_badvaddr_T_1 = or(_r_xcpt_badvaddr_T, UInt<6>(0h3f)) \n node _r_xcpt_badvaddr_T_2 = not(_r_xcpt_badvaddr_T_1) \n node _r_xcpt_badvaddr_T_3 = or(_r_xcpt_badvaddr_T_2, io.enq_uops[0].pc_lob) \n connect r_xcpt_badvaddr, _r_xcpt_badvaddr_T_3 \n connect r_xcpt_uop, next_xcpt_uop \n node _r_xcpt_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) \n node _r_xcpt_uop_br_mask_T_1 = and(next_xcpt_uop.br_mask, _r_xcpt_uop_br_mask_T) \n connect r_xcpt_uop.br_mask, _r_xcpt_uop_br_mask_T_1 \n node _T_280 = and(io.brupdate.b1.mispredict_mask, next_xcpt_uop.br_mask) \n node _T_281 = neq(_T_280, UInt<1>(0h0)) \n node _T_282 = or(io.flush.valid, _T_281) \n when _T_282 : \n connect r_xcpt_val, UInt<1>(0h0) \n node _T_283 = eq(r_xcpt_val, UInt<1>(0h0)) \n node _T_284 = and(exception_thrown, _T_283) \n node _T_285 = eq(_T_284, UInt<1>(0h0)) \n node _T_286 = asUInt(reset) \n node _T_287 = eq(_T_286, UInt<1>(0h0)) \n when _T_287 : \n node _T_288 = eq(_T_285, UInt<1>(0h0)) \n when _T_288 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ROB trying to throw an exception, but it doesn't have a valid xcpt_cause\\n at rob.scala:667 assert (!(exception_thrown && !r_xcpt_val),\\n\") : printf_23 \n assert(clock, _T_285, UInt<1>(0h1), \"\") : assert_23 \n node _T_289 = and(empty, r_xcpt_val) \n node _T_290 = eq(_T_289, UInt<1>(0h0)) \n node _T_291 = asUInt(reset) \n node _T_292 = eq(_T_291, UInt<1>(0h0)) \n when _T_292 : \n node _T_293 = eq(_T_290, UInt<1>(0h0)) \n when _T_293 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ROB is empty, but believes it has an outstanding exception.\\n at rob.scala:670 assert (!(empty && r_xcpt_val),\\n\") : printf_24 \n assert(clock, _T_290, UInt<1>(0h1), \"\") : assert_24 \n node _T_294 = neq(r_xcpt_uop.rob_idx, rob_head) \n node _T_295 = and(_T_240, _T_294) \n node _T_296 = eq(_T_295, UInt<1>(0h0)) \n node _T_297 = asUInt(reset) \n node _T_298 = eq(_T_297, UInt<1>(0h0)) \n when _T_298 : \n node _T_299 = eq(_T_296, UInt<1>(0h0)) \n when _T_299 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ROB is throwing an exception, but the stored exception information's rob_idx does not match the rob_head\\n at rob.scala:673 assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),\\n\") : printf_25 \n assert(clock, _T_296, UInt<1>(0h1), \"\") : assert_25 \n wire rob_deq : UInt<1> \n connect rob_deq, UInt<1>(0h0) \n regreset r_partial_row : UInt<1>, clock, reset, UInt<1>(0h0) \n when io.enq_valids[0] : \n connect r_partial_row, io.enq_partial_stall \n node _finished_committing_row_T = neq(io.commit.valids[0], UInt<1>(0h0)) \n node _finished_committing_row_T_1 = xor(will_commit[0], rob_head_vals[0]) \n node _finished_committing_row_T_2 = eq(_finished_committing_row_T_1, UInt<1>(0h0)) \n node _finished_committing_row_T_3 = and(_finished_committing_row_T, _finished_committing_row_T_2) \n node _finished_committing_row_T_4 = eq(rob_head, rob_tail) \n node _finished_committing_row_T_5 = and(r_partial_row, _finished_committing_row_T_4) \n node _finished_committing_row_T_6 = eq(maybe_full, UInt<1>(0h0)) \n node _finished_committing_row_T_7 = and(_finished_committing_row_T_5, _finished_committing_row_T_6) \n node _finished_committing_row_T_8 = eq(_finished_committing_row_T_7, UInt<1>(0h0)) \n node finished_committing_row = and(_finished_committing_row_T_3, _finished_committing_row_T_8) \n when finished_committing_row : \n node _rob_head_T = add(rob_head, UInt<1>(0h1)) \n node _rob_head_T_1 = tail(_rob_head_T, 1) \n node _rob_head_T_2 = bits(_rob_head_T_1, 4, 0) \n connect rob_head, _rob_head_T_2 \n connect rob_head_lsb, UInt<1>(0h0) \n connect rob_deq, UInt<1>(0h1) \n else :\n\n node _rob_head_lsb_T = bits(rob_head_vals[0], 0, 0) \n node _rob_head_lsb_T_1 = mux(_rob_head_lsb_T, UInt<1>(0h1), UInt<1>(0h0)) \n connect rob_head_lsb, UInt<1>(0h0) \n regreset pnr_maybe_at_tail : UInt<1>, clock, reset, UInt<1>(0h0) \n node _safe_to_inc_T = eq(rob_state, UInt<2>(0h1)) \n node _safe_to_inc_T_1 = eq(rob_state, UInt<2>(0h3)) \n node safe_to_inc = or(_safe_to_inc_T, _safe_to_inc_T_1) \n node _do_inc_row_T = eq(rob_pnr_unsafe[0], UInt<1>(0h0)) \n node _do_inc_row_T_1 = neq(rob_pnr, rob_tail) \n node _do_inc_row_T_2 = eq(pnr_maybe_at_tail, UInt<1>(0h0)) \n node _do_inc_row_T_3 = and(full, _do_inc_row_T_2) \n node _do_inc_row_T_4 = or(_do_inc_row_T_1, _do_inc_row_T_3) \n node do_inc_row = and(_do_inc_row_T, _do_inc_row_T_4) \n node _T_300 = neq(io.enq_valids[0], UInt<1>(0h0)) \n node _T_301 = and(empty, _T_300) \n when _T_301 : \n connect rob_pnr, rob_head \n connect rob_pnr_lsb, UInt<1>(0h0) \n else :\n\n node _T_302 = and(safe_to_inc, do_inc_row) \n when _T_302 : \n node _rob_pnr_T = add(rob_pnr, UInt<1>(0h1)) \n node _rob_pnr_T_1 = tail(_rob_pnr_T, 1) \n node _rob_pnr_T_2 = bits(_rob_pnr_T_1, 4, 0) \n connect rob_pnr, _rob_pnr_T_2 \n connect rob_pnr_lsb, UInt<1>(0h0) \n else :\n\n node _T_303 = neq(rob_pnr, rob_tail) \n node _T_304 = eq(pnr_maybe_at_tail, UInt<1>(0h0)) \n node _T_305 = and(full, _T_304) \n node _T_306 = or(_T_303, _T_305) \n node _T_307 = and(safe_to_inc, _T_306) \n when _T_307 : \n connect rob_pnr_lsb, UInt<1>(0h0) \n else :\n\n node _T_308 = eq(full, UInt<1>(0h0)) \n node _T_309 = and(safe_to_inc, _T_308) \n node _T_310 = eq(empty, UInt<1>(0h0)) \n node _T_311 = and(_T_309, _T_310) \n when _T_311 : \n node _rob_pnr_lsb_T = dshr(rob_tail_vals[0], UInt<1>(0h0)) \n node _rob_pnr_lsb_T_1 = not(_rob_pnr_lsb_T) \n node _rob_pnr_lsb_T_2 = or(rob_pnr_unsafe[0], _rob_pnr_lsb_T_1) \n node _rob_pnr_lsb_T_3 = bits(_rob_pnr_lsb_T_2, 0, 0) \n connect rob_pnr_lsb, UInt<1>(0h0) \n else :\n\n node _T_312 = and(full, pnr_maybe_at_tail) \n when _T_312 : \n connect rob_pnr_lsb, UInt<1>(0h0) \n node _pnr_maybe_at_tail_T = eq(rob_deq, UInt<1>(0h0)) \n node _pnr_maybe_at_tail_T_1 = or(do_inc_row, pnr_maybe_at_tail) \n node _pnr_maybe_at_tail_T_2 = and(_pnr_maybe_at_tail_T, _pnr_maybe_at_tail_T_1) \n connect pnr_maybe_at_tail, _pnr_maybe_at_tail_T_2 \n node _T_313 = lt(rob_pnr, rob_head) \n node _T_314 = lt(rob_pnr, rob_tail) \n node _T_315 = xor(_T_313, _T_314) \n node _T_316 = lt(rob_head, rob_tail) \n node _T_317 = xor(_T_315, _T_316) \n node _T_318 = eq(_T_317, UInt<1>(0h0)) \n node _T_319 = eq(rob_pnr, rob_tail) \n node _T_320 = or(_T_318, _T_319) \n node _T_321 = asUInt(reset) \n node _T_322 = eq(_T_321, UInt<1>(0h0)) \n when _T_322 : \n node _T_323 = eq(_T_320, UInt<1>(0h0)) \n when _T_323 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at rob.scala:749 assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)\\n\") : printf_26 \n assert(clock, _T_320, UInt<1>(0h1), \"\") : assert_26 \n node _T_324 = lt(rob_tail, rob_pnr) \n node _T_325 = lt(rob_tail, rob_head) \n node _T_326 = xor(_T_324, _T_325) \n node _T_327 = lt(rob_pnr, rob_head) \n node _T_328 = xor(_T_326, _T_327) \n node _T_329 = eq(_T_328, UInt<1>(0h0)) \n node _T_330 = or(_T_329, full) \n node _T_331 = asUInt(reset) \n node _T_332 = eq(_T_331, UInt<1>(0h0)) \n when _T_332 : \n node _T_333 = eq(_T_330, UInt<1>(0h0)) \n when _T_333 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at rob.scala:752 assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)\\n\") : printf_27 \n assert(clock, _T_330, UInt<1>(0h1), \"\") : assert_27 \n wire rob_enq : UInt<1> \n connect rob_enq, UInt<1>(0h0) \n node _T_334 = eq(rob_state, UInt<2>(0h2)) \n node _T_335 = neq(rob_tail, rob_head) \n node _T_336 = or(_T_335, maybe_full) \n node _T_337 = and(_T_334, _T_336) \n when _T_337 : \n node _rob_tail_T = sub(rob_tail, UInt<1>(0h1)) \n node _rob_tail_T_1 = tail(_rob_tail_T, 1) \n node _rob_tail_T_2 = bits(_rob_tail_T_1, 4, 0) \n connect rob_tail, _rob_tail_T_2 \n connect rob_tail_lsb, UInt<1>(0h0) \n connect rob_deq, UInt<1>(0h1) \n else :\n\n node _T_338 = eq(rob_state, UInt<2>(0h2)) \n node _T_339 = eq(rob_tail, rob_head) \n node _T_340 = and(_T_338, _T_339) \n node _T_341 = eq(maybe_full, UInt<1>(0h0)) \n node _T_342 = and(_T_340, _T_341) \n when _T_342 : \n connect rob_tail_lsb, rob_head_lsb \n else :\n\n when io.brupdate.b2.mispredict : \n node _rob_tail_T_3 = add(io.brupdate.b2.uop.rob_idx, UInt<1>(0h1)) \n node _rob_tail_T_4 = tail(_rob_tail_T_3, 1) \n node _rob_tail_T_5 = bits(_rob_tail_T_4, 4, 0) \n connect rob_tail, _rob_tail_T_5 \n connect rob_tail_lsb, UInt<1>(0h0) \n else :\n\n node _T_343 = neq(io.enq_valids[0], UInt<1>(0h0)) \n node _T_344 = eq(io.enq_partial_stall, UInt<1>(0h0)) \n node _T_345 = and(_T_343, _T_344) \n when _T_345 : \n node _rob_tail_T_6 = add(rob_tail, UInt<1>(0h1)) \n node _rob_tail_T_7 = tail(_rob_tail_T_6, 1) \n node _rob_tail_T_8 = bits(_rob_tail_T_7, 4, 0) \n connect rob_tail, _rob_tail_T_8 \n connect rob_tail_lsb, UInt<1>(0h0) \n connect rob_enq, UInt<1>(0h1) \n else :\n\n node _T_346 = neq(io.enq_valids[0], UInt<1>(0h0)) \n node _T_347 = and(_T_346, io.enq_partial_stall) \n when _T_347 : \n node _rob_tail_lsb_T = dshr(io.enq_valids[0], UInt<1>(0h0)) \n node _rob_tail_lsb_T_1 = not(_rob_tail_lsb_T) \n node _rob_tail_lsb_T_2 = bits(_rob_tail_lsb_T_1, 0, 0) \n connect rob_tail_lsb, UInt<1>(0h0) \n node _maybe_full_T = eq(rob_deq, UInt<1>(0h0)) \n node _maybe_full_T_1 = or(rob_enq, maybe_full) \n node _maybe_full_T_2 = and(_maybe_full_T, _maybe_full_T_1) \n node _maybe_full_T_3 = neq(io.brupdate.b1.mispredict_mask, UInt<1>(0h0)) \n node _maybe_full_T_4 = or(_maybe_full_T_2, _maybe_full_T_3) \n connect maybe_full, _maybe_full_T_4 \n node _full_T = eq(rob_tail, rob_head) \n node _full_T_1 = and(_full_T, maybe_full) \n connect full, _full_T_1 \n node _empty_T = eq(rob_head, rob_tail) \n node _empty_T_1 = eq(rob_head_vals[0], UInt<1>(0h0)) \n node _empty_T_2 = and(_empty_T, _empty_T_1) \n connect empty, _empty_T_2 \n connect io.rob_head_idx, rob_head \n connect io.rob_tail_idx, rob_tail \n connect io.rob_pnr_idx, rob_pnr \n connect io.empty, empty \n node _io_ready_T = eq(rob_state, UInt<2>(0h1)) \n node _io_ready_T_1 = eq(full, UInt<1>(0h0)) \n node _io_ready_T_2 = and(_io_ready_T, _io_ready_T_1) \n node _io_ready_T_3 = eq(r_xcpt_val, UInt<1>(0h0)) \n node _io_ready_T_4 = and(_io_ready_T_2, _io_ready_T_3) \n connect io.ready, _io_ready_T_4 \n node _T_348 = eq(UInt<2>(0h0), rob_state) \n when _T_348 : \n connect rob_state, UInt<2>(0h1) \n else :\n\n node _T_349 = eq(UInt<2>(0h1), rob_state) \n when _T_349 : \n reg REG : UInt<1>, clock \n connect REG, exception_thrown \n reg REG_1 : UInt<1>, clock \n connect REG_1, REG \n when REG_1 : \n connect rob_state, UInt<2>(0h2) \n else :\n\n node _T_350 = and(io.enq_valids[0], io.enq_uops[0].is_unique) \n when _T_350 : \n connect rob_state, UInt<2>(0h3) \n else :\n\n node _T_351 = eq(UInt<2>(0h2), rob_state) \n when _T_351 : \n when empty : \n connect rob_state, UInt<2>(0h1) \n else :\n\n node _T_352 = eq(UInt<2>(0h3), rob_state) \n when _T_352 : \n reg REG_2 : UInt<1>, clock \n connect REG_2, exception_thrown \n when REG_2 : \n connect rob_state, UInt<2>(0h2) \n else :\n\n when empty : \n connect rob_state, UInt<2>(0h1) \n node _io_com_load_is_at_rob_head_T = bits(rob_head_vals[0], 0, 0) \n node _io_com_load_is_at_rob_head_T_1 = eq(will_commit[0], UInt<1>(0h0)) \n node _io_com_load_is_at_rob_head_T_2 = and(rob_head_uses_ldq[0], _io_com_load_is_at_rob_head_T_1) \n reg io_com_load_is_at_rob_head_REG : UInt<1>, clock \n connect io_com_load_is_at_rob_head_REG, _io_com_load_is_at_rob_head_T_2 \n connect io.com_load_is_at_rob_head, io_com_load_is_at_rob_head_REG"},"response":{"kind":"string","value":"module Rob(\t// @[rob.scala:211:7]\n input clock,\t// @[rob.scala:211:7]\n input reset,\t// @[rob.scala:211:7]\n input io_enq_valids_0,\t// @[rob.scala:216:14]\n input [6:0] io_enq_uops_0_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_enq_uops_0_inst,\t// @[rob.scala:216:14]\n input [31:0] io_enq_uops_0_debug_inst,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_enq_uops_0_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_enq_uops_0_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_enq_uops_0_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_enq_uops_0_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_enq_uops_0_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_enq_uops_0_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_enq_uops_0_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_enq_uops_0_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_enq_uops_0_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_enq_uops_0_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_enq_uops_0_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_enq_uops_0_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_iw_state,\t// @[rob.scala:216:14]\n input io_enq_uops_0_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_enq_uops_0_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_br,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_jalr,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_jal,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_enq_uops_0_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_enq_uops_0_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_enq_uops_0_ftq_idx,\t// @[rob.scala:216:14]\n input io_enq_uops_0_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_pc_lob,\t// @[rob.scala:216:14]\n input io_enq_uops_0_taken,\t// @[rob.scala:216:14]\n input [19:0] io_enq_uops_0_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_enq_uops_0_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_enq_uops_0_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_enq_uops_0_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_enq_uops_0_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_prs3,\t// @[rob.scala:216:14]\n input io_enq_uops_0_prs1_busy,\t// @[rob.scala:216:14]\n input io_enq_uops_0_prs2_busy,\t// @[rob.scala:216:14]\n input io_enq_uops_0_prs3_busy,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_stale_pdst,\t// @[rob.scala:216:14]\n input io_enq_uops_0_exception,\t// @[rob.scala:216:14]\n input [63:0] io_enq_uops_0_exc_cause,\t// @[rob.scala:216:14]\n input io_enq_uops_0_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_enq_uops_0_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_mem_size,\t// @[rob.scala:216:14]\n input io_enq_uops_0_mem_signed,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_fence,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_fencei,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_amo,\t// @[rob.scala:216:14]\n input io_enq_uops_0_uses_ldq,\t// @[rob.scala:216:14]\n input io_enq_uops_0_uses_stq,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_enq_uops_0_is_unique,\t// @[rob.scala:216:14]\n input io_enq_uops_0_flush_on_commit,\t// @[rob.scala:216:14]\n input io_enq_uops_0_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_enq_uops_0_lrs3,\t// @[rob.scala:216:14]\n input io_enq_uops_0_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_enq_uops_0_frs3_en,\t// @[rob.scala:216:14]\n input io_enq_uops_0_fp_val,\t// @[rob.scala:216:14]\n input io_enq_uops_0_fp_single,\t// @[rob.scala:216:14]\n input io_enq_uops_0_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_enq_uops_0_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_enq_uops_0_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_enq_uops_0_bp_debug_if,\t// @[rob.scala:216:14]\n input io_enq_uops_0_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_enq_uops_0_debug_tsrc,\t// @[rob.scala:216:14]\n input io_enq_partial_stall,\t// @[rob.scala:216:14]\n input [39:0] io_xcpt_fetch_pc,\t// @[rob.scala:216:14]\n output [4:0] io_rob_tail_idx,\t// @[rob.scala:216:14]\n output [4:0] io_rob_pnr_idx,\t// @[rob.scala:216:14]\n output [4:0] io_rob_head_idx,\t// @[rob.scala:216:14]\n input [7:0] io_brupdate_b1_resolve_mask,\t// @[rob.scala:216:14]\n input [7:0] io_brupdate_b1_mispredict_mask,\t// @[rob.scala:216:14]\n input [6:0] io_brupdate_b2_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_brupdate_b2_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_brupdate_b2_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_brupdate_b2_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_brupdate_b2_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_brupdate_b2_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_brupdate_b2_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_iw_state,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_br,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_jal,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_brupdate_b2_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_brupdate_b2_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_brupdate_b2_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_brupdate_b2_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_brupdate_b2_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_brupdate_b2_uop_ppred,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_brupdate_b2_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_brupdate_b2_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_mem_size,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_fence,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_amo,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_is_unique,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_brupdate_b2_uop_lrs3,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_fp_val,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_fp_single,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_brupdate_b2_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input io_brupdate_b2_valid,\t// @[rob.scala:216:14]\n input io_brupdate_b2_mispredict,\t// @[rob.scala:216:14]\n input io_brupdate_b2_taken,\t// @[rob.scala:216:14]\n input [2:0] io_brupdate_b2_cfi_type,\t// @[rob.scala:216:14]\n input [1:0] io_brupdate_b2_pc_sel,\t// @[rob.scala:216:14]\n input [39:0] io_brupdate_b2_jalr_target,\t// @[rob.scala:216:14]\n input [20:0] io_brupdate_b2_target_offset,\t// @[rob.scala:216:14]\n input io_wb_resps_0_valid,\t// @[rob.scala:216:14]\n input [6:0] io_wb_resps_0_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_0_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_0_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_wb_resps_0_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_wb_resps_0_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_0_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_0_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_wb_resps_0_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_0_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_wb_resps_0_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_wb_resps_0_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_0_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_0_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_wb_resps_0_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_0_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [64:0] io_wb_resps_0_bits_data,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_predicated,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_valid,\t// @[rob.scala:216:14]\n input [6:0] io_wb_resps_0_bits_fflags_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_0_bits_fflags_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_0_bits_fflags_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_wb_resps_0_bits_fflags_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_fflags_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_wb_resps_0_bits_fflags_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_wb_resps_0_bits_fflags_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_fflags_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_0_bits_fflags_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_wb_resps_0_bits_fflags_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_wb_resps_0_bits_fflags_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_0_bits_fflags_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_0_bits_fflags_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_0_bits_fflags_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_wb_resps_0_bits_fflags_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_0_bits_fflags_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_0_bits_fflags_bits_flags,\t// @[rob.scala:216:14]\n input io_wb_resps_1_valid,\t// @[rob.scala:216:14]\n input [6:0] io_wb_resps_1_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_1_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_1_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_wb_resps_1_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_1_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_wb_resps_1_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_1_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_1_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_1_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_1_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_1_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_wb_resps_1_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_1_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_1_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_wb_resps_1_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_wb_resps_1_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_1_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_1_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_1_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_1_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_wb_resps_1_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_1_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_1_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_wb_resps_1_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_1_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [64:0] io_wb_resps_1_bits_data,\t// @[rob.scala:216:14]\n input io_wb_resps_2_valid,\t// @[rob.scala:216:14]\n input [6:0] io_wb_resps_2_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_2_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_2_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_wb_resps_2_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_wb_resps_2_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_2_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_2_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_wb_resps_2_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_2_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_wb_resps_2_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_wb_resps_2_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_2_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_2_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_wb_resps_2_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_2_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [64:0] io_wb_resps_2_bits_data,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_predicated,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_valid,\t// @[rob.scala:216:14]\n input [6:0] io_wb_resps_2_bits_fflags_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_2_bits_fflags_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_2_bits_fflags_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_wb_resps_2_bits_fflags_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_fflags_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_wb_resps_2_bits_fflags_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_wb_resps_2_bits_fflags_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_fflags_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_2_bits_fflags_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_wb_resps_2_bits_fflags_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_wb_resps_2_bits_fflags_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_2_bits_fflags_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_2_bits_fflags_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_2_bits_fflags_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_wb_resps_2_bits_fflags_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_2_bits_fflags_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_wb_resps_2_bits_fflags_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_2_bits_fflags_bits_flags,\t// @[rob.scala:216:14]\n input io_wb_resps_3_valid,\t// @[rob.scala:216:14]\n input [6:0] io_wb_resps_3_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_3_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_3_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_wb_resps_3_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_wb_resps_3_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_3_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_3_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_wb_resps_3_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_3_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_wb_resps_3_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_wb_resps_3_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_3_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_3_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_wb_resps_3_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_3_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [64:0] io_wb_resps_3_bits_data,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_valid,\t// @[rob.scala:216:14]\n input [6:0] io_wb_resps_3_bits_fflags_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_3_bits_fflags_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_wb_resps_3_bits_fflags_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_wb_resps_3_bits_fflags_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_fflags_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_wb_resps_3_bits_fflags_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_wb_resps_3_bits_fflags_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_fflags_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_3_bits_fflags_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_wb_resps_3_bits_fflags_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_wb_resps_3_bits_fflags_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_3_bits_fflags_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_wb_resps_3_bits_fflags_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_wb_resps_3_bits_fflags_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_wb_resps_3_bits_fflags_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_3_bits_fflags_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_wb_resps_3_bits_fflags_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [4:0] io_wb_resps_3_bits_fflags_bits_flags,\t// @[rob.scala:216:14]\n input io_lsu_clr_bsy_0_valid,\t// @[rob.scala:216:14]\n input [4:0] io_lsu_clr_bsy_0_bits,\t// @[rob.scala:216:14]\n input io_lsu_clr_bsy_1_valid,\t// @[rob.scala:216:14]\n input [4:0] io_lsu_clr_bsy_1_bits,\t// @[rob.scala:216:14]\n input [4:0] io_lsu_clr_unsafe_0_bits,\t// @[rob.scala:216:14]\n input io_debug_wb_valids_0,\t// @[rob.scala:216:14]\n input io_debug_wb_valids_1,\t// @[rob.scala:216:14]\n input io_debug_wb_valids_2,\t// @[rob.scala:216:14]\n input io_debug_wb_valids_3,\t// @[rob.scala:216:14]\n input [63:0] io_debug_wb_wdata_0,\t// @[rob.scala:216:14]\n input [63:0] io_debug_wb_wdata_1,\t// @[rob.scala:216:14]\n input [63:0] io_debug_wb_wdata_2,\t// @[rob.scala:216:14]\n input [63:0] io_debug_wb_wdata_3,\t// @[rob.scala:216:14]\n input io_fflags_0_valid,\t// @[rob.scala:216:14]\n input [6:0] io_fflags_0_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_fflags_0_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_fflags_0_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_fflags_0_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_0_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_fflags_0_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_fflags_0_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_0_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_0_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_0_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_0_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_fflags_0_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_0_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_fflags_0_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_fflags_0_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_fflags_0_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_0_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_0_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_0_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_fflags_0_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_fflags_0_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_0_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_0_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_fflags_0_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_0_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_0_bits_flags,\t// @[rob.scala:216:14]\n input io_fflags_1_valid,\t// @[rob.scala:216:14]\n input [6:0] io_fflags_1_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_fflags_1_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_fflags_1_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_fflags_1_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_1_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_fflags_1_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_fflags_1_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_1_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_1_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_1_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_1_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_fflags_1_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_1_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_fflags_1_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_fflags_1_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_fflags_1_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_1_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_1_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_fflags_1_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_fflags_1_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_fflags_1_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_1_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_fflags_1_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_fflags_1_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_fflags_1_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [4:0] io_fflags_1_bits_flags,\t// @[rob.scala:216:14]\n input io_lxcpt_valid,\t// @[rob.scala:216:14]\n input [6:0] io_lxcpt_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_lxcpt_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_lxcpt_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_lxcpt_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_lxcpt_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_lxcpt_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_lxcpt_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_lxcpt_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_lxcpt_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_lxcpt_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_lxcpt_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_lxcpt_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_lxcpt_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_lxcpt_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_lxcpt_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_lxcpt_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_lxcpt_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_lxcpt_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_lxcpt_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_lxcpt_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_lxcpt_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_lxcpt_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_lxcpt_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_lxcpt_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_lxcpt_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n input [4:0] io_lxcpt_bits_cause,\t// @[rob.scala:216:14]\n input [39:0] io_lxcpt_bits_badvaddr,\t// @[rob.scala:216:14]\n input [6:0] io_csr_replay_bits_uop_uopc,\t// @[rob.scala:216:14]\n input [31:0] io_csr_replay_bits_uop_inst,\t// @[rob.scala:216:14]\n input [31:0] io_csr_replay_bits_uop_debug_inst,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_rvc,\t// @[rob.scala:216:14]\n input [39:0] io_csr_replay_bits_uop_debug_pc,\t// @[rob.scala:216:14]\n input [2:0] io_csr_replay_bits_uop_iq_type,\t// @[rob.scala:216:14]\n input [9:0] io_csr_replay_bits_uop_fu_code,\t// @[rob.scala:216:14]\n input [3:0] io_csr_replay_bits_uop_ctrl_br_type,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_ctrl_op1_sel,\t// @[rob.scala:216:14]\n input [2:0] io_csr_replay_bits_uop_ctrl_op2_sel,\t// @[rob.scala:216:14]\n input [2:0] io_csr_replay_bits_uop_ctrl_imm_sel,\t// @[rob.scala:216:14]\n input [4:0] io_csr_replay_bits_uop_ctrl_op_fcn,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n input [2:0] io_csr_replay_bits_uop_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_ctrl_is_load,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_ctrl_is_sta,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_ctrl_is_std,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_iw_state,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_iw_p1_poisoned,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_iw_p2_poisoned,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_br,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_jalr,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_jal,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_sfb,\t// @[rob.scala:216:14]\n input [7:0] io_csr_replay_bits_uop_br_mask,\t// @[rob.scala:216:14]\n input [2:0] io_csr_replay_bits_uop_br_tag,\t// @[rob.scala:216:14]\n input [3:0] io_csr_replay_bits_uop_ftq_idx,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_edge_inst,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_pc_lob,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_taken,\t// @[rob.scala:216:14]\n input [19:0] io_csr_replay_bits_uop_imm_packed,\t// @[rob.scala:216:14]\n input [11:0] io_csr_replay_bits_uop_csr_addr,\t// @[rob.scala:216:14]\n input [4:0] io_csr_replay_bits_uop_rob_idx,\t// @[rob.scala:216:14]\n input [2:0] io_csr_replay_bits_uop_ldq_idx,\t// @[rob.scala:216:14]\n input [2:0] io_csr_replay_bits_uop_stq_idx,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_rxq_idx,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_pdst,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_prs1,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_prs2,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_prs3,\t// @[rob.scala:216:14]\n input [3:0] io_csr_replay_bits_uop_ppred,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_prs1_busy,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_prs2_busy,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_prs3_busy,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_ppred_busy,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_stale_pdst,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_exception,\t// @[rob.scala:216:14]\n input [63:0] io_csr_replay_bits_uop_exc_cause,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_bypassable,\t// @[rob.scala:216:14]\n input [4:0] io_csr_replay_bits_uop_mem_cmd,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_mem_size,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_mem_signed,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_fence,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_fencei,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_amo,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_uses_ldq,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_uses_stq,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_sys_pc2epc,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_is_unique,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_flush_on_commit,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_ldst_is_rs1,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_ldst,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_lrs1,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_lrs2,\t// @[rob.scala:216:14]\n input [5:0] io_csr_replay_bits_uop_lrs3,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_ldst_val,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_dst_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_lrs1_rtype,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_lrs2_rtype,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_frs3_en,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_fp_val,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_fp_single,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_xcpt_pf_if,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_xcpt_ae_if,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_xcpt_ma_if,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_bp_debug_if,\t// @[rob.scala:216:14]\n input io_csr_replay_bits_uop_bp_xcpt_if,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_debug_fsrc,\t// @[rob.scala:216:14]\n input [1:0] io_csr_replay_bits_uop_debug_tsrc,\t// @[rob.scala:216:14]\n output io_commit_valids_0,\t// @[rob.scala:216:14]\n output io_commit_arch_valids_0,\t// @[rob.scala:216:14]\n output [6:0] io_commit_uops_0_uopc,\t// @[rob.scala:216:14]\n output [31:0] io_commit_uops_0_inst,\t// @[rob.scala:216:14]\n output [31:0] io_commit_uops_0_debug_inst,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_rvc,\t// @[rob.scala:216:14]\n output [39:0] io_commit_uops_0_debug_pc,\t// @[rob.scala:216:14]\n output [2:0] io_commit_uops_0_iq_type,\t// @[rob.scala:216:14]\n output [9:0] io_commit_uops_0_fu_code,\t// @[rob.scala:216:14]\n output [3:0] io_commit_uops_0_ctrl_br_type,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_ctrl_op1_sel,\t// @[rob.scala:216:14]\n output [2:0] io_commit_uops_0_ctrl_op2_sel,\t// @[rob.scala:216:14]\n output [2:0] io_commit_uops_0_ctrl_imm_sel,\t// @[rob.scala:216:14]\n output [4:0] io_commit_uops_0_ctrl_op_fcn,\t// @[rob.scala:216:14]\n output io_commit_uops_0_ctrl_fcn_dw,\t// @[rob.scala:216:14]\n output [2:0] io_commit_uops_0_ctrl_csr_cmd,\t// @[rob.scala:216:14]\n output io_commit_uops_0_ctrl_is_load,\t// @[rob.scala:216:14]\n output io_commit_uops_0_ctrl_is_sta,\t// @[rob.scala:216:14]\n output io_commit_uops_0_ctrl_is_std,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_iw_state,\t// @[rob.scala:216:14]\n output io_commit_uops_0_iw_p1_poisoned,\t// @[rob.scala:216:14]\n output io_commit_uops_0_iw_p2_poisoned,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_br,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_jalr,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_jal,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_sfb,\t// @[rob.scala:216:14]\n output [7:0] io_commit_uops_0_br_mask,\t// @[rob.scala:216:14]\n output [2:0] io_commit_uops_0_br_tag,\t// @[rob.scala:216:14]\n output [3:0] io_commit_uops_0_ftq_idx,\t// @[rob.scala:216:14]\n output io_commit_uops_0_edge_inst,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_pc_lob,\t// @[rob.scala:216:14]\n output io_commit_uops_0_taken,\t// @[rob.scala:216:14]\n output [19:0] io_commit_uops_0_imm_packed,\t// @[rob.scala:216:14]\n output [11:0] io_commit_uops_0_csr_addr,\t// @[rob.scala:216:14]\n output [4:0] io_commit_uops_0_rob_idx,\t// @[rob.scala:216:14]\n output [2:0] io_commit_uops_0_ldq_idx,\t// @[rob.scala:216:14]\n output [2:0] io_commit_uops_0_stq_idx,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_rxq_idx,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_pdst,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_prs1,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_prs2,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_prs3,\t// @[rob.scala:216:14]\n output [3:0] io_commit_uops_0_ppred,\t// @[rob.scala:216:14]\n output io_commit_uops_0_prs1_busy,\t// @[rob.scala:216:14]\n output io_commit_uops_0_prs2_busy,\t// @[rob.scala:216:14]\n output io_commit_uops_0_prs3_busy,\t// @[rob.scala:216:14]\n output io_commit_uops_0_ppred_busy,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_stale_pdst,\t// @[rob.scala:216:14]\n output io_commit_uops_0_exception,\t// @[rob.scala:216:14]\n output [63:0] io_commit_uops_0_exc_cause,\t// @[rob.scala:216:14]\n output io_commit_uops_0_bypassable,\t// @[rob.scala:216:14]\n output [4:0] io_commit_uops_0_mem_cmd,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_mem_size,\t// @[rob.scala:216:14]\n output io_commit_uops_0_mem_signed,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_fence,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_fencei,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_amo,\t// @[rob.scala:216:14]\n output io_commit_uops_0_uses_ldq,\t// @[rob.scala:216:14]\n output io_commit_uops_0_uses_stq,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_sys_pc2epc,\t// @[rob.scala:216:14]\n output io_commit_uops_0_is_unique,\t// @[rob.scala:216:14]\n output io_commit_uops_0_flush_on_commit,\t// @[rob.scala:216:14]\n output io_commit_uops_0_ldst_is_rs1,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_ldst,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_lrs1,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_lrs2,\t// @[rob.scala:216:14]\n output [5:0] io_commit_uops_0_lrs3,\t// @[rob.scala:216:14]\n output io_commit_uops_0_ldst_val,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_dst_rtype,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_lrs1_rtype,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_lrs2_rtype,\t// @[rob.scala:216:14]\n output io_commit_uops_0_frs3_en,\t// @[rob.scala:216:14]\n output io_commit_uops_0_fp_val,\t// @[rob.scala:216:14]\n output io_commit_uops_0_fp_single,\t// @[rob.scala:216:14]\n output io_commit_uops_0_xcpt_pf_if,\t// @[rob.scala:216:14]\n output io_commit_uops_0_xcpt_ae_if,\t// @[rob.scala:216:14]\n output io_commit_uops_0_xcpt_ma_if,\t// @[rob.scala:216:14]\n output io_commit_uops_0_bp_debug_if,\t// @[rob.scala:216:14]\n output io_commit_uops_0_bp_xcpt_if,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_debug_fsrc,\t// @[rob.scala:216:14]\n output [1:0] io_commit_uops_0_debug_tsrc,\t// @[rob.scala:216:14]\n output io_commit_fflags_valid,\t// @[rob.scala:216:14]\n output [4:0] io_commit_fflags_bits,\t// @[rob.scala:216:14]\n output [31:0] io_commit_debug_insts_0,\t// @[rob.scala:216:14]\n output io_commit_rbk_valids_0,\t// @[rob.scala:216:14]\n output io_commit_rollback,\t// @[rob.scala:216:14]\n output [63:0] io_commit_debug_wdata_0,\t// @[rob.scala:216:14]\n output io_com_load_is_at_rob_head,\t// @[rob.scala:216:14]\n output io_com_xcpt_valid,\t// @[rob.scala:216:14]\n output [3:0] io_com_xcpt_bits_ftq_idx,\t// @[rob.scala:216:14]\n output io_com_xcpt_bits_edge_inst,\t// @[rob.scala:216:14]\n output [5:0] io_com_xcpt_bits_pc_lob,\t// @[rob.scala:216:14]\n output [63:0] io_com_xcpt_bits_cause,\t// @[rob.scala:216:14]\n output [63:0] io_com_xcpt_bits_badvaddr,\t// @[rob.scala:216:14]\n input io_csr_stall,\t// @[rob.scala:216:14]\n output io_flush_valid,\t// @[rob.scala:216:14]\n output [3:0] io_flush_bits_ftq_idx,\t// @[rob.scala:216:14]\n output io_flush_bits_edge_inst,\t// @[rob.scala:216:14]\n output io_flush_bits_is_rvc,\t// @[rob.scala:216:14]\n output [5:0] io_flush_bits_pc_lob,\t// @[rob.scala:216:14]\n output [2:0] io_flush_bits_flush_typ,\t// @[rob.scala:216:14]\n output io_empty,\t// @[rob.scala:216:14]\n output io_ready,\t// @[rob.scala:216:14]\n output io_flush_frontend,\t// @[rob.scala:216:14]\n input [63:0] io_debug_tsc\t// @[rob.scala:216:14]\n);\n\n wire [1:0] io_commit_uops_0_debug_tsrc_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_debug_fsrc_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_bp_xcpt_if_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_bp_debug_if_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_xcpt_ma_if_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_xcpt_ae_if_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_xcpt_pf_if_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_fp_single_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_fp_val_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_frs3_en_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_lrs2_rtype_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_lrs1_rtype_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_dst_rtype_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_ldst_val_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_lrs3_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_lrs2_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_lrs1_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_ldst_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_ldst_is_rs1_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_flush_on_commit_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_unique_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_sys_pc2epc_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_uses_stq_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_uses_ldq_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_amo_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_fencei_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_fence_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_mem_signed_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_mem_size_0;\t// @[rob.scala:211:7]\n wire [4:0] io_commit_uops_0_mem_cmd_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_bypassable_0;\t// @[rob.scala:211:7]\n wire [63:0] io_commit_uops_0_exc_cause_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_exception_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_stale_pdst_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_prs3_busy_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_prs2_busy_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_prs1_busy_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_prs3_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_prs2_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_prs1_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_pdst_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_rxq_idx_0;\t// @[rob.scala:211:7]\n wire [2:0] io_commit_uops_0_stq_idx_0;\t// @[rob.scala:211:7]\n wire [2:0] io_commit_uops_0_ldq_idx_0;\t// @[rob.scala:211:7]\n wire [4:0] io_commit_uops_0_rob_idx_0;\t// @[rob.scala:211:7]\n wire [11:0] io_commit_uops_0_csr_addr_0;\t// @[rob.scala:211:7]\n wire [19:0] io_commit_uops_0_imm_packed_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_taken_0;\t// @[rob.scala:211:7]\n wire [2:0] io_commit_uops_0_br_tag_0;\t// @[rob.scala:211:7]\n wire [7:0] io_commit_uops_0_br_mask_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_sfb_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_jal_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_jalr_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_br_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_iw_p2_poisoned_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_iw_p1_poisoned_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_iw_state_0;\t// @[rob.scala:211:7]\n wire [9:0] io_commit_uops_0_fu_code_0;\t// @[rob.scala:211:7]\n wire [2:0] io_commit_uops_0_iq_type_0;\t// @[rob.scala:211:7]\n wire [39:0] io_commit_uops_0_debug_pc_0;\t// @[rob.scala:211:7]\n wire [31:0] io_commit_uops_0_debug_inst_0;\t// @[rob.scala:211:7]\n wire [31:0] io_commit_uops_0_inst_0;\t// @[rob.scala:211:7]\n wire [6:0] io_commit_uops_0_uopc_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_ctrl_is_std_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_ctrl_is_sta_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_ctrl_is_load_0;\t// @[rob.scala:211:7]\n wire [2:0] io_commit_uops_0_ctrl_csr_cmd_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_ctrl_fcn_dw_0;\t// @[rob.scala:211:7]\n wire [4:0] io_commit_uops_0_ctrl_op_fcn_0;\t// @[rob.scala:211:7]\n wire [2:0] io_commit_uops_0_ctrl_imm_sel_0;\t// @[rob.scala:211:7]\n wire [2:0] io_commit_uops_0_ctrl_op2_sel_0;\t// @[rob.scala:211:7]\n wire [1:0] io_commit_uops_0_ctrl_op1_sel_0;\t// @[rob.scala:211:7]\n wire [3:0] io_commit_uops_0_ctrl_br_type_0;\t// @[rob.scala:211:7]\n wire io_commit_valids_0_0;\t// @[rob.scala:211:7]\n wire [5:0] io_commit_uops_0_pc_lob_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_is_rvc_0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_edge_inst_0;\t// @[rob.scala:211:7]\n wire [3:0] io_commit_uops_0_ftq_idx_0;\t// @[rob.scala:211:7]\n wire io_enq_valids_0_0 = io_enq_valids_0;\t// @[rob.scala:211:7]\n wire [6:0] io_enq_uops_0_uopc_0 = io_enq_uops_0_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_enq_uops_0_inst_0 = io_enq_uops_0_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_enq_uops_0_debug_inst_0 = io_enq_uops_0_debug_inst;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_rvc_0 = io_enq_uops_0_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_enq_uops_0_debug_pc_0 = io_enq_uops_0_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_enq_uops_0_iq_type_0 = io_enq_uops_0_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_enq_uops_0_fu_code_0 = io_enq_uops_0_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_enq_uops_0_ctrl_br_type_0 = io_enq_uops_0_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_ctrl_op1_sel_0 = io_enq_uops_0_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_enq_uops_0_ctrl_op2_sel_0 = io_enq_uops_0_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_enq_uops_0_ctrl_imm_sel_0 = io_enq_uops_0_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_enq_uops_0_ctrl_op_fcn_0 = io_enq_uops_0_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_ctrl_fcn_dw_0 = io_enq_uops_0_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_enq_uops_0_ctrl_csr_cmd_0 = io_enq_uops_0_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_ctrl_is_load_0 = io_enq_uops_0_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_ctrl_is_sta_0 = io_enq_uops_0_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_ctrl_is_std_0 = io_enq_uops_0_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_iw_state_0 = io_enq_uops_0_iw_state;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_iw_p1_poisoned_0 = io_enq_uops_0_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_iw_p2_poisoned_0 = io_enq_uops_0_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_br_0 = io_enq_uops_0_is_br;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_jalr_0 = io_enq_uops_0_is_jalr;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_jal_0 = io_enq_uops_0_is_jal;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_sfb_0 = io_enq_uops_0_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_enq_uops_0_br_mask_0 = io_enq_uops_0_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_enq_uops_0_br_tag_0 = io_enq_uops_0_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_enq_uops_0_ftq_idx_0 = io_enq_uops_0_ftq_idx;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_edge_inst_0 = io_enq_uops_0_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_pc_lob_0 = io_enq_uops_0_pc_lob;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_taken_0 = io_enq_uops_0_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_enq_uops_0_imm_packed_0 = io_enq_uops_0_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_enq_uops_0_csr_addr_0 = io_enq_uops_0_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_enq_uops_0_rob_idx_0 = io_enq_uops_0_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_enq_uops_0_ldq_idx_0 = io_enq_uops_0_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_enq_uops_0_stq_idx_0 = io_enq_uops_0_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_rxq_idx_0 = io_enq_uops_0_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_pdst_0 = io_enq_uops_0_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_prs1_0 = io_enq_uops_0_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_prs2_0 = io_enq_uops_0_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_prs3_0 = io_enq_uops_0_prs3;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_prs1_busy_0 = io_enq_uops_0_prs1_busy;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_prs2_busy_0 = io_enq_uops_0_prs2_busy;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_prs3_busy_0 = io_enq_uops_0_prs3_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_stale_pdst_0 = io_enq_uops_0_stale_pdst;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_exception_0 = io_enq_uops_0_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_enq_uops_0_exc_cause_0 = io_enq_uops_0_exc_cause;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_bypassable_0 = io_enq_uops_0_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_enq_uops_0_mem_cmd_0 = io_enq_uops_0_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_mem_size_0 = io_enq_uops_0_mem_size;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_mem_signed_0 = io_enq_uops_0_mem_signed;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_fence_0 = io_enq_uops_0_is_fence;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_fencei_0 = io_enq_uops_0_is_fencei;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_amo_0 = io_enq_uops_0_is_amo;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_uses_ldq_0 = io_enq_uops_0_uses_ldq;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_uses_stq_0 = io_enq_uops_0_uses_stq;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_sys_pc2epc_0 = io_enq_uops_0_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_is_unique_0 = io_enq_uops_0_is_unique;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_flush_on_commit_0 = io_enq_uops_0_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_ldst_is_rs1_0 = io_enq_uops_0_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_ldst_0 = io_enq_uops_0_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_lrs1_0 = io_enq_uops_0_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_lrs2_0 = io_enq_uops_0_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_enq_uops_0_lrs3_0 = io_enq_uops_0_lrs3;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_ldst_val_0 = io_enq_uops_0_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_dst_rtype_0 = io_enq_uops_0_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_lrs1_rtype_0 = io_enq_uops_0_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_lrs2_rtype_0 = io_enq_uops_0_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_frs3_en_0 = io_enq_uops_0_frs3_en;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_fp_val_0 = io_enq_uops_0_fp_val;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_fp_single_0 = io_enq_uops_0_fp_single;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_xcpt_pf_if_0 = io_enq_uops_0_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_xcpt_ae_if_0 = io_enq_uops_0_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_xcpt_ma_if_0 = io_enq_uops_0_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_bp_debug_if_0 = io_enq_uops_0_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_enq_uops_0_bp_xcpt_if_0 = io_enq_uops_0_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_debug_fsrc_0 = io_enq_uops_0_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_enq_uops_0_debug_tsrc_0 = io_enq_uops_0_debug_tsrc;\t// @[rob.scala:211:7]\n wire io_enq_partial_stall_0 = io_enq_partial_stall;\t// @[rob.scala:211:7]\n wire [39:0] io_xcpt_fetch_pc_0 = io_xcpt_fetch_pc;\t// @[rob.scala:211:7]\n wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask;\t// @[rob.scala:211:7]\n wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask;\t// @[rob.scala:211:7]\n wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict;\t// @[rob.scala:211:7]\n wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken;\t// @[rob.scala:211:7]\n wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type;\t// @[rob.scala:211:7]\n wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel;\t// @[rob.scala:211:7]\n wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target;\t// @[rob.scala:211:7]\n wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_valid_0 = io_wb_resps_0_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_wb_resps_0_bits_uop_uopc_0 = io_wb_resps_0_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_0_bits_uop_inst_0 = io_wb_resps_0_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_0_bits_uop_debug_inst_0 = io_wb_resps_0_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_rvc_0 = io_wb_resps_0_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_wb_resps_0_bits_uop_debug_pc_0 = io_wb_resps_0_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_uop_iq_type_0 = io_wb_resps_0_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_wb_resps_0_bits_uop_fu_code_0 = io_wb_resps_0_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_0_bits_uop_ctrl_br_type_0 = io_wb_resps_0_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_ctrl_op1_sel_0 = io_wb_resps_0_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_uop_ctrl_op2_sel_0 = io_wb_resps_0_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_uop_ctrl_imm_sel_0 = io_wb_resps_0_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_0_bits_uop_ctrl_op_fcn_0 = io_wb_resps_0_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_0_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_0_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_ctrl_is_load_0 = io_wb_resps_0_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_ctrl_is_sta_0 = io_wb_resps_0_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_ctrl_is_std_0 = io_wb_resps_0_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_iw_state_0 = io_wb_resps_0_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_iw_p1_poisoned_0 = io_wb_resps_0_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_iw_p2_poisoned_0 = io_wb_resps_0_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_br_0 = io_wb_resps_0_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_jalr_0 = io_wb_resps_0_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_jal_0 = io_wb_resps_0_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_sfb_0 = io_wb_resps_0_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_wb_resps_0_bits_uop_br_mask_0 = io_wb_resps_0_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_uop_br_tag_0 = io_wb_resps_0_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_0_bits_uop_ftq_idx_0 = io_wb_resps_0_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_edge_inst_0 = io_wb_resps_0_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_pc_lob_0 = io_wb_resps_0_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_taken_0 = io_wb_resps_0_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_wb_resps_0_bits_uop_imm_packed_0 = io_wb_resps_0_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_wb_resps_0_bits_uop_csr_addr_0 = io_wb_resps_0_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_0_bits_uop_rob_idx_0 = io_wb_resps_0_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_uop_ldq_idx_0 = io_wb_resps_0_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_uop_stq_idx_0 = io_wb_resps_0_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_rxq_idx_0 = io_wb_resps_0_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_pdst_0 = io_wb_resps_0_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_prs1_0 = io_wb_resps_0_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_prs2_0 = io_wb_resps_0_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_prs3_0 = io_wb_resps_0_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_0_bits_uop_ppred_0 = io_wb_resps_0_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_prs1_busy_0 = io_wb_resps_0_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_prs2_busy_0 = io_wb_resps_0_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_prs3_busy_0 = io_wb_resps_0_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_ppred_busy_0 = io_wb_resps_0_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_stale_pdst_0 = io_wb_resps_0_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_exception_0 = io_wb_resps_0_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_wb_resps_0_bits_uop_exc_cause_0 = io_wb_resps_0_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_bypassable_0 = io_wb_resps_0_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_0_bits_uop_mem_cmd_0 = io_wb_resps_0_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_mem_size_0 = io_wb_resps_0_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_mem_signed_0 = io_wb_resps_0_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_fence_0 = io_wb_resps_0_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_fencei_0 = io_wb_resps_0_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_amo_0 = io_wb_resps_0_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_uses_ldq_0 = io_wb_resps_0_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_uses_stq_0 = io_wb_resps_0_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_sys_pc2epc_0 = io_wb_resps_0_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_is_unique_0 = io_wb_resps_0_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_flush_on_commit_0 = io_wb_resps_0_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_ldst_is_rs1_0 = io_wb_resps_0_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_ldst_0 = io_wb_resps_0_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_lrs1_0 = io_wb_resps_0_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_lrs2_0 = io_wb_resps_0_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_uop_lrs3_0 = io_wb_resps_0_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_ldst_val_0 = io_wb_resps_0_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_dst_rtype_0 = io_wb_resps_0_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_lrs1_rtype_0 = io_wb_resps_0_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_lrs2_rtype_0 = io_wb_resps_0_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_frs3_en_0 = io_wb_resps_0_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_fp_val_0 = io_wb_resps_0_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_fp_single_0 = io_wb_resps_0_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_xcpt_pf_if_0 = io_wb_resps_0_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_xcpt_ae_if_0 = io_wb_resps_0_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_xcpt_ma_if_0 = io_wb_resps_0_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_bp_debug_if_0 = io_wb_resps_0_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_uop_bp_xcpt_if_0 = io_wb_resps_0_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_debug_fsrc_0 = io_wb_resps_0_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_uop_debug_tsrc_0 = io_wb_resps_0_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [64:0] io_wb_resps_0_bits_data_0 = io_wb_resps_0_bits_data;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_predicated_0 = io_wb_resps_0_bits_predicated;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_valid_0 = io_wb_resps_0_bits_fflags_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_uopc_0 = io_wb_resps_0_bits_fflags_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_0_bits_fflags_bits_uop_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_0_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_0_bits_fflags_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_wb_resps_0_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_0_bits_fflags_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_wb_resps_0_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_0_bits_fflags_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_br_0 = io_wb_resps_0_bits_fflags_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_0_bits_fflags_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_0_bits_fflags_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_0_bits_fflags_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_wb_resps_0_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_0_bits_fflags_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_0_bits_fflags_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_0_bits_fflags_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_taken_0 = io_wb_resps_0_bits_fflags_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_wb_resps_0_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_0_bits_fflags_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_wb_resps_0_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_0_bits_fflags_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_pdst_0 = io_wb_resps_0_bits_fflags_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs1_0 = io_wb_resps_0_bits_fflags_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs2_0 = io_wb_resps_0_bits_fflags_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs3_0 = io_wb_resps_0_bits_fflags_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_ppred_0 = io_wb_resps_0_bits_fflags_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_0_bits_fflags_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_exception_0 = io_wb_resps_0_bits_fflags_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_wb_resps_0_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_0_bits_fflags_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_0_bits_fflags_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_0_bits_fflags_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_0_bits_fflags_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_0_bits_fflags_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_0_bits_fflags_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_0_bits_fflags_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_0_bits_fflags_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_ldst_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_0_bits_fflags_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_0_bits_fflags_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_0_bits_fflags_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_0_bits_fflags_bits_flags_0 = io_wb_resps_0_bits_fflags_bits_flags;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_valid_0 = io_wb_resps_1_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_wb_resps_1_bits_uop_uopc_0 = io_wb_resps_1_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_1_bits_uop_inst_0 = io_wb_resps_1_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_1_bits_uop_debug_inst_0 = io_wb_resps_1_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_rvc_0 = io_wb_resps_1_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_wb_resps_1_bits_uop_debug_pc_0 = io_wb_resps_1_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_uop_iq_type_0 = io_wb_resps_1_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_wb_resps_1_bits_uop_fu_code_0 = io_wb_resps_1_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_1_bits_uop_ctrl_br_type_0 = io_wb_resps_1_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_ctrl_op1_sel_0 = io_wb_resps_1_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_uop_ctrl_op2_sel_0 = io_wb_resps_1_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_uop_ctrl_imm_sel_0 = io_wb_resps_1_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_1_bits_uop_ctrl_op_fcn_0 = io_wb_resps_1_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_1_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_1_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_ctrl_is_load_0 = io_wb_resps_1_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_ctrl_is_sta_0 = io_wb_resps_1_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_ctrl_is_std_0 = io_wb_resps_1_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_iw_state_0 = io_wb_resps_1_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_iw_p1_poisoned_0 = io_wb_resps_1_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_iw_p2_poisoned_0 = io_wb_resps_1_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_br_0 = io_wb_resps_1_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_jalr_0 = io_wb_resps_1_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_jal_0 = io_wb_resps_1_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_sfb_0 = io_wb_resps_1_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_wb_resps_1_bits_uop_br_mask_0 = io_wb_resps_1_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_uop_br_tag_0 = io_wb_resps_1_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_1_bits_uop_ftq_idx_0 = io_wb_resps_1_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_edge_inst_0 = io_wb_resps_1_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_pc_lob_0 = io_wb_resps_1_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_taken_0 = io_wb_resps_1_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_wb_resps_1_bits_uop_imm_packed_0 = io_wb_resps_1_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_wb_resps_1_bits_uop_csr_addr_0 = io_wb_resps_1_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_1_bits_uop_rob_idx_0 = io_wb_resps_1_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_uop_ldq_idx_0 = io_wb_resps_1_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_uop_stq_idx_0 = io_wb_resps_1_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_rxq_idx_0 = io_wb_resps_1_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_pdst_0 = io_wb_resps_1_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_prs1_0 = io_wb_resps_1_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_prs2_0 = io_wb_resps_1_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_prs3_0 = io_wb_resps_1_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_1_bits_uop_ppred_0 = io_wb_resps_1_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_prs1_busy_0 = io_wb_resps_1_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_prs2_busy_0 = io_wb_resps_1_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_prs3_busy_0 = io_wb_resps_1_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_ppred_busy_0 = io_wb_resps_1_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_stale_pdst_0 = io_wb_resps_1_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_exception_0 = io_wb_resps_1_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_wb_resps_1_bits_uop_exc_cause_0 = io_wb_resps_1_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_bypassable_0 = io_wb_resps_1_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_1_bits_uop_mem_cmd_0 = io_wb_resps_1_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_mem_size_0 = io_wb_resps_1_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_mem_signed_0 = io_wb_resps_1_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_fence_0 = io_wb_resps_1_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_fencei_0 = io_wb_resps_1_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_amo_0 = io_wb_resps_1_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_uses_ldq_0 = io_wb_resps_1_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_uses_stq_0 = io_wb_resps_1_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_sys_pc2epc_0 = io_wb_resps_1_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_is_unique_0 = io_wb_resps_1_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_flush_on_commit_0 = io_wb_resps_1_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_ldst_is_rs1_0 = io_wb_resps_1_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_ldst_0 = io_wb_resps_1_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_lrs1_0 = io_wb_resps_1_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_lrs2_0 = io_wb_resps_1_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_uop_lrs3_0 = io_wb_resps_1_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_ldst_val_0 = io_wb_resps_1_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_dst_rtype_0 = io_wb_resps_1_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_lrs1_rtype_0 = io_wb_resps_1_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_lrs2_rtype_0 = io_wb_resps_1_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_frs3_en_0 = io_wb_resps_1_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_fp_val_0 = io_wb_resps_1_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_fp_single_0 = io_wb_resps_1_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_xcpt_pf_if_0 = io_wb_resps_1_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_xcpt_ae_if_0 = io_wb_resps_1_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_xcpt_ma_if_0 = io_wb_resps_1_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_bp_debug_if_0 = io_wb_resps_1_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_uop_bp_xcpt_if_0 = io_wb_resps_1_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_debug_fsrc_0 = io_wb_resps_1_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_uop_debug_tsrc_0 = io_wb_resps_1_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [64:0] io_wb_resps_1_bits_data_0 = io_wb_resps_1_bits_data;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_valid_0 = io_wb_resps_2_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_wb_resps_2_bits_uop_uopc_0 = io_wb_resps_2_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_2_bits_uop_inst_0 = io_wb_resps_2_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_2_bits_uop_debug_inst_0 = io_wb_resps_2_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_rvc_0 = io_wb_resps_2_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_wb_resps_2_bits_uop_debug_pc_0 = io_wb_resps_2_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_uop_iq_type_0 = io_wb_resps_2_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_wb_resps_2_bits_uop_fu_code_0 = io_wb_resps_2_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_2_bits_uop_ctrl_br_type_0 = io_wb_resps_2_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_ctrl_op1_sel_0 = io_wb_resps_2_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_uop_ctrl_op2_sel_0 = io_wb_resps_2_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_uop_ctrl_imm_sel_0 = io_wb_resps_2_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_2_bits_uop_ctrl_op_fcn_0 = io_wb_resps_2_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_2_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_2_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_ctrl_is_load_0 = io_wb_resps_2_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_ctrl_is_sta_0 = io_wb_resps_2_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_ctrl_is_std_0 = io_wb_resps_2_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_iw_state_0 = io_wb_resps_2_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_iw_p1_poisoned_0 = io_wb_resps_2_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_iw_p2_poisoned_0 = io_wb_resps_2_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_br_0 = io_wb_resps_2_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_jalr_0 = io_wb_resps_2_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_jal_0 = io_wb_resps_2_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_sfb_0 = io_wb_resps_2_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_wb_resps_2_bits_uop_br_mask_0 = io_wb_resps_2_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_uop_br_tag_0 = io_wb_resps_2_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_2_bits_uop_ftq_idx_0 = io_wb_resps_2_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_edge_inst_0 = io_wb_resps_2_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_pc_lob_0 = io_wb_resps_2_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_taken_0 = io_wb_resps_2_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_wb_resps_2_bits_uop_imm_packed_0 = io_wb_resps_2_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_wb_resps_2_bits_uop_csr_addr_0 = io_wb_resps_2_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_2_bits_uop_rob_idx_0 = io_wb_resps_2_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_uop_ldq_idx_0 = io_wb_resps_2_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_uop_stq_idx_0 = io_wb_resps_2_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_rxq_idx_0 = io_wb_resps_2_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_pdst_0 = io_wb_resps_2_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_prs1_0 = io_wb_resps_2_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_prs2_0 = io_wb_resps_2_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_prs3_0 = io_wb_resps_2_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_2_bits_uop_ppred_0 = io_wb_resps_2_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_prs1_busy_0 = io_wb_resps_2_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_prs2_busy_0 = io_wb_resps_2_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_prs3_busy_0 = io_wb_resps_2_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_ppred_busy_0 = io_wb_resps_2_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_stale_pdst_0 = io_wb_resps_2_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_exception_0 = io_wb_resps_2_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_wb_resps_2_bits_uop_exc_cause_0 = io_wb_resps_2_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_bypassable_0 = io_wb_resps_2_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_2_bits_uop_mem_cmd_0 = io_wb_resps_2_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_mem_size_0 = io_wb_resps_2_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_mem_signed_0 = io_wb_resps_2_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_fence_0 = io_wb_resps_2_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_fencei_0 = io_wb_resps_2_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_amo_0 = io_wb_resps_2_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_uses_ldq_0 = io_wb_resps_2_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_uses_stq_0 = io_wb_resps_2_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_sys_pc2epc_0 = io_wb_resps_2_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_is_unique_0 = io_wb_resps_2_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_flush_on_commit_0 = io_wb_resps_2_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_ldst_is_rs1_0 = io_wb_resps_2_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_ldst_0 = io_wb_resps_2_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_lrs1_0 = io_wb_resps_2_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_lrs2_0 = io_wb_resps_2_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_uop_lrs3_0 = io_wb_resps_2_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_ldst_val_0 = io_wb_resps_2_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_dst_rtype_0 = io_wb_resps_2_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_lrs1_rtype_0 = io_wb_resps_2_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_lrs2_rtype_0 = io_wb_resps_2_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_frs3_en_0 = io_wb_resps_2_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_fp_val_0 = io_wb_resps_2_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_fp_single_0 = io_wb_resps_2_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_xcpt_pf_if_0 = io_wb_resps_2_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_xcpt_ae_if_0 = io_wb_resps_2_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_xcpt_ma_if_0 = io_wb_resps_2_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_bp_debug_if_0 = io_wb_resps_2_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_uop_bp_xcpt_if_0 = io_wb_resps_2_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_debug_fsrc_0 = io_wb_resps_2_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_uop_debug_tsrc_0 = io_wb_resps_2_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [64:0] io_wb_resps_2_bits_data_0 = io_wb_resps_2_bits_data;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_predicated_0 = io_wb_resps_2_bits_predicated;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_valid_0 = io_wb_resps_2_bits_fflags_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_uopc_0 = io_wb_resps_2_bits_fflags_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_2_bits_fflags_bits_uop_inst_0 = io_wb_resps_2_bits_fflags_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_2_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_2_bits_fflags_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_wb_resps_2_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_2_bits_fflags_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_wb_resps_2_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_2_bits_fflags_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_2_bits_fflags_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_2_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_2_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_br_0 = io_wb_resps_2_bits_fflags_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_2_bits_fflags_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_2_bits_fflags_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_2_bits_fflags_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_wb_resps_2_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_2_bits_fflags_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_2_bits_fflags_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_2_bits_fflags_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_2_bits_fflags_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_taken_0 = io_wb_resps_2_bits_fflags_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_wb_resps_2_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_2_bits_fflags_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_wb_resps_2_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_2_bits_fflags_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_pdst_0 = io_wb_resps_2_bits_fflags_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs1_0 = io_wb_resps_2_bits_fflags_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs2_0 = io_wb_resps_2_bits_fflags_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs3_0 = io_wb_resps_2_bits_fflags_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_ppred_0 = io_wb_resps_2_bits_fflags_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_2_bits_fflags_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_exception_0 = io_wb_resps_2_bits_fflags_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_wb_resps_2_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_2_bits_fflags_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_2_bits_fflags_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_2_bits_fflags_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_2_bits_fflags_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_2_bits_fflags_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_2_bits_fflags_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_2_bits_fflags_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_2_bits_fflags_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_2_bits_fflags_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_2_bits_fflags_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_2_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_2_bits_fflags_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_2_bits_fflags_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_2_bits_fflags_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_ldst_0 = io_wb_resps_2_bits_fflags_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_2_bits_fflags_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_2_bits_fflags_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_2_bits_fflags_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_2_bits_fflags_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_2_bits_fflags_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_2_bits_fflags_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_2_bits_fflags_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_2_bits_fflags_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_2_bits_fflags_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_2_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_2_bits_fflags_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_2_bits_fflags_bits_flags_0 = io_wb_resps_2_bits_fflags_bits_flags;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_valid_0 = io_wb_resps_3_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_wb_resps_3_bits_uop_uopc_0 = io_wb_resps_3_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_3_bits_uop_inst_0 = io_wb_resps_3_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_3_bits_uop_debug_inst_0 = io_wb_resps_3_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_rvc_0 = io_wb_resps_3_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_wb_resps_3_bits_uop_debug_pc_0 = io_wb_resps_3_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_uop_iq_type_0 = io_wb_resps_3_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_wb_resps_3_bits_uop_fu_code_0 = io_wb_resps_3_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_3_bits_uop_ctrl_br_type_0 = io_wb_resps_3_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_ctrl_op1_sel_0 = io_wb_resps_3_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_uop_ctrl_op2_sel_0 = io_wb_resps_3_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_uop_ctrl_imm_sel_0 = io_wb_resps_3_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_3_bits_uop_ctrl_op_fcn_0 = io_wb_resps_3_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_3_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_3_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_ctrl_is_load_0 = io_wb_resps_3_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_ctrl_is_sta_0 = io_wb_resps_3_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_ctrl_is_std_0 = io_wb_resps_3_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_iw_state_0 = io_wb_resps_3_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_iw_p1_poisoned_0 = io_wb_resps_3_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_iw_p2_poisoned_0 = io_wb_resps_3_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_br_0 = io_wb_resps_3_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_jalr_0 = io_wb_resps_3_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_jal_0 = io_wb_resps_3_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_sfb_0 = io_wb_resps_3_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_wb_resps_3_bits_uop_br_mask_0 = io_wb_resps_3_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_uop_br_tag_0 = io_wb_resps_3_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_3_bits_uop_ftq_idx_0 = io_wb_resps_3_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_edge_inst_0 = io_wb_resps_3_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_pc_lob_0 = io_wb_resps_3_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_taken_0 = io_wb_resps_3_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_wb_resps_3_bits_uop_imm_packed_0 = io_wb_resps_3_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_wb_resps_3_bits_uop_csr_addr_0 = io_wb_resps_3_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_3_bits_uop_rob_idx_0 = io_wb_resps_3_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_uop_ldq_idx_0 = io_wb_resps_3_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_uop_stq_idx_0 = io_wb_resps_3_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_rxq_idx_0 = io_wb_resps_3_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_pdst_0 = io_wb_resps_3_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_prs1_0 = io_wb_resps_3_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_prs2_0 = io_wb_resps_3_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_prs3_0 = io_wb_resps_3_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_3_bits_uop_ppred_0 = io_wb_resps_3_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_prs1_busy_0 = io_wb_resps_3_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_prs2_busy_0 = io_wb_resps_3_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_prs3_busy_0 = io_wb_resps_3_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_ppred_busy_0 = io_wb_resps_3_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_stale_pdst_0 = io_wb_resps_3_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_exception_0 = io_wb_resps_3_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_wb_resps_3_bits_uop_exc_cause_0 = io_wb_resps_3_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_bypassable_0 = io_wb_resps_3_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_3_bits_uop_mem_cmd_0 = io_wb_resps_3_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_mem_size_0 = io_wb_resps_3_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_mem_signed_0 = io_wb_resps_3_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_fence_0 = io_wb_resps_3_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_fencei_0 = io_wb_resps_3_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_amo_0 = io_wb_resps_3_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_uses_ldq_0 = io_wb_resps_3_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_uses_stq_0 = io_wb_resps_3_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_sys_pc2epc_0 = io_wb_resps_3_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_is_unique_0 = io_wb_resps_3_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_flush_on_commit_0 = io_wb_resps_3_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_ldst_is_rs1_0 = io_wb_resps_3_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_ldst_0 = io_wb_resps_3_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_lrs1_0 = io_wb_resps_3_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_lrs2_0 = io_wb_resps_3_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_uop_lrs3_0 = io_wb_resps_3_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_ldst_val_0 = io_wb_resps_3_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_dst_rtype_0 = io_wb_resps_3_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_lrs1_rtype_0 = io_wb_resps_3_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_lrs2_rtype_0 = io_wb_resps_3_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_frs3_en_0 = io_wb_resps_3_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_fp_val_0 = io_wb_resps_3_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_fp_single_0 = io_wb_resps_3_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_xcpt_pf_if_0 = io_wb_resps_3_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_xcpt_ae_if_0 = io_wb_resps_3_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_xcpt_ma_if_0 = io_wb_resps_3_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_bp_debug_if_0 = io_wb_resps_3_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_uop_bp_xcpt_if_0 = io_wb_resps_3_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_debug_fsrc_0 = io_wb_resps_3_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_uop_debug_tsrc_0 = io_wb_resps_3_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [64:0] io_wb_resps_3_bits_data_0 = io_wb_resps_3_bits_data;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_valid_0 = io_wb_resps_3_bits_fflags_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_uopc_0 = io_wb_resps_3_bits_fflags_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_3_bits_fflags_bits_uop_inst_0 = io_wb_resps_3_bits_fflags_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_3_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_3_bits_fflags_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_wb_resps_3_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_3_bits_fflags_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_wb_resps_3_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_3_bits_fflags_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_3_bits_fflags_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_3_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_3_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_br_0 = io_wb_resps_3_bits_fflags_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_3_bits_fflags_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_3_bits_fflags_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_3_bits_fflags_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_wb_resps_3_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_3_bits_fflags_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_3_bits_fflags_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_3_bits_fflags_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_3_bits_fflags_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_taken_0 = io_wb_resps_3_bits_fflags_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_wb_resps_3_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_3_bits_fflags_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_wb_resps_3_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_3_bits_fflags_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_pdst_0 = io_wb_resps_3_bits_fflags_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs1_0 = io_wb_resps_3_bits_fflags_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs2_0 = io_wb_resps_3_bits_fflags_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs3_0 = io_wb_resps_3_bits_fflags_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_ppred_0 = io_wb_resps_3_bits_fflags_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_3_bits_fflags_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_exception_0 = io_wb_resps_3_bits_fflags_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_wb_resps_3_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_3_bits_fflags_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_3_bits_fflags_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_3_bits_fflags_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_3_bits_fflags_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_3_bits_fflags_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_3_bits_fflags_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_3_bits_fflags_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_3_bits_fflags_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_3_bits_fflags_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_3_bits_fflags_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_3_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_3_bits_fflags_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_3_bits_fflags_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_3_bits_fflags_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_ldst_0 = io_wb_resps_3_bits_fflags_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_3_bits_fflags_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_3_bits_fflags_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_3_bits_fflags_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_3_bits_fflags_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_3_bits_fflags_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_3_bits_fflags_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_3_bits_fflags_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_3_bits_fflags_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_3_bits_fflags_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_3_bits_fflags_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_3_bits_fflags_bits_flags_0 = io_wb_resps_3_bits_fflags_bits_flags;\t// @[rob.scala:211:7]\n wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid;\t// @[rob.scala:211:7]\n wire [4:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits;\t// @[rob.scala:211:7]\n wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid;\t// @[rob.scala:211:7]\n wire [4:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits;\t// @[rob.scala:211:7]\n wire [4:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits;\t// @[rob.scala:211:7]\n wire io_debug_wb_valids_0_0 = io_debug_wb_valids_0;\t// @[rob.scala:211:7]\n wire io_debug_wb_valids_1_0 = io_debug_wb_valids_1;\t// @[rob.scala:211:7]\n wire io_debug_wb_valids_2_0 = io_debug_wb_valids_2;\t// @[rob.scala:211:7]\n wire io_debug_wb_valids_3_0 = io_debug_wb_valids_3;\t// @[rob.scala:211:7]\n wire [63:0] io_debug_wb_wdata_0_0 = io_debug_wb_wdata_0;\t// @[rob.scala:211:7]\n wire [63:0] io_debug_wb_wdata_1_0 = io_debug_wb_wdata_1;\t// @[rob.scala:211:7]\n wire [63:0] io_debug_wb_wdata_2_0 = io_debug_wb_wdata_2;\t// @[rob.scala:211:7]\n wire [63:0] io_debug_wb_wdata_3_0 = io_debug_wb_wdata_3;\t// @[rob.scala:211:7]\n wire io_fflags_0_valid_0 = io_fflags_0_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_fflags_0_bits_uop_uopc_0 = io_fflags_0_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_fflags_0_bits_uop_inst_0 = io_fflags_0_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_fflags_0_bits_uop_debug_inst_0 = io_fflags_0_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_rvc_0 = io_fflags_0_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_fflags_0_bits_uop_debug_pc_0 = io_fflags_0_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_0_bits_uop_iq_type_0 = io_fflags_0_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_fflags_0_bits_uop_fu_code_0 = io_fflags_0_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_fflags_0_bits_uop_ctrl_br_type_0 = io_fflags_0_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_ctrl_op1_sel_0 = io_fflags_0_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_0_bits_uop_ctrl_op2_sel_0 = io_fflags_0_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_0_bits_uop_ctrl_imm_sel_0 = io_fflags_0_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_0_bits_uop_ctrl_op_fcn_0 = io_fflags_0_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_ctrl_fcn_dw_0 = io_fflags_0_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_0_bits_uop_ctrl_csr_cmd_0 = io_fflags_0_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_ctrl_is_load_0 = io_fflags_0_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_ctrl_is_sta_0 = io_fflags_0_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_ctrl_is_std_0 = io_fflags_0_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_iw_state_0 = io_fflags_0_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_iw_p1_poisoned_0 = io_fflags_0_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_iw_p2_poisoned_0 = io_fflags_0_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_br_0 = io_fflags_0_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_jalr_0 = io_fflags_0_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_jal_0 = io_fflags_0_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_sfb_0 = io_fflags_0_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_fflags_0_bits_uop_br_mask_0 = io_fflags_0_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_0_bits_uop_br_tag_0 = io_fflags_0_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_fflags_0_bits_uop_ftq_idx_0 = io_fflags_0_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_edge_inst_0 = io_fflags_0_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_pc_lob_0 = io_fflags_0_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_taken_0 = io_fflags_0_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_fflags_0_bits_uop_imm_packed_0 = io_fflags_0_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_fflags_0_bits_uop_csr_addr_0 = io_fflags_0_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_0_bits_uop_rob_idx_0 = io_fflags_0_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_0_bits_uop_ldq_idx_0 = io_fflags_0_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_0_bits_uop_stq_idx_0 = io_fflags_0_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_rxq_idx_0 = io_fflags_0_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_pdst_0 = io_fflags_0_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_prs1_0 = io_fflags_0_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_prs2_0 = io_fflags_0_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_prs3_0 = io_fflags_0_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_fflags_0_bits_uop_ppred_0 = io_fflags_0_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_prs1_busy_0 = io_fflags_0_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_prs2_busy_0 = io_fflags_0_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_prs3_busy_0 = io_fflags_0_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_ppred_busy_0 = io_fflags_0_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_stale_pdst_0 = io_fflags_0_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_exception_0 = io_fflags_0_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_fflags_0_bits_uop_exc_cause_0 = io_fflags_0_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_bypassable_0 = io_fflags_0_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_0_bits_uop_mem_cmd_0 = io_fflags_0_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_mem_size_0 = io_fflags_0_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_mem_signed_0 = io_fflags_0_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_fence_0 = io_fflags_0_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_fencei_0 = io_fflags_0_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_amo_0 = io_fflags_0_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_uses_ldq_0 = io_fflags_0_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_uses_stq_0 = io_fflags_0_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_sys_pc2epc_0 = io_fflags_0_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_is_unique_0 = io_fflags_0_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_flush_on_commit_0 = io_fflags_0_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_ldst_is_rs1_0 = io_fflags_0_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_ldst_0 = io_fflags_0_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_lrs1_0 = io_fflags_0_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_lrs2_0 = io_fflags_0_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_0_bits_uop_lrs3_0 = io_fflags_0_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_ldst_val_0 = io_fflags_0_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_dst_rtype_0 = io_fflags_0_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_lrs1_rtype_0 = io_fflags_0_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_lrs2_rtype_0 = io_fflags_0_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_frs3_en_0 = io_fflags_0_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_fp_val_0 = io_fflags_0_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_fp_single_0 = io_fflags_0_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_xcpt_pf_if_0 = io_fflags_0_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_xcpt_ae_if_0 = io_fflags_0_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_xcpt_ma_if_0 = io_fflags_0_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_bp_debug_if_0 = io_fflags_0_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_fflags_0_bits_uop_bp_xcpt_if_0 = io_fflags_0_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_debug_fsrc_0 = io_fflags_0_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_0_bits_uop_debug_tsrc_0 = io_fflags_0_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_0_bits_flags_0 = io_fflags_0_bits_flags;\t// @[rob.scala:211:7]\n wire io_fflags_1_valid_0 = io_fflags_1_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_fflags_1_bits_uop_uopc_0 = io_fflags_1_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_fflags_1_bits_uop_inst_0 = io_fflags_1_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_fflags_1_bits_uop_debug_inst_0 = io_fflags_1_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_rvc_0 = io_fflags_1_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_fflags_1_bits_uop_debug_pc_0 = io_fflags_1_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_1_bits_uop_iq_type_0 = io_fflags_1_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_fflags_1_bits_uop_fu_code_0 = io_fflags_1_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_fflags_1_bits_uop_ctrl_br_type_0 = io_fflags_1_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_ctrl_op1_sel_0 = io_fflags_1_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_1_bits_uop_ctrl_op2_sel_0 = io_fflags_1_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_1_bits_uop_ctrl_imm_sel_0 = io_fflags_1_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_1_bits_uop_ctrl_op_fcn_0 = io_fflags_1_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_ctrl_fcn_dw_0 = io_fflags_1_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_1_bits_uop_ctrl_csr_cmd_0 = io_fflags_1_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_ctrl_is_load_0 = io_fflags_1_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_ctrl_is_sta_0 = io_fflags_1_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_ctrl_is_std_0 = io_fflags_1_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_iw_state_0 = io_fflags_1_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_iw_p1_poisoned_0 = io_fflags_1_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_iw_p2_poisoned_0 = io_fflags_1_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_br_0 = io_fflags_1_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_jalr_0 = io_fflags_1_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_jal_0 = io_fflags_1_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_sfb_0 = io_fflags_1_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_fflags_1_bits_uop_br_mask_0 = io_fflags_1_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_1_bits_uop_br_tag_0 = io_fflags_1_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_fflags_1_bits_uop_ftq_idx_0 = io_fflags_1_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_edge_inst_0 = io_fflags_1_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_pc_lob_0 = io_fflags_1_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_taken_0 = io_fflags_1_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_fflags_1_bits_uop_imm_packed_0 = io_fflags_1_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_fflags_1_bits_uop_csr_addr_0 = io_fflags_1_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_1_bits_uop_rob_idx_0 = io_fflags_1_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_1_bits_uop_ldq_idx_0 = io_fflags_1_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_fflags_1_bits_uop_stq_idx_0 = io_fflags_1_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_rxq_idx_0 = io_fflags_1_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_pdst_0 = io_fflags_1_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_prs1_0 = io_fflags_1_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_prs2_0 = io_fflags_1_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_prs3_0 = io_fflags_1_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_fflags_1_bits_uop_ppred_0 = io_fflags_1_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_prs1_busy_0 = io_fflags_1_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_prs2_busy_0 = io_fflags_1_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_prs3_busy_0 = io_fflags_1_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_ppred_busy_0 = io_fflags_1_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_stale_pdst_0 = io_fflags_1_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_exception_0 = io_fflags_1_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_fflags_1_bits_uop_exc_cause_0 = io_fflags_1_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_bypassable_0 = io_fflags_1_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_1_bits_uop_mem_cmd_0 = io_fflags_1_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_mem_size_0 = io_fflags_1_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_mem_signed_0 = io_fflags_1_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_fence_0 = io_fflags_1_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_fencei_0 = io_fflags_1_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_amo_0 = io_fflags_1_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_uses_ldq_0 = io_fflags_1_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_uses_stq_0 = io_fflags_1_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_sys_pc2epc_0 = io_fflags_1_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_is_unique_0 = io_fflags_1_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_flush_on_commit_0 = io_fflags_1_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_ldst_is_rs1_0 = io_fflags_1_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_ldst_0 = io_fflags_1_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_lrs1_0 = io_fflags_1_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_lrs2_0 = io_fflags_1_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_fflags_1_bits_uop_lrs3_0 = io_fflags_1_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_ldst_val_0 = io_fflags_1_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_dst_rtype_0 = io_fflags_1_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_lrs1_rtype_0 = io_fflags_1_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_lrs2_rtype_0 = io_fflags_1_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_frs3_en_0 = io_fflags_1_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_fp_val_0 = io_fflags_1_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_fp_single_0 = io_fflags_1_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_xcpt_pf_if_0 = io_fflags_1_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_xcpt_ae_if_0 = io_fflags_1_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_xcpt_ma_if_0 = io_fflags_1_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_bp_debug_if_0 = io_fflags_1_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_fflags_1_bits_uop_bp_xcpt_if_0 = io_fflags_1_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_debug_fsrc_0 = io_fflags_1_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_fflags_1_bits_uop_debug_tsrc_0 = io_fflags_1_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [4:0] io_fflags_1_bits_flags_0 = io_fflags_1_bits_flags;\t// @[rob.scala:211:7]\n wire io_lxcpt_valid_0 = io_lxcpt_valid;\t// @[rob.scala:211:7]\n wire [6:0] io_lxcpt_bits_uop_uopc_0 = io_lxcpt_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_lxcpt_bits_uop_inst_0 = io_lxcpt_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_lxcpt_bits_uop_debug_inst_0 = io_lxcpt_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_rvc_0 = io_lxcpt_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_lxcpt_bits_uop_debug_pc_0 = io_lxcpt_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_lxcpt_bits_uop_iq_type_0 = io_lxcpt_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_lxcpt_bits_uop_fu_code_0 = io_lxcpt_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_lxcpt_bits_uop_ctrl_br_type_0 = io_lxcpt_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lxcpt_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lxcpt_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lxcpt_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lxcpt_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lxcpt_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lxcpt_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_ctrl_is_load_0 = io_lxcpt_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_ctrl_is_sta_0 = io_lxcpt_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_ctrl_is_std_0 = io_lxcpt_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_iw_state_0 = io_lxcpt_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lxcpt_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lxcpt_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_br_0 = io_lxcpt_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_jalr_0 = io_lxcpt_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_jal_0 = io_lxcpt_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_sfb_0 = io_lxcpt_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_lxcpt_bits_uop_br_mask_0 = io_lxcpt_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_lxcpt_bits_uop_br_tag_0 = io_lxcpt_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_lxcpt_bits_uop_ftq_idx_0 = io_lxcpt_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_edge_inst_0 = io_lxcpt_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_pc_lob_0 = io_lxcpt_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_taken_0 = io_lxcpt_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_lxcpt_bits_uop_imm_packed_0 = io_lxcpt_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_lxcpt_bits_uop_csr_addr_0 = io_lxcpt_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_lxcpt_bits_uop_rob_idx_0 = io_lxcpt_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_lxcpt_bits_uop_ldq_idx_0 = io_lxcpt_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_lxcpt_bits_uop_stq_idx_0 = io_lxcpt_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_rxq_idx_0 = io_lxcpt_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_pdst_0 = io_lxcpt_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_prs1_0 = io_lxcpt_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_prs2_0 = io_lxcpt_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_prs3_0 = io_lxcpt_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_lxcpt_bits_uop_ppred_0 = io_lxcpt_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_prs1_busy_0 = io_lxcpt_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_prs2_busy_0 = io_lxcpt_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_prs3_busy_0 = io_lxcpt_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_ppred_busy_0 = io_lxcpt_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_stale_pdst_0 = io_lxcpt_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_exception_0 = io_lxcpt_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_lxcpt_bits_uop_exc_cause_0 = io_lxcpt_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_bypassable_0 = io_lxcpt_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_lxcpt_bits_uop_mem_cmd_0 = io_lxcpt_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_mem_size_0 = io_lxcpt_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_mem_signed_0 = io_lxcpt_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_fence_0 = io_lxcpt_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_fencei_0 = io_lxcpt_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_amo_0 = io_lxcpt_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_uses_ldq_0 = io_lxcpt_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_uses_stq_0 = io_lxcpt_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lxcpt_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_is_unique_0 = io_lxcpt_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_flush_on_commit_0 = io_lxcpt_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_ldst_is_rs1_0 = io_lxcpt_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_ldst_0 = io_lxcpt_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_lrs1_0 = io_lxcpt_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_lrs2_0 = io_lxcpt_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_lxcpt_bits_uop_lrs3_0 = io_lxcpt_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_ldst_val_0 = io_lxcpt_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_dst_rtype_0 = io_lxcpt_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_lrs1_rtype_0 = io_lxcpt_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_lrs2_rtype_0 = io_lxcpt_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_frs3_en_0 = io_lxcpt_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_fp_val_0 = io_lxcpt_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_fp_single_0 = io_lxcpt_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_xcpt_pf_if_0 = io_lxcpt_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_xcpt_ae_if_0 = io_lxcpt_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_xcpt_ma_if_0 = io_lxcpt_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_bp_debug_if_0 = io_lxcpt_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_lxcpt_bits_uop_bp_xcpt_if_0 = io_lxcpt_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_debug_fsrc_0 = io_lxcpt_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_lxcpt_bits_uop_debug_tsrc_0 = io_lxcpt_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire [4:0] io_lxcpt_bits_cause_0 = io_lxcpt_bits_cause;\t// @[rob.scala:211:7]\n wire [39:0] io_lxcpt_bits_badvaddr_0 = io_lxcpt_bits_badvaddr;\t// @[rob.scala:211:7]\n wire [6:0] io_csr_replay_bits_uop_uopc_0 = io_csr_replay_bits_uop_uopc;\t// @[rob.scala:211:7]\n wire [31:0] io_csr_replay_bits_uop_inst_0 = io_csr_replay_bits_uop_inst;\t// @[rob.scala:211:7]\n wire [31:0] io_csr_replay_bits_uop_debug_inst_0 = io_csr_replay_bits_uop_debug_inst;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_rvc_0 = io_csr_replay_bits_uop_is_rvc;\t// @[rob.scala:211:7]\n wire [39:0] io_csr_replay_bits_uop_debug_pc_0 = io_csr_replay_bits_uop_debug_pc;\t// @[rob.scala:211:7]\n wire [2:0] io_csr_replay_bits_uop_iq_type_0 = io_csr_replay_bits_uop_iq_type;\t// @[rob.scala:211:7]\n wire [9:0] io_csr_replay_bits_uop_fu_code_0 = io_csr_replay_bits_uop_fu_code;\t// @[rob.scala:211:7]\n wire [3:0] io_csr_replay_bits_uop_ctrl_br_type_0 = io_csr_replay_bits_uop_ctrl_br_type;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_ctrl_op1_sel_0 = io_csr_replay_bits_uop_ctrl_op1_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_csr_replay_bits_uop_ctrl_op2_sel_0 = io_csr_replay_bits_uop_ctrl_op2_sel;\t// @[rob.scala:211:7]\n wire [2:0] io_csr_replay_bits_uop_ctrl_imm_sel_0 = io_csr_replay_bits_uop_ctrl_imm_sel;\t// @[rob.scala:211:7]\n wire [4:0] io_csr_replay_bits_uop_ctrl_op_fcn_0 = io_csr_replay_bits_uop_ctrl_op_fcn;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_ctrl_fcn_dw_0 = io_csr_replay_bits_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7]\n wire [2:0] io_csr_replay_bits_uop_ctrl_csr_cmd_0 = io_csr_replay_bits_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_ctrl_is_load_0 = io_csr_replay_bits_uop_ctrl_is_load;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_ctrl_is_sta_0 = io_csr_replay_bits_uop_ctrl_is_sta;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_ctrl_is_std_0 = io_csr_replay_bits_uop_ctrl_is_std;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_iw_state_0 = io_csr_replay_bits_uop_iw_state;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_iw_p1_poisoned_0 = io_csr_replay_bits_uop_iw_p1_poisoned;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_iw_p2_poisoned_0 = io_csr_replay_bits_uop_iw_p2_poisoned;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_br_0 = io_csr_replay_bits_uop_is_br;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_jalr_0 = io_csr_replay_bits_uop_is_jalr;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_jal_0 = io_csr_replay_bits_uop_is_jal;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_sfb_0 = io_csr_replay_bits_uop_is_sfb;\t// @[rob.scala:211:7]\n wire [7:0] io_csr_replay_bits_uop_br_mask_0 = io_csr_replay_bits_uop_br_mask;\t// @[rob.scala:211:7]\n wire [2:0] io_csr_replay_bits_uop_br_tag_0 = io_csr_replay_bits_uop_br_tag;\t// @[rob.scala:211:7]\n wire [3:0] io_csr_replay_bits_uop_ftq_idx_0 = io_csr_replay_bits_uop_ftq_idx;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_edge_inst_0 = io_csr_replay_bits_uop_edge_inst;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_pc_lob_0 = io_csr_replay_bits_uop_pc_lob;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_taken_0 = io_csr_replay_bits_uop_taken;\t// @[rob.scala:211:7]\n wire [19:0] io_csr_replay_bits_uop_imm_packed_0 = io_csr_replay_bits_uop_imm_packed;\t// @[rob.scala:211:7]\n wire [11:0] io_csr_replay_bits_uop_csr_addr_0 = io_csr_replay_bits_uop_csr_addr;\t// @[rob.scala:211:7]\n wire [4:0] io_csr_replay_bits_uop_rob_idx_0 = io_csr_replay_bits_uop_rob_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_csr_replay_bits_uop_ldq_idx_0 = io_csr_replay_bits_uop_ldq_idx;\t// @[rob.scala:211:7]\n wire [2:0] io_csr_replay_bits_uop_stq_idx_0 = io_csr_replay_bits_uop_stq_idx;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_rxq_idx_0 = io_csr_replay_bits_uop_rxq_idx;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_pdst_0 = io_csr_replay_bits_uop_pdst;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_prs1_0 = io_csr_replay_bits_uop_prs1;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_prs2_0 = io_csr_replay_bits_uop_prs2;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_prs3_0 = io_csr_replay_bits_uop_prs3;\t// @[rob.scala:211:7]\n wire [3:0] io_csr_replay_bits_uop_ppred_0 = io_csr_replay_bits_uop_ppred;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_prs1_busy_0 = io_csr_replay_bits_uop_prs1_busy;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_prs2_busy_0 = io_csr_replay_bits_uop_prs2_busy;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_prs3_busy_0 = io_csr_replay_bits_uop_prs3_busy;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_ppred_busy_0 = io_csr_replay_bits_uop_ppred_busy;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_stale_pdst_0 = io_csr_replay_bits_uop_stale_pdst;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_exception_0 = io_csr_replay_bits_uop_exception;\t// @[rob.scala:211:7]\n wire [63:0] io_csr_replay_bits_uop_exc_cause_0 = io_csr_replay_bits_uop_exc_cause;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_bypassable_0 = io_csr_replay_bits_uop_bypassable;\t// @[rob.scala:211:7]\n wire [4:0] io_csr_replay_bits_uop_mem_cmd_0 = io_csr_replay_bits_uop_mem_cmd;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_mem_size_0 = io_csr_replay_bits_uop_mem_size;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_mem_signed_0 = io_csr_replay_bits_uop_mem_signed;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_fence_0 = io_csr_replay_bits_uop_is_fence;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_fencei_0 = io_csr_replay_bits_uop_is_fencei;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_amo_0 = io_csr_replay_bits_uop_is_amo;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_uses_ldq_0 = io_csr_replay_bits_uop_uses_ldq;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_uses_stq_0 = io_csr_replay_bits_uop_uses_stq;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_sys_pc2epc_0 = io_csr_replay_bits_uop_is_sys_pc2epc;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_is_unique_0 = io_csr_replay_bits_uop_is_unique;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_flush_on_commit_0 = io_csr_replay_bits_uop_flush_on_commit;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_ldst_is_rs1_0 = io_csr_replay_bits_uop_ldst_is_rs1;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_ldst_0 = io_csr_replay_bits_uop_ldst;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_lrs1_0 = io_csr_replay_bits_uop_lrs1;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_lrs2_0 = io_csr_replay_bits_uop_lrs2;\t// @[rob.scala:211:7]\n wire [5:0] io_csr_replay_bits_uop_lrs3_0 = io_csr_replay_bits_uop_lrs3;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_ldst_val_0 = io_csr_replay_bits_uop_ldst_val;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_dst_rtype_0 = io_csr_replay_bits_uop_dst_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_lrs1_rtype_0 = io_csr_replay_bits_uop_lrs1_rtype;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_lrs2_rtype_0 = io_csr_replay_bits_uop_lrs2_rtype;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_frs3_en_0 = io_csr_replay_bits_uop_frs3_en;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_fp_val_0 = io_csr_replay_bits_uop_fp_val;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_fp_single_0 = io_csr_replay_bits_uop_fp_single;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_xcpt_pf_if_0 = io_csr_replay_bits_uop_xcpt_pf_if;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_xcpt_ae_if_0 = io_csr_replay_bits_uop_xcpt_ae_if;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_xcpt_ma_if_0 = io_csr_replay_bits_uop_xcpt_ma_if;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_bp_debug_if_0 = io_csr_replay_bits_uop_bp_debug_if;\t// @[rob.scala:211:7]\n wire io_csr_replay_bits_uop_bp_xcpt_if_0 = io_csr_replay_bits_uop_bp_xcpt_if;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_debug_fsrc_0 = io_csr_replay_bits_uop_debug_fsrc;\t// @[rob.scala:211:7]\n wire [1:0] io_csr_replay_bits_uop_debug_tsrc_0 = io_csr_replay_bits_uop_debug_tsrc;\t// @[rob.scala:211:7]\n wire io_csr_stall_0 = io_csr_stall;\t// @[rob.scala:211:7]\n wire [63:0] io_debug_tsc_0 = io_debug_tsc;\t// @[rob.scala:211:7]\n wire _io_commit_rbk_valids_0_T_1 = 1'h1;\t// @[rob.scala:431:63]\n wire _lxcpt_older_T = 1'h1;\t// @[rob.scala:640:23]\n wire lxcpt_older = 1'h1;\t// @[rob.scala:640:44]\n wire io_enq_uops_0_ppred_busy = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_predicated = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_valid = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_br = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_taken = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_exception = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:211:7]\n wire io_wb_resps_3_bits_predicated = 1'h0;\t// @[rob.scala:211:7]\n wire io_lsu_clr_unsafe_0_valid = 1'h0;\t// @[rob.scala:211:7]\n wire io_csr_replay_valid = 1'h0;\t// @[rob.scala:211:7]\n wire io_commit_uops_0_ppred_busy_0 = 1'h0;\t// @[rob.scala:211:7]\n wire debug_entry_0_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_0_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_1_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_2_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_3_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_4_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_5_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_6_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_7_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_8_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_9_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_10_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_11_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_12_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_13_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_14_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_15_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_16_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_17_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_18_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_19_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_20_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_21_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_22_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_23_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_24_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_25_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_26_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_27_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_28_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_29_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_30_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_valid = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_unsafe = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_rvc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_ctrl_fcn_dw = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_ctrl_is_load = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_ctrl_is_sta = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_ctrl_is_std = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_iw_p1_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_iw_p2_poisoned = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_br = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_jalr = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_jal = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_sfb = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_edge_inst = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_taken = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_prs1_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_prs2_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_prs3_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_ppred_busy = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_exception = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_bypassable = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_mem_signed = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_fence = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_fencei = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_amo = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_uses_ldq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_uses_stq = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_sys_pc2epc = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_is_unique = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_flush_on_commit = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_ldst_is_rs1 = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_ldst_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_frs3_en = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_fp_val = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_fp_single = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_xcpt_pf_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_xcpt_ae_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_xcpt_ma_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_bp_debug_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_uop_bp_xcpt_if = 1'h0;\t// @[rob.scala:285:25]\n wire debug_entry_31_exception = 1'h0;\t// @[rob.scala:285:25]\n wire _rob_unsafe_masked_WIRE_0 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_1 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_2 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_3 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_4 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_5 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_6 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_7 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_8 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_9 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_10 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_11 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_12 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_13 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_14 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_15 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_16 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_17 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_18 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_19 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_20 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_21 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_22 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_23 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_24 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_25 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_26 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_27 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_28 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_29 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_30 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_unsafe_masked_WIRE_31 = 1'h0;\t// @[rob.scala:293:43]\n wire _rob_debug_inst_wmask_WIRE_0 = 1'h0;\t// @[rob.scala:297:46]\n wire _rob_val_WIRE_0 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_1 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_2 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_3 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_4 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_5 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_6 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_7 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_8 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_9 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_10 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_11 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_12 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_13 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_14 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_15 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_16 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_17 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_18 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_19 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_20 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_21 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_22 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_23 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_24 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_25 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_26 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_27 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_28 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_29 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_30 = 1'h0;\t// @[rob.scala:308:40]\n wire _rob_val_WIRE_31 = 1'h0;\t// @[rob.scala:308:40]\n wire [3:0] io_enq_uops_0_ppred = 4'h0;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_ftq_idx = 4'h0;\t// @[rob.scala:211:7]\n wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_ppred = 4'h0;\t// @[rob.scala:211:7]\n wire [3:0] io_commit_uops_0_ppred_0 = 4'h0;\t// @[rob.scala:211:7]\n wire [3:0] debug_entry_0_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_0_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_0_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_1_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_1_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_1_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_2_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_2_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_2_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_3_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_3_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_3_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_4_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_4_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_4_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_5_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_5_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_5_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_6_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_6_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_6_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_7_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_7_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_7_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_8_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_8_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_8_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_9_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_9_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_9_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_10_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_10_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_10_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_11_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_11_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_11_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_12_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_12_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_12_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_13_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_13_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_13_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_14_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_14_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_14_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_15_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_15_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_15_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_16_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_16_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_16_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_17_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_17_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_17_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_18_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_18_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_18_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_19_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_19_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_19_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_20_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_20_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_20_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_21_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_21_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_21_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_22_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_22_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_22_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_23_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_23_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_23_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_24_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_24_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_24_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_25_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_25_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_25_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_26_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_26_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_26_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_27_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_27_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_27_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_28_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_28_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_28_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_29_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_29_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_29_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_30_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_30_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_30_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_31_uop_ctrl_br_type = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_31_uop_ftq_idx = 4'h0;\t// @[rob.scala:285:25]\n wire [3:0] debug_entry_31_uop_ppred = 4'h0;\t// @[rob.scala:285:25]\n wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_uopc = 7'h0;\t// @[rob.scala:211:7]\n wire [6:0] debug_entry_0_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_1_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_2_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_3_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_4_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_5_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_6_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_7_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_8_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_9_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_10_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_11_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_12_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_13_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_14_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_15_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_16_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_17_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_18_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_19_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_20_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_21_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_22_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_23_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_24_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_25_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_26_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_27_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_28_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_29_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_30_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [6:0] debug_entry_31_uop_uopc = 7'h0;\t// @[rob.scala:285:25]\n wire [31:0] io_wb_resps_1_bits_fflags_bits_uop_inst = 32'h0;\t// @[rob.scala:211:7]\n wire [31:0] io_wb_resps_1_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[rob.scala:211:7]\n wire [31:0] debug_entry_0_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_0_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_1_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_1_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_2_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_2_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_3_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_3_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_4_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_4_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_5_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_5_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_6_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_6_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_7_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_7_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_8_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_8_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_9_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_9_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_10_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_10_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_11_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_11_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_12_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_12_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_13_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_13_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_14_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_14_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_15_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_15_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_16_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_16_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_17_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_17_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_18_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_18_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_19_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_19_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_20_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_20_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_21_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_21_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_22_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_22_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_23_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_23_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_24_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_24_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_25_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_25_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_26_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_26_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_27_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_27_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_28_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_28_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_29_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_29_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_30_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_30_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_31_uop_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [31:0] debug_entry_31_uop_debug_inst = 32'h0;\t// @[rob.scala:285:25]\n wire [39:0] io_wb_resps_1_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[rob.scala:211:7]\n wire [39:0] io_csr_replay_bits_badvaddr = 40'h0;\t// @[rob.scala:211:7]\n wire [39:0] debug_entry_0_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_1_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_2_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_3_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_4_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_5_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_6_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_7_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_8_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_9_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_10_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_11_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_12_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_13_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_14_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_15_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_16_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_17_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_18_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_19_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_20_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_21_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_22_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_23_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_24_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_25_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_26_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_27_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_28_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_29_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_30_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [39:0] debug_entry_31_uop_debug_pc = 40'h0;\t// @[rob.scala:285:25]\n wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_br_tag = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ldq_idx = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_stq_idx = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] io_com_xcpt_bits_flush_typ = 3'h0;\t// @[rob.scala:211:7]\n wire [2:0] debug_entry_0_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_0_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_0_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_0_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_0_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_0_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_0_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_1_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_1_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_1_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_1_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_1_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_1_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_1_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_2_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_2_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_2_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_2_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_2_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_2_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_2_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_3_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_3_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_3_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_3_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_3_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_3_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_3_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_4_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_4_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_4_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_4_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_4_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_4_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_4_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_5_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_5_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_5_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_5_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_5_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_5_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_5_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_6_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_6_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_6_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_6_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_6_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_6_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_6_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_7_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_7_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_7_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_7_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_7_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_7_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_7_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_8_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_8_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_8_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_8_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_8_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_8_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_8_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_9_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_9_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_9_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_9_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_9_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_9_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_9_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_10_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_10_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_10_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_10_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_10_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_10_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_10_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_11_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_11_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_11_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_11_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_11_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_11_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_11_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_12_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_12_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_12_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_12_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_12_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_12_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_12_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_13_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_13_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_13_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_13_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_13_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_13_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_13_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_14_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_14_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_14_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_14_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_14_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_14_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_14_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_15_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_15_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_15_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_15_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_15_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_15_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_15_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_16_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_16_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_16_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_16_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_16_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_16_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_16_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_17_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_17_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_17_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_17_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_17_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_17_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_17_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_18_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_18_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_18_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_18_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_18_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_18_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_18_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_19_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_19_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_19_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_19_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_19_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_19_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_19_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_20_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_20_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_20_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_20_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_20_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_20_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_20_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_21_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_21_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_21_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_21_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_21_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_21_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_21_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_22_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_22_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_22_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_22_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_22_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_22_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_22_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_23_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_23_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_23_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_23_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_23_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_23_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_23_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_24_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_24_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_24_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_24_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_24_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_24_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_24_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_25_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_25_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_25_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_25_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_25_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_25_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_25_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_26_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_26_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_26_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_26_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_26_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_26_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_26_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_27_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_27_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_27_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_27_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_27_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_27_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_27_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_28_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_28_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_28_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_28_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_28_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_28_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_28_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_29_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_29_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_29_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_29_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_29_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_29_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_29_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_30_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_30_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_30_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_30_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_30_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_30_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_30_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_31_uop_iq_type = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_31_uop_ctrl_op2_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_31_uop_ctrl_imm_sel = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_31_uop_ctrl_csr_cmd = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_31_uop_br_tag = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_31_uop_ldq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [2:0] debug_entry_31_uop_stq_idx = 3'h0;\t// @[rob.scala:285:25]\n wire [9:0] io_wb_resps_1_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[rob.scala:211:7]\n wire [9:0] debug_entry_0_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_1_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_2_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_3_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_4_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_5_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_6_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_7_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_8_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_9_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_10_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_11_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_12_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_13_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_14_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_15_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_16_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_17_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_18_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_19_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_20_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_21_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_22_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_23_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_24_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_25_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_26_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_27_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_28_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_29_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_30_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [9:0] debug_entry_31_uop_fu_code = 10'h0;\t// @[rob.scala:285:25]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[rob.scala:211:7]\n wire [1:0] debug_entry_0_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_0_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_1_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_2_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_3_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_4_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_5_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_6_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_7_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_8_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_9_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_10_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_11_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_12_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_13_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_14_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_15_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_16_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_17_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_18_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_19_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_20_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_21_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_22_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_23_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_24_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_25_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_26_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_27_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_28_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_29_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_30_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_ctrl_op1_sel = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_iw_state = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_rxq_idx = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_mem_size = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_dst_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_lrs1_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_lrs2_rtype = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_debug_fsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [1:0] debug_entry_31_uop_debug_tsrc = 2'h0;\t// @[rob.scala:285:25]\n wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_rob_idx = 5'h0;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[rob.scala:211:7]\n wire [4:0] io_wb_resps_1_bits_fflags_bits_flags = 5'h0;\t// @[rob.scala:211:7]\n wire [4:0] debug_entry_0_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_0_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_0_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_1_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_1_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_1_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_2_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_2_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_2_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_3_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_3_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_3_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_4_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_4_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_4_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_5_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_5_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_5_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_6_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_6_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_6_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_7_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_7_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_7_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_8_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_8_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_8_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_9_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_9_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_9_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_10_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_10_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_10_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_11_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_11_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_11_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_12_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_12_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_12_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_13_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_13_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_13_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_14_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_14_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_14_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_15_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_15_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_15_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_16_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_16_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_16_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_17_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_17_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_17_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_18_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_18_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_18_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_19_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_19_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_19_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_20_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_20_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_20_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_21_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_21_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_21_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_22_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_22_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_22_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_23_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_23_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_23_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_24_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_24_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_24_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_25_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_25_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_25_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_26_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_26_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_26_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_27_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_27_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_27_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_28_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_28_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_28_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_29_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_29_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_29_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_30_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_30_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_30_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_31_uop_ctrl_op_fcn = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_31_uop_rob_idx = 5'h0;\t// @[rob.scala:285:25]\n wire [4:0] debug_entry_31_uop_mem_cmd = 5'h0;\t// @[rob.scala:285:25]\n wire [7:0] io_wb_resps_1_bits_fflags_bits_uop_br_mask = 8'h0;\t// @[rob.scala:211:7]\n wire [7:0] debug_entry_0_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_1_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_2_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_3_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_4_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_5_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_6_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_7_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_8_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_9_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_10_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_11_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_12_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_13_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_14_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_15_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_16_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_17_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_18_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_19_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_20_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_21_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_22_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_23_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_24_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_25_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_26_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_27_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_28_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_29_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_30_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [7:0] debug_entry_31_uop_br_mask = 8'h0;\t// @[rob.scala:285:25]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_pdst = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_prs1 = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_prs2 = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_prs3 = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_stale_pdst = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_ldst = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[rob.scala:211:7]\n wire [5:0] debug_entry_0_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_0_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_1_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_2_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_3_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_4_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_5_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_6_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_7_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_8_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_9_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_10_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_11_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_12_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_13_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_14_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_15_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_16_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_17_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_18_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_19_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_20_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_21_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_22_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_23_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_24_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_25_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_26_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_27_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_28_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_29_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_30_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_pc_lob = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_prs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_prs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_prs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_stale_pdst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_ldst = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_lrs1 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_lrs2 = 6'h0;\t// @[rob.scala:285:25]\n wire [5:0] debug_entry_31_uop_lrs3 = 6'h0;\t// @[rob.scala:285:25]\n wire [19:0] io_wb_resps_1_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[rob.scala:211:7]\n wire [19:0] debug_entry_0_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_1_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_2_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_3_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_4_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_5_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_6_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_7_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_8_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_9_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_10_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_11_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_12_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_13_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_14_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_15_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_16_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_17_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_18_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_19_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_20_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_21_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_22_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_23_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_24_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_25_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_26_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_27_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_28_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_29_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_30_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [19:0] debug_entry_31_uop_imm_packed = 20'h0;\t// @[rob.scala:285:25]\n wire [11:0] io_wb_resps_1_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[rob.scala:211:7]\n wire [11:0] debug_entry_0_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_1_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_2_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_3_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_4_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_5_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_6_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_7_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_8_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_9_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_10_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_11_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_12_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_13_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_14_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_15_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_16_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_17_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_18_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_19_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_20_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_21_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_22_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_23_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_24_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_25_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_26_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_27_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_28_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_29_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_30_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [11:0] debug_entry_31_uop_csr_addr = 12'h0;\t// @[rob.scala:285:25]\n wire [63:0] io_wb_resps_1_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[rob.scala:211:7]\n wire [63:0] io_flush_bits_cause = 64'h0;\t// @[rob.scala:211:7]\n wire [63:0] io_flush_bits_badvaddr = 64'h0;\t// @[rob.scala:211:7]\n wire [63:0] debug_entry_0_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_1_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_2_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_3_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_4_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_5_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_6_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_7_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_8_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_9_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_10_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_11_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_12_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_13_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_14_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_15_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_16_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_17_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_18_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_19_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_20_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_21_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_22_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_23_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_24_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_25_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_26_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_27_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_28_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_29_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_30_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [63:0] debug_entry_31_uop_exc_cause = 64'h0;\t// @[rob.scala:285:25]\n wire [4:0] io_csr_replay_bits_cause = 5'h11;\t// @[rob.scala:211:7]\n wire rob_debug_inst_wmask_0 = io_enq_valids_0_0;\t// @[rob.scala:211:7, :297:38]\n wire _rob_tail_lsb_T = io_enq_valids_0_0;\t// @[util.scala:373:29]\n wire [31:0] rob_debug_inst_wdata_0 = io_enq_uops_0_debug_inst_0;\t// @[rob.scala:211:7, :298:34]\n wire new_xcpt_valid = io_lxcpt_valid_0;\t// @[rob.scala:211:7, :639:41]\n wire [6:0] new_xcpt_uop_uopc = io_lxcpt_bits_uop_uopc_0;\t// @[rob.scala:211:7, :641:23]\n wire [31:0] new_xcpt_uop_inst = io_lxcpt_bits_uop_inst_0;\t// @[rob.scala:211:7, :641:23]\n wire [31:0] new_xcpt_uop_debug_inst = io_lxcpt_bits_uop_debug_inst_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_rvc = io_lxcpt_bits_uop_is_rvc_0;\t// @[rob.scala:211:7, :641:23]\n wire [39:0] new_xcpt_uop_debug_pc = io_lxcpt_bits_uop_debug_pc_0;\t// @[rob.scala:211:7, :641:23]\n wire [2:0] new_xcpt_uop_iq_type = io_lxcpt_bits_uop_iq_type_0;\t// @[rob.scala:211:7, :641:23]\n wire [9:0] new_xcpt_uop_fu_code = io_lxcpt_bits_uop_fu_code_0;\t// @[rob.scala:211:7, :641:23]\n wire [3:0] new_xcpt_uop_ctrl_br_type = io_lxcpt_bits_uop_ctrl_br_type_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_ctrl_op1_sel = io_lxcpt_bits_uop_ctrl_op1_sel_0;\t// @[rob.scala:211:7, :641:23]\n wire [2:0] new_xcpt_uop_ctrl_op2_sel = io_lxcpt_bits_uop_ctrl_op2_sel_0;\t// @[rob.scala:211:7, :641:23]\n wire [2:0] new_xcpt_uop_ctrl_imm_sel = io_lxcpt_bits_uop_ctrl_imm_sel_0;\t// @[rob.scala:211:7, :641:23]\n wire [4:0] new_xcpt_uop_ctrl_op_fcn = io_lxcpt_bits_uop_ctrl_op_fcn_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_ctrl_fcn_dw = io_lxcpt_bits_uop_ctrl_fcn_dw_0;\t// @[rob.scala:211:7, :641:23]\n wire [2:0] new_xcpt_uop_ctrl_csr_cmd = io_lxcpt_bits_uop_ctrl_csr_cmd_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_ctrl_is_load = io_lxcpt_bits_uop_ctrl_is_load_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_ctrl_is_sta = io_lxcpt_bits_uop_ctrl_is_sta_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_ctrl_is_std = io_lxcpt_bits_uop_ctrl_is_std_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_iw_state = io_lxcpt_bits_uop_iw_state_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_iw_p1_poisoned = io_lxcpt_bits_uop_iw_p1_poisoned_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_iw_p2_poisoned = io_lxcpt_bits_uop_iw_p2_poisoned_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_br = io_lxcpt_bits_uop_is_br_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_jalr = io_lxcpt_bits_uop_is_jalr_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_jal = io_lxcpt_bits_uop_is_jal_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_sfb = io_lxcpt_bits_uop_is_sfb_0;\t// @[rob.scala:211:7, :641:23]\n wire [7:0] new_xcpt_uop_br_mask = io_lxcpt_bits_uop_br_mask_0;\t// @[rob.scala:211:7, :641:23]\n wire [2:0] new_xcpt_uop_br_tag = io_lxcpt_bits_uop_br_tag_0;\t// @[rob.scala:211:7, :641:23]\n wire [3:0] new_xcpt_uop_ftq_idx = io_lxcpt_bits_uop_ftq_idx_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_edge_inst = io_lxcpt_bits_uop_edge_inst_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_pc_lob = io_lxcpt_bits_uop_pc_lob_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_taken = io_lxcpt_bits_uop_taken_0;\t// @[rob.scala:211:7, :641:23]\n wire [19:0] new_xcpt_uop_imm_packed = io_lxcpt_bits_uop_imm_packed_0;\t// @[rob.scala:211:7, :641:23]\n wire [11:0] new_xcpt_uop_csr_addr = io_lxcpt_bits_uop_csr_addr_0;\t// @[rob.scala:211:7, :641:23]\n wire [4:0] new_xcpt_uop_rob_idx = io_lxcpt_bits_uop_rob_idx_0;\t// @[rob.scala:211:7, :641:23]\n wire [2:0] new_xcpt_uop_ldq_idx = io_lxcpt_bits_uop_ldq_idx_0;\t// @[rob.scala:211:7, :641:23]\n wire [2:0] new_xcpt_uop_stq_idx = io_lxcpt_bits_uop_stq_idx_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_rxq_idx = io_lxcpt_bits_uop_rxq_idx_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_pdst = io_lxcpt_bits_uop_pdst_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_prs1 = io_lxcpt_bits_uop_prs1_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_prs2 = io_lxcpt_bits_uop_prs2_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_prs3 = io_lxcpt_bits_uop_prs3_0;\t// @[rob.scala:211:7, :641:23]\n wire [3:0] new_xcpt_uop_ppred = io_lxcpt_bits_uop_ppred_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_prs1_busy = io_lxcpt_bits_uop_prs1_busy_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_prs2_busy = io_lxcpt_bits_uop_prs2_busy_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_prs3_busy = io_lxcpt_bits_uop_prs3_busy_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_ppred_busy = io_lxcpt_bits_uop_ppred_busy_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_stale_pdst = io_lxcpt_bits_uop_stale_pdst_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_exception = io_lxcpt_bits_uop_exception_0;\t// @[rob.scala:211:7, :641:23]\n wire [63:0] new_xcpt_uop_exc_cause = io_lxcpt_bits_uop_exc_cause_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_bypassable = io_lxcpt_bits_uop_bypassable_0;\t// @[rob.scala:211:7, :641:23]\n wire [4:0] new_xcpt_uop_mem_cmd = io_lxcpt_bits_uop_mem_cmd_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_mem_size = io_lxcpt_bits_uop_mem_size_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_mem_signed = io_lxcpt_bits_uop_mem_signed_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_fence = io_lxcpt_bits_uop_is_fence_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_fencei = io_lxcpt_bits_uop_is_fencei_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_amo = io_lxcpt_bits_uop_is_amo_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_uses_ldq = io_lxcpt_bits_uop_uses_ldq_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_uses_stq = io_lxcpt_bits_uop_uses_stq_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_sys_pc2epc = io_lxcpt_bits_uop_is_sys_pc2epc_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_is_unique = io_lxcpt_bits_uop_is_unique_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_flush_on_commit = io_lxcpt_bits_uop_flush_on_commit_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_ldst_is_rs1 = io_lxcpt_bits_uop_ldst_is_rs1_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_ldst = io_lxcpt_bits_uop_ldst_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_lrs1 = io_lxcpt_bits_uop_lrs1_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_lrs2 = io_lxcpt_bits_uop_lrs2_0;\t// @[rob.scala:211:7, :641:23]\n wire [5:0] new_xcpt_uop_lrs3 = io_lxcpt_bits_uop_lrs3_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_ldst_val = io_lxcpt_bits_uop_ldst_val_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_dst_rtype = io_lxcpt_bits_uop_dst_rtype_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_lrs1_rtype = io_lxcpt_bits_uop_lrs1_rtype_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_lrs2_rtype = io_lxcpt_bits_uop_lrs2_rtype_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_frs3_en = io_lxcpt_bits_uop_frs3_en_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_fp_val = io_lxcpt_bits_uop_fp_val_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_fp_single = io_lxcpt_bits_uop_fp_single_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_xcpt_pf_if = io_lxcpt_bits_uop_xcpt_pf_if_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_xcpt_ae_if = io_lxcpt_bits_uop_xcpt_ae_if_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_xcpt_ma_if = io_lxcpt_bits_uop_xcpt_ma_if_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_bp_debug_if = io_lxcpt_bits_uop_bp_debug_if_0;\t// @[rob.scala:211:7, :641:23]\n wire new_xcpt_uop_bp_xcpt_if = io_lxcpt_bits_uop_bp_xcpt_if_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_debug_fsrc = io_lxcpt_bits_uop_debug_fsrc_0;\t// @[rob.scala:211:7, :641:23]\n wire [1:0] new_xcpt_uop_debug_tsrc = io_lxcpt_bits_uop_debug_tsrc_0;\t// @[rob.scala:211:7, :641:23]\n wire [4:0] new_xcpt_cause = io_lxcpt_bits_cause_0;\t// @[rob.scala:211:7, :641:23]\n wire [39:0] new_xcpt_badvaddr = io_lxcpt_bits_badvaddr_0;\t// @[rob.scala:211:7, :641:23]\n wire will_commit_0;\t// @[rob.scala:242:33]\n wire _io_commit_arch_valids_0_T_1;\t// @[rob.scala:414:48]\n wire _finished_committing_row_T = io_commit_valids_0_0;\t// @[rob.scala:211:7, :693:30]\n wire [6:0] flush_uop_uopc = io_commit_uops_0_uopc_0;\t// @[rob.scala:211:7, :583:22]\n wire [31:0] flush_uop_inst = io_commit_uops_0_inst_0;\t// @[rob.scala:211:7, :583:22]\n wire [31:0] flush_uop_debug_inst = io_commit_uops_0_debug_inst_0;\t// @[rob.scala:211:7, :583:22]\n wire io_com_xcpt_bits_is_rvc = io_commit_uops_0_is_rvc_0;\t// @[rob.scala:211:7]\n wire flush_uop_is_rvc = io_commit_uops_0_is_rvc_0;\t// @[rob.scala:211:7, :583:22]\n wire [39:0] flush_uop_debug_pc = io_commit_uops_0_debug_pc_0;\t// @[rob.scala:211:7, :583:22]\n wire [2:0] flush_uop_iq_type = io_commit_uops_0_iq_type_0;\t// @[rob.scala:211:7, :583:22]\n wire [9:0] flush_uop_fu_code = io_commit_uops_0_fu_code_0;\t// @[rob.scala:211:7, :583:22]\n wire [3:0] flush_uop_ctrl_br_type = io_commit_uops_0_ctrl_br_type_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_ctrl_op1_sel = io_commit_uops_0_ctrl_op1_sel_0;\t// @[rob.scala:211:7, :583:22]\n wire [2:0] flush_uop_ctrl_op2_sel = io_commit_uops_0_ctrl_op2_sel_0;\t// @[rob.scala:211:7, :583:22]\n wire [2:0] flush_uop_ctrl_imm_sel = io_commit_uops_0_ctrl_imm_sel_0;\t// @[rob.scala:211:7, :583:22]\n wire [4:0] flush_uop_ctrl_op_fcn = io_commit_uops_0_ctrl_op_fcn_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_ctrl_fcn_dw = io_commit_uops_0_ctrl_fcn_dw_0;\t// @[rob.scala:211:7, :583:22]\n wire [2:0] flush_uop_ctrl_csr_cmd = io_commit_uops_0_ctrl_csr_cmd_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_ctrl_is_load = io_commit_uops_0_ctrl_is_load_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_ctrl_is_sta = io_commit_uops_0_ctrl_is_sta_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_ctrl_is_std = io_commit_uops_0_ctrl_is_std_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_iw_state = io_commit_uops_0_iw_state_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_iw_p1_poisoned = io_commit_uops_0_iw_p1_poisoned_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_iw_p2_poisoned = io_commit_uops_0_iw_p2_poisoned_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_br = io_commit_uops_0_is_br_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_jalr = io_commit_uops_0_is_jalr_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_jal = io_commit_uops_0_is_jal_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_sfb = io_commit_uops_0_is_sfb_0;\t// @[rob.scala:211:7, :583:22]\n wire [7:0] flush_uop_br_mask = io_commit_uops_0_br_mask_0;\t// @[rob.scala:211:7, :583:22]\n wire [2:0] flush_uop_br_tag = io_commit_uops_0_br_tag_0;\t// @[rob.scala:211:7, :583:22]\n wire [3:0] io_com_xcpt_bits_ftq_idx_0 = io_commit_uops_0_ftq_idx_0;\t// @[rob.scala:211:7]\n wire [3:0] flush_uop_ftq_idx = io_commit_uops_0_ftq_idx_0;\t// @[rob.scala:211:7, :583:22]\n wire io_com_xcpt_bits_edge_inst_0 = io_commit_uops_0_edge_inst_0;\t// @[rob.scala:211:7]\n wire flush_uop_edge_inst = io_commit_uops_0_edge_inst_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] io_com_xcpt_bits_pc_lob_0 = io_commit_uops_0_pc_lob_0;\t// @[rob.scala:211:7]\n wire [5:0] flush_uop_pc_lob = io_commit_uops_0_pc_lob_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_taken = io_commit_uops_0_taken_0;\t// @[rob.scala:211:7, :583:22]\n wire [19:0] flush_uop_imm_packed = io_commit_uops_0_imm_packed_0;\t// @[rob.scala:211:7, :583:22]\n wire [11:0] flush_uop_csr_addr = io_commit_uops_0_csr_addr_0;\t// @[rob.scala:211:7, :583:22]\n wire [4:0] flush_uop_rob_idx = io_commit_uops_0_rob_idx_0;\t// @[rob.scala:211:7, :583:22]\n wire [2:0] flush_uop_ldq_idx = io_commit_uops_0_ldq_idx_0;\t// @[rob.scala:211:7, :583:22]\n wire [2:0] flush_uop_stq_idx = io_commit_uops_0_stq_idx_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_rxq_idx = io_commit_uops_0_rxq_idx_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_pdst = io_commit_uops_0_pdst_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_prs1 = io_commit_uops_0_prs1_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_prs2 = io_commit_uops_0_prs2_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_prs3 = io_commit_uops_0_prs3_0;\t// @[rob.scala:211:7, :583:22]\n wire [3:0] flush_uop_ppred = io_commit_uops_0_ppred_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_prs1_busy = io_commit_uops_0_prs1_busy_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_prs2_busy = io_commit_uops_0_prs2_busy_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_prs3_busy = io_commit_uops_0_prs3_busy_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_ppred_busy = io_commit_uops_0_ppred_busy_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_stale_pdst = io_commit_uops_0_stale_pdst_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_exception = io_commit_uops_0_exception_0;\t// @[rob.scala:211:7, :583:22]\n wire [63:0] flush_uop_exc_cause = io_commit_uops_0_exc_cause_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_bypassable = io_commit_uops_0_bypassable_0;\t// @[rob.scala:211:7, :583:22]\n wire [4:0] flush_uop_mem_cmd = io_commit_uops_0_mem_cmd_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_mem_size = io_commit_uops_0_mem_size_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_mem_signed = io_commit_uops_0_mem_signed_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_fence = io_commit_uops_0_is_fence_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_fencei = io_commit_uops_0_is_fencei_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_amo = io_commit_uops_0_is_amo_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_uses_ldq = io_commit_uops_0_uses_ldq_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_uses_stq = io_commit_uops_0_uses_stq_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_sys_pc2epc = io_commit_uops_0_is_sys_pc2epc_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_is_unique = io_commit_uops_0_is_unique_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_flush_on_commit = io_commit_uops_0_flush_on_commit_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_ldst_is_rs1 = io_commit_uops_0_ldst_is_rs1_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_ldst = io_commit_uops_0_ldst_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_lrs1 = io_commit_uops_0_lrs1_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_lrs2 = io_commit_uops_0_lrs2_0;\t// @[rob.scala:211:7, :583:22]\n wire [5:0] flush_uop_lrs3 = io_commit_uops_0_lrs3_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_ldst_val = io_commit_uops_0_ldst_val_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_dst_rtype = io_commit_uops_0_dst_rtype_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_lrs1_rtype = io_commit_uops_0_lrs1_rtype_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_lrs2_rtype = io_commit_uops_0_lrs2_rtype_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_frs3_en = io_commit_uops_0_frs3_en_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_fp_val = io_commit_uops_0_fp_val_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_fp_single = io_commit_uops_0_fp_single_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_xcpt_pf_if = io_commit_uops_0_xcpt_pf_if_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_xcpt_ae_if = io_commit_uops_0_xcpt_ae_if_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_xcpt_ma_if = io_commit_uops_0_xcpt_ma_if_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_bp_debug_if = io_commit_uops_0_bp_debug_if_0;\t// @[rob.scala:211:7, :583:22]\n wire flush_uop_bp_xcpt_if = io_commit_uops_0_bp_xcpt_if_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_debug_fsrc = io_commit_uops_0_debug_fsrc_0;\t// @[rob.scala:211:7, :583:22]\n wire [1:0] flush_uop_debug_tsrc = io_commit_uops_0_debug_tsrc_0;\t// @[rob.scala:211:7, :583:22]\n wire fflags_val_0;\t// @[rob.scala:602:24]\n wire [4:0] fflags_0;\t// @[rob.scala:603:24]\n wire _io_commit_rbk_valids_0_T_2;\t// @[rob.scala:431:60]\n wire _io_commit_rollback_T;\t// @[rob.scala:432:38]\n wire _io_com_xcpt_valid_T_1;\t// @[rob.scala:561:41]\n wire [63:0] _io_com_xcpt_bits_badvaddr_T_2;\t// @[util.scala:261:20]\n wire flush_val;\t// @[rob.scala:578:36]\n wire [2:0] io_flush_bits_flush_typ_ret;\t// @[rob.scala:172:10]\n wire empty;\t// @[rob.scala:240:26]\n wire _io_ready_T_4;\t// @[rob.scala:803:56]\n wire io_commit_arch_valids_0_0;\t// @[rob.scala:211:7]\n wire io_commit_fflags_valid_0;\t// @[rob.scala:211:7]\n wire [4:0] io_commit_fflags_bits_0;\t// @[rob.scala:211:7]\n wire [31:0] io_commit_debug_insts_0_0;\t// @[rob.scala:211:7]\n wire io_commit_rbk_valids_0_0;\t// @[rob.scala:211:7]\n wire [63:0] io_commit_debug_wdata_0_0;\t// @[rob.scala:211:7]\n wire io_commit_rollback_0;\t// @[rob.scala:211:7]\n wire [63:0] io_com_xcpt_bits_cause_0;\t// @[rob.scala:211:7]\n wire [63:0] io_com_xcpt_bits_badvaddr_0;\t// @[rob.scala:211:7]\n wire io_com_xcpt_valid_0;\t// @[rob.scala:211:7]\n wire [3:0] io_flush_bits_ftq_idx_0;\t// @[rob.scala:211:7]\n wire io_flush_bits_edge_inst_0;\t// @[rob.scala:211:7]\n wire io_flush_bits_is_rvc_0;\t// @[rob.scala:211:7]\n wire [5:0] io_flush_bits_pc_lob_0;\t// @[rob.scala:211:7]\n wire [2:0] io_flush_bits_flush_typ_0;\t// @[rob.scala:211:7]\n wire io_flush_valid_0;\t// @[rob.scala:211:7]\n wire [4:0] io_rob_tail_idx_0;\t// @[rob.scala:211:7]\n wire [4:0] io_rob_pnr_idx_0;\t// @[rob.scala:211:7]\n wire [4:0] io_rob_head_idx_0;\t// @[rob.scala:211:7]\n wire io_com_load_is_at_rob_head_0;\t// @[rob.scala:211:7]\n wire io_empty_0;\t// @[rob.scala:211:7]\n wire io_ready_0;\t// @[rob.scala:211:7]\n wire io_flush_frontend_0;\t// @[rob.scala:211:7]\n reg [1:0] rob_state;\t// @[rob.scala:220:26]\n reg [4:0] rob_head;\t// @[rob.scala:223:29]\n assign io_rob_head_idx_0 = rob_head;\t// @[rob.scala:211:7, :223:29]\n wire [4:0] _rob_debug_inst_rdata_WIRE = rob_head;\t// @[rob.scala:223:29, :300:53]\n reg [4:0] rob_tail;\t// @[rob.scala:227:29]\n assign io_rob_tail_idx_0 = rob_tail;\t// @[rob.scala:211:7, :227:29]\n reg rob_tail_lsb;\t// @[rob.scala:228:29]\n reg [4:0] rob_pnr;\t// @[rob.scala:231:29]\n assign io_rob_pnr_idx_0 = rob_pnr;\t// @[rob.scala:211:7, :231:29]\n wire _T_351 = rob_state == 2'h2;\t// @[rob.scala:220:26, :235:31]\n wire _com_idx_T;\t// @[rob.scala:235:31]\n assign _com_idx_T = _T_351;\t// @[rob.scala:235:31]\n wire _rbk_row_T;\t// @[rob.scala:429:29]\n assign _rbk_row_T = _T_351;\t// @[rob.scala:235:31, :429:29]\n assign _io_commit_rollback_T = _T_351;\t// @[rob.scala:235:31, :432:38]\n wire [4:0] com_idx = _com_idx_T ? rob_tail : rob_head;\t// @[rob.scala:223:29, :227:29, :235:{20,31}]\n reg maybe_full;\t// @[rob.scala:238:29]\n wire _full_T_1;\t// @[rob.scala:796:39]\n wire full;\t// @[rob.scala:239:26]\n wire _empty_T_2;\t// @[rob.scala:797:41]\n assign io_empty_0 = empty;\t// @[rob.scala:211:7, :240:26]\n wire _will_commit_0_T_3;\t// @[rob.scala:551:70]\n assign io_commit_valids_0_0 = will_commit_0;\t// @[rob.scala:211:7, :242:33]\n wire _can_commit_0_T_3;\t// @[rob.scala:408:64]\n wire can_commit_0;\t// @[rob.scala:243:33]\n wire _can_throw_exception_0_T;\t// @[rob.scala:402:49]\n wire can_throw_exception_0;\t// @[rob.scala:244:33]\n wire _rob_pnr_unsafe_0_T_1;\t// @[rob.scala:497:43]\n wire rob_pnr_unsafe_0;\t// @[rob.scala:246:33]\n wire rob_head_vals_0;\t// @[rob.scala:247:33]\n wire _rob_head_lsb_T = rob_head_vals_0;\t// @[OneHot.scala:85:71]\n wire _io_com_load_is_at_rob_head_T = rob_head_vals_0;\t// @[OneHot.scala:48:45]\n wire rob_tail_vals_0;\t// @[rob.scala:248:33]\n wire _rob_pnr_lsb_T = rob_tail_vals_0;\t// @[util.scala:373:29]\n wire rob_head_uses_stq_0;\t// @[rob.scala:249:33]\n wire rob_head_uses_ldq_0;\t// @[rob.scala:250:33]\n wire [4:0] rob_head_fflags_0;\t// @[rob.scala:251:33]\n wire exception_thrown;\t// @[rob.scala:253:30]\n reg r_xcpt_val;\t// @[rob.scala:257:33]\n assign io_flush_frontend_0 = r_xcpt_val;\t// @[rob.scala:211:7, :257:33]\n reg [6:0] r_xcpt_uop_uopc;\t// @[rob.scala:258:29]\n reg [31:0] r_xcpt_uop_inst;\t// @[rob.scala:258:29]\n reg [31:0] r_xcpt_uop_debug_inst;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_rvc;\t// @[rob.scala:258:29]\n reg [39:0] r_xcpt_uop_debug_pc;\t// @[rob.scala:258:29]\n reg [2:0] r_xcpt_uop_iq_type;\t// @[rob.scala:258:29]\n reg [9:0] r_xcpt_uop_fu_code;\t// @[rob.scala:258:29]\n reg [3:0] r_xcpt_uop_ctrl_br_type;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_ctrl_op1_sel;\t// @[rob.scala:258:29]\n reg [2:0] r_xcpt_uop_ctrl_op2_sel;\t// @[rob.scala:258:29]\n reg [2:0] r_xcpt_uop_ctrl_imm_sel;\t// @[rob.scala:258:29]\n reg [4:0] r_xcpt_uop_ctrl_op_fcn;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_ctrl_fcn_dw;\t// @[rob.scala:258:29]\n reg [2:0] r_xcpt_uop_ctrl_csr_cmd;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_ctrl_is_load;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_ctrl_is_sta;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_ctrl_is_std;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_iw_state;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_iw_p1_poisoned;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_iw_p2_poisoned;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_br;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_jalr;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_jal;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_sfb;\t// @[rob.scala:258:29]\n reg [7:0] r_xcpt_uop_br_mask;\t// @[rob.scala:258:29]\n reg [2:0] r_xcpt_uop_br_tag;\t// @[rob.scala:258:29]\n reg [3:0] r_xcpt_uop_ftq_idx;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_edge_inst;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_pc_lob;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_taken;\t// @[rob.scala:258:29]\n reg [19:0] r_xcpt_uop_imm_packed;\t// @[rob.scala:258:29]\n reg [11:0] r_xcpt_uop_csr_addr;\t// @[rob.scala:258:29]\n reg [4:0] r_xcpt_uop_rob_idx;\t// @[rob.scala:258:29]\n reg [2:0] r_xcpt_uop_ldq_idx;\t// @[rob.scala:258:29]\n reg [2:0] r_xcpt_uop_stq_idx;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_rxq_idx;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_pdst;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_prs1;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_prs2;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_prs3;\t// @[rob.scala:258:29]\n reg [3:0] r_xcpt_uop_ppred;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_prs1_busy;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_prs2_busy;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_prs3_busy;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_ppred_busy;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_stale_pdst;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_exception;\t// @[rob.scala:258:29]\n reg [63:0] r_xcpt_uop_exc_cause;\t// @[rob.scala:258:29]\n assign io_com_xcpt_bits_cause_0 = r_xcpt_uop_exc_cause;\t// @[rob.scala:211:7, :258:29]\n reg r_xcpt_uop_bypassable;\t// @[rob.scala:258:29]\n reg [4:0] r_xcpt_uop_mem_cmd;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_mem_size;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_mem_signed;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_fence;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_fencei;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_amo;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_uses_ldq;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_uses_stq;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_sys_pc2epc;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_is_unique;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_flush_on_commit;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_ldst_is_rs1;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_ldst;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_lrs1;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_lrs2;\t// @[rob.scala:258:29]\n reg [5:0] r_xcpt_uop_lrs3;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_ldst_val;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_dst_rtype;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_lrs1_rtype;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_lrs2_rtype;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_frs3_en;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_fp_val;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_fp_single;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_xcpt_pf_if;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_xcpt_ae_if;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_xcpt_ma_if;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_bp_debug_if;\t// @[rob.scala:258:29]\n reg r_xcpt_uop_bp_xcpt_if;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_debug_fsrc;\t// @[rob.scala:258:29]\n reg [1:0] r_xcpt_uop_debug_tsrc;\t// @[rob.scala:258:29]\n reg [39:0] r_xcpt_badvaddr;\t// @[rob.scala:259:29]\n wire _rob_unsafe_masked_0_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_1_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_2_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_3_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_4_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_5_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_6_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_7_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_8_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_9_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_10_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_11_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_12_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_13_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_14_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_15_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_16_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_17_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_18_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_19_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_20_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_21_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_22_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_23_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_24_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_25_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_26_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_27_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_28_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_29_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_30_T_1;\t// @[rob.scala:494:71]\n wire _rob_unsafe_masked_31_T_1;\t// @[rob.scala:494:71]\n wire rob_unsafe_masked_0;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_1;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_2;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_3;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_4;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_5;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_6;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_7;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_8;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_9;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_10;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_11;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_12;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_13;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_14;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_15;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_16;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_17;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_18;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_19;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_20;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_21;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_22;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_23;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_24;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_25;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_26;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_27;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_28;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_29;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_30;\t// @[rob.scala:293:35]\n wire rob_unsafe_masked_31;\t// @[rob.scala:293:35]\n reg [4:0] rob_fflags_0_0;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_1;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_2;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_3;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_4;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_5;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_6;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_7;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_8;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_9;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_10;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_11;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_12;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_13;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_14;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_15;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_16;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_17;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_18;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_19;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_20;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_21;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_22;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_23;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_24;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_25;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_26;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_27;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_28;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_29;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_30;\t// @[rob.scala:302:46]\n reg [4:0] rob_fflags_0_31;\t// @[rob.scala:302:46]\n reg rob_val_0;\t// @[rob.scala:308:32]\n reg rob_val_1;\t// @[rob.scala:308:32]\n reg rob_val_2;\t// @[rob.scala:308:32]\n reg rob_val_3;\t// @[rob.scala:308:32]\n reg rob_val_4;\t// @[rob.scala:308:32]\n reg rob_val_5;\t// @[rob.scala:308:32]\n reg rob_val_6;\t// @[rob.scala:308:32]\n reg rob_val_7;\t// @[rob.scala:308:32]\n reg rob_val_8;\t// @[rob.scala:308:32]\n reg rob_val_9;\t// @[rob.scala:308:32]\n reg rob_val_10;\t// @[rob.scala:308:32]\n reg rob_val_11;\t// @[rob.scala:308:32]\n reg rob_val_12;\t// @[rob.scala:308:32]\n reg rob_val_13;\t// @[rob.scala:308:32]\n reg rob_val_14;\t// @[rob.scala:308:32]\n reg rob_val_15;\t// @[rob.scala:308:32]\n reg rob_val_16;\t// @[rob.scala:308:32]\n reg rob_val_17;\t// @[rob.scala:308:32]\n reg rob_val_18;\t// @[rob.scala:308:32]\n reg rob_val_19;\t// @[rob.scala:308:32]\n reg rob_val_20;\t// @[rob.scala:308:32]\n reg rob_val_21;\t// @[rob.scala:308:32]\n reg rob_val_22;\t// @[rob.scala:308:32]\n reg rob_val_23;\t// @[rob.scala:308:32]\n reg rob_val_24;\t// @[rob.scala:308:32]\n reg rob_val_25;\t// @[rob.scala:308:32]\n reg rob_val_26;\t// @[rob.scala:308:32]\n reg rob_val_27;\t// @[rob.scala:308:32]\n reg rob_val_28;\t// @[rob.scala:308:32]\n reg rob_val_29;\t// @[rob.scala:308:32]\n reg rob_val_30;\t// @[rob.scala:308:32]\n reg rob_val_31;\t// @[rob.scala:308:32]\n reg rob_bsy_0;\t// @[rob.scala:309:28]\n reg rob_bsy_1;\t// @[rob.scala:309:28]\n reg rob_bsy_2;\t// @[rob.scala:309:28]\n reg rob_bsy_3;\t// @[rob.scala:309:28]\n reg rob_bsy_4;\t// @[rob.scala:309:28]\n reg rob_bsy_5;\t// @[rob.scala:309:28]\n reg rob_bsy_6;\t// @[rob.scala:309:28]\n reg rob_bsy_7;\t// @[rob.scala:309:28]\n reg rob_bsy_8;\t// @[rob.scala:309:28]\n reg rob_bsy_9;\t// @[rob.scala:309:28]\n reg rob_bsy_10;\t// @[rob.scala:309:28]\n reg rob_bsy_11;\t// @[rob.scala:309:28]\n reg rob_bsy_12;\t// @[rob.scala:309:28]\n reg rob_bsy_13;\t// @[rob.scala:309:28]\n reg rob_bsy_14;\t// @[rob.scala:309:28]\n reg rob_bsy_15;\t// @[rob.scala:309:28]\n reg rob_bsy_16;\t// @[rob.scala:309:28]\n reg rob_bsy_17;\t// @[rob.scala:309:28]\n reg rob_bsy_18;\t// @[rob.scala:309:28]\n reg rob_bsy_19;\t// @[rob.scala:309:28]\n reg rob_bsy_20;\t// @[rob.scala:309:28]\n reg rob_bsy_21;\t// @[rob.scala:309:28]\n reg rob_bsy_22;\t// @[rob.scala:309:28]\n reg rob_bsy_23;\t// @[rob.scala:309:28]\n reg rob_bsy_24;\t// @[rob.scala:309:28]\n reg rob_bsy_25;\t// @[rob.scala:309:28]\n reg rob_bsy_26;\t// @[rob.scala:309:28]\n reg rob_bsy_27;\t// @[rob.scala:309:28]\n reg rob_bsy_28;\t// @[rob.scala:309:28]\n reg rob_bsy_29;\t// @[rob.scala:309:28]\n reg rob_bsy_30;\t// @[rob.scala:309:28]\n reg rob_bsy_31;\t// @[rob.scala:309:28]\n reg rob_unsafe_0;\t// @[rob.scala:310:28]\n reg rob_unsafe_1;\t// @[rob.scala:310:28]\n reg rob_unsafe_2;\t// @[rob.scala:310:28]\n reg rob_unsafe_3;\t// @[rob.scala:310:28]\n reg rob_unsafe_4;\t// @[rob.scala:310:28]\n reg rob_unsafe_5;\t// @[rob.scala:310:28]\n reg rob_unsafe_6;\t// @[rob.scala:310:28]\n reg rob_unsafe_7;\t// @[rob.scala:310:28]\n reg rob_unsafe_8;\t// @[rob.scala:310:28]\n reg rob_unsafe_9;\t// @[rob.scala:310:28]\n reg rob_unsafe_10;\t// @[rob.scala:310:28]\n reg rob_unsafe_11;\t// @[rob.scala:310:28]\n reg rob_unsafe_12;\t// @[rob.scala:310:28]\n reg rob_unsafe_13;\t// @[rob.scala:310:28]\n reg rob_unsafe_14;\t// @[rob.scala:310:28]\n reg rob_unsafe_15;\t// @[rob.scala:310:28]\n reg rob_unsafe_16;\t// @[rob.scala:310:28]\n reg rob_unsafe_17;\t// @[rob.scala:310:28]\n reg rob_unsafe_18;\t// @[rob.scala:310:28]\n reg rob_unsafe_19;\t// @[rob.scala:310:28]\n reg rob_unsafe_20;\t// @[rob.scala:310:28]\n reg rob_unsafe_21;\t// @[rob.scala:310:28]\n reg rob_unsafe_22;\t// @[rob.scala:310:28]\n reg rob_unsafe_23;\t// @[rob.scala:310:28]\n reg rob_unsafe_24;\t// @[rob.scala:310:28]\n reg rob_unsafe_25;\t// @[rob.scala:310:28]\n reg rob_unsafe_26;\t// @[rob.scala:310:28]\n reg rob_unsafe_27;\t// @[rob.scala:310:28]\n reg rob_unsafe_28;\t// @[rob.scala:310:28]\n reg rob_unsafe_29;\t// @[rob.scala:310:28]\n reg rob_unsafe_30;\t// @[rob.scala:310:28]\n reg rob_unsafe_31;\t// @[rob.scala:310:28]\n reg [6:0] rob_uop_0_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_0_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_0_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_0_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_0_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_0_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_0_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_0_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_0_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_0_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_0_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_0_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_0_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_0_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_0_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_0_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_0_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_0_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_0_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_0_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_0_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_0_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_0_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_0_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_0_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_0_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_0_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_0_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_0_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_0_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_0_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_0_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_0_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_0_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_0_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_0_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_0_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_0_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_0_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_0_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_0_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_0_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_0_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_0_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_0_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_0_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_0_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_0_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_0_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_0_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_0_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_1_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_1_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_1_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_1_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_1_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_1_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_1_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_1_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_1_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_1_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_1_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_1_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_1_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_1_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_1_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_1_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_1_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_1_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_1_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_1_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_1_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_1_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_1_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_1_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_1_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_1_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_1_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_1_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_1_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_1_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_1_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_1_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_1_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_1_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_1_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_1_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_1_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_1_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_1_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_1_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_1_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_1_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_1_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_1_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_1_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_1_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_1_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_1_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_1_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_1_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_1_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_2_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_2_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_2_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_2_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_2_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_2_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_2_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_2_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_2_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_2_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_2_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_2_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_2_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_2_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_2_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_2_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_2_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_2_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_2_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_2_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_2_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_2_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_2_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_2_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_2_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_2_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_2_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_2_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_2_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_2_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_2_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_2_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_2_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_2_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_2_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_2_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_2_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_2_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_2_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_2_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_2_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_2_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_2_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_2_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_2_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_2_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_2_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_2_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_2_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_2_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_2_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_3_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_3_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_3_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_3_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_3_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_3_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_3_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_3_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_3_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_3_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_3_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_3_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_3_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_3_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_3_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_3_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_3_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_3_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_3_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_3_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_3_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_3_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_3_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_3_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_3_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_3_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_3_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_3_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_3_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_3_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_3_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_3_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_3_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_3_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_3_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_3_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_3_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_3_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_3_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_3_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_3_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_3_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_3_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_3_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_3_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_3_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_3_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_3_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_3_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_3_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_3_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_4_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_4_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_4_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_4_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_4_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_4_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_4_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_4_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_4_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_4_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_4_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_4_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_4_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_4_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_4_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_4_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_4_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_4_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_4_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_4_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_4_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_4_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_4_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_4_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_4_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_4_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_4_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_4_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_4_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_4_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_4_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_4_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_4_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_4_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_4_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_4_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_4_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_4_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_4_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_4_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_4_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_4_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_4_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_4_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_4_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_4_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_4_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_4_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_4_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_4_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_4_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_5_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_5_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_5_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_5_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_5_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_5_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_5_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_5_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_5_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_5_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_5_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_5_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_5_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_5_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_5_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_5_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_5_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_5_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_5_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_5_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_5_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_5_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_5_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_5_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_5_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_5_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_5_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_5_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_5_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_5_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_5_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_5_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_5_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_5_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_5_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_5_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_5_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_5_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_5_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_5_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_5_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_5_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_5_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_5_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_5_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_5_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_5_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_5_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_5_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_5_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_5_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_6_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_6_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_6_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_6_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_6_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_6_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_6_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_6_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_6_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_6_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_6_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_6_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_6_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_6_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_6_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_6_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_6_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_6_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_6_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_6_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_6_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_6_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_6_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_6_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_6_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_6_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_6_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_6_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_6_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_6_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_6_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_6_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_6_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_6_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_6_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_6_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_6_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_6_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_6_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_6_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_6_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_6_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_6_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_6_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_6_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_6_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_6_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_6_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_6_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_6_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_6_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_7_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_7_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_7_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_7_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_7_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_7_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_7_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_7_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_7_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_7_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_7_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_7_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_7_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_7_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_7_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_7_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_7_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_7_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_7_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_7_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_7_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_7_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_7_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_7_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_7_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_7_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_7_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_7_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_7_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_7_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_7_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_7_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_7_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_7_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_7_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_7_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_7_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_7_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_7_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_7_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_7_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_7_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_7_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_7_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_7_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_7_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_7_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_7_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_7_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_7_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_7_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_8_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_8_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_8_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_8_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_8_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_8_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_8_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_8_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_8_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_8_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_8_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_8_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_8_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_8_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_8_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_8_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_8_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_8_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_8_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_8_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_8_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_8_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_8_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_8_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_8_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_8_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_8_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_8_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_8_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_8_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_8_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_8_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_8_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_8_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_8_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_8_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_8_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_8_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_8_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_8_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_8_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_8_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_8_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_8_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_8_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_8_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_8_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_8_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_8_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_8_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_8_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_9_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_9_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_9_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_9_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_9_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_9_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_9_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_9_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_9_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_9_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_9_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_9_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_9_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_9_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_9_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_9_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_9_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_9_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_9_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_9_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_9_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_9_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_9_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_9_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_9_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_9_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_9_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_9_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_9_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_9_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_9_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_9_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_9_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_9_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_9_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_9_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_9_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_9_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_9_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_9_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_9_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_9_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_9_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_9_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_9_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_9_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_9_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_9_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_9_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_9_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_9_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_10_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_10_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_10_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_10_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_10_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_10_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_10_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_10_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_10_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_10_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_10_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_10_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_10_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_10_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_10_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_10_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_10_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_10_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_10_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_10_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_10_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_10_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_10_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_10_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_10_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_10_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_10_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_10_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_10_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_10_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_10_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_10_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_10_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_10_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_10_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_10_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_10_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_10_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_10_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_10_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_10_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_10_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_10_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_10_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_10_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_10_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_10_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_10_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_10_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_10_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_10_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_11_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_11_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_11_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_11_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_11_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_11_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_11_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_11_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_11_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_11_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_11_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_11_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_11_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_11_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_11_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_11_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_11_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_11_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_11_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_11_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_11_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_11_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_11_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_11_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_11_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_11_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_11_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_11_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_11_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_11_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_11_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_11_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_11_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_11_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_11_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_11_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_11_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_11_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_11_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_11_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_11_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_11_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_11_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_11_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_11_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_11_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_11_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_11_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_11_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_11_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_11_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_12_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_12_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_12_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_12_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_12_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_12_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_12_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_12_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_12_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_12_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_12_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_12_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_12_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_12_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_12_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_12_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_12_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_12_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_12_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_12_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_12_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_12_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_12_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_12_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_12_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_12_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_12_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_12_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_12_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_12_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_12_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_12_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_12_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_12_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_12_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_12_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_12_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_12_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_12_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_12_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_12_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_12_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_12_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_12_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_12_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_12_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_12_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_12_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_12_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_12_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_12_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_13_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_13_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_13_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_13_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_13_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_13_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_13_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_13_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_13_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_13_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_13_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_13_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_13_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_13_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_13_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_13_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_13_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_13_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_13_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_13_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_13_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_13_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_13_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_13_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_13_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_13_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_13_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_13_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_13_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_13_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_13_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_13_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_13_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_13_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_13_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_13_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_13_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_13_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_13_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_13_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_13_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_13_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_13_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_13_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_13_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_13_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_13_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_13_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_13_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_13_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_13_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_14_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_14_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_14_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_14_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_14_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_14_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_14_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_14_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_14_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_14_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_14_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_14_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_14_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_14_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_14_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_14_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_14_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_14_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_14_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_14_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_14_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_14_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_14_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_14_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_14_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_14_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_14_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_14_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_14_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_14_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_14_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_14_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_14_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_14_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_14_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_14_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_14_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_14_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_14_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_14_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_14_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_14_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_14_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_14_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_14_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_14_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_14_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_14_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_14_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_14_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_14_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_15_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_15_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_15_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_15_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_15_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_15_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_15_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_15_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_15_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_15_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_15_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_15_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_15_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_15_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_15_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_15_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_15_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_15_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_15_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_15_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_15_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_15_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_15_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_15_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_15_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_15_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_15_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_15_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_15_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_15_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_15_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_15_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_15_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_15_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_15_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_15_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_15_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_15_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_15_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_15_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_15_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_15_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_15_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_15_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_15_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_15_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_15_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_15_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_15_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_15_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_15_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_16_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_16_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_16_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_16_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_16_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_16_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_16_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_16_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_16_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_16_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_16_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_16_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_16_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_16_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_16_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_16_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_16_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_16_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_16_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_16_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_16_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_16_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_16_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_16_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_16_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_16_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_16_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_16_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_16_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_16_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_16_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_16_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_16_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_16_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_16_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_16_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_16_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_16_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_16_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_16_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_16_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_16_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_16_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_16_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_16_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_16_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_16_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_16_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_16_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_16_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_16_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_17_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_17_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_17_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_17_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_17_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_17_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_17_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_17_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_17_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_17_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_17_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_17_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_17_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_17_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_17_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_17_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_17_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_17_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_17_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_17_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_17_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_17_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_17_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_17_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_17_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_17_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_17_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_17_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_17_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_17_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_17_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_17_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_17_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_17_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_17_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_17_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_17_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_17_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_17_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_17_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_17_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_17_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_17_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_17_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_17_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_17_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_17_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_17_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_17_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_17_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_17_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_18_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_18_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_18_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_18_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_18_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_18_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_18_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_18_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_18_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_18_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_18_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_18_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_18_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_18_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_18_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_18_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_18_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_18_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_18_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_18_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_18_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_18_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_18_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_18_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_18_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_18_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_18_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_18_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_18_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_18_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_18_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_18_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_18_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_18_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_18_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_18_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_18_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_18_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_18_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_18_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_18_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_18_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_18_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_18_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_18_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_18_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_18_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_18_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_18_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_18_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_18_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_19_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_19_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_19_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_19_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_19_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_19_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_19_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_19_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_19_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_19_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_19_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_19_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_19_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_19_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_19_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_19_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_19_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_19_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_19_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_19_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_19_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_19_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_19_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_19_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_19_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_19_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_19_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_19_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_19_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_19_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_19_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_19_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_19_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_19_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_19_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_19_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_19_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_19_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_19_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_19_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_19_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_19_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_19_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_19_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_19_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_19_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_19_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_19_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_19_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_19_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_19_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_20_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_20_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_20_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_20_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_20_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_20_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_20_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_20_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_20_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_20_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_20_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_20_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_20_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_20_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_20_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_20_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_20_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_20_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_20_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_20_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_20_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_20_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_20_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_20_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_20_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_20_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_20_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_20_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_20_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_20_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_20_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_20_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_20_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_20_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_20_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_20_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_20_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_20_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_20_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_20_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_20_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_20_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_20_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_20_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_20_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_20_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_20_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_20_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_20_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_20_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_20_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_21_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_21_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_21_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_21_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_21_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_21_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_21_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_21_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_21_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_21_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_21_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_21_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_21_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_21_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_21_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_21_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_21_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_21_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_21_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_21_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_21_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_21_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_21_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_21_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_21_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_21_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_21_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_21_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_21_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_21_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_21_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_21_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_21_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_21_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_21_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_21_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_21_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_21_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_21_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_21_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_21_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_21_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_21_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_21_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_21_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_21_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_21_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_21_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_21_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_21_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_21_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_22_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_22_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_22_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_22_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_22_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_22_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_22_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_22_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_22_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_22_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_22_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_22_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_22_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_22_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_22_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_22_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_22_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_22_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_22_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_22_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_22_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_22_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_22_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_22_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_22_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_22_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_22_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_22_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_22_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_22_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_22_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_22_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_22_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_22_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_22_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_22_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_22_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_22_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_22_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_22_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_22_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_22_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_22_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_22_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_22_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_22_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_22_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_22_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_22_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_22_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_22_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_23_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_23_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_23_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_23_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_23_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_23_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_23_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_23_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_23_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_23_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_23_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_23_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_23_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_23_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_23_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_23_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_23_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_23_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_23_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_23_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_23_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_23_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_23_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_23_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_23_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_23_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_23_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_23_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_23_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_23_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_23_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_23_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_23_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_23_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_23_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_23_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_23_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_23_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_23_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_23_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_23_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_23_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_23_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_23_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_23_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_23_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_23_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_23_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_23_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_23_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_23_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_24_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_24_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_24_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_24_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_24_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_24_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_24_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_24_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_24_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_24_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_24_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_24_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_24_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_24_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_24_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_24_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_24_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_24_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_24_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_24_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_24_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_24_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_24_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_24_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_24_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_24_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_24_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_24_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_24_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_24_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_24_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_24_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_24_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_24_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_24_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_24_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_24_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_24_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_24_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_24_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_24_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_24_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_24_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_24_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_24_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_24_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_24_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_24_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_24_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_24_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_24_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_25_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_25_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_25_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_25_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_25_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_25_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_25_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_25_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_25_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_25_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_25_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_25_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_25_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_25_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_25_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_25_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_25_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_25_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_25_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_25_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_25_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_25_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_25_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_25_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_25_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_25_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_25_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_25_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_25_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_25_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_25_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_25_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_25_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_25_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_25_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_25_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_25_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_25_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_25_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_25_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_25_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_25_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_25_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_25_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_25_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_25_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_25_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_25_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_25_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_25_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_25_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_26_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_26_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_26_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_26_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_26_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_26_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_26_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_26_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_26_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_26_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_26_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_26_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_26_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_26_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_26_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_26_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_26_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_26_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_26_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_26_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_26_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_26_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_26_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_26_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_26_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_26_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_26_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_26_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_26_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_26_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_26_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_26_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_26_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_26_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_26_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_26_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_26_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_26_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_26_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_26_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_26_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_26_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_26_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_26_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_26_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_26_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_26_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_26_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_26_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_26_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_26_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_27_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_27_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_27_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_27_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_27_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_27_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_27_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_27_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_27_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_27_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_27_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_27_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_27_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_27_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_27_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_27_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_27_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_27_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_27_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_27_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_27_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_27_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_27_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_27_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_27_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_27_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_27_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_27_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_27_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_27_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_27_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_27_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_27_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_27_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_27_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_27_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_27_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_27_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_27_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_27_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_27_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_27_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_27_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_27_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_27_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_27_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_27_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_27_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_27_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_27_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_27_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_28_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_28_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_28_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_28_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_28_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_28_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_28_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_28_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_28_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_28_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_28_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_28_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_28_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_28_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_28_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_28_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_28_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_28_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_28_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_28_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_28_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_28_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_28_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_28_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_28_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_28_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_28_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_28_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_28_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_28_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_28_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_28_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_28_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_28_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_28_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_28_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_28_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_28_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_28_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_28_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_28_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_28_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_28_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_28_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_28_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_28_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_28_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_28_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_28_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_28_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_28_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_29_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_29_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_29_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_29_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_29_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_29_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_29_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_29_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_29_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_29_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_29_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_29_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_29_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_29_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_29_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_29_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_29_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_29_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_29_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_29_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_29_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_29_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_29_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_29_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_29_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_29_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_29_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_29_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_29_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_29_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_29_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_29_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_29_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_29_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_29_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_29_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_29_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_29_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_29_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_29_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_29_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_29_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_29_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_29_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_29_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_29_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_29_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_29_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_29_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_29_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_29_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_30_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_30_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_30_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_30_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_30_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_30_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_30_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_30_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_30_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_30_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_30_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_30_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_30_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_30_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_30_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_30_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_30_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_30_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_30_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_30_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_30_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_30_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_30_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_30_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_30_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_30_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_30_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_30_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_30_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_30_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_30_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_30_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_30_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_30_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_30_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_30_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_30_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_30_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_30_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_30_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_30_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_30_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_30_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_30_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_30_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_30_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_30_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_30_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_30_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_30_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_30_debug_tsrc;\t// @[rob.scala:311:28]\n reg [6:0] rob_uop_31_uopc;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_31_inst;\t// @[rob.scala:311:28]\n reg [31:0] rob_uop_31_debug_inst;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_rvc;\t// @[rob.scala:311:28]\n reg [39:0] rob_uop_31_debug_pc;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_31_iq_type;\t// @[rob.scala:311:28]\n reg [9:0] rob_uop_31_fu_code;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_31_ctrl_br_type;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_ctrl_op1_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_31_ctrl_op2_sel;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_31_ctrl_imm_sel;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_31_ctrl_op_fcn;\t// @[rob.scala:311:28]\n reg rob_uop_31_ctrl_fcn_dw;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_31_ctrl_csr_cmd;\t// @[rob.scala:311:28]\n reg rob_uop_31_ctrl_is_load;\t// @[rob.scala:311:28]\n reg rob_uop_31_ctrl_is_sta;\t// @[rob.scala:311:28]\n reg rob_uop_31_ctrl_is_std;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_iw_state;\t// @[rob.scala:311:28]\n reg rob_uop_31_iw_p1_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_31_iw_p2_poisoned;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_br;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_jalr;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_jal;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_sfb;\t// @[rob.scala:311:28]\n reg [7:0] rob_uop_31_br_mask;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_31_br_tag;\t// @[rob.scala:311:28]\n reg [3:0] rob_uop_31_ftq_idx;\t// @[rob.scala:311:28]\n reg rob_uop_31_edge_inst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_pc_lob;\t// @[rob.scala:311:28]\n reg rob_uop_31_taken;\t// @[rob.scala:311:28]\n reg [19:0] rob_uop_31_imm_packed;\t// @[rob.scala:311:28]\n reg [11:0] rob_uop_31_csr_addr;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_31_rob_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_31_ldq_idx;\t// @[rob.scala:311:28]\n reg [2:0] rob_uop_31_stq_idx;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_rxq_idx;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_pdst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_prs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_prs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_prs3;\t// @[rob.scala:311:28]\n reg rob_uop_31_prs1_busy;\t// @[rob.scala:311:28]\n reg rob_uop_31_prs2_busy;\t// @[rob.scala:311:28]\n reg rob_uop_31_prs3_busy;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_stale_pdst;\t// @[rob.scala:311:28]\n reg rob_uop_31_exception;\t// @[rob.scala:311:28]\n reg [63:0] rob_uop_31_exc_cause;\t// @[rob.scala:311:28]\n reg rob_uop_31_bypassable;\t// @[rob.scala:311:28]\n reg [4:0] rob_uop_31_mem_cmd;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_mem_size;\t// @[rob.scala:311:28]\n reg rob_uop_31_mem_signed;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_fence;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_fencei;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_amo;\t// @[rob.scala:311:28]\n reg rob_uop_31_uses_ldq;\t// @[rob.scala:311:28]\n reg rob_uop_31_uses_stq;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_sys_pc2epc;\t// @[rob.scala:311:28]\n reg rob_uop_31_is_unique;\t// @[rob.scala:311:28]\n reg rob_uop_31_flush_on_commit;\t// @[rob.scala:311:28]\n reg rob_uop_31_ldst_is_rs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_ldst;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_lrs1;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_lrs2;\t// @[rob.scala:311:28]\n reg [5:0] rob_uop_31_lrs3;\t// @[rob.scala:311:28]\n reg rob_uop_31_ldst_val;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_dst_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_lrs1_rtype;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_lrs2_rtype;\t// @[rob.scala:311:28]\n reg rob_uop_31_frs3_en;\t// @[rob.scala:311:28]\n reg rob_uop_31_fp_val;\t// @[rob.scala:311:28]\n reg rob_uop_31_fp_single;\t// @[rob.scala:311:28]\n reg rob_uop_31_xcpt_pf_if;\t// @[rob.scala:311:28]\n reg rob_uop_31_xcpt_ae_if;\t// @[rob.scala:311:28]\n reg rob_uop_31_xcpt_ma_if;\t// @[rob.scala:311:28]\n reg rob_uop_31_bp_debug_if;\t// @[rob.scala:311:28]\n reg rob_uop_31_bp_xcpt_if;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_debug_fsrc;\t// @[rob.scala:311:28]\n reg [1:0] rob_uop_31_debug_tsrc;\t// @[rob.scala:311:28]\n reg rob_exception_0;\t// @[rob.scala:312:28]\n reg rob_exception_1;\t// @[rob.scala:312:28]\n reg rob_exception_2;\t// @[rob.scala:312:28]\n reg rob_exception_3;\t// @[rob.scala:312:28]\n reg rob_exception_4;\t// @[rob.scala:312:28]\n reg rob_exception_5;\t// @[rob.scala:312:28]\n reg rob_exception_6;\t// @[rob.scala:312:28]\n reg rob_exception_7;\t// @[rob.scala:312:28]\n reg rob_exception_8;\t// @[rob.scala:312:28]\n reg rob_exception_9;\t// @[rob.scala:312:28]\n reg rob_exception_10;\t// @[rob.scala:312:28]\n reg rob_exception_11;\t// @[rob.scala:312:28]\n reg rob_exception_12;\t// @[rob.scala:312:28]\n reg rob_exception_13;\t// @[rob.scala:312:28]\n reg rob_exception_14;\t// @[rob.scala:312:28]\n reg rob_exception_15;\t// @[rob.scala:312:28]\n reg rob_exception_16;\t// @[rob.scala:312:28]\n reg rob_exception_17;\t// @[rob.scala:312:28]\n reg rob_exception_18;\t// @[rob.scala:312:28]\n reg rob_exception_19;\t// @[rob.scala:312:28]\n reg rob_exception_20;\t// @[rob.scala:312:28]\n reg rob_exception_21;\t// @[rob.scala:312:28]\n reg rob_exception_22;\t// @[rob.scala:312:28]\n reg rob_exception_23;\t// @[rob.scala:312:28]\n reg rob_exception_24;\t// @[rob.scala:312:28]\n reg rob_exception_25;\t// @[rob.scala:312:28]\n reg rob_exception_26;\t// @[rob.scala:312:28]\n reg rob_exception_27;\t// @[rob.scala:312:28]\n reg rob_exception_28;\t// @[rob.scala:312:28]\n reg rob_exception_29;\t// @[rob.scala:312:28]\n reg rob_exception_30;\t// @[rob.scala:312:28]\n reg rob_exception_31;\t// @[rob.scala:312:28]\n reg rob_predicated_0;\t// @[rob.scala:313:29]\n reg rob_predicated_1;\t// @[rob.scala:313:29]\n reg rob_predicated_2;\t// @[rob.scala:313:29]\n reg rob_predicated_3;\t// @[rob.scala:313:29]\n reg rob_predicated_4;\t// @[rob.scala:313:29]\n reg rob_predicated_5;\t// @[rob.scala:313:29]\n reg rob_predicated_6;\t// @[rob.scala:313:29]\n reg rob_predicated_7;\t// @[rob.scala:313:29]\n reg rob_predicated_8;\t// @[rob.scala:313:29]\n reg rob_predicated_9;\t// @[rob.scala:313:29]\n reg rob_predicated_10;\t// @[rob.scala:313:29]\n reg rob_predicated_11;\t// @[rob.scala:313:29]\n reg rob_predicated_12;\t// @[rob.scala:313:29]\n reg rob_predicated_13;\t// @[rob.scala:313:29]\n reg rob_predicated_14;\t// @[rob.scala:313:29]\n reg rob_predicated_15;\t// @[rob.scala:313:29]\n reg rob_predicated_16;\t// @[rob.scala:313:29]\n reg rob_predicated_17;\t// @[rob.scala:313:29]\n reg rob_predicated_18;\t// @[rob.scala:313:29]\n reg rob_predicated_19;\t// @[rob.scala:313:29]\n reg rob_predicated_20;\t// @[rob.scala:313:29]\n reg rob_predicated_21;\t// @[rob.scala:313:29]\n reg rob_predicated_22;\t// @[rob.scala:313:29]\n reg rob_predicated_23;\t// @[rob.scala:313:29]\n reg rob_predicated_24;\t// @[rob.scala:313:29]\n reg rob_predicated_25;\t// @[rob.scala:313:29]\n reg rob_predicated_26;\t// @[rob.scala:313:29]\n reg rob_predicated_27;\t// @[rob.scala:313:29]\n reg rob_predicated_28;\t// @[rob.scala:313:29]\n reg rob_predicated_29;\t// @[rob.scala:313:29]\n reg rob_predicated_30;\t// @[rob.scala:313:29]\n reg rob_predicated_31;\t// @[rob.scala:313:29]\n wire [31:0] _GEN = {{rob_val_31}, {rob_val_30}, {rob_val_29}, {rob_val_28}, {rob_val_27}, {rob_val_26}, {rob_val_25}, {rob_val_24}, {rob_val_23}, {rob_val_22}, {rob_val_21}, {rob_val_20}, {rob_val_19}, {rob_val_18}, {rob_val_17}, {rob_val_16}, {rob_val_15}, {rob_val_14}, {rob_val_13}, {rob_val_12}, {rob_val_11}, {rob_val_10}, {rob_val_9}, {rob_val_8}, {rob_val_7}, {rob_val_6}, {rob_val_5}, {rob_val_4}, {rob_val_3}, {rob_val_2}, {rob_val_1}, {rob_val_0}};\t// @[rob.scala:308:32, :324:31]\n assign rob_tail_vals_0 = _GEN[rob_tail];\t// @[rob.scala:227:29, :248:33, :324:31]\n wire _rob_bsy_T = io_enq_uops_0_is_fence_0 | io_enq_uops_0_is_fencei_0;\t// @[rob.scala:211:7, :325:60]\n wire _rob_bsy_T_1 = ~_rob_bsy_T;\t// @[rob.scala:325:{34,60}]\n wire _rob_unsafe_T = ~io_enq_uops_0_is_fence_0;\t// @[rob.scala:211:7]\n wire _rob_unsafe_T_1 = io_enq_uops_0_uses_stq_0 & _rob_unsafe_T;\t// @[rob.scala:211:7]\n wire _rob_unsafe_T_2 = io_enq_uops_0_uses_ldq_0 | _rob_unsafe_T_1;\t// @[rob.scala:211:7]\n wire _rob_unsafe_T_3 = _rob_unsafe_T_2 | io_enq_uops_0_is_br_0;\t// @[rob.scala:211:7]\n wire _rob_unsafe_T_4 = _rob_unsafe_T_3 | io_enq_uops_0_is_jalr_0;\t// @[rob.scala:211:7]\n wire [31:0] _GEN_0 = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}};\t// @[rob.scala:309:28, :363:26]\n wire _GEN_1 = io_lxcpt_valid_0 & io_lxcpt_bits_cause_0 != 5'h10 & ~reset;\t// @[rob.scala:211:7, :392:{33,66}, :394:15]\n wire [31:0] _GEN_2 = {{rob_unsafe_31}, {rob_unsafe_30}, {rob_unsafe_29}, {rob_unsafe_28}, {rob_unsafe_27}, {rob_unsafe_26}, {rob_unsafe_25}, {rob_unsafe_24}, {rob_unsafe_23}, {rob_unsafe_22}, {rob_unsafe_21}, {rob_unsafe_20}, {rob_unsafe_19}, {rob_unsafe_18}, {rob_unsafe_17}, {rob_unsafe_16}, {rob_unsafe_15}, {rob_unsafe_14}, {rob_unsafe_13}, {rob_unsafe_12}, {rob_unsafe_11}, {rob_unsafe_10}, {rob_unsafe_9}, {rob_unsafe_8}, {rob_unsafe_7}, {rob_unsafe_6}, {rob_unsafe_5}, {rob_unsafe_4}, {rob_unsafe_3}, {rob_unsafe_2}, {rob_unsafe_1}, {rob_unsafe_0}};\t// @[rob.scala:310:28, :394:15]\n assign rob_head_vals_0 = _GEN[rob_head];\t// @[rob.scala:223:29, :247:33, :324:31, :402:49]\n wire [31:0] _GEN_3 = {{rob_exception_31}, {rob_exception_30}, {rob_exception_29}, {rob_exception_28}, {rob_exception_27}, {rob_exception_26}, {rob_exception_25}, {rob_exception_24}, {rob_exception_23}, {rob_exception_22}, {rob_exception_21}, {rob_exception_20}, {rob_exception_19}, {rob_exception_18}, {rob_exception_17}, {rob_exception_16}, {rob_exception_15}, {rob_exception_14}, {rob_exception_13}, {rob_exception_12}, {rob_exception_11}, {rob_exception_10}, {rob_exception_9}, {rob_exception_8}, {rob_exception_7}, {rob_exception_6}, {rob_exception_5}, {rob_exception_4}, {rob_exception_3}, {rob_exception_2}, {rob_exception_1}, {rob_exception_0}};\t// @[rob.scala:312:28, :402:49]\n assign _can_throw_exception_0_T = rob_head_vals_0 & _GEN_3[rob_head];\t// @[rob.scala:223:29, :247:33, :402:49]\n assign can_throw_exception_0 = _can_throw_exception_0_T;\t// @[rob.scala:244:33, :402:49]\n wire _can_commit_0_T = ~_GEN_0[rob_head];\t// @[rob.scala:223:29, :363:26, :408:43]\n wire _can_commit_0_T_1 = rob_head_vals_0 & _can_commit_0_T;\t// @[rob.scala:247:33, :408:{40,43}]\n wire _can_commit_0_T_2 = ~io_csr_stall_0;\t// @[rob.scala:211:7, :408:67]\n assign _can_commit_0_T_3 = _can_commit_0_T_1 & _can_commit_0_T_2;\t// @[rob.scala:408:{40,64,67}]\n assign can_commit_0 = _can_commit_0_T_3;\t// @[rob.scala:243:33, :408:64]\n wire [31:0] _GEN_4 = {{rob_predicated_31}, {rob_predicated_30}, {rob_predicated_29}, {rob_predicated_28}, {rob_predicated_27}, {rob_predicated_26}, {rob_predicated_25}, {rob_predicated_24}, {rob_predicated_23}, {rob_predicated_22}, {rob_predicated_21}, {rob_predicated_20}, {rob_predicated_19}, {rob_predicated_18}, {rob_predicated_17}, {rob_predicated_16}, {rob_predicated_15}, {rob_predicated_14}, {rob_predicated_13}, {rob_predicated_12}, {rob_predicated_11}, {rob_predicated_10}, {rob_predicated_9}, {rob_predicated_8}, {rob_predicated_7}, {rob_predicated_6}, {rob_predicated_5}, {rob_predicated_4}, {rob_predicated_3}, {rob_predicated_2}, {rob_predicated_1}, {rob_predicated_0}};\t// @[rob.scala:313:29, :414:51]\n wire _io_commit_arch_valids_0_T = ~_GEN_4[com_idx];\t// @[rob.scala:235:20, :414:51]\n assign _io_commit_arch_valids_0_T_1 = will_commit_0 & _io_commit_arch_valids_0_T;\t// @[rob.scala:242:33, :414:{48,51}]\n assign io_commit_arch_valids_0_0 = _io_commit_arch_valids_0_T_1;\t// @[rob.scala:211:7, :414:48]\n wire [31:0][6:0] _GEN_5 = {{rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_uopc_0 = _GEN_5[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][31:0] _GEN_6 = {{rob_uop_31_inst}, {rob_uop_30_inst}, {rob_uop_29_inst}, {rob_uop_28_inst}, {rob_uop_27_inst}, {rob_uop_26_inst}, {rob_uop_25_inst}, {rob_uop_24_inst}, {rob_uop_23_inst}, {rob_uop_22_inst}, {rob_uop_21_inst}, {rob_uop_20_inst}, {rob_uop_19_inst}, {rob_uop_18_inst}, {rob_uop_17_inst}, {rob_uop_16_inst}, {rob_uop_15_inst}, {rob_uop_14_inst}, {rob_uop_13_inst}, {rob_uop_12_inst}, {rob_uop_11_inst}, {rob_uop_10_inst}, {rob_uop_9_inst}, {rob_uop_8_inst}, {rob_uop_7_inst}, {rob_uop_6_inst}, {rob_uop_5_inst}, {rob_uop_4_inst}, {rob_uop_3_inst}, {rob_uop_2_inst}, {rob_uop_1_inst}, {rob_uop_0_inst}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_inst_0 = _GEN_6[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][31:0] _GEN_7 = {{rob_uop_31_debug_inst}, {rob_uop_30_debug_inst}, {rob_uop_29_debug_inst}, {rob_uop_28_debug_inst}, {rob_uop_27_debug_inst}, {rob_uop_26_debug_inst}, {rob_uop_25_debug_inst}, {rob_uop_24_debug_inst}, {rob_uop_23_debug_inst}, {rob_uop_22_debug_inst}, {rob_uop_21_debug_inst}, {rob_uop_20_debug_inst}, {rob_uop_19_debug_inst}, {rob_uop_18_debug_inst}, {rob_uop_17_debug_inst}, {rob_uop_16_debug_inst}, {rob_uop_15_debug_inst}, {rob_uop_14_debug_inst}, {rob_uop_13_debug_inst}, {rob_uop_12_debug_inst}, {rob_uop_11_debug_inst}, {rob_uop_10_debug_inst}, {rob_uop_9_debug_inst}, {rob_uop_8_debug_inst}, {rob_uop_7_debug_inst}, {rob_uop_6_debug_inst}, {rob_uop_5_debug_inst}, {rob_uop_4_debug_inst}, {rob_uop_3_debug_inst}, {rob_uop_2_debug_inst}, {rob_uop_1_debug_inst}, {rob_uop_0_debug_inst}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_debug_inst_0 = _GEN_7[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_8 = {{rob_uop_31_is_rvc}, {rob_uop_30_is_rvc}, {rob_uop_29_is_rvc}, {rob_uop_28_is_rvc}, {rob_uop_27_is_rvc}, {rob_uop_26_is_rvc}, {rob_uop_25_is_rvc}, {rob_uop_24_is_rvc}, {rob_uop_23_is_rvc}, {rob_uop_22_is_rvc}, {rob_uop_21_is_rvc}, {rob_uop_20_is_rvc}, {rob_uop_19_is_rvc}, {rob_uop_18_is_rvc}, {rob_uop_17_is_rvc}, {rob_uop_16_is_rvc}, {rob_uop_15_is_rvc}, {rob_uop_14_is_rvc}, {rob_uop_13_is_rvc}, {rob_uop_12_is_rvc}, {rob_uop_11_is_rvc}, {rob_uop_10_is_rvc}, {rob_uop_9_is_rvc}, {rob_uop_8_is_rvc}, {rob_uop_7_is_rvc}, {rob_uop_6_is_rvc}, {rob_uop_5_is_rvc}, {rob_uop_4_is_rvc}, {rob_uop_3_is_rvc}, {rob_uop_2_is_rvc}, {rob_uop_1_is_rvc}, {rob_uop_0_is_rvc}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_rvc_0 = _GEN_8[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][39:0] _GEN_9 = {{rob_uop_31_debug_pc}, {rob_uop_30_debug_pc}, {rob_uop_29_debug_pc}, {rob_uop_28_debug_pc}, {rob_uop_27_debug_pc}, {rob_uop_26_debug_pc}, {rob_uop_25_debug_pc}, {rob_uop_24_debug_pc}, {rob_uop_23_debug_pc}, {rob_uop_22_debug_pc}, {rob_uop_21_debug_pc}, {rob_uop_20_debug_pc}, {rob_uop_19_debug_pc}, {rob_uop_18_debug_pc}, {rob_uop_17_debug_pc}, {rob_uop_16_debug_pc}, {rob_uop_15_debug_pc}, {rob_uop_14_debug_pc}, {rob_uop_13_debug_pc}, {rob_uop_12_debug_pc}, {rob_uop_11_debug_pc}, {rob_uop_10_debug_pc}, {rob_uop_9_debug_pc}, {rob_uop_8_debug_pc}, {rob_uop_7_debug_pc}, {rob_uop_6_debug_pc}, {rob_uop_5_debug_pc}, {rob_uop_4_debug_pc}, {rob_uop_3_debug_pc}, {rob_uop_2_debug_pc}, {rob_uop_1_debug_pc}, {rob_uop_0_debug_pc}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_debug_pc_0 = _GEN_9[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][2:0] _GEN_10 = {{rob_uop_31_iq_type}, {rob_uop_30_iq_type}, {rob_uop_29_iq_type}, {rob_uop_28_iq_type}, {rob_uop_27_iq_type}, {rob_uop_26_iq_type}, {rob_uop_25_iq_type}, {rob_uop_24_iq_type}, {rob_uop_23_iq_type}, {rob_uop_22_iq_type}, {rob_uop_21_iq_type}, {rob_uop_20_iq_type}, {rob_uop_19_iq_type}, {rob_uop_18_iq_type}, {rob_uop_17_iq_type}, {rob_uop_16_iq_type}, {rob_uop_15_iq_type}, {rob_uop_14_iq_type}, {rob_uop_13_iq_type}, {rob_uop_12_iq_type}, {rob_uop_11_iq_type}, {rob_uop_10_iq_type}, {rob_uop_9_iq_type}, {rob_uop_8_iq_type}, {rob_uop_7_iq_type}, {rob_uop_6_iq_type}, {rob_uop_5_iq_type}, {rob_uop_4_iq_type}, {rob_uop_3_iq_type}, {rob_uop_2_iq_type}, {rob_uop_1_iq_type}, {rob_uop_0_iq_type}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_iq_type_0 = _GEN_10[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][9:0] _GEN_11 = {{rob_uop_31_fu_code}, {rob_uop_30_fu_code}, {rob_uop_29_fu_code}, {rob_uop_28_fu_code}, {rob_uop_27_fu_code}, {rob_uop_26_fu_code}, {rob_uop_25_fu_code}, {rob_uop_24_fu_code}, {rob_uop_23_fu_code}, {rob_uop_22_fu_code}, {rob_uop_21_fu_code}, {rob_uop_20_fu_code}, {rob_uop_19_fu_code}, {rob_uop_18_fu_code}, {rob_uop_17_fu_code}, {rob_uop_16_fu_code}, {rob_uop_15_fu_code}, {rob_uop_14_fu_code}, {rob_uop_13_fu_code}, {rob_uop_12_fu_code}, {rob_uop_11_fu_code}, {rob_uop_10_fu_code}, {rob_uop_9_fu_code}, {rob_uop_8_fu_code}, {rob_uop_7_fu_code}, {rob_uop_6_fu_code}, {rob_uop_5_fu_code}, {rob_uop_4_fu_code}, {rob_uop_3_fu_code}, {rob_uop_2_fu_code}, {rob_uop_1_fu_code}, {rob_uop_0_fu_code}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_fu_code_0 = _GEN_11[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][3:0] _GEN_12 = {{rob_uop_31_ctrl_br_type}, {rob_uop_30_ctrl_br_type}, {rob_uop_29_ctrl_br_type}, {rob_uop_28_ctrl_br_type}, {rob_uop_27_ctrl_br_type}, {rob_uop_26_ctrl_br_type}, {rob_uop_25_ctrl_br_type}, {rob_uop_24_ctrl_br_type}, {rob_uop_23_ctrl_br_type}, {rob_uop_22_ctrl_br_type}, {rob_uop_21_ctrl_br_type}, {rob_uop_20_ctrl_br_type}, {rob_uop_19_ctrl_br_type}, {rob_uop_18_ctrl_br_type}, {rob_uop_17_ctrl_br_type}, {rob_uop_16_ctrl_br_type}, {rob_uop_15_ctrl_br_type}, {rob_uop_14_ctrl_br_type}, {rob_uop_13_ctrl_br_type}, {rob_uop_12_ctrl_br_type}, {rob_uop_11_ctrl_br_type}, {rob_uop_10_ctrl_br_type}, {rob_uop_9_ctrl_br_type}, {rob_uop_8_ctrl_br_type}, {rob_uop_7_ctrl_br_type}, {rob_uop_6_ctrl_br_type}, {rob_uop_5_ctrl_br_type}, {rob_uop_4_ctrl_br_type}, {rob_uop_3_ctrl_br_type}, {rob_uop_2_ctrl_br_type}, {rob_uop_1_ctrl_br_type}, {rob_uop_0_ctrl_br_type}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_br_type_0 = _GEN_12[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_13 = {{rob_uop_31_ctrl_op1_sel}, {rob_uop_30_ctrl_op1_sel}, {rob_uop_29_ctrl_op1_sel}, {rob_uop_28_ctrl_op1_sel}, {rob_uop_27_ctrl_op1_sel}, {rob_uop_26_ctrl_op1_sel}, {rob_uop_25_ctrl_op1_sel}, {rob_uop_24_ctrl_op1_sel}, {rob_uop_23_ctrl_op1_sel}, {rob_uop_22_ctrl_op1_sel}, {rob_uop_21_ctrl_op1_sel}, {rob_uop_20_ctrl_op1_sel}, {rob_uop_19_ctrl_op1_sel}, {rob_uop_18_ctrl_op1_sel}, {rob_uop_17_ctrl_op1_sel}, {rob_uop_16_ctrl_op1_sel}, {rob_uop_15_ctrl_op1_sel}, {rob_uop_14_ctrl_op1_sel}, {rob_uop_13_ctrl_op1_sel}, {rob_uop_12_ctrl_op1_sel}, {rob_uop_11_ctrl_op1_sel}, {rob_uop_10_ctrl_op1_sel}, {rob_uop_9_ctrl_op1_sel}, {rob_uop_8_ctrl_op1_sel}, {rob_uop_7_ctrl_op1_sel}, {rob_uop_6_ctrl_op1_sel}, {rob_uop_5_ctrl_op1_sel}, {rob_uop_4_ctrl_op1_sel}, {rob_uop_3_ctrl_op1_sel}, {rob_uop_2_ctrl_op1_sel}, {rob_uop_1_ctrl_op1_sel}, {rob_uop_0_ctrl_op1_sel}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_op1_sel_0 = _GEN_13[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][2:0] _GEN_14 = {{rob_uop_31_ctrl_op2_sel}, {rob_uop_30_ctrl_op2_sel}, {rob_uop_29_ctrl_op2_sel}, {rob_uop_28_ctrl_op2_sel}, {rob_uop_27_ctrl_op2_sel}, {rob_uop_26_ctrl_op2_sel}, {rob_uop_25_ctrl_op2_sel}, {rob_uop_24_ctrl_op2_sel}, {rob_uop_23_ctrl_op2_sel}, {rob_uop_22_ctrl_op2_sel}, {rob_uop_21_ctrl_op2_sel}, {rob_uop_20_ctrl_op2_sel}, {rob_uop_19_ctrl_op2_sel}, {rob_uop_18_ctrl_op2_sel}, {rob_uop_17_ctrl_op2_sel}, {rob_uop_16_ctrl_op2_sel}, {rob_uop_15_ctrl_op2_sel}, {rob_uop_14_ctrl_op2_sel}, {rob_uop_13_ctrl_op2_sel}, {rob_uop_12_ctrl_op2_sel}, {rob_uop_11_ctrl_op2_sel}, {rob_uop_10_ctrl_op2_sel}, {rob_uop_9_ctrl_op2_sel}, {rob_uop_8_ctrl_op2_sel}, {rob_uop_7_ctrl_op2_sel}, {rob_uop_6_ctrl_op2_sel}, {rob_uop_5_ctrl_op2_sel}, {rob_uop_4_ctrl_op2_sel}, {rob_uop_3_ctrl_op2_sel}, {rob_uop_2_ctrl_op2_sel}, {rob_uop_1_ctrl_op2_sel}, {rob_uop_0_ctrl_op2_sel}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_op2_sel_0 = _GEN_14[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][2:0] _GEN_15 = {{rob_uop_31_ctrl_imm_sel}, {rob_uop_30_ctrl_imm_sel}, {rob_uop_29_ctrl_imm_sel}, {rob_uop_28_ctrl_imm_sel}, {rob_uop_27_ctrl_imm_sel}, {rob_uop_26_ctrl_imm_sel}, {rob_uop_25_ctrl_imm_sel}, {rob_uop_24_ctrl_imm_sel}, {rob_uop_23_ctrl_imm_sel}, {rob_uop_22_ctrl_imm_sel}, {rob_uop_21_ctrl_imm_sel}, {rob_uop_20_ctrl_imm_sel}, {rob_uop_19_ctrl_imm_sel}, {rob_uop_18_ctrl_imm_sel}, {rob_uop_17_ctrl_imm_sel}, {rob_uop_16_ctrl_imm_sel}, {rob_uop_15_ctrl_imm_sel}, {rob_uop_14_ctrl_imm_sel}, {rob_uop_13_ctrl_imm_sel}, {rob_uop_12_ctrl_imm_sel}, {rob_uop_11_ctrl_imm_sel}, {rob_uop_10_ctrl_imm_sel}, {rob_uop_9_ctrl_imm_sel}, {rob_uop_8_ctrl_imm_sel}, {rob_uop_7_ctrl_imm_sel}, {rob_uop_6_ctrl_imm_sel}, {rob_uop_5_ctrl_imm_sel}, {rob_uop_4_ctrl_imm_sel}, {rob_uop_3_ctrl_imm_sel}, {rob_uop_2_ctrl_imm_sel}, {rob_uop_1_ctrl_imm_sel}, {rob_uop_0_ctrl_imm_sel}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_imm_sel_0 = _GEN_15[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][4:0] _GEN_16 = {{rob_uop_31_ctrl_op_fcn}, {rob_uop_30_ctrl_op_fcn}, {rob_uop_29_ctrl_op_fcn}, {rob_uop_28_ctrl_op_fcn}, {rob_uop_27_ctrl_op_fcn}, {rob_uop_26_ctrl_op_fcn}, {rob_uop_25_ctrl_op_fcn}, {rob_uop_24_ctrl_op_fcn}, {rob_uop_23_ctrl_op_fcn}, {rob_uop_22_ctrl_op_fcn}, {rob_uop_21_ctrl_op_fcn}, {rob_uop_20_ctrl_op_fcn}, {rob_uop_19_ctrl_op_fcn}, {rob_uop_18_ctrl_op_fcn}, {rob_uop_17_ctrl_op_fcn}, {rob_uop_16_ctrl_op_fcn}, {rob_uop_15_ctrl_op_fcn}, {rob_uop_14_ctrl_op_fcn}, {rob_uop_13_ctrl_op_fcn}, {rob_uop_12_ctrl_op_fcn}, {rob_uop_11_ctrl_op_fcn}, {rob_uop_10_ctrl_op_fcn}, {rob_uop_9_ctrl_op_fcn}, {rob_uop_8_ctrl_op_fcn}, {rob_uop_7_ctrl_op_fcn}, {rob_uop_6_ctrl_op_fcn}, {rob_uop_5_ctrl_op_fcn}, {rob_uop_4_ctrl_op_fcn}, {rob_uop_3_ctrl_op_fcn}, {rob_uop_2_ctrl_op_fcn}, {rob_uop_1_ctrl_op_fcn}, {rob_uop_0_ctrl_op_fcn}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_op_fcn_0 = _GEN_16[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_17 = {{rob_uop_31_ctrl_fcn_dw}, {rob_uop_30_ctrl_fcn_dw}, {rob_uop_29_ctrl_fcn_dw}, {rob_uop_28_ctrl_fcn_dw}, {rob_uop_27_ctrl_fcn_dw}, {rob_uop_26_ctrl_fcn_dw}, {rob_uop_25_ctrl_fcn_dw}, {rob_uop_24_ctrl_fcn_dw}, {rob_uop_23_ctrl_fcn_dw}, {rob_uop_22_ctrl_fcn_dw}, {rob_uop_21_ctrl_fcn_dw}, {rob_uop_20_ctrl_fcn_dw}, {rob_uop_19_ctrl_fcn_dw}, {rob_uop_18_ctrl_fcn_dw}, {rob_uop_17_ctrl_fcn_dw}, {rob_uop_16_ctrl_fcn_dw}, {rob_uop_15_ctrl_fcn_dw}, {rob_uop_14_ctrl_fcn_dw}, {rob_uop_13_ctrl_fcn_dw}, {rob_uop_12_ctrl_fcn_dw}, {rob_uop_11_ctrl_fcn_dw}, {rob_uop_10_ctrl_fcn_dw}, {rob_uop_9_ctrl_fcn_dw}, {rob_uop_8_ctrl_fcn_dw}, {rob_uop_7_ctrl_fcn_dw}, {rob_uop_6_ctrl_fcn_dw}, {rob_uop_5_ctrl_fcn_dw}, {rob_uop_4_ctrl_fcn_dw}, {rob_uop_3_ctrl_fcn_dw}, {rob_uop_2_ctrl_fcn_dw}, {rob_uop_1_ctrl_fcn_dw}, {rob_uop_0_ctrl_fcn_dw}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_fcn_dw_0 = _GEN_17[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][2:0] _GEN_18 = {{rob_uop_31_ctrl_csr_cmd}, {rob_uop_30_ctrl_csr_cmd}, {rob_uop_29_ctrl_csr_cmd}, {rob_uop_28_ctrl_csr_cmd}, {rob_uop_27_ctrl_csr_cmd}, {rob_uop_26_ctrl_csr_cmd}, {rob_uop_25_ctrl_csr_cmd}, {rob_uop_24_ctrl_csr_cmd}, {rob_uop_23_ctrl_csr_cmd}, {rob_uop_22_ctrl_csr_cmd}, {rob_uop_21_ctrl_csr_cmd}, {rob_uop_20_ctrl_csr_cmd}, {rob_uop_19_ctrl_csr_cmd}, {rob_uop_18_ctrl_csr_cmd}, {rob_uop_17_ctrl_csr_cmd}, {rob_uop_16_ctrl_csr_cmd}, {rob_uop_15_ctrl_csr_cmd}, {rob_uop_14_ctrl_csr_cmd}, {rob_uop_13_ctrl_csr_cmd}, {rob_uop_12_ctrl_csr_cmd}, {rob_uop_11_ctrl_csr_cmd}, {rob_uop_10_ctrl_csr_cmd}, {rob_uop_9_ctrl_csr_cmd}, {rob_uop_8_ctrl_csr_cmd}, {rob_uop_7_ctrl_csr_cmd}, {rob_uop_6_ctrl_csr_cmd}, {rob_uop_5_ctrl_csr_cmd}, {rob_uop_4_ctrl_csr_cmd}, {rob_uop_3_ctrl_csr_cmd}, {rob_uop_2_ctrl_csr_cmd}, {rob_uop_1_ctrl_csr_cmd}, {rob_uop_0_ctrl_csr_cmd}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_csr_cmd_0 = _GEN_18[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_19 = {{rob_uop_31_ctrl_is_load}, {rob_uop_30_ctrl_is_load}, {rob_uop_29_ctrl_is_load}, {rob_uop_28_ctrl_is_load}, {rob_uop_27_ctrl_is_load}, {rob_uop_26_ctrl_is_load}, {rob_uop_25_ctrl_is_load}, {rob_uop_24_ctrl_is_load}, {rob_uop_23_ctrl_is_load}, {rob_uop_22_ctrl_is_load}, {rob_uop_21_ctrl_is_load}, {rob_uop_20_ctrl_is_load}, {rob_uop_19_ctrl_is_load}, {rob_uop_18_ctrl_is_load}, {rob_uop_17_ctrl_is_load}, {rob_uop_16_ctrl_is_load}, {rob_uop_15_ctrl_is_load}, {rob_uop_14_ctrl_is_load}, {rob_uop_13_ctrl_is_load}, {rob_uop_12_ctrl_is_load}, {rob_uop_11_ctrl_is_load}, {rob_uop_10_ctrl_is_load}, {rob_uop_9_ctrl_is_load}, {rob_uop_8_ctrl_is_load}, {rob_uop_7_ctrl_is_load}, {rob_uop_6_ctrl_is_load}, {rob_uop_5_ctrl_is_load}, {rob_uop_4_ctrl_is_load}, {rob_uop_3_ctrl_is_load}, {rob_uop_2_ctrl_is_load}, {rob_uop_1_ctrl_is_load}, {rob_uop_0_ctrl_is_load}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_is_load_0 = _GEN_19[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_20 = {{rob_uop_31_ctrl_is_sta}, {rob_uop_30_ctrl_is_sta}, {rob_uop_29_ctrl_is_sta}, {rob_uop_28_ctrl_is_sta}, {rob_uop_27_ctrl_is_sta}, {rob_uop_26_ctrl_is_sta}, {rob_uop_25_ctrl_is_sta}, {rob_uop_24_ctrl_is_sta}, {rob_uop_23_ctrl_is_sta}, {rob_uop_22_ctrl_is_sta}, {rob_uop_21_ctrl_is_sta}, {rob_uop_20_ctrl_is_sta}, {rob_uop_19_ctrl_is_sta}, {rob_uop_18_ctrl_is_sta}, {rob_uop_17_ctrl_is_sta}, {rob_uop_16_ctrl_is_sta}, {rob_uop_15_ctrl_is_sta}, {rob_uop_14_ctrl_is_sta}, {rob_uop_13_ctrl_is_sta}, {rob_uop_12_ctrl_is_sta}, {rob_uop_11_ctrl_is_sta}, {rob_uop_10_ctrl_is_sta}, {rob_uop_9_ctrl_is_sta}, {rob_uop_8_ctrl_is_sta}, {rob_uop_7_ctrl_is_sta}, {rob_uop_6_ctrl_is_sta}, {rob_uop_5_ctrl_is_sta}, {rob_uop_4_ctrl_is_sta}, {rob_uop_3_ctrl_is_sta}, {rob_uop_2_ctrl_is_sta}, {rob_uop_1_ctrl_is_sta}, {rob_uop_0_ctrl_is_sta}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_is_sta_0 = _GEN_20[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_21 = {{rob_uop_31_ctrl_is_std}, {rob_uop_30_ctrl_is_std}, {rob_uop_29_ctrl_is_std}, {rob_uop_28_ctrl_is_std}, {rob_uop_27_ctrl_is_std}, {rob_uop_26_ctrl_is_std}, {rob_uop_25_ctrl_is_std}, {rob_uop_24_ctrl_is_std}, {rob_uop_23_ctrl_is_std}, {rob_uop_22_ctrl_is_std}, {rob_uop_21_ctrl_is_std}, {rob_uop_20_ctrl_is_std}, {rob_uop_19_ctrl_is_std}, {rob_uop_18_ctrl_is_std}, {rob_uop_17_ctrl_is_std}, {rob_uop_16_ctrl_is_std}, {rob_uop_15_ctrl_is_std}, {rob_uop_14_ctrl_is_std}, {rob_uop_13_ctrl_is_std}, {rob_uop_12_ctrl_is_std}, {rob_uop_11_ctrl_is_std}, {rob_uop_10_ctrl_is_std}, {rob_uop_9_ctrl_is_std}, {rob_uop_8_ctrl_is_std}, {rob_uop_7_ctrl_is_std}, {rob_uop_6_ctrl_is_std}, {rob_uop_5_ctrl_is_std}, {rob_uop_4_ctrl_is_std}, {rob_uop_3_ctrl_is_std}, {rob_uop_2_ctrl_is_std}, {rob_uop_1_ctrl_is_std}, {rob_uop_0_ctrl_is_std}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ctrl_is_std_0 = _GEN_21[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_22 = {{rob_uop_31_iw_state}, {rob_uop_30_iw_state}, {rob_uop_29_iw_state}, {rob_uop_28_iw_state}, {rob_uop_27_iw_state}, {rob_uop_26_iw_state}, {rob_uop_25_iw_state}, {rob_uop_24_iw_state}, {rob_uop_23_iw_state}, {rob_uop_22_iw_state}, {rob_uop_21_iw_state}, {rob_uop_20_iw_state}, {rob_uop_19_iw_state}, {rob_uop_18_iw_state}, {rob_uop_17_iw_state}, {rob_uop_16_iw_state}, {rob_uop_15_iw_state}, {rob_uop_14_iw_state}, {rob_uop_13_iw_state}, {rob_uop_12_iw_state}, {rob_uop_11_iw_state}, {rob_uop_10_iw_state}, {rob_uop_9_iw_state}, {rob_uop_8_iw_state}, {rob_uop_7_iw_state}, {rob_uop_6_iw_state}, {rob_uop_5_iw_state}, {rob_uop_4_iw_state}, {rob_uop_3_iw_state}, {rob_uop_2_iw_state}, {rob_uop_1_iw_state}, {rob_uop_0_iw_state}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_iw_state_0 = _GEN_22[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_23 = {{rob_uop_31_iw_p1_poisoned}, {rob_uop_30_iw_p1_poisoned}, {rob_uop_29_iw_p1_poisoned}, {rob_uop_28_iw_p1_poisoned}, {rob_uop_27_iw_p1_poisoned}, {rob_uop_26_iw_p1_poisoned}, {rob_uop_25_iw_p1_poisoned}, {rob_uop_24_iw_p1_poisoned}, {rob_uop_23_iw_p1_poisoned}, {rob_uop_22_iw_p1_poisoned}, {rob_uop_21_iw_p1_poisoned}, {rob_uop_20_iw_p1_poisoned}, {rob_uop_19_iw_p1_poisoned}, {rob_uop_18_iw_p1_poisoned}, {rob_uop_17_iw_p1_poisoned}, {rob_uop_16_iw_p1_poisoned}, {rob_uop_15_iw_p1_poisoned}, {rob_uop_14_iw_p1_poisoned}, {rob_uop_13_iw_p1_poisoned}, {rob_uop_12_iw_p1_poisoned}, {rob_uop_11_iw_p1_poisoned}, {rob_uop_10_iw_p1_poisoned}, {rob_uop_9_iw_p1_poisoned}, {rob_uop_8_iw_p1_poisoned}, {rob_uop_7_iw_p1_poisoned}, {rob_uop_6_iw_p1_poisoned}, {rob_uop_5_iw_p1_poisoned}, {rob_uop_4_iw_p1_poisoned}, {rob_uop_3_iw_p1_poisoned}, {rob_uop_2_iw_p1_poisoned}, {rob_uop_1_iw_p1_poisoned}, {rob_uop_0_iw_p1_poisoned}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_iw_p1_poisoned_0 = _GEN_23[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_24 = {{rob_uop_31_iw_p2_poisoned}, {rob_uop_30_iw_p2_poisoned}, {rob_uop_29_iw_p2_poisoned}, {rob_uop_28_iw_p2_poisoned}, {rob_uop_27_iw_p2_poisoned}, {rob_uop_26_iw_p2_poisoned}, {rob_uop_25_iw_p2_poisoned}, {rob_uop_24_iw_p2_poisoned}, {rob_uop_23_iw_p2_poisoned}, {rob_uop_22_iw_p2_poisoned}, {rob_uop_21_iw_p2_poisoned}, {rob_uop_20_iw_p2_poisoned}, {rob_uop_19_iw_p2_poisoned}, {rob_uop_18_iw_p2_poisoned}, {rob_uop_17_iw_p2_poisoned}, {rob_uop_16_iw_p2_poisoned}, {rob_uop_15_iw_p2_poisoned}, {rob_uop_14_iw_p2_poisoned}, {rob_uop_13_iw_p2_poisoned}, {rob_uop_12_iw_p2_poisoned}, {rob_uop_11_iw_p2_poisoned}, {rob_uop_10_iw_p2_poisoned}, {rob_uop_9_iw_p2_poisoned}, {rob_uop_8_iw_p2_poisoned}, {rob_uop_7_iw_p2_poisoned}, {rob_uop_6_iw_p2_poisoned}, {rob_uop_5_iw_p2_poisoned}, {rob_uop_4_iw_p2_poisoned}, {rob_uop_3_iw_p2_poisoned}, {rob_uop_2_iw_p2_poisoned}, {rob_uop_1_iw_p2_poisoned}, {rob_uop_0_iw_p2_poisoned}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_iw_p2_poisoned_0 = _GEN_24[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_25 = {{rob_uop_31_is_br}, {rob_uop_30_is_br}, {rob_uop_29_is_br}, {rob_uop_28_is_br}, {rob_uop_27_is_br}, {rob_uop_26_is_br}, {rob_uop_25_is_br}, {rob_uop_24_is_br}, {rob_uop_23_is_br}, {rob_uop_22_is_br}, {rob_uop_21_is_br}, {rob_uop_20_is_br}, {rob_uop_19_is_br}, {rob_uop_18_is_br}, {rob_uop_17_is_br}, {rob_uop_16_is_br}, {rob_uop_15_is_br}, {rob_uop_14_is_br}, {rob_uop_13_is_br}, {rob_uop_12_is_br}, {rob_uop_11_is_br}, {rob_uop_10_is_br}, {rob_uop_9_is_br}, {rob_uop_8_is_br}, {rob_uop_7_is_br}, {rob_uop_6_is_br}, {rob_uop_5_is_br}, {rob_uop_4_is_br}, {rob_uop_3_is_br}, {rob_uop_2_is_br}, {rob_uop_1_is_br}, {rob_uop_0_is_br}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_br_0 = _GEN_25[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_26 = {{rob_uop_31_is_jalr}, {rob_uop_30_is_jalr}, {rob_uop_29_is_jalr}, {rob_uop_28_is_jalr}, {rob_uop_27_is_jalr}, {rob_uop_26_is_jalr}, {rob_uop_25_is_jalr}, {rob_uop_24_is_jalr}, {rob_uop_23_is_jalr}, {rob_uop_22_is_jalr}, {rob_uop_21_is_jalr}, {rob_uop_20_is_jalr}, {rob_uop_19_is_jalr}, {rob_uop_18_is_jalr}, {rob_uop_17_is_jalr}, {rob_uop_16_is_jalr}, {rob_uop_15_is_jalr}, {rob_uop_14_is_jalr}, {rob_uop_13_is_jalr}, {rob_uop_12_is_jalr}, {rob_uop_11_is_jalr}, {rob_uop_10_is_jalr}, {rob_uop_9_is_jalr}, {rob_uop_8_is_jalr}, {rob_uop_7_is_jalr}, {rob_uop_6_is_jalr}, {rob_uop_5_is_jalr}, {rob_uop_4_is_jalr}, {rob_uop_3_is_jalr}, {rob_uop_2_is_jalr}, {rob_uop_1_is_jalr}, {rob_uop_0_is_jalr}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_jalr_0 = _GEN_26[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_27 = {{rob_uop_31_is_jal}, {rob_uop_30_is_jal}, {rob_uop_29_is_jal}, {rob_uop_28_is_jal}, {rob_uop_27_is_jal}, {rob_uop_26_is_jal}, {rob_uop_25_is_jal}, {rob_uop_24_is_jal}, {rob_uop_23_is_jal}, {rob_uop_22_is_jal}, {rob_uop_21_is_jal}, {rob_uop_20_is_jal}, {rob_uop_19_is_jal}, {rob_uop_18_is_jal}, {rob_uop_17_is_jal}, {rob_uop_16_is_jal}, {rob_uop_15_is_jal}, {rob_uop_14_is_jal}, {rob_uop_13_is_jal}, {rob_uop_12_is_jal}, {rob_uop_11_is_jal}, {rob_uop_10_is_jal}, {rob_uop_9_is_jal}, {rob_uop_8_is_jal}, {rob_uop_7_is_jal}, {rob_uop_6_is_jal}, {rob_uop_5_is_jal}, {rob_uop_4_is_jal}, {rob_uop_3_is_jal}, {rob_uop_2_is_jal}, {rob_uop_1_is_jal}, {rob_uop_0_is_jal}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_jal_0 = _GEN_27[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_28 = {{rob_uop_31_is_sfb}, {rob_uop_30_is_sfb}, {rob_uop_29_is_sfb}, {rob_uop_28_is_sfb}, {rob_uop_27_is_sfb}, {rob_uop_26_is_sfb}, {rob_uop_25_is_sfb}, {rob_uop_24_is_sfb}, {rob_uop_23_is_sfb}, {rob_uop_22_is_sfb}, {rob_uop_21_is_sfb}, {rob_uop_20_is_sfb}, {rob_uop_19_is_sfb}, {rob_uop_18_is_sfb}, {rob_uop_17_is_sfb}, {rob_uop_16_is_sfb}, {rob_uop_15_is_sfb}, {rob_uop_14_is_sfb}, {rob_uop_13_is_sfb}, {rob_uop_12_is_sfb}, {rob_uop_11_is_sfb}, {rob_uop_10_is_sfb}, {rob_uop_9_is_sfb}, {rob_uop_8_is_sfb}, {rob_uop_7_is_sfb}, {rob_uop_6_is_sfb}, {rob_uop_5_is_sfb}, {rob_uop_4_is_sfb}, {rob_uop_3_is_sfb}, {rob_uop_2_is_sfb}, {rob_uop_1_is_sfb}, {rob_uop_0_is_sfb}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_sfb_0 = _GEN_28[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][7:0] _GEN_29 = {{rob_uop_31_br_mask}, {rob_uop_30_br_mask}, {rob_uop_29_br_mask}, {rob_uop_28_br_mask}, {rob_uop_27_br_mask}, {rob_uop_26_br_mask}, {rob_uop_25_br_mask}, {rob_uop_24_br_mask}, {rob_uop_23_br_mask}, {rob_uop_22_br_mask}, {rob_uop_21_br_mask}, {rob_uop_20_br_mask}, {rob_uop_19_br_mask}, {rob_uop_18_br_mask}, {rob_uop_17_br_mask}, {rob_uop_16_br_mask}, {rob_uop_15_br_mask}, {rob_uop_14_br_mask}, {rob_uop_13_br_mask}, {rob_uop_12_br_mask}, {rob_uop_11_br_mask}, {rob_uop_10_br_mask}, {rob_uop_9_br_mask}, {rob_uop_8_br_mask}, {rob_uop_7_br_mask}, {rob_uop_6_br_mask}, {rob_uop_5_br_mask}, {rob_uop_4_br_mask}, {rob_uop_3_br_mask}, {rob_uop_2_br_mask}, {rob_uop_1_br_mask}, {rob_uop_0_br_mask}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_br_mask_0 = _GEN_29[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][2:0] _GEN_30 = {{rob_uop_31_br_tag}, {rob_uop_30_br_tag}, {rob_uop_29_br_tag}, {rob_uop_28_br_tag}, {rob_uop_27_br_tag}, {rob_uop_26_br_tag}, {rob_uop_25_br_tag}, {rob_uop_24_br_tag}, {rob_uop_23_br_tag}, {rob_uop_22_br_tag}, {rob_uop_21_br_tag}, {rob_uop_20_br_tag}, {rob_uop_19_br_tag}, {rob_uop_18_br_tag}, {rob_uop_17_br_tag}, {rob_uop_16_br_tag}, {rob_uop_15_br_tag}, {rob_uop_14_br_tag}, {rob_uop_13_br_tag}, {rob_uop_12_br_tag}, {rob_uop_11_br_tag}, {rob_uop_10_br_tag}, {rob_uop_9_br_tag}, {rob_uop_8_br_tag}, {rob_uop_7_br_tag}, {rob_uop_6_br_tag}, {rob_uop_5_br_tag}, {rob_uop_4_br_tag}, {rob_uop_3_br_tag}, {rob_uop_2_br_tag}, {rob_uop_1_br_tag}, {rob_uop_0_br_tag}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_br_tag_0 = _GEN_30[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][3:0] _GEN_31 = {{rob_uop_31_ftq_idx}, {rob_uop_30_ftq_idx}, {rob_uop_29_ftq_idx}, {rob_uop_28_ftq_idx}, {rob_uop_27_ftq_idx}, {rob_uop_26_ftq_idx}, {rob_uop_25_ftq_idx}, {rob_uop_24_ftq_idx}, {rob_uop_23_ftq_idx}, {rob_uop_22_ftq_idx}, {rob_uop_21_ftq_idx}, {rob_uop_20_ftq_idx}, {rob_uop_19_ftq_idx}, {rob_uop_18_ftq_idx}, {rob_uop_17_ftq_idx}, {rob_uop_16_ftq_idx}, {rob_uop_15_ftq_idx}, {rob_uop_14_ftq_idx}, {rob_uop_13_ftq_idx}, {rob_uop_12_ftq_idx}, {rob_uop_11_ftq_idx}, {rob_uop_10_ftq_idx}, {rob_uop_9_ftq_idx}, {rob_uop_8_ftq_idx}, {rob_uop_7_ftq_idx}, {rob_uop_6_ftq_idx}, {rob_uop_5_ftq_idx}, {rob_uop_4_ftq_idx}, {rob_uop_3_ftq_idx}, {rob_uop_2_ftq_idx}, {rob_uop_1_ftq_idx}, {rob_uop_0_ftq_idx}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ftq_idx_0 = _GEN_31[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_32 = {{rob_uop_31_edge_inst}, {rob_uop_30_edge_inst}, {rob_uop_29_edge_inst}, {rob_uop_28_edge_inst}, {rob_uop_27_edge_inst}, {rob_uop_26_edge_inst}, {rob_uop_25_edge_inst}, {rob_uop_24_edge_inst}, {rob_uop_23_edge_inst}, {rob_uop_22_edge_inst}, {rob_uop_21_edge_inst}, {rob_uop_20_edge_inst}, {rob_uop_19_edge_inst}, {rob_uop_18_edge_inst}, {rob_uop_17_edge_inst}, {rob_uop_16_edge_inst}, {rob_uop_15_edge_inst}, {rob_uop_14_edge_inst}, {rob_uop_13_edge_inst}, {rob_uop_12_edge_inst}, {rob_uop_11_edge_inst}, {rob_uop_10_edge_inst}, {rob_uop_9_edge_inst}, {rob_uop_8_edge_inst}, {rob_uop_7_edge_inst}, {rob_uop_6_edge_inst}, {rob_uop_5_edge_inst}, {rob_uop_4_edge_inst}, {rob_uop_3_edge_inst}, {rob_uop_2_edge_inst}, {rob_uop_1_edge_inst}, {rob_uop_0_edge_inst}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_edge_inst_0 = _GEN_32[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_33 = {{rob_uop_31_pc_lob}, {rob_uop_30_pc_lob}, {rob_uop_29_pc_lob}, {rob_uop_28_pc_lob}, {rob_uop_27_pc_lob}, {rob_uop_26_pc_lob}, {rob_uop_25_pc_lob}, {rob_uop_24_pc_lob}, {rob_uop_23_pc_lob}, {rob_uop_22_pc_lob}, {rob_uop_21_pc_lob}, {rob_uop_20_pc_lob}, {rob_uop_19_pc_lob}, {rob_uop_18_pc_lob}, {rob_uop_17_pc_lob}, {rob_uop_16_pc_lob}, {rob_uop_15_pc_lob}, {rob_uop_14_pc_lob}, {rob_uop_13_pc_lob}, {rob_uop_12_pc_lob}, {rob_uop_11_pc_lob}, {rob_uop_10_pc_lob}, {rob_uop_9_pc_lob}, {rob_uop_8_pc_lob}, {rob_uop_7_pc_lob}, {rob_uop_6_pc_lob}, {rob_uop_5_pc_lob}, {rob_uop_4_pc_lob}, {rob_uop_3_pc_lob}, {rob_uop_2_pc_lob}, {rob_uop_1_pc_lob}, {rob_uop_0_pc_lob}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_pc_lob_0 = _GEN_33[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_34 = {{rob_uop_31_taken}, {rob_uop_30_taken}, {rob_uop_29_taken}, {rob_uop_28_taken}, {rob_uop_27_taken}, {rob_uop_26_taken}, {rob_uop_25_taken}, {rob_uop_24_taken}, {rob_uop_23_taken}, {rob_uop_22_taken}, {rob_uop_21_taken}, {rob_uop_20_taken}, {rob_uop_19_taken}, {rob_uop_18_taken}, {rob_uop_17_taken}, {rob_uop_16_taken}, {rob_uop_15_taken}, {rob_uop_14_taken}, {rob_uop_13_taken}, {rob_uop_12_taken}, {rob_uop_11_taken}, {rob_uop_10_taken}, {rob_uop_9_taken}, {rob_uop_8_taken}, {rob_uop_7_taken}, {rob_uop_6_taken}, {rob_uop_5_taken}, {rob_uop_4_taken}, {rob_uop_3_taken}, {rob_uop_2_taken}, {rob_uop_1_taken}, {rob_uop_0_taken}};\t// @[rob.scala:311:28, :415:25]\n wire [31:0][19:0] _GEN_35 = {{rob_uop_31_imm_packed}, {rob_uop_30_imm_packed}, {rob_uop_29_imm_packed}, {rob_uop_28_imm_packed}, {rob_uop_27_imm_packed}, {rob_uop_26_imm_packed}, {rob_uop_25_imm_packed}, {rob_uop_24_imm_packed}, {rob_uop_23_imm_packed}, {rob_uop_22_imm_packed}, {rob_uop_21_imm_packed}, {rob_uop_20_imm_packed}, {rob_uop_19_imm_packed}, {rob_uop_18_imm_packed}, {rob_uop_17_imm_packed}, {rob_uop_16_imm_packed}, {rob_uop_15_imm_packed}, {rob_uop_14_imm_packed}, {rob_uop_13_imm_packed}, {rob_uop_12_imm_packed}, {rob_uop_11_imm_packed}, {rob_uop_10_imm_packed}, {rob_uop_9_imm_packed}, {rob_uop_8_imm_packed}, {rob_uop_7_imm_packed}, {rob_uop_6_imm_packed}, {rob_uop_5_imm_packed}, {rob_uop_4_imm_packed}, {rob_uop_3_imm_packed}, {rob_uop_2_imm_packed}, {rob_uop_1_imm_packed}, {rob_uop_0_imm_packed}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_imm_packed_0 = _GEN_35[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][11:0] _GEN_36 = {{rob_uop_31_csr_addr}, {rob_uop_30_csr_addr}, {rob_uop_29_csr_addr}, {rob_uop_28_csr_addr}, {rob_uop_27_csr_addr}, {rob_uop_26_csr_addr}, {rob_uop_25_csr_addr}, {rob_uop_24_csr_addr}, {rob_uop_23_csr_addr}, {rob_uop_22_csr_addr}, {rob_uop_21_csr_addr}, {rob_uop_20_csr_addr}, {rob_uop_19_csr_addr}, {rob_uop_18_csr_addr}, {rob_uop_17_csr_addr}, {rob_uop_16_csr_addr}, {rob_uop_15_csr_addr}, {rob_uop_14_csr_addr}, {rob_uop_13_csr_addr}, {rob_uop_12_csr_addr}, {rob_uop_11_csr_addr}, {rob_uop_10_csr_addr}, {rob_uop_9_csr_addr}, {rob_uop_8_csr_addr}, {rob_uop_7_csr_addr}, {rob_uop_6_csr_addr}, {rob_uop_5_csr_addr}, {rob_uop_4_csr_addr}, {rob_uop_3_csr_addr}, {rob_uop_2_csr_addr}, {rob_uop_1_csr_addr}, {rob_uop_0_csr_addr}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_csr_addr_0 = _GEN_36[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][4:0] _GEN_37 = {{rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_rob_idx_0 = _GEN_37[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][2:0] _GEN_38 = {{rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ldq_idx_0 = _GEN_38[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][2:0] _GEN_39 = {{rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_stq_idx_0 = _GEN_39[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_40 = {{rob_uop_31_rxq_idx}, {rob_uop_30_rxq_idx}, {rob_uop_29_rxq_idx}, {rob_uop_28_rxq_idx}, {rob_uop_27_rxq_idx}, {rob_uop_26_rxq_idx}, {rob_uop_25_rxq_idx}, {rob_uop_24_rxq_idx}, {rob_uop_23_rxq_idx}, {rob_uop_22_rxq_idx}, {rob_uop_21_rxq_idx}, {rob_uop_20_rxq_idx}, {rob_uop_19_rxq_idx}, {rob_uop_18_rxq_idx}, {rob_uop_17_rxq_idx}, {rob_uop_16_rxq_idx}, {rob_uop_15_rxq_idx}, {rob_uop_14_rxq_idx}, {rob_uop_13_rxq_idx}, {rob_uop_12_rxq_idx}, {rob_uop_11_rxq_idx}, {rob_uop_10_rxq_idx}, {rob_uop_9_rxq_idx}, {rob_uop_8_rxq_idx}, {rob_uop_7_rxq_idx}, {rob_uop_6_rxq_idx}, {rob_uop_5_rxq_idx}, {rob_uop_4_rxq_idx}, {rob_uop_3_rxq_idx}, {rob_uop_2_rxq_idx}, {rob_uop_1_rxq_idx}, {rob_uop_0_rxq_idx}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_rxq_idx_0 = _GEN_40[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_41 = {{rob_uop_31_pdst}, {rob_uop_30_pdst}, {rob_uop_29_pdst}, {rob_uop_28_pdst}, {rob_uop_27_pdst}, {rob_uop_26_pdst}, {rob_uop_25_pdst}, {rob_uop_24_pdst}, {rob_uop_23_pdst}, {rob_uop_22_pdst}, {rob_uop_21_pdst}, {rob_uop_20_pdst}, {rob_uop_19_pdst}, {rob_uop_18_pdst}, {rob_uop_17_pdst}, {rob_uop_16_pdst}, {rob_uop_15_pdst}, {rob_uop_14_pdst}, {rob_uop_13_pdst}, {rob_uop_12_pdst}, {rob_uop_11_pdst}, {rob_uop_10_pdst}, {rob_uop_9_pdst}, {rob_uop_8_pdst}, {rob_uop_7_pdst}, {rob_uop_6_pdst}, {rob_uop_5_pdst}, {rob_uop_4_pdst}, {rob_uop_3_pdst}, {rob_uop_2_pdst}, {rob_uop_1_pdst}, {rob_uop_0_pdst}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_pdst_0 = _GEN_41[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_42 = {{rob_uop_31_prs1}, {rob_uop_30_prs1}, {rob_uop_29_prs1}, {rob_uop_28_prs1}, {rob_uop_27_prs1}, {rob_uop_26_prs1}, {rob_uop_25_prs1}, {rob_uop_24_prs1}, {rob_uop_23_prs1}, {rob_uop_22_prs1}, {rob_uop_21_prs1}, {rob_uop_20_prs1}, {rob_uop_19_prs1}, {rob_uop_18_prs1}, {rob_uop_17_prs1}, {rob_uop_16_prs1}, {rob_uop_15_prs1}, {rob_uop_14_prs1}, {rob_uop_13_prs1}, {rob_uop_12_prs1}, {rob_uop_11_prs1}, {rob_uop_10_prs1}, {rob_uop_9_prs1}, {rob_uop_8_prs1}, {rob_uop_7_prs1}, {rob_uop_6_prs1}, {rob_uop_5_prs1}, {rob_uop_4_prs1}, {rob_uop_3_prs1}, {rob_uop_2_prs1}, {rob_uop_1_prs1}, {rob_uop_0_prs1}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_prs1_0 = _GEN_42[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_43 = {{rob_uop_31_prs2}, {rob_uop_30_prs2}, {rob_uop_29_prs2}, {rob_uop_28_prs2}, {rob_uop_27_prs2}, {rob_uop_26_prs2}, {rob_uop_25_prs2}, {rob_uop_24_prs2}, {rob_uop_23_prs2}, {rob_uop_22_prs2}, {rob_uop_21_prs2}, {rob_uop_20_prs2}, {rob_uop_19_prs2}, {rob_uop_18_prs2}, {rob_uop_17_prs2}, {rob_uop_16_prs2}, {rob_uop_15_prs2}, {rob_uop_14_prs2}, {rob_uop_13_prs2}, {rob_uop_12_prs2}, {rob_uop_11_prs2}, {rob_uop_10_prs2}, {rob_uop_9_prs2}, {rob_uop_8_prs2}, {rob_uop_7_prs2}, {rob_uop_6_prs2}, {rob_uop_5_prs2}, {rob_uop_4_prs2}, {rob_uop_3_prs2}, {rob_uop_2_prs2}, {rob_uop_1_prs2}, {rob_uop_0_prs2}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_prs2_0 = _GEN_43[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_44 = {{rob_uop_31_prs3}, {rob_uop_30_prs3}, {rob_uop_29_prs3}, {rob_uop_28_prs3}, {rob_uop_27_prs3}, {rob_uop_26_prs3}, {rob_uop_25_prs3}, {rob_uop_24_prs3}, {rob_uop_23_prs3}, {rob_uop_22_prs3}, {rob_uop_21_prs3}, {rob_uop_20_prs3}, {rob_uop_19_prs3}, {rob_uop_18_prs3}, {rob_uop_17_prs3}, {rob_uop_16_prs3}, {rob_uop_15_prs3}, {rob_uop_14_prs3}, {rob_uop_13_prs3}, {rob_uop_12_prs3}, {rob_uop_11_prs3}, {rob_uop_10_prs3}, {rob_uop_9_prs3}, {rob_uop_8_prs3}, {rob_uop_7_prs3}, {rob_uop_6_prs3}, {rob_uop_5_prs3}, {rob_uop_4_prs3}, {rob_uop_3_prs3}, {rob_uop_2_prs3}, {rob_uop_1_prs3}, {rob_uop_0_prs3}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_prs3_0 = _GEN_44[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_45 = {{rob_uop_31_prs1_busy}, {rob_uop_30_prs1_busy}, {rob_uop_29_prs1_busy}, {rob_uop_28_prs1_busy}, {rob_uop_27_prs1_busy}, {rob_uop_26_prs1_busy}, {rob_uop_25_prs1_busy}, {rob_uop_24_prs1_busy}, {rob_uop_23_prs1_busy}, {rob_uop_22_prs1_busy}, {rob_uop_21_prs1_busy}, {rob_uop_20_prs1_busy}, {rob_uop_19_prs1_busy}, {rob_uop_18_prs1_busy}, {rob_uop_17_prs1_busy}, {rob_uop_16_prs1_busy}, {rob_uop_15_prs1_busy}, {rob_uop_14_prs1_busy}, {rob_uop_13_prs1_busy}, {rob_uop_12_prs1_busy}, {rob_uop_11_prs1_busy}, {rob_uop_10_prs1_busy}, {rob_uop_9_prs1_busy}, {rob_uop_8_prs1_busy}, {rob_uop_7_prs1_busy}, {rob_uop_6_prs1_busy}, {rob_uop_5_prs1_busy}, {rob_uop_4_prs1_busy}, {rob_uop_3_prs1_busy}, {rob_uop_2_prs1_busy}, {rob_uop_1_prs1_busy}, {rob_uop_0_prs1_busy}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_prs1_busy_0 = _GEN_45[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_46 = {{rob_uop_31_prs2_busy}, {rob_uop_30_prs2_busy}, {rob_uop_29_prs2_busy}, {rob_uop_28_prs2_busy}, {rob_uop_27_prs2_busy}, {rob_uop_26_prs2_busy}, {rob_uop_25_prs2_busy}, {rob_uop_24_prs2_busy}, {rob_uop_23_prs2_busy}, {rob_uop_22_prs2_busy}, {rob_uop_21_prs2_busy}, {rob_uop_20_prs2_busy}, {rob_uop_19_prs2_busy}, {rob_uop_18_prs2_busy}, {rob_uop_17_prs2_busy}, {rob_uop_16_prs2_busy}, {rob_uop_15_prs2_busy}, {rob_uop_14_prs2_busy}, {rob_uop_13_prs2_busy}, {rob_uop_12_prs2_busy}, {rob_uop_11_prs2_busy}, {rob_uop_10_prs2_busy}, {rob_uop_9_prs2_busy}, {rob_uop_8_prs2_busy}, {rob_uop_7_prs2_busy}, {rob_uop_6_prs2_busy}, {rob_uop_5_prs2_busy}, {rob_uop_4_prs2_busy}, {rob_uop_3_prs2_busy}, {rob_uop_2_prs2_busy}, {rob_uop_1_prs2_busy}, {rob_uop_0_prs2_busy}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_prs2_busy_0 = _GEN_46[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_47 = {{rob_uop_31_prs3_busy}, {rob_uop_30_prs3_busy}, {rob_uop_29_prs3_busy}, {rob_uop_28_prs3_busy}, {rob_uop_27_prs3_busy}, {rob_uop_26_prs3_busy}, {rob_uop_25_prs3_busy}, {rob_uop_24_prs3_busy}, {rob_uop_23_prs3_busy}, {rob_uop_22_prs3_busy}, {rob_uop_21_prs3_busy}, {rob_uop_20_prs3_busy}, {rob_uop_19_prs3_busy}, {rob_uop_18_prs3_busy}, {rob_uop_17_prs3_busy}, {rob_uop_16_prs3_busy}, {rob_uop_15_prs3_busy}, {rob_uop_14_prs3_busy}, {rob_uop_13_prs3_busy}, {rob_uop_12_prs3_busy}, {rob_uop_11_prs3_busy}, {rob_uop_10_prs3_busy}, {rob_uop_9_prs3_busy}, {rob_uop_8_prs3_busy}, {rob_uop_7_prs3_busy}, {rob_uop_6_prs3_busy}, {rob_uop_5_prs3_busy}, {rob_uop_4_prs3_busy}, {rob_uop_3_prs3_busy}, {rob_uop_2_prs3_busy}, {rob_uop_1_prs3_busy}, {rob_uop_0_prs3_busy}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_prs3_busy_0 = _GEN_47[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_48 = {{rob_uop_31_stale_pdst}, {rob_uop_30_stale_pdst}, {rob_uop_29_stale_pdst}, {rob_uop_28_stale_pdst}, {rob_uop_27_stale_pdst}, {rob_uop_26_stale_pdst}, {rob_uop_25_stale_pdst}, {rob_uop_24_stale_pdst}, {rob_uop_23_stale_pdst}, {rob_uop_22_stale_pdst}, {rob_uop_21_stale_pdst}, {rob_uop_20_stale_pdst}, {rob_uop_19_stale_pdst}, {rob_uop_18_stale_pdst}, {rob_uop_17_stale_pdst}, {rob_uop_16_stale_pdst}, {rob_uop_15_stale_pdst}, {rob_uop_14_stale_pdst}, {rob_uop_13_stale_pdst}, {rob_uop_12_stale_pdst}, {rob_uop_11_stale_pdst}, {rob_uop_10_stale_pdst}, {rob_uop_9_stale_pdst}, {rob_uop_8_stale_pdst}, {rob_uop_7_stale_pdst}, {rob_uop_6_stale_pdst}, {rob_uop_5_stale_pdst}, {rob_uop_4_stale_pdst}, {rob_uop_3_stale_pdst}, {rob_uop_2_stale_pdst}, {rob_uop_1_stale_pdst}, {rob_uop_0_stale_pdst}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_stale_pdst_0 = _GEN_48[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_49 = {{rob_uop_31_exception}, {rob_uop_30_exception}, {rob_uop_29_exception}, {rob_uop_28_exception}, {rob_uop_27_exception}, {rob_uop_26_exception}, {rob_uop_25_exception}, {rob_uop_24_exception}, {rob_uop_23_exception}, {rob_uop_22_exception}, {rob_uop_21_exception}, {rob_uop_20_exception}, {rob_uop_19_exception}, {rob_uop_18_exception}, {rob_uop_17_exception}, {rob_uop_16_exception}, {rob_uop_15_exception}, {rob_uop_14_exception}, {rob_uop_13_exception}, {rob_uop_12_exception}, {rob_uop_11_exception}, {rob_uop_10_exception}, {rob_uop_9_exception}, {rob_uop_8_exception}, {rob_uop_7_exception}, {rob_uop_6_exception}, {rob_uop_5_exception}, {rob_uop_4_exception}, {rob_uop_3_exception}, {rob_uop_2_exception}, {rob_uop_1_exception}, {rob_uop_0_exception}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_exception_0 = _GEN_49[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][63:0] _GEN_50 = {{rob_uop_31_exc_cause}, {rob_uop_30_exc_cause}, {rob_uop_29_exc_cause}, {rob_uop_28_exc_cause}, {rob_uop_27_exc_cause}, {rob_uop_26_exc_cause}, {rob_uop_25_exc_cause}, {rob_uop_24_exc_cause}, {rob_uop_23_exc_cause}, {rob_uop_22_exc_cause}, {rob_uop_21_exc_cause}, {rob_uop_20_exc_cause}, {rob_uop_19_exc_cause}, {rob_uop_18_exc_cause}, {rob_uop_17_exc_cause}, {rob_uop_16_exc_cause}, {rob_uop_15_exc_cause}, {rob_uop_14_exc_cause}, {rob_uop_13_exc_cause}, {rob_uop_12_exc_cause}, {rob_uop_11_exc_cause}, {rob_uop_10_exc_cause}, {rob_uop_9_exc_cause}, {rob_uop_8_exc_cause}, {rob_uop_7_exc_cause}, {rob_uop_6_exc_cause}, {rob_uop_5_exc_cause}, {rob_uop_4_exc_cause}, {rob_uop_3_exc_cause}, {rob_uop_2_exc_cause}, {rob_uop_1_exc_cause}, {rob_uop_0_exc_cause}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_exc_cause_0 = _GEN_50[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_51 = {{rob_uop_31_bypassable}, {rob_uop_30_bypassable}, {rob_uop_29_bypassable}, {rob_uop_28_bypassable}, {rob_uop_27_bypassable}, {rob_uop_26_bypassable}, {rob_uop_25_bypassable}, {rob_uop_24_bypassable}, {rob_uop_23_bypassable}, {rob_uop_22_bypassable}, {rob_uop_21_bypassable}, {rob_uop_20_bypassable}, {rob_uop_19_bypassable}, {rob_uop_18_bypassable}, {rob_uop_17_bypassable}, {rob_uop_16_bypassable}, {rob_uop_15_bypassable}, {rob_uop_14_bypassable}, {rob_uop_13_bypassable}, {rob_uop_12_bypassable}, {rob_uop_11_bypassable}, {rob_uop_10_bypassable}, {rob_uop_9_bypassable}, {rob_uop_8_bypassable}, {rob_uop_7_bypassable}, {rob_uop_6_bypassable}, {rob_uop_5_bypassable}, {rob_uop_4_bypassable}, {rob_uop_3_bypassable}, {rob_uop_2_bypassable}, {rob_uop_1_bypassable}, {rob_uop_0_bypassable}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_bypassable_0 = _GEN_51[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][4:0] _GEN_52 = {{rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_mem_cmd_0 = _GEN_52[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_53 = {{rob_uop_31_mem_size}, {rob_uop_30_mem_size}, {rob_uop_29_mem_size}, {rob_uop_28_mem_size}, {rob_uop_27_mem_size}, {rob_uop_26_mem_size}, {rob_uop_25_mem_size}, {rob_uop_24_mem_size}, {rob_uop_23_mem_size}, {rob_uop_22_mem_size}, {rob_uop_21_mem_size}, {rob_uop_20_mem_size}, {rob_uop_19_mem_size}, {rob_uop_18_mem_size}, {rob_uop_17_mem_size}, {rob_uop_16_mem_size}, {rob_uop_15_mem_size}, {rob_uop_14_mem_size}, {rob_uop_13_mem_size}, {rob_uop_12_mem_size}, {rob_uop_11_mem_size}, {rob_uop_10_mem_size}, {rob_uop_9_mem_size}, {rob_uop_8_mem_size}, {rob_uop_7_mem_size}, {rob_uop_6_mem_size}, {rob_uop_5_mem_size}, {rob_uop_4_mem_size}, {rob_uop_3_mem_size}, {rob_uop_2_mem_size}, {rob_uop_1_mem_size}, {rob_uop_0_mem_size}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_mem_size_0 = _GEN_53[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_54 = {{rob_uop_31_mem_signed}, {rob_uop_30_mem_signed}, {rob_uop_29_mem_signed}, {rob_uop_28_mem_signed}, {rob_uop_27_mem_signed}, {rob_uop_26_mem_signed}, {rob_uop_25_mem_signed}, {rob_uop_24_mem_signed}, {rob_uop_23_mem_signed}, {rob_uop_22_mem_signed}, {rob_uop_21_mem_signed}, {rob_uop_20_mem_signed}, {rob_uop_19_mem_signed}, {rob_uop_18_mem_signed}, {rob_uop_17_mem_signed}, {rob_uop_16_mem_signed}, {rob_uop_15_mem_signed}, {rob_uop_14_mem_signed}, {rob_uop_13_mem_signed}, {rob_uop_12_mem_signed}, {rob_uop_11_mem_signed}, {rob_uop_10_mem_signed}, {rob_uop_9_mem_signed}, {rob_uop_8_mem_signed}, {rob_uop_7_mem_signed}, {rob_uop_6_mem_signed}, {rob_uop_5_mem_signed}, {rob_uop_4_mem_signed}, {rob_uop_3_mem_signed}, {rob_uop_2_mem_signed}, {rob_uop_1_mem_signed}, {rob_uop_0_mem_signed}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_mem_signed_0 = _GEN_54[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_55 = {{rob_uop_31_is_fence}, {rob_uop_30_is_fence}, {rob_uop_29_is_fence}, {rob_uop_28_is_fence}, {rob_uop_27_is_fence}, {rob_uop_26_is_fence}, {rob_uop_25_is_fence}, {rob_uop_24_is_fence}, {rob_uop_23_is_fence}, {rob_uop_22_is_fence}, {rob_uop_21_is_fence}, {rob_uop_20_is_fence}, {rob_uop_19_is_fence}, {rob_uop_18_is_fence}, {rob_uop_17_is_fence}, {rob_uop_16_is_fence}, {rob_uop_15_is_fence}, {rob_uop_14_is_fence}, {rob_uop_13_is_fence}, {rob_uop_12_is_fence}, {rob_uop_11_is_fence}, {rob_uop_10_is_fence}, {rob_uop_9_is_fence}, {rob_uop_8_is_fence}, {rob_uop_7_is_fence}, {rob_uop_6_is_fence}, {rob_uop_5_is_fence}, {rob_uop_4_is_fence}, {rob_uop_3_is_fence}, {rob_uop_2_is_fence}, {rob_uop_1_is_fence}, {rob_uop_0_is_fence}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_fence_0 = _GEN_55[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_56 = {{rob_uop_31_is_fencei}, {rob_uop_30_is_fencei}, {rob_uop_29_is_fencei}, {rob_uop_28_is_fencei}, {rob_uop_27_is_fencei}, {rob_uop_26_is_fencei}, {rob_uop_25_is_fencei}, {rob_uop_24_is_fencei}, {rob_uop_23_is_fencei}, {rob_uop_22_is_fencei}, {rob_uop_21_is_fencei}, {rob_uop_20_is_fencei}, {rob_uop_19_is_fencei}, {rob_uop_18_is_fencei}, {rob_uop_17_is_fencei}, {rob_uop_16_is_fencei}, {rob_uop_15_is_fencei}, {rob_uop_14_is_fencei}, {rob_uop_13_is_fencei}, {rob_uop_12_is_fencei}, {rob_uop_11_is_fencei}, {rob_uop_10_is_fencei}, {rob_uop_9_is_fencei}, {rob_uop_8_is_fencei}, {rob_uop_7_is_fencei}, {rob_uop_6_is_fencei}, {rob_uop_5_is_fencei}, {rob_uop_4_is_fencei}, {rob_uop_3_is_fencei}, {rob_uop_2_is_fencei}, {rob_uop_1_is_fencei}, {rob_uop_0_is_fencei}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_fencei_0 = _GEN_56[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_57 = {{rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_amo_0 = _GEN_57[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_58 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_uses_ldq_0 = _GEN_58[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_59 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_uses_stq_0 = _GEN_59[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_60 = {{rob_uop_31_is_sys_pc2epc}, {rob_uop_30_is_sys_pc2epc}, {rob_uop_29_is_sys_pc2epc}, {rob_uop_28_is_sys_pc2epc}, {rob_uop_27_is_sys_pc2epc}, {rob_uop_26_is_sys_pc2epc}, {rob_uop_25_is_sys_pc2epc}, {rob_uop_24_is_sys_pc2epc}, {rob_uop_23_is_sys_pc2epc}, {rob_uop_22_is_sys_pc2epc}, {rob_uop_21_is_sys_pc2epc}, {rob_uop_20_is_sys_pc2epc}, {rob_uop_19_is_sys_pc2epc}, {rob_uop_18_is_sys_pc2epc}, {rob_uop_17_is_sys_pc2epc}, {rob_uop_16_is_sys_pc2epc}, {rob_uop_15_is_sys_pc2epc}, {rob_uop_14_is_sys_pc2epc}, {rob_uop_13_is_sys_pc2epc}, {rob_uop_12_is_sys_pc2epc}, {rob_uop_11_is_sys_pc2epc}, {rob_uop_10_is_sys_pc2epc}, {rob_uop_9_is_sys_pc2epc}, {rob_uop_8_is_sys_pc2epc}, {rob_uop_7_is_sys_pc2epc}, {rob_uop_6_is_sys_pc2epc}, {rob_uop_5_is_sys_pc2epc}, {rob_uop_4_is_sys_pc2epc}, {rob_uop_3_is_sys_pc2epc}, {rob_uop_2_is_sys_pc2epc}, {rob_uop_1_is_sys_pc2epc}, {rob_uop_0_is_sys_pc2epc}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_sys_pc2epc_0 = _GEN_60[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_61 = {{rob_uop_31_is_unique}, {rob_uop_30_is_unique}, {rob_uop_29_is_unique}, {rob_uop_28_is_unique}, {rob_uop_27_is_unique}, {rob_uop_26_is_unique}, {rob_uop_25_is_unique}, {rob_uop_24_is_unique}, {rob_uop_23_is_unique}, {rob_uop_22_is_unique}, {rob_uop_21_is_unique}, {rob_uop_20_is_unique}, {rob_uop_19_is_unique}, {rob_uop_18_is_unique}, {rob_uop_17_is_unique}, {rob_uop_16_is_unique}, {rob_uop_15_is_unique}, {rob_uop_14_is_unique}, {rob_uop_13_is_unique}, {rob_uop_12_is_unique}, {rob_uop_11_is_unique}, {rob_uop_10_is_unique}, {rob_uop_9_is_unique}, {rob_uop_8_is_unique}, {rob_uop_7_is_unique}, {rob_uop_6_is_unique}, {rob_uop_5_is_unique}, {rob_uop_4_is_unique}, {rob_uop_3_is_unique}, {rob_uop_2_is_unique}, {rob_uop_1_is_unique}, {rob_uop_0_is_unique}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_is_unique_0 = _GEN_61[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_62 = {{rob_uop_31_flush_on_commit}, {rob_uop_30_flush_on_commit}, {rob_uop_29_flush_on_commit}, {rob_uop_28_flush_on_commit}, {rob_uop_27_flush_on_commit}, {rob_uop_26_flush_on_commit}, {rob_uop_25_flush_on_commit}, {rob_uop_24_flush_on_commit}, {rob_uop_23_flush_on_commit}, {rob_uop_22_flush_on_commit}, {rob_uop_21_flush_on_commit}, {rob_uop_20_flush_on_commit}, {rob_uop_19_flush_on_commit}, {rob_uop_18_flush_on_commit}, {rob_uop_17_flush_on_commit}, {rob_uop_16_flush_on_commit}, {rob_uop_15_flush_on_commit}, {rob_uop_14_flush_on_commit}, {rob_uop_13_flush_on_commit}, {rob_uop_12_flush_on_commit}, {rob_uop_11_flush_on_commit}, {rob_uop_10_flush_on_commit}, {rob_uop_9_flush_on_commit}, {rob_uop_8_flush_on_commit}, {rob_uop_7_flush_on_commit}, {rob_uop_6_flush_on_commit}, {rob_uop_5_flush_on_commit}, {rob_uop_4_flush_on_commit}, {rob_uop_3_flush_on_commit}, {rob_uop_2_flush_on_commit}, {rob_uop_1_flush_on_commit}, {rob_uop_0_flush_on_commit}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_flush_on_commit_0 = _GEN_62[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_63 = {{rob_uop_31_ldst_is_rs1}, {rob_uop_30_ldst_is_rs1}, {rob_uop_29_ldst_is_rs1}, {rob_uop_28_ldst_is_rs1}, {rob_uop_27_ldst_is_rs1}, {rob_uop_26_ldst_is_rs1}, {rob_uop_25_ldst_is_rs1}, {rob_uop_24_ldst_is_rs1}, {rob_uop_23_ldst_is_rs1}, {rob_uop_22_ldst_is_rs1}, {rob_uop_21_ldst_is_rs1}, {rob_uop_20_ldst_is_rs1}, {rob_uop_19_ldst_is_rs1}, {rob_uop_18_ldst_is_rs1}, {rob_uop_17_ldst_is_rs1}, {rob_uop_16_ldst_is_rs1}, {rob_uop_15_ldst_is_rs1}, {rob_uop_14_ldst_is_rs1}, {rob_uop_13_ldst_is_rs1}, {rob_uop_12_ldst_is_rs1}, {rob_uop_11_ldst_is_rs1}, {rob_uop_10_ldst_is_rs1}, {rob_uop_9_ldst_is_rs1}, {rob_uop_8_ldst_is_rs1}, {rob_uop_7_ldst_is_rs1}, {rob_uop_6_ldst_is_rs1}, {rob_uop_5_ldst_is_rs1}, {rob_uop_4_ldst_is_rs1}, {rob_uop_3_ldst_is_rs1}, {rob_uop_2_ldst_is_rs1}, {rob_uop_1_ldst_is_rs1}, {rob_uop_0_ldst_is_rs1}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ldst_is_rs1_0 = _GEN_63[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_64 = {{rob_uop_31_ldst}, {rob_uop_30_ldst}, {rob_uop_29_ldst}, {rob_uop_28_ldst}, {rob_uop_27_ldst}, {rob_uop_26_ldst}, {rob_uop_25_ldst}, {rob_uop_24_ldst}, {rob_uop_23_ldst}, {rob_uop_22_ldst}, {rob_uop_21_ldst}, {rob_uop_20_ldst}, {rob_uop_19_ldst}, {rob_uop_18_ldst}, {rob_uop_17_ldst}, {rob_uop_16_ldst}, {rob_uop_15_ldst}, {rob_uop_14_ldst}, {rob_uop_13_ldst}, {rob_uop_12_ldst}, {rob_uop_11_ldst}, {rob_uop_10_ldst}, {rob_uop_9_ldst}, {rob_uop_8_ldst}, {rob_uop_7_ldst}, {rob_uop_6_ldst}, {rob_uop_5_ldst}, {rob_uop_4_ldst}, {rob_uop_3_ldst}, {rob_uop_2_ldst}, {rob_uop_1_ldst}, {rob_uop_0_ldst}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ldst_0 = _GEN_64[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_65 = {{rob_uop_31_lrs1}, {rob_uop_30_lrs1}, {rob_uop_29_lrs1}, {rob_uop_28_lrs1}, {rob_uop_27_lrs1}, {rob_uop_26_lrs1}, {rob_uop_25_lrs1}, {rob_uop_24_lrs1}, {rob_uop_23_lrs1}, {rob_uop_22_lrs1}, {rob_uop_21_lrs1}, {rob_uop_20_lrs1}, {rob_uop_19_lrs1}, {rob_uop_18_lrs1}, {rob_uop_17_lrs1}, {rob_uop_16_lrs1}, {rob_uop_15_lrs1}, {rob_uop_14_lrs1}, {rob_uop_13_lrs1}, {rob_uop_12_lrs1}, {rob_uop_11_lrs1}, {rob_uop_10_lrs1}, {rob_uop_9_lrs1}, {rob_uop_8_lrs1}, {rob_uop_7_lrs1}, {rob_uop_6_lrs1}, {rob_uop_5_lrs1}, {rob_uop_4_lrs1}, {rob_uop_3_lrs1}, {rob_uop_2_lrs1}, {rob_uop_1_lrs1}, {rob_uop_0_lrs1}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_lrs1_0 = _GEN_65[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_66 = {{rob_uop_31_lrs2}, {rob_uop_30_lrs2}, {rob_uop_29_lrs2}, {rob_uop_28_lrs2}, {rob_uop_27_lrs2}, {rob_uop_26_lrs2}, {rob_uop_25_lrs2}, {rob_uop_24_lrs2}, {rob_uop_23_lrs2}, {rob_uop_22_lrs2}, {rob_uop_21_lrs2}, {rob_uop_20_lrs2}, {rob_uop_19_lrs2}, {rob_uop_18_lrs2}, {rob_uop_17_lrs2}, {rob_uop_16_lrs2}, {rob_uop_15_lrs2}, {rob_uop_14_lrs2}, {rob_uop_13_lrs2}, {rob_uop_12_lrs2}, {rob_uop_11_lrs2}, {rob_uop_10_lrs2}, {rob_uop_9_lrs2}, {rob_uop_8_lrs2}, {rob_uop_7_lrs2}, {rob_uop_6_lrs2}, {rob_uop_5_lrs2}, {rob_uop_4_lrs2}, {rob_uop_3_lrs2}, {rob_uop_2_lrs2}, {rob_uop_1_lrs2}, {rob_uop_0_lrs2}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_lrs2_0 = _GEN_66[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][5:0] _GEN_67 = {{rob_uop_31_lrs3}, {rob_uop_30_lrs3}, {rob_uop_29_lrs3}, {rob_uop_28_lrs3}, {rob_uop_27_lrs3}, {rob_uop_26_lrs3}, {rob_uop_25_lrs3}, {rob_uop_24_lrs3}, {rob_uop_23_lrs3}, {rob_uop_22_lrs3}, {rob_uop_21_lrs3}, {rob_uop_20_lrs3}, {rob_uop_19_lrs3}, {rob_uop_18_lrs3}, {rob_uop_17_lrs3}, {rob_uop_16_lrs3}, {rob_uop_15_lrs3}, {rob_uop_14_lrs3}, {rob_uop_13_lrs3}, {rob_uop_12_lrs3}, {rob_uop_11_lrs3}, {rob_uop_10_lrs3}, {rob_uop_9_lrs3}, {rob_uop_8_lrs3}, {rob_uop_7_lrs3}, {rob_uop_6_lrs3}, {rob_uop_5_lrs3}, {rob_uop_4_lrs3}, {rob_uop_3_lrs3}, {rob_uop_2_lrs3}, {rob_uop_1_lrs3}, {rob_uop_0_lrs3}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_lrs3_0 = _GEN_67[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_68 = {{rob_uop_31_ldst_val}, {rob_uop_30_ldst_val}, {rob_uop_29_ldst_val}, {rob_uop_28_ldst_val}, {rob_uop_27_ldst_val}, {rob_uop_26_ldst_val}, {rob_uop_25_ldst_val}, {rob_uop_24_ldst_val}, {rob_uop_23_ldst_val}, {rob_uop_22_ldst_val}, {rob_uop_21_ldst_val}, {rob_uop_20_ldst_val}, {rob_uop_19_ldst_val}, {rob_uop_18_ldst_val}, {rob_uop_17_ldst_val}, {rob_uop_16_ldst_val}, {rob_uop_15_ldst_val}, {rob_uop_14_ldst_val}, {rob_uop_13_ldst_val}, {rob_uop_12_ldst_val}, {rob_uop_11_ldst_val}, {rob_uop_10_ldst_val}, {rob_uop_9_ldst_val}, {rob_uop_8_ldst_val}, {rob_uop_7_ldst_val}, {rob_uop_6_ldst_val}, {rob_uop_5_ldst_val}, {rob_uop_4_ldst_val}, {rob_uop_3_ldst_val}, {rob_uop_2_ldst_val}, {rob_uop_1_ldst_val}, {rob_uop_0_ldst_val}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_ldst_val_0 = _GEN_68[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_69 = {{rob_uop_31_dst_rtype}, {rob_uop_30_dst_rtype}, {rob_uop_29_dst_rtype}, {rob_uop_28_dst_rtype}, {rob_uop_27_dst_rtype}, {rob_uop_26_dst_rtype}, {rob_uop_25_dst_rtype}, {rob_uop_24_dst_rtype}, {rob_uop_23_dst_rtype}, {rob_uop_22_dst_rtype}, {rob_uop_21_dst_rtype}, {rob_uop_20_dst_rtype}, {rob_uop_19_dst_rtype}, {rob_uop_18_dst_rtype}, {rob_uop_17_dst_rtype}, {rob_uop_16_dst_rtype}, {rob_uop_15_dst_rtype}, {rob_uop_14_dst_rtype}, {rob_uop_13_dst_rtype}, {rob_uop_12_dst_rtype}, {rob_uop_11_dst_rtype}, {rob_uop_10_dst_rtype}, {rob_uop_9_dst_rtype}, {rob_uop_8_dst_rtype}, {rob_uop_7_dst_rtype}, {rob_uop_6_dst_rtype}, {rob_uop_5_dst_rtype}, {rob_uop_4_dst_rtype}, {rob_uop_3_dst_rtype}, {rob_uop_2_dst_rtype}, {rob_uop_1_dst_rtype}, {rob_uop_0_dst_rtype}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_dst_rtype_0 = _GEN_69[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_70 = {{rob_uop_31_lrs1_rtype}, {rob_uop_30_lrs1_rtype}, {rob_uop_29_lrs1_rtype}, {rob_uop_28_lrs1_rtype}, {rob_uop_27_lrs1_rtype}, {rob_uop_26_lrs1_rtype}, {rob_uop_25_lrs1_rtype}, {rob_uop_24_lrs1_rtype}, {rob_uop_23_lrs1_rtype}, {rob_uop_22_lrs1_rtype}, {rob_uop_21_lrs1_rtype}, {rob_uop_20_lrs1_rtype}, {rob_uop_19_lrs1_rtype}, {rob_uop_18_lrs1_rtype}, {rob_uop_17_lrs1_rtype}, {rob_uop_16_lrs1_rtype}, {rob_uop_15_lrs1_rtype}, {rob_uop_14_lrs1_rtype}, {rob_uop_13_lrs1_rtype}, {rob_uop_12_lrs1_rtype}, {rob_uop_11_lrs1_rtype}, {rob_uop_10_lrs1_rtype}, {rob_uop_9_lrs1_rtype}, {rob_uop_8_lrs1_rtype}, {rob_uop_7_lrs1_rtype}, {rob_uop_6_lrs1_rtype}, {rob_uop_5_lrs1_rtype}, {rob_uop_4_lrs1_rtype}, {rob_uop_3_lrs1_rtype}, {rob_uop_2_lrs1_rtype}, {rob_uop_1_lrs1_rtype}, {rob_uop_0_lrs1_rtype}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_lrs1_rtype_0 = _GEN_70[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_71 = {{rob_uop_31_lrs2_rtype}, {rob_uop_30_lrs2_rtype}, {rob_uop_29_lrs2_rtype}, {rob_uop_28_lrs2_rtype}, {rob_uop_27_lrs2_rtype}, {rob_uop_26_lrs2_rtype}, {rob_uop_25_lrs2_rtype}, {rob_uop_24_lrs2_rtype}, {rob_uop_23_lrs2_rtype}, {rob_uop_22_lrs2_rtype}, {rob_uop_21_lrs2_rtype}, {rob_uop_20_lrs2_rtype}, {rob_uop_19_lrs2_rtype}, {rob_uop_18_lrs2_rtype}, {rob_uop_17_lrs2_rtype}, {rob_uop_16_lrs2_rtype}, {rob_uop_15_lrs2_rtype}, {rob_uop_14_lrs2_rtype}, {rob_uop_13_lrs2_rtype}, {rob_uop_12_lrs2_rtype}, {rob_uop_11_lrs2_rtype}, {rob_uop_10_lrs2_rtype}, {rob_uop_9_lrs2_rtype}, {rob_uop_8_lrs2_rtype}, {rob_uop_7_lrs2_rtype}, {rob_uop_6_lrs2_rtype}, {rob_uop_5_lrs2_rtype}, {rob_uop_4_lrs2_rtype}, {rob_uop_3_lrs2_rtype}, {rob_uop_2_lrs2_rtype}, {rob_uop_1_lrs2_rtype}, {rob_uop_0_lrs2_rtype}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_lrs2_rtype_0 = _GEN_71[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_72 = {{rob_uop_31_frs3_en}, {rob_uop_30_frs3_en}, {rob_uop_29_frs3_en}, {rob_uop_28_frs3_en}, {rob_uop_27_frs3_en}, {rob_uop_26_frs3_en}, {rob_uop_25_frs3_en}, {rob_uop_24_frs3_en}, {rob_uop_23_frs3_en}, {rob_uop_22_frs3_en}, {rob_uop_21_frs3_en}, {rob_uop_20_frs3_en}, {rob_uop_19_frs3_en}, {rob_uop_18_frs3_en}, {rob_uop_17_frs3_en}, {rob_uop_16_frs3_en}, {rob_uop_15_frs3_en}, {rob_uop_14_frs3_en}, {rob_uop_13_frs3_en}, {rob_uop_12_frs3_en}, {rob_uop_11_frs3_en}, {rob_uop_10_frs3_en}, {rob_uop_9_frs3_en}, {rob_uop_8_frs3_en}, {rob_uop_7_frs3_en}, {rob_uop_6_frs3_en}, {rob_uop_5_frs3_en}, {rob_uop_4_frs3_en}, {rob_uop_3_frs3_en}, {rob_uop_2_frs3_en}, {rob_uop_1_frs3_en}, {rob_uop_0_frs3_en}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_frs3_en_0 = _GEN_72[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_73 = {{rob_uop_31_fp_val}, {rob_uop_30_fp_val}, {rob_uop_29_fp_val}, {rob_uop_28_fp_val}, {rob_uop_27_fp_val}, {rob_uop_26_fp_val}, {rob_uop_25_fp_val}, {rob_uop_24_fp_val}, {rob_uop_23_fp_val}, {rob_uop_22_fp_val}, {rob_uop_21_fp_val}, {rob_uop_20_fp_val}, {rob_uop_19_fp_val}, {rob_uop_18_fp_val}, {rob_uop_17_fp_val}, {rob_uop_16_fp_val}, {rob_uop_15_fp_val}, {rob_uop_14_fp_val}, {rob_uop_13_fp_val}, {rob_uop_12_fp_val}, {rob_uop_11_fp_val}, {rob_uop_10_fp_val}, {rob_uop_9_fp_val}, {rob_uop_8_fp_val}, {rob_uop_7_fp_val}, {rob_uop_6_fp_val}, {rob_uop_5_fp_val}, {rob_uop_4_fp_val}, {rob_uop_3_fp_val}, {rob_uop_2_fp_val}, {rob_uop_1_fp_val}, {rob_uop_0_fp_val}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_fp_val_0 = _GEN_73[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_74 = {{rob_uop_31_fp_single}, {rob_uop_30_fp_single}, {rob_uop_29_fp_single}, {rob_uop_28_fp_single}, {rob_uop_27_fp_single}, {rob_uop_26_fp_single}, {rob_uop_25_fp_single}, {rob_uop_24_fp_single}, {rob_uop_23_fp_single}, {rob_uop_22_fp_single}, {rob_uop_21_fp_single}, {rob_uop_20_fp_single}, {rob_uop_19_fp_single}, {rob_uop_18_fp_single}, {rob_uop_17_fp_single}, {rob_uop_16_fp_single}, {rob_uop_15_fp_single}, {rob_uop_14_fp_single}, {rob_uop_13_fp_single}, {rob_uop_12_fp_single}, {rob_uop_11_fp_single}, {rob_uop_10_fp_single}, {rob_uop_9_fp_single}, {rob_uop_8_fp_single}, {rob_uop_7_fp_single}, {rob_uop_6_fp_single}, {rob_uop_5_fp_single}, {rob_uop_4_fp_single}, {rob_uop_3_fp_single}, {rob_uop_2_fp_single}, {rob_uop_1_fp_single}, {rob_uop_0_fp_single}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_fp_single_0 = _GEN_74[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_75 = {{rob_uop_31_xcpt_pf_if}, {rob_uop_30_xcpt_pf_if}, {rob_uop_29_xcpt_pf_if}, {rob_uop_28_xcpt_pf_if}, {rob_uop_27_xcpt_pf_if}, {rob_uop_26_xcpt_pf_if}, {rob_uop_25_xcpt_pf_if}, {rob_uop_24_xcpt_pf_if}, {rob_uop_23_xcpt_pf_if}, {rob_uop_22_xcpt_pf_if}, {rob_uop_21_xcpt_pf_if}, {rob_uop_20_xcpt_pf_if}, {rob_uop_19_xcpt_pf_if}, {rob_uop_18_xcpt_pf_if}, {rob_uop_17_xcpt_pf_if}, {rob_uop_16_xcpt_pf_if}, {rob_uop_15_xcpt_pf_if}, {rob_uop_14_xcpt_pf_if}, {rob_uop_13_xcpt_pf_if}, {rob_uop_12_xcpt_pf_if}, {rob_uop_11_xcpt_pf_if}, {rob_uop_10_xcpt_pf_if}, {rob_uop_9_xcpt_pf_if}, {rob_uop_8_xcpt_pf_if}, {rob_uop_7_xcpt_pf_if}, {rob_uop_6_xcpt_pf_if}, {rob_uop_5_xcpt_pf_if}, {rob_uop_4_xcpt_pf_if}, {rob_uop_3_xcpt_pf_if}, {rob_uop_2_xcpt_pf_if}, {rob_uop_1_xcpt_pf_if}, {rob_uop_0_xcpt_pf_if}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_xcpt_pf_if_0 = _GEN_75[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_76 = {{rob_uop_31_xcpt_ae_if}, {rob_uop_30_xcpt_ae_if}, {rob_uop_29_xcpt_ae_if}, {rob_uop_28_xcpt_ae_if}, {rob_uop_27_xcpt_ae_if}, {rob_uop_26_xcpt_ae_if}, {rob_uop_25_xcpt_ae_if}, {rob_uop_24_xcpt_ae_if}, {rob_uop_23_xcpt_ae_if}, {rob_uop_22_xcpt_ae_if}, {rob_uop_21_xcpt_ae_if}, {rob_uop_20_xcpt_ae_if}, {rob_uop_19_xcpt_ae_if}, {rob_uop_18_xcpt_ae_if}, {rob_uop_17_xcpt_ae_if}, {rob_uop_16_xcpt_ae_if}, {rob_uop_15_xcpt_ae_if}, {rob_uop_14_xcpt_ae_if}, {rob_uop_13_xcpt_ae_if}, {rob_uop_12_xcpt_ae_if}, {rob_uop_11_xcpt_ae_if}, {rob_uop_10_xcpt_ae_if}, {rob_uop_9_xcpt_ae_if}, {rob_uop_8_xcpt_ae_if}, {rob_uop_7_xcpt_ae_if}, {rob_uop_6_xcpt_ae_if}, {rob_uop_5_xcpt_ae_if}, {rob_uop_4_xcpt_ae_if}, {rob_uop_3_xcpt_ae_if}, {rob_uop_2_xcpt_ae_if}, {rob_uop_1_xcpt_ae_if}, {rob_uop_0_xcpt_ae_if}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_xcpt_ae_if_0 = _GEN_76[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_77 = {{rob_uop_31_xcpt_ma_if}, {rob_uop_30_xcpt_ma_if}, {rob_uop_29_xcpt_ma_if}, {rob_uop_28_xcpt_ma_if}, {rob_uop_27_xcpt_ma_if}, {rob_uop_26_xcpt_ma_if}, {rob_uop_25_xcpt_ma_if}, {rob_uop_24_xcpt_ma_if}, {rob_uop_23_xcpt_ma_if}, {rob_uop_22_xcpt_ma_if}, {rob_uop_21_xcpt_ma_if}, {rob_uop_20_xcpt_ma_if}, {rob_uop_19_xcpt_ma_if}, {rob_uop_18_xcpt_ma_if}, {rob_uop_17_xcpt_ma_if}, {rob_uop_16_xcpt_ma_if}, {rob_uop_15_xcpt_ma_if}, {rob_uop_14_xcpt_ma_if}, {rob_uop_13_xcpt_ma_if}, {rob_uop_12_xcpt_ma_if}, {rob_uop_11_xcpt_ma_if}, {rob_uop_10_xcpt_ma_if}, {rob_uop_9_xcpt_ma_if}, {rob_uop_8_xcpt_ma_if}, {rob_uop_7_xcpt_ma_if}, {rob_uop_6_xcpt_ma_if}, {rob_uop_5_xcpt_ma_if}, {rob_uop_4_xcpt_ma_if}, {rob_uop_3_xcpt_ma_if}, {rob_uop_2_xcpt_ma_if}, {rob_uop_1_xcpt_ma_if}, {rob_uop_0_xcpt_ma_if}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_xcpt_ma_if_0 = _GEN_77[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_78 = {{rob_uop_31_bp_debug_if}, {rob_uop_30_bp_debug_if}, {rob_uop_29_bp_debug_if}, {rob_uop_28_bp_debug_if}, {rob_uop_27_bp_debug_if}, {rob_uop_26_bp_debug_if}, {rob_uop_25_bp_debug_if}, {rob_uop_24_bp_debug_if}, {rob_uop_23_bp_debug_if}, {rob_uop_22_bp_debug_if}, {rob_uop_21_bp_debug_if}, {rob_uop_20_bp_debug_if}, {rob_uop_19_bp_debug_if}, {rob_uop_18_bp_debug_if}, {rob_uop_17_bp_debug_if}, {rob_uop_16_bp_debug_if}, {rob_uop_15_bp_debug_if}, {rob_uop_14_bp_debug_if}, {rob_uop_13_bp_debug_if}, {rob_uop_12_bp_debug_if}, {rob_uop_11_bp_debug_if}, {rob_uop_10_bp_debug_if}, {rob_uop_9_bp_debug_if}, {rob_uop_8_bp_debug_if}, {rob_uop_7_bp_debug_if}, {rob_uop_6_bp_debug_if}, {rob_uop_5_bp_debug_if}, {rob_uop_4_bp_debug_if}, {rob_uop_3_bp_debug_if}, {rob_uop_2_bp_debug_if}, {rob_uop_1_bp_debug_if}, {rob_uop_0_bp_debug_if}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_bp_debug_if_0 = _GEN_78[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0] _GEN_79 = {{rob_uop_31_bp_xcpt_if}, {rob_uop_30_bp_xcpt_if}, {rob_uop_29_bp_xcpt_if}, {rob_uop_28_bp_xcpt_if}, {rob_uop_27_bp_xcpt_if}, {rob_uop_26_bp_xcpt_if}, {rob_uop_25_bp_xcpt_if}, {rob_uop_24_bp_xcpt_if}, {rob_uop_23_bp_xcpt_if}, {rob_uop_22_bp_xcpt_if}, {rob_uop_21_bp_xcpt_if}, {rob_uop_20_bp_xcpt_if}, {rob_uop_19_bp_xcpt_if}, {rob_uop_18_bp_xcpt_if}, {rob_uop_17_bp_xcpt_if}, {rob_uop_16_bp_xcpt_if}, {rob_uop_15_bp_xcpt_if}, {rob_uop_14_bp_xcpt_if}, {rob_uop_13_bp_xcpt_if}, {rob_uop_12_bp_xcpt_if}, {rob_uop_11_bp_xcpt_if}, {rob_uop_10_bp_xcpt_if}, {rob_uop_9_bp_xcpt_if}, {rob_uop_8_bp_xcpt_if}, {rob_uop_7_bp_xcpt_if}, {rob_uop_6_bp_xcpt_if}, {rob_uop_5_bp_xcpt_if}, {rob_uop_4_bp_xcpt_if}, {rob_uop_3_bp_xcpt_if}, {rob_uop_2_bp_xcpt_if}, {rob_uop_1_bp_xcpt_if}, {rob_uop_0_bp_xcpt_if}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_bp_xcpt_if_0 = _GEN_79[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire [31:0][1:0] _GEN_80 = {{rob_uop_31_debug_fsrc}, {rob_uop_30_debug_fsrc}, {rob_uop_29_debug_fsrc}, {rob_uop_28_debug_fsrc}, {rob_uop_27_debug_fsrc}, {rob_uop_26_debug_fsrc}, {rob_uop_25_debug_fsrc}, {rob_uop_24_debug_fsrc}, {rob_uop_23_debug_fsrc}, {rob_uop_22_debug_fsrc}, {rob_uop_21_debug_fsrc}, {rob_uop_20_debug_fsrc}, {rob_uop_19_debug_fsrc}, {rob_uop_18_debug_fsrc}, {rob_uop_17_debug_fsrc}, {rob_uop_16_debug_fsrc}, {rob_uop_15_debug_fsrc}, {rob_uop_14_debug_fsrc}, {rob_uop_13_debug_fsrc}, {rob_uop_12_debug_fsrc}, {rob_uop_11_debug_fsrc}, {rob_uop_10_debug_fsrc}, {rob_uop_9_debug_fsrc}, {rob_uop_8_debug_fsrc}, {rob_uop_7_debug_fsrc}, {rob_uop_6_debug_fsrc}, {rob_uop_5_debug_fsrc}, {rob_uop_4_debug_fsrc}, {rob_uop_3_debug_fsrc}, {rob_uop_2_debug_fsrc}, {rob_uop_1_debug_fsrc}, {rob_uop_0_debug_fsrc}};\t// @[rob.scala:311:28, :415:25]\n wire [31:0][1:0] _GEN_81 = {{rob_uop_31_debug_tsrc}, {rob_uop_30_debug_tsrc}, {rob_uop_29_debug_tsrc}, {rob_uop_28_debug_tsrc}, {rob_uop_27_debug_tsrc}, {rob_uop_26_debug_tsrc}, {rob_uop_25_debug_tsrc}, {rob_uop_24_debug_tsrc}, {rob_uop_23_debug_tsrc}, {rob_uop_22_debug_tsrc}, {rob_uop_21_debug_tsrc}, {rob_uop_20_debug_tsrc}, {rob_uop_19_debug_tsrc}, {rob_uop_18_debug_tsrc}, {rob_uop_17_debug_tsrc}, {rob_uop_16_debug_tsrc}, {rob_uop_15_debug_tsrc}, {rob_uop_14_debug_tsrc}, {rob_uop_13_debug_tsrc}, {rob_uop_12_debug_tsrc}, {rob_uop_11_debug_tsrc}, {rob_uop_10_debug_tsrc}, {rob_uop_9_debug_tsrc}, {rob_uop_8_debug_tsrc}, {rob_uop_7_debug_tsrc}, {rob_uop_6_debug_tsrc}, {rob_uop_5_debug_tsrc}, {rob_uop_4_debug_tsrc}, {rob_uop_3_debug_tsrc}, {rob_uop_2_debug_tsrc}, {rob_uop_1_debug_tsrc}, {rob_uop_0_debug_tsrc}};\t// @[rob.scala:311:28, :415:25]\n assign io_commit_uops_0_debug_tsrc_0 = _GEN_81[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25]\n wire _T_56 = io_brupdate_b2_mispredict_0 & io_brupdate_b2_uop_rob_idx_0 == com_idx;\t// @[rob.scala:211:7, :235:20, :421:57, :422:45]\n assign io_commit_uops_0_debug_fsrc_0 = _T_56 ? 2'h3 : _GEN_80[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25, :421:57, :422:58, :423:36]\n assign io_commit_uops_0_taken_0 = _T_56 ? io_brupdate_b2_taken_0 : _GEN_34[com_idx];\t// @[rob.scala:211:7, :235:20, :415:25, :421:57, :422:58, :424:36]\n wire _rbk_row_T_1 = ~full;\t// @[rob.scala:239:26, :429:47]\n wire rbk_row = _rbk_row_T & _rbk_row_T_1;\t// @[rob.scala:429:{29,44,47}]\n wire _io_commit_rbk_valids_0_T = rbk_row & _GEN[com_idx];\t// @[rob.scala:235:20, :324:31, :429:44, :431:40]\n assign _io_commit_rbk_valids_0_T_2 = _io_commit_rbk_valids_0_T;\t// @[rob.scala:431:{40,60}]\n assign io_commit_rbk_valids_0_0 = _io_commit_rbk_valids_0_T_2;\t// @[rob.scala:211:7, :431:60]\n assign io_commit_rollback_0 = _io_commit_rollback_T;\t// @[rob.scala:211:7, :432:38]\n wire [7:0] _rob_uop_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_0_br_mask_T_1 = rob_uop_0_br_mask & _rob_uop_0_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_1_br_mask_T_1 = rob_uop_1_br_mask & _rob_uop_1_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_2_br_mask_T_1 = rob_uop_2_br_mask & _rob_uop_2_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_3_br_mask_T_1 = rob_uop_3_br_mask & _rob_uop_3_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_4_br_mask_T_1 = rob_uop_4_br_mask & _rob_uop_4_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_5_br_mask_T_1 = rob_uop_5_br_mask & _rob_uop_5_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_6_br_mask_T_1 = rob_uop_6_br_mask & _rob_uop_6_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_7_br_mask_T_1 = rob_uop_7_br_mask & _rob_uop_7_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_8_br_mask_T_1 = rob_uop_8_br_mask & _rob_uop_8_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_9_br_mask_T_1 = rob_uop_9_br_mask & _rob_uop_9_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_10_br_mask_T_1 = rob_uop_10_br_mask & _rob_uop_10_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_11_br_mask_T_1 = rob_uop_11_br_mask & _rob_uop_11_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_12_br_mask_T_1 = rob_uop_12_br_mask & _rob_uop_12_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_13_br_mask_T_1 = rob_uop_13_br_mask & _rob_uop_13_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_14_br_mask_T_1 = rob_uop_14_br_mask & _rob_uop_14_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_15_br_mask_T_1 = rob_uop_15_br_mask & _rob_uop_15_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_16_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_16_br_mask_T_1 = rob_uop_16_br_mask & _rob_uop_16_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_17_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_17_br_mask_T_1 = rob_uop_17_br_mask & _rob_uop_17_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_18_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_18_br_mask_T_1 = rob_uop_18_br_mask & _rob_uop_18_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_19_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_19_br_mask_T_1 = rob_uop_19_br_mask & _rob_uop_19_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_20_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_20_br_mask_T_1 = rob_uop_20_br_mask & _rob_uop_20_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_21_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_21_br_mask_T_1 = rob_uop_21_br_mask & _rob_uop_21_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_22_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_22_br_mask_T_1 = rob_uop_22_br_mask & _rob_uop_22_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_23_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_23_br_mask_T_1 = rob_uop_23_br_mask & _rob_uop_23_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_24_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_24_br_mask_T_1 = rob_uop_24_br_mask & _rob_uop_24_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_25_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_25_br_mask_T_1 = rob_uop_25_br_mask & _rob_uop_25_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_26_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_26_br_mask_T_1 = rob_uop_26_br_mask & _rob_uop_26_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_27_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_27_br_mask_T_1 = rob_uop_27_br_mask & _rob_uop_27_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_28_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_28_br_mask_T_1 = rob_uop_28_br_mask & _rob_uop_28_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_29_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_29_br_mask_T_1 = rob_uop_29_br_mask & _rob_uop_29_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_30_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_30_br_mask_T_1 = rob_uop_30_br_mask & _rob_uop_30_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [7:0] _rob_uop_31_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:89:23]\n wire [7:0] _rob_uop_31_br_mask_T_1 = rob_uop_31_br_mask & _rob_uop_31_br_mask_T;\t// @[util.scala:89:{21,23}]\n wire [31:0][4:0] _GEN_82 = {{rob_fflags_0_31}, {rob_fflags_0_30}, {rob_fflags_0_29}, {rob_fflags_0_28}, {rob_fflags_0_27}, {rob_fflags_0_26}, {rob_fflags_0_25}, {rob_fflags_0_24}, {rob_fflags_0_23}, {rob_fflags_0_22}, {rob_fflags_0_21}, {rob_fflags_0_20}, {rob_fflags_0_19}, {rob_fflags_0_18}, {rob_fflags_0_17}, {rob_fflags_0_16}, {rob_fflags_0_15}, {rob_fflags_0_14}, {rob_fflags_0_13}, {rob_fflags_0_12}, {rob_fflags_0_11}, {rob_fflags_0_10}, {rob_fflags_0_9}, {rob_fflags_0_8}, {rob_fflags_0_7}, {rob_fflags_0_6}, {rob_fflags_0_5}, {rob_fflags_0_4}, {rob_fflags_0_3}, {rob_fflags_0_2}, {rob_fflags_0_1}, {rob_fflags_0_0}};\t// @[rob.scala:302:46, :487:26]\n assign rob_head_fflags_0 = _GEN_82[rob_head];\t// @[rob.scala:223:29, :251:33, :487:26]\n assign rob_head_uses_ldq_0 = _GEN_58[rob_head];\t// @[rob.scala:223:29, :250:33, :415:25, :488:26]\n assign rob_head_uses_stq_0 = _GEN_59[rob_head];\t// @[rob.scala:223:29, :249:33, :415:25, :488:26]\n wire _rob_unsafe_masked_0_T = rob_unsafe_0 | rob_exception_0;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_0_T_1 = rob_val_0 & _rob_unsafe_masked_0_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_0 = _rob_unsafe_masked_0_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_1_T = rob_unsafe_1 | rob_exception_1;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_1_T_1 = rob_val_1 & _rob_unsafe_masked_1_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_1 = _rob_unsafe_masked_1_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_2_T = rob_unsafe_2 | rob_exception_2;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_2_T_1 = rob_val_2 & _rob_unsafe_masked_2_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_2 = _rob_unsafe_masked_2_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_3_T = rob_unsafe_3 | rob_exception_3;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_3_T_1 = rob_val_3 & _rob_unsafe_masked_3_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_3 = _rob_unsafe_masked_3_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_4_T = rob_unsafe_4 | rob_exception_4;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_4_T_1 = rob_val_4 & _rob_unsafe_masked_4_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_4 = _rob_unsafe_masked_4_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_5_T = rob_unsafe_5 | rob_exception_5;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_5_T_1 = rob_val_5 & _rob_unsafe_masked_5_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_5 = _rob_unsafe_masked_5_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_6_T = rob_unsafe_6 | rob_exception_6;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_6_T_1 = rob_val_6 & _rob_unsafe_masked_6_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_6 = _rob_unsafe_masked_6_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_7_T = rob_unsafe_7 | rob_exception_7;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_7_T_1 = rob_val_7 & _rob_unsafe_masked_7_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_7 = _rob_unsafe_masked_7_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_8_T = rob_unsafe_8 | rob_exception_8;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_8_T_1 = rob_val_8 & _rob_unsafe_masked_8_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_8 = _rob_unsafe_masked_8_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_9_T = rob_unsafe_9 | rob_exception_9;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_9_T_1 = rob_val_9 & _rob_unsafe_masked_9_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_9 = _rob_unsafe_masked_9_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_10_T = rob_unsafe_10 | rob_exception_10;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_10_T_1 = rob_val_10 & _rob_unsafe_masked_10_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_10 = _rob_unsafe_masked_10_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_11_T = rob_unsafe_11 | rob_exception_11;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_11_T_1 = rob_val_11 & _rob_unsafe_masked_11_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_11 = _rob_unsafe_masked_11_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_12_T = rob_unsafe_12 | rob_exception_12;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_12_T_1 = rob_val_12 & _rob_unsafe_masked_12_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_12 = _rob_unsafe_masked_12_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_13_T = rob_unsafe_13 | rob_exception_13;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_13_T_1 = rob_val_13 & _rob_unsafe_masked_13_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_13 = _rob_unsafe_masked_13_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_14_T = rob_unsafe_14 | rob_exception_14;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_14_T_1 = rob_val_14 & _rob_unsafe_masked_14_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_14 = _rob_unsafe_masked_14_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_15_T = rob_unsafe_15 | rob_exception_15;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_15_T_1 = rob_val_15 & _rob_unsafe_masked_15_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_15 = _rob_unsafe_masked_15_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_16_T = rob_unsafe_16 | rob_exception_16;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_16_T_1 = rob_val_16 & _rob_unsafe_masked_16_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_16 = _rob_unsafe_masked_16_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_17_T = rob_unsafe_17 | rob_exception_17;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_17_T_1 = rob_val_17 & _rob_unsafe_masked_17_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_17 = _rob_unsafe_masked_17_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_18_T = rob_unsafe_18 | rob_exception_18;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_18_T_1 = rob_val_18 & _rob_unsafe_masked_18_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_18 = _rob_unsafe_masked_18_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_19_T = rob_unsafe_19 | rob_exception_19;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_19_T_1 = rob_val_19 & _rob_unsafe_masked_19_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_19 = _rob_unsafe_masked_19_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_20_T = rob_unsafe_20 | rob_exception_20;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_20_T_1 = rob_val_20 & _rob_unsafe_masked_20_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_20 = _rob_unsafe_masked_20_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_21_T = rob_unsafe_21 | rob_exception_21;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_21_T_1 = rob_val_21 & _rob_unsafe_masked_21_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_21 = _rob_unsafe_masked_21_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_22_T = rob_unsafe_22 | rob_exception_22;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_22_T_1 = rob_val_22 & _rob_unsafe_masked_22_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_22 = _rob_unsafe_masked_22_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_23_T = rob_unsafe_23 | rob_exception_23;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_23_T_1 = rob_val_23 & _rob_unsafe_masked_23_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_23 = _rob_unsafe_masked_23_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_24_T = rob_unsafe_24 | rob_exception_24;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_24_T_1 = rob_val_24 & _rob_unsafe_masked_24_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_24 = _rob_unsafe_masked_24_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_25_T = rob_unsafe_25 | rob_exception_25;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_25_T_1 = rob_val_25 & _rob_unsafe_masked_25_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_25 = _rob_unsafe_masked_25_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_26_T = rob_unsafe_26 | rob_exception_26;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_26_T_1 = rob_val_26 & _rob_unsafe_masked_26_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_26 = _rob_unsafe_masked_26_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_27_T = rob_unsafe_27 | rob_exception_27;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_27_T_1 = rob_val_27 & _rob_unsafe_masked_27_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_27 = _rob_unsafe_masked_27_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_28_T = rob_unsafe_28 | rob_exception_28;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_28_T_1 = rob_val_28 & _rob_unsafe_masked_28_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_28 = _rob_unsafe_masked_28_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_29_T = rob_unsafe_29 | rob_exception_29;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_29_T_1 = rob_val_29 & _rob_unsafe_masked_29_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_29 = _rob_unsafe_masked_29_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_30_T = rob_unsafe_30 | rob_exception_30;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_30_T_1 = rob_val_30 & _rob_unsafe_masked_30_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_30 = _rob_unsafe_masked_30_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_unsafe_masked_31_T = rob_unsafe_31 | rob_exception_31;\t// @[rob.scala:310:28, :312:28, :494:89]\n assign _rob_unsafe_masked_31_T_1 = rob_val_31 & _rob_unsafe_masked_31_T;\t// @[rob.scala:308:32, :494:{71,89}]\n assign rob_unsafe_masked_31 = _rob_unsafe_masked_31_T_1;\t// @[rob.scala:293:35, :494:71]\n wire _rob_pnr_unsafe_0_T = _GEN_2[rob_pnr] | _GEN_3[rob_pnr];\t// @[rob.scala:231:29, :394:15, :402:49, :497:67]\n assign _rob_pnr_unsafe_0_T_1 = _GEN[rob_pnr] & _rob_pnr_unsafe_0_T;\t// @[rob.scala:231:29, :324:31, :497:{43,67}]\n assign rob_pnr_unsafe_0 = _rob_pnr_unsafe_0_T_1;\t// @[rob.scala:246:33, :497:43]\n wire _block_commit_T = rob_state != 2'h1;\t// @[rob.scala:220:26, :544:33]\n wire _block_commit_T_1 = rob_state != 2'h3;\t// @[rob.scala:220:26, :544:61]\n wire _block_commit_T_2 = _block_commit_T & _block_commit_T_1;\t// @[rob.scala:544:{33,47,61}]\n reg block_commit_REG;\t// @[rob.scala:544:94]\n wire _block_commit_T_3 = _block_commit_T_2 | block_commit_REG;\t// @[rob.scala:544:{47,84,94}]\n reg block_commit_REG_1;\t// @[rob.scala:544:131]\n reg block_commit_REG_2;\t// @[rob.scala:544:123]\n wire block_commit = _block_commit_T_3 | block_commit_REG_2;\t// @[rob.scala:544:{84,113,123}]\n assign exception_thrown = can_throw_exception_0 & ~block_commit;\t// @[rob.scala:244:33, :253:30, :544:113, :549:{52,55}]\n wire _will_commit_0_T = ~can_throw_exception_0;\t// @[rob.scala:244:33, :551:46]\n wire _will_commit_0_T_1 = can_commit_0 & _will_commit_0_T;\t// @[rob.scala:243:33, :551:{43,46}]\n wire _will_commit_0_T_2 = ~block_commit;\t// @[rob.scala:544:113, :549:55, :551:73]\n assign _will_commit_0_T_3 = _will_commit_0_T_1 & _will_commit_0_T_2;\t// @[rob.scala:551:{43,70,73}]\n assign will_commit_0 = _will_commit_0_T_3;\t// @[rob.scala:242:33, :551:70]\n wire _is_mini_exception_T = io_com_xcpt_bits_cause_0 == 64'h10;\t// @[package.scala:16:47]\n wire _is_mini_exception_T_1 = io_com_xcpt_bits_cause_0 == 64'h11;\t// @[package.scala:16:47]\n wire is_mini_exception = _is_mini_exception_T | _is_mini_exception_T_1;\t// @[package.scala:16:47, :81:59]\n wire _io_com_xcpt_valid_T = ~is_mini_exception;\t// @[package.scala:81:59]\n assign _io_com_xcpt_valid_T_1 = exception_thrown & _io_com_xcpt_valid_T;\t// @[rob.scala:253:30, :561:{41,44}]\n assign io_com_xcpt_valid_0 = _io_com_xcpt_valid_T_1;\t// @[rob.scala:211:7, :561:41]\n wire _io_com_xcpt_bits_badvaddr_T = r_xcpt_badvaddr[39];\t// @[util.scala:261:46]\n wire [23:0] _io_com_xcpt_bits_badvaddr_T_1 = {24{_io_com_xcpt_bits_badvaddr_T}};\t// @[util.scala:261:{25,46}]\n assign _io_com_xcpt_bits_badvaddr_T_2 = {_io_com_xcpt_bits_badvaddr_T_1, r_xcpt_badvaddr};\t// @[util.scala:261:{20,25}]\n assign io_com_xcpt_bits_badvaddr_0 = _io_com_xcpt_bits_badvaddr_T_2;\t// @[util.scala:261:20]\n wire insn_sys_pc2epc = rob_head_vals_0 & io_commit_uops_0_is_sys_pc2epc_0;\t// @[rob.scala:211:7, :247:33, :567:31]\n wire refetch_inst = exception_thrown | insn_sys_pc2epc;\t// @[rob.scala:253:30, :567:31, :569:39]\n wire flush_commit_mask_0 = io_commit_valids_0_0 & io_commit_uops_0_flush_on_commit_0;\t// @[rob.scala:211:7, :576:75]\n assign flush_val = exception_thrown | flush_commit_mask_0;\t// @[rob.scala:253:30, :576:75, :578:36]\n assign io_flush_valid_0 = flush_val;\t// @[rob.scala:211:7, :578:36]\n assign io_flush_bits_is_rvc_0 = flush_uop_is_rvc;\t// @[rob.scala:211:7, :583:22]\n assign io_flush_bits_ftq_idx_0 = flush_uop_ftq_idx;\t// @[rob.scala:211:7, :583:22]\n assign io_flush_bits_edge_inst_0 = flush_uop_edge_inst;\t// @[rob.scala:211:7, :583:22]\n assign io_flush_bits_pc_lob_0 = flush_uop_pc_lob;\t// @[rob.scala:211:7, :583:22]\n wire _io_flush_bits_flush_typ_T = ~is_mini_exception;\t// @[package.scala:81:59]\n wire _io_flush_bits_flush_typ_T_1 = exception_thrown & _io_flush_bits_flush_typ_T;\t// @[rob.scala:253:30, :593:{66,69}]\n wire _io_flush_bits_flush_typ_T_2 = flush_uop_uopc == 7'h6A;\t// @[rob.scala:583:22, :594:80]\n wire _io_flush_bits_flush_typ_T_3 = flush_commit_mask_0 & _io_flush_bits_flush_typ_T_2;\t// @[rob.scala:576:75, :594:{62,80}]\n wire _io_flush_bits_flush_typ_ret_T = ~flush_val;\t// @[rob.scala:172:11, :578:36]\n wire [2:0] _io_flush_bits_flush_typ_ret_T_1 = refetch_inst ? 3'h2 : 3'h4;\t// @[rob.scala:175:10, :569:39]\n wire [2:0] _io_flush_bits_flush_typ_ret_T_2 = _io_flush_bits_flush_typ_T_1 ? 3'h1 : _io_flush_bits_flush_typ_ret_T_1;\t// @[rob.scala:174:10, :175:10, :593:66]\n wire [2:0] _io_flush_bits_flush_typ_ret_T_3 = _io_flush_bits_flush_typ_T_3 ? 3'h3 : _io_flush_bits_flush_typ_ret_T_2;\t// @[rob.scala:173:10, :174:10, :594:62]\n assign io_flush_bits_flush_typ_ret = _io_flush_bits_flush_typ_ret_T ? 3'h0 : _io_flush_bits_flush_typ_ret_T_3;\t// @[rob.scala:172:{10,11}, :173:10]\n assign io_flush_bits_flush_typ_0 = io_flush_bits_flush_typ_ret;\t// @[rob.scala:172:10, :211:7]\n wire _fflags_val_0_T_2;\t// @[rob.scala:608:32]\n assign io_commit_fflags_valid_0 = fflags_val_0;\t// @[rob.scala:211:7, :602:24]\n wire [4:0] _fflags_0_T;\t// @[rob.scala:611:21]\n assign io_commit_fflags_bits_0 = fflags_0;\t// @[rob.scala:211:7, :603:24]\n wire _fflags_val_0_T = io_commit_valids_0_0 & io_commit_uops_0_fp_val_0;\t// @[rob.scala:211:7, :607:27]\n wire _fflags_val_0_T_1 = ~io_commit_uops_0_uses_stq_0;\t// @[rob.scala:211:7, :609:7]\n assign _fflags_val_0_T_2 = _fflags_val_0_T & _fflags_val_0_T_1;\t// @[rob.scala:607:27, :608:32, :609:7]\n assign fflags_val_0 = _fflags_val_0_T_2;\t// @[rob.scala:602:24, :608:32]\n assign _fflags_0_T = fflags_val_0 ? rob_head_fflags_0 : 5'h0;\t// @[rob.scala:251:33, :602:24, :611:21]\n assign fflags_0 = _fflags_0_T;\t// @[rob.scala:603:24, :611:21]\n wire [3:0] next_xcpt_uop_ctrl_br_type;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_ctrl_op1_sel;\t// @[rob.scala:630:27]\n wire [2:0] next_xcpt_uop_ctrl_op2_sel;\t// @[rob.scala:630:27]\n wire [2:0] next_xcpt_uop_ctrl_imm_sel;\t// @[rob.scala:630:27]\n wire [4:0] next_xcpt_uop_ctrl_op_fcn;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_ctrl_fcn_dw;\t// @[rob.scala:630:27]\n wire [2:0] next_xcpt_uop_ctrl_csr_cmd;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_ctrl_is_load;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_ctrl_is_sta;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_ctrl_is_std;\t// @[rob.scala:630:27]\n wire [6:0] next_xcpt_uop_uopc;\t// @[rob.scala:630:27]\n wire [31:0] next_xcpt_uop_inst;\t// @[rob.scala:630:27]\n wire [31:0] next_xcpt_uop_debug_inst;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_rvc;\t// @[rob.scala:630:27]\n wire [39:0] next_xcpt_uop_debug_pc;\t// @[rob.scala:630:27]\n wire [2:0] next_xcpt_uop_iq_type;\t// @[rob.scala:630:27]\n wire [9:0] next_xcpt_uop_fu_code;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_iw_state;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_iw_p1_poisoned;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_iw_p2_poisoned;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_br;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_jalr;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_jal;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_sfb;\t// @[rob.scala:630:27]\n wire [7:0] next_xcpt_uop_br_mask;\t// @[rob.scala:630:27]\n wire [2:0] next_xcpt_uop_br_tag;\t// @[rob.scala:630:27]\n wire [3:0] next_xcpt_uop_ftq_idx;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_edge_inst;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_pc_lob;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_taken;\t// @[rob.scala:630:27]\n wire [19:0] next_xcpt_uop_imm_packed;\t// @[rob.scala:630:27]\n wire [11:0] next_xcpt_uop_csr_addr;\t// @[rob.scala:630:27]\n wire [4:0] next_xcpt_uop_rob_idx;\t// @[rob.scala:630:27]\n wire [2:0] next_xcpt_uop_ldq_idx;\t// @[rob.scala:630:27]\n wire [2:0] next_xcpt_uop_stq_idx;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_rxq_idx;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_pdst;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_prs1;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_prs2;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_prs3;\t// @[rob.scala:630:27]\n wire [3:0] next_xcpt_uop_ppred;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_prs1_busy;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_prs2_busy;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_prs3_busy;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_ppred_busy;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_stale_pdst;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_exception;\t// @[rob.scala:630:27]\n wire [63:0] next_xcpt_uop_exc_cause;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_bypassable;\t// @[rob.scala:630:27]\n wire [4:0] next_xcpt_uop_mem_cmd;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_mem_size;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_mem_signed;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_fence;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_fencei;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_amo;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_uses_ldq;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_uses_stq;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_sys_pc2epc;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_is_unique;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_flush_on_commit;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_ldst_is_rs1;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_ldst;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_lrs1;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_lrs2;\t// @[rob.scala:630:27]\n wire [5:0] next_xcpt_uop_lrs3;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_ldst_val;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_dst_rtype;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_lrs1_rtype;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_lrs2_rtype;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_frs3_en;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_fp_val;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_fp_single;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_xcpt_pf_if;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_xcpt_ae_if;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_xcpt_ma_if;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_bp_debug_if;\t// @[rob.scala:630:27]\n wire next_xcpt_uop_bp_xcpt_if;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_debug_fsrc;\t// @[rob.scala:630:27]\n wire [1:0] next_xcpt_uop_debug_tsrc;\t// @[rob.scala:630:27]\n wire _enq_xcpts_0_T;\t// @[rob.scala:634:38]\n wire enq_xcpts_0;\t// @[rob.scala:632:23]\n assign _enq_xcpts_0_T = io_enq_valids_0_0 & io_enq_uops_0_exception_0;\t// @[rob.scala:211:7, :634:38]\n assign enq_xcpts_0 = _enq_xcpts_0_T;\t// @[rob.scala:632:23, :634:38]\n wire _T_270 = ~(io_flush_valid_0 | exception_thrown) & rob_state != 2'h2;\t// @[rob.scala:211:7, :220:26, :253:30, :637:{9,26,47,60}]\n wire _lxcpt_older_T_1 = io_lxcpt_bits_uop_rob_idx_0 < io_csr_replay_bits_uop_rob_idx_0;\t// @[util.scala:363:52]\n wire _lxcpt_older_T_2 = io_lxcpt_bits_uop_rob_idx_0 < rob_head;\t// @[util.scala:363:64]\n wire _lxcpt_older_T_3 = _lxcpt_older_T_1 ^ _lxcpt_older_T_2;\t// @[util.scala:363:{52,58,64}]\n wire _lxcpt_older_T_4 = io_csr_replay_bits_uop_rob_idx_0 < rob_head;\t// @[util.scala:363:78]\n wire _lxcpt_older_T_5 = _lxcpt_older_T_3 ^ _lxcpt_older_T_4;\t// @[util.scala:363:{58,72,78}]\n wire _lxcpt_older_T_6 = _lxcpt_older_T_5 & io_lxcpt_valid_0;\t// @[util.scala:363:72]\n wire _T_277 = ~r_xcpt_val | new_xcpt_uop_rob_idx < r_xcpt_uop_rob_idx ^ new_xcpt_uop_rob_idx < rob_head ^ r_xcpt_uop_rob_idx < rob_head;\t// @[util.scala:363:{52,58,64,72,78}]\n wire _T_279 = ~r_xcpt_val & enq_xcpts_0;\t// @[rob.scala:257:33, :632:23, :650:{18,30}]\n assign next_xcpt_uop_uopc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_uopc : r_xcpt_uop_uopc) : _T_279 ? io_enq_uops_0_uopc_0 : r_xcpt_uop_uopc) : r_xcpt_uop_uopc;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_inst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_inst : r_xcpt_uop_inst) : _T_279 ? io_enq_uops_0_inst_0 : r_xcpt_uop_inst) : r_xcpt_uop_inst;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_debug_inst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_inst : r_xcpt_uop_debug_inst) : _T_279 ? io_enq_uops_0_debug_inst_0 : r_xcpt_uop_debug_inst) : r_xcpt_uop_debug_inst;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_rvc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_rvc : r_xcpt_uop_is_rvc) : _T_279 ? io_enq_uops_0_is_rvc_0 : r_xcpt_uop_is_rvc) : r_xcpt_uop_is_rvc;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_debug_pc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_pc : r_xcpt_uop_debug_pc) : _T_279 ? io_enq_uops_0_debug_pc_0 : r_xcpt_uop_debug_pc) : r_xcpt_uop_debug_pc;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_iq_type = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iq_type : r_xcpt_uop_iq_type) : _T_279 ? io_enq_uops_0_iq_type_0 : r_xcpt_uop_iq_type) : r_xcpt_uop_iq_type;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_fu_code = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_fu_code : r_xcpt_uop_fu_code) : _T_279 ? io_enq_uops_0_fu_code_0 : r_xcpt_uop_fu_code) : r_xcpt_uop_fu_code;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_br_type = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_br_type : r_xcpt_uop_ctrl_br_type) : _T_279 ? io_enq_uops_0_ctrl_br_type_0 : r_xcpt_uop_ctrl_br_type) : r_xcpt_uop_ctrl_br_type;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_op1_sel = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_op1_sel : r_xcpt_uop_ctrl_op1_sel) : _T_279 ? io_enq_uops_0_ctrl_op1_sel_0 : r_xcpt_uop_ctrl_op1_sel) : r_xcpt_uop_ctrl_op1_sel;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_op2_sel = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_op2_sel : r_xcpt_uop_ctrl_op2_sel) : _T_279 ? io_enq_uops_0_ctrl_op2_sel_0 : r_xcpt_uop_ctrl_op2_sel) : r_xcpt_uop_ctrl_op2_sel;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_imm_sel = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_imm_sel : r_xcpt_uop_ctrl_imm_sel) : _T_279 ? io_enq_uops_0_ctrl_imm_sel_0 : r_xcpt_uop_ctrl_imm_sel) : r_xcpt_uop_ctrl_imm_sel;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_op_fcn = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_op_fcn : r_xcpt_uop_ctrl_op_fcn) : _T_279 ? io_enq_uops_0_ctrl_op_fcn_0 : r_xcpt_uop_ctrl_op_fcn) : r_xcpt_uop_ctrl_op_fcn;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_fcn_dw = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_fcn_dw : r_xcpt_uop_ctrl_fcn_dw) : _T_279 ? io_enq_uops_0_ctrl_fcn_dw_0 : r_xcpt_uop_ctrl_fcn_dw) : r_xcpt_uop_ctrl_fcn_dw;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_csr_cmd = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_csr_cmd : r_xcpt_uop_ctrl_csr_cmd) : _T_279 ? io_enq_uops_0_ctrl_csr_cmd_0 : r_xcpt_uop_ctrl_csr_cmd) : r_xcpt_uop_ctrl_csr_cmd;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_is_load = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_is_load : r_xcpt_uop_ctrl_is_load) : _T_279 ? io_enq_uops_0_ctrl_is_load_0 : r_xcpt_uop_ctrl_is_load) : r_xcpt_uop_ctrl_is_load;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_is_sta = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_is_sta : r_xcpt_uop_ctrl_is_sta) : _T_279 ? io_enq_uops_0_ctrl_is_sta_0 : r_xcpt_uop_ctrl_is_sta) : r_xcpt_uop_ctrl_is_sta;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ctrl_is_std = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_is_std : r_xcpt_uop_ctrl_is_std) : _T_279 ? io_enq_uops_0_ctrl_is_std_0 : r_xcpt_uop_ctrl_is_std) : r_xcpt_uop_ctrl_is_std;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_iw_state = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iw_state : r_xcpt_uop_iw_state) : _T_279 ? io_enq_uops_0_iw_state_0 : r_xcpt_uop_iw_state) : r_xcpt_uop_iw_state;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_iw_p1_poisoned = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iw_p1_poisoned : r_xcpt_uop_iw_p1_poisoned) : _T_279 ? io_enq_uops_0_iw_p1_poisoned_0 : r_xcpt_uop_iw_p1_poisoned) : r_xcpt_uop_iw_p1_poisoned;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_iw_p2_poisoned = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iw_p2_poisoned : r_xcpt_uop_iw_p2_poisoned) : _T_279 ? io_enq_uops_0_iw_p2_poisoned_0 : r_xcpt_uop_iw_p2_poisoned) : r_xcpt_uop_iw_p2_poisoned;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_br = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_br : r_xcpt_uop_is_br) : _T_279 ? io_enq_uops_0_is_br_0 : r_xcpt_uop_is_br) : r_xcpt_uop_is_br;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_jalr = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_jalr : r_xcpt_uop_is_jalr) : _T_279 ? io_enq_uops_0_is_jalr_0 : r_xcpt_uop_is_jalr) : r_xcpt_uop_is_jalr;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_jal = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_jal : r_xcpt_uop_is_jal) : _T_279 ? io_enq_uops_0_is_jal_0 : r_xcpt_uop_is_jal) : r_xcpt_uop_is_jal;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_sfb = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_sfb : r_xcpt_uop_is_sfb) : _T_279 ? io_enq_uops_0_is_sfb_0 : r_xcpt_uop_is_sfb) : r_xcpt_uop_is_sfb;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_br_mask = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_br_mask : r_xcpt_uop_br_mask) : _T_279 ? io_enq_uops_0_br_mask_0 : r_xcpt_uop_br_mask) : r_xcpt_uop_br_mask;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_br_tag = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_br_tag : r_xcpt_uop_br_tag) : _T_279 ? io_enq_uops_0_br_tag_0 : r_xcpt_uop_br_tag) : r_xcpt_uop_br_tag;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ftq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ftq_idx : r_xcpt_uop_ftq_idx) : _T_279 ? io_enq_uops_0_ftq_idx_0 : r_xcpt_uop_ftq_idx) : r_xcpt_uop_ftq_idx;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_edge_inst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_edge_inst : r_xcpt_uop_edge_inst) : _T_279 ? io_enq_uops_0_edge_inst_0 : r_xcpt_uop_edge_inst) : r_xcpt_uop_edge_inst;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_pc_lob = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_pc_lob : r_xcpt_uop_pc_lob) : _T_279 ? io_enq_uops_0_pc_lob_0 : r_xcpt_uop_pc_lob) : r_xcpt_uop_pc_lob;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_taken = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_taken : r_xcpt_uop_taken) : _T_279 ? io_enq_uops_0_taken_0 : r_xcpt_uop_taken) : r_xcpt_uop_taken;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_imm_packed = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_imm_packed : r_xcpt_uop_imm_packed) : _T_279 ? io_enq_uops_0_imm_packed_0 : r_xcpt_uop_imm_packed) : r_xcpt_uop_imm_packed;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_csr_addr = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_csr_addr : r_xcpt_uop_csr_addr) : _T_279 ? io_enq_uops_0_csr_addr_0 : r_xcpt_uop_csr_addr) : r_xcpt_uop_csr_addr;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_rob_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_rob_idx : r_xcpt_uop_rob_idx) : _T_279 ? io_enq_uops_0_rob_idx_0 : r_xcpt_uop_rob_idx) : r_xcpt_uop_rob_idx;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ldq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldq_idx : r_xcpt_uop_ldq_idx) : _T_279 ? io_enq_uops_0_ldq_idx_0 : r_xcpt_uop_ldq_idx) : r_xcpt_uop_ldq_idx;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_stq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_stq_idx : r_xcpt_uop_stq_idx) : _T_279 ? io_enq_uops_0_stq_idx_0 : r_xcpt_uop_stq_idx) : r_xcpt_uop_stq_idx;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_rxq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_rxq_idx : r_xcpt_uop_rxq_idx) : _T_279 ? io_enq_uops_0_rxq_idx_0 : r_xcpt_uop_rxq_idx) : r_xcpt_uop_rxq_idx;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_pdst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_pdst : r_xcpt_uop_pdst) : _T_279 ? io_enq_uops_0_pdst_0 : r_xcpt_uop_pdst) : r_xcpt_uop_pdst;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_prs1 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs1 : r_xcpt_uop_prs1) : _T_279 ? io_enq_uops_0_prs1_0 : r_xcpt_uop_prs1) : r_xcpt_uop_prs1;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_prs2 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs2 : r_xcpt_uop_prs2) : _T_279 ? io_enq_uops_0_prs2_0 : r_xcpt_uop_prs2) : r_xcpt_uop_prs2;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_prs3 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs3 : r_xcpt_uop_prs3) : _T_279 ? io_enq_uops_0_prs3_0 : r_xcpt_uop_prs3) : r_xcpt_uop_prs3;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ppred = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ppred : r_xcpt_uop_ppred) : _T_279 ? 4'h0 : r_xcpt_uop_ppred) : r_xcpt_uop_ppred;\t// @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_prs1_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs1_busy : r_xcpt_uop_prs1_busy) : _T_279 ? io_enq_uops_0_prs1_busy_0 : r_xcpt_uop_prs1_busy) : r_xcpt_uop_prs1_busy;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_prs2_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs2_busy : r_xcpt_uop_prs2_busy) : _T_279 ? io_enq_uops_0_prs2_busy_0 : r_xcpt_uop_prs2_busy) : r_xcpt_uop_prs2_busy;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_prs3_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs3_busy : r_xcpt_uop_prs3_busy) : _T_279 ? io_enq_uops_0_prs3_busy_0 : r_xcpt_uop_prs3_busy) : r_xcpt_uop_prs3_busy;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ppred_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ppred_busy : r_xcpt_uop_ppred_busy) : ~_T_279 & r_xcpt_uop_ppred_busy) : r_xcpt_uop_ppred_busy;\t// @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_stale_pdst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_stale_pdst : r_xcpt_uop_stale_pdst) : _T_279 ? io_enq_uops_0_stale_pdst_0 : r_xcpt_uop_stale_pdst) : r_xcpt_uop_stale_pdst;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_exception = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_exception : r_xcpt_uop_exception) : _T_279 ? io_enq_uops_0_exception_0 : r_xcpt_uop_exception) : r_xcpt_uop_exception;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_exc_cause = _T_270 ? (new_xcpt_valid ? (_T_277 ? {59'h0, new_xcpt_cause} : r_xcpt_uop_exc_cause) : _T_279 ? io_enq_uops_0_exc_cause_0 : r_xcpt_uop_exc_cause) : r_xcpt_uop_exc_cause;\t// @[package.scala:16:47]\n assign next_xcpt_uop_bypassable = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_bypassable : r_xcpt_uop_bypassable) : _T_279 ? io_enq_uops_0_bypassable_0 : r_xcpt_uop_bypassable) : r_xcpt_uop_bypassable;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_mem_cmd = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_mem_cmd : r_xcpt_uop_mem_cmd) : _T_279 ? io_enq_uops_0_mem_cmd_0 : r_xcpt_uop_mem_cmd) : r_xcpt_uop_mem_cmd;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_mem_size = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_mem_size : r_xcpt_uop_mem_size) : _T_279 ? io_enq_uops_0_mem_size_0 : r_xcpt_uop_mem_size) : r_xcpt_uop_mem_size;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_mem_signed = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_mem_signed : r_xcpt_uop_mem_signed) : _T_279 ? io_enq_uops_0_mem_signed_0 : r_xcpt_uop_mem_signed) : r_xcpt_uop_mem_signed;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_fence = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_fence : r_xcpt_uop_is_fence) : _T_279 ? io_enq_uops_0_is_fence_0 : r_xcpt_uop_is_fence) : r_xcpt_uop_is_fence;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_fencei = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_fencei : r_xcpt_uop_is_fencei) : _T_279 ? io_enq_uops_0_is_fencei_0 : r_xcpt_uop_is_fencei) : r_xcpt_uop_is_fencei;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_amo = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_amo : r_xcpt_uop_is_amo) : _T_279 ? io_enq_uops_0_is_amo_0 : r_xcpt_uop_is_amo) : r_xcpt_uop_is_amo;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_uses_ldq = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_uses_ldq : r_xcpt_uop_uses_ldq) : _T_279 ? io_enq_uops_0_uses_ldq_0 : r_xcpt_uop_uses_ldq) : r_xcpt_uop_uses_ldq;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_uses_stq = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_uses_stq : r_xcpt_uop_uses_stq) : _T_279 ? io_enq_uops_0_uses_stq_0 : r_xcpt_uop_uses_stq) : r_xcpt_uop_uses_stq;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_sys_pc2epc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_sys_pc2epc : r_xcpt_uop_is_sys_pc2epc) : _T_279 ? io_enq_uops_0_is_sys_pc2epc_0 : r_xcpt_uop_is_sys_pc2epc) : r_xcpt_uop_is_sys_pc2epc;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_is_unique = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_unique : r_xcpt_uop_is_unique) : _T_279 ? io_enq_uops_0_is_unique_0 : r_xcpt_uop_is_unique) : r_xcpt_uop_is_unique;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_flush_on_commit = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_flush_on_commit : r_xcpt_uop_flush_on_commit) : _T_279 ? io_enq_uops_0_flush_on_commit_0 : r_xcpt_uop_flush_on_commit) : r_xcpt_uop_flush_on_commit;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ldst_is_rs1 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldst_is_rs1 : r_xcpt_uop_ldst_is_rs1) : _T_279 ? io_enq_uops_0_ldst_is_rs1_0 : r_xcpt_uop_ldst_is_rs1) : r_xcpt_uop_ldst_is_rs1;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ldst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldst : r_xcpt_uop_ldst) : _T_279 ? io_enq_uops_0_ldst_0 : r_xcpt_uop_ldst) : r_xcpt_uop_ldst;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_lrs1 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs1 : r_xcpt_uop_lrs1) : _T_279 ? io_enq_uops_0_lrs1_0 : r_xcpt_uop_lrs1) : r_xcpt_uop_lrs1;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_lrs2 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs2 : r_xcpt_uop_lrs2) : _T_279 ? io_enq_uops_0_lrs2_0 : r_xcpt_uop_lrs2) : r_xcpt_uop_lrs2;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_lrs3 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs3 : r_xcpt_uop_lrs3) : _T_279 ? io_enq_uops_0_lrs3_0 : r_xcpt_uop_lrs3) : r_xcpt_uop_lrs3;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_ldst_val = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldst_val : r_xcpt_uop_ldst_val) : _T_279 ? io_enq_uops_0_ldst_val_0 : r_xcpt_uop_ldst_val) : r_xcpt_uop_ldst_val;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_dst_rtype = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_dst_rtype : r_xcpt_uop_dst_rtype) : _T_279 ? io_enq_uops_0_dst_rtype_0 : r_xcpt_uop_dst_rtype) : r_xcpt_uop_dst_rtype;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_lrs1_rtype = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs1_rtype : r_xcpt_uop_lrs1_rtype) : _T_279 ? io_enq_uops_0_lrs1_rtype_0 : r_xcpt_uop_lrs1_rtype) : r_xcpt_uop_lrs1_rtype;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_lrs2_rtype = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs2_rtype : r_xcpt_uop_lrs2_rtype) : _T_279 ? io_enq_uops_0_lrs2_rtype_0 : r_xcpt_uop_lrs2_rtype) : r_xcpt_uop_lrs2_rtype;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_frs3_en = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_frs3_en : r_xcpt_uop_frs3_en) : _T_279 ? io_enq_uops_0_frs3_en_0 : r_xcpt_uop_frs3_en) : r_xcpt_uop_frs3_en;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_fp_val = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_fp_val : r_xcpt_uop_fp_val) : _T_279 ? io_enq_uops_0_fp_val_0 : r_xcpt_uop_fp_val) : r_xcpt_uop_fp_val;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_fp_single = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_fp_single : r_xcpt_uop_fp_single) : _T_279 ? io_enq_uops_0_fp_single_0 : r_xcpt_uop_fp_single) : r_xcpt_uop_fp_single;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_xcpt_pf_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_xcpt_pf_if : r_xcpt_uop_xcpt_pf_if) : _T_279 ? io_enq_uops_0_xcpt_pf_if_0 : r_xcpt_uop_xcpt_pf_if) : r_xcpt_uop_xcpt_pf_if;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_xcpt_ae_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_xcpt_ae_if : r_xcpt_uop_xcpt_ae_if) : _T_279 ? io_enq_uops_0_xcpt_ae_if_0 : r_xcpt_uop_xcpt_ae_if) : r_xcpt_uop_xcpt_ae_if;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_xcpt_ma_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_xcpt_ma_if : r_xcpt_uop_xcpt_ma_if) : _T_279 ? io_enq_uops_0_xcpt_ma_if_0 : r_xcpt_uop_xcpt_ma_if) : r_xcpt_uop_xcpt_ma_if;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_bp_debug_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_bp_debug_if : r_xcpt_uop_bp_debug_if) : _T_279 ? io_enq_uops_0_bp_debug_if_0 : r_xcpt_uop_bp_debug_if) : r_xcpt_uop_bp_debug_if;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_bp_xcpt_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_bp_xcpt_if : r_xcpt_uop_bp_xcpt_if) : _T_279 ? io_enq_uops_0_bp_xcpt_if_0 : r_xcpt_uop_bp_xcpt_if) : r_xcpt_uop_bp_xcpt_if;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_debug_fsrc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_fsrc : r_xcpt_uop_debug_fsrc) : _T_279 ? io_enq_uops_0_debug_fsrc_0 : r_xcpt_uop_debug_fsrc) : r_xcpt_uop_debug_fsrc;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n assign next_xcpt_uop_debug_tsrc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_tsrc : r_xcpt_uop_debug_tsrc) : _T_279 ? io_enq_uops_0_debug_tsrc_0 : r_xcpt_uop_debug_tsrc) : r_xcpt_uop_debug_tsrc;\t// @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]\n wire [39:0] _r_xcpt_badvaddr_T = ~io_xcpt_fetch_pc_0;\t// @[util.scala:237:7]\n wire [39:0] _r_xcpt_badvaddr_T_1 = {_r_xcpt_badvaddr_T[39:6], 6'h3F};\t// @[util.scala:237:{7,11}]\n wire [39:0] _r_xcpt_badvaddr_T_2 = ~_r_xcpt_badvaddr_T_1;\t// @[util.scala:237:{5,11}]\n wire [39:0] _r_xcpt_badvaddr_T_3 = {_r_xcpt_badvaddr_T_2[39:6], _r_xcpt_badvaddr_T_2[5:0] | io_enq_uops_0_pc_lob_0};\t// @[util.scala:237:5]\n wire [7:0] _r_xcpt_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:85:27, :89:23]\n wire [7:0] _r_xcpt_uop_br_mask_T_1 = next_xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T;\t// @[util.scala:85:{25,27}]\n wire rob_deq;\t// @[rob.scala:685:25]\n reg r_partial_row;\t// @[rob.scala:686:30]\n wire _finished_committing_row_T_1 = will_commit_0 ^ rob_head_vals_0;\t// @[rob.scala:242:33, :247:33, :694:26]\n wire _finished_committing_row_T_2 = ~_finished_committing_row_T_1;\t// @[rob.scala:694:{26,50}]\n wire _finished_committing_row_T_3 = _finished_committing_row_T & _finished_committing_row_T_2;\t// @[rob.scala:693:{30,39}, :694:50]\n wire _T_339 = rob_head == rob_tail;\t// @[rob.scala:223:29, :227:29, :695:33]\n wire _finished_committing_row_T_4;\t// @[rob.scala:695:33]\n assign _finished_committing_row_T_4 = _T_339;\t// @[rob.scala:695:33]\n wire _full_T;\t// @[rob.scala:796:26]\n assign _full_T = _T_339;\t// @[rob.scala:695:33, :796:26]\n wire _empty_T;\t// @[rob.scala:797:27]\n assign _empty_T = _T_339;\t// @[rob.scala:695:33, :797:27]\n wire _finished_committing_row_T_5 = r_partial_row & _finished_committing_row_T_4;\t// @[rob.scala:686:30, :695:{21,33}]\n wire _finished_committing_row_T_6 = ~maybe_full;\t// @[rob.scala:238:29, :695:49]\n wire _finished_committing_row_T_7 = _finished_committing_row_T_5 & _finished_committing_row_T_6;\t// @[rob.scala:695:{21,46,49}]\n wire _finished_committing_row_T_8 = ~_finished_committing_row_T_7;\t// @[rob.scala:695:{5,46}]\n wire finished_committing_row = _finished_committing_row_T_3 & _finished_committing_row_T_8;\t// @[rob.scala:693:39, :694:59, :695:5]\n wire [5:0] _rob_head_T = {1'h0, rob_head} + 6'h1;\t// @[util.scala:203:14]\n wire [4:0] _rob_head_T_1 = _rob_head_T[4:0];\t// @[util.scala:203:14]\n wire [4:0] _rob_head_T_2 = _rob_head_T_1;\t// @[util.scala:203:{14,20}]\n wire _rob_head_lsb_T_1 = _rob_head_lsb_T;\t// @[OneHot.scala:85:71]\n reg pnr_maybe_at_tail;\t// @[rob.scala:723:36]\n wire _T_349 = rob_state == 2'h1;\t// @[rob.scala:220:26, :725:33]\n wire _safe_to_inc_T;\t// @[rob.scala:725:33]\n assign _safe_to_inc_T = _T_349;\t// @[rob.scala:725:33]\n wire _io_ready_T;\t// @[rob.scala:803:33]\n assign _io_ready_T = _T_349;\t// @[rob.scala:725:33, :803:33]\n wire _safe_to_inc_T_1 = &rob_state;\t// @[rob.scala:220:26, :725:59]\n wire safe_to_inc = _safe_to_inc_T | _safe_to_inc_T_1;\t// @[rob.scala:725:{33,46,59}]\n wire _do_inc_row_T = ~rob_pnr_unsafe_0;\t// @[rob.scala:246:33, :726:23]\n wire _do_inc_row_T_1 = rob_pnr != rob_tail;\t// @[rob.scala:227:29, :231:29, :726:64]\n wire _do_inc_row_T_2 = ~pnr_maybe_at_tail;\t// @[rob.scala:723:36, :726:89]\n wire _do_inc_row_T_3 = full & _do_inc_row_T_2;\t// @[rob.scala:239:26, :726:{86,89}]\n wire _do_inc_row_T_4 = _do_inc_row_T_1 | _do_inc_row_T_3;\t// @[rob.scala:726:{64,77,86}]\n wire do_inc_row = _do_inc_row_T & _do_inc_row_T_4;\t// @[rob.scala:726:{23,52,77}]\n wire [5:0] _rob_pnr_T = {1'h0, rob_pnr} + 6'h1;\t// @[util.scala:203:14]\n wire [4:0] _rob_pnr_T_1 = _rob_pnr_T[4:0];\t// @[util.scala:203:14]\n wire [4:0] _rob_pnr_T_2 = _rob_pnr_T_1;\t// @[util.scala:203:{14,20}]\n wire _rob_pnr_lsb_T_1 = ~_rob_pnr_lsb_T;\t// @[util.scala:373:29]\n wire _rob_pnr_lsb_T_2 = rob_pnr_unsafe_0 | _rob_pnr_lsb_T_1;\t// @[rob.scala:246:33, :740:{60,62}]\n wire _rob_pnr_lsb_T_3 = _rob_pnr_lsb_T_2;\t// @[OneHot.scala:48:45]\n wire _pnr_maybe_at_tail_T = ~rob_deq;\t// @[rob.scala:685:25, :745:26]\n wire _pnr_maybe_at_tail_T_1 = do_inc_row | pnr_maybe_at_tail;\t// @[rob.scala:723:36, :726:52, :745:50]\n wire _pnr_maybe_at_tail_T_2 = _pnr_maybe_at_tail_T & _pnr_maybe_at_tail_T_1;\t// @[rob.scala:745:{26,35,50}]"}}},{"rowIdx":32160,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_38 : \n output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} \n\n\n node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) \n node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) \n node _sigSum_T = bits(io.mulAddResult, 48, 48) \n node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) \n node _sigSum_T_2 = tail(_sigSum_T_1, 1) \n node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) \n node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) \n node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) \n node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) \n node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) \n node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) \n node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) \n node CDom_sExp = asSInt(_CDom_sExp_T_2) \n node _CDom_absSigSum_T = bits(sigSum, 74, 25) \n node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) \n node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) \n node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) \n node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) \n node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) \n node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) \n node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) \n node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) \n node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) \n node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) \n node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) \n node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) \n node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) \n node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) \n node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) \n node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) \n wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] \n node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) \n node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) \n connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 \n node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) \n node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) \n connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 \n node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) \n node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) \n connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 \n node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) \n node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) \n connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 \n node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) \n node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) \n connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 \n node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) \n node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) \n connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 \n node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) \n node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) \n connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 \n node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) \n node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) \n node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) \n node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) \n node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) \n node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) \n node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) \n node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) \n node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) \n node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) \n node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) \n node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) \n node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) \n node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) \n node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) \n node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) \n node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) \n node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) \n node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) \n node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) \n node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) \n node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) \n node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) \n node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) \n node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) \n node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) \n node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) \n node _CDom_sig_T = shr(CDom_mainSig, 3) \n node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) \n node _CDom_sig_T_2 = orr(_CDom_sig_T_1) \n node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) \n node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) \n node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) \n node notCDom_signSigSum = bits(sigSum, 51, 51) \n node _notCDom_absSigSum_T = bits(sigSum, 50, 0) \n node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) \n node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) \n node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) \n node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) \n node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) \n wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] \n node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) \n node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) \n node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) \n node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) \n node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) \n node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) \n node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) \n node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) \n node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) \n node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) \n node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) \n node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) \n node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) \n node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) \n node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) \n node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) \n node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) \n node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) \n node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) \n node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) \n node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) \n node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) \n node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) \n node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) \n node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) \n node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) \n node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 \n node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) \n node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) \n node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) \n node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) \n node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) \n node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) \n node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) \n node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) \n node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) \n node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) \n node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) \n node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) \n node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) \n node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) \n node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) \n node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) \n node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) \n node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) \n node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) \n node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) \n node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) \n node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) \n node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) \n node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) \n node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) \n node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) \n node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) \n node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) \n node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) \n node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) \n node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) \n node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) \n node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) \n node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) \n node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) \n node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) \n node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) \n node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) \n node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) \n node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) \n node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) \n node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) \n node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) \n node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) \n node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) \n node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) \n node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) \n node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) \n node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) \n node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) \n node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) \n node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) \n node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) \n node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) \n node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) \n node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) \n node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) \n node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) \n node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) \n node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) \n node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) \n node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) \n node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) \n node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) \n node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) \n node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) \n node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) \n node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) \n node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) \n node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) \n node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) \n node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) \n node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) \n node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) \n node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) \n node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) \n node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) \n node _notCDom_sExp_T = cvt(notCDom_nearNormDist) \n node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) \n node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) \n node notCDom_sExp = asSInt(_notCDom_sExp_T_2) \n node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) \n node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) \n node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) \n node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) \n wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] \n node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) \n node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) \n connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) \n node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) \n connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) \n node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) \n connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) \n node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) \n connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) \n node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) \n connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) \n node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) \n connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) \n node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) \n connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 \n node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) \n node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) \n node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) \n node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) \n node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) \n node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) \n node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) \n node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) \n node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) \n node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) \n node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) \n node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) \n node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) \n node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) \n node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) \n node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) \n node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) \n node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) \n node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) \n node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) \n node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) \n node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) \n node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) \n node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) \n node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) \n node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) \n node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) \n node _notCDom_sig_T = shr(notCDom_mainSig, 3) \n node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) \n node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) \n node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) \n node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) \n node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) \n node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) \n node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) \n node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) \n node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) \n node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) \n node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) \n node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) \n node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) \n node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) \n node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) \n node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) \n node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) \n node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) \n node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) \n node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) \n node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) \n node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) \n connect io.invalidExc, _io_invalidExc_T_9 \n node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) \n connect io.rawOut.isNaN, _io_rawOut_isNaN_T \n connect io.rawOut.isInf, notNaN_isInfOut \n node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) \n node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) \n node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) \n connect io.rawOut.isZero, _io_rawOut_isZero_T_2 \n node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) \n node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) \n node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) \n node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) \n node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) \n node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) \n node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) \n node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) \n node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) \n node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) \n node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) \n node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) \n node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) \n node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) \n node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) \n node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) \n node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) \n node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) \n connect io.rawOut.sign, _io_rawOut_sign_T_17 \n node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) \n connect io.rawOut.sExp, _io_rawOut_sExp_T \n node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) \n connect io.rawOut.sig, _io_rawOut_sig_T"},"response":{"kind":"string","value":"module MulAddRecFNToRaw_postMul_e8_s24_38(\t// @[MulAddRecFN.scala:169:7]\n input io_fromPreMul_isSigNaNAny,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isNaNAOrB,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isInfA,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isZeroA,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_signProd,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isNaNC,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isInfC,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isZeroC,\t// @[MulAddRecFN.scala:172:16]\n input [9:0] io_fromPreMul_sExpSum,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_doSubMags,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_CIsDominant,\t// @[MulAddRecFN.scala:172:16]\n input [4:0] io_fromPreMul_CDom_CAlignDist,\t// @[MulAddRecFN.scala:172:16]\n input [25:0] io_fromPreMul_highAlignedSigC,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_bit0AlignedSigC,\t// @[MulAddRecFN.scala:172:16]\n input [48:0] io_mulAddResult,\t// @[MulAddRecFN.scala:172:16]\n output io_invalidExc,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_isNaN,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_isInf,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_isZero,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_sign,\t// @[MulAddRecFN.scala:172:16]\n output [9:0] io_rawOut_sExp,\t// @[MulAddRecFN.scala:172:16]\n output [26:0] io_rawOut_sig\t// @[MulAddRecFN.scala:172:16]\n);\n\n wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC;\t// @[MulAddRecFN.scala:169:7]\n wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant;\t// @[MulAddRecFN.scala:169:7]\n wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist;\t// @[MulAddRecFN.scala:169:7]\n wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC;\t// @[MulAddRecFN.scala:169:7]\n wire [48:0] io_mulAddResult_0 = io_mulAddResult;\t// @[MulAddRecFN.scala:169:7]\n wire _io_rawOut_sign_T_3 = 1'h1;\t// @[MulAddRecFN.scala:287:29]\n wire [2:0] io_roundingMode = 3'h0;\t// @[MulAddRecFN.scala:169:7, :172:16]\n wire io_fromPreMul_isInfB = 1'h0;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isZeroB = 1'h0;\t// @[MulAddRecFN.scala:169:7]\n wire roundingMode_min = 1'h0;\t// @[MulAddRecFN.scala:186:45]\n wire _io_invalidExc_T = 1'h0;\t// @[MulAddRecFN.scala:272:31]\n wire _io_invalidExc_T_2 = 1'h0;\t// @[MulAddRecFN.scala:273:32]\n wire _io_rawOut_sign_T_8 = 1'h0;\t// @[MulAddRecFN.scala:289:26]\n wire _io_rawOut_sign_T_10 = 1'h0;\t// @[MulAddRecFN.scala:289:46]\n wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0;\t// @[MulAddRecFN.scala:169:7, :271:35]\n wire notNaN_isInfProd = io_fromPreMul_isInfA_0;\t// @[MulAddRecFN.scala:169:7, :264:49]\n wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0;\t// @[MulAddRecFN.scala:169:7, :275:36]\n wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0;\t// @[MulAddRecFN.scala:169:7, :267:32]\n wire _io_invalidExc_T_9;\t// @[MulAddRecFN.scala:273:57]\n wire _io_rawOut_isNaN_T;\t// @[MulAddRecFN.scala:278:48]\n wire notNaN_isInfOut;\t// @[MulAddRecFN.scala:265:44]\n wire _io_rawOut_isZero_T_2;\t// @[MulAddRecFN.scala:282:25]\n wire _io_rawOut_sign_T_17;\t// @[MulAddRecFN.scala:290:50]\n wire [9:0] _io_rawOut_sExp_T;\t// @[MulAddRecFN.scala:293:26]\n wire [26:0] _io_rawOut_sig_T;\t// @[MulAddRecFN.scala:294:25]\n wire io_rawOut_isNaN_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_rawOut_isInf_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_rawOut_isZero_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_rawOut_sign_0;\t// @[MulAddRecFN.scala:169:7]\n wire [9:0] io_rawOut_sExp_0;\t// @[MulAddRecFN.scala:169:7]\n wire [26:0] io_rawOut_sig_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_invalidExc_0;\t// @[MulAddRecFN.scala:169:7]\n wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0;\t// @[MulAddRecFN.scala:169:7, :190:42]\n wire _sigSum_T = io_mulAddResult_0[48];\t// @[MulAddRecFN.scala:169:7, :192:32]\n wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1;\t// @[MulAddRecFN.scala:169:7, :193:47]\n wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0];\t// @[MulAddRecFN.scala:193:47]\n wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0;\t// @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]\n wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0];\t// @[MulAddRecFN.scala:169:7, :196:28]\n wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4};\t// @[MulAddRecFN.scala:192:{12,16}, :196:28]\n wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0};\t// @[MulAddRecFN.scala:169:7, :192:12]\n wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0};\t// @[MulAddRecFN.scala:169:7, :203:69]\n wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0};\t// @[MulAddRecFN.scala:169:7, :203:43]\n wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T};\t// @[MulAddRecFN.scala:203:{43,69}]\n wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0];\t// @[MulAddRecFN.scala:203:43]\n wire [9:0] CDom_sExp = _CDom_sExp_T_2;\t// @[MulAddRecFN.scala:203:43]\n wire [49:0] _CDom_absSigSum_T = sigSum[74:25];\t// @[MulAddRecFN.scala:192:12, :206:20]\n wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T;\t// @[MulAddRecFN.scala:206:{13,20}]\n wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24];\t// @[MulAddRecFN.scala:169:7, :209:46]\n wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2};\t// @[MulAddRecFN.scala:207:22, :209:46]\n wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26];\t// @[MulAddRecFN.scala:192:12, :210:23]\n wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4};\t// @[MulAddRecFN.scala:207:22, :209:71, :210:23]\n wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5;\t// @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]\n wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1];\t// @[MulAddRecFN.scala:192:12, :215:21]\n wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T;\t// @[MulAddRecFN.scala:215:{14,21}]\n wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1;\t// @[MulAddRecFN.scala:215:{14,36}]\n wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1];\t// @[MulAddRecFN.scala:192:12, :216:19]\n wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3;\t// @[MulAddRecFN.scala:216:{19,37}]\n wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4;\t// @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]\n wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0;\t// @[MulAddRecFN.scala:169:7, :205:12, :219:24]\n wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21];\t// @[MulAddRecFN.scala:219:{24,56}]\n wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0];\t// @[MulAddRecFN.scala:205:12, :222:36]\n wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0};\t// @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]\n wire _CDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_3_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_4_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_5_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_6_T_1;\t// @[primitives.scala:123:57]\n wire CDom_reduced4SigExtra_reducedVec_0;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_1;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_2;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_3;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_4;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_5;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_6;\t// @[primitives.scala:118:30]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24];\t// @[primitives.scala:123:15]\n assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T;\t// @[primitives.scala:123:{15,57}]\n assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1;\t// @[primitives.scala:118:30, :123:57]\n wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1};\t// @[primitives.scala:118:30, :124:20]\n wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0};\t// @[primitives.scala:118:30, :124:20]\n wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3};\t// @[primitives.scala:118:30, :124:20]\n wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5};\t// @[primitives.scala:118:30, :124:20]\n wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo};\t// @[primitives.scala:124:20]\n wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo};\t// @[primitives.scala:124:20]\n wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2];\t// @[MulAddRecFN.scala:169:7, :223:51]\n wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3;\t// @[primitives.scala:52:21]\n wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4);\t// @[primitives.scala:52:21, :76:56]\n wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1];\t// @[primitives.scala:76:56, :78:22]\n wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0];\t// @[primitives.scala:77:20, :78:22]\n wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0];\t// @[primitives.scala:77:20]\n wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0];\t// @[primitives.scala:77:20]\n wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1];\t// @[primitives.scala:77:20]\n wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9};\t// @[primitives.scala:77:20]\n wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2];\t// @[primitives.scala:77:20]\n wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0];\t// @[primitives.scala:77:20]\n wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1];\t// @[primitives.scala:77:20]\n wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13};\t// @[primitives.scala:77:20]\n wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14};\t// @[primitives.scala:77:20]\n wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4];\t// @[primitives.scala:77:20, :78:22]\n wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0];\t// @[primitives.scala:77:20]\n wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1];\t// @[primitives.scala:77:20]\n wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18};\t// @[primitives.scala:77:20]\n wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19};\t// @[primitives.scala:77:20]\n wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20};\t// @[primitives.scala:77:20, :124:20]\n wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21;\t// @[MulAddRecFN.scala:222:72, :223:73]\n wire [25:0] _CDom_sig_T = CDom_mainSig[28:3];\t// @[MulAddRecFN.scala:219:56, :225:25]\n wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0];\t// @[MulAddRecFN.scala:219:56, :226:25]\n wire _CDom_sig_T_2 = |_CDom_sig_T_1;\t// @[MulAddRecFN.scala:226:{25,32}]\n wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra;\t// @[MulAddRecFN.scala:223:73, :226:{32,36}]\n wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra;\t// @[MulAddRecFN.scala:214:12, :226:{36,61}]\n wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4};\t// @[MulAddRecFN.scala:225:{12,25}, :226:61]\n wire notCDom_signSigSum = sigSum[51];\t// @[MulAddRecFN.scala:192:12, :232:36]\n wire [50:0] _notCDom_absSigSum_T = sigSum[50:0];\t// @[MulAddRecFN.scala:192:12, :235:20]\n wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0];\t// @[MulAddRecFN.scala:192:12, :235:20, :236:19]\n wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T;\t// @[MulAddRecFN.scala:235:{13,20}]\n wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0};\t// @[MulAddRecFN.scala:169:7, :236:{19,41}]\n wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0];\t// @[MulAddRecFN.scala:236:41]\n wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4;\t// @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]\n wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1;\t// @[primitives.scala:106:57]\n wire notCDom_reduced2AbsSigSum_reducedVec_0;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_1;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_2;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_3;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_4;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_5;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_6;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_7;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_8;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_9;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_10;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_11;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_12;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_13;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_14;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_15;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_16;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_17;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_18;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_19;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_20;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_21;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_22;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_23;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_24;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_25;\t// @[primitives.scala:101:30]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50];\t// @[primitives.scala:106:15]\n assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T;\t// @[primitives.scala:106:{15,57}]\n assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1;\t// @[primitives.scala:101:30, :106:57]\n wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3};\t// @[primitives.scala:101:30, :107:20]\n wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo};\t// @[primitives.scala:107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11};\t// @[primitives.scala:101:30, :107:20]\n wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo};\t// @[primitives.scala:107:20]\n wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo};\t// @[primitives.scala:107:20]\n wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo};\t// @[primitives.scala:107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16};\t// @[primitives.scala:101:30, :107:20]\n wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo};\t// @[primitives.scala:107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24};\t// @[primitives.scala:101:30, :107:20]\n wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo};\t// @[primitives.scala:107:20]\n wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo};\t// @[primitives.scala:107:20]\n wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo};\t// @[primitives.scala:107:20]\n wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo};\t// @[primitives.scala:107:20]\n wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25];\t// @[primitives.scala:91:52, :107:20]\n wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1};\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47;\t// @[Mux.scala:50:70]\n wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48;\t// @[Mux.scala:50:70]\n wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49;\t// @[Mux.scala:50:70]\n wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0};\t// @[Mux.scala:50:70]\n wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist};\t// @[MulAddRecFN.scala:240:56, :241:76]\n wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T};\t// @[MulAddRecFN.scala:203:43, :241:{46,76}]\n wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0];\t// @[MulAddRecFN.scala:241:46]\n wire [9:0] notCDom_sExp = _notCDom_sExp_T_2;\t// @[MulAddRecFN.scala:241:46]\n wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist;\t// @[MulAddRecFN.scala:234:12, :240:56, :243:27]\n wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23];\t// @[MulAddRecFN.scala:243:{27,50}]\n wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0];\t// @[primitives.scala:107:20]\n wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T;\t// @[MulAddRecFN.scala:247:{39,55}]\n wire _notCDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_3_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_4_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_5_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_6_T_1;\t// @[primitives.scala:106:57]\n wire notCDom_reduced4SigExtra_reducedVec_0;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_1;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_2;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_3;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_4;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_5;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_6;\t// @[primitives.scala:101:30]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12];\t// @[primitives.scala:106:15]\n assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T;\t// @[primitives.scala:106:{15,57}]\n assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1;\t// @[primitives.scala:101:30, :106:57]\n wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5};\t// @[primitives.scala:101:30, :107:20]\n wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo};\t// @[primitives.scala:107:20]\n wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo};\t// @[primitives.scala:107:20]\n wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1];\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3;\t// @[primitives.scala:52:21]\n wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4);\t// @[primitives.scala:52:21, :76:56]\n wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1];\t// @[primitives.scala:76:56, :78:22]\n wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0];\t// @[primitives.scala:77:20, :78:22]\n wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0];\t// @[primitives.scala:77:20]\n wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0];\t// @[primitives.scala:77:20]\n wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1];\t// @[primitives.scala:77:20]\n wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9};\t// @[primitives.scala:77:20]\n wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2];\t// @[primitives.scala:77:20]\n wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0];\t// @[primitives.scala:77:20]\n wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1];\t// @[primitives.scala:77:20]\n wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13};\t// @[primitives.scala:77:20]\n wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14};\t// @[primitives.scala:77:20]\n wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4];\t// @[primitives.scala:77:20, :78:22]\n wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0];\t// @[primitives.scala:77:20]\n wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1];\t// @[primitives.scala:77:20]\n wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18};\t// @[primitives.scala:77:20]\n wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19};\t// @[primitives.scala:77:20]\n wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20};\t// @[primitives.scala:77:20, :107:20]\n wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21;\t// @[MulAddRecFN.scala:247:78, :249:11]\n wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3];\t// @[MulAddRecFN.scala:243:50, :251:28]\n wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0];\t// @[MulAddRecFN.scala:243:50, :252:28]\n wire _notCDom_sig_T_2 = |_notCDom_sig_T_1;\t// @[MulAddRecFN.scala:252:{28,35}]\n wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra;\t// @[MulAddRecFN.scala:249:11, :252:{35,39}]\n wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3};\t// @[MulAddRecFN.scala:251:{12,28}, :252:39]\n wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25];\t// @[MulAddRecFN.scala:251:12, :255:21]\n wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0;\t// @[primitives.scala:103:54]\n wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum;\t// @[MulAddRecFN.scala:169:7, :232:36, :259:36]\n wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T;\t// @[MulAddRecFN.scala:255:50, :257:12, :259:36]\n assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0;\t// @[MulAddRecFN.scala:169:7, :264:49, :265:44]\n assign io_rawOut_isInf_0 = notNaN_isInfOut;\t// @[MulAddRecFN.scala:169:7, :265:44]\n wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0;\t// @[MulAddRecFN.scala:169:7, :267:{32,58}]\n wire _io_rawOut_sign_T_4 = notNaN_addZeros;\t// @[MulAddRecFN.scala:267:58, :287:26]\n wire _io_invalidExc_T_3 = _io_invalidExc_T_1;\t// @[MulAddRecFN.scala:271:35, :272:57]\n wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0;\t// @[MulAddRecFN.scala:169:7, :274:10]\n wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5;\t// @[MulAddRecFN.scala:274:{10,36}, :275:36]\n wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0;\t// @[MulAddRecFN.scala:169:7, :274:36, :275:61]\n wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0;\t// @[MulAddRecFN.scala:169:7, :275:61, :276:35]\n assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8;\t// @[MulAddRecFN.scala:272:57, :273:57, :276:35]\n assign io_invalidExc_0 = _io_invalidExc_T_9;\t// @[MulAddRecFN.scala:169:7, :273:57]\n assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0;\t// @[MulAddRecFN.scala:169:7, :278:48]\n assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T;\t// @[MulAddRecFN.scala:169:7, :278:48]\n wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0;\t// @[MulAddRecFN.scala:169:7, :283:14]\n wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation;\t// @[MulAddRecFN.scala:255:50, :283:{14,42}]\n assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1;\t// @[MulAddRecFN.scala:267:58, :282:25, :283:42]\n assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2;\t// @[MulAddRecFN.scala:169:7, :282:25]\n wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0;\t// @[MulAddRecFN.scala:169:7, :264:49, :285:27]\n wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC;\t// @[MulAddRecFN.scala:169:7, :190:42, :286:31]\n wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1;\t// @[MulAddRecFN.scala:285:{27,54}, :286:31]\n wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0;\t// @[MulAddRecFN.scala:169:7, :287:{26,48}]\n wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC;\t// @[MulAddRecFN.scala:190:42, :287:48, :288:36]\n wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6;\t// @[MulAddRecFN.scala:285:54, :286:43, :288:36]\n wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7;\t// @[MulAddRecFN.scala:286:43, :288:48]\n wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC;\t// @[MulAddRecFN.scala:169:7, :190:42, :290:37]\n wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut;\t// @[MulAddRecFN.scala:265:44, :291:10]\n wire _io_rawOut_sign_T_13 = ~notNaN_addZeros;\t// @[MulAddRecFN.scala:267:58, :291:31]\n wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13;\t// @[MulAddRecFN.scala:291:{10,28,31}]\n wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign;\t// @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]\n wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15;\t// @[MulAddRecFN.scala:291:{28,49}, :292:17]\n assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16;\t// @[MulAddRecFN.scala:288:48, :290:50, :291:49]\n assign io_rawOut_sign_0 = _io_rawOut_sign_T_17;\t// @[MulAddRecFN.scala:169:7, :290:50]\n assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp;\t// @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]\n assign io_rawOut_sExp_0 = _io_rawOut_sExp_T;\t// @[MulAddRecFN.scala:169:7, :293:26]\n assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig;\t// @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]\n assign io_rawOut_sig_0 = _io_rawOut_sig_T;\t// @[MulAddRecFN.scala:169:7, :294:25]\n assign io_invalidExc = io_invalidExc_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_isNaN = io_rawOut_isNaN_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_isInf = io_rawOut_isInf_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_isZero = io_rawOut_isZero_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_sign = io_rawOut_sign_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_sExp = io_rawOut_sExp_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_sig = io_rawOut_sig_0;\t// @[MulAddRecFN.scala:169:7]\nendmodule"}}},{"rowIdx":32161,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module ALU_2 : \n input clock : Clock \n input reset : Reset \n output io : { flip dw : UInt<1>, flip fn : UInt<5>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} \n\n\n node _in2_inv_T = bits(io.fn, 3, 3) \n node _in2_inv_T_1 = not(io.in2) \n node in2_inv = mux(_in2_inv_T, _in2_inv_T_1, io.in2) \n node in1_xor_in2 = xor(io.in1, in2_inv) \n node in1_and_in2 = and(io.in1, in2_inv) \n node _io_adder_out_T = add(io.in1, in2_inv) \n node _io_adder_out_T_1 = tail(_io_adder_out_T, 1) \n node _io_adder_out_T_2 = bits(io.fn, 3, 3) \n node _io_adder_out_T_3 = add(_io_adder_out_T_1, _io_adder_out_T_2) \n node _io_adder_out_T_4 = tail(_io_adder_out_T_3, 1) \n connect io.adder_out, _io_adder_out_T_4 \n node _slt_T = bits(io.in1, 63, 63) \n node _slt_T_1 = bits(io.in2, 63, 63) \n node _slt_T_2 = eq(_slt_T, _slt_T_1) \n node _slt_T_3 = bits(io.adder_out, 63, 63) \n node _slt_T_4 = bits(io.fn, 1, 1) \n node _slt_T_5 = bits(io.in2, 63, 63) \n node _slt_T_6 = bits(io.in1, 63, 63) \n node _slt_T_7 = mux(_slt_T_4, _slt_T_5, _slt_T_6) \n node slt = mux(_slt_T_2, _slt_T_3, _slt_T_7) \n node _io_cmp_out_T = bits(io.fn, 0, 0) \n node _io_cmp_out_T_1 = bits(io.fn, 3, 3) \n node _io_cmp_out_T_2 = eq(_io_cmp_out_T_1, UInt<1>(0h0)) \n node _io_cmp_out_T_3 = eq(in1_xor_in2, UInt<1>(0h0)) \n node _io_cmp_out_T_4 = mux(_io_cmp_out_T_2, _io_cmp_out_T_3, slt) \n node _io_cmp_out_T_5 = xor(_io_cmp_out_T, _io_cmp_out_T_4) \n connect io.cmp_out, _io_cmp_out_T_5 \n node _shin_hi_32_T = bits(io.fn, 3, 3) \n node _shin_hi_32_T_1 = bits(io.in1, 31, 31) \n node _shin_hi_32_T_2 = and(_shin_hi_32_T, _shin_hi_32_T_1) \n node shin_hi_32 = mux(_shin_hi_32_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) \n node _shin_hi_T = eq(io.dw, UInt<1>(0h1)) \n node _shin_hi_T_1 = bits(io.in1, 63, 32) \n node shin_hi = mux(_shin_hi_T, _shin_hi_T_1, shin_hi_32) \n node _shamt_T = bits(io.in2, 5, 5) \n node _shamt_T_1 = eq(io.dw, UInt<1>(0h1)) \n node _shamt_T_2 = and(_shamt_T, _shamt_T_1) \n node _shamt_T_3 = bits(io.in2, 4, 0) \n node shamt = cat(_shamt_T_2, _shamt_T_3) \n node _T = bits(io.in1, 31, 0) \n node shin_r = cat(shin_hi, _T) \n node _shin_T = eq(io.fn, UInt<3>(0h5)) \n node _shin_T_1 = eq(io.fn, UInt<4>(0hb)) \n node _shin_T_2 = eq(io.fn, UInt<5>(0h12)) \n node _shin_T_3 = eq(io.fn, UInt<5>(0h13)) \n node _shin_T_4 = or(_shin_T, _shin_T_1) \n node _shin_T_5 = or(_shin_T_4, _shin_T_2) \n node _shin_T_6 = or(_shin_T_5, _shin_T_3) \n node _shin_T_7 = eq(_shin_T_6, UInt<1>(0h0)) \n node _shin_T_8 = shl(UInt<32>(0hffffffff), 32) \n node _shin_T_9 = xor(UInt<64>(0hffffffffffffffff), _shin_T_8) \n node _shin_T_10 = shr(shin_r, 32) \n node _shin_T_11 = and(_shin_T_10, _shin_T_9) \n node _shin_T_12 = bits(shin_r, 31, 0) \n node _shin_T_13 = shl(_shin_T_12, 32) \n node _shin_T_14 = not(_shin_T_9) \n node _shin_T_15 = and(_shin_T_13, _shin_T_14) \n node _shin_T_16 = or(_shin_T_11, _shin_T_15) \n node _shin_T_17 = bits(_shin_T_9, 47, 0) \n node _shin_T_18 = shl(_shin_T_17, 16) \n node _shin_T_19 = xor(_shin_T_9, _shin_T_18) \n node _shin_T_20 = shr(_shin_T_16, 16) \n node _shin_T_21 = and(_shin_T_20, _shin_T_19) \n node _shin_T_22 = bits(_shin_T_16, 47, 0) \n node _shin_T_23 = shl(_shin_T_22, 16) \n node _shin_T_24 = not(_shin_T_19) \n node _shin_T_25 = and(_shin_T_23, _shin_T_24) \n node _shin_T_26 = or(_shin_T_21, _shin_T_25) \n node _shin_T_27 = bits(_shin_T_19, 55, 0) \n node _shin_T_28 = shl(_shin_T_27, 8) \n node _shin_T_29 = xor(_shin_T_19, _shin_T_28) \n node _shin_T_30 = shr(_shin_T_26, 8) \n node _shin_T_31 = and(_shin_T_30, _shin_T_29) \n node _shin_T_32 = bits(_shin_T_26, 55, 0) \n node _shin_T_33 = shl(_shin_T_32, 8) \n node _shin_T_34 = not(_shin_T_29) \n node _shin_T_35 = and(_shin_T_33, _shin_T_34) \n node _shin_T_36 = or(_shin_T_31, _shin_T_35) \n node _shin_T_37 = bits(_shin_T_29, 59, 0) \n node _shin_T_38 = shl(_shin_T_37, 4) \n node _shin_T_39 = xor(_shin_T_29, _shin_T_38) \n node _shin_T_40 = shr(_shin_T_36, 4) \n node _shin_T_41 = and(_shin_T_40, _shin_T_39) \n node _shin_T_42 = bits(_shin_T_36, 59, 0) \n node _shin_T_43 = shl(_shin_T_42, 4) \n node _shin_T_44 = not(_shin_T_39) \n node _shin_T_45 = and(_shin_T_43, _shin_T_44) \n node _shin_T_46 = or(_shin_T_41, _shin_T_45) \n node _shin_T_47 = bits(_shin_T_39, 61, 0) \n node _shin_T_48 = shl(_shin_T_47, 2) \n node _shin_T_49 = xor(_shin_T_39, _shin_T_48) \n node _shin_T_50 = shr(_shin_T_46, 2) \n node _shin_T_51 = and(_shin_T_50, _shin_T_49) \n node _shin_T_52 = bits(_shin_T_46, 61, 0) \n node _shin_T_53 = shl(_shin_T_52, 2) \n node _shin_T_54 = not(_shin_T_49) \n node _shin_T_55 = and(_shin_T_53, _shin_T_54) \n node _shin_T_56 = or(_shin_T_51, _shin_T_55) \n node _shin_T_57 = bits(_shin_T_49, 62, 0) \n node _shin_T_58 = shl(_shin_T_57, 1) \n node _shin_T_59 = xor(_shin_T_49, _shin_T_58) \n node _shin_T_60 = shr(_shin_T_56, 1) \n node _shin_T_61 = and(_shin_T_60, _shin_T_59) \n node _shin_T_62 = bits(_shin_T_56, 62, 0) \n node _shin_T_63 = shl(_shin_T_62, 1) \n node _shin_T_64 = not(_shin_T_59) \n node _shin_T_65 = and(_shin_T_63, _shin_T_64) \n node _shin_T_66 = or(_shin_T_61, _shin_T_65) \n node shin = mux(_shin_T_7, _shin_T_66, shin_r) \n node _shout_r_T = bits(io.fn, 3, 3) \n node _shout_r_T_1 = bits(shin, 63, 63) \n node _shout_r_T_2 = and(_shout_r_T, _shout_r_T_1) \n node _shout_r_T_3 = cat(_shout_r_T_2, shin) \n node _shout_r_T_4 = asSInt(_shout_r_T_3) \n node _shout_r_T_5 = dshr(_shout_r_T_4, shamt) \n node shout_r = bits(_shout_r_T_5, 63, 0) \n node _shout_l_T = shl(UInt<32>(0hffffffff), 32) \n node _shout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _shout_l_T) \n node _shout_l_T_2 = shr(shout_r, 32) \n node _shout_l_T_3 = and(_shout_l_T_2, _shout_l_T_1) \n node _shout_l_T_4 = bits(shout_r, 31, 0) \n node _shout_l_T_5 = shl(_shout_l_T_4, 32) \n node _shout_l_T_6 = not(_shout_l_T_1) \n node _shout_l_T_7 = and(_shout_l_T_5, _shout_l_T_6) \n node _shout_l_T_8 = or(_shout_l_T_3, _shout_l_T_7) \n node _shout_l_T_9 = bits(_shout_l_T_1, 47, 0) \n node _shout_l_T_10 = shl(_shout_l_T_9, 16) \n node _shout_l_T_11 = xor(_shout_l_T_1, _shout_l_T_10) \n node _shout_l_T_12 = shr(_shout_l_T_8, 16) \n node _shout_l_T_13 = and(_shout_l_T_12, _shout_l_T_11) \n node _shout_l_T_14 = bits(_shout_l_T_8, 47, 0) \n node _shout_l_T_15 = shl(_shout_l_T_14, 16) \n node _shout_l_T_16 = not(_shout_l_T_11) \n node _shout_l_T_17 = and(_shout_l_T_15, _shout_l_T_16) \n node _shout_l_T_18 = or(_shout_l_T_13, _shout_l_T_17) \n node _shout_l_T_19 = bits(_shout_l_T_11, 55, 0) \n node _shout_l_T_20 = shl(_shout_l_T_19, 8) \n node _shout_l_T_21 = xor(_shout_l_T_11, _shout_l_T_20) \n node _shout_l_T_22 = shr(_shout_l_T_18, 8) \n node _shout_l_T_23 = and(_shout_l_T_22, _shout_l_T_21) \n node _shout_l_T_24 = bits(_shout_l_T_18, 55, 0) \n node _shout_l_T_25 = shl(_shout_l_T_24, 8) \n node _shout_l_T_26 = not(_shout_l_T_21) \n node _shout_l_T_27 = and(_shout_l_T_25, _shout_l_T_26) \n node _shout_l_T_28 = or(_shout_l_T_23, _shout_l_T_27) \n node _shout_l_T_29 = bits(_shout_l_T_21, 59, 0) \n node _shout_l_T_30 = shl(_shout_l_T_29, 4) \n node _shout_l_T_31 = xor(_shout_l_T_21, _shout_l_T_30) \n node _shout_l_T_32 = shr(_shout_l_T_28, 4) \n node _shout_l_T_33 = and(_shout_l_T_32, _shout_l_T_31) \n node _shout_l_T_34 = bits(_shout_l_T_28, 59, 0) \n node _shout_l_T_35 = shl(_shout_l_T_34, 4) \n node _shout_l_T_36 = not(_shout_l_T_31) \n node _shout_l_T_37 = and(_shout_l_T_35, _shout_l_T_36) \n node _shout_l_T_38 = or(_shout_l_T_33, _shout_l_T_37) \n node _shout_l_T_39 = bits(_shout_l_T_31, 61, 0) \n node _shout_l_T_40 = shl(_shout_l_T_39, 2) \n node _shout_l_T_41 = xor(_shout_l_T_31, _shout_l_T_40) \n node _shout_l_T_42 = shr(_shout_l_T_38, 2) \n node _shout_l_T_43 = and(_shout_l_T_42, _shout_l_T_41) \n node _shout_l_T_44 = bits(_shout_l_T_38, 61, 0) \n node _shout_l_T_45 = shl(_shout_l_T_44, 2) \n node _shout_l_T_46 = not(_shout_l_T_41) \n node _shout_l_T_47 = and(_shout_l_T_45, _shout_l_T_46) \n node _shout_l_T_48 = or(_shout_l_T_43, _shout_l_T_47) \n node _shout_l_T_49 = bits(_shout_l_T_41, 62, 0) \n node _shout_l_T_50 = shl(_shout_l_T_49, 1) \n node _shout_l_T_51 = xor(_shout_l_T_41, _shout_l_T_50) \n node _shout_l_T_52 = shr(_shout_l_T_48, 1) \n node _shout_l_T_53 = and(_shout_l_T_52, _shout_l_T_51) \n node _shout_l_T_54 = bits(_shout_l_T_48, 62, 0) \n node _shout_l_T_55 = shl(_shout_l_T_54, 1) \n node _shout_l_T_56 = not(_shout_l_T_51) \n node _shout_l_T_57 = and(_shout_l_T_55, _shout_l_T_56) \n node shout_l = or(_shout_l_T_53, _shout_l_T_57) \n node _shout_T = eq(io.fn, UInt<3>(0h5)) \n node _shout_T_1 = eq(io.fn, UInt<4>(0hb)) \n node _shout_T_2 = or(_shout_T, _shout_T_1) \n node _shout_T_3 = eq(io.fn, UInt<5>(0h13)) \n node _shout_T_4 = or(_shout_T_2, _shout_T_3) \n node _shout_T_5 = mux(_shout_T_4, shout_r, UInt<1>(0h0)) \n node _shout_T_6 = eq(io.fn, UInt<1>(0h1)) \n node _shout_T_7 = mux(_shout_T_6, shout_l, UInt<1>(0h0)) \n node shout = or(_shout_T_5, _shout_T_7) \n node in2_not_zero = orr(io.in2) \n node _logic_T = eq(io.fn, UInt<3>(0h4)) \n node _logic_T_1 = eq(io.fn, UInt<3>(0h6)) \n node _logic_T_2 = or(_logic_T, _logic_T_1) \n node _logic_T_3 = eq(io.fn, UInt<5>(0h19)) \n node _logic_T_4 = or(_logic_T_2, _logic_T_3) \n node _logic_T_5 = eq(io.fn, UInt<5>(0h1a)) \n node _logic_T_6 = or(_logic_T_4, _logic_T_5) \n node _logic_T_7 = mux(_logic_T_6, in1_xor_in2, UInt<1>(0h0)) \n node _logic_T_8 = eq(io.fn, UInt<3>(0h6)) \n node _logic_T_9 = eq(io.fn, UInt<3>(0h7)) \n node _logic_T_10 = or(_logic_T_8, _logic_T_9) \n node _logic_T_11 = eq(io.fn, UInt<5>(0h19)) \n node _logic_T_12 = or(_logic_T_10, _logic_T_11) \n node _logic_T_13 = eq(io.fn, UInt<5>(0h18)) \n node _logic_T_14 = or(_logic_T_12, _logic_T_13) \n node _logic_T_15 = mux(_logic_T_14, in1_and_in2, UInt<1>(0h0)) \n node logic = or(_logic_T_7, _logic_T_15) \n node _bext_mask_T = eq(io.fn, UInt<5>(0h13)) \n node _bext_mask_T_1 = and(UInt<1>(0h1), _bext_mask_T) \n node _bext_mask_T_2 = not(UInt<64>(0h0)) \n node bext_mask = mux(_bext_mask_T_1, UInt<1>(0h1), _bext_mask_T_2) \n node _shift_logic_T = geq(io.fn, UInt<4>(0hc)) \n node _shift_logic_T_1 = leq(io.fn, UInt<4>(0hf)) \n node _shift_logic_T_2 = and(_shift_logic_T, _shift_logic_T_1) \n node _shift_logic_T_3 = and(_shift_logic_T_2, slt) \n node _shift_logic_T_4 = or(_shift_logic_T_3, logic) \n node _shift_logic_T_5 = and(shout, bext_mask) \n node shift_logic = or(_shift_logic_T_4, _shift_logic_T_5) \n node _tz_in_T = eq(io.dw, UInt<1>(0h0)) \n node _tz_in_T_1 = bits(io.in2, 0, 0) \n node _tz_in_T_2 = eq(_tz_in_T_1, UInt<1>(0h0)) \n node _tz_in_T_3 = cat(_tz_in_T, _tz_in_T_2) \n node _tz_in_T_4 = shl(UInt<32>(0hffffffff), 32) \n node _tz_in_T_5 = xor(UInt<64>(0hffffffffffffffff), _tz_in_T_4) \n node _tz_in_T_6 = shr(io.in1, 32) \n node _tz_in_T_7 = and(_tz_in_T_6, _tz_in_T_5) \n node _tz_in_T_8 = bits(io.in1, 31, 0) \n node _tz_in_T_9 = shl(_tz_in_T_8, 32) \n node _tz_in_T_10 = not(_tz_in_T_5) \n node _tz_in_T_11 = and(_tz_in_T_9, _tz_in_T_10) \n node _tz_in_T_12 = or(_tz_in_T_7, _tz_in_T_11) \n node _tz_in_T_13 = bits(_tz_in_T_5, 47, 0) \n node _tz_in_T_14 = shl(_tz_in_T_13, 16) \n node _tz_in_T_15 = xor(_tz_in_T_5, _tz_in_T_14) \n node _tz_in_T_16 = shr(_tz_in_T_12, 16) \n node _tz_in_T_17 = and(_tz_in_T_16, _tz_in_T_15) \n node _tz_in_T_18 = bits(_tz_in_T_12, 47, 0) \n node _tz_in_T_19 = shl(_tz_in_T_18, 16) \n node _tz_in_T_20 = not(_tz_in_T_15) \n node _tz_in_T_21 = and(_tz_in_T_19, _tz_in_T_20) \n node _tz_in_T_22 = or(_tz_in_T_17, _tz_in_T_21) \n node _tz_in_T_23 = bits(_tz_in_T_15, 55, 0) \n node _tz_in_T_24 = shl(_tz_in_T_23, 8) \n node _tz_in_T_25 = xor(_tz_in_T_15, _tz_in_T_24) \n node _tz_in_T_26 = shr(_tz_in_T_22, 8) \n node _tz_in_T_27 = and(_tz_in_T_26, _tz_in_T_25) \n node _tz_in_T_28 = bits(_tz_in_T_22, 55, 0) \n node _tz_in_T_29 = shl(_tz_in_T_28, 8) \n node _tz_in_T_30 = not(_tz_in_T_25) \n node _tz_in_T_31 = and(_tz_in_T_29, _tz_in_T_30) \n node _tz_in_T_32 = or(_tz_in_T_27, _tz_in_T_31) \n node _tz_in_T_33 = bits(_tz_in_T_25, 59, 0) \n node _tz_in_T_34 = shl(_tz_in_T_33, 4) \n node _tz_in_T_35 = xor(_tz_in_T_25, _tz_in_T_34) \n node _tz_in_T_36 = shr(_tz_in_T_32, 4) \n node _tz_in_T_37 = and(_tz_in_T_36, _tz_in_T_35) \n node _tz_in_T_38 = bits(_tz_in_T_32, 59, 0) \n node _tz_in_T_39 = shl(_tz_in_T_38, 4) \n node _tz_in_T_40 = not(_tz_in_T_35) \n node _tz_in_T_41 = and(_tz_in_T_39, _tz_in_T_40) \n node _tz_in_T_42 = or(_tz_in_T_37, _tz_in_T_41) \n node _tz_in_T_43 = bits(_tz_in_T_35, 61, 0) \n node _tz_in_T_44 = shl(_tz_in_T_43, 2) \n node _tz_in_T_45 = xor(_tz_in_T_35, _tz_in_T_44) \n node _tz_in_T_46 = shr(_tz_in_T_42, 2) \n node _tz_in_T_47 = and(_tz_in_T_46, _tz_in_T_45) \n node _tz_in_T_48 = bits(_tz_in_T_42, 61, 0) \n node _tz_in_T_49 = shl(_tz_in_T_48, 2) \n node _tz_in_T_50 = not(_tz_in_T_45) \n node _tz_in_T_51 = and(_tz_in_T_49, _tz_in_T_50) \n node _tz_in_T_52 = or(_tz_in_T_47, _tz_in_T_51) \n node _tz_in_T_53 = bits(_tz_in_T_45, 62, 0) \n node _tz_in_T_54 = shl(_tz_in_T_53, 1) \n node _tz_in_T_55 = xor(_tz_in_T_45, _tz_in_T_54) \n node _tz_in_T_56 = shr(_tz_in_T_52, 1) \n node _tz_in_T_57 = and(_tz_in_T_56, _tz_in_T_55) \n node _tz_in_T_58 = bits(_tz_in_T_52, 62, 0) \n node _tz_in_T_59 = shl(_tz_in_T_58, 1) \n node _tz_in_T_60 = not(_tz_in_T_55) \n node _tz_in_T_61 = and(_tz_in_T_59, _tz_in_T_60) \n node _tz_in_T_62 = or(_tz_in_T_57, _tz_in_T_61) \n node _tz_in_T_63 = bits(io.in1, 31, 0) \n node _tz_in_T_64 = cat(UInt<1>(0h1), _tz_in_T_63) \n node _tz_in_T_65 = bits(io.in1, 31, 0) \n node _tz_in_T_66 = shl(UInt<16>(0hffff), 16) \n node _tz_in_T_67 = xor(UInt<32>(0hffffffff), _tz_in_T_66) \n node _tz_in_T_68 = shr(_tz_in_T_65, 16) \n node _tz_in_T_69 = and(_tz_in_T_68, _tz_in_T_67) \n node _tz_in_T_70 = bits(_tz_in_T_65, 15, 0) \n node _tz_in_T_71 = shl(_tz_in_T_70, 16) \n node _tz_in_T_72 = not(_tz_in_T_67) \n node _tz_in_T_73 = and(_tz_in_T_71, _tz_in_T_72) \n node _tz_in_T_74 = or(_tz_in_T_69, _tz_in_T_73) \n node _tz_in_T_75 = bits(_tz_in_T_67, 23, 0) \n node _tz_in_T_76 = shl(_tz_in_T_75, 8) \n node _tz_in_T_77 = xor(_tz_in_T_67, _tz_in_T_76) \n node _tz_in_T_78 = shr(_tz_in_T_74, 8) \n node _tz_in_T_79 = and(_tz_in_T_78, _tz_in_T_77) \n node _tz_in_T_80 = bits(_tz_in_T_74, 23, 0) \n node _tz_in_T_81 = shl(_tz_in_T_80, 8) \n node _tz_in_T_82 = not(_tz_in_T_77) \n node _tz_in_T_83 = and(_tz_in_T_81, _tz_in_T_82) \n node _tz_in_T_84 = or(_tz_in_T_79, _tz_in_T_83) \n node _tz_in_T_85 = bits(_tz_in_T_77, 27, 0) \n node _tz_in_T_86 = shl(_tz_in_T_85, 4) \n node _tz_in_T_87 = xor(_tz_in_T_77, _tz_in_T_86) \n node _tz_in_T_88 = shr(_tz_in_T_84, 4) \n node _tz_in_T_89 = and(_tz_in_T_88, _tz_in_T_87) \n node _tz_in_T_90 = bits(_tz_in_T_84, 27, 0) \n node _tz_in_T_91 = shl(_tz_in_T_90, 4) \n node _tz_in_T_92 = not(_tz_in_T_87) \n node _tz_in_T_93 = and(_tz_in_T_91, _tz_in_T_92) \n node _tz_in_T_94 = or(_tz_in_T_89, _tz_in_T_93) \n node _tz_in_T_95 = bits(_tz_in_T_87, 29, 0) \n node _tz_in_T_96 = shl(_tz_in_T_95, 2) \n node _tz_in_T_97 = xor(_tz_in_T_87, _tz_in_T_96) \n node _tz_in_T_98 = shr(_tz_in_T_94, 2) \n node _tz_in_T_99 = and(_tz_in_T_98, _tz_in_T_97) \n node _tz_in_T_100 = bits(_tz_in_T_94, 29, 0) \n node _tz_in_T_101 = shl(_tz_in_T_100, 2) \n node _tz_in_T_102 = not(_tz_in_T_97) \n node _tz_in_T_103 = and(_tz_in_T_101, _tz_in_T_102) \n node _tz_in_T_104 = or(_tz_in_T_99, _tz_in_T_103) \n node _tz_in_T_105 = bits(_tz_in_T_97, 30, 0) \n node _tz_in_T_106 = shl(_tz_in_T_105, 1) \n node _tz_in_T_107 = xor(_tz_in_T_97, _tz_in_T_106) \n node _tz_in_T_108 = shr(_tz_in_T_104, 1) \n node _tz_in_T_109 = and(_tz_in_T_108, _tz_in_T_107) \n node _tz_in_T_110 = bits(_tz_in_T_104, 30, 0) \n node _tz_in_T_111 = shl(_tz_in_T_110, 1) \n node _tz_in_T_112 = not(_tz_in_T_107) \n node _tz_in_T_113 = and(_tz_in_T_111, _tz_in_T_112) \n node _tz_in_T_114 = or(_tz_in_T_109, _tz_in_T_113) \n node _tz_in_T_115 = cat(UInt<1>(0h1), _tz_in_T_114) \n node _tz_in_T_116 = eq(UInt<1>(0h1), _tz_in_T_3) \n node _tz_in_T_117 = mux(_tz_in_T_116, _tz_in_T_62, io.in1) \n node _tz_in_T_118 = eq(UInt<2>(0h2), _tz_in_T_3) \n node _tz_in_T_119 = mux(_tz_in_T_118, _tz_in_T_64, _tz_in_T_117) \n node _tz_in_T_120 = eq(UInt<2>(0h3), _tz_in_T_3) \n node tz_in = mux(_tz_in_T_120, _tz_in_T_115, _tz_in_T_119) \n node _popc_in_T = bits(io.in2, 1, 1) \n node _popc_in_T_1 = eq(io.dw, UInt<1>(0h0)) \n node _popc_in_T_2 = bits(io.in1, 31, 0) \n node _popc_in_T_3 = mux(_popc_in_T_1, _popc_in_T_2, io.in1) \n node _popc_in_T_4 = cat(UInt<1>(0h1), tz_in) \n node _popc_in_T_5 = bits(_popc_in_T_4, 0, 0) \n node _popc_in_T_6 = bits(_popc_in_T_4, 1, 1) \n node _popc_in_T_7 = bits(_popc_in_T_4, 2, 2) \n node _popc_in_T_8 = bits(_popc_in_T_4, 3, 3) \n node _popc_in_T_9 = bits(_popc_in_T_4, 4, 4) \n node _popc_in_T_10 = bits(_popc_in_T_4, 5, 5) \n node _popc_in_T_11 = bits(_popc_in_T_4, 6, 6) \n node _popc_in_T_12 = bits(_popc_in_T_4, 7, 7) \n node _popc_in_T_13 = bits(_popc_in_T_4, 8, 8) \n node _popc_in_T_14 = bits(_popc_in_T_4, 9, 9) \n node _popc_in_T_15 = bits(_popc_in_T_4, 10, 10) \n node _popc_in_T_16 = bits(_popc_in_T_4, 11, 11) \n node _popc_in_T_17 = bits(_popc_in_T_4, 12, 12) \n node _popc_in_T_18 = bits(_popc_in_T_4, 13, 13) \n node _popc_in_T_19 = bits(_popc_in_T_4, 14, 14) \n node _popc_in_T_20 = bits(_popc_in_T_4, 15, 15) \n node _popc_in_T_21 = bits(_popc_in_T_4, 16, 16) \n node _popc_in_T_22 = bits(_popc_in_T_4, 17, 17) \n node _popc_in_T_23 = bits(_popc_in_T_4, 18, 18) \n node _popc_in_T_24 = bits(_popc_in_T_4, 19, 19) \n node _popc_in_T_25 = bits(_popc_in_T_4, 20, 20) \n node _popc_in_T_26 = bits(_popc_in_T_4, 21, 21) \n node _popc_in_T_27 = bits(_popc_in_T_4, 22, 22) \n node _popc_in_T_28 = bits(_popc_in_T_4, 23, 23) \n node _popc_in_T_29 = bits(_popc_in_T_4, 24, 24) \n node _popc_in_T_30 = bits(_popc_in_T_4, 25, 25) \n node _popc_in_T_31 = bits(_popc_in_T_4, 26, 26) \n node _popc_in_T_32 = bits(_popc_in_T_4, 27, 27) \n node _popc_in_T_33 = bits(_popc_in_T_4, 28, 28) \n node _popc_in_T_34 = bits(_popc_in_T_4, 29, 29) \n node _popc_in_T_35 = bits(_popc_in_T_4, 30, 30) \n node _popc_in_T_36 = bits(_popc_in_T_4, 31, 31) \n node _popc_in_T_37 = bits(_popc_in_T_4, 32, 32) \n node _popc_in_T_38 = bits(_popc_in_T_4, 33, 33) \n node _popc_in_T_39 = bits(_popc_in_T_4, 34, 34) \n node _popc_in_T_40 = bits(_popc_in_T_4, 35, 35) \n node _popc_in_T_41 = bits(_popc_in_T_4, 36, 36) \n node _popc_in_T_42 = bits(_popc_in_T_4, 37, 37) \n node _popc_in_T_43 = bits(_popc_in_T_4, 38, 38) \n node _popc_in_T_44 = bits(_popc_in_T_4, 39, 39) \n node _popc_in_T_45 = bits(_popc_in_T_4, 40, 40) \n node _popc_in_T_46 = bits(_popc_in_T_4, 41, 41) \n node _popc_in_T_47 = bits(_popc_in_T_4, 42, 42) \n node _popc_in_T_48 = bits(_popc_in_T_4, 43, 43) \n node _popc_in_T_49 = bits(_popc_in_T_4, 44, 44) \n node _popc_in_T_50 = bits(_popc_in_T_4, 45, 45) \n node _popc_in_T_51 = bits(_popc_in_T_4, 46, 46) \n node _popc_in_T_52 = bits(_popc_in_T_4, 47, 47) \n node _popc_in_T_53 = bits(_popc_in_T_4, 48, 48) \n node _popc_in_T_54 = bits(_popc_in_T_4, 49, 49) \n node _popc_in_T_55 = bits(_popc_in_T_4, 50, 50) \n node _popc_in_T_56 = bits(_popc_in_T_4, 51, 51) \n node _popc_in_T_57 = bits(_popc_in_T_4, 52, 52) \n node _popc_in_T_58 = bits(_popc_in_T_4, 53, 53) \n node _popc_in_T_59 = bits(_popc_in_T_4, 54, 54) \n node _popc_in_T_60 = bits(_popc_in_T_4, 55, 55) \n node _popc_in_T_61 = bits(_popc_in_T_4, 56, 56) \n node _popc_in_T_62 = bits(_popc_in_T_4, 57, 57) \n node _popc_in_T_63 = bits(_popc_in_T_4, 58, 58) \n node _popc_in_T_64 = bits(_popc_in_T_4, 59, 59) \n node _popc_in_T_65 = bits(_popc_in_T_4, 60, 60) \n node _popc_in_T_66 = bits(_popc_in_T_4, 61, 61) \n node _popc_in_T_67 = bits(_popc_in_T_4, 62, 62) \n node _popc_in_T_68 = bits(_popc_in_T_4, 63, 63) \n node _popc_in_T_69 = bits(_popc_in_T_4, 64, 64) \n node _popc_in_T_70 = mux(_popc_in_T_69, UInt<65>(0h10000000000000000), UInt<65>(0h0)) \n node _popc_in_T_71 = mux(_popc_in_T_68, UInt<65>(0h8000000000000000), _popc_in_T_70) \n node _popc_in_T_72 = mux(_popc_in_T_67, UInt<65>(0h4000000000000000), _popc_in_T_71) \n node _popc_in_T_73 = mux(_popc_in_T_66, UInt<65>(0h2000000000000000), _popc_in_T_72) \n node _popc_in_T_74 = mux(_popc_in_T_65, UInt<65>(0h1000000000000000), _popc_in_T_73) \n node _popc_in_T_75 = mux(_popc_in_T_64, UInt<65>(0h800000000000000), _popc_in_T_74) \n node _popc_in_T_76 = mux(_popc_in_T_63, UInt<65>(0h400000000000000), _popc_in_T_75) \n node _popc_in_T_77 = mux(_popc_in_T_62, UInt<65>(0h200000000000000), _popc_in_T_76) \n node _popc_in_T_78 = mux(_popc_in_T_61, UInt<65>(0h100000000000000), _popc_in_T_77) \n node _popc_in_T_79 = mux(_popc_in_T_60, UInt<65>(0h80000000000000), _popc_in_T_78) \n node _popc_in_T_80 = mux(_popc_in_T_59, UInt<65>(0h40000000000000), _popc_in_T_79) \n node _popc_in_T_81 = mux(_popc_in_T_58, UInt<65>(0h20000000000000), _popc_in_T_80) \n node _popc_in_T_82 = mux(_popc_in_T_57, UInt<65>(0h10000000000000), _popc_in_T_81) \n node _popc_in_T_83 = mux(_popc_in_T_56, UInt<65>(0h8000000000000), _popc_in_T_82) \n node _popc_in_T_84 = mux(_popc_in_T_55, UInt<65>(0h4000000000000), _popc_in_T_83) \n node _popc_in_T_85 = mux(_popc_in_T_54, UInt<65>(0h2000000000000), _popc_in_T_84) \n node _popc_in_T_86 = mux(_popc_in_T_53, UInt<65>(0h1000000000000), _popc_in_T_85) \n node _popc_in_T_87 = mux(_popc_in_T_52, UInt<65>(0h800000000000), _popc_in_T_86) \n node _popc_in_T_88 = mux(_popc_in_T_51, UInt<65>(0h400000000000), _popc_in_T_87) \n node _popc_in_T_89 = mux(_popc_in_T_50, UInt<65>(0h200000000000), _popc_in_T_88) \n node _popc_in_T_90 = mux(_popc_in_T_49, UInt<65>(0h100000000000), _popc_in_T_89) \n node _popc_in_T_91 = mux(_popc_in_T_48, UInt<65>(0h80000000000), _popc_in_T_90) \n node _popc_in_T_92 = mux(_popc_in_T_47, UInt<65>(0h40000000000), _popc_in_T_91) \n node _popc_in_T_93 = mux(_popc_in_T_46, UInt<65>(0h20000000000), _popc_in_T_92) \n node _popc_in_T_94 = mux(_popc_in_T_45, UInt<65>(0h10000000000), _popc_in_T_93) \n node _popc_in_T_95 = mux(_popc_in_T_44, UInt<65>(0h8000000000), _popc_in_T_94) \n node _popc_in_T_96 = mux(_popc_in_T_43, UInt<65>(0h4000000000), _popc_in_T_95) \n node _popc_in_T_97 = mux(_popc_in_T_42, UInt<65>(0h2000000000), _popc_in_T_96) \n node _popc_in_T_98 = mux(_popc_in_T_41, UInt<65>(0h1000000000), _popc_in_T_97) \n node _popc_in_T_99 = mux(_popc_in_T_40, UInt<65>(0h800000000), _popc_in_T_98) \n node _popc_in_T_100 = mux(_popc_in_T_39, UInt<65>(0h400000000), _popc_in_T_99) \n node _popc_in_T_101 = mux(_popc_in_T_38, UInt<65>(0h200000000), _popc_in_T_100) \n node _popc_in_T_102 = mux(_popc_in_T_37, UInt<65>(0h100000000), _popc_in_T_101) \n node _popc_in_T_103 = mux(_popc_in_T_36, UInt<65>(0h80000000), _popc_in_T_102) \n node _popc_in_T_104 = mux(_popc_in_T_35, UInt<65>(0h40000000), _popc_in_T_103) \n node _popc_in_T_105 = mux(_popc_in_T_34, UInt<65>(0h20000000), _popc_in_T_104) \n node _popc_in_T_106 = mux(_popc_in_T_33, UInt<65>(0h10000000), _popc_in_T_105) \n node _popc_in_T_107 = mux(_popc_in_T_32, UInt<65>(0h8000000), _popc_in_T_106) \n node _popc_in_T_108 = mux(_popc_in_T_31, UInt<65>(0h4000000), _popc_in_T_107) \n node _popc_in_T_109 = mux(_popc_in_T_30, UInt<65>(0h2000000), _popc_in_T_108) \n node _popc_in_T_110 = mux(_popc_in_T_29, UInt<65>(0h1000000), _popc_in_T_109) \n node _popc_in_T_111 = mux(_popc_in_T_28, UInt<65>(0h800000), _popc_in_T_110) \n node _popc_in_T_112 = mux(_popc_in_T_27, UInt<65>(0h400000), _popc_in_T_111) \n node _popc_in_T_113 = mux(_popc_in_T_26, UInt<65>(0h200000), _popc_in_T_112) \n node _popc_in_T_114 = mux(_popc_in_T_25, UInt<65>(0h100000), _popc_in_T_113) \n node _popc_in_T_115 = mux(_popc_in_T_24, UInt<65>(0h80000), _popc_in_T_114) \n node _popc_in_T_116 = mux(_popc_in_T_23, UInt<65>(0h40000), _popc_in_T_115) \n node _popc_in_T_117 = mux(_popc_in_T_22, UInt<65>(0h20000), _popc_in_T_116) \n node _popc_in_T_118 = mux(_popc_in_T_21, UInt<65>(0h10000), _popc_in_T_117) \n node _popc_in_T_119 = mux(_popc_in_T_20, UInt<65>(0h8000), _popc_in_T_118) \n node _popc_in_T_120 = mux(_popc_in_T_19, UInt<65>(0h4000), _popc_in_T_119) \n node _popc_in_T_121 = mux(_popc_in_T_18, UInt<65>(0h2000), _popc_in_T_120) \n node _popc_in_T_122 = mux(_popc_in_T_17, UInt<65>(0h1000), _popc_in_T_121) \n node _popc_in_T_123 = mux(_popc_in_T_16, UInt<65>(0h800), _popc_in_T_122) \n node _popc_in_T_124 = mux(_popc_in_T_15, UInt<65>(0h400), _popc_in_T_123) \n node _popc_in_T_125 = mux(_popc_in_T_14, UInt<65>(0h200), _popc_in_T_124) \n node _popc_in_T_126 = mux(_popc_in_T_13, UInt<65>(0h100), _popc_in_T_125) \n node _popc_in_T_127 = mux(_popc_in_T_12, UInt<65>(0h80), _popc_in_T_126) \n node _popc_in_T_128 = mux(_popc_in_T_11, UInt<65>(0h40), _popc_in_T_127) \n node _popc_in_T_129 = mux(_popc_in_T_10, UInt<65>(0h20), _popc_in_T_128) \n node _popc_in_T_130 = mux(_popc_in_T_9, UInt<65>(0h10), _popc_in_T_129) \n node _popc_in_T_131 = mux(_popc_in_T_8, UInt<65>(0h8), _popc_in_T_130) \n node _popc_in_T_132 = mux(_popc_in_T_7, UInt<65>(0h4), _popc_in_T_131) \n node _popc_in_T_133 = mux(_popc_in_T_6, UInt<65>(0h2), _popc_in_T_132) \n node _popc_in_T_134 = mux(_popc_in_T_5, UInt<65>(0h1), _popc_in_T_133) \n node _popc_in_T_135 = sub(_popc_in_T_134, UInt<1>(0h1)) \n node _popc_in_T_136 = tail(_popc_in_T_135, 1) \n node _popc_in_T_137 = mux(_popc_in_T, _popc_in_T_3, _popc_in_T_136) \n node popc_in = bits(_popc_in_T_137, 63, 0) \n node _count_T = bits(popc_in, 0, 0) \n node _count_T_1 = bits(popc_in, 1, 1) \n node _count_T_2 = bits(popc_in, 2, 2) \n node _count_T_3 = bits(popc_in, 3, 3) \n node _count_T_4 = bits(popc_in, 4, 4) \n node _count_T_5 = bits(popc_in, 5, 5) \n node _count_T_6 = bits(popc_in, 6, 6) \n node _count_T_7 = bits(popc_in, 7, 7) \n node _count_T_8 = bits(popc_in, 8, 8) \n node _count_T_9 = bits(popc_in, 9, 9) \n node _count_T_10 = bits(popc_in, 10, 10) \n node _count_T_11 = bits(popc_in, 11, 11) \n node _count_T_12 = bits(popc_in, 12, 12) \n node _count_T_13 = bits(popc_in, 13, 13) \n node _count_T_14 = bits(popc_in, 14, 14) \n node _count_T_15 = bits(popc_in, 15, 15) \n node _count_T_16 = bits(popc_in, 16, 16) \n node _count_T_17 = bits(popc_in, 17, 17) \n node _count_T_18 = bits(popc_in, 18, 18) \n node _count_T_19 = bits(popc_in, 19, 19) \n node _count_T_20 = bits(popc_in, 20, 20) \n node _count_T_21 = bits(popc_in, 21, 21) \n node _count_T_22 = bits(popc_in, 22, 22) \n node _count_T_23 = bits(popc_in, 23, 23) \n node _count_T_24 = bits(popc_in, 24, 24) \n node _count_T_25 = bits(popc_in, 25, 25) \n node _count_T_26 = bits(popc_in, 26, 26) \n node _count_T_27 = bits(popc_in, 27, 27) \n node _count_T_28 = bits(popc_in, 28, 28) \n node _count_T_29 = bits(popc_in, 29, 29) \n node _count_T_30 = bits(popc_in, 30, 30) \n node _count_T_31 = bits(popc_in, 31, 31) \n node _count_T_32 = bits(popc_in, 32, 32) \n node _count_T_33 = bits(popc_in, 33, 33) \n node _count_T_34 = bits(popc_in, 34, 34) \n node _count_T_35 = bits(popc_in, 35, 35) \n node _count_T_36 = bits(popc_in, 36, 36) \n node _count_T_37 = bits(popc_in, 37, 37) \n node _count_T_38 = bits(popc_in, 38, 38) \n node _count_T_39 = bits(popc_in, 39, 39) \n node _count_T_40 = bits(popc_in, 40, 40) \n node _count_T_41 = bits(popc_in, 41, 41) \n node _count_T_42 = bits(popc_in, 42, 42) \n node _count_T_43 = bits(popc_in, 43, 43) \n node _count_T_44 = bits(popc_in, 44, 44) \n node _count_T_45 = bits(popc_in, 45, 45) \n node _count_T_46 = bits(popc_in, 46, 46) \n node _count_T_47 = bits(popc_in, 47, 47) \n node _count_T_48 = bits(popc_in, 48, 48) \n node _count_T_49 = bits(popc_in, 49, 49) \n node _count_T_50 = bits(popc_in, 50, 50) \n node _count_T_51 = bits(popc_in, 51, 51) \n node _count_T_52 = bits(popc_in, 52, 52) \n node _count_T_53 = bits(popc_in, 53, 53) \n node _count_T_54 = bits(popc_in, 54, 54) \n node _count_T_55 = bits(popc_in, 55, 55) \n node _count_T_56 = bits(popc_in, 56, 56) \n node _count_T_57 = bits(popc_in, 57, 57) \n node _count_T_58 = bits(popc_in, 58, 58) \n node _count_T_59 = bits(popc_in, 59, 59) \n node _count_T_60 = bits(popc_in, 60, 60) \n node _count_T_61 = bits(popc_in, 61, 61) \n node _count_T_62 = bits(popc_in, 62, 62) \n node _count_T_63 = bits(popc_in, 63, 63) \n node _count_T_64 = add(_count_T, _count_T_1) \n node _count_T_65 = bits(_count_T_64, 1, 0) \n node _count_T_66 = add(_count_T_2, _count_T_3) \n node _count_T_67 = bits(_count_T_66, 1, 0) \n node _count_T_68 = add(_count_T_65, _count_T_67) \n node _count_T_69 = bits(_count_T_68, 2, 0) \n node _count_T_70 = add(_count_T_4, _count_T_5) \n node _count_T_71 = bits(_count_T_70, 1, 0) \n node _count_T_72 = add(_count_T_6, _count_T_7) \n node _count_T_73 = bits(_count_T_72, 1, 0) \n node _count_T_74 = add(_count_T_71, _count_T_73) \n node _count_T_75 = bits(_count_T_74, 2, 0) \n node _count_T_76 = add(_count_T_69, _count_T_75) \n node _count_T_77 = bits(_count_T_76, 3, 0) \n node _count_T_78 = add(_count_T_8, _count_T_9) \n node _count_T_79 = bits(_count_T_78, 1, 0) \n node _count_T_80 = add(_count_T_10, _count_T_11) \n node _count_T_81 = bits(_count_T_80, 1, 0) \n node _count_T_82 = add(_count_T_79, _count_T_81) \n node _count_T_83 = bits(_count_T_82, 2, 0) \n node _count_T_84 = add(_count_T_12, _count_T_13) \n node _count_T_85 = bits(_count_T_84, 1, 0) \n node _count_T_86 = add(_count_T_14, _count_T_15) \n node _count_T_87 = bits(_count_T_86, 1, 0) \n node _count_T_88 = add(_count_T_85, _count_T_87) \n node _count_T_89 = bits(_count_T_88, 2, 0) \n node _count_T_90 = add(_count_T_83, _count_T_89) \n node _count_T_91 = bits(_count_T_90, 3, 0) \n node _count_T_92 = add(_count_T_77, _count_T_91) \n node _count_T_93 = bits(_count_T_92, 4, 0) \n node _count_T_94 = add(_count_T_16, _count_T_17) \n node _count_T_95 = bits(_count_T_94, 1, 0) \n node _count_T_96 = add(_count_T_18, _count_T_19) \n node _count_T_97 = bits(_count_T_96, 1, 0) \n node _count_T_98 = add(_count_T_95, _count_T_97) \n node _count_T_99 = bits(_count_T_98, 2, 0) \n node _count_T_100 = add(_count_T_20, _count_T_21) \n node _count_T_101 = bits(_count_T_100, 1, 0) \n node _count_T_102 = add(_count_T_22, _count_T_23) \n node _count_T_103 = bits(_count_T_102, 1, 0) \n node _count_T_104 = add(_count_T_101, _count_T_103) \n node _count_T_105 = bits(_count_T_104, 2, 0) \n node _count_T_106 = add(_count_T_99, _count_T_105) \n node _count_T_107 = bits(_count_T_106, 3, 0) \n node _count_T_108 = add(_count_T_24, _count_T_25) \n node _count_T_109 = bits(_count_T_108, 1, 0) \n node _count_T_110 = add(_count_T_26, _count_T_27) \n node _count_T_111 = bits(_count_T_110, 1, 0) \n node _count_T_112 = add(_count_T_109, _count_T_111) \n node _count_T_113 = bits(_count_T_112, 2, 0) \n node _count_T_114 = add(_count_T_28, _count_T_29) \n node _count_T_115 = bits(_count_T_114, 1, 0) \n node _count_T_116 = add(_count_T_30, _count_T_31) \n node _count_T_117 = bits(_count_T_116, 1, 0) \n node _count_T_118 = add(_count_T_115, _count_T_117) \n node _count_T_119 = bits(_count_T_118, 2, 0) \n node _count_T_120 = add(_count_T_113, _count_T_119) \n node _count_T_121 = bits(_count_T_120, 3, 0) \n node _count_T_122 = add(_count_T_107, _count_T_121) \n node _count_T_123 = bits(_count_T_122, 4, 0) \n node _count_T_124 = add(_count_T_93, _count_T_123) \n node _count_T_125 = bits(_count_T_124, 5, 0) \n node _count_T_126 = add(_count_T_32, _count_T_33) \n node _count_T_127 = bits(_count_T_126, 1, 0) \n node _count_T_128 = add(_count_T_34, _count_T_35) \n node _count_T_129 = bits(_count_T_128, 1, 0) \n node _count_T_130 = add(_count_T_127, _count_T_129) \n node _count_T_131 = bits(_count_T_130, 2, 0) \n node _count_T_132 = add(_count_T_36, _count_T_37) \n node _count_T_133 = bits(_count_T_132, 1, 0) \n node _count_T_134 = add(_count_T_38, _count_T_39) \n node _count_T_135 = bits(_count_T_134, 1, 0) \n node _count_T_136 = add(_count_T_133, _count_T_135) \n node _count_T_137 = bits(_count_T_136, 2, 0) \n node _count_T_138 = add(_count_T_131, _count_T_137) \n node _count_T_139 = bits(_count_T_138, 3, 0) \n node _count_T_140 = add(_count_T_40, _count_T_41) \n node _count_T_141 = bits(_count_T_140, 1, 0) \n node _count_T_142 = add(_count_T_42, _count_T_43) \n node _count_T_143 = bits(_count_T_142, 1, 0) \n node _count_T_144 = add(_count_T_141, _count_T_143) \n node _count_T_145 = bits(_count_T_144, 2, 0) \n node _count_T_146 = add(_count_T_44, _count_T_45) \n node _count_T_147 = bits(_count_T_146, 1, 0) \n node _count_T_148 = add(_count_T_46, _count_T_47) \n node _count_T_149 = bits(_count_T_148, 1, 0) \n node _count_T_150 = add(_count_T_147, _count_T_149) \n node _count_T_151 = bits(_count_T_150, 2, 0) \n node _count_T_152 = add(_count_T_145, _count_T_151) \n node _count_T_153 = bits(_count_T_152, 3, 0) \n node _count_T_154 = add(_count_T_139, _count_T_153) \n node _count_T_155 = bits(_count_T_154, 4, 0) \n node _count_T_156 = add(_count_T_48, _count_T_49) \n node _count_T_157 = bits(_count_T_156, 1, 0) \n node _count_T_158 = add(_count_T_50, _count_T_51) \n node _count_T_159 = bits(_count_T_158, 1, 0) \n node _count_T_160 = add(_count_T_157, _count_T_159) \n node _count_T_161 = bits(_count_T_160, 2, 0) \n node _count_T_162 = add(_count_T_52, _count_T_53) \n node _count_T_163 = bits(_count_T_162, 1, 0) \n node _count_T_164 = add(_count_T_54, _count_T_55) \n node _count_T_165 = bits(_count_T_164, 1, 0) \n node _count_T_166 = add(_count_T_163, _count_T_165) \n node _count_T_167 = bits(_count_T_166, 2, 0) \n node _count_T_168 = add(_count_T_161, _count_T_167) \n node _count_T_169 = bits(_count_T_168, 3, 0) \n node _count_T_170 = add(_count_T_56, _count_T_57) \n node _count_T_171 = bits(_count_T_170, 1, 0) \n node _count_T_172 = add(_count_T_58, _count_T_59) \n node _count_T_173 = bits(_count_T_172, 1, 0) \n node _count_T_174 = add(_count_T_171, _count_T_173) \n node _count_T_175 = bits(_count_T_174, 2, 0) \n node _count_T_176 = add(_count_T_60, _count_T_61) \n node _count_T_177 = bits(_count_T_176, 1, 0) \n node _count_T_178 = add(_count_T_62, _count_T_63) \n node _count_T_179 = bits(_count_T_178, 1, 0) \n node _count_T_180 = add(_count_T_177, _count_T_179) \n node _count_T_181 = bits(_count_T_180, 2, 0) \n node _count_T_182 = add(_count_T_175, _count_T_181) \n node _count_T_183 = bits(_count_T_182, 3, 0) \n node _count_T_184 = add(_count_T_169, _count_T_183) \n node _count_T_185 = bits(_count_T_184, 4, 0) \n node _count_T_186 = add(_count_T_155, _count_T_185) \n node _count_T_187 = bits(_count_T_186, 5, 0) \n node _count_T_188 = add(_count_T_125, _count_T_187) \n node count = bits(_count_T_188, 6, 0) \n wire in1_bytes : UInt<8>[8] \n wire _in1_bytes_WIRE : UInt<64> \n connect _in1_bytes_WIRE, io.in1 \n node _in1_bytes_T = bits(_in1_bytes_WIRE, 7, 0) \n connect in1_bytes[0], _in1_bytes_T \n node _in1_bytes_T_1 = bits(_in1_bytes_WIRE, 15, 8) \n connect in1_bytes[1], _in1_bytes_T_1 \n node _in1_bytes_T_2 = bits(_in1_bytes_WIRE, 23, 16) \n connect in1_bytes[2], _in1_bytes_T_2 \n node _in1_bytes_T_3 = bits(_in1_bytes_WIRE, 31, 24) \n connect in1_bytes[3], _in1_bytes_T_3 \n node _in1_bytes_T_4 = bits(_in1_bytes_WIRE, 39, 32) \n connect in1_bytes[4], _in1_bytes_T_4 \n node _in1_bytes_T_5 = bits(_in1_bytes_WIRE, 47, 40) \n connect in1_bytes[5], _in1_bytes_T_5 \n node _in1_bytes_T_6 = bits(_in1_bytes_WIRE, 55, 48) \n connect in1_bytes[6], _in1_bytes_T_6 \n node _in1_bytes_T_7 = bits(_in1_bytes_WIRE, 63, 56) \n connect in1_bytes[7], _in1_bytes_T_7 \n node _orcb_T = neq(in1_bytes[0], UInt<1>(0h0)) \n node _orcb_T_1 = mux(_orcb_T, UInt<8>(0hff), UInt<8>(0h0)) \n node _orcb_T_2 = neq(in1_bytes[1], UInt<1>(0h0)) \n node _orcb_T_3 = mux(_orcb_T_2, UInt<8>(0hff), UInt<8>(0h0)) \n node _orcb_T_4 = neq(in1_bytes[2], UInt<1>(0h0)) \n node _orcb_T_5 = mux(_orcb_T_4, UInt<8>(0hff), UInt<8>(0h0)) \n node _orcb_T_6 = neq(in1_bytes[3], UInt<1>(0h0)) \n node _orcb_T_7 = mux(_orcb_T_6, UInt<8>(0hff), UInt<8>(0h0)) \n node _orcb_T_8 = neq(in1_bytes[4], UInt<1>(0h0)) \n node _orcb_T_9 = mux(_orcb_T_8, UInt<8>(0hff), UInt<8>(0h0)) \n node _orcb_T_10 = neq(in1_bytes[5], UInt<1>(0h0)) \n node _orcb_T_11 = mux(_orcb_T_10, UInt<8>(0hff), UInt<8>(0h0)) \n node _orcb_T_12 = neq(in1_bytes[6], UInt<1>(0h0)) \n node _orcb_T_13 = mux(_orcb_T_12, UInt<8>(0hff), UInt<8>(0h0)) \n node _orcb_T_14 = neq(in1_bytes[7], UInt<1>(0h0)) \n node _orcb_T_15 = mux(_orcb_T_14, UInt<8>(0hff), UInt<8>(0h0)) \n wire _orcb_WIRE : UInt<8>[8] \n connect _orcb_WIRE[0], _orcb_T_1 \n connect _orcb_WIRE[1], _orcb_T_3 \n connect _orcb_WIRE[2], _orcb_T_5 \n connect _orcb_WIRE[3], _orcb_T_7 \n connect _orcb_WIRE[4], _orcb_T_9 \n connect _orcb_WIRE[5], _orcb_T_11 \n connect _orcb_WIRE[6], _orcb_T_13 \n connect _orcb_WIRE[7], _orcb_T_15 \n node orcb_lo_lo = cat(_orcb_WIRE[1], _orcb_WIRE[0]) \n node orcb_lo_hi = cat(_orcb_WIRE[3], _orcb_WIRE[2]) \n node orcb_lo = cat(orcb_lo_hi, orcb_lo_lo) \n node orcb_hi_lo = cat(_orcb_WIRE[5], _orcb_WIRE[4]) \n node orcb_hi_hi = cat(_orcb_WIRE[7], _orcb_WIRE[6]) \n node orcb_hi = cat(orcb_hi_hi, orcb_hi_lo) \n node orcb = cat(orcb_hi, orcb_lo) \n wire _rev8_WIRE : UInt<8>[8] \n connect _rev8_WIRE[0], in1_bytes[7] \n connect _rev8_WIRE[1], in1_bytes[6] \n connect _rev8_WIRE[2], in1_bytes[5] \n connect _rev8_WIRE[3], in1_bytes[4] \n connect _rev8_WIRE[4], in1_bytes[3] \n connect _rev8_WIRE[5], in1_bytes[2] \n connect _rev8_WIRE[6], in1_bytes[1] \n connect _rev8_WIRE[7], in1_bytes[0] \n node rev8_lo_lo = cat(_rev8_WIRE[1], _rev8_WIRE[0]) \n node rev8_lo_hi = cat(_rev8_WIRE[3], _rev8_WIRE[2]) \n node rev8_lo = cat(rev8_lo_hi, rev8_lo_lo) \n node rev8_hi_lo = cat(_rev8_WIRE[5], _rev8_WIRE[4]) \n node rev8_hi_hi = cat(_rev8_WIRE[7], _rev8_WIRE[6]) \n node rev8_hi = cat(rev8_hi_hi, rev8_hi_lo) \n node rev8 = cat(rev8_hi, rev8_lo) \n node _unary_T = bits(io.in2, 11, 0) \n node _unary_T_1 = bits(io.in1, 15, 0) \n node _unary_T_2 = bits(io.in1, 7, 7) \n node _unary_T_3 = mux(_unary_T_2, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) \n node _unary_T_4 = bits(io.in1, 7, 0) \n node _unary_T_5 = cat(_unary_T_3, _unary_T_4) \n node _unary_T_6 = bits(io.in1, 15, 15) \n node _unary_T_7 = mux(_unary_T_6, UInt<48>(0hffffffffffff), UInt<48>(0h0)) \n node _unary_T_8 = bits(io.in1, 15, 0) \n node _unary_T_9 = cat(_unary_T_7, _unary_T_8) \n node _unary_T_10 = eq(UInt<10>(0h287), _unary_T) \n node _unary_T_11 = mux(_unary_T_10, orcb, count) \n node _unary_T_12 = eq(UInt<11>(0h6b8), _unary_T) \n node _unary_T_13 = mux(_unary_T_12, rev8, _unary_T_11) \n node _unary_T_14 = eq(UInt<8>(0h80), _unary_T) \n node _unary_T_15 = mux(_unary_T_14, _unary_T_1, _unary_T_13) \n node _unary_T_16 = eq(UInt<11>(0h604), _unary_T) \n node _unary_T_17 = mux(_unary_T_16, _unary_T_5, _unary_T_15) \n node _unary_T_18 = eq(UInt<11>(0h605), _unary_T) \n node unary = mux(_unary_T_18, _unary_T_9, _unary_T_17) \n node maxmin_out = mux(io.cmp_out, io.in2, io.in1) \n node _rot_shamt_T = eq(io.dw, UInt<1>(0h0)) \n node _rot_shamt_T_1 = mux(_rot_shamt_T, UInt<6>(0h20), UInt<7>(0h40)) \n node _rot_shamt_T_2 = sub(_rot_shamt_T_1, shamt) \n node rot_shamt = tail(_rot_shamt_T_2, 1) \n node _rotin_T = bits(io.fn, 0, 0) \n node _rotin_T_1 = shl(UInt<32>(0hffffffff), 32) \n node _rotin_T_2 = xor(UInt<64>(0hffffffffffffffff), _rotin_T_1) \n node _rotin_T_3 = shr(shin_r, 32) \n node _rotin_T_4 = and(_rotin_T_3, _rotin_T_2) \n node _rotin_T_5 = bits(shin_r, 31, 0) \n node _rotin_T_6 = shl(_rotin_T_5, 32) \n node _rotin_T_7 = not(_rotin_T_2) \n node _rotin_T_8 = and(_rotin_T_6, _rotin_T_7) \n node _rotin_T_9 = or(_rotin_T_4, _rotin_T_8) \n node _rotin_T_10 = bits(_rotin_T_2, 47, 0) \n node _rotin_T_11 = shl(_rotin_T_10, 16) \n node _rotin_T_12 = xor(_rotin_T_2, _rotin_T_11) \n node _rotin_T_13 = shr(_rotin_T_9, 16) \n node _rotin_T_14 = and(_rotin_T_13, _rotin_T_12) \n node _rotin_T_15 = bits(_rotin_T_9, 47, 0) \n node _rotin_T_16 = shl(_rotin_T_15, 16) \n node _rotin_T_17 = not(_rotin_T_12) \n node _rotin_T_18 = and(_rotin_T_16, _rotin_T_17) \n node _rotin_T_19 = or(_rotin_T_14, _rotin_T_18) \n node _rotin_T_20 = bits(_rotin_T_12, 55, 0) \n node _rotin_T_21 = shl(_rotin_T_20, 8) \n node _rotin_T_22 = xor(_rotin_T_12, _rotin_T_21) \n node _rotin_T_23 = shr(_rotin_T_19, 8) \n node _rotin_T_24 = and(_rotin_T_23, _rotin_T_22) \n node _rotin_T_25 = bits(_rotin_T_19, 55, 0) \n node _rotin_T_26 = shl(_rotin_T_25, 8) \n node _rotin_T_27 = not(_rotin_T_22) \n node _rotin_T_28 = and(_rotin_T_26, _rotin_T_27) \n node _rotin_T_29 = or(_rotin_T_24, _rotin_T_28) \n node _rotin_T_30 = bits(_rotin_T_22, 59, 0) \n node _rotin_T_31 = shl(_rotin_T_30, 4) \n node _rotin_T_32 = xor(_rotin_T_22, _rotin_T_31) \n node _rotin_T_33 = shr(_rotin_T_29, 4) \n node _rotin_T_34 = and(_rotin_T_33, _rotin_T_32) \n node _rotin_T_35 = bits(_rotin_T_29, 59, 0) \n node _rotin_T_36 = shl(_rotin_T_35, 4) \n node _rotin_T_37 = not(_rotin_T_32) \n node _rotin_T_38 = and(_rotin_T_36, _rotin_T_37) \n node _rotin_T_39 = or(_rotin_T_34, _rotin_T_38) \n node _rotin_T_40 = bits(_rotin_T_32, 61, 0) \n node _rotin_T_41 = shl(_rotin_T_40, 2) \n node _rotin_T_42 = xor(_rotin_T_32, _rotin_T_41) \n node _rotin_T_43 = shr(_rotin_T_39, 2) \n node _rotin_T_44 = and(_rotin_T_43, _rotin_T_42) \n node _rotin_T_45 = bits(_rotin_T_39, 61, 0) \n node _rotin_T_46 = shl(_rotin_T_45, 2) \n node _rotin_T_47 = not(_rotin_T_42) \n node _rotin_T_48 = and(_rotin_T_46, _rotin_T_47) \n node _rotin_T_49 = or(_rotin_T_44, _rotin_T_48) \n node _rotin_T_50 = bits(_rotin_T_42, 62, 0) \n node _rotin_T_51 = shl(_rotin_T_50, 1) \n node _rotin_T_52 = xor(_rotin_T_42, _rotin_T_51) \n node _rotin_T_53 = shr(_rotin_T_49, 1) \n node _rotin_T_54 = and(_rotin_T_53, _rotin_T_52) \n node _rotin_T_55 = bits(_rotin_T_49, 62, 0) \n node _rotin_T_56 = shl(_rotin_T_55, 1) \n node _rotin_T_57 = not(_rotin_T_52) \n node _rotin_T_58 = and(_rotin_T_56, _rotin_T_57) \n node _rotin_T_59 = or(_rotin_T_54, _rotin_T_58) \n node rotin = mux(_rotin_T, shin_r, _rotin_T_59) \n node _rotout_r_T = dshr(rotin, rot_shamt) \n node rotout_r = bits(_rotout_r_T, 63, 0) \n node _rotout_l_T = shl(UInt<32>(0hffffffff), 32) \n node _rotout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _rotout_l_T) \n node _rotout_l_T_2 = shr(rotout_r, 32) \n node _rotout_l_T_3 = and(_rotout_l_T_2, _rotout_l_T_1) \n node _rotout_l_T_4 = bits(rotout_r, 31, 0) \n node _rotout_l_T_5 = shl(_rotout_l_T_4, 32) \n node _rotout_l_T_6 = not(_rotout_l_T_1) \n node _rotout_l_T_7 = and(_rotout_l_T_5, _rotout_l_T_6) \n node _rotout_l_T_8 = or(_rotout_l_T_3, _rotout_l_T_7) \n node _rotout_l_T_9 = bits(_rotout_l_T_1, 47, 0) \n node _rotout_l_T_10 = shl(_rotout_l_T_9, 16) \n node _rotout_l_T_11 = xor(_rotout_l_T_1, _rotout_l_T_10) \n node _rotout_l_T_12 = shr(_rotout_l_T_8, 16) \n node _rotout_l_T_13 = and(_rotout_l_T_12, _rotout_l_T_11) \n node _rotout_l_T_14 = bits(_rotout_l_T_8, 47, 0) \n node _rotout_l_T_15 = shl(_rotout_l_T_14, 16) \n node _rotout_l_T_16 = not(_rotout_l_T_11) \n node _rotout_l_T_17 = and(_rotout_l_T_15, _rotout_l_T_16) \n node _rotout_l_T_18 = or(_rotout_l_T_13, _rotout_l_T_17) \n node _rotout_l_T_19 = bits(_rotout_l_T_11, 55, 0) \n node _rotout_l_T_20 = shl(_rotout_l_T_19, 8) \n node _rotout_l_T_21 = xor(_rotout_l_T_11, _rotout_l_T_20) \n node _rotout_l_T_22 = shr(_rotout_l_T_18, 8) \n node _rotout_l_T_23 = and(_rotout_l_T_22, _rotout_l_T_21) \n node _rotout_l_T_24 = bits(_rotout_l_T_18, 55, 0) \n node _rotout_l_T_25 = shl(_rotout_l_T_24, 8) \n node _rotout_l_T_26 = not(_rotout_l_T_21) \n node _rotout_l_T_27 = and(_rotout_l_T_25, _rotout_l_T_26) \n node _rotout_l_T_28 = or(_rotout_l_T_23, _rotout_l_T_27) \n node _rotout_l_T_29 = bits(_rotout_l_T_21, 59, 0) \n node _rotout_l_T_30 = shl(_rotout_l_T_29, 4) \n node _rotout_l_T_31 = xor(_rotout_l_T_21, _rotout_l_T_30) \n node _rotout_l_T_32 = shr(_rotout_l_T_28, 4) \n node _rotout_l_T_33 = and(_rotout_l_T_32, _rotout_l_T_31) \n node _rotout_l_T_34 = bits(_rotout_l_T_28, 59, 0) \n node _rotout_l_T_35 = shl(_rotout_l_T_34, 4) \n node _rotout_l_T_36 = not(_rotout_l_T_31) \n node _rotout_l_T_37 = and(_rotout_l_T_35, _rotout_l_T_36) \n node _rotout_l_T_38 = or(_rotout_l_T_33, _rotout_l_T_37) \n node _rotout_l_T_39 = bits(_rotout_l_T_31, 61, 0) \n node _rotout_l_T_40 = shl(_rotout_l_T_39, 2) \n node _rotout_l_T_41 = xor(_rotout_l_T_31, _rotout_l_T_40) \n node _rotout_l_T_42 = shr(_rotout_l_T_38, 2) \n node _rotout_l_T_43 = and(_rotout_l_T_42, _rotout_l_T_41) \n node _rotout_l_T_44 = bits(_rotout_l_T_38, 61, 0) \n node _rotout_l_T_45 = shl(_rotout_l_T_44, 2) \n node _rotout_l_T_46 = not(_rotout_l_T_41) \n node _rotout_l_T_47 = and(_rotout_l_T_45, _rotout_l_T_46) \n node _rotout_l_T_48 = or(_rotout_l_T_43, _rotout_l_T_47) \n node _rotout_l_T_49 = bits(_rotout_l_T_41, 62, 0) \n node _rotout_l_T_50 = shl(_rotout_l_T_49, 1) \n node _rotout_l_T_51 = xor(_rotout_l_T_41, _rotout_l_T_50) \n node _rotout_l_T_52 = shr(_rotout_l_T_48, 1) \n node _rotout_l_T_53 = and(_rotout_l_T_52, _rotout_l_T_51) \n node _rotout_l_T_54 = bits(_rotout_l_T_48, 62, 0) \n node _rotout_l_T_55 = shl(_rotout_l_T_54, 1) \n node _rotout_l_T_56 = not(_rotout_l_T_51) \n node _rotout_l_T_57 = and(_rotout_l_T_55, _rotout_l_T_56) \n node rotout_l = or(_rotout_l_T_53, _rotout_l_T_57) \n node _rotout_T = bits(io.fn, 0, 0) \n node _rotout_T_1 = mux(_rotout_T, rotout_r, rotout_l) \n node _rotout_T_2 = bits(io.fn, 0, 0) \n node _rotout_T_3 = mux(_rotout_T_2, shout_l, shout_r) \n node rotout = or(_rotout_T_1, _rotout_T_3) \n node _out_T = eq(UInt<1>(0h0), io.fn) \n node _out_T_1 = mux(_out_T, io.adder_out, shift_logic) \n node _out_T_2 = eq(UInt<4>(0ha), io.fn) \n node _out_T_3 = mux(_out_T_2, io.adder_out, _out_T_1) \n node _out_T_4 = eq(UInt<5>(0h10), io.fn) \n node _out_T_5 = mux(_out_T_4, unary, _out_T_3) \n node _out_T_6 = eq(UInt<5>(0h1c), io.fn) \n node _out_T_7 = mux(_out_T_6, maxmin_out, _out_T_5) \n node _out_T_8 = eq(UInt<5>(0h1d), io.fn) \n node _out_T_9 = mux(_out_T_8, maxmin_out, _out_T_7) \n node _out_T_10 = eq(UInt<5>(0h1e), io.fn) \n node _out_T_11 = mux(_out_T_10, maxmin_out, _out_T_9) \n node _out_T_12 = eq(UInt<5>(0h1f), io.fn) \n node _out_T_13 = mux(_out_T_12, maxmin_out, _out_T_11) \n node _out_T_14 = eq(UInt<5>(0h11), io.fn) \n node _out_T_15 = mux(_out_T_14, rotout, _out_T_13) \n node _out_T_16 = eq(UInt<5>(0h12), io.fn) \n node out = mux(_out_T_16, rotout, _out_T_15) \n connect io.out, out \n node _T_1 = eq(io.dw, UInt<1>(0h0)) \n when _T_1 : \n node _io_out_T = bits(out, 31, 31) \n node _io_out_T_1 = mux(_io_out_T, UInt<32>(0hffffffff), UInt<32>(0h0)) \n node _io_out_T_2 = bits(out, 31, 0) \n node _io_out_T_3 = cat(_io_out_T_1, _io_out_T_2) \n connect io.out, _io_out_T_3"},"response":{"kind":"string","value":"module ALU_2(\t// @[ALU.scala:83:7]\n input clock,\t// @[ALU.scala:83:7]\n input reset,\t// @[ALU.scala:83:7]\n input io_dw,\t// @[ALU.scala:72:14]\n input [4:0] io_fn,\t// @[ALU.scala:72:14]\n input [63:0] io_in2,\t// @[ALU.scala:72:14]\n input [63:0] io_in1,\t// @[ALU.scala:72:14]\n output [63:0] io_out,\t// @[ALU.scala:72:14]\n output [63:0] io_adder_out,\t// @[ALU.scala:72:14]\n output io_cmp_out\t// @[ALU.scala:72:14]\n);\n\n wire [7:0] in1_bytes_6;\t// @[ALU.scala:140:34]\n wire [7:0] in1_bytes_5;\t// @[ALU.scala:140:34]\n wire [7:0] in1_bytes_4;\t// @[ALU.scala:140:34]\n wire [7:0] in1_bytes_3;\t// @[ALU.scala:140:34]\n wire [7:0] in1_bytes_2;\t// @[ALU.scala:140:34]\n wire [7:0] in1_bytes_1;\t// @[ALU.scala:140:34]\n wire [7:0] in1_bytes_0;\t// @[ALU.scala:140:34]\n wire io_dw_0 = io_dw;\t// @[ALU.scala:83:7]\n wire [4:0] io_fn_0 = io_fn;\t// @[ALU.scala:83:7]\n wire [63:0] io_in2_0 = io_in2;\t// @[ALU.scala:83:7]\n wire [63:0] io_in1_0 = io_in1;\t// @[ALU.scala:83:7]\n wire [63:0] _bext_mask_T_2 = 64'hFFFFFFFFFFFFFFFF;\t// @[ALU.scala:122:70]\n wire [31:0] _tz_in_T_67 = 32'hFFFF;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_66 = 32'hFFFF0000;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_72 = 32'hFFFF0000;\t// @[ALU.scala:134:26]\n wire [23:0] _tz_in_T_75 = 24'hFFFF;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_76 = 32'hFFFF00;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_77 = 32'hFF00FF;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_82 = 32'hFF00FF00;\t// @[ALU.scala:134:26]\n wire [27:0] _tz_in_T_85 = 28'hFF00FF;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_86 = 32'hFF00FF0;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_87 = 32'hF0F0F0F;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_92 = 32'hF0F0F0F0;\t// @[ALU.scala:134:26]\n wire [29:0] _tz_in_T_95 = 30'hF0F0F0F;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_96 = 32'h3C3C3C3C;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_97 = 32'h33333333;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_102 = 32'hCCCCCCCC;\t// @[ALU.scala:134:26]\n wire [30:0] _tz_in_T_105 = 31'h33333333;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_106 = 32'h66666666;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_107 = 32'h55555555;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_112 = 32'hAAAAAAAA;\t// @[ALU.scala:134:26]\n wire [63:0] _shin_T_9 = 64'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_1 = 64'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_5 = 64'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_2 = 64'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_1 = 64'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_8 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_14 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:106:46]\n wire [63:0] _shout_l_T = 64'hFFFFFFFF00000000;\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_6 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:108:24]\n wire [63:0] _tz_in_T_4 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_10 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:132:19]\n wire [63:0] _rotin_T_1 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_7 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:156:44]\n wire [63:0] _rotout_l_T = 64'hFFFFFFFF00000000;\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_6 = 64'hFFFFFFFF00000000;\t// @[ALU.scala:158:25]\n wire [47:0] _shin_T_17 = 48'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _shout_l_T_9 = 48'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _tz_in_T_13 = 48'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _rotin_T_10 = 48'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _rotout_l_T_9 = 48'hFFFFFFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_18 = 64'hFFFFFFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_10 = 64'hFFFFFFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_14 = 64'hFFFFFFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_11 = 64'hFFFFFFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_10 = 64'hFFFFFFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_19 = 64'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_11 = 64'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_15 = 64'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_12 = 64'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_11 = 64'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_24 = 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_16 = 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_20 = 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_17 = 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_16 = 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _shin_T_27 = 56'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _shout_l_T_19 = 56'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _tz_in_T_23 = 56'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _rotin_T_20 = 56'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _rotout_l_T_19 = 56'hFFFF0000FFFF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_28 = 64'hFFFF0000FFFF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_20 = 64'hFFFF0000FFFF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_24 = 64'hFFFF0000FFFF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_21 = 64'hFFFF0000FFFF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_20 = 64'hFFFF0000FFFF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_29 = 64'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_21 = 64'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_25 = 64'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_22 = 64'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_21 = 64'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_34 = 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_26 = 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_30 = 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_27 = 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_26 = 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _shin_T_37 = 60'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _shout_l_T_29 = 60'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _tz_in_T_33 = 60'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _rotin_T_30 = 60'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _rotout_l_T_29 = 60'hFF00FF00FF00FF;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_38 = 64'hFF00FF00FF00FF0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_30 = 64'hFF00FF00FF00FF0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_34 = 64'hFF00FF00FF00FF0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_31 = 64'hFF00FF00FF00FF0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_30 = 64'hFF00FF00FF00FF0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_39 = 64'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_31 = 64'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_35 = 64'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_32 = 64'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_31 = 64'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_44 = 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_36 = 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_40 = 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_37 = 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_36 = 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [61:0] _shin_T_47 = 62'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [61:0] _shout_l_T_39 = 62'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [61:0] _tz_in_T_43 = 62'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [61:0] _rotin_T_40 = 62'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [61:0] _rotout_l_T_39 = 62'hF0F0F0F0F0F0F0F;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_48 = 64'h3C3C3C3C3C3C3C3C;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_40 = 64'h3C3C3C3C3C3C3C3C;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_44 = 64'h3C3C3C3C3C3C3C3C;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_41 = 64'h3C3C3C3C3C3C3C3C;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_40 = 64'h3C3C3C3C3C3C3C3C;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_49 = 64'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_41 = 64'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_45 = 64'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_42 = 64'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_41 = 64'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_54 = 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_46 = 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_50 = 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_47 = 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_46 = 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _shin_T_57 = 63'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _shout_l_T_49 = 63'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _tz_in_T_53 = 63'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _rotin_T_50 = 63'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _rotout_l_T_49 = 63'h3333333333333333;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_58 = 64'h6666666666666666;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_50 = 64'h6666666666666666;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_54 = 64'h6666666666666666;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_51 = 64'h6666666666666666;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_50 = 64'h6666666666666666;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_59 = 64'h5555555555555555;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_51 = 64'h5555555555555555;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_55 = 64'h5555555555555555;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_52 = 64'h5555555555555555;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_51 = 64'h5555555555555555;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_64 = 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_56 = 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_60 = 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_57 = 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_56 = 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire _shin_hi_T = io_dw_0;\t// @[ALU.scala:83:7, :102:31]\n wire _shamt_T_1 = io_dw_0;\t// @[ALU.scala:83:7, :103:42]\n wire [63:0] _in1_bytes_WIRE = io_in1_0;\t// @[ALU.scala:83:7, :140:34]\n wire [63:0] _io_adder_out_T_4;\t// @[ALU.scala:88:36]\n wire _io_cmp_out_T_5;\t// @[ALU.scala:94:36]\n wire [63:0] io_out_0;\t// @[ALU.scala:83:7]\n wire [63:0] io_adder_out_0;\t// @[ALU.scala:83:7]\n wire io_cmp_out_0;\t// @[ALU.scala:83:7]\n wire _in2_inv_T = io_fn_0[3];\t// @[ALU.scala:58:29, :83:7]\n wire _io_adder_out_T_2 = io_fn_0[3];\t// @[ALU.scala:58:29, :83:7]\n wire _io_cmp_out_T_1 = io_fn_0[3];\t// @[ALU.scala:58:29, :63:30, :83:7]\n wire _shin_hi_32_T = io_fn_0[3];\t// @[ALU.scala:58:29, :83:7]\n wire _shout_r_T = io_fn_0[3];\t// @[ALU.scala:58:29, :83:7]\n wire [63:0] _in2_inv_T_1 = ~io_in2_0;\t// @[ALU.scala:83:7, :85:35]\n wire [63:0] in2_inv = _in2_inv_T ? _in2_inv_T_1 : io_in2_0;\t// @[ALU.scala:58:29, :83:7, :85:{20,35}]\n wire [63:0] in1_xor_in2 = io_in1_0 ^ in2_inv;\t// @[ALU.scala:83:7, :85:20, :86:28]\n wire [63:0] in1_and_in2 = io_in1_0 & in2_inv;\t// @[ALU.scala:83:7, :85:20, :87:28]\n wire [64:0] _io_adder_out_T = {1'h0, io_in1_0} + {1'h0, in2_inv};\t// @[ALU.scala:83:7, :85:20, :88:26]\n wire [63:0] _io_adder_out_T_1 = _io_adder_out_T[63:0];\t// @[ALU.scala:88:26]\n wire [64:0] _io_adder_out_T_3 = {1'h0, _io_adder_out_T_1} + {64'h0, _io_adder_out_T_2};\t// @[ALU.scala:58:29, :88:{26,36}]\n assign _io_adder_out_T_4 = _io_adder_out_T_3[63:0];\t// @[ALU.scala:88:36]\n assign io_adder_out_0 = _io_adder_out_T_4;\t// @[ALU.scala:83:7, :88:36]\n wire _slt_T = io_in1_0[63];\t// @[ALU.scala:83:7, :92:15]\n wire _slt_T_6 = io_in1_0[63];\t// @[ALU.scala:83:7, :92:15, :93:51]\n wire _slt_T_1 = io_in2_0[63];\t// @[ALU.scala:83:7, :92:34]\n wire _slt_T_5 = io_in2_0[63];\t// @[ALU.scala:83:7, :92:34, :93:35]\n wire _slt_T_2 = _slt_T == _slt_T_1;\t// @[ALU.scala:92:{15,24,34}]\n wire _slt_T_3 = io_adder_out_0[63];\t// @[ALU.scala:83:7, :92:56]\n wire _slt_T_4 = io_fn_0[1];\t// @[ALU.scala:61:35, :83:7]\n wire _slt_T_7 = _slt_T_4 ? _slt_T_5 : _slt_T_6;\t// @[ALU.scala:61:35, :93:{8,35,51}]\n wire slt = _slt_T_2 ? _slt_T_3 : _slt_T_7;\t// @[ALU.scala:92:{8,24,56}, :93:8]\n wire _io_cmp_out_T = io_fn_0[0];\t// @[ALU.scala:62:35, :83:7]\n wire _rotin_T = io_fn_0[0];\t// @[ALU.scala:62:35, :83:7, :156:24]\n wire _rotout_T = io_fn_0[0];\t// @[ALU.scala:62:35, :83:7, :159:25]\n wire _rotout_T_2 = io_fn_0[0];\t// @[ALU.scala:62:35, :83:7, :159:61]\n wire _io_cmp_out_T_2 = ~_io_cmp_out_T_1;\t// @[ALU.scala:63:{26,30}]\n wire _io_cmp_out_T_3 = in1_xor_in2 == 64'h0;\t// @[ALU.scala:86:28, :94:68]\n wire _io_cmp_out_T_4 = _io_cmp_out_T_2 ? _io_cmp_out_T_3 : slt;\t// @[ALU.scala:63:26, :92:8, :94:{41,68}]\n assign _io_cmp_out_T_5 = _io_cmp_out_T ^ _io_cmp_out_T_4;\t// @[ALU.scala:62:35, :94:{36,41}]\n assign io_cmp_out_0 = _io_cmp_out_T_5;\t// @[ALU.scala:83:7, :94:36]\n wire _shin_hi_32_T_1 = io_in1_0[31];\t// @[ALU.scala:83:7, :101:55]\n wire _shin_hi_32_T_2 = _shin_hi_32_T & _shin_hi_32_T_1;\t// @[ALU.scala:58:29, :101:{46,55}]\n wire [31:0] shin_hi_32 = {32{_shin_hi_32_T_2}};\t// @[ALU.scala:101:{28,46}]\n wire [31:0] _shin_hi_T_1 = io_in1_0[63:32];\t// @[ALU.scala:83:7, :102:48]\n wire [31:0] _tz_in_T_6 = io_in1_0[63:32];\t// @[ALU.scala:83:7, :102:48, :132:19]\n wire [31:0] shin_hi = _shin_hi_T ? _shin_hi_T_1 : shin_hi_32;\t// @[ALU.scala:101:28, :102:{24,31,48}]\n wire _shamt_T = io_in2_0[5];\t// @[ALU.scala:83:7, :103:29]\n wire _shamt_T_2 = _shamt_T & _shamt_T_1;\t// @[ALU.scala:103:{29,33,42}]\n wire [4:0] _shamt_T_3 = io_in2_0[4:0];\t// @[ALU.scala:83:7, :103:60]\n wire [5:0] shamt = {_shamt_T_2, _shamt_T_3};\t// @[ALU.scala:103:{22,33,60}]\n wire [31:0] _tz_in_T_8 = io_in1_0[31:0];\t// @[ALU.scala:83:7, :104:34, :132:19]\n wire [31:0] _tz_in_T_63 = io_in1_0[31:0];\t// @[ALU.scala:83:7, :104:34, :133:25]\n wire [31:0] _tz_in_T_65 = io_in1_0[31:0];\t// @[ALU.scala:83:7, :104:34, :134:33]\n wire [31:0] _popc_in_T_2 = io_in1_0[31:0];\t// @[ALU.scala:83:7, :104:34, :137:32]\n wire [63:0] shin_r = {shin_hi, io_in1_0[31:0]};\t// @[ALU.scala:83:7, :102:24, :104:{18,34}]\n wire _GEN = io_fn_0 == 5'h5;\t// @[package.scala:16:47]\n wire _shin_T;\t// @[package.scala:16:47]\n assign _shin_T = _GEN;\t// @[package.scala:16:47]\n wire _shout_T;\t// @[ALU.scala:109:25]\n assign _shout_T = _GEN;\t// @[package.scala:16:47]\n wire _GEN_0 = io_fn_0 == 5'hB;\t// @[package.scala:16:47]\n wire _shin_T_1;\t// @[package.scala:16:47]\n assign _shin_T_1 = _GEN_0;\t// @[package.scala:16:47]\n wire _shout_T_1;\t// @[ALU.scala:109:44]\n assign _shout_T_1 = _GEN_0;\t// @[package.scala:16:47]\n wire _GEN_1 = io_fn_0 == 5'h12;\t// @[package.scala:16:47]\n wire _shin_T_2;\t// @[package.scala:16:47]\n assign _shin_T_2 = _GEN_1;\t// @[package.scala:16:47]\n wire _out_T_16;\t// @[ALU.scala:161:47]\n assign _out_T_16 = _GEN_1;\t// @[package.scala:16:47]\n wire _GEN_2 = io_fn_0 == 5'h13;\t// @[package.scala:16:47]\n wire _shin_T_3;\t// @[package.scala:16:47]\n assign _shin_T_3 = _GEN_2;\t// @[package.scala:16:47]\n wire _shout_T_3;\t// @[ALU.scala:109:64]\n assign _shout_T_3 = _GEN_2;\t// @[package.scala:16:47]\n wire _bext_mask_T;\t// @[ALU.scala:122:52]\n assign _bext_mask_T = _GEN_2;\t// @[package.scala:16:47]\n wire _shin_T_4 = _shin_T | _shin_T_1;\t// @[package.scala:16:47, :81:59]\n wire _shin_T_5 = _shin_T_4 | _shin_T_2;\t// @[package.scala:16:47, :81:59]\n wire _shin_T_6 = _shin_T_5 | _shin_T_3;\t// @[package.scala:16:47, :81:59]\n wire _shin_T_7 = ~_shin_T_6;\t// @[package.scala:81:59]\n wire [31:0] _shin_T_10 = shin_r[63:32];\t// @[ALU.scala:104:18, :106:46]\n wire [31:0] _rotin_T_3 = shin_r[63:32];\t// @[ALU.scala:104:18, :106:46, :156:44]\n wire [63:0] _shin_T_11 = {32'h0, _shin_T_10};\t// @[ALU.scala:106:46]\n wire [31:0] _shin_T_12 = shin_r[31:0];\t// @[ALU.scala:104:18, :106:46]\n wire [31:0] _rotin_T_5 = shin_r[31:0];\t// @[ALU.scala:104:18, :106:46, :156:44]\n wire [63:0] _shin_T_13 = {_shin_T_12, 32'h0};\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_15 = _shin_T_13 & 64'hFFFFFFFF00000000;\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_16 = _shin_T_11 | _shin_T_15;\t// @[ALU.scala:106:46]\n wire [47:0] _shin_T_20 = _shin_T_16[63:16];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_21 = {16'h0, _shin_T_20 & 48'hFFFF0000FFFF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _shin_T_22 = _shin_T_16[47:0];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_23 = {_shin_T_22, 16'h0};\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_25 = _shin_T_23 & 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_26 = _shin_T_21 | _shin_T_25;\t// @[ALU.scala:106:46]\n wire [55:0] _shin_T_30 = _shin_T_26[63:8];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_31 = {8'h0, _shin_T_30 & 56'hFF00FF00FF00FF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _shin_T_32 = _shin_T_26[55:0];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_33 = {_shin_T_32, 8'h0};\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_35 = _shin_T_33 & 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_36 = _shin_T_31 | _shin_T_35;\t// @[ALU.scala:106:46]\n wire [59:0] _shin_T_40 = _shin_T_36[63:4];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_41 = {4'h0, _shin_T_40 & 60'hF0F0F0F0F0F0F0F};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _shin_T_42 = _shin_T_36[59:0];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_43 = {_shin_T_42, 4'h0};\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_45 = _shin_T_43 & 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_46 = _shin_T_41 | _shin_T_45;\t// @[ALU.scala:106:46]\n wire [61:0] _shin_T_50 = _shin_T_46[63:2];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_51 = {2'h0, _shin_T_50 & 62'h3333333333333333};\t// @[package.scala:16:47]\n wire [61:0] _shin_T_52 = _shin_T_46[61:0];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_53 = {_shin_T_52, 2'h0};\t// @[package.scala:16:47]\n wire [63:0] _shin_T_55 = _shin_T_53 & 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_56 = _shin_T_51 | _shin_T_55;\t// @[ALU.scala:106:46]\n wire [62:0] _shin_T_60 = _shin_T_56[63:1];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_61 = {1'h0, _shin_T_60 & 63'h5555555555555555};\t// @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _shin_T_62 = _shin_T_56[62:0];\t// @[ALU.scala:106:46]\n wire [63:0] _shin_T_63 = {_shin_T_62, 1'h0};\t// @[ALU.scala:88:26, :106:46]\n wire [63:0] _shin_T_65 = _shin_T_63 & 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shin_T_66 = _shin_T_61 | _shin_T_65;\t// @[ALU.scala:106:46]\n wire [63:0] shin = _shin_T_7 ? _shin_T_66 : shin_r;\t// @[ALU.scala:64:33, :104:18, :106:{17,46}]\n wire _shout_r_T_1 = shin[63];\t// @[ALU.scala:106:17, :107:41]\n wire _shout_r_T_2 = _shout_r_T & _shout_r_T_1;\t// @[ALU.scala:58:29, :107:{35,41}]\n wire [64:0] _shout_r_T_3 = {_shout_r_T_2, shin};\t// @[ALU.scala:106:17, :107:{21,35}]\n wire [64:0] _shout_r_T_4 = _shout_r_T_3;\t// @[ALU.scala:107:{21,57}]\n wire [64:0] _shout_r_T_5 = $signed($signed(_shout_r_T_4) >>> shamt);\t// @[ALU.scala:103:22, :107:{57,64}]\n wire [63:0] shout_r = _shout_r_T_5[63:0];\t// @[ALU.scala:107:{64,73}]\n wire [31:0] _shout_l_T_2 = shout_r[63:32];\t// @[ALU.scala:107:73, :108:24]\n wire [63:0] _shout_l_T_3 = {32'h0, _shout_l_T_2};\t// @[ALU.scala:108:24]\n wire [31:0] _shout_l_T_4 = shout_r[31:0];\t// @[ALU.scala:107:73, :108:24]\n wire [63:0] _shout_l_T_5 = {_shout_l_T_4, 32'h0};\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_7 = _shout_l_T_5 & 64'hFFFFFFFF00000000;\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_8 = _shout_l_T_3 | _shout_l_T_7;\t// @[ALU.scala:108:24]\n wire [47:0] _shout_l_T_12 = _shout_l_T_8[63:16];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_13 = {16'h0, _shout_l_T_12 & 48'hFFFF0000FFFF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _shout_l_T_14 = _shout_l_T_8[47:0];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_15 = {_shout_l_T_14, 16'h0};\t// @[ALU.scala:106:46, :108:24]\n wire [63:0] _shout_l_T_17 = _shout_l_T_15 & 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_18 = _shout_l_T_13 | _shout_l_T_17;\t// @[ALU.scala:108:24]\n wire [55:0] _shout_l_T_22 = _shout_l_T_18[63:8];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_23 = {8'h0, _shout_l_T_22 & 56'hFF00FF00FF00FF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _shout_l_T_24 = _shout_l_T_18[55:0];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_25 = {_shout_l_T_24, 8'h0};\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_27 = _shout_l_T_25 & 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_28 = _shout_l_T_23 | _shout_l_T_27;\t// @[ALU.scala:108:24]\n wire [59:0] _shout_l_T_32 = _shout_l_T_28[63:4];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_33 = {4'h0, _shout_l_T_32 & 60'hF0F0F0F0F0F0F0F};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _shout_l_T_34 = _shout_l_T_28[59:0];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_35 = {_shout_l_T_34, 4'h0};\t// @[ALU.scala:106:46, :108:24]\n wire [63:0] _shout_l_T_37 = _shout_l_T_35 & 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_38 = _shout_l_T_33 | _shout_l_T_37;\t// @[ALU.scala:108:24]\n wire [61:0] _shout_l_T_42 = _shout_l_T_38[63:2];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_43 = {2'h0, _shout_l_T_42 & 62'h3333333333333333};\t// @[package.scala:16:47]\n wire [61:0] _shout_l_T_44 = _shout_l_T_38[61:0];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_45 = {_shout_l_T_44, 2'h0};\t// @[package.scala:16:47]\n wire [63:0] _shout_l_T_47 = _shout_l_T_45 & 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _shout_l_T_48 = _shout_l_T_43 | _shout_l_T_47;\t// @[ALU.scala:108:24]\n wire [62:0] _shout_l_T_52 = _shout_l_T_48[63:1];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_53 = {1'h0, _shout_l_T_52 & 63'h5555555555555555};\t// @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _shout_l_T_54 = _shout_l_T_48[62:0];\t// @[ALU.scala:108:24]\n wire [63:0] _shout_l_T_55 = {_shout_l_T_54, 1'h0};\t// @[ALU.scala:88:26, :108:24]\n wire [63:0] _shout_l_T_57 = _shout_l_T_55 & 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] shout_l = _shout_l_T_53 | _shout_l_T_57;\t// @[ALU.scala:108:24]\n wire _shout_T_2 = _shout_T | _shout_T_1;\t// @[ALU.scala:109:{25,35,44}]\n wire _shout_T_4 = _shout_T_2 | _shout_T_3;\t// @[ALU.scala:109:{35,55,64}]\n wire [63:0] _shout_T_5 = _shout_T_4 ? shout_r : 64'h0;\t// @[ALU.scala:107:73, :109:{18,55}]\n wire _shout_T_6 = io_fn_0 == 5'h1;\t// @[ALU.scala:83:7, :110:25]\n wire [63:0] _shout_T_7 = _shout_T_6 ? shout_l : 64'h0;\t// @[ALU.scala:108:24, :110:{18,25}]\n wire [63:0] shout = _shout_T_5 | _shout_T_7;\t// @[ALU.scala:109:{18,91}, :110:18]\n wire in2_not_zero = |io_in2_0;\t// @[ALU.scala:83:7, :113:29]\n wire _logic_T = io_fn_0 == 5'h4;\t// @[ALU.scala:83:7, :119:25]\n wire _GEN_3 = io_fn_0 == 5'h6;\t// @[ALU.scala:83:7, :119:45]\n wire _logic_T_1;\t// @[ALU.scala:119:45]\n assign _logic_T_1 = _GEN_3;\t// @[ALU.scala:119:45]\n wire _logic_T_8;\t// @[ALU.scala:120:25]\n assign _logic_T_8 = _GEN_3;\t// @[ALU.scala:119:45, :120:25]\n wire _logic_T_2 = _logic_T | _logic_T_1;\t// @[ALU.scala:119:{25,36,45}]\n wire _GEN_4 = io_fn_0 == 5'h19;\t// @[ALU.scala:83:7, :119:64]\n wire _logic_T_3;\t// @[ALU.scala:119:64]\n assign _logic_T_3 = _GEN_4;\t// @[ALU.scala:119:64]\n wire _logic_T_11;\t// @[ALU.scala:120:64]\n assign _logic_T_11 = _GEN_4;\t// @[ALU.scala:119:64, :120:64]\n wire _logic_T_4 = _logic_T_2 | _logic_T_3;\t// @[ALU.scala:119:{36,55,64}]\n wire _logic_T_5 = io_fn_0 == 5'h1A;\t// @[ALU.scala:83:7, :119:84]\n wire _logic_T_6 = _logic_T_4 | _logic_T_5;\t// @[ALU.scala:119:{55,75,84}]\n wire [63:0] _logic_T_7 = _logic_T_6 ? in1_xor_in2 : 64'h0;\t// @[ALU.scala:86:28, :119:{18,75}]\n wire _logic_T_9 = io_fn_0 == 5'h7;\t// @[ALU.scala:83:7, :120:44]\n wire _logic_T_10 = _logic_T_8 | _logic_T_9;\t// @[ALU.scala:120:{25,35,44}]\n wire _logic_T_12 = _logic_T_10 | _logic_T_11;\t// @[ALU.scala:120:{35,55,64}]\n wire _logic_T_13 = io_fn_0 == 5'h18;\t// @[ALU.scala:83:7, :120:84]\n wire _logic_T_14 = _logic_T_12 | _logic_T_13;\t// @[ALU.scala:120:{55,75,84}]\n wire [63:0] _logic_T_15 = _logic_T_14 ? in1_and_in2 : 64'h0;\t// @[ALU.scala:87:28, :120:{18,75}]\n wire [63:0] logic_0 = _logic_T_7 | _logic_T_15;\t// @[ALU.scala:119:{18,115}, :120:18]\n wire _bext_mask_T_1 = _bext_mask_T;\t// @[ALU.scala:122:{43,52}]\n wire [63:0] bext_mask = _bext_mask_T_1 ? 64'h1 : 64'hFFFFFFFFFFFFFFFF;\t// @[ALU.scala:122:{22,43}]\n wire _shift_logic_T = io_fn_0 > 5'hB;\t// @[ALU.scala:59:31, :83:7]\n wire _shift_logic_T_1 = ~(io_fn_0[4]);\t// @[ALU.scala:59:48, :83:7]\n wire _shift_logic_T_2 = _shift_logic_T & _shift_logic_T_1;\t// @[ALU.scala:59:{31,41,48}]\n wire _shift_logic_T_3 = _shift_logic_T_2 & slt;\t// @[ALU.scala:59:41, :92:8, :123:36]\n wire [63:0] _shift_logic_T_4 = {63'h0, _shift_logic_T_3} | logic_0;\t// @[ALU.scala:119:115, :123:{36,44}]\n wire [63:0] _shift_logic_T_5 = shout & bext_mask;\t// @[ALU.scala:109:91, :122:22, :123:61]\n wire [63:0] shift_logic = _shift_logic_T_4 | _shift_logic_T_5;\t// @[ALU.scala:123:{44,52,61}]\n wire _tz_in_T = ~io_dw_0;\t// @[ALU.scala:83:7, :130:32]\n wire _tz_in_T_1 = io_in2_0[0];\t// @[ALU.scala:83:7, :130:53]\n wire _tz_in_T_2 = ~_tz_in_T_1;\t// @[ALU.scala:130:{46,53}]\n wire [1:0] _tz_in_T_3 = {_tz_in_T, _tz_in_T_2};\t// @[ALU.scala:130:{32,43,46}]\n wire [63:0] _tz_in_T_7 = {32'h0, _tz_in_T_6};\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_9 = {_tz_in_T_8, 32'h0};\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_11 = _tz_in_T_9 & 64'hFFFFFFFF00000000;\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_12 = _tz_in_T_7 | _tz_in_T_11;\t// @[ALU.scala:132:19]\n wire [47:0] _tz_in_T_16 = _tz_in_T_12[63:16];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_17 = {16'h0, _tz_in_T_16 & 48'hFFFF0000FFFF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _tz_in_T_18 = _tz_in_T_12[47:0];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_19 = {_tz_in_T_18, 16'h0};\t// @[ALU.scala:106:46, :132:19]\n wire [63:0] _tz_in_T_21 = _tz_in_T_19 & 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_22 = _tz_in_T_17 | _tz_in_T_21;\t// @[ALU.scala:132:19]\n wire [55:0] _tz_in_T_26 = _tz_in_T_22[63:8];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_27 = {8'h0, _tz_in_T_26 & 56'hFF00FF00FF00FF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _tz_in_T_28 = _tz_in_T_22[55:0];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_29 = {_tz_in_T_28, 8'h0};\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_31 = _tz_in_T_29 & 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_32 = _tz_in_T_27 | _tz_in_T_31;\t// @[ALU.scala:132:19]\n wire [59:0] _tz_in_T_36 = _tz_in_T_32[63:4];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_37 = {4'h0, _tz_in_T_36 & 60'hF0F0F0F0F0F0F0F};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _tz_in_T_38 = _tz_in_T_32[59:0];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_39 = {_tz_in_T_38, 4'h0};\t// @[ALU.scala:106:46, :132:19]\n wire [63:0] _tz_in_T_41 = _tz_in_T_39 & 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_42 = _tz_in_T_37 | _tz_in_T_41;\t// @[ALU.scala:132:19]\n wire [61:0] _tz_in_T_46 = _tz_in_T_42[63:2];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_47 = {2'h0, _tz_in_T_46 & 62'h3333333333333333};\t// @[package.scala:16:47]\n wire [61:0] _tz_in_T_48 = _tz_in_T_42[61:0];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_49 = {_tz_in_T_48, 2'h0};\t// @[package.scala:16:47]\n wire [63:0] _tz_in_T_51 = _tz_in_T_49 & 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_52 = _tz_in_T_47 | _tz_in_T_51;\t// @[ALU.scala:132:19]\n wire [62:0] _tz_in_T_56 = _tz_in_T_52[63:1];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_57 = {1'h0, _tz_in_T_56 & 63'h5555555555555555};\t// @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _tz_in_T_58 = _tz_in_T_52[62:0];\t// @[ALU.scala:132:19]\n wire [63:0] _tz_in_T_59 = {_tz_in_T_58, 1'h0};\t// @[ALU.scala:88:26, :132:19]\n wire [63:0] _tz_in_T_61 = _tz_in_T_59 & 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _tz_in_T_62 = _tz_in_T_57 | _tz_in_T_61;\t// @[ALU.scala:132:19]\n wire [32:0] _tz_in_T_64 = {1'h1, _tz_in_T_63};\t// @[ALU.scala:133:{16,25}]\n wire [15:0] _tz_in_T_68 = _tz_in_T_65[31:16];\t// @[ALU.scala:134:{26,33}]\n wire [31:0] _tz_in_T_69 = {16'h0, _tz_in_T_68};\t// @[ALU.scala:106:46, :134:26]\n wire [15:0] _tz_in_T_70 = _tz_in_T_65[15:0];\t// @[ALU.scala:134:{26,33}]\n wire [31:0] _tz_in_T_71 = {_tz_in_T_70, 16'h0};\t// @[ALU.scala:106:46, :134:26]\n wire [31:0] _tz_in_T_73 = _tz_in_T_71 & 32'hFFFF0000;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_74 = _tz_in_T_69 | _tz_in_T_73;\t// @[ALU.scala:134:26]\n wire [23:0] _tz_in_T_78 = _tz_in_T_74[31:8];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_79 = {8'h0, _tz_in_T_78 & 24'hFF00FF};\t// @[ALU.scala:134:26]\n wire [23:0] _tz_in_T_80 = _tz_in_T_74[23:0];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_81 = {_tz_in_T_80, 8'h0};\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_83 = _tz_in_T_81 & 32'hFF00FF00;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_84 = _tz_in_T_79 | _tz_in_T_83;\t// @[ALU.scala:134:26]\n wire [27:0] _tz_in_T_88 = _tz_in_T_84[31:4];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_89 = {4'h0, _tz_in_T_88 & 28'hF0F0F0F};\t// @[ALU.scala:106:46, :134:26]\n wire [27:0] _tz_in_T_90 = _tz_in_T_84[27:0];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_91 = {_tz_in_T_90, 4'h0};\t// @[ALU.scala:106:46, :134:26]\n wire [31:0] _tz_in_T_93 = _tz_in_T_91 & 32'hF0F0F0F0;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_94 = _tz_in_T_89 | _tz_in_T_93;\t// @[ALU.scala:134:26]\n wire [29:0] _tz_in_T_98 = _tz_in_T_94[31:2];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_99 = {2'h0, _tz_in_T_98 & 30'h33333333};\t// @[package.scala:16:47]\n wire [29:0] _tz_in_T_100 = _tz_in_T_94[29:0];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_101 = {_tz_in_T_100, 2'h0};\t// @[package.scala:16:47]\n wire [31:0] _tz_in_T_103 = _tz_in_T_101 & 32'hCCCCCCCC;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_104 = _tz_in_T_99 | _tz_in_T_103;\t// @[ALU.scala:134:26]\n wire [30:0] _tz_in_T_108 = _tz_in_T_104[31:1];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_109 = {1'h0, _tz_in_T_108 & 31'h55555555};\t// @[ALU.scala:88:26, :134:26]\n wire [30:0] _tz_in_T_110 = _tz_in_T_104[30:0];\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_111 = {_tz_in_T_110, 1'h0};\t// @[ALU.scala:88:26, :134:26]\n wire [31:0] _tz_in_T_113 = _tz_in_T_111 & 32'hAAAAAAAA;\t// @[ALU.scala:134:26]\n wire [31:0] _tz_in_T_114 = _tz_in_T_109 | _tz_in_T_113;\t// @[ALU.scala:134:26]\n wire [32:0] _tz_in_T_115 = {1'h1, _tz_in_T_114};\t// @[ALU.scala:134:{16,26}]\n wire _tz_in_T_116 = _tz_in_T_3 == 2'h1;\t// @[ALU.scala:130:{43,62}]\n wire [63:0] _tz_in_T_117 = _tz_in_T_116 ? _tz_in_T_62 : io_in1_0;\t// @[ALU.scala:83:7, :130:62, :132:19]\n wire _tz_in_T_118 = _tz_in_T_3 == 2'h2;\t// @[ALU.scala:130:{43,62}]\n wire [63:0] _tz_in_T_119 = _tz_in_T_118 ? {31'h0, _tz_in_T_64} : _tz_in_T_117;\t// @[ALU.scala:130:62, :133:16]\n wire _tz_in_T_120 = &_tz_in_T_3;\t// @[ALU.scala:130:{43,62}]\n wire [63:0] tz_in = _tz_in_T_120 ? {31'h0, _tz_in_T_115} : _tz_in_T_119;\t// @[ALU.scala:130:62, :134:16]\n wire _popc_in_T = io_in2_0[1];\t// @[ALU.scala:83:7, :136:27]\n wire _popc_in_T_1 = ~io_dw_0;\t// @[ALU.scala:83:7, :130:32, :137:15]\n wire [63:0] _popc_in_T_3 = _popc_in_T_1 ? {32'h0, _popc_in_T_2} : io_in1_0;\t// @[ALU.scala:83:7, :137:{8,15,32}]\n wire [64:0] _popc_in_T_4 = {1'h1, tz_in};\t// @[ALU.scala:130:62, :138:27]\n wire _popc_in_T_5 = _popc_in_T_4[0];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_6 = _popc_in_T_4[1];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_7 = _popc_in_T_4[2];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_8 = _popc_in_T_4[3];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_9 = _popc_in_T_4[4];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_10 = _popc_in_T_4[5];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_11 = _popc_in_T_4[6];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_12 = _popc_in_T_4[7];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_13 = _popc_in_T_4[8];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_14 = _popc_in_T_4[9];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_15 = _popc_in_T_4[10];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_16 = _popc_in_T_4[11];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_17 = _popc_in_T_4[12];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_18 = _popc_in_T_4[13];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_19 = _popc_in_T_4[14];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_20 = _popc_in_T_4[15];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_21 = _popc_in_T_4[16];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_22 = _popc_in_T_4[17];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_23 = _popc_in_T_4[18];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_24 = _popc_in_T_4[19];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_25 = _popc_in_T_4[20];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_26 = _popc_in_T_4[21];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_27 = _popc_in_T_4[22];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_28 = _popc_in_T_4[23];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_29 = _popc_in_T_4[24];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_30 = _popc_in_T_4[25];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_31 = _popc_in_T_4[26];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_32 = _popc_in_T_4[27];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_33 = _popc_in_T_4[28];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_34 = _popc_in_T_4[29];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_35 = _popc_in_T_4[30];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_36 = _popc_in_T_4[31];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_37 = _popc_in_T_4[32];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_38 = _popc_in_T_4[33];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_39 = _popc_in_T_4[34];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_40 = _popc_in_T_4[35];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_41 = _popc_in_T_4[36];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_42 = _popc_in_T_4[37];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_43 = _popc_in_T_4[38];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_44 = _popc_in_T_4[39];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_45 = _popc_in_T_4[40];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_46 = _popc_in_T_4[41];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_47 = _popc_in_T_4[42];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_48 = _popc_in_T_4[43];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_49 = _popc_in_T_4[44];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_50 = _popc_in_T_4[45];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_51 = _popc_in_T_4[46];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_52 = _popc_in_T_4[47];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_53 = _popc_in_T_4[48];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_54 = _popc_in_T_4[49];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_55 = _popc_in_T_4[50];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_56 = _popc_in_T_4[51];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_57 = _popc_in_T_4[52];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_58 = _popc_in_T_4[53];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_59 = _popc_in_T_4[54];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_60 = _popc_in_T_4[55];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_61 = _popc_in_T_4[56];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_62 = _popc_in_T_4[57];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_63 = _popc_in_T_4[58];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_64 = _popc_in_T_4[59];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_65 = _popc_in_T_4[60];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_66 = _popc_in_T_4[61];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_67 = _popc_in_T_4[62];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_68 = _popc_in_T_4[63];\t// @[OneHot.scala:85:71]\n wire _popc_in_T_69 = _popc_in_T_4[64];\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_70 = {_popc_in_T_69, 64'h0};\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_71 = _popc_in_T_68 ? 65'h8000000000000000 : _popc_in_T_70;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_72 = _popc_in_T_67 ? 65'h4000000000000000 : _popc_in_T_71;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_73 = _popc_in_T_66 ? 65'h2000000000000000 : _popc_in_T_72;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_74 = _popc_in_T_65 ? 65'h1000000000000000 : _popc_in_T_73;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_75 = _popc_in_T_64 ? 65'h800000000000000 : _popc_in_T_74;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_76 = _popc_in_T_63 ? 65'h400000000000000 : _popc_in_T_75;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_77 = _popc_in_T_62 ? 65'h200000000000000 : _popc_in_T_76;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_78 = _popc_in_T_61 ? 65'h100000000000000 : _popc_in_T_77;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_79 = _popc_in_T_60 ? 65'h80000000000000 : _popc_in_T_78;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_80 = _popc_in_T_59 ? 65'h40000000000000 : _popc_in_T_79;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_81 = _popc_in_T_58 ? 65'h20000000000000 : _popc_in_T_80;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_82 = _popc_in_T_57 ? 65'h10000000000000 : _popc_in_T_81;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_83 = _popc_in_T_56 ? 65'h8000000000000 : _popc_in_T_82;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_84 = _popc_in_T_55 ? 65'h4000000000000 : _popc_in_T_83;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_85 = _popc_in_T_54 ? 65'h2000000000000 : _popc_in_T_84;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_86 = _popc_in_T_53 ? 65'h1000000000000 : _popc_in_T_85;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_87 = _popc_in_T_52 ? 65'h800000000000 : _popc_in_T_86;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_88 = _popc_in_T_51 ? 65'h400000000000 : _popc_in_T_87;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_89 = _popc_in_T_50 ? 65'h200000000000 : _popc_in_T_88;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_90 = _popc_in_T_49 ? 65'h100000000000 : _popc_in_T_89;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_91 = _popc_in_T_48 ? 65'h80000000000 : _popc_in_T_90;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_92 = _popc_in_T_47 ? 65'h40000000000 : _popc_in_T_91;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_93 = _popc_in_T_46 ? 65'h20000000000 : _popc_in_T_92;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_94 = _popc_in_T_45 ? 65'h10000000000 : _popc_in_T_93;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_95 = _popc_in_T_44 ? 65'h8000000000 : _popc_in_T_94;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_96 = _popc_in_T_43 ? 65'h4000000000 : _popc_in_T_95;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_97 = _popc_in_T_42 ? 65'h2000000000 : _popc_in_T_96;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_98 = _popc_in_T_41 ? 65'h1000000000 : _popc_in_T_97;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_99 = _popc_in_T_40 ? 65'h800000000 : _popc_in_T_98;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_100 = _popc_in_T_39 ? 65'h400000000 : _popc_in_T_99;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_101 = _popc_in_T_38 ? 65'h200000000 : _popc_in_T_100;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_102 = _popc_in_T_37 ? 65'h100000000 : _popc_in_T_101;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_103 = _popc_in_T_36 ? 65'h80000000 : _popc_in_T_102;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_104 = _popc_in_T_35 ? 65'h40000000 : _popc_in_T_103;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_105 = _popc_in_T_34 ? 65'h20000000 : _popc_in_T_104;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_106 = _popc_in_T_33 ? 65'h10000000 : _popc_in_T_105;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_107 = _popc_in_T_32 ? 65'h8000000 : _popc_in_T_106;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_108 = _popc_in_T_31 ? 65'h4000000 : _popc_in_T_107;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_109 = _popc_in_T_30 ? 65'h2000000 : _popc_in_T_108;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_110 = _popc_in_T_29 ? 65'h1000000 : _popc_in_T_109;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_111 = _popc_in_T_28 ? 65'h800000 : _popc_in_T_110;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_112 = _popc_in_T_27 ? 65'h400000 : _popc_in_T_111;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_113 = _popc_in_T_26 ? 65'h200000 : _popc_in_T_112;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_114 = _popc_in_T_25 ? 65'h100000 : _popc_in_T_113;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_115 = _popc_in_T_24 ? 65'h80000 : _popc_in_T_114;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_116 = _popc_in_T_23 ? 65'h40000 : _popc_in_T_115;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_117 = _popc_in_T_22 ? 65'h20000 : _popc_in_T_116;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_118 = _popc_in_T_21 ? 65'h10000 : _popc_in_T_117;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_119 = _popc_in_T_20 ? 65'h8000 : _popc_in_T_118;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_120 = _popc_in_T_19 ? 65'h4000 : _popc_in_T_119;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_121 = _popc_in_T_18 ? 65'h2000 : _popc_in_T_120;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_122 = _popc_in_T_17 ? 65'h1000 : _popc_in_T_121;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_123 = _popc_in_T_16 ? 65'h800 : _popc_in_T_122;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_124 = _popc_in_T_15 ? 65'h400 : _popc_in_T_123;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_125 = _popc_in_T_14 ? 65'h200 : _popc_in_T_124;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_126 = _popc_in_T_13 ? 65'h100 : _popc_in_T_125;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_127 = _popc_in_T_12 ? 65'h80 : _popc_in_T_126;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_128 = _popc_in_T_11 ? 65'h40 : _popc_in_T_127;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_129 = _popc_in_T_10 ? 65'h20 : _popc_in_T_128;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_130 = _popc_in_T_9 ? 65'h10 : _popc_in_T_129;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_131 = _popc_in_T_8 ? 65'h8 : _popc_in_T_130;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_132 = _popc_in_T_7 ? 65'h4 : _popc_in_T_131;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_133 = _popc_in_T_6 ? 65'h2 : _popc_in_T_132;\t// @[OneHot.scala:85:71]\n wire [64:0] _popc_in_T_134 = _popc_in_T_5 ? 65'h1 : _popc_in_T_133;\t// @[OneHot.scala:85:71]\n wire [65:0] _popc_in_T_135 = {1'h0, _popc_in_T_134} - 66'h1;\t// @[Mux.scala:50:70]\n wire [64:0] _popc_in_T_136 = _popc_in_T_135[64:0];\t// @[ALU.scala:138:37]\n wire [64:0] _popc_in_T_137 = _popc_in_T ? {1'h0, _popc_in_T_3} : _popc_in_T_136;\t// @[ALU.scala:88:26, :136:{20,27}, :137:8, :138:37]\n wire [63:0] popc_in = _popc_in_T_137[63:0];\t// @[ALU.scala:136:20, :138:43]\n wire _count_T = popc_in[0];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_1 = popc_in[1];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_2 = popc_in[2];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_3 = popc_in[3];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_4 = popc_in[4];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_5 = popc_in[5];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_6 = popc_in[6];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_7 = popc_in[7];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_8 = popc_in[8];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_9 = popc_in[9];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_10 = popc_in[10];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_11 = popc_in[11];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_12 = popc_in[12];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_13 = popc_in[13];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_14 = popc_in[14];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_15 = popc_in[15];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_16 = popc_in[16];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_17 = popc_in[17];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_18 = popc_in[18];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_19 = popc_in[19];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_20 = popc_in[20];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_21 = popc_in[21];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_22 = popc_in[22];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_23 = popc_in[23];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_24 = popc_in[24];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_25 = popc_in[25];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_26 = popc_in[26];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_27 = popc_in[27];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_28 = popc_in[28];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_29 = popc_in[29];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_30 = popc_in[30];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_31 = popc_in[31];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_32 = popc_in[32];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_33 = popc_in[33];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_34 = popc_in[34];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_35 = popc_in[35];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_36 = popc_in[36];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_37 = popc_in[37];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_38 = popc_in[38];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_39 = popc_in[39];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_40 = popc_in[40];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_41 = popc_in[41];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_42 = popc_in[42];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_43 = popc_in[43];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_44 = popc_in[44];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_45 = popc_in[45];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_46 = popc_in[46];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_47 = popc_in[47];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_48 = popc_in[48];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_49 = popc_in[49];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_50 = popc_in[50];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_51 = popc_in[51];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_52 = popc_in[52];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_53 = popc_in[53];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_54 = popc_in[54];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_55 = popc_in[55];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_56 = popc_in[56];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_57 = popc_in[57];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_58 = popc_in[58];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_59 = popc_in[59];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_60 = popc_in[60];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_61 = popc_in[61];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_62 = popc_in[62];\t// @[ALU.scala:138:43, :139:23]\n wire _count_T_63 = popc_in[63];\t// @[ALU.scala:138:43, :139:23]\n wire [1:0] _count_T_64 = {1'h0, _count_T} + {1'h0, _count_T_1};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_65 = _count_T_64;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_66 = {1'h0, _count_T_2} + {1'h0, _count_T_3};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_67 = _count_T_66;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_68 = {1'h0, _count_T_65} + {1'h0, _count_T_67};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_69 = _count_T_68;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_70 = {1'h0, _count_T_4} + {1'h0, _count_T_5};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_71 = _count_T_70;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_72 = {1'h0, _count_T_6} + {1'h0, _count_T_7};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_73 = _count_T_72;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_74 = {1'h0, _count_T_71} + {1'h0, _count_T_73};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_75 = _count_T_74;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_76 = {1'h0, _count_T_69} + {1'h0, _count_T_75};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_77 = _count_T_76;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_78 = {1'h0, _count_T_8} + {1'h0, _count_T_9};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_79 = _count_T_78;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_80 = {1'h0, _count_T_10} + {1'h0, _count_T_11};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_81 = _count_T_80;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_82 = {1'h0, _count_T_79} + {1'h0, _count_T_81};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_83 = _count_T_82;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_84 = {1'h0, _count_T_12} + {1'h0, _count_T_13};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_85 = _count_T_84;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_86 = {1'h0, _count_T_14} + {1'h0, _count_T_15};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_87 = _count_T_86;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_88 = {1'h0, _count_T_85} + {1'h0, _count_T_87};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_89 = _count_T_88;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_90 = {1'h0, _count_T_83} + {1'h0, _count_T_89};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_91 = _count_T_90;\t// @[ALU.scala:139:23]\n wire [4:0] _count_T_92 = {1'h0, _count_T_77} + {1'h0, _count_T_91};\t// @[ALU.scala:88:26, :139:23]\n wire [4:0] _count_T_93 = _count_T_92;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_94 = {1'h0, _count_T_16} + {1'h0, _count_T_17};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_95 = _count_T_94;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_96 = {1'h0, _count_T_18} + {1'h0, _count_T_19};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_97 = _count_T_96;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_98 = {1'h0, _count_T_95} + {1'h0, _count_T_97};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_99 = _count_T_98;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_100 = {1'h0, _count_T_20} + {1'h0, _count_T_21};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_101 = _count_T_100;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_102 = {1'h0, _count_T_22} + {1'h0, _count_T_23};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_103 = _count_T_102;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_104 = {1'h0, _count_T_101} + {1'h0, _count_T_103};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_105 = _count_T_104;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_106 = {1'h0, _count_T_99} + {1'h0, _count_T_105};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_107 = _count_T_106;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_108 = {1'h0, _count_T_24} + {1'h0, _count_T_25};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_109 = _count_T_108;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_110 = {1'h0, _count_T_26} + {1'h0, _count_T_27};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_111 = _count_T_110;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_112 = {1'h0, _count_T_109} + {1'h0, _count_T_111};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_113 = _count_T_112;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_114 = {1'h0, _count_T_28} + {1'h0, _count_T_29};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_115 = _count_T_114;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_116 = {1'h0, _count_T_30} + {1'h0, _count_T_31};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_117 = _count_T_116;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_118 = {1'h0, _count_T_115} + {1'h0, _count_T_117};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_119 = _count_T_118;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_120 = {1'h0, _count_T_113} + {1'h0, _count_T_119};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_121 = _count_T_120;\t// @[ALU.scala:139:23]\n wire [4:0] _count_T_122 = {1'h0, _count_T_107} + {1'h0, _count_T_121};\t// @[ALU.scala:88:26, :139:23]\n wire [4:0] _count_T_123 = _count_T_122;\t// @[ALU.scala:139:23]\n wire [5:0] _count_T_124 = {1'h0, _count_T_93} + {1'h0, _count_T_123};\t// @[ALU.scala:88:26, :139:23]\n wire [5:0] _count_T_125 = _count_T_124;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_126 = {1'h0, _count_T_32} + {1'h0, _count_T_33};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_127 = _count_T_126;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_128 = {1'h0, _count_T_34} + {1'h0, _count_T_35};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_129 = _count_T_128;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_130 = {1'h0, _count_T_127} + {1'h0, _count_T_129};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_131 = _count_T_130;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_132 = {1'h0, _count_T_36} + {1'h0, _count_T_37};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_133 = _count_T_132;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_134 = {1'h0, _count_T_38} + {1'h0, _count_T_39};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_135 = _count_T_134;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_136 = {1'h0, _count_T_133} + {1'h0, _count_T_135};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_137 = _count_T_136;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_138 = {1'h0, _count_T_131} + {1'h0, _count_T_137};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_139 = _count_T_138;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_140 = {1'h0, _count_T_40} + {1'h0, _count_T_41};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_141 = _count_T_140;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_142 = {1'h0, _count_T_42} + {1'h0, _count_T_43};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_143 = _count_T_142;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_144 = {1'h0, _count_T_141} + {1'h0, _count_T_143};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_145 = _count_T_144;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_146 = {1'h0, _count_T_44} + {1'h0, _count_T_45};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_147 = _count_T_146;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_148 = {1'h0, _count_T_46} + {1'h0, _count_T_47};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_149 = _count_T_148;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_150 = {1'h0, _count_T_147} + {1'h0, _count_T_149};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_151 = _count_T_150;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_152 = {1'h0, _count_T_145} + {1'h0, _count_T_151};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_153 = _count_T_152;\t// @[ALU.scala:139:23]\n wire [4:0] _count_T_154 = {1'h0, _count_T_139} + {1'h0, _count_T_153};\t// @[ALU.scala:88:26, :139:23]\n wire [4:0] _count_T_155 = _count_T_154;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_156 = {1'h0, _count_T_48} + {1'h0, _count_T_49};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_157 = _count_T_156;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_158 = {1'h0, _count_T_50} + {1'h0, _count_T_51};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_159 = _count_T_158;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_160 = {1'h0, _count_T_157} + {1'h0, _count_T_159};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_161 = _count_T_160;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_162 = {1'h0, _count_T_52} + {1'h0, _count_T_53};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_163 = _count_T_162;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_164 = {1'h0, _count_T_54} + {1'h0, _count_T_55};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_165 = _count_T_164;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_166 = {1'h0, _count_T_163} + {1'h0, _count_T_165};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_167 = _count_T_166;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_168 = {1'h0, _count_T_161} + {1'h0, _count_T_167};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_169 = _count_T_168;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_170 = {1'h0, _count_T_56} + {1'h0, _count_T_57};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_171 = _count_T_170;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_172 = {1'h0, _count_T_58} + {1'h0, _count_T_59};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_173 = _count_T_172;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_174 = {1'h0, _count_T_171} + {1'h0, _count_T_173};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_175 = _count_T_174;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_176 = {1'h0, _count_T_60} + {1'h0, _count_T_61};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_177 = _count_T_176;\t// @[ALU.scala:139:23]\n wire [1:0] _count_T_178 = {1'h0, _count_T_62} + {1'h0, _count_T_63};\t// @[ALU.scala:88:26, :139:23]\n wire [1:0] _count_T_179 = _count_T_178;\t// @[ALU.scala:139:23]\n wire [2:0] _count_T_180 = {1'h0, _count_T_177} + {1'h0, _count_T_179};\t// @[ALU.scala:88:26, :139:23]\n wire [2:0] _count_T_181 = _count_T_180;\t// @[ALU.scala:139:23]\n wire [3:0] _count_T_182 = {1'h0, _count_T_175} + {1'h0, _count_T_181};\t// @[ALU.scala:88:26, :139:23]\n wire [3:0] _count_T_183 = _count_T_182;\t// @[ALU.scala:139:23]\n wire [4:0] _count_T_184 = {1'h0, _count_T_169} + {1'h0, _count_T_183};\t// @[ALU.scala:88:26, :139:23]\n wire [4:0] _count_T_185 = _count_T_184;\t// @[ALU.scala:139:23]\n wire [5:0] _count_T_186 = {1'h0, _count_T_155} + {1'h0, _count_T_185};\t// @[ALU.scala:88:26, :139:23]\n wire [5:0] _count_T_187 = _count_T_186;\t// @[ALU.scala:139:23]\n wire [6:0] _count_T_188 = {1'h0, _count_T_125} + {1'h0, _count_T_187};\t// @[ALU.scala:88:26, :139:23]\n wire [6:0] count = _count_T_188;\t// @[ALU.scala:139:23]\n wire [7:0] _in1_bytes_T;\t// @[ALU.scala:140:34]\n wire [7:0] _in1_bytes_T_1;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_7 = in1_bytes_0;\t// @[ALU.scala:140:34, :142:21]\n wire [7:0] _in1_bytes_T_2;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_6 = in1_bytes_1;\t// @[ALU.scala:140:34, :142:21]\n wire [7:0] _in1_bytes_T_3;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_5 = in1_bytes_2;\t// @[ALU.scala:140:34, :142:21]\n wire [7:0] _in1_bytes_T_4;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_4 = in1_bytes_3;\t// @[ALU.scala:140:34, :142:21]\n wire [7:0] _in1_bytes_T_5;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_3 = in1_bytes_4;\t// @[ALU.scala:140:34, :142:21]\n wire [7:0] _in1_bytes_T_6;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_2 = in1_bytes_5;\t// @[ALU.scala:140:34, :142:21]\n wire [7:0] _in1_bytes_T_7;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_1 = in1_bytes_6;\t// @[ALU.scala:140:34, :142:21]\n wire [7:0] in1_bytes_7;\t// @[ALU.scala:140:34]\n wire [7:0] _rev8_WIRE_0 = in1_bytes_7;\t// @[ALU.scala:140:34, :142:21]\n assign _in1_bytes_T = _in1_bytes_WIRE[7:0];\t// @[ALU.scala:140:34]\n assign in1_bytes_0 = _in1_bytes_T;\t// @[ALU.scala:140:34]\n assign _in1_bytes_T_1 = _in1_bytes_WIRE[15:8];\t// @[ALU.scala:140:34]\n assign in1_bytes_1 = _in1_bytes_T_1;\t// @[ALU.scala:140:34]\n assign _in1_bytes_T_2 = _in1_bytes_WIRE[23:16];\t// @[ALU.scala:140:34]\n assign in1_bytes_2 = _in1_bytes_T_2;\t// @[ALU.scala:140:34]\n assign _in1_bytes_T_3 = _in1_bytes_WIRE[31:24];\t// @[ALU.scala:140:34]\n assign in1_bytes_3 = _in1_bytes_T_3;\t// @[ALU.scala:140:34]\n assign _in1_bytes_T_4 = _in1_bytes_WIRE[39:32];\t// @[ALU.scala:140:34]\n assign in1_bytes_4 = _in1_bytes_T_4;\t// @[ALU.scala:140:34]\n assign _in1_bytes_T_5 = _in1_bytes_WIRE[47:40];\t// @[ALU.scala:140:34]\n assign in1_bytes_5 = _in1_bytes_T_5;\t// @[ALU.scala:140:34]\n assign _in1_bytes_T_6 = _in1_bytes_WIRE[55:48];\t// @[ALU.scala:140:34]\n assign in1_bytes_6 = _in1_bytes_T_6;\t// @[ALU.scala:140:34]\n assign _in1_bytes_T_7 = _in1_bytes_WIRE[63:56];\t// @[ALU.scala:140:34]\n assign in1_bytes_7 = _in1_bytes_T_7;\t// @[ALU.scala:140:34]\n wire _orcb_T = |in1_bytes_0;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_1 = {8{_orcb_T}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_0 = _orcb_T_1;\t// @[ALU.scala:141:{21,45}]\n wire _orcb_T_2 = |in1_bytes_1;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_3 = {8{_orcb_T_2}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_1 = _orcb_T_3;\t// @[ALU.scala:141:{21,45}]\n wire _orcb_T_4 = |in1_bytes_2;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_5 = {8{_orcb_T_4}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_2 = _orcb_T_5;\t// @[ALU.scala:141:{21,45}]\n wire _orcb_T_6 = |in1_bytes_3;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_7 = {8{_orcb_T_6}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_3 = _orcb_T_7;\t// @[ALU.scala:141:{21,45}]\n wire _orcb_T_8 = |in1_bytes_4;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_9 = {8{_orcb_T_8}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_4 = _orcb_T_9;\t// @[ALU.scala:141:{21,45}]\n wire _orcb_T_10 = |in1_bytes_5;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_11 = {8{_orcb_T_10}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_5 = _orcb_T_11;\t// @[ALU.scala:141:{21,45}]\n wire _orcb_T_12 = |in1_bytes_6;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_13 = {8{_orcb_T_12}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_6 = _orcb_T_13;\t// @[ALU.scala:141:{21,45}]\n wire _orcb_T_14 = |in1_bytes_7;\t// @[ALU.scala:140:34, :141:51]\n wire [7:0] _orcb_T_15 = {8{_orcb_T_14}};\t// @[ALU.scala:141:{45,51}]\n wire [7:0] _orcb_WIRE_7 = _orcb_T_15;\t// @[ALU.scala:141:{21,45}]\n wire [15:0] orcb_lo_lo = {_orcb_WIRE_1, _orcb_WIRE_0};\t// @[ALU.scala:141:{21,62}]\n wire [15:0] orcb_lo_hi = {_orcb_WIRE_3, _orcb_WIRE_2};\t// @[ALU.scala:141:{21,62}]\n wire [31:0] orcb_lo = {orcb_lo_hi, orcb_lo_lo};\t// @[ALU.scala:141:62]\n wire [15:0] orcb_hi_lo = {_orcb_WIRE_5, _orcb_WIRE_4};\t// @[ALU.scala:141:{21,62}]\n wire [15:0] orcb_hi_hi = {_orcb_WIRE_7, _orcb_WIRE_6};\t// @[ALU.scala:141:{21,62}]\n wire [31:0] orcb_hi = {orcb_hi_hi, orcb_hi_lo};\t// @[ALU.scala:141:62]\n wire [63:0] orcb = {orcb_hi, orcb_lo};\t// @[ALU.scala:141:62]\n wire [15:0] rev8_lo_lo = {_rev8_WIRE_1, _rev8_WIRE_0};\t// @[ALU.scala:142:{21,41}]\n wire [15:0] rev8_lo_hi = {_rev8_WIRE_3, _rev8_WIRE_2};\t// @[ALU.scala:142:{21,41}]\n wire [31:0] rev8_lo = {rev8_lo_hi, rev8_lo_lo};\t// @[ALU.scala:142:41]\n wire [15:0] rev8_hi_lo = {_rev8_WIRE_5, _rev8_WIRE_4};\t// @[ALU.scala:142:{21,41}]\n wire [15:0] rev8_hi_hi = {_rev8_WIRE_7, _rev8_WIRE_6};\t// @[ALU.scala:142:{21,41}]\n wire [31:0] rev8_hi = {rev8_hi_hi, rev8_hi_lo};\t// @[ALU.scala:142:41]\n wire [63:0] rev8 = {rev8_hi, rev8_lo};\t// @[ALU.scala:142:41]\n wire [11:0] _unary_T = io_in2_0[11:0];\t// @[ALU.scala:83:7, :143:31]\n wire [15:0] _unary_T_1 = io_in1_0[15:0];\t// @[ALU.scala:83:7, :146:22]\n wire [15:0] _unary_T_8 = io_in1_0[15:0];\t// @[ALU.scala:83:7, :146:22, :148:51]\n wire _unary_T_2 = io_in1_0[7];\t// @[ALU.scala:83:7, :147:35]\n wire [55:0] _unary_T_3 = {56{_unary_T_2}};\t// @[ALU.scala:147:{20,35}]\n wire [7:0] _unary_T_4 = io_in1_0[7:0];\t// @[ALU.scala:83:7, :147:49]\n wire [63:0] _unary_T_5 = {_unary_T_3, _unary_T_4};\t// @[ALU.scala:147:{20,40,49}]\n wire _unary_T_6 = io_in1_0[15];\t// @[ALU.scala:83:7, :148:36]\n wire [47:0] _unary_T_7 = {48{_unary_T_6}};\t// @[ALU.scala:148:{20,36}]\n wire [63:0] _unary_T_9 = {_unary_T_7, _unary_T_8};\t// @[ALU.scala:148:{20,42,51}]\n wire _unary_T_10 = _unary_T == 12'h287;\t// @[ALU.scala:143:{31,45}]\n wire [63:0] _unary_T_11 = _unary_T_10 ? orcb : {57'h0, count};\t// @[ALU.scala:139:23, :141:62, :143:45]\n wire _unary_T_12 = _unary_T == 12'h6B8;\t// @[ALU.scala:143:{31,45}]\n wire [63:0] _unary_T_13 = _unary_T_12 ? rev8 : _unary_T_11;\t// @[ALU.scala:142:41, :143:45]\n wire _unary_T_14 = _unary_T == 12'h80;\t// @[ALU.scala:143:{31,45}]\n wire [63:0] _unary_T_15 = _unary_T_14 ? {48'h0, _unary_T_1} : _unary_T_13;\t// @[ALU.scala:143:45, :146:22]\n wire _unary_T_16 = _unary_T == 12'h604;\t// @[ALU.scala:143:{31,45}]\n wire [63:0] _unary_T_17 = _unary_T_16 ? _unary_T_5 : _unary_T_15;\t// @[ALU.scala:143:45, :147:40]\n wire _unary_T_18 = _unary_T == 12'h605;\t// @[ALU.scala:143:{31,45}]\n wire [63:0] unary = _unary_T_18 ? _unary_T_9 : _unary_T_17;\t// @[ALU.scala:143:45, :148:42]\n wire [63:0] maxmin_out = io_cmp_out_0 ? io_in2_0 : io_in1_0;\t// @[ALU.scala:83:7, :152:23]\n wire _rot_shamt_T = ~io_dw_0;\t// @[ALU.scala:83:7, :130:32, :155:29]\n wire [6:0] _rot_shamt_T_1 = _rot_shamt_T ? 7'h20 : 7'h40;\t// @[ALU.scala:155:{22,29}]\n wire [7:0] _rot_shamt_T_2 = {1'h0, _rot_shamt_T_1} - {2'h0, shamt};\t// @[package.scala:16:47]\n wire [6:0] rot_shamt = _rot_shamt_T_2[6:0];\t// @[ALU.scala:155:54]\n wire [63:0] _rotin_T_4 = {32'h0, _rotin_T_3};\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_6 = {_rotin_T_5, 32'h0};\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_8 = _rotin_T_6 & 64'hFFFFFFFF00000000;\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_9 = _rotin_T_4 | _rotin_T_8;\t// @[ALU.scala:156:44]\n wire [47:0] _rotin_T_13 = _rotin_T_9[63:16];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_14 = {16'h0, _rotin_T_13 & 48'hFFFF0000FFFF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _rotin_T_15 = _rotin_T_9[47:0];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_16 = {_rotin_T_15, 16'h0};\t// @[ALU.scala:106:46, :156:44]\n wire [63:0] _rotin_T_18 = _rotin_T_16 & 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_19 = _rotin_T_14 | _rotin_T_18;\t// @[ALU.scala:156:44]\n wire [55:0] _rotin_T_23 = _rotin_T_19[63:8];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_24 = {8'h0, _rotin_T_23 & 56'hFF00FF00FF00FF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _rotin_T_25 = _rotin_T_19[55:0];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_26 = {_rotin_T_25, 8'h0};\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_28 = _rotin_T_26 & 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_29 = _rotin_T_24 | _rotin_T_28;\t// @[ALU.scala:156:44]\n wire [59:0] _rotin_T_33 = _rotin_T_29[63:4];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_34 = {4'h0, _rotin_T_33 & 60'hF0F0F0F0F0F0F0F};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _rotin_T_35 = _rotin_T_29[59:0];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_36 = {_rotin_T_35, 4'h0};\t// @[ALU.scala:106:46, :156:44]\n wire [63:0] _rotin_T_38 = _rotin_T_36 & 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_39 = _rotin_T_34 | _rotin_T_38;\t// @[ALU.scala:156:44]\n wire [61:0] _rotin_T_43 = _rotin_T_39[63:2];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_44 = {2'h0, _rotin_T_43 & 62'h3333333333333333};\t// @[package.scala:16:47]\n wire [61:0] _rotin_T_45 = _rotin_T_39[61:0];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_46 = {_rotin_T_45, 2'h0};\t// @[package.scala:16:47]\n wire [63:0] _rotin_T_48 = _rotin_T_46 & 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_49 = _rotin_T_44 | _rotin_T_48;\t// @[ALU.scala:156:44]\n wire [62:0] _rotin_T_53 = _rotin_T_49[63:1];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_54 = {1'h0, _rotin_T_53 & 63'h5555555555555555};\t// @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _rotin_T_55 = _rotin_T_49[62:0];\t// @[ALU.scala:156:44]\n wire [63:0] _rotin_T_56 = {_rotin_T_55, 1'h0};\t// @[ALU.scala:88:26, :156:44]\n wire [63:0] _rotin_T_58 = _rotin_T_56 & 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotin_T_59 = _rotin_T_54 | _rotin_T_58;\t// @[ALU.scala:156:44]\n wire [63:0] rotin = _rotin_T ? shin_r : _rotin_T_59;\t// @[ALU.scala:104:18, :156:{18,24,44}]\n wire [63:0] _rotout_r_T = rotin >> rot_shamt;\t// @[ALU.scala:155:54, :156:18, :157:25]\n wire [63:0] rotout_r = _rotout_r_T;\t// @[ALU.scala:157:{25,38}]\n wire [31:0] _rotout_l_T_2 = rotout_r[63:32];\t// @[ALU.scala:157:38, :158:25]\n wire [63:0] _rotout_l_T_3 = {32'h0, _rotout_l_T_2};\t// @[ALU.scala:158:25]\n wire [31:0] _rotout_l_T_4 = rotout_r[31:0];\t// @[ALU.scala:157:38, :158:25]\n wire [63:0] _rotout_l_T_5 = {_rotout_l_T_4, 32'h0};\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_7 = _rotout_l_T_5 & 64'hFFFFFFFF00000000;\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_8 = _rotout_l_T_3 | _rotout_l_T_7;\t// @[ALU.scala:158:25]\n wire [47:0] _rotout_l_T_12 = _rotout_l_T_8[63:16];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_13 = {16'h0, _rotout_l_T_12 & 48'hFFFF0000FFFF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [47:0] _rotout_l_T_14 = _rotout_l_T_8[47:0];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_15 = {_rotout_l_T_14, 16'h0};\t// @[ALU.scala:106:46, :158:25]\n wire [63:0] _rotout_l_T_17 = _rotout_l_T_15 & 64'hFFFF0000FFFF0000;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_18 = _rotout_l_T_13 | _rotout_l_T_17;\t// @[ALU.scala:158:25]\n wire [55:0] _rotout_l_T_22 = _rotout_l_T_18[63:8];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_23 = {8'h0, _rotout_l_T_22 & 56'hFF00FF00FF00FF};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [55:0] _rotout_l_T_24 = _rotout_l_T_18[55:0];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_25 = {_rotout_l_T_24, 8'h0};\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_27 = _rotout_l_T_25 & 64'hFF00FF00FF00FF00;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_28 = _rotout_l_T_23 | _rotout_l_T_27;\t// @[ALU.scala:158:25]\n wire [59:0] _rotout_l_T_32 = _rotout_l_T_28[63:4];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_33 = {4'h0, _rotout_l_T_32 & 60'hF0F0F0F0F0F0F0F};\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [59:0] _rotout_l_T_34 = _rotout_l_T_28[59:0];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_35 = {_rotout_l_T_34, 4'h0};\t// @[ALU.scala:106:46, :158:25]\n wire [63:0] _rotout_l_T_37 = _rotout_l_T_35 & 64'hF0F0F0F0F0F0F0F0;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_38 = _rotout_l_T_33 | _rotout_l_T_37;\t// @[ALU.scala:158:25]\n wire [61:0] _rotout_l_T_42 = _rotout_l_T_38[63:2];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_43 = {2'h0, _rotout_l_T_42 & 62'h3333333333333333};\t// @[package.scala:16:47]\n wire [61:0] _rotout_l_T_44 = _rotout_l_T_38[61:0];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_45 = {_rotout_l_T_44, 2'h0};\t// @[package.scala:16:47]\n wire [63:0] _rotout_l_T_47 = _rotout_l_T_45 & 64'hCCCCCCCCCCCCCCCC;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] _rotout_l_T_48 = _rotout_l_T_43 | _rotout_l_T_47;\t// @[ALU.scala:158:25]\n wire [62:0] _rotout_l_T_52 = _rotout_l_T_48[63:1];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_53 = {1'h0, _rotout_l_T_52 & 63'h5555555555555555};\t// @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]\n wire [62:0] _rotout_l_T_54 = _rotout_l_T_48[62:0];\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_l_T_55 = {_rotout_l_T_54, 1'h0};\t// @[ALU.scala:88:26, :158:25]\n wire [63:0] _rotout_l_T_57 = _rotout_l_T_55 & 64'hAAAAAAAAAAAAAAAA;\t// @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]\n wire [63:0] rotout_l = _rotout_l_T_53 | _rotout_l_T_57;\t// @[ALU.scala:158:25]\n wire [63:0] _rotout_T_1 = _rotout_T ? rotout_r : rotout_l;\t// @[ALU.scala:157:38, :158:25, :159:{19,25}]\n wire [63:0] _rotout_T_3 = _rotout_T_2 ? shout_l : shout_r;\t// @[ALU.scala:107:73, :108:24, :159:{55,61}]\n wire [63:0] rotout = _rotout_T_1 | _rotout_T_3;\t// @[ALU.scala:159:{19,50,55}]\n wire _out_T = io_fn_0 == 5'h0;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_1 = _out_T ? io_adder_out_0 : shift_logic;\t// @[ALU.scala:83:7, :123:52, :161:47]\n wire _out_T_2 = io_fn_0 == 5'hA;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_3 = _out_T_2 ? io_adder_out_0 : _out_T_1;\t// @[ALU.scala:83:7, :161:47]\n wire _out_T_4 = io_fn_0 == 5'h10;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_5 = _out_T_4 ? unary : _out_T_3;\t// @[ALU.scala:143:45, :161:47]\n wire _out_T_6 = io_fn_0 == 5'h1C;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_7 = _out_T_6 ? maxmin_out : _out_T_5;\t// @[ALU.scala:152:23, :161:47]\n wire _out_T_8 = io_fn_0 == 5'h1D;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_9 = _out_T_8 ? maxmin_out : _out_T_7;\t// @[ALU.scala:152:23, :161:47]\n wire _out_T_10 = io_fn_0 == 5'h1E;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_11 = _out_T_10 ? maxmin_out : _out_T_9;\t// @[ALU.scala:152:23, :161:47]\n wire _out_T_12 = &io_fn_0;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_13 = _out_T_12 ? maxmin_out : _out_T_11;\t// @[ALU.scala:152:23, :161:47]\n wire _out_T_14 = io_fn_0 == 5'h11;\t// @[ALU.scala:83:7, :161:47]\n wire [63:0] _out_T_15 = _out_T_14 ? rotout : _out_T_13;\t// @[ALU.scala:159:50, :161:47]\n wire [63:0] out = _out_T_16 ? rotout : _out_T_15;\t// @[ALU.scala:159:50, :161:47]\n wire _io_out_T = out[31];\t// @[ALU.scala:161:47, :178:56]\n wire [31:0] _io_out_T_1 = {32{_io_out_T}};\t// @[ALU.scala:178:{48,56}]\n wire [31:0] _io_out_T_2 = out[31:0];\t// @[ALU.scala:161:47, :178:66]\n wire [63:0] _io_out_T_3 = {_io_out_T_1, _io_out_T_2};\t// @[ALU.scala:178:{43,48,66}]\n assign io_out_0 = io_dw_0 ? out : _io_out_T_3;\t// @[ALU.scala:83:7, :161:47, :175:10, :178:{28,37,43}]\n assign io_out = io_out_0;\t// @[ALU.scala:83:7]\n assign io_adder_out = io_adder_out_0;\t// @[ALU.scala:83:7]\n assign io_cmp_out = io_cmp_out_0;\t// @[ALU.scala:83:7]\nendmodule"}}},{"rowIdx":32162,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_7 : \n output io : { flip in : UInt<1>, out : UInt<1>} \n input clock : Clock \n input reset : AsyncReset \n\n\n inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_7 \n connect io_out_sink_valid.clock, clock\n\n connect io_out_sink_valid.reset, reset\n\n connect io_out_sink_valid.io.d, io.in \n wire _io_out_WIRE : UInt<1> \n connect _io_out_WIRE, io_out_sink_valid.io.q \n connect io.out, _io_out_WIRE"},"response":{"kind":"string","value":"module AsyncValidSync_7(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_7 io_out_sink_valid (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":32163,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_18 : \n output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} \n\n\n node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) \n node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) \n node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) \n node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) \n node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) \n node notNaN_signOut = xor(io.a.sign, io.b.sign) \n node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) \n node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) \n node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) \n node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) \n node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) \n node common_sExpOut = asSInt(_common_sExpOut_T_4) \n node _common_sigOut_T = mul(io.a.sig, io.b.sig) \n node common_sigOut = bits(_common_sigOut_T, 47, 0) \n node _io_invalidExc_T = bits(io.a.sig, 22, 22) \n node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) \n node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) \n node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) \n node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) \n node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) \n node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) \n node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) \n connect io.invalidExc, _io_invalidExc_T_7 \n connect io.rawOut.isInf, notNaN_isInfOut \n connect io.rawOut.isZero, notNaN_isZeroOut \n connect io.rawOut.sExp, common_sExpOut \n node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) \n connect io.rawOut.isNaN, _io_rawOut_isNaN_T \n connect io.rawOut.sign, notNaN_signOut \n connect io.rawOut.sig, common_sigOut"},"response":{"kind":"string","value":"module MulFullRawFN_18(\t// @[MulRecFN.scala:47:7]\n input io_a_isNaN,\t// @[MulRecFN.scala:49:16]\n input io_a_isInf,\t// @[MulRecFN.scala:49:16]\n input io_a_isZero,\t// @[MulRecFN.scala:49:16]\n input io_a_sign,\t// @[MulRecFN.scala:49:16]\n input [9:0] io_a_sExp,\t// @[MulRecFN.scala:49:16]\n input [24:0] io_a_sig,\t// @[MulRecFN.scala:49:16]\n input io_b_isNaN,\t// @[MulRecFN.scala:49:16]\n input io_b_isInf,\t// @[MulRecFN.scala:49:16]\n input io_b_isZero,\t// @[MulRecFN.scala:49:16]\n input io_b_sign,\t// @[MulRecFN.scala:49:16]\n input [9:0] io_b_sExp,\t// @[MulRecFN.scala:49:16]\n input [24:0] io_b_sig,\t// @[MulRecFN.scala:49:16]\n output io_invalidExc,\t// @[MulRecFN.scala:49:16]\n output io_rawOut_isNaN,\t// @[MulRecFN.scala:49:16]\n output io_rawOut_isInf,\t// @[MulRecFN.scala:49:16]\n output io_rawOut_isZero,\t// @[MulRecFN.scala:49:16]\n output io_rawOut_sign,\t// @[MulRecFN.scala:49:16]\n output [9:0] io_rawOut_sExp,\t// @[MulRecFN.scala:49:16]\n output [47:0] io_rawOut_sig\t// @[MulRecFN.scala:49:16]\n);\n\n wire io_a_isNaN_0 = io_a_isNaN;\t// @[MulRecFN.scala:47:7]\n wire io_a_isInf_0 = io_a_isInf;\t// @[MulRecFN.scala:47:7]\n wire io_a_isZero_0 = io_a_isZero;\t// @[MulRecFN.scala:47:7]\n wire io_a_sign_0 = io_a_sign;\t// @[MulRecFN.scala:47:7]\n wire [9:0] io_a_sExp_0 = io_a_sExp;\t// @[MulRecFN.scala:47:7]\n wire [24:0] io_a_sig_0 = io_a_sig;\t// @[MulRecFN.scala:47:7]\n wire io_b_isNaN_0 = io_b_isNaN;\t// @[MulRecFN.scala:47:7]\n wire io_b_isInf_0 = io_b_isInf;\t// @[MulRecFN.scala:47:7]\n wire io_b_isZero_0 = io_b_isZero;\t// @[MulRecFN.scala:47:7]\n wire io_b_sign_0 = io_b_sign;\t// @[MulRecFN.scala:47:7]\n wire [9:0] io_b_sExp_0 = io_b_sExp;\t// @[MulRecFN.scala:47:7]\n wire [24:0] io_b_sig_0 = io_b_sig;\t// @[MulRecFN.scala:47:7]\n wire _io_invalidExc_T_7;\t// @[MulRecFN.scala:66:71]\n wire _io_rawOut_isNaN_T;\t// @[MulRecFN.scala:70:35]\n wire notNaN_isInfOut;\t// @[MulRecFN.scala:59:38]\n wire notNaN_isZeroOut;\t// @[MulRecFN.scala:60:40]\n wire notNaN_signOut;\t// @[MulRecFN.scala:61:36]\n wire [9:0] common_sExpOut;\t// @[MulRecFN.scala:62:48]\n wire [47:0] common_sigOut;\t// @[MulRecFN.scala:63:46]\n wire io_rawOut_isNaN_0;\t// @[MulRecFN.scala:47:7]\n wire io_rawOut_isInf_0;\t// @[MulRecFN.scala:47:7]\n wire io_rawOut_isZero_0;\t// @[MulRecFN.scala:47:7]\n wire io_rawOut_sign_0;\t// @[MulRecFN.scala:47:7]\n wire [9:0] io_rawOut_sExp_0;\t// @[MulRecFN.scala:47:7]\n wire [47:0] io_rawOut_sig_0;\t// @[MulRecFN.scala:47:7]\n wire io_invalidExc_0;\t// @[MulRecFN.scala:47:7]\n wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0;\t// @[MulRecFN.scala:47:7, :58:44]\n wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0;\t// @[MulRecFN.scala:47:7, :58:76]\n wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1;\t// @[MulRecFN.scala:58:{44,60,76}]\n assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0;\t// @[MulRecFN.scala:47:7, :59:38]\n assign io_rawOut_isInf_0 = notNaN_isInfOut;\t// @[MulRecFN.scala:47:7, :59:38]\n assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0;\t// @[MulRecFN.scala:47:7, :60:40]\n assign io_rawOut_isZero_0 = notNaN_isZeroOut;\t// @[MulRecFN.scala:47:7, :60:40]\n assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0;\t// @[MulRecFN.scala:47:7, :61:36]\n assign io_rawOut_sign_0 = notNaN_signOut;\t// @[MulRecFN.scala:47:7, :61:36]\n wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0};\t// @[MulRecFN.scala:47:7, :62:36]\n wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0];\t// @[MulRecFN.scala:62:36]\n wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1;\t// @[MulRecFN.scala:62:36]\n wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100;\t// @[MulRecFN.scala:62:{36,48}]\n wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0];\t// @[MulRecFN.scala:62:48]\n assign common_sExpOut = _common_sExpOut_T_4;\t// @[MulRecFN.scala:62:48]\n assign io_rawOut_sExp_0 = common_sExpOut;\t// @[MulRecFN.scala:47:7, :62:48]\n wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0};\t// @[MulRecFN.scala:47:7, :63:35]\n assign common_sigOut = _common_sigOut_T[47:0];\t// @[MulRecFN.scala:63:{35,46}]\n assign io_rawOut_sig_0 = common_sigOut;\t// @[MulRecFN.scala:47:7, :63:46]\n wire _io_invalidExc_T = io_a_sig_0[22];\t// @[common.scala:82:56]\n wire _io_invalidExc_T_1 = ~_io_invalidExc_T;\t// @[common.scala:82:{49,56}]\n wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1;\t// @[common.scala:82:{46,49}]\n wire _io_invalidExc_T_3 = io_b_sig_0[22];\t// @[common.scala:82:56]\n wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3;\t// @[common.scala:82:{49,56}]\n wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4;\t// @[common.scala:82:{46,49}]\n wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5;\t// @[common.scala:82:46]\n assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc;\t// @[MulRecFN.scala:58:60, :66:{45,71}]\n assign io_invalidExc_0 = _io_invalidExc_T_7;\t// @[MulRecFN.scala:47:7, :66:71]\n assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0;\t// @[MulRecFN.scala:47:7, :70:35]\n assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T;\t// @[MulRecFN.scala:47:7, :70:35]\n assign io_invalidExc = io_invalidExc_0;\t// @[MulRecFN.scala:47:7]\n assign io_rawOut_isNaN = io_rawOut_isNaN_0;\t// @[MulRecFN.scala:47:7]\n assign io_rawOut_isInf = io_rawOut_isInf_0;\t// @[MulRecFN.scala:47:7]\n assign io_rawOut_isZero = io_rawOut_isZero_0;\t// @[MulRecFN.scala:47:7]\n assign io_rawOut_sign = io_rawOut_sign_0;\t// @[MulRecFN.scala:47:7]\n assign io_rawOut_sExp = io_rawOut_sExp_0;\t// @[MulRecFN.scala:47:7]\n assign io_rawOut_sig = io_rawOut_sig_0;\t// @[MulRecFN.scala:47:7]\nendmodule"}}},{"rowIdx":32164,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module PE_490 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} \n\n\n inst mac_unit of MacUnit_234 \n connect mac_unit.clock, clock\n\n connect mac_unit.reset, reset\n\n reg c1 : SInt<8>, clock \n reg c2 : SInt<8>, clock \n connect io.out_a, io.in_a \n connect io.out_control.dataflow, io.in_control.dataflow \n connect io.out_control.propagate, io.in_control.propagate \n connect io.out_control.shift, io.in_control.shift \n connect io.out_id, io.in_id \n connect io.out_last, io.in_last \n connect io.out_valid, io.in_valid \n connect mac_unit.io.in_a, io.in_a \n reg last_s : UInt<1>, clock \n when io.in_valid : \n connect last_s, io.in_control.propagate \n node flip = neq(last_s, io.in_control.propagate) \n node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) \n connect io.bad_dataflow, UInt<1>(0h0) \n node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) \n node _T_1 = and(UInt<1>(0h0), _T) \n node _T_2 = or(UInt<1>(0h0), _T_1) \n when _T_2 : \n node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_3 : \n node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) \n node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) \n node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) \n node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) \n node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_1 = asUInt(c1) \n node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) \n node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) \n node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) \n node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) \n node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) \n node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) \n node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T = dshr(c1, shift_offset) \n node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) \n node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) \n node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) \n node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) \n node _io_out_c_T = dshr(c1, shift_offset) \n node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) \n node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) \n node _io_out_c_T_4 = asSInt(_io_out_c_T_3) \n node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) \n node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) \n node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) \n node _io_out_c_T_10 = asSInt(_io_out_c_T_9) \n connect io.out_c, _io_out_c_T_10 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE : SInt<8> \n node _mac_unit_io_in_b_T = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) \n connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE \n connect mac_unit.io.in_c, c2 \n connect c2, mac_unit.io.out_d \n node _c1_T = bits(io.in_d, 7, 0) \n node _c1_T_1 = asSInt(_c1_T) \n connect c1, _c1_T_1 \n else :\n\n node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) \n node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) \n node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) \n node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) \n node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_10 = asUInt(c2) \n node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) \n node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) \n node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) \n node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) \n node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) \n node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) \n node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) \n node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) \n node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) \n node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) \n node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) \n node _io_out_c_T_11 = dshr(c2, shift_offset) \n node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) \n node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) \n node _io_out_c_T_15 = asSInt(_io_out_c_T_14) \n node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) \n node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) \n node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) \n node _io_out_c_T_21 = asSInt(_io_out_c_T_20) \n connect io.out_c, _io_out_c_T_21 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE_1 : SInt<8> \n node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) \n connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 \n connect mac_unit.io.in_c, c1 \n connect c1, mac_unit.io.out_d \n node _c2_T = bits(io.in_d, 7, 0) \n node _c2_T_1 = asSInt(_c2_T) \n connect c2, _c2_T_1 \n else :\n\n node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) \n node _T_5 = and(UInt<1>(0h0), _T_4) \n node _T_6 = or(UInt<1>(0h1), _T_5) \n when _T_6 : \n node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_7 : \n connect io.out_c, c1 \n wire _mac_unit_io_in_b_WIRE_2 : SInt<8> \n node _mac_unit_io_in_b_T_4 = asUInt(c2) \n node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) \n connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c1, io.in_d \n else :\n\n connect io.out_c, c2 \n wire _mac_unit_io_in_b_WIRE_3 : SInt<8> \n node _mac_unit_io_in_b_T_6 = asUInt(c1) \n node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) \n connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c2, io.in_d \n else :\n\n connect io.bad_dataflow, UInt<1>(0h1) \n invalidate io.out_c \n invalidate io.out_b \n wire _mac_unit_io_in_b_WIRE_4 : SInt<8> \n node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) \n connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 \n connect mac_unit.io.in_c, c2 \n node _T_8 = eq(io.in_valid, UInt<1>(0h0)) \n when _T_8 : \n connect c1, c1 \n connect c2, c2 \n invalidate mac_unit.io.in_b \n invalidate mac_unit.io.in_c"},"response":{"kind":"string","value":"module PE_490(\t// @[PE.scala:31:7]\n input clock,\t// @[PE.scala:31:7]\n input reset,\t// @[PE.scala:31:7]\n input [7:0] io_in_a,\t// @[PE.scala:35:14]\n input [19:0] io_in_b,\t// @[PE.scala:35:14]\n input [19:0] io_in_d,\t// @[PE.scala:35:14]\n output [7:0] io_out_a,\t// @[PE.scala:35:14]\n output [19:0] io_out_b,\t// @[PE.scala:35:14]\n output [19:0] io_out_c,\t// @[PE.scala:35:14]\n input io_in_control_dataflow,\t// @[PE.scala:35:14]\n input io_in_control_propagate,\t// @[PE.scala:35:14]\n input [4:0] io_in_control_shift,\t// @[PE.scala:35:14]\n output io_out_control_dataflow,\t// @[PE.scala:35:14]\n output io_out_control_propagate,\t// @[PE.scala:35:14]\n output [4:0] io_out_control_shift,\t// @[PE.scala:35:14]\n input [2:0] io_in_id,\t// @[PE.scala:35:14]\n output [2:0] io_out_id,\t// @[PE.scala:35:14]\n input io_in_last,\t// @[PE.scala:35:14]\n output io_out_last,\t// @[PE.scala:35:14]\n input io_in_valid,\t// @[PE.scala:35:14]\n output io_out_valid\t// @[PE.scala:35:14]\n);\n\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:31:7]\n wire [19:0] io_in_b_0 = io_in_b;\t// @[PE.scala:31:7]\n wire [19:0] io_in_d_0 = io_in_d;\t// @[PE.scala:31:7]\n wire io_in_control_dataflow_0 = io_in_control_dataflow;\t// @[PE.scala:31:7]\n wire io_in_control_propagate_0 = io_in_control_propagate;\t// @[PE.scala:31:7]\n wire [4:0] io_in_control_shift_0 = io_in_control_shift;\t// @[PE.scala:31:7]\n wire [2:0] io_in_id_0 = io_in_id;\t// @[PE.scala:31:7]\n wire io_in_last_0 = io_in_last;\t// @[PE.scala:31:7]\n wire io_in_valid_0 = io_in_valid;\t// @[PE.scala:31:7]\n wire io_bad_dataflow = 1'h0;\t// @[PE.scala:31:7]\n wire _io_out_c_T_5 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_6 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire _io_out_c_T_16 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_17 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire [7:0] io_out_a_0 = io_in_a_0;\t// @[PE.scala:31:7]\n wire [19:0] _mac_unit_io_in_b_T = io_in_b_0;\t// @[PE.scala:31:7, :106:37]\n wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0;\t// @[PE.scala:31:7, :113:37]\n wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0;\t// @[PE.scala:31:7, :137:35]\n wire io_out_control_dataflow_0 = io_in_control_dataflow_0;\t// @[PE.scala:31:7]\n wire io_out_control_propagate_0 = io_in_control_propagate_0;\t// @[PE.scala:31:7]\n wire [4:0] io_out_control_shift_0 = io_in_control_shift_0;\t// @[PE.scala:31:7]\n wire [2:0] io_out_id_0 = io_in_id_0;\t// @[PE.scala:31:7]\n wire io_out_last_0 = io_in_last_0;\t// @[PE.scala:31:7]\n wire io_out_valid_0 = io_in_valid_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_b_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_c_0;\t// @[PE.scala:31:7]\n reg [7:0] c1;\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_zeros_T_1 = c1;\t// @[PE.scala:70:15]\n wire [7:0] _mac_unit_io_in_b_T_6 = c1;\t// @[PE.scala:70:15, :127:38]\n reg [7:0] c2;\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_zeros_T_10 = c2;\t// @[PE.scala:71:15]\n wire [7:0] _mac_unit_io_in_b_T_4 = c2;\t// @[PE.scala:71:15, :121:38]\n reg last_s;\t// @[PE.scala:89:25]\n wire flip = last_s != io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25, :90:21]\n wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0;\t// @[PE.scala:31:7, :90:21, :91:25]\n wire _GEN = shift_offset == 5'h0;\t// @[PE.scala:91:25]\n wire _io_out_c_point_five_T;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T = _GEN;\t// @[Arithmetic.scala:101:32]\n wire _io_out_c_point_five_T_5;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T_5 = _GEN;\t// @[Arithmetic.scala:101:32]\n wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1;\t// @[PE.scala:91:25]\n wire [5:0] _io_out_c_point_five_T_1;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_1 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_2;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_2 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [5:0] _io_out_c_point_five_T_6;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_6 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_11;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_11 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2);\t// @[PE.scala:70:15]\n wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire _GEN_1 = shift_offset < 5'h2;\t// @[PE.scala:91:25]\n wire _io_out_c_zeros_T;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire _io_out_c_zeros_T_9;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T_9 = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros = |_io_out_c_zeros_T_8;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_2 = {3'h0, shift_offset};\t// @[PE.scala:91:25]\n wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2);\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_ones_digit_T;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T = _GEN_3;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T = _GEN_3;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r = _io_out_c_r_T_1;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_4 = _io_out_c_T_3;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_8 = _io_out_c_T_7;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_9 = _io_out_c_T_8;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_10 = _io_out_c_T_9;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T;\t// @[PE.scala:106:37]\n wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0];\t// @[PE.scala:106:37]\n wire [7:0] _c1_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c2_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c1_T_1 = _c1_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7);\t// @[PE.scala:71:15]\n wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2);\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_ones_digit_T_1;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T_1 = _GEN_4;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T_11;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T_11 = _GEN_4;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r_1 = _io_out_c_r_T_3;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_15 = _io_out_c_T_14;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_19 = _io_out_c_T_18;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_20 = _io_out_c_T_19;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_21 = _io_out_c_T_20;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2;\t// @[PE.scala:113:37]\n wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0];\t// @[PE.scala:113:37]\n wire [7:0] _c2_T_1 = _c2_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [7:0] _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4;\t// @[PE.scala:121:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2};\t// @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]\n wire [7:0] _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6;\t// @[PE.scala:127:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8;\t// @[PE.scala:137:35]\n wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0];\t// @[PE.scala:137:35]\n always @(posedge clock) begin\t// @[PE.scala:31:7]\n if (io_in_valid_0 & io_in_control_propagate_0)\t// @[PE.scala:31:7, :102:95, :141:17, :142:8]\n c1 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :70:15]\n if (~(~io_in_valid_0 | io_in_control_propagate_0))\t// @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]\n c2 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :71:15]\n if (io_in_valid_0)\t// @[PE.scala:31:7]\n last_s <= io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25]\n always @(posedge)\n MacUnit_234 mac_unit (\t// @[PE.scala:64:24]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0),\t// @[PE.scala:31:7]\n .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3),\t// @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]\n .io_in_c (io_in_b_0),\t// @[PE.scala:31:7]\n .io_out_d (io_out_b_0)\n );\t// @[PE.scala:64:24]\n assign io_out_a = io_out_a_0;\t// @[PE.scala:31:7]\n assign io_out_b = io_out_b_0;\t// @[PE.scala:31:7]\n assign io_out_c = io_out_c_0;\t// @[PE.scala:31:7]\n assign io_out_control_dataflow = io_out_control_dataflow_0;\t// @[PE.scala:31:7]\n assign io_out_control_propagate = io_out_control_propagate_0;\t// @[PE.scala:31:7]\n assign io_out_control_shift = io_out_control_shift_0;\t// @[PE.scala:31:7]\n assign io_out_id = io_out_id_0;\t// @[PE.scala:31:7]\n assign io_out_last = io_out_last_0;\t// @[PE.scala:31:7]\n assign io_out_valid = io_out_valid_0;\t// @[PE.scala:31:7]\nendmodule"}}},{"rowIdx":32165,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module MacUnit_5 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}} \n\n\n node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31) \n node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23) \n node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0) \n node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0)) \n node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0)) \n node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0) \n node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1) \n node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2) \n node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3) \n node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4) \n node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5) \n node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6) \n node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7) \n node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8) \n node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9) \n node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10) \n node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11) \n node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12) \n node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13) \n node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14) \n node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15) \n node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16) \n node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17) \n node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18) \n node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19) \n node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20) \n node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21) \n node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22) \n node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) \n node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23) \n node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24) \n node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25) \n node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26) \n node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27) \n node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28) \n node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29) \n node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30) \n node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31) \n node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32) \n node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33) \n node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34) \n node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35) \n node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36) \n node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37) \n node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38) \n node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39) \n node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40) \n node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41) \n node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42) \n node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43) \n node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist) \n node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0) \n node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1) \n node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff)) \n node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn) \n node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) \n node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2) \n node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3) \n node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1) \n node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn) \n node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7) \n node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3)) \n wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} \n node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) \n node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T) \n connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1 \n node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn) \n connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T \n connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero \n connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign \n node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0) \n node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T) \n connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1 \n node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0)) \n node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T) \n node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn) \n node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2) \n connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3 \n node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6) \n node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T) \n node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) \n node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2) \n node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3) \n node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0) \n node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5) \n node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0) \n node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7) \n node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31) \n node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23) \n node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0) \n node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0)) \n node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0)) \n node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0) \n node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1) \n node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2) \n node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3) \n node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4) \n node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5) \n node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6) \n node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7) \n node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8) \n node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9) \n node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10) \n node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11) \n node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12) \n node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13) \n node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14) \n node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15) \n node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16) \n node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17) \n node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18) \n node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19) \n node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20) \n node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21) \n node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22) \n node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) \n node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23) \n node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24) \n node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25) \n node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26) \n node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27) \n node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28) \n node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29) \n node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30) \n node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31) \n node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32) \n node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33) \n node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34) \n node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35) \n node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36) \n node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37) \n node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38) \n node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39) \n node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40) \n node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41) \n node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42) \n node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43) \n node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist) \n node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0) \n node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1) \n node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff)) \n node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn) \n node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) \n node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2) \n node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3) \n node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1) \n node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn) \n node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7) \n node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3)) \n wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} \n node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) \n node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T) \n connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1 \n node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn) \n connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T \n connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero \n connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign \n node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0) \n node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T) \n connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1 \n node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0)) \n node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T) \n node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn) \n node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2) \n connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3 \n node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6) \n node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T) \n node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) \n node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2) \n node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3) \n node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0) \n node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5) \n node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0) \n node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7) \n node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31) \n node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23) \n node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0) \n node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0)) \n node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0)) \n node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0) \n node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1) \n node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2) \n node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3) \n node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4) \n node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5) \n node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6) \n node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7) \n node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8) \n node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9) \n node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10) \n node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11) \n node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12) \n node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13) \n node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14) \n node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15) \n node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16) \n node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17) \n node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18) \n node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19) \n node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20) \n node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21) \n node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22) \n node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) \n node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23) \n node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24) \n node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25) \n node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26) \n node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27) \n node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28) \n node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29) \n node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30) \n node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31) \n node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32) \n node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33) \n node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34) \n node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35) \n node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36) \n node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37) \n node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38) \n node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39) \n node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40) \n node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41) \n node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42) \n node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43) \n node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist) \n node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0) \n node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1) \n node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff)) \n node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn) \n node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) \n node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2) \n node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3) \n node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1) \n node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn) \n node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7) \n node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) \n wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} \n node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) \n node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T) \n connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1 \n node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn) \n connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T \n connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero \n connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign \n node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0) \n node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T) \n connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1 \n node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0)) \n node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T) \n node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn) \n node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2) \n connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3 \n node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6) \n node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T) \n node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) \n node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2) \n node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3) \n node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0) \n node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5) \n node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0) \n node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7) \n inst io_out_d_m1_resizer of RecFNToRecFN_174 \n connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec \n connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0) \n connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1) \n inst io_out_d_m2_resizer of RecFNToRecFN_175 \n connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec \n connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0) \n connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1) \n inst io_out_d_muladder of MulAddRecFN_e8_s24_69 \n connect io_out_d_muladder.io.op, UInt<1>(0h0) \n connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0) \n connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1) \n connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out \n connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out \n connect io_out_d_muladder.io.c, io_out_d_self_rec \n wire io_out_d_out : { bits : UInt<32>} \n node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23) \n node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6) \n node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0)) \n node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7) \n node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3)) \n wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} \n node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) \n node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T) \n connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1 \n node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) \n node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0)) \n node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1) \n connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2 \n connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero \n node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32) \n connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T \n node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp) \n connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T \n node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0)) \n node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T) \n node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0) \n node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2) \n connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3 \n node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) \n node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0) \n node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T) \n node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1) \n node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1) \n node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist) \n node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0) \n node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0) \n node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81)) \n node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1) \n node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2) \n node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf) \n node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) \n node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5) \n node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0) \n node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T) \n node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1) \n node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut) \n node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut) \n connect io_out_d_out.bits, _io_out_d_out_bits_T \n connect io.out_d, io_out_d_out"},"response":{"kind":"string","value":"module MacUnit_5(\t// @[PE.scala:14:7]\n input clock,\t// @[PE.scala:14:7]\n input reset,\t// @[PE.scala:14:7]\n input [31:0] io_in_a_bits,\t// @[PE.scala:16:14]\n input [31:0] io_in_b_bits,\t// @[PE.scala:16:14]\n input [31:0] io_in_c_bits,\t// @[PE.scala:16:14]\n output [31:0] io_out_d_bits\t// @[PE.scala:16:14]\n);\n\n wire io_out_d_self_rec_rawIn_isNaN;\t// @[rawFloatFromFN.scala:63:19]\n wire io_out_d_m2_rec_rawIn_isNaN;\t// @[rawFloatFromFN.scala:63:19]\n wire io_out_d_m1_rec_rawIn_isNaN;\t// @[rawFloatFromFN.scala:63:19]\n wire [32:0] _io_out_d_muladder_io_out;\t// @[Arithmetic.scala:376:30]\n wire [32:0] _io_out_d_m2_resizer_io_out;\t// @[Arithmetic.scala:369:32]\n wire [32:0] _io_out_d_m1_resizer_io_out;\t// @[Arithmetic.scala:362:32]\n wire [31:0] io_in_a_bits_0 = io_in_a_bits;\t// @[PE.scala:14:7]\n wire [31:0] io_in_b_bits_0 = io_in_b_bits;\t// @[PE.scala:14:7]\n wire [31:0] io_in_c_bits_0 = io_in_c_bits;\t// @[PE.scala:14:7]\n wire [31:0] io_out_d_out_bits;\t// @[Arithmetic.scala:387:23]\n wire [31:0] io_out_d_bits_0;\t// @[PE.scala:14:7]\n wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31];\t// @[rawFloatFromFN.scala:44:18]\n wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign;\t// @[rawFloatFromFN.scala:44:18, :63:19]\n wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23];\t// @[rawFloatFromFN.scala:45:19]\n wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0];\t// @[rawFloatFromFN.scala:46:21]\n wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0;\t// @[rawFloatFromFN.scala:45:19, :48:30]\n wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0;\t// @[rawFloatFromFN.scala:46:21, :49:34]\n wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22];\t// @[rawFloatFromFN.scala:46:21]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42;\t// @[Mux.scala:50:70]\n wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43;\t// @[Mux.scala:50:70]\n wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist;\t// @[Mux.scala:50:70]\n wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0];\t// @[rawFloatFromFN.scala:52:{33,46}]\n wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0};\t// @[rawFloatFromFN.scala:52:{46,64}]\n wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist};\t// @[Mux.scala:50:70]\n wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn};\t// @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]\n wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1;\t// @[rawFloatFromFN.scala:48:30, :58:14]\n wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2};\t// @[rawFloatFromFN.scala:58:{9,14}]\n wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3};\t// @[rawFloatFromFN.scala:54:10, :57:9, :58:9]\n wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0];\t// @[rawFloatFromFN.scala:57:9]\n wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp;\t// @[rawFloatFromFN.scala:57:9, :68:28]\n wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:48:30, :49:34, :60:30]\n wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero;\t// @[rawFloatFromFN.scala:60:30, :63:19]\n wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7];\t// @[rawFloatFromFN.scala:57:9, :61:32]\n wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T;\t// @[rawFloatFromFN.scala:61:{32,57}]\n wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1;\t// @[rawFloatFromFN.scala:64:28]\n wire _io_out_d_m1_rec_rawIn_out_isInf_T;\t// @[rawFloatFromFN.scala:65:28]\n wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN;\t// @[recFNFromFN.scala:49:20]\n wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1;\t// @[rawFloatFromFN.scala:68:42]\n wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3;\t// @[rawFloatFromFN.scala:70:27]\n wire io_out_d_m1_rec_rawIn_isInf;\t// @[rawFloatFromFN.scala:63:19]\n wire [9:0] io_out_d_m1_rec_rawIn_sExp;\t// @[rawFloatFromFN.scala:63:19]\n wire [24:0] io_out_d_m1_rec_rawIn_sig;\t// @[rawFloatFromFN.scala:63:19]\n wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:49:34, :64:31]\n assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T;\t// @[rawFloatFromFN.scala:61:57, :64:{28,31}]\n assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1;\t// @[rawFloatFromFN.scala:63:19, :64:28]\n assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:49:34, :61:57, :65:28]\n assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T;\t// @[rawFloatFromFN.scala:63:19, :65:28]\n assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T};\t// @[rawFloatFromFN.scala:68:{28,42}]\n assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1;\t// @[rawFloatFromFN.scala:63:19, :68:42]\n wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero;\t// @[rawFloatFromFN.scala:60:30, :70:19]\n wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T};\t// @[rawFloatFromFN.scala:70:{16,19}]\n wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn;\t// @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]\n assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2};\t// @[rawFloatFromFN.scala:70:{16,27,33}]\n assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3;\t// @[rawFloatFromFN.scala:63:19, :70:27]\n wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6];\t// @[recFNFromFN.scala:48:50]\n wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T;\t// @[recFNFromFN.scala:48:{15,50}]\n wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] | _io_out_d_m1_rec_T_2};\t// @[recFNFromFN.scala:48:{15,76}, :49:20]\n wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3};\t// @[recFNFromFN.scala:47:20, :48:76]\n wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0];\t// @[recFNFromFN.scala:50:23]\n wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5};\t// @[recFNFromFN.scala:47:20, :49:45, :50:23]\n wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0];\t// @[recFNFromFN.scala:51:22]\n wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7};\t// @[recFNFromFN.scala:49:45, :50:41, :51:22]\n wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31];\t// @[rawFloatFromFN.scala:44:18]\n wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign;\t// @[rawFloatFromFN.scala:44:18, :63:19]\n wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23];\t// @[rawFloatFromFN.scala:45:19]\n wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0];\t// @[rawFloatFromFN.scala:46:21]\n wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0;\t// @[rawFloatFromFN.scala:45:19, :48:30]\n wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0;\t// @[rawFloatFromFN.scala:46:21, :49:34]\n wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22];\t// @[rawFloatFromFN.scala:46:21]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42;\t// @[Mux.scala:50:70]\n wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43;\t// @[Mux.scala:50:70]\n wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist;\t// @[Mux.scala:50:70]\n wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0];\t// @[rawFloatFromFN.scala:52:{33,46}]\n wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0};\t// @[rawFloatFromFN.scala:52:{46,64}]\n wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist};\t// @[Mux.scala:50:70]\n wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn};\t// @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]\n wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1;\t// @[rawFloatFromFN.scala:48:30, :58:14]\n wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2};\t// @[rawFloatFromFN.scala:58:{9,14}]\n wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3};\t// @[rawFloatFromFN.scala:54:10, :57:9, :58:9]\n wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0];\t// @[rawFloatFromFN.scala:57:9]\n wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp;\t// @[rawFloatFromFN.scala:57:9, :68:28]\n wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:48:30, :49:34, :60:30]\n wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero;\t// @[rawFloatFromFN.scala:60:30, :63:19]\n wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7];\t// @[rawFloatFromFN.scala:57:9, :61:32]\n wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T;\t// @[rawFloatFromFN.scala:61:{32,57}]\n wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1;\t// @[rawFloatFromFN.scala:64:28]\n wire _io_out_d_m2_rec_rawIn_out_isInf_T;\t// @[rawFloatFromFN.scala:65:28]\n wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN;\t// @[recFNFromFN.scala:49:20]\n wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1;\t// @[rawFloatFromFN.scala:68:42]\n wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3;\t// @[rawFloatFromFN.scala:70:27]\n wire io_out_d_m2_rec_rawIn_isInf;\t// @[rawFloatFromFN.scala:63:19]\n wire [9:0] io_out_d_m2_rec_rawIn_sExp;\t// @[rawFloatFromFN.scala:63:19]\n wire [24:0] io_out_d_m2_rec_rawIn_sig;\t// @[rawFloatFromFN.scala:63:19]\n wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:49:34, :64:31]\n assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T;\t// @[rawFloatFromFN.scala:61:57, :64:{28,31}]\n assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1;\t// @[rawFloatFromFN.scala:63:19, :64:28]\n assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:49:34, :61:57, :65:28]\n assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T;\t// @[rawFloatFromFN.scala:63:19, :65:28]\n assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T};\t// @[rawFloatFromFN.scala:68:{28,42}]\n assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1;\t// @[rawFloatFromFN.scala:63:19, :68:42]\n wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero;\t// @[rawFloatFromFN.scala:60:30, :70:19]\n wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T};\t// @[rawFloatFromFN.scala:70:{16,19}]\n wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn;\t// @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]\n assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2};\t// @[rawFloatFromFN.scala:70:{16,27,33}]\n assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3;\t// @[rawFloatFromFN.scala:63:19, :70:27]\n wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6];\t// @[recFNFromFN.scala:48:50]\n wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T;\t// @[recFNFromFN.scala:48:{15,50}]\n wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] | _io_out_d_m2_rec_T_2};\t// @[recFNFromFN.scala:48:{15,76}, :49:20]\n wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3};\t// @[recFNFromFN.scala:47:20, :48:76]\n wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0];\t// @[recFNFromFN.scala:50:23]\n wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5};\t// @[recFNFromFN.scala:47:20, :49:45, :50:23]\n wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0];\t// @[recFNFromFN.scala:51:22]\n wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7};\t// @[recFNFromFN.scala:49:45, :50:41, :51:22]\n wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31];\t// @[rawFloatFromFN.scala:44:18]\n wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign;\t// @[rawFloatFromFN.scala:44:18, :63:19]\n wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23];\t// @[rawFloatFromFN.scala:45:19]\n wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0];\t// @[rawFloatFromFN.scala:46:21]\n wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0;\t// @[rawFloatFromFN.scala:45:19, :48:30]\n wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0;\t// @[rawFloatFromFN.scala:46:21, :49:34]\n wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21];\t// @[rawFloatFromFN.scala:46:21]\n wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22];\t// @[rawFloatFromFN.scala:46:21]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41;\t// @[Mux.scala:50:70]\n wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42;\t// @[Mux.scala:50:70]\n wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43;\t// @[Mux.scala:50:70]\n wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist;\t// @[Mux.scala:50:70]\n wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0];\t// @[rawFloatFromFN.scala:52:{33,46}]\n wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0};\t// @[rawFloatFromFN.scala:52:{46,64}]\n wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist};\t// @[Mux.scala:50:70]\n wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn};\t// @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]\n wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1;\t// @[rawFloatFromFN.scala:48:30, :58:14]\n wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2};\t// @[rawFloatFromFN.scala:58:{9,14}]\n wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3};\t// @[rawFloatFromFN.scala:54:10, :57:9, :58:9]\n wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0];\t// @[rawFloatFromFN.scala:57:9]\n wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp;\t// @[rawFloatFromFN.scala:57:9, :68:28]\n wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:48:30, :49:34, :60:30]\n wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero;\t// @[rawFloatFromFN.scala:60:30, :63:19]\n wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7];\t// @[rawFloatFromFN.scala:57:9, :61:32]\n wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T;\t// @[rawFloatFromFN.scala:61:{32,57}]\n wire _io_out_d_self_rec_rawIn_out_isNaN_T_1;\t// @[rawFloatFromFN.scala:64:28]\n wire _io_out_d_self_rec_rawIn_out_isInf_T;\t// @[rawFloatFromFN.scala:65:28]\n wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN;\t// @[recFNFromFN.scala:49:20]\n wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1;\t// @[rawFloatFromFN.scala:68:42]\n wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3;\t// @[rawFloatFromFN.scala:70:27]\n wire io_out_d_self_rec_rawIn_isInf;\t// @[rawFloatFromFN.scala:63:19]\n wire [9:0] io_out_d_self_rec_rawIn_sExp;\t// @[rawFloatFromFN.scala:63:19]\n wire [24:0] io_out_d_self_rec_rawIn_sig;\t// @[rawFloatFromFN.scala:63:19]\n wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:49:34, :64:31]\n assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T;\t// @[rawFloatFromFN.scala:61:57, :64:{28,31}]\n assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1;\t// @[rawFloatFromFN.scala:63:19, :64:28]\n assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn;\t// @[rawFloatFromFN.scala:49:34, :61:57, :65:28]\n assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T;\t// @[rawFloatFromFN.scala:63:19, :65:28]\n assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T};\t// @[rawFloatFromFN.scala:68:{28,42}]\n assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1;\t// @[rawFloatFromFN.scala:63:19, :68:42]\n wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero;\t// @[rawFloatFromFN.scala:60:30, :70:19]\n wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T};\t// @[rawFloatFromFN.scala:70:{16,19}]\n wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn;\t// @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]\n assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2};\t// @[rawFloatFromFN.scala:70:{16,27,33}]\n assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3;\t// @[rawFloatFromFN.scala:63:19, :70:27]\n wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6];\t// @[recFNFromFN.scala:48:50]\n wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T;\t// @[recFNFromFN.scala:48:{15,50}]\n wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] | _io_out_d_self_rec_T_2};\t// @[recFNFromFN.scala:48:{15,76}, :49:20]\n wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3};\t// @[recFNFromFN.scala:47:20, :48:76]\n wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0];\t// @[recFNFromFN.scala:50:23]\n wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5};\t// @[recFNFromFN.scala:47:20, :49:45, :50:23]\n wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0];\t// @[recFNFromFN.scala:51:22]\n wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7};\t// @[recFNFromFN.scala:49:45, :50:41, :51:22]\n wire [31:0] _io_out_d_out_bits_T;\t// @[fNFromRecFN.scala:66:12]\n assign io_out_d_bits_0 = io_out_d_out_bits;\t// @[PE.scala:14:7]\n wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23];\t// @[rawFloatFromRecFN.scala:51:21]\n wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6];\t// @[rawFloatFromRecFN.scala:51:21, :52:28]\n wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0;\t// @[rawFloatFromRecFN.scala:52:{28,53}]\n wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero;\t// @[rawFloatFromRecFN.scala:52:53, :55:23]\n wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7];\t// @[rawFloatFromRecFN.scala:51:21, :53:28]\n wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T;\t// @[rawFloatFromRecFN.scala:53:{28,53}]\n wire _io_out_d_out_bits_rawIn_out_isNaN_T_1;\t// @[rawFloatFromRecFN.scala:56:33]\n wire _io_out_d_out_bits_rawIn_out_isInf_T_2;\t// @[rawFloatFromRecFN.scala:57:33]\n wire _io_out_d_out_bits_rawIn_out_sign_T;\t// @[rawFloatFromRecFN.scala:59:25]\n wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T;\t// @[rawFloatFromRecFN.scala:60:27]\n wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3;\t// @[rawFloatFromRecFN.scala:61:44]\n wire io_out_d_out_bits_rawIn_isNaN;\t// @[rawFloatFromRecFN.scala:55:23]\n wire io_out_d_out_bits_rawIn_isInf;\t// @[rawFloatFromRecFN.scala:55:23]\n wire io_out_d_out_bits_rawIn_sign;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [9:0] io_out_d_out_bits_rawIn_sExp;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [24:0] io_out_d_out_bits_rawIn_sig;\t// @[rawFloatFromRecFN.scala:55:23]\n wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6];\t// @[rawFloatFromRecFN.scala:51:21, :56:41]\n wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6];\t// @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]\n assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T;\t// @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]\n assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1;\t// @[rawFloatFromRecFN.scala:55:23, :56:33]\n wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T;\t// @[rawFloatFromRecFN.scala:57:{36,41}]\n assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1;\t// @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]\n assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2;\t// @[rawFloatFromRecFN.scala:55:23, :57:33]\n assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32];\t// @[rawFloatFromRecFN.scala:59:25]\n assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T;\t// @[rawFloatFromRecFN.scala:55:23, :59:25]\n assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp};\t// @[rawFloatFromRecFN.scala:51:21, :60:27]\n assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T;\t// @[rawFloatFromRecFN.scala:55:23, :60:27]\n wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero;\t// @[rawFloatFromRecFN.scala:52:53, :61:35]\n wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T};\t// @[rawFloatFromRecFN.scala:61:{32,35}]\n wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0];\t// @[rawFloatFromRecFN.scala:61:49]\n assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2};\t// @[rawFloatFromRecFN.scala:61:{32,44,49}]\n assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3;\t// @[rawFloatFromRecFN.scala:55:23, :61:44]\n wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0];\t// @[rawFloatFromRecFN.scala:55:23]\n wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T};\t// @[fNFromRecFN.scala:52:{35,47}]\n wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0];\t// @[fNFromRecFN.scala:52:35]\n wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1];\t// @[rawFloatFromRecFN.scala:55:23]\n wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist;\t// @[fNFromRecFN.scala:52:35, :53:{38,42}]\n wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0];\t// @[fNFromRecFN.scala:53:{42,60}]\n wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0];\t// @[rawFloatFromRecFN.scala:55:23]\n wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81;\t// @[fNFromRecFN.scala:58:{27,45}]\n wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0];\t// @[fNFromRecFN.scala:58:45]\n wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2;\t// @[fNFromRecFN.scala:51:38, :56:16, :58:45]\n wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN | io_out_d_out_bits_rawIn_isInf;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}};\t// @[fNFromRecFN.scala:60:{21,44}]\n wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 | _io_out_d_out_bits_expOut_T_5;\t// @[fNFromRecFN.scala:56:16, :60:{15,21}]\n wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0];\t// @[rawFloatFromRecFN.scala:55:23]\n wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1;\t// @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]\n wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut};\t// @[rawFloatFromRecFN.scala:55:23]\n assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut};\t// @[fNFromRecFN.scala:62:16, :66:12]\n assign io_out_d_out_bits = _io_out_d_out_bits_T;\t// @[fNFromRecFN.scala:66:12]\n RecFNToRecFN_174 io_out_d_m1_resizer (\t// @[Arithmetic.scala:362:32]\n .io_in (io_out_d_m1_rec),\t// @[recFNFromFN.scala:50:41]\n .io_out (_io_out_d_m1_resizer_io_out)\n );\t// @[Arithmetic.scala:362:32]\n RecFNToRecFN_175 io_out_d_m2_resizer (\t// @[Arithmetic.scala:369:32]\n .io_in (io_out_d_m2_rec),\t// @[recFNFromFN.scala:50:41]\n .io_out (_io_out_d_m2_resizer_io_out)\n );\t// @[Arithmetic.scala:369:32]\n MulAddRecFN_e8_s24_69 io_out_d_muladder (\t// @[Arithmetic.scala:376:30]\n .io_a (_io_out_d_m1_resizer_io_out),\t// @[Arithmetic.scala:362:32]\n .io_b (_io_out_d_m2_resizer_io_out),\t// @[Arithmetic.scala:369:32]\n .io_c (io_out_d_self_rec),\t// @[recFNFromFN.scala:50:41]\n .io_out (_io_out_d_muladder_io_out)\n );\t// @[Arithmetic.scala:376:30]\n assign io_out_d_bits = io_out_d_bits_0;\t// @[PE.scala:14:7]\nendmodule"}}},{"rowIdx":32166,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) \n node _source_ok_T_1 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) \n node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) \n node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) \n node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) \n node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) \n node _source_ok_T_7 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) \n node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) \n node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) \n node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) \n node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) \n node _source_ok_T_13 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) \n node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) \n node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) \n node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) \n node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) \n node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) \n node _source_ok_T_19 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) \n node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) \n node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) \n node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) \n node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) \n node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n wire _source_ok_WIRE : UInt<1>[10] \n connect _source_ok_WIRE[0], _source_ok_T \n connect _source_ok_WIRE[1], _source_ok_T_6 \n connect _source_ok_WIRE[2], _source_ok_T_12 \n connect _source_ok_WIRE[3], _source_ok_T_18 \n connect _source_ok_WIRE[4], _source_ok_T_24 \n connect _source_ok_WIRE[5], _source_ok_T_25 \n connect _source_ok_WIRE[6], _source_ok_T_26 \n connect _source_ok_WIRE[7], _source_ok_T_27 \n connect _source_ok_WIRE[8], _source_ok_T_28 \n connect _source_ok_WIRE[9], _source_ok_T_29 \n node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) \n node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2]) \n node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3]) \n node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4]) \n node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5]) \n node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6]) \n node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7]) \n node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8]) \n node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9]) \n node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_7 = cvt(_T_6) \n node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) \n node _T_9 = asSInt(_T_8) \n node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) \n node _T_11 = or(_T_5, _T_10) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 1, 0) \n node _T_12 = shr(io.in.a.bits.source, 2) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n node _T_14 = leq(UInt<1>(0h0), uncommonBits) \n node _T_15 = and(_T_13, _T_14) \n node _T_16 = leq(uncommonBits, UInt<2>(0h3)) \n node _T_17 = and(_T_15, _T_16) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_20 = cvt(_T_19) \n node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) \n node _T_22 = asSInt(_T_21) \n node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) \n node _T_24 = or(_T_18, _T_23) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) \n node _T_25 = shr(io.in.a.bits.source, 2) \n node _T_26 = eq(_T_25, UInt<1>(0h1)) \n node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_28 = and(_T_26, _T_27) \n node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) \n node _T_30 = and(_T_28, _T_29) \n node _T_31 = eq(_T_30, UInt<1>(0h0)) \n node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_33 = cvt(_T_32) \n node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) \n node _T_35 = asSInt(_T_34) \n node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) \n node _T_37 = or(_T_31, _T_36) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) \n node _T_38 = shr(io.in.a.bits.source, 2) \n node _T_39 = eq(_T_38, UInt<2>(0h2)) \n node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_41 = and(_T_39, _T_40) \n node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) \n node _T_43 = and(_T_41, _T_42) \n node _T_44 = eq(_T_43, UInt<1>(0h0)) \n node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_46 = cvt(_T_45) \n node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) \n node _T_48 = asSInt(_T_47) \n node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) \n node _T_50 = or(_T_44, _T_49) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) \n node _T_51 = shr(io.in.a.bits.source, 2) \n node _T_52 = eq(_T_51, UInt<2>(0h3)) \n node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_54 = and(_T_52, _T_53) \n node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) \n node _T_56 = and(_T_54, _T_55) \n node _T_57 = eq(_T_56, UInt<1>(0h0)) \n node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_59 = cvt(_T_58) \n node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) \n node _T_61 = asSInt(_T_60) \n node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) \n node _T_63 = or(_T_57, _T_62) \n node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_65 = eq(_T_64, UInt<1>(0h0)) \n node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_67 = cvt(_T_66) \n node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) \n node _T_69 = asSInt(_T_68) \n node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) \n node _T_71 = or(_T_65, _T_70) \n node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_73 = eq(_T_72, UInt<1>(0h0)) \n node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_75 = cvt(_T_74) \n node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) \n node _T_77 = asSInt(_T_76) \n node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) \n node _T_79 = or(_T_73, _T_78) \n node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_81 = eq(_T_80, UInt<1>(0h0)) \n node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_83 = cvt(_T_82) \n node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) \n node _T_85 = asSInt(_T_84) \n node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) \n node _T_87 = or(_T_81, _T_86) \n node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_89 = eq(_T_88, UInt<1>(0h0)) \n node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_91 = cvt(_T_90) \n node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) \n node _T_93 = asSInt(_T_92) \n node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) \n node _T_95 = or(_T_89, _T_94) \n node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_97 = eq(_T_96, UInt<1>(0h0)) \n node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_99 = cvt(_T_98) \n node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) \n node _T_101 = asSInt(_T_100) \n node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) \n node _T_103 = or(_T_97, _T_102) \n node _T_104 = and(_T_11, _T_24) \n node _T_105 = and(_T_104, _T_37) \n node _T_106 = and(_T_105, _T_50) \n node _T_107 = and(_T_106, _T_63) \n node _T_108 = and(_T_107, _T_71) \n node _T_109 = and(_T_108, _T_79) \n node _T_110 = and(_T_109, _T_87) \n node _T_111 = and(_T_110, _T_95) \n node _T_112 = and(_T_111, _T_103) \n node _T_113 = asUInt(reset) \n node _T_114 = eq(_T_113, UInt<1>(0h0)) \n when _T_114 : \n node _T_115 = eq(_T_112, UInt<1>(0h0)) \n when _T_115 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_112, UInt<1>(0h1), \"\") : assert_1 \n node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_116 : \n node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_119 = and(_T_117, _T_118) \n node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) \n node _T_121 = shr(io.in.a.bits.source, 2) \n node _T_122 = eq(_T_121, UInt<1>(0h0)) \n node _T_123 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_124 = and(_T_122, _T_123) \n node _T_125 = leq(uncommonBits_4, UInt<2>(0h3)) \n node _T_126 = and(_T_124, _T_125) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) \n node _T_127 = shr(io.in.a.bits.source, 2) \n node _T_128 = eq(_T_127, UInt<1>(0h1)) \n node _T_129 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_130 = and(_T_128, _T_129) \n node _T_131 = leq(uncommonBits_5, UInt<2>(0h3)) \n node _T_132 = and(_T_130, _T_131) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) \n node _T_133 = shr(io.in.a.bits.source, 2) \n node _T_134 = eq(_T_133, UInt<2>(0h2)) \n node _T_135 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_136 = and(_T_134, _T_135) \n node _T_137 = leq(uncommonBits_6, UInt<2>(0h3)) \n node _T_138 = and(_T_136, _T_137) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) \n node _T_139 = shr(io.in.a.bits.source, 2) \n node _T_140 = eq(_T_139, UInt<2>(0h3)) \n node _T_141 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_142 = and(_T_140, _T_141) \n node _T_143 = leq(uncommonBits_7, UInt<2>(0h3)) \n node _T_144 = and(_T_142, _T_143) \n node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_150 = or(_T_120, _T_126) \n node _T_151 = or(_T_150, _T_132) \n node _T_152 = or(_T_151, _T_138) \n node _T_153 = or(_T_152, _T_144) \n node _T_154 = or(_T_153, _T_145) \n node _T_155 = or(_T_154, _T_146) \n node _T_156 = or(_T_155, _T_147) \n node _T_157 = or(_T_156, _T_148) \n node _T_158 = or(_T_157, _T_149) \n node _T_159 = and(_T_119, _T_158) \n node _T_160 = or(UInt<1>(0h0), _T_159) \n node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_162 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_163 = cvt(_T_162) \n node _T_164 = and(_T_163, asSInt(UInt<13>(0h1000))) \n node _T_165 = asSInt(_T_164) \n node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) \n node _T_167 = and(_T_161, _T_166) \n node _T_168 = or(UInt<1>(0h0), _T_167) \n node _T_169 = and(_T_160, _T_168) \n node _T_170 = asUInt(reset) \n node _T_171 = eq(_T_170, UInt<1>(0h0)) \n when _T_171 : \n node _T_172 = eq(_T_169, UInt<1>(0h0)) \n when _T_172 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_169, UInt<1>(0h1), \"\") : assert_2 \n node _T_173 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) \n node _T_174 = shr(io.in.a.bits.source, 2) \n node _T_175 = eq(_T_174, UInt<1>(0h0)) \n node _T_176 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_177 = and(_T_175, _T_176) \n node _T_178 = leq(uncommonBits_8, UInt<2>(0h3)) \n node _T_179 = and(_T_177, _T_178) \n node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) \n node _T_180 = shr(io.in.a.bits.source, 2) \n node _T_181 = eq(_T_180, UInt<1>(0h1)) \n node _T_182 = leq(UInt<1>(0h0), uncommonBits_9) \n node _T_183 = and(_T_181, _T_182) \n node _T_184 = leq(uncommonBits_9, UInt<2>(0h3)) \n node _T_185 = and(_T_183, _T_184) \n node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) \n node _T_186 = shr(io.in.a.bits.source, 2) \n node _T_187 = eq(_T_186, UInt<2>(0h2)) \n node _T_188 = leq(UInt<1>(0h0), uncommonBits_10) \n node _T_189 = and(_T_187, _T_188) \n node _T_190 = leq(uncommonBits_10, UInt<2>(0h3)) \n node _T_191 = and(_T_189, _T_190) \n node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) \n node _T_192 = shr(io.in.a.bits.source, 2) \n node _T_193 = eq(_T_192, UInt<2>(0h3)) \n node _T_194 = leq(UInt<1>(0h0), uncommonBits_11) \n node _T_195 = and(_T_193, _T_194) \n node _T_196 = leq(uncommonBits_11, UInt<2>(0h3)) \n node _T_197 = and(_T_195, _T_196) \n node _T_198 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_201 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_202 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n wire _WIRE : UInt<1>[10] \n connect _WIRE[0], _T_173 \n connect _WIRE[1], _T_179 \n connect _WIRE[2], _T_185 \n connect _WIRE[3], _T_191 \n connect _WIRE[4], _T_197 \n connect _WIRE[5], _T_198 \n connect _WIRE[6], _T_199 \n connect _WIRE[7], _T_200 \n connect _WIRE[8], _T_201 \n connect _WIRE[9], _T_202 \n node _T_203 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_204 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_205 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_206 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_207 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_208 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_209 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_210 = mux(_WIRE[6], _T_203, UInt<1>(0h0)) \n node _T_211 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_212 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_213 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_214 = or(_T_204, _T_205) \n node _T_215 = or(_T_214, _T_206) \n node _T_216 = or(_T_215, _T_207) \n node _T_217 = or(_T_216, _T_208) \n node _T_218 = or(_T_217, _T_209) \n node _T_219 = or(_T_218, _T_210) \n node _T_220 = or(_T_219, _T_211) \n node _T_221 = or(_T_220, _T_212) \n node _T_222 = or(_T_221, _T_213) \n wire _WIRE_1 : UInt<1> \n connect _WIRE_1, _T_222 \n node _T_223 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_224 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_225 = and(_T_223, _T_224) \n node _T_226 = or(UInt<1>(0h0), _T_225) \n node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_228 = cvt(_T_227) \n node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) \n node _T_230 = asSInt(_T_229) \n node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) \n node _T_232 = and(_T_226, _T_231) \n node _T_233 = or(UInt<1>(0h0), _T_232) \n node _T_234 = and(_WIRE_1, _T_233) \n node _T_235 = asUInt(reset) \n node _T_236 = eq(_T_235, UInt<1>(0h0)) \n when _T_236 : \n node _T_237 = eq(_T_234, UInt<1>(0h0)) \n when _T_237 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_234, UInt<1>(0h1), \"\") : assert_3 \n node _T_238 = asUInt(reset) \n node _T_239 = eq(_T_238, UInt<1>(0h0)) \n when _T_239 : \n node _T_240 = eq(source_ok, UInt<1>(0h0)) \n when _T_240 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_4 \n node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_242 = asUInt(reset) \n node _T_243 = eq(_T_242, UInt<1>(0h0)) \n when _T_243 : \n node _T_244 = eq(_T_241, UInt<1>(0h0)) \n when _T_244 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_241, UInt<1>(0h1), \"\") : assert_5 \n node _T_245 = asUInt(reset) \n node _T_246 = eq(_T_245, UInt<1>(0h0)) \n when _T_246 : \n node _T_247 = eq(is_aligned, UInt<1>(0h0)) \n when _T_247 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_249 = asUInt(reset) \n node _T_250 = eq(_T_249, UInt<1>(0h0)) \n when _T_250 : \n node _T_251 = eq(_T_248, UInt<1>(0h0)) \n when _T_251 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_248, UInt<1>(0h1), \"\") : assert_7 \n node _T_252 = not(io.in.a.bits.mask) \n node _T_253 = eq(_T_252, UInt<1>(0h0)) \n node _T_254 = asUInt(reset) \n node _T_255 = eq(_T_254, UInt<1>(0h0)) \n when _T_255 : \n node _T_256 = eq(_T_253, UInt<1>(0h0)) \n when _T_256 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_253, UInt<1>(0h1), \"\") : assert_8 \n node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_258 = asUInt(reset) \n node _T_259 = eq(_T_258, UInt<1>(0h0)) \n when _T_259 : \n node _T_260 = eq(_T_257, UInt<1>(0h0)) \n when _T_260 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_257, UInt<1>(0h1), \"\") : assert_9 \n node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_261 : \n node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_264 = and(_T_262, _T_263) \n node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) \n node _T_266 = shr(io.in.a.bits.source, 2) \n node _T_267 = eq(_T_266, UInt<1>(0h0)) \n node _T_268 = leq(UInt<1>(0h0), uncommonBits_12) \n node _T_269 = and(_T_267, _T_268) \n node _T_270 = leq(uncommonBits_12, UInt<2>(0h3)) \n node _T_271 = and(_T_269, _T_270) \n node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) \n node _T_272 = shr(io.in.a.bits.source, 2) \n node _T_273 = eq(_T_272, UInt<1>(0h1)) \n node _T_274 = leq(UInt<1>(0h0), uncommonBits_13) \n node _T_275 = and(_T_273, _T_274) \n node _T_276 = leq(uncommonBits_13, UInt<2>(0h3)) \n node _T_277 = and(_T_275, _T_276) \n node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) \n node _T_278 = shr(io.in.a.bits.source, 2) \n node _T_279 = eq(_T_278, UInt<2>(0h2)) \n node _T_280 = leq(UInt<1>(0h0), uncommonBits_14) \n node _T_281 = and(_T_279, _T_280) \n node _T_282 = leq(uncommonBits_14, UInt<2>(0h3)) \n node _T_283 = and(_T_281, _T_282) \n node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) \n node _T_284 = shr(io.in.a.bits.source, 2) \n node _T_285 = eq(_T_284, UInt<2>(0h3)) \n node _T_286 = leq(UInt<1>(0h0), uncommonBits_15) \n node _T_287 = and(_T_285, _T_286) \n node _T_288 = leq(uncommonBits_15, UInt<2>(0h3)) \n node _T_289 = and(_T_287, _T_288) \n node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_295 = or(_T_265, _T_271) \n node _T_296 = or(_T_295, _T_277) \n node _T_297 = or(_T_296, _T_283) \n node _T_298 = or(_T_297, _T_289) \n node _T_299 = or(_T_298, _T_290) \n node _T_300 = or(_T_299, _T_291) \n node _T_301 = or(_T_300, _T_292) \n node _T_302 = or(_T_301, _T_293) \n node _T_303 = or(_T_302, _T_294) \n node _T_304 = and(_T_264, _T_303) \n node _T_305 = or(UInt<1>(0h0), _T_304) \n node _T_306 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_307 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_308 = cvt(_T_307) \n node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000))) \n node _T_310 = asSInt(_T_309) \n node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) \n node _T_312 = and(_T_306, _T_311) \n node _T_313 = or(UInt<1>(0h0), _T_312) \n node _T_314 = and(_T_305, _T_313) \n node _T_315 = asUInt(reset) \n node _T_316 = eq(_T_315, UInt<1>(0h0)) \n when _T_316 : \n node _T_317 = eq(_T_314, UInt<1>(0h0)) \n when _T_317 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_314, UInt<1>(0h1), \"\") : assert_10 \n node _T_318 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) \n node _T_319 = shr(io.in.a.bits.source, 2) \n node _T_320 = eq(_T_319, UInt<1>(0h0)) \n node _T_321 = leq(UInt<1>(0h0), uncommonBits_16) \n node _T_322 = and(_T_320, _T_321) \n node _T_323 = leq(uncommonBits_16, UInt<2>(0h3)) \n node _T_324 = and(_T_322, _T_323) \n node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) \n node _T_325 = shr(io.in.a.bits.source, 2) \n node _T_326 = eq(_T_325, UInt<1>(0h1)) \n node _T_327 = leq(UInt<1>(0h0), uncommonBits_17) \n node _T_328 = and(_T_326, _T_327) \n node _T_329 = leq(uncommonBits_17, UInt<2>(0h3)) \n node _T_330 = and(_T_328, _T_329) \n node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) \n node _T_331 = shr(io.in.a.bits.source, 2) \n node _T_332 = eq(_T_331, UInt<2>(0h2)) \n node _T_333 = leq(UInt<1>(0h0), uncommonBits_18) \n node _T_334 = and(_T_332, _T_333) \n node _T_335 = leq(uncommonBits_18, UInt<2>(0h3)) \n node _T_336 = and(_T_334, _T_335) \n node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) \n node _T_337 = shr(io.in.a.bits.source, 2) \n node _T_338 = eq(_T_337, UInt<2>(0h3)) \n node _T_339 = leq(UInt<1>(0h0), uncommonBits_19) \n node _T_340 = and(_T_338, _T_339) \n node _T_341 = leq(uncommonBits_19, UInt<2>(0h3)) \n node _T_342 = and(_T_340, _T_341) \n node _T_343 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n wire _WIRE_2 : UInt<1>[10] \n connect _WIRE_2[0], _T_318 \n connect _WIRE_2[1], _T_324 \n connect _WIRE_2[2], _T_330 \n connect _WIRE_2[3], _T_336 \n connect _WIRE_2[4], _T_342 \n connect _WIRE_2[5], _T_343 \n connect _WIRE_2[6], _T_344 \n connect _WIRE_2[7], _T_345 \n connect _WIRE_2[8], _T_346 \n connect _WIRE_2[9], _T_347 \n node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_349 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_350 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_351 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_352 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_353 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_354 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_355 = mux(_WIRE_2[6], _T_348, UInt<1>(0h0)) \n node _T_356 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_357 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_358 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_359 = or(_T_349, _T_350) \n node _T_360 = or(_T_359, _T_351) \n node _T_361 = or(_T_360, _T_352) \n node _T_362 = or(_T_361, _T_353) \n node _T_363 = or(_T_362, _T_354) \n node _T_364 = or(_T_363, _T_355) \n node _T_365 = or(_T_364, _T_356) \n node _T_366 = or(_T_365, _T_357) \n node _T_367 = or(_T_366, _T_358) \n wire _WIRE_3 : UInt<1> \n connect _WIRE_3, _T_367 \n node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_370 = and(_T_368, _T_369) \n node _T_371 = or(UInt<1>(0h0), _T_370) \n node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_373 = cvt(_T_372) \n node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) \n node _T_375 = asSInt(_T_374) \n node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) \n node _T_377 = and(_T_371, _T_376) \n node _T_378 = or(UInt<1>(0h0), _T_377) \n node _T_379 = and(_WIRE_3, _T_378) \n node _T_380 = asUInt(reset) \n node _T_381 = eq(_T_380, UInt<1>(0h0)) \n when _T_381 : \n node _T_382 = eq(_T_379, UInt<1>(0h0)) \n when _T_382 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_379, UInt<1>(0h1), \"\") : assert_11 \n node _T_383 = asUInt(reset) \n node _T_384 = eq(_T_383, UInt<1>(0h0)) \n when _T_384 : \n node _T_385 = eq(source_ok, UInt<1>(0h0)) \n when _T_385 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_12 \n node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_387 = asUInt(reset) \n node _T_388 = eq(_T_387, UInt<1>(0h0)) \n when _T_388 : \n node _T_389 = eq(_T_386, UInt<1>(0h0)) \n when _T_389 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_386, UInt<1>(0h1), \"\") : assert_13 \n node _T_390 = asUInt(reset) \n node _T_391 = eq(_T_390, UInt<1>(0h0)) \n when _T_391 : \n node _T_392 = eq(is_aligned, UInt<1>(0h0)) \n when _T_392 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_394 = asUInt(reset) \n node _T_395 = eq(_T_394, UInt<1>(0h0)) \n when _T_395 : \n node _T_396 = eq(_T_393, UInt<1>(0h0)) \n when _T_396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_393, UInt<1>(0h1), \"\") : assert_15 \n node _T_397 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_398 = asUInt(reset) \n node _T_399 = eq(_T_398, UInt<1>(0h0)) \n when _T_399 : \n node _T_400 = eq(_T_397, UInt<1>(0h0)) \n when _T_400 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_397, UInt<1>(0h1), \"\") : assert_16 \n node _T_401 = not(io.in.a.bits.mask) \n node _T_402 = eq(_T_401, UInt<1>(0h0)) \n node _T_403 = asUInt(reset) \n node _T_404 = eq(_T_403, UInt<1>(0h0)) \n when _T_404 : \n node _T_405 = eq(_T_402, UInt<1>(0h0)) \n when _T_405 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_402, UInt<1>(0h1), \"\") : assert_17 \n node _T_406 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_407 = asUInt(reset) \n node _T_408 = eq(_T_407, UInt<1>(0h0)) \n when _T_408 : \n node _T_409 = eq(_T_406, UInt<1>(0h0)) \n when _T_409 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_406, UInt<1>(0h1), \"\") : assert_18 \n node _T_410 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_410 : \n node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_413 = and(_T_411, _T_412) \n node _T_414 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) \n node _T_415 = shr(io.in.a.bits.source, 2) \n node _T_416 = eq(_T_415, UInt<1>(0h0)) \n node _T_417 = leq(UInt<1>(0h0), uncommonBits_20) \n node _T_418 = and(_T_416, _T_417) \n node _T_419 = leq(uncommonBits_20, UInt<2>(0h3)) \n node _T_420 = and(_T_418, _T_419) \n node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) \n node _T_421 = shr(io.in.a.bits.source, 2) \n node _T_422 = eq(_T_421, UInt<1>(0h1)) \n node _T_423 = leq(UInt<1>(0h0), uncommonBits_21) \n node _T_424 = and(_T_422, _T_423) \n node _T_425 = leq(uncommonBits_21, UInt<2>(0h3)) \n node _T_426 = and(_T_424, _T_425) \n node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) \n node _T_427 = shr(io.in.a.bits.source, 2) \n node _T_428 = eq(_T_427, UInt<2>(0h2)) \n node _T_429 = leq(UInt<1>(0h0), uncommonBits_22) \n node _T_430 = and(_T_428, _T_429) \n node _T_431 = leq(uncommonBits_22, UInt<2>(0h3)) \n node _T_432 = and(_T_430, _T_431) \n node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) \n node _T_433 = shr(io.in.a.bits.source, 2) \n node _T_434 = eq(_T_433, UInt<2>(0h3)) \n node _T_435 = leq(UInt<1>(0h0), uncommonBits_23) \n node _T_436 = and(_T_434, _T_435) \n node _T_437 = leq(uncommonBits_23, UInt<2>(0h3)) \n node _T_438 = and(_T_436, _T_437) \n node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_444 = or(_T_414, _T_420) \n node _T_445 = or(_T_444, _T_426) \n node _T_446 = or(_T_445, _T_432) \n node _T_447 = or(_T_446, _T_438) \n node _T_448 = or(_T_447, _T_439) \n node _T_449 = or(_T_448, _T_440) \n node _T_450 = or(_T_449, _T_441) \n node _T_451 = or(_T_450, _T_442) \n node _T_452 = or(_T_451, _T_443) \n node _T_453 = and(_T_413, _T_452) \n node _T_454 = or(UInt<1>(0h0), _T_453) \n node _T_455 = asUInt(reset) \n node _T_456 = eq(_T_455, UInt<1>(0h0)) \n when _T_456 : \n node _T_457 = eq(_T_454, UInt<1>(0h0)) \n when _T_457 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_454, UInt<1>(0h1), \"\") : assert_19 \n node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_459 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_460 = and(_T_458, _T_459) \n node _T_461 = or(UInt<1>(0h0), _T_460) \n node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_463 = cvt(_T_462) \n node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) \n node _T_465 = asSInt(_T_464) \n node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) \n node _T_467 = and(_T_461, _T_466) \n node _T_468 = or(UInt<1>(0h0), _T_467) \n node _T_469 = asUInt(reset) \n node _T_470 = eq(_T_469, UInt<1>(0h0)) \n when _T_470 : \n node _T_471 = eq(_T_468, UInt<1>(0h0)) \n when _T_471 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_468, UInt<1>(0h1), \"\") : assert_20 \n node _T_472 = asUInt(reset) \n node _T_473 = eq(_T_472, UInt<1>(0h0)) \n when _T_473 : \n node _T_474 = eq(source_ok, UInt<1>(0h0)) \n when _T_474 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_21 \n node _T_475 = asUInt(reset) \n node _T_476 = eq(_T_475, UInt<1>(0h0)) \n when _T_476 : \n node _T_477 = eq(is_aligned, UInt<1>(0h0)) \n when _T_477 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_478 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_479 = asUInt(reset) \n node _T_480 = eq(_T_479, UInt<1>(0h0)) \n when _T_480 : \n node _T_481 = eq(_T_478, UInt<1>(0h0)) \n when _T_481 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_478, UInt<1>(0h1), \"\") : assert_23 \n node _T_482 = eq(io.in.a.bits.mask, mask) \n node _T_483 = asUInt(reset) \n node _T_484 = eq(_T_483, UInt<1>(0h0)) \n when _T_484 : \n node _T_485 = eq(_T_482, UInt<1>(0h0)) \n when _T_485 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_482, UInt<1>(0h1), \"\") : assert_24 \n node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_487 = asUInt(reset) \n node _T_488 = eq(_T_487, UInt<1>(0h0)) \n when _T_488 : \n node _T_489 = eq(_T_486, UInt<1>(0h0)) \n when _T_489 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_486, UInt<1>(0h1), \"\") : assert_25 \n node _T_490 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_490 : \n node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_493 = and(_T_491, _T_492) \n node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) \n node _T_495 = shr(io.in.a.bits.source, 2) \n node _T_496 = eq(_T_495, UInt<1>(0h0)) \n node _T_497 = leq(UInt<1>(0h0), uncommonBits_24) \n node _T_498 = and(_T_496, _T_497) \n node _T_499 = leq(uncommonBits_24, UInt<2>(0h3)) \n node _T_500 = and(_T_498, _T_499) \n node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) \n node _T_501 = shr(io.in.a.bits.source, 2) \n node _T_502 = eq(_T_501, UInt<1>(0h1)) \n node _T_503 = leq(UInt<1>(0h0), uncommonBits_25) \n node _T_504 = and(_T_502, _T_503) \n node _T_505 = leq(uncommonBits_25, UInt<2>(0h3)) \n node _T_506 = and(_T_504, _T_505) \n node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) \n node _T_507 = shr(io.in.a.bits.source, 2) \n node _T_508 = eq(_T_507, UInt<2>(0h2)) \n node _T_509 = leq(UInt<1>(0h0), uncommonBits_26) \n node _T_510 = and(_T_508, _T_509) \n node _T_511 = leq(uncommonBits_26, UInt<2>(0h3)) \n node _T_512 = and(_T_510, _T_511) \n node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) \n node _T_513 = shr(io.in.a.bits.source, 2) \n node _T_514 = eq(_T_513, UInt<2>(0h3)) \n node _T_515 = leq(UInt<1>(0h0), uncommonBits_27) \n node _T_516 = and(_T_514, _T_515) \n node _T_517 = leq(uncommonBits_27, UInt<2>(0h3)) \n node _T_518 = and(_T_516, _T_517) \n node _T_519 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_524 = or(_T_494, _T_500) \n node _T_525 = or(_T_524, _T_506) \n node _T_526 = or(_T_525, _T_512) \n node _T_527 = or(_T_526, _T_518) \n node _T_528 = or(_T_527, _T_519) \n node _T_529 = or(_T_528, _T_520) \n node _T_530 = or(_T_529, _T_521) \n node _T_531 = or(_T_530, _T_522) \n node _T_532 = or(_T_531, _T_523) \n node _T_533 = and(_T_493, _T_532) \n node _T_534 = or(UInt<1>(0h0), _T_533) \n node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_536 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_537 = and(_T_535, _T_536) \n node _T_538 = or(UInt<1>(0h0), _T_537) \n node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_540 = cvt(_T_539) \n node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) \n node _T_542 = asSInt(_T_541) \n node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) \n node _T_544 = and(_T_538, _T_543) \n node _T_545 = or(UInt<1>(0h0), _T_544) \n node _T_546 = and(_T_534, _T_545) \n node _T_547 = asUInt(reset) \n node _T_548 = eq(_T_547, UInt<1>(0h0)) \n when _T_548 : \n node _T_549 = eq(_T_546, UInt<1>(0h0)) \n when _T_549 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_546, UInt<1>(0h1), \"\") : assert_26 \n node _T_550 = asUInt(reset) \n node _T_551 = eq(_T_550, UInt<1>(0h0)) \n when _T_551 : \n node _T_552 = eq(source_ok, UInt<1>(0h0)) \n when _T_552 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_27 \n node _T_553 = asUInt(reset) \n node _T_554 = eq(_T_553, UInt<1>(0h0)) \n when _T_554 : \n node _T_555 = eq(is_aligned, UInt<1>(0h0)) \n when _T_555 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_556 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_557 = asUInt(reset) \n node _T_558 = eq(_T_557, UInt<1>(0h0)) \n when _T_558 : \n node _T_559 = eq(_T_556, UInt<1>(0h0)) \n when _T_559 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_556, UInt<1>(0h1), \"\") : assert_29 \n node _T_560 = eq(io.in.a.bits.mask, mask) \n node _T_561 = asUInt(reset) \n node _T_562 = eq(_T_561, UInt<1>(0h0)) \n when _T_562 : \n node _T_563 = eq(_T_560, UInt<1>(0h0)) \n when _T_563 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_560, UInt<1>(0h1), \"\") : assert_30 \n node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_564 : \n node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_567 = and(_T_565, _T_566) \n node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) \n node _T_569 = shr(io.in.a.bits.source, 2) \n node _T_570 = eq(_T_569, UInt<1>(0h0)) \n node _T_571 = leq(UInt<1>(0h0), uncommonBits_28) \n node _T_572 = and(_T_570, _T_571) \n node _T_573 = leq(uncommonBits_28, UInt<2>(0h3)) \n node _T_574 = and(_T_572, _T_573) \n node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) \n node _T_575 = shr(io.in.a.bits.source, 2) \n node _T_576 = eq(_T_575, UInt<1>(0h1)) \n node _T_577 = leq(UInt<1>(0h0), uncommonBits_29) \n node _T_578 = and(_T_576, _T_577) \n node _T_579 = leq(uncommonBits_29, UInt<2>(0h3)) \n node _T_580 = and(_T_578, _T_579) \n node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) \n node _T_581 = shr(io.in.a.bits.source, 2) \n node _T_582 = eq(_T_581, UInt<2>(0h2)) \n node _T_583 = leq(UInt<1>(0h0), uncommonBits_30) \n node _T_584 = and(_T_582, _T_583) \n node _T_585 = leq(uncommonBits_30, UInt<2>(0h3)) \n node _T_586 = and(_T_584, _T_585) \n node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) \n node _T_587 = shr(io.in.a.bits.source, 2) \n node _T_588 = eq(_T_587, UInt<2>(0h3)) \n node _T_589 = leq(UInt<1>(0h0), uncommonBits_31) \n node _T_590 = and(_T_588, _T_589) \n node _T_591 = leq(uncommonBits_31, UInt<2>(0h3)) \n node _T_592 = and(_T_590, _T_591) \n node _T_593 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_598 = or(_T_568, _T_574) \n node _T_599 = or(_T_598, _T_580) \n node _T_600 = or(_T_599, _T_586) \n node _T_601 = or(_T_600, _T_592) \n node _T_602 = or(_T_601, _T_593) \n node _T_603 = or(_T_602, _T_594) \n node _T_604 = or(_T_603, _T_595) \n node _T_605 = or(_T_604, _T_596) \n node _T_606 = or(_T_605, _T_597) \n node _T_607 = and(_T_567, _T_606) \n node _T_608 = or(UInt<1>(0h0), _T_607) \n node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_611 = and(_T_609, _T_610) \n node _T_612 = or(UInt<1>(0h0), _T_611) \n node _T_613 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_614 = cvt(_T_613) \n node _T_615 = and(_T_614, asSInt(UInt<13>(0h1000))) \n node _T_616 = asSInt(_T_615) \n node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) \n node _T_618 = and(_T_612, _T_617) \n node _T_619 = or(UInt<1>(0h0), _T_618) \n node _T_620 = and(_T_608, _T_619) \n node _T_621 = asUInt(reset) \n node _T_622 = eq(_T_621, UInt<1>(0h0)) \n when _T_622 : \n node _T_623 = eq(_T_620, UInt<1>(0h0)) \n when _T_623 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_620, UInt<1>(0h1), \"\") : assert_31 \n node _T_624 = asUInt(reset) \n node _T_625 = eq(_T_624, UInt<1>(0h0)) \n when _T_625 : \n node _T_626 = eq(source_ok, UInt<1>(0h0)) \n when _T_626 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_32 \n node _T_627 = asUInt(reset) \n node _T_628 = eq(_T_627, UInt<1>(0h0)) \n when _T_628 : \n node _T_629 = eq(is_aligned, UInt<1>(0h0)) \n when _T_629 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_630 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_631 = asUInt(reset) \n node _T_632 = eq(_T_631, UInt<1>(0h0)) \n when _T_632 : \n node _T_633 = eq(_T_630, UInt<1>(0h0)) \n when _T_633 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_630, UInt<1>(0h1), \"\") : assert_34 \n node _T_634 = not(mask) \n node _T_635 = and(io.in.a.bits.mask, _T_634) \n node _T_636 = eq(_T_635, UInt<1>(0h0)) \n node _T_637 = asUInt(reset) \n node _T_638 = eq(_T_637, UInt<1>(0h0)) \n when _T_638 : \n node _T_639 = eq(_T_636, UInt<1>(0h0)) \n when _T_639 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_636, UInt<1>(0h1), \"\") : assert_35 \n node _T_640 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_640 : \n node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_643 = and(_T_641, _T_642) \n node _T_644 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) \n node _T_645 = shr(io.in.a.bits.source, 2) \n node _T_646 = eq(_T_645, UInt<1>(0h0)) \n node _T_647 = leq(UInt<1>(0h0), uncommonBits_32) \n node _T_648 = and(_T_646, _T_647) \n node _T_649 = leq(uncommonBits_32, UInt<2>(0h3)) \n node _T_650 = and(_T_648, _T_649) \n node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) \n node _T_651 = shr(io.in.a.bits.source, 2) \n node _T_652 = eq(_T_651, UInt<1>(0h1)) \n node _T_653 = leq(UInt<1>(0h0), uncommonBits_33) \n node _T_654 = and(_T_652, _T_653) \n node _T_655 = leq(uncommonBits_33, UInt<2>(0h3)) \n node _T_656 = and(_T_654, _T_655) \n node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) \n node _T_657 = shr(io.in.a.bits.source, 2) \n node _T_658 = eq(_T_657, UInt<2>(0h2)) \n node _T_659 = leq(UInt<1>(0h0), uncommonBits_34) \n node _T_660 = and(_T_658, _T_659) \n node _T_661 = leq(uncommonBits_34, UInt<2>(0h3)) \n node _T_662 = and(_T_660, _T_661) \n node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) \n node _T_663 = shr(io.in.a.bits.source, 2) \n node _T_664 = eq(_T_663, UInt<2>(0h3)) \n node _T_665 = leq(UInt<1>(0h0), uncommonBits_35) \n node _T_666 = and(_T_664, _T_665) \n node _T_667 = leq(uncommonBits_35, UInt<2>(0h3)) \n node _T_668 = and(_T_666, _T_667) \n node _T_669 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_673 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_674 = or(_T_644, _T_650) \n node _T_675 = or(_T_674, _T_656) \n node _T_676 = or(_T_675, _T_662) \n node _T_677 = or(_T_676, _T_668) \n node _T_678 = or(_T_677, _T_669) \n node _T_679 = or(_T_678, _T_670) \n node _T_680 = or(_T_679, _T_671) \n node _T_681 = or(_T_680, _T_672) \n node _T_682 = or(_T_681, _T_673) \n node _T_683 = and(_T_643, _T_682) \n node _T_684 = or(UInt<1>(0h0), _T_683) \n node _T_685 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_686 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_687 = cvt(_T_686) \n node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) \n node _T_689 = asSInt(_T_688) \n node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) \n node _T_691 = and(_T_685, _T_690) \n node _T_692 = or(UInt<1>(0h0), _T_691) \n node _T_693 = and(_T_684, _T_692) \n node _T_694 = asUInt(reset) \n node _T_695 = eq(_T_694, UInt<1>(0h0)) \n when _T_695 : \n node _T_696 = eq(_T_693, UInt<1>(0h0)) \n when _T_696 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_693, UInt<1>(0h1), \"\") : assert_36 \n node _T_697 = asUInt(reset) \n node _T_698 = eq(_T_697, UInt<1>(0h0)) \n when _T_698 : \n node _T_699 = eq(source_ok, UInt<1>(0h0)) \n when _T_699 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_37 \n node _T_700 = asUInt(reset) \n node _T_701 = eq(_T_700, UInt<1>(0h0)) \n when _T_701 : \n node _T_702 = eq(is_aligned, UInt<1>(0h0)) \n when _T_702 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_703 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_704 = asUInt(reset) \n node _T_705 = eq(_T_704, UInt<1>(0h0)) \n when _T_705 : \n node _T_706 = eq(_T_703, UInt<1>(0h0)) \n when _T_706 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_703, UInt<1>(0h1), \"\") : assert_39 \n node _T_707 = eq(io.in.a.bits.mask, mask) \n node _T_708 = asUInt(reset) \n node _T_709 = eq(_T_708, UInt<1>(0h0)) \n when _T_709 : \n node _T_710 = eq(_T_707, UInt<1>(0h0)) \n when _T_710 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_707, UInt<1>(0h1), \"\") : assert_40 \n node _T_711 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_711 : \n node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_713 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_714 = and(_T_712, _T_713) \n node _T_715 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) \n node _T_716 = shr(io.in.a.bits.source, 2) \n node _T_717 = eq(_T_716, UInt<1>(0h0)) \n node _T_718 = leq(UInt<1>(0h0), uncommonBits_36) \n node _T_719 = and(_T_717, _T_718) \n node _T_720 = leq(uncommonBits_36, UInt<2>(0h3)) \n node _T_721 = and(_T_719, _T_720) \n node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) \n node _T_722 = shr(io.in.a.bits.source, 2) \n node _T_723 = eq(_T_722, UInt<1>(0h1)) \n node _T_724 = leq(UInt<1>(0h0), uncommonBits_37) \n node _T_725 = and(_T_723, _T_724) \n node _T_726 = leq(uncommonBits_37, UInt<2>(0h3)) \n node _T_727 = and(_T_725, _T_726) \n node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) \n node _T_728 = shr(io.in.a.bits.source, 2) \n node _T_729 = eq(_T_728, UInt<2>(0h2)) \n node _T_730 = leq(UInt<1>(0h0), uncommonBits_38) \n node _T_731 = and(_T_729, _T_730) \n node _T_732 = leq(uncommonBits_38, UInt<2>(0h3)) \n node _T_733 = and(_T_731, _T_732) \n node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) \n node _T_734 = shr(io.in.a.bits.source, 2) \n node _T_735 = eq(_T_734, UInt<2>(0h3)) \n node _T_736 = leq(UInt<1>(0h0), uncommonBits_39) \n node _T_737 = and(_T_735, _T_736) \n node _T_738 = leq(uncommonBits_39, UInt<2>(0h3)) \n node _T_739 = and(_T_737, _T_738) \n node _T_740 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_744 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_745 = or(_T_715, _T_721) \n node _T_746 = or(_T_745, _T_727) \n node _T_747 = or(_T_746, _T_733) \n node _T_748 = or(_T_747, _T_739) \n node _T_749 = or(_T_748, _T_740) \n node _T_750 = or(_T_749, _T_741) \n node _T_751 = or(_T_750, _T_742) \n node _T_752 = or(_T_751, _T_743) \n node _T_753 = or(_T_752, _T_744) \n node _T_754 = and(_T_714, _T_753) \n node _T_755 = or(UInt<1>(0h0), _T_754) \n node _T_756 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_757 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_758 = cvt(_T_757) \n node _T_759 = and(_T_758, asSInt(UInt<13>(0h1000))) \n node _T_760 = asSInt(_T_759) \n node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0))) \n node _T_762 = and(_T_756, _T_761) \n node _T_763 = or(UInt<1>(0h0), _T_762) \n node _T_764 = and(_T_755, _T_763) \n node _T_765 = asUInt(reset) \n node _T_766 = eq(_T_765, UInt<1>(0h0)) \n when _T_766 : \n node _T_767 = eq(_T_764, UInt<1>(0h0)) \n when _T_767 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_764, UInt<1>(0h1), \"\") : assert_41 \n node _T_768 = asUInt(reset) \n node _T_769 = eq(_T_768, UInt<1>(0h0)) \n when _T_769 : \n node _T_770 = eq(source_ok, UInt<1>(0h0)) \n when _T_770 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_42 \n node _T_771 = asUInt(reset) \n node _T_772 = eq(_T_771, UInt<1>(0h0)) \n when _T_772 : \n node _T_773 = eq(is_aligned, UInt<1>(0h0)) \n when _T_773 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_774 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_775 = asUInt(reset) \n node _T_776 = eq(_T_775, UInt<1>(0h0)) \n when _T_776 : \n node _T_777 = eq(_T_774, UInt<1>(0h0)) \n when _T_777 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_774, UInt<1>(0h1), \"\") : assert_44 \n node _T_778 = eq(io.in.a.bits.mask, mask) \n node _T_779 = asUInt(reset) \n node _T_780 = eq(_T_779, UInt<1>(0h0)) \n when _T_780 : \n node _T_781 = eq(_T_778, UInt<1>(0h0)) \n when _T_781 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_778, UInt<1>(0h1), \"\") : assert_45 \n node _T_782 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_782 : \n node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_785 = and(_T_783, _T_784) \n node _T_786 = eq(io.in.a.bits.source, UInt<5>(0h11)) \n node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) \n node _T_787 = shr(io.in.a.bits.source, 2) \n node _T_788 = eq(_T_787, UInt<1>(0h0)) \n node _T_789 = leq(UInt<1>(0h0), uncommonBits_40) \n node _T_790 = and(_T_788, _T_789) \n node _T_791 = leq(uncommonBits_40, UInt<2>(0h3)) \n node _T_792 = and(_T_790, _T_791) \n node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) \n node _T_793 = shr(io.in.a.bits.source, 2) \n node _T_794 = eq(_T_793, UInt<1>(0h1)) \n node _T_795 = leq(UInt<1>(0h0), uncommonBits_41) \n node _T_796 = and(_T_794, _T_795) \n node _T_797 = leq(uncommonBits_41, UInt<2>(0h3)) \n node _T_798 = and(_T_796, _T_797) \n node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) \n node _T_799 = shr(io.in.a.bits.source, 2) \n node _T_800 = eq(_T_799, UInt<2>(0h2)) \n node _T_801 = leq(UInt<1>(0h0), uncommonBits_42) \n node _T_802 = and(_T_800, _T_801) \n node _T_803 = leq(uncommonBits_42, UInt<2>(0h3)) \n node _T_804 = and(_T_802, _T_803) \n node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) \n node _T_805 = shr(io.in.a.bits.source, 2) \n node _T_806 = eq(_T_805, UInt<2>(0h3)) \n node _T_807 = leq(UInt<1>(0h0), uncommonBits_43) \n node _T_808 = and(_T_806, _T_807) \n node _T_809 = leq(uncommonBits_43, UInt<2>(0h3)) \n node _T_810 = and(_T_808, _T_809) \n node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_816 = or(_T_786, _T_792) \n node _T_817 = or(_T_816, _T_798) \n node _T_818 = or(_T_817, _T_804) \n node _T_819 = or(_T_818, _T_810) \n node _T_820 = or(_T_819, _T_811) \n node _T_821 = or(_T_820, _T_812) \n node _T_822 = or(_T_821, _T_813) \n node _T_823 = or(_T_822, _T_814) \n node _T_824 = or(_T_823, _T_815) \n node _T_825 = and(_T_785, _T_824) \n node _T_826 = or(UInt<1>(0h0), _T_825) \n node _T_827 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_828 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_829 = cvt(_T_828) \n node _T_830 = and(_T_829, asSInt(UInt<13>(0h1000))) \n node _T_831 = asSInt(_T_830) \n node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) \n node _T_833 = and(_T_827, _T_832) \n node _T_834 = or(UInt<1>(0h0), _T_833) \n node _T_835 = and(_T_826, _T_834) \n node _T_836 = asUInt(reset) \n node _T_837 = eq(_T_836, UInt<1>(0h0)) \n when _T_837 : \n node _T_838 = eq(_T_835, UInt<1>(0h0)) \n when _T_838 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_835, UInt<1>(0h1), \"\") : assert_46 \n node _T_839 = asUInt(reset) \n node _T_840 = eq(_T_839, UInt<1>(0h0)) \n when _T_840 : \n node _T_841 = eq(source_ok, UInt<1>(0h0)) \n when _T_841 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_47 \n node _T_842 = asUInt(reset) \n node _T_843 = eq(_T_842, UInt<1>(0h0)) \n when _T_843 : \n node _T_844 = eq(is_aligned, UInt<1>(0h0)) \n when _T_844 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_845 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_846 = asUInt(reset) \n node _T_847 = eq(_T_846, UInt<1>(0h0)) \n when _T_847 : \n node _T_848 = eq(_T_845, UInt<1>(0h0)) \n when _T_848 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_845, UInt<1>(0h1), \"\") : assert_49 \n node _T_849 = eq(io.in.a.bits.mask, mask) \n node _T_850 = asUInt(reset) \n node _T_851 = eq(_T_850, UInt<1>(0h0)) \n when _T_851 : \n node _T_852 = eq(_T_849, UInt<1>(0h0)) \n when _T_852 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_849, UInt<1>(0h1), \"\") : assert_50 \n node _T_853 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_854 = asUInt(reset) \n node _T_855 = eq(_T_854, UInt<1>(0h0)) \n when _T_855 : \n node _T_856 = eq(_T_853, UInt<1>(0h0)) \n when _T_856 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_853, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_857 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_858 = asUInt(reset) \n node _T_859 = eq(_T_858, UInt<1>(0h0)) \n when _T_859 : \n node _T_860 = eq(_T_857, UInt<1>(0h0)) \n when _T_860 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_857, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11)) \n node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) \n node _source_ok_T_39 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0)) \n node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) \n node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) \n node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) \n node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) \n node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) \n node _source_ok_T_45 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1)) \n node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) \n node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) \n node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) \n node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) \n node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) \n node _source_ok_T_51 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2)) \n node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) \n node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) \n node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) \n node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) \n node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) \n node _source_ok_T_57 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3)) \n node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) \n node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) \n node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) \n node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) \n node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10)) \n node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20)) \n node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21)) \n node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22)) \n node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40)) \n wire _source_ok_WIRE_1 : UInt<1>[10] \n connect _source_ok_WIRE_1[0], _source_ok_T_38 \n connect _source_ok_WIRE_1[1], _source_ok_T_44 \n connect _source_ok_WIRE_1[2], _source_ok_T_50 \n connect _source_ok_WIRE_1[3], _source_ok_T_56 \n connect _source_ok_WIRE_1[4], _source_ok_T_62 \n connect _source_ok_WIRE_1[5], _source_ok_T_63 \n connect _source_ok_WIRE_1[6], _source_ok_T_64 \n connect _source_ok_WIRE_1[7], _source_ok_T_65 \n connect _source_ok_WIRE_1[8], _source_ok_T_66 \n connect _source_ok_WIRE_1[9], _source_ok_T_67 \n node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) \n node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2]) \n node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3]) \n node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4]) \n node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5]) \n node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6]) \n node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7]) \n node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8]) \n node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9]) \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_861 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_861 : \n node _T_862 = asUInt(reset) \n node _T_863 = eq(_T_862, UInt<1>(0h0)) \n when _T_863 : \n node _T_864 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_864 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_53 \n node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_866 = asUInt(reset) \n node _T_867 = eq(_T_866, UInt<1>(0h0)) \n when _T_867 : \n node _T_868 = eq(_T_865, UInt<1>(0h0)) \n when _T_868 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_865, UInt<1>(0h1), \"\") : assert_54 \n node _T_869 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_870 = asUInt(reset) \n node _T_871 = eq(_T_870, UInt<1>(0h0)) \n when _T_871 : \n node _T_872 = eq(_T_869, UInt<1>(0h0)) \n when _T_872 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_869, UInt<1>(0h1), \"\") : assert_55 \n node _T_873 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_874 = asUInt(reset) \n node _T_875 = eq(_T_874, UInt<1>(0h0)) \n when _T_875 : \n node _T_876 = eq(_T_873, UInt<1>(0h0)) \n when _T_876 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_873, UInt<1>(0h1), \"\") : assert_56 \n node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_878 = asUInt(reset) \n node _T_879 = eq(_T_878, UInt<1>(0h0)) \n when _T_879 : \n node _T_880 = eq(_T_877, UInt<1>(0h0)) \n when _T_880 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_877, UInt<1>(0h1), \"\") : assert_57 \n node _T_881 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_881 : \n node _T_882 = asUInt(reset) \n node _T_883 = eq(_T_882, UInt<1>(0h0)) \n when _T_883 : \n node _T_884 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_884 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_58 \n node _T_885 = asUInt(reset) \n node _T_886 = eq(_T_885, UInt<1>(0h0)) \n when _T_886 : \n node _T_887 = eq(sink_ok, UInt<1>(0h0)) \n when _T_887 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_888 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_889 = asUInt(reset) \n node _T_890 = eq(_T_889, UInt<1>(0h0)) \n when _T_890 : \n node _T_891 = eq(_T_888, UInt<1>(0h0)) \n when _T_891 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_888, UInt<1>(0h1), \"\") : assert_60 \n node _T_892 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_893 = asUInt(reset) \n node _T_894 = eq(_T_893, UInt<1>(0h0)) \n when _T_894 : \n node _T_895 = eq(_T_892, UInt<1>(0h0)) \n when _T_895 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_892, UInt<1>(0h1), \"\") : assert_61 \n node _T_896 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_897 = asUInt(reset) \n node _T_898 = eq(_T_897, UInt<1>(0h0)) \n when _T_898 : \n node _T_899 = eq(_T_896, UInt<1>(0h0)) \n when _T_899 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_896, UInt<1>(0h1), \"\") : assert_62 \n node _T_900 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_901 = asUInt(reset) \n node _T_902 = eq(_T_901, UInt<1>(0h0)) \n when _T_902 : \n node _T_903 = eq(_T_900, UInt<1>(0h0)) \n when _T_903 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_900, UInt<1>(0h1), \"\") : assert_63 \n node _T_904 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_905 = or(UInt<1>(0h0), _T_904) \n node _T_906 = asUInt(reset) \n node _T_907 = eq(_T_906, UInt<1>(0h0)) \n when _T_907 : \n node _T_908 = eq(_T_905, UInt<1>(0h0)) \n when _T_908 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_905, UInt<1>(0h1), \"\") : assert_64 \n node _T_909 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_909 : \n node _T_910 = asUInt(reset) \n node _T_911 = eq(_T_910, UInt<1>(0h0)) \n when _T_911 : \n node _T_912 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_912 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_65 \n node _T_913 = asUInt(reset) \n node _T_914 = eq(_T_913, UInt<1>(0h0)) \n when _T_914 : \n node _T_915 = eq(sink_ok, UInt<1>(0h0)) \n when _T_915 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_916 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_917 = asUInt(reset) \n node _T_918 = eq(_T_917, UInt<1>(0h0)) \n when _T_918 : \n node _T_919 = eq(_T_916, UInt<1>(0h0)) \n when _T_919 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_916, UInt<1>(0h1), \"\") : assert_67 \n node _T_920 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_921 = asUInt(reset) \n node _T_922 = eq(_T_921, UInt<1>(0h0)) \n when _T_922 : \n node _T_923 = eq(_T_920, UInt<1>(0h0)) \n when _T_923 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_920, UInt<1>(0h1), \"\") : assert_68 \n node _T_924 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_925 = asUInt(reset) \n node _T_926 = eq(_T_925, UInt<1>(0h0)) \n when _T_926 : \n node _T_927 = eq(_T_924, UInt<1>(0h0)) \n when _T_927 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_924, UInt<1>(0h1), \"\") : assert_69 \n node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_929 = or(_T_928, io.in.d.bits.corrupt) \n node _T_930 = asUInt(reset) \n node _T_931 = eq(_T_930, UInt<1>(0h0)) \n when _T_931 : \n node _T_932 = eq(_T_929, UInt<1>(0h0)) \n when _T_932 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_929, UInt<1>(0h1), \"\") : assert_70 \n node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_934 = or(UInt<1>(0h0), _T_933) \n node _T_935 = asUInt(reset) \n node _T_936 = eq(_T_935, UInt<1>(0h0)) \n when _T_936 : \n node _T_937 = eq(_T_934, UInt<1>(0h0)) \n when _T_937 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_934, UInt<1>(0h1), \"\") : assert_71 \n node _T_938 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_938 : \n node _T_939 = asUInt(reset) \n node _T_940 = eq(_T_939, UInt<1>(0h0)) \n when _T_940 : \n node _T_941 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_941 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_72 \n node _T_942 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_943 = asUInt(reset) \n node _T_944 = eq(_T_943, UInt<1>(0h0)) \n when _T_944 : \n node _T_945 = eq(_T_942, UInt<1>(0h0)) \n when _T_945 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_942, UInt<1>(0h1), \"\") : assert_73 \n node _T_946 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_947 = asUInt(reset) \n node _T_948 = eq(_T_947, UInt<1>(0h0)) \n when _T_948 : \n node _T_949 = eq(_T_946, UInt<1>(0h0)) \n when _T_949 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_946, UInt<1>(0h1), \"\") : assert_74 \n node _T_950 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_951 = or(UInt<1>(0h0), _T_950) \n node _T_952 = asUInt(reset) \n node _T_953 = eq(_T_952, UInt<1>(0h0)) \n when _T_953 : \n node _T_954 = eq(_T_951, UInt<1>(0h0)) \n when _T_954 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_951, UInt<1>(0h1), \"\") : assert_75 \n node _T_955 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_955 : \n node _T_956 = asUInt(reset) \n node _T_957 = eq(_T_956, UInt<1>(0h0)) \n when _T_957 : \n node _T_958 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_958 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_76 \n node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_960 = asUInt(reset) \n node _T_961 = eq(_T_960, UInt<1>(0h0)) \n when _T_961 : \n node _T_962 = eq(_T_959, UInt<1>(0h0)) \n when _T_962 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_959, UInt<1>(0h1), \"\") : assert_77 \n node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_964 = or(_T_963, io.in.d.bits.corrupt) \n node _T_965 = asUInt(reset) \n node _T_966 = eq(_T_965, UInt<1>(0h0)) \n when _T_966 : \n node _T_967 = eq(_T_964, UInt<1>(0h0)) \n when _T_967 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_964, UInt<1>(0h1), \"\") : assert_78 \n node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_969 = or(UInt<1>(0h0), _T_968) \n node _T_970 = asUInt(reset) \n node _T_971 = eq(_T_970, UInt<1>(0h0)) \n when _T_971 : \n node _T_972 = eq(_T_969, UInt<1>(0h0)) \n when _T_972 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_969, UInt<1>(0h1), \"\") : assert_79 \n node _T_973 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_973 : \n node _T_974 = asUInt(reset) \n node _T_975 = eq(_T_974, UInt<1>(0h0)) \n when _T_975 : \n node _T_976 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_976 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_80 \n node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_978 = asUInt(reset) \n node _T_979 = eq(_T_978, UInt<1>(0h0)) \n when _T_979 : \n node _T_980 = eq(_T_977, UInt<1>(0h0)) \n when _T_980 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_977, UInt<1>(0h1), \"\") : assert_81 \n node _T_981 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_982 = asUInt(reset) \n node _T_983 = eq(_T_982, UInt<1>(0h0)) \n when _T_983 : \n node _T_984 = eq(_T_981, UInt<1>(0h0)) \n when _T_984 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_981, UInt<1>(0h1), \"\") : assert_82 \n node _T_985 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_986 = or(UInt<1>(0h0), _T_985) \n node _T_987 = asUInt(reset) \n node _T_988 = eq(_T_987, UInt<1>(0h0)) \n when _T_988 : \n node _T_989 = eq(_T_986, UInt<1>(0h0)) \n when _T_989 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_986, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_4.bits.data, UInt<64>(0h0) \n connect _WIRE_4.bits.mask, UInt<8>(0h0) \n connect _WIRE_4.bits.address, UInt<29>(0h0) \n connect _WIRE_4.bits.source, UInt<7>(0h0) \n connect _WIRE_4.bits.size, UInt<3>(0h0) \n connect _WIRE_4.bits.param, UInt<2>(0h0) \n connect _WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_990 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_991 = asUInt(reset) \n node _T_992 = eq(_T_991, UInt<1>(0h0)) \n when _T_992 : \n node _T_993 = eq(_T_990, UInt<1>(0h0)) \n when _T_993 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_990, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<29>(0h0) \n connect _WIRE_6.bits.source, UInt<7>(0h0) \n connect _WIRE_6.bits.size, UInt<3>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_994 = eq(_WIRE_7.valid, UInt<1>(0h0)) \n node _T_995 = asUInt(reset) \n node _T_996 = eq(_T_995, UInt<1>(0h0)) \n when _T_996 : \n node _T_997 = eq(_T_994, UInt<1>(0h0)) \n when _T_997 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_994, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_8.bits.sink, UInt<1>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_998 = eq(_WIRE_9.valid, UInt<1>(0h0)) \n node _T_999 = asUInt(reset) \n node _T_1000 = eq(_T_999, UInt<1>(0h0)) \n when _T_1000 : \n node _T_1001 = eq(_T_998, UInt<1>(0h0)) \n when _T_1001 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_998, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_1002 = eq(a_first, UInt<1>(0h0)) \n node _T_1003 = and(io.in.a.valid, _T_1002) \n when _T_1003 : \n node _T_1004 = eq(io.in.a.bits.opcode, opcode) \n node _T_1005 = asUInt(reset) \n node _T_1006 = eq(_T_1005, UInt<1>(0h0)) \n when _T_1006 : \n node _T_1007 = eq(_T_1004, UInt<1>(0h0)) \n when _T_1007 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_1004, UInt<1>(0h1), \"\") : assert_87 \n node _T_1008 = eq(io.in.a.bits.param, param) \n node _T_1009 = asUInt(reset) \n node _T_1010 = eq(_T_1009, UInt<1>(0h0)) \n when _T_1010 : \n node _T_1011 = eq(_T_1008, UInt<1>(0h0)) \n when _T_1011 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_1008, UInt<1>(0h1), \"\") : assert_88 \n node _T_1012 = eq(io.in.a.bits.size, size) \n node _T_1013 = asUInt(reset) \n node _T_1014 = eq(_T_1013, UInt<1>(0h0)) \n when _T_1014 : \n node _T_1015 = eq(_T_1012, UInt<1>(0h0)) \n when _T_1015 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_1012, UInt<1>(0h1), \"\") : assert_89 \n node _T_1016 = eq(io.in.a.bits.source, source) \n node _T_1017 = asUInt(reset) \n node _T_1018 = eq(_T_1017, UInt<1>(0h0)) \n when _T_1018 : \n node _T_1019 = eq(_T_1016, UInt<1>(0h0)) \n when _T_1019 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_1016, UInt<1>(0h1), \"\") : assert_90 \n node _T_1020 = eq(io.in.a.bits.address, address) \n node _T_1021 = asUInt(reset) \n node _T_1022 = eq(_T_1021, UInt<1>(0h0)) \n when _T_1022 : \n node _T_1023 = eq(_T_1020, UInt<1>(0h0)) \n when _T_1023 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_1020, UInt<1>(0h1), \"\") : assert_91 \n node _T_1024 = and(io.in.a.ready, io.in.a.valid) \n node _T_1025 = and(_T_1024, a_first) \n when _T_1025 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_1026 = eq(d_first, UInt<1>(0h0)) \n node _T_1027 = and(io.in.d.valid, _T_1026) \n when _T_1027 : \n node _T_1028 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_1029 = asUInt(reset) \n node _T_1030 = eq(_T_1029, UInt<1>(0h0)) \n when _T_1030 : \n node _T_1031 = eq(_T_1028, UInt<1>(0h0)) \n when _T_1031 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_1028, UInt<1>(0h1), \"\") : assert_92 \n node _T_1032 = eq(io.in.d.bits.param, param_1) \n node _T_1033 = asUInt(reset) \n node _T_1034 = eq(_T_1033, UInt<1>(0h0)) \n when _T_1034 : \n node _T_1035 = eq(_T_1032, UInt<1>(0h0)) \n when _T_1035 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_1032, UInt<1>(0h1), \"\") : assert_93 \n node _T_1036 = eq(io.in.d.bits.size, size_1) \n node _T_1037 = asUInt(reset) \n node _T_1038 = eq(_T_1037, UInt<1>(0h0)) \n when _T_1038 : \n node _T_1039 = eq(_T_1036, UInt<1>(0h0)) \n when _T_1039 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_1036, UInt<1>(0h1), \"\") : assert_94 \n node _T_1040 = eq(io.in.d.bits.source, source_1) \n node _T_1041 = asUInt(reset) \n node _T_1042 = eq(_T_1041, UInt<1>(0h0)) \n when _T_1042 : \n node _T_1043 = eq(_T_1040, UInt<1>(0h0)) \n when _T_1043 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_1040, UInt<1>(0h1), \"\") : assert_95 \n node _T_1044 = eq(io.in.d.bits.sink, sink) \n node _T_1045 = asUInt(reset) \n node _T_1046 = eq(_T_1045, UInt<1>(0h0)) \n when _T_1046 : \n node _T_1047 = eq(_T_1044, UInt<1>(0h0)) \n when _T_1047 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_1044, UInt<1>(0h1), \"\") : assert_96 \n node _T_1048 = eq(io.in.d.bits.denied, denied) \n node _T_1049 = asUInt(reset) \n node _T_1050 = eq(_T_1049, UInt<1>(0h0)) \n when _T_1050 : \n node _T_1051 = eq(_T_1048, UInt<1>(0h0)) \n when _T_1051 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_1048, UInt<1>(0h1), \"\") : assert_97 \n node _T_1052 = and(io.in.d.ready, io.in.d.valid) \n node _T_1053 = and(_T_1052, d_first) \n when _T_1053 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) \n regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) \n regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<65> \n connect a_set, UInt<65>(0h0) \n wire a_set_wo_ready : UInt<65> \n connect a_set_wo_ready, UInt<65>(0h0) \n wire a_opcodes_set : UInt<260> \n connect a_opcodes_set, UInt<260>(0h0) \n wire a_sizes_set : UInt<260> \n connect a_sizes_set, UInt<260>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<4> \n connect a_sizes_set_interm, UInt<4>(0h0) \n node _T_1054 = and(io.in.a.valid, a_first_1) \n node _T_1055 = and(_T_1054, UInt<1>(0h1)) \n when _T_1055 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_1056 = and(io.in.a.ready, io.in.a.valid) \n node _T_1057 = and(_T_1056, a_first_1) \n node _T_1058 = and(_T_1057, UInt<1>(0h1)) \n when _T_1058 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_1059 = dshr(inflight, io.in.a.bits.source) \n node _T_1060 = bits(_T_1059, 0, 0) \n node _T_1061 = eq(_T_1060, UInt<1>(0h0)) \n node _T_1062 = asUInt(reset) \n node _T_1063 = eq(_T_1062, UInt<1>(0h0)) \n when _T_1063 : \n node _T_1064 = eq(_T_1061, UInt<1>(0h0)) \n when _T_1064 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_1061, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<65> \n connect d_clr, UInt<65>(0h0) \n wire d_clr_wo_ready : UInt<65> \n connect d_clr_wo_ready, UInt<65>(0h0) \n wire d_opcodes_clr : UInt<260> \n connect d_opcodes_clr, UInt<260>(0h0) \n wire d_sizes_clr : UInt<260> \n connect d_sizes_clr, UInt<260>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1065 = and(io.in.d.valid, d_first_1) \n node _T_1066 = and(_T_1065, UInt<1>(0h1)) \n node _T_1067 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1068 = and(_T_1066, _T_1067) \n when _T_1068 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_1069 = and(io.in.d.ready, io.in.d.valid) \n node _T_1070 = and(_T_1069, d_first_1) \n node _T_1071 = and(_T_1070, UInt<1>(0h1)) \n node _T_1072 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1073 = and(_T_1071, _T_1072) \n when _T_1073 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_1074 = and(io.in.d.valid, d_first_1) \n node _T_1075 = and(_T_1074, UInt<1>(0h1)) \n node _T_1076 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1077 = and(_T_1075, _T_1076) \n when _T_1077 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_1078 = dshr(inflight, io.in.d.bits.source) \n node _T_1079 = bits(_T_1078, 0, 0) \n node _T_1080 = or(_T_1079, same_cycle_resp) \n node _T_1081 = asUInt(reset) \n node _T_1082 = eq(_T_1081, UInt<1>(0h0)) \n when _T_1082 : \n node _T_1083 = eq(_T_1080, UInt<1>(0h0)) \n when _T_1083 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_1080, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_1084 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_1085 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_1086 = or(_T_1084, _T_1085) \n node _T_1087 = asUInt(reset) \n node _T_1088 = eq(_T_1087, UInt<1>(0h0)) \n when _T_1088 : \n node _T_1089 = eq(_T_1086, UInt<1>(0h0)) \n when _T_1089 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_1086, UInt<1>(0h1), \"\") : assert_100 \n node _T_1090 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_1091 = asUInt(reset) \n node _T_1092 = eq(_T_1091, UInt<1>(0h0)) \n when _T_1092 : \n node _T_1093 = eq(_T_1090, UInt<1>(0h0)) \n when _T_1093 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_1090, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_1094 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_1095 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_1096 = or(_T_1094, _T_1095) \n node _T_1097 = asUInt(reset) \n node _T_1098 = eq(_T_1097, UInt<1>(0h0)) \n when _T_1098 : \n node _T_1099 = eq(_T_1096, UInt<1>(0h0)) \n when _T_1099 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_1096, UInt<1>(0h1), \"\") : assert_102 \n node _T_1100 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_1101 = asUInt(reset) \n node _T_1102 = eq(_T_1101, UInt<1>(0h0)) \n when _T_1102 : \n node _T_1103 = eq(_T_1100, UInt<1>(0h0)) \n when _T_1103 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_1100, UInt<1>(0h1), \"\") : assert_103 \n node _T_1104 = and(io.in.d.valid, d_first_1) \n node _T_1105 = and(_T_1104, a_first_1) \n node _T_1106 = and(_T_1105, io.in.a.valid) \n node _T_1107 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_1108 = and(_T_1106, _T_1107) \n node _T_1109 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1110 = and(_T_1108, _T_1109) \n when _T_1110 : \n node _T_1111 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_1112 = or(_T_1111, io.in.a.ready) \n node _T_1113 = asUInt(reset) \n node _T_1114 = eq(_T_1113, UInt<1>(0h0)) \n when _T_1114 : \n node _T_1115 = eq(_T_1112, UInt<1>(0h0)) \n when _T_1115 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_1112, UInt<1>(0h1), \"\") : assert_104 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_14 \n node _T_1116 = orr(inflight) \n node _T_1117 = eq(_T_1116, UInt<1>(0h0)) \n node _T_1118 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_1119 = or(_T_1117, _T_1118) \n node _T_1120 = lt(watchdog, plusarg_reader.out) \n node _T_1121 = or(_T_1119, _T_1120) \n node _T_1122 = asUInt(reset) \n node _T_1123 = eq(_T_1122, UInt<1>(0h0)) \n when _T_1123 : \n node _T_1124 = eq(_T_1121, UInt<1>(0h0)) \n when _T_1124 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_1121, UInt<1>(0h1), \"\") : assert_105 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_1125 = and(io.in.a.ready, io.in.a.valid) \n node _T_1126 = and(io.in.d.ready, io.in.d.valid) \n node _T_1127 = or(_T_1125, _T_1126) \n when _T_1127 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) \n regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) \n regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<29>(0h0) \n connect _c_first_WIRE.bits.source, UInt<7>(0h0) \n connect _c_first_WIRE.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<65> \n connect c_set, UInt<65>(0h0) \n wire c_set_wo_ready : UInt<65> \n connect c_set_wo_ready, UInt<65>(0h0) \n wire c_opcodes_set : UInt<260> \n connect c_opcodes_set, UInt<260>(0h0) \n wire c_sizes_set : UInt<260> \n connect c_sizes_set, UInt<260>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<4> \n connect c_sizes_set_interm, UInt<4>(0h0) \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<29>(0h0) \n connect _WIRE_10.bits.source, UInt<7>(0h0) \n connect _WIRE_10.bits.size, UInt<3>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_1128 = and(_WIRE_11.valid, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<29>(0h0) \n connect _WIRE_12.bits.source, UInt<7>(0h0) \n connect _WIRE_12.bits.size, UInt<3>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_1129 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_1130 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_1131 = and(_T_1129, _T_1130) \n node _T_1132 = and(_T_1128, _T_1131) \n when _T_1132 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<29>(0h0) \n connect _WIRE_14.bits.source, UInt<7>(0h0) \n connect _WIRE_14.bits.size, UInt<3>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_1133 = and(_WIRE_15.ready, _WIRE_15.valid) \n node _T_1134 = and(_T_1133, c_first) \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<29>(0h0) \n connect _WIRE_16.bits.source, UInt<7>(0h0) \n connect _WIRE_16.bits.size, UInt<3>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_1135 = bits(_WIRE_17.bits.opcode, 2, 2) \n node _T_1136 = bits(_WIRE_17.bits.opcode, 1, 1) \n node _T_1137 = and(_T_1135, _T_1136) \n node _T_1138 = and(_T_1134, _T_1137) \n when _T_1138 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_set_WIRE.bits.source, UInt<7>(0h0) \n connect _c_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<29>(0h0) \n connect _WIRE_18.bits.source, UInt<7>(0h0) \n connect _WIRE_18.bits.size, UInt<3>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_1139 = dshr(inflight_1, _WIRE_19.bits.source) \n node _T_1140 = bits(_T_1139, 0, 0) \n node _T_1141 = eq(_T_1140, UInt<1>(0h0)) \n node _T_1142 = asUInt(reset) \n node _T_1143 = eq(_T_1142, UInt<1>(0h0)) \n when _T_1143 : \n node _T_1144 = eq(_T_1141, UInt<1>(0h0)) \n when _T_1144 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_1141, UInt<1>(0h1), \"\") : assert_106 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<65> \n connect d_clr_1, UInt<65>(0h0) \n wire d_clr_wo_ready_1 : UInt<65> \n connect d_clr_wo_ready_1, UInt<65>(0h0) \n wire d_opcodes_clr_1 : UInt<260> \n connect d_opcodes_clr_1, UInt<260>(0h0) \n wire d_sizes_clr_1 : UInt<260> \n connect d_sizes_clr_1, UInt<260>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1145 = and(io.in.d.valid, d_first_2) \n node _T_1146 = and(_T_1145, UInt<1>(0h1)) \n node _T_1147 = and(_T_1146, d_release_ack_1) \n when _T_1147 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_1148 = and(io.in.d.ready, io.in.d.valid) \n node _T_1149 = and(_T_1148, d_first_2) \n node _T_1150 = and(_T_1149, UInt<1>(0h1)) \n node _T_1151 = and(_T_1150, d_release_ack_1) \n when _T_1151 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_1152 = and(io.in.d.valid, d_first_2) \n node _T_1153 = and(_T_1152, UInt<1>(0h1)) \n node _T_1154 = and(_T_1153, d_release_ack_1) \n when _T_1154 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_1155 = dshr(inflight_1, io.in.d.bits.source) \n node _T_1156 = bits(_T_1155, 0, 0) \n node _T_1157 = or(_T_1156, same_cycle_resp_1) \n node _T_1158 = asUInt(reset) \n node _T_1159 = eq(_T_1158, UInt<1>(0h0)) \n when _T_1159 : \n node _T_1160 = eq(_T_1157, UInt<1>(0h0)) \n when _T_1160 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_1157, UInt<1>(0h1), \"\") : assert_107 \n when same_cycle_resp_1 : \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<29>(0h0) \n connect _WIRE_20.bits.source, UInt<7>(0h0) \n connect _WIRE_20.bits.size, UInt<3>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_1161 = eq(io.in.d.bits.size, _WIRE_21.bits.size) \n node _T_1162 = asUInt(reset) \n node _T_1163 = eq(_T_1162, UInt<1>(0h0)) \n when _T_1163 : \n node _T_1164 = eq(_T_1161, UInt<1>(0h0)) \n when _T_1164 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_1161, UInt<1>(0h1), \"\") : assert_108 \n else :\n\n node _T_1165 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_1166 = asUInt(reset) \n node _T_1167 = eq(_T_1166, UInt<1>(0h0)) \n when _T_1167 : \n node _T_1168 = eq(_T_1165, UInt<1>(0h0)) \n when _T_1168 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_1165, UInt<1>(0h1), \"\") : assert_109 \n node _T_1169 = and(io.in.d.valid, d_first_2) \n node _T_1170 = and(_T_1169, c_first) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<29>(0h0) \n connect _WIRE_22.bits.source, UInt<7>(0h0) \n connect _WIRE_22.bits.size, UInt<3>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_1171 = and(_T_1170, _WIRE_23.valid) \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<29>(0h0) \n connect _WIRE_24.bits.source, UInt<7>(0h0) \n connect _WIRE_24.bits.size, UInt<3>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_1172 = eq(_WIRE_25.bits.source, io.in.d.bits.source) \n node _T_1173 = and(_T_1171, _T_1172) \n node _T_1174 = and(_T_1173, d_release_ack_1) \n node _T_1175 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_1176 = and(_T_1174, _T_1175) \n when _T_1176 : \n node _T_1177 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_26.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_26.bits.data, UInt<64>(0h0) \n connect _WIRE_26.bits.address, UInt<29>(0h0) \n connect _WIRE_26.bits.source, UInt<7>(0h0) \n connect _WIRE_26.bits.size, UInt<3>(0h0) \n connect _WIRE_26.bits.param, UInt<3>(0h0) \n connect _WIRE_26.bits.opcode, UInt<3>(0h0) \n connect _WIRE_26.valid, UInt<1>(0h0) \n connect _WIRE_26.ready, UInt<1>(0h0) \n wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_27.bits, _WIRE_26.bits \n connect _WIRE_27.valid, _WIRE_26.valid \n connect _WIRE_27.ready, _WIRE_26.ready \n node _T_1178 = or(_T_1177, _WIRE_27.ready) \n node _T_1179 = asUInt(reset) \n node _T_1180 = eq(_T_1179, UInt<1>(0h0)) \n when _T_1180 : \n node _T_1181 = eq(_T_1178, UInt<1>(0h0)) \n when _T_1181 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_1178, UInt<1>(0h1), \"\") : assert_110 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_15 \n node _T_1182 = orr(inflight_1) \n node _T_1183 = eq(_T_1182, UInt<1>(0h0)) \n node _T_1184 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_1185 = or(_T_1183, _T_1184) \n node _T_1186 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_1187 = or(_T_1185, _T_1186) \n node _T_1188 = asUInt(reset) \n node _T_1189 = eq(_T_1188, UInt<1>(0h0)) \n when _T_1189 : \n node _T_1190 = eq(_T_1187, UInt<1>(0h0)) \n when _T_1190 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_1187, UInt<1>(0h1), \"\") : assert_111 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_28.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_28.bits.data, UInt<64>(0h0) \n connect _WIRE_28.bits.address, UInt<29>(0h0) \n connect _WIRE_28.bits.source, UInt<7>(0h0) \n connect _WIRE_28.bits.size, UInt<3>(0h0) \n connect _WIRE_28.bits.param, UInt<3>(0h0) \n connect _WIRE_28.bits.opcode, UInt<3>(0h0) \n connect _WIRE_28.valid, UInt<1>(0h0) \n connect _WIRE_28.ready, UInt<1>(0h0) \n wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_29.bits, _WIRE_28.bits \n connect _WIRE_29.valid, _WIRE_28.valid \n connect _WIRE_29.ready, _WIRE_28.ready \n node _T_1191 = and(_WIRE_29.ready, _WIRE_29.valid) \n node _T_1192 = and(io.in.d.ready, io.in.d.valid) \n node _T_1193 = or(_T_1191, _T_1192) \n when _T_1193 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_7(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [6:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [28:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [6:0] io_in_d_bits_source\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire [12:0] _GEN = {10'h0, io_in_a_bits_size};\t// @[package.scala:243:71]\n wire _a_first_T_1 = io_in_a_ready & io_in_a_valid;\t// @[Decoupled.scala:51:35]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [6:0] source;\t// @[Monitor.scala:390:22]\n reg [28:0] address;\t// @[Monitor.scala:391:22]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [6:0] source_1;\t// @[Monitor.scala:541:22]\n reg [64:0] inflight;\t// @[Monitor.scala:614:27]\n reg [259:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [259:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _GEN_0 = _a_first_T_1 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire d_release_ack = io_in_d_bits_opcode == 3'h6;\t// @[Monitor.scala:673:46]\n wire _GEN_1 = io_in_d_bits_opcode != 3'h6;\t// @[Monitor.scala:673:46, :674:74]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n reg [64:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [259:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32167,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLBFromNoC_9 : \n input clock : Clock \n input reset : Reset \n output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} \n\n\n wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) \n reg const_reg : UInt<45>, clock \n node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) \n node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) \n node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) \n node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) \n connect io.flit.ready, _io_flit_ready_T_2 \n node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) \n node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) \n node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) \n connect protocol.valid, _protocol_valid_T_2 \n wire _protocol_bits_address_WIRE : UInt<29> \n connect _protocol_bits_address_WIRE, const \n connect protocol.bits.address, _protocol_bits_address_WIRE \n node _T = shr(const, 29) \n wire _protocol_bits_source_WIRE : UInt<7> \n connect _protocol_bits_source_WIRE, _T \n connect protocol.bits.source, _protocol_bits_source_WIRE \n node _T_1 = shr(_T, 7) \n wire _protocol_bits_size_WIRE : UInt<4> \n connect _protocol_bits_size_WIRE, _T_1 \n connect protocol.bits.size, _protocol_bits_size_WIRE \n node _T_2 = shr(_T_1, 4) \n wire _protocol_bits_param_WIRE : UInt<2> \n connect _protocol_bits_param_WIRE, _T_2 \n connect protocol.bits.param, _protocol_bits_param_WIRE \n node _T_3 = shr(_T_2, 2) \n wire _protocol_bits_opcode_WIRE : UInt<3> \n connect _protocol_bits_opcode_WIRE, _T_3 \n connect protocol.bits.opcode, _protocol_bits_opcode_WIRE \n node _T_4 = shr(_T_3, 3) \n wire _protocol_bits_corrupt_WIRE : UInt<1> \n connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload \n connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE \n node _T_5 = shr(io.flit.bits.payload, 1) \n wire _protocol_bits_data_WIRE : UInt<64> \n connect _protocol_bits_data_WIRE, _T_5 \n connect protocol.bits.data, _protocol_bits_data_WIRE \n node _T_6 = shr(_T_5, 64) \n wire _protocol_bits_mask_WIRE : UInt<8> \n connect _protocol_bits_mask_WIRE, _T_6 \n connect protocol.bits.mask, _protocol_bits_mask_WIRE \n node _T_7 = shr(_T_6, 8) \n node _T_8 = and(io.flit.ready, io.flit.valid) \n node _T_9 = and(_T_8, io.flit.bits.head) \n when _T_9 : \n connect is_const, UInt<1>(0h0) \n connect const_reg, io.flit.bits.payload \n node _T_10 = and(io.flit.ready, io.flit.valid) \n node _T_11 = and(_T_10, io.flit.bits.tail) \n when _T_11 : \n connect is_const, UInt<1>(0h1) \n connect io.protocol, protocol \n node _io_protocol_bits_source_T = bits(protocol.bits.source, 6, 0) \n connect io.protocol.bits.source, _io_protocol_bits_source_T \n when io.flit.bits.head : \n node _io_protocol_bits_mask_T = not(UInt<8>(0h0)) \n connect io.protocol.bits.mask, _io_protocol_bits_mask_T"},"response":{"kind":"string","value":"module TLBFromNoC_9(\t// @[TilelinkAdapters.scala:145:7]\n input clock,\t// @[TilelinkAdapters.scala:145:7]\n input reset,\t// @[TilelinkAdapters.scala:145:7]\n output io_flit_ready,\t// @[TilelinkAdapters.scala:56:14]\n input io_flit_valid,\t// @[TilelinkAdapters.scala:56:14]\n input io_flit_bits_head,\t// @[TilelinkAdapters.scala:56:14]\n input io_flit_bits_tail\t// @[TilelinkAdapters.scala:56:14]\n);\n\n reg is_const;\t// @[TilelinkAdapters.scala:68:25]\n wire io_flit_ready_0 = is_const & ~io_flit_bits_tail;\t// @[TilelinkAdapters.scala:68:25, :71:{30,33}]\n wire _GEN = io_flit_ready_0 & io_flit_valid;\t// @[Decoupled.scala:51:35]\n always @(posedge clock) begin\t// @[TilelinkAdapters.scala:145:7]\n if (reset)\t// @[TilelinkAdapters.scala:145:7]\n is_const <= 1'h1;\t// @[TilelinkAdapters.scala:68:25, :145:7]\n else\t// @[TilelinkAdapters.scala:145:7]\n is_const <= _GEN & io_flit_bits_tail | ~(_GEN & io_flit_bits_head) & is_const;\t// @[Decoupled.scala:51:35]\n always @(posedge)"}}},{"rowIdx":32168,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module RegisterFileSynthesizable : \n input clock : Clock \n input reset : Reset \n output io : { read_ports : { flip addr : UInt<7>, data : UInt<65>}[3], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<65>}}[2]} \n\n\n cmem regfile : UInt<65> [96] \n wire read_data : UInt<65>[3] \n reg read_addrs_0 : UInt, clock \n connect read_addrs_0, io.read_ports[0].addr \n reg read_addrs_1 : UInt, clock \n connect read_addrs_1, io.read_ports[1].addr \n reg read_addrs_2 : UInt, clock \n connect read_addrs_2, io.read_ports[2].addr \n node _read_data_0_T = or(read_addrs_0, UInt<7>(0h0)) \n node _read_data_0_T_1 = bits(_read_data_0_T, 6, 0) \n infer mport read_data_0_MPORT = regfile[_read_data_0_T_1], clock \n connect read_data[0], read_data_0_MPORT \n node _read_data_1_T = or(read_addrs_1, UInt<7>(0h0)) \n node _read_data_1_T_1 = bits(_read_data_1_T, 6, 0) \n infer mport read_data_1_MPORT = regfile[_read_data_1_T_1], clock \n connect read_data[1], read_data_1_MPORT \n node _read_data_2_T = or(read_addrs_2, UInt<7>(0h0)) \n node _read_data_2_T_1 = bits(_read_data_2_T, 6, 0) \n infer mport read_data_2_MPORT = regfile[_read_data_2_T_1], clock \n connect read_data[2], read_data_2_MPORT \n connect io.read_ports[0].data, read_data[0] \n connect io.read_ports[1].data, read_data[1] \n connect io.read_ports[2].data, read_data[2] \n when io.write_ports[0].valid : \n infer mport MPORT = regfile[io.write_ports[0].bits.addr], clock \n connect MPORT, io.write_ports[0].bits.data \n when io.write_ports[1].valid : \n infer mport MPORT_1 = regfile[io.write_ports[1].bits.addr], clock \n connect MPORT_1, io.write_ports[1].bits.data \n node _T = eq(io.write_ports[0].valid, UInt<1>(0h0)) \n node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0)) \n node _T_2 = or(_T, _T_1) \n node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr) \n node _T_4 = or(_T_2, _T_3) \n node _T_5 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0)) \n node _T_6 = or(_T_4, _T_5) \n node _T_7 = asUInt(reset) \n node _T_8 = eq(_T_7, UInt<1>(0h0)) \n when _T_8 : \n node _T_9 = eq(_T_6, UInt<1>(0h0)) \n when _T_9 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: [regfile] too many writers a register\\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\\n\") : printf \n assert(clock, _T_6, UInt<1>(0h1), \"\") : assert"},"response":{"kind":"string","value":"module RegisterFileSynthesizable(\t// @[regfile.scala:106:7]\n input clock,\t// @[regfile.scala:106:7]\n input reset,\t// @[regfile.scala:106:7]\n input [6:0] io_read_ports_0_addr,\t// @[regfile.scala:82:14]\n output [64:0] io_read_ports_0_data,\t// @[regfile.scala:82:14]\n input [6:0] io_read_ports_1_addr,\t// @[regfile.scala:82:14]\n output [64:0] io_read_ports_1_data,\t// @[regfile.scala:82:14]\n input [6:0] io_read_ports_2_addr,\t// @[regfile.scala:82:14]\n output [64:0] io_read_ports_2_data,\t// @[regfile.scala:82:14]\n input io_write_ports_0_valid,\t// @[regfile.scala:82:14]\n input [6:0] io_write_ports_0_bits_addr,\t// @[regfile.scala:82:14]\n input [64:0] io_write_ports_0_bits_data,\t// @[regfile.scala:82:14]\n input io_write_ports_1_valid,\t// @[regfile.scala:82:14]\n input [6:0] io_write_ports_1_bits_addr,\t// @[regfile.scala:82:14]\n input [64:0] io_write_ports_1_bits_data\t// @[regfile.scala:82:14]\n);\n\n wire [6:0] io_read_ports_0_addr_0 = io_read_ports_0_addr;\t// @[regfile.scala:106:7]\n wire [6:0] io_read_ports_1_addr_0 = io_read_ports_1_addr;\t// @[regfile.scala:106:7]\n wire [6:0] io_read_ports_2_addr_0 = io_read_ports_2_addr;\t// @[regfile.scala:106:7]\n wire io_write_ports_0_valid_0 = io_write_ports_0_valid;\t// @[regfile.scala:106:7]\n wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr;\t// @[regfile.scala:106:7]\n wire [64:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data;\t// @[regfile.scala:106:7]\n wire io_write_ports_1_valid_0 = io_write_ports_1_valid;\t// @[regfile.scala:106:7]\n wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr;\t// @[regfile.scala:106:7]\n wire [64:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data;\t// @[regfile.scala:106:7]\n wire [64:0] read_data_0;\t// @[regfile.scala:122:23]\n wire [64:0] read_data_1;\t// @[regfile.scala:122:23]\n wire [64:0] read_data_2;\t// @[regfile.scala:122:23]\n wire [64:0] io_read_ports_0_data_0;\t// @[regfile.scala:106:7]\n wire [64:0] io_read_ports_1_data_0;\t// @[regfile.scala:106:7]\n wire [64:0] io_read_ports_2_data_0;\t// @[regfile.scala:106:7]\n assign io_read_ports_0_data_0 = read_data_0;\t// @[regfile.scala:106:7, :122:23]\n assign io_read_ports_1_data_0 = read_data_1;\t// @[regfile.scala:106:7, :122:23]\n assign io_read_ports_2_data_0 = read_data_2;\t// @[regfile.scala:106:7, :122:23]\n reg [6:0] read_addrs_0;\t// @[regfile.scala:125:50]\n wire [6:0] _read_data_0_T = read_addrs_0;\t// @[regfile.scala:125:50, :128:28]\n reg [6:0] read_addrs_1;\t// @[regfile.scala:125:50]\n wire [6:0] _read_data_1_T = read_addrs_1;\t// @[regfile.scala:125:50, :128:28]\n reg [6:0] read_addrs_2;\t// @[regfile.scala:125:50]\n wire [6:0] _read_data_2_T = read_addrs_2;\t// @[regfile.scala:125:50, :128:28]\n wire [6:0] _read_data_0_T_1 = _read_data_0_T;\t// @[regfile.scala:128:28]\n wire [6:0] _read_data_1_T_1 = _read_data_1_T;\t// @[regfile.scala:128:28]\n wire [6:0] _read_data_2_T_1 = _read_data_2_T;\t// @[regfile.scala:128:28]"}}},{"rowIdx":32169,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_67 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) \n node _source_ok_T_1 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10)) \n node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) \n node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) \n node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) \n node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) \n node _source_ok_T_7 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11)) \n node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) \n node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) \n node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) \n node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) \n node _source_ok_T_13 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12)) \n node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) \n node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) \n node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) \n node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) \n node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) \n node _source_ok_T_19 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13)) \n node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) \n node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) \n node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) \n node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) \n node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) \n node _source_ok_T_27 = shr(io.in.a.bits.source, 4) \n node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1)) \n node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) \n node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) \n node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf)) \n node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) \n node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) \n node _source_ok_T_33 = shr(io.in.a.bits.source, 4) \n node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) \n node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) \n node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) \n node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf)) \n node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) \n node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n wire _source_ok_WIRE : UInt<1>[11] \n connect _source_ok_WIRE[0], _source_ok_T \n connect _source_ok_WIRE[1], _source_ok_T_6 \n connect _source_ok_WIRE[2], _source_ok_T_12 \n connect _source_ok_WIRE[3], _source_ok_T_18 \n connect _source_ok_WIRE[4], _source_ok_T_24 \n connect _source_ok_WIRE[5], _source_ok_T_25 \n connect _source_ok_WIRE[6], _source_ok_T_26 \n connect _source_ok_WIRE[7], _source_ok_T_32 \n connect _source_ok_WIRE[8], _source_ok_T_38 \n connect _source_ok_WIRE[9], _source_ok_T_39 \n connect _source_ok_WIRE[10], _source_ok_T_40 \n node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) \n node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) \n node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) \n node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) \n node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) \n node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) \n node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) \n node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) \n node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) \n node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10]) \n node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_7 = cvt(_T_6) \n node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) \n node _T_9 = asSInt(_T_8) \n node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) \n node _T_11 = or(_T_5, _T_10) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 1, 0) \n node _T_12 = shr(io.in.a.bits.source, 2) \n node _T_13 = eq(_T_12, UInt<5>(0h10)) \n node _T_14 = leq(UInt<1>(0h0), uncommonBits) \n node _T_15 = and(_T_13, _T_14) \n node _T_16 = leq(uncommonBits, UInt<2>(0h3)) \n node _T_17 = and(_T_15, _T_16) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_20 = cvt(_T_19) \n node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) \n node _T_22 = asSInt(_T_21) \n node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) \n node _T_24 = or(_T_18, _T_23) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) \n node _T_25 = shr(io.in.a.bits.source, 2) \n node _T_26 = eq(_T_25, UInt<5>(0h11)) \n node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_28 = and(_T_26, _T_27) \n node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) \n node _T_30 = and(_T_28, _T_29) \n node _T_31 = eq(_T_30, UInt<1>(0h0)) \n node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_33 = cvt(_T_32) \n node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) \n node _T_35 = asSInt(_T_34) \n node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) \n node _T_37 = or(_T_31, _T_36) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) \n node _T_38 = shr(io.in.a.bits.source, 2) \n node _T_39 = eq(_T_38, UInt<5>(0h12)) \n node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_41 = and(_T_39, _T_40) \n node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) \n node _T_43 = and(_T_41, _T_42) \n node _T_44 = eq(_T_43, UInt<1>(0h0)) \n node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_46 = cvt(_T_45) \n node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) \n node _T_48 = asSInt(_T_47) \n node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) \n node _T_50 = or(_T_44, _T_49) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) \n node _T_51 = shr(io.in.a.bits.source, 2) \n node _T_52 = eq(_T_51, UInt<5>(0h13)) \n node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_54 = and(_T_52, _T_53) \n node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) \n node _T_56 = and(_T_54, _T_55) \n node _T_57 = eq(_T_56, UInt<1>(0h0)) \n node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_59 = cvt(_T_58) \n node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) \n node _T_61 = asSInt(_T_60) \n node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) \n node _T_63 = or(_T_57, _T_62) \n node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_65 = eq(_T_64, UInt<1>(0h0)) \n node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_67 = cvt(_T_66) \n node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) \n node _T_69 = asSInt(_T_68) \n node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) \n node _T_71 = or(_T_65, _T_70) \n node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _T_73 = eq(_T_72, UInt<1>(0h0)) \n node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_75 = cvt(_T_74) \n node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) \n node _T_77 = asSInt(_T_76) \n node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) \n node _T_79 = or(_T_73, _T_78) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) \n node _T_80 = shr(io.in.a.bits.source, 4) \n node _T_81 = eq(_T_80, UInt<1>(0h1)) \n node _T_82 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_83 = and(_T_81, _T_82) \n node _T_84 = leq(uncommonBits_4, UInt<4>(0hf)) \n node _T_85 = and(_T_83, _T_84) \n node _T_86 = eq(_T_85, UInt<1>(0h0)) \n node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_88 = cvt(_T_87) \n node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) \n node _T_90 = asSInt(_T_89) \n node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) \n node _T_92 = or(_T_86, _T_91) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) \n node _T_93 = shr(io.in.a.bits.source, 4) \n node _T_94 = eq(_T_93, UInt<1>(0h0)) \n node _T_95 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_96 = and(_T_94, _T_95) \n node _T_97 = leq(uncommonBits_5, UInt<4>(0hf)) \n node _T_98 = and(_T_96, _T_97) \n node _T_99 = eq(_T_98, UInt<1>(0h0)) \n node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_101 = cvt(_T_100) \n node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) \n node _T_103 = asSInt(_T_102) \n node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) \n node _T_105 = or(_T_99, _T_104) \n node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_107 = eq(_T_106, UInt<1>(0h0)) \n node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_109 = cvt(_T_108) \n node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) \n node _T_111 = asSInt(_T_110) \n node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) \n node _T_113 = or(_T_107, _T_112) \n node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_115 = eq(_T_114, UInt<1>(0h0)) \n node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_117 = cvt(_T_116) \n node _T_118 = and(_T_117, asSInt(UInt<1>(0h0))) \n node _T_119 = asSInt(_T_118) \n node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) \n node _T_121 = or(_T_115, _T_120) \n node _T_122 = and(_T_11, _T_24) \n node _T_123 = and(_T_122, _T_37) \n node _T_124 = and(_T_123, _T_50) \n node _T_125 = and(_T_124, _T_63) \n node _T_126 = and(_T_125, _T_71) \n node _T_127 = and(_T_126, _T_79) \n node _T_128 = and(_T_127, _T_92) \n node _T_129 = and(_T_128, _T_105) \n node _T_130 = and(_T_129, _T_113) \n node _T_131 = and(_T_130, _T_121) \n node _T_132 = asUInt(reset) \n node _T_133 = eq(_T_132, UInt<1>(0h0)) \n when _T_133 : \n node _T_134 = eq(_T_131, UInt<1>(0h0)) \n when _T_134 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_131, UInt<1>(0h1), \"\") : assert_1 \n node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_135 : \n node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_138 = and(_T_136, _T_137) \n node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) \n node _T_140 = shr(io.in.a.bits.source, 2) \n node _T_141 = eq(_T_140, UInt<5>(0h10)) \n node _T_142 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_143 = and(_T_141, _T_142) \n node _T_144 = leq(uncommonBits_6, UInt<2>(0h3)) \n node _T_145 = and(_T_143, _T_144) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) \n node _T_146 = shr(io.in.a.bits.source, 2) \n node _T_147 = eq(_T_146, UInt<5>(0h11)) \n node _T_148 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_149 = and(_T_147, _T_148) \n node _T_150 = leq(uncommonBits_7, UInt<2>(0h3)) \n node _T_151 = and(_T_149, _T_150) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) \n node _T_152 = shr(io.in.a.bits.source, 2) \n node _T_153 = eq(_T_152, UInt<5>(0h12)) \n node _T_154 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_155 = and(_T_153, _T_154) \n node _T_156 = leq(uncommonBits_8, UInt<2>(0h3)) \n node _T_157 = and(_T_155, _T_156) \n node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) \n node _T_158 = shr(io.in.a.bits.source, 2) \n node _T_159 = eq(_T_158, UInt<5>(0h13)) \n node _T_160 = leq(UInt<1>(0h0), uncommonBits_9) \n node _T_161 = and(_T_159, _T_160) \n node _T_162 = leq(uncommonBits_9, UInt<2>(0h3)) \n node _T_163 = and(_T_161, _T_162) \n node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) \n node _T_166 = shr(io.in.a.bits.source, 4) \n node _T_167 = eq(_T_166, UInt<1>(0h1)) \n node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) \n node _T_169 = and(_T_167, _T_168) \n node _T_170 = leq(uncommonBits_10, UInt<4>(0hf)) \n node _T_171 = and(_T_169, _T_170) \n node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) \n node _T_172 = shr(io.in.a.bits.source, 4) \n node _T_173 = eq(_T_172, UInt<1>(0h0)) \n node _T_174 = leq(UInt<1>(0h0), uncommonBits_11) \n node _T_175 = and(_T_173, _T_174) \n node _T_176 = leq(uncommonBits_11, UInt<4>(0hf)) \n node _T_177 = and(_T_175, _T_176) \n node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_180 = or(_T_139, _T_145) \n node _T_181 = or(_T_180, _T_151) \n node _T_182 = or(_T_181, _T_157) \n node _T_183 = or(_T_182, _T_163) \n node _T_184 = or(_T_183, _T_164) \n node _T_185 = or(_T_184, _T_165) \n node _T_186 = or(_T_185, _T_171) \n node _T_187 = or(_T_186, _T_177) \n node _T_188 = or(_T_187, _T_178) \n node _T_189 = or(_T_188, _T_179) \n node _T_190 = and(_T_138, _T_189) \n node _T_191 = or(UInt<1>(0h0), _T_190) \n node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_193 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_194 = cvt(_T_193) \n node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000))) \n node _T_196 = asSInt(_T_195) \n node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) \n node _T_198 = and(_T_192, _T_197) \n node _T_199 = or(UInt<1>(0h0), _T_198) \n node _T_200 = and(_T_191, _T_199) \n node _T_201 = asUInt(reset) \n node _T_202 = eq(_T_201, UInt<1>(0h0)) \n when _T_202 : \n node _T_203 = eq(_T_200, UInt<1>(0h0)) \n when _T_203 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_200, UInt<1>(0h1), \"\") : assert_2 \n node _T_204 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) \n node _T_205 = shr(io.in.a.bits.source, 2) \n node _T_206 = eq(_T_205, UInt<5>(0h10)) \n node _T_207 = leq(UInt<1>(0h0), uncommonBits_12) \n node _T_208 = and(_T_206, _T_207) \n node _T_209 = leq(uncommonBits_12, UInt<2>(0h3)) \n node _T_210 = and(_T_208, _T_209) \n node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) \n node _T_211 = shr(io.in.a.bits.source, 2) \n node _T_212 = eq(_T_211, UInt<5>(0h11)) \n node _T_213 = leq(UInt<1>(0h0), uncommonBits_13) \n node _T_214 = and(_T_212, _T_213) \n node _T_215 = leq(uncommonBits_13, UInt<2>(0h3)) \n node _T_216 = and(_T_214, _T_215) \n node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) \n node _T_217 = shr(io.in.a.bits.source, 2) \n node _T_218 = eq(_T_217, UInt<5>(0h12)) \n node _T_219 = leq(UInt<1>(0h0), uncommonBits_14) \n node _T_220 = and(_T_218, _T_219) \n node _T_221 = leq(uncommonBits_14, UInt<2>(0h3)) \n node _T_222 = and(_T_220, _T_221) \n node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) \n node _T_223 = shr(io.in.a.bits.source, 2) \n node _T_224 = eq(_T_223, UInt<5>(0h13)) \n node _T_225 = leq(UInt<1>(0h0), uncommonBits_15) \n node _T_226 = and(_T_224, _T_225) \n node _T_227 = leq(uncommonBits_15, UInt<2>(0h3)) \n node _T_228 = and(_T_226, _T_227) \n node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) \n node _T_231 = shr(io.in.a.bits.source, 4) \n node _T_232 = eq(_T_231, UInt<1>(0h1)) \n node _T_233 = leq(UInt<1>(0h0), uncommonBits_16) \n node _T_234 = and(_T_232, _T_233) \n node _T_235 = leq(uncommonBits_16, UInt<4>(0hf)) \n node _T_236 = and(_T_234, _T_235) \n node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) \n node _T_237 = shr(io.in.a.bits.source, 4) \n node _T_238 = eq(_T_237, UInt<1>(0h0)) \n node _T_239 = leq(UInt<1>(0h0), uncommonBits_17) \n node _T_240 = and(_T_238, _T_239) \n node _T_241 = leq(uncommonBits_17, UInt<4>(0hf)) \n node _T_242 = and(_T_240, _T_241) \n node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n wire _WIRE : UInt<1>[11] \n connect _WIRE[0], _T_204 \n connect _WIRE[1], _T_210 \n connect _WIRE[2], _T_216 \n connect _WIRE[3], _T_222 \n connect _WIRE[4], _T_228 \n connect _WIRE[5], _T_229 \n connect _WIRE[6], _T_230 \n connect _WIRE[7], _T_236 \n connect _WIRE[8], _T_242 \n connect _WIRE[9], _T_243 \n connect _WIRE[10], _T_244 \n node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_251 = mux(_WIRE[5], _T_245, UInt<1>(0h0)) \n node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_253 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_257 = or(_T_246, _T_247) \n node _T_258 = or(_T_257, _T_248) \n node _T_259 = or(_T_258, _T_249) \n node _T_260 = or(_T_259, _T_250) \n node _T_261 = or(_T_260, _T_251) \n node _T_262 = or(_T_261, _T_252) \n node _T_263 = or(_T_262, _T_253) \n node _T_264 = or(_T_263, _T_254) \n node _T_265 = or(_T_264, _T_255) \n node _T_266 = or(_T_265, _T_256) \n wire _WIRE_1 : UInt<1> \n connect _WIRE_1, _T_266 \n node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_269 = and(_T_267, _T_268) \n node _T_270 = or(UInt<1>(0h0), _T_269) \n node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_272 = cvt(_T_271) \n node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) \n node _T_274 = asSInt(_T_273) \n node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) \n node _T_276 = and(_T_270, _T_275) \n node _T_277 = or(UInt<1>(0h0), _T_276) \n node _T_278 = and(_WIRE_1, _T_277) \n node _T_279 = asUInt(reset) \n node _T_280 = eq(_T_279, UInt<1>(0h0)) \n when _T_280 : \n node _T_281 = eq(_T_278, UInt<1>(0h0)) \n when _T_281 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_278, UInt<1>(0h1), \"\") : assert_3 \n node _T_282 = asUInt(reset) \n node _T_283 = eq(_T_282, UInt<1>(0h0)) \n when _T_283 : \n node _T_284 = eq(source_ok, UInt<1>(0h0)) \n when _T_284 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_4 \n node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_286 = asUInt(reset) \n node _T_287 = eq(_T_286, UInt<1>(0h0)) \n when _T_287 : \n node _T_288 = eq(_T_285, UInt<1>(0h0)) \n when _T_288 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_285, UInt<1>(0h1), \"\") : assert_5 \n node _T_289 = asUInt(reset) \n node _T_290 = eq(_T_289, UInt<1>(0h0)) \n when _T_290 : \n node _T_291 = eq(is_aligned, UInt<1>(0h0)) \n when _T_291 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_293 = asUInt(reset) \n node _T_294 = eq(_T_293, UInt<1>(0h0)) \n when _T_294 : \n node _T_295 = eq(_T_292, UInt<1>(0h0)) \n when _T_295 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_292, UInt<1>(0h1), \"\") : assert_7 \n node _T_296 = not(io.in.a.bits.mask) \n node _T_297 = eq(_T_296, UInt<1>(0h0)) \n node _T_298 = asUInt(reset) \n node _T_299 = eq(_T_298, UInt<1>(0h0)) \n when _T_299 : \n node _T_300 = eq(_T_297, UInt<1>(0h0)) \n when _T_300 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_297, UInt<1>(0h1), \"\") : assert_8 \n node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_302 = asUInt(reset) \n node _T_303 = eq(_T_302, UInt<1>(0h0)) \n when _T_303 : \n node _T_304 = eq(_T_301, UInt<1>(0h0)) \n when _T_304 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_301, UInt<1>(0h1), \"\") : assert_9 \n node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_305 : \n node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_308 = and(_T_306, _T_307) \n node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) \n node _T_310 = shr(io.in.a.bits.source, 2) \n node _T_311 = eq(_T_310, UInt<5>(0h10)) \n node _T_312 = leq(UInt<1>(0h0), uncommonBits_18) \n node _T_313 = and(_T_311, _T_312) \n node _T_314 = leq(uncommonBits_18, UInt<2>(0h3)) \n node _T_315 = and(_T_313, _T_314) \n node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) \n node _T_316 = shr(io.in.a.bits.source, 2) \n node _T_317 = eq(_T_316, UInt<5>(0h11)) \n node _T_318 = leq(UInt<1>(0h0), uncommonBits_19) \n node _T_319 = and(_T_317, _T_318) \n node _T_320 = leq(uncommonBits_19, UInt<2>(0h3)) \n node _T_321 = and(_T_319, _T_320) \n node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) \n node _T_322 = shr(io.in.a.bits.source, 2) \n node _T_323 = eq(_T_322, UInt<5>(0h12)) \n node _T_324 = leq(UInt<1>(0h0), uncommonBits_20) \n node _T_325 = and(_T_323, _T_324) \n node _T_326 = leq(uncommonBits_20, UInt<2>(0h3)) \n node _T_327 = and(_T_325, _T_326) \n node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) \n node _T_328 = shr(io.in.a.bits.source, 2) \n node _T_329 = eq(_T_328, UInt<5>(0h13)) \n node _T_330 = leq(UInt<1>(0h0), uncommonBits_21) \n node _T_331 = and(_T_329, _T_330) \n node _T_332 = leq(uncommonBits_21, UInt<2>(0h3)) \n node _T_333 = and(_T_331, _T_332) \n node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) \n node _T_336 = shr(io.in.a.bits.source, 4) \n node _T_337 = eq(_T_336, UInt<1>(0h1)) \n node _T_338 = leq(UInt<1>(0h0), uncommonBits_22) \n node _T_339 = and(_T_337, _T_338) \n node _T_340 = leq(uncommonBits_22, UInt<4>(0hf)) \n node _T_341 = and(_T_339, _T_340) \n node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) \n node _T_342 = shr(io.in.a.bits.source, 4) \n node _T_343 = eq(_T_342, UInt<1>(0h0)) \n node _T_344 = leq(UInt<1>(0h0), uncommonBits_23) \n node _T_345 = and(_T_343, _T_344) \n node _T_346 = leq(uncommonBits_23, UInt<4>(0hf)) \n node _T_347 = and(_T_345, _T_346) \n node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_350 = or(_T_309, _T_315) \n node _T_351 = or(_T_350, _T_321) \n node _T_352 = or(_T_351, _T_327) \n node _T_353 = or(_T_352, _T_333) \n node _T_354 = or(_T_353, _T_334) \n node _T_355 = or(_T_354, _T_335) \n node _T_356 = or(_T_355, _T_341) \n node _T_357 = or(_T_356, _T_347) \n node _T_358 = or(_T_357, _T_348) \n node _T_359 = or(_T_358, _T_349) \n node _T_360 = and(_T_308, _T_359) \n node _T_361 = or(UInt<1>(0h0), _T_360) \n node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_363 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_364 = cvt(_T_363) \n node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000))) \n node _T_366 = asSInt(_T_365) \n node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0))) \n node _T_368 = and(_T_362, _T_367) \n node _T_369 = or(UInt<1>(0h0), _T_368) \n node _T_370 = and(_T_361, _T_369) \n node _T_371 = asUInt(reset) \n node _T_372 = eq(_T_371, UInt<1>(0h0)) \n when _T_372 : \n node _T_373 = eq(_T_370, UInt<1>(0h0)) \n when _T_373 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_370, UInt<1>(0h1), \"\") : assert_10 \n node _T_374 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) \n node _T_375 = shr(io.in.a.bits.source, 2) \n node _T_376 = eq(_T_375, UInt<5>(0h10)) \n node _T_377 = leq(UInt<1>(0h0), uncommonBits_24) \n node _T_378 = and(_T_376, _T_377) \n node _T_379 = leq(uncommonBits_24, UInt<2>(0h3)) \n node _T_380 = and(_T_378, _T_379) \n node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) \n node _T_381 = shr(io.in.a.bits.source, 2) \n node _T_382 = eq(_T_381, UInt<5>(0h11)) \n node _T_383 = leq(UInt<1>(0h0), uncommonBits_25) \n node _T_384 = and(_T_382, _T_383) \n node _T_385 = leq(uncommonBits_25, UInt<2>(0h3)) \n node _T_386 = and(_T_384, _T_385) \n node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) \n node _T_387 = shr(io.in.a.bits.source, 2) \n node _T_388 = eq(_T_387, UInt<5>(0h12)) \n node _T_389 = leq(UInt<1>(0h0), uncommonBits_26) \n node _T_390 = and(_T_388, _T_389) \n node _T_391 = leq(uncommonBits_26, UInt<2>(0h3)) \n node _T_392 = and(_T_390, _T_391) \n node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) \n node _T_393 = shr(io.in.a.bits.source, 2) \n node _T_394 = eq(_T_393, UInt<5>(0h13)) \n node _T_395 = leq(UInt<1>(0h0), uncommonBits_27) \n node _T_396 = and(_T_394, _T_395) \n node _T_397 = leq(uncommonBits_27, UInt<2>(0h3)) \n node _T_398 = and(_T_396, _T_397) \n node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) \n node _T_401 = shr(io.in.a.bits.source, 4) \n node _T_402 = eq(_T_401, UInt<1>(0h1)) \n node _T_403 = leq(UInt<1>(0h0), uncommonBits_28) \n node _T_404 = and(_T_402, _T_403) \n node _T_405 = leq(uncommonBits_28, UInt<4>(0hf)) \n node _T_406 = and(_T_404, _T_405) \n node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) \n node _T_407 = shr(io.in.a.bits.source, 4) \n node _T_408 = eq(_T_407, UInt<1>(0h0)) \n node _T_409 = leq(UInt<1>(0h0), uncommonBits_29) \n node _T_410 = and(_T_408, _T_409) \n node _T_411 = leq(uncommonBits_29, UInt<4>(0hf)) \n node _T_412 = and(_T_410, _T_411) \n node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n wire _WIRE_2 : UInt<1>[11] \n connect _WIRE_2[0], _T_374 \n connect _WIRE_2[1], _T_380 \n connect _WIRE_2[2], _T_386 \n connect _WIRE_2[3], _T_392 \n connect _WIRE_2[4], _T_398 \n connect _WIRE_2[5], _T_399 \n connect _WIRE_2[6], _T_400 \n connect _WIRE_2[7], _T_406 \n connect _WIRE_2[8], _T_412 \n connect _WIRE_2[9], _T_413 \n connect _WIRE_2[10], _T_414 \n node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_421 = mux(_WIRE_2[5], _T_415, UInt<1>(0h0)) \n node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_423 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_427 = or(_T_416, _T_417) \n node _T_428 = or(_T_427, _T_418) \n node _T_429 = or(_T_428, _T_419) \n node _T_430 = or(_T_429, _T_420) \n node _T_431 = or(_T_430, _T_421) \n node _T_432 = or(_T_431, _T_422) \n node _T_433 = or(_T_432, _T_423) \n node _T_434 = or(_T_433, _T_424) \n node _T_435 = or(_T_434, _T_425) \n node _T_436 = or(_T_435, _T_426) \n wire _WIRE_3 : UInt<1> \n connect _WIRE_3, _T_436 \n node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_439 = and(_T_437, _T_438) \n node _T_440 = or(UInt<1>(0h0), _T_439) \n node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_442 = cvt(_T_441) \n node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) \n node _T_444 = asSInt(_T_443) \n node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) \n node _T_446 = and(_T_440, _T_445) \n node _T_447 = or(UInt<1>(0h0), _T_446) \n node _T_448 = and(_WIRE_3, _T_447) \n node _T_449 = asUInt(reset) \n node _T_450 = eq(_T_449, UInt<1>(0h0)) \n when _T_450 : \n node _T_451 = eq(_T_448, UInt<1>(0h0)) \n when _T_451 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_448, UInt<1>(0h1), \"\") : assert_11 \n node _T_452 = asUInt(reset) \n node _T_453 = eq(_T_452, UInt<1>(0h0)) \n when _T_453 : \n node _T_454 = eq(source_ok, UInt<1>(0h0)) \n when _T_454 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_12 \n node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_456 = asUInt(reset) \n node _T_457 = eq(_T_456, UInt<1>(0h0)) \n when _T_457 : \n node _T_458 = eq(_T_455, UInt<1>(0h0)) \n when _T_458 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_455, UInt<1>(0h1), \"\") : assert_13 \n node _T_459 = asUInt(reset) \n node _T_460 = eq(_T_459, UInt<1>(0h0)) \n when _T_460 : \n node _T_461 = eq(is_aligned, UInt<1>(0h0)) \n when _T_461 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_463 = asUInt(reset) \n node _T_464 = eq(_T_463, UInt<1>(0h0)) \n when _T_464 : \n node _T_465 = eq(_T_462, UInt<1>(0h0)) \n when _T_465 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_462, UInt<1>(0h1), \"\") : assert_15 \n node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_467 = asUInt(reset) \n node _T_468 = eq(_T_467, UInt<1>(0h0)) \n when _T_468 : \n node _T_469 = eq(_T_466, UInt<1>(0h0)) \n when _T_469 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_466, UInt<1>(0h1), \"\") : assert_16 \n node _T_470 = not(io.in.a.bits.mask) \n node _T_471 = eq(_T_470, UInt<1>(0h0)) \n node _T_472 = asUInt(reset) \n node _T_473 = eq(_T_472, UInt<1>(0h0)) \n when _T_473 : \n node _T_474 = eq(_T_471, UInt<1>(0h0)) \n when _T_474 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_471, UInt<1>(0h1), \"\") : assert_17 \n node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_476 = asUInt(reset) \n node _T_477 = eq(_T_476, UInt<1>(0h0)) \n when _T_477 : \n node _T_478 = eq(_T_475, UInt<1>(0h0)) \n when _T_478 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_475, UInt<1>(0h1), \"\") : assert_18 \n node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_479 : \n node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_482 = and(_T_480, _T_481) \n node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) \n node _T_484 = shr(io.in.a.bits.source, 2) \n node _T_485 = eq(_T_484, UInt<5>(0h10)) \n node _T_486 = leq(UInt<1>(0h0), uncommonBits_30) \n node _T_487 = and(_T_485, _T_486) \n node _T_488 = leq(uncommonBits_30, UInt<2>(0h3)) \n node _T_489 = and(_T_487, _T_488) \n node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) \n node _T_490 = shr(io.in.a.bits.source, 2) \n node _T_491 = eq(_T_490, UInt<5>(0h11)) \n node _T_492 = leq(UInt<1>(0h0), uncommonBits_31) \n node _T_493 = and(_T_491, _T_492) \n node _T_494 = leq(uncommonBits_31, UInt<2>(0h3)) \n node _T_495 = and(_T_493, _T_494) \n node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) \n node _T_496 = shr(io.in.a.bits.source, 2) \n node _T_497 = eq(_T_496, UInt<5>(0h12)) \n node _T_498 = leq(UInt<1>(0h0), uncommonBits_32) \n node _T_499 = and(_T_497, _T_498) \n node _T_500 = leq(uncommonBits_32, UInt<2>(0h3)) \n node _T_501 = and(_T_499, _T_500) \n node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) \n node _T_502 = shr(io.in.a.bits.source, 2) \n node _T_503 = eq(_T_502, UInt<5>(0h13)) \n node _T_504 = leq(UInt<1>(0h0), uncommonBits_33) \n node _T_505 = and(_T_503, _T_504) \n node _T_506 = leq(uncommonBits_33, UInt<2>(0h3)) \n node _T_507 = and(_T_505, _T_506) \n node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) \n node _T_510 = shr(io.in.a.bits.source, 4) \n node _T_511 = eq(_T_510, UInt<1>(0h1)) \n node _T_512 = leq(UInt<1>(0h0), uncommonBits_34) \n node _T_513 = and(_T_511, _T_512) \n node _T_514 = leq(uncommonBits_34, UInt<4>(0hf)) \n node _T_515 = and(_T_513, _T_514) \n node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) \n node _T_516 = shr(io.in.a.bits.source, 4) \n node _T_517 = eq(_T_516, UInt<1>(0h0)) \n node _T_518 = leq(UInt<1>(0h0), uncommonBits_35) \n node _T_519 = and(_T_517, _T_518) \n node _T_520 = leq(uncommonBits_35, UInt<4>(0hf)) \n node _T_521 = and(_T_519, _T_520) \n node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_524 = or(_T_483, _T_489) \n node _T_525 = or(_T_524, _T_495) \n node _T_526 = or(_T_525, _T_501) \n node _T_527 = or(_T_526, _T_507) \n node _T_528 = or(_T_527, _T_508) \n node _T_529 = or(_T_528, _T_509) \n node _T_530 = or(_T_529, _T_515) \n node _T_531 = or(_T_530, _T_521) \n node _T_532 = or(_T_531, _T_522) \n node _T_533 = or(_T_532, _T_523) \n node _T_534 = and(_T_482, _T_533) \n node _T_535 = or(UInt<1>(0h0), _T_534) \n node _T_536 = asUInt(reset) \n node _T_537 = eq(_T_536, UInt<1>(0h0)) \n when _T_537 : \n node _T_538 = eq(_T_535, UInt<1>(0h0)) \n when _T_538 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_535, UInt<1>(0h1), \"\") : assert_19 \n node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_541 = and(_T_539, _T_540) \n node _T_542 = or(UInt<1>(0h0), _T_541) \n node _T_543 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_544 = cvt(_T_543) \n node _T_545 = and(_T_544, asSInt(UInt<13>(0h1000))) \n node _T_546 = asSInt(_T_545) \n node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0))) \n node _T_548 = and(_T_542, _T_547) \n node _T_549 = or(UInt<1>(0h0), _T_548) \n node _T_550 = asUInt(reset) \n node _T_551 = eq(_T_550, UInt<1>(0h0)) \n when _T_551 : \n node _T_552 = eq(_T_549, UInt<1>(0h0)) \n when _T_552 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_549, UInt<1>(0h1), \"\") : assert_20 \n node _T_553 = asUInt(reset) \n node _T_554 = eq(_T_553, UInt<1>(0h0)) \n when _T_554 : \n node _T_555 = eq(source_ok, UInt<1>(0h0)) \n when _T_555 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_21 \n node _T_556 = asUInt(reset) \n node _T_557 = eq(_T_556, UInt<1>(0h0)) \n when _T_557 : \n node _T_558 = eq(is_aligned, UInt<1>(0h0)) \n when _T_558 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_560 = asUInt(reset) \n node _T_561 = eq(_T_560, UInt<1>(0h0)) \n when _T_561 : \n node _T_562 = eq(_T_559, UInt<1>(0h0)) \n when _T_562 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_559, UInt<1>(0h1), \"\") : assert_23 \n node _T_563 = eq(io.in.a.bits.mask, mask) \n node _T_564 = asUInt(reset) \n node _T_565 = eq(_T_564, UInt<1>(0h0)) \n when _T_565 : \n node _T_566 = eq(_T_563, UInt<1>(0h0)) \n when _T_566 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_563, UInt<1>(0h1), \"\") : assert_24 \n node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_568 = asUInt(reset) \n node _T_569 = eq(_T_568, UInt<1>(0h0)) \n when _T_569 : \n node _T_570 = eq(_T_567, UInt<1>(0h0)) \n when _T_570 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_567, UInt<1>(0h1), \"\") : assert_25 \n node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_571 : \n node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_574 = and(_T_572, _T_573) \n node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) \n node _T_576 = shr(io.in.a.bits.source, 2) \n node _T_577 = eq(_T_576, UInt<5>(0h10)) \n node _T_578 = leq(UInt<1>(0h0), uncommonBits_36) \n node _T_579 = and(_T_577, _T_578) \n node _T_580 = leq(uncommonBits_36, UInt<2>(0h3)) \n node _T_581 = and(_T_579, _T_580) \n node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) \n node _T_582 = shr(io.in.a.bits.source, 2) \n node _T_583 = eq(_T_582, UInt<5>(0h11)) \n node _T_584 = leq(UInt<1>(0h0), uncommonBits_37) \n node _T_585 = and(_T_583, _T_584) \n node _T_586 = leq(uncommonBits_37, UInt<2>(0h3)) \n node _T_587 = and(_T_585, _T_586) \n node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) \n node _T_588 = shr(io.in.a.bits.source, 2) \n node _T_589 = eq(_T_588, UInt<5>(0h12)) \n node _T_590 = leq(UInt<1>(0h0), uncommonBits_38) \n node _T_591 = and(_T_589, _T_590) \n node _T_592 = leq(uncommonBits_38, UInt<2>(0h3)) \n node _T_593 = and(_T_591, _T_592) \n node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) \n node _T_594 = shr(io.in.a.bits.source, 2) \n node _T_595 = eq(_T_594, UInt<5>(0h13)) \n node _T_596 = leq(UInt<1>(0h0), uncommonBits_39) \n node _T_597 = and(_T_595, _T_596) \n node _T_598 = leq(uncommonBits_39, UInt<2>(0h3)) \n node _T_599 = and(_T_597, _T_598) \n node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0) \n node _T_602 = shr(io.in.a.bits.source, 4) \n node _T_603 = eq(_T_602, UInt<1>(0h1)) \n node _T_604 = leq(UInt<1>(0h0), uncommonBits_40) \n node _T_605 = and(_T_603, _T_604) \n node _T_606 = leq(uncommonBits_40, UInt<4>(0hf)) \n node _T_607 = and(_T_605, _T_606) \n node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0) \n node _T_608 = shr(io.in.a.bits.source, 4) \n node _T_609 = eq(_T_608, UInt<1>(0h0)) \n node _T_610 = leq(UInt<1>(0h0), uncommonBits_41) \n node _T_611 = and(_T_609, _T_610) \n node _T_612 = leq(uncommonBits_41, UInt<4>(0hf)) \n node _T_613 = and(_T_611, _T_612) \n node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_616 = or(_T_575, _T_581) \n node _T_617 = or(_T_616, _T_587) \n node _T_618 = or(_T_617, _T_593) \n node _T_619 = or(_T_618, _T_599) \n node _T_620 = or(_T_619, _T_600) \n node _T_621 = or(_T_620, _T_601) \n node _T_622 = or(_T_621, _T_607) \n node _T_623 = or(_T_622, _T_613) \n node _T_624 = or(_T_623, _T_614) \n node _T_625 = or(_T_624, _T_615) \n node _T_626 = and(_T_574, _T_625) \n node _T_627 = or(UInt<1>(0h0), _T_626) \n node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_630 = and(_T_628, _T_629) \n node _T_631 = or(UInt<1>(0h0), _T_630) \n node _T_632 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_633 = cvt(_T_632) \n node _T_634 = and(_T_633, asSInt(UInt<13>(0h1000))) \n node _T_635 = asSInt(_T_634) \n node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0))) \n node _T_637 = and(_T_631, _T_636) \n node _T_638 = or(UInt<1>(0h0), _T_637) \n node _T_639 = and(_T_627, _T_638) \n node _T_640 = asUInt(reset) \n node _T_641 = eq(_T_640, UInt<1>(0h0)) \n when _T_641 : \n node _T_642 = eq(_T_639, UInt<1>(0h0)) \n when _T_642 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_639, UInt<1>(0h1), \"\") : assert_26 \n node _T_643 = asUInt(reset) \n node _T_644 = eq(_T_643, UInt<1>(0h0)) \n when _T_644 : \n node _T_645 = eq(source_ok, UInt<1>(0h0)) \n when _T_645 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_27 \n node _T_646 = asUInt(reset) \n node _T_647 = eq(_T_646, UInt<1>(0h0)) \n when _T_647 : \n node _T_648 = eq(is_aligned, UInt<1>(0h0)) \n when _T_648 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_650 = asUInt(reset) \n node _T_651 = eq(_T_650, UInt<1>(0h0)) \n when _T_651 : \n node _T_652 = eq(_T_649, UInt<1>(0h0)) \n when _T_652 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_649, UInt<1>(0h1), \"\") : assert_29 \n node _T_653 = eq(io.in.a.bits.mask, mask) \n node _T_654 = asUInt(reset) \n node _T_655 = eq(_T_654, UInt<1>(0h0)) \n when _T_655 : \n node _T_656 = eq(_T_653, UInt<1>(0h0)) \n when _T_656 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_653, UInt<1>(0h1), \"\") : assert_30 \n node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_657 : \n node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_660 = and(_T_658, _T_659) \n node _T_661 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) \n node _T_662 = shr(io.in.a.bits.source, 2) \n node _T_663 = eq(_T_662, UInt<5>(0h10)) \n node _T_664 = leq(UInt<1>(0h0), uncommonBits_42) \n node _T_665 = and(_T_663, _T_664) \n node _T_666 = leq(uncommonBits_42, UInt<2>(0h3)) \n node _T_667 = and(_T_665, _T_666) \n node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) \n node _T_668 = shr(io.in.a.bits.source, 2) \n node _T_669 = eq(_T_668, UInt<5>(0h11)) \n node _T_670 = leq(UInt<1>(0h0), uncommonBits_43) \n node _T_671 = and(_T_669, _T_670) \n node _T_672 = leq(uncommonBits_43, UInt<2>(0h3)) \n node _T_673 = and(_T_671, _T_672) \n node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) \n node _T_674 = shr(io.in.a.bits.source, 2) \n node _T_675 = eq(_T_674, UInt<5>(0h12)) \n node _T_676 = leq(UInt<1>(0h0), uncommonBits_44) \n node _T_677 = and(_T_675, _T_676) \n node _T_678 = leq(uncommonBits_44, UInt<2>(0h3)) \n node _T_679 = and(_T_677, _T_678) \n node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) \n node _T_680 = shr(io.in.a.bits.source, 2) \n node _T_681 = eq(_T_680, UInt<5>(0h13)) \n node _T_682 = leq(UInt<1>(0h0), uncommonBits_45) \n node _T_683 = and(_T_681, _T_682) \n node _T_684 = leq(uncommonBits_45, UInt<2>(0h3)) \n node _T_685 = and(_T_683, _T_684) \n node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0) \n node _T_688 = shr(io.in.a.bits.source, 4) \n node _T_689 = eq(_T_688, UInt<1>(0h1)) \n node _T_690 = leq(UInt<1>(0h0), uncommonBits_46) \n node _T_691 = and(_T_689, _T_690) \n node _T_692 = leq(uncommonBits_46, UInt<4>(0hf)) \n node _T_693 = and(_T_691, _T_692) \n node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0) \n node _T_694 = shr(io.in.a.bits.source, 4) \n node _T_695 = eq(_T_694, UInt<1>(0h0)) \n node _T_696 = leq(UInt<1>(0h0), uncommonBits_47) \n node _T_697 = and(_T_695, _T_696) \n node _T_698 = leq(uncommonBits_47, UInt<4>(0hf)) \n node _T_699 = and(_T_697, _T_698) \n node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_701 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_702 = or(_T_661, _T_667) \n node _T_703 = or(_T_702, _T_673) \n node _T_704 = or(_T_703, _T_679) \n node _T_705 = or(_T_704, _T_685) \n node _T_706 = or(_T_705, _T_686) \n node _T_707 = or(_T_706, _T_687) \n node _T_708 = or(_T_707, _T_693) \n node _T_709 = or(_T_708, _T_699) \n node _T_710 = or(_T_709, _T_700) \n node _T_711 = or(_T_710, _T_701) \n node _T_712 = and(_T_660, _T_711) \n node _T_713 = or(UInt<1>(0h0), _T_712) \n node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_716 = and(_T_714, _T_715) \n node _T_717 = or(UInt<1>(0h0), _T_716) \n node _T_718 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_719 = cvt(_T_718) \n node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) \n node _T_721 = asSInt(_T_720) \n node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) \n node _T_723 = and(_T_717, _T_722) \n node _T_724 = or(UInt<1>(0h0), _T_723) \n node _T_725 = and(_T_713, _T_724) \n node _T_726 = asUInt(reset) \n node _T_727 = eq(_T_726, UInt<1>(0h0)) \n when _T_727 : \n node _T_728 = eq(_T_725, UInt<1>(0h0)) \n when _T_728 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_725, UInt<1>(0h1), \"\") : assert_31 \n node _T_729 = asUInt(reset) \n node _T_730 = eq(_T_729, UInt<1>(0h0)) \n when _T_730 : \n node _T_731 = eq(source_ok, UInt<1>(0h0)) \n when _T_731 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_32 \n node _T_732 = asUInt(reset) \n node _T_733 = eq(_T_732, UInt<1>(0h0)) \n when _T_733 : \n node _T_734 = eq(is_aligned, UInt<1>(0h0)) \n when _T_734 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_736 = asUInt(reset) \n node _T_737 = eq(_T_736, UInt<1>(0h0)) \n when _T_737 : \n node _T_738 = eq(_T_735, UInt<1>(0h0)) \n when _T_738 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_735, UInt<1>(0h1), \"\") : assert_34 \n node _T_739 = not(mask) \n node _T_740 = and(io.in.a.bits.mask, _T_739) \n node _T_741 = eq(_T_740, UInt<1>(0h0)) \n node _T_742 = asUInt(reset) \n node _T_743 = eq(_T_742, UInt<1>(0h0)) \n when _T_743 : \n node _T_744 = eq(_T_741, UInt<1>(0h0)) \n when _T_744 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_741, UInt<1>(0h1), \"\") : assert_35 \n node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_745 : \n node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_748 = and(_T_746, _T_747) \n node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) \n node _T_750 = shr(io.in.a.bits.source, 2) \n node _T_751 = eq(_T_750, UInt<5>(0h10)) \n node _T_752 = leq(UInt<1>(0h0), uncommonBits_48) \n node _T_753 = and(_T_751, _T_752) \n node _T_754 = leq(uncommonBits_48, UInt<2>(0h3)) \n node _T_755 = and(_T_753, _T_754) \n node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) \n node _T_756 = shr(io.in.a.bits.source, 2) \n node _T_757 = eq(_T_756, UInt<5>(0h11)) \n node _T_758 = leq(UInt<1>(0h0), uncommonBits_49) \n node _T_759 = and(_T_757, _T_758) \n node _T_760 = leq(uncommonBits_49, UInt<2>(0h3)) \n node _T_761 = and(_T_759, _T_760) \n node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) \n node _T_762 = shr(io.in.a.bits.source, 2) \n node _T_763 = eq(_T_762, UInt<5>(0h12)) \n node _T_764 = leq(UInt<1>(0h0), uncommonBits_50) \n node _T_765 = and(_T_763, _T_764) \n node _T_766 = leq(uncommonBits_50, UInt<2>(0h3)) \n node _T_767 = and(_T_765, _T_766) \n node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) \n node _T_768 = shr(io.in.a.bits.source, 2) \n node _T_769 = eq(_T_768, UInt<5>(0h13)) \n node _T_770 = leq(UInt<1>(0h0), uncommonBits_51) \n node _T_771 = and(_T_769, _T_770) \n node _T_772 = leq(uncommonBits_51, UInt<2>(0h3)) \n node _T_773 = and(_T_771, _T_772) \n node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0) \n node _T_776 = shr(io.in.a.bits.source, 4) \n node _T_777 = eq(_T_776, UInt<1>(0h1)) \n node _T_778 = leq(UInt<1>(0h0), uncommonBits_52) \n node _T_779 = and(_T_777, _T_778) \n node _T_780 = leq(uncommonBits_52, UInt<4>(0hf)) \n node _T_781 = and(_T_779, _T_780) \n node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0) \n node _T_782 = shr(io.in.a.bits.source, 4) \n node _T_783 = eq(_T_782, UInt<1>(0h0)) \n node _T_784 = leq(UInt<1>(0h0), uncommonBits_53) \n node _T_785 = and(_T_783, _T_784) \n node _T_786 = leq(uncommonBits_53, UInt<4>(0hf)) \n node _T_787 = and(_T_785, _T_786) \n node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_789 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_790 = or(_T_749, _T_755) \n node _T_791 = or(_T_790, _T_761) \n node _T_792 = or(_T_791, _T_767) \n node _T_793 = or(_T_792, _T_773) \n node _T_794 = or(_T_793, _T_774) \n node _T_795 = or(_T_794, _T_775) \n node _T_796 = or(_T_795, _T_781) \n node _T_797 = or(_T_796, _T_787) \n node _T_798 = or(_T_797, _T_788) \n node _T_799 = or(_T_798, _T_789) \n node _T_800 = and(_T_748, _T_799) \n node _T_801 = or(UInt<1>(0h0), _T_800) \n node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_803 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_804 = cvt(_T_803) \n node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000))) \n node _T_806 = asSInt(_T_805) \n node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) \n node _T_808 = and(_T_802, _T_807) \n node _T_809 = or(UInt<1>(0h0), _T_808) \n node _T_810 = and(_T_801, _T_809) \n node _T_811 = asUInt(reset) \n node _T_812 = eq(_T_811, UInt<1>(0h0)) \n when _T_812 : \n node _T_813 = eq(_T_810, UInt<1>(0h0)) \n when _T_813 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_810, UInt<1>(0h1), \"\") : assert_36 \n node _T_814 = asUInt(reset) \n node _T_815 = eq(_T_814, UInt<1>(0h0)) \n when _T_815 : \n node _T_816 = eq(source_ok, UInt<1>(0h0)) \n when _T_816 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_37 \n node _T_817 = asUInt(reset) \n node _T_818 = eq(_T_817, UInt<1>(0h0)) \n when _T_818 : \n node _T_819 = eq(is_aligned, UInt<1>(0h0)) \n when _T_819 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_821 = asUInt(reset) \n node _T_822 = eq(_T_821, UInt<1>(0h0)) \n when _T_822 : \n node _T_823 = eq(_T_820, UInt<1>(0h0)) \n when _T_823 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_820, UInt<1>(0h1), \"\") : assert_39 \n node _T_824 = eq(io.in.a.bits.mask, mask) \n node _T_825 = asUInt(reset) \n node _T_826 = eq(_T_825, UInt<1>(0h0)) \n when _T_826 : \n node _T_827 = eq(_T_824, UInt<1>(0h0)) \n when _T_827 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_824, UInt<1>(0h1), \"\") : assert_40 \n node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_828 : \n node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_831 = and(_T_829, _T_830) \n node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) \n node _T_833 = shr(io.in.a.bits.source, 2) \n node _T_834 = eq(_T_833, UInt<5>(0h10)) \n node _T_835 = leq(UInt<1>(0h0), uncommonBits_54) \n node _T_836 = and(_T_834, _T_835) \n node _T_837 = leq(uncommonBits_54, UInt<2>(0h3)) \n node _T_838 = and(_T_836, _T_837) \n node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) \n node _T_839 = shr(io.in.a.bits.source, 2) \n node _T_840 = eq(_T_839, UInt<5>(0h11)) \n node _T_841 = leq(UInt<1>(0h0), uncommonBits_55) \n node _T_842 = and(_T_840, _T_841) \n node _T_843 = leq(uncommonBits_55, UInt<2>(0h3)) \n node _T_844 = and(_T_842, _T_843) \n node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) \n node _T_845 = shr(io.in.a.bits.source, 2) \n node _T_846 = eq(_T_845, UInt<5>(0h12)) \n node _T_847 = leq(UInt<1>(0h0), uncommonBits_56) \n node _T_848 = and(_T_846, _T_847) \n node _T_849 = leq(uncommonBits_56, UInt<2>(0h3)) \n node _T_850 = and(_T_848, _T_849) \n node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) \n node _T_851 = shr(io.in.a.bits.source, 2) \n node _T_852 = eq(_T_851, UInt<5>(0h13)) \n node _T_853 = leq(UInt<1>(0h0), uncommonBits_57) \n node _T_854 = and(_T_852, _T_853) \n node _T_855 = leq(uncommonBits_57, UInt<2>(0h3)) \n node _T_856 = and(_T_854, _T_855) \n node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0) \n node _T_859 = shr(io.in.a.bits.source, 4) \n node _T_860 = eq(_T_859, UInt<1>(0h1)) \n node _T_861 = leq(UInt<1>(0h0), uncommonBits_58) \n node _T_862 = and(_T_860, _T_861) \n node _T_863 = leq(uncommonBits_58, UInt<4>(0hf)) \n node _T_864 = and(_T_862, _T_863) \n node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0) \n node _T_865 = shr(io.in.a.bits.source, 4) \n node _T_866 = eq(_T_865, UInt<1>(0h0)) \n node _T_867 = leq(UInt<1>(0h0), uncommonBits_59) \n node _T_868 = and(_T_866, _T_867) \n node _T_869 = leq(uncommonBits_59, UInt<4>(0hf)) \n node _T_870 = and(_T_868, _T_869) \n node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_872 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_873 = or(_T_832, _T_838) \n node _T_874 = or(_T_873, _T_844) \n node _T_875 = or(_T_874, _T_850) \n node _T_876 = or(_T_875, _T_856) \n node _T_877 = or(_T_876, _T_857) \n node _T_878 = or(_T_877, _T_858) \n node _T_879 = or(_T_878, _T_864) \n node _T_880 = or(_T_879, _T_870) \n node _T_881 = or(_T_880, _T_871) \n node _T_882 = or(_T_881, _T_872) \n node _T_883 = and(_T_831, _T_882) \n node _T_884 = or(UInt<1>(0h0), _T_883) \n node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_886 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_887 = cvt(_T_886) \n node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000))) \n node _T_889 = asSInt(_T_888) \n node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) \n node _T_891 = and(_T_885, _T_890) \n node _T_892 = or(UInt<1>(0h0), _T_891) \n node _T_893 = and(_T_884, _T_892) \n node _T_894 = asUInt(reset) \n node _T_895 = eq(_T_894, UInt<1>(0h0)) \n when _T_895 : \n node _T_896 = eq(_T_893, UInt<1>(0h0)) \n when _T_896 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_893, UInt<1>(0h1), \"\") : assert_41 \n node _T_897 = asUInt(reset) \n node _T_898 = eq(_T_897, UInt<1>(0h0)) \n when _T_898 : \n node _T_899 = eq(source_ok, UInt<1>(0h0)) \n when _T_899 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_42 \n node _T_900 = asUInt(reset) \n node _T_901 = eq(_T_900, UInt<1>(0h0)) \n when _T_901 : \n node _T_902 = eq(is_aligned, UInt<1>(0h0)) \n when _T_902 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_904 = asUInt(reset) \n node _T_905 = eq(_T_904, UInt<1>(0h0)) \n when _T_905 : \n node _T_906 = eq(_T_903, UInt<1>(0h0)) \n when _T_906 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_903, UInt<1>(0h1), \"\") : assert_44 \n node _T_907 = eq(io.in.a.bits.mask, mask) \n node _T_908 = asUInt(reset) \n node _T_909 = eq(_T_908, UInt<1>(0h0)) \n when _T_909 : \n node _T_910 = eq(_T_907, UInt<1>(0h0)) \n when _T_910 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_907, UInt<1>(0h1), \"\") : assert_45 \n node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_911 : \n node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_914 = and(_T_912, _T_913) \n node _T_915 = eq(io.in.a.bits.source, UInt<7>(0h50)) \n node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) \n node _T_916 = shr(io.in.a.bits.source, 2) \n node _T_917 = eq(_T_916, UInt<5>(0h10)) \n node _T_918 = leq(UInt<1>(0h0), uncommonBits_60) \n node _T_919 = and(_T_917, _T_918) \n node _T_920 = leq(uncommonBits_60, UInt<2>(0h3)) \n node _T_921 = and(_T_919, _T_920) \n node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) \n node _T_922 = shr(io.in.a.bits.source, 2) \n node _T_923 = eq(_T_922, UInt<5>(0h11)) \n node _T_924 = leq(UInt<1>(0h0), uncommonBits_61) \n node _T_925 = and(_T_923, _T_924) \n node _T_926 = leq(uncommonBits_61, UInt<2>(0h3)) \n node _T_927 = and(_T_925, _T_926) \n node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) \n node _T_928 = shr(io.in.a.bits.source, 2) \n node _T_929 = eq(_T_928, UInt<5>(0h12)) \n node _T_930 = leq(UInt<1>(0h0), uncommonBits_62) \n node _T_931 = and(_T_929, _T_930) \n node _T_932 = leq(uncommonBits_62, UInt<2>(0h3)) \n node _T_933 = and(_T_931, _T_932) \n node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) \n node _T_934 = shr(io.in.a.bits.source, 2) \n node _T_935 = eq(_T_934, UInt<5>(0h13)) \n node _T_936 = leq(UInt<1>(0h0), uncommonBits_63) \n node _T_937 = and(_T_935, _T_936) \n node _T_938 = leq(uncommonBits_63, UInt<2>(0h3)) \n node _T_939 = and(_T_937, _T_938) \n node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h20)) \n node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h21)) \n node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0) \n node _T_942 = shr(io.in.a.bits.source, 4) \n node _T_943 = eq(_T_942, UInt<1>(0h1)) \n node _T_944 = leq(UInt<1>(0h0), uncommonBits_64) \n node _T_945 = and(_T_943, _T_944) \n node _T_946 = leq(uncommonBits_64, UInt<4>(0hf)) \n node _T_947 = and(_T_945, _T_946) \n node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0) \n node _T_948 = shr(io.in.a.bits.source, 4) \n node _T_949 = eq(_T_948, UInt<1>(0h0)) \n node _T_950 = leq(UInt<1>(0h0), uncommonBits_65) \n node _T_951 = and(_T_949, _T_950) \n node _T_952 = leq(uncommonBits_65, UInt<4>(0hf)) \n node _T_953 = and(_T_951, _T_952) \n node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h22)) \n node _T_955 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_956 = or(_T_915, _T_921) \n node _T_957 = or(_T_956, _T_927) \n node _T_958 = or(_T_957, _T_933) \n node _T_959 = or(_T_958, _T_939) \n node _T_960 = or(_T_959, _T_940) \n node _T_961 = or(_T_960, _T_941) \n node _T_962 = or(_T_961, _T_947) \n node _T_963 = or(_T_962, _T_953) \n node _T_964 = or(_T_963, _T_954) \n node _T_965 = or(_T_964, _T_955) \n node _T_966 = and(_T_914, _T_965) \n node _T_967 = or(UInt<1>(0h0), _T_966) \n node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_969 = xor(io.in.a.bits.address, UInt<21>(0h110000)) \n node _T_970 = cvt(_T_969) \n node _T_971 = and(_T_970, asSInt(UInt<13>(0h1000))) \n node _T_972 = asSInt(_T_971) \n node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0))) \n node _T_974 = and(_T_968, _T_973) \n node _T_975 = or(UInt<1>(0h0), _T_974) \n node _T_976 = and(_T_967, _T_975) \n node _T_977 = asUInt(reset) \n node _T_978 = eq(_T_977, UInt<1>(0h0)) \n when _T_978 : \n node _T_979 = eq(_T_976, UInt<1>(0h0)) \n when _T_979 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_976, UInt<1>(0h1), \"\") : assert_46 \n node _T_980 = asUInt(reset) \n node _T_981 = eq(_T_980, UInt<1>(0h0)) \n when _T_981 : \n node _T_982 = eq(source_ok, UInt<1>(0h0)) \n when _T_982 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_47 \n node _T_983 = asUInt(reset) \n node _T_984 = eq(_T_983, UInt<1>(0h0)) \n when _T_984 : \n node _T_985 = eq(is_aligned, UInt<1>(0h0)) \n when _T_985 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_987 = asUInt(reset) \n node _T_988 = eq(_T_987, UInt<1>(0h0)) \n when _T_988 : \n node _T_989 = eq(_T_986, UInt<1>(0h0)) \n when _T_989 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_986, UInt<1>(0h1), \"\") : assert_49 \n node _T_990 = eq(io.in.a.bits.mask, mask) \n node _T_991 = asUInt(reset) \n node _T_992 = eq(_T_991, UInt<1>(0h0)) \n when _T_992 : \n node _T_993 = eq(_T_990, UInt<1>(0h0)) \n when _T_993 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_990, UInt<1>(0h1), \"\") : assert_50 \n node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_995 = asUInt(reset) \n node _T_996 = eq(_T_995, UInt<1>(0h0)) \n when _T_996 : \n node _T_997 = eq(_T_994, UInt<1>(0h0)) \n when _T_997 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_994, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_999 = asUInt(reset) \n node _T_1000 = eq(_T_999, UInt<1>(0h0)) \n when _T_1000 : \n node _T_1001 = eq(_T_998, UInt<1>(0h0)) \n when _T_1001 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_998, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50)) \n node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) \n node _source_ok_T_51 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10)) \n node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) \n node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) \n node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) \n node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) \n node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) \n node _source_ok_T_57 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11)) \n node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) \n node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) \n node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) \n node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) \n node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) \n node _source_ok_T_63 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12)) \n node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) \n node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) \n node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) \n node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) \n node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) \n node _source_ok_T_69 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13)) \n node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) \n node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) \n node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) \n node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) \n node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) \n node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21)) \n node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0)) \n node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0) \n node _source_ok_T_77 = shr(io.in.d.bits.source, 4) \n node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1)) \n node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) \n node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) \n node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf)) \n node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) \n node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0)) \n node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0) \n node _source_ok_T_83 = shr(io.in.d.bits.source, 4) \n node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0)) \n node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) \n node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) \n node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf)) \n node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) \n node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22)) \n node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80)) \n wire _source_ok_WIRE_1 : UInt<1>[11] \n connect _source_ok_WIRE_1[0], _source_ok_T_50 \n connect _source_ok_WIRE_1[1], _source_ok_T_56 \n connect _source_ok_WIRE_1[2], _source_ok_T_62 \n connect _source_ok_WIRE_1[3], _source_ok_T_68 \n connect _source_ok_WIRE_1[4], _source_ok_T_74 \n connect _source_ok_WIRE_1[5], _source_ok_T_75 \n connect _source_ok_WIRE_1[6], _source_ok_T_76 \n connect _source_ok_WIRE_1[7], _source_ok_T_82 \n connect _source_ok_WIRE_1[8], _source_ok_T_88 \n connect _source_ok_WIRE_1[9], _source_ok_T_89 \n connect _source_ok_WIRE_1[10], _source_ok_T_90 \n node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) \n node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2]) \n node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3]) \n node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4]) \n node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5]) \n node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6]) \n node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7]) \n node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8]) \n node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9]) \n node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10]) \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_1002 : \n node _T_1003 = asUInt(reset) \n node _T_1004 = eq(_T_1003, UInt<1>(0h0)) \n when _T_1004 : \n node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1005 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_53 \n node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1007 = asUInt(reset) \n node _T_1008 = eq(_T_1007, UInt<1>(0h0)) \n when _T_1008 : \n node _T_1009 = eq(_T_1006, UInt<1>(0h0)) \n when _T_1009 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_1006, UInt<1>(0h1), \"\") : assert_54 \n node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1011 = asUInt(reset) \n node _T_1012 = eq(_T_1011, UInt<1>(0h0)) \n when _T_1012 : \n node _T_1013 = eq(_T_1010, UInt<1>(0h0)) \n when _T_1013 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_1010, UInt<1>(0h1), \"\") : assert_55 \n node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1015 = asUInt(reset) \n node _T_1016 = eq(_T_1015, UInt<1>(0h0)) \n when _T_1016 : \n node _T_1017 = eq(_T_1014, UInt<1>(0h0)) \n when _T_1017 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_1014, UInt<1>(0h1), \"\") : assert_56 \n node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1019 = asUInt(reset) \n node _T_1020 = eq(_T_1019, UInt<1>(0h0)) \n when _T_1020 : \n node _T_1021 = eq(_T_1018, UInt<1>(0h0)) \n when _T_1021 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_1018, UInt<1>(0h1), \"\") : assert_57 \n node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_1022 : \n node _T_1023 = asUInt(reset) \n node _T_1024 = eq(_T_1023, UInt<1>(0h0)) \n when _T_1024 : \n node _T_1025 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1025 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_58 \n node _T_1026 = asUInt(reset) \n node _T_1027 = eq(_T_1026, UInt<1>(0h0)) \n when _T_1027 : \n node _T_1028 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1028 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1030 = asUInt(reset) \n node _T_1031 = eq(_T_1030, UInt<1>(0h0)) \n when _T_1031 : \n node _T_1032 = eq(_T_1029, UInt<1>(0h0)) \n when _T_1032 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_1029, UInt<1>(0h1), \"\") : assert_60 \n node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1034 = asUInt(reset) \n node _T_1035 = eq(_T_1034, UInt<1>(0h0)) \n when _T_1035 : \n node _T_1036 = eq(_T_1033, UInt<1>(0h0)) \n when _T_1036 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_1033, UInt<1>(0h1), \"\") : assert_61 \n node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1038 = asUInt(reset) \n node _T_1039 = eq(_T_1038, UInt<1>(0h0)) \n when _T_1039 : \n node _T_1040 = eq(_T_1037, UInt<1>(0h0)) \n when _T_1040 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_1037, UInt<1>(0h1), \"\") : assert_62 \n node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1042 = asUInt(reset) \n node _T_1043 = eq(_T_1042, UInt<1>(0h0)) \n when _T_1043 : \n node _T_1044 = eq(_T_1041, UInt<1>(0h0)) \n when _T_1044 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_1041, UInt<1>(0h1), \"\") : assert_63 \n node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1046 = or(UInt<1>(0h0), _T_1045) \n node _T_1047 = asUInt(reset) \n node _T_1048 = eq(_T_1047, UInt<1>(0h0)) \n when _T_1048 : \n node _T_1049 = eq(_T_1046, UInt<1>(0h0)) \n when _T_1049 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_1046, UInt<1>(0h1), \"\") : assert_64 \n node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_1050 : \n node _T_1051 = asUInt(reset) \n node _T_1052 = eq(_T_1051, UInt<1>(0h0)) \n when _T_1052 : \n node _T_1053 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1053 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_65 \n node _T_1054 = asUInt(reset) \n node _T_1055 = eq(_T_1054, UInt<1>(0h0)) \n when _T_1055 : \n node _T_1056 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1056 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1058 = asUInt(reset) \n node _T_1059 = eq(_T_1058, UInt<1>(0h0)) \n when _T_1059 : \n node _T_1060 = eq(_T_1057, UInt<1>(0h0)) \n when _T_1060 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_1057, UInt<1>(0h1), \"\") : assert_67 \n node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1062 = asUInt(reset) \n node _T_1063 = eq(_T_1062, UInt<1>(0h0)) \n when _T_1063 : \n node _T_1064 = eq(_T_1061, UInt<1>(0h0)) \n when _T_1064 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_1061, UInt<1>(0h1), \"\") : assert_68 \n node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1066 = asUInt(reset) \n node _T_1067 = eq(_T_1066, UInt<1>(0h0)) \n when _T_1067 : \n node _T_1068 = eq(_T_1065, UInt<1>(0h0)) \n when _T_1068 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_1065, UInt<1>(0h1), \"\") : assert_69 \n node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1070 = or(_T_1069, io.in.d.bits.corrupt) \n node _T_1071 = asUInt(reset) \n node _T_1072 = eq(_T_1071, UInt<1>(0h0)) \n when _T_1072 : \n node _T_1073 = eq(_T_1070, UInt<1>(0h0)) \n when _T_1073 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_1070, UInt<1>(0h1), \"\") : assert_70 \n node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1075 = or(UInt<1>(0h0), _T_1074) \n node _T_1076 = asUInt(reset) \n node _T_1077 = eq(_T_1076, UInt<1>(0h0)) \n when _T_1077 : \n node _T_1078 = eq(_T_1075, UInt<1>(0h0)) \n when _T_1078 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_1075, UInt<1>(0h1), \"\") : assert_71 \n node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_1079 : \n node _T_1080 = asUInt(reset) \n node _T_1081 = eq(_T_1080, UInt<1>(0h0)) \n when _T_1081 : \n node _T_1082 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1082 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_72 \n node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1084 = asUInt(reset) \n node _T_1085 = eq(_T_1084, UInt<1>(0h0)) \n when _T_1085 : \n node _T_1086 = eq(_T_1083, UInt<1>(0h0)) \n when _T_1086 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_1083, UInt<1>(0h1), \"\") : assert_73 \n node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1088 = asUInt(reset) \n node _T_1089 = eq(_T_1088, UInt<1>(0h0)) \n when _T_1089 : \n node _T_1090 = eq(_T_1087, UInt<1>(0h0)) \n when _T_1090 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_1087, UInt<1>(0h1), \"\") : assert_74 \n node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1092 = or(UInt<1>(0h0), _T_1091) \n node _T_1093 = asUInt(reset) \n node _T_1094 = eq(_T_1093, UInt<1>(0h0)) \n when _T_1094 : \n node _T_1095 = eq(_T_1092, UInt<1>(0h0)) \n when _T_1095 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_1092, UInt<1>(0h1), \"\") : assert_75 \n node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_1096 : \n node _T_1097 = asUInt(reset) \n node _T_1098 = eq(_T_1097, UInt<1>(0h0)) \n when _T_1098 : \n node _T_1099 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1099 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_76 \n node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1101 = asUInt(reset) \n node _T_1102 = eq(_T_1101, UInt<1>(0h0)) \n when _T_1102 : \n node _T_1103 = eq(_T_1100, UInt<1>(0h0)) \n when _T_1103 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_1100, UInt<1>(0h1), \"\") : assert_77 \n node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1105 = or(_T_1104, io.in.d.bits.corrupt) \n node _T_1106 = asUInt(reset) \n node _T_1107 = eq(_T_1106, UInt<1>(0h0)) \n when _T_1107 : \n node _T_1108 = eq(_T_1105, UInt<1>(0h0)) \n when _T_1108 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_1105, UInt<1>(0h1), \"\") : assert_78 \n node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1110 = or(UInt<1>(0h0), _T_1109) \n node _T_1111 = asUInt(reset) \n node _T_1112 = eq(_T_1111, UInt<1>(0h0)) \n when _T_1112 : \n node _T_1113 = eq(_T_1110, UInt<1>(0h0)) \n when _T_1113 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_1110, UInt<1>(0h1), \"\") : assert_79 \n node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_1114 : \n node _T_1115 = asUInt(reset) \n node _T_1116 = eq(_T_1115, UInt<1>(0h0)) \n when _T_1116 : \n node _T_1117 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1117 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_80 \n node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1119 = asUInt(reset) \n node _T_1120 = eq(_T_1119, UInt<1>(0h0)) \n when _T_1120 : \n node _T_1121 = eq(_T_1118, UInt<1>(0h0)) \n when _T_1121 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_1118, UInt<1>(0h1), \"\") : assert_81 \n node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1123 = asUInt(reset) \n node _T_1124 = eq(_T_1123, UInt<1>(0h0)) \n when _T_1124 : \n node _T_1125 = eq(_T_1122, UInt<1>(0h0)) \n when _T_1125 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_1122, UInt<1>(0h1), \"\") : assert_82 \n node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1127 = or(UInt<1>(0h0), _T_1126) \n node _T_1128 = asUInt(reset) \n node _T_1129 = eq(_T_1128, UInt<1>(0h0)) \n when _T_1129 : \n node _T_1130 = eq(_T_1127, UInt<1>(0h0)) \n when _T_1130 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_1127, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_4.bits.data, UInt<64>(0h0) \n connect _WIRE_4.bits.mask, UInt<8>(0h0) \n connect _WIRE_4.bits.address, UInt<21>(0h0) \n connect _WIRE_4.bits.source, UInt<8>(0h0) \n connect _WIRE_4.bits.size, UInt<3>(0h0) \n connect _WIRE_4.bits.param, UInt<2>(0h0) \n connect _WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_1132 = asUInt(reset) \n node _T_1133 = eq(_T_1132, UInt<1>(0h0)) \n when _T_1133 : \n node _T_1134 = eq(_T_1131, UInt<1>(0h0)) \n when _T_1134 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_1131, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<21>(0h0) \n connect _WIRE_6.bits.source, UInt<8>(0h0) \n connect _WIRE_6.bits.size, UInt<3>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0)) \n node _T_1136 = asUInt(reset) \n node _T_1137 = eq(_T_1136, UInt<1>(0h0)) \n when _T_1137 : \n node _T_1138 = eq(_T_1135, UInt<1>(0h0)) \n when _T_1138 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_1135, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_8.bits.sink, UInt<1>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0)) \n node _T_1140 = asUInt(reset) \n node _T_1141 = eq(_T_1140, UInt<1>(0h0)) \n when _T_1141 : \n node _T_1142 = eq(_T_1139, UInt<1>(0h0)) \n when _T_1142 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_1139, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_1143 = eq(a_first, UInt<1>(0h0)) \n node _T_1144 = and(io.in.a.valid, _T_1143) \n when _T_1144 : \n node _T_1145 = eq(io.in.a.bits.opcode, opcode) \n node _T_1146 = asUInt(reset) \n node _T_1147 = eq(_T_1146, UInt<1>(0h0)) \n when _T_1147 : \n node _T_1148 = eq(_T_1145, UInt<1>(0h0)) \n when _T_1148 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_1145, UInt<1>(0h1), \"\") : assert_87 \n node _T_1149 = eq(io.in.a.bits.param, param) \n node _T_1150 = asUInt(reset) \n node _T_1151 = eq(_T_1150, UInt<1>(0h0)) \n when _T_1151 : \n node _T_1152 = eq(_T_1149, UInt<1>(0h0)) \n when _T_1152 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_1149, UInt<1>(0h1), \"\") : assert_88 \n node _T_1153 = eq(io.in.a.bits.size, size) \n node _T_1154 = asUInt(reset) \n node _T_1155 = eq(_T_1154, UInt<1>(0h0)) \n when _T_1155 : \n node _T_1156 = eq(_T_1153, UInt<1>(0h0)) \n when _T_1156 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_1153, UInt<1>(0h1), \"\") : assert_89 \n node _T_1157 = eq(io.in.a.bits.source, source) \n node _T_1158 = asUInt(reset) \n node _T_1159 = eq(_T_1158, UInt<1>(0h0)) \n when _T_1159 : \n node _T_1160 = eq(_T_1157, UInt<1>(0h0)) \n when _T_1160 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_1157, UInt<1>(0h1), \"\") : assert_90 \n node _T_1161 = eq(io.in.a.bits.address, address) \n node _T_1162 = asUInt(reset) \n node _T_1163 = eq(_T_1162, UInt<1>(0h0)) \n when _T_1163 : \n node _T_1164 = eq(_T_1161, UInt<1>(0h0)) \n when _T_1164 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_1161, UInt<1>(0h1), \"\") : assert_91 \n node _T_1165 = and(io.in.a.ready, io.in.a.valid) \n node _T_1166 = and(_T_1165, a_first) \n when _T_1166 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_1167 = eq(d_first, UInt<1>(0h0)) \n node _T_1168 = and(io.in.d.valid, _T_1167) \n when _T_1168 : \n node _T_1169 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_1170 = asUInt(reset) \n node _T_1171 = eq(_T_1170, UInt<1>(0h0)) \n when _T_1171 : \n node _T_1172 = eq(_T_1169, UInt<1>(0h0)) \n when _T_1172 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_1169, UInt<1>(0h1), \"\") : assert_92 \n node _T_1173 = eq(io.in.d.bits.param, param_1) \n node _T_1174 = asUInt(reset) \n node _T_1175 = eq(_T_1174, UInt<1>(0h0)) \n when _T_1175 : \n node _T_1176 = eq(_T_1173, UInt<1>(0h0)) \n when _T_1176 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_1173, UInt<1>(0h1), \"\") : assert_93 \n node _T_1177 = eq(io.in.d.bits.size, size_1) \n node _T_1178 = asUInt(reset) \n node _T_1179 = eq(_T_1178, UInt<1>(0h0)) \n when _T_1179 : \n node _T_1180 = eq(_T_1177, UInt<1>(0h0)) \n when _T_1180 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_1177, UInt<1>(0h1), \"\") : assert_94 \n node _T_1181 = eq(io.in.d.bits.source, source_1) \n node _T_1182 = asUInt(reset) \n node _T_1183 = eq(_T_1182, UInt<1>(0h0)) \n when _T_1183 : \n node _T_1184 = eq(_T_1181, UInt<1>(0h0)) \n when _T_1184 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_1181, UInt<1>(0h1), \"\") : assert_95 \n node _T_1185 = eq(io.in.d.bits.sink, sink) \n node _T_1186 = asUInt(reset) \n node _T_1187 = eq(_T_1186, UInt<1>(0h0)) \n when _T_1187 : \n node _T_1188 = eq(_T_1185, UInt<1>(0h0)) \n when _T_1188 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_1185, UInt<1>(0h1), \"\") : assert_96 \n node _T_1189 = eq(io.in.d.bits.denied, denied) \n node _T_1190 = asUInt(reset) \n node _T_1191 = eq(_T_1190, UInt<1>(0h0)) \n when _T_1191 : \n node _T_1192 = eq(_T_1189, UInt<1>(0h0)) \n when _T_1192 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_1189, UInt<1>(0h1), \"\") : assert_97 \n node _T_1193 = and(io.in.d.ready, io.in.d.valid) \n node _T_1194 = and(_T_1193, d_first) \n when _T_1194 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) \n regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) \n regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<129> \n connect a_set, UInt<129>(0h0) \n wire a_set_wo_ready : UInt<129> \n connect a_set_wo_ready, UInt<129>(0h0) \n wire a_opcodes_set : UInt<516> \n connect a_opcodes_set, UInt<516>(0h0) \n wire a_sizes_set : UInt<516> \n connect a_sizes_set, UInt<516>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<4> \n connect a_sizes_set_interm, UInt<4>(0h0) \n node _T_1195 = and(io.in.a.valid, a_first_1) \n node _T_1196 = and(_T_1195, UInt<1>(0h1)) \n when _T_1196 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_1197 = and(io.in.a.ready, io.in.a.valid) \n node _T_1198 = and(_T_1197, a_first_1) \n node _T_1199 = and(_T_1198, UInt<1>(0h1)) \n when _T_1199 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_1200 = dshr(inflight, io.in.a.bits.source) \n node _T_1201 = bits(_T_1200, 0, 0) \n node _T_1202 = eq(_T_1201, UInt<1>(0h0)) \n node _T_1203 = asUInt(reset) \n node _T_1204 = eq(_T_1203, UInt<1>(0h0)) \n when _T_1204 : \n node _T_1205 = eq(_T_1202, UInt<1>(0h0)) \n when _T_1205 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_1202, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<129> \n connect d_clr, UInt<129>(0h0) \n wire d_clr_wo_ready : UInt<129> \n connect d_clr_wo_ready, UInt<129>(0h0) \n wire d_opcodes_clr : UInt<516> \n connect d_opcodes_clr, UInt<516>(0h0) \n wire d_sizes_clr : UInt<516> \n connect d_sizes_clr, UInt<516>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1206 = and(io.in.d.valid, d_first_1) \n node _T_1207 = and(_T_1206, UInt<1>(0h1)) \n node _T_1208 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1209 = and(_T_1207, _T_1208) \n when _T_1209 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_1210 = and(io.in.d.ready, io.in.d.valid) \n node _T_1211 = and(_T_1210, d_first_1) \n node _T_1212 = and(_T_1211, UInt<1>(0h1)) \n node _T_1213 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1214 = and(_T_1212, _T_1213) \n when _T_1214 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_1215 = and(io.in.d.valid, d_first_1) \n node _T_1216 = and(_T_1215, UInt<1>(0h1)) \n node _T_1217 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1218 = and(_T_1216, _T_1217) \n when _T_1218 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_1219 = dshr(inflight, io.in.d.bits.source) \n node _T_1220 = bits(_T_1219, 0, 0) \n node _T_1221 = or(_T_1220, same_cycle_resp) \n node _T_1222 = asUInt(reset) \n node _T_1223 = eq(_T_1222, UInt<1>(0h0)) \n when _T_1223 : \n node _T_1224 = eq(_T_1221, UInt<1>(0h0)) \n when _T_1224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_1221, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_1227 = or(_T_1225, _T_1226) \n node _T_1228 = asUInt(reset) \n node _T_1229 = eq(_T_1228, UInt<1>(0h0)) \n when _T_1229 : \n node _T_1230 = eq(_T_1227, UInt<1>(0h0)) \n when _T_1230 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_1227, UInt<1>(0h1), \"\") : assert_100 \n node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_1232 = asUInt(reset) \n node _T_1233 = eq(_T_1232, UInt<1>(0h0)) \n when _T_1233 : \n node _T_1234 = eq(_T_1231, UInt<1>(0h0)) \n when _T_1234 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_1231, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_1237 = or(_T_1235, _T_1236) \n node _T_1238 = asUInt(reset) \n node _T_1239 = eq(_T_1238, UInt<1>(0h0)) \n when _T_1239 : \n node _T_1240 = eq(_T_1237, UInt<1>(0h0)) \n when _T_1240 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_1237, UInt<1>(0h1), \"\") : assert_102 \n node _T_1241 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_1242 = asUInt(reset) \n node _T_1243 = eq(_T_1242, UInt<1>(0h0)) \n when _T_1243 : \n node _T_1244 = eq(_T_1241, UInt<1>(0h0)) \n when _T_1244 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_1241, UInt<1>(0h1), \"\") : assert_103 \n node _T_1245 = and(io.in.d.valid, d_first_1) \n node _T_1246 = and(_T_1245, a_first_1) \n node _T_1247 = and(_T_1246, io.in.a.valid) \n node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_1249 = and(_T_1247, _T_1248) \n node _T_1250 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1251 = and(_T_1249, _T_1250) \n when _T_1251 : \n node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_1253 = or(_T_1252, io.in.a.ready) \n node _T_1254 = asUInt(reset) \n node _T_1255 = eq(_T_1254, UInt<1>(0h0)) \n when _T_1255 : \n node _T_1256 = eq(_T_1253, UInt<1>(0h0)) \n when _T_1256 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_1253, UInt<1>(0h1), \"\") : assert_104 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_138 \n node _T_1257 = orr(inflight) \n node _T_1258 = eq(_T_1257, UInt<1>(0h0)) \n node _T_1259 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_1260 = or(_T_1258, _T_1259) \n node _T_1261 = lt(watchdog, plusarg_reader.out) \n node _T_1262 = or(_T_1260, _T_1261) \n node _T_1263 = asUInt(reset) \n node _T_1264 = eq(_T_1263, UInt<1>(0h0)) \n when _T_1264 : \n node _T_1265 = eq(_T_1262, UInt<1>(0h0)) \n when _T_1265 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_1262, UInt<1>(0h1), \"\") : assert_105 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_1266 = and(io.in.a.ready, io.in.a.valid) \n node _T_1267 = and(io.in.d.ready, io.in.d.valid) \n node _T_1268 = or(_T_1266, _T_1267) \n when _T_1268 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) \n regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) \n regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<21>(0h0) \n connect _c_first_WIRE.bits.source, UInt<8>(0h0) \n connect _c_first_WIRE.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<129> \n connect c_set, UInt<129>(0h0) \n wire c_set_wo_ready : UInt<129> \n connect c_set_wo_ready, UInt<129>(0h0) \n wire c_opcodes_set : UInt<516> \n connect c_opcodes_set, UInt<516>(0h0) \n wire c_sizes_set : UInt<516> \n connect c_sizes_set, UInt<516>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<4> \n connect c_sizes_set_interm, UInt<4>(0h0) \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<21>(0h0) \n connect _WIRE_10.bits.source, UInt<8>(0h0) \n connect _WIRE_10.bits.size, UInt<3>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_1269 = and(_WIRE_11.valid, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<21>(0h0) \n connect _WIRE_12.bits.source, UInt<8>(0h0) \n connect _WIRE_12.bits.size, UInt<3>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_1270 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_1271 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_1272 = and(_T_1270, _T_1271) \n node _T_1273 = and(_T_1269, _T_1272) \n when _T_1273 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<21>(0h0) \n connect _WIRE_14.bits.source, UInt<8>(0h0) \n connect _WIRE_14.bits.size, UInt<3>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_1274 = and(_WIRE_15.ready, _WIRE_15.valid) \n node _T_1275 = and(_T_1274, c_first) \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<21>(0h0) \n connect _WIRE_16.bits.source, UInt<8>(0h0) \n connect _WIRE_16.bits.size, UInt<3>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_1276 = bits(_WIRE_17.bits.opcode, 2, 2) \n node _T_1277 = bits(_WIRE_17.bits.opcode, 1, 1) \n node _T_1278 = and(_T_1276, _T_1277) \n node _T_1279 = and(_T_1275, _T_1278) \n when _T_1279 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<21>(0h0) \n connect _c_set_WIRE.bits.source, UInt<8>(0h0) \n connect _c_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<21>(0h0) \n connect _WIRE_18.bits.source, UInt<8>(0h0) \n connect _WIRE_18.bits.size, UInt<3>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_1280 = dshr(inflight_1, _WIRE_19.bits.source) \n node _T_1281 = bits(_T_1280, 0, 0) \n node _T_1282 = eq(_T_1281, UInt<1>(0h0)) \n node _T_1283 = asUInt(reset) \n node _T_1284 = eq(_T_1283, UInt<1>(0h0)) \n when _T_1284 : \n node _T_1285 = eq(_T_1282, UInt<1>(0h0)) \n when _T_1285 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_1282, UInt<1>(0h1), \"\") : assert_106 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<129> \n connect d_clr_1, UInt<129>(0h0) \n wire d_clr_wo_ready_1 : UInt<129> \n connect d_clr_wo_ready_1, UInt<129>(0h0) \n wire d_opcodes_clr_1 : UInt<516> \n connect d_opcodes_clr_1, UInt<516>(0h0) \n wire d_sizes_clr_1 : UInt<516> \n connect d_sizes_clr_1, UInt<516>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1286 = and(io.in.d.valid, d_first_2) \n node _T_1287 = and(_T_1286, UInt<1>(0h1)) \n node _T_1288 = and(_T_1287, d_release_ack_1) \n when _T_1288 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_1289 = and(io.in.d.ready, io.in.d.valid) \n node _T_1290 = and(_T_1289, d_first_2) \n node _T_1291 = and(_T_1290, UInt<1>(0h1)) \n node _T_1292 = and(_T_1291, d_release_ack_1) \n when _T_1292 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_1293 = and(io.in.d.valid, d_first_2) \n node _T_1294 = and(_T_1293, UInt<1>(0h1)) \n node _T_1295 = and(_T_1294, d_release_ack_1) \n when _T_1295 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_1296 = dshr(inflight_1, io.in.d.bits.source) \n node _T_1297 = bits(_T_1296, 0, 0) \n node _T_1298 = or(_T_1297, same_cycle_resp_1) \n node _T_1299 = asUInt(reset) \n node _T_1300 = eq(_T_1299, UInt<1>(0h0)) \n when _T_1300 : \n node _T_1301 = eq(_T_1298, UInt<1>(0h0)) \n when _T_1301 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_1298, UInt<1>(0h1), \"\") : assert_107 \n when same_cycle_resp_1 : \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<21>(0h0) \n connect _WIRE_20.bits.source, UInt<8>(0h0) \n connect _WIRE_20.bits.size, UInt<3>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_1302 = eq(io.in.d.bits.size, _WIRE_21.bits.size) \n node _T_1303 = asUInt(reset) \n node _T_1304 = eq(_T_1303, UInt<1>(0h0)) \n when _T_1304 : \n node _T_1305 = eq(_T_1302, UInt<1>(0h0)) \n when _T_1305 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_1302, UInt<1>(0h1), \"\") : assert_108 \n else :\n\n node _T_1306 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_1307 = asUInt(reset) \n node _T_1308 = eq(_T_1307, UInt<1>(0h0)) \n when _T_1308 : \n node _T_1309 = eq(_T_1306, UInt<1>(0h0)) \n when _T_1309 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_1306, UInt<1>(0h1), \"\") : assert_109 \n node _T_1310 = and(io.in.d.valid, d_first_2) \n node _T_1311 = and(_T_1310, c_first) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<21>(0h0) \n connect _WIRE_22.bits.source, UInt<8>(0h0) \n connect _WIRE_22.bits.size, UInt<3>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_1312 = and(_T_1311, _WIRE_23.valid) \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<21>(0h0) \n connect _WIRE_24.bits.source, UInt<8>(0h0) \n connect _WIRE_24.bits.size, UInt<3>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_1313 = eq(_WIRE_25.bits.source, io.in.d.bits.source) \n node _T_1314 = and(_T_1312, _T_1313) \n node _T_1315 = and(_T_1314, d_release_ack_1) \n node _T_1316 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_1317 = and(_T_1315, _T_1316) \n when _T_1317 : \n node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_26.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_26.bits.data, UInt<64>(0h0) \n connect _WIRE_26.bits.address, UInt<21>(0h0) \n connect _WIRE_26.bits.source, UInt<8>(0h0) \n connect _WIRE_26.bits.size, UInt<3>(0h0) \n connect _WIRE_26.bits.param, UInt<3>(0h0) \n connect _WIRE_26.bits.opcode, UInt<3>(0h0) \n connect _WIRE_26.valid, UInt<1>(0h0) \n connect _WIRE_26.ready, UInt<1>(0h0) \n wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_27.bits, _WIRE_26.bits \n connect _WIRE_27.valid, _WIRE_26.valid \n connect _WIRE_27.ready, _WIRE_26.ready \n node _T_1319 = or(_T_1318, _WIRE_27.ready) \n node _T_1320 = asUInt(reset) \n node _T_1321 = eq(_T_1320, UInt<1>(0h0)) \n when _T_1321 : \n node _T_1322 = eq(_T_1319, UInt<1>(0h0)) \n when _T_1322 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_1319, UInt<1>(0h1), \"\") : assert_110 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_139 \n node _T_1323 = orr(inflight_1) \n node _T_1324 = eq(_T_1323, UInt<1>(0h0)) \n node _T_1325 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_1326 = or(_T_1324, _T_1325) \n node _T_1327 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_1328 = or(_T_1326, _T_1327) \n node _T_1329 = asUInt(reset) \n node _T_1330 = eq(_T_1329, UInt<1>(0h0)) \n when _T_1330 : \n node _T_1331 = eq(_T_1328, UInt<1>(0h0)) \n when _T_1331 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_1328, UInt<1>(0h1), \"\") : assert_111 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_28.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_28.bits.data, UInt<64>(0h0) \n connect _WIRE_28.bits.address, UInt<21>(0h0) \n connect _WIRE_28.bits.source, UInt<8>(0h0) \n connect _WIRE_28.bits.size, UInt<3>(0h0) \n connect _WIRE_28.bits.param, UInt<3>(0h0) \n connect _WIRE_28.bits.opcode, UInt<3>(0h0) \n connect _WIRE_28.valid, UInt<1>(0h0) \n connect _WIRE_28.ready, UInt<1>(0h0) \n wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_29.bits, _WIRE_28.bits \n connect _WIRE_29.valid, _WIRE_28.valid \n connect _WIRE_29.ready, _WIRE_28.ready \n node _T_1332 = and(_WIRE_29.ready, _WIRE_29.valid) \n node _T_1333 = and(io.in.d.ready, io.in.d.valid) \n node _T_1334 = or(_T_1332, _T_1333) \n when _T_1334 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_67(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [20:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_d_bits_source\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data = 64'h0;\t// @[Monitor.scala:36:7]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_5 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_11 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_15 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_17 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_21 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_23 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_29 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_31 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_35 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_37 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_53 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_55 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_59 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_61 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_65 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_67 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_71 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_73 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_79 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_81 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_85 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_87 = 1'h1;\t// @[Parameters.scala:57:20]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_d_bits_param = 2'h0;\t// @[Monitor.scala:36:7]\n wire [20:0] _c_first_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_first_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_first_WIRE_2_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_first_WIRE_3_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_set_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_set_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [2050:0] _c_opcodes_set_T_1 = 2051'h0;\t// @[Monitor.scala:767:54]\n wire [2050:0] _c_sizes_set_T_1 = 2051'h0;\t// @[Monitor.scala:768:52]\n wire [10:0] _c_opcodes_set_T = 11'h0;\t// @[Monitor.scala:767:79]\n wire [10:0] _c_sizes_set_T = 11'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [255:0] _c_set_wo_ready_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [255:0] _c_set_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [515:0] c_opcodes_set = 516'h0;\t// @[Monitor.scala:740:34]\n wire [515:0] c_sizes_set = 516'h0;\t// @[Monitor.scala:741:34]\n wire [128:0] c_set = 129'h0;\t// @[Monitor.scala:738:34]\n wire [128:0] c_set_wo_ready = 129'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = io_in_a_bits_source_0 == 8'h50;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_0 = _source_ok_T;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_2 = _source_ok_T_1 == 6'h10;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_4 = _source_ok_T_2;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_6 = _source_ok_T_4;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1 = _source_ok_T_6;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_8 = _source_ok_T_7 == 6'h11;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_10 = _source_ok_T_8;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_12 = _source_ok_T_10;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_2 = _source_ok_T_12;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_14 = _source_ok_T_13 == 6'h12;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_16 = _source_ok_T_14;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_18 = _source_ok_T_16;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_3 = _source_ok_T_18;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_20 = _source_ok_T_19 == 6'h13;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_22 = _source_ok_T_20;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_24 = _source_ok_T_22;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_4 = _source_ok_T_24;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_5 = _source_ok_T_25;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_6 = _source_ok_T_26;\t// @[Parameters.scala:1138:31]\n wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4];\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_28 = _source_ok_T_27 == 4'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_30 = _source_ok_T_28;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_32 = _source_ok_T_30;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_7 = _source_ok_T_32;\t// @[Parameters.scala:1138:31]\n wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_34 = _source_ok_T_33 == 4'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_36 = _source_ok_T_34;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_38 = _source_ok_T_36;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_8 = _source_ok_T_38;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_9 = _source_ok_T_39;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_10 = _source_ok_T_40;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 21'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [1:0] uncommonBits = _uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_0 = _source_ok_T_50;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_52 = _source_ok_T_51 == 6'h10;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_54 = _source_ok_T_52;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_56 = _source_ok_T_54;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_1 = _source_ok_T_56;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_58 = _source_ok_T_57 == 6'h11;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_60 = _source_ok_T_58;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_62 = _source_ok_T_60;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_2 = _source_ok_T_62;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_64 = _source_ok_T_63 == 6'h12;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_66 = _source_ok_T_64;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_68 = _source_ok_T_66;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_3 = _source_ok_T_68;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_70 = _source_ok_T_69 == 6'h13;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_72 = _source_ok_T_70;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_74 = _source_ok_T_72;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_4 = _source_ok_T_74;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_5 = _source_ok_T_75;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_6 = _source_ok_T_76;\t// @[Parameters.scala:1138:31]\n wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4];\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_78 = _source_ok_T_77 == 4'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_80 = _source_ok_T_78;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_82 = _source_ok_T_80;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_7 = _source_ok_T_82;\t// @[Parameters.scala:1138:31]\n wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_84 = _source_ok_T_83 == 4'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_86 = _source_ok_T_84;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_88 = _source_ok_T_86;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_8 = _source_ok_T_88;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_9 = _source_ok_T_89;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_10 = _source_ok_T_90;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1266;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1266;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [7:0] source;\t// @[Monitor.scala:390:22]\n reg [20:0] address;\t// @[Monitor.scala:391:22]\n wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_1334;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_1334;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_1334;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [7:0] source_1;\t// @[Monitor.scala:541:22]\n reg [128:0] inflight;\t// @[Monitor.scala:614:27]\n reg [515:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [515:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [128:0] a_set;\t// @[Monitor.scala:626:34]\n wire [128:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [515:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [515:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [10:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [10:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [10:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [10:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [10:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [10:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [10:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [10:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire _T_1199 = _T_1266 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [10:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [10:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [128:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [128:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [515:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [515:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1245 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [128:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [128:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [128:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [128:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [515:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [515:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [128:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [128:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [515:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [515:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1310 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1292 ? _d_clr_T_1[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[515:0] : 516'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[515:0] : 516'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [128:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32170,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) \n node _source_ok_T = shr(io.in.a.bits.source, 11) \n node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) \n node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) \n node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) \n node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T_5 \n node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 10, 0) \n node _T_4 = shr(io.in.a.bits.source, 11) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = leq(UInt<1>(0h0), uncommonBits) \n node _T_7 = and(_T_5, _T_6) \n node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) \n node _T_9 = and(_T_7, _T_8) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_12 = cvt(_T_11) \n node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) \n node _T_14 = asSInt(_T_13) \n node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) \n node _T_16 = or(_T_10, _T_15) \n node _T_17 = asUInt(reset) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n when _T_18 : \n node _T_19 = eq(_T_16, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_16, UInt<1>(0h1), \"\") : assert_1 \n node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_20 : \n node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_23 = and(_T_21, _T_22) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) \n node _T_24 = shr(io.in.a.bits.source, 11) \n node _T_25 = eq(_T_24, UInt<1>(0h0)) \n node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_27 = and(_T_25, _T_26) \n node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) \n node _T_29 = and(_T_27, _T_28) \n node _T_30 = and(_T_23, _T_29) \n node _T_31 = or(UInt<1>(0h0), _T_30) \n node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_34 = cvt(_T_33) \n node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) \n node _T_36 = asSInt(_T_35) \n node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) \n node _T_38 = and(_T_32, _T_37) \n node _T_39 = or(UInt<1>(0h0), _T_38) \n node _T_40 = and(_T_31, _T_39) \n node _T_41 = asUInt(reset) \n node _T_42 = eq(_T_41, UInt<1>(0h0)) \n when _T_42 : \n node _T_43 = eq(_T_40, UInt<1>(0h0)) \n when _T_43 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_40, UInt<1>(0h1), \"\") : assert_2 \n node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_46 = and(_T_44, _T_45) \n node _T_47 = or(UInt<1>(0h0), _T_46) \n node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_49 = cvt(_T_48) \n node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) \n node _T_51 = asSInt(_T_50) \n node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) \n node _T_53 = and(_T_47, _T_52) \n node _T_54 = or(UInt<1>(0h0), _T_53) \n node _T_55 = and(UInt<1>(0h0), _T_54) \n node _T_56 = asUInt(reset) \n node _T_57 = eq(_T_56, UInt<1>(0h0)) \n when _T_57 : \n node _T_58 = eq(_T_55, UInt<1>(0h0)) \n when _T_58 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_55, UInt<1>(0h1), \"\") : assert_3 \n node _T_59 = asUInt(reset) \n node _T_60 = eq(_T_59, UInt<1>(0h0)) \n when _T_60 : \n node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_61 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_63 = asUInt(reset) \n node _T_64 = eq(_T_63, UInt<1>(0h0)) \n when _T_64 : \n node _T_65 = eq(_T_62, UInt<1>(0h0)) \n when _T_65 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_62, UInt<1>(0h1), \"\") : assert_5 \n node _T_66 = asUInt(reset) \n node _T_67 = eq(_T_66, UInt<1>(0h0)) \n when _T_67 : \n node _T_68 = eq(is_aligned, UInt<1>(0h0)) \n when _T_68 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_70 = asUInt(reset) \n node _T_71 = eq(_T_70, UInt<1>(0h0)) \n when _T_71 : \n node _T_72 = eq(_T_69, UInt<1>(0h0)) \n when _T_72 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_69, UInt<1>(0h1), \"\") : assert_7 \n node _T_73 = not(io.in.a.bits.mask) \n node _T_74 = eq(_T_73, UInt<1>(0h0)) \n node _T_75 = asUInt(reset) \n node _T_76 = eq(_T_75, UInt<1>(0h0)) \n when _T_76 : \n node _T_77 = eq(_T_74, UInt<1>(0h0)) \n when _T_77 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_74, UInt<1>(0h1), \"\") : assert_8 \n node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_79 = asUInt(reset) \n node _T_80 = eq(_T_79, UInt<1>(0h0)) \n when _T_80 : \n node _T_81 = eq(_T_78, UInt<1>(0h0)) \n when _T_81 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_78, UInt<1>(0h1), \"\") : assert_9 \n node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_82 : \n node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_85 = and(_T_83, _T_84) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) \n node _T_86 = shr(io.in.a.bits.source, 11) \n node _T_87 = eq(_T_86, UInt<1>(0h0)) \n node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_89 = and(_T_87, _T_88) \n node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) \n node _T_91 = and(_T_89, _T_90) \n node _T_92 = and(_T_85, _T_91) \n node _T_93 = or(UInt<1>(0h0), _T_92) \n node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_96 = cvt(_T_95) \n node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) \n node _T_98 = asSInt(_T_97) \n node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) \n node _T_100 = and(_T_94, _T_99) \n node _T_101 = or(UInt<1>(0h0), _T_100) \n node _T_102 = and(_T_93, _T_101) \n node _T_103 = asUInt(reset) \n node _T_104 = eq(_T_103, UInt<1>(0h0)) \n when _T_104 : \n node _T_105 = eq(_T_102, UInt<1>(0h0)) \n when _T_105 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_102, UInt<1>(0h1), \"\") : assert_10 \n node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_108 = and(_T_106, _T_107) \n node _T_109 = or(UInt<1>(0h0), _T_108) \n node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_111 = cvt(_T_110) \n node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) \n node _T_113 = asSInt(_T_112) \n node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) \n node _T_115 = and(_T_109, _T_114) \n node _T_116 = or(UInt<1>(0h0), _T_115) \n node _T_117 = and(UInt<1>(0h0), _T_116) \n node _T_118 = asUInt(reset) \n node _T_119 = eq(_T_118, UInt<1>(0h0)) \n when _T_119 : \n node _T_120 = eq(_T_117, UInt<1>(0h0)) \n when _T_120 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_117, UInt<1>(0h1), \"\") : assert_11 \n node _T_121 = asUInt(reset) \n node _T_122 = eq(_T_121, UInt<1>(0h0)) \n when _T_122 : \n node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_123 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_125 = asUInt(reset) \n node _T_126 = eq(_T_125, UInt<1>(0h0)) \n when _T_126 : \n node _T_127 = eq(_T_124, UInt<1>(0h0)) \n when _T_127 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_124, UInt<1>(0h1), \"\") : assert_13 \n node _T_128 = asUInt(reset) \n node _T_129 = eq(_T_128, UInt<1>(0h0)) \n when _T_129 : \n node _T_130 = eq(is_aligned, UInt<1>(0h0)) \n when _T_130 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_132 = asUInt(reset) \n node _T_133 = eq(_T_132, UInt<1>(0h0)) \n when _T_133 : \n node _T_134 = eq(_T_131, UInt<1>(0h0)) \n when _T_134 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_131, UInt<1>(0h1), \"\") : assert_15 \n node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_136 = asUInt(reset) \n node _T_137 = eq(_T_136, UInt<1>(0h0)) \n when _T_137 : \n node _T_138 = eq(_T_135, UInt<1>(0h0)) \n when _T_138 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_135, UInt<1>(0h1), \"\") : assert_16 \n node _T_139 = not(io.in.a.bits.mask) \n node _T_140 = eq(_T_139, UInt<1>(0h0)) \n node _T_141 = asUInt(reset) \n node _T_142 = eq(_T_141, UInt<1>(0h0)) \n when _T_142 : \n node _T_143 = eq(_T_140, UInt<1>(0h0)) \n when _T_143 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_140, UInt<1>(0h1), \"\") : assert_17 \n node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_145 = asUInt(reset) \n node _T_146 = eq(_T_145, UInt<1>(0h0)) \n when _T_146 : \n node _T_147 = eq(_T_144, UInt<1>(0h0)) \n when _T_147 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_144, UInt<1>(0h1), \"\") : assert_18 \n node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_148 : \n node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_151 = and(_T_149, _T_150) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) \n node _T_152 = shr(io.in.a.bits.source, 11) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_155 = and(_T_153, _T_154) \n node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) \n node _T_157 = and(_T_155, _T_156) \n node _T_158 = and(_T_151, _T_157) \n node _T_159 = or(UInt<1>(0h0), _T_158) \n node _T_160 = asUInt(reset) \n node _T_161 = eq(_T_160, UInt<1>(0h0)) \n when _T_161 : \n node _T_162 = eq(_T_159, UInt<1>(0h0)) \n when _T_162 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_159, UInt<1>(0h1), \"\") : assert_19 \n node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_165 = and(_T_163, _T_164) \n node _T_166 = or(UInt<1>(0h0), _T_165) \n node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_168 = cvt(_T_167) \n node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) \n node _T_170 = asSInt(_T_169) \n node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) \n node _T_172 = and(_T_166, _T_171) \n node _T_173 = or(UInt<1>(0h0), _T_172) \n node _T_174 = asUInt(reset) \n node _T_175 = eq(_T_174, UInt<1>(0h0)) \n when _T_175 : \n node _T_176 = eq(_T_173, UInt<1>(0h0)) \n when _T_176 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_173, UInt<1>(0h1), \"\") : assert_20 \n node _T_177 = asUInt(reset) \n node _T_178 = eq(_T_177, UInt<1>(0h0)) \n when _T_178 : \n node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_179 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_180 = asUInt(reset) \n node _T_181 = eq(_T_180, UInt<1>(0h0)) \n when _T_181 : \n node _T_182 = eq(is_aligned, UInt<1>(0h0)) \n when _T_182 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_184 = asUInt(reset) \n node _T_185 = eq(_T_184, UInt<1>(0h0)) \n when _T_185 : \n node _T_186 = eq(_T_183, UInt<1>(0h0)) \n when _T_186 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_183, UInt<1>(0h1), \"\") : assert_23 \n node _T_187 = eq(io.in.a.bits.mask, mask) \n node _T_188 = asUInt(reset) \n node _T_189 = eq(_T_188, UInt<1>(0h0)) \n when _T_189 : \n node _T_190 = eq(_T_187, UInt<1>(0h0)) \n when _T_190 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_187, UInt<1>(0h1), \"\") : assert_24 \n node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_192 = asUInt(reset) \n node _T_193 = eq(_T_192, UInt<1>(0h0)) \n when _T_193 : \n node _T_194 = eq(_T_191, UInt<1>(0h0)) \n when _T_194 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_191, UInt<1>(0h1), \"\") : assert_25 \n node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_195 : \n node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_198 = and(_T_196, _T_197) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) \n node _T_199 = shr(io.in.a.bits.source, 11) \n node _T_200 = eq(_T_199, UInt<1>(0h0)) \n node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_202 = and(_T_200, _T_201) \n node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) \n node _T_204 = and(_T_202, _T_203) \n node _T_205 = and(_T_198, _T_204) \n node _T_206 = or(UInt<1>(0h0), _T_205) \n node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_209 = and(_T_207, _T_208) \n node _T_210 = or(UInt<1>(0h0), _T_209) \n node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_212 = cvt(_T_211) \n node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) \n node _T_214 = asSInt(_T_213) \n node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) \n node _T_216 = and(_T_210, _T_215) \n node _T_217 = or(UInt<1>(0h0), _T_216) \n node _T_218 = and(_T_206, _T_217) \n node _T_219 = asUInt(reset) \n node _T_220 = eq(_T_219, UInt<1>(0h0)) \n when _T_220 : \n node _T_221 = eq(_T_218, UInt<1>(0h0)) \n when _T_221 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_218, UInt<1>(0h1), \"\") : assert_26 \n node _T_222 = asUInt(reset) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n when _T_223 : \n node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_225 = asUInt(reset) \n node _T_226 = eq(_T_225, UInt<1>(0h0)) \n when _T_226 : \n node _T_227 = eq(is_aligned, UInt<1>(0h0)) \n when _T_227 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_229 = asUInt(reset) \n node _T_230 = eq(_T_229, UInt<1>(0h0)) \n when _T_230 : \n node _T_231 = eq(_T_228, UInt<1>(0h0)) \n when _T_231 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_228, UInt<1>(0h1), \"\") : assert_29 \n node _T_232 = eq(io.in.a.bits.mask, mask) \n node _T_233 = asUInt(reset) \n node _T_234 = eq(_T_233, UInt<1>(0h0)) \n when _T_234 : \n node _T_235 = eq(_T_232, UInt<1>(0h0)) \n when _T_235 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_232, UInt<1>(0h1), \"\") : assert_30 \n node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_236 : \n node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_239 = and(_T_237, _T_238) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) \n node _T_240 = shr(io.in.a.bits.source, 11) \n node _T_241 = eq(_T_240, UInt<1>(0h0)) \n node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_243 = and(_T_241, _T_242) \n node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) \n node _T_245 = and(_T_243, _T_244) \n node _T_246 = and(_T_239, _T_245) \n node _T_247 = or(UInt<1>(0h0), _T_246) \n node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_250 = and(_T_248, _T_249) \n node _T_251 = or(UInt<1>(0h0), _T_250) \n node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_253 = cvt(_T_252) \n node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) \n node _T_255 = asSInt(_T_254) \n node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) \n node _T_257 = and(_T_251, _T_256) \n node _T_258 = or(UInt<1>(0h0), _T_257) \n node _T_259 = and(_T_247, _T_258) \n node _T_260 = asUInt(reset) \n node _T_261 = eq(_T_260, UInt<1>(0h0)) \n when _T_261 : \n node _T_262 = eq(_T_259, UInt<1>(0h0)) \n when _T_262 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_259, UInt<1>(0h1), \"\") : assert_31 \n node _T_263 = asUInt(reset) \n node _T_264 = eq(_T_263, UInt<1>(0h0)) \n when _T_264 : \n node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_265 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_266 = asUInt(reset) \n node _T_267 = eq(_T_266, UInt<1>(0h0)) \n when _T_267 : \n node _T_268 = eq(is_aligned, UInt<1>(0h0)) \n when _T_268 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_270 = asUInt(reset) \n node _T_271 = eq(_T_270, UInt<1>(0h0)) \n when _T_271 : \n node _T_272 = eq(_T_269, UInt<1>(0h0)) \n when _T_272 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_269, UInt<1>(0h1), \"\") : assert_34 \n node _T_273 = not(mask) \n node _T_274 = and(io.in.a.bits.mask, _T_273) \n node _T_275 = eq(_T_274, UInt<1>(0h0)) \n node _T_276 = asUInt(reset) \n node _T_277 = eq(_T_276, UInt<1>(0h0)) \n when _T_277 : \n node _T_278 = eq(_T_275, UInt<1>(0h0)) \n when _T_278 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_275, UInt<1>(0h1), \"\") : assert_35 \n node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_279 : \n node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_282 = and(_T_280, _T_281) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) \n node _T_283 = shr(io.in.a.bits.source, 11) \n node _T_284 = eq(_T_283, UInt<1>(0h0)) \n node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_286 = and(_T_284, _T_285) \n node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) \n node _T_288 = and(_T_286, _T_287) \n node _T_289 = and(_T_282, _T_288) \n node _T_290 = or(UInt<1>(0h0), _T_289) \n node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_293 = cvt(_T_292) \n node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) \n node _T_295 = asSInt(_T_294) \n node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) \n node _T_297 = and(_T_291, _T_296) \n node _T_298 = or(UInt<1>(0h0), _T_297) \n node _T_299 = and(_T_290, _T_298) \n node _T_300 = asUInt(reset) \n node _T_301 = eq(_T_300, UInt<1>(0h0)) \n when _T_301 : \n node _T_302 = eq(_T_299, UInt<1>(0h0)) \n when _T_302 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_299, UInt<1>(0h1), \"\") : assert_36 \n node _T_303 = asUInt(reset) \n node _T_304 = eq(_T_303, UInt<1>(0h0)) \n when _T_304 : \n node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_305 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_306 = asUInt(reset) \n node _T_307 = eq(_T_306, UInt<1>(0h0)) \n when _T_307 : \n node _T_308 = eq(is_aligned, UInt<1>(0h0)) \n when _T_308 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_310 = asUInt(reset) \n node _T_311 = eq(_T_310, UInt<1>(0h0)) \n when _T_311 : \n node _T_312 = eq(_T_309, UInt<1>(0h0)) \n when _T_312 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_309, UInt<1>(0h1), \"\") : assert_39 \n node _T_313 = eq(io.in.a.bits.mask, mask) \n node _T_314 = asUInt(reset) \n node _T_315 = eq(_T_314, UInt<1>(0h0)) \n when _T_315 : \n node _T_316 = eq(_T_313, UInt<1>(0h0)) \n when _T_316 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_313, UInt<1>(0h1), \"\") : assert_40 \n node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_317 : \n node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_320 = and(_T_318, _T_319) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) \n node _T_321 = shr(io.in.a.bits.source, 11) \n node _T_322 = eq(_T_321, UInt<1>(0h0)) \n node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_324 = and(_T_322, _T_323) \n node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) \n node _T_326 = and(_T_324, _T_325) \n node _T_327 = and(_T_320, _T_326) \n node _T_328 = or(UInt<1>(0h0), _T_327) \n node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_331 = cvt(_T_330) \n node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) \n node _T_333 = asSInt(_T_332) \n node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) \n node _T_335 = and(_T_329, _T_334) \n node _T_336 = or(UInt<1>(0h0), _T_335) \n node _T_337 = and(_T_328, _T_336) \n node _T_338 = asUInt(reset) \n node _T_339 = eq(_T_338, UInt<1>(0h0)) \n when _T_339 : \n node _T_340 = eq(_T_337, UInt<1>(0h0)) \n when _T_340 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_337, UInt<1>(0h1), \"\") : assert_41 \n node _T_341 = asUInt(reset) \n node _T_342 = eq(_T_341, UInt<1>(0h0)) \n when _T_342 : \n node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_343 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_344 = asUInt(reset) \n node _T_345 = eq(_T_344, UInt<1>(0h0)) \n when _T_345 : \n node _T_346 = eq(is_aligned, UInt<1>(0h0)) \n when _T_346 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_348 = asUInt(reset) \n node _T_349 = eq(_T_348, UInt<1>(0h0)) \n when _T_349 : \n node _T_350 = eq(_T_347, UInt<1>(0h0)) \n when _T_350 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_347, UInt<1>(0h1), \"\") : assert_44 \n node _T_351 = eq(io.in.a.bits.mask, mask) \n node _T_352 = asUInt(reset) \n node _T_353 = eq(_T_352, UInt<1>(0h0)) \n when _T_353 : \n node _T_354 = eq(_T_351, UInt<1>(0h0)) \n when _T_354 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_351, UInt<1>(0h1), \"\") : assert_45 \n node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_355 : \n node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_358 = and(_T_356, _T_357) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) \n node _T_359 = shr(io.in.a.bits.source, 11) \n node _T_360 = eq(_T_359, UInt<1>(0h0)) \n node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_362 = and(_T_360, _T_361) \n node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) \n node _T_364 = and(_T_362, _T_363) \n node _T_365 = and(_T_358, _T_364) \n node _T_366 = or(UInt<1>(0h0), _T_365) \n node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_369 = cvt(_T_368) \n node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) \n node _T_371 = asSInt(_T_370) \n node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) \n node _T_373 = and(_T_367, _T_372) \n node _T_374 = or(UInt<1>(0h0), _T_373) \n node _T_375 = and(_T_366, _T_374) \n node _T_376 = asUInt(reset) \n node _T_377 = eq(_T_376, UInt<1>(0h0)) \n when _T_377 : \n node _T_378 = eq(_T_375, UInt<1>(0h0)) \n when _T_378 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_375, UInt<1>(0h1), \"\") : assert_46 \n node _T_379 = asUInt(reset) \n node _T_380 = eq(_T_379, UInt<1>(0h0)) \n when _T_380 : \n node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_381 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_382 = asUInt(reset) \n node _T_383 = eq(_T_382, UInt<1>(0h0)) \n when _T_383 : \n node _T_384 = eq(is_aligned, UInt<1>(0h0)) \n when _T_384 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_386 = asUInt(reset) \n node _T_387 = eq(_T_386, UInt<1>(0h0)) \n when _T_387 : \n node _T_388 = eq(_T_385, UInt<1>(0h0)) \n when _T_388 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_385, UInt<1>(0h1), \"\") : assert_49 \n node _T_389 = eq(io.in.a.bits.mask, mask) \n node _T_390 = asUInt(reset) \n node _T_391 = eq(_T_390, UInt<1>(0h0)) \n when _T_391 : \n node _T_392 = eq(_T_389, UInt<1>(0h0)) \n when _T_392 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_389, UInt<1>(0h1), \"\") : assert_50 \n node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_394 = asUInt(reset) \n node _T_395 = eq(_T_394, UInt<1>(0h0)) \n when _T_395 : \n node _T_396 = eq(_T_393, UInt<1>(0h0)) \n when _T_396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_393, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_398 = asUInt(reset) \n node _T_399 = eq(_T_398, UInt<1>(0h0)) \n when _T_399 : \n node _T_400 = eq(_T_397, UInt<1>(0h0)) \n when _T_400 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_397, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) \n node _source_ok_T_6 = shr(io.in.d.bits.source, 11) \n node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) \n node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) \n node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) \n node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_11 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_401 : \n node _T_402 = asUInt(reset) \n node _T_403 = eq(_T_402, UInt<1>(0h0)) \n when _T_403 : \n node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_404 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_406 = asUInt(reset) \n node _T_407 = eq(_T_406, UInt<1>(0h0)) \n when _T_407 : \n node _T_408 = eq(_T_405, UInt<1>(0h0)) \n when _T_408 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_405, UInt<1>(0h1), \"\") : assert_54 \n node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_410 = asUInt(reset) \n node _T_411 = eq(_T_410, UInt<1>(0h0)) \n when _T_411 : \n node _T_412 = eq(_T_409, UInt<1>(0h0)) \n when _T_412 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_409, UInt<1>(0h1), \"\") : assert_55 \n node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_414 = asUInt(reset) \n node _T_415 = eq(_T_414, UInt<1>(0h0)) \n when _T_415 : \n node _T_416 = eq(_T_413, UInt<1>(0h0)) \n when _T_416 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_413, UInt<1>(0h1), \"\") : assert_56 \n node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_418 = asUInt(reset) \n node _T_419 = eq(_T_418, UInt<1>(0h0)) \n when _T_419 : \n node _T_420 = eq(_T_417, UInt<1>(0h0)) \n when _T_420 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_417, UInt<1>(0h1), \"\") : assert_57 \n node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_421 : \n node _T_422 = asUInt(reset) \n node _T_423 = eq(_T_422, UInt<1>(0h0)) \n when _T_423 : \n node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_424 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_425 = asUInt(reset) \n node _T_426 = eq(_T_425, UInt<1>(0h0)) \n when _T_426 : \n node _T_427 = eq(sink_ok, UInt<1>(0h0)) \n when _T_427 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_429 = asUInt(reset) \n node _T_430 = eq(_T_429, UInt<1>(0h0)) \n when _T_430 : \n node _T_431 = eq(_T_428, UInt<1>(0h0)) \n when _T_431 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_428, UInt<1>(0h1), \"\") : assert_60 \n node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_433 = asUInt(reset) \n node _T_434 = eq(_T_433, UInt<1>(0h0)) \n when _T_434 : \n node _T_435 = eq(_T_432, UInt<1>(0h0)) \n when _T_435 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_432, UInt<1>(0h1), \"\") : assert_61 \n node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_437 = asUInt(reset) \n node _T_438 = eq(_T_437, UInt<1>(0h0)) \n when _T_438 : \n node _T_439 = eq(_T_436, UInt<1>(0h0)) \n when _T_439 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_436, UInt<1>(0h1), \"\") : assert_62 \n node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_441 = asUInt(reset) \n node _T_442 = eq(_T_441, UInt<1>(0h0)) \n when _T_442 : \n node _T_443 = eq(_T_440, UInt<1>(0h0)) \n when _T_443 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_440, UInt<1>(0h1), \"\") : assert_63 \n node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_445 = or(UInt<1>(0h0), _T_444) \n node _T_446 = asUInt(reset) \n node _T_447 = eq(_T_446, UInt<1>(0h0)) \n when _T_447 : \n node _T_448 = eq(_T_445, UInt<1>(0h0)) \n when _T_448 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_445, UInt<1>(0h1), \"\") : assert_64 \n node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_449 : \n node _T_450 = asUInt(reset) \n node _T_451 = eq(_T_450, UInt<1>(0h0)) \n when _T_451 : \n node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_452 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_453 = asUInt(reset) \n node _T_454 = eq(_T_453, UInt<1>(0h0)) \n when _T_454 : \n node _T_455 = eq(sink_ok, UInt<1>(0h0)) \n when _T_455 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_457 = asUInt(reset) \n node _T_458 = eq(_T_457, UInt<1>(0h0)) \n when _T_458 : \n node _T_459 = eq(_T_456, UInt<1>(0h0)) \n when _T_459 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_456, UInt<1>(0h1), \"\") : assert_67 \n node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_461 = asUInt(reset) \n node _T_462 = eq(_T_461, UInt<1>(0h0)) \n when _T_462 : \n node _T_463 = eq(_T_460, UInt<1>(0h0)) \n when _T_463 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_460, UInt<1>(0h1), \"\") : assert_68 \n node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_465 = asUInt(reset) \n node _T_466 = eq(_T_465, UInt<1>(0h0)) \n when _T_466 : \n node _T_467 = eq(_T_464, UInt<1>(0h0)) \n when _T_467 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_464, UInt<1>(0h1), \"\") : assert_69 \n node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_469 = or(_T_468, io.in.d.bits.corrupt) \n node _T_470 = asUInt(reset) \n node _T_471 = eq(_T_470, UInt<1>(0h0)) \n when _T_471 : \n node _T_472 = eq(_T_469, UInt<1>(0h0)) \n when _T_472 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_469, UInt<1>(0h1), \"\") : assert_70 \n node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_474 = or(UInt<1>(0h0), _T_473) \n node _T_475 = asUInt(reset) \n node _T_476 = eq(_T_475, UInt<1>(0h0)) \n when _T_476 : \n node _T_477 = eq(_T_474, UInt<1>(0h0)) \n when _T_477 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_474, UInt<1>(0h1), \"\") : assert_71 \n node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_478 : \n node _T_479 = asUInt(reset) \n node _T_480 = eq(_T_479, UInt<1>(0h0)) \n when _T_480 : \n node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_481 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_483 = asUInt(reset) \n node _T_484 = eq(_T_483, UInt<1>(0h0)) \n when _T_484 : \n node _T_485 = eq(_T_482, UInt<1>(0h0)) \n when _T_485 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_482, UInt<1>(0h1), \"\") : assert_73 \n node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_487 = asUInt(reset) \n node _T_488 = eq(_T_487, UInt<1>(0h0)) \n when _T_488 : \n node _T_489 = eq(_T_486, UInt<1>(0h0)) \n when _T_489 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_486, UInt<1>(0h1), \"\") : assert_74 \n node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_491 = or(UInt<1>(0h0), _T_490) \n node _T_492 = asUInt(reset) \n node _T_493 = eq(_T_492, UInt<1>(0h0)) \n when _T_493 : \n node _T_494 = eq(_T_491, UInt<1>(0h0)) \n when _T_494 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_491, UInt<1>(0h1), \"\") : assert_75 \n node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_495 : \n node _T_496 = asUInt(reset) \n node _T_497 = eq(_T_496, UInt<1>(0h0)) \n when _T_497 : \n node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_498 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_500 = asUInt(reset) \n node _T_501 = eq(_T_500, UInt<1>(0h0)) \n when _T_501 : \n node _T_502 = eq(_T_499, UInt<1>(0h0)) \n when _T_502 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_499, UInt<1>(0h1), \"\") : assert_77 \n node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_504 = or(_T_503, io.in.d.bits.corrupt) \n node _T_505 = asUInt(reset) \n node _T_506 = eq(_T_505, UInt<1>(0h0)) \n when _T_506 : \n node _T_507 = eq(_T_504, UInt<1>(0h0)) \n when _T_507 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_504, UInt<1>(0h1), \"\") : assert_78 \n node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_509 = or(UInt<1>(0h0), _T_508) \n node _T_510 = asUInt(reset) \n node _T_511 = eq(_T_510, UInt<1>(0h0)) \n when _T_511 : \n node _T_512 = eq(_T_509, UInt<1>(0h0)) \n when _T_512 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_509, UInt<1>(0h1), \"\") : assert_79 \n node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_513 : \n node _T_514 = asUInt(reset) \n node _T_515 = eq(_T_514, UInt<1>(0h0)) \n when _T_515 : \n node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_516 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_518 = asUInt(reset) \n node _T_519 = eq(_T_518, UInt<1>(0h0)) \n when _T_519 : \n node _T_520 = eq(_T_517, UInt<1>(0h0)) \n when _T_520 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_517, UInt<1>(0h1), \"\") : assert_81 \n node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_522 = asUInt(reset) \n node _T_523 = eq(_T_522, UInt<1>(0h0)) \n when _T_523 : \n node _T_524 = eq(_T_521, UInt<1>(0h0)) \n when _T_524 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_521, UInt<1>(0h1), \"\") : assert_82 \n node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_526 = or(UInt<1>(0h0), _T_525) \n node _T_527 = asUInt(reset) \n node _T_528 = eq(_T_527, UInt<1>(0h0)) \n when _T_528 : \n node _T_529 = eq(_T_526, UInt<1>(0h0)) \n when _T_529 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_526, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<29>(0h0) \n connect _WIRE.bits.source, UInt<11>(0h0) \n connect _WIRE.bits.size, UInt<2>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_531 = asUInt(reset) \n node _T_532 = eq(_T_531, UInt<1>(0h0)) \n when _T_532 : \n node _T_533 = eq(_T_530, UInt<1>(0h0)) \n when _T_533 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_530, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<29>(0h0) \n connect _WIRE_2.bits.source, UInt<11>(0h0) \n connect _WIRE_2.bits.size, UInt<2>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_535 = asUInt(reset) \n node _T_536 = eq(_T_535, UInt<1>(0h0)) \n when _T_536 : \n node _T_537 = eq(_T_534, UInt<1>(0h0)) \n when _T_537 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_534, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_539 = asUInt(reset) \n node _T_540 = eq(_T_539, UInt<1>(0h0)) \n when _T_540 : \n node _T_541 = eq(_T_538, UInt<1>(0h0)) \n when _T_541 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_538, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_542 = eq(a_first, UInt<1>(0h0)) \n node _T_543 = and(io.in.a.valid, _T_542) \n when _T_543 : \n node _T_544 = eq(io.in.a.bits.opcode, opcode) \n node _T_545 = asUInt(reset) \n node _T_546 = eq(_T_545, UInt<1>(0h0)) \n when _T_546 : \n node _T_547 = eq(_T_544, UInt<1>(0h0)) \n when _T_547 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_544, UInt<1>(0h1), \"\") : assert_87 \n node _T_548 = eq(io.in.a.bits.param, param) \n node _T_549 = asUInt(reset) \n node _T_550 = eq(_T_549, UInt<1>(0h0)) \n when _T_550 : \n node _T_551 = eq(_T_548, UInt<1>(0h0)) \n when _T_551 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_548, UInt<1>(0h1), \"\") : assert_88 \n node _T_552 = eq(io.in.a.bits.size, size) \n node _T_553 = asUInt(reset) \n node _T_554 = eq(_T_553, UInt<1>(0h0)) \n when _T_554 : \n node _T_555 = eq(_T_552, UInt<1>(0h0)) \n when _T_555 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_552, UInt<1>(0h1), \"\") : assert_89 \n node _T_556 = eq(io.in.a.bits.source, source) \n node _T_557 = asUInt(reset) \n node _T_558 = eq(_T_557, UInt<1>(0h0)) \n when _T_558 : \n node _T_559 = eq(_T_556, UInt<1>(0h0)) \n when _T_559 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_556, UInt<1>(0h1), \"\") : assert_90 \n node _T_560 = eq(io.in.a.bits.address, address) \n node _T_561 = asUInt(reset) \n node _T_562 = eq(_T_561, UInt<1>(0h0)) \n when _T_562 : \n node _T_563 = eq(_T_560, UInt<1>(0h0)) \n when _T_563 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_560, UInt<1>(0h1), \"\") : assert_91 \n node _T_564 = and(io.in.a.ready, io.in.a.valid) \n node _T_565 = and(_T_564, a_first) \n when _T_565 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_566 = eq(d_first, UInt<1>(0h0)) \n node _T_567 = and(io.in.d.valid, _T_566) \n when _T_567 : \n node _T_568 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_569 = asUInt(reset) \n node _T_570 = eq(_T_569, UInt<1>(0h0)) \n when _T_570 : \n node _T_571 = eq(_T_568, UInt<1>(0h0)) \n when _T_571 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_568, UInt<1>(0h1), \"\") : assert_92 \n node _T_572 = eq(io.in.d.bits.param, param_1) \n node _T_573 = asUInt(reset) \n node _T_574 = eq(_T_573, UInt<1>(0h0)) \n when _T_574 : \n node _T_575 = eq(_T_572, UInt<1>(0h0)) \n when _T_575 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_572, UInt<1>(0h1), \"\") : assert_93 \n node _T_576 = eq(io.in.d.bits.size, size_1) \n node _T_577 = asUInt(reset) \n node _T_578 = eq(_T_577, UInt<1>(0h0)) \n when _T_578 : \n node _T_579 = eq(_T_576, UInt<1>(0h0)) \n when _T_579 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_576, UInt<1>(0h1), \"\") : assert_94 \n node _T_580 = eq(io.in.d.bits.source, source_1) \n node _T_581 = asUInt(reset) \n node _T_582 = eq(_T_581, UInt<1>(0h0)) \n when _T_582 : \n node _T_583 = eq(_T_580, UInt<1>(0h0)) \n when _T_583 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_580, UInt<1>(0h1), \"\") : assert_95 \n node _T_584 = eq(io.in.d.bits.sink, sink) \n node _T_585 = asUInt(reset) \n node _T_586 = eq(_T_585, UInt<1>(0h0)) \n when _T_586 : \n node _T_587 = eq(_T_584, UInt<1>(0h0)) \n when _T_587 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_584, UInt<1>(0h1), \"\") : assert_96 \n node _T_588 = eq(io.in.d.bits.denied, denied) \n node _T_589 = asUInt(reset) \n node _T_590 = eq(_T_589, UInt<1>(0h0)) \n when _T_590 : \n node _T_591 = eq(_T_588, UInt<1>(0h0)) \n when _T_591 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_588, UInt<1>(0h1), \"\") : assert_97 \n node _T_592 = and(io.in.d.ready, io.in.d.valid) \n node _T_593 = and(_T_592, d_first) \n when _T_593 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) \n regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) \n regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<1040> \n connect a_set, UInt<1040>(0h0) \n wire a_set_wo_ready : UInt<1040> \n connect a_set_wo_ready, UInt<1040>(0h0) \n wire a_opcodes_set : UInt<4160> \n connect a_opcodes_set, UInt<4160>(0h0) \n wire a_sizes_set : UInt<4160> \n connect a_sizes_set, UInt<4160>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<3> \n connect a_sizes_set_interm, UInt<3>(0h0) \n node _T_594 = and(io.in.a.valid, a_first_1) \n node _T_595 = and(_T_594, UInt<1>(0h1)) \n when _T_595 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_596 = and(io.in.a.ready, io.in.a.valid) \n node _T_597 = and(_T_596, a_first_1) \n node _T_598 = and(_T_597, UInt<1>(0h1)) \n when _T_598 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_599 = dshr(inflight, io.in.a.bits.source) \n node _T_600 = bits(_T_599, 0, 0) \n node _T_601 = eq(_T_600, UInt<1>(0h0)) \n node _T_602 = asUInt(reset) \n node _T_603 = eq(_T_602, UInt<1>(0h0)) \n when _T_603 : \n node _T_604 = eq(_T_601, UInt<1>(0h0)) \n when _T_604 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_601, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<1040> \n connect d_clr, UInt<1040>(0h0) \n wire d_clr_wo_ready : UInt<1040> \n connect d_clr_wo_ready, UInt<1040>(0h0) \n wire d_opcodes_clr : UInt<4160> \n connect d_opcodes_clr, UInt<4160>(0h0) \n wire d_sizes_clr : UInt<4160> \n connect d_sizes_clr, UInt<4160>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_605 = and(io.in.d.valid, d_first_1) \n node _T_606 = and(_T_605, UInt<1>(0h1)) \n node _T_607 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_608 = and(_T_606, _T_607) \n when _T_608 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_609 = and(io.in.d.ready, io.in.d.valid) \n node _T_610 = and(_T_609, d_first_1) \n node _T_611 = and(_T_610, UInt<1>(0h1)) \n node _T_612 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_613 = and(_T_611, _T_612) \n when _T_613 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_614 = and(io.in.d.valid, d_first_1) \n node _T_615 = and(_T_614, UInt<1>(0h1)) \n node _T_616 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_617 = and(_T_615, _T_616) \n when _T_617 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_618 = dshr(inflight, io.in.d.bits.source) \n node _T_619 = bits(_T_618, 0, 0) \n node _T_620 = or(_T_619, same_cycle_resp) \n node _T_621 = asUInt(reset) \n node _T_622 = eq(_T_621, UInt<1>(0h0)) \n when _T_622 : \n node _T_623 = eq(_T_620, UInt<1>(0h0)) \n when _T_623 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_620, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_626 = or(_T_624, _T_625) \n node _T_627 = asUInt(reset) \n node _T_628 = eq(_T_627, UInt<1>(0h0)) \n when _T_628 : \n node _T_629 = eq(_T_626, UInt<1>(0h0)) \n when _T_629 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_626, UInt<1>(0h1), \"\") : assert_100 \n node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_631 = asUInt(reset) \n node _T_632 = eq(_T_631, UInt<1>(0h0)) \n when _T_632 : \n node _T_633 = eq(_T_630, UInt<1>(0h0)) \n when _T_633 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_630, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_636 = or(_T_634, _T_635) \n node _T_637 = asUInt(reset) \n node _T_638 = eq(_T_637, UInt<1>(0h0)) \n when _T_638 : \n node _T_639 = eq(_T_636, UInt<1>(0h0)) \n when _T_639 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_636, UInt<1>(0h1), \"\") : assert_102 \n node _T_640 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_641 = asUInt(reset) \n node _T_642 = eq(_T_641, UInt<1>(0h0)) \n when _T_642 : \n node _T_643 = eq(_T_640, UInt<1>(0h0)) \n when _T_643 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_640, UInt<1>(0h1), \"\") : assert_103 \n node _T_644 = and(io.in.d.valid, d_first_1) \n node _T_645 = and(_T_644, a_first_1) \n node _T_646 = and(_T_645, io.in.a.valid) \n node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_648 = and(_T_646, _T_647) \n node _T_649 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_650 = and(_T_648, _T_649) \n when _T_650 : \n node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_652 = or(_T_651, io.in.a.ready) \n node _T_653 = asUInt(reset) \n node _T_654 = eq(_T_653, UInt<1>(0h0)) \n when _T_654 : \n node _T_655 = eq(_T_652, UInt<1>(0h0)) \n when _T_655 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_652, UInt<1>(0h1), \"\") : assert_104 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_123 \n node _T_656 = orr(inflight) \n node _T_657 = eq(_T_656, UInt<1>(0h0)) \n node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_659 = or(_T_657, _T_658) \n node _T_660 = lt(watchdog, plusarg_reader.out) \n node _T_661 = or(_T_659, _T_660) \n node _T_662 = asUInt(reset) \n node _T_663 = eq(_T_662, UInt<1>(0h0)) \n when _T_663 : \n node _T_664 = eq(_T_661, UInt<1>(0h0)) \n when _T_664 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_661, UInt<1>(0h1), \"\") : assert_105 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_665 = and(io.in.a.ready, io.in.a.valid) \n node _T_666 = and(io.in.d.ready, io.in.d.valid) \n node _T_667 = or(_T_665, _T_666) \n when _T_667 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) \n regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) \n regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<29>(0h0) \n connect _c_first_WIRE.bits.source, UInt<11>(0h0) \n connect _c_first_WIRE.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<1040> \n connect c_set, UInt<1040>(0h0) \n wire c_set_wo_ready : UInt<1040> \n connect c_set_wo_ready, UInt<1040>(0h0) \n wire c_opcodes_set : UInt<4160> \n connect c_opcodes_set, UInt<4160>(0h0) \n wire c_sizes_set : UInt<4160> \n connect c_sizes_set, UInt<4160>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<3> \n connect c_sizes_set_interm, UInt<3>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<29>(0h0) \n connect _WIRE_6.bits.source, UInt<11>(0h0) \n connect _WIRE_6.bits.size, UInt<2>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_668 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<29>(0h0) \n connect _WIRE_8.bits.source, UInt<11>(0h0) \n connect _WIRE_8.bits.size, UInt<2>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_671 = and(_T_669, _T_670) \n node _T_672 = and(_T_668, _T_671) \n when _T_672 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<29>(0h0) \n connect _WIRE_10.bits.source, UInt<11>(0h0) \n connect _WIRE_10.bits.size, UInt<2>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_674 = and(_T_673, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<29>(0h0) \n connect _WIRE_12.bits.source, UInt<11>(0h0) \n connect _WIRE_12.bits.size, UInt<2>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_677 = and(_T_675, _T_676) \n node _T_678 = and(_T_674, _T_677) \n when _T_678 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_set_WIRE.bits.source, UInt<11>(0h0) \n connect _c_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<29>(0h0) \n connect _WIRE_14.bits.source, UInt<11>(0h0) \n connect _WIRE_14.bits.size, UInt<2>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_680 = bits(_T_679, 0, 0) \n node _T_681 = eq(_T_680, UInt<1>(0h0)) \n node _T_682 = asUInt(reset) \n node _T_683 = eq(_T_682, UInt<1>(0h0)) \n when _T_683 : \n node _T_684 = eq(_T_681, UInt<1>(0h0)) \n when _T_684 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_681, UInt<1>(0h1), \"\") : assert_106 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<1040> \n connect d_clr_1, UInt<1040>(0h0) \n wire d_clr_wo_ready_1 : UInt<1040> \n connect d_clr_wo_ready_1, UInt<1040>(0h0) \n wire d_opcodes_clr_1 : UInt<4160> \n connect d_opcodes_clr_1, UInt<4160>(0h0) \n wire d_sizes_clr_1 : UInt<4160> \n connect d_sizes_clr_1, UInt<4160>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_685 = and(io.in.d.valid, d_first_2) \n node _T_686 = and(_T_685, UInt<1>(0h1)) \n node _T_687 = and(_T_686, d_release_ack_1) \n when _T_687 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_688 = and(io.in.d.ready, io.in.d.valid) \n node _T_689 = and(_T_688, d_first_2) \n node _T_690 = and(_T_689, UInt<1>(0h1)) \n node _T_691 = and(_T_690, d_release_ack_1) \n when _T_691 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_692 = and(io.in.d.valid, d_first_2) \n node _T_693 = and(_T_692, UInt<1>(0h1)) \n node _T_694 = and(_T_693, d_release_ack_1) \n when _T_694 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_695 = dshr(inflight_1, io.in.d.bits.source) \n node _T_696 = bits(_T_695, 0, 0) \n node _T_697 = or(_T_696, same_cycle_resp_1) \n node _T_698 = asUInt(reset) \n node _T_699 = eq(_T_698, UInt<1>(0h0)) \n when _T_699 : \n node _T_700 = eq(_T_697, UInt<1>(0h0)) \n when _T_700 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_697, UInt<1>(0h1), \"\") : assert_107 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<29>(0h0) \n connect _WIRE_16.bits.source, UInt<11>(0h0) \n connect _WIRE_16.bits.size, UInt<2>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_702 = asUInt(reset) \n node _T_703 = eq(_T_702, UInt<1>(0h0)) \n when _T_703 : \n node _T_704 = eq(_T_701, UInt<1>(0h0)) \n when _T_704 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_701, UInt<1>(0h1), \"\") : assert_108 \n else :\n\n node _T_705 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_706 = asUInt(reset) \n node _T_707 = eq(_T_706, UInt<1>(0h0)) \n when _T_707 : \n node _T_708 = eq(_T_705, UInt<1>(0h0)) \n when _T_708 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_705, UInt<1>(0h1), \"\") : assert_109 \n node _T_709 = and(io.in.d.valid, d_first_2) \n node _T_710 = and(_T_709, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<29>(0h0) \n connect _WIRE_18.bits.source, UInt<11>(0h0) \n connect _WIRE_18.bits.size, UInt<2>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_711 = and(_T_710, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<29>(0h0) \n connect _WIRE_20.bits.source, UInt<11>(0h0) \n connect _WIRE_20.bits.size, UInt<2>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_713 = and(_T_711, _T_712) \n node _T_714 = and(_T_713, d_release_ack_1) \n node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_716 = and(_T_714, _T_715) \n when _T_716 : \n node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<29>(0h0) \n connect _WIRE_22.bits.source, UInt<11>(0h0) \n connect _WIRE_22.bits.size, UInt<2>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_718 = or(_T_717, _WIRE_23.ready) \n node _T_719 = asUInt(reset) \n node _T_720 = eq(_T_719, UInt<1>(0h0)) \n when _T_720 : \n node _T_721 = eq(_T_718, UInt<1>(0h0)) \n when _T_721 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_718, UInt<1>(0h1), \"\") : assert_110 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_124 \n node _T_722 = orr(inflight_1) \n node _T_723 = eq(_T_722, UInt<1>(0h0)) \n node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_725 = or(_T_723, _T_724) \n node _T_726 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_727 = or(_T_725, _T_726) \n node _T_728 = asUInt(reset) \n node _T_729 = eq(_T_728, UInt<1>(0h0)) \n when _T_729 : \n node _T_730 = eq(_T_727, UInt<1>(0h0)) \n when _T_730 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_727, UInt<1>(0h1), \"\") : assert_111 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<29>(0h0) \n connect _WIRE_24.bits.source, UInt<11>(0h0) \n connect _WIRE_24.bits.size, UInt<2>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_732 = and(io.in.d.ready, io.in.d.valid) \n node _T_733 = or(_T_731, _T_732) \n when _T_733 : \n connect watchdog_1, UInt<1>(0h0) \n\n\n\n\n extmodule plusarg_reader_125 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 1\n\n parameter FORMAT = \"uart_tx=%d\"\n\n parameter WIDTH = 32\n\n\n\n extmodule plusarg_reader_126 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"uart_tx_printf=%d\"\n\n parameter WIDTH = 32"},"response":{"kind":"string","value":"module TLMonitor_61(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [10:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [28:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [10:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _source_ok_T_6 = 1'h0;\t// @[Parameters.scala:54:10]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire a_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire a_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire c_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_first_count_T = 1'h0;\t// @[Edges.scala:234:27]\n wire c_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_counter_T = 1'h0;\t// @[Edges.scala:236:21]\n wire d_first_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _source_ok_T_7 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _a_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _a_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire c_first_counter1 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_2 = 1'h1;\t// @[Edges.scala:232:33]\n wire [1:0] _c_first_counter1_T = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_d_bits_param = 2'h0;\t// @[Monitor.scala:36:7]\n wire [1:0] _c_first_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_first_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_first_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_first_WIRE_2_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_first_WIRE_3_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_set_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_set_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_first_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_first_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_first_WIRE_2_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_first_WIRE_3_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_set_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_set_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_beats1_decode_T_2 = 3'h0;\t// @[package.scala:243:46]\n wire [2:0] c_sizes_set_interm = 3'h0;\t// @[Monitor.scala:755:40]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_T = 3'h0;\t// @[Monitor.scala:766:51]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [16385:0] _c_sizes_set_T_1 = 16386'h0;\t// @[Monitor.scala:768:52]\n wire [13:0] _c_opcodes_set_T = 14'h0;\t// @[Monitor.scala:767:79]\n wire [13:0] _c_sizes_set_T = 14'h0;\t// @[Monitor.scala:768:77]\n wire [16386:0] _c_opcodes_set_T_1 = 16387'h0;\t// @[Monitor.scala:767:54]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_sizes_set_interm_T_1 = 3'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [2047:0] _c_set_wo_ready_T = 2048'h1;\t// @[OneHot.scala:58:35]\n wire [2047:0] _c_set_T = 2048'h1;\t// @[OneHot.scala:58:35]\n wire [4159:0] c_opcodes_set = 4160'h0;\t// @[Monitor.scala:740:34]\n wire [4159:0] c_sizes_set = 4160'h0;\t// @[Monitor.scala:741:34]\n wire [1039:0] c_set = 1040'h0;\t// @[Monitor.scala:738:34]\n wire [1039:0] c_set_wo_ready = 1040'h0;\t// @[Monitor.scala:739:34]\n wire [2:0] _c_first_beats1_decode_T_1 = 3'h7;\t// @[package.scala:243:76]\n wire [5:0] _c_first_beats1_decode_T = 6'h7;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_4;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 29'h0;\t// @[Edges.scala:21:{16,24}]\n wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0};\t// @[Misc.scala:202:34]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [10:0] uncommonBits = _uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_1 = _uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_2 = _uncommonBits_T_2;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_3 = _uncommonBits_T_3;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_4 = _uncommonBits_T_4;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_5 = _uncommonBits_T_5;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_6 = _uncommonBits_T_6;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_7 = _uncommonBits_T_7;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_8 = _uncommonBits_T_8;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_10;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_665;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_665;\t// @[Decoupled.scala:51:35]\n wire a_first_done = _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n wire _a_first_last_T = a_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1 = _a_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~a_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T = ~a_first & a_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [1:0] size;\t// @[Monitor.scala:389:22]\n reg [10:0] source;\t// @[Monitor.scala:390:22]\n reg [28:0] address;\t// @[Monitor.scala:391:22]\n wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_733;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_733;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_733;\t// @[Decoupled.scala:51:35]\n wire d_first_done = _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n wire _d_first_last_T = d_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1 = _d_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire d_first = ~d_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T = ~d_first & d_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg [10:0] source_1;\t// @[Monitor.scala:541:22]\n reg [1039:0] inflight;\t// @[Monitor.scala:614:27]\n reg [4159:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [4159:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire a_first_done_1 = _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n wire _a_first_last_T_2 = a_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1_1 = _a_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire a_first_1 = ~a_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_first_done_1 = _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_2 = d_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_1 = _d_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire d_first_1 = ~d_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [1039:0] a_set;\t// @[Monitor.scala:626:34]\n wire [1039:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [4159:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [4159:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [13:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [13:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [13:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [13:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [13:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [13:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [13:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [13:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [2:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [2047:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [2047:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire _T_598 = _T_665 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [13:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [13:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [1039:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [1039:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [4159:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [4159:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_644 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire _T_613 = _T_733 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [1039:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [1039:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [1039:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [1039:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [4159:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [4159:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire d_first_done_2 = _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_4 = d_first_counter_2;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_2 = _d_first_counter1_T_2[0];\t// @[Edges.scala:230:28]\n wire d_first_2 = ~d_first_counter_2;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [1039:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [1039:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [4159:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [4159:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_709 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire _T_691 = _T_733 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [1039:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32171,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module ScratchpadBank : \n output auto : { flip xbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} \n output clock : Clock \n output reset : Reset \n\n\n wire childClock : Clock \n wire childReset : Reset \n node _childClock_T = asClock(UInt<1>(0h0)) \n connect childClock, _childClock_T \n invalidate childReset \n inst xbar of TLXbar_i1_o1_a28d64s3k1z3u \n connect xbar.clock, childClock\n\n connect xbar.reset, childReset\n\n inst ram of TLRAM_ScratchpadBank \n connect ram.clock, childClock\n\n connect ram.reset, childReset\n\n inst fragmenter of TLFragmenter_ScratchpadBank \n connect fragmenter.clock, childClock\n\n connect fragmenter.reset, childReset\n\n inst buffer of TLBuffer_a28d64s3k1z3u_1 \n connect buffer.clock, childClock\n\n connect buffer.reset, childReset\n\n wire clockNodeIn : { clock : Clock, reset : Reset} \n invalidate clockNodeIn.reset \n invalidate clockNodeIn.clock \n connect buffer.auto.in, xbar.auto.anon_out \n connect ram.auto.in, fragmenter.auto.anon_out \n connect fragmenter.auto.anon_in, buffer.auto.out \n connect clockNodeIn, auto.clock_in \n connect xbar.auto.anon_in, auto.xbar_anon_in \n connect childClock, clockNodeIn.clock \n connect childReset, clockNodeIn.reset \n connect clock, clockNodeIn.clock \n connect reset, clockNodeIn.reset"},"response":{"kind":"string","value":"module ScratchpadBank(\t// @[ClockDomain.scala:14:9]\n output auto_xbar_anon_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_xbar_anon_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_xbar_anon_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_xbar_anon_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_xbar_anon_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_xbar_anon_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [27:0] auto_xbar_anon_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_xbar_anon_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_xbar_anon_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_xbar_anon_in_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_xbar_anon_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_xbar_anon_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_xbar_anon_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_xbar_anon_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_xbar_anon_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_xbar_anon_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_xbar_anon_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_xbar_anon_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_xbar_anon_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_xbar_anon_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_clock_in_clock,\t// @[LazyModuleImp.scala:107:25]\n input auto_clock_in_reset\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire xbar_out_0_d_bits_sink;\t// @[Xbar.scala:216:19]\n wire [2:0] xbar_in_0_d_bits_source;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar_in_0_a_bits_source;\t// @[Xbar.scala:159:18]\n wire xbar_auto_anon_out_d_valid;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_out_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_auto_anon_out_d_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_out_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_out_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_out_d_bits_source;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_out_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [1:0] xbar_auto_anon_out_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_out_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_out_a_ready;\t// @[Xbar.scala:74:9]\n wire _buffer_auto_out_a_valid;\t// @[Buffer.scala:75:28]\n wire [2:0] _buffer_auto_out_a_bits_opcode;\t// @[Buffer.scala:75:28]\n wire [2:0] _buffer_auto_out_a_bits_param;\t// @[Buffer.scala:75:28]\n wire [2:0] _buffer_auto_out_a_bits_size;\t// @[Buffer.scala:75:28]\n wire [2:0] _buffer_auto_out_a_bits_source;\t// @[Buffer.scala:75:28]\n wire [27:0] _buffer_auto_out_a_bits_address;\t// @[Buffer.scala:75:28]\n wire [7:0] _buffer_auto_out_a_bits_mask;\t// @[Buffer.scala:75:28]\n wire [63:0] _buffer_auto_out_a_bits_data;\t// @[Buffer.scala:75:28]\n wire _buffer_auto_out_a_bits_corrupt;\t// @[Buffer.scala:75:28]\n wire _buffer_auto_out_d_ready;\t// @[Buffer.scala:75:28]\n wire _fragmenter_auto_anon_in_a_ready;\t// @[Fragmenter.scala:345:34]\n wire _fragmenter_auto_anon_in_d_valid;\t// @[Fragmenter.scala:345:34]\n wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode;\t// @[Fragmenter.scala:345:34]\n wire [2:0] _fragmenter_auto_anon_in_d_bits_size;\t// @[Fragmenter.scala:345:34]\n wire [2:0] _fragmenter_auto_anon_in_d_bits_source;\t// @[Fragmenter.scala:345:34]\n wire [63:0] _fragmenter_auto_anon_in_d_bits_data;\t// @[Fragmenter.scala:345:34]\n wire _fragmenter_auto_anon_out_a_valid;\t// @[Fragmenter.scala:345:34]\n wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode;\t// @[Fragmenter.scala:345:34]\n wire [2:0] _fragmenter_auto_anon_out_a_bits_param;\t// @[Fragmenter.scala:345:34]\n wire [1:0] _fragmenter_auto_anon_out_a_bits_size;\t// @[Fragmenter.scala:345:34]\n wire [6:0] _fragmenter_auto_anon_out_a_bits_source;\t// @[Fragmenter.scala:345:34]\n wire [27:0] _fragmenter_auto_anon_out_a_bits_address;\t// @[Fragmenter.scala:345:34]\n wire [7:0] _fragmenter_auto_anon_out_a_bits_mask;\t// @[Fragmenter.scala:345:34]\n wire [63:0] _fragmenter_auto_anon_out_a_bits_data;\t// @[Fragmenter.scala:345:34]\n wire _fragmenter_auto_anon_out_a_bits_corrupt;\t// @[Fragmenter.scala:345:34]\n wire _fragmenter_auto_anon_out_d_ready;\t// @[Fragmenter.scala:345:34]\n wire _ram_auto_in_a_ready;\t// @[Scratchpad.scala:33:25]\n wire _ram_auto_in_d_valid;\t// @[Scratchpad.scala:33:25]\n wire [2:0] _ram_auto_in_d_bits_opcode;\t// @[Scratchpad.scala:33:25]\n wire [1:0] _ram_auto_in_d_bits_size;\t// @[Scratchpad.scala:33:25]\n wire [6:0] _ram_auto_in_d_bits_source;\t// @[Scratchpad.scala:33:25]\n wire [63:0] _ram_auto_in_d_bits_data;\t// @[Scratchpad.scala:33:25]\n wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source;\t// @[ClockDomain.scala:14:9]\n wire [27:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address;\t// @[ClockDomain.scala:14:9]\n wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data;\t// @[ClockDomain.scala:14:9]\n wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt;\t// @[ClockDomain.scala:14:9]\n wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready;\t// @[ClockDomain.scala:14:9]\n wire auto_clock_in_clock_0 = auto_clock_in_clock;\t// @[ClockDomain.scala:14:9]\n wire auto_clock_in_reset_0 = auto_clock_in_reset;\t// @[ClockDomain.scala:14:9]\n wire _childClock_T = 1'h0;\t// @[LazyModuleImp.scala:160:25]\n wire xbar__addressC_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__addressC_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__addressC_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__addressC_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar__addressC_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar__addressC_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar__requestBOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__requestBOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__requestBOI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__requestBOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__requestBOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__requestBOI_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire xbar__requestDOI_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire xbar__requestEIO_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__requestEIO_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__requestEIO_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__requestEIO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__requestEIO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__requestEIO_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__beatsBO_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__beatsBO_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__beatsBO_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__beatsBO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__beatsBO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__beatsBO_opdata_T = 1'h0;\t// @[Edges.scala:97:37]\n wire xbar__beatsCI_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__beatsCI_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__beatsCI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__beatsCI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar__beatsCI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar_beatsCI_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire xbar__beatsEI_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__beatsEI_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__beatsEI_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__beatsEI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__beatsEI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__beatsEI_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__portsBIO_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__portsBIO_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__portsBIO_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire xbar__portsBIO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__portsBIO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire xbar_portsBIO_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar_portsBIO_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar_portsBIO_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar__portsBIO_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire xbar__portsCOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__portsCOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__portsCOI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire xbar__portsCOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar__portsCOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire xbar_portsCOI_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar_portsCOI_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar__portsCOI_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire xbar__portsEOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__portsEOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__portsEOI_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire xbar__portsEOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__portsEOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar__portsEOI_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire xbar_portsEOI_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar_portsEOI_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar_portsEOI_filtered_0_bits_sink = 1'h0;\t// @[Xbar.scala:352:24]\n wire xbar__portsEOI_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire [1:0] xbar__requestBOI_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] xbar__requestBOI_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] xbar__beatsBO_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] xbar__beatsBO_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] xbar__portsBIO_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] xbar__portsBIO_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] xbar_portsBIO_filtered_0_bits_param = 2'h0;\t// @[Xbar.scala:352:24]\n wire xbar__requestAIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire xbar_requestAIO_0_0 = 1'h1;\t// @[Xbar.scala:307:107]\n wire xbar__requestCIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire xbar_requestCIO_0_0 = 1'h1;\t// @[Xbar.scala:308:107]\n wire xbar__requestBOI_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire xbar__requestBOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire xbar__requestBOI_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire xbar__requestBOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire xbar_requestBOI_0_0 = 1'h1;\t// @[Parameters.scala:56:48]\n wire xbar__requestDOI_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire xbar__requestDOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire xbar__requestDOI_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire xbar__requestDOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire xbar_requestDOI_0_0 = 1'h1;\t// @[Parameters.scala:56:48]\n wire xbar_beatsBO_opdata = 1'h1;\t// @[Edges.scala:97:28]\n wire xbar__portsAOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire xbar__portsBIO_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire xbar__portsCOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire xbar__portsDIO_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire xbar__portsEOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire [63:0] xbar__addressC_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] xbar__addressC_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] xbar__requestBOI_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:264:74]\n wire [63:0] xbar__requestBOI_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:264:61]\n wire [63:0] xbar__beatsBO_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:264:74]\n wire [63:0] xbar__beatsBO_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:264:61]\n wire [63:0] xbar__beatsCI_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] xbar__beatsCI_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] xbar__portsBIO_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:264:74]\n wire [63:0] xbar__portsBIO_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:264:61]\n wire [63:0] xbar_portsBIO_filtered_0_bits_data = 64'h0;\t// @[Xbar.scala:352:24]\n wire [63:0] xbar__portsCOI_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] xbar__portsCOI_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] xbar_portsCOI_filtered_0_bits_data = 64'h0;\t// @[Xbar.scala:352:24]\n wire [27:0] xbar__addressC_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] xbar__addressC_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] xbar__requestCIO_T = 28'h0;\t// @[Parameters.scala:137:31]\n wire [27:0] xbar__requestBOI_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:264:74]\n wire [27:0] xbar__requestBOI_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:264:61]\n wire [27:0] xbar__beatsBO_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:264:74]\n wire [27:0] xbar__beatsBO_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:264:61]\n wire [27:0] xbar__beatsCI_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] xbar__beatsCI_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] xbar__portsBIO_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:264:74]\n wire [27:0] xbar__portsBIO_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:264:61]\n wire [27:0] xbar_portsBIO_filtered_0_bits_address = 28'h0;\t// @[Xbar.scala:352:24]\n wire [27:0] xbar__portsCOI_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] xbar__portsCOI_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] xbar_portsCOI_filtered_0_bits_address = 28'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] xbar__addressC_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__addressC_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__addressC_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__addressC_WIRE_bits_source = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__addressC_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__addressC_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__addressC_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__addressC_WIRE_1_bits_source = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__requestBOI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__requestBOI_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__requestBOI_WIRE_bits_source = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__requestBOI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar__requestBOI_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar__requestBOI_WIRE_1_bits_source = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar__requestBOI_uncommonBits_T = 3'h0;\t// @[Parameters.scala:52:29]\n wire [2:0] xbar_requestBOI_uncommonBits = 3'h0;\t// @[Parameters.scala:52:56]\n wire [2:0] xbar__beatsBO_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__beatsBO_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__beatsBO_WIRE_bits_source = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__beatsBO_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar__beatsBO_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar__beatsBO_WIRE_1_bits_source = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar_beatsBO_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] xbar_beatsBO_0 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] xbar__beatsCI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__beatsCI_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__beatsCI_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__beatsCI_WIRE_bits_source = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__beatsCI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__beatsCI_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__beatsCI_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__beatsCI_WIRE_1_bits_source = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar_beatsCI_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] xbar_beatsCI_0 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] xbar__portsBIO_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__portsBIO_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__portsBIO_WIRE_bits_source = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] xbar__portsBIO_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar__portsBIO_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar__portsBIO_WIRE_1_bits_source = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] xbar_portsBIO_filtered_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] xbar_portsBIO_filtered_0_bits_size = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] xbar_portsBIO_filtered_0_bits_source = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] xbar__portsCOI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__portsCOI_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__portsCOI_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__portsCOI_WIRE_bits_source = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] xbar__portsCOI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__portsCOI_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__portsCOI_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar__portsCOI_WIRE_1_bits_source = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] xbar_portsCOI_filtered_0_bits_param = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] xbar_portsCOI_filtered_0_bits_size = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] xbar_portsCOI_filtered_0_bits_source = 3'h0;\t// @[Xbar.scala:352:24]\n wire [7:0] xbar__requestBOI_WIRE_bits_mask = 8'h0;\t// @[Bundles.scala:264:74]\n wire [7:0] xbar__requestBOI_WIRE_1_bits_mask = 8'h0;\t// @[Bundles.scala:264:61]\n wire [7:0] xbar__beatsBO_WIRE_bits_mask = 8'h0;\t// @[Bundles.scala:264:74]\n wire [7:0] xbar__beatsBO_WIRE_1_bits_mask = 8'h0;\t// @[Bundles.scala:264:61]\n wire [7:0] xbar__portsBIO_WIRE_bits_mask = 8'h0;\t// @[Bundles.scala:264:74]\n wire [7:0] xbar__portsBIO_WIRE_1_bits_mask = 8'h0;\t// @[Bundles.scala:264:61]\n wire [7:0] xbar_portsBIO_filtered_0_bits_mask = 8'h0;\t// @[Xbar.scala:352:24]\n wire [5:0] xbar__beatsBO_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] xbar__beatsCI_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] xbar__beatsBO_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [5:0] xbar__beatsCI_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] xbar__beatsBO_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [12:0] xbar__beatsCI_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire xbar_auto_anon_in_a_ready;\t// @[Xbar.scala:74:9]\n wire [28:0] xbar__requestAIO_T_2 = 29'h0;\t// @[Parameters.scala:137:46]\n wire [28:0] xbar__requestAIO_T_3 = 29'h0;\t// @[Parameters.scala:137:46]\n wire [28:0] xbar__requestCIO_T_1 = 29'h0;\t// @[Parameters.scala:137:41]\n wire [28:0] xbar__requestCIO_T_2 = 29'h0;\t// @[Parameters.scala:137:46]\n wire [28:0] xbar__requestCIO_T_3 = 29'h0;\t// @[Parameters.scala:137:46]\n wire xbar_auto_anon_in_a_valid = auto_xbar_anon_in_a_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_in_a_bits_opcode = auto_xbar_anon_in_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_in_a_bits_param = auto_xbar_anon_in_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_in_a_bits_size = auto_xbar_anon_in_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_in_a_bits_source = auto_xbar_anon_in_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [27:0] xbar_auto_anon_in_a_bits_address = auto_xbar_anon_in_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [7:0] xbar_auto_anon_in_a_bits_mask = auto_xbar_anon_in_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_auto_anon_in_a_bits_data = auto_xbar_anon_in_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_in_a_bits_corrupt = auto_xbar_anon_in_a_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_in_d_ready = auto_xbar_anon_in_d_ready_0;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_in_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_in_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] xbar_auto_anon_in_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_in_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_in_d_bits_source;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_in_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_in_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_auto_anon_in_d_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_in_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire clockNodeIn_clock = auto_clock_in_clock_0;\t// @[ClockDomain.scala:14:9]\n wire clockNodeIn_reset = auto_clock_in_reset_0;\t// @[ClockDomain.scala:14:9]\n wire auto_xbar_anon_in_a_ready_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_xbar_anon_in_d_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n wire [1:0] auto_xbar_anon_in_d_bits_param_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_xbar_anon_in_d_bits_size_0;\t// @[ClockDomain.scala:14:9]\n wire [2:0] auto_xbar_anon_in_d_bits_source_0;\t// @[ClockDomain.scala:14:9]\n wire auto_xbar_anon_in_d_bits_sink_0;\t// @[ClockDomain.scala:14:9]\n wire auto_xbar_anon_in_d_bits_denied_0;\t// @[ClockDomain.scala:14:9]\n wire [63:0] auto_xbar_anon_in_d_bits_data_0;\t// @[ClockDomain.scala:14:9]\n wire auto_xbar_anon_in_d_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\n wire auto_xbar_anon_in_d_valid_0;\t// @[ClockDomain.scala:14:9]\n wire childClock;\t// @[LazyModuleImp.scala:155:31]\n wire childReset;\t// @[LazyModuleImp.scala:158:31]\n wire xbar_anonIn_a_ready;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_a_ready_0 = xbar_auto_anon_in_a_ready;\t// @[Xbar.scala:74:9]\n wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [27:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_anonIn_a_bits_corrupt = xbar_auto_anon_in_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready;\t// @[Xbar.scala:74:9]\n wire xbar_anonIn_d_valid;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_valid_0 = xbar_auto_anon_in_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_opcode_0 = xbar_auto_anon_in_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] xbar_anonIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_param_0 = xbar_auto_anon_in_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_size_0 = xbar_auto_anon_in_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_source_0 = xbar_auto_anon_in_d_bits_source;\t// @[Xbar.scala:74:9]\n wire xbar_anonIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_sink_0 = xbar_auto_anon_in_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire xbar_anonIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_denied_0 = xbar_auto_anon_in_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_anonIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_data_0 = xbar_auto_anon_in_d_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_anonIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n assign auto_xbar_anon_in_d_bits_corrupt_0 = xbar_auto_anon_in_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready;\t// @[Xbar.scala:74:9]\n wire xbar_anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] xbar_anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] xbar_anonOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [2:0] xbar_anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [2:0] xbar_anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [27:0] xbar_anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] xbar_anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] xbar_anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire xbar_anonOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire xbar_anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source;\t// @[Xbar.scala:74:9]\n wire xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_out_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_out_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_out_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_auto_anon_out_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [27:0] xbar_auto_anon_out_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [7:0] xbar_auto_anon_out_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_auto_anon_out_a_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_out_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_out_a_valid;\t// @[Xbar.scala:74:9]\n wire xbar_auto_anon_out_d_ready;\t// @[Xbar.scala:74:9]\n wire xbar_out_0_a_ready = xbar_anonOut_a_ready;\t// @[Xbar.scala:216:19]\n wire xbar_out_0_a_valid;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [27:0] xbar_out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [7:0] xbar_out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_out_0_a_bits_corrupt;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_a_bits_corrupt = xbar_anonOut_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire xbar_out_0_d_ready;\t// @[Xbar.scala:216:19]\n assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready;\t// @[Xbar.scala:74:9]\n wire xbar_out_0_d_valid = xbar_anonOut_d_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param;\t// @[Xbar.scala:216:19]\n wire [2:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size;\t// @[Xbar.scala:216:19]\n wire [2:0] xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source;\t// @[Xbar.scala:216:19]\n wire xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink;\t// @[Xbar.scala:251:53]\n wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied;\t// @[Xbar.scala:216:19]\n wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data;\t// @[Xbar.scala:216:19]\n wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt;\t// @[Xbar.scala:216:19]\n wire xbar_in_0_a_ready;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready;\t// @[Xbar.scala:74:9]\n wire xbar_in_0_a_valid = xbar_anonIn_a_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source;\t// @[Xbar.scala:166:55]\n wire [27:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask;\t// @[Xbar.scala:159:18]\n wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data;\t// @[Xbar.scala:159:18]\n wire xbar_in_0_a_bits_corrupt = xbar_anonIn_a_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire xbar_in_0_d_ready = xbar_anonIn_d_ready;\t// @[Xbar.scala:159:18]\n wire xbar_in_0_d_valid;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] xbar_in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar_in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] xbar__anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source;\t// @[Xbar.scala:74:9]\n wire xbar_in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire xbar_in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [63:0] xbar_in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data;\t// @[Xbar.scala:74:9]\n wire xbar_in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire xbar_portsAOI_filtered_0_ready;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_a_ready = xbar_in_0_a_ready;\t// @[Xbar.scala:159:18]\n wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n wire [27:0] xbar__requestAIO_T = xbar_in_0_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [27:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask;\t// @[Xbar.scala:159:18, :352:24]\n wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n wire xbar_portsAOI_filtered_0_bits_corrupt = xbar_in_0_a_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire xbar_portsDIO_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_valid = xbar_in_0_d_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar_portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] xbar_portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar_portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n wire [2:0] xbar_portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:352:24]\n assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source;\t// @[Xbar.scala:156:69, :159:18]\n wire xbar_portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n wire xbar_portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n wire [63:0] xbar_portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n wire xbar_portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T;\t// @[Xbar.scala:159:18, :166:55]\n assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready;\t// @[Xbar.scala:216:19, :352:24]\n wire xbar_portsAOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign xbar_anonOut_a_valid = xbar_out_0_a_valid;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_a_bits_corrupt = xbar_out_0_a_bits_corrupt;\t// @[Xbar.scala:216:19]\n assign xbar_anonOut_d_ready = xbar_out_0_d_ready;\t// @[Xbar.scala:216:19]\n wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid;\t// @[Xbar.scala:216:19, :355:40]\n assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n wire [2:0] xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source;\t// @[Xbar.scala:216:19]\n assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T;\t// @[Xbar.scala:216:19, :251:53]\n wire [28:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T};\t// @[Parameters.scala:137:{31,41}]\n wire [2:0] xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [12:0] xbar__beatsAI_decode_T = 13'h3F << xbar_in_0_a_bits_size;\t// @[package.scala:243:71]\n wire [5:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2];\t// @[Xbar.scala:159:18]\n wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n wire [12:0] xbar__beatsDO_decode_T = 13'h3F << xbar_out_0_d_bits_size;\t// @[package.scala:243:71]\n wire [5:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0];\t// @[Xbar.scala:216:19]\n wire [2:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_out_0_a_bits_corrupt = xbar_portsAOI_filtered_0_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready;\t// @[Xbar.scala:216:19, :352:24]\n assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n assign childClock = clockNodeIn_clock;\t// @[MixedNode.scala:551:17]\n assign childReset = clockNodeIn_reset;\t// @[MixedNode.scala:551:17]\n TLRAM_ScratchpadBank ram (\t// @[Scratchpad.scala:33:25]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset),\t// @[LazyModuleImp.scala:158:31]\n .auto_in_a_ready (_ram_auto_in_a_ready),\n .auto_in_a_valid (_fragmenter_auto_anon_out_a_valid),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),\t// @[Fragmenter.scala:345:34]\n .auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),\t// @[Fragmenter.scala:345:34]\n .auto_in_d_ready (_fragmenter_auto_anon_out_d_ready),\t// @[Fragmenter.scala:345:34]\n .auto_in_d_valid (_ram_auto_in_d_valid),\n .auto_in_d_bits_opcode (_ram_auto_in_d_bits_opcode),\n .auto_in_d_bits_size (_ram_auto_in_d_bits_size),\n .auto_in_d_bits_source (_ram_auto_in_d_bits_source),\n .auto_in_d_bits_data (_ram_auto_in_d_bits_data)\n );\t// @[Scratchpad.scala:33:25]\n TLFragmenter_ScratchpadBank fragmenter (\t// @[Fragmenter.scala:345:34]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset),\t// @[LazyModuleImp.scala:158:31]\n .auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),\n .auto_anon_in_a_valid (_buffer_auto_out_a_valid),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data),\t// @[Buffer.scala:75:28]\n .auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),\t// @[Buffer.scala:75:28]\n .auto_anon_in_d_ready (_buffer_auto_out_d_ready),\t// @[Buffer.scala:75:28]\n .auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),\n .auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),\n .auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),\n .auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),\n .auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),\n .auto_anon_out_a_ready (_ram_auto_in_a_ready),\t// @[Scratchpad.scala:33:25]\n .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),\n .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),\n .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),\n .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),\n .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),\n .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),\n .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),\n .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),\n .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),\n .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),\n .auto_anon_out_d_valid (_ram_auto_in_d_valid),\t// @[Scratchpad.scala:33:25]\n .auto_anon_out_d_bits_opcode (_ram_auto_in_d_bits_opcode),\t// @[Scratchpad.scala:33:25]\n .auto_anon_out_d_bits_size (_ram_auto_in_d_bits_size),\t// @[Scratchpad.scala:33:25]\n .auto_anon_out_d_bits_source (_ram_auto_in_d_bits_source),\t// @[Scratchpad.scala:33:25]\n .auto_anon_out_d_bits_data (_ram_auto_in_d_bits_data)\t// @[Scratchpad.scala:33:25]\n );\t// @[Fragmenter.scala:345:34]\n TLBuffer_a28d64s3k1z3u_1 buffer (\t// @[Buffer.scala:75:28]\n .clock (childClock),\t// @[LazyModuleImp.scala:155:31]\n .reset (childReset),\t// @[LazyModuleImp.scala:158:31]\n .auto_in_a_ready (xbar_auto_anon_out_a_ready),\n .auto_in_a_valid (xbar_auto_anon_out_a_valid),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data),\t// @[Xbar.scala:74:9]\n .auto_in_a_bits_corrupt (xbar_auto_anon_out_a_bits_corrupt),\t// @[Xbar.scala:74:9]\n .auto_in_d_ready (xbar_auto_anon_out_d_ready),\t// @[Xbar.scala:74:9]\n .auto_in_d_valid (xbar_auto_anon_out_d_valid),\n .auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode),\n .auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param),\n .auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size),\n .auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source),\n .auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink),\n .auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied),\n .auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data),\n .auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt),\n .auto_out_a_ready (_fragmenter_auto_anon_in_a_ready),\t// @[Fragmenter.scala:345:34]\n .auto_out_a_valid (_buffer_auto_out_a_valid),\n .auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),\n .auto_out_a_bits_param (_buffer_auto_out_a_bits_param),\n .auto_out_a_bits_size (_buffer_auto_out_a_bits_size),\n .auto_out_a_bits_source (_buffer_auto_out_a_bits_source),\n .auto_out_a_bits_address (_buffer_auto_out_a_bits_address),\n .auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),\n .auto_out_a_bits_data (_buffer_auto_out_a_bits_data),\n .auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),\n .auto_out_d_ready (_buffer_auto_out_d_ready),\n .auto_out_d_valid (_fragmenter_auto_anon_in_d_valid),\t// @[Fragmenter.scala:345:34]\n .auto_out_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),\t// @[Fragmenter.scala:345:34]\n .auto_out_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),\t// @[Fragmenter.scala:345:34]\n .auto_out_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),\t// @[Fragmenter.scala:345:34]\n .auto_out_d_bits_data (_fragmenter_auto_anon_in_d_bits_data)\t// @[Fragmenter.scala:345:34]\n );\t// @[Buffer.scala:75:28]\n assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_param = auto_xbar_anon_in_d_bits_param_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_sink = auto_xbar_anon_in_d_bits_sink_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_denied = auto_xbar_anon_in_d_bits_denied_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0;\t// @[ClockDomain.scala:14:9]\n assign auto_xbar_anon_in_d_bits_corrupt = auto_xbar_anon_in_d_bits_corrupt_0;\t// @[ClockDomain.scala:14:9]\nendmodule"}}},{"rowIdx":32172,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_8 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} \n\n\n wire _in_flight_WIRE : UInt<1>[10] \n connect _in_flight_WIRE[0], UInt<1>(0h0) \n connect _in_flight_WIRE[1], UInt<1>(0h0) \n connect _in_flight_WIRE[2], UInt<1>(0h0) \n connect _in_flight_WIRE[3], UInt<1>(0h0) \n connect _in_flight_WIRE[4], UInt<1>(0h0) \n connect _in_flight_WIRE[5], UInt<1>(0h0) \n connect _in_flight_WIRE[6], UInt<1>(0h0) \n connect _in_flight_WIRE[7], UInt<1>(0h0) \n connect _in_flight_WIRE[8], UInt<1>(0h0) \n connect _in_flight_WIRE[9], UInt<1>(0h0) \n regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE \n when io.in.flit[0].valid : \n when io.in.flit[0].bits.head : \n connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) \n node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Flit head/tail sequencing is broken\\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \\\"Flit head/tail sequencing is broken\\\")\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n when io.in.flit[0].bits.tail : \n connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) \n node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) \n when _T_4 : \n node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) \n node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_8 = and(_T_6, _T_7) \n node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_10 = and(_T_8, _T_9) \n node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_12 = and(_T_10, _T_11) \n node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) \n node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_15 = and(_T_13, _T_14) \n node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_17 = and(_T_15, _T_16) \n node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_19 = and(_T_17, _T_18) \n node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) \n node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_22 = and(_T_20, _T_21) \n node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_24 = and(_T_22, _T_23) \n node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_26 = and(_T_24, _T_25) \n node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) \n node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_29 = and(_T_27, _T_28) \n node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_31 = and(_T_29, _T_30) \n node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_33 = and(_T_31, _T_32) \n node _T_34 = or(_T_12, _T_19) \n node _T_35 = or(_T_34, _T_26) \n node _T_36 = or(_T_35, _T_33) \n node _T_37 = or(_T_5, _T_36) \n node _T_38 = asUInt(reset) \n node _T_39 = eq(_T_38, UInt<1>(0h0)) \n when _T_39 : \n node _T_40 = eq(_T_37, UInt<1>(0h0)) \n when _T_40 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_1 \n assert(clock, _T_37, UInt<1>(0h1), \"\") : assert_1 \n node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) \n node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_43 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_44 = and(_T_42, _T_43) \n node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_46 = and(_T_44, _T_45) \n node _T_47 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_48 = and(_T_46, _T_47) \n node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) \n node _T_50 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_51 = and(_T_49, _T_50) \n node _T_52 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_53 = and(_T_51, _T_52) \n node _T_54 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_55 = and(_T_53, _T_54) \n node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) \n node _T_57 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_58 = and(_T_56, _T_57) \n node _T_59 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_60 = and(_T_58, _T_59) \n node _T_61 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_62 = and(_T_60, _T_61) \n node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) \n node _T_64 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_65 = and(_T_63, _T_64) \n node _T_66 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) \n node _T_67 = and(_T_65, _T_66) \n node _T_68 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) \n node _T_69 = and(_T_67, _T_68) \n node _T_70 = or(_T_48, _T_55) \n node _T_71 = or(_T_70, _T_62) \n node _T_72 = or(_T_71, _T_69) \n node _T_73 = or(_T_41, _T_72) \n node _T_74 = asUInt(reset) \n node _T_75 = eq(_T_74, UInt<1>(0h0)) \n when _T_75 : \n node _T_76 = eq(_T_73, UInt<1>(0h0)) \n when _T_76 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_2 \n assert(clock, _T_73, UInt<1>(0h1), \"\") : assert_2 \n node _T_77 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) \n node _T_78 = or(_T_77, UInt<1>(0h0)) \n node _T_79 = asUInt(reset) \n node _T_80 = eq(_T_79, UInt<1>(0h0)) \n when _T_80 : \n node _T_81 = eq(_T_78, UInt<1>(0h0)) \n when _T_81 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_3 \n assert(clock, _T_78, UInt<1>(0h1), \"\") : assert_3 \n node _T_82 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) \n node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) \n node _T_85 = and(_T_83, _T_84) \n node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_87 = and(_T_85, _T_86) \n node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_89 = and(_T_87, _T_88) \n node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) \n node _T_92 = and(_T_90, _T_91) \n node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_94 = and(_T_92, _T_93) \n node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_96 = and(_T_94, _T_95) \n node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) \n node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) \n node _T_99 = and(_T_97, _T_98) \n node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) \n node _T_101 = and(_T_99, _T_100) \n node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_103 = and(_T_101, _T_102) \n node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) \n node _T_106 = and(_T_104, _T_105) \n node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_108 = and(_T_106, _T_107) \n node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_110 = and(_T_108, _T_109) \n node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) \n node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) \n node _T_113 = and(_T_111, _T_112) \n node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) \n node _T_115 = and(_T_113, _T_114) \n node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_117 = and(_T_115, _T_116) \n node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) \n node _T_120 = and(_T_118, _T_119) \n node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_122 = and(_T_120, _T_121) \n node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_124 = and(_T_122, _T_123) \n node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_126 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) \n node _T_127 = and(_T_125, _T_126) \n node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_129 = and(_T_127, _T_128) \n node _T_130 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_131 = and(_T_129, _T_130) \n node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_133 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) \n node _T_134 = and(_T_132, _T_133) \n node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_136 = and(_T_134, _T_135) \n node _T_137 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_138 = and(_T_136, _T_137) \n node _T_139 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_140 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) \n node _T_141 = and(_T_139, _T_140) \n node _T_142 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_143 = and(_T_141, _T_142) \n node _T_144 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_145 = and(_T_143, _T_144) \n node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) \n node _T_148 = and(_T_146, _T_147) \n node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_150 = and(_T_148, _T_149) \n node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_152 = and(_T_150, _T_151) \n node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) \n node _T_155 = and(_T_153, _T_154) \n node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_157 = and(_T_155, _T_156) \n node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_159 = and(_T_157, _T_158) \n node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) \n node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) \n node _T_162 = and(_T_160, _T_161) \n node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) \n node _T_164 = and(_T_162, _T_163) \n node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_166 = and(_T_164, _T_165) \n node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) \n node _T_169 = and(_T_167, _T_168) \n node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_171 = and(_T_169, _T_170) \n node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_173 = and(_T_171, _T_172) \n node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) \n node _T_176 = and(_T_174, _T_175) \n node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_178 = and(_T_176, _T_177) \n node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_180 = and(_T_178, _T_179) \n node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) \n node _T_183 = and(_T_181, _T_182) \n node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_185 = and(_T_183, _T_184) \n node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_187 = and(_T_185, _T_186) \n node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) \n node _T_190 = and(_T_188, _T_189) \n node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_192 = and(_T_190, _T_191) \n node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_194 = and(_T_192, _T_193) \n node _T_195 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) \n node _T_196 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) \n node _T_197 = and(_T_195, _T_196) \n node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) \n node _T_199 = and(_T_197, _T_198) \n node _T_200 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_201 = and(_T_199, _T_200) \n node _T_202 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_203 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) \n node _T_204 = and(_T_202, _T_203) \n node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_206 = and(_T_204, _T_205) \n node _T_207 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_208 = and(_T_206, _T_207) \n node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_210 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) \n node _T_211 = and(_T_209, _T_210) \n node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_213 = and(_T_211, _T_212) \n node _T_214 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_215 = and(_T_213, _T_214) \n node _T_216 = or(_T_89, _T_96) \n node _T_217 = or(_T_216, _T_103) \n node _T_218 = or(_T_217, _T_110) \n node _T_219 = or(_T_218, _T_117) \n node _T_220 = or(_T_219, _T_124) \n node _T_221 = or(_T_220, _T_131) \n node _T_222 = or(_T_221, _T_138) \n node _T_223 = or(_T_222, _T_145) \n node _T_224 = or(_T_223, _T_152) \n node _T_225 = or(_T_224, _T_159) \n node _T_226 = or(_T_225, _T_166) \n node _T_227 = or(_T_226, _T_173) \n node _T_228 = or(_T_227, _T_180) \n node _T_229 = or(_T_228, _T_187) \n node _T_230 = or(_T_229, _T_194) \n node _T_231 = or(_T_230, _T_201) \n node _T_232 = or(_T_231, _T_208) \n node _T_233 = or(_T_232, _T_215) \n node _T_234 = or(_T_82, _T_233) \n node _T_235 = asUInt(reset) \n node _T_236 = eq(_T_235, UInt<1>(0h0)) \n when _T_236 : \n node _T_237 = eq(_T_234, UInt<1>(0h0)) \n when _T_237 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_4 \n assert(clock, _T_234, UInt<1>(0h1), \"\") : assert_4 \n node _T_238 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) \n node _T_239 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_240 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_241 = and(_T_239, _T_240) \n node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_243 = and(_T_241, _T_242) \n node _T_244 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_245 = and(_T_243, _T_244) \n node _T_246 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) \n node _T_247 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_248 = and(_T_246, _T_247) \n node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_250 = and(_T_248, _T_249) \n node _T_251 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_252 = and(_T_250, _T_251) \n node _T_253 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) \n node _T_254 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_255 = and(_T_253, _T_254) \n node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_257 = and(_T_255, _T_256) \n node _T_258 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_259 = and(_T_257, _T_258) \n node _T_260 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) \n node _T_261 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_262 = and(_T_260, _T_261) \n node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_264 = and(_T_262, _T_263) \n node _T_265 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_266 = and(_T_264, _T_265) \n node _T_267 = or(_T_245, _T_252) \n node _T_268 = or(_T_267, _T_259) \n node _T_269 = or(_T_268, _T_266) \n node _T_270 = or(_T_238, _T_269) \n node _T_271 = asUInt(reset) \n node _T_272 = eq(_T_271, UInt<1>(0h0)) \n when _T_272 : \n node _T_273 = eq(_T_270, UInt<1>(0h0)) \n when _T_273 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_5 \n assert(clock, _T_270, UInt<1>(0h1), \"\") : assert_5 \n node _T_274 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) \n node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_276 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_277 = and(_T_275, _T_276) \n node _T_278 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_279 = and(_T_277, _T_278) \n node _T_280 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_281 = and(_T_279, _T_280) \n node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) \n node _T_283 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_284 = and(_T_282, _T_283) \n node _T_285 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_286 = and(_T_284, _T_285) \n node _T_287 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_288 = and(_T_286, _T_287) \n node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) \n node _T_290 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_291 = and(_T_289, _T_290) \n node _T_292 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_293 = and(_T_291, _T_292) \n node _T_294 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_295 = and(_T_293, _T_294) \n node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) \n node _T_297 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_298 = and(_T_296, _T_297) \n node _T_299 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) \n node _T_300 = and(_T_298, _T_299) \n node _T_301 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) \n node _T_302 = and(_T_300, _T_301) \n node _T_303 = or(_T_281, _T_288) \n node _T_304 = or(_T_303, _T_295) \n node _T_305 = or(_T_304, _T_302) \n node _T_306 = or(_T_274, _T_305) \n node _T_307 = asUInt(reset) \n node _T_308 = eq(_T_307, UInt<1>(0h0)) \n when _T_308 : \n node _T_309 = eq(_T_306, UInt<1>(0h0)) \n when _T_309 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_6 \n assert(clock, _T_306, UInt<1>(0h1), \"\") : assert_6 \n node _T_310 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) \n node _T_311 = or(_T_310, UInt<1>(0h0)) \n node _T_312 = asUInt(reset) \n node _T_313 = eq(_T_312, UInt<1>(0h0)) \n when _T_313 : \n node _T_314 = eq(_T_311, UInt<1>(0h0)) \n when _T_314 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_7 \n assert(clock, _T_311, UInt<1>(0h1), \"\") : assert_7 \n node _T_315 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) \n node _T_316 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_317 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) \n node _T_318 = and(_T_316, _T_317) \n node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_320 = and(_T_318, _T_319) \n node _T_321 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_322 = and(_T_320, _T_321) \n node _T_323 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_324 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) \n node _T_325 = and(_T_323, _T_324) \n node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_327 = and(_T_325, _T_326) \n node _T_328 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_329 = and(_T_327, _T_328) \n node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_331 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) \n node _T_332 = and(_T_330, _T_331) \n node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_334 = and(_T_332, _T_333) \n node _T_335 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_336 = and(_T_334, _T_335) \n node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_338 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) \n node _T_339 = and(_T_337, _T_338) \n node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_341 = and(_T_339, _T_340) \n node _T_342 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_343 = and(_T_341, _T_342) \n node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_345 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) \n node _T_346 = and(_T_344, _T_345) \n node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_348 = and(_T_346, _T_347) \n node _T_349 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_350 = and(_T_348, _T_349) \n node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_352 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) \n node _T_353 = and(_T_351, _T_352) \n node _T_354 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_355 = and(_T_353, _T_354) \n node _T_356 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_357 = and(_T_355, _T_356) \n node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_359 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) \n node _T_360 = and(_T_358, _T_359) \n node _T_361 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_362 = and(_T_360, _T_361) \n node _T_363 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_364 = and(_T_362, _T_363) \n node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_366 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) \n node _T_367 = and(_T_365, _T_366) \n node _T_368 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_369 = and(_T_367, _T_368) \n node _T_370 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_371 = and(_T_369, _T_370) \n node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) \n node _T_373 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) \n node _T_374 = and(_T_372, _T_373) \n node _T_375 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_376 = and(_T_374, _T_375) \n node _T_377 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_378 = and(_T_376, _T_377) \n node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_380 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) \n node _T_381 = and(_T_379, _T_380) \n node _T_382 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_383 = and(_T_381, _T_382) \n node _T_384 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_385 = and(_T_383, _T_384) \n node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) \n node _T_387 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) \n node _T_388 = and(_T_386, _T_387) \n node _T_389 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_390 = and(_T_388, _T_389) \n node _T_391 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_392 = and(_T_390, _T_391) \n node _T_393 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) \n node _T_394 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) \n node _T_395 = and(_T_393, _T_394) \n node _T_396 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_397 = and(_T_395, _T_396) \n node _T_398 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_399 = and(_T_397, _T_398) \n node _T_400 = or(_T_322, _T_329) \n node _T_401 = or(_T_400, _T_336) \n node _T_402 = or(_T_401, _T_343) \n node _T_403 = or(_T_402, _T_350) \n node _T_404 = or(_T_403, _T_357) \n node _T_405 = or(_T_404, _T_364) \n node _T_406 = or(_T_405, _T_371) \n node _T_407 = or(_T_406, _T_378) \n node _T_408 = or(_T_407, _T_385) \n node _T_409 = or(_T_408, _T_392) \n node _T_410 = or(_T_409, _T_399) \n node _T_411 = or(_T_315, _T_410) \n node _T_412 = asUInt(reset) \n node _T_413 = eq(_T_412, UInt<1>(0h0)) \n when _T_413 : \n node _T_414 = eq(_T_411, UInt<1>(0h0)) \n when _T_414 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_8 \n assert(clock, _T_411, UInt<1>(0h1), \"\") : assert_8 \n node _T_415 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) \n node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) \n node _T_417 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_418 = and(_T_416, _T_417) \n node _T_419 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_420 = and(_T_418, _T_419) \n node _T_421 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_422 = and(_T_420, _T_421) \n node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) \n node _T_424 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_425 = and(_T_423, _T_424) \n node _T_426 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_427 = and(_T_425, _T_426) \n node _T_428 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_429 = and(_T_427, _T_428) \n node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_431 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_432 = and(_T_430, _T_431) \n node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_434 = and(_T_432, _T_433) \n node _T_435 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_436 = and(_T_434, _T_435) \n node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) \n node _T_438 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_439 = and(_T_437, _T_438) \n node _T_440 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_441 = and(_T_439, _T_440) \n node _T_442 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_443 = and(_T_441, _T_442) \n node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) \n node _T_445 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_446 = and(_T_444, _T_445) \n node _T_447 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_448 = and(_T_446, _T_447) \n node _T_449 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_450 = and(_T_448, _T_449) \n node _T_451 = or(_T_422, _T_429) \n node _T_452 = or(_T_451, _T_436) \n node _T_453 = or(_T_452, _T_443) \n node _T_454 = or(_T_453, _T_450) \n node _T_455 = or(_T_415, _T_454) \n node _T_456 = asUInt(reset) \n node _T_457 = eq(_T_456, UInt<1>(0h0)) \n when _T_457 : \n node _T_458 = eq(_T_455, UInt<1>(0h0)) \n when _T_458 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_9 \n assert(clock, _T_455, UInt<1>(0h1), \"\") : assert_9 \n node _T_459 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) \n node _T_460 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) \n node _T_461 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_462 = and(_T_460, _T_461) \n node _T_463 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_464 = and(_T_462, _T_463) \n node _T_465 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_466 = and(_T_464, _T_465) \n node _T_467 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) \n node _T_468 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_469 = and(_T_467, _T_468) \n node _T_470 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_471 = and(_T_469, _T_470) \n node _T_472 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_473 = and(_T_471, _T_472) \n node _T_474 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_475 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_476 = and(_T_474, _T_475) \n node _T_477 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_478 = and(_T_476, _T_477) \n node _T_479 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_480 = and(_T_478, _T_479) \n node _T_481 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) \n node _T_482 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_483 = and(_T_481, _T_482) \n node _T_484 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_485 = and(_T_483, _T_484) \n node _T_486 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_487 = and(_T_485, _T_486) \n node _T_488 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) \n node _T_489 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_490 = and(_T_488, _T_489) \n node _T_491 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_492 = and(_T_490, _T_491) \n node _T_493 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_494 = and(_T_492, _T_493) \n node _T_495 = or(_T_466, _T_473) \n node _T_496 = or(_T_495, _T_480) \n node _T_497 = or(_T_496, _T_487) \n node _T_498 = or(_T_497, _T_494) \n node _T_499 = or(_T_459, _T_498) \n node _T_500 = asUInt(reset) \n node _T_501 = eq(_T_500, UInt<1>(0h0)) \n when _T_501 : \n node _T_502 = eq(_T_499, UInt<1>(0h0)) \n when _T_502 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_10 \n assert(clock, _T_499, UInt<1>(0h1), \"\") : assert_10"},"response":{"kind":"string","value":"module NoCMonitor_8(\t// @[Monitor.scala:11:7]\n input clock,\t// @[Monitor.scala:11:7]\n input reset,\t// @[Monitor.scala:11:7]\n input io_in_flit_0_valid,\t// @[Monitor.scala:12:14]\n input io_in_flit_0_bits_head,\t// @[Monitor.scala:12:14]\n input io_in_flit_0_bits_tail,\t// @[Monitor.scala:12:14]\n input [3:0] io_in_flit_0_bits_flow_ingress_node,\t// @[Monitor.scala:12:14]\n input [2:0] io_in_flit_0_bits_flow_ingress_node_id,\t// @[Monitor.scala:12:14]\n input [3:0] io_in_flit_0_bits_flow_egress_node,\t// @[Monitor.scala:12:14]\n input [2:0] io_in_flit_0_bits_flow_egress_node_id,\t// @[Monitor.scala:12:14]\n input [3:0] io_in_flit_0_bits_virt_channel_id\t// @[Monitor.scala:12:14]\n);\n\n reg in_flight_0;\t// @[Monitor.scala:16:26]\n reg in_flight_1;\t// @[Monitor.scala:16:26]\n reg in_flight_2;\t// @[Monitor.scala:16:26]\n reg in_flight_3;\t// @[Monitor.scala:16:26]\n reg in_flight_4;\t// @[Monitor.scala:16:26]\n reg in_flight_5;\t// @[Monitor.scala:16:26]\n reg in_flight_6;\t// @[Monitor.scala:16:26]\n reg in_flight_7;\t// @[Monitor.scala:16:26]\n reg in_flight_8;\t// @[Monitor.scala:16:26]\n reg in_flight_9;\t// @[Monitor.scala:16:26]\n wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h2;\t// @[Monitor.scala:21:46]\n wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h6;\t// @[Monitor.scala:21:46]"}}},{"rowIdx":32173,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_10 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} \n\n\n regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) \n reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock \n inst q of Queue2_EgressFlit_10 \n connect q.clock, clock\n\n connect q.reset, reset\n\n connect q.io.enq.valid, io.in[0].valid \n connect q.io.enq.bits.head, io.in[0].bits.head \n connect q.io.enq.bits.tail, io.in[0].bits.tail \n node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) \n node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) \n node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) \n node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) \n node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) \n node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) \n node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) \n node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) \n node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) \n node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28) \n node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31) \n node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34) \n node _q_io_enq_bits_ingress_id_T_36 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_37 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_38 = and(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37) \n node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h14), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h10), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0ha), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h0), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0hc), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h16), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h12), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h4), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h6), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_48 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0he), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_49 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0h18), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_50 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0h8), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_51 = mux(_q_io_enq_bits_ingress_id_T_38, UInt<5>(0h2), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_39, _q_io_enq_bits_ingress_id_T_40) \n node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_41) \n node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_42) \n node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_43) \n node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_44) \n node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_45) \n node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_46) \n node _q_io_enq_bits_ingress_id_T_59 = or(_q_io_enq_bits_ingress_id_T_58, _q_io_enq_bits_ingress_id_T_47) \n node _q_io_enq_bits_ingress_id_T_60 = or(_q_io_enq_bits_ingress_id_T_59, _q_io_enq_bits_ingress_id_T_48) \n node _q_io_enq_bits_ingress_id_T_61 = or(_q_io_enq_bits_ingress_id_T_60, _q_io_enq_bits_ingress_id_T_49) \n node _q_io_enq_bits_ingress_id_T_62 = or(_q_io_enq_bits_ingress_id_T_61, _q_io_enq_bits_ingress_id_T_50) \n node _q_io_enq_bits_ingress_id_T_63 = or(_q_io_enq_bits_ingress_id_T_62, _q_io_enq_bits_ingress_id_T_51) \n wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> \n connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_63 \n connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE \n connect q.io.enq.bits.payload, io.in[0].bits.payload \n connect io.out.bits, q.io.deq.bits \n connect io.out.valid, q.io.deq.valid \n connect q.io.deq.ready, io.out.ready \n node _T = eq(q.io.enq.ready, UInt<1>(0h0)) \n node _T_1 = and(q.io.enq.valid, _T) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n node _T_3 = asUInt(reset) \n node _T_4 = eq(_T_3, UInt<1>(0h0)) \n when _T_4 : \n node _T_5 = eq(_T_2, UInt<1>(0h0)) \n when _T_5 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\\n\") : printf \n assert(clock, _T_2, UInt<1>(0h1), \"\") : assert \n node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) \n connect io.credit_available[0], _io_credit_available_0_T \n node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) \n connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T \n connect io.channel_status[0].flow, flow \n node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) \n when _T_6 : \n connect channel_empty, UInt<1>(0h1) \n when io.allocs[0].alloc : \n connect channel_empty, UInt<1>(0h0) \n connect flow, io.allocs[0].flow"},"response":{"kind":"string","value":"module EgressUnit_10(\t// @[EgressUnit.scala:12:7]\n input clock,\t// @[EgressUnit.scala:12:7]\n input reset,\t// @[EgressUnit.scala:12:7]\n input io_in_0_valid,\t// @[EgressUnit.scala:18:14]\n input io_in_0_bits_head,\t// @[EgressUnit.scala:18:14]\n input io_in_0_bits_tail,\t// @[EgressUnit.scala:18:14]\n input [144:0] io_in_0_bits_payload,\t// @[EgressUnit.scala:18:14]\n input [3:0] io_in_0_bits_flow_ingress_node,\t// @[EgressUnit.scala:18:14]\n input [2:0] io_in_0_bits_flow_ingress_node_id,\t// @[EgressUnit.scala:18:14]\n output io_credit_available_0,\t// @[EgressUnit.scala:18:14]\n output io_channel_status_0_occupied,\t// @[EgressUnit.scala:18:14]\n input io_allocs_0_alloc,\t// @[EgressUnit.scala:18:14]\n input io_credit_alloc_0_alloc,\t// @[EgressUnit.scala:18:14]\n input io_credit_alloc_0_tail,\t// @[EgressUnit.scala:18:14]\n input io_out_ready,\t// @[EgressUnit.scala:18:14]\n output io_out_valid,\t// @[EgressUnit.scala:18:14]\n output io_out_bits_head,\t// @[EgressUnit.scala:18:14]\n output io_out_bits_tail,\t// @[EgressUnit.scala:18:14]\n output [144:0] io_out_bits_payload\t// @[EgressUnit.scala:18:14]\n);\n\n wire _q_io_enq_ready;\t// @[EgressUnit.scala:22:17]\n wire [1:0] _q_io_count;\t// @[EgressUnit.scala:22:17]\n reg channel_empty;\t// @[EgressUnit.scala:20:30]\n wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 3'h0;\t// @[EgressUnit.scala:32:27]"}}},{"rowIdx":32174,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_21 : \n input clock : Clock \n input reset : Reset \n output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1]}, credit_alloc : { `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[4]}, switch_sel : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} \n\n\n inst arbs_0 of SwitchArbiter_70 \n connect arbs_0.clock, clock\n\n connect arbs_0.reset, reset\n\n inst arbs_1 of SwitchArbiter_71 \n connect arbs_1.clock, clock\n\n connect arbs_1.reset, reset\n\n inst arbs_2 of SwitchArbiter_72 \n connect arbs_2.clock, clock\n\n connect arbs_2.reset, reset\n\n connect arbs_0.io.out[0].ready, UInt<1>(0h1) \n connect arbs_1.io.out[0].ready, UInt<1>(0h1) \n connect arbs_2.io.out[0].ready, UInt<1>(0h1) \n wire fires : UInt<1>[3] \n node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) \n node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2]) \n node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3]) \n node _arbs_0_io_in_0_valid_T_3 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_2) \n connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_3 \n connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail \n connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] \n connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] \n connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] \n connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] \n connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] \n connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] \n node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) \n connect fires[0], _fires_0_T \n node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) \n connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T \n connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail \n connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] \n connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] \n connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] \n connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] \n connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] \n connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] \n node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) \n connect fires[1], _fires_1_T \n node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0]) \n connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T \n connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail \n connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] \n connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] \n connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] \n connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] \n connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] \n connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] \n node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid) \n connect fires[2], _fires_2_T \n node _io_req_0_0_ready_T = or(fires[0], fires[1]) \n node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2]) \n connect io.req.`0`[0].ready, _io_req_0_0_ready_T_1 \n wire fires_1 : UInt<1>[3] \n node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) \n node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2]) \n node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3]) \n node _arbs_0_io_in_1_valid_T_3 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_2) \n connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_3 \n connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail \n connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] \n connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] \n connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] \n connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] \n connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] \n connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] \n node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) \n connect fires_1[0], _fires_0_T_1 \n node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) \n connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T \n connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail \n connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] \n connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] \n connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] \n connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] \n connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] \n connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] \n node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) \n connect fires_1[1], _fires_1_T_1 \n node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0]) \n connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T \n connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail \n connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] \n connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] \n connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] \n connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] \n connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] \n connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] \n node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid) \n connect fires_1[2], _fires_2_T_1 \n node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) \n node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2]) \n connect io.req.`1`[0].ready, _io_req_1_0_ready_T_1 \n wire fires_2 : UInt<1>[3] \n node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) \n node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2]) \n node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3]) \n node _arbs_0_io_in_2_valid_T_3 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_2) \n connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_3 \n connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail \n connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] \n connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] \n connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] \n connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] \n connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] \n connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] \n node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) \n connect fires_2[0], _fires_0_T_2 \n node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) \n connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T \n connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail \n connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] \n connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] \n connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] \n connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] \n connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] \n connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] \n node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) \n connect fires_2[1], _fires_1_T_2 \n node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0]) \n connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T \n connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail \n connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] \n connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] \n connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] \n connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] \n connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] \n connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] \n node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid) \n connect fires_2[2], _fires_2_T_2 \n node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) \n node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2]) \n connect io.req.`2`[0].ready, _io_req_2_0_ready_T_1 \n node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) \n node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) \n node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) \n connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 \n node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) \n node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) \n node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) \n connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 \n node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) \n node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) \n node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) \n connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 \n node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) \n node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) \n node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) \n connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 \n node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) \n node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) \n node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) \n connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 \n node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) \n node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) \n node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) \n connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 \n node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0) \n node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T) \n node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid) \n connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2 \n node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1) \n node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T) \n node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid) \n connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2 \n node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2) \n node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T) \n node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid) \n connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2 \n connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) \n connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) \n connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0) \n connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0) \n connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) \n connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0) \n connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) \n connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) \n connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0) \n connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0) \n connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) \n connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0) \n node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) \n when _T : \n connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) \n connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail \n node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) \n when _T_1 : \n connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) \n connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail \n node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2]) \n when _T_2 : \n connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1) \n connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail \n node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3]) \n when _T_3 : \n connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1) \n connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail \n node _T_4 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) \n when _T_4 : \n connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) \n connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail \n node _T_5 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0]) \n when _T_5 : \n connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1) \n connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail"},"response":{"kind":"string","value":"module SwitchAllocator_21(\t// @[SwitchAllocator.scala:64:7]\n input clock,\t// @[SwitchAllocator.scala:64:7]\n input reset,\t// @[SwitchAllocator.scala:64:7]\n output io_req_0_0_ready,\t// @[SwitchAllocator.scala:74:14]\n input io_req_0_0_valid,\t// @[SwitchAllocator.scala:74:14]\n input io_req_0_0_bits_vc_sel_2_0,\t// @[SwitchAllocator.scala:74:14]\n input io_req_0_0_bits_vc_sel_1_0,\t// @[SwitchAllocator.scala:74:14]\n input io_req_0_0_bits_vc_sel_0_0,\t// @[SwitchAllocator.scala:74:14]\n input io_req_0_0_bits_vc_sel_0_1,\t// @[SwitchAllocator.scala:74:14]\n input io_req_0_0_bits_tail,\t// @[SwitchAllocator.scala:74:14]\n output io_credit_alloc_2_0_alloc,\t// @[SwitchAllocator.scala:74:14]\n output io_credit_alloc_2_0_tail,\t// @[SwitchAllocator.scala:74:14]\n output io_credit_alloc_1_0_alloc,\t// @[SwitchAllocator.scala:74:14]\n output io_credit_alloc_1_0_tail,\t// @[SwitchAllocator.scala:74:14]\n output io_credit_alloc_0_0_alloc,\t// @[SwitchAllocator.scala:74:14]\n output io_credit_alloc_0_1_alloc,\t// @[SwitchAllocator.scala:74:14]\n output io_switch_sel_2_0_0_0,\t// @[SwitchAllocator.scala:74:14]\n output io_switch_sel_1_0_0_0,\t// @[SwitchAllocator.scala:74:14]\n output io_switch_sel_0_0_0_0\t// @[SwitchAllocator.scala:74:14]\n);\n\n wire _arbs_2_io_in_0_ready;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_2_io_out_0_valid;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_2_io_out_0_bits_vc_sel_2_0;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_2_io_out_0_bits_tail;\t// @[SwitchAllocator.scala:83:45]\n wire [2:0] _arbs_2_io_chosen_oh_0;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_1_io_in_0_ready;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_1_io_out_0_valid;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_1_io_out_0_bits_vc_sel_1_0;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_1_io_out_0_bits_tail;\t// @[SwitchAllocator.scala:83:45]\n wire [2:0] _arbs_1_io_chosen_oh_0;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_0_io_in_0_ready;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_0_io_out_0_valid;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_0_io_out_0_bits_vc_sel_0_0;\t// @[SwitchAllocator.scala:83:45]\n wire _arbs_0_io_out_0_bits_vc_sel_0_1;\t// @[SwitchAllocator.scala:83:45]\n wire [2:0] _arbs_0_io_chosen_oh_0;\t// @[SwitchAllocator.scala:83:45]\n wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_0 | io_req_0_0_bits_vc_sel_0_1);\t// @[SwitchAllocator.scala:95:{37,65}]\n wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0;\t// @[SwitchAllocator.scala:95:37]\n wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0;\t// @[SwitchAllocator.scala:95:37]\n wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0;\t// @[SwitchAllocator.scala:83:45, :120:33]\n wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0;\t// @[SwitchAllocator.scala:83:45, :120:33]\n SwitchArbiter_70 arbs_0 (\t// @[SwitchAllocator.scala:83:45]\n .clock (clock),\n .reset (reset),\n .io_in_0_ready (_arbs_0_io_in_0_ready),\n .io_in_0_valid (arbs_0_io_in_0_valid),\t// @[SwitchAllocator.scala:95:37]\n .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),\n .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),\n .io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),\n .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),\n .io_in_0_bits_tail (io_req_0_0_bits_tail),\n .io_out_0_valid (_arbs_0_io_out_0_valid),\n .io_out_0_bits_vc_sel_2_0 (/* unused */),\n .io_out_0_bits_vc_sel_1_0 (/* unused */),\n .io_out_0_bits_vc_sel_0_0 (_arbs_0_io_out_0_bits_vc_sel_0_0),\n .io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1),\n .io_out_0_bits_tail (/* unused */),\n .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0)\n );\t// @[SwitchAllocator.scala:83:45]\n SwitchArbiter_70 arbs_1 (\t// @[SwitchAllocator.scala:83:45]\n .clock (clock),\n .reset (reset),\n .io_in_0_ready (_arbs_1_io_in_0_ready),\n .io_in_0_valid (arbs_1_io_in_0_valid),\t// @[SwitchAllocator.scala:95:37]\n .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),\n .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),\n .io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),\n .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),\n .io_in_0_bits_tail (io_req_0_0_bits_tail),\n .io_out_0_valid (_arbs_1_io_out_0_valid),\n .io_out_0_bits_vc_sel_2_0 (/* unused */),\n .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0),\n .io_out_0_bits_vc_sel_0_0 (/* unused */),\n .io_out_0_bits_vc_sel_0_1 (/* unused */),\n .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail),\n .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0)\n );\t// @[SwitchAllocator.scala:83:45]\n SwitchArbiter_70 arbs_2 (\t// @[SwitchAllocator.scala:83:45]\n .clock (clock),\n .reset (reset),\n .io_in_0_ready (_arbs_2_io_in_0_ready),\n .io_in_0_valid (arbs_2_io_in_0_valid),\t// @[SwitchAllocator.scala:95:37]\n .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),\n .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),\n .io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),\n .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),\n .io_in_0_bits_tail (io_req_0_0_bits_tail),\n .io_out_0_valid (_arbs_2_io_out_0_valid),\n .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0),\n .io_out_0_bits_vc_sel_1_0 (/* unused */),\n .io_out_0_bits_vc_sel_0_0 (/* unused */),\n .io_out_0_bits_vc_sel_0_1 (/* unused */),\n .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail),\n .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0)\n );\t// @[SwitchAllocator.scala:83:45]\n assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid;\t// @[Decoupled.scala:51:35]\n assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0;\t// @[SwitchAllocator.scala:64:7, :120:33]\n assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail;\t// @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]\n assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0;\t// @[SwitchAllocator.scala:64:7, :120:33]\n assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail;\t// @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]\n assign io_credit_alloc_0_0_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_0;\t// @[SwitchAllocator.scala:64:7, :83:45, :120:33]\n assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1;\t// @[SwitchAllocator.scala:64:7, :83:45, :120:33]\n assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid;\t// @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]\n assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid;\t// @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]\n assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid;\t// @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]\nendmodule"}}},{"rowIdx":32175,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_96 : \n input clock : Clock \n input reset : AsyncReset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _sync_2_T = bits(io.d, 0, 0) \n connect sync_2, _sync_2_T \n connect sync_0, sync_1 \n connect sync_1, sync_2 \n connect io.q, sync_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_96(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":32176,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_12 : \n input clock : Clock \n input reset : Reset \n output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]} \n\n\n connect io.xcpt_if, UInt<1>(0h0) \n connect io.xcpt_ld, UInt<1>(0h0) \n connect io.xcpt_st, UInt<1>(0h0) \n connect io.debug_if, UInt<1>(0h0) \n connect io.debug_ld, UInt<1>(0h0) \n connect io.debug_st, UInt<1>(0h0)"},"response":{"kind":"string","value":"module BreakpointUnit_12(\t// @[Breakpoint.scala:79:7]\n input clock,\t// @[Breakpoint.scala:79:7]\n input reset,\t// @[Breakpoint.scala:79:7]\n input io_status_debug,\t// @[Breakpoint.scala:80:14]\n input io_status_cease,\t// @[Breakpoint.scala:80:14]\n input io_status_wfi,\t// @[Breakpoint.scala:80:14]\n input [1:0] io_status_dprv,\t// @[Breakpoint.scala:80:14]\n input io_status_dv,\t// @[Breakpoint.scala:80:14]\n input [1:0] io_status_prv,\t// @[Breakpoint.scala:80:14]\n input io_status_v,\t// @[Breakpoint.scala:80:14]\n input io_status_sd,\t// @[Breakpoint.scala:80:14]\n input io_status_mpv,\t// @[Breakpoint.scala:80:14]\n input io_status_gva,\t// @[Breakpoint.scala:80:14]\n input io_status_tsr,\t// @[Breakpoint.scala:80:14]\n input io_status_tw,\t// @[Breakpoint.scala:80:14]\n input io_status_tvm,\t// @[Breakpoint.scala:80:14]\n input io_status_mxr,\t// @[Breakpoint.scala:80:14]\n input io_status_sum,\t// @[Breakpoint.scala:80:14]\n input io_status_mprv,\t// @[Breakpoint.scala:80:14]\n input [1:0] io_status_fs,\t// @[Breakpoint.scala:80:14]\n input [1:0] io_status_mpp,\t// @[Breakpoint.scala:80:14]\n input io_status_spp,\t// @[Breakpoint.scala:80:14]\n input io_status_mpie,\t// @[Breakpoint.scala:80:14]\n input io_status_spie,\t// @[Breakpoint.scala:80:14]\n input io_status_mie,\t// @[Breakpoint.scala:80:14]\n input io_status_sie,\t// @[Breakpoint.scala:80:14]\n input [38:0] io_pc\t// @[Breakpoint.scala:80:14]\n);\n\n wire io_status_debug_0 = io_status_debug;\t// @[Breakpoint.scala:79:7]\n wire io_status_cease_0 = io_status_cease;\t// @[Breakpoint.scala:79:7]\n wire io_status_wfi_0 = io_status_wfi;\t// @[Breakpoint.scala:79:7]\n wire [1:0] io_status_dprv_0 = io_status_dprv;\t// @[Breakpoint.scala:79:7]\n wire io_status_dv_0 = io_status_dv;\t// @[Breakpoint.scala:79:7]\n wire [1:0] io_status_prv_0 = io_status_prv;\t// @[Breakpoint.scala:79:7]\n wire io_status_v_0 = io_status_v;\t// @[Breakpoint.scala:79:7]\n wire io_status_sd_0 = io_status_sd;\t// @[Breakpoint.scala:79:7]\n wire io_status_mpv_0 = io_status_mpv;\t// @[Breakpoint.scala:79:7]\n wire io_status_gva_0 = io_status_gva;\t// @[Breakpoint.scala:79:7]\n wire io_status_tsr_0 = io_status_tsr;\t// @[Breakpoint.scala:79:7]\n wire io_status_tw_0 = io_status_tw;\t// @[Breakpoint.scala:79:7]\n wire io_status_tvm_0 = io_status_tvm;\t// @[Breakpoint.scala:79:7]\n wire io_status_mxr_0 = io_status_mxr;\t// @[Breakpoint.scala:79:7]\n wire io_status_sum_0 = io_status_sum;\t// @[Breakpoint.scala:79:7]\n wire io_status_mprv_0 = io_status_mprv;\t// @[Breakpoint.scala:79:7]\n wire [1:0] io_status_fs_0 = io_status_fs;\t// @[Breakpoint.scala:79:7]\n wire [1:0] io_status_mpp_0 = io_status_mpp;\t// @[Breakpoint.scala:79:7]\n wire io_status_spp_0 = io_status_spp;\t// @[Breakpoint.scala:79:7]\n wire io_status_mpie_0 = io_status_mpie;\t// @[Breakpoint.scala:79:7]\n wire io_status_spie_0 = io_status_spie;\t// @[Breakpoint.scala:79:7]\n wire io_status_mie_0 = io_status_mie;\t// @[Breakpoint.scala:79:7]\n wire io_status_sie_0 = io_status_sie;\t// @[Breakpoint.scala:79:7]\n wire [38:0] io_pc_0 = io_pc;\t// @[Breakpoint.scala:79:7]\n wire [38:0] io_ea = 39'h0;\t// @[Breakpoint.scala:79:7, :80:14]\n wire [1:0] io_status_sxl = 2'h2;\t// @[Breakpoint.scala:79:7, :80:14]\n wire [1:0] io_status_uxl = 2'h2;\t// @[Breakpoint.scala:79:7, :80:14]\n wire [1:0] io_status_xs = 2'h0;\t// @[Breakpoint.scala:79:7, :80:14]\n wire [1:0] io_status_vs = 2'h0;\t// @[Breakpoint.scala:79:7, :80:14]\n wire [7:0] io_status_zero1 = 8'h0;\t// @[Breakpoint.scala:79:7, :80:14]\n wire io_status_mbe = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_status_sbe = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_status_sd_rv32 = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_status_ube = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_status_upie = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_status_hie = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_status_uie = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_xcpt_if = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_xcpt_ld = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_xcpt_st = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_debug_if = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_debug_ld = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire io_debug_st = 1'h0;\t// @[Breakpoint.scala:79:7]\n wire [22:0] io_status_zero2 = 23'h0;\t// @[Breakpoint.scala:79:7, :80:14]\n wire [31:0] io_status_isa = 32'h14112D;\t// @[Breakpoint.scala:79:7, :80:14]\nendmodule"}}},{"rowIdx":32177,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_54 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T \n node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_lo = cat(mask_acc_1, mask_acc) \n node mask_hi = cat(mask_acc_3, mask_acc_2) \n node mask = cat(mask_hi, mask_lo) \n node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_7 = cvt(_T_6) \n node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) \n node _T_9 = asSInt(_T_8) \n node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) \n node _T_11 = or(_T_5, _T_10) \n node _T_12 = asUInt(reset) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n when _T_13 : \n node _T_14 = eq(_T_11, UInt<1>(0h0)) \n when _T_14 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_11, UInt<1>(0h1), \"\") : assert_1 \n node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_15 : \n node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_17 = and(UInt<1>(0h0), _T_16) \n node _T_18 = or(UInt<1>(0h0), _T_17) \n node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_21 = cvt(_T_20) \n node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) \n node _T_23 = asSInt(_T_22) \n node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) \n node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_26 = cvt(_T_25) \n node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) \n node _T_28 = asSInt(_T_27) \n node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) \n node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_31 = cvt(_T_30) \n node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) \n node _T_33 = asSInt(_T_32) \n node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) \n node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_36 = cvt(_T_35) \n node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) \n node _T_38 = asSInt(_T_37) \n node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) \n node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_41 = cvt(_T_40) \n node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) \n node _T_43 = asSInt(_T_42) \n node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) \n node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_46 = cvt(_T_45) \n node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) \n node _T_48 = asSInt(_T_47) \n node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) \n node _T_50 = or(_T_24, _T_29) \n node _T_51 = or(_T_50, _T_34) \n node _T_52 = or(_T_51, _T_39) \n node _T_53 = or(_T_52, _T_44) \n node _T_54 = or(_T_53, _T_49) \n node _T_55 = and(_T_19, _T_54) \n node _T_56 = or(UInt<1>(0h0), _T_55) \n node _T_57 = and(_T_18, _T_56) \n node _T_58 = asUInt(reset) \n node _T_59 = eq(_T_58, UInt<1>(0h0)) \n when _T_59 : \n node _T_60 = eq(_T_57, UInt<1>(0h0)) \n when _T_60 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_57, UInt<1>(0h1), \"\") : assert_2 \n node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_63 = and(_T_61, _T_62) \n node _T_64 = or(UInt<1>(0h0), _T_63) \n node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_66 = cvt(_T_65) \n node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) \n node _T_68 = asSInt(_T_67) \n node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) \n node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_71 = cvt(_T_70) \n node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) \n node _T_73 = asSInt(_T_72) \n node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) \n node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_76 = cvt(_T_75) \n node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) \n node _T_78 = asSInt(_T_77) \n node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) \n node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_81 = cvt(_T_80) \n node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) \n node _T_83 = asSInt(_T_82) \n node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) \n node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_86 = cvt(_T_85) \n node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) \n node _T_88 = asSInt(_T_87) \n node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) \n node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_91 = cvt(_T_90) \n node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) \n node _T_93 = asSInt(_T_92) \n node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) \n node _T_95 = or(_T_69, _T_74) \n node _T_96 = or(_T_95, _T_79) \n node _T_97 = or(_T_96, _T_84) \n node _T_98 = or(_T_97, _T_89) \n node _T_99 = or(_T_98, _T_94) \n node _T_100 = and(_T_64, _T_99) \n node _T_101 = or(UInt<1>(0h0), _T_100) \n node _T_102 = and(UInt<1>(0h0), _T_101) \n node _T_103 = asUInt(reset) \n node _T_104 = eq(_T_103, UInt<1>(0h0)) \n when _T_104 : \n node _T_105 = eq(_T_102, UInt<1>(0h0)) \n when _T_105 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_102, UInt<1>(0h1), \"\") : assert_3 \n node _T_106 = asUInt(reset) \n node _T_107 = eq(_T_106, UInt<1>(0h0)) \n when _T_107 : \n node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_108 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_110 = asUInt(reset) \n node _T_111 = eq(_T_110, UInt<1>(0h0)) \n when _T_111 : \n node _T_112 = eq(_T_109, UInt<1>(0h0)) \n when _T_112 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_109, UInt<1>(0h1), \"\") : assert_5 \n node _T_113 = asUInt(reset) \n node _T_114 = eq(_T_113, UInt<1>(0h0)) \n when _T_114 : \n node _T_115 = eq(is_aligned, UInt<1>(0h0)) \n when _T_115 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_117 = asUInt(reset) \n node _T_118 = eq(_T_117, UInt<1>(0h0)) \n when _T_118 : \n node _T_119 = eq(_T_116, UInt<1>(0h0)) \n when _T_119 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_116, UInt<1>(0h1), \"\") : assert_7 \n node _T_120 = not(io.in.a.bits.mask) \n node _T_121 = eq(_T_120, UInt<1>(0h0)) \n node _T_122 = asUInt(reset) \n node _T_123 = eq(_T_122, UInt<1>(0h0)) \n when _T_123 : \n node _T_124 = eq(_T_121, UInt<1>(0h0)) \n when _T_124 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_121, UInt<1>(0h1), \"\") : assert_8 \n node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_126 = asUInt(reset) \n node _T_127 = eq(_T_126, UInt<1>(0h0)) \n when _T_127 : \n node _T_128 = eq(_T_125, UInt<1>(0h0)) \n when _T_128 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_125, UInt<1>(0h1), \"\") : assert_9 \n node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_129 : \n node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_131 = and(UInt<1>(0h0), _T_130) \n node _T_132 = or(UInt<1>(0h0), _T_131) \n node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_135 = cvt(_T_134) \n node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) \n node _T_137 = asSInt(_T_136) \n node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) \n node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_140 = cvt(_T_139) \n node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) \n node _T_142 = asSInt(_T_141) \n node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) \n node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_145 = cvt(_T_144) \n node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) \n node _T_147 = asSInt(_T_146) \n node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) \n node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_150 = cvt(_T_149) \n node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) \n node _T_152 = asSInt(_T_151) \n node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) \n node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_155 = cvt(_T_154) \n node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) \n node _T_157 = asSInt(_T_156) \n node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) \n node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_160 = cvt(_T_159) \n node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) \n node _T_162 = asSInt(_T_161) \n node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) \n node _T_164 = or(_T_138, _T_143) \n node _T_165 = or(_T_164, _T_148) \n node _T_166 = or(_T_165, _T_153) \n node _T_167 = or(_T_166, _T_158) \n node _T_168 = or(_T_167, _T_163) \n node _T_169 = and(_T_133, _T_168) \n node _T_170 = or(UInt<1>(0h0), _T_169) \n node _T_171 = and(_T_132, _T_170) \n node _T_172 = asUInt(reset) \n node _T_173 = eq(_T_172, UInt<1>(0h0)) \n when _T_173 : \n node _T_174 = eq(_T_171, UInt<1>(0h0)) \n when _T_174 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_171, UInt<1>(0h1), \"\") : assert_10 \n node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_177 = and(_T_175, _T_176) \n node _T_178 = or(UInt<1>(0h0), _T_177) \n node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_180 = cvt(_T_179) \n node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) \n node _T_182 = asSInt(_T_181) \n node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) \n node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_185 = cvt(_T_184) \n node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) \n node _T_187 = asSInt(_T_186) \n node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) \n node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_190 = cvt(_T_189) \n node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) \n node _T_192 = asSInt(_T_191) \n node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) \n node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_195 = cvt(_T_194) \n node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) \n node _T_197 = asSInt(_T_196) \n node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) \n node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_200 = cvt(_T_199) \n node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) \n node _T_202 = asSInt(_T_201) \n node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) \n node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_205 = cvt(_T_204) \n node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) \n node _T_207 = asSInt(_T_206) \n node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) \n node _T_209 = or(_T_183, _T_188) \n node _T_210 = or(_T_209, _T_193) \n node _T_211 = or(_T_210, _T_198) \n node _T_212 = or(_T_211, _T_203) \n node _T_213 = or(_T_212, _T_208) \n node _T_214 = and(_T_178, _T_213) \n node _T_215 = or(UInt<1>(0h0), _T_214) \n node _T_216 = and(UInt<1>(0h0), _T_215) \n node _T_217 = asUInt(reset) \n node _T_218 = eq(_T_217, UInt<1>(0h0)) \n when _T_218 : \n node _T_219 = eq(_T_216, UInt<1>(0h0)) \n when _T_219 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_216, UInt<1>(0h1), \"\") : assert_11 \n node _T_220 = asUInt(reset) \n node _T_221 = eq(_T_220, UInt<1>(0h0)) \n when _T_221 : \n node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_222 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_224 = asUInt(reset) \n node _T_225 = eq(_T_224, UInt<1>(0h0)) \n when _T_225 : \n node _T_226 = eq(_T_223, UInt<1>(0h0)) \n when _T_226 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_223, UInt<1>(0h1), \"\") : assert_13 \n node _T_227 = asUInt(reset) \n node _T_228 = eq(_T_227, UInt<1>(0h0)) \n when _T_228 : \n node _T_229 = eq(is_aligned, UInt<1>(0h0)) \n when _T_229 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_231 = asUInt(reset) \n node _T_232 = eq(_T_231, UInt<1>(0h0)) \n when _T_232 : \n node _T_233 = eq(_T_230, UInt<1>(0h0)) \n when _T_233 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_230, UInt<1>(0h1), \"\") : assert_15 \n node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_235 = asUInt(reset) \n node _T_236 = eq(_T_235, UInt<1>(0h0)) \n when _T_236 : \n node _T_237 = eq(_T_234, UInt<1>(0h0)) \n when _T_237 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_234, UInt<1>(0h1), \"\") : assert_16 \n node _T_238 = not(io.in.a.bits.mask) \n node _T_239 = eq(_T_238, UInt<1>(0h0)) \n node _T_240 = asUInt(reset) \n node _T_241 = eq(_T_240, UInt<1>(0h0)) \n when _T_241 : \n node _T_242 = eq(_T_239, UInt<1>(0h0)) \n when _T_242 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_239, UInt<1>(0h1), \"\") : assert_17 \n node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_244 = asUInt(reset) \n node _T_245 = eq(_T_244, UInt<1>(0h0)) \n when _T_245 : \n node _T_246 = eq(_T_243, UInt<1>(0h0)) \n when _T_246 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_243, UInt<1>(0h1), \"\") : assert_18 \n node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_247 : \n node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) \n node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_250 = and(_T_248, _T_249) \n node _T_251 = or(UInt<1>(0h0), _T_250) \n node _T_252 = asUInt(reset) \n node _T_253 = eq(_T_252, UInt<1>(0h0)) \n when _T_253 : \n node _T_254 = eq(_T_251, UInt<1>(0h0)) \n when _T_254 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_251, UInt<1>(0h1), \"\") : assert_19 \n node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_257 = and(_T_255, _T_256) \n node _T_258 = or(UInt<1>(0h0), _T_257) \n node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_260 = cvt(_T_259) \n node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) \n node _T_262 = asSInt(_T_261) \n node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) \n node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_265 = cvt(_T_264) \n node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) \n node _T_267 = asSInt(_T_266) \n node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) \n node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_270 = cvt(_T_269) \n node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) \n node _T_272 = asSInt(_T_271) \n node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) \n node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_275 = cvt(_T_274) \n node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) \n node _T_277 = asSInt(_T_276) \n node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) \n node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_280 = cvt(_T_279) \n node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) \n node _T_282 = asSInt(_T_281) \n node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) \n node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_285 = cvt(_T_284) \n node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) \n node _T_287 = asSInt(_T_286) \n node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) \n node _T_289 = or(_T_263, _T_268) \n node _T_290 = or(_T_289, _T_273) \n node _T_291 = or(_T_290, _T_278) \n node _T_292 = or(_T_291, _T_283) \n node _T_293 = or(_T_292, _T_288) \n node _T_294 = and(_T_258, _T_293) \n node _T_295 = or(UInt<1>(0h0), _T_294) \n node _T_296 = asUInt(reset) \n node _T_297 = eq(_T_296, UInt<1>(0h0)) \n when _T_297 : \n node _T_298 = eq(_T_295, UInt<1>(0h0)) \n when _T_298 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_295, UInt<1>(0h1), \"\") : assert_20 \n node _T_299 = asUInt(reset) \n node _T_300 = eq(_T_299, UInt<1>(0h0)) \n when _T_300 : \n node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_301 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_302 = asUInt(reset) \n node _T_303 = eq(_T_302, UInt<1>(0h0)) \n when _T_303 : \n node _T_304 = eq(is_aligned, UInt<1>(0h0)) \n when _T_304 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_306 = asUInt(reset) \n node _T_307 = eq(_T_306, UInt<1>(0h0)) \n when _T_307 : \n node _T_308 = eq(_T_305, UInt<1>(0h0)) \n when _T_308 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_305, UInt<1>(0h1), \"\") : assert_23 \n node _T_309 = eq(io.in.a.bits.mask, mask) \n node _T_310 = asUInt(reset) \n node _T_311 = eq(_T_310, UInt<1>(0h0)) \n when _T_311 : \n node _T_312 = eq(_T_309, UInt<1>(0h0)) \n when _T_312 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_309, UInt<1>(0h1), \"\") : assert_24 \n node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_314 = asUInt(reset) \n node _T_315 = eq(_T_314, UInt<1>(0h0)) \n when _T_315 : \n node _T_316 = eq(_T_313, UInt<1>(0h0)) \n when _T_316 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_313, UInt<1>(0h1), \"\") : assert_25 \n node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_317 : \n node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) \n node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_320 = and(_T_318, _T_319) \n node _T_321 = or(UInt<1>(0h0), _T_320) \n node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_324 = and(_T_322, _T_323) \n node _T_325 = or(UInt<1>(0h0), _T_324) \n node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_327 = cvt(_T_326) \n node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) \n node _T_329 = asSInt(_T_328) \n node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) \n node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_332 = cvt(_T_331) \n node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) \n node _T_334 = asSInt(_T_333) \n node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) \n node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_337 = cvt(_T_336) \n node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) \n node _T_339 = asSInt(_T_338) \n node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) \n node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_342 = cvt(_T_341) \n node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) \n node _T_344 = asSInt(_T_343) \n node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) \n node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_347 = cvt(_T_346) \n node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) \n node _T_349 = asSInt(_T_348) \n node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) \n node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_352 = cvt(_T_351) \n node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) \n node _T_354 = asSInt(_T_353) \n node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) \n node _T_356 = or(_T_330, _T_335) \n node _T_357 = or(_T_356, _T_340) \n node _T_358 = or(_T_357, _T_345) \n node _T_359 = or(_T_358, _T_350) \n node _T_360 = or(_T_359, _T_355) \n node _T_361 = and(_T_325, _T_360) \n node _T_362 = or(UInt<1>(0h0), _T_361) \n node _T_363 = and(_T_321, _T_362) \n node _T_364 = asUInt(reset) \n node _T_365 = eq(_T_364, UInt<1>(0h0)) \n when _T_365 : \n node _T_366 = eq(_T_363, UInt<1>(0h0)) \n when _T_366 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_363, UInt<1>(0h1), \"\") : assert_26 \n node _T_367 = asUInt(reset) \n node _T_368 = eq(_T_367, UInt<1>(0h0)) \n when _T_368 : \n node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_369 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_370 = asUInt(reset) \n node _T_371 = eq(_T_370, UInt<1>(0h0)) \n when _T_371 : \n node _T_372 = eq(is_aligned, UInt<1>(0h0)) \n when _T_372 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_374 = asUInt(reset) \n node _T_375 = eq(_T_374, UInt<1>(0h0)) \n when _T_375 : \n node _T_376 = eq(_T_373, UInt<1>(0h0)) \n when _T_376 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_373, UInt<1>(0h1), \"\") : assert_29 \n node _T_377 = eq(io.in.a.bits.mask, mask) \n node _T_378 = asUInt(reset) \n node _T_379 = eq(_T_378, UInt<1>(0h0)) \n when _T_379 : \n node _T_380 = eq(_T_377, UInt<1>(0h0)) \n when _T_380 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_377, UInt<1>(0h1), \"\") : assert_30 \n node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_381 : \n node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_383 = and(UInt<1>(0h0), _T_382) \n node _T_384 = or(UInt<1>(0h0), _T_383) \n node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_387 = and(_T_385, _T_386) \n node _T_388 = or(UInt<1>(0h0), _T_387) \n node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_390 = cvt(_T_389) \n node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) \n node _T_392 = asSInt(_T_391) \n node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) \n node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_395 = cvt(_T_394) \n node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) \n node _T_397 = asSInt(_T_396) \n node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) \n node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_400 = cvt(_T_399) \n node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) \n node _T_402 = asSInt(_T_401) \n node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) \n node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_405 = cvt(_T_404) \n node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) \n node _T_407 = asSInt(_T_406) \n node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) \n node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_410 = cvt(_T_409) \n node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) \n node _T_412 = asSInt(_T_411) \n node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) \n node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_415 = cvt(_T_414) \n node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) \n node _T_417 = asSInt(_T_416) \n node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) \n node _T_419 = or(_T_393, _T_398) \n node _T_420 = or(_T_419, _T_403) \n node _T_421 = or(_T_420, _T_408) \n node _T_422 = or(_T_421, _T_413) \n node _T_423 = or(_T_422, _T_418) \n node _T_424 = and(_T_388, _T_423) \n node _T_425 = or(UInt<1>(0h0), _T_424) \n node _T_426 = and(_T_384, _T_425) \n node _T_427 = asUInt(reset) \n node _T_428 = eq(_T_427, UInt<1>(0h0)) \n when _T_428 : \n node _T_429 = eq(_T_426, UInt<1>(0h0)) \n when _T_429 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_426, UInt<1>(0h1), \"\") : assert_31 \n node _T_430 = asUInt(reset) \n node _T_431 = eq(_T_430, UInt<1>(0h0)) \n when _T_431 : \n node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_432 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_433 = asUInt(reset) \n node _T_434 = eq(_T_433, UInt<1>(0h0)) \n when _T_434 : \n node _T_435 = eq(is_aligned, UInt<1>(0h0)) \n when _T_435 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_437 = asUInt(reset) \n node _T_438 = eq(_T_437, UInt<1>(0h0)) \n when _T_438 : \n node _T_439 = eq(_T_436, UInt<1>(0h0)) \n when _T_439 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_436, UInt<1>(0h1), \"\") : assert_34 \n node _T_440 = not(mask) \n node _T_441 = and(io.in.a.bits.mask, _T_440) \n node _T_442 = eq(_T_441, UInt<1>(0h0)) \n node _T_443 = asUInt(reset) \n node _T_444 = eq(_T_443, UInt<1>(0h0)) \n when _T_444 : \n node _T_445 = eq(_T_442, UInt<1>(0h0)) \n when _T_445 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_442, UInt<1>(0h1), \"\") : assert_35 \n node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_446 : \n node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_448 = and(UInt<1>(0h0), _T_447) \n node _T_449 = or(UInt<1>(0h0), _T_448) \n node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_452 = cvt(_T_451) \n node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) \n node _T_454 = asSInt(_T_453) \n node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) \n node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_457 = cvt(_T_456) \n node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) \n node _T_459 = asSInt(_T_458) \n node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) \n node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_462 = cvt(_T_461) \n node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) \n node _T_464 = asSInt(_T_463) \n node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) \n node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_467 = cvt(_T_466) \n node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) \n node _T_469 = asSInt(_T_468) \n node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) \n node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_472 = cvt(_T_471) \n node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) \n node _T_474 = asSInt(_T_473) \n node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) \n node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_477 = cvt(_T_476) \n node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) \n node _T_479 = asSInt(_T_478) \n node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) \n node _T_481 = or(_T_455, _T_460) \n node _T_482 = or(_T_481, _T_465) \n node _T_483 = or(_T_482, _T_470) \n node _T_484 = or(_T_483, _T_475) \n node _T_485 = or(_T_484, _T_480) \n node _T_486 = and(_T_450, _T_485) \n node _T_487 = or(UInt<1>(0h0), _T_486) \n node _T_488 = and(_T_449, _T_487) \n node _T_489 = asUInt(reset) \n node _T_490 = eq(_T_489, UInt<1>(0h0)) \n when _T_490 : \n node _T_491 = eq(_T_488, UInt<1>(0h0)) \n when _T_491 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_488, UInt<1>(0h1), \"\") : assert_36 \n node _T_492 = asUInt(reset) \n node _T_493 = eq(_T_492, UInt<1>(0h0)) \n when _T_493 : \n node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_494 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_495 = asUInt(reset) \n node _T_496 = eq(_T_495, UInt<1>(0h0)) \n when _T_496 : \n node _T_497 = eq(is_aligned, UInt<1>(0h0)) \n when _T_497 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_499 = asUInt(reset) \n node _T_500 = eq(_T_499, UInt<1>(0h0)) \n when _T_500 : \n node _T_501 = eq(_T_498, UInt<1>(0h0)) \n when _T_501 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_498, UInt<1>(0h1), \"\") : assert_39 \n node _T_502 = eq(io.in.a.bits.mask, mask) \n node _T_503 = asUInt(reset) \n node _T_504 = eq(_T_503, UInt<1>(0h0)) \n when _T_504 : \n node _T_505 = eq(_T_502, UInt<1>(0h0)) \n when _T_505 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_502, UInt<1>(0h1), \"\") : assert_40 \n node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_506 : \n node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_508 = and(UInt<1>(0h0), _T_507) \n node _T_509 = or(UInt<1>(0h0), _T_508) \n node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_512 = cvt(_T_511) \n node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) \n node _T_514 = asSInt(_T_513) \n node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) \n node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_517 = cvt(_T_516) \n node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) \n node _T_519 = asSInt(_T_518) \n node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) \n node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_522 = cvt(_T_521) \n node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) \n node _T_524 = asSInt(_T_523) \n node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) \n node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_527 = cvt(_T_526) \n node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) \n node _T_529 = asSInt(_T_528) \n node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) \n node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_532 = cvt(_T_531) \n node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) \n node _T_534 = asSInt(_T_533) \n node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) \n node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_537 = cvt(_T_536) \n node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) \n node _T_539 = asSInt(_T_538) \n node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) \n node _T_541 = or(_T_515, _T_520) \n node _T_542 = or(_T_541, _T_525) \n node _T_543 = or(_T_542, _T_530) \n node _T_544 = or(_T_543, _T_535) \n node _T_545 = or(_T_544, _T_540) \n node _T_546 = and(_T_510, _T_545) \n node _T_547 = or(UInt<1>(0h0), _T_546) \n node _T_548 = and(_T_509, _T_547) \n node _T_549 = asUInt(reset) \n node _T_550 = eq(_T_549, UInt<1>(0h0)) \n when _T_550 : \n node _T_551 = eq(_T_548, UInt<1>(0h0)) \n when _T_551 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_548, UInt<1>(0h1), \"\") : assert_41 \n node _T_552 = asUInt(reset) \n node _T_553 = eq(_T_552, UInt<1>(0h0)) \n when _T_553 : \n node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_554 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_555 = asUInt(reset) \n node _T_556 = eq(_T_555, UInt<1>(0h0)) \n when _T_556 : \n node _T_557 = eq(is_aligned, UInt<1>(0h0)) \n when _T_557 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_559 = asUInt(reset) \n node _T_560 = eq(_T_559, UInt<1>(0h0)) \n when _T_560 : \n node _T_561 = eq(_T_558, UInt<1>(0h0)) \n when _T_561 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_558, UInt<1>(0h1), \"\") : assert_44 \n node _T_562 = eq(io.in.a.bits.mask, mask) \n node _T_563 = asUInt(reset) \n node _T_564 = eq(_T_563, UInt<1>(0h0)) \n when _T_564 : \n node _T_565 = eq(_T_562, UInt<1>(0h0)) \n when _T_565 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_562, UInt<1>(0h1), \"\") : assert_45 \n node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_566 : \n node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_568 = and(UInt<1>(0h0), _T_567) \n node _T_569 = or(UInt<1>(0h0), _T_568) \n node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_572 = cvt(_T_571) \n node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) \n node _T_574 = asSInt(_T_573) \n node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) \n node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) \n node _T_577 = cvt(_T_576) \n node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) \n node _T_579 = asSInt(_T_578) \n node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) \n node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) \n node _T_582 = cvt(_T_581) \n node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) \n node _T_584 = asSInt(_T_583) \n node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) \n node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) \n node _T_587 = cvt(_T_586) \n node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) \n node _T_589 = asSInt(_T_588) \n node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) \n node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) \n node _T_592 = cvt(_T_591) \n node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) \n node _T_594 = asSInt(_T_593) \n node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) \n node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) \n node _T_597 = cvt(_T_596) \n node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) \n node _T_599 = asSInt(_T_598) \n node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) \n node _T_601 = or(_T_575, _T_580) \n node _T_602 = or(_T_601, _T_585) \n node _T_603 = or(_T_602, _T_590) \n node _T_604 = or(_T_603, _T_595) \n node _T_605 = or(_T_604, _T_600) \n node _T_606 = and(_T_570, _T_605) \n node _T_607 = or(UInt<1>(0h0), _T_606) \n node _T_608 = and(_T_569, _T_607) \n node _T_609 = asUInt(reset) \n node _T_610 = eq(_T_609, UInt<1>(0h0)) \n when _T_610 : \n node _T_611 = eq(_T_608, UInt<1>(0h0)) \n when _T_611 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_608, UInt<1>(0h1), \"\") : assert_46 \n node _T_612 = asUInt(reset) \n node _T_613 = eq(_T_612, UInt<1>(0h0)) \n when _T_613 : \n node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_614 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_615 = asUInt(reset) \n node _T_616 = eq(_T_615, UInt<1>(0h0)) \n when _T_616 : \n node _T_617 = eq(is_aligned, UInt<1>(0h0)) \n when _T_617 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_619 = asUInt(reset) \n node _T_620 = eq(_T_619, UInt<1>(0h0)) \n when _T_620 : \n node _T_621 = eq(_T_618, UInt<1>(0h0)) \n when _T_621 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_618, UInt<1>(0h1), \"\") : assert_49 \n node _T_622 = eq(io.in.a.bits.mask, mask) \n node _T_623 = asUInt(reset) \n node _T_624 = eq(_T_623, UInt<1>(0h0)) \n when _T_624 : \n node _T_625 = eq(_T_622, UInt<1>(0h0)) \n when _T_625 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_622, UInt<1>(0h1), \"\") : assert_50 \n node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_627 = asUInt(reset) \n node _T_628 = eq(_T_627, UInt<1>(0h0)) \n when _T_628 : \n node _T_629 = eq(_T_626, UInt<1>(0h0)) \n when _T_629 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_626, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_631 = asUInt(reset) \n node _T_632 = eq(_T_631, UInt<1>(0h0)) \n when _T_632 : \n node _T_633 = eq(_T_630, UInt<1>(0h0)) \n when _T_633 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_630, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_1 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_634 : \n node _T_635 = asUInt(reset) \n node _T_636 = eq(_T_635, UInt<1>(0h0)) \n when _T_636 : \n node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_637 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_639 = asUInt(reset) \n node _T_640 = eq(_T_639, UInt<1>(0h0)) \n when _T_640 : \n node _T_641 = eq(_T_638, UInt<1>(0h0)) \n when _T_641 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_638, UInt<1>(0h1), \"\") : assert_54 \n node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_643 = asUInt(reset) \n node _T_644 = eq(_T_643, UInt<1>(0h0)) \n when _T_644 : \n node _T_645 = eq(_T_642, UInt<1>(0h0)) \n when _T_645 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_642, UInt<1>(0h1), \"\") : assert_55 \n node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_647 = asUInt(reset) \n node _T_648 = eq(_T_647, UInt<1>(0h0)) \n when _T_648 : \n node _T_649 = eq(_T_646, UInt<1>(0h0)) \n when _T_649 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_646, UInt<1>(0h1), \"\") : assert_56 \n node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_651 = asUInt(reset) \n node _T_652 = eq(_T_651, UInt<1>(0h0)) \n when _T_652 : \n node _T_653 = eq(_T_650, UInt<1>(0h0)) \n when _T_653 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_650, UInt<1>(0h1), \"\") : assert_57 \n node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_654 : \n node _T_655 = asUInt(reset) \n node _T_656 = eq(_T_655, UInt<1>(0h0)) \n when _T_656 : \n node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_657 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_658 = asUInt(reset) \n node _T_659 = eq(_T_658, UInt<1>(0h0)) \n when _T_659 : \n node _T_660 = eq(sink_ok, UInt<1>(0h0)) \n when _T_660 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_662 = asUInt(reset) \n node _T_663 = eq(_T_662, UInt<1>(0h0)) \n when _T_663 : \n node _T_664 = eq(_T_661, UInt<1>(0h0)) \n when _T_664 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_661, UInt<1>(0h1), \"\") : assert_60 \n node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_666 = asUInt(reset) \n node _T_667 = eq(_T_666, UInt<1>(0h0)) \n when _T_667 : \n node _T_668 = eq(_T_665, UInt<1>(0h0)) \n when _T_668 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_665, UInt<1>(0h1), \"\") : assert_61 \n node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_670 = asUInt(reset) \n node _T_671 = eq(_T_670, UInt<1>(0h0)) \n when _T_671 : \n node _T_672 = eq(_T_669, UInt<1>(0h0)) \n when _T_672 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_669, UInt<1>(0h1), \"\") : assert_62 \n node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_674 = asUInt(reset) \n node _T_675 = eq(_T_674, UInt<1>(0h0)) \n when _T_675 : \n node _T_676 = eq(_T_673, UInt<1>(0h0)) \n when _T_676 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_673, UInt<1>(0h1), \"\") : assert_63 \n node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_678 = or(UInt<1>(0h1), _T_677) \n node _T_679 = asUInt(reset) \n node _T_680 = eq(_T_679, UInt<1>(0h0)) \n when _T_680 : \n node _T_681 = eq(_T_678, UInt<1>(0h0)) \n when _T_681 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_678, UInt<1>(0h1), \"\") : assert_64 \n node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_682 : \n node _T_683 = asUInt(reset) \n node _T_684 = eq(_T_683, UInt<1>(0h0)) \n when _T_684 : \n node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_685 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_686 = asUInt(reset) \n node _T_687 = eq(_T_686, UInt<1>(0h0)) \n when _T_687 : \n node _T_688 = eq(sink_ok, UInt<1>(0h0)) \n when _T_688 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_690 = asUInt(reset) \n node _T_691 = eq(_T_690, UInt<1>(0h0)) \n when _T_691 : \n node _T_692 = eq(_T_689, UInt<1>(0h0)) \n when _T_692 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_689, UInt<1>(0h1), \"\") : assert_67 \n node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_694 = asUInt(reset) \n node _T_695 = eq(_T_694, UInt<1>(0h0)) \n when _T_695 : \n node _T_696 = eq(_T_693, UInt<1>(0h0)) \n when _T_696 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_693, UInt<1>(0h1), \"\") : assert_68 \n node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_698 = asUInt(reset) \n node _T_699 = eq(_T_698, UInt<1>(0h0)) \n when _T_699 : \n node _T_700 = eq(_T_697, UInt<1>(0h0)) \n when _T_700 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_697, UInt<1>(0h1), \"\") : assert_69 \n node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_702 = or(_T_701, io.in.d.bits.corrupt) \n node _T_703 = asUInt(reset) \n node _T_704 = eq(_T_703, UInt<1>(0h0)) \n when _T_704 : \n node _T_705 = eq(_T_702, UInt<1>(0h0)) \n when _T_705 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_702, UInt<1>(0h1), \"\") : assert_70 \n node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_707 = or(UInt<1>(0h1), _T_706) \n node _T_708 = asUInt(reset) \n node _T_709 = eq(_T_708, UInt<1>(0h0)) \n when _T_709 : \n node _T_710 = eq(_T_707, UInt<1>(0h0)) \n when _T_710 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_707, UInt<1>(0h1), \"\") : assert_71 \n node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_711 : \n node _T_712 = asUInt(reset) \n node _T_713 = eq(_T_712, UInt<1>(0h0)) \n when _T_713 : \n node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_714 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_716 = asUInt(reset) \n node _T_717 = eq(_T_716, UInt<1>(0h0)) \n when _T_717 : \n node _T_718 = eq(_T_715, UInt<1>(0h0)) \n when _T_718 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_715, UInt<1>(0h1), \"\") : assert_73 \n node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_720 = asUInt(reset) \n node _T_721 = eq(_T_720, UInt<1>(0h0)) \n when _T_721 : \n node _T_722 = eq(_T_719, UInt<1>(0h0)) \n when _T_722 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_719, UInt<1>(0h1), \"\") : assert_74 \n node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_724 = or(UInt<1>(0h1), _T_723) \n node _T_725 = asUInt(reset) \n node _T_726 = eq(_T_725, UInt<1>(0h0)) \n when _T_726 : \n node _T_727 = eq(_T_724, UInt<1>(0h0)) \n when _T_727 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_724, UInt<1>(0h1), \"\") : assert_75 \n node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_728 : \n node _T_729 = asUInt(reset) \n node _T_730 = eq(_T_729, UInt<1>(0h0)) \n when _T_730 : \n node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_731 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_733 = asUInt(reset) \n node _T_734 = eq(_T_733, UInt<1>(0h0)) \n when _T_734 : \n node _T_735 = eq(_T_732, UInt<1>(0h0)) \n when _T_735 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_732, UInt<1>(0h1), \"\") : assert_77 \n node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_737 = or(_T_736, io.in.d.bits.corrupt) \n node _T_738 = asUInt(reset) \n node _T_739 = eq(_T_738, UInt<1>(0h0)) \n when _T_739 : \n node _T_740 = eq(_T_737, UInt<1>(0h0)) \n when _T_740 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_737, UInt<1>(0h1), \"\") : assert_78 \n node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_742 = or(UInt<1>(0h1), _T_741) \n node _T_743 = asUInt(reset) \n node _T_744 = eq(_T_743, UInt<1>(0h0)) \n when _T_744 : \n node _T_745 = eq(_T_742, UInt<1>(0h0)) \n when _T_745 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_742, UInt<1>(0h1), \"\") : assert_79 \n node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_746 : \n node _T_747 = asUInt(reset) \n node _T_748 = eq(_T_747, UInt<1>(0h0)) \n when _T_748 : \n node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_749 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_751 = asUInt(reset) \n node _T_752 = eq(_T_751, UInt<1>(0h0)) \n when _T_752 : \n node _T_753 = eq(_T_750, UInt<1>(0h0)) \n when _T_753 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_750, UInt<1>(0h1), \"\") : assert_81 \n node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_755 = asUInt(reset) \n node _T_756 = eq(_T_755, UInt<1>(0h0)) \n when _T_756 : \n node _T_757 = eq(_T_754, UInt<1>(0h0)) \n when _T_757 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_754, UInt<1>(0h1), \"\") : assert_82 \n node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_759 = or(UInt<1>(0h1), _T_758) \n node _T_760 = asUInt(reset) \n node _T_761 = eq(_T_760, UInt<1>(0h0)) \n when _T_761 : \n node _T_762 = eq(_T_759, UInt<1>(0h0)) \n when _T_762 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_759, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<32>(0h0) \n connect _WIRE.bits.mask, UInt<4>(0h0) \n connect _WIRE.bits.address, UInt<9>(0h0) \n connect _WIRE.bits.source, UInt<1>(0h0) \n connect _WIRE.bits.size, UInt<2>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_764 = asUInt(reset) \n node _T_765 = eq(_T_764, UInt<1>(0h0)) \n when _T_765 : \n node _T_766 = eq(_T_763, UInt<1>(0h0)) \n when _T_766 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_763, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<32>(0h0) \n connect _WIRE_2.bits.address, UInt<9>(0h0) \n connect _WIRE_2.bits.source, UInt<1>(0h0) \n connect _WIRE_2.bits.size, UInt<2>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_768 = asUInt(reset) \n node _T_769 = eq(_T_768, UInt<1>(0h0)) \n when _T_769 : \n node _T_770 = eq(_T_767, UInt<1>(0h0)) \n when _T_770 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_767, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_772 = asUInt(reset) \n node _T_773 = eq(_T_772, UInt<1>(0h0)) \n when _T_773 : \n node _T_774 = eq(_T_771, UInt<1>(0h0)) \n when _T_774 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_771, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_775 = eq(a_first, UInt<1>(0h0)) \n node _T_776 = and(io.in.a.valid, _T_775) \n when _T_776 : \n node _T_777 = eq(io.in.a.bits.opcode, opcode) \n node _T_778 = asUInt(reset) \n node _T_779 = eq(_T_778, UInt<1>(0h0)) \n when _T_779 : \n node _T_780 = eq(_T_777, UInt<1>(0h0)) \n when _T_780 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_777, UInt<1>(0h1), \"\") : assert_87 \n node _T_781 = eq(io.in.a.bits.param, param) \n node _T_782 = asUInt(reset) \n node _T_783 = eq(_T_782, UInt<1>(0h0)) \n when _T_783 : \n node _T_784 = eq(_T_781, UInt<1>(0h0)) \n when _T_784 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_781, UInt<1>(0h1), \"\") : assert_88 \n node _T_785 = eq(io.in.a.bits.size, size) \n node _T_786 = asUInt(reset) \n node _T_787 = eq(_T_786, UInt<1>(0h0)) \n when _T_787 : \n node _T_788 = eq(_T_785, UInt<1>(0h0)) \n when _T_788 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_785, UInt<1>(0h1), \"\") : assert_89 \n node _T_789 = eq(io.in.a.bits.source, source) \n node _T_790 = asUInt(reset) \n node _T_791 = eq(_T_790, UInt<1>(0h0)) \n when _T_791 : \n node _T_792 = eq(_T_789, UInt<1>(0h0)) \n when _T_792 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_789, UInt<1>(0h1), \"\") : assert_90 \n node _T_793 = eq(io.in.a.bits.address, address) \n node _T_794 = asUInt(reset) \n node _T_795 = eq(_T_794, UInt<1>(0h0)) \n when _T_795 : \n node _T_796 = eq(_T_793, UInt<1>(0h0)) \n when _T_796 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_793, UInt<1>(0h1), \"\") : assert_91 \n node _T_797 = and(io.in.a.ready, io.in.a.valid) \n node _T_798 = and(_T_797, a_first) \n when _T_798 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_799 = eq(d_first, UInt<1>(0h0)) \n node _T_800 = and(io.in.d.valid, _T_799) \n when _T_800 : \n node _T_801 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_802 = asUInt(reset) \n node _T_803 = eq(_T_802, UInt<1>(0h0)) \n when _T_803 : \n node _T_804 = eq(_T_801, UInt<1>(0h0)) \n when _T_804 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_801, UInt<1>(0h1), \"\") : assert_92 \n node _T_805 = eq(io.in.d.bits.param, param_1) \n node _T_806 = asUInt(reset) \n node _T_807 = eq(_T_806, UInt<1>(0h0)) \n when _T_807 : \n node _T_808 = eq(_T_805, UInt<1>(0h0)) \n when _T_808 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_805, UInt<1>(0h1), \"\") : assert_93 \n node _T_809 = eq(io.in.d.bits.size, size_1) \n node _T_810 = asUInt(reset) \n node _T_811 = eq(_T_810, UInt<1>(0h0)) \n when _T_811 : \n node _T_812 = eq(_T_809, UInt<1>(0h0)) \n when _T_812 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_809, UInt<1>(0h1), \"\") : assert_94 \n node _T_813 = eq(io.in.d.bits.source, source_1) \n node _T_814 = asUInt(reset) \n node _T_815 = eq(_T_814, UInt<1>(0h0)) \n when _T_815 : \n node _T_816 = eq(_T_813, UInt<1>(0h0)) \n when _T_816 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_813, UInt<1>(0h1), \"\") : assert_95 \n node _T_817 = eq(io.in.d.bits.sink, sink) \n node _T_818 = asUInt(reset) \n node _T_819 = eq(_T_818, UInt<1>(0h0)) \n when _T_819 : \n node _T_820 = eq(_T_817, UInt<1>(0h0)) \n when _T_820 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_817, UInt<1>(0h1), \"\") : assert_96 \n node _T_821 = eq(io.in.d.bits.denied, denied) \n node _T_822 = asUInt(reset) \n node _T_823 = eq(_T_822, UInt<1>(0h0)) \n when _T_823 : \n node _T_824 = eq(_T_821, UInt<1>(0h0)) \n when _T_824 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_821, UInt<1>(0h1), \"\") : assert_97 \n node _T_825 = and(io.in.d.ready, io.in.d.valid) \n node _T_826 = and(_T_825, d_first) \n when _T_826 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) \n regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<1> \n connect a_set, UInt<1>(0h0) \n wire a_set_wo_ready : UInt<1> \n connect a_set_wo_ready, UInt<1>(0h0) \n wire a_opcodes_set : UInt<4> \n connect a_opcodes_set, UInt<4>(0h0) \n wire a_sizes_set : UInt<4> \n connect a_sizes_set, UInt<4>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<3> \n connect a_sizes_set_interm, UInt<3>(0h0) \n node _T_827 = and(io.in.a.valid, a_first_1) \n node _T_828 = and(_T_827, UInt<1>(0h1)) \n when _T_828 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_829 = and(io.in.a.ready, io.in.a.valid) \n node _T_830 = and(_T_829, a_first_1) \n node _T_831 = and(_T_830, UInt<1>(0h1)) \n when _T_831 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_832 = dshr(inflight, io.in.a.bits.source) \n node _T_833 = bits(_T_832, 0, 0) \n node _T_834 = eq(_T_833, UInt<1>(0h0)) \n node _T_835 = asUInt(reset) \n node _T_836 = eq(_T_835, UInt<1>(0h0)) \n when _T_836 : \n node _T_837 = eq(_T_834, UInt<1>(0h0)) \n when _T_837 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_834, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<1> \n connect d_clr, UInt<1>(0h0) \n wire d_clr_wo_ready : UInt<1> \n connect d_clr_wo_ready, UInt<1>(0h0) \n wire d_opcodes_clr : UInt<4> \n connect d_opcodes_clr, UInt<4>(0h0) \n wire d_sizes_clr : UInt<4> \n connect d_sizes_clr, UInt<4>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_838 = and(io.in.d.valid, d_first_1) \n node _T_839 = and(_T_838, UInt<1>(0h1)) \n node _T_840 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_841 = and(_T_839, _T_840) \n when _T_841 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_842 = and(io.in.d.ready, io.in.d.valid) \n node _T_843 = and(_T_842, d_first_1) \n node _T_844 = and(_T_843, UInt<1>(0h1)) \n node _T_845 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_846 = and(_T_844, _T_845) \n when _T_846 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_847 = and(io.in.d.valid, d_first_1) \n node _T_848 = and(_T_847, UInt<1>(0h1)) \n node _T_849 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_850 = and(_T_848, _T_849) \n when _T_850 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_851 = dshr(inflight, io.in.d.bits.source) \n node _T_852 = bits(_T_851, 0, 0) \n node _T_853 = or(_T_852, same_cycle_resp) \n node _T_854 = asUInt(reset) \n node _T_855 = eq(_T_854, UInt<1>(0h0)) \n when _T_855 : \n node _T_856 = eq(_T_853, UInt<1>(0h0)) \n when _T_856 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_853, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_859 = or(_T_857, _T_858) \n node _T_860 = asUInt(reset) \n node _T_861 = eq(_T_860, UInt<1>(0h0)) \n when _T_861 : \n node _T_862 = eq(_T_859, UInt<1>(0h0)) \n when _T_862 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_859, UInt<1>(0h1), \"\") : assert_100 \n node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_864 = asUInt(reset) \n node _T_865 = eq(_T_864, UInt<1>(0h0)) \n when _T_865 : \n node _T_866 = eq(_T_863, UInt<1>(0h0)) \n when _T_866 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_863, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_869 = or(_T_867, _T_868) \n node _T_870 = asUInt(reset) \n node _T_871 = eq(_T_870, UInt<1>(0h0)) \n when _T_871 : \n node _T_872 = eq(_T_869, UInt<1>(0h0)) \n when _T_872 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_869, UInt<1>(0h1), \"\") : assert_102 \n node _T_873 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_874 = asUInt(reset) \n node _T_875 = eq(_T_874, UInt<1>(0h0)) \n when _T_875 : \n node _T_876 = eq(_T_873, UInt<1>(0h0)) \n when _T_876 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_873, UInt<1>(0h1), \"\") : assert_103 \n node _T_877 = and(io.in.d.valid, d_first_1) \n node _T_878 = and(_T_877, a_first_1) \n node _T_879 = and(_T_878, io.in.a.valid) \n node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_881 = and(_T_879, _T_880) \n node _T_882 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_883 = and(_T_881, _T_882) \n when _T_883 : \n node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_885 = or(_T_884, io.in.a.ready) \n node _T_886 = asUInt(reset) \n node _T_887 = eq(_T_886, UInt<1>(0h0)) \n when _T_887 : \n node _T_888 = eq(_T_885, UInt<1>(0h0)) \n when _T_888 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_885, UInt<1>(0h1), \"\") : assert_104 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_110 \n node _T_889 = orr(inflight) \n node _T_890 = eq(_T_889, UInt<1>(0h0)) \n node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_892 = or(_T_890, _T_891) \n node _T_893 = lt(watchdog, plusarg_reader.out) \n node _T_894 = or(_T_892, _T_893) \n node _T_895 = asUInt(reset) \n node _T_896 = eq(_T_895, UInt<1>(0h0)) \n when _T_896 : \n node _T_897 = eq(_T_894, UInt<1>(0h0)) \n when _T_897 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_894, UInt<1>(0h1), \"\") : assert_105 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_898 = and(io.in.a.ready, io.in.a.valid) \n node _T_899 = and(io.in.d.ready, io.in.d.valid) \n node _T_900 = or(_T_898, _T_899) \n when _T_900 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) \n regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE.bits.address, UInt<9>(0h0) \n connect _c_first_WIRE.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<1> \n connect c_set, UInt<1>(0h0) \n wire c_set_wo_ready : UInt<1> \n connect c_set_wo_ready, UInt<1>(0h0) \n wire c_opcodes_set : UInt<4> \n connect c_opcodes_set, UInt<4>(0h0) \n wire c_sizes_set : UInt<4> \n connect c_sizes_set, UInt<4>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<3> \n connect c_sizes_set_interm, UInt<3>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<32>(0h0) \n connect _WIRE_6.bits.address, UInt<9>(0h0) \n connect _WIRE_6.bits.source, UInt<1>(0h0) \n connect _WIRE_6.bits.size, UInt<2>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_901 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<32>(0h0) \n connect _WIRE_8.bits.address, UInt<9>(0h0) \n connect _WIRE_8.bits.source, UInt<1>(0h0) \n connect _WIRE_8.bits.size, UInt<2>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_904 = and(_T_902, _T_903) \n node _T_905 = and(_T_901, _T_904) \n when _T_905 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<32>(0h0) \n connect _WIRE_10.bits.address, UInt<9>(0h0) \n connect _WIRE_10.bits.source, UInt<1>(0h0) \n connect _WIRE_10.bits.size, UInt<2>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_907 = and(_T_906, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<32>(0h0) \n connect _WIRE_12.bits.address, UInt<9>(0h0) \n connect _WIRE_12.bits.source, UInt<1>(0h0) \n connect _WIRE_12.bits.size, UInt<2>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_910 = and(_T_908, _T_909) \n node _T_911 = and(_T_907, _T_910) \n when _T_911 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_WIRE.bits.address, UInt<9>(0h0) \n connect _c_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<32>(0h0) \n connect _WIRE_14.bits.address, UInt<9>(0h0) \n connect _WIRE_14.bits.source, UInt<1>(0h0) \n connect _WIRE_14.bits.size, UInt<2>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_913 = bits(_T_912, 0, 0) \n node _T_914 = eq(_T_913, UInt<1>(0h0)) \n node _T_915 = asUInt(reset) \n node _T_916 = eq(_T_915, UInt<1>(0h0)) \n when _T_916 : \n node _T_917 = eq(_T_914, UInt<1>(0h0)) \n when _T_917 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_914, UInt<1>(0h1), \"\") : assert_106 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<1> \n connect d_clr_1, UInt<1>(0h0) \n wire d_clr_wo_ready_1 : UInt<1> \n connect d_clr_wo_ready_1, UInt<1>(0h0) \n wire d_opcodes_clr_1 : UInt<4> \n connect d_opcodes_clr_1, UInt<4>(0h0) \n wire d_sizes_clr_1 : UInt<4> \n connect d_sizes_clr_1, UInt<4>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_918 = and(io.in.d.valid, d_first_2) \n node _T_919 = and(_T_918, UInt<1>(0h1)) \n node _T_920 = and(_T_919, d_release_ack_1) \n when _T_920 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_921 = and(io.in.d.ready, io.in.d.valid) \n node _T_922 = and(_T_921, d_first_2) \n node _T_923 = and(_T_922, UInt<1>(0h1)) \n node _T_924 = and(_T_923, d_release_ack_1) \n when _T_924 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_925 = and(io.in.d.valid, d_first_2) \n node _T_926 = and(_T_925, UInt<1>(0h1)) \n node _T_927 = and(_T_926, d_release_ack_1) \n when _T_927 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_928 = dshr(inflight_1, io.in.d.bits.source) \n node _T_929 = bits(_T_928, 0, 0) \n node _T_930 = or(_T_929, same_cycle_resp_1) \n node _T_931 = asUInt(reset) \n node _T_932 = eq(_T_931, UInt<1>(0h0)) \n when _T_932 : \n node _T_933 = eq(_T_930, UInt<1>(0h0)) \n when _T_933 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_930, UInt<1>(0h1), \"\") : assert_107 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<32>(0h0) \n connect _WIRE_16.bits.address, UInt<9>(0h0) \n connect _WIRE_16.bits.source, UInt<1>(0h0) \n connect _WIRE_16.bits.size, UInt<2>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_935 = asUInt(reset) \n node _T_936 = eq(_T_935, UInt<1>(0h0)) \n when _T_936 : \n node _T_937 = eq(_T_934, UInt<1>(0h0)) \n when _T_937 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_934, UInt<1>(0h1), \"\") : assert_108 \n else :\n\n node _T_938 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_939 = asUInt(reset) \n node _T_940 = eq(_T_939, UInt<1>(0h0)) \n when _T_940 : \n node _T_941 = eq(_T_938, UInt<1>(0h0)) \n when _T_941 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_938, UInt<1>(0h1), \"\") : assert_109 \n node _T_942 = and(io.in.d.valid, d_first_2) \n node _T_943 = and(_T_942, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<32>(0h0) \n connect _WIRE_18.bits.address, UInt<9>(0h0) \n connect _WIRE_18.bits.source, UInt<1>(0h0) \n connect _WIRE_18.bits.size, UInt<2>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_944 = and(_T_943, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<32>(0h0) \n connect _WIRE_20.bits.address, UInt<9>(0h0) \n connect _WIRE_20.bits.source, UInt<1>(0h0) \n connect _WIRE_20.bits.size, UInt<2>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_946 = and(_T_944, _T_945) \n node _T_947 = and(_T_946, d_release_ack_1) \n node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_949 = and(_T_947, _T_948) \n when _T_949 : \n node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<32>(0h0) \n connect _WIRE_22.bits.address, UInt<9>(0h0) \n connect _WIRE_22.bits.source, UInt<1>(0h0) \n connect _WIRE_22.bits.size, UInt<2>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_951 = or(_T_950, _WIRE_23.ready) \n node _T_952 = asUInt(reset) \n node _T_953 = eq(_T_952, UInt<1>(0h0)) \n when _T_953 : \n node _T_954 = eq(_T_951, UInt<1>(0h0)) \n when _T_954 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_951, UInt<1>(0h1), \"\") : assert_110 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_111 \n node _T_955 = orr(inflight_1) \n node _T_956 = eq(_T_955, UInt<1>(0h0)) \n node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_958 = or(_T_956, _T_957) \n node _T_959 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_960 = or(_T_958, _T_959) \n node _T_961 = asUInt(reset) \n node _T_962 = eq(_T_961, UInt<1>(0h0)) \n when _T_962 : \n node _T_963 = eq(_T_960, UInt<1>(0h0)) \n when _T_963 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_960, UInt<1>(0h1), \"\") : assert_111 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<32>(0h0) \n connect _WIRE_24.bits.address, UInt<9>(0h0) \n connect _WIRE_24.bits.source, UInt<1>(0h0) \n connect _WIRE_24.bits.size, UInt<2>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_965 = and(io.in.d.ready, io.in.d.valid) \n node _T_966 = or(_T_964, _T_965) \n when _T_966 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_54(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [8:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_source = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire mask_sizeOH_shiftAmount = 1'h0;\t// @[OneHot.scala:64:49]\n wire mask_sub_size = 1'h0;\t// @[Misc.scala:209:26]\n wire _mask_sub_acc_T = 1'h0;\t// @[Misc.scala:215:38]\n wire _mask_sub_acc_T_1 = 1'h0;\t// @[Misc.scala:215:38]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire a_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire a_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire c_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_first_count_T = 1'h0;\t// @[Edges.scala:234:27]\n wire c_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_counter_T = 1'h0;\t// @[Edges.scala:236:21]\n wire d_first_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire c_set = 1'h0;\t// @[Monitor.scala:738:34]\n wire c_set_wo_ready = 1'h0;\t// @[Monitor.scala:739:34]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire _source_ok_T = 1'h1;\t// @[Parameters.scala:46:9]\n wire _source_ok_WIRE_0 = 1'h1;\t// @[Parameters.scala:1138:31]\n wire mask_sub_sub_0_1 = 1'h1;\t// @[Misc.scala:206:21]\n wire mask_sub_0_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_sub_1_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_size = 1'h1;\t// @[Misc.scala:209:26]\n wire mask_acc = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_2 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_3 = 1'h1;\t// @[Misc.scala:215:29]\n wire _a_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _a_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire c_first_counter1 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_2 = 1'h1;\t// @[Edges.scala:232:33]\n wire [1:0] is_aligned_mask = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] mask_lo = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] _a_first_beats1_decode_T_2 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _a_first_beats1_decode_T_5 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _c_first_beats1_decode_T_1 = 2'h3;\t// @[package.scala:243:76]\n wire [1:0] _c_first_counter1_T = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_a_bits_size = 2'h2;\t// @[Monitor.scala:36:7]\n wire [1:0] _mask_sizeOH_T = 2'h2;\t// @[Misc.scala:202:34]\n wire [2:0] io_in_a_bits_param = 3'h0;\t// @[Monitor.scala:36:7]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_sizes_set_interm = 3'h0;\t// @[Monitor.scala:755:40]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_T = 3'h0;\t// @[Monitor.scala:766:51]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] io_in_a_bits_mask = 4'hF;\t// @[Monitor.scala:36:7]\n wire [3:0] mask = 4'hF;\t// @[Misc.scala:222:10]\n wire [31:0] _c_first_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_first_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_first_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_first_WIRE_2_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_first_WIRE_3_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_set_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_set_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _is_aligned_mask_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_4 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _c_first_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_beats1_decode_T_2 = 2'h0;\t// @[package.scala:243:46]\n wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [17:0] _c_sizes_set_T_1 = 18'h0;\t// @[Monitor.scala:768:52]\n wire [3:0] _a_opcodes_set_T = 4'h0;\t// @[Monitor.scala:659:79]\n wire [3:0] _a_sizes_set_T = 4'h0;\t// @[Monitor.scala:660:77]\n wire [3:0] c_opcodes_set = 4'h0;\t// @[Monitor.scala:740:34]\n wire [3:0] c_sizes_set = 4'h0;\t// @[Monitor.scala:741:34]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_opcodes_set_T = 4'h0;\t// @[Monitor.scala:767:79]\n wire [3:0] _c_sizes_set_T = 4'h0;\t// @[Monitor.scala:768:77]\n wire [18:0] _c_opcodes_set_T_1 = 19'h0;\t// @[Monitor.scala:767:54]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_sizes_set_interm_T_1 = 3'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [1:0] _mask_sizeOH_T_1 = 2'h1;\t// @[OneHot.scala:65:12]\n wire [1:0] _mask_sizeOH_T_2 = 2'h1;\t// @[OneHot.scala:65:27]\n wire [1:0] mask_sizeOH = 2'h1;\t// @[Misc.scala:202:81]\n wire [1:0] _a_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _a_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [4:0] _c_first_beats1_decode_T = 5'h3;\t// @[package.scala:243:71]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T_1 = 3'h5;\t// @[Monitor.scala:658:59]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T = 3'h4;\t// @[Monitor.scala:658:51]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [4:0] _is_aligned_mask_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T_3 = 5'hC;\t// @[package.scala:243:71]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]};\t// @[Monitor.scala:36:7]\n wire is_aligned = _is_aligned_T == 9'h0;\t// @[Edges.scala:21:{16,24}]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_1_2 = mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_eq;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_eq_1;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_eq_2;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_eq_3;\t// @[Misc.scala:214:27, :215:38]\n wire _source_ok_T_1 = ~io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_0 = _source_ok_T_1;\t// @[Parameters.scala:1138:31]\n wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_898;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_898;\t// @[Decoupled.scala:51:35]\n wire a_first_done = _a_first_T;\t// @[Decoupled.scala:51:35]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n wire _a_first_last_T = a_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1 = _a_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~a_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T = ~a_first & a_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [8:0] address;\t// @[Monitor.scala:391:22]\n wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_966;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_966;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_966;\t// @[Decoupled.scala:51:35]\n wire d_first_done = _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN;\t// @[package.scala:243:71]\n wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n wire _d_first_last_T = d_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1 = _d_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire d_first = ~d_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T = ~d_first & d_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [1:0] inflight;\t// @[Monitor.scala:614:27]\n reg [3:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [3:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire a_first_done_1 = _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n wire _a_first_last_T_2 = a_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1_1 = _a_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire a_first_1 = ~a_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_first_done_1 = _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_2 = d_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_1 = _d_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire d_first_1 = ~d_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire a_set;\t// @[Monitor.scala:626:34]\n wire a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [3:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [3:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [3:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_0;\t// @[Monitor.scala:637:69]\n wire [3:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_0;\t// @[Monitor.scala:637:69, :641:65]\n wire [3:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_0;\t// @[Monitor.scala:637:69, :680:101]\n wire [3:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_0;\t// @[Monitor.scala:637:69, :681:99]\n wire [3:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_0;\t// @[Monitor.scala:637:69, :749:69]\n wire [3:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_0;\t// @[Monitor.scala:637:69, :750:67]\n wire [3:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_0;\t// @[Monitor.scala:637:69, :790:101]\n wire [3:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_0;\t// @[Monitor.scala:637:69, :791:99]\n wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1};\t// @[Monitor.scala:637:{44,97}]\n wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1};\t// @[Monitor.scala:637:97, :641:{40,91}]\n wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [2:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _T_828 = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26]\n assign a_set_wo_ready = _T_828;\t// @[Monitor.scala:627:34, :651:26]\n wire _same_cycle_resp_T;\t// @[Monitor.scala:684:44]\n assign _same_cycle_resp_T = _T_828;\t// @[Monitor.scala:651:26, :684:44]\n assign a_set = _T_898 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]\n assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0;\t// @[Monitor.scala:626:34, :648:38, :655:70, :658:28]\n wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm};\t// @[Monitor.scala:646:40, :659:54]\n assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]\n wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm};\t// @[Monitor.scala:648:38, :659:54, :660:52]\n assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]\n wire d_clr;\t// @[Monitor.scala:664:34]\n wire d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [3:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [3:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_1;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_1;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_877 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0};\t// @[OneHot.scala:58:35]\n wire [1:0] _GEN_3 = 2'h1 << _GEN_2;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_3;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_3;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_3;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_3;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0];\t// @[OneHot.scala:58:35]\n wire _T_846 = _T_966 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_846 & _d_clr_T[0];\t// @[OneHot.scala:58:35]\n wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set};\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1};\t// @[Monitor.scala:705:{27,36,38}]\n wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [1:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [1:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [3:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [3:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire d_first_done_2 = _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_4 = d_first_counter_2;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_2 = _d_first_counter1_T_2[0];\t// @[Edges.scala:230:28]\n wire d_first_2 = ~d_first_counter_2;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1};\t// @[Monitor.scala:637:97, :749:{44,97}]\n wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1};\t// @[Monitor.scala:637:97, :750:{42,93}]\n wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire d_clr_1;\t// @[Monitor.scala:774:34]\n wire d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [3:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [3:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_942 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0];\t// @[OneHot.scala:58:35]\n wire _T_924 = _T_966 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_924 & _d_clr_T_1[0];\t// @[OneHot.scala:58:35]\n wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :795:113]\n wire _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4};\t// @[Monitor.scala:814:{35,44,46}]\n wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32178,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) \n node _source_ok_T = shr(io.in.a.bits.source, 5) \n node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) \n node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) \n node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) \n node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T_5 \n node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 4, 0) \n node _T_4 = shr(io.in.a.bits.source, 5) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = leq(UInt<1>(0h0), uncommonBits) \n node _T_7 = and(_T_5, _T_6) \n node _T_8 = leq(uncommonBits, UInt<5>(0h13)) \n node _T_9 = and(_T_7, _T_8) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_12 = cvt(_T_11) \n node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) \n node _T_14 = asSInt(_T_13) \n node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) \n node _T_16 = or(_T_10, _T_15) \n node _T_17 = asUInt(reset) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n when _T_18 : \n node _T_19 = eq(_T_16, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_16, UInt<1>(0h1), \"\") : assert_1 \n node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_20 : \n node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_23 = and(_T_21, _T_22) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) \n node _T_24 = shr(io.in.a.bits.source, 5) \n node _T_25 = eq(_T_24, UInt<1>(0h0)) \n node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_27 = and(_T_25, _T_26) \n node _T_28 = leq(uncommonBits_1, UInt<5>(0h13)) \n node _T_29 = and(_T_27, _T_28) \n node _T_30 = and(_T_23, _T_29) \n node _T_31 = or(UInt<1>(0h0), _T_30) \n node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_34 = cvt(_T_33) \n node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) \n node _T_36 = asSInt(_T_35) \n node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) \n node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_39 = cvt(_T_38) \n node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000))) \n node _T_41 = asSInt(_T_40) \n node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) \n node _T_43 = or(_T_37, _T_42) \n node _T_44 = and(_T_32, _T_43) \n node _T_45 = or(UInt<1>(0h0), _T_44) \n node _T_46 = and(_T_31, _T_45) \n node _T_47 = asUInt(reset) \n node _T_48 = eq(_T_47, UInt<1>(0h0)) \n when _T_48 : \n node _T_49 = eq(_T_46, UInt<1>(0h0)) \n when _T_49 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_46, UInt<1>(0h1), \"\") : assert_2 \n node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_52 = and(_T_50, _T_51) \n node _T_53 = or(UInt<1>(0h0), _T_52) \n node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_55 = cvt(_T_54) \n node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) \n node _T_57 = asSInt(_T_56) \n node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) \n node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_60 = cvt(_T_59) \n node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000))) \n node _T_62 = asSInt(_T_61) \n node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) \n node _T_64 = or(_T_58, _T_63) \n node _T_65 = and(_T_53, _T_64) \n node _T_66 = or(UInt<1>(0h0), _T_65) \n node _T_67 = and(UInt<1>(0h0), _T_66) \n node _T_68 = asUInt(reset) \n node _T_69 = eq(_T_68, UInt<1>(0h0)) \n when _T_69 : \n node _T_70 = eq(_T_67, UInt<1>(0h0)) \n when _T_70 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_67, UInt<1>(0h1), \"\") : assert_3 \n node _T_71 = asUInt(reset) \n node _T_72 = eq(_T_71, UInt<1>(0h0)) \n when _T_72 : \n node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_73 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_75 = asUInt(reset) \n node _T_76 = eq(_T_75, UInt<1>(0h0)) \n when _T_76 : \n node _T_77 = eq(_T_74, UInt<1>(0h0)) \n when _T_77 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_74, UInt<1>(0h1), \"\") : assert_5 \n node _T_78 = asUInt(reset) \n node _T_79 = eq(_T_78, UInt<1>(0h0)) \n when _T_79 : \n node _T_80 = eq(is_aligned, UInt<1>(0h0)) \n when _T_80 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_82 = asUInt(reset) \n node _T_83 = eq(_T_82, UInt<1>(0h0)) \n when _T_83 : \n node _T_84 = eq(_T_81, UInt<1>(0h0)) \n when _T_84 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_81, UInt<1>(0h1), \"\") : assert_7 \n node _T_85 = not(io.in.a.bits.mask) \n node _T_86 = eq(_T_85, UInt<1>(0h0)) \n node _T_87 = asUInt(reset) \n node _T_88 = eq(_T_87, UInt<1>(0h0)) \n when _T_88 : \n node _T_89 = eq(_T_86, UInt<1>(0h0)) \n when _T_89 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_86, UInt<1>(0h1), \"\") : assert_8 \n node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_91 = asUInt(reset) \n node _T_92 = eq(_T_91, UInt<1>(0h0)) \n when _T_92 : \n node _T_93 = eq(_T_90, UInt<1>(0h0)) \n when _T_93 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_90, UInt<1>(0h1), \"\") : assert_9 \n node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_94 : \n node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_97 = and(_T_95, _T_96) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) \n node _T_98 = shr(io.in.a.bits.source, 5) \n node _T_99 = eq(_T_98, UInt<1>(0h0)) \n node _T_100 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_101 = and(_T_99, _T_100) \n node _T_102 = leq(uncommonBits_2, UInt<5>(0h13)) \n node _T_103 = and(_T_101, _T_102) \n node _T_104 = and(_T_97, _T_103) \n node _T_105 = or(UInt<1>(0h0), _T_104) \n node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_108 = cvt(_T_107) \n node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000))) \n node _T_110 = asSInt(_T_109) \n node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) \n node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_113 = cvt(_T_112) \n node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000))) \n node _T_115 = asSInt(_T_114) \n node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) \n node _T_117 = or(_T_111, _T_116) \n node _T_118 = and(_T_106, _T_117) \n node _T_119 = or(UInt<1>(0h0), _T_118) \n node _T_120 = and(_T_105, _T_119) \n node _T_121 = asUInt(reset) \n node _T_122 = eq(_T_121, UInt<1>(0h0)) \n when _T_122 : \n node _T_123 = eq(_T_120, UInt<1>(0h0)) \n when _T_123 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_120, UInt<1>(0h1), \"\") : assert_10 \n node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_126 = and(_T_124, _T_125) \n node _T_127 = or(UInt<1>(0h0), _T_126) \n node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_129 = cvt(_T_128) \n node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000))) \n node _T_131 = asSInt(_T_130) \n node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0))) \n node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_134 = cvt(_T_133) \n node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000))) \n node _T_136 = asSInt(_T_135) \n node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0))) \n node _T_138 = or(_T_132, _T_137) \n node _T_139 = and(_T_127, _T_138) \n node _T_140 = or(UInt<1>(0h0), _T_139) \n node _T_141 = and(UInt<1>(0h0), _T_140) \n node _T_142 = asUInt(reset) \n node _T_143 = eq(_T_142, UInt<1>(0h0)) \n when _T_143 : \n node _T_144 = eq(_T_141, UInt<1>(0h0)) \n when _T_144 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_141, UInt<1>(0h1), \"\") : assert_11 \n node _T_145 = asUInt(reset) \n node _T_146 = eq(_T_145, UInt<1>(0h0)) \n when _T_146 : \n node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_147 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_149 = asUInt(reset) \n node _T_150 = eq(_T_149, UInt<1>(0h0)) \n when _T_150 : \n node _T_151 = eq(_T_148, UInt<1>(0h0)) \n when _T_151 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_148, UInt<1>(0h1), \"\") : assert_13 \n node _T_152 = asUInt(reset) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n when _T_153 : \n node _T_154 = eq(is_aligned, UInt<1>(0h0)) \n when _T_154 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_156 = asUInt(reset) \n node _T_157 = eq(_T_156, UInt<1>(0h0)) \n when _T_157 : \n node _T_158 = eq(_T_155, UInt<1>(0h0)) \n when _T_158 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_155, UInt<1>(0h1), \"\") : assert_15 \n node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_160 = asUInt(reset) \n node _T_161 = eq(_T_160, UInt<1>(0h0)) \n when _T_161 : \n node _T_162 = eq(_T_159, UInt<1>(0h0)) \n when _T_162 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_159, UInt<1>(0h1), \"\") : assert_16 \n node _T_163 = not(io.in.a.bits.mask) \n node _T_164 = eq(_T_163, UInt<1>(0h0)) \n node _T_165 = asUInt(reset) \n node _T_166 = eq(_T_165, UInt<1>(0h0)) \n when _T_166 : \n node _T_167 = eq(_T_164, UInt<1>(0h0)) \n when _T_167 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_164, UInt<1>(0h1), \"\") : assert_17 \n node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_169 = asUInt(reset) \n node _T_170 = eq(_T_169, UInt<1>(0h0)) \n when _T_170 : \n node _T_171 = eq(_T_168, UInt<1>(0h0)) \n when _T_171 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_168, UInt<1>(0h1), \"\") : assert_18 \n node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_172 : \n node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_175 = and(_T_173, _T_174) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) \n node _T_176 = shr(io.in.a.bits.source, 5) \n node _T_177 = eq(_T_176, UInt<1>(0h0)) \n node _T_178 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_179 = and(_T_177, _T_178) \n node _T_180 = leq(uncommonBits_3, UInt<5>(0h13)) \n node _T_181 = and(_T_179, _T_180) \n node _T_182 = and(_T_175, _T_181) \n node _T_183 = or(UInt<1>(0h0), _T_182) \n node _T_184 = asUInt(reset) \n node _T_185 = eq(_T_184, UInt<1>(0h0)) \n when _T_185 : \n node _T_186 = eq(_T_183, UInt<1>(0h0)) \n when _T_186 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_183, UInt<1>(0h1), \"\") : assert_19 \n node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_189 = and(_T_187, _T_188) \n node _T_190 = or(UInt<1>(0h0), _T_189) \n node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_192 = cvt(_T_191) \n node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000))) \n node _T_194 = asSInt(_T_193) \n node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) \n node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_197 = cvt(_T_196) \n node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000))) \n node _T_199 = asSInt(_T_198) \n node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) \n node _T_201 = or(_T_195, _T_200) \n node _T_202 = and(_T_190, _T_201) \n node _T_203 = or(UInt<1>(0h0), _T_202) \n node _T_204 = asUInt(reset) \n node _T_205 = eq(_T_204, UInt<1>(0h0)) \n when _T_205 : \n node _T_206 = eq(_T_203, UInt<1>(0h0)) \n when _T_206 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_203, UInt<1>(0h1), \"\") : assert_20 \n node _T_207 = asUInt(reset) \n node _T_208 = eq(_T_207, UInt<1>(0h0)) \n when _T_208 : \n node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_209 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_210 = asUInt(reset) \n node _T_211 = eq(_T_210, UInt<1>(0h0)) \n when _T_211 : \n node _T_212 = eq(is_aligned, UInt<1>(0h0)) \n when _T_212 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_214 = asUInt(reset) \n node _T_215 = eq(_T_214, UInt<1>(0h0)) \n when _T_215 : \n node _T_216 = eq(_T_213, UInt<1>(0h0)) \n when _T_216 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_213, UInt<1>(0h1), \"\") : assert_23 \n node _T_217 = eq(io.in.a.bits.mask, mask) \n node _T_218 = asUInt(reset) \n node _T_219 = eq(_T_218, UInt<1>(0h0)) \n when _T_219 : \n node _T_220 = eq(_T_217, UInt<1>(0h0)) \n when _T_220 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_217, UInt<1>(0h1), \"\") : assert_24 \n node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_222 = asUInt(reset) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n when _T_223 : \n node _T_224 = eq(_T_221, UInt<1>(0h0)) \n when _T_224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_221, UInt<1>(0h1), \"\") : assert_25 \n node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_225 : \n node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_228 = and(_T_226, _T_227) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) \n node _T_229 = shr(io.in.a.bits.source, 5) \n node _T_230 = eq(_T_229, UInt<1>(0h0)) \n node _T_231 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_232 = and(_T_230, _T_231) \n node _T_233 = leq(uncommonBits_4, UInt<5>(0h13)) \n node _T_234 = and(_T_232, _T_233) \n node _T_235 = and(_T_228, _T_234) \n node _T_236 = or(UInt<1>(0h0), _T_235) \n node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_239 = and(_T_237, _T_238) \n node _T_240 = or(UInt<1>(0h0), _T_239) \n node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_242 = cvt(_T_241) \n node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) \n node _T_244 = asSInt(_T_243) \n node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) \n node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_247 = cvt(_T_246) \n node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) \n node _T_249 = asSInt(_T_248) \n node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) \n node _T_251 = or(_T_245, _T_250) \n node _T_252 = and(_T_240, _T_251) \n node _T_253 = or(UInt<1>(0h0), _T_252) \n node _T_254 = and(_T_236, _T_253) \n node _T_255 = asUInt(reset) \n node _T_256 = eq(_T_255, UInt<1>(0h0)) \n when _T_256 : \n node _T_257 = eq(_T_254, UInt<1>(0h0)) \n when _T_257 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_254, UInt<1>(0h1), \"\") : assert_26 \n node _T_258 = asUInt(reset) \n node _T_259 = eq(_T_258, UInt<1>(0h0)) \n when _T_259 : \n node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_260 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_261 = asUInt(reset) \n node _T_262 = eq(_T_261, UInt<1>(0h0)) \n when _T_262 : \n node _T_263 = eq(is_aligned, UInt<1>(0h0)) \n when _T_263 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_265 = asUInt(reset) \n node _T_266 = eq(_T_265, UInt<1>(0h0)) \n when _T_266 : \n node _T_267 = eq(_T_264, UInt<1>(0h0)) \n when _T_267 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_264, UInt<1>(0h1), \"\") : assert_29 \n node _T_268 = eq(io.in.a.bits.mask, mask) \n node _T_269 = asUInt(reset) \n node _T_270 = eq(_T_269, UInt<1>(0h0)) \n when _T_270 : \n node _T_271 = eq(_T_268, UInt<1>(0h0)) \n when _T_271 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_268, UInt<1>(0h1), \"\") : assert_30 \n node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_272 : \n node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_275 = and(_T_273, _T_274) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) \n node _T_276 = shr(io.in.a.bits.source, 5) \n node _T_277 = eq(_T_276, UInt<1>(0h0)) \n node _T_278 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_279 = and(_T_277, _T_278) \n node _T_280 = leq(uncommonBits_5, UInt<5>(0h13)) \n node _T_281 = and(_T_279, _T_280) \n node _T_282 = and(_T_275, _T_281) \n node _T_283 = or(UInt<1>(0h0), _T_282) \n node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_286 = and(_T_284, _T_285) \n node _T_287 = or(UInt<1>(0h0), _T_286) \n node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_289 = cvt(_T_288) \n node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) \n node _T_291 = asSInt(_T_290) \n node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) \n node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_294 = cvt(_T_293) \n node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000))) \n node _T_296 = asSInt(_T_295) \n node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) \n node _T_298 = or(_T_292, _T_297) \n node _T_299 = and(_T_287, _T_298) \n node _T_300 = or(UInt<1>(0h0), _T_299) \n node _T_301 = and(_T_283, _T_300) \n node _T_302 = asUInt(reset) \n node _T_303 = eq(_T_302, UInt<1>(0h0)) \n when _T_303 : \n node _T_304 = eq(_T_301, UInt<1>(0h0)) \n when _T_304 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_301, UInt<1>(0h1), \"\") : assert_31 \n node _T_305 = asUInt(reset) \n node _T_306 = eq(_T_305, UInt<1>(0h0)) \n when _T_306 : \n node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_307 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_308 = asUInt(reset) \n node _T_309 = eq(_T_308, UInt<1>(0h0)) \n when _T_309 : \n node _T_310 = eq(is_aligned, UInt<1>(0h0)) \n when _T_310 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_312 = asUInt(reset) \n node _T_313 = eq(_T_312, UInt<1>(0h0)) \n when _T_313 : \n node _T_314 = eq(_T_311, UInt<1>(0h0)) \n when _T_314 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_311, UInt<1>(0h1), \"\") : assert_34 \n node _T_315 = not(mask) \n node _T_316 = and(io.in.a.bits.mask, _T_315) \n node _T_317 = eq(_T_316, UInt<1>(0h0)) \n node _T_318 = asUInt(reset) \n node _T_319 = eq(_T_318, UInt<1>(0h0)) \n when _T_319 : \n node _T_320 = eq(_T_317, UInt<1>(0h0)) \n when _T_320 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_317, UInt<1>(0h1), \"\") : assert_35 \n node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_321 : \n node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_324 = and(_T_322, _T_323) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) \n node _T_325 = shr(io.in.a.bits.source, 5) \n node _T_326 = eq(_T_325, UInt<1>(0h0)) \n node _T_327 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_328 = and(_T_326, _T_327) \n node _T_329 = leq(uncommonBits_6, UInt<5>(0h13)) \n node _T_330 = and(_T_328, _T_329) \n node _T_331 = and(_T_324, _T_330) \n node _T_332 = or(UInt<1>(0h0), _T_331) \n node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_335 = cvt(_T_334) \n node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) \n node _T_337 = asSInt(_T_336) \n node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) \n node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_340 = cvt(_T_339) \n node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000))) \n node _T_342 = asSInt(_T_341) \n node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) \n node _T_344 = or(_T_338, _T_343) \n node _T_345 = and(_T_333, _T_344) \n node _T_346 = or(UInt<1>(0h0), _T_345) \n node _T_347 = and(_T_332, _T_346) \n node _T_348 = asUInt(reset) \n node _T_349 = eq(_T_348, UInt<1>(0h0)) \n when _T_349 : \n node _T_350 = eq(_T_347, UInt<1>(0h0)) \n when _T_350 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_347, UInt<1>(0h1), \"\") : assert_36 \n node _T_351 = asUInt(reset) \n node _T_352 = eq(_T_351, UInt<1>(0h0)) \n when _T_352 : \n node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_353 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_354 = asUInt(reset) \n node _T_355 = eq(_T_354, UInt<1>(0h0)) \n when _T_355 : \n node _T_356 = eq(is_aligned, UInt<1>(0h0)) \n when _T_356 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_358 = asUInt(reset) \n node _T_359 = eq(_T_358, UInt<1>(0h0)) \n when _T_359 : \n node _T_360 = eq(_T_357, UInt<1>(0h0)) \n when _T_360 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_357, UInt<1>(0h1), \"\") : assert_39 \n node _T_361 = eq(io.in.a.bits.mask, mask) \n node _T_362 = asUInt(reset) \n node _T_363 = eq(_T_362, UInt<1>(0h0)) \n when _T_363 : \n node _T_364 = eq(_T_361, UInt<1>(0h0)) \n when _T_364 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_361, UInt<1>(0h1), \"\") : assert_40 \n node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_365 : \n node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_368 = and(_T_366, _T_367) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) \n node _T_369 = shr(io.in.a.bits.source, 5) \n node _T_370 = eq(_T_369, UInt<1>(0h0)) \n node _T_371 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_372 = and(_T_370, _T_371) \n node _T_373 = leq(uncommonBits_7, UInt<5>(0h13)) \n node _T_374 = and(_T_372, _T_373) \n node _T_375 = and(_T_368, _T_374) \n node _T_376 = or(UInt<1>(0h0), _T_375) \n node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_379 = cvt(_T_378) \n node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) \n node _T_381 = asSInt(_T_380) \n node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) \n node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_384 = cvt(_T_383) \n node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000))) \n node _T_386 = asSInt(_T_385) \n node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) \n node _T_388 = or(_T_382, _T_387) \n node _T_389 = and(_T_377, _T_388) \n node _T_390 = or(UInt<1>(0h0), _T_389) \n node _T_391 = and(_T_376, _T_390) \n node _T_392 = asUInt(reset) \n node _T_393 = eq(_T_392, UInt<1>(0h0)) \n when _T_393 : \n node _T_394 = eq(_T_391, UInt<1>(0h0)) \n when _T_394 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_391, UInt<1>(0h1), \"\") : assert_41 \n node _T_395 = asUInt(reset) \n node _T_396 = eq(_T_395, UInt<1>(0h0)) \n when _T_396 : \n node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_397 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_398 = asUInt(reset) \n node _T_399 = eq(_T_398, UInt<1>(0h0)) \n when _T_399 : \n node _T_400 = eq(is_aligned, UInt<1>(0h0)) \n when _T_400 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_402 = asUInt(reset) \n node _T_403 = eq(_T_402, UInt<1>(0h0)) \n when _T_403 : \n node _T_404 = eq(_T_401, UInt<1>(0h0)) \n when _T_404 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_401, UInt<1>(0h1), \"\") : assert_44 \n node _T_405 = eq(io.in.a.bits.mask, mask) \n node _T_406 = asUInt(reset) \n node _T_407 = eq(_T_406, UInt<1>(0h0)) \n when _T_407 : \n node _T_408 = eq(_T_405, UInt<1>(0h0)) \n when _T_408 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_405, UInt<1>(0h1), \"\") : assert_45 \n node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_409 : \n node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_412 = and(_T_410, _T_411) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) \n node _T_413 = shr(io.in.a.bits.source, 5) \n node _T_414 = eq(_T_413, UInt<1>(0h0)) \n node _T_415 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_416 = and(_T_414, _T_415) \n node _T_417 = leq(uncommonBits_8, UInt<5>(0h13)) \n node _T_418 = and(_T_416, _T_417) \n node _T_419 = and(_T_412, _T_418) \n node _T_420 = or(UInt<1>(0h0), _T_419) \n node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_423 = cvt(_T_422) \n node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000))) \n node _T_425 = asSInt(_T_424) \n node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0))) \n node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_428 = cvt(_T_427) \n node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000))) \n node _T_430 = asSInt(_T_429) \n node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) \n node _T_432 = or(_T_426, _T_431) \n node _T_433 = and(_T_421, _T_432) \n node _T_434 = or(UInt<1>(0h0), _T_433) \n node _T_435 = and(_T_420, _T_434) \n node _T_436 = asUInt(reset) \n node _T_437 = eq(_T_436, UInt<1>(0h0)) \n when _T_437 : \n node _T_438 = eq(_T_435, UInt<1>(0h0)) \n when _T_438 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_435, UInt<1>(0h1), \"\") : assert_46 \n node _T_439 = asUInt(reset) \n node _T_440 = eq(_T_439, UInt<1>(0h0)) \n when _T_440 : \n node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_441 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_442 = asUInt(reset) \n node _T_443 = eq(_T_442, UInt<1>(0h0)) \n when _T_443 : \n node _T_444 = eq(is_aligned, UInt<1>(0h0)) \n when _T_444 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_446 = asUInt(reset) \n node _T_447 = eq(_T_446, UInt<1>(0h0)) \n when _T_447 : \n node _T_448 = eq(_T_445, UInt<1>(0h0)) \n when _T_448 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_445, UInt<1>(0h1), \"\") : assert_49 \n node _T_449 = eq(io.in.a.bits.mask, mask) \n node _T_450 = asUInt(reset) \n node _T_451 = eq(_T_450, UInt<1>(0h0)) \n when _T_451 : \n node _T_452 = eq(_T_449, UInt<1>(0h0)) \n when _T_452 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_449, UInt<1>(0h1), \"\") : assert_50 \n node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_454 = asUInt(reset) \n node _T_455 = eq(_T_454, UInt<1>(0h0)) \n when _T_455 : \n node _T_456 = eq(_T_453, UInt<1>(0h0)) \n when _T_456 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_453, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_458 = asUInt(reset) \n node _T_459 = eq(_T_458, UInt<1>(0h0)) \n when _T_459 : \n node _T_460 = eq(_T_457, UInt<1>(0h0)) \n when _T_460 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_457, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) \n node _source_ok_T_6 = shr(io.in.d.bits.source, 5) \n node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) \n node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) \n node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) \n node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_11 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_461 : \n node _T_462 = asUInt(reset) \n node _T_463 = eq(_T_462, UInt<1>(0h0)) \n when _T_463 : \n node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_464 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_466 = asUInt(reset) \n node _T_467 = eq(_T_466, UInt<1>(0h0)) \n when _T_467 : \n node _T_468 = eq(_T_465, UInt<1>(0h0)) \n when _T_468 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_465, UInt<1>(0h1), \"\") : assert_54 \n node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_470 = asUInt(reset) \n node _T_471 = eq(_T_470, UInt<1>(0h0)) \n when _T_471 : \n node _T_472 = eq(_T_469, UInt<1>(0h0)) \n when _T_472 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_469, UInt<1>(0h1), \"\") : assert_55 \n node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_474 = asUInt(reset) \n node _T_475 = eq(_T_474, UInt<1>(0h0)) \n when _T_475 : \n node _T_476 = eq(_T_473, UInt<1>(0h0)) \n when _T_476 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_473, UInt<1>(0h1), \"\") : assert_56 \n node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_478 = asUInt(reset) \n node _T_479 = eq(_T_478, UInt<1>(0h0)) \n when _T_479 : \n node _T_480 = eq(_T_477, UInt<1>(0h0)) \n when _T_480 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_477, UInt<1>(0h1), \"\") : assert_57 \n node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_481 : \n node _T_482 = asUInt(reset) \n node _T_483 = eq(_T_482, UInt<1>(0h0)) \n when _T_483 : \n node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_484 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_485 = asUInt(reset) \n node _T_486 = eq(_T_485, UInt<1>(0h0)) \n when _T_486 : \n node _T_487 = eq(sink_ok, UInt<1>(0h0)) \n when _T_487 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_489 = asUInt(reset) \n node _T_490 = eq(_T_489, UInt<1>(0h0)) \n when _T_490 : \n node _T_491 = eq(_T_488, UInt<1>(0h0)) \n when _T_491 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_488, UInt<1>(0h1), \"\") : assert_60 \n node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_493 = asUInt(reset) \n node _T_494 = eq(_T_493, UInt<1>(0h0)) \n when _T_494 : \n node _T_495 = eq(_T_492, UInt<1>(0h0)) \n when _T_495 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_492, UInt<1>(0h1), \"\") : assert_61 \n node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_497 = asUInt(reset) \n node _T_498 = eq(_T_497, UInt<1>(0h0)) \n when _T_498 : \n node _T_499 = eq(_T_496, UInt<1>(0h0)) \n when _T_499 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_496, UInt<1>(0h1), \"\") : assert_62 \n node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_501 = asUInt(reset) \n node _T_502 = eq(_T_501, UInt<1>(0h0)) \n when _T_502 : \n node _T_503 = eq(_T_500, UInt<1>(0h0)) \n when _T_503 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_500, UInt<1>(0h1), \"\") : assert_63 \n node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_505 = or(UInt<1>(0h1), _T_504) \n node _T_506 = asUInt(reset) \n node _T_507 = eq(_T_506, UInt<1>(0h0)) \n when _T_507 : \n node _T_508 = eq(_T_505, UInt<1>(0h0)) \n when _T_508 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_505, UInt<1>(0h1), \"\") : assert_64 \n node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_509 : \n node _T_510 = asUInt(reset) \n node _T_511 = eq(_T_510, UInt<1>(0h0)) \n when _T_511 : \n node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_512 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_513 = asUInt(reset) \n node _T_514 = eq(_T_513, UInt<1>(0h0)) \n when _T_514 : \n node _T_515 = eq(sink_ok, UInt<1>(0h0)) \n when _T_515 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_517 = asUInt(reset) \n node _T_518 = eq(_T_517, UInt<1>(0h0)) \n when _T_518 : \n node _T_519 = eq(_T_516, UInt<1>(0h0)) \n when _T_519 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_516, UInt<1>(0h1), \"\") : assert_67 \n node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_521 = asUInt(reset) \n node _T_522 = eq(_T_521, UInt<1>(0h0)) \n when _T_522 : \n node _T_523 = eq(_T_520, UInt<1>(0h0)) \n when _T_523 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_520, UInt<1>(0h1), \"\") : assert_68 \n node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_525 = asUInt(reset) \n node _T_526 = eq(_T_525, UInt<1>(0h0)) \n when _T_526 : \n node _T_527 = eq(_T_524, UInt<1>(0h0)) \n when _T_527 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_524, UInt<1>(0h1), \"\") : assert_69 \n node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_529 = or(_T_528, io.in.d.bits.corrupt) \n node _T_530 = asUInt(reset) \n node _T_531 = eq(_T_530, UInt<1>(0h0)) \n when _T_531 : \n node _T_532 = eq(_T_529, UInt<1>(0h0)) \n when _T_532 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_529, UInt<1>(0h1), \"\") : assert_70 \n node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_534 = or(UInt<1>(0h1), _T_533) \n node _T_535 = asUInt(reset) \n node _T_536 = eq(_T_535, UInt<1>(0h0)) \n when _T_536 : \n node _T_537 = eq(_T_534, UInt<1>(0h0)) \n when _T_537 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_534, UInt<1>(0h1), \"\") : assert_71 \n node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_538 : \n node _T_539 = asUInt(reset) \n node _T_540 = eq(_T_539, UInt<1>(0h0)) \n when _T_540 : \n node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_541 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_543 = asUInt(reset) \n node _T_544 = eq(_T_543, UInt<1>(0h0)) \n when _T_544 : \n node _T_545 = eq(_T_542, UInt<1>(0h0)) \n when _T_545 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_542, UInt<1>(0h1), \"\") : assert_73 \n node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_547 = asUInt(reset) \n node _T_548 = eq(_T_547, UInt<1>(0h0)) \n when _T_548 : \n node _T_549 = eq(_T_546, UInt<1>(0h0)) \n when _T_549 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_546, UInt<1>(0h1), \"\") : assert_74 \n node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_551 = or(UInt<1>(0h1), _T_550) \n node _T_552 = asUInt(reset) \n node _T_553 = eq(_T_552, UInt<1>(0h0)) \n when _T_553 : \n node _T_554 = eq(_T_551, UInt<1>(0h0)) \n when _T_554 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_551, UInt<1>(0h1), \"\") : assert_75 \n node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_555 : \n node _T_556 = asUInt(reset) \n node _T_557 = eq(_T_556, UInt<1>(0h0)) \n when _T_557 : \n node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_558 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_560 = asUInt(reset) \n node _T_561 = eq(_T_560, UInt<1>(0h0)) \n when _T_561 : \n node _T_562 = eq(_T_559, UInt<1>(0h0)) \n when _T_562 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_559, UInt<1>(0h1), \"\") : assert_77 \n node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_564 = or(_T_563, io.in.d.bits.corrupt) \n node _T_565 = asUInt(reset) \n node _T_566 = eq(_T_565, UInt<1>(0h0)) \n when _T_566 : \n node _T_567 = eq(_T_564, UInt<1>(0h0)) \n when _T_567 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_564, UInt<1>(0h1), \"\") : assert_78 \n node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_569 = or(UInt<1>(0h1), _T_568) \n node _T_570 = asUInt(reset) \n node _T_571 = eq(_T_570, UInt<1>(0h0)) \n when _T_571 : \n node _T_572 = eq(_T_569, UInt<1>(0h0)) \n when _T_572 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_569, UInt<1>(0h1), \"\") : assert_79 \n node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_573 : \n node _T_574 = asUInt(reset) \n node _T_575 = eq(_T_574, UInt<1>(0h0)) \n when _T_575 : \n node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_576 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_578 = asUInt(reset) \n node _T_579 = eq(_T_578, UInt<1>(0h0)) \n when _T_579 : \n node _T_580 = eq(_T_577, UInt<1>(0h0)) \n when _T_580 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_577, UInt<1>(0h1), \"\") : assert_81 \n node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_582 = asUInt(reset) \n node _T_583 = eq(_T_582, UInt<1>(0h0)) \n when _T_583 : \n node _T_584 = eq(_T_581, UInt<1>(0h0)) \n when _T_584 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_581, UInt<1>(0h1), \"\") : assert_82 \n node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_586 = or(UInt<1>(0h1), _T_585) \n node _T_587 = asUInt(reset) \n node _T_588 = eq(_T_587, UInt<1>(0h0)) \n when _T_588 : \n node _T_589 = eq(_T_586, UInt<1>(0h0)) \n when _T_589 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_586, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<5>(0h0) \n connect _WIRE.bits.size, UInt<3>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_591 = asUInt(reset) \n node _T_592 = eq(_T_591, UInt<1>(0h0)) \n when _T_592 : \n node _T_593 = eq(_T_590, UInt<1>(0h0)) \n when _T_593 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_590, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<5>(0h0) \n connect _WIRE_2.bits.size, UInt<3>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_595 = asUInt(reset) \n node _T_596 = eq(_T_595, UInt<1>(0h0)) \n when _T_596 : \n node _T_597 = eq(_T_594, UInt<1>(0h0)) \n when _T_597 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_594, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_599 = asUInt(reset) \n node _T_600 = eq(_T_599, UInt<1>(0h0)) \n when _T_600 : \n node _T_601 = eq(_T_598, UInt<1>(0h0)) \n when _T_601 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_598, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_602 = eq(a_first, UInt<1>(0h0)) \n node _T_603 = and(io.in.a.valid, _T_602) \n when _T_603 : \n node _T_604 = eq(io.in.a.bits.opcode, opcode) \n node _T_605 = asUInt(reset) \n node _T_606 = eq(_T_605, UInt<1>(0h0)) \n when _T_606 : \n node _T_607 = eq(_T_604, UInt<1>(0h0)) \n when _T_607 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_604, UInt<1>(0h1), \"\") : assert_87 \n node _T_608 = eq(io.in.a.bits.param, param) \n node _T_609 = asUInt(reset) \n node _T_610 = eq(_T_609, UInt<1>(0h0)) \n when _T_610 : \n node _T_611 = eq(_T_608, UInt<1>(0h0)) \n when _T_611 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_608, UInt<1>(0h1), \"\") : assert_88 \n node _T_612 = eq(io.in.a.bits.size, size) \n node _T_613 = asUInt(reset) \n node _T_614 = eq(_T_613, UInt<1>(0h0)) \n when _T_614 : \n node _T_615 = eq(_T_612, UInt<1>(0h0)) \n when _T_615 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_612, UInt<1>(0h1), \"\") : assert_89 \n node _T_616 = eq(io.in.a.bits.source, source) \n node _T_617 = asUInt(reset) \n node _T_618 = eq(_T_617, UInt<1>(0h0)) \n when _T_618 : \n node _T_619 = eq(_T_616, UInt<1>(0h0)) \n when _T_619 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_616, UInt<1>(0h1), \"\") : assert_90 \n node _T_620 = eq(io.in.a.bits.address, address) \n node _T_621 = asUInt(reset) \n node _T_622 = eq(_T_621, UInt<1>(0h0)) \n when _T_622 : \n node _T_623 = eq(_T_620, UInt<1>(0h0)) \n when _T_623 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_620, UInt<1>(0h1), \"\") : assert_91 \n node _T_624 = and(io.in.a.ready, io.in.a.valid) \n node _T_625 = and(_T_624, a_first) \n when _T_625 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_626 = eq(d_first, UInt<1>(0h0)) \n node _T_627 = and(io.in.d.valid, _T_626) \n when _T_627 : \n node _T_628 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_629 = asUInt(reset) \n node _T_630 = eq(_T_629, UInt<1>(0h0)) \n when _T_630 : \n node _T_631 = eq(_T_628, UInt<1>(0h0)) \n when _T_631 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_628, UInt<1>(0h1), \"\") : assert_92 \n node _T_632 = eq(io.in.d.bits.param, param_1) \n node _T_633 = asUInt(reset) \n node _T_634 = eq(_T_633, UInt<1>(0h0)) \n when _T_634 : \n node _T_635 = eq(_T_632, UInt<1>(0h0)) \n when _T_635 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_632, UInt<1>(0h1), \"\") : assert_93 \n node _T_636 = eq(io.in.d.bits.size, size_1) \n node _T_637 = asUInt(reset) \n node _T_638 = eq(_T_637, UInt<1>(0h0)) \n when _T_638 : \n node _T_639 = eq(_T_636, UInt<1>(0h0)) \n when _T_639 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_636, UInt<1>(0h1), \"\") : assert_94 \n node _T_640 = eq(io.in.d.bits.source, source_1) \n node _T_641 = asUInt(reset) \n node _T_642 = eq(_T_641, UInt<1>(0h0)) \n when _T_642 : \n node _T_643 = eq(_T_640, UInt<1>(0h0)) \n when _T_643 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_640, UInt<1>(0h1), \"\") : assert_95 \n node _T_644 = eq(io.in.d.bits.sink, sink) \n node _T_645 = asUInt(reset) \n node _T_646 = eq(_T_645, UInt<1>(0h0)) \n when _T_646 : \n node _T_647 = eq(_T_644, UInt<1>(0h0)) \n when _T_647 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_644, UInt<1>(0h1), \"\") : assert_96 \n node _T_648 = eq(io.in.d.bits.denied, denied) \n node _T_649 = asUInt(reset) \n node _T_650 = eq(_T_649, UInt<1>(0h0)) \n when _T_650 : \n node _T_651 = eq(_T_648, UInt<1>(0h0)) \n when _T_651 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_648, UInt<1>(0h1), \"\") : assert_97 \n node _T_652 = and(io.in.d.ready, io.in.d.valid) \n node _T_653 = and(_T_652, d_first) \n when _T_653 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0) \n regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0) \n regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<20> \n connect a_set, UInt<20>(0h0) \n wire a_set_wo_ready : UInt<20> \n connect a_set_wo_ready, UInt<20>(0h0) \n wire a_opcodes_set : UInt<80> \n connect a_opcodes_set, UInt<80>(0h0) \n wire a_sizes_set : UInt<80> \n connect a_sizes_set, UInt<80>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<4> \n connect a_sizes_set_interm, UInt<4>(0h0) \n node _T_654 = and(io.in.a.valid, a_first_1) \n node _T_655 = and(_T_654, UInt<1>(0h1)) \n when _T_655 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_656 = and(io.in.a.ready, io.in.a.valid) \n node _T_657 = and(_T_656, a_first_1) \n node _T_658 = and(_T_657, UInt<1>(0h1)) \n when _T_658 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_659 = dshr(inflight, io.in.a.bits.source) \n node _T_660 = bits(_T_659, 0, 0) \n node _T_661 = eq(_T_660, UInt<1>(0h0)) \n node _T_662 = asUInt(reset) \n node _T_663 = eq(_T_662, UInt<1>(0h0)) \n when _T_663 : \n node _T_664 = eq(_T_661, UInt<1>(0h0)) \n when _T_664 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_661, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<20> \n connect d_clr, UInt<20>(0h0) \n wire d_clr_wo_ready : UInt<20> \n connect d_clr_wo_ready, UInt<20>(0h0) \n wire d_opcodes_clr : UInt<80> \n connect d_opcodes_clr, UInt<80>(0h0) \n wire d_sizes_clr : UInt<80> \n connect d_sizes_clr, UInt<80>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_665 = and(io.in.d.valid, d_first_1) \n node _T_666 = and(_T_665, UInt<1>(0h1)) \n node _T_667 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_668 = and(_T_666, _T_667) \n when _T_668 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_669 = and(io.in.d.ready, io.in.d.valid) \n node _T_670 = and(_T_669, d_first_1) \n node _T_671 = and(_T_670, UInt<1>(0h1)) \n node _T_672 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_673 = and(_T_671, _T_672) \n when _T_673 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_674 = and(io.in.d.valid, d_first_1) \n node _T_675 = and(_T_674, UInt<1>(0h1)) \n node _T_676 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_677 = and(_T_675, _T_676) \n when _T_677 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_678 = dshr(inflight, io.in.d.bits.source) \n node _T_679 = bits(_T_678, 0, 0) \n node _T_680 = or(_T_679, same_cycle_resp) \n node _T_681 = asUInt(reset) \n node _T_682 = eq(_T_681, UInt<1>(0h0)) \n when _T_682 : \n node _T_683 = eq(_T_680, UInt<1>(0h0)) \n when _T_683 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_680, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_686 = or(_T_684, _T_685) \n node _T_687 = asUInt(reset) \n node _T_688 = eq(_T_687, UInt<1>(0h0)) \n when _T_688 : \n node _T_689 = eq(_T_686, UInt<1>(0h0)) \n when _T_689 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_686, UInt<1>(0h1), \"\") : assert_100 \n node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_691 = asUInt(reset) \n node _T_692 = eq(_T_691, UInt<1>(0h0)) \n when _T_692 : \n node _T_693 = eq(_T_690, UInt<1>(0h0)) \n when _T_693 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_690, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_696 = or(_T_694, _T_695) \n node _T_697 = asUInt(reset) \n node _T_698 = eq(_T_697, UInt<1>(0h0)) \n when _T_698 : \n node _T_699 = eq(_T_696, UInt<1>(0h0)) \n when _T_699 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_696, UInt<1>(0h1), \"\") : assert_102 \n node _T_700 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_701 = asUInt(reset) \n node _T_702 = eq(_T_701, UInt<1>(0h0)) \n when _T_702 : \n node _T_703 = eq(_T_700, UInt<1>(0h0)) \n when _T_703 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_700, UInt<1>(0h1), \"\") : assert_103 \n node _T_704 = and(io.in.d.valid, d_first_1) \n node _T_705 = and(_T_704, a_first_1) \n node _T_706 = and(_T_705, io.in.a.valid) \n node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_708 = and(_T_706, _T_707) \n node _T_709 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_710 = and(_T_708, _T_709) \n when _T_710 : \n node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_712 = or(_T_711, io.in.a.ready) \n node _T_713 = asUInt(reset) \n node _T_714 = eq(_T_713, UInt<1>(0h0)) \n when _T_714 : \n node _T_715 = eq(_T_712, UInt<1>(0h0)) \n when _T_715 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_712, UInt<1>(0h1), \"\") : assert_104 \n node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_717 = orr(a_set_wo_ready) \n node _T_718 = eq(_T_717, UInt<1>(0h0)) \n node _T_719 = or(_T_716, _T_718) \n node _T_720 = asUInt(reset) \n node _T_721 = eq(_T_720, UInt<1>(0h0)) \n when _T_721 : \n node _T_722 = eq(_T_719, UInt<1>(0h0)) \n when _T_722 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_719, UInt<1>(0h1), \"\") : assert_105 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_80 \n node _T_723 = orr(inflight) \n node _T_724 = eq(_T_723, UInt<1>(0h0)) \n node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_726 = or(_T_724, _T_725) \n node _T_727 = lt(watchdog, plusarg_reader.out) \n node _T_728 = or(_T_726, _T_727) \n node _T_729 = asUInt(reset) \n node _T_730 = eq(_T_729, UInt<1>(0h0)) \n when _T_730 : \n node _T_731 = eq(_T_728, UInt<1>(0h0)) \n when _T_731 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_728, UInt<1>(0h1), \"\") : assert_106 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_732 = and(io.in.a.ready, io.in.a.valid) \n node _T_733 = and(io.in.d.ready, io.in.d.valid) \n node _T_734 = or(_T_732, _T_733) \n when _T_734 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0) \n regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0) \n regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE.bits.source, UInt<5>(0h0) \n connect _c_first_WIRE.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<20> \n connect c_set, UInt<20>(0h0) \n wire c_set_wo_ready : UInt<20> \n connect c_set_wo_ready, UInt<20>(0h0) \n wire c_opcodes_set : UInt<80> \n connect c_opcodes_set, UInt<80>(0h0) \n wire c_sizes_set : UInt<80> \n connect c_sizes_set, UInt<80>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<4> \n connect c_sizes_set_interm, UInt<4>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<5>(0h0) \n connect _WIRE_6.bits.size, UInt<3>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_735 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<5>(0h0) \n connect _WIRE_8.bits.size, UInt<3>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_738 = and(_T_736, _T_737) \n node _T_739 = and(_T_735, _T_738) \n when _T_739 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<32>(0h0) \n connect _WIRE_10.bits.source, UInt<5>(0h0) \n connect _WIRE_10.bits.size, UInt<3>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_741 = and(_T_740, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<32>(0h0) \n connect _WIRE_12.bits.source, UInt<5>(0h0) \n connect _WIRE_12.bits.size, UInt<3>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_744 = and(_T_742, _T_743) \n node _T_745 = and(_T_741, _T_744) \n when _T_745 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_WIRE.bits.source, UInt<5>(0h0) \n connect _c_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<32>(0h0) \n connect _WIRE_14.bits.source, UInt<5>(0h0) \n connect _WIRE_14.bits.size, UInt<3>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_746 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_747 = bits(_T_746, 0, 0) \n node _T_748 = eq(_T_747, UInt<1>(0h0)) \n node _T_749 = asUInt(reset) \n node _T_750 = eq(_T_749, UInt<1>(0h0)) \n when _T_750 : \n node _T_751 = eq(_T_748, UInt<1>(0h0)) \n when _T_751 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_748, UInt<1>(0h1), \"\") : assert_107 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<20> \n connect d_clr_1, UInt<20>(0h0) \n wire d_clr_wo_ready_1 : UInt<20> \n connect d_clr_wo_ready_1, UInt<20>(0h0) \n wire d_opcodes_clr_1 : UInt<80> \n connect d_opcodes_clr_1, UInt<80>(0h0) \n wire d_sizes_clr_1 : UInt<80> \n connect d_sizes_clr_1, UInt<80>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_752 = and(io.in.d.valid, d_first_2) \n node _T_753 = and(_T_752, UInt<1>(0h1)) \n node _T_754 = and(_T_753, d_release_ack_1) \n when _T_754 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_755 = and(io.in.d.ready, io.in.d.valid) \n node _T_756 = and(_T_755, d_first_2) \n node _T_757 = and(_T_756, UInt<1>(0h1)) \n node _T_758 = and(_T_757, d_release_ack_1) \n when _T_758 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_759 = and(io.in.d.valid, d_first_2) \n node _T_760 = and(_T_759, UInt<1>(0h1)) \n node _T_761 = and(_T_760, d_release_ack_1) \n when _T_761 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_762 = dshr(inflight_1, io.in.d.bits.source) \n node _T_763 = bits(_T_762, 0, 0) \n node _T_764 = or(_T_763, same_cycle_resp_1) \n node _T_765 = asUInt(reset) \n node _T_766 = eq(_T_765, UInt<1>(0h0)) \n when _T_766 : \n node _T_767 = eq(_T_764, UInt<1>(0h0)) \n when _T_767 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_764, UInt<1>(0h1), \"\") : assert_108 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<32>(0h0) \n connect _WIRE_16.bits.source, UInt<5>(0h0) \n connect _WIRE_16.bits.size, UInt<3>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_769 = asUInt(reset) \n node _T_770 = eq(_T_769, UInt<1>(0h0)) \n when _T_770 : \n node _T_771 = eq(_T_768, UInt<1>(0h0)) \n when _T_771 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_768, UInt<1>(0h1), \"\") : assert_109 \n else :\n\n node _T_772 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_773 = asUInt(reset) \n node _T_774 = eq(_T_773, UInt<1>(0h0)) \n when _T_774 : \n node _T_775 = eq(_T_772, UInt<1>(0h0)) \n when _T_775 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_772, UInt<1>(0h1), \"\") : assert_110 \n node _T_776 = and(io.in.d.valid, d_first_2) \n node _T_777 = and(_T_776, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<32>(0h0) \n connect _WIRE_18.bits.source, UInt<5>(0h0) \n connect _WIRE_18.bits.size, UInt<3>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_778 = and(_T_777, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<32>(0h0) \n connect _WIRE_20.bits.source, UInt<5>(0h0) \n connect _WIRE_20.bits.size, UInt<3>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_780 = and(_T_778, _T_779) \n node _T_781 = and(_T_780, d_release_ack_1) \n node _T_782 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_783 = and(_T_781, _T_782) \n when _T_783 : \n node _T_784 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<32>(0h0) \n connect _WIRE_22.bits.source, UInt<5>(0h0) \n connect _WIRE_22.bits.size, UInt<3>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_785 = or(_T_784, _WIRE_23.ready) \n node _T_786 = asUInt(reset) \n node _T_787 = eq(_T_786, UInt<1>(0h0)) \n when _T_787 : \n node _T_788 = eq(_T_785, UInt<1>(0h0)) \n when _T_788 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_785, UInt<1>(0h1), \"\") : assert_111 \n node _T_789 = orr(c_set_wo_ready) \n when _T_789 : \n node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_791 = asUInt(reset) \n node _T_792 = eq(_T_791, UInt<1>(0h0)) \n when _T_792 : \n node _T_793 = eq(_T_790, UInt<1>(0h0)) \n when _T_793 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_790, UInt<1>(0h1), \"\") : assert_112 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_81 \n node _T_794 = orr(inflight_1) \n node _T_795 = eq(_T_794, UInt<1>(0h0)) \n node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_797 = or(_T_795, _T_796) \n node _T_798 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_799 = or(_T_797, _T_798) \n node _T_800 = asUInt(reset) \n node _T_801 = eq(_T_800, UInt<1>(0h0)) \n when _T_801 : \n node _T_802 = eq(_T_799, UInt<1>(0h0)) \n when _T_802 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, _T_799, UInt<1>(0h1), \"\") : assert_113 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<32>(0h0) \n connect _WIRE_24.bits.source, UInt<5>(0h0) \n connect _WIRE_24.bits.size, UInt<3>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_804 = and(io.in.d.ready, io.in.d.valid) \n node _T_805 = or(_T_803, _T_804) \n when _T_805 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_40(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [4:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [4:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _source_ok_T_6 = 1'h0;\t// @[Parameters.scala:54:10]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _source_ok_T_7 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:54:67]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_first_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_first_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_first_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_first_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [258:0] _c_opcodes_set_T_1 = 259'h0;\t// @[Monitor.scala:767:54]\n wire [258:0] _c_sizes_set_T_1 = 259'h0;\t// @[Monitor.scala:768:52]\n wire [7:0] _c_opcodes_set_T = 8'h0;\t// @[Monitor.scala:767:79]\n wire [7:0] _c_sizes_set_T = 8'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [31:0] _c_set_wo_ready_T = 32'h1;\t// @[OneHot.scala:58:35]\n wire [31:0] _c_set_T = 32'h1;\t// @[OneHot.scala:58:35]\n wire [79:0] c_opcodes_set = 80'h0;\t// @[Monitor.scala:740:34]\n wire [79:0] c_sizes_set = 80'h0;\t// @[Monitor.scala:741:34]\n wire [19:0] c_set = 20'h0;\t// @[Monitor.scala:738:34]\n wire [19:0] c_set_wo_ready = 20'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_4;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [4:0] uncommonBits = _uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_1 = _uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_2 = _uncommonBits_T_2;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_3 = _uncommonBits_T_3;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_4 = _uncommonBits_T_4;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_5 = _uncommonBits_T_5;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_6 = _uncommonBits_T_6;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_7 = _uncommonBits_T_7;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_8 = _uncommonBits_T_8;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_10;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_732;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_732;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [4:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_805;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_805;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_805;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [4:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [19:0] inflight;\t// @[Monitor.scala:614:27]\n reg [79:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [79:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [19:0] a_set;\t// @[Monitor.scala:626:34]\n wire [19:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [79:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [79:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [7:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [7:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [7:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [7:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [7:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [7:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [7:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [7:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [31:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [31:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_658 = _T_732 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [7:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [7:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [19:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [19:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [79:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [79:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_704 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_673 = _T_805 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [19:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [19:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [19:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [19:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [79:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [79:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [19:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [19:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [79:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [79:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_776 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_758 = _T_805 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [19:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32179,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T \n node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_lo = cat(mask_acc_1, mask_acc) \n node mask_hi = cat(mask_acc_3, mask_acc_2) \n node mask = cat(mask_hi, mask_lo) \n node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_7 = cvt(_T_6) \n node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) \n node _T_9 = asSInt(_T_8) \n node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) \n node _T_11 = or(_T_5, _T_10) \n node _T_12 = asUInt(reset) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n when _T_13 : \n node _T_14 = eq(_T_11, UInt<1>(0h0)) \n when _T_14 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_11, UInt<1>(0h1), \"\") : assert_1 \n node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_15 : \n node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_17 = and(UInt<1>(0h0), _T_16) \n node _T_18 = or(UInt<1>(0h0), _T_17) \n node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_21 = cvt(_T_20) \n node _T_22 = and(_T_21, asSInt(UInt<10>(0h200))) \n node _T_23 = asSInt(_T_22) \n node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) \n node _T_25 = and(_T_19, _T_24) \n node _T_26 = or(UInt<1>(0h0), _T_25) \n node _T_27 = and(_T_18, _T_26) \n node _T_28 = asUInt(reset) \n node _T_29 = eq(_T_28, UInt<1>(0h0)) \n when _T_29 : \n node _T_30 = eq(_T_27, UInt<1>(0h0)) \n when _T_30 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_27, UInt<1>(0h1), \"\") : assert_2 \n node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_33 = and(_T_31, _T_32) \n node _T_34 = or(UInt<1>(0h0), _T_33) \n node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_36 = cvt(_T_35) \n node _T_37 = and(_T_36, asSInt(UInt<10>(0h200))) \n node _T_38 = asSInt(_T_37) \n node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) \n node _T_40 = and(_T_34, _T_39) \n node _T_41 = or(UInt<1>(0h0), _T_40) \n node _T_42 = and(UInt<1>(0h0), _T_41) \n node _T_43 = asUInt(reset) \n node _T_44 = eq(_T_43, UInt<1>(0h0)) \n when _T_44 : \n node _T_45 = eq(_T_42, UInt<1>(0h0)) \n when _T_45 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_42, UInt<1>(0h1), \"\") : assert_3 \n node _T_46 = asUInt(reset) \n node _T_47 = eq(_T_46, UInt<1>(0h0)) \n when _T_47 : \n node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_48 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_50 = asUInt(reset) \n node _T_51 = eq(_T_50, UInt<1>(0h0)) \n when _T_51 : \n node _T_52 = eq(_T_49, UInt<1>(0h0)) \n when _T_52 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_49, UInt<1>(0h1), \"\") : assert_5 \n node _T_53 = asUInt(reset) \n node _T_54 = eq(_T_53, UInt<1>(0h0)) \n when _T_54 : \n node _T_55 = eq(is_aligned, UInt<1>(0h0)) \n when _T_55 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_57 = asUInt(reset) \n node _T_58 = eq(_T_57, UInt<1>(0h0)) \n when _T_58 : \n node _T_59 = eq(_T_56, UInt<1>(0h0)) \n when _T_59 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_56, UInt<1>(0h1), \"\") : assert_7 \n node _T_60 = not(io.in.a.bits.mask) \n node _T_61 = eq(_T_60, UInt<1>(0h0)) \n node _T_62 = asUInt(reset) \n node _T_63 = eq(_T_62, UInt<1>(0h0)) \n when _T_63 : \n node _T_64 = eq(_T_61, UInt<1>(0h0)) \n when _T_64 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_61, UInt<1>(0h1), \"\") : assert_8 \n node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_66 = asUInt(reset) \n node _T_67 = eq(_T_66, UInt<1>(0h0)) \n when _T_67 : \n node _T_68 = eq(_T_65, UInt<1>(0h0)) \n when _T_68 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_65, UInt<1>(0h1), \"\") : assert_9 \n node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_69 : \n node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_71 = and(UInt<1>(0h0), _T_70) \n node _T_72 = or(UInt<1>(0h0), _T_71) \n node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_75 = cvt(_T_74) \n node _T_76 = and(_T_75, asSInt(UInt<10>(0h200))) \n node _T_77 = asSInt(_T_76) \n node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) \n node _T_79 = and(_T_73, _T_78) \n node _T_80 = or(UInt<1>(0h0), _T_79) \n node _T_81 = and(_T_72, _T_80) \n node _T_82 = asUInt(reset) \n node _T_83 = eq(_T_82, UInt<1>(0h0)) \n when _T_83 : \n node _T_84 = eq(_T_81, UInt<1>(0h0)) \n when _T_84 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_81, UInt<1>(0h1), \"\") : assert_10 \n node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_87 = and(_T_85, _T_86) \n node _T_88 = or(UInt<1>(0h0), _T_87) \n node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_90 = cvt(_T_89) \n node _T_91 = and(_T_90, asSInt(UInt<10>(0h200))) \n node _T_92 = asSInt(_T_91) \n node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) \n node _T_94 = and(_T_88, _T_93) \n node _T_95 = or(UInt<1>(0h0), _T_94) \n node _T_96 = and(UInt<1>(0h0), _T_95) \n node _T_97 = asUInt(reset) \n node _T_98 = eq(_T_97, UInt<1>(0h0)) \n when _T_98 : \n node _T_99 = eq(_T_96, UInt<1>(0h0)) \n when _T_99 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_96, UInt<1>(0h1), \"\") : assert_11 \n node _T_100 = asUInt(reset) \n node _T_101 = eq(_T_100, UInt<1>(0h0)) \n when _T_101 : \n node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_102 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_104 = asUInt(reset) \n node _T_105 = eq(_T_104, UInt<1>(0h0)) \n when _T_105 : \n node _T_106 = eq(_T_103, UInt<1>(0h0)) \n when _T_106 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_103, UInt<1>(0h1), \"\") : assert_13 \n node _T_107 = asUInt(reset) \n node _T_108 = eq(_T_107, UInt<1>(0h0)) \n when _T_108 : \n node _T_109 = eq(is_aligned, UInt<1>(0h0)) \n when _T_109 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_111 = asUInt(reset) \n node _T_112 = eq(_T_111, UInt<1>(0h0)) \n when _T_112 : \n node _T_113 = eq(_T_110, UInt<1>(0h0)) \n when _T_113 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_110, UInt<1>(0h1), \"\") : assert_15 \n node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_115 = asUInt(reset) \n node _T_116 = eq(_T_115, UInt<1>(0h0)) \n when _T_116 : \n node _T_117 = eq(_T_114, UInt<1>(0h0)) \n when _T_117 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_114, UInt<1>(0h1), \"\") : assert_16 \n node _T_118 = not(io.in.a.bits.mask) \n node _T_119 = eq(_T_118, UInt<1>(0h0)) \n node _T_120 = asUInt(reset) \n node _T_121 = eq(_T_120, UInt<1>(0h0)) \n when _T_121 : \n node _T_122 = eq(_T_119, UInt<1>(0h0)) \n when _T_122 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_119, UInt<1>(0h1), \"\") : assert_17 \n node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_124 = asUInt(reset) \n node _T_125 = eq(_T_124, UInt<1>(0h0)) \n when _T_125 : \n node _T_126 = eq(_T_123, UInt<1>(0h0)) \n when _T_126 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_123, UInt<1>(0h1), \"\") : assert_18 \n node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_127 : \n node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size) \n node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_130 = and(_T_128, _T_129) \n node _T_131 = or(UInt<1>(0h0), _T_130) \n node _T_132 = asUInt(reset) \n node _T_133 = eq(_T_132, UInt<1>(0h0)) \n when _T_133 : \n node _T_134 = eq(_T_131, UInt<1>(0h0)) \n when _T_134 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_131, UInt<1>(0h1), \"\") : assert_19 \n node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_137 = and(_T_135, _T_136) \n node _T_138 = or(UInt<1>(0h0), _T_137) \n node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_140 = cvt(_T_139) \n node _T_141 = and(_T_140, asSInt(UInt<10>(0h200))) \n node _T_142 = asSInt(_T_141) \n node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) \n node _T_144 = and(_T_138, _T_143) \n node _T_145 = or(UInt<1>(0h0), _T_144) \n node _T_146 = asUInt(reset) \n node _T_147 = eq(_T_146, UInt<1>(0h0)) \n when _T_147 : \n node _T_148 = eq(_T_145, UInt<1>(0h0)) \n when _T_148 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_145, UInt<1>(0h1), \"\") : assert_20 \n node _T_149 = asUInt(reset) \n node _T_150 = eq(_T_149, UInt<1>(0h0)) \n when _T_150 : \n node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_151 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_152 = asUInt(reset) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n when _T_153 : \n node _T_154 = eq(is_aligned, UInt<1>(0h0)) \n when _T_154 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_156 = asUInt(reset) \n node _T_157 = eq(_T_156, UInt<1>(0h0)) \n when _T_157 : \n node _T_158 = eq(_T_155, UInt<1>(0h0)) \n when _T_158 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_155, UInt<1>(0h1), \"\") : assert_23 \n node _T_159 = eq(io.in.a.bits.mask, mask) \n node _T_160 = asUInt(reset) \n node _T_161 = eq(_T_160, UInt<1>(0h0)) \n when _T_161 : \n node _T_162 = eq(_T_159, UInt<1>(0h0)) \n when _T_162 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_159, UInt<1>(0h1), \"\") : assert_24 \n node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_164 = asUInt(reset) \n node _T_165 = eq(_T_164, UInt<1>(0h0)) \n when _T_165 : \n node _T_166 = eq(_T_163, UInt<1>(0h0)) \n when _T_166 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_163, UInt<1>(0h1), \"\") : assert_25 \n node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_167 : \n node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size) \n node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_170 = and(_T_168, _T_169) \n node _T_171 = or(UInt<1>(0h0), _T_170) \n node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_174 = and(_T_172, _T_173) \n node _T_175 = or(UInt<1>(0h0), _T_174) \n node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_177 = cvt(_T_176) \n node _T_178 = and(_T_177, asSInt(UInt<10>(0h200))) \n node _T_179 = asSInt(_T_178) \n node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) \n node _T_181 = and(_T_175, _T_180) \n node _T_182 = or(UInt<1>(0h0), _T_181) \n node _T_183 = and(_T_171, _T_182) \n node _T_184 = asUInt(reset) \n node _T_185 = eq(_T_184, UInt<1>(0h0)) \n when _T_185 : \n node _T_186 = eq(_T_183, UInt<1>(0h0)) \n when _T_186 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_183, UInt<1>(0h1), \"\") : assert_26 \n node _T_187 = asUInt(reset) \n node _T_188 = eq(_T_187, UInt<1>(0h0)) \n when _T_188 : \n node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_189 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_190 = asUInt(reset) \n node _T_191 = eq(_T_190, UInt<1>(0h0)) \n when _T_191 : \n node _T_192 = eq(is_aligned, UInt<1>(0h0)) \n when _T_192 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_194 = asUInt(reset) \n node _T_195 = eq(_T_194, UInt<1>(0h0)) \n when _T_195 : \n node _T_196 = eq(_T_193, UInt<1>(0h0)) \n when _T_196 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_193, UInt<1>(0h1), \"\") : assert_29 \n node _T_197 = eq(io.in.a.bits.mask, mask) \n node _T_198 = asUInt(reset) \n node _T_199 = eq(_T_198, UInt<1>(0h0)) \n when _T_199 : \n node _T_200 = eq(_T_197, UInt<1>(0h0)) \n when _T_200 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_197, UInt<1>(0h1), \"\") : assert_30 \n node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_201 : \n node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_203 = and(UInt<1>(0h0), _T_202) \n node _T_204 = or(UInt<1>(0h0), _T_203) \n node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_207 = and(_T_205, _T_206) \n node _T_208 = or(UInt<1>(0h0), _T_207) \n node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_210 = cvt(_T_209) \n node _T_211 = and(_T_210, asSInt(UInt<10>(0h200))) \n node _T_212 = asSInt(_T_211) \n node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) \n node _T_214 = and(_T_208, _T_213) \n node _T_215 = or(UInt<1>(0h0), _T_214) \n node _T_216 = and(_T_204, _T_215) \n node _T_217 = asUInt(reset) \n node _T_218 = eq(_T_217, UInt<1>(0h0)) \n when _T_218 : \n node _T_219 = eq(_T_216, UInt<1>(0h0)) \n when _T_219 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_216, UInt<1>(0h1), \"\") : assert_31 \n node _T_220 = asUInt(reset) \n node _T_221 = eq(_T_220, UInt<1>(0h0)) \n when _T_221 : \n node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_222 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_223 = asUInt(reset) \n node _T_224 = eq(_T_223, UInt<1>(0h0)) \n when _T_224 : \n node _T_225 = eq(is_aligned, UInt<1>(0h0)) \n when _T_225 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_227 = asUInt(reset) \n node _T_228 = eq(_T_227, UInt<1>(0h0)) \n when _T_228 : \n node _T_229 = eq(_T_226, UInt<1>(0h0)) \n when _T_229 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_226, UInt<1>(0h1), \"\") : assert_34 \n node _T_230 = not(mask) \n node _T_231 = and(io.in.a.bits.mask, _T_230) \n node _T_232 = eq(_T_231, UInt<1>(0h0)) \n node _T_233 = asUInt(reset) \n node _T_234 = eq(_T_233, UInt<1>(0h0)) \n when _T_234 : \n node _T_235 = eq(_T_232, UInt<1>(0h0)) \n when _T_235 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_232, UInt<1>(0h1), \"\") : assert_35 \n node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_236 : \n node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_238 = and(UInt<1>(0h0), _T_237) \n node _T_239 = or(UInt<1>(0h0), _T_238) \n node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_242 = cvt(_T_241) \n node _T_243 = and(_T_242, asSInt(UInt<10>(0h200))) \n node _T_244 = asSInt(_T_243) \n node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) \n node _T_246 = and(_T_240, _T_245) \n node _T_247 = or(UInt<1>(0h0), _T_246) \n node _T_248 = and(_T_239, _T_247) \n node _T_249 = asUInt(reset) \n node _T_250 = eq(_T_249, UInt<1>(0h0)) \n when _T_250 : \n node _T_251 = eq(_T_248, UInt<1>(0h0)) \n when _T_251 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_248, UInt<1>(0h1), \"\") : assert_36 \n node _T_252 = asUInt(reset) \n node _T_253 = eq(_T_252, UInt<1>(0h0)) \n when _T_253 : \n node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_254 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_255 = asUInt(reset) \n node _T_256 = eq(_T_255, UInt<1>(0h0)) \n when _T_256 : \n node _T_257 = eq(is_aligned, UInt<1>(0h0)) \n when _T_257 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_259 = asUInt(reset) \n node _T_260 = eq(_T_259, UInt<1>(0h0)) \n when _T_260 : \n node _T_261 = eq(_T_258, UInt<1>(0h0)) \n when _T_261 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_258, UInt<1>(0h1), \"\") : assert_39 \n node _T_262 = eq(io.in.a.bits.mask, mask) \n node _T_263 = asUInt(reset) \n node _T_264 = eq(_T_263, UInt<1>(0h0)) \n when _T_264 : \n node _T_265 = eq(_T_262, UInt<1>(0h0)) \n when _T_265 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_262, UInt<1>(0h1), \"\") : assert_40 \n node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_266 : \n node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_268 = and(UInt<1>(0h0), _T_267) \n node _T_269 = or(UInt<1>(0h0), _T_268) \n node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_272 = cvt(_T_271) \n node _T_273 = and(_T_272, asSInt(UInt<10>(0h200))) \n node _T_274 = asSInt(_T_273) \n node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) \n node _T_276 = and(_T_270, _T_275) \n node _T_277 = or(UInt<1>(0h0), _T_276) \n node _T_278 = and(_T_269, _T_277) \n node _T_279 = asUInt(reset) \n node _T_280 = eq(_T_279, UInt<1>(0h0)) \n when _T_280 : \n node _T_281 = eq(_T_278, UInt<1>(0h0)) \n when _T_281 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_278, UInt<1>(0h1), \"\") : assert_41 \n node _T_282 = asUInt(reset) \n node _T_283 = eq(_T_282, UInt<1>(0h0)) \n when _T_283 : \n node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_284 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_285 = asUInt(reset) \n node _T_286 = eq(_T_285, UInt<1>(0h0)) \n when _T_286 : \n node _T_287 = eq(is_aligned, UInt<1>(0h0)) \n when _T_287 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_289 = asUInt(reset) \n node _T_290 = eq(_T_289, UInt<1>(0h0)) \n when _T_290 : \n node _T_291 = eq(_T_288, UInt<1>(0h0)) \n when _T_291 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_288, UInt<1>(0h1), \"\") : assert_44 \n node _T_292 = eq(io.in.a.bits.mask, mask) \n node _T_293 = asUInt(reset) \n node _T_294 = eq(_T_293, UInt<1>(0h0)) \n when _T_294 : \n node _T_295 = eq(_T_292, UInt<1>(0h0)) \n when _T_295 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_292, UInt<1>(0h1), \"\") : assert_45 \n node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_296 : \n node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_298 = and(UInt<1>(0h0), _T_297) \n node _T_299 = or(UInt<1>(0h0), _T_298) \n node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_302 = cvt(_T_301) \n node _T_303 = and(_T_302, asSInt(UInt<10>(0h200))) \n node _T_304 = asSInt(_T_303) \n node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) \n node _T_306 = and(_T_300, _T_305) \n node _T_307 = or(UInt<1>(0h0), _T_306) \n node _T_308 = and(_T_299, _T_307) \n node _T_309 = asUInt(reset) \n node _T_310 = eq(_T_309, UInt<1>(0h0)) \n when _T_310 : \n node _T_311 = eq(_T_308, UInt<1>(0h0)) \n when _T_311 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_308, UInt<1>(0h1), \"\") : assert_46 \n node _T_312 = asUInt(reset) \n node _T_313 = eq(_T_312, UInt<1>(0h0)) \n when _T_313 : \n node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_314 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_315 = asUInt(reset) \n node _T_316 = eq(_T_315, UInt<1>(0h0)) \n when _T_316 : \n node _T_317 = eq(is_aligned, UInt<1>(0h0)) \n when _T_317 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_319 = asUInt(reset) \n node _T_320 = eq(_T_319, UInt<1>(0h0)) \n when _T_320 : \n node _T_321 = eq(_T_318, UInt<1>(0h0)) \n when _T_321 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_318, UInt<1>(0h1), \"\") : assert_49 \n node _T_322 = eq(io.in.a.bits.mask, mask) \n node _T_323 = asUInt(reset) \n node _T_324 = eq(_T_323, UInt<1>(0h0)) \n when _T_324 : \n node _T_325 = eq(_T_322, UInt<1>(0h0)) \n when _T_325 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_322, UInt<1>(0h1), \"\") : assert_50 \n node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_327 = asUInt(reset) \n node _T_328 = eq(_T_327, UInt<1>(0h0)) \n when _T_328 : \n node _T_329 = eq(_T_326, UInt<1>(0h0)) \n when _T_329 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_326, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_331 = asUInt(reset) \n node _T_332 = eq(_T_331, UInt<1>(0h0)) \n when _T_332 : \n node _T_333 = eq(_T_330, UInt<1>(0h0)) \n when _T_333 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_330, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_1 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_334 : \n node _T_335 = asUInt(reset) \n node _T_336 = eq(_T_335, UInt<1>(0h0)) \n when _T_336 : \n node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_337 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_339 = asUInt(reset) \n node _T_340 = eq(_T_339, UInt<1>(0h0)) \n when _T_340 : \n node _T_341 = eq(_T_338, UInt<1>(0h0)) \n when _T_341 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_338, UInt<1>(0h1), \"\") : assert_54 \n node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_343 = asUInt(reset) \n node _T_344 = eq(_T_343, UInt<1>(0h0)) \n when _T_344 : \n node _T_345 = eq(_T_342, UInt<1>(0h0)) \n when _T_345 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_342, UInt<1>(0h1), \"\") : assert_55 \n node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_347 = asUInt(reset) \n node _T_348 = eq(_T_347, UInt<1>(0h0)) \n when _T_348 : \n node _T_349 = eq(_T_346, UInt<1>(0h0)) \n when _T_349 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_346, UInt<1>(0h1), \"\") : assert_56 \n node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_351 = asUInt(reset) \n node _T_352 = eq(_T_351, UInt<1>(0h0)) \n when _T_352 : \n node _T_353 = eq(_T_350, UInt<1>(0h0)) \n when _T_353 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_350, UInt<1>(0h1), \"\") : assert_57 \n node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_354 : \n node _T_355 = asUInt(reset) \n node _T_356 = eq(_T_355, UInt<1>(0h0)) \n when _T_356 : \n node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_357 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_358 = asUInt(reset) \n node _T_359 = eq(_T_358, UInt<1>(0h0)) \n when _T_359 : \n node _T_360 = eq(sink_ok, UInt<1>(0h0)) \n when _T_360 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_362 = asUInt(reset) \n node _T_363 = eq(_T_362, UInt<1>(0h0)) \n when _T_363 : \n node _T_364 = eq(_T_361, UInt<1>(0h0)) \n when _T_364 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_361, UInt<1>(0h1), \"\") : assert_60 \n node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_366 = asUInt(reset) \n node _T_367 = eq(_T_366, UInt<1>(0h0)) \n when _T_367 : \n node _T_368 = eq(_T_365, UInt<1>(0h0)) \n when _T_368 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_365, UInt<1>(0h1), \"\") : assert_61 \n node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_370 = asUInt(reset) \n node _T_371 = eq(_T_370, UInt<1>(0h0)) \n when _T_371 : \n node _T_372 = eq(_T_369, UInt<1>(0h0)) \n when _T_372 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_369, UInt<1>(0h1), \"\") : assert_62 \n node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_374 = asUInt(reset) \n node _T_375 = eq(_T_374, UInt<1>(0h0)) \n when _T_375 : \n node _T_376 = eq(_T_373, UInt<1>(0h0)) \n when _T_376 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_373, UInt<1>(0h1), \"\") : assert_63 \n node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_378 = or(UInt<1>(0h1), _T_377) \n node _T_379 = asUInt(reset) \n node _T_380 = eq(_T_379, UInt<1>(0h0)) \n when _T_380 : \n node _T_381 = eq(_T_378, UInt<1>(0h0)) \n when _T_381 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_378, UInt<1>(0h1), \"\") : assert_64 \n node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_382 : \n node _T_383 = asUInt(reset) \n node _T_384 = eq(_T_383, UInt<1>(0h0)) \n when _T_384 : \n node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_385 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_386 = asUInt(reset) \n node _T_387 = eq(_T_386, UInt<1>(0h0)) \n when _T_387 : \n node _T_388 = eq(sink_ok, UInt<1>(0h0)) \n when _T_388 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_390 = asUInt(reset) \n node _T_391 = eq(_T_390, UInt<1>(0h0)) \n when _T_391 : \n node _T_392 = eq(_T_389, UInt<1>(0h0)) \n when _T_392 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_389, UInt<1>(0h1), \"\") : assert_67 \n node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_394 = asUInt(reset) \n node _T_395 = eq(_T_394, UInt<1>(0h0)) \n when _T_395 : \n node _T_396 = eq(_T_393, UInt<1>(0h0)) \n when _T_396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_393, UInt<1>(0h1), \"\") : assert_68 \n node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_398 = asUInt(reset) \n node _T_399 = eq(_T_398, UInt<1>(0h0)) \n when _T_399 : \n node _T_400 = eq(_T_397, UInt<1>(0h0)) \n when _T_400 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_397, UInt<1>(0h1), \"\") : assert_69 \n node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_402 = or(_T_401, io.in.d.bits.corrupt) \n node _T_403 = asUInt(reset) \n node _T_404 = eq(_T_403, UInt<1>(0h0)) \n when _T_404 : \n node _T_405 = eq(_T_402, UInt<1>(0h0)) \n when _T_405 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_402, UInt<1>(0h1), \"\") : assert_70 \n node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_407 = or(UInt<1>(0h1), _T_406) \n node _T_408 = asUInt(reset) \n node _T_409 = eq(_T_408, UInt<1>(0h0)) \n when _T_409 : \n node _T_410 = eq(_T_407, UInt<1>(0h0)) \n when _T_410 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_407, UInt<1>(0h1), \"\") : assert_71 \n node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_411 : \n node _T_412 = asUInt(reset) \n node _T_413 = eq(_T_412, UInt<1>(0h0)) \n when _T_413 : \n node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_414 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_416 = asUInt(reset) \n node _T_417 = eq(_T_416, UInt<1>(0h0)) \n when _T_417 : \n node _T_418 = eq(_T_415, UInt<1>(0h0)) \n when _T_418 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_415, UInt<1>(0h1), \"\") : assert_73 \n node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_420 = asUInt(reset) \n node _T_421 = eq(_T_420, UInt<1>(0h0)) \n when _T_421 : \n node _T_422 = eq(_T_419, UInt<1>(0h0)) \n when _T_422 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_419, UInt<1>(0h1), \"\") : assert_74 \n node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_424 = or(UInt<1>(0h1), _T_423) \n node _T_425 = asUInt(reset) \n node _T_426 = eq(_T_425, UInt<1>(0h0)) \n when _T_426 : \n node _T_427 = eq(_T_424, UInt<1>(0h0)) \n when _T_427 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_424, UInt<1>(0h1), \"\") : assert_75 \n node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_428 : \n node _T_429 = asUInt(reset) \n node _T_430 = eq(_T_429, UInt<1>(0h0)) \n when _T_430 : \n node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_431 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_433 = asUInt(reset) \n node _T_434 = eq(_T_433, UInt<1>(0h0)) \n when _T_434 : \n node _T_435 = eq(_T_432, UInt<1>(0h0)) \n when _T_435 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_432, UInt<1>(0h1), \"\") : assert_77 \n node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_437 = or(_T_436, io.in.d.bits.corrupt) \n node _T_438 = asUInt(reset) \n node _T_439 = eq(_T_438, UInt<1>(0h0)) \n when _T_439 : \n node _T_440 = eq(_T_437, UInt<1>(0h0)) \n when _T_440 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_437, UInt<1>(0h1), \"\") : assert_78 \n node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_442 = or(UInt<1>(0h1), _T_441) \n node _T_443 = asUInt(reset) \n node _T_444 = eq(_T_443, UInt<1>(0h0)) \n when _T_444 : \n node _T_445 = eq(_T_442, UInt<1>(0h0)) \n when _T_445 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_442, UInt<1>(0h1), \"\") : assert_79 \n node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_446 : \n node _T_447 = asUInt(reset) \n node _T_448 = eq(_T_447, UInt<1>(0h0)) \n when _T_448 : \n node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_449 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_451 = asUInt(reset) \n node _T_452 = eq(_T_451, UInt<1>(0h0)) \n when _T_452 : \n node _T_453 = eq(_T_450, UInt<1>(0h0)) \n when _T_453 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_450, UInt<1>(0h1), \"\") : assert_81 \n node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_455 = asUInt(reset) \n node _T_456 = eq(_T_455, UInt<1>(0h0)) \n when _T_456 : \n node _T_457 = eq(_T_454, UInt<1>(0h0)) \n when _T_457 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_454, UInt<1>(0h1), \"\") : assert_82 \n node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_459 = or(UInt<1>(0h1), _T_458) \n node _T_460 = asUInt(reset) \n node _T_461 = eq(_T_460, UInt<1>(0h0)) \n when _T_461 : \n node _T_462 = eq(_T_459, UInt<1>(0h0)) \n when _T_462 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_459, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<32>(0h0) \n connect _WIRE.bits.mask, UInt<4>(0h0) \n connect _WIRE.bits.address, UInt<9>(0h0) \n connect _WIRE.bits.source, UInt<1>(0h0) \n connect _WIRE.bits.size, UInt<2>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_464 = asUInt(reset) \n node _T_465 = eq(_T_464, UInt<1>(0h0)) \n when _T_465 : \n node _T_466 = eq(_T_463, UInt<1>(0h0)) \n when _T_466 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_463, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<32>(0h0) \n connect _WIRE_2.bits.address, UInt<9>(0h0) \n connect _WIRE_2.bits.source, UInt<1>(0h0) \n connect _WIRE_2.bits.size, UInt<2>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_468 = asUInt(reset) \n node _T_469 = eq(_T_468, UInt<1>(0h0)) \n when _T_469 : \n node _T_470 = eq(_T_467, UInt<1>(0h0)) \n when _T_470 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_467, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_472 = asUInt(reset) \n node _T_473 = eq(_T_472, UInt<1>(0h0)) \n when _T_473 : \n node _T_474 = eq(_T_471, UInt<1>(0h0)) \n when _T_474 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_471, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_475 = eq(a_first, UInt<1>(0h0)) \n node _T_476 = and(io.in.a.valid, _T_475) \n when _T_476 : \n node _T_477 = eq(io.in.a.bits.opcode, opcode) \n node _T_478 = asUInt(reset) \n node _T_479 = eq(_T_478, UInt<1>(0h0)) \n when _T_479 : \n node _T_480 = eq(_T_477, UInt<1>(0h0)) \n when _T_480 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_477, UInt<1>(0h1), \"\") : assert_87 \n node _T_481 = eq(io.in.a.bits.param, param) \n node _T_482 = asUInt(reset) \n node _T_483 = eq(_T_482, UInt<1>(0h0)) \n when _T_483 : \n node _T_484 = eq(_T_481, UInt<1>(0h0)) \n when _T_484 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_481, UInt<1>(0h1), \"\") : assert_88 \n node _T_485 = eq(io.in.a.bits.size, size) \n node _T_486 = asUInt(reset) \n node _T_487 = eq(_T_486, UInt<1>(0h0)) \n when _T_487 : \n node _T_488 = eq(_T_485, UInt<1>(0h0)) \n when _T_488 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_485, UInt<1>(0h1), \"\") : assert_89 \n node _T_489 = eq(io.in.a.bits.source, source) \n node _T_490 = asUInt(reset) \n node _T_491 = eq(_T_490, UInt<1>(0h0)) \n when _T_491 : \n node _T_492 = eq(_T_489, UInt<1>(0h0)) \n when _T_492 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_489, UInt<1>(0h1), \"\") : assert_90 \n node _T_493 = eq(io.in.a.bits.address, address) \n node _T_494 = asUInt(reset) \n node _T_495 = eq(_T_494, UInt<1>(0h0)) \n when _T_495 : \n node _T_496 = eq(_T_493, UInt<1>(0h0)) \n when _T_496 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_493, UInt<1>(0h1), \"\") : assert_91 \n node _T_497 = and(io.in.a.ready, io.in.a.valid) \n node _T_498 = and(_T_497, a_first) \n when _T_498 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_499 = eq(d_first, UInt<1>(0h0)) \n node _T_500 = and(io.in.d.valid, _T_499) \n when _T_500 : \n node _T_501 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_502 = asUInt(reset) \n node _T_503 = eq(_T_502, UInt<1>(0h0)) \n when _T_503 : \n node _T_504 = eq(_T_501, UInt<1>(0h0)) \n when _T_504 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_501, UInt<1>(0h1), \"\") : assert_92 \n node _T_505 = eq(io.in.d.bits.param, param_1) \n node _T_506 = asUInt(reset) \n node _T_507 = eq(_T_506, UInt<1>(0h0)) \n when _T_507 : \n node _T_508 = eq(_T_505, UInt<1>(0h0)) \n when _T_508 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_505, UInt<1>(0h1), \"\") : assert_93 \n node _T_509 = eq(io.in.d.bits.size, size_1) \n node _T_510 = asUInt(reset) \n node _T_511 = eq(_T_510, UInt<1>(0h0)) \n when _T_511 : \n node _T_512 = eq(_T_509, UInt<1>(0h0)) \n when _T_512 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_509, UInt<1>(0h1), \"\") : assert_94 \n node _T_513 = eq(io.in.d.bits.source, source_1) \n node _T_514 = asUInt(reset) \n node _T_515 = eq(_T_514, UInt<1>(0h0)) \n when _T_515 : \n node _T_516 = eq(_T_513, UInt<1>(0h0)) \n when _T_516 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_513, UInt<1>(0h1), \"\") : assert_95 \n node _T_517 = eq(io.in.d.bits.sink, sink) \n node _T_518 = asUInt(reset) \n node _T_519 = eq(_T_518, UInt<1>(0h0)) \n when _T_519 : \n node _T_520 = eq(_T_517, UInt<1>(0h0)) \n when _T_520 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_517, UInt<1>(0h1), \"\") : assert_96 \n node _T_521 = eq(io.in.d.bits.denied, denied) \n node _T_522 = asUInt(reset) \n node _T_523 = eq(_T_522, UInt<1>(0h0)) \n when _T_523 : \n node _T_524 = eq(_T_521, UInt<1>(0h0)) \n when _T_524 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_521, UInt<1>(0h1), \"\") : assert_97 \n node _T_525 = and(io.in.d.ready, io.in.d.valid) \n node _T_526 = and(_T_525, d_first) \n when _T_526 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) \n regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<1> \n connect a_set, UInt<1>(0h0) \n wire a_set_wo_ready : UInt<1> \n connect a_set_wo_ready, UInt<1>(0h0) \n wire a_opcodes_set : UInt<4> \n connect a_opcodes_set, UInt<4>(0h0) \n wire a_sizes_set : UInt<4> \n connect a_sizes_set, UInt<4>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<3> \n connect a_sizes_set_interm, UInt<3>(0h0) \n node _T_527 = and(io.in.a.valid, a_first_1) \n node _T_528 = and(_T_527, UInt<1>(0h1)) \n when _T_528 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_529 = and(io.in.a.ready, io.in.a.valid) \n node _T_530 = and(_T_529, a_first_1) \n node _T_531 = and(_T_530, UInt<1>(0h1)) \n when _T_531 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_532 = dshr(inflight, io.in.a.bits.source) \n node _T_533 = bits(_T_532, 0, 0) \n node _T_534 = eq(_T_533, UInt<1>(0h0)) \n node _T_535 = asUInt(reset) \n node _T_536 = eq(_T_535, UInt<1>(0h0)) \n when _T_536 : \n node _T_537 = eq(_T_534, UInt<1>(0h0)) \n when _T_537 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_534, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<1> \n connect d_clr, UInt<1>(0h0) \n wire d_clr_wo_ready : UInt<1> \n connect d_clr_wo_ready, UInt<1>(0h0) \n wire d_opcodes_clr : UInt<4> \n connect d_opcodes_clr, UInt<4>(0h0) \n wire d_sizes_clr : UInt<4> \n connect d_sizes_clr, UInt<4>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_538 = and(io.in.d.valid, d_first_1) \n node _T_539 = and(_T_538, UInt<1>(0h1)) \n node _T_540 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_541 = and(_T_539, _T_540) \n when _T_541 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_542 = and(io.in.d.ready, io.in.d.valid) \n node _T_543 = and(_T_542, d_first_1) \n node _T_544 = and(_T_543, UInt<1>(0h1)) \n node _T_545 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_546 = and(_T_544, _T_545) \n when _T_546 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_547 = and(io.in.d.valid, d_first_1) \n node _T_548 = and(_T_547, UInt<1>(0h1)) \n node _T_549 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_550 = and(_T_548, _T_549) \n when _T_550 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_551 = dshr(inflight, io.in.d.bits.source) \n node _T_552 = bits(_T_551, 0, 0) \n node _T_553 = or(_T_552, same_cycle_resp) \n node _T_554 = asUInt(reset) \n node _T_555 = eq(_T_554, UInt<1>(0h0)) \n when _T_555 : \n node _T_556 = eq(_T_553, UInt<1>(0h0)) \n when _T_556 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_553, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_559 = or(_T_557, _T_558) \n node _T_560 = asUInt(reset) \n node _T_561 = eq(_T_560, UInt<1>(0h0)) \n when _T_561 : \n node _T_562 = eq(_T_559, UInt<1>(0h0)) \n when _T_562 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_559, UInt<1>(0h1), \"\") : assert_100 \n node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_564 = asUInt(reset) \n node _T_565 = eq(_T_564, UInt<1>(0h0)) \n when _T_565 : \n node _T_566 = eq(_T_563, UInt<1>(0h0)) \n when _T_566 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_563, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_569 = or(_T_567, _T_568) \n node _T_570 = asUInt(reset) \n node _T_571 = eq(_T_570, UInt<1>(0h0)) \n when _T_571 : \n node _T_572 = eq(_T_569, UInt<1>(0h0)) \n when _T_572 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_569, UInt<1>(0h1), \"\") : assert_102 \n node _T_573 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_574 = asUInt(reset) \n node _T_575 = eq(_T_574, UInt<1>(0h0)) \n when _T_575 : \n node _T_576 = eq(_T_573, UInt<1>(0h0)) \n when _T_576 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_573, UInt<1>(0h1), \"\") : assert_103 \n node _T_577 = and(io.in.d.valid, d_first_1) \n node _T_578 = and(_T_577, a_first_1) \n node _T_579 = and(_T_578, io.in.a.valid) \n node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_581 = and(_T_579, _T_580) \n node _T_582 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_583 = and(_T_581, _T_582) \n when _T_583 : \n node _T_584 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_585 = or(_T_584, io.in.a.ready) \n node _T_586 = asUInt(reset) \n node _T_587 = eq(_T_586, UInt<1>(0h0)) \n when _T_587 : \n node _T_588 = eq(_T_585, UInt<1>(0h0)) \n when _T_588 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_585, UInt<1>(0h1), \"\") : assert_104 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_104 \n node _T_589 = orr(inflight) \n node _T_590 = eq(_T_589, UInt<1>(0h0)) \n node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_592 = or(_T_590, _T_591) \n node _T_593 = lt(watchdog, plusarg_reader.out) \n node _T_594 = or(_T_592, _T_593) \n node _T_595 = asUInt(reset) \n node _T_596 = eq(_T_595, UInt<1>(0h0)) \n when _T_596 : \n node _T_597 = eq(_T_594, UInt<1>(0h0)) \n when _T_597 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_594, UInt<1>(0h1), \"\") : assert_105 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_598 = and(io.in.a.ready, io.in.a.valid) \n node _T_599 = and(io.in.d.ready, io.in.d.valid) \n node _T_600 = or(_T_598, _T_599) \n when _T_600 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) \n regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE.bits.address, UInt<9>(0h0) \n connect _c_first_WIRE.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<1> \n connect c_set, UInt<1>(0h0) \n wire c_set_wo_ready : UInt<1> \n connect c_set_wo_ready, UInt<1>(0h0) \n wire c_opcodes_set : UInt<4> \n connect c_opcodes_set, UInt<4>(0h0) \n wire c_sizes_set : UInt<4> \n connect c_sizes_set, UInt<4>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<3> \n connect c_sizes_set_interm, UInt<3>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<32>(0h0) \n connect _WIRE_6.bits.address, UInt<9>(0h0) \n connect _WIRE_6.bits.source, UInt<1>(0h0) \n connect _WIRE_6.bits.size, UInt<2>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_601 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<32>(0h0) \n connect _WIRE_8.bits.address, UInt<9>(0h0) \n connect _WIRE_8.bits.source, UInt<1>(0h0) \n connect _WIRE_8.bits.size, UInt<2>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_604 = and(_T_602, _T_603) \n node _T_605 = and(_T_601, _T_604) \n when _T_605 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<32>(0h0) \n connect _WIRE_10.bits.address, UInt<9>(0h0) \n connect _WIRE_10.bits.source, UInt<1>(0h0) \n connect _WIRE_10.bits.size, UInt<2>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_607 = and(_T_606, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<32>(0h0) \n connect _WIRE_12.bits.address, UInt<9>(0h0) \n connect _WIRE_12.bits.source, UInt<1>(0h0) \n connect _WIRE_12.bits.size, UInt<2>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_610 = and(_T_608, _T_609) \n node _T_611 = and(_T_607, _T_610) \n when _T_611 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_WIRE.bits.address, UInt<9>(0h0) \n connect _c_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<32>(0h0) \n connect _WIRE_14.bits.address, UInt<9>(0h0) \n connect _WIRE_14.bits.source, UInt<1>(0h0) \n connect _WIRE_14.bits.size, UInt<2>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_612 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_613 = bits(_T_612, 0, 0) \n node _T_614 = eq(_T_613, UInt<1>(0h0)) \n node _T_615 = asUInt(reset) \n node _T_616 = eq(_T_615, UInt<1>(0h0)) \n when _T_616 : \n node _T_617 = eq(_T_614, UInt<1>(0h0)) \n when _T_617 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_614, UInt<1>(0h1), \"\") : assert_106 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<1> \n connect d_clr_1, UInt<1>(0h0) \n wire d_clr_wo_ready_1 : UInt<1> \n connect d_clr_wo_ready_1, UInt<1>(0h0) \n wire d_opcodes_clr_1 : UInt<4> \n connect d_opcodes_clr_1, UInt<4>(0h0) \n wire d_sizes_clr_1 : UInt<4> \n connect d_sizes_clr_1, UInt<4>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_618 = and(io.in.d.valid, d_first_2) \n node _T_619 = and(_T_618, UInt<1>(0h1)) \n node _T_620 = and(_T_619, d_release_ack_1) \n when _T_620 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_621 = and(io.in.d.ready, io.in.d.valid) \n node _T_622 = and(_T_621, d_first_2) \n node _T_623 = and(_T_622, UInt<1>(0h1)) \n node _T_624 = and(_T_623, d_release_ack_1) \n when _T_624 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_625 = and(io.in.d.valid, d_first_2) \n node _T_626 = and(_T_625, UInt<1>(0h1)) \n node _T_627 = and(_T_626, d_release_ack_1) \n when _T_627 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_628 = dshr(inflight_1, io.in.d.bits.source) \n node _T_629 = bits(_T_628, 0, 0) \n node _T_630 = or(_T_629, same_cycle_resp_1) \n node _T_631 = asUInt(reset) \n node _T_632 = eq(_T_631, UInt<1>(0h0)) \n when _T_632 : \n node _T_633 = eq(_T_630, UInt<1>(0h0)) \n when _T_633 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_630, UInt<1>(0h1), \"\") : assert_107 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<32>(0h0) \n connect _WIRE_16.bits.address, UInt<9>(0h0) \n connect _WIRE_16.bits.source, UInt<1>(0h0) \n connect _WIRE_16.bits.size, UInt<2>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_635 = asUInt(reset) \n node _T_636 = eq(_T_635, UInt<1>(0h0)) \n when _T_636 : \n node _T_637 = eq(_T_634, UInt<1>(0h0)) \n when _T_637 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_634, UInt<1>(0h1), \"\") : assert_108 \n else :\n\n node _T_638 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_639 = asUInt(reset) \n node _T_640 = eq(_T_639, UInt<1>(0h0)) \n when _T_640 : \n node _T_641 = eq(_T_638, UInt<1>(0h0)) \n when _T_641 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_638, UInt<1>(0h1), \"\") : assert_109 \n node _T_642 = and(io.in.d.valid, d_first_2) \n node _T_643 = and(_T_642, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<32>(0h0) \n connect _WIRE_18.bits.address, UInt<9>(0h0) \n connect _WIRE_18.bits.source, UInt<1>(0h0) \n connect _WIRE_18.bits.size, UInt<2>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_644 = and(_T_643, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<32>(0h0) \n connect _WIRE_20.bits.address, UInt<9>(0h0) \n connect _WIRE_20.bits.source, UInt<1>(0h0) \n connect _WIRE_20.bits.size, UInt<2>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_646 = and(_T_644, _T_645) \n node _T_647 = and(_T_646, d_release_ack_1) \n node _T_648 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_649 = and(_T_647, _T_648) \n when _T_649 : \n node _T_650 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<32>(0h0) \n connect _WIRE_22.bits.address, UInt<9>(0h0) \n connect _WIRE_22.bits.source, UInt<1>(0h0) \n connect _WIRE_22.bits.size, UInt<2>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_651 = or(_T_650, _WIRE_23.ready) \n node _T_652 = asUInt(reset) \n node _T_653 = eq(_T_652, UInt<1>(0h0)) \n when _T_653 : \n node _T_654 = eq(_T_651, UInt<1>(0h0)) \n when _T_654 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_651, UInt<1>(0h1), \"\") : assert_110 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_105 \n node _T_655 = orr(inflight_1) \n node _T_656 = eq(_T_655, UInt<1>(0h0)) \n node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_658 = or(_T_656, _T_657) \n node _T_659 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_660 = or(_T_658, _T_659) \n node _T_661 = asUInt(reset) \n node _T_662 = eq(_T_661, UInt<1>(0h0)) \n when _T_662 : \n node _T_663 = eq(_T_660, UInt<1>(0h0)) \n when _T_663 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_660, UInt<1>(0h1), \"\") : assert_111 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<32>(0h0) \n connect _WIRE_24.bits.address, UInt<9>(0h0) \n connect _WIRE_24.bits.source, UInt<1>(0h0) \n connect _WIRE_24.bits.size, UInt<2>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_665 = and(io.in.d.ready, io.in.d.valid) \n node _T_666 = or(_T_664, _T_665) \n when _T_666 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_51(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [8:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_source = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_source = 1'h0;\t// @[Monitor.scala:36:7]\n wire mask_sizeOH_shiftAmount = 1'h0;\t// @[OneHot.scala:64:49]\n wire mask_sub_size = 1'h0;\t// @[Misc.scala:209:26]\n wire _mask_sub_acc_T = 1'h0;\t// @[Misc.scala:215:38]\n wire _mask_sub_acc_T_1 = 1'h0;\t// @[Misc.scala:215:38]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire a_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire a_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire c_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_first_count_T = 1'h0;\t// @[Edges.scala:234:27]\n wire c_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_counter_T = 1'h0;\t// @[Edges.scala:236:21]\n wire d_first_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire c_set = 1'h0;\t// @[Monitor.scala:738:34]\n wire c_set_wo_ready = 1'h0;\t// @[Monitor.scala:739:34]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire _source_ok_T = 1'h1;\t// @[Parameters.scala:46:9]\n wire _source_ok_WIRE_0 = 1'h1;\t// @[Parameters.scala:1138:31]\n wire mask_sub_sub_0_1 = 1'h1;\t// @[Misc.scala:206:21]\n wire mask_sub_0_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_sub_1_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_size = 1'h1;\t// @[Misc.scala:209:26]\n wire mask_acc = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_2 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_3 = 1'h1;\t// @[Misc.scala:215:29]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:46:9]\n wire _source_ok_WIRE_1_0 = 1'h1;\t// @[Parameters.scala:1138:31]\n wire _a_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _a_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _same_cycle_resp_T_2 = 1'h1;\t// @[Monitor.scala:684:113]\n wire c_first_counter1 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_2 = 1'h1;\t// @[Edges.scala:232:33]\n wire _same_cycle_resp_T_8 = 1'h1;\t// @[Monitor.scala:795:113]\n wire [1:0] is_aligned_mask = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] mask_lo = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] _a_first_beats1_decode_T_2 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _a_first_beats1_decode_T_5 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _c_first_beats1_decode_T_1 = 2'h3;\t// @[package.scala:243:76]\n wire [1:0] _c_first_counter1_T = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_a_bits_size = 2'h2;\t// @[Monitor.scala:36:7]\n wire [1:0] _mask_sizeOH_T = 2'h2;\t// @[Misc.scala:202:34]\n wire [2:0] io_in_a_bits_param = 3'h0;\t// @[Monitor.scala:36:7]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_sizes_set_interm = 3'h0;\t// @[Monitor.scala:755:40]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_T = 3'h0;\t// @[Monitor.scala:766:51]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] io_in_a_bits_mask = 4'hF;\t// @[Monitor.scala:36:7]\n wire [3:0] mask = 4'hF;\t// @[Misc.scala:222:10]\n wire [31:0] _c_first_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_first_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_first_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_first_WIRE_2_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_first_WIRE_3_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_set_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_set_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _is_aligned_mask_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_4 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _c_first_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_beats1_decode_T_2 = 2'h0;\t// @[package.scala:243:46]\n wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [30:0] _d_opcodes_clr_T_5 = 31'hF;\t// @[Monitor.scala:680:76]\n wire [30:0] _d_sizes_clr_T_5 = 31'hF;\t// @[Monitor.scala:681:74]\n wire [30:0] _d_opcodes_clr_T_11 = 31'hF;\t// @[Monitor.scala:790:76]\n wire [30:0] _d_sizes_clr_T_11 = 31'hF;\t// @[Monitor.scala:791:74]\n wire [3:0] _a_opcode_lookup_T = 4'h0;\t// @[Monitor.scala:637:69]\n wire [3:0] _a_size_lookup_T = 4'h0;\t// @[Monitor.scala:641:65]\n wire [3:0] _a_opcodes_set_T = 4'h0;\t// @[Monitor.scala:659:79]\n wire [3:0] _a_sizes_set_T = 4'h0;\t// @[Monitor.scala:660:77]\n wire [3:0] _d_opcodes_clr_T_4 = 4'h0;\t// @[Monitor.scala:680:101]\n wire [3:0] _d_sizes_clr_T_4 = 4'h0;\t// @[Monitor.scala:681:99]\n wire [3:0] c_opcodes_set = 4'h0;\t// @[Monitor.scala:740:34]\n wire [3:0] c_sizes_set = 4'h0;\t// @[Monitor.scala:741:34]\n wire [3:0] _c_opcode_lookup_T = 4'h0;\t// @[Monitor.scala:749:69]\n wire [3:0] _c_size_lookup_T = 4'h0;\t// @[Monitor.scala:750:67]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_opcodes_set_T = 4'h0;\t// @[Monitor.scala:767:79]\n wire [3:0] _c_sizes_set_T = 4'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _d_opcodes_clr_T_10 = 4'h0;\t// @[Monitor.scala:790:101]\n wire [3:0] _d_sizes_clr_T_10 = 4'h0;\t// @[Monitor.scala:791:99]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [1:0] _mask_sizeOH_T_1 = 2'h1;\t// @[OneHot.scala:65:12]\n wire [1:0] _mask_sizeOH_T_2 = 2'h1;\t// @[OneHot.scala:65:27]\n wire [1:0] mask_sizeOH = 2'h1;\t// @[Misc.scala:202:81]\n wire [1:0] _a_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _a_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T_1 = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T_1 = 2'h1;\t// @[OneHot.scala:58:35]\n wire [17:0] _c_sizes_set_T_1 = 18'h0;\t// @[Monitor.scala:768:52]\n wire [18:0] _c_opcodes_set_T_1 = 19'h0;\t// @[Monitor.scala:767:54]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_sizes_set_interm_T_1 = 3'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [4:0] _c_first_beats1_decode_T = 5'h3;\t// @[package.scala:243:71]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T_1 = 3'h5;\t// @[Monitor.scala:658:59]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T = 3'h4;\t// @[Monitor.scala:658:51]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [4:0] _is_aligned_mask_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T_3 = 5'hC;\t// @[package.scala:243:71]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]};\t// @[Monitor.scala:36:7]\n wire is_aligned = _is_aligned_T == 9'h0;\t// @[Edges.scala:21:{16,24}]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_1_2 = mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_eq;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_eq_1;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_eq_2;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_eq_3;\t// @[Misc.scala:214:27, :215:38]\n wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_598;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_598;\t// @[Decoupled.scala:51:35]\n wire a_first_done = _a_first_T;\t// @[Decoupled.scala:51:35]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n wire _a_first_last_T = a_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1 = _a_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~a_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T = ~a_first & a_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [8:0] address;\t// @[Monitor.scala:391:22]\n wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_666;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_666;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_666;\t// @[Decoupled.scala:51:35]\n wire d_first_done = _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN;\t// @[package.scala:243:71]\n wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n wire _d_first_last_T = d_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1 = _d_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire d_first = ~d_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T = ~d_first & d_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [1:0] inflight;\t// @[Monitor.scala:614:27]\n reg [3:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes;\t// @[Monitor.scala:616:35, :637:44]\n reg [3:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [3:0] _a_size_lookup_T_1 = inflight_sizes;\t// @[Monitor.scala:618:33, :641:40]\n wire a_first_done_1 = _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n wire _a_first_last_T_2 = a_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1_1 = _a_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire a_first_1 = ~a_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_first_done_1 = _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_2 = d_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_1 = _d_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire d_first_1 = ~d_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire a_set;\t// @[Monitor.scala:626:34]\n wire a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [3:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [3:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1};\t// @[Monitor.scala:637:{44,97}]\n wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1};\t// @[Monitor.scala:637:97, :641:{40,91}]\n wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [2:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _T_528 = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26]\n assign a_set_wo_ready = _T_528;\t// @[Monitor.scala:627:34, :651:26]\n wire _same_cycle_resp_T;\t// @[Monitor.scala:684:44]\n assign _same_cycle_resp_T = _T_528;\t// @[Monitor.scala:651:26, :684:44]\n assign a_set = _T_598 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]\n assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0;\t// @[Monitor.scala:626:34, :648:38, :655:70, :658:28]\n wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm};\t// @[Monitor.scala:646:40, :659:54]\n assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]\n wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm};\t// @[Monitor.scala:648:38, :659:54, :660:52]\n assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]\n wire d_clr;\t// @[Monitor.scala:664:34]\n wire d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [3:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [3:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_0;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_0;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_577 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n assign d_clr_wo_ready = _T_577 & ~d_release_ack;\t// @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]\n assign d_clr = _T_666 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n wire [3:0] _GEN_1 = {4{d_clr}};\t// @[Monitor.scala:664:34, :668:33, :678:89, :680:21]\n assign d_opcodes_clr = _GEN_1;\t// @[Monitor.scala:668:33, :678:89, :680:21]\n assign d_sizes_clr = _GEN_1;\t// @[Monitor.scala:668:33, :670:31, :678:89, :680:21]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire same_cycle_resp = _same_cycle_resp_T_1;\t// @[Monitor.scala:684:{55,88}]\n wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set};\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1};\t// @[Monitor.scala:705:{27,36,38}]\n wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [1:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [1:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [3:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :749:44]\n wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [3:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :750:42]\n wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire d_first_done_2 = _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_4 = d_first_counter_2;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_2 = _d_first_counter1_T_2[0];\t// @[Edges.scala:230:28]\n wire d_first_2 = ~d_first_counter_2;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1};\t// @[Monitor.scala:637:97, :749:{44,97}]\n wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1};\t// @[Monitor.scala:637:97, :750:{42,93}]\n wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire d_clr_1;\t// @[Monitor.scala:774:34]\n wire d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [3:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [3:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_642 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1;\t// @[Monitor.scala:775:34, :783:46, :784:{26,71}]\n assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n wire [3:0] _GEN_2 = {4{d_clr_1}};\t// @[Monitor.scala:774:34, :776:34, :788:88, :790:21]\n assign d_opcodes_clr_1 = _GEN_2;\t// @[Monitor.scala:776:34, :788:88, :790:21]\n assign d_sizes_clr_1 = _GEN_2;\t// @[Monitor.scala:776:34, :777:34, :788:88, :790:21]\n wire _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4};\t// @[Monitor.scala:814:{35,44,46}]\n wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32180,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_240 : \n input clock : Clock \n input reset : AsyncReset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _sync_2_T = bits(io.d, 0, 0) \n connect sync_2, _sync_2_T \n connect sync_0, sync_1 \n connect sync_1, sync_2 \n connect io.q, sync_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_240(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":32181,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e11_s53 : \n input clock : Clock \n input reset : Reset \n output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} \n\n\n inst divSqrtRawFN of DivSqrtRawFN_small_e11_s53 \n connect divSqrtRawFN.clock, clock\n\n connect divSqrtRawFN.reset, reset\n\n connect io.inReady, divSqrtRawFN.io.inReady \n connect divSqrtRawFN.io.inValid, io.inValid \n connect divSqrtRawFN.io.sqrtOp, io.sqrtOp \n node divSqrtRawFN_io_a_exp = bits(io.a, 63, 52) \n node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 11, 9) \n node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) \n node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 11, 10) \n node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) \n wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} \n node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 9, 9) \n node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) \n connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 \n node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 9, 9) \n node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) \n node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) \n connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 \n connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero \n node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 64, 64) \n connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T \n node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) \n connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T \n node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) \n node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) \n node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 51, 0) \n node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) \n connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 \n connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig \n connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp \n connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign \n connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero \n connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf \n connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN \n node divSqrtRawFN_io_b_exp = bits(io.b, 63, 52) \n node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 11, 9) \n node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) \n node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 11, 10) \n node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) \n wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} \n node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 9, 9) \n node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) \n connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 \n node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 9, 9) \n node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) \n node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) \n connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 \n connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero \n node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 64, 64) \n connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T \n node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) \n connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T \n node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) \n node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) \n node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 51, 0) \n node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) \n connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 \n connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig \n connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp \n connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign \n connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero \n connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf \n connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN \n connect divSqrtRawFN.io.roundingMode, io.roundingMode \n connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div \n connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt \n connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut \n connect io.invalidExc, divSqrtRawFN.io.invalidExc \n connect io.infiniteExc, divSqrtRawFN.io.infiniteExc \n connect io.rawOut, divSqrtRawFN.io.rawOut"},"response":{"kind":"string","value":"module DivSqrtRecFMToRaw_small_e11_s53(\t// @[DivSqrtRecFN_small.scala:422:5]\n input clock,\t// @[DivSqrtRecFN_small.scala:422:5]\n input reset,\t// @[DivSqrtRecFN_small.scala:422:5]\n output io_inReady,\t// @[DivSqrtRecFN_small.scala:426:16]\n input io_inValid,\t// @[DivSqrtRecFN_small.scala:426:16]\n input io_sqrtOp,\t// @[DivSqrtRecFN_small.scala:426:16]\n input [64:0] io_a,\t// @[DivSqrtRecFN_small.scala:426:16]\n input [64:0] io_b,\t// @[DivSqrtRecFN_small.scala:426:16]\n input [2:0] io_roundingMode,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_rawOutValid_div,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_rawOutValid_sqrt,\t// @[DivSqrtRecFN_small.scala:426:16]\n output [2:0] io_roundingModeOut,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_invalidExc,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_infiniteExc,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_rawOut_isNaN,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_rawOut_isInf,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_rawOut_isZero,\t// @[DivSqrtRecFN_small.scala:426:16]\n output io_rawOut_sign,\t// @[DivSqrtRecFN_small.scala:426:16]\n output [12:0] io_rawOut_sExp,\t// @[DivSqrtRecFN_small.scala:426:16]\n output [55:0] io_rawOut_sig\t// @[DivSqrtRecFN_small.scala:426:16]\n);\n\n wire io_inValid_0 = io_inValid;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_sqrtOp_0 = io_sqrtOp;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire [64:0] io_a_0 = io_a;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire [64:0] io_b_0 = io_b;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire [2:0] io_roundingMode_0 = io_roundingMode;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_rawOut_isNaN_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_rawOut_isInf_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_rawOut_isZero_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_rawOut_sign_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire [12:0] io_rawOut_sExp_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire [55:0] io_rawOut_sig_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_inReady_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_rawOutValid_div_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_rawOutValid_sqrt_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire [2:0] io_roundingModeOut_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_invalidExc_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire io_infiniteExc_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n wire [11:0] divSqrtRawFN_io_a_exp = io_a_0[63:52];\t// @[rawFloatFromRecFN.scala:51:21]\n wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[11:9];\t// @[rawFloatFromRecFN.scala:51:21, :52:28]\n wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0;\t// @[rawFloatFromRecFN.scala:52:{28,53}]\n wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero;\t// @[rawFloatFromRecFN.scala:52:53, :55:23]\n wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[11:10];\t// @[rawFloatFromRecFN.scala:51:21, :53:28]\n wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T;\t// @[rawFloatFromRecFN.scala:53:{28,53}]\n wire _divSqrtRawFN_io_a_out_isNaN_T_1;\t// @[rawFloatFromRecFN.scala:56:33]\n wire _divSqrtRawFN_io_a_out_isInf_T_2;\t// @[rawFloatFromRecFN.scala:57:33]\n wire _divSqrtRawFN_io_a_out_sign_T;\t// @[rawFloatFromRecFN.scala:59:25]\n wire [12:0] _divSqrtRawFN_io_a_out_sExp_T;\t// @[rawFloatFromRecFN.scala:60:27]\n wire [53:0] _divSqrtRawFN_io_a_out_sig_T_3;\t// @[rawFloatFromRecFN.scala:61:44]\n wire divSqrtRawFN_io_a_out_isNaN;\t// @[rawFloatFromRecFN.scala:55:23]\n wire divSqrtRawFN_io_a_out_isInf;\t// @[rawFloatFromRecFN.scala:55:23]\n wire divSqrtRawFN_io_a_out_sign;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [12:0] divSqrtRawFN_io_a_out_sExp;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [53:0] divSqrtRawFN_io_a_out_sig;\t// @[rawFloatFromRecFN.scala:55:23]\n wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[9];\t// @[rawFloatFromRecFN.scala:51:21, :56:41]\n wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[9];\t// @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]\n assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T;\t// @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]\n assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1;\t// @[rawFloatFromRecFN.scala:55:23, :56:33]\n wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T;\t// @[rawFloatFromRecFN.scala:57:{36,41}]\n assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1;\t// @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]\n assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2;\t// @[rawFloatFromRecFN.scala:55:23, :57:33]\n assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[64];\t// @[rawFloatFromRecFN.scala:59:25]\n assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T;\t// @[rawFloatFromRecFN.scala:55:23, :59:25]\n assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp};\t// @[rawFloatFromRecFN.scala:51:21, :60:27]\n assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T;\t// @[rawFloatFromRecFN.scala:55:23, :60:27]\n wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero;\t// @[rawFloatFromRecFN.scala:52:53, :61:35]\n wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T};\t// @[rawFloatFromRecFN.scala:61:{32,35}]\n wire [51:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[51:0];\t// @[rawFloatFromRecFN.scala:61:49]\n assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2};\t// @[rawFloatFromRecFN.scala:61:{32,44,49}]\n assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3;\t// @[rawFloatFromRecFN.scala:55:23, :61:44]\n wire [11:0] divSqrtRawFN_io_b_exp = io_b_0[63:52];\t// @[rawFloatFromRecFN.scala:51:21]\n wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[11:9];\t// @[rawFloatFromRecFN.scala:51:21, :52:28]\n wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0;\t// @[rawFloatFromRecFN.scala:52:{28,53}]\n wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero;\t// @[rawFloatFromRecFN.scala:52:53, :55:23]\n wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[11:10];\t// @[rawFloatFromRecFN.scala:51:21, :53:28]\n wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T;\t// @[rawFloatFromRecFN.scala:53:{28,53}]\n wire _divSqrtRawFN_io_b_out_isNaN_T_1;\t// @[rawFloatFromRecFN.scala:56:33]\n wire _divSqrtRawFN_io_b_out_isInf_T_2;\t// @[rawFloatFromRecFN.scala:57:33]\n wire _divSqrtRawFN_io_b_out_sign_T;\t// @[rawFloatFromRecFN.scala:59:25]\n wire [12:0] _divSqrtRawFN_io_b_out_sExp_T;\t// @[rawFloatFromRecFN.scala:60:27]\n wire [53:0] _divSqrtRawFN_io_b_out_sig_T_3;\t// @[rawFloatFromRecFN.scala:61:44]\n wire divSqrtRawFN_io_b_out_isNaN;\t// @[rawFloatFromRecFN.scala:55:23]\n wire divSqrtRawFN_io_b_out_isInf;\t// @[rawFloatFromRecFN.scala:55:23]\n wire divSqrtRawFN_io_b_out_sign;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [12:0] divSqrtRawFN_io_b_out_sExp;\t// @[rawFloatFromRecFN.scala:55:23]\n wire [53:0] divSqrtRawFN_io_b_out_sig;\t// @[rawFloatFromRecFN.scala:55:23]\n wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[9];\t// @[rawFloatFromRecFN.scala:51:21, :56:41]\n wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[9];\t// @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]\n assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T;\t// @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]\n assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1;\t// @[rawFloatFromRecFN.scala:55:23, :56:33]\n wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T;\t// @[rawFloatFromRecFN.scala:57:{36,41}]\n assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1;\t// @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]\n assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2;\t// @[rawFloatFromRecFN.scala:55:23, :57:33]\n assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[64];\t// @[rawFloatFromRecFN.scala:59:25]\n assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T;\t// @[rawFloatFromRecFN.scala:55:23, :59:25]\n assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp};\t// @[rawFloatFromRecFN.scala:51:21, :60:27]\n assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T;\t// @[rawFloatFromRecFN.scala:55:23, :60:27]\n wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero;\t// @[rawFloatFromRecFN.scala:52:53, :61:35]\n wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T};\t// @[rawFloatFromRecFN.scala:61:{32,35}]\n wire [51:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[51:0];\t// @[rawFloatFromRecFN.scala:61:49]\n assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2};\t// @[rawFloatFromRecFN.scala:61:{32,44,49}]\n assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3;\t// @[rawFloatFromRecFN.scala:55:23, :61:44]\n DivSqrtRawFN_small_e11_s53 divSqrtRawFN (\t// @[DivSqrtRecFN_small.scala:446:15]\n .clock (clock),\n .reset (reset),\n .io_inReady (io_inReady_0),\n .io_inValid (io_inValid_0),\t// @[DivSqrtRecFN_small.scala:422:5]\n .io_sqrtOp (io_sqrtOp_0),\t// @[DivSqrtRecFN_small.scala:422:5]\n .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_a_isInf (divSqrtRawFN_io_a_out_isInf),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_a_isZero (divSqrtRawFN_io_a_out_isZero),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_a_sign (divSqrtRawFN_io_a_out_sign),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_a_sExp (divSqrtRawFN_io_a_out_sExp),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_a_sig (divSqrtRawFN_io_a_out_sig),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_b_isInf (divSqrtRawFN_io_b_out_isInf),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_b_isZero (divSqrtRawFN_io_b_out_isZero),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_b_sign (divSqrtRawFN_io_b_out_sign),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_b_sExp (divSqrtRawFN_io_b_out_sExp),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_b_sig (divSqrtRawFN_io_b_out_sig),\t// @[rawFloatFromRecFN.scala:55:23]\n .io_roundingMode (io_roundingMode_0),\t// @[DivSqrtRecFN_small.scala:422:5]\n .io_rawOutValid_div (io_rawOutValid_div_0),\n .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0),\n .io_roundingModeOut (io_roundingModeOut_0),\n .io_invalidExc (io_invalidExc_0),\n .io_infiniteExc (io_infiniteExc_0),\n .io_rawOut_isNaN (io_rawOut_isNaN_0),\n .io_rawOut_isInf (io_rawOut_isInf_0),\n .io_rawOut_isZero (io_rawOut_isZero_0),\n .io_rawOut_sign (io_rawOut_sign_0),\n .io_rawOut_sExp (io_rawOut_sExp_0),\n .io_rawOut_sig (io_rawOut_sig_0)\n );\t// @[DivSqrtRecFN_small.scala:446:15]\n assign io_inReady = io_inReady_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOutValid_div = io_rawOutValid_div_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_roundingModeOut = io_roundingModeOut_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_invalidExc = io_invalidExc_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_infiniteExc = io_infiniteExc_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOut_isNaN = io_rawOut_isNaN_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOut_isInf = io_rawOut_isInf_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOut_isZero = io_rawOut_isZero_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOut_sign = io_rawOut_sign_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOut_sExp = io_rawOut_sExp_0;\t// @[DivSqrtRecFN_small.scala:422:5]\n assign io_rawOut_sig = io_rawOut_sig_0;\t// @[DivSqrtRecFN_small.scala:422:5]\nendmodule"}}},{"rowIdx":32182,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) \n node _source_ok_T_1 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) \n node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) \n node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) \n node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) \n node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) \n node _source_ok_T_7 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) \n node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) \n node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) \n node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) \n node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) \n node _source_ok_T_13 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) \n node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) \n node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) \n node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) \n node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) \n node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) \n node _source_ok_T_19 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) \n node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) \n node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) \n node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) \n node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) \n node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) \n node _source_ok_T_31 = shr(io.in.a.bits.source, 3) \n node _source_ok_T_32 = eq(_source_ok_T_31, UInt<3>(0h6)) \n node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) \n node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) \n node _source_ok_T_35 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) \n node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) \n node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) \n node _source_ok_T_39 = shr(io.in.a.bits.source, 3) \n node _source_ok_T_40 = eq(_source_ok_T_39, UInt<3>(0h4)) \n node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) \n node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) \n node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<3>(0h4)) \n node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) \n node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n wire _source_ok_WIRE : UInt<1>[18] \n connect _source_ok_WIRE[0], _source_ok_T \n connect _source_ok_WIRE[1], _source_ok_T_6 \n connect _source_ok_WIRE[2], _source_ok_T_12 \n connect _source_ok_WIRE[3], _source_ok_T_18 \n connect _source_ok_WIRE[4], _source_ok_T_24 \n connect _source_ok_WIRE[5], _source_ok_T_25 \n connect _source_ok_WIRE[6], _source_ok_T_26 \n connect _source_ok_WIRE[7], _source_ok_T_27 \n connect _source_ok_WIRE[8], _source_ok_T_28 \n connect _source_ok_WIRE[9], _source_ok_T_29 \n connect _source_ok_WIRE[10], _source_ok_T_30 \n connect _source_ok_WIRE[11], _source_ok_T_36 \n connect _source_ok_WIRE[12], _source_ok_T_37 \n connect _source_ok_WIRE[13], _source_ok_T_38 \n connect _source_ok_WIRE[14], _source_ok_T_44 \n connect _source_ok_WIRE[15], _source_ok_T_45 \n connect _source_ok_WIRE[16], _source_ok_T_46 \n connect _source_ok_WIRE[17], _source_ok_T_47 \n node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) \n node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) \n node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) \n node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) \n node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) \n node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) \n node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[7]) \n node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[8]) \n node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[9]) \n node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[10]) \n node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[11]) \n node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[12]) \n node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[13]) \n node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[14]) \n node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[15]) \n node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[16]) \n node source_ok = or(_source_ok_T_63, _source_ok_WIRE[17]) \n node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_7 = cvt(_T_6) \n node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) \n node _T_9 = asSInt(_T_8) \n node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) \n node _T_11 = or(_T_5, _T_10) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 1, 0) \n node _T_12 = shr(io.in.a.bits.source, 2) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n node _T_14 = leq(UInt<1>(0h0), uncommonBits) \n node _T_15 = and(_T_13, _T_14) \n node _T_16 = leq(uncommonBits, UInt<2>(0h3)) \n node _T_17 = and(_T_15, _T_16) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_20 = cvt(_T_19) \n node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) \n node _T_22 = asSInt(_T_21) \n node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) \n node _T_24 = or(_T_18, _T_23) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) \n node _T_25 = shr(io.in.a.bits.source, 2) \n node _T_26 = eq(_T_25, UInt<1>(0h1)) \n node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_28 = and(_T_26, _T_27) \n node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) \n node _T_30 = and(_T_28, _T_29) \n node _T_31 = eq(_T_30, UInt<1>(0h0)) \n node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_33 = cvt(_T_32) \n node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) \n node _T_35 = asSInt(_T_34) \n node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) \n node _T_37 = or(_T_31, _T_36) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) \n node _T_38 = shr(io.in.a.bits.source, 2) \n node _T_39 = eq(_T_38, UInt<2>(0h2)) \n node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_41 = and(_T_39, _T_40) \n node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) \n node _T_43 = and(_T_41, _T_42) \n node _T_44 = eq(_T_43, UInt<1>(0h0)) \n node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_46 = cvt(_T_45) \n node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) \n node _T_48 = asSInt(_T_47) \n node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) \n node _T_50 = or(_T_44, _T_49) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) \n node _T_51 = shr(io.in.a.bits.source, 2) \n node _T_52 = eq(_T_51, UInt<2>(0h3)) \n node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_54 = and(_T_52, _T_53) \n node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) \n node _T_56 = and(_T_54, _T_55) \n node _T_57 = eq(_T_56, UInt<1>(0h0)) \n node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_59 = cvt(_T_58) \n node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) \n node _T_61 = asSInt(_T_60) \n node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) \n node _T_63 = or(_T_57, _T_62) \n node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_65 = eq(_T_64, UInt<1>(0h0)) \n node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_67 = cvt(_T_66) \n node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) \n node _T_69 = asSInt(_T_68) \n node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) \n node _T_71 = or(_T_65, _T_70) \n node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_73 = eq(_T_72, UInt<1>(0h0)) \n node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_75 = cvt(_T_74) \n node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) \n node _T_77 = asSInt(_T_76) \n node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) \n node _T_79 = or(_T_73, _T_78) \n node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_81 = eq(_T_80, UInt<1>(0h0)) \n node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_83 = cvt(_T_82) \n node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) \n node _T_85 = asSInt(_T_84) \n node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) \n node _T_87 = or(_T_81, _T_86) \n node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_89 = eq(_T_88, UInt<1>(0h0)) \n node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_91 = cvt(_T_90) \n node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) \n node _T_93 = asSInt(_T_92) \n node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) \n node _T_95 = or(_T_89, _T_94) \n node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_97 = eq(_T_96, UInt<1>(0h0)) \n node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_99 = cvt(_T_98) \n node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) \n node _T_101 = asSInt(_T_100) \n node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) \n node _T_103 = or(_T_97, _T_102) \n node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _T_105 = eq(_T_104, UInt<1>(0h0)) \n node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_107 = cvt(_T_106) \n node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) \n node _T_109 = asSInt(_T_108) \n node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) \n node _T_111 = or(_T_105, _T_110) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) \n node _T_112 = shr(io.in.a.bits.source, 3) \n node _T_113 = eq(_T_112, UInt<3>(0h6)) \n node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_115 = and(_T_113, _T_114) \n node _T_116 = leq(uncommonBits_4, UInt<3>(0h4)) \n node _T_117 = and(_T_115, _T_116) \n node _T_118 = eq(_T_117, UInt<1>(0h0)) \n node _T_119 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_120 = cvt(_T_119) \n node _T_121 = and(_T_120, asSInt(UInt<1>(0h0))) \n node _T_122 = asSInt(_T_121) \n node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) \n node _T_124 = or(_T_118, _T_123) \n node _T_125 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_126 = eq(_T_125, UInt<1>(0h0)) \n node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_128 = cvt(_T_127) \n node _T_129 = and(_T_128, asSInt(UInt<1>(0h0))) \n node _T_130 = asSInt(_T_129) \n node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) \n node _T_132 = or(_T_126, _T_131) \n node _T_133 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _T_134 = eq(_T_133, UInt<1>(0h0)) \n node _T_135 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_136 = cvt(_T_135) \n node _T_137 = and(_T_136, asSInt(UInt<1>(0h0))) \n node _T_138 = asSInt(_T_137) \n node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) \n node _T_140 = or(_T_134, _T_139) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) \n node _T_141 = shr(io.in.a.bits.source, 3) \n node _T_142 = eq(_T_141, UInt<3>(0h4)) \n node _T_143 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_144 = and(_T_142, _T_143) \n node _T_145 = leq(uncommonBits_5, UInt<3>(0h4)) \n node _T_146 = and(_T_144, _T_145) \n node _T_147 = eq(_T_146, UInt<1>(0h0)) \n node _T_148 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_149 = cvt(_T_148) \n node _T_150 = and(_T_149, asSInt(UInt<1>(0h0))) \n node _T_151 = asSInt(_T_150) \n node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0))) \n node _T_153 = or(_T_147, _T_152) \n node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_155 = eq(_T_154, UInt<1>(0h0)) \n node _T_156 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_157 = cvt(_T_156) \n node _T_158 = and(_T_157, asSInt(UInt<1>(0h0))) \n node _T_159 = asSInt(_T_158) \n node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) \n node _T_161 = or(_T_155, _T_160) \n node _T_162 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_163 = eq(_T_162, UInt<1>(0h0)) \n node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_165 = cvt(_T_164) \n node _T_166 = and(_T_165, asSInt(UInt<1>(0h0))) \n node _T_167 = asSInt(_T_166) \n node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) \n node _T_169 = or(_T_163, _T_168) \n node _T_170 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_171 = eq(_T_170, UInt<1>(0h0)) \n node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_173 = cvt(_T_172) \n node _T_174 = and(_T_173, asSInt(UInt<1>(0h0))) \n node _T_175 = asSInt(_T_174) \n node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) \n node _T_177 = or(_T_171, _T_176) \n node _T_178 = and(_T_11, _T_24) \n node _T_179 = and(_T_178, _T_37) \n node _T_180 = and(_T_179, _T_50) \n node _T_181 = and(_T_180, _T_63) \n node _T_182 = and(_T_181, _T_71) \n node _T_183 = and(_T_182, _T_79) \n node _T_184 = and(_T_183, _T_87) \n node _T_185 = and(_T_184, _T_95) \n node _T_186 = and(_T_185, _T_103) \n node _T_187 = and(_T_186, _T_111) \n node _T_188 = and(_T_187, _T_124) \n node _T_189 = and(_T_188, _T_132) \n node _T_190 = and(_T_189, _T_140) \n node _T_191 = and(_T_190, _T_153) \n node _T_192 = and(_T_191, _T_161) \n node _T_193 = and(_T_192, _T_169) \n node _T_194 = and(_T_193, _T_177) \n node _T_195 = asUInt(reset) \n node _T_196 = eq(_T_195, UInt<1>(0h0)) \n when _T_196 : \n node _T_197 = eq(_T_194, UInt<1>(0h0)) \n when _T_197 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_194, UInt<1>(0h1), \"\") : assert_1 \n node _T_198 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_198 : \n node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_201 = and(_T_199, _T_200) \n node _T_202 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) \n node _T_203 = shr(io.in.a.bits.source, 2) \n node _T_204 = eq(_T_203, UInt<1>(0h0)) \n node _T_205 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_206 = and(_T_204, _T_205) \n node _T_207 = leq(uncommonBits_6, UInt<2>(0h3)) \n node _T_208 = and(_T_206, _T_207) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) \n node _T_209 = shr(io.in.a.bits.source, 2) \n node _T_210 = eq(_T_209, UInt<1>(0h1)) \n node _T_211 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_212 = and(_T_210, _T_211) \n node _T_213 = leq(uncommonBits_7, UInt<2>(0h3)) \n node _T_214 = and(_T_212, _T_213) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) \n node _T_215 = shr(io.in.a.bits.source, 2) \n node _T_216 = eq(_T_215, UInt<2>(0h2)) \n node _T_217 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_218 = and(_T_216, _T_217) \n node _T_219 = leq(uncommonBits_8, UInt<2>(0h3)) \n node _T_220 = and(_T_218, _T_219) \n node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) \n node _T_221 = shr(io.in.a.bits.source, 2) \n node _T_222 = eq(_T_221, UInt<2>(0h3)) \n node _T_223 = leq(UInt<1>(0h0), uncommonBits_9) \n node _T_224 = and(_T_222, _T_223) \n node _T_225 = leq(uncommonBits_9, UInt<2>(0h3)) \n node _T_226 = and(_T_224, _T_225) \n node _T_227 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_228 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_230 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_231 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) \n node _T_233 = shr(io.in.a.bits.source, 3) \n node _T_234 = eq(_T_233, UInt<3>(0h6)) \n node _T_235 = leq(UInt<1>(0h0), uncommonBits_10) \n node _T_236 = and(_T_234, _T_235) \n node _T_237 = leq(uncommonBits_10, UInt<3>(0h4)) \n node _T_238 = and(_T_236, _T_237) \n node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) \n node _T_241 = shr(io.in.a.bits.source, 3) \n node _T_242 = eq(_T_241, UInt<3>(0h4)) \n node _T_243 = leq(UInt<1>(0h0), uncommonBits_11) \n node _T_244 = and(_T_242, _T_243) \n node _T_245 = leq(uncommonBits_11, UInt<3>(0h4)) \n node _T_246 = and(_T_244, _T_245) \n node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_249 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_250 = or(_T_202, _T_208) \n node _T_251 = or(_T_250, _T_214) \n node _T_252 = or(_T_251, _T_220) \n node _T_253 = or(_T_252, _T_226) \n node _T_254 = or(_T_253, _T_227) \n node _T_255 = or(_T_254, _T_228) \n node _T_256 = or(_T_255, _T_229) \n node _T_257 = or(_T_256, _T_230) \n node _T_258 = or(_T_257, _T_231) \n node _T_259 = or(_T_258, _T_232) \n node _T_260 = or(_T_259, _T_238) \n node _T_261 = or(_T_260, _T_239) \n node _T_262 = or(_T_261, _T_240) \n node _T_263 = or(_T_262, _T_246) \n node _T_264 = or(_T_263, _T_247) \n node _T_265 = or(_T_264, _T_248) \n node _T_266 = or(_T_265, _T_249) \n node _T_267 = and(_T_201, _T_266) \n node _T_268 = or(UInt<1>(0h0), _T_267) \n node _T_269 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_270 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_271 = cvt(_T_270) \n node _T_272 = and(_T_271, asSInt(UInt<14>(0h2000))) \n node _T_273 = asSInt(_T_272) \n node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0))) \n node _T_275 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_276 = cvt(_T_275) \n node _T_277 = and(_T_276, asSInt(UInt<13>(0h1000))) \n node _T_278 = asSInt(_T_277) \n node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0))) \n node _T_280 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_281 = cvt(_T_280) \n node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) \n node _T_283 = asSInt(_T_282) \n node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) \n node _T_285 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_286 = cvt(_T_285) \n node _T_287 = and(_T_286, asSInt(UInt<18>(0h2f000))) \n node _T_288 = asSInt(_T_287) \n node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) \n node _T_290 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_291 = cvt(_T_290) \n node _T_292 = and(_T_291, asSInt(UInt<17>(0h10000))) \n node _T_293 = asSInt(_T_292) \n node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) \n node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_296 = cvt(_T_295) \n node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) \n node _T_298 = asSInt(_T_297) \n node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) \n node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_301 = cvt(_T_300) \n node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000))) \n node _T_303 = asSInt(_T_302) \n node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) \n node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_306 = cvt(_T_305) \n node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000))) \n node _T_308 = asSInt(_T_307) \n node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) \n node _T_310 = or(_T_274, _T_279) \n node _T_311 = or(_T_310, _T_284) \n node _T_312 = or(_T_311, _T_289) \n node _T_313 = or(_T_312, _T_294) \n node _T_314 = or(_T_313, _T_299) \n node _T_315 = or(_T_314, _T_304) \n node _T_316 = or(_T_315, _T_309) \n node _T_317 = and(_T_269, _T_316) \n node _T_318 = or(UInt<1>(0h0), _T_317) \n node _T_319 = and(_T_268, _T_318) \n node _T_320 = asUInt(reset) \n node _T_321 = eq(_T_320, UInt<1>(0h0)) \n when _T_321 : \n node _T_322 = eq(_T_319, UInt<1>(0h0)) \n when _T_322 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_319, UInt<1>(0h1), \"\") : assert_2 \n node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) \n node _T_324 = shr(io.in.a.bits.source, 2) \n node _T_325 = eq(_T_324, UInt<1>(0h0)) \n node _T_326 = leq(UInt<1>(0h0), uncommonBits_12) \n node _T_327 = and(_T_325, _T_326) \n node _T_328 = leq(uncommonBits_12, UInt<2>(0h3)) \n node _T_329 = and(_T_327, _T_328) \n node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) \n node _T_330 = shr(io.in.a.bits.source, 2) \n node _T_331 = eq(_T_330, UInt<1>(0h1)) \n node _T_332 = leq(UInt<1>(0h0), uncommonBits_13) \n node _T_333 = and(_T_331, _T_332) \n node _T_334 = leq(uncommonBits_13, UInt<2>(0h3)) \n node _T_335 = and(_T_333, _T_334) \n node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) \n node _T_336 = shr(io.in.a.bits.source, 2) \n node _T_337 = eq(_T_336, UInt<2>(0h2)) \n node _T_338 = leq(UInt<1>(0h0), uncommonBits_14) \n node _T_339 = and(_T_337, _T_338) \n node _T_340 = leq(uncommonBits_14, UInt<2>(0h3)) \n node _T_341 = and(_T_339, _T_340) \n node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) \n node _T_342 = shr(io.in.a.bits.source, 2) \n node _T_343 = eq(_T_342, UInt<2>(0h3)) \n node _T_344 = leq(UInt<1>(0h0), uncommonBits_15) \n node _T_345 = and(_T_343, _T_344) \n node _T_346 = leq(uncommonBits_15, UInt<2>(0h3)) \n node _T_347 = and(_T_345, _T_346) \n node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_350 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_351 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_352 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_353 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) \n node _T_354 = shr(io.in.a.bits.source, 3) \n node _T_355 = eq(_T_354, UInt<3>(0h6)) \n node _T_356 = leq(UInt<1>(0h0), uncommonBits_16) \n node _T_357 = and(_T_355, _T_356) \n node _T_358 = leq(uncommonBits_16, UInt<3>(0h4)) \n node _T_359 = and(_T_357, _T_358) \n node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_361 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) \n node _T_362 = shr(io.in.a.bits.source, 3) \n node _T_363 = eq(_T_362, UInt<3>(0h4)) \n node _T_364 = leq(UInt<1>(0h0), uncommonBits_17) \n node _T_365 = and(_T_363, _T_364) \n node _T_366 = leq(uncommonBits_17, UInt<3>(0h4)) \n node _T_367 = and(_T_365, _T_366) \n node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_370 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n wire _WIRE : UInt<1>[18] \n connect _WIRE[0], _T_323 \n connect _WIRE[1], _T_329 \n connect _WIRE[2], _T_335 \n connect _WIRE[3], _T_341 \n connect _WIRE[4], _T_347 \n connect _WIRE[5], _T_348 \n connect _WIRE[6], _T_349 \n connect _WIRE[7], _T_350 \n connect _WIRE[8], _T_351 \n connect _WIRE[9], _T_352 \n connect _WIRE[10], _T_353 \n connect _WIRE[11], _T_359 \n connect _WIRE[12], _T_360 \n connect _WIRE[13], _T_361 \n connect _WIRE[14], _T_367 \n connect _WIRE[15], _T_368 \n connect _WIRE[16], _T_369 \n connect _WIRE[17], _T_370 \n node _T_371 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_372 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_373 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_375 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_376 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_377 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_378 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_379 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_380 = mux(_WIRE[5], _T_371, UInt<1>(0h0)) \n node _T_381 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_382 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_383 = mux(_WIRE[8], _T_372, UInt<1>(0h0)) \n node _T_384 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_385 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_386 = mux(_WIRE[11], _T_373, UInt<1>(0h0)) \n node _T_387 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_388 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_389 = mux(_WIRE[14], _T_374, UInt<1>(0h0)) \n node _T_390 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_391 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_392 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_393 = or(_T_375, _T_376) \n node _T_394 = or(_T_393, _T_377) \n node _T_395 = or(_T_394, _T_378) \n node _T_396 = or(_T_395, _T_379) \n node _T_397 = or(_T_396, _T_380) \n node _T_398 = or(_T_397, _T_381) \n node _T_399 = or(_T_398, _T_382) \n node _T_400 = or(_T_399, _T_383) \n node _T_401 = or(_T_400, _T_384) \n node _T_402 = or(_T_401, _T_385) \n node _T_403 = or(_T_402, _T_386) \n node _T_404 = or(_T_403, _T_387) \n node _T_405 = or(_T_404, _T_388) \n node _T_406 = or(_T_405, _T_389) \n node _T_407 = or(_T_406, _T_390) \n node _T_408 = or(_T_407, _T_391) \n node _T_409 = or(_T_408, _T_392) \n wire _WIRE_1 : UInt<1> \n connect _WIRE_1, _T_409 \n node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_412 = and(_T_410, _T_411) \n node _T_413 = or(UInt<1>(0h0), _T_412) \n node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_415 = cvt(_T_414) \n node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000))) \n node _T_417 = asSInt(_T_416) \n node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) \n node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_420 = cvt(_T_419) \n node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) \n node _T_422 = asSInt(_T_421) \n node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) \n node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_425 = cvt(_T_424) \n node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) \n node _T_427 = asSInt(_T_426) \n node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) \n node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_430 = cvt(_T_429) \n node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000))) \n node _T_432 = asSInt(_T_431) \n node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) \n node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_435 = cvt(_T_434) \n node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000))) \n node _T_437 = asSInt(_T_436) \n node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) \n node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_440 = cvt(_T_439) \n node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000))) \n node _T_442 = asSInt(_T_441) \n node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) \n node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_445 = cvt(_T_444) \n node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000))) \n node _T_447 = asSInt(_T_446) \n node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) \n node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_450 = cvt(_T_449) \n node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000))) \n node _T_452 = asSInt(_T_451) \n node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) \n node _T_454 = or(_T_418, _T_423) \n node _T_455 = or(_T_454, _T_428) \n node _T_456 = or(_T_455, _T_433) \n node _T_457 = or(_T_456, _T_438) \n node _T_458 = or(_T_457, _T_443) \n node _T_459 = or(_T_458, _T_448) \n node _T_460 = or(_T_459, _T_453) \n node _T_461 = and(_T_413, _T_460) \n node _T_462 = or(UInt<1>(0h0), _T_461) \n node _T_463 = and(_WIRE_1, _T_462) \n node _T_464 = asUInt(reset) \n node _T_465 = eq(_T_464, UInt<1>(0h0)) \n when _T_465 : \n node _T_466 = eq(_T_463, UInt<1>(0h0)) \n when _T_466 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_463, UInt<1>(0h1), \"\") : assert_3 \n node _T_467 = asUInt(reset) \n node _T_468 = eq(_T_467, UInt<1>(0h0)) \n when _T_468 : \n node _T_469 = eq(source_ok, UInt<1>(0h0)) \n when _T_469 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_4 \n node _T_470 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_471 = asUInt(reset) \n node _T_472 = eq(_T_471, UInt<1>(0h0)) \n when _T_472 : \n node _T_473 = eq(_T_470, UInt<1>(0h0)) \n when _T_473 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_470, UInt<1>(0h1), \"\") : assert_5 \n node _T_474 = asUInt(reset) \n node _T_475 = eq(_T_474, UInt<1>(0h0)) \n when _T_475 : \n node _T_476 = eq(is_aligned, UInt<1>(0h0)) \n when _T_476 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_477 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_478 = asUInt(reset) \n node _T_479 = eq(_T_478, UInt<1>(0h0)) \n when _T_479 : \n node _T_480 = eq(_T_477, UInt<1>(0h0)) \n when _T_480 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_477, UInt<1>(0h1), \"\") : assert_7 \n node _T_481 = not(io.in.a.bits.mask) \n node _T_482 = eq(_T_481, UInt<1>(0h0)) \n node _T_483 = asUInt(reset) \n node _T_484 = eq(_T_483, UInt<1>(0h0)) \n when _T_484 : \n node _T_485 = eq(_T_482, UInt<1>(0h0)) \n when _T_485 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_482, UInt<1>(0h1), \"\") : assert_8 \n node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_487 = asUInt(reset) \n node _T_488 = eq(_T_487, UInt<1>(0h0)) \n when _T_488 : \n node _T_489 = eq(_T_486, UInt<1>(0h0)) \n when _T_489 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_486, UInt<1>(0h1), \"\") : assert_9 \n node _T_490 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_490 : \n node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_493 = and(_T_491, _T_492) \n node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) \n node _T_495 = shr(io.in.a.bits.source, 2) \n node _T_496 = eq(_T_495, UInt<1>(0h0)) \n node _T_497 = leq(UInt<1>(0h0), uncommonBits_18) \n node _T_498 = and(_T_496, _T_497) \n node _T_499 = leq(uncommonBits_18, UInt<2>(0h3)) \n node _T_500 = and(_T_498, _T_499) \n node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) \n node _T_501 = shr(io.in.a.bits.source, 2) \n node _T_502 = eq(_T_501, UInt<1>(0h1)) \n node _T_503 = leq(UInt<1>(0h0), uncommonBits_19) \n node _T_504 = and(_T_502, _T_503) \n node _T_505 = leq(uncommonBits_19, UInt<2>(0h3)) \n node _T_506 = and(_T_504, _T_505) \n node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) \n node _T_507 = shr(io.in.a.bits.source, 2) \n node _T_508 = eq(_T_507, UInt<2>(0h2)) \n node _T_509 = leq(UInt<1>(0h0), uncommonBits_20) \n node _T_510 = and(_T_508, _T_509) \n node _T_511 = leq(uncommonBits_20, UInt<2>(0h3)) \n node _T_512 = and(_T_510, _T_511) \n node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) \n node _T_513 = shr(io.in.a.bits.source, 2) \n node _T_514 = eq(_T_513, UInt<2>(0h3)) \n node _T_515 = leq(UInt<1>(0h0), uncommonBits_21) \n node _T_516 = and(_T_514, _T_515) \n node _T_517 = leq(uncommonBits_21, UInt<2>(0h3)) \n node _T_518 = and(_T_516, _T_517) \n node _T_519 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_520 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_521 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_524 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0) \n node _T_525 = shr(io.in.a.bits.source, 3) \n node _T_526 = eq(_T_525, UInt<3>(0h6)) \n node _T_527 = leq(UInt<1>(0h0), uncommonBits_22) \n node _T_528 = and(_T_526, _T_527) \n node _T_529 = leq(uncommonBits_22, UInt<3>(0h4)) \n node _T_530 = and(_T_528, _T_529) \n node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0) \n node _T_533 = shr(io.in.a.bits.source, 3) \n node _T_534 = eq(_T_533, UInt<3>(0h4)) \n node _T_535 = leq(UInt<1>(0h0), uncommonBits_23) \n node _T_536 = and(_T_534, _T_535) \n node _T_537 = leq(uncommonBits_23, UInt<3>(0h4)) \n node _T_538 = and(_T_536, _T_537) \n node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_540 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_541 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_542 = or(_T_494, _T_500) \n node _T_543 = or(_T_542, _T_506) \n node _T_544 = or(_T_543, _T_512) \n node _T_545 = or(_T_544, _T_518) \n node _T_546 = or(_T_545, _T_519) \n node _T_547 = or(_T_546, _T_520) \n node _T_548 = or(_T_547, _T_521) \n node _T_549 = or(_T_548, _T_522) \n node _T_550 = or(_T_549, _T_523) \n node _T_551 = or(_T_550, _T_524) \n node _T_552 = or(_T_551, _T_530) \n node _T_553 = or(_T_552, _T_531) \n node _T_554 = or(_T_553, _T_532) \n node _T_555 = or(_T_554, _T_538) \n node _T_556 = or(_T_555, _T_539) \n node _T_557 = or(_T_556, _T_540) \n node _T_558 = or(_T_557, _T_541) \n node _T_559 = and(_T_493, _T_558) \n node _T_560 = or(UInt<1>(0h0), _T_559) \n node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_562 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_563 = cvt(_T_562) \n node _T_564 = and(_T_563, asSInt(UInt<14>(0h2000))) \n node _T_565 = asSInt(_T_564) \n node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) \n node _T_567 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_568 = cvt(_T_567) \n node _T_569 = and(_T_568, asSInt(UInt<13>(0h1000))) \n node _T_570 = asSInt(_T_569) \n node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) \n node _T_572 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_573 = cvt(_T_572) \n node _T_574 = and(_T_573, asSInt(UInt<17>(0h10000))) \n node _T_575 = asSInt(_T_574) \n node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) \n node _T_577 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_578 = cvt(_T_577) \n node _T_579 = and(_T_578, asSInt(UInt<18>(0h2f000))) \n node _T_580 = asSInt(_T_579) \n node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) \n node _T_582 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_583 = cvt(_T_582) \n node _T_584 = and(_T_583, asSInt(UInt<17>(0h10000))) \n node _T_585 = asSInt(_T_584) \n node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) \n node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_588 = cvt(_T_587) \n node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000))) \n node _T_590 = asSInt(_T_589) \n node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) \n node _T_592 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_593 = cvt(_T_592) \n node _T_594 = and(_T_593, asSInt(UInt<27>(0h4000000))) \n node _T_595 = asSInt(_T_594) \n node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0))) \n node _T_597 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_598 = cvt(_T_597) \n node _T_599 = and(_T_598, asSInt(UInt<13>(0h1000))) \n node _T_600 = asSInt(_T_599) \n node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0))) \n node _T_602 = or(_T_566, _T_571) \n node _T_603 = or(_T_602, _T_576) \n node _T_604 = or(_T_603, _T_581) \n node _T_605 = or(_T_604, _T_586) \n node _T_606 = or(_T_605, _T_591) \n node _T_607 = or(_T_606, _T_596) \n node _T_608 = or(_T_607, _T_601) \n node _T_609 = and(_T_561, _T_608) \n node _T_610 = or(UInt<1>(0h0), _T_609) \n node _T_611 = and(_T_560, _T_610) \n node _T_612 = asUInt(reset) \n node _T_613 = eq(_T_612, UInt<1>(0h0)) \n when _T_613 : \n node _T_614 = eq(_T_611, UInt<1>(0h0)) \n when _T_614 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_611, UInt<1>(0h1), \"\") : assert_10 \n node _T_615 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) \n node _T_616 = shr(io.in.a.bits.source, 2) \n node _T_617 = eq(_T_616, UInt<1>(0h0)) \n node _T_618 = leq(UInt<1>(0h0), uncommonBits_24) \n node _T_619 = and(_T_617, _T_618) \n node _T_620 = leq(uncommonBits_24, UInt<2>(0h3)) \n node _T_621 = and(_T_619, _T_620) \n node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) \n node _T_622 = shr(io.in.a.bits.source, 2) \n node _T_623 = eq(_T_622, UInt<1>(0h1)) \n node _T_624 = leq(UInt<1>(0h0), uncommonBits_25) \n node _T_625 = and(_T_623, _T_624) \n node _T_626 = leq(uncommonBits_25, UInt<2>(0h3)) \n node _T_627 = and(_T_625, _T_626) \n node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) \n node _T_628 = shr(io.in.a.bits.source, 2) \n node _T_629 = eq(_T_628, UInt<2>(0h2)) \n node _T_630 = leq(UInt<1>(0h0), uncommonBits_26) \n node _T_631 = and(_T_629, _T_630) \n node _T_632 = leq(uncommonBits_26, UInt<2>(0h3)) \n node _T_633 = and(_T_631, _T_632) \n node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) \n node _T_634 = shr(io.in.a.bits.source, 2) \n node _T_635 = eq(_T_634, UInt<2>(0h3)) \n node _T_636 = leq(UInt<1>(0h0), uncommonBits_27) \n node _T_637 = and(_T_635, _T_636) \n node _T_638 = leq(uncommonBits_27, UInt<2>(0h3)) \n node _T_639 = and(_T_637, _T_638) \n node _T_640 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_642 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_643 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_644 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_645 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0) \n node _T_646 = shr(io.in.a.bits.source, 3) \n node _T_647 = eq(_T_646, UInt<3>(0h6)) \n node _T_648 = leq(UInt<1>(0h0), uncommonBits_28) \n node _T_649 = and(_T_647, _T_648) \n node _T_650 = leq(uncommonBits_28, UInt<3>(0h4)) \n node _T_651 = and(_T_649, _T_650) \n node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_653 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) \n node _T_654 = shr(io.in.a.bits.source, 3) \n node _T_655 = eq(_T_654, UInt<3>(0h4)) \n node _T_656 = leq(UInt<1>(0h0), uncommonBits_29) \n node _T_657 = and(_T_655, _T_656) \n node _T_658 = leq(uncommonBits_29, UInt<3>(0h4)) \n node _T_659 = and(_T_657, _T_658) \n node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_662 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n wire _WIRE_2 : UInt<1>[18] \n connect _WIRE_2[0], _T_615 \n connect _WIRE_2[1], _T_621 \n connect _WIRE_2[2], _T_627 \n connect _WIRE_2[3], _T_633 \n connect _WIRE_2[4], _T_639 \n connect _WIRE_2[5], _T_640 \n connect _WIRE_2[6], _T_641 \n connect _WIRE_2[7], _T_642 \n connect _WIRE_2[8], _T_643 \n connect _WIRE_2[9], _T_644 \n connect _WIRE_2[10], _T_645 \n connect _WIRE_2[11], _T_651 \n connect _WIRE_2[12], _T_652 \n connect _WIRE_2[13], _T_653 \n connect _WIRE_2[14], _T_659 \n connect _WIRE_2[15], _T_660 \n connect _WIRE_2[16], _T_661 \n connect _WIRE_2[17], _T_662 \n node _T_663 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_664 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_665 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_666 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_667 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_668 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_669 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_670 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_671 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_672 = mux(_WIRE_2[5], _T_663, UInt<1>(0h0)) \n node _T_673 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_674 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_675 = mux(_WIRE_2[8], _T_664, UInt<1>(0h0)) \n node _T_676 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_677 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_678 = mux(_WIRE_2[11], _T_665, UInt<1>(0h0)) \n node _T_679 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_680 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_681 = mux(_WIRE_2[14], _T_666, UInt<1>(0h0)) \n node _T_682 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_683 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_684 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_685 = or(_T_667, _T_668) \n node _T_686 = or(_T_685, _T_669) \n node _T_687 = or(_T_686, _T_670) \n node _T_688 = or(_T_687, _T_671) \n node _T_689 = or(_T_688, _T_672) \n node _T_690 = or(_T_689, _T_673) \n node _T_691 = or(_T_690, _T_674) \n node _T_692 = or(_T_691, _T_675) \n node _T_693 = or(_T_692, _T_676) \n node _T_694 = or(_T_693, _T_677) \n node _T_695 = or(_T_694, _T_678) \n node _T_696 = or(_T_695, _T_679) \n node _T_697 = or(_T_696, _T_680) \n node _T_698 = or(_T_697, _T_681) \n node _T_699 = or(_T_698, _T_682) \n node _T_700 = or(_T_699, _T_683) \n node _T_701 = or(_T_700, _T_684) \n wire _WIRE_3 : UInt<1> \n connect _WIRE_3, _T_701 \n node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_703 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_704 = and(_T_702, _T_703) \n node _T_705 = or(UInt<1>(0h0), _T_704) \n node _T_706 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_707 = cvt(_T_706) \n node _T_708 = and(_T_707, asSInt(UInt<14>(0h2000))) \n node _T_709 = asSInt(_T_708) \n node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) \n node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_712 = cvt(_T_711) \n node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000))) \n node _T_714 = asSInt(_T_713) \n node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) \n node _T_716 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_717 = cvt(_T_716) \n node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) \n node _T_719 = asSInt(_T_718) \n node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) \n node _T_721 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_722 = cvt(_T_721) \n node _T_723 = and(_T_722, asSInt(UInt<18>(0h2f000))) \n node _T_724 = asSInt(_T_723) \n node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) \n node _T_726 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_727 = cvt(_T_726) \n node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) \n node _T_729 = asSInt(_T_728) \n node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) \n node _T_731 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_732 = cvt(_T_731) \n node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) \n node _T_734 = asSInt(_T_733) \n node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) \n node _T_736 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_737 = cvt(_T_736) \n node _T_738 = and(_T_737, asSInt(UInt<27>(0h4000000))) \n node _T_739 = asSInt(_T_738) \n node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) \n node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_742 = cvt(_T_741) \n node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) \n node _T_744 = asSInt(_T_743) \n node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) \n node _T_746 = or(_T_710, _T_715) \n node _T_747 = or(_T_746, _T_720) \n node _T_748 = or(_T_747, _T_725) \n node _T_749 = or(_T_748, _T_730) \n node _T_750 = or(_T_749, _T_735) \n node _T_751 = or(_T_750, _T_740) \n node _T_752 = or(_T_751, _T_745) \n node _T_753 = and(_T_705, _T_752) \n node _T_754 = or(UInt<1>(0h0), _T_753) \n node _T_755 = and(_WIRE_3, _T_754) \n node _T_756 = asUInt(reset) \n node _T_757 = eq(_T_756, UInt<1>(0h0)) \n when _T_757 : \n node _T_758 = eq(_T_755, UInt<1>(0h0)) \n when _T_758 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_755, UInt<1>(0h1), \"\") : assert_11 \n node _T_759 = asUInt(reset) \n node _T_760 = eq(_T_759, UInt<1>(0h0)) \n when _T_760 : \n node _T_761 = eq(source_ok, UInt<1>(0h0)) \n when _T_761 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_12 \n node _T_762 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_763 = asUInt(reset) \n node _T_764 = eq(_T_763, UInt<1>(0h0)) \n when _T_764 : \n node _T_765 = eq(_T_762, UInt<1>(0h0)) \n when _T_765 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_762, UInt<1>(0h1), \"\") : assert_13 \n node _T_766 = asUInt(reset) \n node _T_767 = eq(_T_766, UInt<1>(0h0)) \n when _T_767 : \n node _T_768 = eq(is_aligned, UInt<1>(0h0)) \n when _T_768 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_769 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_770 = asUInt(reset) \n node _T_771 = eq(_T_770, UInt<1>(0h0)) \n when _T_771 : \n node _T_772 = eq(_T_769, UInt<1>(0h0)) \n when _T_772 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_769, UInt<1>(0h1), \"\") : assert_15 \n node _T_773 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_774 = asUInt(reset) \n node _T_775 = eq(_T_774, UInt<1>(0h0)) \n when _T_775 : \n node _T_776 = eq(_T_773, UInt<1>(0h0)) \n when _T_776 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_773, UInt<1>(0h1), \"\") : assert_16 \n node _T_777 = not(io.in.a.bits.mask) \n node _T_778 = eq(_T_777, UInt<1>(0h0)) \n node _T_779 = asUInt(reset) \n node _T_780 = eq(_T_779, UInt<1>(0h0)) \n when _T_780 : \n node _T_781 = eq(_T_778, UInt<1>(0h0)) \n when _T_781 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_778, UInt<1>(0h1), \"\") : assert_17 \n node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_783 = asUInt(reset) \n node _T_784 = eq(_T_783, UInt<1>(0h0)) \n when _T_784 : \n node _T_785 = eq(_T_782, UInt<1>(0h0)) \n when _T_785 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_782, UInt<1>(0h1), \"\") : assert_18 \n node _T_786 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_786 : \n node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_789 = and(_T_787, _T_788) \n node _T_790 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) \n node _T_791 = shr(io.in.a.bits.source, 2) \n node _T_792 = eq(_T_791, UInt<1>(0h0)) \n node _T_793 = leq(UInt<1>(0h0), uncommonBits_30) \n node _T_794 = and(_T_792, _T_793) \n node _T_795 = leq(uncommonBits_30, UInt<2>(0h3)) \n node _T_796 = and(_T_794, _T_795) \n node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) \n node _T_797 = shr(io.in.a.bits.source, 2) \n node _T_798 = eq(_T_797, UInt<1>(0h1)) \n node _T_799 = leq(UInt<1>(0h0), uncommonBits_31) \n node _T_800 = and(_T_798, _T_799) \n node _T_801 = leq(uncommonBits_31, UInt<2>(0h3)) \n node _T_802 = and(_T_800, _T_801) \n node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) \n node _T_803 = shr(io.in.a.bits.source, 2) \n node _T_804 = eq(_T_803, UInt<2>(0h2)) \n node _T_805 = leq(UInt<1>(0h0), uncommonBits_32) \n node _T_806 = and(_T_804, _T_805) \n node _T_807 = leq(uncommonBits_32, UInt<2>(0h3)) \n node _T_808 = and(_T_806, _T_807) \n node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) \n node _T_809 = shr(io.in.a.bits.source, 2) \n node _T_810 = eq(_T_809, UInt<2>(0h3)) \n node _T_811 = leq(UInt<1>(0h0), uncommonBits_33) \n node _T_812 = and(_T_810, _T_811) \n node _T_813 = leq(uncommonBits_33, UInt<2>(0h3)) \n node _T_814 = and(_T_812, _T_813) \n node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_816 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_817 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_818 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_819 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) \n node _T_821 = shr(io.in.a.bits.source, 3) \n node _T_822 = eq(_T_821, UInt<3>(0h6)) \n node _T_823 = leq(UInt<1>(0h0), uncommonBits_34) \n node _T_824 = and(_T_822, _T_823) \n node _T_825 = leq(uncommonBits_34, UInt<3>(0h4)) \n node _T_826 = and(_T_824, _T_825) \n node _T_827 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_828 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0) \n node _T_829 = shr(io.in.a.bits.source, 3) \n node _T_830 = eq(_T_829, UInt<3>(0h4)) \n node _T_831 = leq(UInt<1>(0h0), uncommonBits_35) \n node _T_832 = and(_T_830, _T_831) \n node _T_833 = leq(uncommonBits_35, UInt<3>(0h4)) \n node _T_834 = and(_T_832, _T_833) \n node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_837 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_838 = or(_T_790, _T_796) \n node _T_839 = or(_T_838, _T_802) \n node _T_840 = or(_T_839, _T_808) \n node _T_841 = or(_T_840, _T_814) \n node _T_842 = or(_T_841, _T_815) \n node _T_843 = or(_T_842, _T_816) \n node _T_844 = or(_T_843, _T_817) \n node _T_845 = or(_T_844, _T_818) \n node _T_846 = or(_T_845, _T_819) \n node _T_847 = or(_T_846, _T_820) \n node _T_848 = or(_T_847, _T_826) \n node _T_849 = or(_T_848, _T_827) \n node _T_850 = or(_T_849, _T_828) \n node _T_851 = or(_T_850, _T_834) \n node _T_852 = or(_T_851, _T_835) \n node _T_853 = or(_T_852, _T_836) \n node _T_854 = or(_T_853, _T_837) \n node _T_855 = and(_T_789, _T_854) \n node _T_856 = or(UInt<1>(0h0), _T_855) \n node _T_857 = asUInt(reset) \n node _T_858 = eq(_T_857, UInt<1>(0h0)) \n when _T_858 : \n node _T_859 = eq(_T_856, UInt<1>(0h0)) \n when _T_859 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_856, UInt<1>(0h1), \"\") : assert_19 \n node _T_860 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_861 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_862 = and(_T_860, _T_861) \n node _T_863 = or(UInt<1>(0h0), _T_862) \n node _T_864 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_865 = cvt(_T_864) \n node _T_866 = and(_T_865, asSInt(UInt<13>(0h1000))) \n node _T_867 = asSInt(_T_866) \n node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) \n node _T_869 = and(_T_863, _T_868) \n node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_871 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_872 = and(_T_870, _T_871) \n node _T_873 = or(UInt<1>(0h0), _T_872) \n node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_875 = cvt(_T_874) \n node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) \n node _T_877 = asSInt(_T_876) \n node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) \n node _T_879 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_880 = cvt(_T_879) \n node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) \n node _T_882 = asSInt(_T_881) \n node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) \n node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_885 = cvt(_T_884) \n node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) \n node _T_887 = asSInt(_T_886) \n node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) \n node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_890 = cvt(_T_889) \n node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) \n node _T_892 = asSInt(_T_891) \n node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) \n node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_895 = cvt(_T_894) \n node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) \n node _T_897 = asSInt(_T_896) \n node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) \n node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_900 = cvt(_T_899) \n node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) \n node _T_902 = asSInt(_T_901) \n node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) \n node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_905 = cvt(_T_904) \n node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) \n node _T_907 = asSInt(_T_906) \n node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) \n node _T_909 = or(_T_878, _T_883) \n node _T_910 = or(_T_909, _T_888) \n node _T_911 = or(_T_910, _T_893) \n node _T_912 = or(_T_911, _T_898) \n node _T_913 = or(_T_912, _T_903) \n node _T_914 = or(_T_913, _T_908) \n node _T_915 = and(_T_873, _T_914) \n node _T_916 = or(UInt<1>(0h0), _T_869) \n node _T_917 = or(_T_916, _T_915) \n node _T_918 = asUInt(reset) \n node _T_919 = eq(_T_918, UInt<1>(0h0)) \n when _T_919 : \n node _T_920 = eq(_T_917, UInt<1>(0h0)) \n when _T_920 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_917, UInt<1>(0h1), \"\") : assert_20 \n node _T_921 = asUInt(reset) \n node _T_922 = eq(_T_921, UInt<1>(0h0)) \n when _T_922 : \n node _T_923 = eq(source_ok, UInt<1>(0h0)) \n when _T_923 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_21 \n node _T_924 = asUInt(reset) \n node _T_925 = eq(_T_924, UInt<1>(0h0)) \n when _T_925 : \n node _T_926 = eq(is_aligned, UInt<1>(0h0)) \n when _T_926 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_927 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_928 = asUInt(reset) \n node _T_929 = eq(_T_928, UInt<1>(0h0)) \n when _T_929 : \n node _T_930 = eq(_T_927, UInt<1>(0h0)) \n when _T_930 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_927, UInt<1>(0h1), \"\") : assert_23 \n node _T_931 = eq(io.in.a.bits.mask, mask) \n node _T_932 = asUInt(reset) \n node _T_933 = eq(_T_932, UInt<1>(0h0)) \n when _T_933 : \n node _T_934 = eq(_T_931, UInt<1>(0h0)) \n when _T_934 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_931, UInt<1>(0h1), \"\") : assert_24 \n node _T_935 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_936 = asUInt(reset) \n node _T_937 = eq(_T_936, UInt<1>(0h0)) \n when _T_937 : \n node _T_938 = eq(_T_935, UInt<1>(0h0)) \n when _T_938 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_935, UInt<1>(0h1), \"\") : assert_25 \n node _T_939 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_939 : \n node _T_940 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_941 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_942 = and(_T_940, _T_941) \n node _T_943 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) \n node _T_944 = shr(io.in.a.bits.source, 2) \n node _T_945 = eq(_T_944, UInt<1>(0h0)) \n node _T_946 = leq(UInt<1>(0h0), uncommonBits_36) \n node _T_947 = and(_T_945, _T_946) \n node _T_948 = leq(uncommonBits_36, UInt<2>(0h3)) \n node _T_949 = and(_T_947, _T_948) \n node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) \n node _T_950 = shr(io.in.a.bits.source, 2) \n node _T_951 = eq(_T_950, UInt<1>(0h1)) \n node _T_952 = leq(UInt<1>(0h0), uncommonBits_37) \n node _T_953 = and(_T_951, _T_952) \n node _T_954 = leq(uncommonBits_37, UInt<2>(0h3)) \n node _T_955 = and(_T_953, _T_954) \n node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) \n node _T_956 = shr(io.in.a.bits.source, 2) \n node _T_957 = eq(_T_956, UInt<2>(0h2)) \n node _T_958 = leq(UInt<1>(0h0), uncommonBits_38) \n node _T_959 = and(_T_957, _T_958) \n node _T_960 = leq(uncommonBits_38, UInt<2>(0h3)) \n node _T_961 = and(_T_959, _T_960) \n node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) \n node _T_962 = shr(io.in.a.bits.source, 2) \n node _T_963 = eq(_T_962, UInt<2>(0h3)) \n node _T_964 = leq(UInt<1>(0h0), uncommonBits_39) \n node _T_965 = and(_T_963, _T_964) \n node _T_966 = leq(uncommonBits_39, UInt<2>(0h3)) \n node _T_967 = and(_T_965, _T_966) \n node _T_968 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_969 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_970 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_971 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_972 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_973 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) \n node _T_974 = shr(io.in.a.bits.source, 3) \n node _T_975 = eq(_T_974, UInt<3>(0h6)) \n node _T_976 = leq(UInt<1>(0h0), uncommonBits_40) \n node _T_977 = and(_T_975, _T_976) \n node _T_978 = leq(uncommonBits_40, UInt<3>(0h4)) \n node _T_979 = and(_T_977, _T_978) \n node _T_980 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_981 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) \n node _T_982 = shr(io.in.a.bits.source, 3) \n node _T_983 = eq(_T_982, UInt<3>(0h4)) \n node _T_984 = leq(UInt<1>(0h0), uncommonBits_41) \n node _T_985 = and(_T_983, _T_984) \n node _T_986 = leq(uncommonBits_41, UInt<3>(0h4)) \n node _T_987 = and(_T_985, _T_986) \n node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_990 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_991 = or(_T_943, _T_949) \n node _T_992 = or(_T_991, _T_955) \n node _T_993 = or(_T_992, _T_961) \n node _T_994 = or(_T_993, _T_967) \n node _T_995 = or(_T_994, _T_968) \n node _T_996 = or(_T_995, _T_969) \n node _T_997 = or(_T_996, _T_970) \n node _T_998 = or(_T_997, _T_971) \n node _T_999 = or(_T_998, _T_972) \n node _T_1000 = or(_T_999, _T_973) \n node _T_1001 = or(_T_1000, _T_979) \n node _T_1002 = or(_T_1001, _T_980) \n node _T_1003 = or(_T_1002, _T_981) \n node _T_1004 = or(_T_1003, _T_987) \n node _T_1005 = or(_T_1004, _T_988) \n node _T_1006 = or(_T_1005, _T_989) \n node _T_1007 = or(_T_1006, _T_990) \n node _T_1008 = and(_T_942, _T_1007) \n node _T_1009 = or(UInt<1>(0h0), _T_1008) \n node _T_1010 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1011 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1012 = and(_T_1010, _T_1011) \n node _T_1013 = or(UInt<1>(0h0), _T_1012) \n node _T_1014 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_1015 = cvt(_T_1014) \n node _T_1016 = and(_T_1015, asSInt(UInt<13>(0h1000))) \n node _T_1017 = asSInt(_T_1016) \n node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) \n node _T_1019 = and(_T_1013, _T_1018) \n node _T_1020 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1021 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_1022 = and(_T_1020, _T_1021) \n node _T_1023 = or(UInt<1>(0h0), _T_1022) \n node _T_1024 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_1025 = cvt(_T_1024) \n node _T_1026 = and(_T_1025, asSInt(UInt<14>(0h2000))) \n node _T_1027 = asSInt(_T_1026) \n node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) \n node _T_1029 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_1030 = cvt(_T_1029) \n node _T_1031 = and(_T_1030, asSInt(UInt<18>(0h2f000))) \n node _T_1032 = asSInt(_T_1031) \n node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) \n node _T_1034 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_1035 = cvt(_T_1034) \n node _T_1036 = and(_T_1035, asSInt(UInt<17>(0h10000))) \n node _T_1037 = asSInt(_T_1036) \n node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0))) \n node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_1040 = cvt(_T_1039) \n node _T_1041 = and(_T_1040, asSInt(UInt<13>(0h1000))) \n node _T_1042 = asSInt(_T_1041) \n node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) \n node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_1045 = cvt(_T_1044) \n node _T_1046 = and(_T_1045, asSInt(UInt<27>(0h4000000))) \n node _T_1047 = asSInt(_T_1046) \n node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) \n node _T_1049 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_1050 = cvt(_T_1049) \n node _T_1051 = and(_T_1050, asSInt(UInt<13>(0h1000))) \n node _T_1052 = asSInt(_T_1051) \n node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) \n node _T_1054 = or(_T_1028, _T_1033) \n node _T_1055 = or(_T_1054, _T_1038) \n node _T_1056 = or(_T_1055, _T_1043) \n node _T_1057 = or(_T_1056, _T_1048) \n node _T_1058 = or(_T_1057, _T_1053) \n node _T_1059 = and(_T_1023, _T_1058) \n node _T_1060 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1061 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_1062 = cvt(_T_1061) \n node _T_1063 = and(_T_1062, asSInt(UInt<17>(0h10000))) \n node _T_1064 = asSInt(_T_1063) \n node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) \n node _T_1066 = and(_T_1060, _T_1065) \n node _T_1067 = or(UInt<1>(0h0), _T_1019) \n node _T_1068 = or(_T_1067, _T_1059) \n node _T_1069 = or(_T_1068, _T_1066) \n node _T_1070 = and(_T_1009, _T_1069) \n node _T_1071 = asUInt(reset) \n node _T_1072 = eq(_T_1071, UInt<1>(0h0)) \n when _T_1072 : \n node _T_1073 = eq(_T_1070, UInt<1>(0h0)) \n when _T_1073 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_1070, UInt<1>(0h1), \"\") : assert_26 \n node _T_1074 = asUInt(reset) \n node _T_1075 = eq(_T_1074, UInt<1>(0h0)) \n when _T_1075 : \n node _T_1076 = eq(source_ok, UInt<1>(0h0)) \n when _T_1076 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_27 \n node _T_1077 = asUInt(reset) \n node _T_1078 = eq(_T_1077, UInt<1>(0h0)) \n when _T_1078 : \n node _T_1079 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1079 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_1080 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_1081 = asUInt(reset) \n node _T_1082 = eq(_T_1081, UInt<1>(0h0)) \n when _T_1082 : \n node _T_1083 = eq(_T_1080, UInt<1>(0h0)) \n when _T_1083 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_1080, UInt<1>(0h1), \"\") : assert_29 \n node _T_1084 = eq(io.in.a.bits.mask, mask) \n node _T_1085 = asUInt(reset) \n node _T_1086 = eq(_T_1085, UInt<1>(0h0)) \n when _T_1086 : \n node _T_1087 = eq(_T_1084, UInt<1>(0h0)) \n when _T_1087 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_1084, UInt<1>(0h1), \"\") : assert_30 \n node _T_1088 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_1088 : \n node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1090 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1091 = and(_T_1089, _T_1090) \n node _T_1092 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) \n node _T_1093 = shr(io.in.a.bits.source, 2) \n node _T_1094 = eq(_T_1093, UInt<1>(0h0)) \n node _T_1095 = leq(UInt<1>(0h0), uncommonBits_42) \n node _T_1096 = and(_T_1094, _T_1095) \n node _T_1097 = leq(uncommonBits_42, UInt<2>(0h3)) \n node _T_1098 = and(_T_1096, _T_1097) \n node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) \n node _T_1099 = shr(io.in.a.bits.source, 2) \n node _T_1100 = eq(_T_1099, UInt<1>(0h1)) \n node _T_1101 = leq(UInt<1>(0h0), uncommonBits_43) \n node _T_1102 = and(_T_1100, _T_1101) \n node _T_1103 = leq(uncommonBits_43, UInt<2>(0h3)) \n node _T_1104 = and(_T_1102, _T_1103) \n node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) \n node _T_1105 = shr(io.in.a.bits.source, 2) \n node _T_1106 = eq(_T_1105, UInt<2>(0h2)) \n node _T_1107 = leq(UInt<1>(0h0), uncommonBits_44) \n node _T_1108 = and(_T_1106, _T_1107) \n node _T_1109 = leq(uncommonBits_44, UInt<2>(0h3)) \n node _T_1110 = and(_T_1108, _T_1109) \n node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) \n node _T_1111 = shr(io.in.a.bits.source, 2) \n node _T_1112 = eq(_T_1111, UInt<2>(0h3)) \n node _T_1113 = leq(UInt<1>(0h0), uncommonBits_45) \n node _T_1114 = and(_T_1112, _T_1113) \n node _T_1115 = leq(uncommonBits_45, UInt<2>(0h3)) \n node _T_1116 = and(_T_1114, _T_1115) \n node _T_1117 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_1118 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_1119 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_1120 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_1121 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_1122 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) \n node _T_1123 = shr(io.in.a.bits.source, 3) \n node _T_1124 = eq(_T_1123, UInt<3>(0h6)) \n node _T_1125 = leq(UInt<1>(0h0), uncommonBits_46) \n node _T_1126 = and(_T_1124, _T_1125) \n node _T_1127 = leq(uncommonBits_46, UInt<3>(0h4)) \n node _T_1128 = and(_T_1126, _T_1127) \n node _T_1129 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_1130 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) \n node _T_1131 = shr(io.in.a.bits.source, 3) \n node _T_1132 = eq(_T_1131, UInt<3>(0h4)) \n node _T_1133 = leq(UInt<1>(0h0), uncommonBits_47) \n node _T_1134 = and(_T_1132, _T_1133) \n node _T_1135 = leq(uncommonBits_47, UInt<3>(0h4)) \n node _T_1136 = and(_T_1134, _T_1135) \n node _T_1137 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_1138 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_1139 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_1140 = or(_T_1092, _T_1098) \n node _T_1141 = or(_T_1140, _T_1104) \n node _T_1142 = or(_T_1141, _T_1110) \n node _T_1143 = or(_T_1142, _T_1116) \n node _T_1144 = or(_T_1143, _T_1117) \n node _T_1145 = or(_T_1144, _T_1118) \n node _T_1146 = or(_T_1145, _T_1119) \n node _T_1147 = or(_T_1146, _T_1120) \n node _T_1148 = or(_T_1147, _T_1121) \n node _T_1149 = or(_T_1148, _T_1122) \n node _T_1150 = or(_T_1149, _T_1128) \n node _T_1151 = or(_T_1150, _T_1129) \n node _T_1152 = or(_T_1151, _T_1130) \n node _T_1153 = or(_T_1152, _T_1136) \n node _T_1154 = or(_T_1153, _T_1137) \n node _T_1155 = or(_T_1154, _T_1138) \n node _T_1156 = or(_T_1155, _T_1139) \n node _T_1157 = and(_T_1091, _T_1156) \n node _T_1158 = or(UInt<1>(0h0), _T_1157) \n node _T_1159 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1160 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1161 = and(_T_1159, _T_1160) \n node _T_1162 = or(UInt<1>(0h0), _T_1161) \n node _T_1163 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_1164 = cvt(_T_1163) \n node _T_1165 = and(_T_1164, asSInt(UInt<13>(0h1000))) \n node _T_1166 = asSInt(_T_1165) \n node _T_1167 = eq(_T_1166, asSInt(UInt<1>(0h0))) \n node _T_1168 = and(_T_1162, _T_1167) \n node _T_1169 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1170 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_1171 = and(_T_1169, _T_1170) \n node _T_1172 = or(UInt<1>(0h0), _T_1171) \n node _T_1173 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_1174 = cvt(_T_1173) \n node _T_1175 = and(_T_1174, asSInt(UInt<14>(0h2000))) \n node _T_1176 = asSInt(_T_1175) \n node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0))) \n node _T_1178 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_1179 = cvt(_T_1178) \n node _T_1180 = and(_T_1179, asSInt(UInt<18>(0h2f000))) \n node _T_1181 = asSInt(_T_1180) \n node _T_1182 = eq(_T_1181, asSInt(UInt<1>(0h0))) \n node _T_1183 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_1184 = cvt(_T_1183) \n node _T_1185 = and(_T_1184, asSInt(UInt<17>(0h10000))) \n node _T_1186 = asSInt(_T_1185) \n node _T_1187 = eq(_T_1186, asSInt(UInt<1>(0h0))) \n node _T_1188 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_1189 = cvt(_T_1188) \n node _T_1190 = and(_T_1189, asSInt(UInt<13>(0h1000))) \n node _T_1191 = asSInt(_T_1190) \n node _T_1192 = eq(_T_1191, asSInt(UInt<1>(0h0))) \n node _T_1193 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_1194 = cvt(_T_1193) \n node _T_1195 = and(_T_1194, asSInt(UInt<27>(0h4000000))) \n node _T_1196 = asSInt(_T_1195) \n node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0))) \n node _T_1198 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_1199 = cvt(_T_1198) \n node _T_1200 = and(_T_1199, asSInt(UInt<13>(0h1000))) \n node _T_1201 = asSInt(_T_1200) \n node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0))) \n node _T_1203 = or(_T_1177, _T_1182) \n node _T_1204 = or(_T_1203, _T_1187) \n node _T_1205 = or(_T_1204, _T_1192) \n node _T_1206 = or(_T_1205, _T_1197) \n node _T_1207 = or(_T_1206, _T_1202) \n node _T_1208 = and(_T_1172, _T_1207) \n node _T_1209 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1210 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_1211 = cvt(_T_1210) \n node _T_1212 = and(_T_1211, asSInt(UInt<17>(0h10000))) \n node _T_1213 = asSInt(_T_1212) \n node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) \n node _T_1215 = and(_T_1209, _T_1214) \n node _T_1216 = or(UInt<1>(0h0), _T_1168) \n node _T_1217 = or(_T_1216, _T_1208) \n node _T_1218 = or(_T_1217, _T_1215) \n node _T_1219 = and(_T_1158, _T_1218) \n node _T_1220 = asUInt(reset) \n node _T_1221 = eq(_T_1220, UInt<1>(0h0)) \n when _T_1221 : \n node _T_1222 = eq(_T_1219, UInt<1>(0h0)) \n when _T_1222 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_1219, UInt<1>(0h1), \"\") : assert_31 \n node _T_1223 = asUInt(reset) \n node _T_1224 = eq(_T_1223, UInt<1>(0h0)) \n when _T_1224 : \n node _T_1225 = eq(source_ok, UInt<1>(0h0)) \n when _T_1225 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_32 \n node _T_1226 = asUInt(reset) \n node _T_1227 = eq(_T_1226, UInt<1>(0h0)) \n when _T_1227 : \n node _T_1228 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1228 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_1229 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_1230 = asUInt(reset) \n node _T_1231 = eq(_T_1230, UInt<1>(0h0)) \n when _T_1231 : \n node _T_1232 = eq(_T_1229, UInt<1>(0h0)) \n when _T_1232 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_1229, UInt<1>(0h1), \"\") : assert_34 \n node _T_1233 = not(mask) \n node _T_1234 = and(io.in.a.bits.mask, _T_1233) \n node _T_1235 = eq(_T_1234, UInt<1>(0h0)) \n node _T_1236 = asUInt(reset) \n node _T_1237 = eq(_T_1236, UInt<1>(0h0)) \n when _T_1237 : \n node _T_1238 = eq(_T_1235, UInt<1>(0h0)) \n when _T_1238 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_1235, UInt<1>(0h1), \"\") : assert_35 \n node _T_1239 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_1239 : \n node _T_1240 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1241 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1242 = and(_T_1240, _T_1241) \n node _T_1243 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) \n node _T_1244 = shr(io.in.a.bits.source, 2) \n node _T_1245 = eq(_T_1244, UInt<1>(0h0)) \n node _T_1246 = leq(UInt<1>(0h0), uncommonBits_48) \n node _T_1247 = and(_T_1245, _T_1246) \n node _T_1248 = leq(uncommonBits_48, UInt<2>(0h3)) \n node _T_1249 = and(_T_1247, _T_1248) \n node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) \n node _T_1250 = shr(io.in.a.bits.source, 2) \n node _T_1251 = eq(_T_1250, UInt<1>(0h1)) \n node _T_1252 = leq(UInt<1>(0h0), uncommonBits_49) \n node _T_1253 = and(_T_1251, _T_1252) \n node _T_1254 = leq(uncommonBits_49, UInt<2>(0h3)) \n node _T_1255 = and(_T_1253, _T_1254) \n node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) \n node _T_1256 = shr(io.in.a.bits.source, 2) \n node _T_1257 = eq(_T_1256, UInt<2>(0h2)) \n node _T_1258 = leq(UInt<1>(0h0), uncommonBits_50) \n node _T_1259 = and(_T_1257, _T_1258) \n node _T_1260 = leq(uncommonBits_50, UInt<2>(0h3)) \n node _T_1261 = and(_T_1259, _T_1260) \n node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) \n node _T_1262 = shr(io.in.a.bits.source, 2) \n node _T_1263 = eq(_T_1262, UInt<2>(0h3)) \n node _T_1264 = leq(UInt<1>(0h0), uncommonBits_51) \n node _T_1265 = and(_T_1263, _T_1264) \n node _T_1266 = leq(uncommonBits_51, UInt<2>(0h3)) \n node _T_1267 = and(_T_1265, _T_1266) \n node _T_1268 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_1269 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_1270 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_1271 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_1272 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_1273 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0) \n node _T_1274 = shr(io.in.a.bits.source, 3) \n node _T_1275 = eq(_T_1274, UInt<3>(0h6)) \n node _T_1276 = leq(UInt<1>(0h0), uncommonBits_52) \n node _T_1277 = and(_T_1275, _T_1276) \n node _T_1278 = leq(uncommonBits_52, UInt<3>(0h4)) \n node _T_1279 = and(_T_1277, _T_1278) \n node _T_1280 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_1281 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) \n node _T_1282 = shr(io.in.a.bits.source, 3) \n node _T_1283 = eq(_T_1282, UInt<3>(0h4)) \n node _T_1284 = leq(UInt<1>(0h0), uncommonBits_53) \n node _T_1285 = and(_T_1283, _T_1284) \n node _T_1286 = leq(uncommonBits_53, UInt<3>(0h4)) \n node _T_1287 = and(_T_1285, _T_1286) \n node _T_1288 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_1289 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_1290 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_1291 = or(_T_1243, _T_1249) \n node _T_1292 = or(_T_1291, _T_1255) \n node _T_1293 = or(_T_1292, _T_1261) \n node _T_1294 = or(_T_1293, _T_1267) \n node _T_1295 = or(_T_1294, _T_1268) \n node _T_1296 = or(_T_1295, _T_1269) \n node _T_1297 = or(_T_1296, _T_1270) \n node _T_1298 = or(_T_1297, _T_1271) \n node _T_1299 = or(_T_1298, _T_1272) \n node _T_1300 = or(_T_1299, _T_1273) \n node _T_1301 = or(_T_1300, _T_1279) \n node _T_1302 = or(_T_1301, _T_1280) \n node _T_1303 = or(_T_1302, _T_1281) \n node _T_1304 = or(_T_1303, _T_1287) \n node _T_1305 = or(_T_1304, _T_1288) \n node _T_1306 = or(_T_1305, _T_1289) \n node _T_1307 = or(_T_1306, _T_1290) \n node _T_1308 = and(_T_1242, _T_1307) \n node _T_1309 = or(UInt<1>(0h0), _T_1308) \n node _T_1310 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1311 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_1312 = and(_T_1310, _T_1311) \n node _T_1313 = or(UInt<1>(0h0), _T_1312) \n node _T_1314 = xor(io.in.a.bits.address, UInt<13>(0h1000)) \n node _T_1315 = cvt(_T_1314) \n node _T_1316 = and(_T_1315, asSInt(UInt<15>(0h5000))) \n node _T_1317 = asSInt(_T_1316) \n node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0))) \n node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_1320 = cvt(_T_1319) \n node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) \n node _T_1322 = asSInt(_T_1321) \n node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) \n node _T_1324 = or(_T_1318, _T_1323) \n node _T_1325 = and(_T_1313, _T_1324) \n node _T_1326 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1327 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_1328 = cvt(_T_1327) \n node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000))) \n node _T_1330 = asSInt(_T_1329) \n node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0))) \n node _T_1332 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_1333 = cvt(_T_1332) \n node _T_1334 = and(_T_1333, asSInt(UInt<17>(0h10000))) \n node _T_1335 = asSInt(_T_1334) \n node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0))) \n node _T_1337 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_1338 = cvt(_T_1337) \n node _T_1339 = and(_T_1338, asSInt(UInt<18>(0h2f000))) \n node _T_1340 = asSInt(_T_1339) \n node _T_1341 = eq(_T_1340, asSInt(UInt<1>(0h0))) \n node _T_1342 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_1343 = cvt(_T_1342) \n node _T_1344 = and(_T_1343, asSInt(UInt<17>(0h10000))) \n node _T_1345 = asSInt(_T_1344) \n node _T_1346 = eq(_T_1345, asSInt(UInt<1>(0h0))) \n node _T_1347 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_1348 = cvt(_T_1347) \n node _T_1349 = and(_T_1348, asSInt(UInt<13>(0h1000))) \n node _T_1350 = asSInt(_T_1349) \n node _T_1351 = eq(_T_1350, asSInt(UInt<1>(0h0))) \n node _T_1352 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_1353 = cvt(_T_1352) \n node _T_1354 = and(_T_1353, asSInt(UInt<27>(0h4000000))) \n node _T_1355 = asSInt(_T_1354) \n node _T_1356 = eq(_T_1355, asSInt(UInt<1>(0h0))) \n node _T_1357 = or(_T_1331, _T_1336) \n node _T_1358 = or(_T_1357, _T_1341) \n node _T_1359 = or(_T_1358, _T_1346) \n node _T_1360 = or(_T_1359, _T_1351) \n node _T_1361 = or(_T_1360, _T_1356) \n node _T_1362 = and(_T_1326, _T_1361) \n node _T_1363 = or(UInt<1>(0h0), _T_1325) \n node _T_1364 = or(_T_1363, _T_1362) \n node _T_1365 = and(_T_1309, _T_1364) \n node _T_1366 = asUInt(reset) \n node _T_1367 = eq(_T_1366, UInt<1>(0h0)) \n when _T_1367 : \n node _T_1368 = eq(_T_1365, UInt<1>(0h0)) \n when _T_1368 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_1365, UInt<1>(0h1), \"\") : assert_36 \n node _T_1369 = asUInt(reset) \n node _T_1370 = eq(_T_1369, UInt<1>(0h0)) \n when _T_1370 : \n node _T_1371 = eq(source_ok, UInt<1>(0h0)) \n when _T_1371 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_37 \n node _T_1372 = asUInt(reset) \n node _T_1373 = eq(_T_1372, UInt<1>(0h0)) \n when _T_1373 : \n node _T_1374 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1374 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_1375 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_1376 = asUInt(reset) \n node _T_1377 = eq(_T_1376, UInt<1>(0h0)) \n when _T_1377 : \n node _T_1378 = eq(_T_1375, UInt<1>(0h0)) \n when _T_1378 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_1375, UInt<1>(0h1), \"\") : assert_39 \n node _T_1379 = eq(io.in.a.bits.mask, mask) \n node _T_1380 = asUInt(reset) \n node _T_1381 = eq(_T_1380, UInt<1>(0h0)) \n when _T_1381 : \n node _T_1382 = eq(_T_1379, UInt<1>(0h0)) \n when _T_1382 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_1379, UInt<1>(0h1), \"\") : assert_40 \n node _T_1383 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_1383 : \n node _T_1384 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1385 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1386 = and(_T_1384, _T_1385) \n node _T_1387 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) \n node _T_1388 = shr(io.in.a.bits.source, 2) \n node _T_1389 = eq(_T_1388, UInt<1>(0h0)) \n node _T_1390 = leq(UInt<1>(0h0), uncommonBits_54) \n node _T_1391 = and(_T_1389, _T_1390) \n node _T_1392 = leq(uncommonBits_54, UInt<2>(0h3)) \n node _T_1393 = and(_T_1391, _T_1392) \n node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) \n node _T_1394 = shr(io.in.a.bits.source, 2) \n node _T_1395 = eq(_T_1394, UInt<1>(0h1)) \n node _T_1396 = leq(UInt<1>(0h0), uncommonBits_55) \n node _T_1397 = and(_T_1395, _T_1396) \n node _T_1398 = leq(uncommonBits_55, UInt<2>(0h3)) \n node _T_1399 = and(_T_1397, _T_1398) \n node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) \n node _T_1400 = shr(io.in.a.bits.source, 2) \n node _T_1401 = eq(_T_1400, UInt<2>(0h2)) \n node _T_1402 = leq(UInt<1>(0h0), uncommonBits_56) \n node _T_1403 = and(_T_1401, _T_1402) \n node _T_1404 = leq(uncommonBits_56, UInt<2>(0h3)) \n node _T_1405 = and(_T_1403, _T_1404) \n node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) \n node _T_1406 = shr(io.in.a.bits.source, 2) \n node _T_1407 = eq(_T_1406, UInt<2>(0h3)) \n node _T_1408 = leq(UInt<1>(0h0), uncommonBits_57) \n node _T_1409 = and(_T_1407, _T_1408) \n node _T_1410 = leq(uncommonBits_57, UInt<2>(0h3)) \n node _T_1411 = and(_T_1409, _T_1410) \n node _T_1412 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_1413 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_1414 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_1415 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_1416 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_1417 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_58 = bits(_uncommonBits_T_58, 2, 0) \n node _T_1418 = shr(io.in.a.bits.source, 3) \n node _T_1419 = eq(_T_1418, UInt<3>(0h6)) \n node _T_1420 = leq(UInt<1>(0h0), uncommonBits_58) \n node _T_1421 = and(_T_1419, _T_1420) \n node _T_1422 = leq(uncommonBits_58, UInt<3>(0h4)) \n node _T_1423 = and(_T_1421, _T_1422) \n node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) \n node _T_1426 = shr(io.in.a.bits.source, 3) \n node _T_1427 = eq(_T_1426, UInt<3>(0h4)) \n node _T_1428 = leq(UInt<1>(0h0), uncommonBits_59) \n node _T_1429 = and(_T_1427, _T_1428) \n node _T_1430 = leq(uncommonBits_59, UInt<3>(0h4)) \n node _T_1431 = and(_T_1429, _T_1430) \n node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_1434 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_1435 = or(_T_1387, _T_1393) \n node _T_1436 = or(_T_1435, _T_1399) \n node _T_1437 = or(_T_1436, _T_1405) \n node _T_1438 = or(_T_1437, _T_1411) \n node _T_1439 = or(_T_1438, _T_1412) \n node _T_1440 = or(_T_1439, _T_1413) \n node _T_1441 = or(_T_1440, _T_1414) \n node _T_1442 = or(_T_1441, _T_1415) \n node _T_1443 = or(_T_1442, _T_1416) \n node _T_1444 = or(_T_1443, _T_1417) \n node _T_1445 = or(_T_1444, _T_1423) \n node _T_1446 = or(_T_1445, _T_1424) \n node _T_1447 = or(_T_1446, _T_1425) \n node _T_1448 = or(_T_1447, _T_1431) \n node _T_1449 = or(_T_1448, _T_1432) \n node _T_1450 = or(_T_1449, _T_1433) \n node _T_1451 = or(_T_1450, _T_1434) \n node _T_1452 = and(_T_1386, _T_1451) \n node _T_1453 = or(UInt<1>(0h0), _T_1452) \n node _T_1454 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1455 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_1456 = and(_T_1454, _T_1455) \n node _T_1457 = or(UInt<1>(0h0), _T_1456) \n node _T_1458 = xor(io.in.a.bits.address, UInt<13>(0h1000)) \n node _T_1459 = cvt(_T_1458) \n node _T_1460 = and(_T_1459, asSInt(UInt<15>(0h5000))) \n node _T_1461 = asSInt(_T_1460) \n node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0))) \n node _T_1463 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_1464 = cvt(_T_1463) \n node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000))) \n node _T_1466 = asSInt(_T_1465) \n node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0))) \n node _T_1468 = or(_T_1462, _T_1467) \n node _T_1469 = and(_T_1457, _T_1468) \n node _T_1470 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1471 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_1472 = cvt(_T_1471) \n node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) \n node _T_1474 = asSInt(_T_1473) \n node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) \n node _T_1476 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_1477 = cvt(_T_1476) \n node _T_1478 = and(_T_1477, asSInt(UInt<17>(0h10000))) \n node _T_1479 = asSInt(_T_1478) \n node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) \n node _T_1481 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_1482 = cvt(_T_1481) \n node _T_1483 = and(_T_1482, asSInt(UInt<18>(0h2f000))) \n node _T_1484 = asSInt(_T_1483) \n node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) \n node _T_1486 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_1487 = cvt(_T_1486) \n node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000))) \n node _T_1489 = asSInt(_T_1488) \n node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) \n node _T_1491 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_1492 = cvt(_T_1491) \n node _T_1493 = and(_T_1492, asSInt(UInt<13>(0h1000))) \n node _T_1494 = asSInt(_T_1493) \n node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) \n node _T_1496 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_1497 = cvt(_T_1496) \n node _T_1498 = and(_T_1497, asSInt(UInt<27>(0h4000000))) \n node _T_1499 = asSInt(_T_1498) \n node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) \n node _T_1501 = or(_T_1475, _T_1480) \n node _T_1502 = or(_T_1501, _T_1485) \n node _T_1503 = or(_T_1502, _T_1490) \n node _T_1504 = or(_T_1503, _T_1495) \n node _T_1505 = or(_T_1504, _T_1500) \n node _T_1506 = and(_T_1470, _T_1505) \n node _T_1507 = or(UInt<1>(0h0), _T_1469) \n node _T_1508 = or(_T_1507, _T_1506) \n node _T_1509 = and(_T_1453, _T_1508) \n node _T_1510 = asUInt(reset) \n node _T_1511 = eq(_T_1510, UInt<1>(0h0)) \n when _T_1511 : \n node _T_1512 = eq(_T_1509, UInt<1>(0h0)) \n when _T_1512 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_1509, UInt<1>(0h1), \"\") : assert_41 \n node _T_1513 = asUInt(reset) \n node _T_1514 = eq(_T_1513, UInt<1>(0h0)) \n when _T_1514 : \n node _T_1515 = eq(source_ok, UInt<1>(0h0)) \n when _T_1515 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_42 \n node _T_1516 = asUInt(reset) \n node _T_1517 = eq(_T_1516, UInt<1>(0h0)) \n when _T_1517 : \n node _T_1518 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1518 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_1519 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_1520 = asUInt(reset) \n node _T_1521 = eq(_T_1520, UInt<1>(0h0)) \n when _T_1521 : \n node _T_1522 = eq(_T_1519, UInt<1>(0h0)) \n when _T_1522 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_1519, UInt<1>(0h1), \"\") : assert_44 \n node _T_1523 = eq(io.in.a.bits.mask, mask) \n node _T_1524 = asUInt(reset) \n node _T_1525 = eq(_T_1524, UInt<1>(0h0)) \n when _T_1525 : \n node _T_1526 = eq(_T_1523, UInt<1>(0h0)) \n when _T_1526 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_1523, UInt<1>(0h1), \"\") : assert_45 \n node _T_1527 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_1527 : \n node _T_1528 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1529 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1530 = and(_T_1528, _T_1529) \n node _T_1531 = eq(io.in.a.bits.source, UInt<5>(0h10)) \n node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) \n node _T_1532 = shr(io.in.a.bits.source, 2) \n node _T_1533 = eq(_T_1532, UInt<1>(0h0)) \n node _T_1534 = leq(UInt<1>(0h0), uncommonBits_60) \n node _T_1535 = and(_T_1533, _T_1534) \n node _T_1536 = leq(uncommonBits_60, UInt<2>(0h3)) \n node _T_1537 = and(_T_1535, _T_1536) \n node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) \n node _T_1538 = shr(io.in.a.bits.source, 2) \n node _T_1539 = eq(_T_1538, UInt<1>(0h1)) \n node _T_1540 = leq(UInt<1>(0h0), uncommonBits_61) \n node _T_1541 = and(_T_1539, _T_1540) \n node _T_1542 = leq(uncommonBits_61, UInt<2>(0h3)) \n node _T_1543 = and(_T_1541, _T_1542) \n node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) \n node _T_1544 = shr(io.in.a.bits.source, 2) \n node _T_1545 = eq(_T_1544, UInt<2>(0h2)) \n node _T_1546 = leq(UInt<1>(0h0), uncommonBits_62) \n node _T_1547 = and(_T_1545, _T_1546) \n node _T_1548 = leq(uncommonBits_62, UInt<2>(0h3)) \n node _T_1549 = and(_T_1547, _T_1548) \n node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) \n node _T_1550 = shr(io.in.a.bits.source, 2) \n node _T_1551 = eq(_T_1550, UInt<2>(0h3)) \n node _T_1552 = leq(UInt<1>(0h0), uncommonBits_63) \n node _T_1553 = and(_T_1551, _T_1552) \n node _T_1554 = leq(uncommonBits_63, UInt<2>(0h3)) \n node _T_1555 = and(_T_1553, _T_1554) \n node _T_1556 = eq(io.in.a.bits.source, UInt<7>(0h44)) \n node _T_1557 = eq(io.in.a.bits.source, UInt<7>(0h45)) \n node _T_1558 = eq(io.in.a.bits.source, UInt<7>(0h46)) \n node _T_1559 = eq(io.in.a.bits.source, UInt<7>(0h40)) \n node _T_1560 = eq(io.in.a.bits.source, UInt<7>(0h41)) \n node _T_1561 = eq(io.in.a.bits.source, UInt<7>(0h42)) \n node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) \n node _T_1562 = shr(io.in.a.bits.source, 3) \n node _T_1563 = eq(_T_1562, UInt<3>(0h6)) \n node _T_1564 = leq(UInt<1>(0h0), uncommonBits_64) \n node _T_1565 = and(_T_1563, _T_1564) \n node _T_1566 = leq(uncommonBits_64, UInt<3>(0h4)) \n node _T_1567 = and(_T_1565, _T_1566) \n node _T_1568 = eq(io.in.a.bits.source, UInt<6>(0h35)) \n node _T_1569 = eq(io.in.a.bits.source, UInt<6>(0h38)) \n node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<3>(0h0)) \n node uncommonBits_65 = bits(_uncommonBits_T_65, 2, 0) \n node _T_1570 = shr(io.in.a.bits.source, 3) \n node _T_1571 = eq(_T_1570, UInt<3>(0h4)) \n node _T_1572 = leq(UInt<1>(0h0), uncommonBits_65) \n node _T_1573 = and(_T_1571, _T_1572) \n node _T_1574 = leq(uncommonBits_65, UInt<3>(0h4)) \n node _T_1575 = and(_T_1573, _T_1574) \n node _T_1576 = eq(io.in.a.bits.source, UInt<6>(0h25)) \n node _T_1577 = eq(io.in.a.bits.source, UInt<6>(0h28)) \n node _T_1578 = eq(io.in.a.bits.source, UInt<8>(0h80)) \n node _T_1579 = or(_T_1531, _T_1537) \n node _T_1580 = or(_T_1579, _T_1543) \n node _T_1581 = or(_T_1580, _T_1549) \n node _T_1582 = or(_T_1581, _T_1555) \n node _T_1583 = or(_T_1582, _T_1556) \n node _T_1584 = or(_T_1583, _T_1557) \n node _T_1585 = or(_T_1584, _T_1558) \n node _T_1586 = or(_T_1585, _T_1559) \n node _T_1587 = or(_T_1586, _T_1560) \n node _T_1588 = or(_T_1587, _T_1561) \n node _T_1589 = or(_T_1588, _T_1567) \n node _T_1590 = or(_T_1589, _T_1568) \n node _T_1591 = or(_T_1590, _T_1569) \n node _T_1592 = or(_T_1591, _T_1575) \n node _T_1593 = or(_T_1592, _T_1576) \n node _T_1594 = or(_T_1593, _T_1577) \n node _T_1595 = or(_T_1594, _T_1578) \n node _T_1596 = and(_T_1530, _T_1595) \n node _T_1597 = or(UInt<1>(0h0), _T_1596) \n node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1600 = and(_T_1598, _T_1599) \n node _T_1601 = or(UInt<1>(0h0), _T_1600) \n node _T_1602 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_1603 = cvt(_T_1602) \n node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000))) \n node _T_1605 = asSInt(_T_1604) \n node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) \n node _T_1607 = and(_T_1601, _T_1606) \n node _T_1608 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1609 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_1610 = cvt(_T_1609) \n node _T_1611 = and(_T_1610, asSInt(UInt<14>(0h2000))) \n node _T_1612 = asSInt(_T_1611) \n node _T_1613 = eq(_T_1612, asSInt(UInt<1>(0h0))) \n node _T_1614 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_1615 = cvt(_T_1614) \n node _T_1616 = and(_T_1615, asSInt(UInt<17>(0h10000))) \n node _T_1617 = asSInt(_T_1616) \n node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) \n node _T_1619 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_1620 = cvt(_T_1619) \n node _T_1621 = and(_T_1620, asSInt(UInt<18>(0h2f000))) \n node _T_1622 = asSInt(_T_1621) \n node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) \n node _T_1624 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_1625 = cvt(_T_1624) \n node _T_1626 = and(_T_1625, asSInt(UInt<17>(0h10000))) \n node _T_1627 = asSInt(_T_1626) \n node _T_1628 = eq(_T_1627, asSInt(UInt<1>(0h0))) \n node _T_1629 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_1630 = cvt(_T_1629) \n node _T_1631 = and(_T_1630, asSInt(UInt<13>(0h1000))) \n node _T_1632 = asSInt(_T_1631) \n node _T_1633 = eq(_T_1632, asSInt(UInt<1>(0h0))) \n node _T_1634 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_1635 = cvt(_T_1634) \n node _T_1636 = and(_T_1635, asSInt(UInt<27>(0h4000000))) \n node _T_1637 = asSInt(_T_1636) \n node _T_1638 = eq(_T_1637, asSInt(UInt<1>(0h0))) \n node _T_1639 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_1640 = cvt(_T_1639) \n node _T_1641 = and(_T_1640, asSInt(UInt<13>(0h1000))) \n node _T_1642 = asSInt(_T_1641) \n node _T_1643 = eq(_T_1642, asSInt(UInt<1>(0h0))) \n node _T_1644 = or(_T_1613, _T_1618) \n node _T_1645 = or(_T_1644, _T_1623) \n node _T_1646 = or(_T_1645, _T_1628) \n node _T_1647 = or(_T_1646, _T_1633) \n node _T_1648 = or(_T_1647, _T_1638) \n node _T_1649 = or(_T_1648, _T_1643) \n node _T_1650 = and(_T_1608, _T_1649) \n node _T_1651 = or(UInt<1>(0h0), _T_1607) \n node _T_1652 = or(_T_1651, _T_1650) \n node _T_1653 = and(_T_1597, _T_1652) \n node _T_1654 = asUInt(reset) \n node _T_1655 = eq(_T_1654, UInt<1>(0h0)) \n when _T_1655 : \n node _T_1656 = eq(_T_1653, UInt<1>(0h0)) \n when _T_1656 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_1653, UInt<1>(0h1), \"\") : assert_46 \n node _T_1657 = asUInt(reset) \n node _T_1658 = eq(_T_1657, UInt<1>(0h0)) \n when _T_1658 : \n node _T_1659 = eq(source_ok, UInt<1>(0h0)) \n when _T_1659 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_47 \n node _T_1660 = asUInt(reset) \n node _T_1661 = eq(_T_1660, UInt<1>(0h0)) \n when _T_1661 : \n node _T_1662 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1662 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_1663 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_1664 = asUInt(reset) \n node _T_1665 = eq(_T_1664, UInt<1>(0h0)) \n when _T_1665 : \n node _T_1666 = eq(_T_1663, UInt<1>(0h0)) \n when _T_1666 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_1663, UInt<1>(0h1), \"\") : assert_49 \n node _T_1667 = eq(io.in.a.bits.mask, mask) \n node _T_1668 = asUInt(reset) \n node _T_1669 = eq(_T_1668, UInt<1>(0h0)) \n when _T_1669 : \n node _T_1670 = eq(_T_1667, UInt<1>(0h0)) \n when _T_1670 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_1667, UInt<1>(0h1), \"\") : assert_50 \n node _T_1671 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_1672 = asUInt(reset) \n node _T_1673 = eq(_T_1672, UInt<1>(0h0)) \n when _T_1673 : \n node _T_1674 = eq(_T_1671, UInt<1>(0h0)) \n when _T_1674 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_1671, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_1675 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1676 = asUInt(reset) \n node _T_1677 = eq(_T_1676, UInt<1>(0h0)) \n when _T_1677 : \n node _T_1678 = eq(_T_1675, UInt<1>(0h0)) \n when _T_1678 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_1675, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<5>(0h10)) \n node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) \n node _source_ok_T_65 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h0)) \n node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) \n node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) \n node _source_ok_T_69 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) \n node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) \n node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) \n node _source_ok_T_71 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1)) \n node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) \n node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) \n node _source_ok_T_75 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) \n node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) \n node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) \n node _source_ok_T_77 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h2)) \n node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) \n node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) \n node _source_ok_T_81 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) \n node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) \n node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) \n node _source_ok_T_83 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_84 = eq(_source_ok_T_83, UInt<2>(0h3)) \n node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) \n node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) \n node _source_ok_T_87 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) \n node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) \n node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h44)) \n node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<7>(0h45)) \n node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h46)) \n node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<7>(0h40)) \n node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h41)) \n node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h42)) \n node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<3>(0h0)) \n node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 2, 0) \n node _source_ok_T_95 = shr(io.in.d.bits.source, 3) \n node _source_ok_T_96 = eq(_source_ok_T_95, UInt<3>(0h6)) \n node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) \n node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) \n node _source_ok_T_99 = leq(source_ok_uncommonBits_10, UInt<3>(0h4)) \n node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) \n node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<6>(0h35)) \n node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<6>(0h38)) \n node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) \n node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) \n node _source_ok_T_103 = shr(io.in.d.bits.source, 3) \n node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) \n node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) \n node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) \n node _source_ok_T_107 = leq(source_ok_uncommonBits_11, UInt<3>(0h4)) \n node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) \n node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h25)) \n node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h28)) \n node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<8>(0h80)) \n wire _source_ok_WIRE_1 : UInt<1>[18] \n connect _source_ok_WIRE_1[0], _source_ok_T_64 \n connect _source_ok_WIRE_1[1], _source_ok_T_70 \n connect _source_ok_WIRE_1[2], _source_ok_T_76 \n connect _source_ok_WIRE_1[3], _source_ok_T_82 \n connect _source_ok_WIRE_1[4], _source_ok_T_88 \n connect _source_ok_WIRE_1[5], _source_ok_T_89 \n connect _source_ok_WIRE_1[6], _source_ok_T_90 \n connect _source_ok_WIRE_1[7], _source_ok_T_91 \n connect _source_ok_WIRE_1[8], _source_ok_T_92 \n connect _source_ok_WIRE_1[9], _source_ok_T_93 \n connect _source_ok_WIRE_1[10], _source_ok_T_94 \n connect _source_ok_WIRE_1[11], _source_ok_T_100 \n connect _source_ok_WIRE_1[12], _source_ok_T_101 \n connect _source_ok_WIRE_1[13], _source_ok_T_102 \n connect _source_ok_WIRE_1[14], _source_ok_T_108 \n connect _source_ok_WIRE_1[15], _source_ok_T_109 \n connect _source_ok_WIRE_1[16], _source_ok_T_110 \n connect _source_ok_WIRE_1[17], _source_ok_T_111 \n node _source_ok_T_112 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) \n node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[2]) \n node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[3]) \n node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[4]) \n node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[5]) \n node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[6]) \n node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[7]) \n node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[8]) \n node _source_ok_T_120 = or(_source_ok_T_119, _source_ok_WIRE_1[9]) \n node _source_ok_T_121 = or(_source_ok_T_120, _source_ok_WIRE_1[10]) \n node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_1[11]) \n node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_1[12]) \n node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_1[13]) \n node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_1[14]) \n node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[15]) \n node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[16]) \n node source_ok_1 = or(_source_ok_T_127, _source_ok_WIRE_1[17]) \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_1679 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_1679 : \n node _T_1680 = asUInt(reset) \n node _T_1681 = eq(_T_1680, UInt<1>(0h0)) \n when _T_1681 : \n node _T_1682 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1682 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_53 \n node _T_1683 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1684 = asUInt(reset) \n node _T_1685 = eq(_T_1684, UInt<1>(0h0)) \n when _T_1685 : \n node _T_1686 = eq(_T_1683, UInt<1>(0h0)) \n when _T_1686 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_1683, UInt<1>(0h1), \"\") : assert_54 \n node _T_1687 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1688 = asUInt(reset) \n node _T_1689 = eq(_T_1688, UInt<1>(0h0)) \n when _T_1689 : \n node _T_1690 = eq(_T_1687, UInt<1>(0h0)) \n when _T_1690 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_1687, UInt<1>(0h1), \"\") : assert_55 \n node _T_1691 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1692 = asUInt(reset) \n node _T_1693 = eq(_T_1692, UInt<1>(0h0)) \n when _T_1693 : \n node _T_1694 = eq(_T_1691, UInt<1>(0h0)) \n when _T_1694 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_1691, UInt<1>(0h1), \"\") : assert_56 \n node _T_1695 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1696 = asUInt(reset) \n node _T_1697 = eq(_T_1696, UInt<1>(0h0)) \n when _T_1697 : \n node _T_1698 = eq(_T_1695, UInt<1>(0h0)) \n when _T_1698 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_1695, UInt<1>(0h1), \"\") : assert_57 \n node _T_1699 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_1699 : \n node _T_1700 = asUInt(reset) \n node _T_1701 = eq(_T_1700, UInt<1>(0h0)) \n when _T_1701 : \n node _T_1702 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1702 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_58 \n node _T_1703 = asUInt(reset) \n node _T_1704 = eq(_T_1703, UInt<1>(0h0)) \n when _T_1704 : \n node _T_1705 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1705 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_1706 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1707 = asUInt(reset) \n node _T_1708 = eq(_T_1707, UInt<1>(0h0)) \n when _T_1708 : \n node _T_1709 = eq(_T_1706, UInt<1>(0h0)) \n when _T_1709 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_1706, UInt<1>(0h1), \"\") : assert_60 \n node _T_1710 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1711 = asUInt(reset) \n node _T_1712 = eq(_T_1711, UInt<1>(0h0)) \n when _T_1712 : \n node _T_1713 = eq(_T_1710, UInt<1>(0h0)) \n when _T_1713 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_1710, UInt<1>(0h1), \"\") : assert_61 \n node _T_1714 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1715 = asUInt(reset) \n node _T_1716 = eq(_T_1715, UInt<1>(0h0)) \n when _T_1716 : \n node _T_1717 = eq(_T_1714, UInt<1>(0h0)) \n when _T_1717 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_1714, UInt<1>(0h1), \"\") : assert_62 \n node _T_1718 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1719 = asUInt(reset) \n node _T_1720 = eq(_T_1719, UInt<1>(0h0)) \n when _T_1720 : \n node _T_1721 = eq(_T_1718, UInt<1>(0h0)) \n when _T_1721 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_1718, UInt<1>(0h1), \"\") : assert_63 \n node _T_1722 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1723 = or(UInt<1>(0h1), _T_1722) \n node _T_1724 = asUInt(reset) \n node _T_1725 = eq(_T_1724, UInt<1>(0h0)) \n when _T_1725 : \n node _T_1726 = eq(_T_1723, UInt<1>(0h0)) \n when _T_1726 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_1723, UInt<1>(0h1), \"\") : assert_64 \n node _T_1727 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_1727 : \n node _T_1728 = asUInt(reset) \n node _T_1729 = eq(_T_1728, UInt<1>(0h0)) \n when _T_1729 : \n node _T_1730 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1730 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_65 \n node _T_1731 = asUInt(reset) \n node _T_1732 = eq(_T_1731, UInt<1>(0h0)) \n when _T_1732 : \n node _T_1733 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1733 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_1734 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1735 = asUInt(reset) \n node _T_1736 = eq(_T_1735, UInt<1>(0h0)) \n when _T_1736 : \n node _T_1737 = eq(_T_1734, UInt<1>(0h0)) \n when _T_1737 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_1734, UInt<1>(0h1), \"\") : assert_67 \n node _T_1738 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1739 = asUInt(reset) \n node _T_1740 = eq(_T_1739, UInt<1>(0h0)) \n when _T_1740 : \n node _T_1741 = eq(_T_1738, UInt<1>(0h0)) \n when _T_1741 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_1738, UInt<1>(0h1), \"\") : assert_68 \n node _T_1742 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1743 = asUInt(reset) \n node _T_1744 = eq(_T_1743, UInt<1>(0h0)) \n when _T_1744 : \n node _T_1745 = eq(_T_1742, UInt<1>(0h0)) \n when _T_1745 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_1742, UInt<1>(0h1), \"\") : assert_69 \n node _T_1746 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1747 = or(_T_1746, io.in.d.bits.corrupt) \n node _T_1748 = asUInt(reset) \n node _T_1749 = eq(_T_1748, UInt<1>(0h0)) \n when _T_1749 : \n node _T_1750 = eq(_T_1747, UInt<1>(0h0)) \n when _T_1750 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_1747, UInt<1>(0h1), \"\") : assert_70 \n node _T_1751 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1752 = or(UInt<1>(0h1), _T_1751) \n node _T_1753 = asUInt(reset) \n node _T_1754 = eq(_T_1753, UInt<1>(0h0)) \n when _T_1754 : \n node _T_1755 = eq(_T_1752, UInt<1>(0h0)) \n when _T_1755 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_1752, UInt<1>(0h1), \"\") : assert_71 \n node _T_1756 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_1756 : \n node _T_1757 = asUInt(reset) \n node _T_1758 = eq(_T_1757, UInt<1>(0h0)) \n when _T_1758 : \n node _T_1759 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1759 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_72 \n node _T_1760 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1761 = asUInt(reset) \n node _T_1762 = eq(_T_1761, UInt<1>(0h0)) \n when _T_1762 : \n node _T_1763 = eq(_T_1760, UInt<1>(0h0)) \n when _T_1763 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_1760, UInt<1>(0h1), \"\") : assert_73 \n node _T_1764 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1765 = asUInt(reset) \n node _T_1766 = eq(_T_1765, UInt<1>(0h0)) \n when _T_1766 : \n node _T_1767 = eq(_T_1764, UInt<1>(0h0)) \n when _T_1767 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_1764, UInt<1>(0h1), \"\") : assert_74 \n node _T_1768 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1769 = or(UInt<1>(0h1), _T_1768) \n node _T_1770 = asUInt(reset) \n node _T_1771 = eq(_T_1770, UInt<1>(0h0)) \n when _T_1771 : \n node _T_1772 = eq(_T_1769, UInt<1>(0h0)) \n when _T_1772 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_1769, UInt<1>(0h1), \"\") : assert_75 \n node _T_1773 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_1773 : \n node _T_1774 = asUInt(reset) \n node _T_1775 = eq(_T_1774, UInt<1>(0h0)) \n when _T_1775 : \n node _T_1776 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1776 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_76 \n node _T_1777 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1778 = asUInt(reset) \n node _T_1779 = eq(_T_1778, UInt<1>(0h0)) \n when _T_1779 : \n node _T_1780 = eq(_T_1777, UInt<1>(0h0)) \n when _T_1780 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_1777, UInt<1>(0h1), \"\") : assert_77 \n node _T_1781 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1782 = or(_T_1781, io.in.d.bits.corrupt) \n node _T_1783 = asUInt(reset) \n node _T_1784 = eq(_T_1783, UInt<1>(0h0)) \n when _T_1784 : \n node _T_1785 = eq(_T_1782, UInt<1>(0h0)) \n when _T_1785 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_1782, UInt<1>(0h1), \"\") : assert_78 \n node _T_1786 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1787 = or(UInt<1>(0h1), _T_1786) \n node _T_1788 = asUInt(reset) \n node _T_1789 = eq(_T_1788, UInt<1>(0h0)) \n when _T_1789 : \n node _T_1790 = eq(_T_1787, UInt<1>(0h0)) \n when _T_1790 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_1787, UInt<1>(0h1), \"\") : assert_79 \n node _T_1791 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_1791 : \n node _T_1792 = asUInt(reset) \n node _T_1793 = eq(_T_1792, UInt<1>(0h0)) \n when _T_1793 : \n node _T_1794 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1794 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_80 \n node _T_1795 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1796 = asUInt(reset) \n node _T_1797 = eq(_T_1796, UInt<1>(0h0)) \n when _T_1797 : \n node _T_1798 = eq(_T_1795, UInt<1>(0h0)) \n when _T_1798 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_1795, UInt<1>(0h1), \"\") : assert_81 \n node _T_1799 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1800 = asUInt(reset) \n node _T_1801 = eq(_T_1800, UInt<1>(0h0)) \n when _T_1801 : \n node _T_1802 = eq(_T_1799, UInt<1>(0h0)) \n when _T_1802 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_1799, UInt<1>(0h1), \"\") : assert_82 \n node _T_1803 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1804 = or(UInt<1>(0h1), _T_1803) \n node _T_1805 = asUInt(reset) \n node _T_1806 = eq(_T_1805, UInt<1>(0h0)) \n when _T_1806 : \n node _T_1807 = eq(_T_1804, UInt<1>(0h0)) \n when _T_1807 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_1804, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_4.bits.data, UInt<64>(0h0) \n connect _WIRE_4.bits.mask, UInt<8>(0h0) \n connect _WIRE_4.bits.address, UInt<29>(0h0) \n connect _WIRE_4.bits.source, UInt<8>(0h0) \n connect _WIRE_4.bits.size, UInt<4>(0h0) \n connect _WIRE_4.bits.param, UInt<2>(0h0) \n connect _WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_1808 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_1809 = asUInt(reset) \n node _T_1810 = eq(_T_1809, UInt<1>(0h0)) \n when _T_1810 : \n node _T_1811 = eq(_T_1808, UInt<1>(0h0)) \n when _T_1811 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_1808, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<29>(0h0) \n connect _WIRE_6.bits.source, UInt<8>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_1812 = eq(_WIRE_7.valid, UInt<1>(0h0)) \n node _T_1813 = asUInt(reset) \n node _T_1814 = eq(_T_1813, UInt<1>(0h0)) \n when _T_1814 : \n node _T_1815 = eq(_T_1812, UInt<1>(0h0)) \n when _T_1815 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_1812, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_8.bits.sink, UInt<1>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_1816 = eq(_WIRE_9.valid, UInt<1>(0h0)) \n node _T_1817 = asUInt(reset) \n node _T_1818 = eq(_T_1817, UInt<1>(0h0)) \n when _T_1818 : \n node _T_1819 = eq(_T_1816, UInt<1>(0h0)) \n when _T_1819 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_1816, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_1820 = eq(a_first, UInt<1>(0h0)) \n node _T_1821 = and(io.in.a.valid, _T_1820) \n when _T_1821 : \n node _T_1822 = eq(io.in.a.bits.opcode, opcode) \n node _T_1823 = asUInt(reset) \n node _T_1824 = eq(_T_1823, UInt<1>(0h0)) \n when _T_1824 : \n node _T_1825 = eq(_T_1822, UInt<1>(0h0)) \n when _T_1825 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_1822, UInt<1>(0h1), \"\") : assert_87 \n node _T_1826 = eq(io.in.a.bits.param, param) \n node _T_1827 = asUInt(reset) \n node _T_1828 = eq(_T_1827, UInt<1>(0h0)) \n when _T_1828 : \n node _T_1829 = eq(_T_1826, UInt<1>(0h0)) \n when _T_1829 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_1826, UInt<1>(0h1), \"\") : assert_88 \n node _T_1830 = eq(io.in.a.bits.size, size) \n node _T_1831 = asUInt(reset) \n node _T_1832 = eq(_T_1831, UInt<1>(0h0)) \n when _T_1832 : \n node _T_1833 = eq(_T_1830, UInt<1>(0h0)) \n when _T_1833 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_1830, UInt<1>(0h1), \"\") : assert_89 \n node _T_1834 = eq(io.in.a.bits.source, source) \n node _T_1835 = asUInt(reset) \n node _T_1836 = eq(_T_1835, UInt<1>(0h0)) \n when _T_1836 : \n node _T_1837 = eq(_T_1834, UInt<1>(0h0)) \n when _T_1837 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_1834, UInt<1>(0h1), \"\") : assert_90 \n node _T_1838 = eq(io.in.a.bits.address, address) \n node _T_1839 = asUInt(reset) \n node _T_1840 = eq(_T_1839, UInt<1>(0h0)) \n when _T_1840 : \n node _T_1841 = eq(_T_1838, UInt<1>(0h0)) \n when _T_1841 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_1838, UInt<1>(0h1), \"\") : assert_91 \n node _T_1842 = and(io.in.a.ready, io.in.a.valid) \n node _T_1843 = and(_T_1842, a_first) \n when _T_1843 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_1844 = eq(d_first, UInt<1>(0h0)) \n node _T_1845 = and(io.in.d.valid, _T_1844) \n when _T_1845 : \n node _T_1846 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_1847 = asUInt(reset) \n node _T_1848 = eq(_T_1847, UInt<1>(0h0)) \n when _T_1848 : \n node _T_1849 = eq(_T_1846, UInt<1>(0h0)) \n when _T_1849 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_1846, UInt<1>(0h1), \"\") : assert_92 \n node _T_1850 = eq(io.in.d.bits.param, param_1) \n node _T_1851 = asUInt(reset) \n node _T_1852 = eq(_T_1851, UInt<1>(0h0)) \n when _T_1852 : \n node _T_1853 = eq(_T_1850, UInt<1>(0h0)) \n when _T_1853 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_1850, UInt<1>(0h1), \"\") : assert_93 \n node _T_1854 = eq(io.in.d.bits.size, size_1) \n node _T_1855 = asUInt(reset) \n node _T_1856 = eq(_T_1855, UInt<1>(0h0)) \n when _T_1856 : \n node _T_1857 = eq(_T_1854, UInt<1>(0h0)) \n when _T_1857 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_1854, UInt<1>(0h1), \"\") : assert_94 \n node _T_1858 = eq(io.in.d.bits.source, source_1) \n node _T_1859 = asUInt(reset) \n node _T_1860 = eq(_T_1859, UInt<1>(0h0)) \n when _T_1860 : \n node _T_1861 = eq(_T_1858, UInt<1>(0h0)) \n when _T_1861 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_1858, UInt<1>(0h1), \"\") : assert_95 \n node _T_1862 = eq(io.in.d.bits.sink, sink) \n node _T_1863 = asUInt(reset) \n node _T_1864 = eq(_T_1863, UInt<1>(0h0)) \n when _T_1864 : \n node _T_1865 = eq(_T_1862, UInt<1>(0h0)) \n when _T_1865 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_1862, UInt<1>(0h1), \"\") : assert_96 \n node _T_1866 = eq(io.in.d.bits.denied, denied) \n node _T_1867 = asUInt(reset) \n node _T_1868 = eq(_T_1867, UInt<1>(0h0)) \n when _T_1868 : \n node _T_1869 = eq(_T_1866, UInt<1>(0h0)) \n when _T_1869 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_1866, UInt<1>(0h1), \"\") : assert_97 \n node _T_1870 = and(io.in.d.ready, io.in.d.valid) \n node _T_1871 = and(_T_1870, d_first) \n when _T_1871 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) \n regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) \n regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<129> \n connect a_set, UInt<129>(0h0) \n wire a_set_wo_ready : UInt<129> \n connect a_set_wo_ready, UInt<129>(0h0) \n wire a_opcodes_set : UInt<516> \n connect a_opcodes_set, UInt<516>(0h0) \n wire a_sizes_set : UInt<1032> \n connect a_sizes_set, UInt<1032>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<8> \n connect a_size_lookup, UInt<8>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<5> \n connect a_sizes_set_interm, UInt<5>(0h0) \n node _T_1872 = and(io.in.a.valid, a_first_1) \n node _T_1873 = and(_T_1872, UInt<1>(0h1)) \n when _T_1873 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_1874 = and(io.in.a.ready, io.in.a.valid) \n node _T_1875 = and(_T_1874, a_first_1) \n node _T_1876 = and(_T_1875, UInt<1>(0h1)) \n when _T_1876 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_1877 = dshr(inflight, io.in.a.bits.source) \n node _T_1878 = bits(_T_1877, 0, 0) \n node _T_1879 = eq(_T_1878, UInt<1>(0h0)) \n node _T_1880 = asUInt(reset) \n node _T_1881 = eq(_T_1880, UInt<1>(0h0)) \n when _T_1881 : \n node _T_1882 = eq(_T_1879, UInt<1>(0h0)) \n when _T_1882 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_1879, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<129> \n connect d_clr, UInt<129>(0h0) \n wire d_clr_wo_ready : UInt<129> \n connect d_clr_wo_ready, UInt<129>(0h0) \n wire d_opcodes_clr : UInt<516> \n connect d_opcodes_clr, UInt<516>(0h0) \n wire d_sizes_clr : UInt<1032> \n connect d_sizes_clr, UInt<1032>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1883 = and(io.in.d.valid, d_first_1) \n node _T_1884 = and(_T_1883, UInt<1>(0h1)) \n node _T_1885 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1886 = and(_T_1884, _T_1885) \n when _T_1886 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_1887 = and(io.in.d.ready, io.in.d.valid) \n node _T_1888 = and(_T_1887, d_first_1) \n node _T_1889 = and(_T_1888, UInt<1>(0h1)) \n node _T_1890 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1891 = and(_T_1889, _T_1890) \n when _T_1891 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_1892 = and(io.in.d.valid, d_first_1) \n node _T_1893 = and(_T_1892, UInt<1>(0h1)) \n node _T_1894 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1895 = and(_T_1893, _T_1894) \n when _T_1895 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_1896 = dshr(inflight, io.in.d.bits.source) \n node _T_1897 = bits(_T_1896, 0, 0) \n node _T_1898 = or(_T_1897, same_cycle_resp) \n node _T_1899 = asUInt(reset) \n node _T_1900 = eq(_T_1899, UInt<1>(0h0)) \n when _T_1900 : \n node _T_1901 = eq(_T_1898, UInt<1>(0h0)) \n when _T_1901 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_1898, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_1902 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_1903 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_1904 = or(_T_1902, _T_1903) \n node _T_1905 = asUInt(reset) \n node _T_1906 = eq(_T_1905, UInt<1>(0h0)) \n when _T_1906 : \n node _T_1907 = eq(_T_1904, UInt<1>(0h0)) \n when _T_1907 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_1904, UInt<1>(0h1), \"\") : assert_100 \n node _T_1908 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_1909 = asUInt(reset) \n node _T_1910 = eq(_T_1909, UInt<1>(0h0)) \n when _T_1910 : \n node _T_1911 = eq(_T_1908, UInt<1>(0h0)) \n when _T_1911 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_1908, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_1912 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_1913 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_1914 = or(_T_1912, _T_1913) \n node _T_1915 = asUInt(reset) \n node _T_1916 = eq(_T_1915, UInt<1>(0h0)) \n when _T_1916 : \n node _T_1917 = eq(_T_1914, UInt<1>(0h0)) \n when _T_1917 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_1914, UInt<1>(0h1), \"\") : assert_102 \n node _T_1918 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_1919 = asUInt(reset) \n node _T_1920 = eq(_T_1919, UInt<1>(0h0)) \n when _T_1920 : \n node _T_1921 = eq(_T_1918, UInt<1>(0h0)) \n when _T_1921 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_1918, UInt<1>(0h1), \"\") : assert_103 \n node _T_1922 = and(io.in.d.valid, d_first_1) \n node _T_1923 = and(_T_1922, a_first_1) \n node _T_1924 = and(_T_1923, io.in.a.valid) \n node _T_1925 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_1926 = and(_T_1924, _T_1925) \n node _T_1927 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1928 = and(_T_1926, _T_1927) \n when _T_1928 : \n node _T_1929 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_1930 = or(_T_1929, io.in.a.ready) \n node _T_1931 = asUInt(reset) \n node _T_1932 = eq(_T_1931, UInt<1>(0h0)) \n when _T_1932 : \n node _T_1933 = eq(_T_1930, UInt<1>(0h0)) \n when _T_1933 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_1930, UInt<1>(0h1), \"\") : assert_104 \n node _T_1934 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_1935 = orr(a_set_wo_ready) \n node _T_1936 = eq(_T_1935, UInt<1>(0h0)) \n node _T_1937 = or(_T_1934, _T_1936) \n node _T_1938 = asUInt(reset) \n node _T_1939 = eq(_T_1938, UInt<1>(0h0)) \n when _T_1939 : \n node _T_1940 = eq(_T_1937, UInt<1>(0h0)) \n when _T_1940 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_1937, UInt<1>(0h1), \"\") : assert_105 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_44 \n node _T_1941 = orr(inflight) \n node _T_1942 = eq(_T_1941, UInt<1>(0h0)) \n node _T_1943 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_1944 = or(_T_1942, _T_1943) \n node _T_1945 = lt(watchdog, plusarg_reader.out) \n node _T_1946 = or(_T_1944, _T_1945) \n node _T_1947 = asUInt(reset) \n node _T_1948 = eq(_T_1947, UInt<1>(0h0)) \n when _T_1948 : \n node _T_1949 = eq(_T_1946, UInt<1>(0h0)) \n when _T_1949 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_1946, UInt<1>(0h1), \"\") : assert_106 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_1950 = and(io.in.a.ready, io.in.a.valid) \n node _T_1951 = and(io.in.d.ready, io.in.d.valid) \n node _T_1952 = or(_T_1950, _T_1951) \n when _T_1952 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) \n regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) \n regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<29>(0h0) \n connect _c_first_WIRE.bits.source, UInt<8>(0h0) \n connect _c_first_WIRE.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<129> \n connect c_set, UInt<129>(0h0) \n wire c_set_wo_ready : UInt<129> \n connect c_set_wo_ready, UInt<129>(0h0) \n wire c_opcodes_set : UInt<516> \n connect c_opcodes_set, UInt<516>(0h0) \n wire c_sizes_set : UInt<1032> \n connect c_sizes_set, UInt<1032>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<8> \n connect c_size_lookup, UInt<8>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<5> \n connect c_sizes_set_interm, UInt<5>(0h0) \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<29>(0h0) \n connect _WIRE_10.bits.source, UInt<8>(0h0) \n connect _WIRE_10.bits.size, UInt<4>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_1953 = and(_WIRE_11.valid, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<29>(0h0) \n connect _WIRE_12.bits.source, UInt<8>(0h0) \n connect _WIRE_12.bits.size, UInt<4>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_1954 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_1955 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_1956 = and(_T_1954, _T_1955) \n node _T_1957 = and(_T_1953, _T_1956) \n when _T_1957 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<29>(0h0) \n connect _WIRE_14.bits.source, UInt<8>(0h0) \n connect _WIRE_14.bits.size, UInt<4>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_1958 = and(_WIRE_15.ready, _WIRE_15.valid) \n node _T_1959 = and(_T_1958, c_first) \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<29>(0h0) \n connect _WIRE_16.bits.source, UInt<8>(0h0) \n connect _WIRE_16.bits.size, UInt<4>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_1960 = bits(_WIRE_17.bits.opcode, 2, 2) \n node _T_1961 = bits(_WIRE_17.bits.opcode, 1, 1) \n node _T_1962 = and(_T_1960, _T_1961) \n node _T_1963 = and(_T_1959, _T_1962) \n when _T_1963 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_set_WIRE.bits.source, UInt<8>(0h0) \n connect _c_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<29>(0h0) \n connect _WIRE_18.bits.source, UInt<8>(0h0) \n connect _WIRE_18.bits.size, UInt<4>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_1964 = dshr(inflight_1, _WIRE_19.bits.source) \n node _T_1965 = bits(_T_1964, 0, 0) \n node _T_1966 = eq(_T_1965, UInt<1>(0h0)) \n node _T_1967 = asUInt(reset) \n node _T_1968 = eq(_T_1967, UInt<1>(0h0)) \n when _T_1968 : \n node _T_1969 = eq(_T_1966, UInt<1>(0h0)) \n when _T_1969 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_1966, UInt<1>(0h1), \"\") : assert_107 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<129> \n connect d_clr_1, UInt<129>(0h0) \n wire d_clr_wo_ready_1 : UInt<129> \n connect d_clr_wo_ready_1, UInt<129>(0h0) \n wire d_opcodes_clr_1 : UInt<516> \n connect d_opcodes_clr_1, UInt<516>(0h0) \n wire d_sizes_clr_1 : UInt<1032> \n connect d_sizes_clr_1, UInt<1032>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1970 = and(io.in.d.valid, d_first_2) \n node _T_1971 = and(_T_1970, UInt<1>(0h1)) \n node _T_1972 = and(_T_1971, d_release_ack_1) \n when _T_1972 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_1973 = and(io.in.d.ready, io.in.d.valid) \n node _T_1974 = and(_T_1973, d_first_2) \n node _T_1975 = and(_T_1974, UInt<1>(0h1)) \n node _T_1976 = and(_T_1975, d_release_ack_1) \n when _T_1976 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_1977 = and(io.in.d.valid, d_first_2) \n node _T_1978 = and(_T_1977, UInt<1>(0h1)) \n node _T_1979 = and(_T_1978, d_release_ack_1) \n when _T_1979 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_1980 = dshr(inflight_1, io.in.d.bits.source) \n node _T_1981 = bits(_T_1980, 0, 0) \n node _T_1982 = or(_T_1981, same_cycle_resp_1) \n node _T_1983 = asUInt(reset) \n node _T_1984 = eq(_T_1983, UInt<1>(0h0)) \n when _T_1984 : \n node _T_1985 = eq(_T_1982, UInt<1>(0h0)) \n when _T_1985 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_1982, UInt<1>(0h1), \"\") : assert_108 \n when same_cycle_resp_1 : \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<29>(0h0) \n connect _WIRE_20.bits.source, UInt<8>(0h0) \n connect _WIRE_20.bits.size, UInt<4>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_1986 = eq(io.in.d.bits.size, _WIRE_21.bits.size) \n node _T_1987 = asUInt(reset) \n node _T_1988 = eq(_T_1987, UInt<1>(0h0)) \n when _T_1988 : \n node _T_1989 = eq(_T_1986, UInt<1>(0h0)) \n when _T_1989 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_1986, UInt<1>(0h1), \"\") : assert_109 \n else :\n\n node _T_1990 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_1991 = asUInt(reset) \n node _T_1992 = eq(_T_1991, UInt<1>(0h0)) \n when _T_1992 : \n node _T_1993 = eq(_T_1990, UInt<1>(0h0)) \n when _T_1993 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_1990, UInt<1>(0h1), \"\") : assert_110 \n node _T_1994 = and(io.in.d.valid, d_first_2) \n node _T_1995 = and(_T_1994, c_first) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<29>(0h0) \n connect _WIRE_22.bits.source, UInt<8>(0h0) \n connect _WIRE_22.bits.size, UInt<4>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_1996 = and(_T_1995, _WIRE_23.valid) \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<29>(0h0) \n connect _WIRE_24.bits.source, UInt<8>(0h0) \n connect _WIRE_24.bits.size, UInt<4>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_1997 = eq(_WIRE_25.bits.source, io.in.d.bits.source) \n node _T_1998 = and(_T_1996, _T_1997) \n node _T_1999 = and(_T_1998, d_release_ack_1) \n node _T_2000 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_2001 = and(_T_1999, _T_2000) \n when _T_2001 : \n node _T_2002 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_26.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_26.bits.data, UInt<64>(0h0) \n connect _WIRE_26.bits.address, UInt<29>(0h0) \n connect _WIRE_26.bits.source, UInt<8>(0h0) \n connect _WIRE_26.bits.size, UInt<4>(0h0) \n connect _WIRE_26.bits.param, UInt<3>(0h0) \n connect _WIRE_26.bits.opcode, UInt<3>(0h0) \n connect _WIRE_26.valid, UInt<1>(0h0) \n connect _WIRE_26.ready, UInt<1>(0h0) \n wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_27.bits, _WIRE_26.bits \n connect _WIRE_27.valid, _WIRE_26.valid \n connect _WIRE_27.ready, _WIRE_26.ready \n node _T_2003 = or(_T_2002, _WIRE_27.ready) \n node _T_2004 = asUInt(reset) \n node _T_2005 = eq(_T_2004, UInt<1>(0h0)) \n when _T_2005 : \n node _T_2006 = eq(_T_2003, UInt<1>(0h0)) \n when _T_2006 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_2003, UInt<1>(0h1), \"\") : assert_111 \n node _T_2007 = orr(c_set_wo_ready) \n when _T_2007 : \n node _T_2008 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_2009 = asUInt(reset) \n node _T_2010 = eq(_T_2009, UInt<1>(0h0)) \n when _T_2010 : \n node _T_2011 = eq(_T_2008, UInt<1>(0h0)) \n when _T_2011 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_2008, UInt<1>(0h1), \"\") : assert_112 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_45 \n node _T_2012 = orr(inflight_1) \n node _T_2013 = eq(_T_2012, UInt<1>(0h0)) \n node _T_2014 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_2015 = or(_T_2013, _T_2014) \n node _T_2016 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_2017 = or(_T_2015, _T_2016) \n node _T_2018 = asUInt(reset) \n node _T_2019 = eq(_T_2018, UInt<1>(0h0)) \n when _T_2019 : \n node _T_2020 = eq(_T_2017, UInt<1>(0h0)) \n when _T_2020 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, _T_2017, UInt<1>(0h1), \"\") : assert_113 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_28.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_28.bits.data, UInt<64>(0h0) \n connect _WIRE_28.bits.address, UInt<29>(0h0) \n connect _WIRE_28.bits.source, UInt<8>(0h0) \n connect _WIRE_28.bits.size, UInt<4>(0h0) \n connect _WIRE_28.bits.param, UInt<3>(0h0) \n connect _WIRE_28.bits.opcode, UInt<3>(0h0) \n connect _WIRE_28.valid, UInt<1>(0h0) \n connect _WIRE_28.ready, UInt<1>(0h0) \n wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_29.bits, _WIRE_28.bits \n connect _WIRE_29.valid, _WIRE_28.valid \n connect _WIRE_29.ready, _WIRE_28.ready \n node _T_2021 = and(_WIRE_29.ready, _WIRE_29.valid) \n node _T_2022 = and(io.in.d.ready, io.in.d.valid) \n node _T_2023 = or(_T_2021, _T_2022) \n when _T_2023 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_22(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [28:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [8:0] c_first_beats1_decode = 9'h0;\t// @[Edges.scala:220:59]\n wire [8:0] c_first_beats1 = 9'h0;\t// @[Edges.scala:221:14]\n wire [8:0] _c_first_count_T = 9'h0;\t// @[Edges.scala:234:27]\n wire [8:0] c_first_count = 9'h0;\t// @[Edges.scala:234:25]\n wire [8:0] _c_first_counter_T = 9'h0;\t// @[Edges.scala:236:21]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_5 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_11 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_15 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_17 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_21 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_23 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_33 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_41 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_67 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_69 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_73 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_75 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_79 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_81 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_85 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_87 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_97 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_105 = 1'h1;\t// @[Parameters.scala:56:32]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [8:0] c_first_counter1 = 9'h1FF;\t// @[Edges.scala:230:28]\n wire [9:0] _c_first_counter1_T = 10'h3FF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_first_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_first_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_first_WIRE_2_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_first_WIRE_3_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_set_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_set_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0;\t// @[Bundles.scala:265:74]\n wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [2051:0] _c_sizes_set_T_1 = 2052'h0;\t// @[Monitor.scala:768:52]\n wire [10:0] _c_opcodes_set_T = 11'h0;\t// @[Monitor.scala:767:79]\n wire [10:0] _c_sizes_set_T = 11'h0;\t// @[Monitor.scala:768:77]\n wire [2050:0] _c_opcodes_set_T_1 = 2051'h0;\t// @[Monitor.scala:767:54]\n wire [4:0] _c_sizes_set_interm_T_1 = 5'h1;\t// @[Monitor.scala:766:59]\n wire [4:0] c_sizes_set_interm = 5'h0;\t// @[Monitor.scala:755:40]\n wire [4:0] _c_sizes_set_interm_T = 5'h0;\t// @[Monitor.scala:766:51]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [255:0] _c_set_wo_ready_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [255:0] _c_set_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [1031:0] c_sizes_set = 1032'h0;\t// @[Monitor.scala:741:34]\n wire [515:0] c_opcodes_set = 516'h0;\t// @[Monitor.scala:740:34]\n wire [128:0] c_set = 129'h0;\t// @[Monitor.scala:738:34]\n wire [128:0] c_set_wo_ready = 129'h0;\t// @[Monitor.scala:739:34]\n wire [11:0] _c_first_beats1_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [26:0] _c_first_beats1_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_sizes_clr_T = 4'h8;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_sizes_clr_T_6 = 4'h8;\t// @[Monitor.scala:791:48]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = io_in_a_bits_source_0 == 8'h10;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_0 = _source_ok_T;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_2 = _source_ok_T_1 == 6'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_4 = _source_ok_T_2;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_6 = _source_ok_T_4;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1 = _source_ok_T_6;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_8 = _source_ok_T_7 == 6'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_10 = _source_ok_T_8;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_12 = _source_ok_T_10;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_2 = _source_ok_T_12;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_14 = _source_ok_T_13 == 6'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_16 = _source_ok_T_14;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_18 = _source_ok_T_16;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_3 = _source_ok_T_18;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_20 = _source_ok_T_19 == 6'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_22 = _source_ok_T_20;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_24 = _source_ok_T_22;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_4 = _source_ok_T_24;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_5 = _source_ok_T_25;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_6 = _source_ok_T_26;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_7 = _source_ok_T_27;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_8 = _source_ok_T_28;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_9 = _source_ok_T_29;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_10 = _source_ok_T_30;\t// @[Parameters.scala:1138:31]\n wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_32 = _source_ok_T_31 == 5'h6;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_34 = _source_ok_T_32;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_11 = _source_ok_T_36;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_12 = _source_ok_T_37;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_13 = _source_ok_T_38;\t// @[Parameters.scala:1138:31]\n wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_40 = _source_ok_T_39 == 5'h4;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_42 = _source_ok_T_40;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_14 = _source_ok_T_44;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_15 = _source_ok_T_45;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_16 = _source_ok_T_46;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_17 = _source_ok_T_47;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 29'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [1:0] uncommonBits = _uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_0 = _source_ok_T_64;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_66 = _source_ok_T_65 == 6'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_68 = _source_ok_T_66;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_70 = _source_ok_T_68;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_1 = _source_ok_T_70;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_72 = _source_ok_T_71 == 6'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_74 = _source_ok_T_72;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_76 = _source_ok_T_74;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_2 = _source_ok_T_76;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_78 = _source_ok_T_77 == 6'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_80 = _source_ok_T_78;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_82 = _source_ok_T_80;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_3 = _source_ok_T_82;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_84 = _source_ok_T_83 == 6'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_86 = _source_ok_T_84;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_88 = _source_ok_T_86;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_4 = _source_ok_T_88;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_5 = _source_ok_T_89;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_6 = _source_ok_T_90;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_7 = _source_ok_T_91;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_8 = _source_ok_T_92;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_9 = _source_ok_T_93;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_10 = _source_ok_T_94;\t// @[Parameters.scala:1138:31]\n wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_96 = _source_ok_T_95 == 5'h6;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_98 = _source_ok_T_96;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_11 = _source_ok_T_100;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_12 = _source_ok_T_101;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_13 = _source_ok_T_102;\t// @[Parameters.scala:1138:31]\n wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_104 = _source_ok_T_103 == 5'h4;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_106 = _source_ok_T_104;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_14 = _source_ok_T_108;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_15 = _source_ok_T_109;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_16 = _source_ok_T_110;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_17 = _source_ok_T_111;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1950 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1950;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1950;\t// @[Decoupled.scala:51:35]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [3:0] size;\t// @[Monitor.scala:389:22]\n reg [7:0] source;\t// @[Monitor.scala:390:22]\n reg [28:0] address;\t// @[Monitor.scala:391:22]\n wire _T_2023 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_2023;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_2023;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_2023;\t// @[Decoupled.scala:51:35]\n wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [3:0] size_1;\t// @[Monitor.scala:540:22]\n reg [7:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [128:0] inflight;\t// @[Monitor.scala:614:27]\n reg [515:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [1031:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [128:0] a_set;\t// @[Monitor.scala:626:34]\n wire [128:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [515:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [1031:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [10:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [10:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [10:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [10:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [7:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :641:65]\n wire [10:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65]\n wire [10:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_2;\t// @[Monitor.scala:641:65, :681:99]\n wire [10:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65, :750:67]\n wire [10:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_2;\t// @[Monitor.scala:641:65, :791:99]\n wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[7:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [4:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_3;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_3;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire _T_1876 = _T_1950 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1876 ? _a_set_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1876 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1876 ? _a_sizes_set_interm_T_1 : 5'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1876 ? _a_opcodes_set_T_1[515:0] : 516'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :660:77]\n wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_1876 ? _a_sizes_set_T_1[1031:0] : 1032'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [128:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [128:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [515:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [1031:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1922 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1922 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire _T_1891 = _T_2023 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1891 ? _d_clr_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1891 ? _d_opcodes_clr_T_5[515:0] : 516'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1891 ? _d_sizes_clr_T_5[1031:0] : 1032'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [128:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [128:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [128:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [128:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [515:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [1031:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [7:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[7:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [128:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [128:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [515:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [1031:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1994 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1994 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire _T_1976 = _T_2023 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1976 ? _d_clr_T_1[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1976 ? _d_opcodes_clr_T_11[515:0] : 516'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1976 ? _d_sizes_clr_T_11[1031:0] : 1032'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [128:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32183,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module PE_415 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} \n\n\n inst mac_unit of MacUnit_159 \n connect mac_unit.clock, clock\n\n connect mac_unit.reset, reset\n\n reg c1 : SInt<8>, clock \n reg c2 : SInt<8>, clock \n connect io.out_a, io.in_a \n connect io.out_control.dataflow, io.in_control.dataflow \n connect io.out_control.propagate, io.in_control.propagate \n connect io.out_control.shift, io.in_control.shift \n connect io.out_id, io.in_id \n connect io.out_last, io.in_last \n connect io.out_valid, io.in_valid \n connect mac_unit.io.in_a, io.in_a \n reg last_s : UInt<1>, clock \n when io.in_valid : \n connect last_s, io.in_control.propagate \n node flip = neq(last_s, io.in_control.propagate) \n node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) \n connect io.bad_dataflow, UInt<1>(0h0) \n node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) \n node _T_1 = and(UInt<1>(0h0), _T) \n node _T_2 = or(UInt<1>(0h0), _T_1) \n when _T_2 : \n node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_3 : \n node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) \n node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) \n node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) \n node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) \n node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_1 = asUInt(c1) \n node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) \n node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) \n node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) \n node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) \n node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) \n node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) \n node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T = dshr(c1, shift_offset) \n node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) \n node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) \n node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) \n node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) \n node _io_out_c_T = dshr(c1, shift_offset) \n node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) \n node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) \n node _io_out_c_T_4 = asSInt(_io_out_c_T_3) \n node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) \n node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) \n node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) \n node _io_out_c_T_10 = asSInt(_io_out_c_T_9) \n connect io.out_c, _io_out_c_T_10 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE : SInt<8> \n node _mac_unit_io_in_b_T = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) \n connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE \n connect mac_unit.io.in_c, c2 \n connect c2, mac_unit.io.out_d \n node _c1_T = bits(io.in_d, 7, 0) \n node _c1_T_1 = asSInt(_c1_T) \n connect c1, _c1_T_1 \n else :\n\n node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) \n node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) \n node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) \n node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) \n node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_10 = asUInt(c2) \n node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) \n node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) \n node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) \n node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) \n node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) \n node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) \n node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) \n node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) \n node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) \n node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) \n node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) \n node _io_out_c_T_11 = dshr(c2, shift_offset) \n node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) \n node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) \n node _io_out_c_T_15 = asSInt(_io_out_c_T_14) \n node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) \n node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) \n node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) \n node _io_out_c_T_21 = asSInt(_io_out_c_T_20) \n connect io.out_c, _io_out_c_T_21 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE_1 : SInt<8> \n node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) \n connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 \n connect mac_unit.io.in_c, c1 \n connect c1, mac_unit.io.out_d \n node _c2_T = bits(io.in_d, 7, 0) \n node _c2_T_1 = asSInt(_c2_T) \n connect c2, _c2_T_1 \n else :\n\n node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) \n node _T_5 = and(UInt<1>(0h0), _T_4) \n node _T_6 = or(UInt<1>(0h1), _T_5) \n when _T_6 : \n node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_7 : \n connect io.out_c, c1 \n wire _mac_unit_io_in_b_WIRE_2 : SInt<8> \n node _mac_unit_io_in_b_T_4 = asUInt(c2) \n node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) \n connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c1, io.in_d \n else :\n\n connect io.out_c, c2 \n wire _mac_unit_io_in_b_WIRE_3 : SInt<8> \n node _mac_unit_io_in_b_T_6 = asUInt(c1) \n node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) \n connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c2, io.in_d \n else :\n\n connect io.bad_dataflow, UInt<1>(0h1) \n invalidate io.out_c \n invalidate io.out_b \n wire _mac_unit_io_in_b_WIRE_4 : SInt<8> \n node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) \n connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 \n connect mac_unit.io.in_c, c2 \n node _T_8 = eq(io.in_valid, UInt<1>(0h0)) \n when _T_8 : \n connect c1, c1 \n connect c2, c2 \n invalidate mac_unit.io.in_b \n invalidate mac_unit.io.in_c"},"response":{"kind":"string","value":"module PE_415(\t// @[PE.scala:31:7]\n input clock,\t// @[PE.scala:31:7]\n input reset,\t// @[PE.scala:31:7]\n input [7:0] io_in_a,\t// @[PE.scala:35:14]\n input [19:0] io_in_b,\t// @[PE.scala:35:14]\n input [19:0] io_in_d,\t// @[PE.scala:35:14]\n output [7:0] io_out_a,\t// @[PE.scala:35:14]\n output [19:0] io_out_b,\t// @[PE.scala:35:14]\n output [19:0] io_out_c,\t// @[PE.scala:35:14]\n input io_in_control_dataflow,\t// @[PE.scala:35:14]\n input io_in_control_propagate,\t// @[PE.scala:35:14]\n input [4:0] io_in_control_shift,\t// @[PE.scala:35:14]\n output io_out_control_dataflow,\t// @[PE.scala:35:14]\n output io_out_control_propagate,\t// @[PE.scala:35:14]\n output [4:0] io_out_control_shift,\t// @[PE.scala:35:14]\n input [2:0] io_in_id,\t// @[PE.scala:35:14]\n output [2:0] io_out_id,\t// @[PE.scala:35:14]\n input io_in_last,\t// @[PE.scala:35:14]\n output io_out_last,\t// @[PE.scala:35:14]\n input io_in_valid,\t// @[PE.scala:35:14]\n output io_out_valid\t// @[PE.scala:35:14]\n);\n\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:31:7]\n wire [19:0] io_in_b_0 = io_in_b;\t// @[PE.scala:31:7]\n wire [19:0] io_in_d_0 = io_in_d;\t// @[PE.scala:31:7]\n wire io_in_control_dataflow_0 = io_in_control_dataflow;\t// @[PE.scala:31:7]\n wire io_in_control_propagate_0 = io_in_control_propagate;\t// @[PE.scala:31:7]\n wire [4:0] io_in_control_shift_0 = io_in_control_shift;\t// @[PE.scala:31:7]\n wire [2:0] io_in_id_0 = io_in_id;\t// @[PE.scala:31:7]\n wire io_in_last_0 = io_in_last;\t// @[PE.scala:31:7]\n wire io_in_valid_0 = io_in_valid;\t// @[PE.scala:31:7]\n wire io_bad_dataflow = 1'h0;\t// @[PE.scala:31:7]\n wire _io_out_c_T_5 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_6 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire _io_out_c_T_16 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_17 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire [7:0] io_out_a_0 = io_in_a_0;\t// @[PE.scala:31:7]\n wire [19:0] _mac_unit_io_in_b_T = io_in_b_0;\t// @[PE.scala:31:7, :106:37]\n wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0;\t// @[PE.scala:31:7, :113:37]\n wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0;\t// @[PE.scala:31:7, :137:35]\n wire io_out_control_dataflow_0 = io_in_control_dataflow_0;\t// @[PE.scala:31:7]\n wire io_out_control_propagate_0 = io_in_control_propagate_0;\t// @[PE.scala:31:7]\n wire [4:0] io_out_control_shift_0 = io_in_control_shift_0;\t// @[PE.scala:31:7]\n wire [2:0] io_out_id_0 = io_in_id_0;\t// @[PE.scala:31:7]\n wire io_out_last_0 = io_in_last_0;\t// @[PE.scala:31:7]\n wire io_out_valid_0 = io_in_valid_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_b_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_c_0;\t// @[PE.scala:31:7]\n reg [7:0] c1;\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_zeros_T_1 = c1;\t// @[PE.scala:70:15]\n wire [7:0] _mac_unit_io_in_b_T_6 = c1;\t// @[PE.scala:70:15, :127:38]\n reg [7:0] c2;\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_zeros_T_10 = c2;\t// @[PE.scala:71:15]\n wire [7:0] _mac_unit_io_in_b_T_4 = c2;\t// @[PE.scala:71:15, :121:38]\n reg last_s;\t// @[PE.scala:89:25]\n wire flip = last_s != io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25, :90:21]\n wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0;\t// @[PE.scala:31:7, :90:21, :91:25]\n wire _GEN = shift_offset == 5'h0;\t// @[PE.scala:91:25]\n wire _io_out_c_point_five_T;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T = _GEN;\t// @[Arithmetic.scala:101:32]\n wire _io_out_c_point_five_T_5;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T_5 = _GEN;\t// @[Arithmetic.scala:101:32]\n wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1;\t// @[PE.scala:91:25]\n wire [5:0] _io_out_c_point_five_T_1;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_1 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_2;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_2 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [5:0] _io_out_c_point_five_T_6;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_6 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_11;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_11 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2);\t// @[PE.scala:70:15]\n wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire _GEN_1 = shift_offset < 5'h2;\t// @[PE.scala:91:25]\n wire _io_out_c_zeros_T;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire _io_out_c_zeros_T_9;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T_9 = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros = |_io_out_c_zeros_T_8;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_2 = {3'h0, shift_offset};\t// @[PE.scala:91:25]\n wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2);\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_ones_digit_T;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T = _GEN_3;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T = _GEN_3;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r = _io_out_c_r_T_1;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_4 = _io_out_c_T_3;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_8 = _io_out_c_T_7;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_9 = _io_out_c_T_8;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_10 = _io_out_c_T_9;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T;\t// @[PE.scala:106:37]\n wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0];\t// @[PE.scala:106:37]\n wire [7:0] _c1_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c2_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c1_T_1 = _c1_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7);\t// @[PE.scala:71:15]\n wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2);\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_ones_digit_T_1;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T_1 = _GEN_4;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T_11;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T_11 = _GEN_4;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r_1 = _io_out_c_r_T_3;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_15 = _io_out_c_T_14;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_19 = _io_out_c_T_18;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_20 = _io_out_c_T_19;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_21 = _io_out_c_T_20;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2;\t// @[PE.scala:113:37]\n wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0];\t// @[PE.scala:113:37]\n wire [7:0] _c2_T_1 = _c2_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [7:0] _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4;\t// @[PE.scala:121:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2};\t// @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]\n wire [7:0] _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6;\t// @[PE.scala:127:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8;\t// @[PE.scala:137:35]\n wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0];\t// @[PE.scala:137:35]\n always @(posedge clock) begin\t// @[PE.scala:31:7]\n if (io_in_valid_0 & io_in_control_propagate_0)\t// @[PE.scala:31:7, :102:95, :141:17, :142:8]\n c1 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :70:15]\n if (~(~io_in_valid_0 | io_in_control_propagate_0))\t// @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]\n c2 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :71:15]\n if (io_in_valid_0)\t// @[PE.scala:31:7]\n last_s <= io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25]\n always @(posedge)\n MacUnit_159 mac_unit (\t// @[PE.scala:64:24]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0),\t// @[PE.scala:31:7]\n .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3),\t// @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]\n .io_in_c (io_in_b_0),\t// @[PE.scala:31:7]\n .io_out_d (io_out_b_0)\n );\t// @[PE.scala:64:24]\n assign io_out_a = io_out_a_0;\t// @[PE.scala:31:7]\n assign io_out_b = io_out_b_0;\t// @[PE.scala:31:7]\n assign io_out_c = io_out_c_0;\t// @[PE.scala:31:7]\n assign io_out_control_dataflow = io_out_control_dataflow_0;\t// @[PE.scala:31:7]\n assign io_out_control_propagate = io_out_control_propagate_0;\t// @[PE.scala:31:7]\n assign io_out_control_shift = io_out_control_shift_0;\t// @[PE.scala:31:7]\n assign io_out_id = io_out_id_0;\t// @[PE.scala:31:7]\n assign io_out_last = io_out_last_0;\t// @[PE.scala:31:7]\n assign io_out_valid = io_out_valid_0;\t// @[PE.scala:31:7]\nendmodule"}}},{"rowIdx":32184,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_2 : \n input clock : Clock \n input reset : Reset \n output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} \n\n\n node default = gt(io.prv, UInt<1>(0h1)) \n wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect _pmp0_WIRE.mask, UInt<32>(0h0) \n connect _pmp0_WIRE.addr, UInt<30>(0h0) \n connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) \n connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) \n connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) \n connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) \n connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) \n connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) \n wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect pmp0, _pmp0_WIRE \n connect pmp0.cfg.r, default \n connect pmp0.cfg.w, default \n connect pmp0.cfg.x, default \n node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) \n node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) \n node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) \n node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) \n node _res_hit_msbMatch_T = shr(io.addr, 3) \n node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) \n node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) \n node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) \n node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) \n node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) \n node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) \n node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) \n node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) \n node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) \n node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) \n node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) \n node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) \n node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) \n node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) \n node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) \n node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) \n node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) \n node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) \n node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) \n node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) \n node _res_hit_T_5 = not(_res_hit_T_4) \n node _res_hit_msbsLess_T = shr(io.addr, 3) \n node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) \n node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) \n node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) \n node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) \n node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) \n node _res_hit_msbsEqual_T = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) \n node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) \n node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) \n node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) \n node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) \n node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) \n node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) \n node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) \n node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) \n node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) \n node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) \n node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) \n node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) \n node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_6 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) \n node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) \n node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) \n node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) \n node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) \n node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) \n node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) \n node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) \n node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) \n node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) \n node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) \n node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) \n node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) \n node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) \n node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) \n node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) \n node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) \n node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) \n node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) \n node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) \n node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) \n node res_ignore = and(default, _res_ignore_T) \n node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) \n node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) \n node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) \n node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) \n node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) \n node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) \n node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) \n node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) \n node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) \n node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) \n node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) \n node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) \n node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) \n node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) \n node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) \n node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) \n node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) \n node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) \n node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) \n node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) \n node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) \n node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) \n node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) \n node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) \n node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) \n node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) \n node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) \n node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) \n node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) \n node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) \n node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) \n node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) \n node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) \n node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) \n node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) \n node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) \n node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) \n node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) \n node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) \n node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) \n node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) \n node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) \n node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) \n node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) \n node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) \n node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) \n node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) \n node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) \n node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) \n node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) \n node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) \n node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) \n node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) \n node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) \n node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) \n node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) \n node _res_T_18 = and(_res_T_17, res_hit) \n node _res_T_19 = and(_res_T_18, res_aligned) \n node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) \n node _res_T_21 = and(_res_T_19, _res_T_20) \n node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) \n node _res_T_23 = and(_res_T_22, res_aligned) \n node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) \n node _res_T_25 = and(_res_T_23, _res_T_24) \n node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) \n node _res_T_27 = and(_res_T_26, res_hit) \n node _res_T_28 = and(_res_T_27, res_aligned) \n node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) \n node _res_T_30 = and(_res_T_28, _res_T_29) \n node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) \n node _res_T_32 = and(_res_T_31, res_aligned) \n node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) \n node _res_T_34 = and(_res_T_32, _res_T_33) \n node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) \n node _res_T_36 = and(_res_T_35, res_hit) \n node _res_T_37 = and(_res_T_36, res_aligned) \n node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) \n node _res_T_39 = and(_res_T_37, _res_T_38) \n node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) \n node _res_T_41 = and(_res_T_40, res_aligned) \n node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) \n node _res_T_43 = and(_res_T_41, _res_T_42) \n wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur, io.pmp[7] \n node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) \n node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) \n connect res_cur.cfg.r, _res_cur_cfg_r_T_1 \n node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) \n node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) \n connect res_cur.cfg.w, _res_cur_cfg_w_T_1 \n node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) \n node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) \n connect res_cur.cfg.x, _res_cur_cfg_x_T_1 \n node _res_T_44 = mux(res_hit, res_cur, pmp0) \n node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) \n node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) \n node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) \n node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) \n node _res_hit_msbMatch_T_10 = shr(io.addr, 3) \n node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) \n node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) \n node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) \n node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) \n node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) \n node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) \n node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) \n node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) \n node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) \n node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) \n node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) \n node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) \n node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) \n node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) \n node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) \n node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) \n node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) \n node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) \n node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) \n node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) \n node _res_hit_T_18 = not(_res_hit_T_17) \n node _res_hit_msbsLess_T_12 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) \n node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) \n node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) \n node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) \n node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) \n node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) \n node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) \n node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) \n node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) \n node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) \n node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) \n node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) \n node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) \n node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) \n node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) \n node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) \n node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) \n node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) \n node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_18 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) \n node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) \n node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) \n node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) \n node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) \n node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) \n node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) \n node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) \n node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) \n node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) \n node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) \n node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) \n node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) \n node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) \n node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) \n node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) \n node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) \n node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) \n node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) \n node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) \n node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) \n node res_ignore_1 = and(default, _res_ignore_T_1) \n node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) \n node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) \n node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) \n node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) \n node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) \n node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) \n node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) \n node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) \n node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) \n node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) \n node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) \n node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) \n node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) \n node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) \n node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) \n node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) \n node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) \n node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) \n node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) \n node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) \n node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) \n node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) \n node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) \n node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) \n node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) \n node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) \n node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) \n node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) \n node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) \n node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) \n node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) \n node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) \n node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) \n node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) \n node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) \n node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) \n node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) \n node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) \n node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) \n node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) \n node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) \n node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) \n node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) \n node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) \n node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) \n node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) \n node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) \n node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) \n node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) \n node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) \n node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) \n node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) \n node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) \n node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) \n node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) \n node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) \n node _res_T_63 = and(_res_T_62, res_hit_1) \n node _res_T_64 = and(_res_T_63, res_aligned_1) \n node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) \n node _res_T_66 = and(_res_T_64, _res_T_65) \n node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) \n node _res_T_68 = and(_res_T_67, res_aligned_1) \n node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) \n node _res_T_70 = and(_res_T_68, _res_T_69) \n node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) \n node _res_T_72 = and(_res_T_71, res_hit_1) \n node _res_T_73 = and(_res_T_72, res_aligned_1) \n node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) \n node _res_T_75 = and(_res_T_73, _res_T_74) \n node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) \n node _res_T_77 = and(_res_T_76, res_aligned_1) \n node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) \n node _res_T_79 = and(_res_T_77, _res_T_78) \n node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) \n node _res_T_81 = and(_res_T_80, res_hit_1) \n node _res_T_82 = and(_res_T_81, res_aligned_1) \n node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) \n node _res_T_84 = and(_res_T_82, _res_T_83) \n node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) \n node _res_T_86 = and(_res_T_85, res_aligned_1) \n node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) \n node _res_T_88 = and(_res_T_86, _res_T_87) \n wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur_1, io.pmp[6] \n node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) \n node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) \n connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 \n node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) \n node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) \n connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 \n node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) \n node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) \n connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 \n node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) \n node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) \n node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) \n node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) \n node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) \n node _res_hit_msbMatch_T_20 = shr(io.addr, 3) \n node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) \n node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) \n node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) \n node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) \n node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) \n node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) \n node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) \n node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) \n node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) \n node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) \n node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) \n node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) \n node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) \n node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) \n node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) \n node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) \n node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) \n node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) \n node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) \n node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) \n node _res_hit_T_31 = not(_res_hit_T_30) \n node _res_hit_msbsLess_T_24 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) \n node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) \n node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) \n node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) \n node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) \n node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) \n node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) \n node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) \n node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) \n node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) \n node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) \n node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) \n node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) \n node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) \n node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) \n node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) \n node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) \n node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) \n node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_30 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) \n node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) \n node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) \n node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) \n node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) \n node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) \n node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) \n node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) \n node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) \n node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) \n node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) \n node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) \n node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) \n node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) \n node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) \n node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) \n node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) \n node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) \n node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) \n node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) \n node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) \n node res_ignore_2 = and(default, _res_ignore_T_2) \n node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) \n node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) \n node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) \n node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) \n node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) \n node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) \n node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) \n node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) \n node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) \n node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) \n node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) \n node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) \n node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) \n node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) \n node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) \n node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) \n node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) \n node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) \n node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) \n node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) \n node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) \n node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) \n node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) \n node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) \n node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) \n node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) \n node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) \n node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) \n node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) \n node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) \n node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) \n node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) \n node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) \n node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) \n node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) \n node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) \n node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) \n node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) \n node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) \n node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) \n node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) \n node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) \n node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) \n node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) \n node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) \n node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) \n node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) \n node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) \n node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) \n node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) \n node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) \n node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) \n node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) \n node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) \n node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) \n node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) \n node _res_T_108 = and(_res_T_107, res_hit_2) \n node _res_T_109 = and(_res_T_108, res_aligned_2) \n node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) \n node _res_T_111 = and(_res_T_109, _res_T_110) \n node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) \n node _res_T_113 = and(_res_T_112, res_aligned_2) \n node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) \n node _res_T_115 = and(_res_T_113, _res_T_114) \n node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) \n node _res_T_117 = and(_res_T_116, res_hit_2) \n node _res_T_118 = and(_res_T_117, res_aligned_2) \n node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) \n node _res_T_120 = and(_res_T_118, _res_T_119) \n node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) \n node _res_T_122 = and(_res_T_121, res_aligned_2) \n node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) \n node _res_T_124 = and(_res_T_122, _res_T_123) \n node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) \n node _res_T_126 = and(_res_T_125, res_hit_2) \n node _res_T_127 = and(_res_T_126, res_aligned_2) \n node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) \n node _res_T_129 = and(_res_T_127, _res_T_128) \n node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) \n node _res_T_131 = and(_res_T_130, res_aligned_2) \n node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) \n node _res_T_133 = and(_res_T_131, _res_T_132) \n wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur_2, io.pmp[5] \n node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) \n node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) \n connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 \n node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) \n node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) \n connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 \n node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) \n node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) \n connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 \n node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) \n node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) \n node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) \n node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) \n node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) \n node _res_hit_msbMatch_T_30 = shr(io.addr, 3) \n node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) \n node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) \n node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) \n node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) \n node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) \n node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) \n node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) \n node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) \n node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) \n node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) \n node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) \n node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) \n node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) \n node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) \n node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) \n node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) \n node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) \n node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) \n node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) \n node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) \n node _res_hit_T_44 = not(_res_hit_T_43) \n node _res_hit_msbsLess_T_36 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) \n node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) \n node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) \n node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) \n node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) \n node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) \n node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) \n node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) \n node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) \n node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) \n node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) \n node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) \n node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) \n node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) \n node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) \n node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) \n node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) \n node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) \n node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_42 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) \n node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) \n node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) \n node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) \n node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) \n node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) \n node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) \n node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) \n node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) \n node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) \n node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) \n node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) \n node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) \n node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) \n node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) \n node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) \n node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) \n node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) \n node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) \n node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) \n node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) \n node res_ignore_3 = and(default, _res_ignore_T_3) \n node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) \n node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) \n node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) \n node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) \n node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) \n node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) \n node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) \n node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) \n node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) \n node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) \n node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) \n node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) \n node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) \n node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) \n node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) \n node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) \n node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) \n node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) \n node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) \n node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) \n node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) \n node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) \n node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) \n node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) \n node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) \n node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) \n node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) \n node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) \n node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) \n node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) \n node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) \n node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) \n node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) \n node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) \n node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) \n node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) \n node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) \n node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) \n node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) \n node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) \n node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) \n node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) \n node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) \n node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) \n node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) \n node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) \n node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) \n node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) \n node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) \n node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) \n node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) \n node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) \n node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) \n node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) \n node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) \n node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) \n node _res_T_153 = and(_res_T_152, res_hit_3) \n node _res_T_154 = and(_res_T_153, res_aligned_3) \n node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) \n node _res_T_156 = and(_res_T_154, _res_T_155) \n node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) \n node _res_T_158 = and(_res_T_157, res_aligned_3) \n node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) \n node _res_T_160 = and(_res_T_158, _res_T_159) \n node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) \n node _res_T_162 = and(_res_T_161, res_hit_3) \n node _res_T_163 = and(_res_T_162, res_aligned_3) \n node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) \n node _res_T_165 = and(_res_T_163, _res_T_164) \n node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) \n node _res_T_167 = and(_res_T_166, res_aligned_3) \n node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) \n node _res_T_169 = and(_res_T_167, _res_T_168) \n node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) \n node _res_T_171 = and(_res_T_170, res_hit_3) \n node _res_T_172 = and(_res_T_171, res_aligned_3) \n node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) \n node _res_T_174 = and(_res_T_172, _res_T_173) \n node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) \n node _res_T_176 = and(_res_T_175, res_aligned_3) \n node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) \n node _res_T_178 = and(_res_T_176, _res_T_177) \n wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur_3, io.pmp[4] \n node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) \n node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) \n connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 \n node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) \n node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) \n connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 \n node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) \n node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) \n connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 \n node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) \n node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) \n node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) \n node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) \n node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) \n node _res_hit_msbMatch_T_40 = shr(io.addr, 3) \n node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) \n node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) \n node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) \n node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) \n node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) \n node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) \n node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) \n node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) \n node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) \n node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) \n node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) \n node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) \n node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) \n node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) \n node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) \n node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) \n node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) \n node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) \n node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) \n node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) \n node _res_hit_T_57 = not(_res_hit_T_56) \n node _res_hit_msbsLess_T_48 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) \n node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) \n node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) \n node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) \n node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) \n node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) \n node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) \n node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) \n node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) \n node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) \n node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) \n node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) \n node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) \n node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) \n node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) \n node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) \n node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) \n node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) \n node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_54 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) \n node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) \n node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) \n node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) \n node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) \n node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) \n node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) \n node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) \n node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) \n node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) \n node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) \n node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) \n node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) \n node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) \n node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) \n node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) \n node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) \n node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) \n node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) \n node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) \n node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) \n node res_ignore_4 = and(default, _res_ignore_T_4) \n node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) \n node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) \n node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) \n node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) \n node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) \n node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) \n node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) \n node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) \n node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) \n node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) \n node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) \n node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) \n node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) \n node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) \n node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) \n node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) \n node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) \n node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) \n node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) \n node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) \n node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) \n node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) \n node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) \n node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) \n node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) \n node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) \n node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) \n node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) \n node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) \n node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) \n node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) \n node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) \n node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) \n node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) \n node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) \n node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) \n node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) \n node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) \n node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) \n node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) \n node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) \n node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) \n node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) \n node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) \n node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) \n node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) \n node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) \n node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) \n node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) \n node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) \n node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) \n node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) \n node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) \n node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) \n node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) \n node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) \n node _res_T_198 = and(_res_T_197, res_hit_4) \n node _res_T_199 = and(_res_T_198, res_aligned_4) \n node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) \n node _res_T_201 = and(_res_T_199, _res_T_200) \n node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) \n node _res_T_203 = and(_res_T_202, res_aligned_4) \n node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) \n node _res_T_205 = and(_res_T_203, _res_T_204) \n node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) \n node _res_T_207 = and(_res_T_206, res_hit_4) \n node _res_T_208 = and(_res_T_207, res_aligned_4) \n node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) \n node _res_T_210 = and(_res_T_208, _res_T_209) \n node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) \n node _res_T_212 = and(_res_T_211, res_aligned_4) \n node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) \n node _res_T_214 = and(_res_T_212, _res_T_213) \n node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) \n node _res_T_216 = and(_res_T_215, res_hit_4) \n node _res_T_217 = and(_res_T_216, res_aligned_4) \n node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) \n node _res_T_219 = and(_res_T_217, _res_T_218) \n node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) \n node _res_T_221 = and(_res_T_220, res_aligned_4) \n node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) \n node _res_T_223 = and(_res_T_221, _res_T_222) \n wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur_4, io.pmp[3] \n node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) \n node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) \n connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 \n node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) \n node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) \n connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 \n node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) \n node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) \n connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 \n node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) \n node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) \n node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) \n node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) \n node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) \n node _res_hit_msbMatch_T_50 = shr(io.addr, 3) \n node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) \n node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) \n node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) \n node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) \n node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) \n node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) \n node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) \n node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) \n node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) \n node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) \n node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) \n node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) \n node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) \n node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) \n node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) \n node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) \n node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) \n node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) \n node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) \n node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) \n node _res_hit_T_70 = not(_res_hit_T_69) \n node _res_hit_msbsLess_T_60 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) \n node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) \n node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) \n node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) \n node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) \n node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) \n node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) \n node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) \n node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) \n node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) \n node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) \n node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) \n node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) \n node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) \n node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) \n node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) \n node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) \n node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) \n node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_66 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) \n node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) \n node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) \n node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) \n node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) \n node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) \n node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) \n node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) \n node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) \n node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) \n node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) \n node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) \n node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) \n node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) \n node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) \n node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) \n node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) \n node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) \n node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) \n node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) \n node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) \n node res_ignore_5 = and(default, _res_ignore_T_5) \n node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) \n node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) \n node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) \n node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) \n node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) \n node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) \n node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) \n node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) \n node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) \n node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) \n node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) \n node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) \n node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) \n node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) \n node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) \n node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) \n node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) \n node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) \n node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) \n node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) \n node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) \n node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) \n node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) \n node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) \n node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) \n node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) \n node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) \n node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) \n node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) \n node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) \n node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) \n node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) \n node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) \n node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) \n node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) \n node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) \n node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) \n node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) \n node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) \n node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) \n node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) \n node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) \n node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) \n node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) \n node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) \n node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) \n node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) \n node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) \n node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) \n node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) \n node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) \n node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) \n node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) \n node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) \n node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) \n node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) \n node _res_T_243 = and(_res_T_242, res_hit_5) \n node _res_T_244 = and(_res_T_243, res_aligned_5) \n node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) \n node _res_T_246 = and(_res_T_244, _res_T_245) \n node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) \n node _res_T_248 = and(_res_T_247, res_aligned_5) \n node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) \n node _res_T_250 = and(_res_T_248, _res_T_249) \n node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) \n node _res_T_252 = and(_res_T_251, res_hit_5) \n node _res_T_253 = and(_res_T_252, res_aligned_5) \n node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) \n node _res_T_255 = and(_res_T_253, _res_T_254) \n node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) \n node _res_T_257 = and(_res_T_256, res_aligned_5) \n node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) \n node _res_T_259 = and(_res_T_257, _res_T_258) \n node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) \n node _res_T_261 = and(_res_T_260, res_hit_5) \n node _res_T_262 = and(_res_T_261, res_aligned_5) \n node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) \n node _res_T_264 = and(_res_T_262, _res_T_263) \n node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) \n node _res_T_266 = and(_res_T_265, res_aligned_5) \n node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) \n node _res_T_268 = and(_res_T_266, _res_T_267) \n wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur_5, io.pmp[2] \n node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) \n node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) \n connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 \n node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) \n node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) \n connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 \n node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) \n node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) \n connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 \n node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) \n node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) \n node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) \n node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) \n node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) \n node _res_hit_msbMatch_T_60 = shr(io.addr, 3) \n node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) \n node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) \n node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) \n node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) \n node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) \n node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) \n node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) \n node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) \n node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) \n node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) \n node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) \n node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) \n node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) \n node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) \n node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) \n node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) \n node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) \n node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) \n node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) \n node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) \n node _res_hit_T_83 = not(_res_hit_T_82) \n node _res_hit_msbsLess_T_72 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) \n node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) \n node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) \n node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) \n node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) \n node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) \n node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) \n node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) \n node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) \n node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) \n node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) \n node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) \n node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) \n node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) \n node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) \n node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) \n node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) \n node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) \n node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_78 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) \n node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) \n node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) \n node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) \n node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) \n node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) \n node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) \n node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) \n node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) \n node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) \n node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) \n node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) \n node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) \n node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) \n node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) \n node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) \n node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) \n node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) \n node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) \n node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) \n node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) \n node res_ignore_6 = and(default, _res_ignore_T_6) \n node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) \n node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) \n node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) \n node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) \n node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) \n node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) \n node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) \n node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) \n node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) \n node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) \n node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) \n node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) \n node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) \n node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) \n node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) \n node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) \n node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) \n node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) \n node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) \n node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) \n node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) \n node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) \n node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) \n node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) \n node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) \n node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) \n node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) \n node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) \n node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) \n node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) \n node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) \n node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) \n node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) \n node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) \n node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) \n node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) \n node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) \n node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) \n node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) \n node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) \n node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) \n node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) \n node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) \n node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) \n node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) \n node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) \n node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) \n node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) \n node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) \n node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) \n node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) \n node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) \n node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) \n node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) \n node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) \n node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) \n node _res_T_288 = and(_res_T_287, res_hit_6) \n node _res_T_289 = and(_res_T_288, res_aligned_6) \n node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) \n node _res_T_291 = and(_res_T_289, _res_T_290) \n node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) \n node _res_T_293 = and(_res_T_292, res_aligned_6) \n node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) \n node _res_T_295 = and(_res_T_293, _res_T_294) \n node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) \n node _res_T_297 = and(_res_T_296, res_hit_6) \n node _res_T_298 = and(_res_T_297, res_aligned_6) \n node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) \n node _res_T_300 = and(_res_T_298, _res_T_299) \n node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) \n node _res_T_302 = and(_res_T_301, res_aligned_6) \n node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) \n node _res_T_304 = and(_res_T_302, _res_T_303) \n node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) \n node _res_T_306 = and(_res_T_305, res_hit_6) \n node _res_T_307 = and(_res_T_306, res_aligned_6) \n node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) \n node _res_T_309 = and(_res_T_307, _res_T_308) \n node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) \n node _res_T_311 = and(_res_T_310, res_aligned_6) \n node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) \n node _res_T_313 = and(_res_T_311, _res_T_312) \n wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur_6, io.pmp[1] \n node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) \n node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) \n connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 \n node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) \n node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) \n connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 \n node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) \n node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) \n connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 \n node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) \n node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) \n node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) \n node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) \n node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) \n node _res_hit_msbMatch_T_70 = shr(io.addr, 3) \n node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) \n node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) \n node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) \n node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) \n node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) \n node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) \n node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) \n node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) \n node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) \n node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) \n node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) \n node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) \n node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) \n node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) \n node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) \n node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) \n node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) \n node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) \n node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) \n node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) \n node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) \n node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) \n node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) \n node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) \n node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) \n node _res_hit_T_96 = not(_res_hit_T_95) \n node _res_hit_msbsLess_T_84 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) \n node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) \n node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) \n node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) \n node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) \n node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) \n node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) \n node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) \n node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) \n node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) \n node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) \n node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) \n node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) \n node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) \n node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) \n node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) \n node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) \n node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) \n node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) \n node _res_hit_msbsLess_T_90 = shr(io.addr, 3) \n node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) \n node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) \n node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) \n node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) \n node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) \n node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) \n node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) \n node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) \n node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) \n node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) \n node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) \n node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) \n node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) \n node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) \n node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) \n node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) \n node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) \n node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) \n node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) \n node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) \n node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) \n node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) \n node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) \n node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) \n node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) \n node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) \n node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) \n node res_ignore_7 = and(default, _res_ignore_T_7) \n node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) \n node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) \n node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) \n node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) \n node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) \n node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) \n node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) \n node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) \n node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) \n node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) \n node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) \n node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) \n node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) \n node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) \n node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) \n node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) \n node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) \n node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) \n node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) \n node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) \n node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) \n node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) \n node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) \n node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) \n node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) \n node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) \n node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) \n node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) \n node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) \n node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) \n node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) \n node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) \n node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) \n node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) \n node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) \n node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) \n node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) \n node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) \n node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) \n node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) \n node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) \n node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) \n node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) \n node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) \n node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) \n node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) \n node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) \n node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) \n node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) \n node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) \n node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) \n node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) \n node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) \n node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) \n node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) \n node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) \n node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) \n node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) \n node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) \n node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) \n node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) \n node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) \n node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) \n node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) \n node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) \n node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) \n node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) \n node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) \n node _res_T_333 = and(_res_T_332, res_hit_7) \n node _res_T_334 = and(_res_T_333, res_aligned_7) \n node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) \n node _res_T_336 = and(_res_T_334, _res_T_335) \n node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) \n node _res_T_338 = and(_res_T_337, res_aligned_7) \n node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) \n node _res_T_340 = and(_res_T_338, _res_T_339) \n node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) \n node _res_T_342 = and(_res_T_341, res_hit_7) \n node _res_T_343 = and(_res_T_342, res_aligned_7) \n node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) \n node _res_T_345 = and(_res_T_343, _res_T_344) \n node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) \n node _res_T_347 = and(_res_T_346, res_aligned_7) \n node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) \n node _res_T_349 = and(_res_T_347, _res_T_348) \n node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) \n node _res_T_351 = and(_res_T_350, res_hit_7) \n node _res_T_352 = and(_res_T_351, res_aligned_7) \n node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) \n node _res_T_354 = and(_res_T_352, _res_T_353) \n node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) \n node _res_T_356 = and(_res_T_355, res_aligned_7) \n node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) \n node _res_T_358 = and(_res_T_356, _res_T_357) \n wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} \n connect res_cur_7, io.pmp[0] \n node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) \n node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) \n connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 \n node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) \n node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) \n connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 \n node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) \n node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) \n connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 \n node res = mux(res_hit_7, res_cur_7, _res_T_314) \n connect io.r, res.cfg.r \n connect io.w, res.cfg.w \n connect io.x, res.cfg.x"},"response":{"kind":"string","value":"module PMPChecker_s3_2(\t// @[PMP.scala:143:7]\n input clock,\t// @[PMP.scala:143:7]\n input reset,\t// @[PMP.scala:143:7]\n input [1:0] io_prv,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_0_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_0_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_0_mask,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_1_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_1_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_1_mask,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_2_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_2_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_2_mask,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_3_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_3_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_3_mask,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_4_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_4_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_4_mask,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_5_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_5_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_5_mask,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_6_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_6_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_6_mask,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_7_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_7_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_7_mask,\t// @[PMP.scala:146:14]\n input [31:0] io_addr,\t// @[PMP.scala:146:14]\n input [1:0] io_size,\t// @[PMP.scala:146:14]\n output io_r,\t// @[PMP.scala:146:14]\n output io_w,\t// @[PMP.scala:146:14]\n output io_x\t// @[PMP.scala:146:14]\n);\n\n wire [1:0] io_prv_0 = io_prv;\t// @[PMP.scala:143:7]\n wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask;\t// @[PMP.scala:143:7]\n wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask;\t// @[PMP.scala:143:7]\n wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask;\t// @[PMP.scala:143:7]\n wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask;\t// @[PMP.scala:143:7]\n wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask;\t// @[PMP.scala:143:7]\n wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask;\t// @[PMP.scala:143:7]\n wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask;\t// @[PMP.scala:143:7]\n wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a;\t// @[PMP.scala:143:7]\n wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x;\t// @[PMP.scala:143:7]\n wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w;\t// @[PMP.scala:143:7]\n wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r;\t// @[PMP.scala:143:7]\n wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr;\t// @[PMP.scala:143:7]\n wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask;\t// @[PMP.scala:143:7]\n wire [31:0] io_addr_0 = io_addr;\t// @[PMP.scala:143:7]\n wire [1:0] io_size_0 = io_size;\t// @[PMP.scala:143:7]\n wire [29:0] _pmp0_WIRE_addr = 30'h0;\t// @[PMP.scala:157:35]\n wire [29:0] pmp0_addr = 30'h0;\t// @[PMP.scala:157:22]\n wire _res_hit_T_99 = 1'h1;\t// @[PMP.scala:88:5]\n wire [28:0] _res_hit_msbsLess_T_89 = 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67]\n wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67]\n wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF;\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _pmp0_WIRE_mask = 32'h0;\t// @[PMP.scala:157:35]\n wire [31:0] pmp0_mask = 32'h0;\t// @[PMP.scala:157:22]\n wire [31:0] _res_hit_msbsLess_T_85 = 32'h0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_88 = 32'h0;\t// @[PMP.scala:60:27]\n wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0;\t// @[PMP.scala:60:27]\n wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0;\t// @[PMP.scala:60:27]\n wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0;\t// @[PMP.scala:60:27]\n wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0;\t// @[PMP.scala:60:27]\n wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}]\n wire _pmp0_WIRE_cfg_l = 1'h0;\t// @[PMP.scala:157:35]\n wire _pmp0_WIRE_cfg_x = 1'h0;\t// @[PMP.scala:157:35]\n wire _pmp0_WIRE_cfg_w = 1'h0;\t// @[PMP.scala:157:35]\n wire _pmp0_WIRE_cfg_r = 1'h0;\t// @[PMP.scala:157:35]\n wire pmp0_cfg_l = 1'h0;\t// @[PMP.scala:157:22]\n wire res_hit_msbsLess_14 = 1'h0;\t// @[PMP.scala:80:39]\n wire res_hit_lsbsLess_14 = 1'h0;\t// @[PMP.scala:82:53]\n wire _res_hit_T_97 = 1'h0;\t// @[PMP.scala:83:30]\n wire _res_hit_T_98 = 1'h0;\t// @[PMP.scala:83:16]\n wire _res_aligned_straddlesLowerBound_T_135 = 1'h0;\t// @[PMP.scala:123:147]\n wire res_aligned_straddlesLowerBound_7 = 1'h0;\t// @[PMP.scala:123:90]\n wire [1:0] io_pmp_0_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_1_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_2_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_3_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_4_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_5_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_6_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] io_pmp_7_cfg_res = 2'h0;\t// @[PMP.scala:143:7]\n wire [1:0] _pmp0_WIRE_cfg_res = 2'h0;\t// @[PMP.scala:157:35]\n wire [1:0] _pmp0_WIRE_cfg_a = 2'h0;\t// @[PMP.scala:157:35]\n wire [1:0] pmp0_cfg_res = 2'h0;\t// @[PMP.scala:157:22]\n wire [1:0] pmp0_cfg_a = 2'h0;\t// @[PMP.scala:157:22]\n wire [1:0] res_cur_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] _res_T_44_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire [1:0] res_cur_1_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] _res_T_89_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire [1:0] res_cur_2_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] _res_T_134_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire [1:0] res_cur_3_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] _res_T_179_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire [1:0] res_cur_4_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] _res_T_224_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire [1:0] res_cur_5_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] _res_T_269_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire [1:0] res_cur_6_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] _res_T_314_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire [1:0] res_cur_7_cfg_res = 2'h0;\t// @[PMP.scala:181:23]\n wire [1:0] res_cfg_res = 2'h0;\t// @[PMP.scala:185:8]\n wire _res_T_319 = io_pmp_0_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_7_addr = io_pmp_0_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_7_mask = io_pmp_0_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire _res_T_274 = io_pmp_1_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_6_addr = io_pmp_1_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_6_mask = io_pmp_1_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire _res_T_229 = io_pmp_2_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_5_addr = io_pmp_2_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_5_mask = io_pmp_2_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire _res_T_184 = io_pmp_3_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_4_addr = io_pmp_3_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_4_mask = io_pmp_3_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire _res_T_139 = io_pmp_4_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_3_addr = io_pmp_4_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_3_mask = io_pmp_4_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire _res_T_94 = io_pmp_5_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_2_addr = io_pmp_5_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_2_mask = io_pmp_5_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire _res_T_49 = io_pmp_6_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_1_addr = io_pmp_6_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_1_mask = io_pmp_6_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire _res_T_4 = io_pmp_7_cfg_l_0;\t// @[PMP.scala:143:7, :170:30]\n wire res_cur_cfg_l = io_pmp_7_cfg_l_0;\t// @[PMP.scala:143:7, :181:23]\n wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0;\t// @[PMP.scala:143:7, :181:23]\n wire [29:0] res_cur_addr = io_pmp_7_addr_0;\t// @[PMP.scala:143:7, :181:23]\n wire [31:0] res_cur_mask = io_pmp_7_mask_0;\t// @[PMP.scala:143:7, :181:23]\n wire res_cfg_r;\t// @[PMP.scala:185:8]\n wire res_cfg_w;\t// @[PMP.scala:185:8]\n wire res_cfg_x;\t// @[PMP.scala:185:8]\n wire io_r_0;\t// @[PMP.scala:143:7]\n wire io_w_0;\t// @[PMP.scala:143:7]\n wire io_x_0;\t// @[PMP.scala:143:7]\n wire default_0 = io_prv_0[1];\t// @[PMP.scala:143:7, :156:56]\n wire pmp0_cfg_x = default_0;\t// @[PMP.scala:156:56, :157:22]\n wire pmp0_cfg_w = default_0;\t// @[PMP.scala:156:56, :157:22]\n wire pmp0_cfg_r = default_0;\t// @[PMP.scala:156:56, :157:22]\n wire _res_hit_T = io_pmp_7_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T = io_pmp_7_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [5:0] _GEN = 6'h7 << io_size_0;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_3;\t// @[package.scala:243:71]\n assign _res_hit_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T_3;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_16;\t// @[package.scala:243:71]\n assign _res_hit_T_16 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T_2;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T_2 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T_6;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T_6 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_29;\t// @[package.scala:243:71]\n assign _res_hit_T_29 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T_4;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T_4 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T_9;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T_9 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_42;\t// @[package.scala:243:71]\n assign _res_hit_T_42 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T_6;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T_6 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T_12;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T_12 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_55;\t// @[package.scala:243:71]\n assign _res_hit_T_55 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T_8;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T_8 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T_15;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T_15 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_68;\t// @[package.scala:243:71]\n assign _res_hit_T_68 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T_10;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T_10 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T_18;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T_18 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_81;\t// @[package.scala:243:71]\n assign _res_hit_T_81 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T_12;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T_12 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_lsbMask_T_21;\t// @[package.scala:243:71]\n assign _res_hit_lsbMask_T_21 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_hit_T_94;\t// @[package.scala:243:71]\n assign _res_hit_T_94 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _res_aligned_lsbMask_T_14;\t// @[package.scala:243:71]\n assign _res_aligned_lsbMask_T_14 = _GEN;\t// @[package.scala:243:71]\n wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2};\t// @[package.scala:243:46]\n wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :143:7]\n wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :80:25, :143:7]\n wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :81:27, :143:7]\n wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :123:35, :143:7]\n wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3];\t// @[PMP.scala:69:29, :124:35, :143:7]\n wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbMatch_T_1;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_1 = _GEN_0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_1;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_1 = _GEN_0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_7;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_7 = _GEN_0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_8;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_8 = _GEN_0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_9;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_9 = _GEN_0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_1;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_8;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :82:25, :143:7]\n wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :123:129, :143:7]\n wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0];\t// @[PMP.scala:70:28, :124:119, :143:7]\n wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_5 = ~_res_hit_T_4;\t// @[package.scala:243:{46,76}]\n wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbsLess_T_1;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_1 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_1;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_1 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_2;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_2 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_1;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_8;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_11;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_11 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_11;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_11 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_19;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_19 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_22;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_22 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_23;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_23 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_18;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_25;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_8 = ~_res_hit_T_7;\t// @[PMP.scala:83:16, :88:5]\n wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10;\t// @[PMP.scala:83:16, :88:5, :94:48]\n wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T = ~io_pmp_7_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore = default_0 & _res_ignore_T;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3];\t// @[PMP.scala:60:27, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5;\t// @[PMP.scala:123:{35,49,67}]\n wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0];\t// @[PMP.scala:60:27, :123:108]\n wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13;\t// @[PMP.scala:123:{127,129}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14;\t// @[PMP.scala:123:{108,125,127}]\n wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15;\t// @[PMP.scala:123:{125,147}]\n wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16;\t// @[PMP.scala:123:{82,90,147}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound;\t// @[PMP.scala:123:90, :124:85, :125:46]\n wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T = io_pmp_7_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_1;\t// @[PMP.scala:168:32]\n assign _res_T_1 = _GEN_2;\t// @[PMP.scala:168:32]\n wire _res_T_20;\t// @[PMP.scala:177:61]\n assign _res_T_20 = _GEN_2;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_24;\t// @[PMP.scala:178:63]\n assign _res_T_24 = _GEN_2;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_2;\t// @[PMP.scala:168:32]\n assign _res_T_2 = _GEN_3;\t// @[PMP.scala:168:32]\n wire _res_T_29;\t// @[PMP.scala:177:61]\n assign _res_T_29 = _GEN_3;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_33;\t// @[PMP.scala:178:63]\n assign _res_T_33 = _GEN_3;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_3 = &io_pmp_7_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi;\t// @[PMP.scala:174:26]\n assign res_hi = _GEN_4;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_1;\t// @[PMP.scala:174:26]\n assign res_hi_1 = _GEN_4;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_2;\t// @[PMP.scala:174:26]\n assign res_hi_2 = _GEN_4;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_3;\t// @[PMP.scala:174:26]\n assign res_hi_3 = _GEN_4;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_4;\t// @[PMP.scala:174:26]\n assign res_hi_4 = _GEN_4;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_5;\t// @[PMP.scala:174:26]\n assign res_hi_5 = _GEN_4;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_6 = _res_T_5 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_8 = _res_T_7 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_10 = _res_T_9 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_12 = _res_T_11 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_14 = _res_T_13 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_16 = &_res_T_15;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_17 = ~res_ignore;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_18 = _res_T_17 & res_hit;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_19 = _res_T_18 & res_aligned;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_21 = _res_T_19 & _res_T_20;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_22;\t// @[PMP.scala:178:32]\n assign _res_T_22 = _GEN_5;\t// @[PMP.scala:178:32]\n wire _res_T_31;\t// @[PMP.scala:178:32]\n assign _res_T_31 = _GEN_5;\t// @[PMP.scala:178:32]\n wire _res_T_40;\t// @[PMP.scala:178:32]\n assign _res_T_40 = _GEN_5;\t// @[PMP.scala:178:32]\n wire _res_T_23 = _res_T_22 & res_aligned;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_25 = _res_T_23 & _res_T_24;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_26 = ~res_ignore;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_27 = _res_T_26 & res_hit;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_28 = _res_T_27 & res_aligned;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_30 = _res_T_28 & _res_T_29;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_32 = _res_T_31 & res_aligned;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_34 = _res_T_32 & _res_T_33;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_35 = ~res_ignore;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_36 = _res_T_35 & res_hit;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_37 = _res_T_36 & res_aligned;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_38 = &io_pmp_7_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_39 = _res_T_37 & _res_T_38;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_41 = _res_T_40 & res_aligned;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_42 = &io_pmp_7_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_43 = _res_T_41 & _res_T_42;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_1;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_1;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_1;\t// @[PMP.scala:182:26]\n wire res_cur_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_cfg_r = _res_cur_cfg_r_T_1;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_cfg_w = _res_cur_cfg_w_T_1;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_cfg_x = _res_cur_cfg_x_T_1;\t// @[PMP.scala:181:23, :184:26]\n wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x;\t// @[PMP.scala:132:8, :157:22, :181:23, :185:8]\n wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w;\t// @[PMP.scala:132:8, :157:22, :181:23, :185:8]\n wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r;\t// @[PMP.scala:132:8, :157:22, :181:23, :185:8]\n wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5};\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_18 = ~_res_hit_T_17;\t// @[package.scala:243:{46,76}]\n wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbsLess_T_13;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_13 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_15;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_15 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_16;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_16 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_18;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_25;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_21;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_21 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_21;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_21 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_31;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_31 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_36;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_36 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_37;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_37 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_35;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_42;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_21 = ~_res_hit_T_20;\t// @[PMP.scala:83:16, :88:5]\n wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23;\t// @[PMP.scala:83:16, :88:5, :94:48]\n wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore_1 = default_0 & _res_ignore_T_1;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3;\t// @[package.scala:243:{46,76}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3];\t// @[PMP.scala:60:27, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22;\t// @[PMP.scala:123:{35,49,67}]\n wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0];\t// @[PMP.scala:60:27, :123:108]\n wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30;\t// @[PMP.scala:123:{127,129}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31;\t// @[PMP.scala:123:{108,125,127}]\n wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32;\t// @[PMP.scala:123:{125,147}]\n wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33;\t// @[PMP.scala:123:{82,90,147}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1;\t// @[PMP.scala:123:90, :124:85, :125:46]\n wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_46;\t// @[PMP.scala:168:32]\n assign _res_T_46 = _GEN_7;\t// @[PMP.scala:168:32]\n wire _res_T_65;\t// @[PMP.scala:177:61]\n assign _res_T_65 = _GEN_7;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_69;\t// @[PMP.scala:178:63]\n assign _res_T_69 = _GEN_7;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_47;\t// @[PMP.scala:168:32]\n assign _res_T_47 = _GEN_8;\t// @[PMP.scala:168:32]\n wire _res_T_74;\t// @[PMP.scala:177:61]\n assign _res_T_74 = _GEN_8;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_78;\t// @[PMP.scala:178:63]\n assign _res_T_78 = _GEN_8;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_48 = &io_pmp_6_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi_6;\t// @[PMP.scala:174:26]\n assign res_hi_6 = _GEN_9;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_7;\t// @[PMP.scala:174:26]\n assign res_hi_7 = _GEN_9;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_8;\t// @[PMP.scala:174:26]\n assign res_hi_8 = _GEN_9;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_9;\t// @[PMP.scala:174:26]\n assign res_hi_9 = _GEN_9;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_10;\t// @[PMP.scala:174:26]\n assign res_hi_10 = _GEN_9;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_11;\t// @[PMP.scala:174:26]\n assign res_hi_11 = _GEN_9;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_51 = _res_T_50 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_53 = _res_T_52 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_55 = _res_T_54 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_57 = _res_T_56 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_59 = _res_T_58 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_61 = &_res_T_60;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_62 = ~res_ignore_1;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_63 = _res_T_62 & res_hit_1;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_64 = _res_T_63 & res_aligned_1;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_66 = _res_T_64 & _res_T_65;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_67;\t// @[PMP.scala:178:32]\n assign _res_T_67 = _GEN_10;\t// @[PMP.scala:178:32]\n wire _res_T_76;\t// @[PMP.scala:178:32]\n assign _res_T_76 = _GEN_10;\t// @[PMP.scala:178:32]\n wire _res_T_85;\t// @[PMP.scala:178:32]\n assign _res_T_85 = _GEN_10;\t// @[PMP.scala:178:32]\n wire _res_T_68 = _res_T_67 & res_aligned_1;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_70 = _res_T_68 & _res_T_69;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_71 = ~res_ignore_1;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_72 = _res_T_71 & res_hit_1;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_73 = _res_T_72 & res_aligned_1;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_75 = _res_T_73 & _res_T_74;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_77 = _res_T_76 & res_aligned_1;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_79 = _res_T_77 & _res_T_78;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_80 = ~res_ignore_1;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_81 = _res_T_80 & res_hit_1;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_82 = _res_T_81 & res_aligned_1;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_83 = &io_pmp_6_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_84 = _res_T_82 & _res_T_83;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_86 = _res_T_85 & res_aligned_1;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_87 = &io_pmp_6_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_88 = _res_T_86 & _res_T_87;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_3;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_3;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_3;\t// @[PMP.scala:182:26]\n wire res_cur_1_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_1_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_1_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3;\t// @[PMP.scala:181:23, :184:26]\n wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8};\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_31 = ~_res_hit_T_30;\t// @[package.scala:243:{46,76}]\n wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbsLess_T_25;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_25 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_29;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_29 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_30;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_30 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_35;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_42;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_31;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_31 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_31;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_31 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_43;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_43 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_50;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_50 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_51;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_51 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_52;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_59;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_34 = ~_res_hit_T_33;\t// @[PMP.scala:83:16, :88:5]\n wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36;\t// @[PMP.scala:83:16, :88:5, :94:48]\n wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore_2 = default_0 & _res_ignore_T_2;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5;\t// @[package.scala:243:{46,76}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3];\t// @[PMP.scala:60:27, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39;\t// @[PMP.scala:123:{35,49,67}]\n wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0];\t// @[PMP.scala:60:27, :123:108]\n wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47;\t// @[PMP.scala:123:{127,129}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48;\t// @[PMP.scala:123:{108,125,127}]\n wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49;\t// @[PMP.scala:123:{125,147}]\n wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50;\t// @[PMP.scala:123:{82,90,147}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2;\t// @[PMP.scala:123:90, :124:85, :125:46]\n wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_91;\t// @[PMP.scala:168:32]\n assign _res_T_91 = _GEN_12;\t// @[PMP.scala:168:32]\n wire _res_T_110;\t// @[PMP.scala:177:61]\n assign _res_T_110 = _GEN_12;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_114;\t// @[PMP.scala:178:63]\n assign _res_T_114 = _GEN_12;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_92;\t// @[PMP.scala:168:32]\n assign _res_T_92 = _GEN_13;\t// @[PMP.scala:168:32]\n wire _res_T_119;\t// @[PMP.scala:177:61]\n assign _res_T_119 = _GEN_13;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_123;\t// @[PMP.scala:178:63]\n assign _res_T_123 = _GEN_13;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_93 = &io_pmp_5_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi_12;\t// @[PMP.scala:174:26]\n assign res_hi_12 = _GEN_14;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_13;\t// @[PMP.scala:174:26]\n assign res_hi_13 = _GEN_14;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_14;\t// @[PMP.scala:174:26]\n assign res_hi_14 = _GEN_14;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_15;\t// @[PMP.scala:174:26]\n assign res_hi_15 = _GEN_14;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_16;\t// @[PMP.scala:174:26]\n assign res_hi_16 = _GEN_14;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_17;\t// @[PMP.scala:174:26]\n assign res_hi_17 = _GEN_14;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_96 = _res_T_95 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_98 = _res_T_97 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_100 = _res_T_99 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_102 = _res_T_101 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_104 = _res_T_103 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_106 = &_res_T_105;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_107 = ~res_ignore_2;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_108 = _res_T_107 & res_hit_2;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_109 = _res_T_108 & res_aligned_2;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_111 = _res_T_109 & _res_T_110;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_112;\t// @[PMP.scala:178:32]\n assign _res_T_112 = _GEN_15;\t// @[PMP.scala:178:32]\n wire _res_T_121;\t// @[PMP.scala:178:32]\n assign _res_T_121 = _GEN_15;\t// @[PMP.scala:178:32]\n wire _res_T_130;\t// @[PMP.scala:178:32]\n assign _res_T_130 = _GEN_15;\t// @[PMP.scala:178:32]\n wire _res_T_113 = _res_T_112 & res_aligned_2;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_115 = _res_T_113 & _res_T_114;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_116 = ~res_ignore_2;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_117 = _res_T_116 & res_hit_2;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_118 = _res_T_117 & res_aligned_2;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_120 = _res_T_118 & _res_T_119;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_122 = _res_T_121 & res_aligned_2;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_124 = _res_T_122 & _res_T_123;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_125 = ~res_ignore_2;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_126 = _res_T_125 & res_hit_2;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_127 = _res_T_126 & res_aligned_2;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_128 = &io_pmp_5_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_129 = _res_T_127 & _res_T_128;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_131 = _res_T_130 & res_aligned_2;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_132 = &io_pmp_5_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_133 = _res_T_131 & _res_T_132;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_5;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_5;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_5;\t// @[PMP.scala:182:26]\n wire res_cur_2_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_2_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_2_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5;\t// @[PMP.scala:181:23, :184:26]\n wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11};\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_44 = ~_res_hit_T_43;\t// @[package.scala:243:{46,76}]\n wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbsLess_T_37;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_37 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_43;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_43 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_44;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_44 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_52;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_59;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_41;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_41 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_41;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_41 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_55;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_55 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_64;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_64 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_65;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_65 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_69;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_76;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_47 = ~_res_hit_T_46;\t// @[PMP.scala:83:16, :88:5]\n wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49;\t// @[PMP.scala:83:16, :88:5, :94:48]\n wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore_3 = default_0 & _res_ignore_T_3;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7;\t// @[package.scala:243:{46,76}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3];\t// @[PMP.scala:60:27, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56;\t// @[PMP.scala:123:{35,49,67}]\n wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0];\t// @[PMP.scala:60:27, :123:108]\n wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64;\t// @[PMP.scala:123:{127,129}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65;\t// @[PMP.scala:123:{108,125,127}]\n wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66;\t// @[PMP.scala:123:{125,147}]\n wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67;\t// @[PMP.scala:123:{82,90,147}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3;\t// @[PMP.scala:123:90, :124:85, :125:46]\n wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_136;\t// @[PMP.scala:168:32]\n assign _res_T_136 = _GEN_17;\t// @[PMP.scala:168:32]\n wire _res_T_155;\t// @[PMP.scala:177:61]\n assign _res_T_155 = _GEN_17;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_159;\t// @[PMP.scala:178:63]\n assign _res_T_159 = _GEN_17;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_137;\t// @[PMP.scala:168:32]\n assign _res_T_137 = _GEN_18;\t// @[PMP.scala:168:32]\n wire _res_T_164;\t// @[PMP.scala:177:61]\n assign _res_T_164 = _GEN_18;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_168;\t// @[PMP.scala:178:63]\n assign _res_T_168 = _GEN_18;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_138 = &io_pmp_4_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi_18;\t// @[PMP.scala:174:26]\n assign res_hi_18 = _GEN_19;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_19;\t// @[PMP.scala:174:26]\n assign res_hi_19 = _GEN_19;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_20;\t// @[PMP.scala:174:26]\n assign res_hi_20 = _GEN_19;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_21;\t// @[PMP.scala:174:26]\n assign res_hi_21 = _GEN_19;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_22;\t// @[PMP.scala:174:26]\n assign res_hi_22 = _GEN_19;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_23;\t// @[PMP.scala:174:26]\n assign res_hi_23 = _GEN_19;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_141 = _res_T_140 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_143 = _res_T_142 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_145 = _res_T_144 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_147 = _res_T_146 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_149 = _res_T_148 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_151 = &_res_T_150;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_152 = ~res_ignore_3;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_153 = _res_T_152 & res_hit_3;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_154 = _res_T_153 & res_aligned_3;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_156 = _res_T_154 & _res_T_155;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_157;\t// @[PMP.scala:178:32]\n assign _res_T_157 = _GEN_20;\t// @[PMP.scala:178:32]\n wire _res_T_166;\t// @[PMP.scala:178:32]\n assign _res_T_166 = _GEN_20;\t// @[PMP.scala:178:32]\n wire _res_T_175;\t// @[PMP.scala:178:32]\n assign _res_T_175 = _GEN_20;\t// @[PMP.scala:178:32]\n wire _res_T_158 = _res_T_157 & res_aligned_3;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_160 = _res_T_158 & _res_T_159;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_161 = ~res_ignore_3;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_162 = _res_T_161 & res_hit_3;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_163 = _res_T_162 & res_aligned_3;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_165 = _res_T_163 & _res_T_164;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_167 = _res_T_166 & res_aligned_3;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_169 = _res_T_167 & _res_T_168;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_170 = ~res_ignore_3;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_171 = _res_T_170 & res_hit_3;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_172 = _res_T_171 & res_aligned_3;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_173 = &io_pmp_4_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_174 = _res_T_172 & _res_T_173;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_176 = _res_T_175 & res_aligned_3;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_177 = &io_pmp_4_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_178 = _res_T_176 & _res_T_177;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_7;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_7;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_7;\t// @[PMP.scala:182:26]\n wire res_cur_3_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_3_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_3_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7;\t// @[PMP.scala:181:23, :184:26]\n wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14};\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_57 = ~_res_hit_T_56;\t// @[package.scala:243:{46,76}]\n wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbsLess_T_49;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_49 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_57;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_57 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_58;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_58 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_69;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_76;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_51;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_51 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_51;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_51 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_67;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_67 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_78;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_78 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_79;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_79 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_86;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_93;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_60 = ~_res_hit_T_59;\t// @[PMP.scala:83:16, :88:5]\n wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62;\t// @[PMP.scala:83:16, :88:5, :94:48]\n wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore_4 = default_0 & _res_ignore_T_4;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9;\t// @[package.scala:243:{46,76}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3];\t// @[PMP.scala:60:27, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73;\t// @[PMP.scala:123:{35,49,67}]\n wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0];\t// @[PMP.scala:60:27, :123:108]\n wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81;\t// @[PMP.scala:123:{127,129}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82;\t// @[PMP.scala:123:{108,125,127}]\n wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83;\t// @[PMP.scala:123:{125,147}]\n wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84;\t// @[PMP.scala:123:{82,90,147}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4;\t// @[PMP.scala:123:90, :124:85, :125:46]\n wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_181;\t// @[PMP.scala:168:32]\n assign _res_T_181 = _GEN_22;\t// @[PMP.scala:168:32]\n wire _res_T_200;\t// @[PMP.scala:177:61]\n assign _res_T_200 = _GEN_22;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_204;\t// @[PMP.scala:178:63]\n assign _res_T_204 = _GEN_22;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_182;\t// @[PMP.scala:168:32]\n assign _res_T_182 = _GEN_23;\t// @[PMP.scala:168:32]\n wire _res_T_209;\t// @[PMP.scala:177:61]\n assign _res_T_209 = _GEN_23;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_213;\t// @[PMP.scala:178:63]\n assign _res_T_213 = _GEN_23;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_183 = &io_pmp_3_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi_24;\t// @[PMP.scala:174:26]\n assign res_hi_24 = _GEN_24;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_25;\t// @[PMP.scala:174:26]\n assign res_hi_25 = _GEN_24;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_26;\t// @[PMP.scala:174:26]\n assign res_hi_26 = _GEN_24;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_27;\t// @[PMP.scala:174:26]\n assign res_hi_27 = _GEN_24;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_28;\t// @[PMP.scala:174:26]\n assign res_hi_28 = _GEN_24;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_29;\t// @[PMP.scala:174:26]\n assign res_hi_29 = _GEN_24;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_186 = _res_T_185 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_188 = _res_T_187 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_190 = _res_T_189 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_192 = _res_T_191 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_194 = _res_T_193 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_196 = &_res_T_195;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_197 = ~res_ignore_4;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_198 = _res_T_197 & res_hit_4;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_199 = _res_T_198 & res_aligned_4;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_201 = _res_T_199 & _res_T_200;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_202;\t// @[PMP.scala:178:32]\n assign _res_T_202 = _GEN_25;\t// @[PMP.scala:178:32]\n wire _res_T_211;\t// @[PMP.scala:178:32]\n assign _res_T_211 = _GEN_25;\t// @[PMP.scala:178:32]\n wire _res_T_220;\t// @[PMP.scala:178:32]\n assign _res_T_220 = _GEN_25;\t// @[PMP.scala:178:32]\n wire _res_T_203 = _res_T_202 & res_aligned_4;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_205 = _res_T_203 & _res_T_204;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_206 = ~res_ignore_4;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_207 = _res_T_206 & res_hit_4;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_208 = _res_T_207 & res_aligned_4;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_210 = _res_T_208 & _res_T_209;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_212 = _res_T_211 & res_aligned_4;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_214 = _res_T_212 & _res_T_213;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_215 = ~res_ignore_4;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_216 = _res_T_215 & res_hit_4;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_217 = _res_T_216 & res_aligned_4;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_218 = &io_pmp_3_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_219 = _res_T_217 & _res_T_218;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_221 = _res_T_220 & res_aligned_4;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_222 = &io_pmp_3_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_223 = _res_T_221 & _res_T_222;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_9;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_9;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_9;\t// @[PMP.scala:182:26]\n wire res_cur_4_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_4_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_4_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9;\t// @[PMP.scala:181:23, :184:26]\n wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17};\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_70 = ~_res_hit_T_69;\t// @[package.scala:243:{46,76}]\n wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbsLess_T_61;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_61 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_71;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_71 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_72;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_72 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_86;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_93;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_61;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_61 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_61;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_61 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_79;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_79 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_92;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_92 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_93;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_93 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_103;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_110;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_73 = ~_res_hit_T_72;\t// @[PMP.scala:83:16, :88:5]\n wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75;\t// @[PMP.scala:83:16, :88:5, :94:48]\n wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore_5 = default_0 & _res_ignore_T_5;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11;\t// @[package.scala:243:{46,76}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3];\t// @[PMP.scala:60:27, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90;\t// @[PMP.scala:123:{35,49,67}]\n wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0];\t// @[PMP.scala:60:27, :123:108]\n wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98;\t// @[PMP.scala:123:{127,129}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99;\t// @[PMP.scala:123:{108,125,127}]\n wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100;\t// @[PMP.scala:123:{125,147}]\n wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101;\t// @[PMP.scala:123:{82,90,147}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5;\t// @[PMP.scala:123:90, :124:85, :125:46]\n wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_226;\t// @[PMP.scala:168:32]\n assign _res_T_226 = _GEN_27;\t// @[PMP.scala:168:32]\n wire _res_T_245;\t// @[PMP.scala:177:61]\n assign _res_T_245 = _GEN_27;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_249;\t// @[PMP.scala:178:63]\n assign _res_T_249 = _GEN_27;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_227;\t// @[PMP.scala:168:32]\n assign _res_T_227 = _GEN_28;\t// @[PMP.scala:168:32]\n wire _res_T_254;\t// @[PMP.scala:177:61]\n assign _res_T_254 = _GEN_28;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_258;\t// @[PMP.scala:178:63]\n assign _res_T_258 = _GEN_28;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_228 = &io_pmp_2_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi_30;\t// @[PMP.scala:174:26]\n assign res_hi_30 = _GEN_29;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_31;\t// @[PMP.scala:174:26]\n assign res_hi_31 = _GEN_29;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_32;\t// @[PMP.scala:174:26]\n assign res_hi_32 = _GEN_29;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_33;\t// @[PMP.scala:174:26]\n assign res_hi_33 = _GEN_29;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_34;\t// @[PMP.scala:174:26]\n assign res_hi_34 = _GEN_29;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_35;\t// @[PMP.scala:174:26]\n assign res_hi_35 = _GEN_29;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_231 = _res_T_230 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_233 = _res_T_232 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_235 = _res_T_234 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_237 = _res_T_236 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_239 = _res_T_238 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_241 = &_res_T_240;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_242 = ~res_ignore_5;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_243 = _res_T_242 & res_hit_5;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_244 = _res_T_243 & res_aligned_5;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_246 = _res_T_244 & _res_T_245;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_247;\t// @[PMP.scala:178:32]\n assign _res_T_247 = _GEN_30;\t// @[PMP.scala:178:32]\n wire _res_T_256;\t// @[PMP.scala:178:32]\n assign _res_T_256 = _GEN_30;\t// @[PMP.scala:178:32]\n wire _res_T_265;\t// @[PMP.scala:178:32]\n assign _res_T_265 = _GEN_30;\t// @[PMP.scala:178:32]\n wire _res_T_248 = _res_T_247 & res_aligned_5;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_250 = _res_T_248 & _res_T_249;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_251 = ~res_ignore_5;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_252 = _res_T_251 & res_hit_5;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_253 = _res_T_252 & res_aligned_5;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_255 = _res_T_253 & _res_T_254;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_257 = _res_T_256 & res_aligned_5;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_259 = _res_T_257 & _res_T_258;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_260 = ~res_ignore_5;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_261 = _res_T_260 & res_hit_5;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_262 = _res_T_261 & res_aligned_5;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_263 = &io_pmp_2_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_264 = _res_T_262 & _res_T_263;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_266 = _res_T_265 & res_aligned_5;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_267 = &io_pmp_2_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_268 = _res_T_266 & _res_T_267;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_11;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_11;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_11;\t// @[PMP.scala:182:26]\n wire res_cur_5_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_5_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_5_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11;\t// @[PMP.scala:181:23, :184:26]\n wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20};\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_83 = ~_res_hit_T_82;\t// @[package.scala:243:{46,76}]\n wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0};\t// @[PMP.scala:60:36, :143:7]\n wire [31:0] _res_hit_msbsLess_T_73;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_73 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_85;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_85 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_86;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_86 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_103;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesLowerBound_T_110;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbMatch_T_71;\t// @[PMP.scala:60:36]\n assign _res_hit_msbMatch_T_71 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbMatch_T_71;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbMatch_T_71 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_91;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsLess_T_91 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsEqual_T_106;\t// @[PMP.scala:60:36]\n assign _res_hit_msbsEqual_T_106 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_lsbsLess_T_107;\t// @[PMP.scala:60:36]\n assign _res_hit_lsbsLess_T_107 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_120;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_aligned_straddlesUpperBound_T_127;\t// @[PMP.scala:60:36]\n assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31;\t// @[PMP.scala:60:36]\n wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_86 = ~_res_hit_T_85;\t// @[PMP.scala:83:16, :88:5]\n wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88;\t// @[PMP.scala:83:16, :88:5, :94:48]\n wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore_6 = default_0 & _res_ignore_T_6;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13;\t// @[package.scala:243:{46,76}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3];\t// @[PMP.scala:60:27, :123:67]\n wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107;\t// @[PMP.scala:123:{35,49,67}]\n wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0];\t// @[PMP.scala:60:27, :123:108]\n wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115;\t// @[PMP.scala:123:{127,129}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116;\t// @[PMP.scala:123:{108,125,127}]\n wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117;\t// @[PMP.scala:123:{125,147}]\n wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118;\t// @[PMP.scala:123:{82,90,147}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6;\t// @[PMP.scala:123:90, :124:85, :125:46]\n wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_271;\t// @[PMP.scala:168:32]\n assign _res_T_271 = _GEN_32;\t// @[PMP.scala:168:32]\n wire _res_T_290;\t// @[PMP.scala:177:61]\n assign _res_T_290 = _GEN_32;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_294;\t// @[PMP.scala:178:63]\n assign _res_T_294 = _GEN_32;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_272;\t// @[PMP.scala:168:32]\n assign _res_T_272 = _GEN_33;\t// @[PMP.scala:168:32]\n wire _res_T_299;\t// @[PMP.scala:177:61]\n assign _res_T_299 = _GEN_33;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_303;\t// @[PMP.scala:178:63]\n assign _res_T_303 = _GEN_33;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_273 = &io_pmp_1_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi_36;\t// @[PMP.scala:174:26]\n assign res_hi_36 = _GEN_34;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_37;\t// @[PMP.scala:174:26]\n assign res_hi_37 = _GEN_34;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_38;\t// @[PMP.scala:174:26]\n assign res_hi_38 = _GEN_34;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_39;\t// @[PMP.scala:174:26]\n assign res_hi_39 = _GEN_34;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_40;\t// @[PMP.scala:174:26]\n assign res_hi_40 = _GEN_34;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_41;\t// @[PMP.scala:174:26]\n assign res_hi_41 = _GEN_34;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_276 = _res_T_275 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_278 = _res_T_277 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_280 = _res_T_279 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_282 = _res_T_281 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_284 = _res_T_283 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_286 = &_res_T_285;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_287 = ~res_ignore_6;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_288 = _res_T_287 & res_hit_6;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_289 = _res_T_288 & res_aligned_6;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_291 = _res_T_289 & _res_T_290;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_292;\t// @[PMP.scala:178:32]\n assign _res_T_292 = _GEN_35;\t// @[PMP.scala:178:32]\n wire _res_T_301;\t// @[PMP.scala:178:32]\n assign _res_T_301 = _GEN_35;\t// @[PMP.scala:178:32]\n wire _res_T_310;\t// @[PMP.scala:178:32]\n assign _res_T_310 = _GEN_35;\t// @[PMP.scala:178:32]\n wire _res_T_293 = _res_T_292 & res_aligned_6;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_295 = _res_T_293 & _res_T_294;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_296 = ~res_ignore_6;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_297 = _res_T_296 & res_hit_6;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_298 = _res_T_297 & res_aligned_6;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_300 = _res_T_298 & _res_T_299;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_302 = _res_T_301 & res_aligned_6;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_304 = _res_T_302 & _res_T_303;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_305 = ~res_ignore_6;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_306 = _res_T_305 & res_hit_6;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_307 = _res_T_306 & res_aligned_6;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_308 = &io_pmp_1_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_309 = _res_T_307 & _res_T_308;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_311 = _res_T_310 & res_aligned_6;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_312 = &io_pmp_1_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_313 = _res_T_311 & _res_T_312;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_13;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_13;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_13;\t// @[PMP.scala:182:26]\n wire res_cur_6_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_6_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_6_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13;\t// @[PMP.scala:181:23, :184:26]\n wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1];\t// @[PMP.scala:45:20, :143:7]\n wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3];\t// @[PMP.scala:68:26, :69:72, :143:7]\n wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0];\t// @[PMP.scala:68:26, :126:39, :143:7]\n wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23};\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3];\t// @[PMP.scala:60:27, :69:53]\n wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75;\t// @[PMP.scala:63:47, :69:{29,53}]\n wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76;\t// @[PMP.scala:63:54, :69:72]\n wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0;\t// @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]\n wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0];\t// @[PMP.scala:60:27, :70:55]\n wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0];\t// @[PMP.scala:68:26, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75;\t// @[PMP.scala:63:47, :70:{28,55}]\n wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76;\t// @[PMP.scala:63:54, :70:80]\n wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78;\t// @[PMP.scala:63:{47,52,54}]\n wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0;\t// @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]\n wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7;\t// @[PMP.scala:63:58, :71:16]\n wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0];\t// @[PMP.scala:46:26, :143:7]\n wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _res_hit_T_96 = ~_res_hit_T_95;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98;\t// @[PMP.scala:81:{27,41}]\n wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96;\t// @[package.scala:243:46]\n wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3];\t// @[PMP.scala:60:27, :80:52]\n wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95;\t// @[PMP.scala:80:{25,39,52}]\n wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3];\t// @[PMP.scala:60:27, :81:54]\n wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110;\t// @[PMP.scala:81:{27,41,54}]\n wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0;\t// @[PMP.scala:80:52, :81:{41,54,69}, :123:67]\n wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105;\t// @[PMP.scala:82:{25,42}]\n wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0];\t// @[PMP.scala:60:27, :82:64]\n wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111;\t// @[PMP.scala:82:{42,53,64}]\n wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15;\t// @[PMP.scala:81:69, :82:53, :83:30]\n wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100;\t// @[PMP.scala:80:39, :83:{16,30}]\n wire _res_hit_T_102 = _res_hit_T_101;\t// @[PMP.scala:83:16, :94:48]\n wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102;\t// @[PMP.scala:46:26, :94:48, :132:61]\n wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103;\t// @[PMP.scala:45:20, :71:16, :132:{8,61}]\n wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0;\t// @[PMP.scala:143:7, :164:29]\n wire res_ignore_7 = default_0 & _res_ignore_T_7;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15;\t// @[package.scala:243:{46,76}]\n wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119;\t// @[PMP.scala:123:{35,49}]\n wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:{49,67,82}]\n wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132;\t// @[PMP.scala:123:{127,129}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122;\t// @[PMP.scala:60:{27,48}]\n wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3];\t// @[PMP.scala:60:27, :124:62]\n wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124;\t// @[PMP.scala:124:{35,49,62}]\n wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0;\t// @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127;\t// @[PMP.scala:60:{29,36}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3};\t// @[PMP.scala:60:{29,48}]\n wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129;\t// @[PMP.scala:60:{27,48}]\n wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0];\t// @[PMP.scala:60:27, :124:98]\n wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7;\t// @[package.scala:243:46]\n wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133;\t// @[PMP.scala:124:{98,115,136}]\n wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134;\t// @[PMP.scala:124:{115,148}]\n wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135;\t// @[PMP.scala:124:{77,85,148}]\n wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7;\t// @[PMP.scala:124:85, :125:46]\n wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7;\t// @[PMP.scala:125:{24,46}]\n wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21;\t// @[PMP.scala:126:{34,39}]\n wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22;\t// @[package.scala:243:46]\n wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]\n wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7;\t// @[PMP.scala:45:20, :125:24, :126:57, :127:8]\n wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0;\t// @[PMP.scala:143:7, :168:32]\n wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_316;\t// @[PMP.scala:168:32]\n assign _res_T_316 = _GEN_36;\t// @[PMP.scala:168:32]\n wire _res_T_335;\t// @[PMP.scala:177:61]\n assign _res_T_335 = _GEN_36;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_339;\t// @[PMP.scala:178:63]\n assign _res_T_339 = _GEN_36;\t// @[PMP.scala:168:32, :178:63]\n wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2;\t// @[PMP.scala:143:7, :168:32]\n wire _res_T_317;\t// @[PMP.scala:168:32]\n assign _res_T_317 = _GEN_37;\t// @[PMP.scala:168:32]\n wire _res_T_344;\t// @[PMP.scala:177:61]\n assign _res_T_344 = _GEN_37;\t// @[PMP.scala:168:32, :177:61]\n wire _res_T_348;\t// @[PMP.scala:178:63]\n assign _res_T_348 = _GEN_37;\t// @[PMP.scala:168:32, :178:63]\n wire _res_T_318 = &io_pmp_0_cfg_a_0;\t// @[PMP.scala:143:7, :168:32]\n wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0};\t// @[PMP.scala:143:7, :174:26]\n wire [1:0] res_hi_42;\t// @[PMP.scala:174:26]\n assign res_hi_42 = _GEN_38;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_43;\t// @[PMP.scala:174:26]\n assign res_hi_43 = _GEN_38;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_44;\t// @[PMP.scala:174:26]\n assign res_hi_44 = _GEN_38;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_45;\t// @[PMP.scala:174:26]\n assign res_hi_45 = _GEN_38;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_46;\t// @[PMP.scala:174:26]\n assign res_hi_46 = _GEN_38;\t// @[PMP.scala:174:26]\n wire [1:0] res_hi_47;\t// @[PMP.scala:174:26]\n assign res_hi_47 = _GEN_38;\t// @[PMP.scala:174:26]\n wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_321 = _res_T_320 == 3'h0;\t// @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]\n wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_323 = _res_T_322 == 3'h1;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_325 = _res_T_324 == 3'h3;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_327 = _res_T_326 == 3'h4;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_329 = _res_T_328 == 3'h5;\t// @[PMP.scala:174:{26,60}]\n wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0};\t// @[PMP.scala:143:7, :174:26]\n wire _res_T_331 = &_res_T_330;\t// @[PMP.scala:174:{26,60}]\n wire _res_T_332 = ~res_ignore_7;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_333 = _res_T_332 & res_hit_7;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_334 = _res_T_333 & res_aligned_7;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_336 = _res_T_334 & _res_T_335;\t// @[PMP.scala:177:{37,48,61}]\n wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7;\t// @[PMP.scala:132:8, :143:7, :178:32]\n wire _res_T_337;\t// @[PMP.scala:178:32]\n assign _res_T_337 = _GEN_39;\t// @[PMP.scala:178:32]\n wire _res_T_346;\t// @[PMP.scala:178:32]\n assign _res_T_346 = _GEN_39;\t// @[PMP.scala:178:32]\n wire _res_T_355;\t// @[PMP.scala:178:32]\n assign _res_T_355 = _GEN_39;\t// @[PMP.scala:178:32]\n wire _res_T_338 = _res_T_337 & res_aligned_7;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_340 = _res_T_338 & _res_T_339;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_341 = ~res_ignore_7;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_342 = _res_T_341 & res_hit_7;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_343 = _res_T_342 & res_aligned_7;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_345 = _res_T_343 & _res_T_344;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_347 = _res_T_346 & res_aligned_7;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_349 = _res_T_347 & _res_T_348;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_T_350 = ~res_ignore_7;\t// @[PMP.scala:164:26, :177:22]\n wire _res_T_351 = _res_T_350 & res_hit_7;\t// @[PMP.scala:132:8, :177:{22,30}]\n wire _res_T_352 = _res_T_351 & res_aligned_7;\t// @[PMP.scala:127:8, :177:{30,37}]\n wire _res_T_353 = &io_pmp_0_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :177:61]\n wire _res_T_354 = _res_T_352 & _res_T_353;\t// @[PMP.scala:177:{37,48,61}]\n wire _res_T_356 = _res_T_355 & res_aligned_7;\t// @[PMP.scala:127:8, :178:{32,39}]\n wire _res_T_357 = &io_pmp_0_cfg_a_0;\t// @[PMP.scala:143:7, :168:32, :178:63]\n wire _res_T_358 = _res_T_356 & _res_T_357;\t// @[PMP.scala:178:{39,50,63}]\n wire _res_cur_cfg_x_T_15;\t// @[PMP.scala:184:26]\n wire _res_cur_cfg_w_T_15;\t// @[PMP.scala:183:26]\n wire _res_cur_cfg_r_T_15;\t// @[PMP.scala:182:26]\n wire res_cur_7_cfg_x;\t// @[PMP.scala:181:23]\n wire res_cur_7_cfg_w;\t// @[PMP.scala:181:23]\n wire res_cur_7_cfg_r;\t// @[PMP.scala:181:23]\n wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7;\t// @[PMP.scala:143:7, :164:26, :182:40]\n assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14;\t// @[PMP.scala:127:8, :182:{26,40}]\n assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15;\t// @[PMP.scala:181:23, :182:26]\n wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7;\t// @[PMP.scala:143:7, :164:26, :183:40]\n assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14;\t// @[PMP.scala:127:8, :183:{26,40}]\n assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15;\t// @[PMP.scala:181:23, :183:26]\n wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7;\t// @[PMP.scala:143:7, :164:26, :184:40]\n assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14;\t// @[PMP.scala:127:8, :184:{26,40}]\n assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15;\t// @[PMP.scala:181:23, :184:26]\n wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a;\t// @[PMP.scala:132:8, :181:23, :185:8]\n assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x;\t// @[PMP.scala:132:8, :181:23, :185:8]\n assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w;\t// @[PMP.scala:132:8, :181:23, :185:8]\n assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr;\t// @[PMP.scala:132:8, :181:23, :185:8]\n wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask;\t// @[PMP.scala:132:8, :181:23, :185:8]\n assign io_x_0 = res_cfg_x;\t// @[PMP.scala:143:7, :185:8]\n assign io_w_0 = res_cfg_w;\t// @[PMP.scala:143:7, :185:8]\n assign io_r_0 = res_cfg_r;\t// @[PMP.scala:143:7, :185:8]\n assign io_r = io_r_0;\t// @[PMP.scala:143:7]\n assign io_w = io_w_0;\t// @[PMP.scala:143:7]\n assign io_x = io_x_0;\t// @[PMP.scala:143:7]\nendmodule"}}},{"rowIdx":32185,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k5z4c_1 : \n input clock : Clock \n input reset : Reset \n output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}} \n\n\n wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}} \n invalidate nodeIn.e.bits.sink \n invalidate nodeIn.e.valid \n invalidate nodeIn.e.ready \n invalidate nodeIn.d.bits.corrupt \n invalidate nodeIn.d.bits.data \n invalidate nodeIn.d.bits.denied \n invalidate nodeIn.d.bits.sink \n invalidate nodeIn.d.bits.source \n invalidate nodeIn.d.bits.size \n invalidate nodeIn.d.bits.param \n invalidate nodeIn.d.bits.opcode \n invalidate nodeIn.d.valid \n invalidate nodeIn.d.ready \n invalidate nodeIn.c.bits.corrupt \n invalidate nodeIn.c.bits.data \n invalidate nodeIn.c.bits.address \n invalidate nodeIn.c.bits.source \n invalidate nodeIn.c.bits.size \n invalidate nodeIn.c.bits.param \n invalidate nodeIn.c.bits.opcode \n invalidate nodeIn.c.valid \n invalidate nodeIn.c.ready \n invalidate nodeIn.b.bits.corrupt \n invalidate nodeIn.b.bits.data \n invalidate nodeIn.b.bits.mask \n invalidate nodeIn.b.bits.address \n invalidate nodeIn.b.bits.source \n invalidate nodeIn.b.bits.size \n invalidate nodeIn.b.bits.param \n invalidate nodeIn.b.bits.opcode \n invalidate nodeIn.b.valid \n invalidate nodeIn.b.ready \n invalidate nodeIn.a.bits.corrupt \n invalidate nodeIn.a.bits.data \n invalidate nodeIn.a.bits.mask \n invalidate nodeIn.a.bits.address \n invalidate nodeIn.a.bits.source \n invalidate nodeIn.a.bits.size \n invalidate nodeIn.a.bits.param \n invalidate nodeIn.a.bits.opcode \n invalidate nodeIn.a.valid \n invalidate nodeIn.a.ready \n inst monitor of TLMonitor_58 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink \n connect monitor.io.in.e.valid, nodeIn.e.valid \n connect monitor.io.in.e.ready, nodeIn.e.ready \n connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, nodeIn.d.bits.data \n connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink \n connect monitor.io.in.d.bits.source, nodeIn.d.bits.source \n connect monitor.io.in.d.bits.size, nodeIn.d.bits.size \n connect monitor.io.in.d.bits.param, nodeIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode \n connect monitor.io.in.d.valid, nodeIn.d.valid \n connect monitor.io.in.d.ready, nodeIn.d.ready \n connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt \n connect monitor.io.in.c.bits.data, nodeIn.c.bits.data \n connect monitor.io.in.c.bits.address, nodeIn.c.bits.address \n connect monitor.io.in.c.bits.source, nodeIn.c.bits.source \n connect monitor.io.in.c.bits.size, nodeIn.c.bits.size \n connect monitor.io.in.c.bits.param, nodeIn.c.bits.param \n connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode \n connect monitor.io.in.c.valid, nodeIn.c.valid \n connect monitor.io.in.c.ready, nodeIn.c.ready \n connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt \n connect monitor.io.in.b.bits.data, nodeIn.b.bits.data \n connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask \n connect monitor.io.in.b.bits.address, nodeIn.b.bits.address \n connect monitor.io.in.b.bits.source, nodeIn.b.bits.source \n connect monitor.io.in.b.bits.size, nodeIn.b.bits.size \n connect monitor.io.in.b.bits.param, nodeIn.b.bits.param \n connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode \n connect monitor.io.in.b.valid, nodeIn.b.valid \n connect monitor.io.in.b.ready, nodeIn.b.ready \n connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, nodeIn.a.bits.data \n connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask \n connect monitor.io.in.a.bits.address, nodeIn.a.bits.address \n connect monitor.io.in.a.bits.source, nodeIn.a.bits.source \n connect monitor.io.in.a.bits.size, nodeIn.a.bits.size \n connect monitor.io.in.a.bits.param, nodeIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode \n connect monitor.io.in.a.valid, nodeIn.a.valid \n connect monitor.io.in.a.ready, nodeIn.a.ready \n wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}} \n invalidate nodeOut.e.bits.sink \n invalidate nodeOut.e.valid \n invalidate nodeOut.e.ready \n invalidate nodeOut.d.bits.corrupt \n invalidate nodeOut.d.bits.data \n invalidate nodeOut.d.bits.denied \n invalidate nodeOut.d.bits.sink \n invalidate nodeOut.d.bits.source \n invalidate nodeOut.d.bits.size \n invalidate nodeOut.d.bits.param \n invalidate nodeOut.d.bits.opcode \n invalidate nodeOut.d.valid \n invalidate nodeOut.d.ready \n invalidate nodeOut.c.bits.corrupt \n invalidate nodeOut.c.bits.data \n invalidate nodeOut.c.bits.address \n invalidate nodeOut.c.bits.source \n invalidate nodeOut.c.bits.size \n invalidate nodeOut.c.bits.param \n invalidate nodeOut.c.bits.opcode \n invalidate nodeOut.c.valid \n invalidate nodeOut.c.ready \n invalidate nodeOut.b.bits.corrupt \n invalidate nodeOut.b.bits.data \n invalidate nodeOut.b.bits.mask \n invalidate nodeOut.b.bits.address \n invalidate nodeOut.b.bits.source \n invalidate nodeOut.b.bits.size \n invalidate nodeOut.b.bits.param \n invalidate nodeOut.b.bits.opcode \n invalidate nodeOut.b.valid \n invalidate nodeOut.b.ready \n invalidate nodeOut.a.bits.corrupt \n invalidate nodeOut.a.bits.data \n invalidate nodeOut.a.bits.mask \n invalidate nodeOut.a.bits.address \n invalidate nodeOut.a.bits.source \n invalidate nodeOut.a.bits.size \n invalidate nodeOut.a.bits.param \n invalidate nodeOut.a.bits.opcode \n invalidate nodeOut.a.valid \n invalidate nodeOut.a.ready \n connect auto.out, nodeOut \n connect nodeIn, auto.in \n inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k5z4c \n connect nodeOut_a_q.clock, clock\n\n connect nodeOut_a_q.reset, reset\n\n connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid \n connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt \n connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data \n connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask \n connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address \n connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source \n connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size \n connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param \n connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode \n connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready \n connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits \n connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid \n connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready \n inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k5z4c \n connect nodeIn_d_q.clock, clock\n\n connect nodeIn_d_q.reset, reset\n\n connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid \n connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt \n connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data \n connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied \n connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink \n connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source \n connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size \n connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param \n connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode \n connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready \n connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits \n connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid \n connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready \n inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k5z4c \n connect nodeIn_b_q.clock, clock\n\n connect nodeIn_b_q.reset, reset\n\n connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid \n connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt \n connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data \n connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask \n connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address \n connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source \n connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size \n connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param \n connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode \n connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready \n connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits \n connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid \n connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready \n inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k5z4c \n connect nodeOut_c_q.clock, clock\n\n connect nodeOut_c_q.reset, reset\n\n connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid \n connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt \n connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data \n connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address \n connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source \n connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size \n connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param \n connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode \n connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready \n connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits \n connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid \n connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready \n inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k5z4c \n connect nodeOut_e_q.clock, clock\n\n connect nodeOut_e_q.reset, reset\n\n connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid \n connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink \n connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready \n connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits \n connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid \n connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready"},"response":{"kind":"string","value":"module TLBuffer_a32d64s2k5z4c_1(\t// @[Buffer.scala:40:9]\n input clock,\t// @[Buffer.scala:40:9]\n input reset,\t// @[Buffer.scala:40:9]\n output auto_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_in_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_in_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_in_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_out_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_e_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_out_e_bits_sink\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire _nodeOut_e_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n wire _nodeOut_c_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_b_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n wire [2:0] _nodeIn_b_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_b_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n wire [3:0] _nodeIn_b_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_b_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n wire [31:0] _nodeIn_b_q_io_deq_bits_address;\t// @[Decoupled.scala:362:21]\n wire [7:0] _nodeIn_b_q_io_deq_bits_mask;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_b_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_d_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n wire [2:0] _nodeIn_d_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_d_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n wire [3:0] _nodeIn_d_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_d_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n wire [4:0] _nodeIn_d_q_io_deq_bits_sink;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_d_q_io_deq_bits_denied;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_d_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n wire _nodeOut_a_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n TLMonitor_58 monitor (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (_nodeOut_a_q_io_enq_ready),\t// @[Decoupled.scala:362:21]\n .io_in_a_valid (auto_in_a_valid),\n .io_in_a_bits_opcode (auto_in_a_bits_opcode),\n .io_in_a_bits_param (auto_in_a_bits_param),\n .io_in_a_bits_size (auto_in_a_bits_size),\n .io_in_a_bits_source (auto_in_a_bits_source),\n .io_in_a_bits_address (auto_in_a_bits_address),\n .io_in_a_bits_mask (auto_in_a_bits_mask),\n .io_in_b_ready (auto_in_b_ready),\n .io_in_b_valid (_nodeIn_b_q_io_deq_valid),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_param (_nodeIn_b_q_io_deq_bits_param),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_size (_nodeIn_b_q_io_deq_bits_size),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_source (_nodeIn_b_q_io_deq_bits_source),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_address (_nodeIn_b_q_io_deq_bits_address),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_mask (_nodeIn_b_q_io_deq_bits_mask),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt),\t// @[Decoupled.scala:362:21]\n .io_in_c_ready (_nodeOut_c_q_io_enq_ready),\t// @[Decoupled.scala:362:21]\n .io_in_c_valid (auto_in_c_valid),\n .io_in_c_bits_opcode (auto_in_c_bits_opcode),\n .io_in_c_bits_param (auto_in_c_bits_param),\n .io_in_c_bits_size (auto_in_c_bits_size),\n .io_in_c_bits_source (auto_in_c_bits_source),\n .io_in_c_bits_address (auto_in_c_bits_address),\n .io_in_d_ready (auto_in_d_ready),\n .io_in_d_valid (_nodeIn_d_q_io_deq_valid),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt),\t// @[Decoupled.scala:362:21]\n .io_in_e_ready (_nodeOut_e_q_io_enq_ready),\t// @[Decoupled.scala:362:21]\n .io_in_e_valid (auto_in_e_valid),\n .io_in_e_bits_sink (auto_in_e_bits_sink)\n );\t// @[Nodes.scala:27:25]\n Queue2_TLBundleA_a32d64s2k5z4c nodeOut_a_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_nodeOut_a_q_io_enq_ready),\n .io_enq_valid (auto_in_a_valid),\n .io_enq_bits_opcode (auto_in_a_bits_opcode),\n .io_enq_bits_param (auto_in_a_bits_param),\n .io_enq_bits_size (auto_in_a_bits_size),\n .io_enq_bits_source (auto_in_a_bits_source),\n .io_enq_bits_address (auto_in_a_bits_address),\n .io_enq_bits_mask (auto_in_a_bits_mask),\n .io_enq_bits_data (auto_in_a_bits_data),\n .io_deq_ready (auto_out_a_ready),\n .io_deq_valid (auto_out_a_valid),\n .io_deq_bits_opcode (auto_out_a_bits_opcode),\n .io_deq_bits_param (auto_out_a_bits_param),\n .io_deq_bits_size (auto_out_a_bits_size),\n .io_deq_bits_source (auto_out_a_bits_source),\n .io_deq_bits_address (auto_out_a_bits_address),\n .io_deq_bits_mask (auto_out_a_bits_mask),\n .io_deq_bits_data (auto_out_a_bits_data),\n .io_deq_bits_corrupt (auto_out_a_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleD_a32d64s2k5z4c nodeIn_d_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (auto_out_d_ready),\n .io_enq_valid (auto_out_d_valid),\n .io_enq_bits_opcode (auto_out_d_bits_opcode),\n .io_enq_bits_param (auto_out_d_bits_param),\n .io_enq_bits_size (auto_out_d_bits_size),\n .io_enq_bits_source (auto_out_d_bits_source),\n .io_enq_bits_sink (auto_out_d_bits_sink),\n .io_enq_bits_denied (auto_out_d_bits_denied),\n .io_enq_bits_data (auto_out_d_bits_data),\n .io_enq_bits_corrupt (auto_out_d_bits_corrupt),\n .io_deq_ready (auto_in_d_ready),\n .io_deq_valid (_nodeIn_d_q_io_deq_valid),\n .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),\n .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),\n .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),\n .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),\n .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),\n .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),\n .io_deq_bits_data (auto_in_d_bits_data),\n .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleB_a32d64s2k5z4c nodeIn_b_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (auto_out_b_ready),\n .io_enq_valid (auto_out_b_valid),\n .io_enq_bits_opcode (auto_out_b_bits_opcode),\n .io_enq_bits_param (auto_out_b_bits_param),\n .io_enq_bits_size (auto_out_b_bits_size),\n .io_enq_bits_source (auto_out_b_bits_source),\n .io_enq_bits_address (auto_out_b_bits_address),\n .io_enq_bits_mask (auto_out_b_bits_mask),\n .io_enq_bits_data (auto_out_b_bits_data),\n .io_enq_bits_corrupt (auto_out_b_bits_corrupt),\n .io_deq_ready (auto_in_b_ready),\n .io_deq_valid (_nodeIn_b_q_io_deq_valid),\n .io_deq_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode),\n .io_deq_bits_param (_nodeIn_b_q_io_deq_bits_param),\n .io_deq_bits_size (_nodeIn_b_q_io_deq_bits_size),\n .io_deq_bits_source (_nodeIn_b_q_io_deq_bits_source),\n .io_deq_bits_address (_nodeIn_b_q_io_deq_bits_address),\n .io_deq_bits_mask (_nodeIn_b_q_io_deq_bits_mask),\n .io_deq_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleC_a32d64s2k5z4c nodeOut_c_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_nodeOut_c_q_io_enq_ready),\n .io_enq_valid (auto_in_c_valid),\n .io_enq_bits_opcode (auto_in_c_bits_opcode),\n .io_enq_bits_param (auto_in_c_bits_param),\n .io_enq_bits_size (auto_in_c_bits_size),\n .io_enq_bits_source (auto_in_c_bits_source),\n .io_enq_bits_address (auto_in_c_bits_address),\n .io_enq_bits_data (auto_in_c_bits_data),\n .io_deq_ready (auto_out_c_ready),\n .io_deq_valid (auto_out_c_valid),\n .io_deq_bits_opcode (auto_out_c_bits_opcode),\n .io_deq_bits_param (auto_out_c_bits_param),\n .io_deq_bits_size (auto_out_c_bits_size),\n .io_deq_bits_source (auto_out_c_bits_source),\n .io_deq_bits_address (auto_out_c_bits_address),\n .io_deq_bits_data (auto_out_c_bits_data),\n .io_deq_bits_corrupt (auto_out_c_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleE_a32d64s2k5z4c nodeOut_e_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_nodeOut_e_q_io_enq_ready),\n .io_enq_valid (auto_in_e_valid),\n .io_enq_bits_sink (auto_in_e_bits_sink),\n .io_deq_ready (auto_out_e_ready),\n .io_deq_valid (auto_out_e_valid),\n .io_deq_bits_sink (auto_out_e_bits_sink)\n );\t// @[Decoupled.scala:362:21]\n assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_valid = _nodeIn_b_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_opcode = _nodeIn_b_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_param = _nodeIn_b_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_size = _nodeIn_b_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_source = _nodeIn_b_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_address = _nodeIn_b_q_io_deq_bits_address;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_mask = _nodeIn_b_q_io_deq_bits_mask;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_corrupt = _nodeIn_b_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n assign auto_in_c_ready = _nodeOut_c_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n assign auto_in_e_ready = _nodeOut_e_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\nendmodule"}}},{"rowIdx":32186,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_1 : \n input clock : Clock \n input reset : Reset \n output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} \n\n\n wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} \n invalidate nodeIn.e.bits.sink \n invalidate nodeIn.e.valid \n invalidate nodeIn.e.ready \n invalidate nodeIn.d.bits.corrupt \n invalidate nodeIn.d.bits.data \n invalidate nodeIn.d.bits.denied \n invalidate nodeIn.d.bits.sink \n invalidate nodeIn.d.bits.source \n invalidate nodeIn.d.bits.size \n invalidate nodeIn.d.bits.param \n invalidate nodeIn.d.bits.opcode \n invalidate nodeIn.d.valid \n invalidate nodeIn.d.ready \n invalidate nodeIn.c.bits.corrupt \n invalidate nodeIn.c.bits.data \n invalidate nodeIn.c.bits.address \n invalidate nodeIn.c.bits.source \n invalidate nodeIn.c.bits.size \n invalidate nodeIn.c.bits.param \n invalidate nodeIn.c.bits.opcode \n invalidate nodeIn.c.valid \n invalidate nodeIn.c.ready \n invalidate nodeIn.b.bits.corrupt \n invalidate nodeIn.b.bits.data \n invalidate nodeIn.b.bits.mask \n invalidate nodeIn.b.bits.address \n invalidate nodeIn.b.bits.source \n invalidate nodeIn.b.bits.size \n invalidate nodeIn.b.bits.param \n invalidate nodeIn.b.bits.opcode \n invalidate nodeIn.b.valid \n invalidate nodeIn.b.ready \n invalidate nodeIn.a.bits.corrupt \n invalidate nodeIn.a.bits.data \n invalidate nodeIn.a.bits.mask \n invalidate nodeIn.a.bits.address \n invalidate nodeIn.a.bits.source \n invalidate nodeIn.a.bits.size \n invalidate nodeIn.a.bits.param \n invalidate nodeIn.a.bits.opcode \n invalidate nodeIn.a.valid \n invalidate nodeIn.a.ready \n inst monitor of TLMonitor_41 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink \n connect monitor.io.in.e.valid, nodeIn.e.valid \n connect monitor.io.in.e.ready, nodeIn.e.ready \n connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, nodeIn.d.bits.data \n connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink \n connect monitor.io.in.d.bits.source, nodeIn.d.bits.source \n connect monitor.io.in.d.bits.size, nodeIn.d.bits.size \n connect monitor.io.in.d.bits.param, nodeIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode \n connect monitor.io.in.d.valid, nodeIn.d.valid \n connect monitor.io.in.d.ready, nodeIn.d.ready \n connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt \n connect monitor.io.in.c.bits.data, nodeIn.c.bits.data \n connect monitor.io.in.c.bits.address, nodeIn.c.bits.address \n connect monitor.io.in.c.bits.source, nodeIn.c.bits.source \n connect monitor.io.in.c.bits.size, nodeIn.c.bits.size \n connect monitor.io.in.c.bits.param, nodeIn.c.bits.param \n connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode \n connect monitor.io.in.c.valid, nodeIn.c.valid \n connect monitor.io.in.c.ready, nodeIn.c.ready \n connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt \n connect monitor.io.in.b.bits.data, nodeIn.b.bits.data \n connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask \n connect monitor.io.in.b.bits.address, nodeIn.b.bits.address \n connect monitor.io.in.b.bits.source, nodeIn.b.bits.source \n connect monitor.io.in.b.bits.size, nodeIn.b.bits.size \n connect monitor.io.in.b.bits.param, nodeIn.b.bits.param \n connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode \n connect monitor.io.in.b.valid, nodeIn.b.valid \n connect monitor.io.in.b.ready, nodeIn.b.ready \n connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, nodeIn.a.bits.data \n connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask \n connect monitor.io.in.a.bits.address, nodeIn.a.bits.address \n connect monitor.io.in.a.bits.source, nodeIn.a.bits.source \n connect monitor.io.in.a.bits.size, nodeIn.a.bits.size \n connect monitor.io.in.a.bits.param, nodeIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode \n connect monitor.io.in.a.valid, nodeIn.a.valid \n connect monitor.io.in.a.ready, nodeIn.a.ready \n wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} \n invalidate nodeOut.e.bits.sink \n invalidate nodeOut.e.valid \n invalidate nodeOut.e.ready \n invalidate nodeOut.d.bits.corrupt \n invalidate nodeOut.d.bits.data \n invalidate nodeOut.d.bits.denied \n invalidate nodeOut.d.bits.sink \n invalidate nodeOut.d.bits.source \n invalidate nodeOut.d.bits.size \n invalidate nodeOut.d.bits.param \n invalidate nodeOut.d.bits.opcode \n invalidate nodeOut.d.valid \n invalidate nodeOut.d.ready \n invalidate nodeOut.c.bits.corrupt \n invalidate nodeOut.c.bits.data \n invalidate nodeOut.c.bits.address \n invalidate nodeOut.c.bits.source \n invalidate nodeOut.c.bits.size \n invalidate nodeOut.c.bits.param \n invalidate nodeOut.c.bits.opcode \n invalidate nodeOut.c.valid \n invalidate nodeOut.c.ready \n invalidate nodeOut.b.bits.corrupt \n invalidate nodeOut.b.bits.data \n invalidate nodeOut.b.bits.mask \n invalidate nodeOut.b.bits.address \n invalidate nodeOut.b.bits.source \n invalidate nodeOut.b.bits.size \n invalidate nodeOut.b.bits.param \n invalidate nodeOut.b.bits.opcode \n invalidate nodeOut.b.valid \n invalidate nodeOut.b.ready \n invalidate nodeOut.a.bits.corrupt \n invalidate nodeOut.a.bits.data \n invalidate nodeOut.a.bits.mask \n invalidate nodeOut.a.bits.address \n invalidate nodeOut.a.bits.source \n invalidate nodeOut.a.bits.size \n invalidate nodeOut.a.bits.param \n invalidate nodeOut.a.bits.opcode \n invalidate nodeOut.a.valid \n invalidate nodeOut.a.ready \n connect auto.out, nodeOut \n connect nodeIn, auto.in \n inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c \n connect nodeOut_a_q.clock, clock\n\n connect nodeOut_a_q.reset, reset\n\n connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid \n connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt \n connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data \n connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask \n connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address \n connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source \n connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size \n connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param \n connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode \n connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready \n connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits \n connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid \n connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready \n inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c \n connect nodeIn_d_q.clock, clock\n\n connect nodeIn_d_q.reset, reset\n\n connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid \n connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt \n connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data \n connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied \n connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink \n connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source \n connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size \n connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param \n connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode \n connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready \n connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits \n connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid \n connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready \n inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c \n connect nodeIn_b_q.clock, clock\n\n connect nodeIn_b_q.reset, reset\n\n connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid \n connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt \n connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data \n connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask \n connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address \n connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source \n connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size \n connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param \n connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode \n connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready \n connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits \n connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid \n connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready \n inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c \n connect nodeOut_c_q.clock, clock\n\n connect nodeOut_c_q.reset, reset\n\n connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid \n connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt \n connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data \n connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address \n connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source \n connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size \n connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param \n connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode \n connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready \n connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits \n connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid \n connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready \n inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c \n connect nodeOut_e_q.clock, clock\n\n connect nodeOut_e_q.reset, reset\n\n connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid \n connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink \n connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready \n connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits \n connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid \n connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready"},"response":{"kind":"string","value":"module TLBuffer_a32d64s2k3z4c_1(\t// @[Buffer.scala:40:9]\n input clock,\t// @[Buffer.scala:40:9]\n input reset,\t// @[Buffer.scala:40:9]\n output auto_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_in_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_in_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_c_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_bits_sink\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire _nodeOut_e_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n wire _nodeOut_c_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_b_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n wire [2:0] _nodeIn_b_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_b_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n wire [3:0] _nodeIn_b_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_b_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n wire [31:0] _nodeIn_b_q_io_deq_bits_address;\t// @[Decoupled.scala:362:21]\n wire [7:0] _nodeIn_b_q_io_deq_bits_mask;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_b_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_d_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n wire [2:0] _nodeIn_d_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_d_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n wire [3:0] _nodeIn_d_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n wire [1:0] _nodeIn_d_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n wire [2:0] _nodeIn_d_q_io_deq_bits_sink;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_d_q_io_deq_bits_denied;\t// @[Decoupled.scala:362:21]\n wire _nodeIn_d_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n wire _nodeOut_a_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n TLMonitor_41 monitor (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (_nodeOut_a_q_io_enq_ready),\t// @[Decoupled.scala:362:21]\n .io_in_a_valid (auto_in_a_valid),\n .io_in_a_bits_opcode (auto_in_a_bits_opcode),\n .io_in_a_bits_param (auto_in_a_bits_param),\n .io_in_a_bits_size (auto_in_a_bits_size),\n .io_in_a_bits_source (auto_in_a_bits_source),\n .io_in_a_bits_address (auto_in_a_bits_address),\n .io_in_a_bits_mask (auto_in_a_bits_mask),\n .io_in_b_ready (auto_in_b_ready),\n .io_in_b_valid (_nodeIn_b_q_io_deq_valid),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_param (_nodeIn_b_q_io_deq_bits_param),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_size (_nodeIn_b_q_io_deq_bits_size),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_source (_nodeIn_b_q_io_deq_bits_source),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_address (_nodeIn_b_q_io_deq_bits_address),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_mask (_nodeIn_b_q_io_deq_bits_mask),\t// @[Decoupled.scala:362:21]\n .io_in_b_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt),\t// @[Decoupled.scala:362:21]\n .io_in_c_ready (_nodeOut_c_q_io_enq_ready),\t// @[Decoupled.scala:362:21]\n .io_in_c_valid (auto_in_c_valid),\n .io_in_c_bits_opcode (auto_in_c_bits_opcode),\n .io_in_c_bits_param (auto_in_c_bits_param),\n .io_in_c_bits_size (auto_in_c_bits_size),\n .io_in_c_bits_source (auto_in_c_bits_source),\n .io_in_c_bits_address (auto_in_c_bits_address),\n .io_in_d_ready (auto_in_d_ready),\n .io_in_d_valid (_nodeIn_d_q_io_deq_valid),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied),\t// @[Decoupled.scala:362:21]\n .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt),\t// @[Decoupled.scala:362:21]\n .io_in_e_ready (_nodeOut_e_q_io_enq_ready),\t// @[Decoupled.scala:362:21]\n .io_in_e_valid (auto_in_e_valid),\n .io_in_e_bits_sink (auto_in_e_bits_sink)\n );\t// @[Nodes.scala:27:25]\n Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_nodeOut_a_q_io_enq_ready),\n .io_enq_valid (auto_in_a_valid),\n .io_enq_bits_opcode (auto_in_a_bits_opcode),\n .io_enq_bits_param (auto_in_a_bits_param),\n .io_enq_bits_size (auto_in_a_bits_size),\n .io_enq_bits_source (auto_in_a_bits_source),\n .io_enq_bits_address (auto_in_a_bits_address),\n .io_enq_bits_mask (auto_in_a_bits_mask),\n .io_enq_bits_data (auto_in_a_bits_data),\n .io_deq_ready (auto_out_a_ready),\n .io_deq_valid (auto_out_a_valid),\n .io_deq_bits_opcode (auto_out_a_bits_opcode),\n .io_deq_bits_param (auto_out_a_bits_param),\n .io_deq_bits_size (auto_out_a_bits_size),\n .io_deq_bits_source (auto_out_a_bits_source),\n .io_deq_bits_address (auto_out_a_bits_address),\n .io_deq_bits_mask (auto_out_a_bits_mask),\n .io_deq_bits_data (auto_out_a_bits_data),\n .io_deq_bits_corrupt (auto_out_a_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (auto_out_d_ready),\n .io_enq_valid (auto_out_d_valid),\n .io_enq_bits_opcode (auto_out_d_bits_opcode),\n .io_enq_bits_param (auto_out_d_bits_param),\n .io_enq_bits_size (auto_out_d_bits_size),\n .io_enq_bits_source (auto_out_d_bits_source),\n .io_enq_bits_sink (auto_out_d_bits_sink),\n .io_enq_bits_denied (auto_out_d_bits_denied),\n .io_enq_bits_data (auto_out_d_bits_data),\n .io_enq_bits_corrupt (auto_out_d_bits_corrupt),\n .io_deq_ready (auto_in_d_ready),\n .io_deq_valid (_nodeIn_d_q_io_deq_valid),\n .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),\n .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),\n .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),\n .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),\n .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),\n .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),\n .io_deq_bits_data (auto_in_d_bits_data),\n .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (auto_out_b_ready),\n .io_enq_valid (auto_out_b_valid),\n .io_enq_bits_param (auto_out_b_bits_param),\n .io_enq_bits_address (auto_out_b_bits_address),\n .io_deq_ready (auto_in_b_ready),\n .io_deq_valid (_nodeIn_b_q_io_deq_valid),\n .io_deq_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode),\n .io_deq_bits_param (_nodeIn_b_q_io_deq_bits_param),\n .io_deq_bits_size (_nodeIn_b_q_io_deq_bits_size),\n .io_deq_bits_source (_nodeIn_b_q_io_deq_bits_source),\n .io_deq_bits_address (_nodeIn_b_q_io_deq_bits_address),\n .io_deq_bits_mask (_nodeIn_b_q_io_deq_bits_mask),\n .io_deq_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_nodeOut_c_q_io_enq_ready),\n .io_enq_valid (auto_in_c_valid),\n .io_enq_bits_opcode (auto_in_c_bits_opcode),\n .io_enq_bits_param (auto_in_c_bits_param),\n .io_enq_bits_size (auto_in_c_bits_size),\n .io_enq_bits_source (auto_in_c_bits_source),\n .io_enq_bits_address (auto_in_c_bits_address),\n .io_enq_bits_data (auto_in_c_bits_data),\n .io_deq_ready (auto_out_c_ready),\n .io_deq_valid (auto_out_c_valid),\n .io_deq_bits_opcode (auto_out_c_bits_opcode),\n .io_deq_bits_param (auto_out_c_bits_param),\n .io_deq_bits_size (auto_out_c_bits_size),\n .io_deq_bits_source (auto_out_c_bits_source),\n .io_deq_bits_address (auto_out_c_bits_address),\n .io_deq_bits_data (auto_out_c_bits_data),\n .io_deq_bits_corrupt (auto_out_c_bits_corrupt)\n );\t// @[Decoupled.scala:362:21]\n Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q (\t// @[Decoupled.scala:362:21]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_nodeOut_e_q_io_enq_ready),\n .io_enq_valid (auto_in_e_valid),\n .io_enq_bits_sink (auto_in_e_bits_sink),\n .io_deq_valid (auto_out_e_valid),\n .io_deq_bits_sink (auto_out_e_bits_sink)\n );\t// @[Decoupled.scala:362:21]\n assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_valid = _nodeIn_b_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_opcode = _nodeIn_b_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_param = _nodeIn_b_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_size = _nodeIn_b_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_source = _nodeIn_b_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_address = _nodeIn_b_q_io_deq_bits_address;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_mask = _nodeIn_b_q_io_deq_bits_mask;\t// @[Decoupled.scala:362:21]\n assign auto_in_b_bits_corrupt = _nodeIn_b_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n assign auto_in_c_ready = _nodeOut_c_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied;\t// @[Decoupled.scala:362:21]\n assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt;\t// @[Decoupled.scala:362:21]\n assign auto_in_e_ready = _nodeOut_e_q_io_enq_ready;\t// @[Decoupled.scala:362:21]\nendmodule"}}},{"rowIdx":32187,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_27 : \n input clock : Clock \n input reset : Reset \n output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} \n\n\n connect io.y, io.x"},"response":{"kind":"string","value":"module OptimizationBarrier_EntryData_27(\t// @[package.scala:267:30]\n input clock,\t// @[package.scala:267:30]\n input reset,\t// @[package.scala:267:30]\n input [19:0] io_x_ppn,\t// @[package.scala:268:18]\n input io_x_u,\t// @[package.scala:268:18]\n input io_x_g,\t// @[package.scala:268:18]\n input io_x_ae,\t// @[package.scala:268:18]\n input io_x_sw,\t// @[package.scala:268:18]\n input io_x_sx,\t// @[package.scala:268:18]\n input io_x_sr,\t// @[package.scala:268:18]\n input io_x_pw,\t// @[package.scala:268:18]\n input io_x_px,\t// @[package.scala:268:18]\n input io_x_pr,\t// @[package.scala:268:18]\n input io_x_pal,\t// @[package.scala:268:18]\n input io_x_paa,\t// @[package.scala:268:18]\n input io_x_eff,\t// @[package.scala:268:18]\n input io_x_c,\t// @[package.scala:268:18]\n input io_x_fragmented_superpage,\t// @[package.scala:268:18]\n output [19:0] io_y_ppn\t// @[package.scala:268:18]\n);\n\n wire [19:0] io_x_ppn_0 = io_x_ppn;\t// @[package.scala:267:30]\n wire io_x_u_0 = io_x_u;\t// @[package.scala:267:30]\n wire io_x_g_0 = io_x_g;\t// @[package.scala:267:30]\n wire io_x_ae_0 = io_x_ae;\t// @[package.scala:267:30]\n wire io_x_sw_0 = io_x_sw;\t// @[package.scala:267:30]\n wire io_x_sx_0 = io_x_sx;\t// @[package.scala:267:30]\n wire io_x_sr_0 = io_x_sr;\t// @[package.scala:267:30]\n wire io_x_pw_0 = io_x_pw;\t// @[package.scala:267:30]\n wire io_x_px_0 = io_x_px;\t// @[package.scala:267:30]\n wire io_x_pr_0 = io_x_pr;\t// @[package.scala:267:30]\n wire io_x_pal_0 = io_x_pal;\t// @[package.scala:267:30]\n wire io_x_paa_0 = io_x_paa;\t// @[package.scala:267:30]\n wire io_x_eff_0 = io_x_eff;\t// @[package.scala:267:30]\n wire io_x_c_0 = io_x_c;\t// @[package.scala:267:30]\n wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage;\t// @[package.scala:267:30]\n wire [19:0] io_y_ppn_0 = io_x_ppn_0;\t// @[package.scala:267:30]\n wire io_y_u = io_x_u_0;\t// @[package.scala:267:30]\n wire io_y_g = io_x_g_0;\t// @[package.scala:267:30]\n wire io_y_ae = io_x_ae_0;\t// @[package.scala:267:30]\n wire io_y_sw = io_x_sw_0;\t// @[package.scala:267:30]\n wire io_y_sx = io_x_sx_0;\t// @[package.scala:267:30]\n wire io_y_sr = io_x_sr_0;\t// @[package.scala:267:30]\n wire io_y_pw = io_x_pw_0;\t// @[package.scala:267:30]\n wire io_y_px = io_x_px_0;\t// @[package.scala:267:30]\n wire io_y_pr = io_x_pr_0;\t// @[package.scala:267:30]\n wire io_y_pal = io_x_pal_0;\t// @[package.scala:267:30]\n wire io_y_paa = io_x_paa_0;\t// @[package.scala:267:30]\n wire io_y_eff = io_x_eff_0;\t// @[package.scala:267:30]\n wire io_y_c = io_x_c_0;\t// @[package.scala:267:30]\n wire io_y_fragmented_superpage = io_x_fragmented_superpage_0;\t// @[package.scala:267:30]\n assign io_y_ppn = io_y_ppn_0;\t// @[package.scala:267:30]\nendmodule"}}},{"rowIdx":32188,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_111 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_111(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire io_d = 1'h1;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire _output_T_1 = 1'h1;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":32189,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module CLINTClockSinkDomain : \n output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_11 : { sync : UInt<1>[2]}, int_in_clock_xing_out_10 : { sync : UInt<1>[2]}, int_in_clock_xing_out_9 : { sync : UInt<1>[2]}, int_in_clock_xing_out_8 : { sync : UInt<1>[2]}, int_in_clock_xing_out_7 : { sync : UInt<1>[2]}, int_in_clock_xing_out_6 : { sync : UInt<1>[2]}, int_in_clock_xing_out_5 : { sync : UInt<1>[2]}, int_in_clock_xing_out_4 : { sync : UInt<1>[2]}, int_in_clock_xing_out_3 : { sync : UInt<1>[2]}, int_in_clock_xing_out_2 : { sync : UInt<1>[2]}, int_in_clock_xing_out_1 : { sync : UInt<1>[2]}, int_in_clock_xing_out_0 : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}} \n input tick : UInt<1> \n output clock : Clock \n output reset : Reset \n\n\n wire childClock : Clock \n wire childReset : Reset \n node _childClock_T = asClock(UInt<1>(0h0)) \n connect childClock, _childClock_T \n invalidate childReset \n inst clint of CLINT \n connect clint.clock, childClock\n\n connect clint.reset, childReset\n\n inst intsource of IntSyncCrossingSource_n1x2 \n connect intsource.clock, childClock\n\n connect intsource.reset, childReset\n\n inst intsource_1 of IntSyncCrossingSource_n1x2_1 \n connect intsource_1.clock, childClock\n\n connect intsource_1.reset, childReset\n\n inst intsource_2 of IntSyncCrossingSource_n1x2_2 \n connect intsource_2.clock, childClock\n\n connect intsource_2.reset, childReset\n\n inst intsource_3 of IntSyncCrossingSource_n1x2_3 \n connect intsource_3.clock, childClock\n\n connect intsource_3.reset, childReset\n\n inst intsource_4 of IntSyncCrossingSource_n1x2_4 \n connect intsource_4.clock, childClock\n\n connect intsource_4.reset, childReset\n\n inst intsource_5 of IntSyncCrossingSource_n1x2_5 \n connect intsource_5.clock, childClock\n\n connect intsource_5.reset, childReset\n\n inst intsource_6 of IntSyncCrossingSource_n1x2_6 \n connect intsource_6.clock, childClock\n\n connect intsource_6.reset, childReset\n\n inst intsource_7 of IntSyncCrossingSource_n1x2_7 \n connect intsource_7.clock, childClock\n\n connect intsource_7.reset, childReset\n\n inst intsource_8 of IntSyncCrossingSource_n1x2_8 \n connect intsource_8.clock, childClock\n\n connect intsource_8.reset, childReset\n\n inst intsource_9 of IntSyncCrossingSource_n1x2_9 \n connect intsource_9.clock, childClock\n\n connect intsource_9.reset, childReset\n\n inst intsource_10 of IntSyncCrossingSource_n1x2_10 \n connect intsource_10.clock, childClock\n\n connect intsource_10.reset, childReset\n\n inst intsource_11 of IntSyncCrossingSource_n1x2_11 \n connect intsource_11.clock, childClock\n\n connect intsource_11.reset, childReset\n\n wire clockNodeIn : { clock : Clock, reset : Reset} \n invalidate clockNodeIn.reset \n invalidate clockNodeIn.clock \n wire intInClockXingOut : { sync : UInt<1>[2]} \n invalidate intInClockXingOut.sync[0] \n invalidate intInClockXingOut.sync[1] \n wire intInClockXingIn : { sync : UInt<1>[2]} \n invalidate intInClockXingIn.sync[0] \n invalidate intInClockXingIn.sync[1] \n connect intInClockXingOut, intInClockXingIn \n wire intInClockXingOut_1 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_1.sync[0] \n invalidate intInClockXingOut_1.sync[1] \n wire intInClockXingIn_1 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_1.sync[0] \n invalidate intInClockXingIn_1.sync[1] \n connect intInClockXingOut_1, intInClockXingIn_1 \n wire intInClockXingOut_2 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_2.sync[0] \n invalidate intInClockXingOut_2.sync[1] \n wire intInClockXingIn_2 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_2.sync[0] \n invalidate intInClockXingIn_2.sync[1] \n connect intInClockXingOut_2, intInClockXingIn_2 \n wire intInClockXingOut_3 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_3.sync[0] \n invalidate intInClockXingOut_3.sync[1] \n wire intInClockXingIn_3 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_3.sync[0] \n invalidate intInClockXingIn_3.sync[1] \n connect intInClockXingOut_3, intInClockXingIn_3 \n wire intInClockXingOut_4 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_4.sync[0] \n invalidate intInClockXingOut_4.sync[1] \n wire intInClockXingIn_4 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_4.sync[0] \n invalidate intInClockXingIn_4.sync[1] \n connect intInClockXingOut_4, intInClockXingIn_4 \n wire intInClockXingOut_5 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_5.sync[0] \n invalidate intInClockXingOut_5.sync[1] \n wire intInClockXingIn_5 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_5.sync[0] \n invalidate intInClockXingIn_5.sync[1] \n connect intInClockXingOut_5, intInClockXingIn_5 \n wire intInClockXingOut_6 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_6.sync[0] \n invalidate intInClockXingOut_6.sync[1] \n wire intInClockXingIn_6 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_6.sync[0] \n invalidate intInClockXingIn_6.sync[1] \n connect intInClockXingOut_6, intInClockXingIn_6 \n wire intInClockXingOut_7 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_7.sync[0] \n invalidate intInClockXingOut_7.sync[1] \n wire intInClockXingIn_7 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_7.sync[0] \n invalidate intInClockXingIn_7.sync[1] \n connect intInClockXingOut_7, intInClockXingIn_7 \n wire intInClockXingOut_8 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_8.sync[0] \n invalidate intInClockXingOut_8.sync[1] \n wire intInClockXingIn_8 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_8.sync[0] \n invalidate intInClockXingIn_8.sync[1] \n connect intInClockXingOut_8, intInClockXingIn_8 \n wire intInClockXingOut_9 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_9.sync[0] \n invalidate intInClockXingOut_9.sync[1] \n wire intInClockXingIn_9 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_9.sync[0] \n invalidate intInClockXingIn_9.sync[1] \n connect intInClockXingOut_9, intInClockXingIn_9 \n wire intInClockXingOut_10 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_10.sync[0] \n invalidate intInClockXingOut_10.sync[1] \n wire intInClockXingIn_10 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_10.sync[0] \n invalidate intInClockXingIn_10.sync[1] \n connect intInClockXingOut_10, intInClockXingIn_10 \n wire intInClockXingOut_11 : { sync : UInt<1>[2]} \n invalidate intInClockXingOut_11.sync[0] \n invalidate intInClockXingOut_11.sync[1] \n wire intInClockXingIn_11 : { sync : UInt<1>[2]} \n invalidate intInClockXingIn_11.sync[0] \n invalidate intInClockXingIn_11.sync[1] \n connect intInClockXingOut_11, intInClockXingIn_11 \n connect intsource.auto.in[0], clint.auto.int_out_0[0] \n connect intsource.auto.in[1], clint.auto.int_out_0[1] \n connect intsource_1.auto.in[0], clint.auto.int_out_1[0] \n connect intsource_1.auto.in[1], clint.auto.int_out_1[1] \n connect intsource_2.auto.in[0], clint.auto.int_out_2[0] \n connect intsource_2.auto.in[1], clint.auto.int_out_2[1] \n connect intsource_3.auto.in[0], clint.auto.int_out_3[0] \n connect intsource_3.auto.in[1], clint.auto.int_out_3[1] \n connect intsource_4.auto.in[0], clint.auto.int_out_4[0] \n connect intsource_4.auto.in[1], clint.auto.int_out_4[1] \n connect intsource_5.auto.in[0], clint.auto.int_out_5[0] \n connect intsource_5.auto.in[1], clint.auto.int_out_5[1] \n connect intsource_6.auto.in[0], clint.auto.int_out_6[0] \n connect intsource_6.auto.in[1], clint.auto.int_out_6[1] \n connect intsource_7.auto.in[0], clint.auto.int_out_7[0] \n connect intsource_7.auto.in[1], clint.auto.int_out_7[1] \n connect intsource_8.auto.in[0], clint.auto.int_out_8[0] \n connect intsource_8.auto.in[1], clint.auto.int_out_8[1] \n connect intsource_9.auto.in[0], clint.auto.int_out_9[0] \n connect intsource_9.auto.in[1], clint.auto.int_out_9[1] \n connect intsource_10.auto.in[0], clint.auto.int_out_10[0] \n connect intsource_10.auto.in[1], clint.auto.int_out_10[1] \n connect intsource_11.auto.in[0], clint.auto.int_out_11[0] \n connect intsource_11.auto.in[1], clint.auto.int_out_11[1] \n connect intInClockXingIn, intsource.auto.out \n connect intInClockXingIn_1, intsource_1.auto.out \n connect intInClockXingIn_2, intsource_2.auto.out \n connect intInClockXingIn_3, intsource_3.auto.out \n connect intInClockXingIn_4, intsource_4.auto.out \n connect intInClockXingIn_5, intsource_5.auto.out \n connect intInClockXingIn_6, intsource_6.auto.out \n connect intInClockXingIn_7, intsource_7.auto.out \n connect intInClockXingIn_8, intsource_8.auto.out \n connect intInClockXingIn_9, intsource_9.auto.out \n connect intInClockXingIn_10, intsource_10.auto.out \n connect intInClockXingIn_11, intsource_11.auto.out \n connect clockNodeIn, auto.clock_in \n connect auto.int_in_clock_xing_out_0, intInClockXingOut \n connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 \n connect auto.int_in_clock_xing_out_2, intInClockXingOut_2 \n connect auto.int_in_clock_xing_out_3, intInClockXingOut_3 \n connect auto.int_in_clock_xing_out_4, intInClockXingOut_4 \n connect auto.int_in_clock_xing_out_5, intInClockXingOut_5 \n connect auto.int_in_clock_xing_out_6, intInClockXingOut_6 \n connect auto.int_in_clock_xing_out_7, intInClockXingOut_7 \n connect auto.int_in_clock_xing_out_8, intInClockXingOut_8 \n connect auto.int_in_clock_xing_out_9, intInClockXingOut_9 \n connect auto.int_in_clock_xing_out_10, intInClockXingOut_10 \n connect auto.int_in_clock_xing_out_11, intInClockXingOut_11 \n connect clint.auto.in, auto.clint_in \n connect clint.io.rtcTick, tick \n connect childClock, clockNodeIn.clock \n connect childReset, clockNodeIn.reset \n connect clock, clockNodeIn.clock \n connect reset, clockNodeIn.reset \n\n\n extmodule plusarg_reader_250 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32\n\n\n\n extmodule plusarg_reader_251 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32"},"response":{"kind":"string","value":"module CLINTClockSinkDomain(\t// @[ClockDomain.scala:14:9]\n output auto_clint_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_clint_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_clint_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_clint_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_clint_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [11:0] auto_clint_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [25:0] auto_clint_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_clint_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_clint_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_clint_in_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_clint_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_clint_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_clint_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_clint_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [11:0] auto_clint_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_clint_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_11_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_11_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_10_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_10_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_9_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_9_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_8_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_8_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_7_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_7_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_6_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_6_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_5_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_5_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_4_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_4_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_3_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_3_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_2_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_2_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_1_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_1_sync_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_0_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_int_in_clock_xing_out_0_sync_1,\t// @[LazyModuleImp.scala:107:25]\n input auto_clock_in_clock,\t// @[LazyModuleImp.scala:107:25]\n input auto_clock_in_reset,\t// @[LazyModuleImp.scala:107:25]\n input tick,\t// @[CLINT.scala:115:20]\n output clock,\t// @[ClockDomain.scala:21:19]\n output reset\t// @[ClockDomain.scala:22:19]\n);\n\n wire _clint_auto_int_out_11_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_11_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_10_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_10_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_9_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_9_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_8_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_8_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_7_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_7_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_6_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_6_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_5_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_5_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_4_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_4_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_3_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_3_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_2_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_2_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_1_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_1_1;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_0_0;\t// @[CLINT.scala:112:48]\n wire _clint_auto_int_out_0_1;\t// @[CLINT.scala:112:48]\n CLINT clint (\t// @[CLINT.scala:112:48]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_int_out_11_0 (_clint_auto_int_out_11_0),\n .auto_int_out_11_1 (_clint_auto_int_out_11_1),\n .auto_int_out_10_0 (_clint_auto_int_out_10_0),\n .auto_int_out_10_1 (_clint_auto_int_out_10_1),\n .auto_int_out_9_0 (_clint_auto_int_out_9_0),\n .auto_int_out_9_1 (_clint_auto_int_out_9_1),\n .auto_int_out_8_0 (_clint_auto_int_out_8_0),\n .auto_int_out_8_1 (_clint_auto_int_out_8_1),\n .auto_int_out_7_0 (_clint_auto_int_out_7_0),\n .auto_int_out_7_1 (_clint_auto_int_out_7_1),\n .auto_int_out_6_0 (_clint_auto_int_out_6_0),\n .auto_int_out_6_1 (_clint_auto_int_out_6_1),\n .auto_int_out_5_0 (_clint_auto_int_out_5_0),\n .auto_int_out_5_1 (_clint_auto_int_out_5_1),\n .auto_int_out_4_0 (_clint_auto_int_out_4_0),\n .auto_int_out_4_1 (_clint_auto_int_out_4_1),\n .auto_int_out_3_0 (_clint_auto_int_out_3_0),\n .auto_int_out_3_1 (_clint_auto_int_out_3_1),\n .auto_int_out_2_0 (_clint_auto_int_out_2_0),\n .auto_int_out_2_1 (_clint_auto_int_out_2_1),\n .auto_int_out_1_0 (_clint_auto_int_out_1_0),\n .auto_int_out_1_1 (_clint_auto_int_out_1_1),\n .auto_int_out_0_0 (_clint_auto_int_out_0_0),\n .auto_int_out_0_1 (_clint_auto_int_out_0_1),\n .auto_in_a_ready (auto_clint_in_a_ready),\n .auto_in_a_valid (auto_clint_in_a_valid),\n .auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode),\n .auto_in_a_bits_param (auto_clint_in_a_bits_param),\n .auto_in_a_bits_size (auto_clint_in_a_bits_size),\n .auto_in_a_bits_source (auto_clint_in_a_bits_source),\n .auto_in_a_bits_address (auto_clint_in_a_bits_address),\n .auto_in_a_bits_mask (auto_clint_in_a_bits_mask),\n .auto_in_a_bits_data (auto_clint_in_a_bits_data),\n .auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt),\n .auto_in_d_ready (auto_clint_in_d_ready),\n .auto_in_d_valid (auto_clint_in_d_valid),\n .auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode),\n .auto_in_d_bits_size (auto_clint_in_d_bits_size),\n .auto_in_d_bits_source (auto_clint_in_d_bits_source),\n .auto_in_d_bits_data (auto_clint_in_d_bits_data),\n .io_rtcTick (tick)\n );\t// @[CLINT.scala:112:48]\n IntSyncCrossingSource_n1x2 intsource (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_0_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_0_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_0_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_0_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_1 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_1_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_1_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_1_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_1_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_2 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_2_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_2_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_2_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_2_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_3 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_3_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_3_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_3_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_3_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_4 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_4_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_4_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_4_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_4_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_5 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_5_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_5_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_5_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_5_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_6 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_6_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_6_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_6_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_6_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_7 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_7_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_7_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_7_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_7_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_8 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_8_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_8_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_8_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_8_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_9 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_9_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_9_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_9_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_9_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_10 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_10_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_10_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_10_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_10_sync_1)\n );\t// @[Crossing.scala:29:31]\n IntSyncCrossingSource_n1x2 intsource_11 (\t// @[Crossing.scala:29:31]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_in_0 (_clint_auto_int_out_11_0),\t// @[CLINT.scala:112:48]\n .auto_in_1 (_clint_auto_int_out_11_1),\t// @[CLINT.scala:112:48]\n .auto_out_sync_0 (auto_int_in_clock_xing_out_11_sync_0),\n .auto_out_sync_1 (auto_int_in_clock_xing_out_11_sync_1)\n );\t// @[Crossing.scala:29:31]\n assign clock = auto_clock_in_clock;\t// @[ClockDomain.scala:14:9]\n assign reset = auto_clock_in_reset;\t// @[ClockDomain.scala:14:9]\nendmodule"}}},{"rowIdx":32190,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter_4 : \n input clock : Clock \n input reset : Reset \n output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} \n\n\n reg s1_id : UInt, clock \n reg s2_id : UInt, clock \n connect s2_id, s1_id \n node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled) \n connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T \n node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid) \n connect io.mem.req.valid, _io_mem_req_valid_T \n connect io.requestor[0].req.ready, io.mem.req.ready \n node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0)) \n node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T) \n connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1 \n connect io.mem.req.bits, io.requestor[1].req.bits \n node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1)) \n connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T \n connect s1_id, UInt<1>(0h1) \n connect io.mem.s1_kill, io.requestor[1].s1_kill \n connect io.mem.s1_data, io.requestor[1].s1_data \n connect io.mem.s2_kill, io.requestor[1].s2_kill \n when io.requestor[0].req.valid : \n connect io.mem.req.bits, io.requestor[0].req.bits \n node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0)) \n connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1 \n connect s1_id, UInt<1>(0h0) \n node _T = eq(s1_id, UInt<1>(0h0)) \n when _T : \n connect io.mem.s1_kill, io.requestor[0].s1_kill \n connect io.mem.s1_data, io.requestor[0].s1_data \n node _T_1 = eq(s2_id, UInt<1>(0h0)) \n when _T_1 : \n connect io.mem.s2_kill, io.requestor[0].s2_kill \n node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0) \n node tag_hit = eq(_tag_hit_T, UInt<1>(0h0)) \n node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit) \n connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T \n connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt \n connect io.requestor[0].s2_gpa, io.mem.s2_gpa \n connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte \n connect io.requestor[0].ordered, io.mem.ordered \n connect io.requestor[0].store_pending, io.mem.store_pending \n connect io.requestor[0].perf, io.mem.perf \n node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0)) \n node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T) \n connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1 \n connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw \n connect io.requestor[0].s2_uncached, io.mem.s2_uncached \n connect io.requestor[0].s2_paddr, io.mem.s2_paddr \n connect io.requestor[0].clock_enabled, io.mem.clock_enabled \n connect io.requestor[0].resp.bits, io.mem.resp.bits \n node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) \n connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T \n connect io.requestor[0].replay_next, io.mem.replay_next \n node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0) \n node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1)) \n node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1) \n connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T \n connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt \n connect io.requestor[1].s2_gpa, io.mem.s2_gpa \n connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte \n connect io.requestor[1].ordered, io.mem.ordered \n connect io.requestor[1].store_pending, io.mem.store_pending \n connect io.requestor[1].perf, io.mem.perf \n node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1)) \n node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T) \n connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1 \n connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw \n connect io.requestor[1].s2_uncached, io.mem.s2_uncached \n connect io.requestor[1].s2_paddr, io.mem.s2_paddr \n connect io.requestor[1].clock_enabled, io.mem.clock_enabled \n connect io.requestor[1].resp.bits, io.mem.resp.bits \n node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) \n connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T \n connect io.requestor[1].replay_next, io.mem.replay_next"},"response":{"kind":"string","value":"module HellaCacheArbiter_4(\t// @[HellaCacheArbiter.scala:10:7]\n input clock,\t// @[HellaCacheArbiter.scala:10:7]\n input reset,\t// @[HellaCacheArbiter.scala:10:7]\n output io_requestor_0_req_ready,\t// @[HellaCacheArbiter.scala:12:14]\n input io_requestor_0_req_valid,\t// @[HellaCacheArbiter.scala:12:14]\n input [39:0] io_requestor_0_req_bits_addr,\t// @[HellaCacheArbiter.scala:12:14]\n input io_requestor_0_req_bits_dv,\t// @[HellaCacheArbiter.scala:12:14]\n input io_requestor_0_s1_kill,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_nack,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_nack_cause_raw,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_uncached,\t// @[HellaCacheArbiter.scala:12:14]\n output [31:0] io_requestor_0_s2_paddr,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_resp_valid,\t// @[HellaCacheArbiter.scala:12:14]\n output [39:0] io_requestor_0_resp_bits_addr,\t// @[HellaCacheArbiter.scala:12:14]\n output [7:0] io_requestor_0_resp_bits_tag,\t// @[HellaCacheArbiter.scala:12:14]\n output [4:0] io_requestor_0_resp_bits_cmd,\t// @[HellaCacheArbiter.scala:12:14]\n output [1:0] io_requestor_0_resp_bits_size,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_resp_bits_signed,\t// @[HellaCacheArbiter.scala:12:14]\n output [1:0] io_requestor_0_resp_bits_dprv,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_resp_bits_dv,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_0_resp_bits_data,\t// @[HellaCacheArbiter.scala:12:14]\n output [7:0] io_requestor_0_resp_bits_mask,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_resp_bits_replay,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_resp_bits_has_data,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_0_resp_bits_data_word_bypass,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_0_resp_bits_data_raw,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_0_resp_bits_store_data,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_replay_next,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_xcpt_ma_ld,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_xcpt_ma_st,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_xcpt_pf_ld,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_xcpt_pf_st,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_xcpt_ae_ld,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_s2_xcpt_ae_st,\t// @[HellaCacheArbiter.scala:12:14]\n output [39:0] io_requestor_0_s2_gpa,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_ordered,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_store_pending,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_acquire,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_release,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_grant,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_tlbMiss,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_blocked,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_canAcceptStoreThenLoad,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_canAcceptStoreThenRMW,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_canAcceptLoadThenLoad,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_storeBufferEmptyAfterLoad,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_0_perf_storeBufferEmptyAfterStore,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_req_ready,\t// @[HellaCacheArbiter.scala:12:14]\n input io_requestor_1_req_valid,\t// @[HellaCacheArbiter.scala:12:14]\n input [39:0] io_requestor_1_req_bits_addr,\t// @[HellaCacheArbiter.scala:12:14]\n input [7:0] io_requestor_1_req_bits_tag,\t// @[HellaCacheArbiter.scala:12:14]\n input [1:0] io_requestor_1_req_bits_dprv,\t// @[HellaCacheArbiter.scala:12:14]\n input io_requestor_1_req_bits_dv,\t// @[HellaCacheArbiter.scala:12:14]\n input [63:0] io_requestor_1_s1_data_data,\t// @[HellaCacheArbiter.scala:12:14]\n input [7:0] io_requestor_1_s1_data_mask,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_nack,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_nack_cause_raw,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_uncached,\t// @[HellaCacheArbiter.scala:12:14]\n output [31:0] io_requestor_1_s2_paddr,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_resp_valid,\t// @[HellaCacheArbiter.scala:12:14]\n output [39:0] io_requestor_1_resp_bits_addr,\t// @[HellaCacheArbiter.scala:12:14]\n output [7:0] io_requestor_1_resp_bits_tag,\t// @[HellaCacheArbiter.scala:12:14]\n output [4:0] io_requestor_1_resp_bits_cmd,\t// @[HellaCacheArbiter.scala:12:14]\n output [1:0] io_requestor_1_resp_bits_size,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_resp_bits_signed,\t// @[HellaCacheArbiter.scala:12:14]\n output [1:0] io_requestor_1_resp_bits_dprv,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_resp_bits_dv,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_1_resp_bits_data,\t// @[HellaCacheArbiter.scala:12:14]\n output [7:0] io_requestor_1_resp_bits_mask,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_resp_bits_replay,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_resp_bits_has_data,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_1_resp_bits_data_word_bypass,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_1_resp_bits_data_raw,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_requestor_1_resp_bits_store_data,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_replay_next,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_xcpt_ma_ld,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_xcpt_ma_st,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_xcpt_pf_ld,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_xcpt_pf_st,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_xcpt_ae_ld,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_s2_xcpt_ae_st,\t// @[HellaCacheArbiter.scala:12:14]\n output [39:0] io_requestor_1_s2_gpa,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_ordered,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_store_pending,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_acquire,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_release,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_grant,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_tlbMiss,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_blocked,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_canAcceptStoreThenLoad,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_canAcceptStoreThenRMW,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_canAcceptLoadThenLoad,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_storeBufferEmptyAfterLoad,\t// @[HellaCacheArbiter.scala:12:14]\n output io_requestor_1_perf_storeBufferEmptyAfterStore,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_req_ready,\t// @[HellaCacheArbiter.scala:12:14]\n output io_mem_req_valid,\t// @[HellaCacheArbiter.scala:12:14]\n output [39:0] io_mem_req_bits_addr,\t// @[HellaCacheArbiter.scala:12:14]\n output [7:0] io_mem_req_bits_tag,\t// @[HellaCacheArbiter.scala:12:14]\n output [1:0] io_mem_req_bits_dprv,\t// @[HellaCacheArbiter.scala:12:14]\n output io_mem_req_bits_dv,\t// @[HellaCacheArbiter.scala:12:14]\n output io_mem_req_bits_phys,\t// @[HellaCacheArbiter.scala:12:14]\n output io_mem_s1_kill,\t// @[HellaCacheArbiter.scala:12:14]\n output [63:0] io_mem_s1_data_data,\t// @[HellaCacheArbiter.scala:12:14]\n output [7:0] io_mem_s1_data_mask,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_nack,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_nack_cause_raw,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_uncached,\t// @[HellaCacheArbiter.scala:12:14]\n input [31:0] io_mem_s2_paddr,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_resp_valid,\t// @[HellaCacheArbiter.scala:12:14]\n input [39:0] io_mem_resp_bits_addr,\t// @[HellaCacheArbiter.scala:12:14]\n input [7:0] io_mem_resp_bits_tag,\t// @[HellaCacheArbiter.scala:12:14]\n input [4:0] io_mem_resp_bits_cmd,\t// @[HellaCacheArbiter.scala:12:14]\n input [1:0] io_mem_resp_bits_size,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_resp_bits_signed,\t// @[HellaCacheArbiter.scala:12:14]\n input [1:0] io_mem_resp_bits_dprv,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_resp_bits_dv,\t// @[HellaCacheArbiter.scala:12:14]\n input [63:0] io_mem_resp_bits_data,\t// @[HellaCacheArbiter.scala:12:14]\n input [7:0] io_mem_resp_bits_mask,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_resp_bits_replay,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_resp_bits_has_data,\t// @[HellaCacheArbiter.scala:12:14]\n input [63:0] io_mem_resp_bits_data_word_bypass,\t// @[HellaCacheArbiter.scala:12:14]\n input [63:0] io_mem_resp_bits_data_raw,\t// @[HellaCacheArbiter.scala:12:14]\n input [63:0] io_mem_resp_bits_store_data,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_replay_next,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_xcpt_ma_ld,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_xcpt_ma_st,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_xcpt_pf_ld,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_xcpt_pf_st,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_xcpt_ae_ld,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_s2_xcpt_ae_st,\t// @[HellaCacheArbiter.scala:12:14]\n input [39:0] io_mem_s2_gpa,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_ordered,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_store_pending,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_acquire,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_release,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_grant,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_tlbMiss,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_blocked,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_canAcceptStoreThenLoad,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_canAcceptStoreThenRMW,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_canAcceptLoadThenLoad,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_storeBufferEmptyAfterLoad,\t// @[HellaCacheArbiter.scala:12:14]\n input io_mem_perf_storeBufferEmptyAfterStore\t// @[HellaCacheArbiter.scala:12:14]\n);\n\n wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_requestor_1_req_bits_dprv_0 = io_requestor_1_req_bits_dprv;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_bits_dv_0 = io_requestor_1_req_bits_dv;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_req_ready_0 = io_mem_req_ready;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_nack_0 = io_mem_s2_nack;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_uncached_0 = io_mem_s2_uncached;\t// @[HellaCacheArbiter.scala:10:7]\n wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_resp_valid_0 = io_mem_resp_valid;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag;\t// @[HellaCacheArbiter.scala:10:7]\n wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_replay_next_0 = io_mem_replay_next;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_ordered_0 = io_mem_ordered;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_store_pending_0 = io_mem_store_pending;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_acquire_0 = io_mem_perf_acquire;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_release_0 = io_mem_perf_release;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_grant_0 = io_mem_perf_grant;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_blocked_0 = io_mem_perf_blocked;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore;\t// @[HellaCacheArbiter.scala:10:7]\n wire [8:0] _io_mem_req_bits_tag_T_1 = 9'h0;\t// @[HellaCacheArbiter.scala:34:35]\n wire [1:0] io_requestor_0_req_bits_dprv = 2'h1;\t// @[HellaCacheArbiter.scala:10:7, :12:14]\n wire [7:0] io_requestor_0_req_bits_tag = 8'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_0_req_bits_mask = 8'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_0_s1_data_mask = 8'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_1_req_bits_mask = 8'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_mem_req_bits_mask = 8'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_0_req_bits_data = 64'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_0_s1_data_data = 64'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_1_req_bits_data = 64'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_mem_req_bits_data = 64'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_requestor_0_req_bits_size = 2'h3;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_requestor_1_req_bits_size = 2'h3;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_mem_req_bits_size = 2'h3;\t// @[HellaCacheArbiter.scala:10:7]\n wire [4:0] io_requestor_0_req_bits_cmd = 5'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [4:0] io_requestor_1_req_bits_cmd = 5'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [4:0] io_mem_req_bits_cmd = 5'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_req_bits_phys = 1'h1;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_clock_enabled = 1'h1;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_clock_enabled = 1'h1;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_clock_enabled = 1'h1;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_req_bits_signed = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_req_bits_no_resp = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_req_bits_no_alloc = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_req_bits_no_xcpt = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_kill = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_gf_ld = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_gf_st = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_gpa_is_pte = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_keep_clock_enabled = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_bits_signed = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_bits_phys = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_bits_no_resp = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_bits_no_alloc = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_bits_no_xcpt = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s1_kill = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_kill = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_gf_ld = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_gf_st = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_gpa_is_pte = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_keep_clock_enabled = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_req_bits_signed = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_req_bits_no_resp = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_req_bits_no_alloc = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_req_bits_no_xcpt = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_kill = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_gf_ld = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_xcpt_gf_st = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s2_gpa_is_pte = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_keep_clock_enabled = 1'h0;\t// @[HellaCacheArbiter.scala:10:7]\n wire _io_mem_keep_clock_enabled_T = 1'h0;\t// @[HellaCacheArbiter.scala:23:81]\n wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire _io_requestor_0_s2_nack_T_1;\t// @[HellaCacheArbiter.scala:68:49]\n wire _io_requestor_0_resp_valid_T;\t// @[HellaCacheArbiter.scala:61:39]\n wire _io_requestor_1_req_ready_T_1;\t// @[HellaCacheArbiter.scala:28:64]\n wire _io_requestor_1_s2_nack_T_1;\t// @[HellaCacheArbiter.scala:68:49]\n wire _io_requestor_1_resp_valid_T;\t// @[HellaCacheArbiter.scala:61:39]\n wire io_requestor_0_req_ready_0 = io_mem_req_ready_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire _io_mem_req_valid_T;\t// @[HellaCacheArbiter.scala:25:63]\n wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_replay_next_0 = io_mem_replay_next_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_replay_next_0 = io_mem_replay_next_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_ordered_0 = io_mem_ordered_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_ordered_0 = io_mem_ordered_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_store_pending_0 = io_mem_store_pending_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_store_pending_0 = io_mem_store_pending_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_release_0 = io_mem_perf_release_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_release_0 = io_mem_perf_release_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_0_resp_bits_tag_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_resp_valid_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_0_s2_nack_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_req_ready_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_requestor_1_resp_bits_tag_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_resp_valid_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_requestor_1_s2_nack_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [39:0] io_mem_req_bits_addr_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_mem_req_bits_tag_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [1:0] io_mem_req_bits_dprv_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_req_bits_dv_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_req_valid_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [63:0] io_mem_s1_data_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire [7:0] io_mem_s1_data_mask_0;\t// @[HellaCacheArbiter.scala:10:7]\n wire io_mem_s1_kill_0;\t// @[HellaCacheArbiter.scala:10:7]\n reg s1_id;\t// @[HellaCacheArbiter.scala:20:20]\n reg s2_id;\t// @[HellaCacheArbiter.scala:21:24]\n wire _io_requestor_1_s2_nack_T = s2_id;\t// @[HellaCacheArbiter.scala:21:24, :68:58]\n assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0;\t// @[HellaCacheArbiter.scala:10:7, :25:63]\n assign io_mem_req_valid_0 = _io_mem_req_valid_T;\t// @[HellaCacheArbiter.scala:10:7, :25:63]\n wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0;\t// @[HellaCacheArbiter.scala:10:7, :28:67]\n assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T;\t// @[HellaCacheArbiter.scala:10:7, :28:{64,67}]\n assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1;\t// @[HellaCacheArbiter.scala:10:7, :28:64]\n wire [8:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1};\t// @[HellaCacheArbiter.scala:10:7, :34:35]\n assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0;\t// @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]\n assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_bits_dprv_0;\t// @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]\n assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : io_requestor_1_req_bits_dv_0;\t// @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]\n assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 8'h0 : _io_mem_req_bits_tag_T[7:0];\t// @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26]\n assign io_mem_s1_kill_0 = ~s1_id & io_requestor_0_s1_kill_0;\t// @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:{21,30}]\n assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0;\t// @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30]\n assign io_mem_s1_data_mask_0 = s1_id ? io_requestor_1_s1_data_mask_0 : 8'h0;\t// @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30]\n wire _io_requestor_0_s2_nack_T = ~s2_id;\t// @[HellaCacheArbiter.scala:21:24, :52:21, :68:58]\n wire _tag_hit_T = io_mem_resp_bits_tag_0[0];\t// @[HellaCacheArbiter.scala:10:7, :60:41]\n wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0];\t// @[HellaCacheArbiter.scala:10:7, :60:41]\n wire tag_hit = ~_tag_hit_T;\t// @[HellaCacheArbiter.scala:60:{41,57}]\n assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit;\t// @[HellaCacheArbiter.scala:10:7, :60:57, :61:39]\n assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T;\t// @[HellaCacheArbiter.scala:10:7, :61:39]\n assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T;\t// @[HellaCacheArbiter.scala:10:7, :68:{49,58}]\n assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1;\t// @[HellaCacheArbiter.scala:10:7, :68:49]\n wire [6:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1];\t// @[HellaCacheArbiter.scala:10:7, :74:45]\n wire [6:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1];\t// @[HellaCacheArbiter.scala:10:7, :74:45]\n assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T};\t// @[HellaCacheArbiter.scala:10:7, :74:{21,45}]\n wire tag_hit_1 = _tag_hit_T_1;\t// @[HellaCacheArbiter.scala:60:{41,57}]\n assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1;\t// @[HellaCacheArbiter.scala:10:7, :60:57, :61:39]\n assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T;\t// @[HellaCacheArbiter.scala:10:7, :61:39]\n assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T;\t// @[HellaCacheArbiter.scala:10:7, :68:{49,58}]\n assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1;\t// @[HellaCacheArbiter.scala:10:7, :68:49]\n assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T};\t// @[HellaCacheArbiter.scala:10:7, :74:{21,45}]\n always @(posedge clock) begin\t// @[HellaCacheArbiter.scala:10:7]\n s1_id <= ~io_requestor_0_req_valid_0;\t// @[HellaCacheArbiter.scala:10:7, :20:20, :28:67]\n s2_id <= s1_id;\t// @[HellaCacheArbiter.scala:20:20, :21:24]\n always @(posedge)\n assign io_requestor_0_req_ready = io_requestor_0_req_ready_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_replay_next = io_requestor_0_replay_next_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_ordered = io_requestor_0_ordered_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_store_pending = io_requestor_0_store_pending_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_release = io_requestor_0_perf_release_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_req_ready = io_requestor_1_req_ready_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_replay_next = io_requestor_1_replay_next_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_ordered = io_requestor_1_ordered_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_store_pending = io_requestor_1_store_pending_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_release = io_requestor_1_perf_release_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_req_valid = io_mem_req_valid_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_req_bits_addr = io_mem_req_bits_addr_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_req_bits_tag = io_mem_req_bits_tag_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_req_bits_dv = io_mem_req_bits_dv_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_req_bits_phys = io_mem_req_bits_phys_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_s1_kill = io_mem_s1_kill_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_s1_data_data = io_mem_s1_data_data_0;\t// @[HellaCacheArbiter.scala:10:7]\n assign io_mem_s1_data_mask = io_mem_s1_data_mask_0;\t// @[HellaCacheArbiter.scala:10:7]\nendmodule"}}},{"rowIdx":32191,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158 : \n input clock : Clock \n input reset : AsyncReset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _sync_2_T = bits(io.d, 0, 0) \n connect sync_2, _sync_2_T \n connect sync_0, sync_1 \n connect sync_1, sync_2 \n connect io.q, sync_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d = 1'h1;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire _sync_2_T = 1'h1;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h1;\t// @[SynchronizerReg.scala:51:87, :54:22, :68:19]\n end\n always @(posedge, posedge)"}}},{"rowIdx":32192,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_12 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<4>, q : UInt<4>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n node _output_T_2 = asAsyncReset(reset) \n node _output_T_3 = bits(io.d, 1, 1) \n inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_138 \n connect output_chain_1.clock, clock\n\n connect output_chain_1.reset, _output_T_2\n\n connect output_chain_1.io.d, _output_T_3 \n wire output_1 : UInt<1> \n connect output_1, output_chain_1.io.q \n node _output_T_4 = asAsyncReset(reset) \n node _output_T_5 = bits(io.d, 2, 2) \n inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_139 \n connect output_chain_2.clock, clock\n\n connect output_chain_2.reset, _output_T_4\n\n connect output_chain_2.io.d, _output_T_5 \n wire output_2 : UInt<1> \n connect output_2, output_chain_2.io.q \n node _output_T_6 = asAsyncReset(reset) \n node _output_T_7 = bits(io.d, 3, 3) \n inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_140 \n connect output_chain_3.clock, clock\n\n connect output_chain_3.reset, _output_T_6\n\n connect output_chain_3.io.d, _output_T_7 \n wire output_3 : UInt<1> \n connect output_3, output_chain_3.io.q \n node io_q_lo = cat(output_1, output_0) \n node io_q_hi = cat(output_3, output_2) \n node _io_q_T = cat(io_q_hi, io_q_lo) \n connect io.q, _io_q_T"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w4_d3_i0_12(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input [3:0] io_d,\t// @[ShiftReg.scala:36:14]\n output [3:0] io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire [3:0] io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_2 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_4 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_6 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire [3:0] _io_q_T;\t// @[SynchronizerReg.scala:90:14]\n wire [3:0] io_q_0;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T_1 = io_d_0[0];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire _output_T_3 = io_d_0[1];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_1;\t// @[ShiftReg.scala:48:24]\n wire _output_T_5 = io_d_0[2];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_2;\t// @[ShiftReg.scala:48:24]\n wire _output_T_7 = io_d_0[3];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_3;\t// @[ShiftReg.scala:48:24]\n wire [1:0] io_q_lo = {output_1, output_0};\t// @[SynchronizerReg.scala:90:14]\n wire [1:0] io_q_hi = {output_3, output_2};\t// @[SynchronizerReg.scala:90:14]\n assign _io_q_T = {io_q_hi, io_q_lo};\t// @[SynchronizerReg.scala:90:14]\n assign io_q_0 = _io_q_T;\t// @[SynchronizerReg.scala:80:7, :90:14]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_138 output_chain_1 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_2),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_3),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_1)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_139 output_chain_2 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_4),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_5),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_2)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_140 output_chain_3 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_6),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_7),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_3)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":32193,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module MacUnit_196 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} \n\n\n node _io_out_d_T = mul(io.in_a, io.in_b) \n node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) \n node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) \n node _io_out_d_T_3 = asSInt(_io_out_d_T_2) \n connect io.out_d, _io_out_d_T_3"},"response":{"kind":"string","value":"module MacUnit_196(\t// @[PE.scala:14:7]\n input clock,\t// @[PE.scala:14:7]\n input reset,\t// @[PE.scala:14:7]\n input [7:0] io_in_a,\t// @[PE.scala:16:14]\n input [7:0] io_in_b,\t// @[PE.scala:16:14]\n input [19:0] io_in_c,\t// @[PE.scala:16:14]\n output [19:0] io_out_d\t// @[PE.scala:16:14]\n);\n\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:14:7]\n wire [7:0] io_in_b_0 = io_in_b;\t// @[PE.scala:14:7]\n wire [19:0] io_in_c_0 = io_in_c;\t// @[PE.scala:14:7]\n wire [19:0] _io_out_d_T_3;\t// @[Arithmetic.scala:93:54]\n wire [19:0] io_out_d_0;\t// @[PE.scala:14:7]\n wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0};\t// @[PE.scala:14:7]\n wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0};\t// @[PE.scala:14:7]\n wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0];\t// @[Arithmetic.scala:93:54]\n assign _io_out_d_T_3 = _io_out_d_T_2;\t// @[Arithmetic.scala:93:54]\n assign io_out_d_0 = _io_out_d_T_3;\t// @[PE.scala:14:7]\n assign io_out_d = io_out_d_0;\t// @[PE.scala:14:7]\nendmodule"}}},{"rowIdx":32194,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_43 : \n output io : { flip in : UInt<1>, out : UInt<1>} \n input clock : Clock \n input reset : AsyncReset \n\n\n inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_53 \n connect io_out_sink_valid.clock, clock\n\n connect io_out_sink_valid.reset, reset\n\n connect io_out_sink_valid.io.d, io.in \n wire _io_out_WIRE : UInt<1> \n connect _io_out_WIRE, io_out_sink_valid.io.q \n connect io.out, _io_out_WIRE"},"response":{"kind":"string","value":"module AsyncValidSync_43(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_53 io_out_sink_valid (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":32195,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64_mulAddZ31 : \n input clock : Clock \n input reset : Reset \n output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} \n\n\n inst divSqrtRecF64ToRaw of DivSqrtRecF64ToRaw_mulAddZ31 \n connect divSqrtRecF64ToRaw.clock, clock\n\n connect divSqrtRecF64ToRaw.reset, reset\n\n connect io.inReady_div, divSqrtRecF64ToRaw.io.inReady_div \n connect io.inReady_sqrt, divSqrtRecF64ToRaw.io.inReady_sqrt \n connect divSqrtRecF64ToRaw.io.inValid, io.inValid \n connect divSqrtRecF64ToRaw.io.sqrtOp, io.sqrtOp \n connect divSqrtRecF64ToRaw.io.a, io.a \n connect divSqrtRecF64ToRaw.io.b, io.b \n connect divSqrtRecF64ToRaw.io.roundingMode, io.roundingMode \n connect io.usingMulAdd, divSqrtRecF64ToRaw.io.usingMulAdd \n connect io.latchMulAddA_0, divSqrtRecF64ToRaw.io.latchMulAddA_0 \n connect io.mulAddA_0, divSqrtRecF64ToRaw.io.mulAddA_0 \n connect io.latchMulAddB_0, divSqrtRecF64ToRaw.io.latchMulAddB_0 \n connect io.mulAddB_0, divSqrtRecF64ToRaw.io.mulAddB_0 \n connect io.mulAddC_2, divSqrtRecF64ToRaw.io.mulAddC_2 \n connect divSqrtRecF64ToRaw.io.mulAddResult_3, io.mulAddResult_3 \n connect io.outValid_div, divSqrtRecF64ToRaw.io.rawOutValid_div \n connect io.outValid_sqrt, divSqrtRecF64ToRaw.io.rawOutValid_sqrt \n inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_1 \n connect roundRawFNToRecFN.io.invalidExc, divSqrtRecF64ToRaw.io.invalidExc \n connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecF64ToRaw.io.infiniteExc \n connect roundRawFNToRecFN.io.in.sig, divSqrtRecF64ToRaw.io.rawOut.sig \n connect roundRawFNToRecFN.io.in.sExp, divSqrtRecF64ToRaw.io.rawOut.sExp \n connect roundRawFNToRecFN.io.in.sign, divSqrtRecF64ToRaw.io.rawOut.sign \n connect roundRawFNToRecFN.io.in.isZero, divSqrtRecF64ToRaw.io.rawOut.isZero \n connect roundRawFNToRecFN.io.in.isInf, divSqrtRecF64ToRaw.io.rawOut.isInf \n connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecF64ToRaw.io.rawOut.isNaN \n connect roundRawFNToRecFN.io.roundingMode, divSqrtRecF64ToRaw.io.roundingModeOut \n connect roundRawFNToRecFN.io.detectTininess, io.detectTininess \n connect io.out, roundRawFNToRecFN.io.out \n connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags"},"response":{"kind":"string","value":"module DivSqrtRecF64_mulAddZ31(\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n input clock,\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n input reset,\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n output io_inReady_div,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output io_inReady_sqrt,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n input io_inValid,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n input io_sqrtOp,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n input [64:0] io_a,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n input [64:0] io_b,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n input [2:0] io_roundingMode,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output [3:0] io_usingMulAdd,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output io_latchMulAddA_0,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output [53:0] io_mulAddA_0,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output io_latchMulAddB_0,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output [53:0] io_mulAddB_0,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output [104:0] io_mulAddC_2,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n input [104:0] io_mulAddResult_3,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output io_outValid_div,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output io_outValid_sqrt,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output [64:0] io_out,\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n output [4:0] io_exceptionFlags\t// @[DivSqrtRecF64_mulAddZ31.scala:721:16]\n);\n\n wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire _divSqrtRecF64ToRaw_io_invalidExc;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire _divSqrtRecF64ToRaw_io_infiniteExc;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire _divSqrtRecF64ToRaw_io_rawOut_isNaN;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire _divSqrtRecF64ToRaw_io_rawOut_isInf;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire _divSqrtRecF64ToRaw_io_rawOut_isZero;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire _divSqrtRecF64ToRaw_io_rawOut_sign;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig;\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n wire io_inValid_0 = io_inValid;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire io_sqrtOp_0 = io_sqrtOp;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [64:0] io_a_0 = io_a;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [64:0] io_b_0 = io_b;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [2:0] io_roundingMode_0 = io_roundingMode;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire io_detectTininess = 1'h0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7, :721:16, :775:15]\n wire io_inReady_div_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire io_inReady_sqrt_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [3:0] io_usingMulAdd_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire io_latchMulAddA_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [53:0] io_mulAddA_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire io_latchMulAddB_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [53:0] io_mulAddB_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [104:0] io_mulAddC_2_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire io_outValid_div_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire io_outValid_sqrt_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [64:0] io_out_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n wire [4:0] io_exceptionFlags_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n DivSqrtRecF64ToRaw_mulAddZ31 divSqrtRecF64ToRaw (\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .clock (clock),\n .reset (reset),\n .io_inReady_div (io_inReady_div_0),\n .io_inReady_sqrt (io_inReady_sqrt_0),\n .io_inValid (io_inValid_0),\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n .io_sqrtOp (io_sqrtOp_0),\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n .io_a (io_a_0),\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n .io_b (io_b_0),\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n .io_roundingMode (io_roundingMode_0),\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n .io_usingMulAdd (io_usingMulAdd_0),\n .io_latchMulAddA_0 (io_latchMulAddA_0_0),\n .io_mulAddA_0 (io_mulAddA_0_0),\n .io_latchMulAddB_0 (io_latchMulAddB_0_0),\n .io_mulAddB_0 (io_mulAddB_0_0),\n .io_mulAddC_2 (io_mulAddC_2_0),\n .io_mulAddResult_3 (io_mulAddResult_3_0),\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n .io_rawOutValid_div (io_outValid_div_0),\n .io_rawOutValid_sqrt (io_outValid_sqrt_0),\n .io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut),\n .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),\n .io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),\n .io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),\n .io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),\n .io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),\n .io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),\n .io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig)\n );\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n RoundRawFNToRecFN_e11_s53_1 roundRawFNToRecFN (\t// @[DivSqrtRecF64_mulAddZ31.scala:775:15]\n .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut),\t// @[DivSqrtRecF64_mulAddZ31.scala:751:36]\n .io_out (io_out_0),\n .io_exceptionFlags (io_exceptionFlags_0)\n );\t// @[DivSqrtRecF64_mulAddZ31.scala:775:15]\n assign io_inReady_div = io_inReady_div_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_inReady_sqrt = io_inReady_sqrt_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_usingMulAdd = io_usingMulAdd_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_latchMulAddA_0 = io_latchMulAddA_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_mulAddA_0 = io_mulAddA_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_latchMulAddB_0 = io_latchMulAddB_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_mulAddB_0 = io_mulAddB_0_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_mulAddC_2 = io_mulAddC_2_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_outValid_div = io_outValid_div_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_outValid_sqrt = io_outValid_sqrt_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_out = io_out_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\n assign io_exceptionFlags = io_exceptionFlags_0;\t// @[DivSqrtRecF64_mulAddZ31.scala:719:7]\nendmodule"}}},{"rowIdx":32196,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) \n node _source_ok_T = shr(io.in.a.bits.source, 11) \n node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) \n node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) \n node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) \n node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T_5 \n node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 10, 0) \n node _T_4 = shr(io.in.a.bits.source, 11) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = leq(UInt<1>(0h0), uncommonBits) \n node _T_7 = and(_T_5, _T_6) \n node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) \n node _T_9 = and(_T_7, _T_8) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_12 = cvt(_T_11) \n node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) \n node _T_14 = asSInt(_T_13) \n node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) \n node _T_16 = or(_T_10, _T_15) \n node _T_17 = asUInt(reset) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n when _T_18 : \n node _T_19 = eq(_T_16, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_16, UInt<1>(0h1), \"\") : assert_1 \n node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_20 : \n node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_23 = and(_T_21, _T_22) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) \n node _T_24 = shr(io.in.a.bits.source, 11) \n node _T_25 = eq(_T_24, UInt<1>(0h0)) \n node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_27 = and(_T_25, _T_26) \n node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) \n node _T_29 = and(_T_27, _T_28) \n node _T_30 = and(_T_23, _T_29) \n node _T_31 = or(UInt<1>(0h0), _T_30) \n node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_34 = cvt(_T_33) \n node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) \n node _T_36 = asSInt(_T_35) \n node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) \n node _T_38 = and(_T_32, _T_37) \n node _T_39 = or(UInt<1>(0h0), _T_38) \n node _T_40 = and(_T_31, _T_39) \n node _T_41 = asUInt(reset) \n node _T_42 = eq(_T_41, UInt<1>(0h0)) \n when _T_42 : \n node _T_43 = eq(_T_40, UInt<1>(0h0)) \n when _T_43 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_40, UInt<1>(0h1), \"\") : assert_2 \n node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_46 = and(_T_44, _T_45) \n node _T_47 = or(UInt<1>(0h0), _T_46) \n node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_49 = cvt(_T_48) \n node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) \n node _T_51 = asSInt(_T_50) \n node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) \n node _T_53 = and(_T_47, _T_52) \n node _T_54 = or(UInt<1>(0h0), _T_53) \n node _T_55 = and(UInt<1>(0h0), _T_54) \n node _T_56 = asUInt(reset) \n node _T_57 = eq(_T_56, UInt<1>(0h0)) \n when _T_57 : \n node _T_58 = eq(_T_55, UInt<1>(0h0)) \n when _T_58 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_55, UInt<1>(0h1), \"\") : assert_3 \n node _T_59 = asUInt(reset) \n node _T_60 = eq(_T_59, UInt<1>(0h0)) \n when _T_60 : \n node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_61 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_63 = asUInt(reset) \n node _T_64 = eq(_T_63, UInt<1>(0h0)) \n when _T_64 : \n node _T_65 = eq(_T_62, UInt<1>(0h0)) \n when _T_65 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_62, UInt<1>(0h1), \"\") : assert_5 \n node _T_66 = asUInt(reset) \n node _T_67 = eq(_T_66, UInt<1>(0h0)) \n when _T_67 : \n node _T_68 = eq(is_aligned, UInt<1>(0h0)) \n when _T_68 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_70 = asUInt(reset) \n node _T_71 = eq(_T_70, UInt<1>(0h0)) \n when _T_71 : \n node _T_72 = eq(_T_69, UInt<1>(0h0)) \n when _T_72 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_69, UInt<1>(0h1), \"\") : assert_7 \n node _T_73 = not(io.in.a.bits.mask) \n node _T_74 = eq(_T_73, UInt<1>(0h0)) \n node _T_75 = asUInt(reset) \n node _T_76 = eq(_T_75, UInt<1>(0h0)) \n when _T_76 : \n node _T_77 = eq(_T_74, UInt<1>(0h0)) \n when _T_77 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_74, UInt<1>(0h1), \"\") : assert_8 \n node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_79 = asUInt(reset) \n node _T_80 = eq(_T_79, UInt<1>(0h0)) \n when _T_80 : \n node _T_81 = eq(_T_78, UInt<1>(0h0)) \n when _T_81 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_78, UInt<1>(0h1), \"\") : assert_9 \n node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_82 : \n node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_85 = and(_T_83, _T_84) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) \n node _T_86 = shr(io.in.a.bits.source, 11) \n node _T_87 = eq(_T_86, UInt<1>(0h0)) \n node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_89 = and(_T_87, _T_88) \n node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) \n node _T_91 = and(_T_89, _T_90) \n node _T_92 = and(_T_85, _T_91) \n node _T_93 = or(UInt<1>(0h0), _T_92) \n node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_96 = cvt(_T_95) \n node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) \n node _T_98 = asSInt(_T_97) \n node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) \n node _T_100 = and(_T_94, _T_99) \n node _T_101 = or(UInt<1>(0h0), _T_100) \n node _T_102 = and(_T_93, _T_101) \n node _T_103 = asUInt(reset) \n node _T_104 = eq(_T_103, UInt<1>(0h0)) \n when _T_104 : \n node _T_105 = eq(_T_102, UInt<1>(0h0)) \n when _T_105 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_102, UInt<1>(0h1), \"\") : assert_10 \n node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_108 = and(_T_106, _T_107) \n node _T_109 = or(UInt<1>(0h0), _T_108) \n node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_111 = cvt(_T_110) \n node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) \n node _T_113 = asSInt(_T_112) \n node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) \n node _T_115 = and(_T_109, _T_114) \n node _T_116 = or(UInt<1>(0h0), _T_115) \n node _T_117 = and(UInt<1>(0h0), _T_116) \n node _T_118 = asUInt(reset) \n node _T_119 = eq(_T_118, UInt<1>(0h0)) \n when _T_119 : \n node _T_120 = eq(_T_117, UInt<1>(0h0)) \n when _T_120 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_117, UInt<1>(0h1), \"\") : assert_11 \n node _T_121 = asUInt(reset) \n node _T_122 = eq(_T_121, UInt<1>(0h0)) \n when _T_122 : \n node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_123 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_125 = asUInt(reset) \n node _T_126 = eq(_T_125, UInt<1>(0h0)) \n when _T_126 : \n node _T_127 = eq(_T_124, UInt<1>(0h0)) \n when _T_127 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_124, UInt<1>(0h1), \"\") : assert_13 \n node _T_128 = asUInt(reset) \n node _T_129 = eq(_T_128, UInt<1>(0h0)) \n when _T_129 : \n node _T_130 = eq(is_aligned, UInt<1>(0h0)) \n when _T_130 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_132 = asUInt(reset) \n node _T_133 = eq(_T_132, UInt<1>(0h0)) \n when _T_133 : \n node _T_134 = eq(_T_131, UInt<1>(0h0)) \n when _T_134 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_131, UInt<1>(0h1), \"\") : assert_15 \n node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_136 = asUInt(reset) \n node _T_137 = eq(_T_136, UInt<1>(0h0)) \n when _T_137 : \n node _T_138 = eq(_T_135, UInt<1>(0h0)) \n when _T_138 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_135, UInt<1>(0h1), \"\") : assert_16 \n node _T_139 = not(io.in.a.bits.mask) \n node _T_140 = eq(_T_139, UInt<1>(0h0)) \n node _T_141 = asUInt(reset) \n node _T_142 = eq(_T_141, UInt<1>(0h0)) \n when _T_142 : \n node _T_143 = eq(_T_140, UInt<1>(0h0)) \n when _T_143 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_140, UInt<1>(0h1), \"\") : assert_17 \n node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_145 = asUInt(reset) \n node _T_146 = eq(_T_145, UInt<1>(0h0)) \n when _T_146 : \n node _T_147 = eq(_T_144, UInt<1>(0h0)) \n when _T_147 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_144, UInt<1>(0h1), \"\") : assert_18 \n node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_148 : \n node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_151 = and(_T_149, _T_150) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) \n node _T_152 = shr(io.in.a.bits.source, 11) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_155 = and(_T_153, _T_154) \n node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) \n node _T_157 = and(_T_155, _T_156) \n node _T_158 = and(_T_151, _T_157) \n node _T_159 = or(UInt<1>(0h0), _T_158) \n node _T_160 = asUInt(reset) \n node _T_161 = eq(_T_160, UInt<1>(0h0)) \n when _T_161 : \n node _T_162 = eq(_T_159, UInt<1>(0h0)) \n when _T_162 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_159, UInt<1>(0h1), \"\") : assert_19 \n node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_165 = and(_T_163, _T_164) \n node _T_166 = or(UInt<1>(0h0), _T_165) \n node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_168 = cvt(_T_167) \n node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) \n node _T_170 = asSInt(_T_169) \n node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) \n node _T_172 = and(_T_166, _T_171) \n node _T_173 = or(UInt<1>(0h0), _T_172) \n node _T_174 = asUInt(reset) \n node _T_175 = eq(_T_174, UInt<1>(0h0)) \n when _T_175 : \n node _T_176 = eq(_T_173, UInt<1>(0h0)) \n when _T_176 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_173, UInt<1>(0h1), \"\") : assert_20 \n node _T_177 = asUInt(reset) \n node _T_178 = eq(_T_177, UInt<1>(0h0)) \n when _T_178 : \n node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_179 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_180 = asUInt(reset) \n node _T_181 = eq(_T_180, UInt<1>(0h0)) \n when _T_181 : \n node _T_182 = eq(is_aligned, UInt<1>(0h0)) \n when _T_182 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_184 = asUInt(reset) \n node _T_185 = eq(_T_184, UInt<1>(0h0)) \n when _T_185 : \n node _T_186 = eq(_T_183, UInt<1>(0h0)) \n when _T_186 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_183, UInt<1>(0h1), \"\") : assert_23 \n node _T_187 = eq(io.in.a.bits.mask, mask) \n node _T_188 = asUInt(reset) \n node _T_189 = eq(_T_188, UInt<1>(0h0)) \n when _T_189 : \n node _T_190 = eq(_T_187, UInt<1>(0h0)) \n when _T_190 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_187, UInt<1>(0h1), \"\") : assert_24 \n node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_192 = asUInt(reset) \n node _T_193 = eq(_T_192, UInt<1>(0h0)) \n when _T_193 : \n node _T_194 = eq(_T_191, UInt<1>(0h0)) \n when _T_194 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_191, UInt<1>(0h1), \"\") : assert_25 \n node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_195 : \n node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_198 = and(_T_196, _T_197) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) \n node _T_199 = shr(io.in.a.bits.source, 11) \n node _T_200 = eq(_T_199, UInt<1>(0h0)) \n node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_202 = and(_T_200, _T_201) \n node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) \n node _T_204 = and(_T_202, _T_203) \n node _T_205 = and(_T_198, _T_204) \n node _T_206 = or(UInt<1>(0h0), _T_205) \n node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_209 = cvt(_T_208) \n node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) \n node _T_211 = asSInt(_T_210) \n node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) \n node _T_213 = and(_T_207, _T_212) \n node _T_214 = or(UInt<1>(0h0), _T_213) \n node _T_215 = and(_T_206, _T_214) \n node _T_216 = asUInt(reset) \n node _T_217 = eq(_T_216, UInt<1>(0h0)) \n when _T_217 : \n node _T_218 = eq(_T_215, UInt<1>(0h0)) \n when _T_218 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_215, UInt<1>(0h1), \"\") : assert_26 \n node _T_219 = asUInt(reset) \n node _T_220 = eq(_T_219, UInt<1>(0h0)) \n when _T_220 : \n node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_221 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_222 = asUInt(reset) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n when _T_223 : \n node _T_224 = eq(is_aligned, UInt<1>(0h0)) \n when _T_224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_226 = asUInt(reset) \n node _T_227 = eq(_T_226, UInt<1>(0h0)) \n when _T_227 : \n node _T_228 = eq(_T_225, UInt<1>(0h0)) \n when _T_228 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_225, UInt<1>(0h1), \"\") : assert_29 \n node _T_229 = eq(io.in.a.bits.mask, mask) \n node _T_230 = asUInt(reset) \n node _T_231 = eq(_T_230, UInt<1>(0h0)) \n when _T_231 : \n node _T_232 = eq(_T_229, UInt<1>(0h0)) \n when _T_232 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_229, UInt<1>(0h1), \"\") : assert_30 \n node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_233 : \n node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_236 = and(_T_234, _T_235) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) \n node _T_237 = shr(io.in.a.bits.source, 11) \n node _T_238 = eq(_T_237, UInt<1>(0h0)) \n node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_240 = and(_T_238, _T_239) \n node _T_241 = leq(uncommonBits_5, UInt<11>(0h40f)) \n node _T_242 = and(_T_240, _T_241) \n node _T_243 = and(_T_236, _T_242) \n node _T_244 = or(UInt<1>(0h0), _T_243) \n node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_247 = cvt(_T_246) \n node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) \n node _T_249 = asSInt(_T_248) \n node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) \n node _T_251 = and(_T_245, _T_250) \n node _T_252 = or(UInt<1>(0h0), _T_251) \n node _T_253 = and(_T_244, _T_252) \n node _T_254 = asUInt(reset) \n node _T_255 = eq(_T_254, UInt<1>(0h0)) \n when _T_255 : \n node _T_256 = eq(_T_253, UInt<1>(0h0)) \n when _T_256 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_253, UInt<1>(0h1), \"\") : assert_31 \n node _T_257 = asUInt(reset) \n node _T_258 = eq(_T_257, UInt<1>(0h0)) \n when _T_258 : \n node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_259 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_260 = asUInt(reset) \n node _T_261 = eq(_T_260, UInt<1>(0h0)) \n when _T_261 : \n node _T_262 = eq(is_aligned, UInt<1>(0h0)) \n when _T_262 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_264 = asUInt(reset) \n node _T_265 = eq(_T_264, UInt<1>(0h0)) \n when _T_265 : \n node _T_266 = eq(_T_263, UInt<1>(0h0)) \n when _T_266 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_263, UInt<1>(0h1), \"\") : assert_34 \n node _T_267 = not(mask) \n node _T_268 = and(io.in.a.bits.mask, _T_267) \n node _T_269 = eq(_T_268, UInt<1>(0h0)) \n node _T_270 = asUInt(reset) \n node _T_271 = eq(_T_270, UInt<1>(0h0)) \n when _T_271 : \n node _T_272 = eq(_T_269, UInt<1>(0h0)) \n when _T_272 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_269, UInt<1>(0h1), \"\") : assert_35 \n node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_273 : \n node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_276 = and(_T_274, _T_275) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) \n node _T_277 = shr(io.in.a.bits.source, 11) \n node _T_278 = eq(_T_277, UInt<1>(0h0)) \n node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_280 = and(_T_278, _T_279) \n node _T_281 = leq(uncommonBits_6, UInt<11>(0h40f)) \n node _T_282 = and(_T_280, _T_281) \n node _T_283 = and(_T_276, _T_282) \n node _T_284 = or(UInt<1>(0h0), _T_283) \n node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_287 = cvt(_T_286) \n node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) \n node _T_289 = asSInt(_T_288) \n node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) \n node _T_291 = and(_T_285, _T_290) \n node _T_292 = or(UInt<1>(0h0), _T_291) \n node _T_293 = and(_T_284, _T_292) \n node _T_294 = asUInt(reset) \n node _T_295 = eq(_T_294, UInt<1>(0h0)) \n when _T_295 : \n node _T_296 = eq(_T_293, UInt<1>(0h0)) \n when _T_296 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_293, UInt<1>(0h1), \"\") : assert_36 \n node _T_297 = asUInt(reset) \n node _T_298 = eq(_T_297, UInt<1>(0h0)) \n when _T_298 : \n node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_299 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_300 = asUInt(reset) \n node _T_301 = eq(_T_300, UInt<1>(0h0)) \n when _T_301 : \n node _T_302 = eq(is_aligned, UInt<1>(0h0)) \n when _T_302 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_304 = asUInt(reset) \n node _T_305 = eq(_T_304, UInt<1>(0h0)) \n when _T_305 : \n node _T_306 = eq(_T_303, UInt<1>(0h0)) \n when _T_306 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_303, UInt<1>(0h1), \"\") : assert_39 \n node _T_307 = eq(io.in.a.bits.mask, mask) \n node _T_308 = asUInt(reset) \n node _T_309 = eq(_T_308, UInt<1>(0h0)) \n when _T_309 : \n node _T_310 = eq(_T_307, UInt<1>(0h0)) \n when _T_310 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_307, UInt<1>(0h1), \"\") : assert_40 \n node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_311 : \n node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_314 = and(_T_312, _T_313) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) \n node _T_315 = shr(io.in.a.bits.source, 11) \n node _T_316 = eq(_T_315, UInt<1>(0h0)) \n node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_318 = and(_T_316, _T_317) \n node _T_319 = leq(uncommonBits_7, UInt<11>(0h40f)) \n node _T_320 = and(_T_318, _T_319) \n node _T_321 = and(_T_314, _T_320) \n node _T_322 = or(UInt<1>(0h0), _T_321) \n node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_325 = cvt(_T_324) \n node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) \n node _T_327 = asSInt(_T_326) \n node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) \n node _T_329 = and(_T_323, _T_328) \n node _T_330 = or(UInt<1>(0h0), _T_329) \n node _T_331 = and(_T_322, _T_330) \n node _T_332 = asUInt(reset) \n node _T_333 = eq(_T_332, UInt<1>(0h0)) \n when _T_333 : \n node _T_334 = eq(_T_331, UInt<1>(0h0)) \n when _T_334 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_331, UInt<1>(0h1), \"\") : assert_41 \n node _T_335 = asUInt(reset) \n node _T_336 = eq(_T_335, UInt<1>(0h0)) \n when _T_336 : \n node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_337 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_338 = asUInt(reset) \n node _T_339 = eq(_T_338, UInt<1>(0h0)) \n when _T_339 : \n node _T_340 = eq(is_aligned, UInt<1>(0h0)) \n when _T_340 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_342 = asUInt(reset) \n node _T_343 = eq(_T_342, UInt<1>(0h0)) \n when _T_343 : \n node _T_344 = eq(_T_341, UInt<1>(0h0)) \n when _T_344 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_341, UInt<1>(0h1), \"\") : assert_44 \n node _T_345 = eq(io.in.a.bits.mask, mask) \n node _T_346 = asUInt(reset) \n node _T_347 = eq(_T_346, UInt<1>(0h0)) \n when _T_347 : \n node _T_348 = eq(_T_345, UInt<1>(0h0)) \n when _T_348 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_345, UInt<1>(0h1), \"\") : assert_45 \n node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_349 : \n node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_352 = and(_T_350, _T_351) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) \n node _T_353 = shr(io.in.a.bits.source, 11) \n node _T_354 = eq(_T_353, UInt<1>(0h0)) \n node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_356 = and(_T_354, _T_355) \n node _T_357 = leq(uncommonBits_8, UInt<11>(0h40f)) \n node _T_358 = and(_T_356, _T_357) \n node _T_359 = and(_T_352, _T_358) \n node _T_360 = or(UInt<1>(0h0), _T_359) \n node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_363 = cvt(_T_362) \n node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) \n node _T_365 = asSInt(_T_364) \n node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) \n node _T_367 = and(_T_361, _T_366) \n node _T_368 = or(UInt<1>(0h0), _T_367) \n node _T_369 = and(_T_360, _T_368) \n node _T_370 = asUInt(reset) \n node _T_371 = eq(_T_370, UInt<1>(0h0)) \n when _T_371 : \n node _T_372 = eq(_T_369, UInt<1>(0h0)) \n when _T_372 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_369, UInt<1>(0h1), \"\") : assert_46 \n node _T_373 = asUInt(reset) \n node _T_374 = eq(_T_373, UInt<1>(0h0)) \n when _T_374 : \n node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_375 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_376 = asUInt(reset) \n node _T_377 = eq(_T_376, UInt<1>(0h0)) \n when _T_377 : \n node _T_378 = eq(is_aligned, UInt<1>(0h0)) \n when _T_378 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_380 = asUInt(reset) \n node _T_381 = eq(_T_380, UInt<1>(0h0)) \n when _T_381 : \n node _T_382 = eq(_T_379, UInt<1>(0h0)) \n when _T_382 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_379, UInt<1>(0h1), \"\") : assert_49 \n node _T_383 = eq(io.in.a.bits.mask, mask) \n node _T_384 = asUInt(reset) \n node _T_385 = eq(_T_384, UInt<1>(0h0)) \n when _T_385 : \n node _T_386 = eq(_T_383, UInt<1>(0h0)) \n when _T_386 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_383, UInt<1>(0h1), \"\") : assert_50 \n node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_388 = asUInt(reset) \n node _T_389 = eq(_T_388, UInt<1>(0h0)) \n when _T_389 : \n node _T_390 = eq(_T_387, UInt<1>(0h0)) \n when _T_390 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_387, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_392 = asUInt(reset) \n node _T_393 = eq(_T_392, UInt<1>(0h0)) \n when _T_393 : \n node _T_394 = eq(_T_391, UInt<1>(0h0)) \n when _T_394 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_391, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) \n node _source_ok_T_6 = shr(io.in.d.bits.source, 11) \n node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) \n node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) \n node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) \n node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_11 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_395 : \n node _T_396 = asUInt(reset) \n node _T_397 = eq(_T_396, UInt<1>(0h0)) \n when _T_397 : \n node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_398 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_400 = asUInt(reset) \n node _T_401 = eq(_T_400, UInt<1>(0h0)) \n when _T_401 : \n node _T_402 = eq(_T_399, UInt<1>(0h0)) \n when _T_402 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_399, UInt<1>(0h1), \"\") : assert_54 \n node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_404 = asUInt(reset) \n node _T_405 = eq(_T_404, UInt<1>(0h0)) \n when _T_405 : \n node _T_406 = eq(_T_403, UInt<1>(0h0)) \n when _T_406 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_403, UInt<1>(0h1), \"\") : assert_55 \n node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_408 = asUInt(reset) \n node _T_409 = eq(_T_408, UInt<1>(0h0)) \n when _T_409 : \n node _T_410 = eq(_T_407, UInt<1>(0h0)) \n when _T_410 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_407, UInt<1>(0h1), \"\") : assert_56 \n node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_412 = asUInt(reset) \n node _T_413 = eq(_T_412, UInt<1>(0h0)) \n when _T_413 : \n node _T_414 = eq(_T_411, UInt<1>(0h0)) \n when _T_414 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_411, UInt<1>(0h1), \"\") : assert_57 \n node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_415 : \n node _T_416 = asUInt(reset) \n node _T_417 = eq(_T_416, UInt<1>(0h0)) \n when _T_417 : \n node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_418 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_419 = asUInt(reset) \n node _T_420 = eq(_T_419, UInt<1>(0h0)) \n when _T_420 : \n node _T_421 = eq(sink_ok, UInt<1>(0h0)) \n when _T_421 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_423 = asUInt(reset) \n node _T_424 = eq(_T_423, UInt<1>(0h0)) \n when _T_424 : \n node _T_425 = eq(_T_422, UInt<1>(0h0)) \n when _T_425 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_422, UInt<1>(0h1), \"\") : assert_60 \n node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_427 = asUInt(reset) \n node _T_428 = eq(_T_427, UInt<1>(0h0)) \n when _T_428 : \n node _T_429 = eq(_T_426, UInt<1>(0h0)) \n when _T_429 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_426, UInt<1>(0h1), \"\") : assert_61 \n node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_431 = asUInt(reset) \n node _T_432 = eq(_T_431, UInt<1>(0h0)) \n when _T_432 : \n node _T_433 = eq(_T_430, UInt<1>(0h0)) \n when _T_433 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_430, UInt<1>(0h1), \"\") : assert_62 \n node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_435 = asUInt(reset) \n node _T_436 = eq(_T_435, UInt<1>(0h0)) \n when _T_436 : \n node _T_437 = eq(_T_434, UInt<1>(0h0)) \n when _T_437 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_434, UInt<1>(0h1), \"\") : assert_63 \n node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_439 = or(UInt<1>(0h0), _T_438) \n node _T_440 = asUInt(reset) \n node _T_441 = eq(_T_440, UInt<1>(0h0)) \n when _T_441 : \n node _T_442 = eq(_T_439, UInt<1>(0h0)) \n when _T_442 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_439, UInt<1>(0h1), \"\") : assert_64 \n node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_443 : \n node _T_444 = asUInt(reset) \n node _T_445 = eq(_T_444, UInt<1>(0h0)) \n when _T_445 : \n node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_446 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_447 = asUInt(reset) \n node _T_448 = eq(_T_447, UInt<1>(0h0)) \n when _T_448 : \n node _T_449 = eq(sink_ok, UInt<1>(0h0)) \n when _T_449 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_451 = asUInt(reset) \n node _T_452 = eq(_T_451, UInt<1>(0h0)) \n when _T_452 : \n node _T_453 = eq(_T_450, UInt<1>(0h0)) \n when _T_453 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_450, UInt<1>(0h1), \"\") : assert_67 \n node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_455 = asUInt(reset) \n node _T_456 = eq(_T_455, UInt<1>(0h0)) \n when _T_456 : \n node _T_457 = eq(_T_454, UInt<1>(0h0)) \n when _T_457 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_454, UInt<1>(0h1), \"\") : assert_68 \n node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_459 = asUInt(reset) \n node _T_460 = eq(_T_459, UInt<1>(0h0)) \n when _T_460 : \n node _T_461 = eq(_T_458, UInt<1>(0h0)) \n when _T_461 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_458, UInt<1>(0h1), \"\") : assert_69 \n node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_463 = or(_T_462, io.in.d.bits.corrupt) \n node _T_464 = asUInt(reset) \n node _T_465 = eq(_T_464, UInt<1>(0h0)) \n when _T_465 : \n node _T_466 = eq(_T_463, UInt<1>(0h0)) \n when _T_466 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_463, UInt<1>(0h1), \"\") : assert_70 \n node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_468 = or(UInt<1>(0h0), _T_467) \n node _T_469 = asUInt(reset) \n node _T_470 = eq(_T_469, UInt<1>(0h0)) \n when _T_470 : \n node _T_471 = eq(_T_468, UInt<1>(0h0)) \n when _T_471 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_468, UInt<1>(0h1), \"\") : assert_71 \n node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_472 : \n node _T_473 = asUInt(reset) \n node _T_474 = eq(_T_473, UInt<1>(0h0)) \n when _T_474 : \n node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_475 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_477 = asUInt(reset) \n node _T_478 = eq(_T_477, UInt<1>(0h0)) \n when _T_478 : \n node _T_479 = eq(_T_476, UInt<1>(0h0)) \n when _T_479 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_476, UInt<1>(0h1), \"\") : assert_73 \n node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_481 = asUInt(reset) \n node _T_482 = eq(_T_481, UInt<1>(0h0)) \n when _T_482 : \n node _T_483 = eq(_T_480, UInt<1>(0h0)) \n when _T_483 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_480, UInt<1>(0h1), \"\") : assert_74 \n node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_485 = or(UInt<1>(0h0), _T_484) \n node _T_486 = asUInt(reset) \n node _T_487 = eq(_T_486, UInt<1>(0h0)) \n when _T_487 : \n node _T_488 = eq(_T_485, UInt<1>(0h0)) \n when _T_488 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_485, UInt<1>(0h1), \"\") : assert_75 \n node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_489 : \n node _T_490 = asUInt(reset) \n node _T_491 = eq(_T_490, UInt<1>(0h0)) \n when _T_491 : \n node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_492 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_494 = asUInt(reset) \n node _T_495 = eq(_T_494, UInt<1>(0h0)) \n when _T_495 : \n node _T_496 = eq(_T_493, UInt<1>(0h0)) \n when _T_496 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_493, UInt<1>(0h1), \"\") : assert_77 \n node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_498 = or(_T_497, io.in.d.bits.corrupt) \n node _T_499 = asUInt(reset) \n node _T_500 = eq(_T_499, UInt<1>(0h0)) \n when _T_500 : \n node _T_501 = eq(_T_498, UInt<1>(0h0)) \n when _T_501 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_498, UInt<1>(0h1), \"\") : assert_78 \n node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_503 = or(UInt<1>(0h0), _T_502) \n node _T_504 = asUInt(reset) \n node _T_505 = eq(_T_504, UInt<1>(0h0)) \n when _T_505 : \n node _T_506 = eq(_T_503, UInt<1>(0h0)) \n when _T_506 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_503, UInt<1>(0h1), \"\") : assert_79 \n node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_507 : \n node _T_508 = asUInt(reset) \n node _T_509 = eq(_T_508, UInt<1>(0h0)) \n when _T_509 : \n node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_510 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_512 = asUInt(reset) \n node _T_513 = eq(_T_512, UInt<1>(0h0)) \n when _T_513 : \n node _T_514 = eq(_T_511, UInt<1>(0h0)) \n when _T_514 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_511, UInt<1>(0h1), \"\") : assert_81 \n node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_516 = asUInt(reset) \n node _T_517 = eq(_T_516, UInt<1>(0h0)) \n when _T_517 : \n node _T_518 = eq(_T_515, UInt<1>(0h0)) \n when _T_518 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_515, UInt<1>(0h1), \"\") : assert_82 \n node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_520 = or(UInt<1>(0h0), _T_519) \n node _T_521 = asUInt(reset) \n node _T_522 = eq(_T_521, UInt<1>(0h0)) \n when _T_522 : \n node _T_523 = eq(_T_520, UInt<1>(0h0)) \n when _T_523 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_520, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<17>(0h0) \n connect _WIRE.bits.source, UInt<11>(0h0) \n connect _WIRE.bits.size, UInt<2>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_525 = asUInt(reset) \n node _T_526 = eq(_T_525, UInt<1>(0h0)) \n when _T_526 : \n node _T_527 = eq(_T_524, UInt<1>(0h0)) \n when _T_527 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_524, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<17>(0h0) \n connect _WIRE_2.bits.source, UInt<11>(0h0) \n connect _WIRE_2.bits.size, UInt<2>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_529 = asUInt(reset) \n node _T_530 = eq(_T_529, UInt<1>(0h0)) \n when _T_530 : \n node _T_531 = eq(_T_528, UInt<1>(0h0)) \n when _T_531 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_528, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_533 = asUInt(reset) \n node _T_534 = eq(_T_533, UInt<1>(0h0)) \n when _T_534 : \n node _T_535 = eq(_T_532, UInt<1>(0h0)) \n when _T_535 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_532, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_536 = eq(a_first, UInt<1>(0h0)) \n node _T_537 = and(io.in.a.valid, _T_536) \n when _T_537 : \n node _T_538 = eq(io.in.a.bits.opcode, opcode) \n node _T_539 = asUInt(reset) \n node _T_540 = eq(_T_539, UInt<1>(0h0)) \n when _T_540 : \n node _T_541 = eq(_T_538, UInt<1>(0h0)) \n when _T_541 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_538, UInt<1>(0h1), \"\") : assert_87 \n node _T_542 = eq(io.in.a.bits.param, param) \n node _T_543 = asUInt(reset) \n node _T_544 = eq(_T_543, UInt<1>(0h0)) \n when _T_544 : \n node _T_545 = eq(_T_542, UInt<1>(0h0)) \n when _T_545 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_542, UInt<1>(0h1), \"\") : assert_88 \n node _T_546 = eq(io.in.a.bits.size, size) \n node _T_547 = asUInt(reset) \n node _T_548 = eq(_T_547, UInt<1>(0h0)) \n when _T_548 : \n node _T_549 = eq(_T_546, UInt<1>(0h0)) \n when _T_549 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_546, UInt<1>(0h1), \"\") : assert_89 \n node _T_550 = eq(io.in.a.bits.source, source) \n node _T_551 = asUInt(reset) \n node _T_552 = eq(_T_551, UInt<1>(0h0)) \n when _T_552 : \n node _T_553 = eq(_T_550, UInt<1>(0h0)) \n when _T_553 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_550, UInt<1>(0h1), \"\") : assert_90 \n node _T_554 = eq(io.in.a.bits.address, address) \n node _T_555 = asUInt(reset) \n node _T_556 = eq(_T_555, UInt<1>(0h0)) \n when _T_556 : \n node _T_557 = eq(_T_554, UInt<1>(0h0)) \n when _T_557 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_554, UInt<1>(0h1), \"\") : assert_91 \n node _T_558 = and(io.in.a.ready, io.in.a.valid) \n node _T_559 = and(_T_558, a_first) \n when _T_559 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_560 = eq(d_first, UInt<1>(0h0)) \n node _T_561 = and(io.in.d.valid, _T_560) \n when _T_561 : \n node _T_562 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_563 = asUInt(reset) \n node _T_564 = eq(_T_563, UInt<1>(0h0)) \n when _T_564 : \n node _T_565 = eq(_T_562, UInt<1>(0h0)) \n when _T_565 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_562, UInt<1>(0h1), \"\") : assert_92 \n node _T_566 = eq(io.in.d.bits.param, param_1) \n node _T_567 = asUInt(reset) \n node _T_568 = eq(_T_567, UInt<1>(0h0)) \n when _T_568 : \n node _T_569 = eq(_T_566, UInt<1>(0h0)) \n when _T_569 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_566, UInt<1>(0h1), \"\") : assert_93 \n node _T_570 = eq(io.in.d.bits.size, size_1) \n node _T_571 = asUInt(reset) \n node _T_572 = eq(_T_571, UInt<1>(0h0)) \n when _T_572 : \n node _T_573 = eq(_T_570, UInt<1>(0h0)) \n when _T_573 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_570, UInt<1>(0h1), \"\") : assert_94 \n node _T_574 = eq(io.in.d.bits.source, source_1) \n node _T_575 = asUInt(reset) \n node _T_576 = eq(_T_575, UInt<1>(0h0)) \n when _T_576 : \n node _T_577 = eq(_T_574, UInt<1>(0h0)) \n when _T_577 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_574, UInt<1>(0h1), \"\") : assert_95 \n node _T_578 = eq(io.in.d.bits.sink, sink) \n node _T_579 = asUInt(reset) \n node _T_580 = eq(_T_579, UInt<1>(0h0)) \n when _T_580 : \n node _T_581 = eq(_T_578, UInt<1>(0h0)) \n when _T_581 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_578, UInt<1>(0h1), \"\") : assert_96 \n node _T_582 = eq(io.in.d.bits.denied, denied) \n node _T_583 = asUInt(reset) \n node _T_584 = eq(_T_583, UInt<1>(0h0)) \n when _T_584 : \n node _T_585 = eq(_T_582, UInt<1>(0h0)) \n when _T_585 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_582, UInt<1>(0h1), \"\") : assert_97 \n node _T_586 = and(io.in.d.ready, io.in.d.valid) \n node _T_587 = and(_T_586, d_first) \n when _T_587 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) \n regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) \n regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<1040> \n connect a_set, UInt<1040>(0h0) \n wire a_set_wo_ready : UInt<1040> \n connect a_set_wo_ready, UInt<1040>(0h0) \n wire a_opcodes_set : UInt<4160> \n connect a_opcodes_set, UInt<4160>(0h0) \n wire a_sizes_set : UInt<4160> \n connect a_sizes_set, UInt<4160>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<3> \n connect a_sizes_set_interm, UInt<3>(0h0) \n node _T_588 = and(io.in.a.valid, a_first_1) \n node _T_589 = and(_T_588, UInt<1>(0h1)) \n when _T_589 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_590 = and(io.in.a.ready, io.in.a.valid) \n node _T_591 = and(_T_590, a_first_1) \n node _T_592 = and(_T_591, UInt<1>(0h1)) \n when _T_592 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_593 = dshr(inflight, io.in.a.bits.source) \n node _T_594 = bits(_T_593, 0, 0) \n node _T_595 = eq(_T_594, UInt<1>(0h0)) \n node _T_596 = asUInt(reset) \n node _T_597 = eq(_T_596, UInt<1>(0h0)) \n when _T_597 : \n node _T_598 = eq(_T_595, UInt<1>(0h0)) \n when _T_598 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_595, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<1040> \n connect d_clr, UInt<1040>(0h0) \n wire d_clr_wo_ready : UInt<1040> \n connect d_clr_wo_ready, UInt<1040>(0h0) \n wire d_opcodes_clr : UInt<4160> \n connect d_opcodes_clr, UInt<4160>(0h0) \n wire d_sizes_clr : UInt<4160> \n connect d_sizes_clr, UInt<4160>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_599 = and(io.in.d.valid, d_first_1) \n node _T_600 = and(_T_599, UInt<1>(0h1)) \n node _T_601 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_602 = and(_T_600, _T_601) \n when _T_602 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_603 = and(io.in.d.ready, io.in.d.valid) \n node _T_604 = and(_T_603, d_first_1) \n node _T_605 = and(_T_604, UInt<1>(0h1)) \n node _T_606 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_607 = and(_T_605, _T_606) \n when _T_607 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_608 = and(io.in.d.valid, d_first_1) \n node _T_609 = and(_T_608, UInt<1>(0h1)) \n node _T_610 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_611 = and(_T_609, _T_610) \n when _T_611 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_612 = dshr(inflight, io.in.d.bits.source) \n node _T_613 = bits(_T_612, 0, 0) \n node _T_614 = or(_T_613, same_cycle_resp) \n node _T_615 = asUInt(reset) \n node _T_616 = eq(_T_615, UInt<1>(0h0)) \n when _T_616 : \n node _T_617 = eq(_T_614, UInt<1>(0h0)) \n when _T_617 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_614, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_620 = or(_T_618, _T_619) \n node _T_621 = asUInt(reset) \n node _T_622 = eq(_T_621, UInt<1>(0h0)) \n when _T_622 : \n node _T_623 = eq(_T_620, UInt<1>(0h0)) \n when _T_623 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_620, UInt<1>(0h1), \"\") : assert_100 \n node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_625 = asUInt(reset) \n node _T_626 = eq(_T_625, UInt<1>(0h0)) \n when _T_626 : \n node _T_627 = eq(_T_624, UInt<1>(0h0)) \n when _T_627 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_624, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_630 = or(_T_628, _T_629) \n node _T_631 = asUInt(reset) \n node _T_632 = eq(_T_631, UInt<1>(0h0)) \n when _T_632 : \n node _T_633 = eq(_T_630, UInt<1>(0h0)) \n when _T_633 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_630, UInt<1>(0h1), \"\") : assert_102 \n node _T_634 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_635 = asUInt(reset) \n node _T_636 = eq(_T_635, UInt<1>(0h0)) \n when _T_636 : \n node _T_637 = eq(_T_634, UInt<1>(0h0)) \n when _T_637 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_634, UInt<1>(0h1), \"\") : assert_103 \n node _T_638 = and(io.in.d.valid, d_first_1) \n node _T_639 = and(_T_638, a_first_1) \n node _T_640 = and(_T_639, io.in.a.valid) \n node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_642 = and(_T_640, _T_641) \n node _T_643 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_644 = and(_T_642, _T_643) \n when _T_644 : \n node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_646 = or(_T_645, io.in.a.ready) \n node _T_647 = asUInt(reset) \n node _T_648 = eq(_T_647, UInt<1>(0h0)) \n when _T_648 : \n node _T_649 = eq(_T_646, UInt<1>(0h0)) \n when _T_649 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_646, UInt<1>(0h1), \"\") : assert_104 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_111 \n node _T_650 = orr(inflight) \n node _T_651 = eq(_T_650, UInt<1>(0h0)) \n node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_653 = or(_T_651, _T_652) \n node _T_654 = lt(watchdog, plusarg_reader.out) \n node _T_655 = or(_T_653, _T_654) \n node _T_656 = asUInt(reset) \n node _T_657 = eq(_T_656, UInt<1>(0h0)) \n when _T_657 : \n node _T_658 = eq(_T_655, UInt<1>(0h0)) \n when _T_658 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_655, UInt<1>(0h1), \"\") : assert_105 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_659 = and(io.in.a.ready, io.in.a.valid) \n node _T_660 = and(io.in.d.ready, io.in.d.valid) \n node _T_661 = or(_T_659, _T_660) \n when _T_661 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) \n regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) \n regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<17>(0h0) \n connect _c_first_WIRE.bits.source, UInt<11>(0h0) \n connect _c_first_WIRE.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<1040> \n connect c_set, UInt<1040>(0h0) \n wire c_set_wo_ready : UInt<1040> \n connect c_set_wo_ready, UInt<1040>(0h0) \n wire c_opcodes_set : UInt<4160> \n connect c_opcodes_set, UInt<4160>(0h0) \n wire c_sizes_set : UInt<4160> \n connect c_sizes_set, UInt<4160>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<3> \n connect c_sizes_set_interm, UInt<3>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<17>(0h0) \n connect _WIRE_6.bits.source, UInt<11>(0h0) \n connect _WIRE_6.bits.size, UInt<2>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_662 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<17>(0h0) \n connect _WIRE_8.bits.source, UInt<11>(0h0) \n connect _WIRE_8.bits.size, UInt<2>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_665 = and(_T_663, _T_664) \n node _T_666 = and(_T_662, _T_665) \n when _T_666 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<17>(0h0) \n connect _WIRE_10.bits.source, UInt<11>(0h0) \n connect _WIRE_10.bits.size, UInt<2>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_668 = and(_T_667, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<17>(0h0) \n connect _WIRE_12.bits.source, UInt<11>(0h0) \n connect _WIRE_12.bits.size, UInt<2>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_671 = and(_T_669, _T_670) \n node _T_672 = and(_T_668, _T_671) \n when _T_672 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<17>(0h0) \n connect _c_set_WIRE.bits.source, UInt<11>(0h0) \n connect _c_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<17>(0h0) \n connect _WIRE_14.bits.source, UInt<11>(0h0) \n connect _WIRE_14.bits.size, UInt<2>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_674 = bits(_T_673, 0, 0) \n node _T_675 = eq(_T_674, UInt<1>(0h0)) \n node _T_676 = asUInt(reset) \n node _T_677 = eq(_T_676, UInt<1>(0h0)) \n when _T_677 : \n node _T_678 = eq(_T_675, UInt<1>(0h0)) \n when _T_678 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_675, UInt<1>(0h1), \"\") : assert_106 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<1040> \n connect d_clr_1, UInt<1040>(0h0) \n wire d_clr_wo_ready_1 : UInt<1040> \n connect d_clr_wo_ready_1, UInt<1040>(0h0) \n wire d_opcodes_clr_1 : UInt<4160> \n connect d_opcodes_clr_1, UInt<4160>(0h0) \n wire d_sizes_clr_1 : UInt<4160> \n connect d_sizes_clr_1, UInt<4160>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_679 = and(io.in.d.valid, d_first_2) \n node _T_680 = and(_T_679, UInt<1>(0h1)) \n node _T_681 = and(_T_680, d_release_ack_1) \n when _T_681 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_682 = and(io.in.d.ready, io.in.d.valid) \n node _T_683 = and(_T_682, d_first_2) \n node _T_684 = and(_T_683, UInt<1>(0h1)) \n node _T_685 = and(_T_684, d_release_ack_1) \n when _T_685 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_686 = and(io.in.d.valid, d_first_2) \n node _T_687 = and(_T_686, UInt<1>(0h1)) \n node _T_688 = and(_T_687, d_release_ack_1) \n when _T_688 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_689 = dshr(inflight_1, io.in.d.bits.source) \n node _T_690 = bits(_T_689, 0, 0) \n node _T_691 = or(_T_690, same_cycle_resp_1) \n node _T_692 = asUInt(reset) \n node _T_693 = eq(_T_692, UInt<1>(0h0)) \n when _T_693 : \n node _T_694 = eq(_T_691, UInt<1>(0h0)) \n when _T_694 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_691, UInt<1>(0h1), \"\") : assert_107 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<17>(0h0) \n connect _WIRE_16.bits.source, UInt<11>(0h0) \n connect _WIRE_16.bits.size, UInt<2>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_696 = asUInt(reset) \n node _T_697 = eq(_T_696, UInt<1>(0h0)) \n when _T_697 : \n node _T_698 = eq(_T_695, UInt<1>(0h0)) \n when _T_698 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_695, UInt<1>(0h1), \"\") : assert_108 \n else :\n\n node _T_699 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_700 = asUInt(reset) \n node _T_701 = eq(_T_700, UInt<1>(0h0)) \n when _T_701 : \n node _T_702 = eq(_T_699, UInt<1>(0h0)) \n when _T_702 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_699, UInt<1>(0h1), \"\") : assert_109 \n node _T_703 = and(io.in.d.valid, d_first_2) \n node _T_704 = and(_T_703, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<17>(0h0) \n connect _WIRE_18.bits.source, UInt<11>(0h0) \n connect _WIRE_18.bits.size, UInt<2>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_705 = and(_T_704, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<17>(0h0) \n connect _WIRE_20.bits.source, UInt<11>(0h0) \n connect _WIRE_20.bits.size, UInt<2>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_707 = and(_T_705, _T_706) \n node _T_708 = and(_T_707, d_release_ack_1) \n node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_710 = and(_T_708, _T_709) \n when _T_710 : \n node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<17>(0h0) \n connect _WIRE_22.bits.source, UInt<11>(0h0) \n connect _WIRE_22.bits.size, UInt<2>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_712 = or(_T_711, _WIRE_23.ready) \n node _T_713 = asUInt(reset) \n node _T_714 = eq(_T_713, UInt<1>(0h0)) \n when _T_714 : \n node _T_715 = eq(_T_712, UInt<1>(0h0)) \n when _T_715 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_712, UInt<1>(0h1), \"\") : assert_110 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_112 \n node _T_716 = orr(inflight_1) \n node _T_717 = eq(_T_716, UInt<1>(0h0)) \n node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_719 = or(_T_717, _T_718) \n node _T_720 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_721 = or(_T_719, _T_720) \n node _T_722 = asUInt(reset) \n node _T_723 = eq(_T_722, UInt<1>(0h0)) \n when _T_723 : \n node _T_724 = eq(_T_721, UInt<1>(0h0)) \n when _T_724 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_721, UInt<1>(0h1), \"\") : assert_111 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<17>(0h0) \n connect _WIRE_24.bits.source, UInt<11>(0h0) \n connect _WIRE_24.bits.size, UInt<2>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_726 = and(io.in.d.ready, io.in.d.valid) \n node _T_727 = or(_T_725, _T_726) \n when _T_727 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_55(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [10:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [16:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [10:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _source_ok_T_6 = 1'h0;\t// @[Parameters.scala:54:10]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire a_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire a_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_release_ack = 1'h0;\t// @[Monitor.scala:673:46]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire c_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_first_count_T = 1'h0;\t// @[Edges.scala:234:27]\n wire c_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_counter_T = 1'h0;\t// @[Edges.scala:236:21]\n wire d_first_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire d_release_ack_1 = 1'h0;\t// @[Monitor.scala:783:46]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _source_ok_T_7 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _a_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire d_first_beats1_opdata = 1'h1;\t// @[Edges.scala:106:36]\n wire _d_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _a_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire d_first_beats1_opdata_1 = 1'h1;\t// @[Edges.scala:106:36]\n wire _d_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire c_first_counter1 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire d_first_beats1_opdata_2 = 1'h1;\t// @[Edges.scala:106:36]\n wire _d_first_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_2 = 1'h1;\t// @[Edges.scala:232:33]\n wire [1:0] _c_first_counter1_T = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_d_bits_param = 2'h0;\t// @[Monitor.scala:36:7]\n wire [1:0] _c_first_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] io_in_d_bits_opcode = 3'h1;\t// @[Monitor.scala:36:7]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_sizes_set_interm_T_1 = 3'h1;\t// @[Monitor.scala:766:59]\n wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;\t// @[Monitor.scala:815:62]\n wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;\t// @[Monitor.scala:816:58]\n wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;\t// @[Monitor.scala:814:46]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_first_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_first_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_first_WIRE_2_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_first_WIRE_3_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_set_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_set_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0;\t// @[Bundles.scala:265:74]\n wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_first_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_first_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_first_WIRE_2_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_first_WIRE_3_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_set_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_set_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0;\t// @[Bundles.scala:265:74]\n wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_beats1_decode_T_2 = 3'h0;\t// @[package.scala:243:46]\n wire [2:0] c_sizes_set_interm = 3'h0;\t// @[Monitor.scala:755:40]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_T = 3'h0;\t// @[Monitor.scala:766:51]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [4159:0] c_opcodes_set = 4160'h0;\t// @[Monitor.scala:740:34]\n wire [4159:0] c_sizes_set = 4160'h0;\t// @[Monitor.scala:741:34]\n wire [4159:0] d_opcodes_clr_1 = 4160'h0;\t// @[Monitor.scala:776:34]\n wire [4159:0] d_sizes_clr_1 = 4160'h0;\t// @[Monitor.scala:777:34]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [1039:0] c_set = 1040'h0;\t// @[Monitor.scala:738:34]\n wire [1039:0] c_set_wo_ready = 1040'h0;\t// @[Monitor.scala:739:34]\n wire [1039:0] d_clr_1 = 1040'h0;\t// @[Monitor.scala:774:34]\n wire [1039:0] d_clr_wo_ready_1 = 1040'h0;\t// @[Monitor.scala:775:34]\n wire [16385:0] _c_sizes_set_T_1 = 16386'h0;\t// @[Monitor.scala:768:52]\n wire [13:0] _c_opcodes_set_T = 14'h0;\t// @[Monitor.scala:767:79]\n wire [13:0] _c_sizes_set_T = 14'h0;\t// @[Monitor.scala:768:77]\n wire [16386:0] _c_opcodes_set_T_1 = 16387'h0;\t// @[Monitor.scala:767:54]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [2047:0] _c_set_wo_ready_T = 2048'h1;\t// @[OneHot.scala:58:35]\n wire [2047:0] _c_set_T = 2048'h1;\t// @[OneHot.scala:58:35]\n wire [2:0] _c_first_beats1_decode_T_1 = 3'h7;\t// @[package.scala:243:76]\n wire [5:0] _c_first_beats1_decode_T = 6'h7;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_4;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 17'h0;\t// @[Edges.scala:21:{16,24}]\n wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0};\t// @[Misc.scala:202:34]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [10:0] uncommonBits = _uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_1 = _uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_2 = _uncommonBits_T_2;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_3 = _uncommonBits_T_3;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_4 = _uncommonBits_T_4;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_5 = _uncommonBits_T_5;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_6 = _uncommonBits_T_6;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_7 = _uncommonBits_T_7;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] uncommonBits_8 = _uncommonBits_T_8;\t// @[Parameters.scala:52:{29,56}]\n wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_10;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_659;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_659;\t// @[Decoupled.scala:51:35]\n wire a_first_done = _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n wire _a_first_last_T = a_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1 = _a_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~a_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T = ~a_first & a_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [1:0] size;\t// @[Monitor.scala:389:22]\n reg [10:0] source;\t// @[Monitor.scala:390:22]\n reg [16:0] address;\t// @[Monitor.scala:391:22]\n wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_727;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_727;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_727;\t// @[Decoupled.scala:51:35]\n wire d_first_done = _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n wire _d_first_last_T = d_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1 = _d_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire d_first = ~d_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T = ~d_first & d_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg [10:0] source_1;\t// @[Monitor.scala:541:22]\n reg [1039:0] inflight;\t// @[Monitor.scala:614:27]\n reg [4159:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [4159:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire a_first_done_1 = _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n wire _a_first_last_T_2 = a_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1_1 = _a_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire a_first_1 = ~a_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_first_done_1 = _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_2 = d_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_1 = _d_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire d_first_1 = ~d_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [1039:0] a_set;\t// @[Monitor.scala:626:34]\n wire [1039:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [4159:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [4159:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [13:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [13:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [13:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [13:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [13:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [13:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [13:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [13:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [2:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [2047:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [2047:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire _T_592 = _T_659 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [13:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [13:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [1039:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [1039:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [4159:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [4159:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _T_638 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_4;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_4;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_4;\t// @[OneHot.scala:58:35]\n wire [2047:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_4;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire _T_605 = _T_727 & d_first_1;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0;\t// @[OneHot.scala:58:35]\n wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0;\t// @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]\n wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0;\t// @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [1039:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [1039:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [1039:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [1039:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [4159:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [4159:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire d_first_done_2 = _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_4 = d_first_counter_2;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_2 = _d_first_counter1_T_2[0];\t// @[Edges.scala:230:28]\n wire d_first_2 = ~d_first_counter_2;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [1039:0] _inflight_T_5 = _inflight_T_3;\t// @[Monitor.scala:814:{35,44}]\n wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3;\t// @[Monitor.scala:815:{43,60}]\n wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3;\t// @[Monitor.scala:816:{41,56}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":32197,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_112 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_200 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_112(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_200 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":32198,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c_5 : \n input clock : Clock \n input reset : Reset \n output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} \n\n\n wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} \n invalidate anonIn.e.bits.sink \n invalidate anonIn.e.valid \n invalidate anonIn.e.ready \n invalidate anonIn.d.bits.corrupt \n invalidate anonIn.d.bits.data \n invalidate anonIn.d.bits.denied \n invalidate anonIn.d.bits.sink \n invalidate anonIn.d.bits.source \n invalidate anonIn.d.bits.size \n invalidate anonIn.d.bits.param \n invalidate anonIn.d.bits.opcode \n invalidate anonIn.d.valid \n invalidate anonIn.d.ready \n invalidate anonIn.c.bits.corrupt \n invalidate anonIn.c.bits.data \n invalidate anonIn.c.bits.address \n invalidate anonIn.c.bits.source \n invalidate anonIn.c.bits.size \n invalidate anonIn.c.bits.param \n invalidate anonIn.c.bits.opcode \n invalidate anonIn.c.valid \n invalidate anonIn.c.ready \n invalidate anonIn.b.bits.corrupt \n invalidate anonIn.b.bits.data \n invalidate anonIn.b.bits.mask \n invalidate anonIn.b.bits.address \n invalidate anonIn.b.bits.source \n invalidate anonIn.b.bits.size \n invalidate anonIn.b.bits.param \n invalidate anonIn.b.bits.opcode \n invalidate anonIn.b.valid \n invalidate anonIn.b.ready \n invalidate anonIn.a.bits.corrupt \n invalidate anonIn.a.bits.data \n invalidate anonIn.a.bits.mask \n invalidate anonIn.a.bits.address \n invalidate anonIn.a.bits.source \n invalidate anonIn.a.bits.size \n invalidate anonIn.a.bits.param \n invalidate anonIn.a.bits.opcode \n invalidate anonIn.a.valid \n invalidate anonIn.a.ready \n wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} \n invalidate anonIn_1.d.bits.corrupt \n invalidate anonIn_1.d.bits.data \n invalidate anonIn_1.d.bits.denied \n invalidate anonIn_1.d.bits.sink \n invalidate anonIn_1.d.bits.source \n invalidate anonIn_1.d.bits.size \n invalidate anonIn_1.d.bits.param \n invalidate anonIn_1.d.bits.opcode \n invalidate anonIn_1.d.valid \n invalidate anonIn_1.d.ready \n invalidate anonIn_1.a.bits.corrupt \n invalidate anonIn_1.a.bits.data \n invalidate anonIn_1.a.bits.mask \n invalidate anonIn_1.a.bits.address \n invalidate anonIn_1.a.bits.source \n invalidate anonIn_1.a.bits.size \n invalidate anonIn_1.a.bits.param \n invalidate anonIn_1.a.bits.opcode \n invalidate anonIn_1.a.valid \n invalidate anonIn_1.a.ready \n inst monitor of TLMonitor_63 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.e.bits.sink, anonIn.e.bits.sink \n connect monitor.io.in.e.valid, anonIn.e.valid \n connect monitor.io.in.e.ready, anonIn.e.ready \n connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, anonIn.d.bits.data \n connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink \n connect monitor.io.in.d.bits.source, anonIn.d.bits.source \n connect monitor.io.in.d.bits.size, anonIn.d.bits.size \n connect monitor.io.in.d.bits.param, anonIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode \n connect monitor.io.in.d.valid, anonIn.d.valid \n connect monitor.io.in.d.ready, anonIn.d.ready \n connect monitor.io.in.c.bits.corrupt, anonIn.c.bits.corrupt \n connect monitor.io.in.c.bits.data, anonIn.c.bits.data \n connect monitor.io.in.c.bits.address, anonIn.c.bits.address \n connect monitor.io.in.c.bits.source, anonIn.c.bits.source \n connect monitor.io.in.c.bits.size, anonIn.c.bits.size \n connect monitor.io.in.c.bits.param, anonIn.c.bits.param \n connect monitor.io.in.c.bits.opcode, anonIn.c.bits.opcode \n connect monitor.io.in.c.valid, anonIn.c.valid \n connect monitor.io.in.c.ready, anonIn.c.ready \n connect monitor.io.in.b.bits.corrupt, anonIn.b.bits.corrupt \n connect monitor.io.in.b.bits.data, anonIn.b.bits.data \n connect monitor.io.in.b.bits.mask, anonIn.b.bits.mask \n connect monitor.io.in.b.bits.address, anonIn.b.bits.address \n connect monitor.io.in.b.bits.source, anonIn.b.bits.source \n connect monitor.io.in.b.bits.size, anonIn.b.bits.size \n connect monitor.io.in.b.bits.param, anonIn.b.bits.param \n connect monitor.io.in.b.bits.opcode, anonIn.b.bits.opcode \n connect monitor.io.in.b.valid, anonIn.b.valid \n connect monitor.io.in.b.ready, anonIn.b.ready \n connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, anonIn.a.bits.data \n connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask \n connect monitor.io.in.a.bits.address, anonIn.a.bits.address \n connect monitor.io.in.a.bits.source, anonIn.a.bits.source \n connect monitor.io.in.a.bits.size, anonIn.a.bits.size \n connect monitor.io.in.a.bits.param, anonIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode \n connect monitor.io.in.a.valid, anonIn.a.valid \n connect monitor.io.in.a.ready, anonIn.a.ready \n inst monitor_1 of TLMonitor_64 \n connect monitor_1.clock, clock\n\n connect monitor_1.reset, reset\n\n connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt \n connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data \n connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied \n connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink \n connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source \n connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size \n connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param \n connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode \n connect monitor_1.io.in.d.valid, anonIn_1.d.valid \n connect monitor_1.io.in.d.ready, anonIn_1.d.ready \n connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt \n connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data \n connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask \n connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address \n connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source \n connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size \n connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param \n connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode \n connect monitor_1.io.in.a.valid, anonIn_1.a.valid \n connect monitor_1.io.in.a.ready, anonIn_1.a.ready \n wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} \n invalidate anonOut.e.bits.sink \n invalidate anonOut.e.valid \n invalidate anonOut.e.ready \n invalidate anonOut.d.bits.corrupt \n invalidate anonOut.d.bits.data \n invalidate anonOut.d.bits.denied \n invalidate anonOut.d.bits.sink \n invalidate anonOut.d.bits.source \n invalidate anonOut.d.bits.size \n invalidate anonOut.d.bits.param \n invalidate anonOut.d.bits.opcode \n invalidate anonOut.d.valid \n invalidate anonOut.d.ready \n invalidate anonOut.c.bits.corrupt \n invalidate anonOut.c.bits.data \n invalidate anonOut.c.bits.address \n invalidate anonOut.c.bits.source \n invalidate anonOut.c.bits.size \n invalidate anonOut.c.bits.param \n invalidate anonOut.c.bits.opcode \n invalidate anonOut.c.valid \n invalidate anonOut.c.ready \n invalidate anonOut.b.bits.corrupt \n invalidate anonOut.b.bits.data \n invalidate anonOut.b.bits.mask \n invalidate anonOut.b.bits.address \n invalidate anonOut.b.bits.source \n invalidate anonOut.b.bits.size \n invalidate anonOut.b.bits.param \n invalidate anonOut.b.bits.opcode \n invalidate anonOut.b.valid \n invalidate anonOut.b.ready \n invalidate anonOut.a.bits.corrupt \n invalidate anonOut.a.bits.data \n invalidate anonOut.a.bits.mask \n invalidate anonOut.a.bits.address \n invalidate anonOut.a.bits.source \n invalidate anonOut.a.bits.size \n invalidate anonOut.a.bits.param \n invalidate anonOut.a.bits.opcode \n invalidate anonOut.a.valid \n invalidate anonOut.a.ready \n connect auto.anon_out, anonOut \n connect anonIn, auto.anon_in_0 \n connect anonIn_1, auto.anon_in_1 \n wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2] \n connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt \n connect in[0].a.bits.data, anonIn.a.bits.data \n connect in[0].a.bits.mask, anonIn.a.bits.mask \n connect in[0].a.bits.address, anonIn.a.bits.address \n connect in[0].a.bits.source, anonIn.a.bits.source \n connect in[0].a.bits.size, anonIn.a.bits.size \n connect in[0].a.bits.param, anonIn.a.bits.param \n connect in[0].a.bits.opcode, anonIn.a.bits.opcode \n connect in[0].a.valid, anonIn.a.valid \n connect anonIn.a.ready, in[0].a.ready \n node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) \n connect in[0].a.bits.source, _in_0_a_bits_source_T \n connect anonIn.b.bits.corrupt, in[0].b.bits.corrupt \n connect anonIn.b.bits.data, in[0].b.bits.data \n connect anonIn.b.bits.mask, in[0].b.bits.mask \n connect anonIn.b.bits.address, in[0].b.bits.address \n connect anonIn.b.bits.source, in[0].b.bits.source \n connect anonIn.b.bits.size, in[0].b.bits.size \n connect anonIn.b.bits.param, in[0].b.bits.param \n connect anonIn.b.bits.opcode, in[0].b.bits.opcode \n connect anonIn.b.valid, in[0].b.valid \n connect in[0].b.ready, anonIn.b.ready \n node _anonIn_b_bits_source_T = bits(in[0].b.bits.source, 0, 0) \n connect anonIn.b.bits.source, _anonIn_b_bits_source_T \n connect in[0].c.bits.corrupt, anonIn.c.bits.corrupt \n connect in[0].c.bits.data, anonIn.c.bits.data \n connect in[0].c.bits.address, anonIn.c.bits.address \n connect in[0].c.bits.source, anonIn.c.bits.source \n connect in[0].c.bits.size, anonIn.c.bits.size \n connect in[0].c.bits.param, anonIn.c.bits.param \n connect in[0].c.bits.opcode, anonIn.c.bits.opcode \n connect in[0].c.valid, anonIn.c.valid \n connect anonIn.c.ready, in[0].c.ready \n node _in_0_c_bits_source_T = or(anonIn.c.bits.source, UInt<1>(0h0)) \n connect in[0].c.bits.source, _in_0_c_bits_source_T \n connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt \n connect anonIn.d.bits.data, in[0].d.bits.data \n connect anonIn.d.bits.denied, in[0].d.bits.denied \n connect anonIn.d.bits.sink, in[0].d.bits.sink \n connect anonIn.d.bits.source, in[0].d.bits.source \n connect anonIn.d.bits.size, in[0].d.bits.size \n connect anonIn.d.bits.param, in[0].d.bits.param \n connect anonIn.d.bits.opcode, in[0].d.bits.opcode \n connect anonIn.d.valid, in[0].d.valid \n connect in[0].d.ready, anonIn.d.ready \n node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 0, 0) \n connect anonIn.d.bits.source, _anonIn_d_bits_source_T \n connect in[0].e.bits.sink, anonIn.e.bits.sink \n connect in[0].e.valid, anonIn.e.valid \n connect anonIn.e.ready, in[0].e.ready \n connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt \n connect in[1].a.bits.data, anonIn_1.a.bits.data \n connect in[1].a.bits.mask, anonIn_1.a.bits.mask \n connect in[1].a.bits.address, anonIn_1.a.bits.address \n connect in[1].a.bits.source, anonIn_1.a.bits.source \n connect in[1].a.bits.size, anonIn_1.a.bits.size \n connect in[1].a.bits.param, anonIn_1.a.bits.param \n connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode \n connect in[1].a.valid, anonIn_1.a.valid \n connect anonIn_1.a.ready, in[1].a.ready \n node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<2>(0h2)) \n connect in[1].a.bits.source, _in_1_a_bits_source_T \n invalidate in[1].b.bits.corrupt \n invalidate in[1].b.bits.data \n invalidate in[1].b.bits.mask \n invalidate in[1].b.bits.address \n invalidate in[1].b.bits.source \n invalidate in[1].b.bits.size \n invalidate in[1].b.bits.param \n invalidate in[1].b.bits.opcode \n invalidate in[1].b.valid \n invalidate in[1].b.ready \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<1>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n invalidate _WIRE_1.bits.corrupt \n invalidate _WIRE_1.bits.data \n invalidate _WIRE_1.bits.mask \n invalidate _WIRE_1.bits.address \n invalidate _WIRE_1.bits.source \n invalidate _WIRE_1.bits.size \n invalidate _WIRE_1.bits.param \n invalidate _WIRE_1.bits.opcode \n invalidate _WIRE_1.valid \n invalidate _WIRE_1.ready \n connect in[1].b.ready, UInt<1>(0h1) \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.mask, UInt<8>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<1>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<2>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n connect _WIRE_3.valid, UInt<1>(0h0) \n invalidate in[1].c.bits.corrupt \n invalidate in[1].c.bits.data \n invalidate in[1].c.bits.address \n invalidate in[1].c.bits.source \n invalidate in[1].c.bits.size \n invalidate in[1].c.bits.param \n invalidate in[1].c.bits.opcode \n invalidate in[1].c.valid \n invalidate in[1].c.ready \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_4.bits.data, UInt<64>(0h0) \n connect _WIRE_4.bits.address, UInt<32>(0h0) \n connect _WIRE_4.bits.source, UInt<1>(0h0) \n connect _WIRE_4.bits.size, UInt<4>(0h0) \n connect _WIRE_4.bits.param, UInt<3>(0h0) \n connect _WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n invalidate _WIRE_5.bits.corrupt \n invalidate _WIRE_5.bits.data \n invalidate _WIRE_5.bits.address \n invalidate _WIRE_5.bits.source \n invalidate _WIRE_5.bits.size \n invalidate _WIRE_5.bits.param \n invalidate _WIRE_5.bits.opcode \n invalidate _WIRE_5.valid \n invalidate _WIRE_5.ready \n connect in[1].c.valid, UInt<1>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<1>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n connect _WIRE_7.ready, UInt<1>(0h1) \n connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt \n connect anonIn_1.d.bits.data, in[1].d.bits.data \n connect anonIn_1.d.bits.denied, in[1].d.bits.denied \n connect anonIn_1.d.bits.sink, in[1].d.bits.sink \n connect anonIn_1.d.bits.source, in[1].d.bits.source \n connect anonIn_1.d.bits.size, in[1].d.bits.size \n connect anonIn_1.d.bits.param, in[1].d.bits.param \n connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode \n connect anonIn_1.d.valid, in[1].d.valid \n connect in[1].d.ready, anonIn_1.d.ready \n connect anonIn_1.d.bits.source, UInt<1>(0h0) \n invalidate in[1].e.bits.sink \n invalidate in[1].e.valid \n invalidate in[1].e.ready \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} \n connect _WIRE_8.bits.sink, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n invalidate _WIRE_9.bits.sink \n invalidate _WIRE_9.valid \n invalidate _WIRE_9.ready \n connect in[1].e.valid, UInt<1>(0h0) \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} \n connect _WIRE_10.bits.sink, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n connect _WIRE_11.ready, UInt<1>(0h1) \n wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[1] \n connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt \n connect anonOut.a.bits.data, out[0].a.bits.data \n connect anonOut.a.bits.mask, out[0].a.bits.mask \n connect anonOut.a.bits.address, out[0].a.bits.address \n connect anonOut.a.bits.source, out[0].a.bits.source \n connect anonOut.a.bits.size, out[0].a.bits.size \n connect anonOut.a.bits.param, out[0].a.bits.param \n connect anonOut.a.bits.opcode, out[0].a.bits.opcode \n connect anonOut.a.valid, out[0].a.valid \n connect out[0].a.ready, anonOut.a.ready \n connect out[0].b.bits.corrupt, anonOut.b.bits.corrupt \n connect out[0].b.bits.data, anonOut.b.bits.data \n connect out[0].b.bits.mask, anonOut.b.bits.mask \n connect out[0].b.bits.address, anonOut.b.bits.address \n connect out[0].b.bits.source, anonOut.b.bits.source \n connect out[0].b.bits.size, anonOut.b.bits.size \n connect out[0].b.bits.param, anonOut.b.bits.param \n connect out[0].b.bits.opcode, anonOut.b.bits.opcode \n connect out[0].b.valid, anonOut.b.valid \n connect anonOut.b.ready, out[0].b.ready \n connect anonOut.c.bits.corrupt, out[0].c.bits.corrupt \n connect anonOut.c.bits.data, out[0].c.bits.data \n connect anonOut.c.bits.address, out[0].c.bits.address \n connect anonOut.c.bits.source, out[0].c.bits.source \n connect anonOut.c.bits.size, out[0].c.bits.size \n connect anonOut.c.bits.param, out[0].c.bits.param \n connect anonOut.c.bits.opcode, out[0].c.bits.opcode \n connect anonOut.c.valid, out[0].c.valid \n connect out[0].c.ready, anonOut.c.ready \n connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt \n connect out[0].d.bits.data, anonOut.d.bits.data \n connect out[0].d.bits.denied, anonOut.d.bits.denied \n connect out[0].d.bits.sink, anonOut.d.bits.sink \n connect out[0].d.bits.source, anonOut.d.bits.source \n connect out[0].d.bits.size, anonOut.d.bits.size \n connect out[0].d.bits.param, anonOut.d.bits.param \n connect out[0].d.bits.opcode, anonOut.d.bits.opcode \n connect out[0].d.valid, anonOut.d.valid \n connect anonOut.d.ready, out[0].d.ready \n node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) \n connect out[0].d.bits.sink, _out_0_d_bits_sink_T \n connect anonOut.e.bits.sink, out[0].e.bits.sink \n connect anonOut.e.valid, out[0].e.valid \n connect out[0].e.ready, anonOut.e.ready \n node _anonOut_e_bits_sink_T = bits(out[0].e.bits.sink, 2, 0) \n connect anonOut.e.bits.sink, _anonOut_e_bits_sink_T \n node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) \n node _requestAIO_T_1 = cvt(_requestAIO_T) \n node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) \n node _requestAIO_T_3 = asSInt(_requestAIO_T_2) \n node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) \n node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) \n node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) \n node _requestAIO_T_6 = cvt(_requestAIO_T_5) \n node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) \n node _requestAIO_T_8 = asSInt(_requestAIO_T_7) \n node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) \n node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) \n node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0)) \n node _requestCIO_T_1 = cvt(_requestCIO_T) \n node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) \n node _requestCIO_T_3 = asSInt(_requestCIO_T_2) \n node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) \n node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) \n node _requestCIO_T_5 = xor(in[1].c.bits.address, UInt<1>(0h0)) \n node _requestCIO_T_6 = cvt(_requestCIO_T_5) \n node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) \n node _requestCIO_T_8 = asSInt(_requestCIO_T_7) \n node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) \n node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) \n node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<1>(0h0)) \n node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 0, 0) \n node _requestBOI_T = shr(out[0].b.bits.source, 1) \n node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) \n node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) \n node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) \n node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<1>(0h1)) \n node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) \n node requestBOI_0_1 = eq(out[0].b.bits.source, UInt<2>(0h2)) \n node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<1>(0h0)) \n node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 0, 0) \n node _requestDOI_T = shr(out[0].d.bits.source, 1) \n node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) \n node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) \n node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) \n node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<1>(0h1)) \n node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) \n node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<2>(0h2)) \n node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0)) \n node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0) \n node _requestEIO_T = shr(in[0].e.bits.sink, 3) \n node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) \n node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) \n node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) \n node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7)) \n node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4) \n node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0)) \n node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0) \n node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3) \n node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) \n node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) \n node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) \n node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7)) \n node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9) \n node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) \n node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) \n node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) \n node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) \n node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) \n node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) \n node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) \n node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) \n node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) \n node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) \n node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) \n node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) \n node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) \n node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) \n node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size) \n node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) \n node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) \n node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) \n node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2) \n node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) \n node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) \n node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size) \n node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) \n node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) \n node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) \n node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0) \n node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) \n node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size) \n node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) \n node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) \n node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) \n node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0) \n node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) \n node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) \n node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) \n node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) \n node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) \n node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) \n node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) \n wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] \n connect portsAOI_filtered[0].bits, in[0].a.bits \n node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) \n node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) \n connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 \n connect in[0].a.ready, portsAOI_filtered[0].ready \n wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] \n connect portsAOI_filtered_1[0].bits, in[1].a.bits \n node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) \n node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) \n connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 \n connect in[1].a.ready, portsAOI_filtered_1[0].ready \n wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] \n connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt \n connect portsBIO_filtered[0].bits.data, out[0].b.bits.data \n connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask \n connect portsBIO_filtered[0].bits.address, out[0].b.bits.address \n connect portsBIO_filtered[0].bits.source, out[0].b.bits.source \n connect portsBIO_filtered[0].bits.size, out[0].b.bits.size \n connect portsBIO_filtered[0].bits.param, out[0].b.bits.param \n connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode \n node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) \n node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T) \n connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 \n connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt \n connect portsBIO_filtered[1].bits.data, out[0].b.bits.data \n connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask \n connect portsBIO_filtered[1].bits.address, out[0].b.bits.address \n connect portsBIO_filtered[1].bits.source, out[0].b.bits.source \n connect portsBIO_filtered[1].bits.size, out[0].b.bits.size \n connect portsBIO_filtered[1].bits.param, out[0].b.bits.param \n connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode \n node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) \n node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T) \n connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 \n node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) \n node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) \n node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1) \n wire _portsBIO_out_0_b_ready_WIRE : UInt<1> \n connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2 \n connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE \n wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] \n connect portsCOI_filtered[0].bits, in[0].c.bits \n node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) \n node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T) \n connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 \n connect in[0].c.ready, portsCOI_filtered[0].ready \n wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] \n connect portsCOI_filtered_1[0].bits, in[1].c.bits \n node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) \n node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2) \n connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 \n connect in[1].c.ready, portsCOI_filtered_1[0].ready \n wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] \n connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt \n connect portsDIO_filtered[0].bits.data, out[0].d.bits.data \n connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied \n connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink \n connect portsDIO_filtered[0].bits.source, out[0].d.bits.source \n connect portsDIO_filtered[0].bits.size, out[0].d.bits.size \n connect portsDIO_filtered[0].bits.param, out[0].d.bits.param \n connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode \n node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) \n node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) \n connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 \n connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt \n connect portsDIO_filtered[1].bits.data, out[0].d.bits.data \n connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied \n connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink \n connect portsDIO_filtered[1].bits.source, out[0].d.bits.source \n connect portsDIO_filtered[1].bits.size, out[0].d.bits.size \n connect portsDIO_filtered[1].bits.param, out[0].d.bits.param \n connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode \n node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) \n node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) \n connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 \n node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) \n node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) \n node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) \n wire _portsDIO_out_0_d_ready_WIRE : UInt<1> \n connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 \n connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE \n wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] \n connect portsEOI_filtered[0].bits, in[0].e.bits \n node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1)) \n node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T) \n connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 \n connect in[0].e.ready, portsEOI_filtered[0].ready \n wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] \n connect portsEOI_filtered_1[0].bits, in[1].e.bits \n node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1)) \n node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2) \n connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 \n connect in[1].e.ready, portsEOI_filtered_1[0].ready \n regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) \n node idle = eq(beatsLeft, UInt<1>(0h0)) \n node latch = and(idle, out[0].a.ready) \n node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) \n node readys_valid = bits(_readys_T, 1, 0) \n node _readys_T_1 = eq(readys_valid, _readys_T) \n node _readys_T_2 = asUInt(reset) \n node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) \n when _readys_T_3 : \n node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) \n when _readys_T_4 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:22 assert (valid === valids)\\n\") : readys_printf \n assert(clock, _readys_T_1, UInt<1>(0h1), \"\") : readys_assert \n regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) \n node _readys_filter_T = not(readys_mask) \n node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) \n node readys_filter = cat(_readys_filter_T_1, readys_valid) \n node _readys_unready_T = shr(readys_filter, 1) \n node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) \n node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) \n node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) \n node _readys_unready_T_4 = shl(readys_mask, 2) \n node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) \n node _readys_readys_T = shr(readys_unready, 2) \n node _readys_readys_T_1 = bits(readys_unready, 1, 0) \n node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) \n node readys_readys = not(_readys_readys_T_2) \n node _readys_T_5 = orr(readys_valid) \n node _readys_T_6 = and(latch, _readys_T_5) \n when _readys_T_6 : \n node _readys_mask_T = and(readys_readys, readys_valid) \n node _readys_mask_T_1 = shl(_readys_mask_T, 1) \n node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) \n node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) \n node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) \n connect readys_mask, _readys_mask_T_4 \n node _readys_T_7 = bits(readys_readys, 1, 0) \n node _readys_T_8 = bits(_readys_T_7, 0, 0) \n node _readys_T_9 = bits(_readys_T_7, 1, 1) \n wire readys : UInt<1>[2] \n connect readys[0], _readys_T_8 \n connect readys[1], _readys_T_9 \n node _winner_T = and(readys[0], portsAOI_filtered[0].valid) \n node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) \n wire winner : UInt<1>[2] \n connect winner[0], _winner_T \n connect winner[1], _winner_T_1 \n node prefixOR_1 = or(UInt<1>(0h0), winner[0]) \n node _prefixOR_T = or(prefixOR_1, winner[1]) \n node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1 = eq(winner[0], UInt<1>(0h0)) \n node _T_2 = or(_T, _T_1) \n node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) \n node _T_4 = eq(winner[1], UInt<1>(0h0)) \n node _T_5 = or(_T_3, _T_4) \n node _T_6 = and(_T_2, _T_5) \n node _T_7 = asUInt(reset) \n node _T_8 = eq(_T_7, UInt<1>(0h0)) \n when _T_8 : \n node _T_9 = eq(_T_6, UInt<1>(0h0)) \n when _T_9 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\\n\") : printf \n assert(clock, _T_6, UInt<1>(0h1), \"\") : assert \n node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) \n node _T_11 = eq(_T_10, UInt<1>(0h0)) \n node _T_12 = or(winner[0], winner[1]) \n node _T_13 = or(_T_11, _T_12) \n node _T_14 = asUInt(reset) \n node _T_15 = eq(_T_14, UInt<1>(0h0)) \n when _T_15 : \n node _T_16 = eq(_T_13, UInt<1>(0h0)) \n when _T_16 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\\n\") : printf_1 \n assert(clock, _T_13, UInt<1>(0h1), \"\") : assert_1 \n node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) \n node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) \n node initBeats = or(maskedBeats_0, maskedBeats_1) \n node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) \n node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) \n node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) \n node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) \n connect beatsLeft, _beatsLeft_T_3 \n wire _state_WIRE : UInt<1>[2] \n connect _state_WIRE[0], UInt<1>(0h0) \n connect _state_WIRE[1], UInt<1>(0h0) \n regreset state : UInt<1>[2], clock, reset, _state_WIRE \n node muxState = mux(idle, winner, state) \n connect state, muxState \n node allowed = mux(idle, readys, state) \n node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) \n connect portsAOI_filtered[0].ready, _filtered_0_ready_T \n node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) \n connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 \n node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) \n node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) \n node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) \n node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) \n wire _out_0_a_valid_WIRE : UInt<1> \n connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 \n node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) \n connect out[0].a.valid, _out_0_a_valid_T_4 \n wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} \n node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) \n node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) \n node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) \n wire _out_0_a_bits_WIRE_1 : UInt<1> \n connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 \n connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 \n node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) \n node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) \n node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) \n wire _out_0_a_bits_WIRE_2 : UInt<64> \n connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 \n connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 \n node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) \n node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) \n node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) \n wire _out_0_a_bits_WIRE_3 : UInt<8> \n connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 \n connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 \n wire _out_0_a_bits_WIRE_4 : { } \n connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 \n wire _out_0_a_bits_WIRE_5 : { } \n connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 \n node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) \n node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) \n node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) \n wire _out_0_a_bits_WIRE_6 : UInt<32> \n connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 \n connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 \n node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) \n node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) \n node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) \n wire _out_0_a_bits_WIRE_7 : UInt<2> \n connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 \n connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 \n node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) \n node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) \n node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) \n wire _out_0_a_bits_WIRE_8 : UInt<4> \n connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 \n connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 \n node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) \n node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) \n node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) \n wire _out_0_a_bits_WIRE_9 : UInt<3> \n connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 \n connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 \n node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) \n node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) \n node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) \n wire _out_0_a_bits_WIRE_10 : UInt<3> \n connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 \n connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 \n connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt \n connect out[0].a.bits.data, _out_0_a_bits_WIRE.data \n connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask \n connect out[0].a.bits.address, _out_0_a_bits_WIRE.address \n connect out[0].a.bits.source, _out_0_a_bits_WIRE.source \n connect out[0].a.bits.size, _out_0_a_bits_WIRE.size \n connect out[0].a.bits.param, _out_0_a_bits_WIRE.param \n connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode \n connect out[0].c, portsCOI_filtered[0] \n connect out[0].e, portsEOI_filtered[0] \n connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) \n connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) \n connect in[0].b, portsBIO_filtered[0] \n connect in[0].d, portsDIO_filtered[0] \n invalidate in[1].b.bits.corrupt \n invalidate in[1].b.bits.data \n invalidate in[1].b.bits.mask \n invalidate in[1].b.bits.address \n invalidate in[1].b.bits.source \n invalidate in[1].b.bits.size \n invalidate in[1].b.bits.param \n invalidate in[1].b.bits.opcode \n connect in[1].d, portsDIO_filtered[1] \n connect portsBIO_filtered[1].ready, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c_5(\t// @[Xbar.scala:74:9]\n input clock,\t// @[Xbar.scala:74:9]\n input reset,\t// @[Xbar.scala:74:9]\n output auto_anon_in_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_in_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_0_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_in_0_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_in_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_0_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_0_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_0_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_in_0_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_in_0_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_in_0_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_0_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_0_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_in_0_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_0_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_in_0_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_out_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_out_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_out_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_c_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_c_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_out_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_out_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_e_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_e_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_e_bits_sink\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [2:0] out_0_e_bits_sink;\t// @[Xbar.scala:216:19]\n wire [2:0] out_0_d_bits_sink;\t// @[Xbar.scala:216:19]\n wire [1:0] in_0_c_bits_source;\t// @[Xbar.scala:159:18]\n wire [1:0] in_0_a_bits_source;\t// @[Xbar.scala:159:18]\n wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address;\t// @[Xbar.scala:74:9]\n wire [7:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready;\t// @[Xbar.scala:74:9]\n wire _readys_T_2 = reset;\t// @[Arbiter.scala:22:12]\n wire auto_anon_in_1_d_ready = 1'h1;\t// @[Xbar.scala:74:9]\n wire anonIn_1_d_ready = 1'h1;\t// @[MixedNode.scala:551:17]\n wire in_1_b_ready = 1'h1;\t// @[Xbar.scala:159:18]\n wire in_1_d_ready = 1'h1;\t// @[Xbar.scala:159:18]\n wire _requestAIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestAIO_0_0 = 1'h1;\t// @[Xbar.scala:307:107]\n wire _requestAIO_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestAIO_1_0 = 1'h1;\t// @[Xbar.scala:307:107]\n wire _requestCIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestCIO_0_0 = 1'h1;\t// @[Xbar.scala:308:107]\n wire _requestCIO_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestCIO_1_0 = 1'h1;\t// @[Xbar.scala:308:107]\n wire _requestBOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestBOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _requestDOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestDOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _requestEIO_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _requestEIO_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestEIO_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _requestEIO_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire requestEIO_0_0 = 1'h1;\t// @[Parameters.scala:56:48]\n wire _requestEIO_T_6 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _requestEIO_T_7 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestEIO_T_8 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _requestEIO_T_9 = 1'h1;\t// @[Parameters.scala:57:20]\n wire requestEIO_1_0 = 1'h1;\t// @[Parameters.scala:56:48]\n wire _beatsAI_opdata_T_1 = 1'h1;\t// @[Edges.scala:92:37]\n wire _portsAOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsAOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsCOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsCOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire portsDIO_filtered_1_ready = 1'h1;\t// @[Xbar.scala:352:24]\n wire _portsEOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsEOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_1_a_bits_opcode = 3'h4;\t// @[MixedNode.scala:551:17]\n wire [2:0] in_1_a_bits_opcode = 3'h4;\t// @[Xbar.scala:159:18]\n wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4;\t// @[Xbar.scala:352:24]\n wire [2:0] auto_anon_in_1_a_bits_param = 3'h0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_1_a_bits_param = 3'h0;\t// @[MixedNode.scala:551:17]\n wire [2:0] in_1_a_bits_param = 3'h0;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_b_bits_opcode = 3'h0;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_c_bits_opcode = 3'h0;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_c_bits_param = 3'h0;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_e_bits_sink = 3'h0;\t// @[Xbar.scala:159:18]\n wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0;\t// @[Parameters.scala:52:29]\n wire [2:0] requestEIO_uncommonBits_1 = 3'h0;\t// @[Parameters.scala:52:56]\n wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] _out_0_a_bits_T_19 = 3'h0;\t// @[Mux.scala:30:73]\n wire [3:0] auto_anon_in_1_a_bits_size = 4'h6;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_1_a_bits_size = 4'h6;\t// @[MixedNode.scala:551:17]\n wire [3:0] in_1_a_bits_size = 4'h6;\t// @[Xbar.scala:159:18]\n wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6;\t// @[Xbar.scala:352:24]\n wire auto_anon_in_1_a_bits_source = 1'h0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_a_bits_corrupt = 1'h0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_source = 1'h0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_bits_corrupt = 1'h0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_c_bits_corrupt = 1'h0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_bits_corrupt = 1'h0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_c_bits_corrupt = 1'h0;\t// @[Xbar.scala:74:9]\n wire anonIn_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:551:17]\n wire anonIn_c_bits_corrupt = 1'h0;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_a_bits_source = 1'h0;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_source = 1'h0;\t// @[MixedNode.scala:551:17]\n wire anonOut_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire anonOut_c_bits_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire in_0_a_bits_corrupt = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_0_c_bits_corrupt = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_a_bits_corrupt = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_b_valid = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_b_bits_corrupt = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_c_ready = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_c_valid = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_c_bits_corrupt = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_e_ready = 1'h0;\t// @[Xbar.scala:159:18]\n wire in_1_e_valid = 1'h0;\t// @[Xbar.scala:159:18]\n wire out_0_a_bits_corrupt = 1'h0;\t// @[Xbar.scala:216:19]\n wire out_0_c_bits_corrupt = 1'h0;\t// @[Xbar.scala:216:19]\n wire _requestEIO_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _requestEIO_T_5 = 1'h0;\t// @[Parameters.scala:54:10]\n wire beatsAI_opdata_1 = 1'h0;\t// @[Edges.scala:92:28]\n wire beatsCI_opdata_1 = 1'h0;\t// @[Edges.scala:102:36]\n wire portsAOI_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsAOI_filtered_1_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_1_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsBIO_out_0_b_ready_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire portsCOI_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_1_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_1_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_1_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsCOI_filtered_0_valid_T_3 = 1'h0;\t// @[Xbar.scala:355:40]\n wire portsEOI_filtered_1_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsEOI_filtered_1_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsEOI_filtered_0_valid_T_3 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _state_WIRE_0 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _state_WIRE_1 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _out_0_a_bits_WIRE_corrupt = 1'h0;\t// @[Mux.scala:30:73]\n wire _out_0_a_bits_T = 1'h0;\t// @[Mux.scala:30:73]\n wire _out_0_a_bits_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire _out_0_a_bits_T_2 = 1'h0;\t// @[Mux.scala:30:73]\n wire _out_0_a_bits_WIRE_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF;\t// @[Xbar.scala:74:9]\n wire [7:0] anonIn_1_a_bits_mask = 8'hFF;\t// @[MixedNode.scala:551:17]\n wire [7:0] in_1_a_bits_mask = 8'hFF;\t// @[Xbar.scala:159:18]\n wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF;\t// @[Xbar.scala:352:24]\n wire [63:0] auto_anon_in_1_a_bits_data = 64'h0;\t// @[Xbar.scala:74:9]\n wire [63:0] anonIn_1_a_bits_data = 64'h0;\t// @[MixedNode.scala:551:17]\n wire [63:0] in_1_a_bits_data = 64'h0;\t// @[Xbar.scala:159:18]\n wire [63:0] in_1_b_bits_data = 64'h0;\t// @[Xbar.scala:159:18]\n wire [63:0] in_1_c_bits_data = 64'h0;\t// @[Xbar.scala:159:18]\n wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0;\t// @[Xbar.scala:352:24]\n wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0;\t// @[Xbar.scala:352:24]\n wire [63:0] _out_0_a_bits_T_4 = 64'h0;\t// @[Mux.scala:30:73]\n wire [8:0] beatsAI_1 = 9'h0;\t// @[Edges.scala:221:14]\n wire [8:0] beatsBO_0 = 9'h0;\t// @[Edges.scala:221:14]\n wire [8:0] beatsCI_decode_1 = 9'h0;\t// @[Edges.scala:220:59]\n wire [8:0] beatsCI_1 = 9'h0;\t// @[Edges.scala:221:14]\n wire [8:0] maskedBeats_1 = 9'h0;\t// @[Arbiter.scala:82:69]\n wire [31:0] in_1_b_bits_address = 32'h0;\t// @[Xbar.scala:159:18]\n wire [31:0] in_1_c_bits_address = 32'h0;\t// @[Xbar.scala:159:18]\n wire [31:0] _requestCIO_T_5 = 32'h0;\t// @[Parameters.scala:137:31]\n wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [1:0] in_1_b_bits_param = 2'h0;\t// @[Xbar.scala:159:18]\n wire [1:0] in_1_b_bits_source = 2'h0;\t// @[Xbar.scala:159:18]\n wire [1:0] in_1_c_bits_source = 2'h0;\t// @[Xbar.scala:159:18]\n wire [1:0] portsCOI_filtered_1_0_bits_source = 2'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] in_1_b_bits_size = 4'h0;\t// @[Xbar.scala:159:18]\n wire [3:0] in_1_c_bits_size = 4'h0;\t// @[Xbar.scala:159:18]\n wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [1:0] in_1_a_bits_source = 2'h2;\t// @[Xbar.scala:159:18]\n wire [1:0] _in_1_a_bits_source_T = 2'h2;\t// @[Xbar.scala:166:55]\n wire [1:0] portsAOI_filtered_1_0_bits_source = 2'h2;\t// @[Xbar.scala:352:24]\n wire [11:0] _beatsCI_decode_T_5 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _beatsCI_decode_T_4 = 12'hFFF;\t// @[package.scala:243:76]\n wire [26:0] _beatsCI_decode_T_3 = 27'hFFF;\t// @[package.scala:243:71]\n wire [8:0] beatsAI_decode_1 = 9'h7;\t// @[Edges.scala:220:59]\n wire [11:0] _beatsAI_decode_T_5 = 12'h3F;\t// @[package.scala:243:46]\n wire [11:0] _beatsAI_decode_T_4 = 12'hFC0;\t// @[package.scala:243:76]\n wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0;\t// @[package.scala:243:71]\n wire [32:0] _requestAIO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_7 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_8 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_6 = 33'h0;\t// @[Parameters.scala:137:41]\n wire [32:0] _requestCIO_T_7 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_8 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [7:0] in_1_b_bits_mask = 8'h0;\t// @[Xbar.scala:159:18]\n wire anonIn_1_a_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_1_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_1_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_1_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_1_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] anonIn_1_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_valid = auto_anon_in_0_a_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonIn_b_ready = auto_anon_in_0_b_ready_0;\t// @[Xbar.scala:74:9]\n wire anonIn_b_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_b_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_b_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_b_bits_size;\t// @[MixedNode.scala:551:17]\n wire anonIn_b_bits_source;\t// @[MixedNode.scala:551:17]\n wire [31:0] anonIn_b_bits_address;\t// @[MixedNode.scala:551:17]\n wire [7:0] anonIn_b_bits_mask;\t// @[MixedNode.scala:551:17]\n wire [63:0] anonIn_b_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_b_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonIn_c_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_c_valid = auto_anon_in_0_c_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0;\t// @[Xbar.scala:74:9]\n wire anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [63:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonIn_d_ready = auto_anon_in_0_d_ready_0;\t// @[Xbar.scala:74:9]\n wire anonIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] anonIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonIn_e_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_e_valid = auto_anon_in_0_e_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire anonOut_a_ready = auto_anon_out_a_ready_0;\t// @[Xbar.scala:74:9]\n wire anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire anonOut_b_ready;\t// @[MixedNode.scala:542:17]\n wire anonOut_b_valid = auto_anon_out_b_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [1:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [7:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [63:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire anonOut_c_ready = auto_anon_out_c_ready_0;\t// @[Xbar.scala:74:9]\n wire anonOut_c_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_c_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_c_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_c_bits_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] anonOut_c_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_c_bits_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] anonOut_c_bits_data;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_valid = auto_anon_out_d_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire anonOut_e_ready = auto_anon_out_e_ready_0;\t// @[Xbar.scala:74:9]\n wire anonOut_e_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_e_bits_sink;\t// @[MixedNode.scala:542:17]\n wire auto_anon_in_1_a_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_in_1_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_in_1_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_b_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_in_0_b_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_b_bits_size_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_b_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_0_b_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [7:0] auto_anon_in_0_b_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_in_0_b_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_b_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_b_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_c_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_in_0_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_in_0_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_e_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_out_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [7:0] auto_anon_out_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_out_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_b_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_c_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_c_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_c_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_c_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_out_c_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [63:0] auto_anon_out_c_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_c_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_e_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_e_valid_0;\t// @[Xbar.scala:74:9]\n wire in_0_a_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_a_ready_0 = anonIn_a_ready;\t// @[Xbar.scala:74:9]\n wire in_0_a_valid = anonIn_a_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_a_bits_param = anonIn_a_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] in_0_a_bits_size = anonIn_a_bits_size;\t// @[Xbar.scala:159:18]\n wire _in_0_a_bits_source_T = anonIn_a_bits_source;\t// @[Xbar.scala:166:55]\n wire [31:0] in_0_a_bits_address = anonIn_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask;\t// @[Xbar.scala:159:18]\n wire [63:0] in_0_a_bits_data = anonIn_a_bits_data;\t// @[Xbar.scala:159:18]\n wire in_0_b_ready = anonIn_b_ready;\t// @[Xbar.scala:159:18]\n wire in_0_b_valid;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_valid_0 = anonIn_b_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] in_0_b_bits_opcode;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] in_0_b_bits_param;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] in_0_b_bits_size;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size;\t// @[Xbar.scala:74:9]\n wire _anonIn_b_bits_source_T;\t// @[Xbar.scala:156:69]\n assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] in_0_b_bits_address;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address;\t// @[Xbar.scala:74:9]\n wire [7:0] in_0_b_bits_mask;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask;\t// @[Xbar.scala:74:9]\n wire [63:0] in_0_b_bits_data;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data;\t// @[Xbar.scala:74:9]\n wire in_0_b_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire in_0_c_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_c_ready_0 = anonIn_c_ready;\t// @[Xbar.scala:74:9]\n wire in_0_c_valid = anonIn_c_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_c_bits_param = anonIn_c_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] in_0_c_bits_size = anonIn_c_bits_size;\t// @[Xbar.scala:159:18]\n wire _in_0_c_bits_source_T = anonIn_c_bits_source;\t// @[Xbar.scala:187:55]\n wire [31:0] in_0_c_bits_address = anonIn_c_bits_address;\t// @[Xbar.scala:159:18]\n wire [63:0] in_0_c_bits_data = anonIn_c_bits_data;\t// @[Xbar.scala:159:18]\n wire in_0_d_ready = anonIn_d_ready;\t// @[Xbar.scala:159:18]\n wire in_0_d_valid;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_valid_0 = anonIn_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size;\t// @[Xbar.scala:74:9]\n wire _anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source;\t// @[Xbar.scala:74:9]\n wire [2:0] in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [63:0] in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data;\t// @[Xbar.scala:74:9]\n wire in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire in_0_e_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_e_ready_0 = anonIn_e_ready;\t// @[Xbar.scala:74:9]\n wire in_0_e_valid = anonIn_e_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_e_bits_sink = anonIn_e_bits_sink;\t// @[Xbar.scala:159:18]\n wire in_1_a_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready;\t// @[Xbar.scala:74:9]\n wire in_1_a_valid = anonIn_1_a_valid;\t// @[Xbar.scala:159:18]\n wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address;\t// @[Xbar.scala:159:18]\n wire in_1_d_valid;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] in_1_d_bits_opcode;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] in_1_d_bits_param;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] in_1_d_bits_size;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [2:0] in_1_d_bits_sink;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire in_1_d_bits_denied;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [63:0] in_1_d_bits_data;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data;\t// @[Xbar.scala:74:9]\n wire in_1_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire out_0_a_ready = anonOut_a_ready;\t// @[Xbar.scala:216:19]\n wire out_0_a_valid;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_valid_0 = anonOut_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [1:0] out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [7:0] out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [63:0] out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data;\t// @[Xbar.scala:74:9]\n wire out_0_b_ready;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_b_ready_0 = anonOut_b_ready;\t// @[Xbar.scala:74:9]\n wire out_0_b_valid = anonOut_b_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [1:0] out_0_b_bits_param = anonOut_b_bits_param;\t// @[Xbar.scala:216:19]\n wire [3:0] out_0_b_bits_size = anonOut_b_bits_size;\t// @[Xbar.scala:216:19]\n wire [1:0] out_0_b_bits_source = anonOut_b_bits_source;\t// @[Xbar.scala:216:19]\n wire [31:0] out_0_b_bits_address = anonOut_b_bits_address;\t// @[Xbar.scala:216:19]\n wire [7:0] out_0_b_bits_mask = anonOut_b_bits_mask;\t// @[Xbar.scala:216:19]\n wire [63:0] out_0_b_bits_data = anonOut_b_bits_data;\t// @[Xbar.scala:216:19]\n wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt;\t// @[Xbar.scala:216:19]\n wire out_0_c_ready = anonOut_c_ready;\t// @[Xbar.scala:216:19]\n wire out_0_c_valid;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_c_valid_0 = anonOut_c_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_c_bits_opcode;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_c_bits_param;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] out_0_c_bits_size;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size;\t// @[Xbar.scala:74:9]\n wire [1:0] out_0_c_bits_source;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] out_0_c_bits_address;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address;\t// @[Xbar.scala:74:9]\n wire [63:0] out_0_c_bits_data;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data;\t// @[Xbar.scala:74:9]\n wire out_0_d_ready;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_d_ready_0 = anonOut_d_ready;\t// @[Xbar.scala:74:9]\n wire out_0_d_valid = anonOut_d_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [1:0] out_0_d_bits_param = anonOut_d_bits_param;\t// @[Xbar.scala:216:19]\n wire [3:0] out_0_d_bits_size = anonOut_d_bits_size;\t// @[Xbar.scala:216:19]\n wire [1:0] out_0_d_bits_source = anonOut_d_bits_source;\t// @[Xbar.scala:216:19]\n wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink;\t// @[Xbar.scala:251:53]\n wire out_0_d_bits_denied = anonOut_d_bits_denied;\t// @[Xbar.scala:216:19]\n wire [63:0] out_0_d_bits_data = anonOut_d_bits_data;\t// @[Xbar.scala:216:19]\n wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt;\t// @[Xbar.scala:216:19]\n wire out_0_e_ready = anonOut_e_ready;\t// @[Xbar.scala:216:19]\n wire out_0_e_valid;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_e_valid_0 = anonOut_e_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] _anonOut_e_bits_sink_T;\t// @[Xbar.scala:156:69]\n assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink;\t// @[Xbar.scala:74:9]\n wire portsAOI_filtered_0_ready;\t// @[Xbar.scala:352:24]\n assign anonIn_a_ready = in_0_a_ready;\t// @[Xbar.scala:159:18]\n wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n wire [1:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] _requestAIO_T = in_0_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask;\t// @[Xbar.scala:159:18, :352:24]\n wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n wire portsBIO_filtered_0_ready = in_0_b_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsBIO_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign anonIn_b_valid = in_0_b_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] portsBIO_filtered_0_bits_opcode;\t// @[Xbar.scala:352:24]\n assign anonIn_b_bits_opcode = in_0_b_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] portsBIO_filtered_0_bits_param;\t// @[Xbar.scala:352:24]\n assign anonIn_b_bits_param = in_0_b_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] portsBIO_filtered_0_bits_size;\t// @[Xbar.scala:352:24]\n assign anonIn_b_bits_size = in_0_b_bits_size;\t// @[Xbar.scala:159:18]\n wire [1:0] portsBIO_filtered_0_bits_source;\t// @[Xbar.scala:352:24]\n wire [31:0] portsBIO_filtered_0_bits_address;\t// @[Xbar.scala:352:24]\n assign anonIn_b_bits_address = in_0_b_bits_address;\t// @[Xbar.scala:159:18]\n wire [7:0] portsBIO_filtered_0_bits_mask;\t// @[Xbar.scala:352:24]\n assign anonIn_b_bits_mask = in_0_b_bits_mask;\t// @[Xbar.scala:159:18]\n wire [63:0] portsBIO_filtered_0_bits_data;\t// @[Xbar.scala:352:24]\n assign anonIn_b_bits_data = in_0_b_bits_data;\t// @[Xbar.scala:159:18]\n wire portsBIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire portsCOI_filtered_0_ready;\t// @[Xbar.scala:352:24]\n assign anonIn_c_ready = in_0_c_ready;\t// @[Xbar.scala:159:18]\n wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n wire [1:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] _requestCIO_T = in_0_c_bits_address;\t// @[Xbar.scala:159:18]\n wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire [63:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_0_ready = in_0_d_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign anonIn_d_valid = in_0_d_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_opcode = in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_param = in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_size = in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:352:24]\n wire [2:0] portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_sink = in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_denied = in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n wire [63:0] portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_data = in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire portsEOI_filtered_0_ready;\t// @[Xbar.scala:352:24]\n assign anonIn_e_ready = in_0_e_ready;\t// @[Xbar.scala:159:18]\n wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink;\t// @[Xbar.scala:159:18]\n wire portsAOI_filtered_1_0_ready;\t// @[Xbar.scala:352:24]\n wire [2:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign anonIn_1_a_ready = in_1_a_ready;\t// @[Xbar.scala:159:18]\n wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [31:0] _requestAIO_T_5 = in_1_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_1_valid;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_valid = in_1_d_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] portsDIO_filtered_1_bits_opcode;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_1_bits_param;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_param = in_1_d_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] portsDIO_filtered_1_bits_size;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_size = in_1_d_bits_size;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_1_bits_source;\t// @[Xbar.scala:352:24]\n wire [2:0] portsDIO_filtered_1_bits_sink;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_sink = in_1_d_bits_sink;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_1_bits_denied;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_denied = in_1_d_bits_denied;\t// @[Xbar.scala:159:18]\n wire [63:0] portsDIO_filtered_1_bits_data;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_data = in_1_d_bits_data;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_1_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire [1:0] in_0_b_bits_source;\t// @[Xbar.scala:159:18]\n wire [1:0] in_0_d_bits_source;\t// @[Xbar.scala:159:18]\n wire [1:0] in_1_d_bits_source;\t// @[Xbar.scala:159:18]\n assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T};\t// @[Xbar.scala:159:18, :166:{29,55}]\n assign _anonIn_b_bits_source_T = in_0_b_bits_source[0];\t// @[Xbar.scala:156:69, :159:18]\n assign anonIn_b_bits_source = _anonIn_b_bits_source_T;\t// @[Xbar.scala:156:69]\n assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T};\t// @[Xbar.scala:159:18, :187:{29,55}]\n assign _anonIn_d_bits_source_T = in_0_d_bits_source[0];\t// @[Xbar.scala:156:69, :159:18]\n assign anonIn_d_bits_source = _anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n wire _out_0_a_valid_T_4;\t// @[Arbiter.scala:96:24]\n assign anonOut_a_valid = out_0_a_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] _out_0_a_bits_WIRE_opcode;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_opcode = out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [2:0] _out_0_a_bits_WIRE_param;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_param = out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n wire [3:0] _out_0_a_bits_WIRE_size;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_size = out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n wire [1:0] _out_0_a_bits_WIRE_source;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_source = out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n wire [31:0] _out_0_a_bits_WIRE_address;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_address = out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n wire [7:0] _out_0_a_bits_WIRE_mask;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_mask = out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n wire [63:0] _out_0_a_bits_WIRE_data;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_data = out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n wire _portsBIO_out_0_b_ready_WIRE;\t// @[Mux.scala:30:73]\n assign anonOut_b_ready = out_0_b_ready;\t// @[Xbar.scala:216:19]\n assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign portsBIO_filtered_0_bits_param = out_0_b_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign portsBIO_filtered_0_bits_size = out_0_b_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n wire [1:0] _requestBOI_uncommonBits_T = out_0_b_bits_source;\t// @[Xbar.scala:216:19]\n assign portsBIO_filtered_0_bits_source = out_0_b_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n wire [1:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign portsBIO_filtered_0_bits_address = out_0_b_bits_address;\t// @[Xbar.scala:216:19, :352:24]\n wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address;\t// @[Xbar.scala:216:19, :352:24]\n assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask;\t// @[Xbar.scala:216:19, :352:24]\n wire [7:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask;\t// @[Xbar.scala:216:19, :352:24]\n assign portsBIO_filtered_0_bits_data = out_0_b_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n wire [63:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign portsCOI_filtered_0_ready = out_0_c_ready;\t// @[Xbar.scala:216:19, :352:24]\n wire portsCOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign anonOut_c_valid = out_0_c_valid;\t// @[Xbar.scala:216:19]\n assign anonOut_c_bits_opcode = out_0_c_bits_opcode;\t// @[Xbar.scala:216:19]\n assign anonOut_c_bits_param = out_0_c_bits_param;\t// @[Xbar.scala:216:19]\n assign anonOut_c_bits_size = out_0_c_bits_size;\t// @[Xbar.scala:216:19]\n assign anonOut_c_bits_source = out_0_c_bits_source;\t// @[Xbar.scala:216:19]\n assign anonOut_c_bits_address = out_0_c_bits_address;\t// @[Xbar.scala:216:19]\n assign anonOut_c_bits_data = out_0_c_bits_data;\t// @[Xbar.scala:216:19]\n wire _portsDIO_out_0_d_ready_WIRE;\t// @[Mux.scala:30:73]\n assign anonOut_d_ready = out_0_d_ready;\t// @[Xbar.scala:216:19]\n assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_param = out_0_d_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_param = out_0_d_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_size = out_0_d_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_size = out_0_d_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n wire [1:0] _requestDOI_uncommonBits_T = out_0_d_bits_source;\t// @[Xbar.scala:216:19]\n assign portsDIO_filtered_0_bits_source = out_0_d_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_source = out_0_d_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_data = out_0_d_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_data = out_0_d_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign portsEOI_filtered_0_ready = out_0_e_ready;\t// @[Xbar.scala:216:19, :352:24]\n wire portsEOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign anonOut_e_valid = out_0_e_valid;\t// @[Xbar.scala:216:19]\n assign _anonOut_e_bits_sink_T = out_0_e_bits_sink;\t// @[Xbar.scala:156:69, :216:19]\n assign out_0_d_bits_sink = _out_0_d_bits_sink_T;\t// @[Xbar.scala:216:19, :251:53]\n assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T;\t// @[Xbar.scala:156:69]\n wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T};\t// @[Parameters.scala:137:{31,41}]\n wire requestBOI_uncommonBits = _requestBOI_uncommonBits_T[0];\t// @[Parameters.scala:52:{29,56}]\n wire _requestBOI_T = out_0_b_bits_source[1];\t// @[Xbar.scala:216:19]\n wire _requestBOI_T_1 = ~_requestBOI_T;\t// @[Parameters.scala:54:{10,32}]\n wire _requestBOI_T_3 = _requestBOI_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire requestBOI_0_0 = _requestBOI_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _portsBIO_filtered_0_valid_T = requestBOI_0_0;\t// @[Xbar.scala:355:54]\n wire requestBOI_0_1 = out_0_b_bits_source == 2'h2;\t// @[Xbar.scala:216:19]\n wire _portsBIO_filtered_1_valid_T = requestBOI_0_1;\t// @[Xbar.scala:355:54]\n wire requestDOI_uncommonBits = _requestDOI_uncommonBits_T[0];\t// @[Parameters.scala:52:{29,56}]\n wire _requestDOI_T = out_0_d_bits_source[1];\t// @[Xbar.scala:216:19]\n wire _requestDOI_T_1 = ~_requestDOI_T;\t// @[Parameters.scala:54:{10,32}]\n wire _requestDOI_T_3 = _requestDOI_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire requestDOI_0_0 = _requestDOI_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _portsDIO_filtered_0_valid_T = requestDOI_0_0;\t// @[Xbar.scala:355:54]\n wire requestDOI_0_1 = out_0_d_bits_source == 2'h2;\t// @[Xbar.scala:216:19]\n wire _portsDIO_filtered_1_valid_T = requestDOI_0_1;\t// @[Xbar.scala:355:54]\n wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1;\t// @[Mux.scala:30:73]\n wire [2:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _beatsAI_opdata_T = in_0_a_bits_opcode[2];\t// @[Xbar.scala:159:18]\n wire beatsAI_opdata = ~_beatsAI_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] beatsBO_decode = _beatsBO_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _beatsBO_opdata_T = out_0_b_bits_opcode[2];\t// @[Xbar.scala:216:19]\n wire beatsBO_opdata = ~_beatsBO_opdata_T;\t// @[Edges.scala:97:{28,37}]\n wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] beatsCI_decode = _beatsCI_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire beatsCI_opdata = in_0_c_bits_opcode[0];\t// @[Xbar.scala:159:18]\n wire [8:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 9'h0;\t// @[Edges.scala:102:36, :220:59, :221:14]\n wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire beatsDO_opdata = out_0_d_bits_opcode[0];\t// @[Xbar.scala:216:19]\n wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n wire _filtered_0_ready_T;\t// @[Arbiter.scala:94:31]\n assign in_0_a_ready = portsAOI_filtered_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _filtered_0_ready_T_1;\t// @[Arbiter.scala:94:31]\n assign in_1_a_ready = portsAOI_filtered_1_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]\n assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsBIO_filtered_0_valid_T_1;\t// @[Xbar.scala:355:40]\n assign in_0_b_valid = portsBIO_filtered_0_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_param = portsBIO_filtered_0_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_size = portsBIO_filtered_0_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_source = portsBIO_filtered_0_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_address = portsBIO_filtered_0_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_data = portsBIO_filtered_0_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire _portsBIO_filtered_1_valid_T_1;\t// @[Xbar.scala:355:40]\n wire portsBIO_filtered_1_valid;\t// @[Xbar.scala:352:24]\n assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready;\t// @[Mux.scala:30:73]\n wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T;\t// @[Mux.scala:30:73]\n assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2;\t// @[Mux.scala:30:73]\n assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE;\t// @[Mux.scala:30:73]\n assign in_0_c_ready = portsCOI_filtered_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n assign out_0_c_valid = portsCOI_filtered_0_valid;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_c_bits_param = portsCOI_filtered_0_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_c_bits_size = portsCOI_filtered_0_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_c_bits_source = portsCOI_filtered_0_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_c_bits_address = portsCOI_filtered_0_bits_address;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_c_bits_data = portsCOI_filtered_0_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsDIO_filtered_0_valid_T_1;\t// @[Xbar.scala:355:40]\n assign in_0_d_valid = portsDIO_filtered_0_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_param = portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_size = portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_source = portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_data = portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire _portsDIO_filtered_1_valid_T_1;\t// @[Xbar.scala:355:40]\n assign in_1_d_valid = portsDIO_filtered_1_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_param = portsDIO_filtered_1_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_size = portsDIO_filtered_1_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_source = portsDIO_filtered_1_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_data = portsDIO_filtered_1_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready;\t// @[Mux.scala:30:73]\n wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1;\t// @[Mux.scala:30:73]\n assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2;\t// @[Mux.scala:30:73]\n assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE;\t// @[Mux.scala:30:73]\n assign in_0_e_ready = portsEOI_filtered_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n assign out_0_e_valid = portsEOI_filtered_0_valid;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n reg [8:0] beatsLeft;\t// @[Arbiter.scala:60:30]\n wire idle = beatsLeft == 9'h0;\t// @[Arbiter.scala:60:30, :61:28]\n wire latch = idle & out_0_a_ready;\t// @[Xbar.scala:216:19]\n wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid};\t// @[Xbar.scala:352:24]\n wire [1:0] readys_valid = _readys_T;\t// @[Arbiter.scala:21:23, :68:51]\n wire _readys_T_1 = readys_valid == _readys_T;\t// @[Arbiter.scala:21:23, :22:19, :68:51]\n wire _readys_T_3 = ~_readys_T_2;\t// @[Arbiter.scala:22:12]\n wire _readys_T_4 = ~_readys_T_1;\t// @[Arbiter.scala:22:{12,19}]\n reg [1:0] readys_mask;\t// @[Arbiter.scala:23:23]\n wire [1:0] _readys_filter_T = ~readys_mask;\t// @[Arbiter.scala:23:23, :24:30]\n wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T;\t// @[Arbiter.scala:21:23, :24:{28,30}]\n wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid};\t// @[Arbiter.scala:21:23, :24:{21,28}]\n wire [2:0] _readys_unready_T = readys_filter[3:1];\t// @[package.scala:262:48]\n wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T};\t// @[package.scala:262:{43,48}]\n wire [3:0] _readys_unready_T_2 = _readys_unready_T_1;\t// @[package.scala:262:43, :263:17]\n wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1];\t// @[package.scala:263:17]\n wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0};\t// @[Arbiter.scala:23:23, :25:66]\n wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4;\t// @[Arbiter.scala:25:{52,58,66}]\n wire [1:0] _readys_readys_T = readys_unready[3:2];\t// @[Arbiter.scala:25:58, :26:29]\n wire [1:0] _readys_readys_T_1 = readys_unready[1:0];\t// @[Arbiter.scala:25:58, :26:48]\n wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1;\t// @[Arbiter.scala:26:{29,39,48}]\n wire [1:0] readys_readys = ~_readys_readys_T_2;\t// @[Arbiter.scala:26:{18,39}]\n wire [1:0] _readys_T_7 = readys_readys;\t// @[Arbiter.scala:26:18, :30:11]\n wire _readys_T_5 = |readys_valid;\t// @[Arbiter.scala:21:23, :27:27]\n wire _readys_T_6 = latch & _readys_T_5;\t// @[Arbiter.scala:27:{18,27}, :62:24]\n wire [1:0] _readys_mask_T = readys_readys & readys_valid;\t// @[Arbiter.scala:21:23, :26:18, :28:29]\n wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0};\t// @[package.scala:253:48]\n wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0];\t// @[package.scala:253:{48,53}]\n wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2;\t// @[package.scala:253:{43,53}]\n wire [1:0] _readys_mask_T_4 = _readys_mask_T_3;\t// @[package.scala:253:43, :254:17]\n wire _readys_T_8 = _readys_T_7[0];\t// @[Arbiter.scala:30:11, :68:76]\n wire readys_0 = _readys_T_8;\t// @[Arbiter.scala:68:{27,76}]\n wire _readys_T_9 = _readys_T_7[1];\t// @[Arbiter.scala:30:11, :68:76]\n wire readys_1 = _readys_T_9;\t// @[Arbiter.scala:68:{27,76}]\n wire _winner_T = readys_0 & portsAOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n wire winner_0 = _winner_T;\t// @[Arbiter.scala:71:{27,69}]\n wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]\n wire winner_1 = _winner_T_1;\t// @[Arbiter.scala:71:{27,69}]\n wire prefixOR_1 = winner_0;\t// @[Arbiter.scala:71:27, :76:48]\n wire _prefixOR_T = prefixOR_1 | winner_1;\t// @[Arbiter.scala:71:27, :76:48]\n wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]"}}},{"rowIdx":32199,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49 : \n output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} \n\n\n node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) \n node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) \n node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) \n node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) \n node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) \n node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) \n node _roundMagUp_T = and(roundingMode_min, io.in.sign) \n node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) \n node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) \n node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) \n node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) \n node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) \n node sAdjustedExp = cvt(_sAdjustedExp_T_1) \n node adjustedSig = shl(io.in.sig, 25) \n wire common_expOut : UInt<9> \n wire common_fractOut : UInt<23> \n wire common_overflow : UInt<1> \n wire common_totalUnderflow : UInt<1> \n wire common_underflow : UInt<1> \n wire common_inexact : UInt<1> \n node _common_expOut_T = bits(sAdjustedExp, 8, 0) \n node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) \n node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) \n connect common_expOut, _common_expOut_T_2 \n node _common_fractOut_T = bits(adjustedSig, 25, 3) \n node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) \n node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) \n connect common_fractOut, _common_fractOut_T_2 \n connect common_overflow, UInt<1>(0h0) \n connect common_totalUnderflow, UInt<1>(0h0) \n connect common_underflow, UInt<1>(0h0) \n connect common_inexact, UInt<1>(0h0) \n node isNaNOut = or(io.invalidExc, io.in.isNaN) \n node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) \n node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) \n node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) \n node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) \n node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) \n node commonCase = and(_commonCase_T_2, _commonCase_T_3) \n node overflow = and(commonCase, common_overflow) \n node underflow = and(commonCase, common_underflow) \n node _inexact_T = and(commonCase, common_inexact) \n node inexact = or(overflow, _inexact_T) \n node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) \n node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) \n node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) \n node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) \n node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) \n node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) \n node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) \n node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) \n node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) \n node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) \n node _expOut_T = or(io.in.isZero, common_totalUnderflow) \n node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) \n node _expOut_T_2 = not(_expOut_T_1) \n node _expOut_T_3 = and(common_expOut, _expOut_T_2) \n node _expOut_T_4 = not(UInt<9>(0h6b)) \n node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) \n node _expOut_T_6 = not(_expOut_T_5) \n node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) \n node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) \n node _expOut_T_9 = not(_expOut_T_8) \n node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) \n node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) \n node _expOut_T_12 = not(_expOut_T_11) \n node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) \n node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) \n node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) \n node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) \n node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) \n node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) \n node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) \n node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) \n node expOut = or(_expOut_T_19, _expOut_T_20) \n node _fractOut_T = or(isNaNOut, io.in.isZero) \n node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) \n node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) \n node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) \n node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) \n node fractOut = or(_fractOut_T_3, _fractOut_T_4) \n node _io_out_T = cat(signOut, expOut) \n node _io_out_T_1 = cat(_io_out_T, fractOut) \n connect io.out, _io_out_T_1 \n node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) \n node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) \n node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) \n node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) \n connect io.exceptionFlags, _io_exceptionFlags_T_3"},"response":{"kind":"string","value":"module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49();\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire [8:0] _expOut_T_4 = 9'h194;\t// @[RoundAnyRawFNToRecFN.scala:258:19]\n wire [26:0] adjustedSig = 27'h2000000;\t// @[RoundAnyRawFNToRecFN.scala:114:22]\n wire [22:0] _common_fractOut_T = 23'h400000;\t// @[RoundAnyRawFNToRecFN.scala:139:28]\n wire [8:0] _expOut_T_2 = 9'h1FF;\t// @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]\n wire [8:0] _expOut_T_6 = 9'h1FF;\t// @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]\n wire [8:0] _expOut_T_9 = 9'h1FF;\t// @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]\n wire [8:0] _expOut_T_12 = 9'h1FF;\t// @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]\n wire [8:0] _expOut_T_1 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _expOut_T_5 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _expOut_T_8 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _expOut_T_11 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _expOut_T_14 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _expOut_T_16 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _expOut_T_18 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _expOut_T_20 = 9'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]\n wire [8:0] _sAdjustedExp_T_1 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] common_expOut = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _common_expOut_T = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _common_expOut_T_2 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _expOut_T_3 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _expOut_T_7 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _expOut_T_10 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _expOut_T_13 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _expOut_T_15 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _expOut_T_17 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] _expOut_T_19 = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [8:0] expOut = 9'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]\n wire [22:0] common_fractOut = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]\n wire [22:0] _common_fractOut_T_1 = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]\n wire [22:0] _common_fractOut_T_2 = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]\n wire [22:0] _fractOut_T_2 = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]\n wire [22:0] _fractOut_T_3 = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]\n wire [22:0] _fractOut_T_4 = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]\n wire [22:0] fractOut = 23'h0;\t// @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]\n wire [9:0] _sAdjustedExp_T = 10'h100;\t// @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]\n wire [9:0] sAdjustedExp = 10'h100;\t// @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]\n wire [9:0] _common_expOut_T_1 = 10'h100;\t// @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]\n wire [9:0] _io_out_T = 10'h100;\t// @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]\n wire [1:0] _io_exceptionFlags_T = 2'h0;\t// @[RoundAnyRawFNToRecFN.scala:288:23]\n wire [3:0] _io_exceptionFlags_T_2 = 4'h0;\t// @[RoundAnyRawFNToRecFN.scala:288:53]\n wire [4:0] io_exceptionFlags = 5'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]\n wire [4:0] _io_exceptionFlags_T_3 = 5'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]\n wire [32:0] io_out = 33'h80000000;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]\n wire [32:0] _io_out_T_1 = 33'h80000000;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]\n wire io_detectTininess = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire roundingMode_near_even = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire _roundMagUp_T_1 = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire _commonCase_T = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire _commonCase_T_1 = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire _commonCase_T_2 = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire _commonCase_T_3 = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire commonCase = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire _overflow_roundMagUp_T = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire overflow_roundMagUp = 1'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]\n wire [2:0] io_roundingMode = 3'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]\n wire [2:0] _io_exceptionFlags_T_1 = 3'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]\n wire [1:0] io_in_sig = 2'h1;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]\n wire [3:0] io_in_sExp = 4'h4;\t// @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]\n wire io_invalidExc = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_infiniteExc = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isNaN = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isInf = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_isZero = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire io_in_sign = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:48:5]\n wire roundingMode_minMag = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:91:53]\n wire roundingMode_min = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:92:53]\n wire roundingMode_max = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:93:53]\n wire roundingMode_near_maxMag = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:94:53]\n wire roundingMode_odd = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:95:53]\n wire _roundMagUp_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:98:27]\n wire _roundMagUp_T_2 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:98:63]\n wire roundMagUp = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:98:42]\n wire common_overflow = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:124:37]\n wire common_totalUnderflow = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:125:37]\n wire common_underflow = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:126:37]\n wire common_inexact = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:127:37]\n wire isNaNOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:235:34]\n wire notNaN_isSpecialInfOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:236:49]\n wire overflow = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:238:32]\n wire underflow = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:239:32]\n wire _inexact_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:240:43]\n wire inexact = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:240:28]\n wire _pegMinNonzeroMagOut_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:245:20]\n wire _pegMinNonzeroMagOut_T_1 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:245:60]\n wire pegMinNonzeroMagOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:245:45]\n wire _pegMaxFiniteMagOut_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:246:42]\n wire pegMaxFiniteMagOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:246:39]\n wire _notNaN_isInfOut_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:248:45]\n wire notNaN_isInfOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:248:32]\n wire signOut = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:250:22]\n wire _expOut_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:253:32]\n wire _fractOut_T = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:280:22]\n wire _fractOut_T_1 = 1'h0;\t// @[RoundAnyRawFNToRecFN.scala:280:38]\nendmodule"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":321,"numItemsPerPage":100,"numTotalItems":35529,"offset":32100,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc1MjU5NDQyNywic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vY2hpc2VsLXZlcmlsb2ctcGFpcnMiLCJleHAiOjE3NTI1OTgwMjcsImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.uEMI4uTdg8QC28GWh8-4RI4Efko6_y3MZRwDzs_PvoA7IHtCctJDLy2ZstxIVnt9dq64FzMJU8_gRCOimDlkDg","displayUrls":true},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
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Generate the Verilog code corresponding to this FIRRTL code module MacUnit_194 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_194( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_CLINT :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_24
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0)
reg dOrig : UInt, clock
regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0)
node dFragnum = bits(anonOut.d.bits.source, 2, 0)
node dFirst = eq(acknum, UInt<1>(0h0))
node dLast = eq(dFragnum, UInt<1>(0h0))
node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0)
node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount)
node dsizeOH = bits(_dsizeOH_T, 3, 0)
node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size)
node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0)
node dsizeOH1 = not(_dsizeOH1_T_1)
node dHasData = bits(anonOut.d.bits.opcode, 0, 0)
node acknum_fragment = shl(dFragnum, 0)
node acknum_size = shr(dsizeOH1, 3)
node _T = eq(anonOut.d.valid, UInt<1>(0h0))
node _T_1 = and(acknum_fragment, acknum_size)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = or(_T, _T_2)
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0))
node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T)
node _ack_decrement_T = shr(dsizeOH, 3)
node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T)
node _dFirst_size_T = shl(dFragnum, 3)
node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1)
node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1)
node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1))
node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1)
node _dFirst_size_T_5 = not(_dFirst_size_T_4)
node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5)
node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4)
node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0)
node _dFirst_size_T_7 = orr(dFirst_size_hi)
node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo)
node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2)
node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0)
node _dFirst_size_T_9 = orr(dFirst_size_hi_1)
node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1)
node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1)
node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11)
node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12)
node _T_7 = and(anonOut.d.ready, anonOut.d.valid)
when _T_7 :
node _acknum_T = sub(acknum, ack_decrement)
node _acknum_T_1 = tail(_acknum_T, 1)
node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1)
connect acknum, _acknum_T_2
when dFirst :
connect dOrig, dFirst_size
node _dToggle_T = bits(anonOut.d.bits.source, 3, 3)
connect dToggle, _dToggle_T
node _drop_T = eq(dHasData, UInt<1>(0h0))
node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast)
node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0))
node drop = and(_drop_T, _drop_T_2)
node _anonOut_d_ready_T = or(anonIn.d.ready, drop)
connect anonOut.d.ready, _anonOut_d_ready_T
node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0))
node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T)
connect anonIn.d.valid, _anonIn_d_valid_T_1
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig)
connect anonIn.d.bits.size, _anonIn_d_bits_size_T
inst repeater of Repeater_TLBundleA_a26d64s7k1z3u_1
connect repeater.clock, clock
connect repeater.reset, reset
connect repeater.io.enq, anonIn.a
node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0))
node _find_T_1 = cvt(_find_T)
node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0)))
node _find_T_3 = asSInt(_find_T_2)
node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0)))
wire find : UInt<1>[1]
connect find[0], _find_T_4
node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode)
node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3))
node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode)
node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1)
node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode)
node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3)
node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode)
node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5)
node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode)
node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7)
node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode)
node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9)
node _aFrag_T = gt(repeater.io.deq.bits.size, limit)
node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size)
node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size)
node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0)
node aOrigOH1 = not(_aOrigOH1_T_1)
node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag)
node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0)
node aFragOH1 = not(_aFragOH1_T_1)
node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2)
node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0))
node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1)
regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0)
node aFirst = eq(gennum, UInt<1>(0h0))
node _old_gennum1_T = shr(aOrigOH1, 3)
node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1))
node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1)
node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2)
node _new_gennum_T = not(old_gennum1)
node _new_gennum_T_1 = shr(aMask, 3)
node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1)
node new_gennum = not(_new_gennum_T_2)
node _aFragnum_T = shr(old_gennum1, 0)
node _aFragnum_T_1 = not(_aFragnum_T)
node _aFragnum_T_2 = shr(aFragOH1, 3)
node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2)
node aFragnum = not(_aFragnum_T_3)
node aLast = eq(aFragnum, UInt<1>(0h0))
reg aToggle_r : UInt<1>, clock
when aFirst :
connect aToggle_r, dToggle
node _aToggle_T = mux(aFirst, dToggle, aToggle_r)
node aToggle = eq(_aToggle_T, UInt<1>(0h0))
node _T_8 = and(anonOut.a.ready, anonOut.a.valid)
when _T_8 :
connect gennum, new_gennum
node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0))
node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0))
node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1)
connect repeater.io.repeat, _repeater_io_repeat_T_2
connect anonOut.a.bits, repeater.io.deq.bits
connect anonOut.a.valid, repeater.io.deq.valid
connect repeater.io.deq.ready, anonOut.a.ready
node _anonOut_a_bits_address_T = shl(old_gennum1, 3)
node _anonOut_a_bits_address_T_1 = not(aOrigOH1)
node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1)
node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1)
node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7))
node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4)
node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5)
connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6
node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle)
node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum)
connect anonOut.a.bits.source, _anonOut_a_bits_source_T
connect anonOut.a.bits.size, aFrag
node _T_9 = eq(repeater.io.full, UInt<1>(0h0))
node _T_10 = eq(aHasData, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
connect anonOut.a.bits.data, anonIn.a.bits.data
node _T_15 = eq(repeater.io.full, UInt<1>(0h0))
node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff))
node _T_17 = or(_T_15, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T
wire anonOut_a_bits_user_out : { }
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLFragmenter_CLINT( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30]
wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [25:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49]
wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18]
wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}]
wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}]
wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}]
reg aToggle_r; // @[Fragmenter.scala:309:54] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = or(_T_667, _T_672)
node _T_709 = or(_T_708, _T_677)
node _T_710 = or(_T_709, _T_682)
node _T_711 = or(_T_710, _T_687)
node _T_712 = or(_T_711, _T_692)
node _T_713 = or(_T_712, _T_697)
node _T_714 = or(_T_713, _T_702)
node _T_715 = or(_T_714, _T_707)
node _T_716 = and(_T_662, _T_715)
node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_716)
node _T_725 = or(_T_724, _T_723)
node _T_726 = and(_T_658, _T_725)
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_726, UInt<1>(0h1), "") : assert_36
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_736, UInt<1>(0h1), "") : assert_39
node _T_740 = eq(io.in.a.bits.mask, mask)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_740, UInt<1>(0h1), "") : assert_40
node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_753 = and(_T_751, _T_752)
node _T_754 = or(UInt<1>(0h0), _T_753)
node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_759, _T_764)
node _T_801 = or(_T_800, _T_769)
node _T_802 = or(_T_801, _T_774)
node _T_803 = or(_T_802, _T_779)
node _T_804 = or(_T_803, _T_784)
node _T_805 = or(_T_804, _T_789)
node _T_806 = or(_T_805, _T_794)
node _T_807 = or(_T_806, _T_799)
node _T_808 = and(_T_754, _T_807)
node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = and(_T_809, _T_814)
node _T_816 = or(UInt<1>(0h0), _T_808)
node _T_817 = or(_T_816, _T_815)
node _T_818 = and(_T_750, _T_817)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_818, UInt<1>(0h1), "") : assert_41
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(is_aligned, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_828, UInt<1>(0h1), "") : assert_44
node _T_832 = eq(io.in.a.bits.mask, mask)
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_832, UInt<1>(0h1), "") : assert_45
node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_836 :
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = or(_T_858, _T_863)
node _T_890 = or(_T_889, _T_868)
node _T_891 = or(_T_890, _T_873)
node _T_892 = or(_T_891, _T_878)
node _T_893 = or(_T_892, _T_883)
node _T_894 = or(_T_893, _T_888)
node _T_895 = and(_T_853, _T_894)
node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_898 = and(_T_896, _T_897)
node _T_899 = or(UInt<1>(0h0), _T_898)
node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_901 = cvt(_T_900)
node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000)))
node _T_903 = asSInt(_T_902)
node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0)))
node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_906 = cvt(_T_905)
node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000)))
node _T_908 = asSInt(_T_907)
node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0)))
node _T_910 = or(_T_904, _T_909)
node _T_911 = and(_T_899, _T_910)
node _T_912 = or(UInt<1>(0h0), _T_852)
node _T_913 = or(_T_912, _T_895)
node _T_914 = or(_T_913, _T_911)
node _T_915 = and(_T_842, _T_914)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_915, UInt<1>(0h1), "") : assert_46
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(is_aligned, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_925, UInt<1>(0h1), "") : assert_49
node _T_929 = eq(io.in.a.bits.mask, mask)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_929, UInt<1>(0h1), "") : assert_50
node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_933, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_937, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20))
node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_941 :
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_945, UInt<1>(0h1), "") : assert_54
node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_949, UInt<1>(0h1), "") : assert_55
node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_953, UInt<1>(0h1), "") : assert_56
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_957, UInt<1>(0h1), "") : assert_57
node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_961 :
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(sink_ok, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_968, UInt<1>(0h1), "") : assert_60
node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_972, UInt<1>(0h1), "") : assert_61
node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_976, UInt<1>(0h1), "") : assert_62
node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_980, UInt<1>(0h1), "") : assert_63
node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_985 = or(UInt<1>(0h1), _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_985, UInt<1>(0h1), "") : assert_64
node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_989 :
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(sink_ok, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_T_996, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_996, UInt<1>(0h1), "") : assert_67
node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68
node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69
node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1009 = or(_T_1008, io.in.d.bits.corrupt)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70
node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1014 = or(UInt<1>(0h1), _T_1013)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71
node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73
node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74
node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1031 = or(UInt<1>(0h1), _T_1030)
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75
node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1035 :
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77
node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1044 = or(_T_1043, io.in.d.bits.corrupt)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78
node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1049 = or(UInt<1>(0h1), _T_1048)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79
node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1053 :
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81
node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82
node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1066 = or(UInt<1>(0h1), _T_1065)
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_4.bits.sink, UInt<5>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1082 = eq(a_first, UInt<1>(0h0))
node _T_1083 = and(io.in.a.valid, _T_1082)
when _T_1083 :
node _T_1084 = eq(io.in.a.bits.opcode, opcode)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87
node _T_1088 = eq(io.in.a.bits.param, param)
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88
node _T_1092 = eq(io.in.a.bits.size, size)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89
node _T_1096 = eq(io.in.a.bits.source, source)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90
node _T_1100 = eq(io.in.a.bits.address, address)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91
node _T_1104 = and(io.in.a.ready, io.in.a.valid)
node _T_1105 = and(_T_1104, a_first)
when _T_1105 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1106 = eq(d_first, UInt<1>(0h0))
node _T_1107 = and(io.in.d.valid, _T_1106)
when _T_1107 :
node _T_1108 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92
node _T_1112 = eq(io.in.d.bits.param, param_1)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93
node _T_1116 = eq(io.in.d.bits.size, size_1)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94
node _T_1120 = eq(io.in.d.bits.source, source_1)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95
node _T_1124 = eq(io.in.d.bits.sink, sink)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96
node _T_1128 = eq(io.in.d.bits.denied, denied)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97
node _T_1132 = and(io.in.d.ready, io.in.d.valid)
node _T_1133 = and(_T_1132, d_first)
when _T_1133 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1134 = and(io.in.a.valid, a_first_1)
node _T_1135 = and(_T_1134, UInt<1>(0h1))
when _T_1135 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1136 = and(io.in.a.ready, io.in.a.valid)
node _T_1137 = and(_T_1136, a_first_1)
node _T_1138 = and(_T_1137, UInt<1>(0h1))
when _T_1138 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1139 = dshr(inflight, io.in.a.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1145 = and(io.in.d.valid, d_first_1)
node _T_1146 = and(_T_1145, UInt<1>(0h1))
node _T_1147 = eq(d_release_ack, UInt<1>(0h0))
node _T_1148 = and(_T_1146, _T_1147)
when _T_1148 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1149 = and(io.in.d.ready, io.in.d.valid)
node _T_1150 = and(_T_1149, d_first_1)
node _T_1151 = and(_T_1150, UInt<1>(0h1))
node _T_1152 = eq(d_release_ack, UInt<1>(0h0))
node _T_1153 = and(_T_1151, _T_1152)
when _T_1153 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1154 = and(io.in.d.valid, d_first_1)
node _T_1155 = and(_T_1154, UInt<1>(0h1))
node _T_1156 = eq(d_release_ack, UInt<1>(0h0))
node _T_1157 = and(_T_1155, _T_1156)
when _T_1157 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1158 = dshr(inflight, io.in.d.bits.source)
node _T_1159 = bits(_T_1158, 0, 0)
node _T_1160 = or(_T_1159, same_cycle_resp)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1166 = or(_T_1164, _T_1165)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100
node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101
else :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102
node _T_1180 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103
node _T_1184 = and(io.in.d.valid, d_first_1)
node _T_1185 = and(_T_1184, a_first_1)
node _T_1186 = and(_T_1185, io.in.a.valid)
node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(d_release_ack, UInt<1>(0h0))
node _T_1190 = and(_T_1188, _T_1189)
when _T_1190 :
node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1192 = or(_T_1191, io.in.a.ready)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104
node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1197 = orr(a_set_wo_ready)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = or(_T_1196, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_33
node _T_1203 = orr(inflight)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1206 = or(_T_1204, _T_1205)
node _T_1207 = lt(watchdog, plusarg_reader.out)
node _T_1208 = or(_T_1206, _T_1207)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1212 = and(io.in.a.ready, io.in.a.valid)
node _T_1213 = and(io.in.d.ready, io.in.d.valid)
node _T_1214 = or(_T_1212, _T_1213)
when _T_1214 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1215 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1218 = and(_T_1216, _T_1217)
node _T_1219 = and(_T_1215, _T_1218)
when _T_1219 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1221 = and(_T_1220, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1224 = and(_T_1222, _T_1223)
node _T_1225 = and(_T_1221, _T_1224)
when _T_1225 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1227 = bits(_T_1226, 0, 0)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1232 = and(io.in.d.valid, d_first_2)
node _T_1233 = and(_T_1232, UInt<1>(0h1))
node _T_1234 = and(_T_1233, d_release_ack_1)
when _T_1234 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1235 = and(io.in.d.ready, io.in.d.valid)
node _T_1236 = and(_T_1235, d_first_2)
node _T_1237 = and(_T_1236, UInt<1>(0h1))
node _T_1238 = and(_T_1237, d_release_ack_1)
when _T_1238 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1239 = and(io.in.d.valid, d_first_2)
node _T_1240 = and(_T_1239, UInt<1>(0h1))
node _T_1241 = and(_T_1240, d_release_ack_1)
when _T_1241 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1242 = dshr(inflight_1, io.in.d.bits.source)
node _T_1243 = bits(_T_1242, 0, 0)
node _T_1244 = or(_T_1243, same_cycle_resp_1)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109
else :
node _T_1252 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110
node _T_1256 = and(io.in.d.valid, d_first_2)
node _T_1257 = and(_T_1256, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1258 = and(_T_1257, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1260 = and(_T_1258, _T_1259)
node _T_1261 = and(_T_1260, d_release_ack_1)
node _T_1262 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1263 = and(_T_1261, _T_1262)
when _T_1263 :
node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1265 = or(_T_1264, _WIRE_23.ready)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111
node _T_1269 = orr(c_set_wo_ready)
when _T_1269 :
node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_34
node _T_1274 = orr(inflight_1)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1277 = or(_T_1275, _T_1276)
node _T_1278 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1279 = or(_T_1277, _T_1278)
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1284 = and(io.in.d.ready, io.in.d.valid)
node _T_1285 = or(_T_1283, _T_1284)
when _T_1285 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_35 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_36 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_12( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLDFromBeat_serial_tl_0_a64d64s8k8z8c :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<65>, head : UInt<1>, tail : UInt<1>}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect io.protocol, protocol
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<30>, clock
node const = mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
node _io_beat_ready_T = eq(io.beat.bits.tail, UInt<1>(0h0))
node _io_beat_ready_T_1 = and(is_const, _io_beat_ready_T)
node _io_beat_ready_T_2 = or(_io_beat_ready_T_1, protocol.ready)
connect io.beat.ready, _io_beat_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.beat.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.beat.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_denied_WIRE : UInt<1>
connect _protocol_bits_denied_WIRE, const
connect protocol.bits.denied, _protocol_bits_denied_WIRE
node _T = shr(const, 1)
wire _protocol_bits_sink_WIRE : UInt<8>
connect _protocol_bits_sink_WIRE, _T
connect protocol.bits.sink, _protocol_bits_sink_WIRE
node _T_1 = shr(_T, 8)
wire _protocol_bits_echo_WIRE : { }
wire _protocol_bits_echo_WIRE_1 : UInt<0>
connect _protocol_bits_echo_WIRE_1, _T_1
connect protocol.bits.echo, _protocol_bits_echo_WIRE
node _T_2 = shr(_T_1, 0)
wire _protocol_bits_user_WIRE : { }
wire _protocol_bits_user_WIRE_1 : UInt<0>
connect _protocol_bits_user_WIRE_1, _T_2
connect protocol.bits.user, _protocol_bits_user_WIRE
node _T_3 = shr(_T_2, 0)
wire _protocol_bits_source_WIRE : UInt<8>
connect _protocol_bits_source_WIRE, _T_3
connect protocol.bits.source, _protocol_bits_source_WIRE
node _T_4 = shr(_T_3, 8)
wire _protocol_bits_size_WIRE : UInt<8>
connect _protocol_bits_size_WIRE, _T_4
connect protocol.bits.size, _protocol_bits_size_WIRE
node _T_5 = shr(_T_4, 8)
wire _protocol_bits_param_WIRE : UInt<2>
connect _protocol_bits_param_WIRE, _T_5
connect protocol.bits.param, _protocol_bits_param_WIRE
node _T_6 = shr(_T_5, 2)
wire _protocol_bits_opcode_WIRE : UInt<3>
connect _protocol_bits_opcode_WIRE, _T_6
connect protocol.bits.opcode, _protocol_bits_opcode_WIRE
node _T_7 = shr(_T_6, 3)
wire _protocol_bits_corrupt_WIRE : UInt<1>
connect _protocol_bits_corrupt_WIRE, io.beat.bits.payload
connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE
node _T_8 = shr(io.beat.bits.payload, 1)
wire _protocol_bits_data_WIRE : UInt<64>
connect _protocol_bits_data_WIRE, _T_8
connect protocol.bits.data, _protocol_bits_data_WIRE
node _T_9 = shr(_T_8, 64)
node _T_10 = and(io.beat.ready, io.beat.valid)
node _T_11 = and(_T_10, io.beat.bits.head)
when _T_11 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.beat.bits.payload
node _T_12 = and(io.beat.ready, io.beat.valid)
node _T_13 = and(_T_12, io.beat.bits.tail)
when _T_13 :
connect is_const, UInt<1>(0h1) | module TLDFromBeat_serial_tl_0_a64d64s8k8z8c( // @[TLChannelCompactor.scala:134:7]
input clock, // @[TLChannelCompactor.scala:134:7]
input reset, // @[TLChannelCompactor.scala:134:7]
output io_protocol_valid, // @[TLChannelCompactor.scala:75:14]
output [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:75:14]
output [1:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:75:14]
output [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:75:14]
output [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:75:14]
output [7:0] io_protocol_bits_sink, // @[TLChannelCompactor.scala:75:14]
output io_protocol_bits_denied, // @[TLChannelCompactor.scala:75:14]
output [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:75:14]
output io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:75:14]
output io_beat_ready, // @[TLChannelCompactor.scala:75:14]
input io_beat_valid, // @[TLChannelCompactor.scala:75:14]
input [64:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_head, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_tail // @[TLChannelCompactor.scala:75:14]
);
wire io_beat_valid_0 = io_beat_valid; // @[TLChannelCompactor.scala:134:7]
wire [64:0] io_beat_bits_payload_0 = io_beat_bits_payload; // @[TLChannelCompactor.scala:134:7]
wire io_beat_bits_head_0 = io_beat_bits_head; // @[TLChannelCompactor.scala:134:7]
wire io_beat_bits_tail_0 = io_beat_bits_tail; // @[TLChannelCompactor.scala:134:7]
wire io_protocol_ready = 1'h0; // @[TLChannelCompactor.scala:134:7]
wire protocol_ready = 1'h0; // @[TLChannelCompactor.scala:83:22]
wire protocol_valid; // @[TLChannelCompactor.scala:83:22]
wire [2:0] protocol_bits_opcode; // @[TLChannelCompactor.scala:83:22]
wire [1:0] protocol_bits_param; // @[TLChannelCompactor.scala:83:22]
wire [7:0] protocol_bits_size; // @[TLChannelCompactor.scala:83:22]
wire [7:0] protocol_bits_source; // @[TLChannelCompactor.scala:83:22]
wire [7:0] protocol_bits_sink; // @[TLChannelCompactor.scala:83:22]
wire protocol_bits_denied; // @[TLChannelCompactor.scala:83:22]
wire [63:0] protocol_bits_data; // @[TLChannelCompactor.scala:83:22]
wire protocol_bits_corrupt; // @[TLChannelCompactor.scala:83:22]
wire _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53]
wire [2:0] io_protocol_bits_opcode_0; // @[TLChannelCompactor.scala:134:7]
wire [1:0] io_protocol_bits_param_0; // @[TLChannelCompactor.scala:134:7]
wire [7:0] io_protocol_bits_size_0; // @[TLChannelCompactor.scala:134:7]
wire [7:0] io_protocol_bits_source_0; // @[TLChannelCompactor.scala:134:7]
wire [7:0] io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:134:7]
wire io_protocol_bits_denied_0; // @[TLChannelCompactor.scala:134:7]
wire [63:0] io_protocol_bits_data_0; // @[TLChannelCompactor.scala:134:7]
wire io_protocol_bits_corrupt_0; // @[TLChannelCompactor.scala:134:7]
wire io_protocol_valid_0; // @[TLChannelCompactor.scala:134:7]
wire io_beat_ready_0; // @[TLChannelCompactor.scala:134:7]
wire _protocol_valid_T_2; // @[TLChannelCompactor.scala:92:54]
assign io_protocol_valid_0 = protocol_valid; // @[TLChannelCompactor.scala:83:22, :134:7]
wire [2:0] _protocol_bits_opcode_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_opcode_0 = protocol_bits_opcode; // @[TLChannelCompactor.scala:83:22, :134:7]
wire [1:0] _protocol_bits_param_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_param_0 = protocol_bits_param; // @[TLChannelCompactor.scala:83:22, :134:7]
wire [7:0] _protocol_bits_size_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_size_0 = protocol_bits_size; // @[TLChannelCompactor.scala:83:22, :134:7]
wire [7:0] _protocol_bits_source_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_source_0 = protocol_bits_source; // @[TLChannelCompactor.scala:83:22, :134:7]
wire [7:0] _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_sink_0 = protocol_bits_sink; // @[TLChannelCompactor.scala:83:22, :134:7]
wire _protocol_bits_denied_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_denied_0 = protocol_bits_denied; // @[TLChannelCompactor.scala:83:22, :134:7]
wire [63:0] _protocol_bits_data_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_data_0 = protocol_bits_data; // @[TLChannelCompactor.scala:83:22, :134:7]
wire _protocol_bits_corrupt_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_corrupt_0 = protocol_bits_corrupt; // @[TLChannelCompactor.scala:83:22, :134:7]
reg is_const; // @[TLChannelCompactor.scala:88:25]
reg [29:0] const_reg; // @[TLChannelCompactor.scala:89:22]
wire [64:0] const_0 = io_beat_bits_head_0 ? io_beat_bits_payload_0 : {35'h0, const_reg}; // @[TLChannelCompactor.scala:89:22, :90:18, :134:7]
wire _io_beat_ready_T = ~io_beat_bits_tail_0; // @[TLChannelCompactor.scala:91:33, :134:7]
wire _io_beat_ready_T_1 = is_const & _io_beat_ready_T; // @[TLChannelCompactor.scala:88:25, :91:{30,33}]
assign _io_beat_ready_T_2 = _io_beat_ready_T_1; // @[TLChannelCompactor.scala:91:{30,53}]
assign io_beat_ready_0 = _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53, :134:7]
wire _protocol_valid_T = ~is_const; // @[TLChannelCompactor.scala:88:25, :92:22]
wire _protocol_valid_T_1 = _protocol_valid_T | io_beat_bits_tail_0; // @[TLChannelCompactor.scala:92:{22,32}, :134:7]
assign _protocol_valid_T_2 = _protocol_valid_T_1 & io_beat_valid_0; // @[TLChannelCompactor.scala:92:{32,54}, :134:7]
assign protocol_valid = _protocol_valid_T_2; // @[TLChannelCompactor.scala:83:22, :92:54]
assign protocol_bits_denied = _protocol_bits_denied_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
assign _protocol_bits_denied_WIRE = const_0[0]; // @[TLChannelCompactor.scala:90:18, :97:22]
assign protocol_bits_sink = _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
assign _protocol_bits_sink_WIRE = const_0[8:1]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13]
assign protocol_bits_source = _protocol_bits_source_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
assign _protocol_bits_source_WIRE = const_0[16:9]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13]
assign protocol_bits_size = _protocol_bits_size_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
assign _protocol_bits_size_WIRE = const_0[24:17]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13]
assign protocol_bits_param = _protocol_bits_param_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
assign _protocol_bits_param_WIRE = const_0[26:25]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13]
assign protocol_bits_opcode = _protocol_bits_opcode_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
assign _protocol_bits_opcode_WIRE = const_0[29:27]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13]
assign protocol_bits_corrupt = _protocol_bits_corrupt_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
assign _protocol_bits_corrupt_WIRE = io_beat_bits_payload_0[0]; // @[TLChannelCompactor.scala:97:22, :134:7]
assign _protocol_bits_data_WIRE = io_beat_bits_payload_0[64:1]; // @[TLChannelCompactor.scala:97:22, :98:13, :134:7]
assign protocol_bits_data = _protocol_bits_data_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
wire _T_12 = io_beat_ready_0 & io_beat_valid_0; // @[Decoupled.scala:51:35]
wire _T_11 = _T_12 & io_beat_bits_head_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TLChannelCompactor.scala:134:7]
if (reset) // @[TLChannelCompactor.scala:134:7]
is_const <= 1'h1; // @[TLChannelCompactor.scala:88:25]
else // @[TLChannelCompactor.scala:134:7]
is_const <= _T_12 & io_beat_bits_tail_0 | ~_T_11 & is_const; // @[Decoupled.scala:51:35]
if (_T_11) // @[TLChannelCompactor.scala:104:22]
const_reg <= io_beat_bits_payload_0[29:0]; // @[TLChannelCompactor.scala:89:22, :104:77, :134:7]
always @(posedge)
assign io_protocol_valid = io_protocol_valid_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_opcode = io_protocol_bits_opcode_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_param = io_protocol_bits_param_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_size = io_protocol_bits_size_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_source = io_protocol_bits_source_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_sink = io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_denied = io_protocol_bits_denied_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_data = io_protocol_bits_data_0; // @[TLChannelCompactor.scala:134:7]
assign io_protocol_bits_corrupt = io_protocol_bits_corrupt_0; // @[TLChannelCompactor.scala:134:7]
assign io_beat_ready = io_beat_ready_0; // @[TLChannelCompactor.scala:134:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a26d64s9k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a26d64s9k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [8:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [25:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [8:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [25:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [8:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [25:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [8:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [25:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [8:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [25:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [8:0] saved_source; // @[Repeater.scala:21:18]
reg [25:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_4 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<6>, vc_free : UInt<6>}}
wire _in_flight_WIRE : UInt<1>[6]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
regreset in_flight : UInt<1>[6], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_89 = and(_T_87, _T_88)
node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_126 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_133 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_140 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_173 = and(_T_171, _T_172)
node _T_174 = or(_T_12, _T_19)
node _T_175 = or(_T_174, _T_26)
node _T_176 = or(_T_175, _T_33)
node _T_177 = or(_T_176, _T_40)
node _T_178 = or(_T_177, _T_47)
node _T_179 = or(_T_178, _T_54)
node _T_180 = or(_T_179, _T_61)
node _T_181 = or(_T_180, _T_68)
node _T_182 = or(_T_181, _T_75)
node _T_183 = or(_T_182, _T_82)
node _T_184 = or(_T_183, _T_89)
node _T_185 = or(_T_184, _T_96)
node _T_186 = or(_T_185, _T_103)
node _T_187 = or(_T_186, _T_110)
node _T_188 = or(_T_187, _T_117)
node _T_189 = or(_T_188, _T_124)
node _T_190 = or(_T_189, _T_131)
node _T_191 = or(_T_190, _T_138)
node _T_192 = or(_T_191, _T_145)
node _T_193 = or(_T_192, _T_152)
node _T_194 = or(_T_193, _T_159)
node _T_195 = or(_T_194, _T_166)
node _T_196 = or(_T_195, _T_173)
node _T_197 = or(_T_5, _T_196)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_197, UInt<1>(0h1), "") : assert_1
node _T_201 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_202 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_203 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_204 = and(_T_202, _T_203)
node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_206 = and(_T_204, _T_205)
node _T_207 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_208 = and(_T_206, _T_207)
node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_210 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_211 = and(_T_209, _T_210)
node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_213 = and(_T_211, _T_212)
node _T_214 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_215 = and(_T_213, _T_214)
node _T_216 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_217 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_218 = and(_T_216, _T_217)
node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_220 = and(_T_218, _T_219)
node _T_221 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_224 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_227 = and(_T_225, _T_226)
node _T_228 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_229 = and(_T_227, _T_228)
node _T_230 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_231 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_232 = and(_T_230, _T_231)
node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_236 = and(_T_234, _T_235)
node _T_237 = or(_T_208, _T_215)
node _T_238 = or(_T_237, _T_222)
node _T_239 = or(_T_238, _T_229)
node _T_240 = or(_T_239, _T_236)
node _T_241 = or(_T_201, _T_240)
node _T_242 = asUInt(reset)
node _T_243 = eq(_T_242, UInt<1>(0h0))
when _T_243 :
node _T_244 = eq(_T_241, UInt<1>(0h0))
when _T_244 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_241, UInt<1>(0h1), "") : assert_2
node _T_245 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_246 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_247 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_254 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_261 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_268 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_275 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_282 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_287 = and(_T_285, _T_286)
node _T_288 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_289 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_294 = and(_T_292, _T_293)
node _T_295 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_296 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_301 = and(_T_299, _T_300)
node _T_302 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_303 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_310 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_313 = and(_T_311, _T_312)
node _T_314 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_315 = and(_T_313, _T_314)
node _T_316 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_317 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_322 = and(_T_320, _T_321)
node _T_323 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_324 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_329 = and(_T_327, _T_328)
node _T_330 = or(_T_252, _T_259)
node _T_331 = or(_T_330, _T_266)
node _T_332 = or(_T_331, _T_273)
node _T_333 = or(_T_332, _T_280)
node _T_334 = or(_T_333, _T_287)
node _T_335 = or(_T_334, _T_294)
node _T_336 = or(_T_335, _T_301)
node _T_337 = or(_T_336, _T_308)
node _T_338 = or(_T_337, _T_315)
node _T_339 = or(_T_338, _T_322)
node _T_340 = or(_T_339, _T_329)
node _T_341 = or(_T_245, _T_340)
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_341, UInt<1>(0h1), "") : assert_3
node _T_345 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_347 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_348 = and(_T_346, _T_347)
node _T_349 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_354 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_355 = and(_T_353, _T_354)
node _T_356 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_361 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_364 = and(_T_362, _T_363)
node _T_365 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_368 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_369 = and(_T_367, _T_368)
node _T_370 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_371 = and(_T_369, _T_370)
node _T_372 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_375 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_376 = and(_T_374, _T_375)
node _T_377 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_378 = and(_T_376, _T_377)
node _T_379 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_382 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_383 = and(_T_381, _T_382)
node _T_384 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_385 = and(_T_383, _T_384)
node _T_386 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_387 = and(_T_385, _T_386)
node _T_388 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_389 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_390 = and(_T_388, _T_389)
node _T_391 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_392 = and(_T_390, _T_391)
node _T_393 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_396 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_397 = and(_T_395, _T_396)
node _T_398 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_399 = and(_T_397, _T_398)
node _T_400 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_401 = and(_T_399, _T_400)
node _T_402 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_403 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_404 = and(_T_402, _T_403)
node _T_405 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_406 = and(_T_404, _T_405)
node _T_407 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_408 = and(_T_406, _T_407)
node _T_409 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_410 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_411 = and(_T_409, _T_410)
node _T_412 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_413 = and(_T_411, _T_412)
node _T_414 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_415 = and(_T_413, _T_414)
node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_417 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_418 = and(_T_416, _T_417)
node _T_419 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_420 = and(_T_418, _T_419)
node _T_421 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_424 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_425 = and(_T_423, _T_424)
node _T_426 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_427 = and(_T_425, _T_426)
node _T_428 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_431 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_432 = and(_T_430, _T_431)
node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_438 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_439 = and(_T_437, _T_438)
node _T_440 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_445 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_446 = and(_T_444, _T_445)
node _T_447 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_448 = and(_T_446, _T_447)
node _T_449 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_452 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_453 = and(_T_451, _T_452)
node _T_454 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_455 = and(_T_453, _T_454)
node _T_456 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_457 = and(_T_455, _T_456)
node _T_458 = or(_T_352, _T_359)
node _T_459 = or(_T_458, _T_366)
node _T_460 = or(_T_459, _T_373)
node _T_461 = or(_T_460, _T_380)
node _T_462 = or(_T_461, _T_387)
node _T_463 = or(_T_462, _T_394)
node _T_464 = or(_T_463, _T_401)
node _T_465 = or(_T_464, _T_408)
node _T_466 = or(_T_465, _T_415)
node _T_467 = or(_T_466, _T_422)
node _T_468 = or(_T_467, _T_429)
node _T_469 = or(_T_468, _T_436)
node _T_470 = or(_T_469, _T_443)
node _T_471 = or(_T_470, _T_450)
node _T_472 = or(_T_471, _T_457)
node _T_473 = or(_T_345, _T_472)
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_473, UInt<1>(0h1), "") : assert_4
node _T_477 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_478 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_479 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_484 = and(_T_482, _T_483)
node _T_485 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_486 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_489 = and(_T_487, _T_488)
node _T_490 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_491 = and(_T_489, _T_490)
node _T_492 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_493 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_496 = and(_T_494, _T_495)
node _T_497 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_498 = and(_T_496, _T_497)
node _T_499 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_500 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_503 = and(_T_501, _T_502)
node _T_504 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_505 = and(_T_503, _T_504)
node _T_506 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_507 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_510 = and(_T_508, _T_509)
node _T_511 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_512 = and(_T_510, _T_511)
node _T_513 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_514 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_517 = and(_T_515, _T_516)
node _T_518 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_521 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_522 = and(_T_520, _T_521)
node _T_523 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_524 = and(_T_522, _T_523)
node _T_525 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_526 = and(_T_524, _T_525)
node _T_527 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_528 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_529 = and(_T_527, _T_528)
node _T_530 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_531 = and(_T_529, _T_530)
node _T_532 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_535 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_538 = and(_T_536, _T_537)
node _T_539 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_540 = and(_T_538, _T_539)
node _T_541 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_542 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_545 = and(_T_543, _T_544)
node _T_546 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_547 = and(_T_545, _T_546)
node _T_548 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_549 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_550 = and(_T_548, _T_549)
node _T_551 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_552 = and(_T_550, _T_551)
node _T_553 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_554 = and(_T_552, _T_553)
node _T_555 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_556 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_557 = and(_T_555, _T_556)
node _T_558 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_559 = and(_T_557, _T_558)
node _T_560 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_561 = and(_T_559, _T_560)
node _T_562 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_563 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_564 = and(_T_562, _T_563)
node _T_565 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_566 = and(_T_564, _T_565)
node _T_567 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_568 = and(_T_566, _T_567)
node _T_569 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_570 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_571 = and(_T_569, _T_570)
node _T_572 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_573 = and(_T_571, _T_572)
node _T_574 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_575 = and(_T_573, _T_574)
node _T_576 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_577 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_578 = and(_T_576, _T_577)
node _T_579 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_580 = and(_T_578, _T_579)
node _T_581 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_582 = and(_T_580, _T_581)
node _T_583 = or(_T_484, _T_491)
node _T_584 = or(_T_583, _T_498)
node _T_585 = or(_T_584, _T_505)
node _T_586 = or(_T_585, _T_512)
node _T_587 = or(_T_586, _T_519)
node _T_588 = or(_T_587, _T_526)
node _T_589 = or(_T_588, _T_533)
node _T_590 = or(_T_589, _T_540)
node _T_591 = or(_T_590, _T_547)
node _T_592 = or(_T_591, _T_554)
node _T_593 = or(_T_592, _T_561)
node _T_594 = or(_T_593, _T_568)
node _T_595 = or(_T_594, _T_575)
node _T_596 = or(_T_595, _T_582)
node _T_597 = or(_T_477, _T_596)
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_597, UInt<1>(0h1), "") : assert_5
node _T_601 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_602 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_603 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_604 = and(_T_602, _T_603)
node _T_605 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_606 = and(_T_604, _T_605)
node _T_607 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
node _T_609 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_610 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
node _T_614 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_615 = and(_T_613, _T_614)
node _T_616 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_617 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_618 = and(_T_616, _T_617)
node _T_619 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_620 = and(_T_618, _T_619)
node _T_621 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
node _T_623 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_624 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_625 = and(_T_623, _T_624)
node _T_626 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_627 = and(_T_625, _T_626)
node _T_628 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_629 = and(_T_627, _T_628)
node _T_630 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_631 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_632 = and(_T_630, _T_631)
node _T_633 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_634 = and(_T_632, _T_633)
node _T_635 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_636 = and(_T_634, _T_635)
node _T_637 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_638 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_639 = and(_T_637, _T_638)
node _T_640 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_641 = and(_T_639, _T_640)
node _T_642 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_645 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_646 = and(_T_644, _T_645)
node _T_647 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
node _T_651 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_652 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_653 = and(_T_651, _T_652)
node _T_654 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_657 = and(_T_655, _T_656)
node _T_658 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_659 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_662 = and(_T_660, _T_661)
node _T_663 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_664 = and(_T_662, _T_663)
node _T_665 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_666 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_667 = and(_T_665, _T_666)
node _T_668 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_669 = and(_T_667, _T_668)
node _T_670 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_671 = and(_T_669, _T_670)
node _T_672 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_673 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_674 = and(_T_672, _T_673)
node _T_675 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_676 = and(_T_674, _T_675)
node _T_677 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_678 = and(_T_676, _T_677)
node _T_679 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_680 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_681 = and(_T_679, _T_680)
node _T_682 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_683 = and(_T_681, _T_682)
node _T_684 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_685 = and(_T_683, _T_684)
node _T_686 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_687 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_688 = and(_T_686, _T_687)
node _T_689 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_690 = and(_T_688, _T_689)
node _T_691 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_692 = and(_T_690, _T_691)
node _T_693 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_694 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_695 = and(_T_693, _T_694)
node _T_696 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_699 = and(_T_697, _T_698)
node _T_700 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_701 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_702 = and(_T_700, _T_701)
node _T_703 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_704 = and(_T_702, _T_703)
node _T_705 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_706 = and(_T_704, _T_705)
node _T_707 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_708 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_709 = and(_T_707, _T_708)
node _T_710 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_711 = and(_T_709, _T_710)
node _T_712 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_713 = and(_T_711, _T_712)
node _T_714 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_715 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_716 = and(_T_714, _T_715)
node _T_717 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_718 = and(_T_716, _T_717)
node _T_719 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_720 = and(_T_718, _T_719)
node _T_721 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_722 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_723 = and(_T_721, _T_722)
node _T_724 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_725 = and(_T_723, _T_724)
node _T_726 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_727 = and(_T_725, _T_726)
node _T_728 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_729 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_730 = and(_T_728, _T_729)
node _T_731 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_734 = and(_T_732, _T_733)
node _T_735 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_736 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_737 = and(_T_735, _T_736)
node _T_738 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_739 = and(_T_737, _T_738)
node _T_740 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_741 = and(_T_739, _T_740)
node _T_742 = or(_T_608, _T_615)
node _T_743 = or(_T_742, _T_622)
node _T_744 = or(_T_743, _T_629)
node _T_745 = or(_T_744, _T_636)
node _T_746 = or(_T_745, _T_643)
node _T_747 = or(_T_746, _T_650)
node _T_748 = or(_T_747, _T_657)
node _T_749 = or(_T_748, _T_664)
node _T_750 = or(_T_749, _T_671)
node _T_751 = or(_T_750, _T_678)
node _T_752 = or(_T_751, _T_685)
node _T_753 = or(_T_752, _T_692)
node _T_754 = or(_T_753, _T_699)
node _T_755 = or(_T_754, _T_706)
node _T_756 = or(_T_755, _T_713)
node _T_757 = or(_T_756, _T_720)
node _T_758 = or(_T_757, _T_727)
node _T_759 = or(_T_758, _T_734)
node _T_760 = or(_T_759, _T_741)
node _T_761 = or(_T_601, _T_760)
node _T_762 = asUInt(reset)
node _T_763 = eq(_T_762, UInt<1>(0h0))
when _T_763 :
node _T_764 = eq(_T_761, UInt<1>(0h0))
when _T_764 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_761, UInt<1>(0h1), "") : assert_6 | module NoCMonitor_4( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_230 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_230( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_227 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_483
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_227( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_483 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_16 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_16( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 6)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 6)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<6>(0h20))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<6>(0h21))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<6>(0h22))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<6>(0h23))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_64 = shr(io.in.a.bits.source, 6)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_77 = shr(io.in.a.bits.source, 6)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<6>(0h20))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<6>(0h21))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<6>(0h22))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<6>(0h23))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_164 = shr(io.in.a.bits.source, 6)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_170 = shr(io.in.a.bits.source, 6)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_177 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_178 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_179 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<14>(0h2000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<17>(0h10000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<18>(0h2f000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_224 = cvt(_T_223)
node _T_225 = and(_T_224, asSInt(UInt<27>(0h4000000)))
node _T_226 = asSInt(_T_225)
node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0)))
node _T_228 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = or(_T_197, _T_202)
node _T_234 = or(_T_233, _T_207)
node _T_235 = or(_T_234, _T_212)
node _T_236 = or(_T_235, _T_217)
node _T_237 = or(_T_236, _T_222)
node _T_238 = or(_T_237, _T_227)
node _T_239 = or(_T_238, _T_232)
node _T_240 = and(_T_192, _T_239)
node _T_241 = or(UInt<1>(0h0), _T_240)
node _T_242 = and(_T_191, _T_241)
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_242, UInt<1>(0h1), "") : assert_2
node _T_246 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_247 = shr(io.in.a.bits.source, 2)
node _T_248 = eq(_T_247, UInt<6>(0h20))
node _T_249 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_250 = and(_T_248, _T_249)
node _T_251 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_252 = and(_T_250, _T_251)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_253 = shr(io.in.a.bits.source, 2)
node _T_254 = eq(_T_253, UInt<6>(0h21))
node _T_255 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_256 = and(_T_254, _T_255)
node _T_257 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_258 = and(_T_256, _T_257)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_259 = shr(io.in.a.bits.source, 2)
node _T_260 = eq(_T_259, UInt<6>(0h22))
node _T_261 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_262 = and(_T_260, _T_261)
node _T_263 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_264 = and(_T_262, _T_263)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_265 = shr(io.in.a.bits.source, 2)
node _T_266 = eq(_T_265, UInt<6>(0h23))
node _T_267 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_268 = and(_T_266, _T_267)
node _T_269 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_270 = and(_T_268, _T_269)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_271 = shr(io.in.a.bits.source, 6)
node _T_272 = eq(_T_271, UInt<1>(0h1))
node _T_273 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_274 = and(_T_272, _T_273)
node _T_275 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_276 = and(_T_274, _T_275)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_277 = shr(io.in.a.bits.source, 6)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_280 = and(_T_278, _T_279)
node _T_281 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_282 = and(_T_280, _T_281)
node _T_283 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_284 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_285 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_286 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_246
connect _WIRE[1], _T_252
connect _WIRE[2], _T_258
connect _WIRE[3], _T_264
connect _WIRE[4], _T_270
connect _WIRE[5], _T_276
connect _WIRE[6], _T_282
connect _WIRE[7], _T_283
connect _WIRE[8], _T_284
connect _WIRE[9], _T_285
connect _WIRE[10], _T_286
node _T_287 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_288 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_289 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_293 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_294 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_295 = mux(_WIRE[7], _T_287, UInt<1>(0h0))
node _T_296 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_297 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_298 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_299 = or(_T_288, _T_289)
node _T_300 = or(_T_299, _T_290)
node _T_301 = or(_T_300, _T_291)
node _T_302 = or(_T_301, _T_292)
node _T_303 = or(_T_302, _T_293)
node _T_304 = or(_T_303, _T_294)
node _T_305 = or(_T_304, _T_295)
node _T_306 = or(_T_305, _T_296)
node _T_307 = or(_T_306, _T_297)
node _T_308 = or(_T_307, _T_298)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_308
node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_311 = and(_T_309, _T_310)
node _T_312 = or(UInt<1>(0h0), _T_311)
node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_339 = cvt(_T_338)
node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000)))
node _T_341 = asSInt(_T_340)
node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0)))
node _T_343 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_344 = cvt(_T_343)
node _T_345 = and(_T_344, asSInt(UInt<27>(0h4000000)))
node _T_346 = asSInt(_T_345)
node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0)))
node _T_348 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<13>(0h1000)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = or(_T_317, _T_322)
node _T_354 = or(_T_353, _T_327)
node _T_355 = or(_T_354, _T_332)
node _T_356 = or(_T_355, _T_337)
node _T_357 = or(_T_356, _T_342)
node _T_358 = or(_T_357, _T_347)
node _T_359 = or(_T_358, _T_352)
node _T_360 = and(_T_312, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = and(_WIRE_1, _T_361)
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_362, UInt<1>(0h1), "") : assert_3
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(source_ok, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_369 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_369, UInt<1>(0h1), "") : assert_5
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(is_aligned, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_376 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_376, UInt<1>(0h1), "") : assert_7
node _T_380 = not(io.in.a.bits.mask)
node _T_381 = eq(_T_380, UInt<1>(0h0))
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_381, UInt<1>(0h1), "") : assert_8
node _T_385 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_385, UInt<1>(0h1), "") : assert_9
node _T_389 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_389 :
node _T_390 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_391 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_392 = and(_T_390, _T_391)
node _T_393 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_394 = shr(io.in.a.bits.source, 2)
node _T_395 = eq(_T_394, UInt<6>(0h20))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_400 = shr(io.in.a.bits.source, 2)
node _T_401 = eq(_T_400, UInt<6>(0h21))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_406 = shr(io.in.a.bits.source, 2)
node _T_407 = eq(_T_406, UInt<6>(0h22))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_412 = shr(io.in.a.bits.source, 2)
node _T_413 = eq(_T_412, UInt<6>(0h23))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_417 = and(_T_415, _T_416)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0)
node _T_418 = shr(io.in.a.bits.source, 6)
node _T_419 = eq(_T_418, UInt<1>(0h1))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_22, UInt<6>(0h3f))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0)
node _T_424 = shr(io.in.a.bits.source, 6)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_23, UInt<6>(0h3f))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_431 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_432 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_433 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_434 = or(_T_393, _T_399)
node _T_435 = or(_T_434, _T_405)
node _T_436 = or(_T_435, _T_411)
node _T_437 = or(_T_436, _T_417)
node _T_438 = or(_T_437, _T_423)
node _T_439 = or(_T_438, _T_429)
node _T_440 = or(_T_439, _T_430)
node _T_441 = or(_T_440, _T_431)
node _T_442 = or(_T_441, _T_432)
node _T_443 = or(_T_442, _T_433)
node _T_444 = and(_T_392, _T_443)
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_447 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<14>(0h2000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_453 = cvt(_T_452)
node _T_454 = and(_T_453, asSInt(UInt<13>(0h1000)))
node _T_455 = asSInt(_T_454)
node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0)))
node _T_457 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<17>(0h10000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<18>(0h2f000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<17>(0h10000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<27>(0h4000000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<13>(0h1000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = or(_T_451, _T_456)
node _T_488 = or(_T_487, _T_461)
node _T_489 = or(_T_488, _T_466)
node _T_490 = or(_T_489, _T_471)
node _T_491 = or(_T_490, _T_476)
node _T_492 = or(_T_491, _T_481)
node _T_493 = or(_T_492, _T_486)
node _T_494 = and(_T_446, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = and(_T_445, _T_495)
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_496, UInt<1>(0h1), "") : assert_10
node _T_500 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<6>(0h20))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<6>(0h21))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<6>(0h22))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_519 = shr(io.in.a.bits.source, 2)
node _T_520 = eq(_T_519, UInt<6>(0h23))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0)
node _T_525 = shr(io.in.a.bits.source, 6)
node _T_526 = eq(_T_525, UInt<1>(0h1))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_28, UInt<6>(0h3f))
node _T_530 = and(_T_528, _T_529)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0)
node _T_531 = shr(io.in.a.bits.source, 6)
node _T_532 = eq(_T_531, UInt<1>(0h0))
node _T_533 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_534 = and(_T_532, _T_533)
node _T_535 = leq(uncommonBits_29, UInt<6>(0h3f))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_538 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_539 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_540 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_500
connect _WIRE_2[1], _T_506
connect _WIRE_2[2], _T_512
connect _WIRE_2[3], _T_518
connect _WIRE_2[4], _T_524
connect _WIRE_2[5], _T_530
connect _WIRE_2[6], _T_536
connect _WIRE_2[7], _T_537
connect _WIRE_2[8], _T_538
connect _WIRE_2[9], _T_539
connect _WIRE_2[10], _T_540
node _T_541 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_542 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_543 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_544 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_546 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_547 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_548 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_549 = mux(_WIRE_2[7], _T_541, UInt<1>(0h0))
node _T_550 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_552 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_553 = or(_T_542, _T_543)
node _T_554 = or(_T_553, _T_544)
node _T_555 = or(_T_554, _T_545)
node _T_556 = or(_T_555, _T_546)
node _T_557 = or(_T_556, _T_547)
node _T_558 = or(_T_557, _T_548)
node _T_559 = or(_T_558, _T_549)
node _T_560 = or(_T_559, _T_550)
node _T_561 = or(_T_560, _T_551)
node _T_562 = or(_T_561, _T_552)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_562
node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_565 = and(_T_563, _T_564)
node _T_566 = or(UInt<1>(0h0), _T_565)
node _T_567 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<14>(0h2000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_578 = cvt(_T_577)
node _T_579 = and(_T_578, asSInt(UInt<17>(0h10000)))
node _T_580 = asSInt(_T_579)
node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0)))
node _T_582 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<18>(0h2f000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_588 = cvt(_T_587)
node _T_589 = and(_T_588, asSInt(UInt<17>(0h10000)))
node _T_590 = asSInt(_T_589)
node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0)))
node _T_592 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_593 = cvt(_T_592)
node _T_594 = and(_T_593, asSInt(UInt<13>(0h1000)))
node _T_595 = asSInt(_T_594)
node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0)))
node _T_597 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_598 = cvt(_T_597)
node _T_599 = and(_T_598, asSInt(UInt<27>(0h4000000)))
node _T_600 = asSInt(_T_599)
node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0)))
node _T_602 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_603 = cvt(_T_602)
node _T_604 = and(_T_603, asSInt(UInt<13>(0h1000)))
node _T_605 = asSInt(_T_604)
node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0)))
node _T_607 = or(_T_571, _T_576)
node _T_608 = or(_T_607, _T_581)
node _T_609 = or(_T_608, _T_586)
node _T_610 = or(_T_609, _T_591)
node _T_611 = or(_T_610, _T_596)
node _T_612 = or(_T_611, _T_601)
node _T_613 = or(_T_612, _T_606)
node _T_614 = and(_T_566, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = and(_WIRE_3, _T_615)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_616, UInt<1>(0h1), "") : assert_11
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(source_ok, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_623 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_623, UInt<1>(0h1), "") : assert_13
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(is_aligned, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_630 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_630, UInt<1>(0h1), "") : assert_15
node _T_634 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_634, UInt<1>(0h1), "") : assert_16
node _T_638 = not(io.in.a.bits.mask)
node _T_639 = eq(_T_638, UInt<1>(0h0))
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_639, UInt<1>(0h1), "") : assert_17
node _T_643 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(_T_643, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_643, UInt<1>(0h1), "") : assert_18
node _T_647 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_647 :
node _T_648 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_649 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_650 = and(_T_648, _T_649)
node _T_651 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_652 = shr(io.in.a.bits.source, 2)
node _T_653 = eq(_T_652, UInt<6>(0h20))
node _T_654 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_655 = and(_T_653, _T_654)
node _T_656 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_657 = and(_T_655, _T_656)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_658 = shr(io.in.a.bits.source, 2)
node _T_659 = eq(_T_658, UInt<6>(0h21))
node _T_660 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_661 = and(_T_659, _T_660)
node _T_662 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_663 = and(_T_661, _T_662)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<6>(0h22))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_670 = shr(io.in.a.bits.source, 2)
node _T_671 = eq(_T_670, UInt<6>(0h23))
node _T_672 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_673 = and(_T_671, _T_672)
node _T_674 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_675 = and(_T_673, _T_674)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0)
node _T_676 = shr(io.in.a.bits.source, 6)
node _T_677 = eq(_T_676, UInt<1>(0h1))
node _T_678 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_679 = and(_T_677, _T_678)
node _T_680 = leq(uncommonBits_34, UInt<6>(0h3f))
node _T_681 = and(_T_679, _T_680)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0)
node _T_682 = shr(io.in.a.bits.source, 6)
node _T_683 = eq(_T_682, UInt<1>(0h0))
node _T_684 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_685 = and(_T_683, _T_684)
node _T_686 = leq(uncommonBits_35, UInt<6>(0h3f))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_689 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_690 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_691 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_692 = or(_T_651, _T_657)
node _T_693 = or(_T_692, _T_663)
node _T_694 = or(_T_693, _T_669)
node _T_695 = or(_T_694, _T_675)
node _T_696 = or(_T_695, _T_681)
node _T_697 = or(_T_696, _T_687)
node _T_698 = or(_T_697, _T_688)
node _T_699 = or(_T_698, _T_689)
node _T_700 = or(_T_699, _T_690)
node _T_701 = or(_T_700, _T_691)
node _T_702 = and(_T_650, _T_701)
node _T_703 = or(UInt<1>(0h0), _T_702)
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_703, UInt<1>(0h1), "") : assert_19
node _T_707 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_708 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_709 = and(_T_707, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = and(_T_710, _T_715)
node _T_717 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_718 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_719 = and(_T_717, _T_718)
node _T_720 = or(UInt<1>(0h0), _T_719)
node _T_721 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<14>(0h2000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<18>(0h2f000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<27>(0h4000000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = or(_T_725, _T_730)
node _T_757 = or(_T_756, _T_735)
node _T_758 = or(_T_757, _T_740)
node _T_759 = or(_T_758, _T_745)
node _T_760 = or(_T_759, _T_750)
node _T_761 = or(_T_760, _T_755)
node _T_762 = and(_T_720, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_716)
node _T_764 = or(_T_763, _T_762)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_764, UInt<1>(0h1), "") : assert_20
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(source_ok, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(is_aligned, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_774 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_774, UInt<1>(0h1), "") : assert_23
node _T_778 = eq(io.in.a.bits.mask, mask)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_778, UInt<1>(0h1), "") : assert_24
node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_782, UInt<1>(0h1), "") : assert_25
node _T_786 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_786 :
node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_789 = and(_T_787, _T_788)
node _T_790 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<6>(0h20))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_797 = shr(io.in.a.bits.source, 2)
node _T_798 = eq(_T_797, UInt<6>(0h21))
node _T_799 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_800 = and(_T_798, _T_799)
node _T_801 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_802 = and(_T_800, _T_801)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_803 = shr(io.in.a.bits.source, 2)
node _T_804 = eq(_T_803, UInt<6>(0h22))
node _T_805 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_806 = and(_T_804, _T_805)
node _T_807 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_808 = and(_T_806, _T_807)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<6>(0h23))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0)
node _T_815 = shr(io.in.a.bits.source, 6)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_40, UInt<6>(0h3f))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0)
node _T_821 = shr(io.in.a.bits.source, 6)
node _T_822 = eq(_T_821, UInt<1>(0h0))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_41, UInt<6>(0h3f))
node _T_826 = and(_T_824, _T_825)
node _T_827 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_828 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_829 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_830 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_831 = or(_T_790, _T_796)
node _T_832 = or(_T_831, _T_802)
node _T_833 = or(_T_832, _T_808)
node _T_834 = or(_T_833, _T_814)
node _T_835 = or(_T_834, _T_820)
node _T_836 = or(_T_835, _T_826)
node _T_837 = or(_T_836, _T_827)
node _T_838 = or(_T_837, _T_828)
node _T_839 = or(_T_838, _T_829)
node _T_840 = or(_T_839, _T_830)
node _T_841 = and(_T_789, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_854 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<14>(0h2000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<18>(0h2f000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_868 = cvt(_T_867)
node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000)))
node _T_870 = asSInt(_T_869)
node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0)))
node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_873 = cvt(_T_872)
node _T_874 = and(_T_873, asSInt(UInt<13>(0h1000)))
node _T_875 = asSInt(_T_874)
node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0)))
node _T_877 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_878 = cvt(_T_877)
node _T_879 = and(_T_878, asSInt(UInt<27>(0h4000000)))
node _T_880 = asSInt(_T_879)
node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0)))
node _T_882 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_883 = cvt(_T_882)
node _T_884 = and(_T_883, asSInt(UInt<13>(0h1000)))
node _T_885 = asSInt(_T_884)
node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0)))
node _T_887 = or(_T_861, _T_866)
node _T_888 = or(_T_887, _T_871)
node _T_889 = or(_T_888, _T_876)
node _T_890 = or(_T_889, _T_881)
node _T_891 = or(_T_890, _T_886)
node _T_892 = and(_T_856, _T_891)
node _T_893 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_894 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = and(_T_893, _T_898)
node _T_900 = or(UInt<1>(0h0), _T_852)
node _T_901 = or(_T_900, _T_892)
node _T_902 = or(_T_901, _T_899)
node _T_903 = and(_T_842, _T_902)
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_903, UInt<1>(0h1), "") : assert_26
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(source_ok, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(is_aligned, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_913 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_913, UInt<1>(0h1), "") : assert_29
node _T_917 = eq(io.in.a.bits.mask, mask)
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_917, UInt<1>(0h1), "") : assert_30
node _T_921 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_921 :
node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_924 = and(_T_922, _T_923)
node _T_925 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_926 = shr(io.in.a.bits.source, 2)
node _T_927 = eq(_T_926, UInt<6>(0h20))
node _T_928 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_929 = and(_T_927, _T_928)
node _T_930 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_931 = and(_T_929, _T_930)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_932 = shr(io.in.a.bits.source, 2)
node _T_933 = eq(_T_932, UInt<6>(0h21))
node _T_934 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_935 = and(_T_933, _T_934)
node _T_936 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_937 = and(_T_935, _T_936)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_938 = shr(io.in.a.bits.source, 2)
node _T_939 = eq(_T_938, UInt<6>(0h22))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_943 = and(_T_941, _T_942)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_944 = shr(io.in.a.bits.source, 2)
node _T_945 = eq(_T_944, UInt<6>(0h23))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0)
node _T_950 = shr(io.in.a.bits.source, 6)
node _T_951 = eq(_T_950, UInt<1>(0h1))
node _T_952 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_953 = and(_T_951, _T_952)
node _T_954 = leq(uncommonBits_46, UInt<6>(0h3f))
node _T_955 = and(_T_953, _T_954)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0)
node _T_956 = shr(io.in.a.bits.source, 6)
node _T_957 = eq(_T_956, UInt<1>(0h0))
node _T_958 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_959 = and(_T_957, _T_958)
node _T_960 = leq(uncommonBits_47, UInt<6>(0h3f))
node _T_961 = and(_T_959, _T_960)
node _T_962 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_963 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_964 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_965 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_966 = or(_T_925, _T_931)
node _T_967 = or(_T_966, _T_937)
node _T_968 = or(_T_967, _T_943)
node _T_969 = or(_T_968, _T_949)
node _T_970 = or(_T_969, _T_955)
node _T_971 = or(_T_970, _T_961)
node _T_972 = or(_T_971, _T_962)
node _T_973 = or(_T_972, _T_963)
node _T_974 = or(_T_973, _T_964)
node _T_975 = or(_T_974, _T_965)
node _T_976 = and(_T_924, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_979 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_980 = and(_T_978, _T_979)
node _T_981 = or(UInt<1>(0h0), _T_980)
node _T_982 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = and(_T_981, _T_986)
node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_990 = and(_T_988, _T_989)
node _T_991 = or(UInt<1>(0h0), _T_990)
node _T_992 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<14>(0h2000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1013 = cvt(_T_1012)
node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000)))
node _T_1015 = asSInt(_T_1014)
node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0)))
node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1018 = cvt(_T_1017)
node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000)))
node _T_1020 = asSInt(_T_1019)
node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0)))
node _T_1022 = or(_T_996, _T_1001)
node _T_1023 = or(_T_1022, _T_1006)
node _T_1024 = or(_T_1023, _T_1011)
node _T_1025 = or(_T_1024, _T_1016)
node _T_1026 = or(_T_1025, _T_1021)
node _T_1027 = and(_T_991, _T_1026)
node _T_1028 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1029 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1030 = cvt(_T_1029)
node _T_1031 = and(_T_1030, asSInt(UInt<17>(0h10000)))
node _T_1032 = asSInt(_T_1031)
node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0)))
node _T_1034 = and(_T_1028, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_987)
node _T_1036 = or(_T_1035, _T_1027)
node _T_1037 = or(_T_1036, _T_1034)
node _T_1038 = and(_T_977, _T_1037)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_31
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(source_ok, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(is_aligned, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1048 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_34
node _T_1052 = not(mask)
node _T_1053 = and(io.in.a.bits.mask, _T_1052)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_35
node _T_1058 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1058 :
node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1063 = shr(io.in.a.bits.source, 2)
node _T_1064 = eq(_T_1063, UInt<6>(0h20))
node _T_1065 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1068 = and(_T_1066, _T_1067)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_1069 = shr(io.in.a.bits.source, 2)
node _T_1070 = eq(_T_1069, UInt<6>(0h21))
node _T_1071 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1072 = and(_T_1070, _T_1071)
node _T_1073 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_1074 = and(_T_1072, _T_1073)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1075 = shr(io.in.a.bits.source, 2)
node _T_1076 = eq(_T_1075, UInt<6>(0h22))
node _T_1077 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1080 = and(_T_1078, _T_1079)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1081 = shr(io.in.a.bits.source, 2)
node _T_1082 = eq(_T_1081, UInt<6>(0h23))
node _T_1083 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1086 = and(_T_1084, _T_1085)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0)
node _T_1087 = shr(io.in.a.bits.source, 6)
node _T_1088 = eq(_T_1087, UInt<1>(0h1))
node _T_1089 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1090 = and(_T_1088, _T_1089)
node _T_1091 = leq(uncommonBits_52, UInt<6>(0h3f))
node _T_1092 = and(_T_1090, _T_1091)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0)
node _T_1093 = shr(io.in.a.bits.source, 6)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
node _T_1095 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1096 = and(_T_1094, _T_1095)
node _T_1097 = leq(uncommonBits_53, UInt<6>(0h3f))
node _T_1098 = and(_T_1096, _T_1097)
node _T_1099 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1100 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1101 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1102 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1103 = or(_T_1062, _T_1068)
node _T_1104 = or(_T_1103, _T_1074)
node _T_1105 = or(_T_1104, _T_1080)
node _T_1106 = or(_T_1105, _T_1086)
node _T_1107 = or(_T_1106, _T_1092)
node _T_1108 = or(_T_1107, _T_1098)
node _T_1109 = or(_T_1108, _T_1099)
node _T_1110 = or(_T_1109, _T_1100)
node _T_1111 = or(_T_1110, _T_1101)
node _T_1112 = or(_T_1111, _T_1102)
node _T_1113 = and(_T_1061, _T_1112)
node _T_1114 = or(UInt<1>(0h0), _T_1113)
node _T_1115 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1116 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1117 = and(_T_1115, _T_1116)
node _T_1118 = or(UInt<1>(0h0), _T_1117)
node _T_1119 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<15>(0h5000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<13>(0h1000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = or(_T_1123, _T_1128)
node _T_1130 = and(_T_1118, _T_1129)
node _T_1131 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1132 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1133 = cvt(_T_1132)
node _T_1134 = and(_T_1133, asSInt(UInt<13>(0h1000)))
node _T_1135 = asSInt(_T_1134)
node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0)))
node _T_1137 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1138 = cvt(_T_1137)
node _T_1139 = and(_T_1138, asSInt(UInt<17>(0h10000)))
node _T_1140 = asSInt(_T_1139)
node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0)))
node _T_1142 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1143 = cvt(_T_1142)
node _T_1144 = and(_T_1143, asSInt(UInt<18>(0h2f000)))
node _T_1145 = asSInt(_T_1144)
node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1148 = cvt(_T_1147)
node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000)))
node _T_1150 = asSInt(_T_1149)
node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0)))
node _T_1152 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<13>(0h1000)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1158 = cvt(_T_1157)
node _T_1159 = and(_T_1158, asSInt(UInt<27>(0h4000000)))
node _T_1160 = asSInt(_T_1159)
node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0)))
node _T_1162 = or(_T_1136, _T_1141)
node _T_1163 = or(_T_1162, _T_1146)
node _T_1164 = or(_T_1163, _T_1151)
node _T_1165 = or(_T_1164, _T_1156)
node _T_1166 = or(_T_1165, _T_1161)
node _T_1167 = and(_T_1131, _T_1166)
node _T_1168 = or(UInt<1>(0h0), _T_1130)
node _T_1169 = or(_T_1168, _T_1167)
node _T_1170 = and(_T_1114, _T_1169)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_36
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(source_ok, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(is_aligned, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1180 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_39
node _T_1184 = eq(io.in.a.bits.mask, mask)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_40
node _T_1188 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1188 :
node _T_1189 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1190 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1191 = and(_T_1189, _T_1190)
node _T_1192 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_1193 = shr(io.in.a.bits.source, 2)
node _T_1194 = eq(_T_1193, UInt<6>(0h20))
node _T_1195 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1196 = and(_T_1194, _T_1195)
node _T_1197 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_1198 = and(_T_1196, _T_1197)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1199 = shr(io.in.a.bits.source, 2)
node _T_1200 = eq(_T_1199, UInt<6>(0h21))
node _T_1201 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1202 = and(_T_1200, _T_1201)
node _T_1203 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1204 = and(_T_1202, _T_1203)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1205 = shr(io.in.a.bits.source, 2)
node _T_1206 = eq(_T_1205, UInt<6>(0h22))
node _T_1207 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1208 = and(_T_1206, _T_1207)
node _T_1209 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1210 = and(_T_1208, _T_1209)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1211 = shr(io.in.a.bits.source, 2)
node _T_1212 = eq(_T_1211, UInt<6>(0h23))
node _T_1213 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1214 = and(_T_1212, _T_1213)
node _T_1215 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1216 = and(_T_1214, _T_1215)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0)
node _T_1217 = shr(io.in.a.bits.source, 6)
node _T_1218 = eq(_T_1217, UInt<1>(0h1))
node _T_1219 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1220 = and(_T_1218, _T_1219)
node _T_1221 = leq(uncommonBits_58, UInt<6>(0h3f))
node _T_1222 = and(_T_1220, _T_1221)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0)
node _T_1223 = shr(io.in.a.bits.source, 6)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
node _T_1225 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1226 = and(_T_1224, _T_1225)
node _T_1227 = leq(uncommonBits_59, UInt<6>(0h3f))
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1230 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1231 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1232 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1233 = or(_T_1192, _T_1198)
node _T_1234 = or(_T_1233, _T_1204)
node _T_1235 = or(_T_1234, _T_1210)
node _T_1236 = or(_T_1235, _T_1216)
node _T_1237 = or(_T_1236, _T_1222)
node _T_1238 = or(_T_1237, _T_1228)
node _T_1239 = or(_T_1238, _T_1229)
node _T_1240 = or(_T_1239, _T_1230)
node _T_1241 = or(_T_1240, _T_1231)
node _T_1242 = or(_T_1241, _T_1232)
node _T_1243 = and(_T_1191, _T_1242)
node _T_1244 = or(UInt<1>(0h0), _T_1243)
node _T_1245 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1246 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1247 = and(_T_1245, _T_1246)
node _T_1248 = or(UInt<1>(0h0), _T_1247)
node _T_1249 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1250 = cvt(_T_1249)
node _T_1251 = and(_T_1250, asSInt(UInt<15>(0h5000)))
node _T_1252 = asSInt(_T_1251)
node _T_1253 = eq(_T_1252, asSInt(UInt<1>(0h0)))
node _T_1254 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<13>(0h1000)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = or(_T_1253, _T_1258)
node _T_1260 = and(_T_1248, _T_1259)
node _T_1261 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1262 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1263 = cvt(_T_1262)
node _T_1264 = and(_T_1263, asSInt(UInt<13>(0h1000)))
node _T_1265 = asSInt(_T_1264)
node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0)))
node _T_1267 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1268 = cvt(_T_1267)
node _T_1269 = and(_T_1268, asSInt(UInt<17>(0h10000)))
node _T_1270 = asSInt(_T_1269)
node _T_1271 = eq(_T_1270, asSInt(UInt<1>(0h0)))
node _T_1272 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1273 = cvt(_T_1272)
node _T_1274 = and(_T_1273, asSInt(UInt<18>(0h2f000)))
node _T_1275 = asSInt(_T_1274)
node _T_1276 = eq(_T_1275, asSInt(UInt<1>(0h0)))
node _T_1277 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1278 = cvt(_T_1277)
node _T_1279 = and(_T_1278, asSInt(UInt<17>(0h10000)))
node _T_1280 = asSInt(_T_1279)
node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0)))
node _T_1282 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1283 = cvt(_T_1282)
node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000)))
node _T_1285 = asSInt(_T_1284)
node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0)))
node _T_1287 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1288 = cvt(_T_1287)
node _T_1289 = and(_T_1288, asSInt(UInt<27>(0h4000000)))
node _T_1290 = asSInt(_T_1289)
node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0)))
node _T_1292 = or(_T_1266, _T_1271)
node _T_1293 = or(_T_1292, _T_1276)
node _T_1294 = or(_T_1293, _T_1281)
node _T_1295 = or(_T_1294, _T_1286)
node _T_1296 = or(_T_1295, _T_1291)
node _T_1297 = and(_T_1261, _T_1296)
node _T_1298 = or(UInt<1>(0h0), _T_1260)
node _T_1299 = or(_T_1298, _T_1297)
node _T_1300 = and(_T_1244, _T_1299)
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(_T_1300, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1300, UInt<1>(0h1), "") : assert_41
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(source_ok, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(is_aligned, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1310 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_44
node _T_1314 = eq(io.in.a.bits.mask, mask)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_45
node _T_1318 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1318 :
node _T_1319 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1320 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1321 = and(_T_1319, _T_1320)
node _T_1322 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1323 = shr(io.in.a.bits.source, 2)
node _T_1324 = eq(_T_1323, UInt<6>(0h20))
node _T_1325 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1326 = and(_T_1324, _T_1325)
node _T_1327 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1328 = and(_T_1326, _T_1327)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1329 = shr(io.in.a.bits.source, 2)
node _T_1330 = eq(_T_1329, UInt<6>(0h21))
node _T_1331 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1332 = and(_T_1330, _T_1331)
node _T_1333 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1334 = and(_T_1332, _T_1333)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1335 = shr(io.in.a.bits.source, 2)
node _T_1336 = eq(_T_1335, UInt<6>(0h22))
node _T_1337 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1338 = and(_T_1336, _T_1337)
node _T_1339 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1340 = and(_T_1338, _T_1339)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1341 = shr(io.in.a.bits.source, 2)
node _T_1342 = eq(_T_1341, UInt<6>(0h23))
node _T_1343 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1344 = and(_T_1342, _T_1343)
node _T_1345 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1346 = and(_T_1344, _T_1345)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0)
node _T_1347 = shr(io.in.a.bits.source, 6)
node _T_1348 = eq(_T_1347, UInt<1>(0h1))
node _T_1349 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1350 = and(_T_1348, _T_1349)
node _T_1351 = leq(uncommonBits_64, UInt<6>(0h3f))
node _T_1352 = and(_T_1350, _T_1351)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0)
node _T_1353 = shr(io.in.a.bits.source, 6)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
node _T_1355 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1356 = and(_T_1354, _T_1355)
node _T_1357 = leq(uncommonBits_65, UInt<6>(0h3f))
node _T_1358 = and(_T_1356, _T_1357)
node _T_1359 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1360 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1361 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1362 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1363 = or(_T_1322, _T_1328)
node _T_1364 = or(_T_1363, _T_1334)
node _T_1365 = or(_T_1364, _T_1340)
node _T_1366 = or(_T_1365, _T_1346)
node _T_1367 = or(_T_1366, _T_1352)
node _T_1368 = or(_T_1367, _T_1358)
node _T_1369 = or(_T_1368, _T_1359)
node _T_1370 = or(_T_1369, _T_1360)
node _T_1371 = or(_T_1370, _T_1361)
node _T_1372 = or(_T_1371, _T_1362)
node _T_1373 = and(_T_1321, _T_1372)
node _T_1374 = or(UInt<1>(0h0), _T_1373)
node _T_1375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1376 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1377 = and(_T_1375, _T_1376)
node _T_1378 = or(UInt<1>(0h0), _T_1377)
node _T_1379 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1380 = cvt(_T_1379)
node _T_1381 = and(_T_1380, asSInt(UInt<13>(0h1000)))
node _T_1382 = asSInt(_T_1381)
node _T_1383 = eq(_T_1382, asSInt(UInt<1>(0h0)))
node _T_1384 = and(_T_1378, _T_1383)
node _T_1385 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1386 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<14>(0h2000)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1392 = cvt(_T_1391)
node _T_1393 = and(_T_1392, asSInt(UInt<17>(0h10000)))
node _T_1394 = asSInt(_T_1393)
node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0)))
node _T_1396 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1397 = cvt(_T_1396)
node _T_1398 = and(_T_1397, asSInt(UInt<18>(0h2f000)))
node _T_1399 = asSInt(_T_1398)
node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0)))
node _T_1401 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1402 = cvt(_T_1401)
node _T_1403 = and(_T_1402, asSInt(UInt<17>(0h10000)))
node _T_1404 = asSInt(_T_1403)
node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0)))
node _T_1406 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1407 = cvt(_T_1406)
node _T_1408 = and(_T_1407, asSInt(UInt<13>(0h1000)))
node _T_1409 = asSInt(_T_1408)
node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0)))
node _T_1411 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<27>(0h4000000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = or(_T_1390, _T_1395)
node _T_1422 = or(_T_1421, _T_1400)
node _T_1423 = or(_T_1422, _T_1405)
node _T_1424 = or(_T_1423, _T_1410)
node _T_1425 = or(_T_1424, _T_1415)
node _T_1426 = or(_T_1425, _T_1420)
node _T_1427 = and(_T_1385, _T_1426)
node _T_1428 = or(UInt<1>(0h0), _T_1384)
node _T_1429 = or(_T_1428, _T_1427)
node _T_1430 = and(_T_1374, _T_1429)
node _T_1431 = asUInt(reset)
node _T_1432 = eq(_T_1431, UInt<1>(0h0))
when _T_1432 :
node _T_1433 = eq(_T_1430, UInt<1>(0h0))
when _T_1433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1430, UInt<1>(0h1), "") : assert_46
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(source_ok, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1437 = asUInt(reset)
node _T_1438 = eq(_T_1437, UInt<1>(0h0))
when _T_1438 :
node _T_1439 = eq(is_aligned, UInt<1>(0h0))
when _T_1439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1440 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1441 = asUInt(reset)
node _T_1442 = eq(_T_1441, UInt<1>(0h0))
when _T_1442 :
node _T_1443 = eq(_T_1440, UInt<1>(0h0))
when _T_1443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1440, UInt<1>(0h1), "") : assert_49
node _T_1444 = eq(io.in.a.bits.mask, mask)
node _T_1445 = asUInt(reset)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
when _T_1446 :
node _T_1447 = eq(_T_1444, UInt<1>(0h0))
when _T_1447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1444, UInt<1>(0h1), "") : assert_50
node _T_1448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1449 = asUInt(reset)
node _T_1450 = eq(_T_1449, UInt<1>(0h0))
when _T_1450 :
node _T_1451 = eq(_T_1448, UInt<1>(0h0))
when _T_1451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1448, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1452 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1453 = asUInt(reset)
node _T_1454 = eq(_T_1453, UInt<1>(0h0))
when _T_1454 :
node _T_1455 = eq(_T_1452, UInt<1>(0h0))
when _T_1455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1452, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<6>(0h20))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<6>(0h21))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<6>(0h22))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<6>(0h23))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 6)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 6)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha0))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<8>(0ha1))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<8>(0ha2))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1456 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1456 :
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(source_ok_1, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1460 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_54
node _T_1464 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_55
node _T_1468 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_56
node _T_1472 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_57
node _T_1476 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1476 :
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(source_ok_1, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(sink_ok, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1483 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_60
node _T_1487 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_61
node _T_1491 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_62
node _T_1495 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_63
node _T_1499 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1500 = or(UInt<1>(0h1), _T_1499)
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(_T_1500, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1500, UInt<1>(0h1), "") : assert_64
node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1504 :
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(source_ok_1, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(sink_ok, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1511 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_67
node _T_1515 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_68
node _T_1519 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_69
node _T_1523 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1524 = or(_T_1523, io.in.d.bits.corrupt)
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(_T_1524, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1524, UInt<1>(0h1), "") : assert_70
node _T_1528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1529 = or(UInt<1>(0h1), _T_1528)
node _T_1530 = asUInt(reset)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
when _T_1531 :
node _T_1532 = eq(_T_1529, UInt<1>(0h0))
when _T_1532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1529, UInt<1>(0h1), "") : assert_71
node _T_1533 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = asUInt(reset)
node _T_1535 = eq(_T_1534, UInt<1>(0h0))
when _T_1535 :
node _T_1536 = eq(source_ok_1, UInt<1>(0h0))
when _T_1536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1537 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1538 = asUInt(reset)
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
when _T_1539 :
node _T_1540 = eq(_T_1537, UInt<1>(0h0))
when _T_1540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1537, UInt<1>(0h1), "") : assert_73
node _T_1541 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1542 = asUInt(reset)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
when _T_1543 :
node _T_1544 = eq(_T_1541, UInt<1>(0h0))
when _T_1544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1541, UInt<1>(0h1), "") : assert_74
node _T_1545 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1546 = or(UInt<1>(0h1), _T_1545)
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(_T_1546, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1546, UInt<1>(0h1), "") : assert_75
node _T_1550 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1550 :
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(source_ok_1, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1554 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_77
node _T_1558 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1559 = or(_T_1558, io.in.d.bits.corrupt)
node _T_1560 = asUInt(reset)
node _T_1561 = eq(_T_1560, UInt<1>(0h0))
when _T_1561 :
node _T_1562 = eq(_T_1559, UInt<1>(0h0))
when _T_1562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1559, UInt<1>(0h1), "") : assert_78
node _T_1563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1564 = or(UInt<1>(0h1), _T_1563)
node _T_1565 = asUInt(reset)
node _T_1566 = eq(_T_1565, UInt<1>(0h0))
when _T_1566 :
node _T_1567 = eq(_T_1564, UInt<1>(0h0))
when _T_1567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1564, UInt<1>(0h1), "") : assert_79
node _T_1568 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1568 :
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(source_ok_1, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1572 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1573 = asUInt(reset)
node _T_1574 = eq(_T_1573, UInt<1>(0h0))
when _T_1574 :
node _T_1575 = eq(_T_1572, UInt<1>(0h0))
when _T_1575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1572, UInt<1>(0h1), "") : assert_81
node _T_1576 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_82
node _T_1580 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1581 = or(UInt<1>(0h1), _T_1580)
node _T_1582 = asUInt(reset)
node _T_1583 = eq(_T_1582, UInt<1>(0h0))
when _T_1583 :
node _T_1584 = eq(_T_1581, UInt<1>(0h0))
when _T_1584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1581, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<9>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1585 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(_T_1585, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1585, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1589 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(_T_1589, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1589, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1593 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1597 = eq(a_first, UInt<1>(0h0))
node _T_1598 = and(io.in.a.valid, _T_1597)
when _T_1598 :
node _T_1599 = eq(io.in.a.bits.opcode, opcode)
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_87
node _T_1603 = eq(io.in.a.bits.param, param)
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_88
node _T_1607 = eq(io.in.a.bits.size, size)
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(_T_1607, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1607, UInt<1>(0h1), "") : assert_89
node _T_1611 = eq(io.in.a.bits.source, source)
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_90
node _T_1615 = eq(io.in.a.bits.address, address)
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_91
node _T_1619 = and(io.in.a.ready, io.in.a.valid)
node _T_1620 = and(_T_1619, a_first)
when _T_1620 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1621 = eq(d_first, UInt<1>(0h0))
node _T_1622 = and(io.in.d.valid, _T_1621)
when _T_1622 :
node _T_1623 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1624 = asUInt(reset)
node _T_1625 = eq(_T_1624, UInt<1>(0h0))
when _T_1625 :
node _T_1626 = eq(_T_1623, UInt<1>(0h0))
when _T_1626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1623, UInt<1>(0h1), "") : assert_92
node _T_1627 = eq(io.in.d.bits.param, param_1)
node _T_1628 = asUInt(reset)
node _T_1629 = eq(_T_1628, UInt<1>(0h0))
when _T_1629 :
node _T_1630 = eq(_T_1627, UInt<1>(0h0))
when _T_1630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1627, UInt<1>(0h1), "") : assert_93
node _T_1631 = eq(io.in.d.bits.size, size_1)
node _T_1632 = asUInt(reset)
node _T_1633 = eq(_T_1632, UInt<1>(0h0))
when _T_1633 :
node _T_1634 = eq(_T_1631, UInt<1>(0h0))
when _T_1634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1631, UInt<1>(0h1), "") : assert_94
node _T_1635 = eq(io.in.d.bits.source, source_1)
node _T_1636 = asUInt(reset)
node _T_1637 = eq(_T_1636, UInt<1>(0h0))
when _T_1637 :
node _T_1638 = eq(_T_1635, UInt<1>(0h0))
when _T_1638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1635, UInt<1>(0h1), "") : assert_95
node _T_1639 = eq(io.in.d.bits.sink, sink)
node _T_1640 = asUInt(reset)
node _T_1641 = eq(_T_1640, UInt<1>(0h0))
when _T_1641 :
node _T_1642 = eq(_T_1639, UInt<1>(0h0))
when _T_1642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1639, UInt<1>(0h1), "") : assert_96
node _T_1643 = eq(io.in.d.bits.denied, denied)
node _T_1644 = asUInt(reset)
node _T_1645 = eq(_T_1644, UInt<1>(0h0))
when _T_1645 :
node _T_1646 = eq(_T_1643, UInt<1>(0h0))
when _T_1646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1643, UInt<1>(0h1), "") : assert_97
node _T_1647 = and(io.in.d.ready, io.in.d.valid)
node _T_1648 = and(_T_1647, d_first)
when _T_1648 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes : UInt<2056>, clock, reset, UInt<2056>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<257>
connect a_set, UInt<257>(0h0)
wire a_set_wo_ready : UInt<257>
connect a_set_wo_ready, UInt<257>(0h0)
wire a_opcodes_set : UInt<1028>
connect a_opcodes_set, UInt<1028>(0h0)
wire a_sizes_set : UInt<2056>
connect a_sizes_set, UInt<2056>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1649 = and(io.in.a.valid, a_first_1)
node _T_1650 = and(_T_1649, UInt<1>(0h1))
when _T_1650 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1651 = and(io.in.a.ready, io.in.a.valid)
node _T_1652 = and(_T_1651, a_first_1)
node _T_1653 = and(_T_1652, UInt<1>(0h1))
when _T_1653 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1654 = dshr(inflight, io.in.a.bits.source)
node _T_1655 = bits(_T_1654, 0, 0)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
node _T_1657 = asUInt(reset)
node _T_1658 = eq(_T_1657, UInt<1>(0h0))
when _T_1658 :
node _T_1659 = eq(_T_1656, UInt<1>(0h0))
when _T_1659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1656, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<257>
connect d_clr, UInt<257>(0h0)
wire d_clr_wo_ready : UInt<257>
connect d_clr_wo_ready, UInt<257>(0h0)
wire d_opcodes_clr : UInt<1028>
connect d_opcodes_clr, UInt<1028>(0h0)
wire d_sizes_clr : UInt<2056>
connect d_sizes_clr, UInt<2056>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1660 = and(io.in.d.valid, d_first_1)
node _T_1661 = and(_T_1660, UInt<1>(0h1))
node _T_1662 = eq(d_release_ack, UInt<1>(0h0))
node _T_1663 = and(_T_1661, _T_1662)
when _T_1663 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1664 = and(io.in.d.ready, io.in.d.valid)
node _T_1665 = and(_T_1664, d_first_1)
node _T_1666 = and(_T_1665, UInt<1>(0h1))
node _T_1667 = eq(d_release_ack, UInt<1>(0h0))
node _T_1668 = and(_T_1666, _T_1667)
when _T_1668 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1669 = and(io.in.d.valid, d_first_1)
node _T_1670 = and(_T_1669, UInt<1>(0h1))
node _T_1671 = eq(d_release_ack, UInt<1>(0h0))
node _T_1672 = and(_T_1670, _T_1671)
when _T_1672 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1673 = dshr(inflight, io.in.d.bits.source)
node _T_1674 = bits(_T_1673, 0, 0)
node _T_1675 = or(_T_1674, same_cycle_resp)
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(_T_1675, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1675, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1679 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1680 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1681 = or(_T_1679, _T_1680)
node _T_1682 = asUInt(reset)
node _T_1683 = eq(_T_1682, UInt<1>(0h0))
when _T_1683 :
node _T_1684 = eq(_T_1681, UInt<1>(0h0))
when _T_1684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1681, UInt<1>(0h1), "") : assert_100
node _T_1685 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1686 = asUInt(reset)
node _T_1687 = eq(_T_1686, UInt<1>(0h0))
when _T_1687 :
node _T_1688 = eq(_T_1685, UInt<1>(0h0))
when _T_1688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1685, UInt<1>(0h1), "") : assert_101
else :
node _T_1689 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1690 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1691 = or(_T_1689, _T_1690)
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_102
node _T_1695 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_103
node _T_1699 = and(io.in.d.valid, d_first_1)
node _T_1700 = and(_T_1699, a_first_1)
node _T_1701 = and(_T_1700, io.in.a.valid)
node _T_1702 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1703 = and(_T_1701, _T_1702)
node _T_1704 = eq(d_release_ack, UInt<1>(0h0))
node _T_1705 = and(_T_1703, _T_1704)
when _T_1705 :
node _T_1706 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1707 = or(_T_1706, io.in.a.ready)
node _T_1708 = asUInt(reset)
node _T_1709 = eq(_T_1708, UInt<1>(0h0))
when _T_1709 :
node _T_1710 = eq(_T_1707, UInt<1>(0h0))
when _T_1710 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1707, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_38
node _T_1711 = orr(inflight)
node _T_1712 = eq(_T_1711, UInt<1>(0h0))
node _T_1713 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1714 = or(_T_1712, _T_1713)
node _T_1715 = lt(watchdog, plusarg_reader.out)
node _T_1716 = or(_T_1714, _T_1715)
node _T_1717 = asUInt(reset)
node _T_1718 = eq(_T_1717, UInt<1>(0h0))
when _T_1718 :
node _T_1719 = eq(_T_1716, UInt<1>(0h0))
when _T_1719 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1716, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1720 = and(io.in.a.ready, io.in.a.valid)
node _T_1721 = and(io.in.d.ready, io.in.d.valid)
node _T_1722 = or(_T_1720, _T_1721)
when _T_1722 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes_1 : UInt<2056>, clock, reset, UInt<2056>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<9>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<257>
connect c_set, UInt<257>(0h0)
wire c_set_wo_ready : UInt<257>
connect c_set_wo_ready, UInt<257>(0h0)
wire c_opcodes_set : UInt<1028>
connect c_opcodes_set, UInt<1028>(0h0)
wire c_sizes_set : UInt<2056>
connect c_sizes_set, UInt<2056>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<9>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1723 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<9>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1724 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1725 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1726 = and(_T_1724, _T_1725)
node _T_1727 = and(_T_1723, _T_1726)
when _T_1727 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<9>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1728 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1729 = and(_T_1728, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<9>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1730 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1731 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1732 = and(_T_1730, _T_1731)
node _T_1733 = and(_T_1729, _T_1732)
when _T_1733 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<9>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1734 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1735 = bits(_T_1734, 0, 0)
node _T_1736 = eq(_T_1735, UInt<1>(0h0))
node _T_1737 = asUInt(reset)
node _T_1738 = eq(_T_1737, UInt<1>(0h0))
when _T_1738 :
node _T_1739 = eq(_T_1736, UInt<1>(0h0))
when _T_1739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1736, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<257>
connect d_clr_1, UInt<257>(0h0)
wire d_clr_wo_ready_1 : UInt<257>
connect d_clr_wo_ready_1, UInt<257>(0h0)
wire d_opcodes_clr_1 : UInt<1028>
connect d_opcodes_clr_1, UInt<1028>(0h0)
wire d_sizes_clr_1 : UInt<2056>
connect d_sizes_clr_1, UInt<2056>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1740 = and(io.in.d.valid, d_first_2)
node _T_1741 = and(_T_1740, UInt<1>(0h1))
node _T_1742 = and(_T_1741, d_release_ack_1)
when _T_1742 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1743 = and(io.in.d.ready, io.in.d.valid)
node _T_1744 = and(_T_1743, d_first_2)
node _T_1745 = and(_T_1744, UInt<1>(0h1))
node _T_1746 = and(_T_1745, d_release_ack_1)
when _T_1746 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1747 = and(io.in.d.valid, d_first_2)
node _T_1748 = and(_T_1747, UInt<1>(0h1))
node _T_1749 = and(_T_1748, d_release_ack_1)
when _T_1749 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1750 = dshr(inflight_1, io.in.d.bits.source)
node _T_1751 = bits(_T_1750, 0, 0)
node _T_1752 = or(_T_1751, same_cycle_resp_1)
node _T_1753 = asUInt(reset)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
when _T_1754 :
node _T_1755 = eq(_T_1752, UInt<1>(0h0))
when _T_1755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1752, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<9>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1756 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_108
else :
node _T_1760 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1761 = asUInt(reset)
node _T_1762 = eq(_T_1761, UInt<1>(0h0))
when _T_1762 :
node _T_1763 = eq(_T_1760, UInt<1>(0h0))
when _T_1763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1760, UInt<1>(0h1), "") : assert_109
node _T_1764 = and(io.in.d.valid, d_first_2)
node _T_1765 = and(_T_1764, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<9>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1766 = and(_T_1765, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<9>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1767 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1768 = and(_T_1766, _T_1767)
node _T_1769 = and(_T_1768, d_release_ack_1)
node _T_1770 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1771 = and(_T_1769, _T_1770)
when _T_1771 :
node _T_1772 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<9>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1773 = or(_T_1772, _WIRE_27.ready)
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(_T_1773, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1773, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_39
node _T_1777 = orr(inflight_1)
node _T_1778 = eq(_T_1777, UInt<1>(0h0))
node _T_1779 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1780 = or(_T_1778, _T_1779)
node _T_1781 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1782 = or(_T_1780, _T_1781)
node _T_1783 = asUInt(reset)
node _T_1784 = eq(_T_1783, UInt<1>(0h0))
when _T_1784 :
node _T_1785 = eq(_T_1782, UInt<1>(0h0))
when _T_1785 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1782, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<9>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1786 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1787 = and(io.in.d.ready, io.in.d.valid)
node _T_1788 = or(_T_1786, _T_1787)
when _T_1788 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1720 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1720; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1720; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1788 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1788; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1788; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1788; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1653 = _T_1720 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1653 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1668 = _T_1788 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1668 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2055:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1764 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1764 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1746 = _T_1788 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1746 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1746 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1746 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveToNoC_13 :
input clock : Clock
input reset : Reset
output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}}
inst a of TLAFromNoC_13
connect a.clock, clock
connect a.reset, reset
inst b of TLBToNoC_13
connect b.clock, clock
connect b.reset, reset
inst c of TLCFromNoC_13
connect c.clock, clock
connect c.reset, reset
inst d of TLDToNoC_13
connect d.clock, clock
connect d.reset, reset
inst e of TLEFromNoC_13
connect e.clock, clock
connect e.reset, reset
connect io.tilelink.a.bits, a.io.protocol.bits
connect io.tilelink.a.valid, a.io.protocol.valid
connect a.io.protocol.ready, io.tilelink.a.ready
wire _b_io_protocol_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _b_io_protocol_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_io_protocol_WIRE.bits.data, UInt<64>(0h0)
connect _b_io_protocol_WIRE.bits.mask, UInt<8>(0h0)
connect _b_io_protocol_WIRE.bits.address, UInt<32>(0h0)
connect _b_io_protocol_WIRE.bits.source, UInt<6>(0h0)
connect _b_io_protocol_WIRE.bits.size, UInt<3>(0h0)
connect _b_io_protocol_WIRE.bits.param, UInt<2>(0h0)
connect _b_io_protocol_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_io_protocol_WIRE.valid, UInt<1>(0h0)
connect _b_io_protocol_WIRE.ready, UInt<1>(0h0)
wire _b_io_protocol_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _b_io_protocol_WIRE_1.bits, _b_io_protocol_WIRE.bits
connect _b_io_protocol_WIRE_1.valid, _b_io_protocol_WIRE.valid
connect _b_io_protocol_WIRE_1.ready, _b_io_protocol_WIRE.ready
connect b.io.protocol, _b_io_protocol_WIRE_1
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<3>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.bits, c.io.protocol.bits
connect _WIRE_1.valid, c.io.protocol.valid
connect c.io.protocol.ready, _WIRE_1.ready
connect d.io.protocol, io.tilelink.d
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_2.bits.sink, UInt<1>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.bits, e.io.protocol.bits
connect _WIRE_3.valid, e.io.protocol.valid
connect e.io.protocol.ready, _WIRE_3.ready
connect a.io.flit, io.flits.a
connect io.flits.b.bits, b.io.flit.bits
connect io.flits.b.valid, b.io.flit.valid
connect b.io.flit.ready, io.flits.b.ready
connect c.io.flit, io.flits.c
connect io.flits.d.bits, d.io.flit.bits
connect io.flits.d.valid, d.io.flit.valid
connect d.io.flit.ready, io.flits.d.ready
connect e.io.flit, io.flits.e | module TLSlaveToNoC_13( // @[Tilelink.scala:125:7]
input clock, // @[Tilelink.scala:125:7]
input reset, // @[Tilelink.scala:125:7]
input io_tilelink_a_ready, // @[Tilelink.scala:132:14]
output io_tilelink_a_valid, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14]
output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14]
output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14]
output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14]
output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14]
output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14]
output io_tilelink_d_ready, // @[Tilelink.scala:132:14]
input io_tilelink_d_valid, // @[Tilelink.scala:132:14]
input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14]
input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14]
input [2:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14]
input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14]
input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14]
output io_flits_a_ready, // @[Tilelink.scala:132:14]
input io_flits_a_valid, // @[Tilelink.scala:132:14]
input io_flits_a_bits_head, // @[Tilelink.scala:132:14]
input io_flits_a_bits_tail, // @[Tilelink.scala:132:14]
input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14]
output io_flits_c_ready, // @[Tilelink.scala:132:14]
input io_flits_c_valid, // @[Tilelink.scala:132:14]
input io_flits_c_bits_head, // @[Tilelink.scala:132:14]
input io_flits_c_bits_tail, // @[Tilelink.scala:132:14]
input io_flits_d_ready, // @[Tilelink.scala:132:14]
output io_flits_d_valid, // @[Tilelink.scala:132:14]
output io_flits_d_bits_head, // @[Tilelink.scala:132:14]
output io_flits_d_bits_tail, // @[Tilelink.scala:132:14]
output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14]
output [2:0] io_flits_d_bits_egress_id, // @[Tilelink.scala:132:14]
output io_flits_e_ready, // @[Tilelink.scala:132:14]
input io_flits_e_valid, // @[Tilelink.scala:132:14]
input io_flits_e_bits_head, // @[Tilelink.scala:132:14]
input io_flits_e_bits_tail // @[Tilelink.scala:132:14]
);
wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17]
TLAFromNoC_13 a ( // @[Tilelink.scala:143:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload)
); // @[Tilelink.scala:143:17]
TLCFromNoC_13 c ( // @[Tilelink.scala:145:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail)
); // @[Tilelink.scala:145:17]
TLDToNoC_13 d ( // @[Tilelink.scala:146:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (_d_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_d_bits_egress_id)
); // @[Tilelink.scala:146:17]
TLEFromNoC_5 e ( // @[Tilelink.scala:147:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_tail (io_flits_e_bits_tail)
); // @[Tilelink.scala:147:17]
assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_62 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied | module IssueSlot_62( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_clint :
input clock : Clock
input reset : Reset
output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fragmenter of TLFragmenter_CLINT
connect fragmenter.clock, clock
connect fragmenter.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect fragmenter.auto.anon_in, tlOut
connect tlIn, auto.tl_in
connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d
connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits
connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid
connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready
extmodule plusarg_reader_48 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_49 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_cbus_to_clint( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [6:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [10:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [25:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [6:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [25:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [10:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [25:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [25:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
TLFragmenter_CLINT fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (tlOut_a_ready),
.auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_d_valid (tlOut_d_valid),
.auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode),
.auto_anon_in_d_bits_size (tlOut_d_bits_size),
.auto_anon_in_d_bits_source (tlOut_d_bits_source),
.auto_anon_in_d_bits_data (tlOut_d_bits_data),
.auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0),
.auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7]
); // @[Fragmenter.scala:345:34]
assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_97 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_265
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_266
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_267 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_268 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_97( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [8:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_26 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_26
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_26
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_41
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_26( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_26 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_26 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_41 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing :
input clock : Clock
input reset : Reset
output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[3], iss_valids : UInt<1>[1], iss_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip fu_types : UInt<10>[1], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush_pipeline : UInt<1>, flip ld_miss : UInt<1>, event_empty : UInt<1>, flip tsc_reg : UInt<64>}
wire _WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
wire _WIRE_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
wire _WIRE_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect _WIRE, io.dis_uops[0].bits
connect _WIRE.iw_p1_poisoned, UInt<1>(0h0)
connect _WIRE.iw_p2_poisoned, UInt<1>(0h0)
connect _WIRE.iw_state, UInt<2>(0h1)
node _T = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h2))
when _T :
connect _WIRE.lrs1_rtype, UInt<2>(0h2)
connect _WIRE.prs1_busy, UInt<1>(0h0)
node _T_1 = and(io.dis_uops[0].bits.ppred_busy, io.dis_uops[0].valid)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit.scala:145 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
connect _WIRE.ppred_busy, UInt<1>(0h0)
connect _WIRE_1, io.dis_uops[1].bits
connect _WIRE_1.iw_p1_poisoned, UInt<1>(0h0)
connect _WIRE_1.iw_p2_poisoned, UInt<1>(0h0)
connect _WIRE_1.iw_state, UInt<2>(0h1)
node _T_6 = eq(io.dis_uops[1].bits.uopc, UInt<7>(0h2))
when _T_6 :
connect _WIRE_1.lrs1_rtype, UInt<2>(0h2)
connect _WIRE_1.prs1_busy, UInt<1>(0h0)
node _T_7 = and(io.dis_uops[1].bits.ppred_busy, io.dis_uops[1].valid)
node _T_8 = eq(_T_7, UInt<1>(0h0))
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit.scala:145 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf_1
assert(clock, _T_8, UInt<1>(0h1), "") : assert_1
connect _WIRE_1.ppred_busy, UInt<1>(0h0)
connect _WIRE_2, io.dis_uops[2].bits
connect _WIRE_2.iw_p1_poisoned, UInt<1>(0h0)
connect _WIRE_2.iw_p2_poisoned, UInt<1>(0h0)
connect _WIRE_2.iw_state, UInt<2>(0h1)
node _T_12 = eq(io.dis_uops[2].bits.uopc, UInt<7>(0h2))
when _T_12 :
connect _WIRE_2.lrs1_rtype, UInt<2>(0h2)
connect _WIRE_2.prs1_busy, UInt<1>(0h0)
node _T_13 = and(io.dis_uops[2].bits.ppred_busy, io.dis_uops[2].valid)
node _T_14 = eq(_T_13, UInt<1>(0h0))
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit.scala:145 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf_2
assert(clock, _T_14, UInt<1>(0h1), "") : assert_2
connect _WIRE_2.ppred_busy, UInt<1>(0h0)
inst slots_0 of IssueSlot
connect slots_0.clock, clock
connect slots_0.reset, reset
inst slots_1 of IssueSlot_1
connect slots_1.clock, clock
connect slots_1.reset, reset
inst slots_2 of IssueSlot_2
connect slots_2.clock, clock
connect slots_2.reset, reset
inst slots_3 of IssueSlot_3
connect slots_3.clock, clock
connect slots_3.reset, reset
inst slots_4 of IssueSlot_4
connect slots_4.clock, clock
connect slots_4.reset, reset
inst slots_5 of IssueSlot_5
connect slots_5.clock, clock
connect slots_5.reset, reset
inst slots_6 of IssueSlot_6
connect slots_6.clock, clock
connect slots_6.reset, reset
inst slots_7 of IssueSlot_7
connect slots_7.clock, clock
connect slots_7.reset, reset
inst slots_8 of IssueSlot_8
connect slots_8.clock, clock
connect slots_8.reset, reset
inst slots_9 of IssueSlot_9
connect slots_9.clock, clock
connect slots_9.reset, reset
inst slots_10 of IssueSlot_10
connect slots_10.clock, clock
connect slots_10.reset, reset
inst slots_11 of IssueSlot_11
connect slots_11.clock, clock
connect slots_11.reset, reset
inst slots_12 of IssueSlot_12
connect slots_12.clock, clock
connect slots_12.reset, reset
inst slots_13 of IssueSlot_13
connect slots_13.clock, clock
connect slots_13.reset, reset
inst slots_14 of IssueSlot_14
connect slots_14.clock, clock
connect slots_14.reset, reset
inst slots_15 of IssueSlot_15
connect slots_15.clock, clock
connect slots_15.reset, reset
inst slots_16 of IssueSlot_16
connect slots_16.clock, clock
connect slots_16.reset, reset
inst slots_17 of IssueSlot_17
connect slots_17.clock, clock
connect slots_17.reset, reset
inst slots_18 of IssueSlot_18
connect slots_18.clock, clock
connect slots_18.reset, reset
inst slots_19 of IssueSlot_19
connect slots_19.clock, clock
connect slots_19.reset, reset
inst slots_20 of IssueSlot_20
connect slots_20.clock, clock
connect slots_20.reset, reset
inst slots_21 of IssueSlot_21
connect slots_21.clock, clock
connect slots_21.reset, reset
inst slots_22 of IssueSlot_22
connect slots_22.clock, clock
connect slots_22.reset, reset
inst slots_23 of IssueSlot_23
connect slots_23.clock, clock
connect slots_23.reset, reset
wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}[24]
connect issue_slots[0].debug.state, slots_0.io.debug.state
connect issue_slots[0].debug.ppred, slots_0.io.debug.ppred
connect issue_slots[0].debug.p3, slots_0.io.debug.p3
connect issue_slots[0].debug.p2, slots_0.io.debug.p2
connect issue_slots[0].debug.p1, slots_0.io.debug.p1
connect issue_slots[0].uop.debug_tsrc, slots_0.io.uop.debug_tsrc
connect issue_slots[0].uop.debug_fsrc, slots_0.io.uop.debug_fsrc
connect issue_slots[0].uop.bp_xcpt_if, slots_0.io.uop.bp_xcpt_if
connect issue_slots[0].uop.bp_debug_if, slots_0.io.uop.bp_debug_if
connect issue_slots[0].uop.xcpt_ma_if, slots_0.io.uop.xcpt_ma_if
connect issue_slots[0].uop.xcpt_ae_if, slots_0.io.uop.xcpt_ae_if
connect issue_slots[0].uop.xcpt_pf_if, slots_0.io.uop.xcpt_pf_if
connect issue_slots[0].uop.fp_single, slots_0.io.uop.fp_single
connect issue_slots[0].uop.fp_val, slots_0.io.uop.fp_val
connect issue_slots[0].uop.frs3_en, slots_0.io.uop.frs3_en
connect issue_slots[0].uop.lrs2_rtype, slots_0.io.uop.lrs2_rtype
connect issue_slots[0].uop.lrs1_rtype, slots_0.io.uop.lrs1_rtype
connect issue_slots[0].uop.dst_rtype, slots_0.io.uop.dst_rtype
connect issue_slots[0].uop.ldst_val, slots_0.io.uop.ldst_val
connect issue_slots[0].uop.lrs3, slots_0.io.uop.lrs3
connect issue_slots[0].uop.lrs2, slots_0.io.uop.lrs2
connect issue_slots[0].uop.lrs1, slots_0.io.uop.lrs1
connect issue_slots[0].uop.ldst, slots_0.io.uop.ldst
connect issue_slots[0].uop.ldst_is_rs1, slots_0.io.uop.ldst_is_rs1
connect issue_slots[0].uop.flush_on_commit, slots_0.io.uop.flush_on_commit
connect issue_slots[0].uop.is_unique, slots_0.io.uop.is_unique
connect issue_slots[0].uop.is_sys_pc2epc, slots_0.io.uop.is_sys_pc2epc
connect issue_slots[0].uop.uses_stq, slots_0.io.uop.uses_stq
connect issue_slots[0].uop.uses_ldq, slots_0.io.uop.uses_ldq
connect issue_slots[0].uop.is_amo, slots_0.io.uop.is_amo
connect issue_slots[0].uop.is_fencei, slots_0.io.uop.is_fencei
connect issue_slots[0].uop.is_fence, slots_0.io.uop.is_fence
connect issue_slots[0].uop.mem_signed, slots_0.io.uop.mem_signed
connect issue_slots[0].uop.mem_size, slots_0.io.uop.mem_size
connect issue_slots[0].uop.mem_cmd, slots_0.io.uop.mem_cmd
connect issue_slots[0].uop.bypassable, slots_0.io.uop.bypassable
connect issue_slots[0].uop.exc_cause, slots_0.io.uop.exc_cause
connect issue_slots[0].uop.exception, slots_0.io.uop.exception
connect issue_slots[0].uop.stale_pdst, slots_0.io.uop.stale_pdst
connect issue_slots[0].uop.ppred_busy, slots_0.io.uop.ppred_busy
connect issue_slots[0].uop.prs3_busy, slots_0.io.uop.prs3_busy
connect issue_slots[0].uop.prs2_busy, slots_0.io.uop.prs2_busy
connect issue_slots[0].uop.prs1_busy, slots_0.io.uop.prs1_busy
connect issue_slots[0].uop.ppred, slots_0.io.uop.ppred
connect issue_slots[0].uop.prs3, slots_0.io.uop.prs3
connect issue_slots[0].uop.prs2, slots_0.io.uop.prs2
connect issue_slots[0].uop.prs1, slots_0.io.uop.prs1
connect issue_slots[0].uop.pdst, slots_0.io.uop.pdst
connect issue_slots[0].uop.rxq_idx, slots_0.io.uop.rxq_idx
connect issue_slots[0].uop.stq_idx, slots_0.io.uop.stq_idx
connect issue_slots[0].uop.ldq_idx, slots_0.io.uop.ldq_idx
connect issue_slots[0].uop.rob_idx, slots_0.io.uop.rob_idx
connect issue_slots[0].uop.csr_addr, slots_0.io.uop.csr_addr
connect issue_slots[0].uop.imm_packed, slots_0.io.uop.imm_packed
connect issue_slots[0].uop.taken, slots_0.io.uop.taken
connect issue_slots[0].uop.pc_lob, slots_0.io.uop.pc_lob
connect issue_slots[0].uop.edge_inst, slots_0.io.uop.edge_inst
connect issue_slots[0].uop.ftq_idx, slots_0.io.uop.ftq_idx
connect issue_slots[0].uop.br_tag, slots_0.io.uop.br_tag
connect issue_slots[0].uop.br_mask, slots_0.io.uop.br_mask
connect issue_slots[0].uop.is_sfb, slots_0.io.uop.is_sfb
connect issue_slots[0].uop.is_jal, slots_0.io.uop.is_jal
connect issue_slots[0].uop.is_jalr, slots_0.io.uop.is_jalr
connect issue_slots[0].uop.is_br, slots_0.io.uop.is_br
connect issue_slots[0].uop.iw_p2_poisoned, slots_0.io.uop.iw_p2_poisoned
connect issue_slots[0].uop.iw_p1_poisoned, slots_0.io.uop.iw_p1_poisoned
connect issue_slots[0].uop.iw_state, slots_0.io.uop.iw_state
connect issue_slots[0].uop.ctrl.is_std, slots_0.io.uop.ctrl.is_std
connect issue_slots[0].uop.ctrl.is_sta, slots_0.io.uop.ctrl.is_sta
connect issue_slots[0].uop.ctrl.is_load, slots_0.io.uop.ctrl.is_load
connect issue_slots[0].uop.ctrl.csr_cmd, slots_0.io.uop.ctrl.csr_cmd
connect issue_slots[0].uop.ctrl.fcn_dw, slots_0.io.uop.ctrl.fcn_dw
connect issue_slots[0].uop.ctrl.op_fcn, slots_0.io.uop.ctrl.op_fcn
connect issue_slots[0].uop.ctrl.imm_sel, slots_0.io.uop.ctrl.imm_sel
connect issue_slots[0].uop.ctrl.op2_sel, slots_0.io.uop.ctrl.op2_sel
connect issue_slots[0].uop.ctrl.op1_sel, slots_0.io.uop.ctrl.op1_sel
connect issue_slots[0].uop.ctrl.br_type, slots_0.io.uop.ctrl.br_type
connect issue_slots[0].uop.fu_code, slots_0.io.uop.fu_code
connect issue_slots[0].uop.iq_type, slots_0.io.uop.iq_type
connect issue_slots[0].uop.debug_pc, slots_0.io.uop.debug_pc
connect issue_slots[0].uop.is_rvc, slots_0.io.uop.is_rvc
connect issue_slots[0].uop.debug_inst, slots_0.io.uop.debug_inst
connect issue_slots[0].uop.inst, slots_0.io.uop.inst
connect issue_slots[0].uop.uopc, slots_0.io.uop.uopc
connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc
connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc
connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if
connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if
connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if
connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if
connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if
connect issue_slots[0].out_uop.fp_single, slots_0.io.out_uop.fp_single
connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val
connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en
connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype
connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype
connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype
connect issue_slots[0].out_uop.ldst_val, slots_0.io.out_uop.ldst_val
connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3
connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2
connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1
connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst
connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1
connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit
connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique
connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc
connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq
connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq
connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo
connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei
connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence
connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed
connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size
connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd
connect issue_slots[0].out_uop.bypassable, slots_0.io.out_uop.bypassable
connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause
connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception
connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst
connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy
connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy
connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy
connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy
connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred
connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3
connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2
connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1
connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst
connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx
connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx
connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx
connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx
connect issue_slots[0].out_uop.csr_addr, slots_0.io.out_uop.csr_addr
connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed
connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken
connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob
connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst
connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx
connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag
connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask
connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb
connect issue_slots[0].out_uop.is_jal, slots_0.io.out_uop.is_jal
connect issue_slots[0].out_uop.is_jalr, slots_0.io.out_uop.is_jalr
connect issue_slots[0].out_uop.is_br, slots_0.io.out_uop.is_br
connect issue_slots[0].out_uop.iw_p2_poisoned, slots_0.io.out_uop.iw_p2_poisoned
connect issue_slots[0].out_uop.iw_p1_poisoned, slots_0.io.out_uop.iw_p1_poisoned
connect issue_slots[0].out_uop.iw_state, slots_0.io.out_uop.iw_state
connect issue_slots[0].out_uop.ctrl.is_std, slots_0.io.out_uop.ctrl.is_std
connect issue_slots[0].out_uop.ctrl.is_sta, slots_0.io.out_uop.ctrl.is_sta
connect issue_slots[0].out_uop.ctrl.is_load, slots_0.io.out_uop.ctrl.is_load
connect issue_slots[0].out_uop.ctrl.csr_cmd, slots_0.io.out_uop.ctrl.csr_cmd
connect issue_slots[0].out_uop.ctrl.fcn_dw, slots_0.io.out_uop.ctrl.fcn_dw
connect issue_slots[0].out_uop.ctrl.op_fcn, slots_0.io.out_uop.ctrl.op_fcn
connect issue_slots[0].out_uop.ctrl.imm_sel, slots_0.io.out_uop.ctrl.imm_sel
connect issue_slots[0].out_uop.ctrl.op2_sel, slots_0.io.out_uop.ctrl.op2_sel
connect issue_slots[0].out_uop.ctrl.op1_sel, slots_0.io.out_uop.ctrl.op1_sel
connect issue_slots[0].out_uop.ctrl.br_type, slots_0.io.out_uop.ctrl.br_type
connect issue_slots[0].out_uop.fu_code, slots_0.io.out_uop.fu_code
connect issue_slots[0].out_uop.iq_type, slots_0.io.out_uop.iq_type
connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc
connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc
connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst
connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst
connect issue_slots[0].out_uop.uopc, slots_0.io.out_uop.uopc
connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc
connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc
connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if
connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if
connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if
connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if
connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if
connect slots_0.io.in_uop.bits.fp_single, issue_slots[0].in_uop.bits.fp_single
connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val
connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en
connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype
connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype
connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype
connect slots_0.io.in_uop.bits.ldst_val, issue_slots[0].in_uop.bits.ldst_val
connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3
connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2
connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1
connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst
connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1
connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit
connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique
connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc
connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq
connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq
connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo
connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei
connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence
connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed
connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size
connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd
connect slots_0.io.in_uop.bits.bypassable, issue_slots[0].in_uop.bits.bypassable
connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause
connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception
connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst
connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy
connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy
connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy
connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy
connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred
connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3
connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2
connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1
connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst
connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx
connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx
connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx
connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx
connect slots_0.io.in_uop.bits.csr_addr, issue_slots[0].in_uop.bits.csr_addr
connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed
connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken
connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob
connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst
connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx
connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag
connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask
connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb
connect slots_0.io.in_uop.bits.is_jal, issue_slots[0].in_uop.bits.is_jal
connect slots_0.io.in_uop.bits.is_jalr, issue_slots[0].in_uop.bits.is_jalr
connect slots_0.io.in_uop.bits.is_br, issue_slots[0].in_uop.bits.is_br
connect slots_0.io.in_uop.bits.iw_p2_poisoned, issue_slots[0].in_uop.bits.iw_p2_poisoned
connect slots_0.io.in_uop.bits.iw_p1_poisoned, issue_slots[0].in_uop.bits.iw_p1_poisoned
connect slots_0.io.in_uop.bits.iw_state, issue_slots[0].in_uop.bits.iw_state
connect slots_0.io.in_uop.bits.ctrl.is_std, issue_slots[0].in_uop.bits.ctrl.is_std
connect slots_0.io.in_uop.bits.ctrl.is_sta, issue_slots[0].in_uop.bits.ctrl.is_sta
connect slots_0.io.in_uop.bits.ctrl.is_load, issue_slots[0].in_uop.bits.ctrl.is_load
connect slots_0.io.in_uop.bits.ctrl.csr_cmd, issue_slots[0].in_uop.bits.ctrl.csr_cmd
connect slots_0.io.in_uop.bits.ctrl.fcn_dw, issue_slots[0].in_uop.bits.ctrl.fcn_dw
connect slots_0.io.in_uop.bits.ctrl.op_fcn, issue_slots[0].in_uop.bits.ctrl.op_fcn
connect slots_0.io.in_uop.bits.ctrl.imm_sel, issue_slots[0].in_uop.bits.ctrl.imm_sel
connect slots_0.io.in_uop.bits.ctrl.op2_sel, issue_slots[0].in_uop.bits.ctrl.op2_sel
connect slots_0.io.in_uop.bits.ctrl.op1_sel, issue_slots[0].in_uop.bits.ctrl.op1_sel
connect slots_0.io.in_uop.bits.ctrl.br_type, issue_slots[0].in_uop.bits.ctrl.br_type
connect slots_0.io.in_uop.bits.fu_code, issue_slots[0].in_uop.bits.fu_code
connect slots_0.io.in_uop.bits.iq_type, issue_slots[0].in_uop.bits.iq_type
connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc
connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc
connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst
connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst
connect slots_0.io.in_uop.bits.uopc, issue_slots[0].in_uop.bits.uopc
connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid
connect slots_0.io.spec_ld_wakeup[0].bits, issue_slots[0].spec_ld_wakeup[0].bits
connect slots_0.io.spec_ld_wakeup[0].valid, issue_slots[0].spec_ld_wakeup[0].valid
connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits
connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid
connect slots_0.io.wakeup_ports[0].bits.poisoned, issue_slots[0].wakeup_ports[0].bits.poisoned
connect slots_0.io.wakeup_ports[0].bits.pdst, issue_slots[0].wakeup_ports[0].bits.pdst
connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid
connect slots_0.io.wakeup_ports[1].bits.poisoned, issue_slots[0].wakeup_ports[1].bits.poisoned
connect slots_0.io.wakeup_ports[1].bits.pdst, issue_slots[0].wakeup_ports[1].bits.pdst
connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid
connect slots_0.io.ldspec_miss, issue_slots[0].ldspec_miss
connect slots_0.io.clear, issue_slots[0].clear
connect slots_0.io.kill, issue_slots[0].kill
connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset
connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target
connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel
connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type
connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken
connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict
connect slots_0.io.brupdate.b2.valid, issue_slots[0].brupdate.b2.valid
connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc
connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc
connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if
connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if
connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if
connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if
connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if
connect slots_0.io.brupdate.b2.uop.fp_single, issue_slots[0].brupdate.b2.uop.fp_single
connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val
connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en
connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype
connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype
connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype
connect slots_0.io.brupdate.b2.uop.ldst_val, issue_slots[0].brupdate.b2.uop.ldst_val
connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3
connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2
connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1
connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst
connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1
connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit
connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique
connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc
connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq
connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq
connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo
connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei
connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence
connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed
connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size
connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd
connect slots_0.io.brupdate.b2.uop.bypassable, issue_slots[0].brupdate.b2.uop.bypassable
connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause
connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception
connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst
connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy
connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy
connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy
connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy
connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred
connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3
connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2
connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1
connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst
connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx
connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx
connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx
connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx
connect slots_0.io.brupdate.b2.uop.csr_addr, issue_slots[0].brupdate.b2.uop.csr_addr
connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed
connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken
connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob
connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst
connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx
connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag
connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask
connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb
connect slots_0.io.brupdate.b2.uop.is_jal, issue_slots[0].brupdate.b2.uop.is_jal
connect slots_0.io.brupdate.b2.uop.is_jalr, issue_slots[0].brupdate.b2.uop.is_jalr
connect slots_0.io.brupdate.b2.uop.is_br, issue_slots[0].brupdate.b2.uop.is_br
connect slots_0.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[0].brupdate.b2.uop.iw_p2_poisoned
connect slots_0.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[0].brupdate.b2.uop.iw_p1_poisoned
connect slots_0.io.brupdate.b2.uop.iw_state, issue_slots[0].brupdate.b2.uop.iw_state
connect slots_0.io.brupdate.b2.uop.ctrl.is_std, issue_slots[0].brupdate.b2.uop.ctrl.is_std
connect slots_0.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[0].brupdate.b2.uop.ctrl.is_sta
connect slots_0.io.brupdate.b2.uop.ctrl.is_load, issue_slots[0].brupdate.b2.uop.ctrl.is_load
connect slots_0.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd
connect slots_0.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw
connect slots_0.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[0].brupdate.b2.uop.ctrl.op_fcn
connect slots_0.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[0].brupdate.b2.uop.ctrl.imm_sel
connect slots_0.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[0].brupdate.b2.uop.ctrl.op2_sel
connect slots_0.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[0].brupdate.b2.uop.ctrl.op1_sel
connect slots_0.io.brupdate.b2.uop.ctrl.br_type, issue_slots[0].brupdate.b2.uop.ctrl.br_type
connect slots_0.io.brupdate.b2.uop.fu_code, issue_slots[0].brupdate.b2.uop.fu_code
connect slots_0.io.brupdate.b2.uop.iq_type, issue_slots[0].brupdate.b2.uop.iq_type
connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc
connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc
connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst
connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst
connect slots_0.io.brupdate.b2.uop.uopc, issue_slots[0].brupdate.b2.uop.uopc
connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask
connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask
connect slots_0.io.grant, issue_slots[0].grant
connect issue_slots[0].request_hp, slots_0.io.request_hp
connect issue_slots[0].request, slots_0.io.request
connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid
connect issue_slots[0].valid, slots_0.io.valid
connect issue_slots[1].debug.state, slots_1.io.debug.state
connect issue_slots[1].debug.ppred, slots_1.io.debug.ppred
connect issue_slots[1].debug.p3, slots_1.io.debug.p3
connect issue_slots[1].debug.p2, slots_1.io.debug.p2
connect issue_slots[1].debug.p1, slots_1.io.debug.p1
connect issue_slots[1].uop.debug_tsrc, slots_1.io.uop.debug_tsrc
connect issue_slots[1].uop.debug_fsrc, slots_1.io.uop.debug_fsrc
connect issue_slots[1].uop.bp_xcpt_if, slots_1.io.uop.bp_xcpt_if
connect issue_slots[1].uop.bp_debug_if, slots_1.io.uop.bp_debug_if
connect issue_slots[1].uop.xcpt_ma_if, slots_1.io.uop.xcpt_ma_if
connect issue_slots[1].uop.xcpt_ae_if, slots_1.io.uop.xcpt_ae_if
connect issue_slots[1].uop.xcpt_pf_if, slots_1.io.uop.xcpt_pf_if
connect issue_slots[1].uop.fp_single, slots_1.io.uop.fp_single
connect issue_slots[1].uop.fp_val, slots_1.io.uop.fp_val
connect issue_slots[1].uop.frs3_en, slots_1.io.uop.frs3_en
connect issue_slots[1].uop.lrs2_rtype, slots_1.io.uop.lrs2_rtype
connect issue_slots[1].uop.lrs1_rtype, slots_1.io.uop.lrs1_rtype
connect issue_slots[1].uop.dst_rtype, slots_1.io.uop.dst_rtype
connect issue_slots[1].uop.ldst_val, slots_1.io.uop.ldst_val
connect issue_slots[1].uop.lrs3, slots_1.io.uop.lrs3
connect issue_slots[1].uop.lrs2, slots_1.io.uop.lrs2
connect issue_slots[1].uop.lrs1, slots_1.io.uop.lrs1
connect issue_slots[1].uop.ldst, slots_1.io.uop.ldst
connect issue_slots[1].uop.ldst_is_rs1, slots_1.io.uop.ldst_is_rs1
connect issue_slots[1].uop.flush_on_commit, slots_1.io.uop.flush_on_commit
connect issue_slots[1].uop.is_unique, slots_1.io.uop.is_unique
connect issue_slots[1].uop.is_sys_pc2epc, slots_1.io.uop.is_sys_pc2epc
connect issue_slots[1].uop.uses_stq, slots_1.io.uop.uses_stq
connect issue_slots[1].uop.uses_ldq, slots_1.io.uop.uses_ldq
connect issue_slots[1].uop.is_amo, slots_1.io.uop.is_amo
connect issue_slots[1].uop.is_fencei, slots_1.io.uop.is_fencei
connect issue_slots[1].uop.is_fence, slots_1.io.uop.is_fence
connect issue_slots[1].uop.mem_signed, slots_1.io.uop.mem_signed
connect issue_slots[1].uop.mem_size, slots_1.io.uop.mem_size
connect issue_slots[1].uop.mem_cmd, slots_1.io.uop.mem_cmd
connect issue_slots[1].uop.bypassable, slots_1.io.uop.bypassable
connect issue_slots[1].uop.exc_cause, slots_1.io.uop.exc_cause
connect issue_slots[1].uop.exception, slots_1.io.uop.exception
connect issue_slots[1].uop.stale_pdst, slots_1.io.uop.stale_pdst
connect issue_slots[1].uop.ppred_busy, slots_1.io.uop.ppred_busy
connect issue_slots[1].uop.prs3_busy, slots_1.io.uop.prs3_busy
connect issue_slots[1].uop.prs2_busy, slots_1.io.uop.prs2_busy
connect issue_slots[1].uop.prs1_busy, slots_1.io.uop.prs1_busy
connect issue_slots[1].uop.ppred, slots_1.io.uop.ppred
connect issue_slots[1].uop.prs3, slots_1.io.uop.prs3
connect issue_slots[1].uop.prs2, slots_1.io.uop.prs2
connect issue_slots[1].uop.prs1, slots_1.io.uop.prs1
connect issue_slots[1].uop.pdst, slots_1.io.uop.pdst
connect issue_slots[1].uop.rxq_idx, slots_1.io.uop.rxq_idx
connect issue_slots[1].uop.stq_idx, slots_1.io.uop.stq_idx
connect issue_slots[1].uop.ldq_idx, slots_1.io.uop.ldq_idx
connect issue_slots[1].uop.rob_idx, slots_1.io.uop.rob_idx
connect issue_slots[1].uop.csr_addr, slots_1.io.uop.csr_addr
connect issue_slots[1].uop.imm_packed, slots_1.io.uop.imm_packed
connect issue_slots[1].uop.taken, slots_1.io.uop.taken
connect issue_slots[1].uop.pc_lob, slots_1.io.uop.pc_lob
connect issue_slots[1].uop.edge_inst, slots_1.io.uop.edge_inst
connect issue_slots[1].uop.ftq_idx, slots_1.io.uop.ftq_idx
connect issue_slots[1].uop.br_tag, slots_1.io.uop.br_tag
connect issue_slots[1].uop.br_mask, slots_1.io.uop.br_mask
connect issue_slots[1].uop.is_sfb, slots_1.io.uop.is_sfb
connect issue_slots[1].uop.is_jal, slots_1.io.uop.is_jal
connect issue_slots[1].uop.is_jalr, slots_1.io.uop.is_jalr
connect issue_slots[1].uop.is_br, slots_1.io.uop.is_br
connect issue_slots[1].uop.iw_p2_poisoned, slots_1.io.uop.iw_p2_poisoned
connect issue_slots[1].uop.iw_p1_poisoned, slots_1.io.uop.iw_p1_poisoned
connect issue_slots[1].uop.iw_state, slots_1.io.uop.iw_state
connect issue_slots[1].uop.ctrl.is_std, slots_1.io.uop.ctrl.is_std
connect issue_slots[1].uop.ctrl.is_sta, slots_1.io.uop.ctrl.is_sta
connect issue_slots[1].uop.ctrl.is_load, slots_1.io.uop.ctrl.is_load
connect issue_slots[1].uop.ctrl.csr_cmd, slots_1.io.uop.ctrl.csr_cmd
connect issue_slots[1].uop.ctrl.fcn_dw, slots_1.io.uop.ctrl.fcn_dw
connect issue_slots[1].uop.ctrl.op_fcn, slots_1.io.uop.ctrl.op_fcn
connect issue_slots[1].uop.ctrl.imm_sel, slots_1.io.uop.ctrl.imm_sel
connect issue_slots[1].uop.ctrl.op2_sel, slots_1.io.uop.ctrl.op2_sel
connect issue_slots[1].uop.ctrl.op1_sel, slots_1.io.uop.ctrl.op1_sel
connect issue_slots[1].uop.ctrl.br_type, slots_1.io.uop.ctrl.br_type
connect issue_slots[1].uop.fu_code, slots_1.io.uop.fu_code
connect issue_slots[1].uop.iq_type, slots_1.io.uop.iq_type
connect issue_slots[1].uop.debug_pc, slots_1.io.uop.debug_pc
connect issue_slots[1].uop.is_rvc, slots_1.io.uop.is_rvc
connect issue_slots[1].uop.debug_inst, slots_1.io.uop.debug_inst
connect issue_slots[1].uop.inst, slots_1.io.uop.inst
connect issue_slots[1].uop.uopc, slots_1.io.uop.uopc
connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc
connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc
connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if
connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if
connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if
connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if
connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if
connect issue_slots[1].out_uop.fp_single, slots_1.io.out_uop.fp_single
connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val
connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en
connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype
connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype
connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype
connect issue_slots[1].out_uop.ldst_val, slots_1.io.out_uop.ldst_val
connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3
connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2
connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1
connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst
connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1
connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit
connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique
connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc
connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq
connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq
connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo
connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei
connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence
connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed
connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size
connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd
connect issue_slots[1].out_uop.bypassable, slots_1.io.out_uop.bypassable
connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause
connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception
connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst
connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy
connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy
connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy
connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy
connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred
connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3
connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2
connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1
connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst
connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx
connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx
connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx
connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx
connect issue_slots[1].out_uop.csr_addr, slots_1.io.out_uop.csr_addr
connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed
connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken
connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob
connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst
connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx
connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag
connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask
connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb
connect issue_slots[1].out_uop.is_jal, slots_1.io.out_uop.is_jal
connect issue_slots[1].out_uop.is_jalr, slots_1.io.out_uop.is_jalr
connect issue_slots[1].out_uop.is_br, slots_1.io.out_uop.is_br
connect issue_slots[1].out_uop.iw_p2_poisoned, slots_1.io.out_uop.iw_p2_poisoned
connect issue_slots[1].out_uop.iw_p1_poisoned, slots_1.io.out_uop.iw_p1_poisoned
connect issue_slots[1].out_uop.iw_state, slots_1.io.out_uop.iw_state
connect issue_slots[1].out_uop.ctrl.is_std, slots_1.io.out_uop.ctrl.is_std
connect issue_slots[1].out_uop.ctrl.is_sta, slots_1.io.out_uop.ctrl.is_sta
connect issue_slots[1].out_uop.ctrl.is_load, slots_1.io.out_uop.ctrl.is_load
connect issue_slots[1].out_uop.ctrl.csr_cmd, slots_1.io.out_uop.ctrl.csr_cmd
connect issue_slots[1].out_uop.ctrl.fcn_dw, slots_1.io.out_uop.ctrl.fcn_dw
connect issue_slots[1].out_uop.ctrl.op_fcn, slots_1.io.out_uop.ctrl.op_fcn
connect issue_slots[1].out_uop.ctrl.imm_sel, slots_1.io.out_uop.ctrl.imm_sel
connect issue_slots[1].out_uop.ctrl.op2_sel, slots_1.io.out_uop.ctrl.op2_sel
connect issue_slots[1].out_uop.ctrl.op1_sel, slots_1.io.out_uop.ctrl.op1_sel
connect issue_slots[1].out_uop.ctrl.br_type, slots_1.io.out_uop.ctrl.br_type
connect issue_slots[1].out_uop.fu_code, slots_1.io.out_uop.fu_code
connect issue_slots[1].out_uop.iq_type, slots_1.io.out_uop.iq_type
connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc
connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc
connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst
connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst
connect issue_slots[1].out_uop.uopc, slots_1.io.out_uop.uopc
connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc
connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc
connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if
connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if
connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if
connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if
connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if
connect slots_1.io.in_uop.bits.fp_single, issue_slots[1].in_uop.bits.fp_single
connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val
connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en
connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype
connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype
connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype
connect slots_1.io.in_uop.bits.ldst_val, issue_slots[1].in_uop.bits.ldst_val
connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3
connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2
connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1
connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst
connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1
connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit
connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique
connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc
connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq
connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq
connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo
connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei
connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence
connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed
connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size
connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd
connect slots_1.io.in_uop.bits.bypassable, issue_slots[1].in_uop.bits.bypassable
connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause
connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception
connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst
connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy
connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy
connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy
connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy
connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred
connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3
connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2
connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1
connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst
connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx
connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx
connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx
connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx
connect slots_1.io.in_uop.bits.csr_addr, issue_slots[1].in_uop.bits.csr_addr
connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed
connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken
connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob
connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst
connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx
connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag
connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask
connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb
connect slots_1.io.in_uop.bits.is_jal, issue_slots[1].in_uop.bits.is_jal
connect slots_1.io.in_uop.bits.is_jalr, issue_slots[1].in_uop.bits.is_jalr
connect slots_1.io.in_uop.bits.is_br, issue_slots[1].in_uop.bits.is_br
connect slots_1.io.in_uop.bits.iw_p2_poisoned, issue_slots[1].in_uop.bits.iw_p2_poisoned
connect slots_1.io.in_uop.bits.iw_p1_poisoned, issue_slots[1].in_uop.bits.iw_p1_poisoned
connect slots_1.io.in_uop.bits.iw_state, issue_slots[1].in_uop.bits.iw_state
connect slots_1.io.in_uop.bits.ctrl.is_std, issue_slots[1].in_uop.bits.ctrl.is_std
connect slots_1.io.in_uop.bits.ctrl.is_sta, issue_slots[1].in_uop.bits.ctrl.is_sta
connect slots_1.io.in_uop.bits.ctrl.is_load, issue_slots[1].in_uop.bits.ctrl.is_load
connect slots_1.io.in_uop.bits.ctrl.csr_cmd, issue_slots[1].in_uop.bits.ctrl.csr_cmd
connect slots_1.io.in_uop.bits.ctrl.fcn_dw, issue_slots[1].in_uop.bits.ctrl.fcn_dw
connect slots_1.io.in_uop.bits.ctrl.op_fcn, issue_slots[1].in_uop.bits.ctrl.op_fcn
connect slots_1.io.in_uop.bits.ctrl.imm_sel, issue_slots[1].in_uop.bits.ctrl.imm_sel
connect slots_1.io.in_uop.bits.ctrl.op2_sel, issue_slots[1].in_uop.bits.ctrl.op2_sel
connect slots_1.io.in_uop.bits.ctrl.op1_sel, issue_slots[1].in_uop.bits.ctrl.op1_sel
connect slots_1.io.in_uop.bits.ctrl.br_type, issue_slots[1].in_uop.bits.ctrl.br_type
connect slots_1.io.in_uop.bits.fu_code, issue_slots[1].in_uop.bits.fu_code
connect slots_1.io.in_uop.bits.iq_type, issue_slots[1].in_uop.bits.iq_type
connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc
connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc
connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst
connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst
connect slots_1.io.in_uop.bits.uopc, issue_slots[1].in_uop.bits.uopc
connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid
connect slots_1.io.spec_ld_wakeup[0].bits, issue_slots[1].spec_ld_wakeup[0].bits
connect slots_1.io.spec_ld_wakeup[0].valid, issue_slots[1].spec_ld_wakeup[0].valid
connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits
connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid
connect slots_1.io.wakeup_ports[0].bits.poisoned, issue_slots[1].wakeup_ports[0].bits.poisoned
connect slots_1.io.wakeup_ports[0].bits.pdst, issue_slots[1].wakeup_ports[0].bits.pdst
connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid
connect slots_1.io.wakeup_ports[1].bits.poisoned, issue_slots[1].wakeup_ports[1].bits.poisoned
connect slots_1.io.wakeup_ports[1].bits.pdst, issue_slots[1].wakeup_ports[1].bits.pdst
connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid
connect slots_1.io.ldspec_miss, issue_slots[1].ldspec_miss
connect slots_1.io.clear, issue_slots[1].clear
connect slots_1.io.kill, issue_slots[1].kill
connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset
connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target
connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel
connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type
connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken
connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict
connect slots_1.io.brupdate.b2.valid, issue_slots[1].brupdate.b2.valid
connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc
connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc
connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if
connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if
connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if
connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if
connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if
connect slots_1.io.brupdate.b2.uop.fp_single, issue_slots[1].brupdate.b2.uop.fp_single
connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val
connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en
connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype
connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype
connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype
connect slots_1.io.brupdate.b2.uop.ldst_val, issue_slots[1].brupdate.b2.uop.ldst_val
connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3
connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2
connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1
connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst
connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1
connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit
connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique
connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc
connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq
connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq
connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo
connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei
connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence
connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed
connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size
connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd
connect slots_1.io.brupdate.b2.uop.bypassable, issue_slots[1].brupdate.b2.uop.bypassable
connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause
connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception
connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst
connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy
connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy
connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy
connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy
connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred
connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3
connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2
connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1
connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst
connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx
connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx
connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx
connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx
connect slots_1.io.brupdate.b2.uop.csr_addr, issue_slots[1].brupdate.b2.uop.csr_addr
connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed
connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken
connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob
connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst
connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx
connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag
connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask
connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb
connect slots_1.io.brupdate.b2.uop.is_jal, issue_slots[1].brupdate.b2.uop.is_jal
connect slots_1.io.brupdate.b2.uop.is_jalr, issue_slots[1].brupdate.b2.uop.is_jalr
connect slots_1.io.brupdate.b2.uop.is_br, issue_slots[1].brupdate.b2.uop.is_br
connect slots_1.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[1].brupdate.b2.uop.iw_p2_poisoned
connect slots_1.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[1].brupdate.b2.uop.iw_p1_poisoned
connect slots_1.io.brupdate.b2.uop.iw_state, issue_slots[1].brupdate.b2.uop.iw_state
connect slots_1.io.brupdate.b2.uop.ctrl.is_std, issue_slots[1].brupdate.b2.uop.ctrl.is_std
connect slots_1.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[1].brupdate.b2.uop.ctrl.is_sta
connect slots_1.io.brupdate.b2.uop.ctrl.is_load, issue_slots[1].brupdate.b2.uop.ctrl.is_load
connect slots_1.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd
connect slots_1.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw
connect slots_1.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[1].brupdate.b2.uop.ctrl.op_fcn
connect slots_1.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[1].brupdate.b2.uop.ctrl.imm_sel
connect slots_1.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[1].brupdate.b2.uop.ctrl.op2_sel
connect slots_1.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[1].brupdate.b2.uop.ctrl.op1_sel
connect slots_1.io.brupdate.b2.uop.ctrl.br_type, issue_slots[1].brupdate.b2.uop.ctrl.br_type
connect slots_1.io.brupdate.b2.uop.fu_code, issue_slots[1].brupdate.b2.uop.fu_code
connect slots_1.io.brupdate.b2.uop.iq_type, issue_slots[1].brupdate.b2.uop.iq_type
connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc
connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc
connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst
connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst
connect slots_1.io.brupdate.b2.uop.uopc, issue_slots[1].brupdate.b2.uop.uopc
connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask
connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask
connect slots_1.io.grant, issue_slots[1].grant
connect issue_slots[1].request_hp, slots_1.io.request_hp
connect issue_slots[1].request, slots_1.io.request
connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid
connect issue_slots[1].valid, slots_1.io.valid
connect issue_slots[2].debug.state, slots_2.io.debug.state
connect issue_slots[2].debug.ppred, slots_2.io.debug.ppred
connect issue_slots[2].debug.p3, slots_2.io.debug.p3
connect issue_slots[2].debug.p2, slots_2.io.debug.p2
connect issue_slots[2].debug.p1, slots_2.io.debug.p1
connect issue_slots[2].uop.debug_tsrc, slots_2.io.uop.debug_tsrc
connect issue_slots[2].uop.debug_fsrc, slots_2.io.uop.debug_fsrc
connect issue_slots[2].uop.bp_xcpt_if, slots_2.io.uop.bp_xcpt_if
connect issue_slots[2].uop.bp_debug_if, slots_2.io.uop.bp_debug_if
connect issue_slots[2].uop.xcpt_ma_if, slots_2.io.uop.xcpt_ma_if
connect issue_slots[2].uop.xcpt_ae_if, slots_2.io.uop.xcpt_ae_if
connect issue_slots[2].uop.xcpt_pf_if, slots_2.io.uop.xcpt_pf_if
connect issue_slots[2].uop.fp_single, slots_2.io.uop.fp_single
connect issue_slots[2].uop.fp_val, slots_2.io.uop.fp_val
connect issue_slots[2].uop.frs3_en, slots_2.io.uop.frs3_en
connect issue_slots[2].uop.lrs2_rtype, slots_2.io.uop.lrs2_rtype
connect issue_slots[2].uop.lrs1_rtype, slots_2.io.uop.lrs1_rtype
connect issue_slots[2].uop.dst_rtype, slots_2.io.uop.dst_rtype
connect issue_slots[2].uop.ldst_val, slots_2.io.uop.ldst_val
connect issue_slots[2].uop.lrs3, slots_2.io.uop.lrs3
connect issue_slots[2].uop.lrs2, slots_2.io.uop.lrs2
connect issue_slots[2].uop.lrs1, slots_2.io.uop.lrs1
connect issue_slots[2].uop.ldst, slots_2.io.uop.ldst
connect issue_slots[2].uop.ldst_is_rs1, slots_2.io.uop.ldst_is_rs1
connect issue_slots[2].uop.flush_on_commit, slots_2.io.uop.flush_on_commit
connect issue_slots[2].uop.is_unique, slots_2.io.uop.is_unique
connect issue_slots[2].uop.is_sys_pc2epc, slots_2.io.uop.is_sys_pc2epc
connect issue_slots[2].uop.uses_stq, slots_2.io.uop.uses_stq
connect issue_slots[2].uop.uses_ldq, slots_2.io.uop.uses_ldq
connect issue_slots[2].uop.is_amo, slots_2.io.uop.is_amo
connect issue_slots[2].uop.is_fencei, slots_2.io.uop.is_fencei
connect issue_slots[2].uop.is_fence, slots_2.io.uop.is_fence
connect issue_slots[2].uop.mem_signed, slots_2.io.uop.mem_signed
connect issue_slots[2].uop.mem_size, slots_2.io.uop.mem_size
connect issue_slots[2].uop.mem_cmd, slots_2.io.uop.mem_cmd
connect issue_slots[2].uop.bypassable, slots_2.io.uop.bypassable
connect issue_slots[2].uop.exc_cause, slots_2.io.uop.exc_cause
connect issue_slots[2].uop.exception, slots_2.io.uop.exception
connect issue_slots[2].uop.stale_pdst, slots_2.io.uop.stale_pdst
connect issue_slots[2].uop.ppred_busy, slots_2.io.uop.ppred_busy
connect issue_slots[2].uop.prs3_busy, slots_2.io.uop.prs3_busy
connect issue_slots[2].uop.prs2_busy, slots_2.io.uop.prs2_busy
connect issue_slots[2].uop.prs1_busy, slots_2.io.uop.prs1_busy
connect issue_slots[2].uop.ppred, slots_2.io.uop.ppred
connect issue_slots[2].uop.prs3, slots_2.io.uop.prs3
connect issue_slots[2].uop.prs2, slots_2.io.uop.prs2
connect issue_slots[2].uop.prs1, slots_2.io.uop.prs1
connect issue_slots[2].uop.pdst, slots_2.io.uop.pdst
connect issue_slots[2].uop.rxq_idx, slots_2.io.uop.rxq_idx
connect issue_slots[2].uop.stq_idx, slots_2.io.uop.stq_idx
connect issue_slots[2].uop.ldq_idx, slots_2.io.uop.ldq_idx
connect issue_slots[2].uop.rob_idx, slots_2.io.uop.rob_idx
connect issue_slots[2].uop.csr_addr, slots_2.io.uop.csr_addr
connect issue_slots[2].uop.imm_packed, slots_2.io.uop.imm_packed
connect issue_slots[2].uop.taken, slots_2.io.uop.taken
connect issue_slots[2].uop.pc_lob, slots_2.io.uop.pc_lob
connect issue_slots[2].uop.edge_inst, slots_2.io.uop.edge_inst
connect issue_slots[2].uop.ftq_idx, slots_2.io.uop.ftq_idx
connect issue_slots[2].uop.br_tag, slots_2.io.uop.br_tag
connect issue_slots[2].uop.br_mask, slots_2.io.uop.br_mask
connect issue_slots[2].uop.is_sfb, slots_2.io.uop.is_sfb
connect issue_slots[2].uop.is_jal, slots_2.io.uop.is_jal
connect issue_slots[2].uop.is_jalr, slots_2.io.uop.is_jalr
connect issue_slots[2].uop.is_br, slots_2.io.uop.is_br
connect issue_slots[2].uop.iw_p2_poisoned, slots_2.io.uop.iw_p2_poisoned
connect issue_slots[2].uop.iw_p1_poisoned, slots_2.io.uop.iw_p1_poisoned
connect issue_slots[2].uop.iw_state, slots_2.io.uop.iw_state
connect issue_slots[2].uop.ctrl.is_std, slots_2.io.uop.ctrl.is_std
connect issue_slots[2].uop.ctrl.is_sta, slots_2.io.uop.ctrl.is_sta
connect issue_slots[2].uop.ctrl.is_load, slots_2.io.uop.ctrl.is_load
connect issue_slots[2].uop.ctrl.csr_cmd, slots_2.io.uop.ctrl.csr_cmd
connect issue_slots[2].uop.ctrl.fcn_dw, slots_2.io.uop.ctrl.fcn_dw
connect issue_slots[2].uop.ctrl.op_fcn, slots_2.io.uop.ctrl.op_fcn
connect issue_slots[2].uop.ctrl.imm_sel, slots_2.io.uop.ctrl.imm_sel
connect issue_slots[2].uop.ctrl.op2_sel, slots_2.io.uop.ctrl.op2_sel
connect issue_slots[2].uop.ctrl.op1_sel, slots_2.io.uop.ctrl.op1_sel
connect issue_slots[2].uop.ctrl.br_type, slots_2.io.uop.ctrl.br_type
connect issue_slots[2].uop.fu_code, slots_2.io.uop.fu_code
connect issue_slots[2].uop.iq_type, slots_2.io.uop.iq_type
connect issue_slots[2].uop.debug_pc, slots_2.io.uop.debug_pc
connect issue_slots[2].uop.is_rvc, slots_2.io.uop.is_rvc
connect issue_slots[2].uop.debug_inst, slots_2.io.uop.debug_inst
connect issue_slots[2].uop.inst, slots_2.io.uop.inst
connect issue_slots[2].uop.uopc, slots_2.io.uop.uopc
connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc
connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc
connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if
connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if
connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if
connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if
connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if
connect issue_slots[2].out_uop.fp_single, slots_2.io.out_uop.fp_single
connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val
connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en
connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype
connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype
connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype
connect issue_slots[2].out_uop.ldst_val, slots_2.io.out_uop.ldst_val
connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3
connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2
connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1
connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst
connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1
connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit
connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique
connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc
connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq
connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq
connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo
connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei
connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence
connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed
connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size
connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd
connect issue_slots[2].out_uop.bypassable, slots_2.io.out_uop.bypassable
connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause
connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception
connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst
connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy
connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy
connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy
connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy
connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred
connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3
connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2
connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1
connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst
connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx
connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx
connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx
connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx
connect issue_slots[2].out_uop.csr_addr, slots_2.io.out_uop.csr_addr
connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed
connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken
connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob
connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst
connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx
connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag
connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask
connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb
connect issue_slots[2].out_uop.is_jal, slots_2.io.out_uop.is_jal
connect issue_slots[2].out_uop.is_jalr, slots_2.io.out_uop.is_jalr
connect issue_slots[2].out_uop.is_br, slots_2.io.out_uop.is_br
connect issue_slots[2].out_uop.iw_p2_poisoned, slots_2.io.out_uop.iw_p2_poisoned
connect issue_slots[2].out_uop.iw_p1_poisoned, slots_2.io.out_uop.iw_p1_poisoned
connect issue_slots[2].out_uop.iw_state, slots_2.io.out_uop.iw_state
connect issue_slots[2].out_uop.ctrl.is_std, slots_2.io.out_uop.ctrl.is_std
connect issue_slots[2].out_uop.ctrl.is_sta, slots_2.io.out_uop.ctrl.is_sta
connect issue_slots[2].out_uop.ctrl.is_load, slots_2.io.out_uop.ctrl.is_load
connect issue_slots[2].out_uop.ctrl.csr_cmd, slots_2.io.out_uop.ctrl.csr_cmd
connect issue_slots[2].out_uop.ctrl.fcn_dw, slots_2.io.out_uop.ctrl.fcn_dw
connect issue_slots[2].out_uop.ctrl.op_fcn, slots_2.io.out_uop.ctrl.op_fcn
connect issue_slots[2].out_uop.ctrl.imm_sel, slots_2.io.out_uop.ctrl.imm_sel
connect issue_slots[2].out_uop.ctrl.op2_sel, slots_2.io.out_uop.ctrl.op2_sel
connect issue_slots[2].out_uop.ctrl.op1_sel, slots_2.io.out_uop.ctrl.op1_sel
connect issue_slots[2].out_uop.ctrl.br_type, slots_2.io.out_uop.ctrl.br_type
connect issue_slots[2].out_uop.fu_code, slots_2.io.out_uop.fu_code
connect issue_slots[2].out_uop.iq_type, slots_2.io.out_uop.iq_type
connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc
connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc
connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst
connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst
connect issue_slots[2].out_uop.uopc, slots_2.io.out_uop.uopc
connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc
connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc
connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if
connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if
connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if
connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if
connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if
connect slots_2.io.in_uop.bits.fp_single, issue_slots[2].in_uop.bits.fp_single
connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val
connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en
connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype
connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype
connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype
connect slots_2.io.in_uop.bits.ldst_val, issue_slots[2].in_uop.bits.ldst_val
connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3
connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2
connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1
connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst
connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1
connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit
connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique
connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc
connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq
connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq
connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo
connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei
connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence
connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed
connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size
connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd
connect slots_2.io.in_uop.bits.bypassable, issue_slots[2].in_uop.bits.bypassable
connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause
connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception
connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst
connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy
connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy
connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy
connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy
connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred
connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3
connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2
connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1
connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst
connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx
connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx
connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx
connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx
connect slots_2.io.in_uop.bits.csr_addr, issue_slots[2].in_uop.bits.csr_addr
connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed
connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken
connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob
connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst
connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx
connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag
connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask
connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb
connect slots_2.io.in_uop.bits.is_jal, issue_slots[2].in_uop.bits.is_jal
connect slots_2.io.in_uop.bits.is_jalr, issue_slots[2].in_uop.bits.is_jalr
connect slots_2.io.in_uop.bits.is_br, issue_slots[2].in_uop.bits.is_br
connect slots_2.io.in_uop.bits.iw_p2_poisoned, issue_slots[2].in_uop.bits.iw_p2_poisoned
connect slots_2.io.in_uop.bits.iw_p1_poisoned, issue_slots[2].in_uop.bits.iw_p1_poisoned
connect slots_2.io.in_uop.bits.iw_state, issue_slots[2].in_uop.bits.iw_state
connect slots_2.io.in_uop.bits.ctrl.is_std, issue_slots[2].in_uop.bits.ctrl.is_std
connect slots_2.io.in_uop.bits.ctrl.is_sta, issue_slots[2].in_uop.bits.ctrl.is_sta
connect slots_2.io.in_uop.bits.ctrl.is_load, issue_slots[2].in_uop.bits.ctrl.is_load
connect slots_2.io.in_uop.bits.ctrl.csr_cmd, issue_slots[2].in_uop.bits.ctrl.csr_cmd
connect slots_2.io.in_uop.bits.ctrl.fcn_dw, issue_slots[2].in_uop.bits.ctrl.fcn_dw
connect slots_2.io.in_uop.bits.ctrl.op_fcn, issue_slots[2].in_uop.bits.ctrl.op_fcn
connect slots_2.io.in_uop.bits.ctrl.imm_sel, issue_slots[2].in_uop.bits.ctrl.imm_sel
connect slots_2.io.in_uop.bits.ctrl.op2_sel, issue_slots[2].in_uop.bits.ctrl.op2_sel
connect slots_2.io.in_uop.bits.ctrl.op1_sel, issue_slots[2].in_uop.bits.ctrl.op1_sel
connect slots_2.io.in_uop.bits.ctrl.br_type, issue_slots[2].in_uop.bits.ctrl.br_type
connect slots_2.io.in_uop.bits.fu_code, issue_slots[2].in_uop.bits.fu_code
connect slots_2.io.in_uop.bits.iq_type, issue_slots[2].in_uop.bits.iq_type
connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc
connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc
connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst
connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst
connect slots_2.io.in_uop.bits.uopc, issue_slots[2].in_uop.bits.uopc
connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid
connect slots_2.io.spec_ld_wakeup[0].bits, issue_slots[2].spec_ld_wakeup[0].bits
connect slots_2.io.spec_ld_wakeup[0].valid, issue_slots[2].spec_ld_wakeup[0].valid
connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits
connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid
connect slots_2.io.wakeup_ports[0].bits.poisoned, issue_slots[2].wakeup_ports[0].bits.poisoned
connect slots_2.io.wakeup_ports[0].bits.pdst, issue_slots[2].wakeup_ports[0].bits.pdst
connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid
connect slots_2.io.wakeup_ports[1].bits.poisoned, issue_slots[2].wakeup_ports[1].bits.poisoned
connect slots_2.io.wakeup_ports[1].bits.pdst, issue_slots[2].wakeup_ports[1].bits.pdst
connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid
connect slots_2.io.ldspec_miss, issue_slots[2].ldspec_miss
connect slots_2.io.clear, issue_slots[2].clear
connect slots_2.io.kill, issue_slots[2].kill
connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset
connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target
connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel
connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type
connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken
connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict
connect slots_2.io.brupdate.b2.valid, issue_slots[2].brupdate.b2.valid
connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc
connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc
connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if
connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if
connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if
connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if
connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if
connect slots_2.io.brupdate.b2.uop.fp_single, issue_slots[2].brupdate.b2.uop.fp_single
connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val
connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en
connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype
connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype
connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype
connect slots_2.io.brupdate.b2.uop.ldst_val, issue_slots[2].brupdate.b2.uop.ldst_val
connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3
connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2
connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1
connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst
connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1
connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit
connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique
connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc
connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq
connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq
connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo
connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei
connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence
connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed
connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size
connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd
connect slots_2.io.brupdate.b2.uop.bypassable, issue_slots[2].brupdate.b2.uop.bypassable
connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause
connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception
connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst
connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy
connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy
connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy
connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy
connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred
connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3
connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2
connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1
connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst
connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx
connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx
connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx
connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx
connect slots_2.io.brupdate.b2.uop.csr_addr, issue_slots[2].brupdate.b2.uop.csr_addr
connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed
connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken
connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob
connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst
connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx
connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag
connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask
connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb
connect slots_2.io.brupdate.b2.uop.is_jal, issue_slots[2].brupdate.b2.uop.is_jal
connect slots_2.io.brupdate.b2.uop.is_jalr, issue_slots[2].brupdate.b2.uop.is_jalr
connect slots_2.io.brupdate.b2.uop.is_br, issue_slots[2].brupdate.b2.uop.is_br
connect slots_2.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[2].brupdate.b2.uop.iw_p2_poisoned
connect slots_2.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[2].brupdate.b2.uop.iw_p1_poisoned
connect slots_2.io.brupdate.b2.uop.iw_state, issue_slots[2].brupdate.b2.uop.iw_state
connect slots_2.io.brupdate.b2.uop.ctrl.is_std, issue_slots[2].brupdate.b2.uop.ctrl.is_std
connect slots_2.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[2].brupdate.b2.uop.ctrl.is_sta
connect slots_2.io.brupdate.b2.uop.ctrl.is_load, issue_slots[2].brupdate.b2.uop.ctrl.is_load
connect slots_2.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd
connect slots_2.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw
connect slots_2.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[2].brupdate.b2.uop.ctrl.op_fcn
connect slots_2.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[2].brupdate.b2.uop.ctrl.imm_sel
connect slots_2.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[2].brupdate.b2.uop.ctrl.op2_sel
connect slots_2.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[2].brupdate.b2.uop.ctrl.op1_sel
connect slots_2.io.brupdate.b2.uop.ctrl.br_type, issue_slots[2].brupdate.b2.uop.ctrl.br_type
connect slots_2.io.brupdate.b2.uop.fu_code, issue_slots[2].brupdate.b2.uop.fu_code
connect slots_2.io.brupdate.b2.uop.iq_type, issue_slots[2].brupdate.b2.uop.iq_type
connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc
connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc
connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst
connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst
connect slots_2.io.brupdate.b2.uop.uopc, issue_slots[2].brupdate.b2.uop.uopc
connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask
connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask
connect slots_2.io.grant, issue_slots[2].grant
connect issue_slots[2].request_hp, slots_2.io.request_hp
connect issue_slots[2].request, slots_2.io.request
connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid
connect issue_slots[2].valid, slots_2.io.valid
connect issue_slots[3].debug.state, slots_3.io.debug.state
connect issue_slots[3].debug.ppred, slots_3.io.debug.ppred
connect issue_slots[3].debug.p3, slots_3.io.debug.p3
connect issue_slots[3].debug.p2, slots_3.io.debug.p2
connect issue_slots[3].debug.p1, slots_3.io.debug.p1
connect issue_slots[3].uop.debug_tsrc, slots_3.io.uop.debug_tsrc
connect issue_slots[3].uop.debug_fsrc, slots_3.io.uop.debug_fsrc
connect issue_slots[3].uop.bp_xcpt_if, slots_3.io.uop.bp_xcpt_if
connect issue_slots[3].uop.bp_debug_if, slots_3.io.uop.bp_debug_if
connect issue_slots[3].uop.xcpt_ma_if, slots_3.io.uop.xcpt_ma_if
connect issue_slots[3].uop.xcpt_ae_if, slots_3.io.uop.xcpt_ae_if
connect issue_slots[3].uop.xcpt_pf_if, slots_3.io.uop.xcpt_pf_if
connect issue_slots[3].uop.fp_single, slots_3.io.uop.fp_single
connect issue_slots[3].uop.fp_val, slots_3.io.uop.fp_val
connect issue_slots[3].uop.frs3_en, slots_3.io.uop.frs3_en
connect issue_slots[3].uop.lrs2_rtype, slots_3.io.uop.lrs2_rtype
connect issue_slots[3].uop.lrs1_rtype, slots_3.io.uop.lrs1_rtype
connect issue_slots[3].uop.dst_rtype, slots_3.io.uop.dst_rtype
connect issue_slots[3].uop.ldst_val, slots_3.io.uop.ldst_val
connect issue_slots[3].uop.lrs3, slots_3.io.uop.lrs3
connect issue_slots[3].uop.lrs2, slots_3.io.uop.lrs2
connect issue_slots[3].uop.lrs1, slots_3.io.uop.lrs1
connect issue_slots[3].uop.ldst, slots_3.io.uop.ldst
connect issue_slots[3].uop.ldst_is_rs1, slots_3.io.uop.ldst_is_rs1
connect issue_slots[3].uop.flush_on_commit, slots_3.io.uop.flush_on_commit
connect issue_slots[3].uop.is_unique, slots_3.io.uop.is_unique
connect issue_slots[3].uop.is_sys_pc2epc, slots_3.io.uop.is_sys_pc2epc
connect issue_slots[3].uop.uses_stq, slots_3.io.uop.uses_stq
connect issue_slots[3].uop.uses_ldq, slots_3.io.uop.uses_ldq
connect issue_slots[3].uop.is_amo, slots_3.io.uop.is_amo
connect issue_slots[3].uop.is_fencei, slots_3.io.uop.is_fencei
connect issue_slots[3].uop.is_fence, slots_3.io.uop.is_fence
connect issue_slots[3].uop.mem_signed, slots_3.io.uop.mem_signed
connect issue_slots[3].uop.mem_size, slots_3.io.uop.mem_size
connect issue_slots[3].uop.mem_cmd, slots_3.io.uop.mem_cmd
connect issue_slots[3].uop.bypassable, slots_3.io.uop.bypassable
connect issue_slots[3].uop.exc_cause, slots_3.io.uop.exc_cause
connect issue_slots[3].uop.exception, slots_3.io.uop.exception
connect issue_slots[3].uop.stale_pdst, slots_3.io.uop.stale_pdst
connect issue_slots[3].uop.ppred_busy, slots_3.io.uop.ppred_busy
connect issue_slots[3].uop.prs3_busy, slots_3.io.uop.prs3_busy
connect issue_slots[3].uop.prs2_busy, slots_3.io.uop.prs2_busy
connect issue_slots[3].uop.prs1_busy, slots_3.io.uop.prs1_busy
connect issue_slots[3].uop.ppred, slots_3.io.uop.ppred
connect issue_slots[3].uop.prs3, slots_3.io.uop.prs3
connect issue_slots[3].uop.prs2, slots_3.io.uop.prs2
connect issue_slots[3].uop.prs1, slots_3.io.uop.prs1
connect issue_slots[3].uop.pdst, slots_3.io.uop.pdst
connect issue_slots[3].uop.rxq_idx, slots_3.io.uop.rxq_idx
connect issue_slots[3].uop.stq_idx, slots_3.io.uop.stq_idx
connect issue_slots[3].uop.ldq_idx, slots_3.io.uop.ldq_idx
connect issue_slots[3].uop.rob_idx, slots_3.io.uop.rob_idx
connect issue_slots[3].uop.csr_addr, slots_3.io.uop.csr_addr
connect issue_slots[3].uop.imm_packed, slots_3.io.uop.imm_packed
connect issue_slots[3].uop.taken, slots_3.io.uop.taken
connect issue_slots[3].uop.pc_lob, slots_3.io.uop.pc_lob
connect issue_slots[3].uop.edge_inst, slots_3.io.uop.edge_inst
connect issue_slots[3].uop.ftq_idx, slots_3.io.uop.ftq_idx
connect issue_slots[3].uop.br_tag, slots_3.io.uop.br_tag
connect issue_slots[3].uop.br_mask, slots_3.io.uop.br_mask
connect issue_slots[3].uop.is_sfb, slots_3.io.uop.is_sfb
connect issue_slots[3].uop.is_jal, slots_3.io.uop.is_jal
connect issue_slots[3].uop.is_jalr, slots_3.io.uop.is_jalr
connect issue_slots[3].uop.is_br, slots_3.io.uop.is_br
connect issue_slots[3].uop.iw_p2_poisoned, slots_3.io.uop.iw_p2_poisoned
connect issue_slots[3].uop.iw_p1_poisoned, slots_3.io.uop.iw_p1_poisoned
connect issue_slots[3].uop.iw_state, slots_3.io.uop.iw_state
connect issue_slots[3].uop.ctrl.is_std, slots_3.io.uop.ctrl.is_std
connect issue_slots[3].uop.ctrl.is_sta, slots_3.io.uop.ctrl.is_sta
connect issue_slots[3].uop.ctrl.is_load, slots_3.io.uop.ctrl.is_load
connect issue_slots[3].uop.ctrl.csr_cmd, slots_3.io.uop.ctrl.csr_cmd
connect issue_slots[3].uop.ctrl.fcn_dw, slots_3.io.uop.ctrl.fcn_dw
connect issue_slots[3].uop.ctrl.op_fcn, slots_3.io.uop.ctrl.op_fcn
connect issue_slots[3].uop.ctrl.imm_sel, slots_3.io.uop.ctrl.imm_sel
connect issue_slots[3].uop.ctrl.op2_sel, slots_3.io.uop.ctrl.op2_sel
connect issue_slots[3].uop.ctrl.op1_sel, slots_3.io.uop.ctrl.op1_sel
connect issue_slots[3].uop.ctrl.br_type, slots_3.io.uop.ctrl.br_type
connect issue_slots[3].uop.fu_code, slots_3.io.uop.fu_code
connect issue_slots[3].uop.iq_type, slots_3.io.uop.iq_type
connect issue_slots[3].uop.debug_pc, slots_3.io.uop.debug_pc
connect issue_slots[3].uop.is_rvc, slots_3.io.uop.is_rvc
connect issue_slots[3].uop.debug_inst, slots_3.io.uop.debug_inst
connect issue_slots[3].uop.inst, slots_3.io.uop.inst
connect issue_slots[3].uop.uopc, slots_3.io.uop.uopc
connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc
connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc
connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if
connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if
connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if
connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if
connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if
connect issue_slots[3].out_uop.fp_single, slots_3.io.out_uop.fp_single
connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val
connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en
connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype
connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype
connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype
connect issue_slots[3].out_uop.ldst_val, slots_3.io.out_uop.ldst_val
connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3
connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2
connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1
connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst
connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1
connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit
connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique
connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc
connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq
connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq
connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo
connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei
connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence
connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed
connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size
connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd
connect issue_slots[3].out_uop.bypassable, slots_3.io.out_uop.bypassable
connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause
connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception
connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst
connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy
connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy
connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy
connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy
connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred
connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3
connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2
connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1
connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst
connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx
connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx
connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx
connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx
connect issue_slots[3].out_uop.csr_addr, slots_3.io.out_uop.csr_addr
connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed
connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken
connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob
connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst
connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx
connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag
connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask
connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb
connect issue_slots[3].out_uop.is_jal, slots_3.io.out_uop.is_jal
connect issue_slots[3].out_uop.is_jalr, slots_3.io.out_uop.is_jalr
connect issue_slots[3].out_uop.is_br, slots_3.io.out_uop.is_br
connect issue_slots[3].out_uop.iw_p2_poisoned, slots_3.io.out_uop.iw_p2_poisoned
connect issue_slots[3].out_uop.iw_p1_poisoned, slots_3.io.out_uop.iw_p1_poisoned
connect issue_slots[3].out_uop.iw_state, slots_3.io.out_uop.iw_state
connect issue_slots[3].out_uop.ctrl.is_std, slots_3.io.out_uop.ctrl.is_std
connect issue_slots[3].out_uop.ctrl.is_sta, slots_3.io.out_uop.ctrl.is_sta
connect issue_slots[3].out_uop.ctrl.is_load, slots_3.io.out_uop.ctrl.is_load
connect issue_slots[3].out_uop.ctrl.csr_cmd, slots_3.io.out_uop.ctrl.csr_cmd
connect issue_slots[3].out_uop.ctrl.fcn_dw, slots_3.io.out_uop.ctrl.fcn_dw
connect issue_slots[3].out_uop.ctrl.op_fcn, slots_3.io.out_uop.ctrl.op_fcn
connect issue_slots[3].out_uop.ctrl.imm_sel, slots_3.io.out_uop.ctrl.imm_sel
connect issue_slots[3].out_uop.ctrl.op2_sel, slots_3.io.out_uop.ctrl.op2_sel
connect issue_slots[3].out_uop.ctrl.op1_sel, slots_3.io.out_uop.ctrl.op1_sel
connect issue_slots[3].out_uop.ctrl.br_type, slots_3.io.out_uop.ctrl.br_type
connect issue_slots[3].out_uop.fu_code, slots_3.io.out_uop.fu_code
connect issue_slots[3].out_uop.iq_type, slots_3.io.out_uop.iq_type
connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc
connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc
connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst
connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst
connect issue_slots[3].out_uop.uopc, slots_3.io.out_uop.uopc
connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc
connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc
connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if
connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if
connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if
connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if
connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if
connect slots_3.io.in_uop.bits.fp_single, issue_slots[3].in_uop.bits.fp_single
connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val
connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en
connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype
connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype
connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype
connect slots_3.io.in_uop.bits.ldst_val, issue_slots[3].in_uop.bits.ldst_val
connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3
connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2
connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1
connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst
connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1
connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit
connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique
connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc
connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq
connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq
connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo
connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei
connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence
connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed
connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size
connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd
connect slots_3.io.in_uop.bits.bypassable, issue_slots[3].in_uop.bits.bypassable
connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause
connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception
connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst
connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy
connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy
connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy
connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy
connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred
connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3
connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2
connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1
connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst
connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx
connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx
connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx
connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx
connect slots_3.io.in_uop.bits.csr_addr, issue_slots[3].in_uop.bits.csr_addr
connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed
connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken
connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob
connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst
connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx
connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag
connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask
connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb
connect slots_3.io.in_uop.bits.is_jal, issue_slots[3].in_uop.bits.is_jal
connect slots_3.io.in_uop.bits.is_jalr, issue_slots[3].in_uop.bits.is_jalr
connect slots_3.io.in_uop.bits.is_br, issue_slots[3].in_uop.bits.is_br
connect slots_3.io.in_uop.bits.iw_p2_poisoned, issue_slots[3].in_uop.bits.iw_p2_poisoned
connect slots_3.io.in_uop.bits.iw_p1_poisoned, issue_slots[3].in_uop.bits.iw_p1_poisoned
connect slots_3.io.in_uop.bits.iw_state, issue_slots[3].in_uop.bits.iw_state
connect slots_3.io.in_uop.bits.ctrl.is_std, issue_slots[3].in_uop.bits.ctrl.is_std
connect slots_3.io.in_uop.bits.ctrl.is_sta, issue_slots[3].in_uop.bits.ctrl.is_sta
connect slots_3.io.in_uop.bits.ctrl.is_load, issue_slots[3].in_uop.bits.ctrl.is_load
connect slots_3.io.in_uop.bits.ctrl.csr_cmd, issue_slots[3].in_uop.bits.ctrl.csr_cmd
connect slots_3.io.in_uop.bits.ctrl.fcn_dw, issue_slots[3].in_uop.bits.ctrl.fcn_dw
connect slots_3.io.in_uop.bits.ctrl.op_fcn, issue_slots[3].in_uop.bits.ctrl.op_fcn
connect slots_3.io.in_uop.bits.ctrl.imm_sel, issue_slots[3].in_uop.bits.ctrl.imm_sel
connect slots_3.io.in_uop.bits.ctrl.op2_sel, issue_slots[3].in_uop.bits.ctrl.op2_sel
connect slots_3.io.in_uop.bits.ctrl.op1_sel, issue_slots[3].in_uop.bits.ctrl.op1_sel
connect slots_3.io.in_uop.bits.ctrl.br_type, issue_slots[3].in_uop.bits.ctrl.br_type
connect slots_3.io.in_uop.bits.fu_code, issue_slots[3].in_uop.bits.fu_code
connect slots_3.io.in_uop.bits.iq_type, issue_slots[3].in_uop.bits.iq_type
connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc
connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc
connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst
connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst
connect slots_3.io.in_uop.bits.uopc, issue_slots[3].in_uop.bits.uopc
connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid
connect slots_3.io.spec_ld_wakeup[0].bits, issue_slots[3].spec_ld_wakeup[0].bits
connect slots_3.io.spec_ld_wakeup[0].valid, issue_slots[3].spec_ld_wakeup[0].valid
connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits
connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid
connect slots_3.io.wakeup_ports[0].bits.poisoned, issue_slots[3].wakeup_ports[0].bits.poisoned
connect slots_3.io.wakeup_ports[0].bits.pdst, issue_slots[3].wakeup_ports[0].bits.pdst
connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid
connect slots_3.io.wakeup_ports[1].bits.poisoned, issue_slots[3].wakeup_ports[1].bits.poisoned
connect slots_3.io.wakeup_ports[1].bits.pdst, issue_slots[3].wakeup_ports[1].bits.pdst
connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid
connect slots_3.io.ldspec_miss, issue_slots[3].ldspec_miss
connect slots_3.io.clear, issue_slots[3].clear
connect slots_3.io.kill, issue_slots[3].kill
connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset
connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target
connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel
connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type
connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken
connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict
connect slots_3.io.brupdate.b2.valid, issue_slots[3].brupdate.b2.valid
connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc
connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc
connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if
connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if
connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if
connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if
connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if
connect slots_3.io.brupdate.b2.uop.fp_single, issue_slots[3].brupdate.b2.uop.fp_single
connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val
connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en
connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype
connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype
connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype
connect slots_3.io.brupdate.b2.uop.ldst_val, issue_slots[3].brupdate.b2.uop.ldst_val
connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3
connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2
connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1
connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst
connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1
connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit
connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique
connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc
connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq
connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq
connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo
connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei
connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence
connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed
connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size
connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd
connect slots_3.io.brupdate.b2.uop.bypassable, issue_slots[3].brupdate.b2.uop.bypassable
connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause
connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception
connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst
connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy
connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy
connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy
connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy
connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred
connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3
connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2
connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1
connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst
connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx
connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx
connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx
connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx
connect slots_3.io.brupdate.b2.uop.csr_addr, issue_slots[3].brupdate.b2.uop.csr_addr
connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed
connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken
connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob
connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst
connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx
connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag
connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask
connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb
connect slots_3.io.brupdate.b2.uop.is_jal, issue_slots[3].brupdate.b2.uop.is_jal
connect slots_3.io.brupdate.b2.uop.is_jalr, issue_slots[3].brupdate.b2.uop.is_jalr
connect slots_3.io.brupdate.b2.uop.is_br, issue_slots[3].brupdate.b2.uop.is_br
connect slots_3.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[3].brupdate.b2.uop.iw_p2_poisoned
connect slots_3.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[3].brupdate.b2.uop.iw_p1_poisoned
connect slots_3.io.brupdate.b2.uop.iw_state, issue_slots[3].brupdate.b2.uop.iw_state
connect slots_3.io.brupdate.b2.uop.ctrl.is_std, issue_slots[3].brupdate.b2.uop.ctrl.is_std
connect slots_3.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[3].brupdate.b2.uop.ctrl.is_sta
connect slots_3.io.brupdate.b2.uop.ctrl.is_load, issue_slots[3].brupdate.b2.uop.ctrl.is_load
connect slots_3.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd
connect slots_3.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw
connect slots_3.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[3].brupdate.b2.uop.ctrl.op_fcn
connect slots_3.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[3].brupdate.b2.uop.ctrl.imm_sel
connect slots_3.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[3].brupdate.b2.uop.ctrl.op2_sel
connect slots_3.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[3].brupdate.b2.uop.ctrl.op1_sel
connect slots_3.io.brupdate.b2.uop.ctrl.br_type, issue_slots[3].brupdate.b2.uop.ctrl.br_type
connect slots_3.io.brupdate.b2.uop.fu_code, issue_slots[3].brupdate.b2.uop.fu_code
connect slots_3.io.brupdate.b2.uop.iq_type, issue_slots[3].brupdate.b2.uop.iq_type
connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc
connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc
connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst
connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst
connect slots_3.io.brupdate.b2.uop.uopc, issue_slots[3].brupdate.b2.uop.uopc
connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask
connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask
connect slots_3.io.grant, issue_slots[3].grant
connect issue_slots[3].request_hp, slots_3.io.request_hp
connect issue_slots[3].request, slots_3.io.request
connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid
connect issue_slots[3].valid, slots_3.io.valid
connect issue_slots[4].debug.state, slots_4.io.debug.state
connect issue_slots[4].debug.ppred, slots_4.io.debug.ppred
connect issue_slots[4].debug.p3, slots_4.io.debug.p3
connect issue_slots[4].debug.p2, slots_4.io.debug.p2
connect issue_slots[4].debug.p1, slots_4.io.debug.p1
connect issue_slots[4].uop.debug_tsrc, slots_4.io.uop.debug_tsrc
connect issue_slots[4].uop.debug_fsrc, slots_4.io.uop.debug_fsrc
connect issue_slots[4].uop.bp_xcpt_if, slots_4.io.uop.bp_xcpt_if
connect issue_slots[4].uop.bp_debug_if, slots_4.io.uop.bp_debug_if
connect issue_slots[4].uop.xcpt_ma_if, slots_4.io.uop.xcpt_ma_if
connect issue_slots[4].uop.xcpt_ae_if, slots_4.io.uop.xcpt_ae_if
connect issue_slots[4].uop.xcpt_pf_if, slots_4.io.uop.xcpt_pf_if
connect issue_slots[4].uop.fp_single, slots_4.io.uop.fp_single
connect issue_slots[4].uop.fp_val, slots_4.io.uop.fp_val
connect issue_slots[4].uop.frs3_en, slots_4.io.uop.frs3_en
connect issue_slots[4].uop.lrs2_rtype, slots_4.io.uop.lrs2_rtype
connect issue_slots[4].uop.lrs1_rtype, slots_4.io.uop.lrs1_rtype
connect issue_slots[4].uop.dst_rtype, slots_4.io.uop.dst_rtype
connect issue_slots[4].uop.ldst_val, slots_4.io.uop.ldst_val
connect issue_slots[4].uop.lrs3, slots_4.io.uop.lrs3
connect issue_slots[4].uop.lrs2, slots_4.io.uop.lrs2
connect issue_slots[4].uop.lrs1, slots_4.io.uop.lrs1
connect issue_slots[4].uop.ldst, slots_4.io.uop.ldst
connect issue_slots[4].uop.ldst_is_rs1, slots_4.io.uop.ldst_is_rs1
connect issue_slots[4].uop.flush_on_commit, slots_4.io.uop.flush_on_commit
connect issue_slots[4].uop.is_unique, slots_4.io.uop.is_unique
connect issue_slots[4].uop.is_sys_pc2epc, slots_4.io.uop.is_sys_pc2epc
connect issue_slots[4].uop.uses_stq, slots_4.io.uop.uses_stq
connect issue_slots[4].uop.uses_ldq, slots_4.io.uop.uses_ldq
connect issue_slots[4].uop.is_amo, slots_4.io.uop.is_amo
connect issue_slots[4].uop.is_fencei, slots_4.io.uop.is_fencei
connect issue_slots[4].uop.is_fence, slots_4.io.uop.is_fence
connect issue_slots[4].uop.mem_signed, slots_4.io.uop.mem_signed
connect issue_slots[4].uop.mem_size, slots_4.io.uop.mem_size
connect issue_slots[4].uop.mem_cmd, slots_4.io.uop.mem_cmd
connect issue_slots[4].uop.bypassable, slots_4.io.uop.bypassable
connect issue_slots[4].uop.exc_cause, slots_4.io.uop.exc_cause
connect issue_slots[4].uop.exception, slots_4.io.uop.exception
connect issue_slots[4].uop.stale_pdst, slots_4.io.uop.stale_pdst
connect issue_slots[4].uop.ppred_busy, slots_4.io.uop.ppred_busy
connect issue_slots[4].uop.prs3_busy, slots_4.io.uop.prs3_busy
connect issue_slots[4].uop.prs2_busy, slots_4.io.uop.prs2_busy
connect issue_slots[4].uop.prs1_busy, slots_4.io.uop.prs1_busy
connect issue_slots[4].uop.ppred, slots_4.io.uop.ppred
connect issue_slots[4].uop.prs3, slots_4.io.uop.prs3
connect issue_slots[4].uop.prs2, slots_4.io.uop.prs2
connect issue_slots[4].uop.prs1, slots_4.io.uop.prs1
connect issue_slots[4].uop.pdst, slots_4.io.uop.pdst
connect issue_slots[4].uop.rxq_idx, slots_4.io.uop.rxq_idx
connect issue_slots[4].uop.stq_idx, slots_4.io.uop.stq_idx
connect issue_slots[4].uop.ldq_idx, slots_4.io.uop.ldq_idx
connect issue_slots[4].uop.rob_idx, slots_4.io.uop.rob_idx
connect issue_slots[4].uop.csr_addr, slots_4.io.uop.csr_addr
connect issue_slots[4].uop.imm_packed, slots_4.io.uop.imm_packed
connect issue_slots[4].uop.taken, slots_4.io.uop.taken
connect issue_slots[4].uop.pc_lob, slots_4.io.uop.pc_lob
connect issue_slots[4].uop.edge_inst, slots_4.io.uop.edge_inst
connect issue_slots[4].uop.ftq_idx, slots_4.io.uop.ftq_idx
connect issue_slots[4].uop.br_tag, slots_4.io.uop.br_tag
connect issue_slots[4].uop.br_mask, slots_4.io.uop.br_mask
connect issue_slots[4].uop.is_sfb, slots_4.io.uop.is_sfb
connect issue_slots[4].uop.is_jal, slots_4.io.uop.is_jal
connect issue_slots[4].uop.is_jalr, slots_4.io.uop.is_jalr
connect issue_slots[4].uop.is_br, slots_4.io.uop.is_br
connect issue_slots[4].uop.iw_p2_poisoned, slots_4.io.uop.iw_p2_poisoned
connect issue_slots[4].uop.iw_p1_poisoned, slots_4.io.uop.iw_p1_poisoned
connect issue_slots[4].uop.iw_state, slots_4.io.uop.iw_state
connect issue_slots[4].uop.ctrl.is_std, slots_4.io.uop.ctrl.is_std
connect issue_slots[4].uop.ctrl.is_sta, slots_4.io.uop.ctrl.is_sta
connect issue_slots[4].uop.ctrl.is_load, slots_4.io.uop.ctrl.is_load
connect issue_slots[4].uop.ctrl.csr_cmd, slots_4.io.uop.ctrl.csr_cmd
connect issue_slots[4].uop.ctrl.fcn_dw, slots_4.io.uop.ctrl.fcn_dw
connect issue_slots[4].uop.ctrl.op_fcn, slots_4.io.uop.ctrl.op_fcn
connect issue_slots[4].uop.ctrl.imm_sel, slots_4.io.uop.ctrl.imm_sel
connect issue_slots[4].uop.ctrl.op2_sel, slots_4.io.uop.ctrl.op2_sel
connect issue_slots[4].uop.ctrl.op1_sel, slots_4.io.uop.ctrl.op1_sel
connect issue_slots[4].uop.ctrl.br_type, slots_4.io.uop.ctrl.br_type
connect issue_slots[4].uop.fu_code, slots_4.io.uop.fu_code
connect issue_slots[4].uop.iq_type, slots_4.io.uop.iq_type
connect issue_slots[4].uop.debug_pc, slots_4.io.uop.debug_pc
connect issue_slots[4].uop.is_rvc, slots_4.io.uop.is_rvc
connect issue_slots[4].uop.debug_inst, slots_4.io.uop.debug_inst
connect issue_slots[4].uop.inst, slots_4.io.uop.inst
connect issue_slots[4].uop.uopc, slots_4.io.uop.uopc
connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc
connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc
connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if
connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if
connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if
connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if
connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if
connect issue_slots[4].out_uop.fp_single, slots_4.io.out_uop.fp_single
connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val
connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en
connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype
connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype
connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype
connect issue_slots[4].out_uop.ldst_val, slots_4.io.out_uop.ldst_val
connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3
connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2
connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1
connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst
connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1
connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit
connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique
connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc
connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq
connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq
connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo
connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei
connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence
connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed
connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size
connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd
connect issue_slots[4].out_uop.bypassable, slots_4.io.out_uop.bypassable
connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause
connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception
connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst
connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy
connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy
connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy
connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy
connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred
connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3
connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2
connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1
connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst
connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx
connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx
connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx
connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx
connect issue_slots[4].out_uop.csr_addr, slots_4.io.out_uop.csr_addr
connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed
connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken
connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob
connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst
connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx
connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag
connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask
connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb
connect issue_slots[4].out_uop.is_jal, slots_4.io.out_uop.is_jal
connect issue_slots[4].out_uop.is_jalr, slots_4.io.out_uop.is_jalr
connect issue_slots[4].out_uop.is_br, slots_4.io.out_uop.is_br
connect issue_slots[4].out_uop.iw_p2_poisoned, slots_4.io.out_uop.iw_p2_poisoned
connect issue_slots[4].out_uop.iw_p1_poisoned, slots_4.io.out_uop.iw_p1_poisoned
connect issue_slots[4].out_uop.iw_state, slots_4.io.out_uop.iw_state
connect issue_slots[4].out_uop.ctrl.is_std, slots_4.io.out_uop.ctrl.is_std
connect issue_slots[4].out_uop.ctrl.is_sta, slots_4.io.out_uop.ctrl.is_sta
connect issue_slots[4].out_uop.ctrl.is_load, slots_4.io.out_uop.ctrl.is_load
connect issue_slots[4].out_uop.ctrl.csr_cmd, slots_4.io.out_uop.ctrl.csr_cmd
connect issue_slots[4].out_uop.ctrl.fcn_dw, slots_4.io.out_uop.ctrl.fcn_dw
connect issue_slots[4].out_uop.ctrl.op_fcn, slots_4.io.out_uop.ctrl.op_fcn
connect issue_slots[4].out_uop.ctrl.imm_sel, slots_4.io.out_uop.ctrl.imm_sel
connect issue_slots[4].out_uop.ctrl.op2_sel, slots_4.io.out_uop.ctrl.op2_sel
connect issue_slots[4].out_uop.ctrl.op1_sel, slots_4.io.out_uop.ctrl.op1_sel
connect issue_slots[4].out_uop.ctrl.br_type, slots_4.io.out_uop.ctrl.br_type
connect issue_slots[4].out_uop.fu_code, slots_4.io.out_uop.fu_code
connect issue_slots[4].out_uop.iq_type, slots_4.io.out_uop.iq_type
connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc
connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc
connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst
connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst
connect issue_slots[4].out_uop.uopc, slots_4.io.out_uop.uopc
connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc
connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc
connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if
connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if
connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if
connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if
connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if
connect slots_4.io.in_uop.bits.fp_single, issue_slots[4].in_uop.bits.fp_single
connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val
connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en
connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype
connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype
connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype
connect slots_4.io.in_uop.bits.ldst_val, issue_slots[4].in_uop.bits.ldst_val
connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3
connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2
connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1
connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst
connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1
connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit
connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique
connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc
connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq
connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq
connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo
connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei
connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence
connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed
connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size
connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd
connect slots_4.io.in_uop.bits.bypassable, issue_slots[4].in_uop.bits.bypassable
connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause
connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception
connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst
connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy
connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy
connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy
connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy
connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred
connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3
connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2
connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1
connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst
connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx
connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx
connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx
connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx
connect slots_4.io.in_uop.bits.csr_addr, issue_slots[4].in_uop.bits.csr_addr
connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed
connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken
connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob
connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst
connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx
connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag
connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask
connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb
connect slots_4.io.in_uop.bits.is_jal, issue_slots[4].in_uop.bits.is_jal
connect slots_4.io.in_uop.bits.is_jalr, issue_slots[4].in_uop.bits.is_jalr
connect slots_4.io.in_uop.bits.is_br, issue_slots[4].in_uop.bits.is_br
connect slots_4.io.in_uop.bits.iw_p2_poisoned, issue_slots[4].in_uop.bits.iw_p2_poisoned
connect slots_4.io.in_uop.bits.iw_p1_poisoned, issue_slots[4].in_uop.bits.iw_p1_poisoned
connect slots_4.io.in_uop.bits.iw_state, issue_slots[4].in_uop.bits.iw_state
connect slots_4.io.in_uop.bits.ctrl.is_std, issue_slots[4].in_uop.bits.ctrl.is_std
connect slots_4.io.in_uop.bits.ctrl.is_sta, issue_slots[4].in_uop.bits.ctrl.is_sta
connect slots_4.io.in_uop.bits.ctrl.is_load, issue_slots[4].in_uop.bits.ctrl.is_load
connect slots_4.io.in_uop.bits.ctrl.csr_cmd, issue_slots[4].in_uop.bits.ctrl.csr_cmd
connect slots_4.io.in_uop.bits.ctrl.fcn_dw, issue_slots[4].in_uop.bits.ctrl.fcn_dw
connect slots_4.io.in_uop.bits.ctrl.op_fcn, issue_slots[4].in_uop.bits.ctrl.op_fcn
connect slots_4.io.in_uop.bits.ctrl.imm_sel, issue_slots[4].in_uop.bits.ctrl.imm_sel
connect slots_4.io.in_uop.bits.ctrl.op2_sel, issue_slots[4].in_uop.bits.ctrl.op2_sel
connect slots_4.io.in_uop.bits.ctrl.op1_sel, issue_slots[4].in_uop.bits.ctrl.op1_sel
connect slots_4.io.in_uop.bits.ctrl.br_type, issue_slots[4].in_uop.bits.ctrl.br_type
connect slots_4.io.in_uop.bits.fu_code, issue_slots[4].in_uop.bits.fu_code
connect slots_4.io.in_uop.bits.iq_type, issue_slots[4].in_uop.bits.iq_type
connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc
connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc
connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst
connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst
connect slots_4.io.in_uop.bits.uopc, issue_slots[4].in_uop.bits.uopc
connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid
connect slots_4.io.spec_ld_wakeup[0].bits, issue_slots[4].spec_ld_wakeup[0].bits
connect slots_4.io.spec_ld_wakeup[0].valid, issue_slots[4].spec_ld_wakeup[0].valid
connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits
connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid
connect slots_4.io.wakeup_ports[0].bits.poisoned, issue_slots[4].wakeup_ports[0].bits.poisoned
connect slots_4.io.wakeup_ports[0].bits.pdst, issue_slots[4].wakeup_ports[0].bits.pdst
connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid
connect slots_4.io.wakeup_ports[1].bits.poisoned, issue_slots[4].wakeup_ports[1].bits.poisoned
connect slots_4.io.wakeup_ports[1].bits.pdst, issue_slots[4].wakeup_ports[1].bits.pdst
connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid
connect slots_4.io.ldspec_miss, issue_slots[4].ldspec_miss
connect slots_4.io.clear, issue_slots[4].clear
connect slots_4.io.kill, issue_slots[4].kill
connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset
connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target
connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel
connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type
connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken
connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict
connect slots_4.io.brupdate.b2.valid, issue_slots[4].brupdate.b2.valid
connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc
connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc
connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if
connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if
connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if
connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if
connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if
connect slots_4.io.brupdate.b2.uop.fp_single, issue_slots[4].brupdate.b2.uop.fp_single
connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val
connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en
connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype
connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype
connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype
connect slots_4.io.brupdate.b2.uop.ldst_val, issue_slots[4].brupdate.b2.uop.ldst_val
connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3
connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2
connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1
connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst
connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1
connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit
connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique
connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc
connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq
connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq
connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo
connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei
connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence
connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed
connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size
connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd
connect slots_4.io.brupdate.b2.uop.bypassable, issue_slots[4].brupdate.b2.uop.bypassable
connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause
connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception
connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst
connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy
connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy
connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy
connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy
connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred
connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3
connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2
connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1
connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst
connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx
connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx
connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx
connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx
connect slots_4.io.brupdate.b2.uop.csr_addr, issue_slots[4].brupdate.b2.uop.csr_addr
connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed
connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken
connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob
connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst
connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx
connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag
connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask
connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb
connect slots_4.io.brupdate.b2.uop.is_jal, issue_slots[4].brupdate.b2.uop.is_jal
connect slots_4.io.brupdate.b2.uop.is_jalr, issue_slots[4].brupdate.b2.uop.is_jalr
connect slots_4.io.brupdate.b2.uop.is_br, issue_slots[4].brupdate.b2.uop.is_br
connect slots_4.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[4].brupdate.b2.uop.iw_p2_poisoned
connect slots_4.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[4].brupdate.b2.uop.iw_p1_poisoned
connect slots_4.io.brupdate.b2.uop.iw_state, issue_slots[4].brupdate.b2.uop.iw_state
connect slots_4.io.brupdate.b2.uop.ctrl.is_std, issue_slots[4].brupdate.b2.uop.ctrl.is_std
connect slots_4.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[4].brupdate.b2.uop.ctrl.is_sta
connect slots_4.io.brupdate.b2.uop.ctrl.is_load, issue_slots[4].brupdate.b2.uop.ctrl.is_load
connect slots_4.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd
connect slots_4.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw
connect slots_4.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[4].brupdate.b2.uop.ctrl.op_fcn
connect slots_4.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[4].brupdate.b2.uop.ctrl.imm_sel
connect slots_4.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[4].brupdate.b2.uop.ctrl.op2_sel
connect slots_4.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[4].brupdate.b2.uop.ctrl.op1_sel
connect slots_4.io.brupdate.b2.uop.ctrl.br_type, issue_slots[4].brupdate.b2.uop.ctrl.br_type
connect slots_4.io.brupdate.b2.uop.fu_code, issue_slots[4].brupdate.b2.uop.fu_code
connect slots_4.io.brupdate.b2.uop.iq_type, issue_slots[4].brupdate.b2.uop.iq_type
connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc
connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc
connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst
connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst
connect slots_4.io.brupdate.b2.uop.uopc, issue_slots[4].brupdate.b2.uop.uopc
connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask
connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask
connect slots_4.io.grant, issue_slots[4].grant
connect issue_slots[4].request_hp, slots_4.io.request_hp
connect issue_slots[4].request, slots_4.io.request
connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid
connect issue_slots[4].valid, slots_4.io.valid
connect issue_slots[5].debug.state, slots_5.io.debug.state
connect issue_slots[5].debug.ppred, slots_5.io.debug.ppred
connect issue_slots[5].debug.p3, slots_5.io.debug.p3
connect issue_slots[5].debug.p2, slots_5.io.debug.p2
connect issue_slots[5].debug.p1, slots_5.io.debug.p1
connect issue_slots[5].uop.debug_tsrc, slots_5.io.uop.debug_tsrc
connect issue_slots[5].uop.debug_fsrc, slots_5.io.uop.debug_fsrc
connect issue_slots[5].uop.bp_xcpt_if, slots_5.io.uop.bp_xcpt_if
connect issue_slots[5].uop.bp_debug_if, slots_5.io.uop.bp_debug_if
connect issue_slots[5].uop.xcpt_ma_if, slots_5.io.uop.xcpt_ma_if
connect issue_slots[5].uop.xcpt_ae_if, slots_5.io.uop.xcpt_ae_if
connect issue_slots[5].uop.xcpt_pf_if, slots_5.io.uop.xcpt_pf_if
connect issue_slots[5].uop.fp_single, slots_5.io.uop.fp_single
connect issue_slots[5].uop.fp_val, slots_5.io.uop.fp_val
connect issue_slots[5].uop.frs3_en, slots_5.io.uop.frs3_en
connect issue_slots[5].uop.lrs2_rtype, slots_5.io.uop.lrs2_rtype
connect issue_slots[5].uop.lrs1_rtype, slots_5.io.uop.lrs1_rtype
connect issue_slots[5].uop.dst_rtype, slots_5.io.uop.dst_rtype
connect issue_slots[5].uop.ldst_val, slots_5.io.uop.ldst_val
connect issue_slots[5].uop.lrs3, slots_5.io.uop.lrs3
connect issue_slots[5].uop.lrs2, slots_5.io.uop.lrs2
connect issue_slots[5].uop.lrs1, slots_5.io.uop.lrs1
connect issue_slots[5].uop.ldst, slots_5.io.uop.ldst
connect issue_slots[5].uop.ldst_is_rs1, slots_5.io.uop.ldst_is_rs1
connect issue_slots[5].uop.flush_on_commit, slots_5.io.uop.flush_on_commit
connect issue_slots[5].uop.is_unique, slots_5.io.uop.is_unique
connect issue_slots[5].uop.is_sys_pc2epc, slots_5.io.uop.is_sys_pc2epc
connect issue_slots[5].uop.uses_stq, slots_5.io.uop.uses_stq
connect issue_slots[5].uop.uses_ldq, slots_5.io.uop.uses_ldq
connect issue_slots[5].uop.is_amo, slots_5.io.uop.is_amo
connect issue_slots[5].uop.is_fencei, slots_5.io.uop.is_fencei
connect issue_slots[5].uop.is_fence, slots_5.io.uop.is_fence
connect issue_slots[5].uop.mem_signed, slots_5.io.uop.mem_signed
connect issue_slots[5].uop.mem_size, slots_5.io.uop.mem_size
connect issue_slots[5].uop.mem_cmd, slots_5.io.uop.mem_cmd
connect issue_slots[5].uop.bypassable, slots_5.io.uop.bypassable
connect issue_slots[5].uop.exc_cause, slots_5.io.uop.exc_cause
connect issue_slots[5].uop.exception, slots_5.io.uop.exception
connect issue_slots[5].uop.stale_pdst, slots_5.io.uop.stale_pdst
connect issue_slots[5].uop.ppred_busy, slots_5.io.uop.ppred_busy
connect issue_slots[5].uop.prs3_busy, slots_5.io.uop.prs3_busy
connect issue_slots[5].uop.prs2_busy, slots_5.io.uop.prs2_busy
connect issue_slots[5].uop.prs1_busy, slots_5.io.uop.prs1_busy
connect issue_slots[5].uop.ppred, slots_5.io.uop.ppred
connect issue_slots[5].uop.prs3, slots_5.io.uop.prs3
connect issue_slots[5].uop.prs2, slots_5.io.uop.prs2
connect issue_slots[5].uop.prs1, slots_5.io.uop.prs1
connect issue_slots[5].uop.pdst, slots_5.io.uop.pdst
connect issue_slots[5].uop.rxq_idx, slots_5.io.uop.rxq_idx
connect issue_slots[5].uop.stq_idx, slots_5.io.uop.stq_idx
connect issue_slots[5].uop.ldq_idx, slots_5.io.uop.ldq_idx
connect issue_slots[5].uop.rob_idx, slots_5.io.uop.rob_idx
connect issue_slots[5].uop.csr_addr, slots_5.io.uop.csr_addr
connect issue_slots[5].uop.imm_packed, slots_5.io.uop.imm_packed
connect issue_slots[5].uop.taken, slots_5.io.uop.taken
connect issue_slots[5].uop.pc_lob, slots_5.io.uop.pc_lob
connect issue_slots[5].uop.edge_inst, slots_5.io.uop.edge_inst
connect issue_slots[5].uop.ftq_idx, slots_5.io.uop.ftq_idx
connect issue_slots[5].uop.br_tag, slots_5.io.uop.br_tag
connect issue_slots[5].uop.br_mask, slots_5.io.uop.br_mask
connect issue_slots[5].uop.is_sfb, slots_5.io.uop.is_sfb
connect issue_slots[5].uop.is_jal, slots_5.io.uop.is_jal
connect issue_slots[5].uop.is_jalr, slots_5.io.uop.is_jalr
connect issue_slots[5].uop.is_br, slots_5.io.uop.is_br
connect issue_slots[5].uop.iw_p2_poisoned, slots_5.io.uop.iw_p2_poisoned
connect issue_slots[5].uop.iw_p1_poisoned, slots_5.io.uop.iw_p1_poisoned
connect issue_slots[5].uop.iw_state, slots_5.io.uop.iw_state
connect issue_slots[5].uop.ctrl.is_std, slots_5.io.uop.ctrl.is_std
connect issue_slots[5].uop.ctrl.is_sta, slots_5.io.uop.ctrl.is_sta
connect issue_slots[5].uop.ctrl.is_load, slots_5.io.uop.ctrl.is_load
connect issue_slots[5].uop.ctrl.csr_cmd, slots_5.io.uop.ctrl.csr_cmd
connect issue_slots[5].uop.ctrl.fcn_dw, slots_5.io.uop.ctrl.fcn_dw
connect issue_slots[5].uop.ctrl.op_fcn, slots_5.io.uop.ctrl.op_fcn
connect issue_slots[5].uop.ctrl.imm_sel, slots_5.io.uop.ctrl.imm_sel
connect issue_slots[5].uop.ctrl.op2_sel, slots_5.io.uop.ctrl.op2_sel
connect issue_slots[5].uop.ctrl.op1_sel, slots_5.io.uop.ctrl.op1_sel
connect issue_slots[5].uop.ctrl.br_type, slots_5.io.uop.ctrl.br_type
connect issue_slots[5].uop.fu_code, slots_5.io.uop.fu_code
connect issue_slots[5].uop.iq_type, slots_5.io.uop.iq_type
connect issue_slots[5].uop.debug_pc, slots_5.io.uop.debug_pc
connect issue_slots[5].uop.is_rvc, slots_5.io.uop.is_rvc
connect issue_slots[5].uop.debug_inst, slots_5.io.uop.debug_inst
connect issue_slots[5].uop.inst, slots_5.io.uop.inst
connect issue_slots[5].uop.uopc, slots_5.io.uop.uopc
connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc
connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc
connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if
connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if
connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if
connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if
connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if
connect issue_slots[5].out_uop.fp_single, slots_5.io.out_uop.fp_single
connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val
connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en
connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype
connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype
connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype
connect issue_slots[5].out_uop.ldst_val, slots_5.io.out_uop.ldst_val
connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3
connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2
connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1
connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst
connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1
connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit
connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique
connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc
connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq
connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq
connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo
connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei
connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence
connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed
connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size
connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd
connect issue_slots[5].out_uop.bypassable, slots_5.io.out_uop.bypassable
connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause
connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception
connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst
connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy
connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy
connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy
connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy
connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred
connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3
connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2
connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1
connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst
connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx
connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx
connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx
connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx
connect issue_slots[5].out_uop.csr_addr, slots_5.io.out_uop.csr_addr
connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed
connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken
connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob
connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst
connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx
connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag
connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask
connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb
connect issue_slots[5].out_uop.is_jal, slots_5.io.out_uop.is_jal
connect issue_slots[5].out_uop.is_jalr, slots_5.io.out_uop.is_jalr
connect issue_slots[5].out_uop.is_br, slots_5.io.out_uop.is_br
connect issue_slots[5].out_uop.iw_p2_poisoned, slots_5.io.out_uop.iw_p2_poisoned
connect issue_slots[5].out_uop.iw_p1_poisoned, slots_5.io.out_uop.iw_p1_poisoned
connect issue_slots[5].out_uop.iw_state, slots_5.io.out_uop.iw_state
connect issue_slots[5].out_uop.ctrl.is_std, slots_5.io.out_uop.ctrl.is_std
connect issue_slots[5].out_uop.ctrl.is_sta, slots_5.io.out_uop.ctrl.is_sta
connect issue_slots[5].out_uop.ctrl.is_load, slots_5.io.out_uop.ctrl.is_load
connect issue_slots[5].out_uop.ctrl.csr_cmd, slots_5.io.out_uop.ctrl.csr_cmd
connect issue_slots[5].out_uop.ctrl.fcn_dw, slots_5.io.out_uop.ctrl.fcn_dw
connect issue_slots[5].out_uop.ctrl.op_fcn, slots_5.io.out_uop.ctrl.op_fcn
connect issue_slots[5].out_uop.ctrl.imm_sel, slots_5.io.out_uop.ctrl.imm_sel
connect issue_slots[5].out_uop.ctrl.op2_sel, slots_5.io.out_uop.ctrl.op2_sel
connect issue_slots[5].out_uop.ctrl.op1_sel, slots_5.io.out_uop.ctrl.op1_sel
connect issue_slots[5].out_uop.ctrl.br_type, slots_5.io.out_uop.ctrl.br_type
connect issue_slots[5].out_uop.fu_code, slots_5.io.out_uop.fu_code
connect issue_slots[5].out_uop.iq_type, slots_5.io.out_uop.iq_type
connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc
connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc
connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst
connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst
connect issue_slots[5].out_uop.uopc, slots_5.io.out_uop.uopc
connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc
connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc
connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if
connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if
connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if
connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if
connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if
connect slots_5.io.in_uop.bits.fp_single, issue_slots[5].in_uop.bits.fp_single
connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val
connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en
connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype
connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype
connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype
connect slots_5.io.in_uop.bits.ldst_val, issue_slots[5].in_uop.bits.ldst_val
connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3
connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2
connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1
connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst
connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1
connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit
connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique
connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc
connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq
connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq
connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo
connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei
connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence
connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed
connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size
connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd
connect slots_5.io.in_uop.bits.bypassable, issue_slots[5].in_uop.bits.bypassable
connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause
connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception
connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst
connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy
connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy
connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy
connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy
connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred
connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3
connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2
connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1
connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst
connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx
connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx
connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx
connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx
connect slots_5.io.in_uop.bits.csr_addr, issue_slots[5].in_uop.bits.csr_addr
connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed
connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken
connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob
connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst
connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx
connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag
connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask
connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb
connect slots_5.io.in_uop.bits.is_jal, issue_slots[5].in_uop.bits.is_jal
connect slots_5.io.in_uop.bits.is_jalr, issue_slots[5].in_uop.bits.is_jalr
connect slots_5.io.in_uop.bits.is_br, issue_slots[5].in_uop.bits.is_br
connect slots_5.io.in_uop.bits.iw_p2_poisoned, issue_slots[5].in_uop.bits.iw_p2_poisoned
connect slots_5.io.in_uop.bits.iw_p1_poisoned, issue_slots[5].in_uop.bits.iw_p1_poisoned
connect slots_5.io.in_uop.bits.iw_state, issue_slots[5].in_uop.bits.iw_state
connect slots_5.io.in_uop.bits.ctrl.is_std, issue_slots[5].in_uop.bits.ctrl.is_std
connect slots_5.io.in_uop.bits.ctrl.is_sta, issue_slots[5].in_uop.bits.ctrl.is_sta
connect slots_5.io.in_uop.bits.ctrl.is_load, issue_slots[5].in_uop.bits.ctrl.is_load
connect slots_5.io.in_uop.bits.ctrl.csr_cmd, issue_slots[5].in_uop.bits.ctrl.csr_cmd
connect slots_5.io.in_uop.bits.ctrl.fcn_dw, issue_slots[5].in_uop.bits.ctrl.fcn_dw
connect slots_5.io.in_uop.bits.ctrl.op_fcn, issue_slots[5].in_uop.bits.ctrl.op_fcn
connect slots_5.io.in_uop.bits.ctrl.imm_sel, issue_slots[5].in_uop.bits.ctrl.imm_sel
connect slots_5.io.in_uop.bits.ctrl.op2_sel, issue_slots[5].in_uop.bits.ctrl.op2_sel
connect slots_5.io.in_uop.bits.ctrl.op1_sel, issue_slots[5].in_uop.bits.ctrl.op1_sel
connect slots_5.io.in_uop.bits.ctrl.br_type, issue_slots[5].in_uop.bits.ctrl.br_type
connect slots_5.io.in_uop.bits.fu_code, issue_slots[5].in_uop.bits.fu_code
connect slots_5.io.in_uop.bits.iq_type, issue_slots[5].in_uop.bits.iq_type
connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc
connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc
connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst
connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst
connect slots_5.io.in_uop.bits.uopc, issue_slots[5].in_uop.bits.uopc
connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid
connect slots_5.io.spec_ld_wakeup[0].bits, issue_slots[5].spec_ld_wakeup[0].bits
connect slots_5.io.spec_ld_wakeup[0].valid, issue_slots[5].spec_ld_wakeup[0].valid
connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits
connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid
connect slots_5.io.wakeup_ports[0].bits.poisoned, issue_slots[5].wakeup_ports[0].bits.poisoned
connect slots_5.io.wakeup_ports[0].bits.pdst, issue_slots[5].wakeup_ports[0].bits.pdst
connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid
connect slots_5.io.wakeup_ports[1].bits.poisoned, issue_slots[5].wakeup_ports[1].bits.poisoned
connect slots_5.io.wakeup_ports[1].bits.pdst, issue_slots[5].wakeup_ports[1].bits.pdst
connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid
connect slots_5.io.ldspec_miss, issue_slots[5].ldspec_miss
connect slots_5.io.clear, issue_slots[5].clear
connect slots_5.io.kill, issue_slots[5].kill
connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset
connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target
connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel
connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type
connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken
connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict
connect slots_5.io.brupdate.b2.valid, issue_slots[5].brupdate.b2.valid
connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc
connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc
connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if
connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if
connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if
connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if
connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if
connect slots_5.io.brupdate.b2.uop.fp_single, issue_slots[5].brupdate.b2.uop.fp_single
connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val
connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en
connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype
connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype
connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype
connect slots_5.io.brupdate.b2.uop.ldst_val, issue_slots[5].brupdate.b2.uop.ldst_val
connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3
connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2
connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1
connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst
connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1
connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit
connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique
connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc
connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq
connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq
connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo
connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei
connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence
connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed
connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size
connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd
connect slots_5.io.brupdate.b2.uop.bypassable, issue_slots[5].brupdate.b2.uop.bypassable
connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause
connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception
connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst
connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy
connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy
connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy
connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy
connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred
connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3
connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2
connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1
connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst
connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx
connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx
connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx
connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx
connect slots_5.io.brupdate.b2.uop.csr_addr, issue_slots[5].brupdate.b2.uop.csr_addr
connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed
connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken
connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob
connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst
connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx
connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag
connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask
connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb
connect slots_5.io.brupdate.b2.uop.is_jal, issue_slots[5].brupdate.b2.uop.is_jal
connect slots_5.io.brupdate.b2.uop.is_jalr, issue_slots[5].brupdate.b2.uop.is_jalr
connect slots_5.io.brupdate.b2.uop.is_br, issue_slots[5].brupdate.b2.uop.is_br
connect slots_5.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[5].brupdate.b2.uop.iw_p2_poisoned
connect slots_5.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[5].brupdate.b2.uop.iw_p1_poisoned
connect slots_5.io.brupdate.b2.uop.iw_state, issue_slots[5].brupdate.b2.uop.iw_state
connect slots_5.io.brupdate.b2.uop.ctrl.is_std, issue_slots[5].brupdate.b2.uop.ctrl.is_std
connect slots_5.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[5].brupdate.b2.uop.ctrl.is_sta
connect slots_5.io.brupdate.b2.uop.ctrl.is_load, issue_slots[5].brupdate.b2.uop.ctrl.is_load
connect slots_5.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd
connect slots_5.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw
connect slots_5.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[5].brupdate.b2.uop.ctrl.op_fcn
connect slots_5.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[5].brupdate.b2.uop.ctrl.imm_sel
connect slots_5.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[5].brupdate.b2.uop.ctrl.op2_sel
connect slots_5.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[5].brupdate.b2.uop.ctrl.op1_sel
connect slots_5.io.brupdate.b2.uop.ctrl.br_type, issue_slots[5].brupdate.b2.uop.ctrl.br_type
connect slots_5.io.brupdate.b2.uop.fu_code, issue_slots[5].brupdate.b2.uop.fu_code
connect slots_5.io.brupdate.b2.uop.iq_type, issue_slots[5].brupdate.b2.uop.iq_type
connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc
connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc
connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst
connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst
connect slots_5.io.brupdate.b2.uop.uopc, issue_slots[5].brupdate.b2.uop.uopc
connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask
connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask
connect slots_5.io.grant, issue_slots[5].grant
connect issue_slots[5].request_hp, slots_5.io.request_hp
connect issue_slots[5].request, slots_5.io.request
connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid
connect issue_slots[5].valid, slots_5.io.valid
connect issue_slots[6].debug.state, slots_6.io.debug.state
connect issue_slots[6].debug.ppred, slots_6.io.debug.ppred
connect issue_slots[6].debug.p3, slots_6.io.debug.p3
connect issue_slots[6].debug.p2, slots_6.io.debug.p2
connect issue_slots[6].debug.p1, slots_6.io.debug.p1
connect issue_slots[6].uop.debug_tsrc, slots_6.io.uop.debug_tsrc
connect issue_slots[6].uop.debug_fsrc, slots_6.io.uop.debug_fsrc
connect issue_slots[6].uop.bp_xcpt_if, slots_6.io.uop.bp_xcpt_if
connect issue_slots[6].uop.bp_debug_if, slots_6.io.uop.bp_debug_if
connect issue_slots[6].uop.xcpt_ma_if, slots_6.io.uop.xcpt_ma_if
connect issue_slots[6].uop.xcpt_ae_if, slots_6.io.uop.xcpt_ae_if
connect issue_slots[6].uop.xcpt_pf_if, slots_6.io.uop.xcpt_pf_if
connect issue_slots[6].uop.fp_single, slots_6.io.uop.fp_single
connect issue_slots[6].uop.fp_val, slots_6.io.uop.fp_val
connect issue_slots[6].uop.frs3_en, slots_6.io.uop.frs3_en
connect issue_slots[6].uop.lrs2_rtype, slots_6.io.uop.lrs2_rtype
connect issue_slots[6].uop.lrs1_rtype, slots_6.io.uop.lrs1_rtype
connect issue_slots[6].uop.dst_rtype, slots_6.io.uop.dst_rtype
connect issue_slots[6].uop.ldst_val, slots_6.io.uop.ldst_val
connect issue_slots[6].uop.lrs3, slots_6.io.uop.lrs3
connect issue_slots[6].uop.lrs2, slots_6.io.uop.lrs2
connect issue_slots[6].uop.lrs1, slots_6.io.uop.lrs1
connect issue_slots[6].uop.ldst, slots_6.io.uop.ldst
connect issue_slots[6].uop.ldst_is_rs1, slots_6.io.uop.ldst_is_rs1
connect issue_slots[6].uop.flush_on_commit, slots_6.io.uop.flush_on_commit
connect issue_slots[6].uop.is_unique, slots_6.io.uop.is_unique
connect issue_slots[6].uop.is_sys_pc2epc, slots_6.io.uop.is_sys_pc2epc
connect issue_slots[6].uop.uses_stq, slots_6.io.uop.uses_stq
connect issue_slots[6].uop.uses_ldq, slots_6.io.uop.uses_ldq
connect issue_slots[6].uop.is_amo, slots_6.io.uop.is_amo
connect issue_slots[6].uop.is_fencei, slots_6.io.uop.is_fencei
connect issue_slots[6].uop.is_fence, slots_6.io.uop.is_fence
connect issue_slots[6].uop.mem_signed, slots_6.io.uop.mem_signed
connect issue_slots[6].uop.mem_size, slots_6.io.uop.mem_size
connect issue_slots[6].uop.mem_cmd, slots_6.io.uop.mem_cmd
connect issue_slots[6].uop.bypassable, slots_6.io.uop.bypassable
connect issue_slots[6].uop.exc_cause, slots_6.io.uop.exc_cause
connect issue_slots[6].uop.exception, slots_6.io.uop.exception
connect issue_slots[6].uop.stale_pdst, slots_6.io.uop.stale_pdst
connect issue_slots[6].uop.ppred_busy, slots_6.io.uop.ppred_busy
connect issue_slots[6].uop.prs3_busy, slots_6.io.uop.prs3_busy
connect issue_slots[6].uop.prs2_busy, slots_6.io.uop.prs2_busy
connect issue_slots[6].uop.prs1_busy, slots_6.io.uop.prs1_busy
connect issue_slots[6].uop.ppred, slots_6.io.uop.ppred
connect issue_slots[6].uop.prs3, slots_6.io.uop.prs3
connect issue_slots[6].uop.prs2, slots_6.io.uop.prs2
connect issue_slots[6].uop.prs1, slots_6.io.uop.prs1
connect issue_slots[6].uop.pdst, slots_6.io.uop.pdst
connect issue_slots[6].uop.rxq_idx, slots_6.io.uop.rxq_idx
connect issue_slots[6].uop.stq_idx, slots_6.io.uop.stq_idx
connect issue_slots[6].uop.ldq_idx, slots_6.io.uop.ldq_idx
connect issue_slots[6].uop.rob_idx, slots_6.io.uop.rob_idx
connect issue_slots[6].uop.csr_addr, slots_6.io.uop.csr_addr
connect issue_slots[6].uop.imm_packed, slots_6.io.uop.imm_packed
connect issue_slots[6].uop.taken, slots_6.io.uop.taken
connect issue_slots[6].uop.pc_lob, slots_6.io.uop.pc_lob
connect issue_slots[6].uop.edge_inst, slots_6.io.uop.edge_inst
connect issue_slots[6].uop.ftq_idx, slots_6.io.uop.ftq_idx
connect issue_slots[6].uop.br_tag, slots_6.io.uop.br_tag
connect issue_slots[6].uop.br_mask, slots_6.io.uop.br_mask
connect issue_slots[6].uop.is_sfb, slots_6.io.uop.is_sfb
connect issue_slots[6].uop.is_jal, slots_6.io.uop.is_jal
connect issue_slots[6].uop.is_jalr, slots_6.io.uop.is_jalr
connect issue_slots[6].uop.is_br, slots_6.io.uop.is_br
connect issue_slots[6].uop.iw_p2_poisoned, slots_6.io.uop.iw_p2_poisoned
connect issue_slots[6].uop.iw_p1_poisoned, slots_6.io.uop.iw_p1_poisoned
connect issue_slots[6].uop.iw_state, slots_6.io.uop.iw_state
connect issue_slots[6].uop.ctrl.is_std, slots_6.io.uop.ctrl.is_std
connect issue_slots[6].uop.ctrl.is_sta, slots_6.io.uop.ctrl.is_sta
connect issue_slots[6].uop.ctrl.is_load, slots_6.io.uop.ctrl.is_load
connect issue_slots[6].uop.ctrl.csr_cmd, slots_6.io.uop.ctrl.csr_cmd
connect issue_slots[6].uop.ctrl.fcn_dw, slots_6.io.uop.ctrl.fcn_dw
connect issue_slots[6].uop.ctrl.op_fcn, slots_6.io.uop.ctrl.op_fcn
connect issue_slots[6].uop.ctrl.imm_sel, slots_6.io.uop.ctrl.imm_sel
connect issue_slots[6].uop.ctrl.op2_sel, slots_6.io.uop.ctrl.op2_sel
connect issue_slots[6].uop.ctrl.op1_sel, slots_6.io.uop.ctrl.op1_sel
connect issue_slots[6].uop.ctrl.br_type, slots_6.io.uop.ctrl.br_type
connect issue_slots[6].uop.fu_code, slots_6.io.uop.fu_code
connect issue_slots[6].uop.iq_type, slots_6.io.uop.iq_type
connect issue_slots[6].uop.debug_pc, slots_6.io.uop.debug_pc
connect issue_slots[6].uop.is_rvc, slots_6.io.uop.is_rvc
connect issue_slots[6].uop.debug_inst, slots_6.io.uop.debug_inst
connect issue_slots[6].uop.inst, slots_6.io.uop.inst
connect issue_slots[6].uop.uopc, slots_6.io.uop.uopc
connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc
connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc
connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if
connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if
connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if
connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if
connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if
connect issue_slots[6].out_uop.fp_single, slots_6.io.out_uop.fp_single
connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val
connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en
connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype
connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype
connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype
connect issue_slots[6].out_uop.ldst_val, slots_6.io.out_uop.ldst_val
connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3
connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2
connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1
connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst
connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1
connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit
connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique
connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc
connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq
connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq
connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo
connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei
connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence
connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed
connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size
connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd
connect issue_slots[6].out_uop.bypassable, slots_6.io.out_uop.bypassable
connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause
connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception
connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst
connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy
connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy
connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy
connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy
connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred
connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3
connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2
connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1
connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst
connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx
connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx
connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx
connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx
connect issue_slots[6].out_uop.csr_addr, slots_6.io.out_uop.csr_addr
connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed
connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken
connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob
connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst
connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx
connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag
connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask
connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb
connect issue_slots[6].out_uop.is_jal, slots_6.io.out_uop.is_jal
connect issue_slots[6].out_uop.is_jalr, slots_6.io.out_uop.is_jalr
connect issue_slots[6].out_uop.is_br, slots_6.io.out_uop.is_br
connect issue_slots[6].out_uop.iw_p2_poisoned, slots_6.io.out_uop.iw_p2_poisoned
connect issue_slots[6].out_uop.iw_p1_poisoned, slots_6.io.out_uop.iw_p1_poisoned
connect issue_slots[6].out_uop.iw_state, slots_6.io.out_uop.iw_state
connect issue_slots[6].out_uop.ctrl.is_std, slots_6.io.out_uop.ctrl.is_std
connect issue_slots[6].out_uop.ctrl.is_sta, slots_6.io.out_uop.ctrl.is_sta
connect issue_slots[6].out_uop.ctrl.is_load, slots_6.io.out_uop.ctrl.is_load
connect issue_slots[6].out_uop.ctrl.csr_cmd, slots_6.io.out_uop.ctrl.csr_cmd
connect issue_slots[6].out_uop.ctrl.fcn_dw, slots_6.io.out_uop.ctrl.fcn_dw
connect issue_slots[6].out_uop.ctrl.op_fcn, slots_6.io.out_uop.ctrl.op_fcn
connect issue_slots[6].out_uop.ctrl.imm_sel, slots_6.io.out_uop.ctrl.imm_sel
connect issue_slots[6].out_uop.ctrl.op2_sel, slots_6.io.out_uop.ctrl.op2_sel
connect issue_slots[6].out_uop.ctrl.op1_sel, slots_6.io.out_uop.ctrl.op1_sel
connect issue_slots[6].out_uop.ctrl.br_type, slots_6.io.out_uop.ctrl.br_type
connect issue_slots[6].out_uop.fu_code, slots_6.io.out_uop.fu_code
connect issue_slots[6].out_uop.iq_type, slots_6.io.out_uop.iq_type
connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc
connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc
connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst
connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst
connect issue_slots[6].out_uop.uopc, slots_6.io.out_uop.uopc
connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc
connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc
connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if
connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if
connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if
connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if
connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if
connect slots_6.io.in_uop.bits.fp_single, issue_slots[6].in_uop.bits.fp_single
connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val
connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en
connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype
connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype
connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype
connect slots_6.io.in_uop.bits.ldst_val, issue_slots[6].in_uop.bits.ldst_val
connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3
connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2
connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1
connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst
connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1
connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit
connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique
connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc
connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq
connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq
connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo
connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei
connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence
connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed
connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size
connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd
connect slots_6.io.in_uop.bits.bypassable, issue_slots[6].in_uop.bits.bypassable
connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause
connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception
connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst
connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy
connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy
connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy
connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy
connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred
connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3
connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2
connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1
connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst
connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx
connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx
connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx
connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx
connect slots_6.io.in_uop.bits.csr_addr, issue_slots[6].in_uop.bits.csr_addr
connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed
connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken
connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob
connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst
connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx
connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag
connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask
connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb
connect slots_6.io.in_uop.bits.is_jal, issue_slots[6].in_uop.bits.is_jal
connect slots_6.io.in_uop.bits.is_jalr, issue_slots[6].in_uop.bits.is_jalr
connect slots_6.io.in_uop.bits.is_br, issue_slots[6].in_uop.bits.is_br
connect slots_6.io.in_uop.bits.iw_p2_poisoned, issue_slots[6].in_uop.bits.iw_p2_poisoned
connect slots_6.io.in_uop.bits.iw_p1_poisoned, issue_slots[6].in_uop.bits.iw_p1_poisoned
connect slots_6.io.in_uop.bits.iw_state, issue_slots[6].in_uop.bits.iw_state
connect slots_6.io.in_uop.bits.ctrl.is_std, issue_slots[6].in_uop.bits.ctrl.is_std
connect slots_6.io.in_uop.bits.ctrl.is_sta, issue_slots[6].in_uop.bits.ctrl.is_sta
connect slots_6.io.in_uop.bits.ctrl.is_load, issue_slots[6].in_uop.bits.ctrl.is_load
connect slots_6.io.in_uop.bits.ctrl.csr_cmd, issue_slots[6].in_uop.bits.ctrl.csr_cmd
connect slots_6.io.in_uop.bits.ctrl.fcn_dw, issue_slots[6].in_uop.bits.ctrl.fcn_dw
connect slots_6.io.in_uop.bits.ctrl.op_fcn, issue_slots[6].in_uop.bits.ctrl.op_fcn
connect slots_6.io.in_uop.bits.ctrl.imm_sel, issue_slots[6].in_uop.bits.ctrl.imm_sel
connect slots_6.io.in_uop.bits.ctrl.op2_sel, issue_slots[6].in_uop.bits.ctrl.op2_sel
connect slots_6.io.in_uop.bits.ctrl.op1_sel, issue_slots[6].in_uop.bits.ctrl.op1_sel
connect slots_6.io.in_uop.bits.ctrl.br_type, issue_slots[6].in_uop.bits.ctrl.br_type
connect slots_6.io.in_uop.bits.fu_code, issue_slots[6].in_uop.bits.fu_code
connect slots_6.io.in_uop.bits.iq_type, issue_slots[6].in_uop.bits.iq_type
connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc
connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc
connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst
connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst
connect slots_6.io.in_uop.bits.uopc, issue_slots[6].in_uop.bits.uopc
connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid
connect slots_6.io.spec_ld_wakeup[0].bits, issue_slots[6].spec_ld_wakeup[0].bits
connect slots_6.io.spec_ld_wakeup[0].valid, issue_slots[6].spec_ld_wakeup[0].valid
connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits
connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid
connect slots_6.io.wakeup_ports[0].bits.poisoned, issue_slots[6].wakeup_ports[0].bits.poisoned
connect slots_6.io.wakeup_ports[0].bits.pdst, issue_slots[6].wakeup_ports[0].bits.pdst
connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid
connect slots_6.io.wakeup_ports[1].bits.poisoned, issue_slots[6].wakeup_ports[1].bits.poisoned
connect slots_6.io.wakeup_ports[1].bits.pdst, issue_slots[6].wakeup_ports[1].bits.pdst
connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid
connect slots_6.io.ldspec_miss, issue_slots[6].ldspec_miss
connect slots_6.io.clear, issue_slots[6].clear
connect slots_6.io.kill, issue_slots[6].kill
connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset
connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target
connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel
connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type
connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken
connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict
connect slots_6.io.brupdate.b2.valid, issue_slots[6].brupdate.b2.valid
connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc
connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc
connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if
connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if
connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if
connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if
connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if
connect slots_6.io.brupdate.b2.uop.fp_single, issue_slots[6].brupdate.b2.uop.fp_single
connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val
connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en
connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype
connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype
connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype
connect slots_6.io.brupdate.b2.uop.ldst_val, issue_slots[6].brupdate.b2.uop.ldst_val
connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3
connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2
connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1
connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst
connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1
connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit
connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique
connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc
connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq
connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq
connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo
connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei
connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence
connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed
connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size
connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd
connect slots_6.io.brupdate.b2.uop.bypassable, issue_slots[6].brupdate.b2.uop.bypassable
connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause
connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception
connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst
connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy
connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy
connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy
connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy
connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred
connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3
connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2
connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1
connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst
connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx
connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx
connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx
connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx
connect slots_6.io.brupdate.b2.uop.csr_addr, issue_slots[6].brupdate.b2.uop.csr_addr
connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed
connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken
connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob
connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst
connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx
connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag
connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask
connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb
connect slots_6.io.brupdate.b2.uop.is_jal, issue_slots[6].brupdate.b2.uop.is_jal
connect slots_6.io.brupdate.b2.uop.is_jalr, issue_slots[6].brupdate.b2.uop.is_jalr
connect slots_6.io.brupdate.b2.uop.is_br, issue_slots[6].brupdate.b2.uop.is_br
connect slots_6.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[6].brupdate.b2.uop.iw_p2_poisoned
connect slots_6.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[6].brupdate.b2.uop.iw_p1_poisoned
connect slots_6.io.brupdate.b2.uop.iw_state, issue_slots[6].brupdate.b2.uop.iw_state
connect slots_6.io.brupdate.b2.uop.ctrl.is_std, issue_slots[6].brupdate.b2.uop.ctrl.is_std
connect slots_6.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[6].brupdate.b2.uop.ctrl.is_sta
connect slots_6.io.brupdate.b2.uop.ctrl.is_load, issue_slots[6].brupdate.b2.uop.ctrl.is_load
connect slots_6.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd
connect slots_6.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw
connect slots_6.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[6].brupdate.b2.uop.ctrl.op_fcn
connect slots_6.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[6].brupdate.b2.uop.ctrl.imm_sel
connect slots_6.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[6].brupdate.b2.uop.ctrl.op2_sel
connect slots_6.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[6].brupdate.b2.uop.ctrl.op1_sel
connect slots_6.io.brupdate.b2.uop.ctrl.br_type, issue_slots[6].brupdate.b2.uop.ctrl.br_type
connect slots_6.io.brupdate.b2.uop.fu_code, issue_slots[6].brupdate.b2.uop.fu_code
connect slots_6.io.brupdate.b2.uop.iq_type, issue_slots[6].brupdate.b2.uop.iq_type
connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc
connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc
connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst
connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst
connect slots_6.io.brupdate.b2.uop.uopc, issue_slots[6].brupdate.b2.uop.uopc
connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask
connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask
connect slots_6.io.grant, issue_slots[6].grant
connect issue_slots[6].request_hp, slots_6.io.request_hp
connect issue_slots[6].request, slots_6.io.request
connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid
connect issue_slots[6].valid, slots_6.io.valid
connect issue_slots[7].debug.state, slots_7.io.debug.state
connect issue_slots[7].debug.ppred, slots_7.io.debug.ppred
connect issue_slots[7].debug.p3, slots_7.io.debug.p3
connect issue_slots[7].debug.p2, slots_7.io.debug.p2
connect issue_slots[7].debug.p1, slots_7.io.debug.p1
connect issue_slots[7].uop.debug_tsrc, slots_7.io.uop.debug_tsrc
connect issue_slots[7].uop.debug_fsrc, slots_7.io.uop.debug_fsrc
connect issue_slots[7].uop.bp_xcpt_if, slots_7.io.uop.bp_xcpt_if
connect issue_slots[7].uop.bp_debug_if, slots_7.io.uop.bp_debug_if
connect issue_slots[7].uop.xcpt_ma_if, slots_7.io.uop.xcpt_ma_if
connect issue_slots[7].uop.xcpt_ae_if, slots_7.io.uop.xcpt_ae_if
connect issue_slots[7].uop.xcpt_pf_if, slots_7.io.uop.xcpt_pf_if
connect issue_slots[7].uop.fp_single, slots_7.io.uop.fp_single
connect issue_slots[7].uop.fp_val, slots_7.io.uop.fp_val
connect issue_slots[7].uop.frs3_en, slots_7.io.uop.frs3_en
connect issue_slots[7].uop.lrs2_rtype, slots_7.io.uop.lrs2_rtype
connect issue_slots[7].uop.lrs1_rtype, slots_7.io.uop.lrs1_rtype
connect issue_slots[7].uop.dst_rtype, slots_7.io.uop.dst_rtype
connect issue_slots[7].uop.ldst_val, slots_7.io.uop.ldst_val
connect issue_slots[7].uop.lrs3, slots_7.io.uop.lrs3
connect issue_slots[7].uop.lrs2, slots_7.io.uop.lrs2
connect issue_slots[7].uop.lrs1, slots_7.io.uop.lrs1
connect issue_slots[7].uop.ldst, slots_7.io.uop.ldst
connect issue_slots[7].uop.ldst_is_rs1, slots_7.io.uop.ldst_is_rs1
connect issue_slots[7].uop.flush_on_commit, slots_7.io.uop.flush_on_commit
connect issue_slots[7].uop.is_unique, slots_7.io.uop.is_unique
connect issue_slots[7].uop.is_sys_pc2epc, slots_7.io.uop.is_sys_pc2epc
connect issue_slots[7].uop.uses_stq, slots_7.io.uop.uses_stq
connect issue_slots[7].uop.uses_ldq, slots_7.io.uop.uses_ldq
connect issue_slots[7].uop.is_amo, slots_7.io.uop.is_amo
connect issue_slots[7].uop.is_fencei, slots_7.io.uop.is_fencei
connect issue_slots[7].uop.is_fence, slots_7.io.uop.is_fence
connect issue_slots[7].uop.mem_signed, slots_7.io.uop.mem_signed
connect issue_slots[7].uop.mem_size, slots_7.io.uop.mem_size
connect issue_slots[7].uop.mem_cmd, slots_7.io.uop.mem_cmd
connect issue_slots[7].uop.bypassable, slots_7.io.uop.bypassable
connect issue_slots[7].uop.exc_cause, slots_7.io.uop.exc_cause
connect issue_slots[7].uop.exception, slots_7.io.uop.exception
connect issue_slots[7].uop.stale_pdst, slots_7.io.uop.stale_pdst
connect issue_slots[7].uop.ppred_busy, slots_7.io.uop.ppred_busy
connect issue_slots[7].uop.prs3_busy, slots_7.io.uop.prs3_busy
connect issue_slots[7].uop.prs2_busy, slots_7.io.uop.prs2_busy
connect issue_slots[7].uop.prs1_busy, slots_7.io.uop.prs1_busy
connect issue_slots[7].uop.ppred, slots_7.io.uop.ppred
connect issue_slots[7].uop.prs3, slots_7.io.uop.prs3
connect issue_slots[7].uop.prs2, slots_7.io.uop.prs2
connect issue_slots[7].uop.prs1, slots_7.io.uop.prs1
connect issue_slots[7].uop.pdst, slots_7.io.uop.pdst
connect issue_slots[7].uop.rxq_idx, slots_7.io.uop.rxq_idx
connect issue_slots[7].uop.stq_idx, slots_7.io.uop.stq_idx
connect issue_slots[7].uop.ldq_idx, slots_7.io.uop.ldq_idx
connect issue_slots[7].uop.rob_idx, slots_7.io.uop.rob_idx
connect issue_slots[7].uop.csr_addr, slots_7.io.uop.csr_addr
connect issue_slots[7].uop.imm_packed, slots_7.io.uop.imm_packed
connect issue_slots[7].uop.taken, slots_7.io.uop.taken
connect issue_slots[7].uop.pc_lob, slots_7.io.uop.pc_lob
connect issue_slots[7].uop.edge_inst, slots_7.io.uop.edge_inst
connect issue_slots[7].uop.ftq_idx, slots_7.io.uop.ftq_idx
connect issue_slots[7].uop.br_tag, slots_7.io.uop.br_tag
connect issue_slots[7].uop.br_mask, slots_7.io.uop.br_mask
connect issue_slots[7].uop.is_sfb, slots_7.io.uop.is_sfb
connect issue_slots[7].uop.is_jal, slots_7.io.uop.is_jal
connect issue_slots[7].uop.is_jalr, slots_7.io.uop.is_jalr
connect issue_slots[7].uop.is_br, slots_7.io.uop.is_br
connect issue_slots[7].uop.iw_p2_poisoned, slots_7.io.uop.iw_p2_poisoned
connect issue_slots[7].uop.iw_p1_poisoned, slots_7.io.uop.iw_p1_poisoned
connect issue_slots[7].uop.iw_state, slots_7.io.uop.iw_state
connect issue_slots[7].uop.ctrl.is_std, slots_7.io.uop.ctrl.is_std
connect issue_slots[7].uop.ctrl.is_sta, slots_7.io.uop.ctrl.is_sta
connect issue_slots[7].uop.ctrl.is_load, slots_7.io.uop.ctrl.is_load
connect issue_slots[7].uop.ctrl.csr_cmd, slots_7.io.uop.ctrl.csr_cmd
connect issue_slots[7].uop.ctrl.fcn_dw, slots_7.io.uop.ctrl.fcn_dw
connect issue_slots[7].uop.ctrl.op_fcn, slots_7.io.uop.ctrl.op_fcn
connect issue_slots[7].uop.ctrl.imm_sel, slots_7.io.uop.ctrl.imm_sel
connect issue_slots[7].uop.ctrl.op2_sel, slots_7.io.uop.ctrl.op2_sel
connect issue_slots[7].uop.ctrl.op1_sel, slots_7.io.uop.ctrl.op1_sel
connect issue_slots[7].uop.ctrl.br_type, slots_7.io.uop.ctrl.br_type
connect issue_slots[7].uop.fu_code, slots_7.io.uop.fu_code
connect issue_slots[7].uop.iq_type, slots_7.io.uop.iq_type
connect issue_slots[7].uop.debug_pc, slots_7.io.uop.debug_pc
connect issue_slots[7].uop.is_rvc, slots_7.io.uop.is_rvc
connect issue_slots[7].uop.debug_inst, slots_7.io.uop.debug_inst
connect issue_slots[7].uop.inst, slots_7.io.uop.inst
connect issue_slots[7].uop.uopc, slots_7.io.uop.uopc
connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc
connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc
connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if
connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if
connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if
connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if
connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if
connect issue_slots[7].out_uop.fp_single, slots_7.io.out_uop.fp_single
connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val
connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en
connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype
connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype
connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype
connect issue_slots[7].out_uop.ldst_val, slots_7.io.out_uop.ldst_val
connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3
connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2
connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1
connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst
connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1
connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit
connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique
connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc
connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq
connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq
connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo
connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei
connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence
connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed
connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size
connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd
connect issue_slots[7].out_uop.bypassable, slots_7.io.out_uop.bypassable
connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause
connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception
connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst
connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy
connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy
connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy
connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy
connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred
connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3
connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2
connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1
connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst
connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx
connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx
connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx
connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx
connect issue_slots[7].out_uop.csr_addr, slots_7.io.out_uop.csr_addr
connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed
connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken
connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob
connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst
connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx
connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag
connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask
connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb
connect issue_slots[7].out_uop.is_jal, slots_7.io.out_uop.is_jal
connect issue_slots[7].out_uop.is_jalr, slots_7.io.out_uop.is_jalr
connect issue_slots[7].out_uop.is_br, slots_7.io.out_uop.is_br
connect issue_slots[7].out_uop.iw_p2_poisoned, slots_7.io.out_uop.iw_p2_poisoned
connect issue_slots[7].out_uop.iw_p1_poisoned, slots_7.io.out_uop.iw_p1_poisoned
connect issue_slots[7].out_uop.iw_state, slots_7.io.out_uop.iw_state
connect issue_slots[7].out_uop.ctrl.is_std, slots_7.io.out_uop.ctrl.is_std
connect issue_slots[7].out_uop.ctrl.is_sta, slots_7.io.out_uop.ctrl.is_sta
connect issue_slots[7].out_uop.ctrl.is_load, slots_7.io.out_uop.ctrl.is_load
connect issue_slots[7].out_uop.ctrl.csr_cmd, slots_7.io.out_uop.ctrl.csr_cmd
connect issue_slots[7].out_uop.ctrl.fcn_dw, slots_7.io.out_uop.ctrl.fcn_dw
connect issue_slots[7].out_uop.ctrl.op_fcn, slots_7.io.out_uop.ctrl.op_fcn
connect issue_slots[7].out_uop.ctrl.imm_sel, slots_7.io.out_uop.ctrl.imm_sel
connect issue_slots[7].out_uop.ctrl.op2_sel, slots_7.io.out_uop.ctrl.op2_sel
connect issue_slots[7].out_uop.ctrl.op1_sel, slots_7.io.out_uop.ctrl.op1_sel
connect issue_slots[7].out_uop.ctrl.br_type, slots_7.io.out_uop.ctrl.br_type
connect issue_slots[7].out_uop.fu_code, slots_7.io.out_uop.fu_code
connect issue_slots[7].out_uop.iq_type, slots_7.io.out_uop.iq_type
connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc
connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc
connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst
connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst
connect issue_slots[7].out_uop.uopc, slots_7.io.out_uop.uopc
connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc
connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc
connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if
connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if
connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if
connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if
connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if
connect slots_7.io.in_uop.bits.fp_single, issue_slots[7].in_uop.bits.fp_single
connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val
connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en
connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype
connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype
connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype
connect slots_7.io.in_uop.bits.ldst_val, issue_slots[7].in_uop.bits.ldst_val
connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3
connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2
connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1
connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst
connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1
connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit
connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique
connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc
connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq
connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq
connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo
connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei
connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence
connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed
connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size
connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd
connect slots_7.io.in_uop.bits.bypassable, issue_slots[7].in_uop.bits.bypassable
connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause
connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception
connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst
connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy
connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy
connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy
connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy
connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred
connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3
connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2
connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1
connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst
connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx
connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx
connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx
connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx
connect slots_7.io.in_uop.bits.csr_addr, issue_slots[7].in_uop.bits.csr_addr
connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed
connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken
connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob
connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst
connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx
connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag
connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask
connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb
connect slots_7.io.in_uop.bits.is_jal, issue_slots[7].in_uop.bits.is_jal
connect slots_7.io.in_uop.bits.is_jalr, issue_slots[7].in_uop.bits.is_jalr
connect slots_7.io.in_uop.bits.is_br, issue_slots[7].in_uop.bits.is_br
connect slots_7.io.in_uop.bits.iw_p2_poisoned, issue_slots[7].in_uop.bits.iw_p2_poisoned
connect slots_7.io.in_uop.bits.iw_p1_poisoned, issue_slots[7].in_uop.bits.iw_p1_poisoned
connect slots_7.io.in_uop.bits.iw_state, issue_slots[7].in_uop.bits.iw_state
connect slots_7.io.in_uop.bits.ctrl.is_std, issue_slots[7].in_uop.bits.ctrl.is_std
connect slots_7.io.in_uop.bits.ctrl.is_sta, issue_slots[7].in_uop.bits.ctrl.is_sta
connect slots_7.io.in_uop.bits.ctrl.is_load, issue_slots[7].in_uop.bits.ctrl.is_load
connect slots_7.io.in_uop.bits.ctrl.csr_cmd, issue_slots[7].in_uop.bits.ctrl.csr_cmd
connect slots_7.io.in_uop.bits.ctrl.fcn_dw, issue_slots[7].in_uop.bits.ctrl.fcn_dw
connect slots_7.io.in_uop.bits.ctrl.op_fcn, issue_slots[7].in_uop.bits.ctrl.op_fcn
connect slots_7.io.in_uop.bits.ctrl.imm_sel, issue_slots[7].in_uop.bits.ctrl.imm_sel
connect slots_7.io.in_uop.bits.ctrl.op2_sel, issue_slots[7].in_uop.bits.ctrl.op2_sel
connect slots_7.io.in_uop.bits.ctrl.op1_sel, issue_slots[7].in_uop.bits.ctrl.op1_sel
connect slots_7.io.in_uop.bits.ctrl.br_type, issue_slots[7].in_uop.bits.ctrl.br_type
connect slots_7.io.in_uop.bits.fu_code, issue_slots[7].in_uop.bits.fu_code
connect slots_7.io.in_uop.bits.iq_type, issue_slots[7].in_uop.bits.iq_type
connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc
connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc
connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst
connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst
connect slots_7.io.in_uop.bits.uopc, issue_slots[7].in_uop.bits.uopc
connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid
connect slots_7.io.spec_ld_wakeup[0].bits, issue_slots[7].spec_ld_wakeup[0].bits
connect slots_7.io.spec_ld_wakeup[0].valid, issue_slots[7].spec_ld_wakeup[0].valid
connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits
connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid
connect slots_7.io.wakeup_ports[0].bits.poisoned, issue_slots[7].wakeup_ports[0].bits.poisoned
connect slots_7.io.wakeup_ports[0].bits.pdst, issue_slots[7].wakeup_ports[0].bits.pdst
connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid
connect slots_7.io.wakeup_ports[1].bits.poisoned, issue_slots[7].wakeup_ports[1].bits.poisoned
connect slots_7.io.wakeup_ports[1].bits.pdst, issue_slots[7].wakeup_ports[1].bits.pdst
connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid
connect slots_7.io.ldspec_miss, issue_slots[7].ldspec_miss
connect slots_7.io.clear, issue_slots[7].clear
connect slots_7.io.kill, issue_slots[7].kill
connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset
connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target
connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel
connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type
connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken
connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict
connect slots_7.io.brupdate.b2.valid, issue_slots[7].brupdate.b2.valid
connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc
connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc
connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if
connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if
connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if
connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if
connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if
connect slots_7.io.brupdate.b2.uop.fp_single, issue_slots[7].brupdate.b2.uop.fp_single
connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val
connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en
connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype
connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype
connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype
connect slots_7.io.brupdate.b2.uop.ldst_val, issue_slots[7].brupdate.b2.uop.ldst_val
connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3
connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2
connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1
connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst
connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1
connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit
connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique
connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc
connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq
connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq
connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo
connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei
connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence
connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed
connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size
connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd
connect slots_7.io.brupdate.b2.uop.bypassable, issue_slots[7].brupdate.b2.uop.bypassable
connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause
connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception
connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst
connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy
connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy
connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy
connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy
connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred
connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3
connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2
connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1
connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst
connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx
connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx
connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx
connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx
connect slots_7.io.brupdate.b2.uop.csr_addr, issue_slots[7].brupdate.b2.uop.csr_addr
connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed
connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken
connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob
connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst
connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx
connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag
connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask
connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb
connect slots_7.io.brupdate.b2.uop.is_jal, issue_slots[7].brupdate.b2.uop.is_jal
connect slots_7.io.brupdate.b2.uop.is_jalr, issue_slots[7].brupdate.b2.uop.is_jalr
connect slots_7.io.brupdate.b2.uop.is_br, issue_slots[7].brupdate.b2.uop.is_br
connect slots_7.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[7].brupdate.b2.uop.iw_p2_poisoned
connect slots_7.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[7].brupdate.b2.uop.iw_p1_poisoned
connect slots_7.io.brupdate.b2.uop.iw_state, issue_slots[7].brupdate.b2.uop.iw_state
connect slots_7.io.brupdate.b2.uop.ctrl.is_std, issue_slots[7].brupdate.b2.uop.ctrl.is_std
connect slots_7.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[7].brupdate.b2.uop.ctrl.is_sta
connect slots_7.io.brupdate.b2.uop.ctrl.is_load, issue_slots[7].brupdate.b2.uop.ctrl.is_load
connect slots_7.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd
connect slots_7.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw
connect slots_7.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[7].brupdate.b2.uop.ctrl.op_fcn
connect slots_7.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[7].brupdate.b2.uop.ctrl.imm_sel
connect slots_7.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[7].brupdate.b2.uop.ctrl.op2_sel
connect slots_7.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[7].brupdate.b2.uop.ctrl.op1_sel
connect slots_7.io.brupdate.b2.uop.ctrl.br_type, issue_slots[7].brupdate.b2.uop.ctrl.br_type
connect slots_7.io.brupdate.b2.uop.fu_code, issue_slots[7].brupdate.b2.uop.fu_code
connect slots_7.io.brupdate.b2.uop.iq_type, issue_slots[7].brupdate.b2.uop.iq_type
connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc
connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc
connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst
connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst
connect slots_7.io.brupdate.b2.uop.uopc, issue_slots[7].brupdate.b2.uop.uopc
connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask
connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask
connect slots_7.io.grant, issue_slots[7].grant
connect issue_slots[7].request_hp, slots_7.io.request_hp
connect issue_slots[7].request, slots_7.io.request
connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid
connect issue_slots[7].valid, slots_7.io.valid
connect issue_slots[8].debug.state, slots_8.io.debug.state
connect issue_slots[8].debug.ppred, slots_8.io.debug.ppred
connect issue_slots[8].debug.p3, slots_8.io.debug.p3
connect issue_slots[8].debug.p2, slots_8.io.debug.p2
connect issue_slots[8].debug.p1, slots_8.io.debug.p1
connect issue_slots[8].uop.debug_tsrc, slots_8.io.uop.debug_tsrc
connect issue_slots[8].uop.debug_fsrc, slots_8.io.uop.debug_fsrc
connect issue_slots[8].uop.bp_xcpt_if, slots_8.io.uop.bp_xcpt_if
connect issue_slots[8].uop.bp_debug_if, slots_8.io.uop.bp_debug_if
connect issue_slots[8].uop.xcpt_ma_if, slots_8.io.uop.xcpt_ma_if
connect issue_slots[8].uop.xcpt_ae_if, slots_8.io.uop.xcpt_ae_if
connect issue_slots[8].uop.xcpt_pf_if, slots_8.io.uop.xcpt_pf_if
connect issue_slots[8].uop.fp_single, slots_8.io.uop.fp_single
connect issue_slots[8].uop.fp_val, slots_8.io.uop.fp_val
connect issue_slots[8].uop.frs3_en, slots_8.io.uop.frs3_en
connect issue_slots[8].uop.lrs2_rtype, slots_8.io.uop.lrs2_rtype
connect issue_slots[8].uop.lrs1_rtype, slots_8.io.uop.lrs1_rtype
connect issue_slots[8].uop.dst_rtype, slots_8.io.uop.dst_rtype
connect issue_slots[8].uop.ldst_val, slots_8.io.uop.ldst_val
connect issue_slots[8].uop.lrs3, slots_8.io.uop.lrs3
connect issue_slots[8].uop.lrs2, slots_8.io.uop.lrs2
connect issue_slots[8].uop.lrs1, slots_8.io.uop.lrs1
connect issue_slots[8].uop.ldst, slots_8.io.uop.ldst
connect issue_slots[8].uop.ldst_is_rs1, slots_8.io.uop.ldst_is_rs1
connect issue_slots[8].uop.flush_on_commit, slots_8.io.uop.flush_on_commit
connect issue_slots[8].uop.is_unique, slots_8.io.uop.is_unique
connect issue_slots[8].uop.is_sys_pc2epc, slots_8.io.uop.is_sys_pc2epc
connect issue_slots[8].uop.uses_stq, slots_8.io.uop.uses_stq
connect issue_slots[8].uop.uses_ldq, slots_8.io.uop.uses_ldq
connect issue_slots[8].uop.is_amo, slots_8.io.uop.is_amo
connect issue_slots[8].uop.is_fencei, slots_8.io.uop.is_fencei
connect issue_slots[8].uop.is_fence, slots_8.io.uop.is_fence
connect issue_slots[8].uop.mem_signed, slots_8.io.uop.mem_signed
connect issue_slots[8].uop.mem_size, slots_8.io.uop.mem_size
connect issue_slots[8].uop.mem_cmd, slots_8.io.uop.mem_cmd
connect issue_slots[8].uop.bypassable, slots_8.io.uop.bypassable
connect issue_slots[8].uop.exc_cause, slots_8.io.uop.exc_cause
connect issue_slots[8].uop.exception, slots_8.io.uop.exception
connect issue_slots[8].uop.stale_pdst, slots_8.io.uop.stale_pdst
connect issue_slots[8].uop.ppred_busy, slots_8.io.uop.ppred_busy
connect issue_slots[8].uop.prs3_busy, slots_8.io.uop.prs3_busy
connect issue_slots[8].uop.prs2_busy, slots_8.io.uop.prs2_busy
connect issue_slots[8].uop.prs1_busy, slots_8.io.uop.prs1_busy
connect issue_slots[8].uop.ppred, slots_8.io.uop.ppred
connect issue_slots[8].uop.prs3, slots_8.io.uop.prs3
connect issue_slots[8].uop.prs2, slots_8.io.uop.prs2
connect issue_slots[8].uop.prs1, slots_8.io.uop.prs1
connect issue_slots[8].uop.pdst, slots_8.io.uop.pdst
connect issue_slots[8].uop.rxq_idx, slots_8.io.uop.rxq_idx
connect issue_slots[8].uop.stq_idx, slots_8.io.uop.stq_idx
connect issue_slots[8].uop.ldq_idx, slots_8.io.uop.ldq_idx
connect issue_slots[8].uop.rob_idx, slots_8.io.uop.rob_idx
connect issue_slots[8].uop.csr_addr, slots_8.io.uop.csr_addr
connect issue_slots[8].uop.imm_packed, slots_8.io.uop.imm_packed
connect issue_slots[8].uop.taken, slots_8.io.uop.taken
connect issue_slots[8].uop.pc_lob, slots_8.io.uop.pc_lob
connect issue_slots[8].uop.edge_inst, slots_8.io.uop.edge_inst
connect issue_slots[8].uop.ftq_idx, slots_8.io.uop.ftq_idx
connect issue_slots[8].uop.br_tag, slots_8.io.uop.br_tag
connect issue_slots[8].uop.br_mask, slots_8.io.uop.br_mask
connect issue_slots[8].uop.is_sfb, slots_8.io.uop.is_sfb
connect issue_slots[8].uop.is_jal, slots_8.io.uop.is_jal
connect issue_slots[8].uop.is_jalr, slots_8.io.uop.is_jalr
connect issue_slots[8].uop.is_br, slots_8.io.uop.is_br
connect issue_slots[8].uop.iw_p2_poisoned, slots_8.io.uop.iw_p2_poisoned
connect issue_slots[8].uop.iw_p1_poisoned, slots_8.io.uop.iw_p1_poisoned
connect issue_slots[8].uop.iw_state, slots_8.io.uop.iw_state
connect issue_slots[8].uop.ctrl.is_std, slots_8.io.uop.ctrl.is_std
connect issue_slots[8].uop.ctrl.is_sta, slots_8.io.uop.ctrl.is_sta
connect issue_slots[8].uop.ctrl.is_load, slots_8.io.uop.ctrl.is_load
connect issue_slots[8].uop.ctrl.csr_cmd, slots_8.io.uop.ctrl.csr_cmd
connect issue_slots[8].uop.ctrl.fcn_dw, slots_8.io.uop.ctrl.fcn_dw
connect issue_slots[8].uop.ctrl.op_fcn, slots_8.io.uop.ctrl.op_fcn
connect issue_slots[8].uop.ctrl.imm_sel, slots_8.io.uop.ctrl.imm_sel
connect issue_slots[8].uop.ctrl.op2_sel, slots_8.io.uop.ctrl.op2_sel
connect issue_slots[8].uop.ctrl.op1_sel, slots_8.io.uop.ctrl.op1_sel
connect issue_slots[8].uop.ctrl.br_type, slots_8.io.uop.ctrl.br_type
connect issue_slots[8].uop.fu_code, slots_8.io.uop.fu_code
connect issue_slots[8].uop.iq_type, slots_8.io.uop.iq_type
connect issue_slots[8].uop.debug_pc, slots_8.io.uop.debug_pc
connect issue_slots[8].uop.is_rvc, slots_8.io.uop.is_rvc
connect issue_slots[8].uop.debug_inst, slots_8.io.uop.debug_inst
connect issue_slots[8].uop.inst, slots_8.io.uop.inst
connect issue_slots[8].uop.uopc, slots_8.io.uop.uopc
connect issue_slots[8].out_uop.debug_tsrc, slots_8.io.out_uop.debug_tsrc
connect issue_slots[8].out_uop.debug_fsrc, slots_8.io.out_uop.debug_fsrc
connect issue_slots[8].out_uop.bp_xcpt_if, slots_8.io.out_uop.bp_xcpt_if
connect issue_slots[8].out_uop.bp_debug_if, slots_8.io.out_uop.bp_debug_if
connect issue_slots[8].out_uop.xcpt_ma_if, slots_8.io.out_uop.xcpt_ma_if
connect issue_slots[8].out_uop.xcpt_ae_if, slots_8.io.out_uop.xcpt_ae_if
connect issue_slots[8].out_uop.xcpt_pf_if, slots_8.io.out_uop.xcpt_pf_if
connect issue_slots[8].out_uop.fp_single, slots_8.io.out_uop.fp_single
connect issue_slots[8].out_uop.fp_val, slots_8.io.out_uop.fp_val
connect issue_slots[8].out_uop.frs3_en, slots_8.io.out_uop.frs3_en
connect issue_slots[8].out_uop.lrs2_rtype, slots_8.io.out_uop.lrs2_rtype
connect issue_slots[8].out_uop.lrs1_rtype, slots_8.io.out_uop.lrs1_rtype
connect issue_slots[8].out_uop.dst_rtype, slots_8.io.out_uop.dst_rtype
connect issue_slots[8].out_uop.ldst_val, slots_8.io.out_uop.ldst_val
connect issue_slots[8].out_uop.lrs3, slots_8.io.out_uop.lrs3
connect issue_slots[8].out_uop.lrs2, slots_8.io.out_uop.lrs2
connect issue_slots[8].out_uop.lrs1, slots_8.io.out_uop.lrs1
connect issue_slots[8].out_uop.ldst, slots_8.io.out_uop.ldst
connect issue_slots[8].out_uop.ldst_is_rs1, slots_8.io.out_uop.ldst_is_rs1
connect issue_slots[8].out_uop.flush_on_commit, slots_8.io.out_uop.flush_on_commit
connect issue_slots[8].out_uop.is_unique, slots_8.io.out_uop.is_unique
connect issue_slots[8].out_uop.is_sys_pc2epc, slots_8.io.out_uop.is_sys_pc2epc
connect issue_slots[8].out_uop.uses_stq, slots_8.io.out_uop.uses_stq
connect issue_slots[8].out_uop.uses_ldq, slots_8.io.out_uop.uses_ldq
connect issue_slots[8].out_uop.is_amo, slots_8.io.out_uop.is_amo
connect issue_slots[8].out_uop.is_fencei, slots_8.io.out_uop.is_fencei
connect issue_slots[8].out_uop.is_fence, slots_8.io.out_uop.is_fence
connect issue_slots[8].out_uop.mem_signed, slots_8.io.out_uop.mem_signed
connect issue_slots[8].out_uop.mem_size, slots_8.io.out_uop.mem_size
connect issue_slots[8].out_uop.mem_cmd, slots_8.io.out_uop.mem_cmd
connect issue_slots[8].out_uop.bypassable, slots_8.io.out_uop.bypassable
connect issue_slots[8].out_uop.exc_cause, slots_8.io.out_uop.exc_cause
connect issue_slots[8].out_uop.exception, slots_8.io.out_uop.exception
connect issue_slots[8].out_uop.stale_pdst, slots_8.io.out_uop.stale_pdst
connect issue_slots[8].out_uop.ppred_busy, slots_8.io.out_uop.ppred_busy
connect issue_slots[8].out_uop.prs3_busy, slots_8.io.out_uop.prs3_busy
connect issue_slots[8].out_uop.prs2_busy, slots_8.io.out_uop.prs2_busy
connect issue_slots[8].out_uop.prs1_busy, slots_8.io.out_uop.prs1_busy
connect issue_slots[8].out_uop.ppred, slots_8.io.out_uop.ppred
connect issue_slots[8].out_uop.prs3, slots_8.io.out_uop.prs3
connect issue_slots[8].out_uop.prs2, slots_8.io.out_uop.prs2
connect issue_slots[8].out_uop.prs1, slots_8.io.out_uop.prs1
connect issue_slots[8].out_uop.pdst, slots_8.io.out_uop.pdst
connect issue_slots[8].out_uop.rxq_idx, slots_8.io.out_uop.rxq_idx
connect issue_slots[8].out_uop.stq_idx, slots_8.io.out_uop.stq_idx
connect issue_slots[8].out_uop.ldq_idx, slots_8.io.out_uop.ldq_idx
connect issue_slots[8].out_uop.rob_idx, slots_8.io.out_uop.rob_idx
connect issue_slots[8].out_uop.csr_addr, slots_8.io.out_uop.csr_addr
connect issue_slots[8].out_uop.imm_packed, slots_8.io.out_uop.imm_packed
connect issue_slots[8].out_uop.taken, slots_8.io.out_uop.taken
connect issue_slots[8].out_uop.pc_lob, slots_8.io.out_uop.pc_lob
connect issue_slots[8].out_uop.edge_inst, slots_8.io.out_uop.edge_inst
connect issue_slots[8].out_uop.ftq_idx, slots_8.io.out_uop.ftq_idx
connect issue_slots[8].out_uop.br_tag, slots_8.io.out_uop.br_tag
connect issue_slots[8].out_uop.br_mask, slots_8.io.out_uop.br_mask
connect issue_slots[8].out_uop.is_sfb, slots_8.io.out_uop.is_sfb
connect issue_slots[8].out_uop.is_jal, slots_8.io.out_uop.is_jal
connect issue_slots[8].out_uop.is_jalr, slots_8.io.out_uop.is_jalr
connect issue_slots[8].out_uop.is_br, slots_8.io.out_uop.is_br
connect issue_slots[8].out_uop.iw_p2_poisoned, slots_8.io.out_uop.iw_p2_poisoned
connect issue_slots[8].out_uop.iw_p1_poisoned, slots_8.io.out_uop.iw_p1_poisoned
connect issue_slots[8].out_uop.iw_state, slots_8.io.out_uop.iw_state
connect issue_slots[8].out_uop.ctrl.is_std, slots_8.io.out_uop.ctrl.is_std
connect issue_slots[8].out_uop.ctrl.is_sta, slots_8.io.out_uop.ctrl.is_sta
connect issue_slots[8].out_uop.ctrl.is_load, slots_8.io.out_uop.ctrl.is_load
connect issue_slots[8].out_uop.ctrl.csr_cmd, slots_8.io.out_uop.ctrl.csr_cmd
connect issue_slots[8].out_uop.ctrl.fcn_dw, slots_8.io.out_uop.ctrl.fcn_dw
connect issue_slots[8].out_uop.ctrl.op_fcn, slots_8.io.out_uop.ctrl.op_fcn
connect issue_slots[8].out_uop.ctrl.imm_sel, slots_8.io.out_uop.ctrl.imm_sel
connect issue_slots[8].out_uop.ctrl.op2_sel, slots_8.io.out_uop.ctrl.op2_sel
connect issue_slots[8].out_uop.ctrl.op1_sel, slots_8.io.out_uop.ctrl.op1_sel
connect issue_slots[8].out_uop.ctrl.br_type, slots_8.io.out_uop.ctrl.br_type
connect issue_slots[8].out_uop.fu_code, slots_8.io.out_uop.fu_code
connect issue_slots[8].out_uop.iq_type, slots_8.io.out_uop.iq_type
connect issue_slots[8].out_uop.debug_pc, slots_8.io.out_uop.debug_pc
connect issue_slots[8].out_uop.is_rvc, slots_8.io.out_uop.is_rvc
connect issue_slots[8].out_uop.debug_inst, slots_8.io.out_uop.debug_inst
connect issue_slots[8].out_uop.inst, slots_8.io.out_uop.inst
connect issue_slots[8].out_uop.uopc, slots_8.io.out_uop.uopc
connect slots_8.io.in_uop.bits.debug_tsrc, issue_slots[8].in_uop.bits.debug_tsrc
connect slots_8.io.in_uop.bits.debug_fsrc, issue_slots[8].in_uop.bits.debug_fsrc
connect slots_8.io.in_uop.bits.bp_xcpt_if, issue_slots[8].in_uop.bits.bp_xcpt_if
connect slots_8.io.in_uop.bits.bp_debug_if, issue_slots[8].in_uop.bits.bp_debug_if
connect slots_8.io.in_uop.bits.xcpt_ma_if, issue_slots[8].in_uop.bits.xcpt_ma_if
connect slots_8.io.in_uop.bits.xcpt_ae_if, issue_slots[8].in_uop.bits.xcpt_ae_if
connect slots_8.io.in_uop.bits.xcpt_pf_if, issue_slots[8].in_uop.bits.xcpt_pf_if
connect slots_8.io.in_uop.bits.fp_single, issue_slots[8].in_uop.bits.fp_single
connect slots_8.io.in_uop.bits.fp_val, issue_slots[8].in_uop.bits.fp_val
connect slots_8.io.in_uop.bits.frs3_en, issue_slots[8].in_uop.bits.frs3_en
connect slots_8.io.in_uop.bits.lrs2_rtype, issue_slots[8].in_uop.bits.lrs2_rtype
connect slots_8.io.in_uop.bits.lrs1_rtype, issue_slots[8].in_uop.bits.lrs1_rtype
connect slots_8.io.in_uop.bits.dst_rtype, issue_slots[8].in_uop.bits.dst_rtype
connect slots_8.io.in_uop.bits.ldst_val, issue_slots[8].in_uop.bits.ldst_val
connect slots_8.io.in_uop.bits.lrs3, issue_slots[8].in_uop.bits.lrs3
connect slots_8.io.in_uop.bits.lrs2, issue_slots[8].in_uop.bits.lrs2
connect slots_8.io.in_uop.bits.lrs1, issue_slots[8].in_uop.bits.lrs1
connect slots_8.io.in_uop.bits.ldst, issue_slots[8].in_uop.bits.ldst
connect slots_8.io.in_uop.bits.ldst_is_rs1, issue_slots[8].in_uop.bits.ldst_is_rs1
connect slots_8.io.in_uop.bits.flush_on_commit, issue_slots[8].in_uop.bits.flush_on_commit
connect slots_8.io.in_uop.bits.is_unique, issue_slots[8].in_uop.bits.is_unique
connect slots_8.io.in_uop.bits.is_sys_pc2epc, issue_slots[8].in_uop.bits.is_sys_pc2epc
connect slots_8.io.in_uop.bits.uses_stq, issue_slots[8].in_uop.bits.uses_stq
connect slots_8.io.in_uop.bits.uses_ldq, issue_slots[8].in_uop.bits.uses_ldq
connect slots_8.io.in_uop.bits.is_amo, issue_slots[8].in_uop.bits.is_amo
connect slots_8.io.in_uop.bits.is_fencei, issue_slots[8].in_uop.bits.is_fencei
connect slots_8.io.in_uop.bits.is_fence, issue_slots[8].in_uop.bits.is_fence
connect slots_8.io.in_uop.bits.mem_signed, issue_slots[8].in_uop.bits.mem_signed
connect slots_8.io.in_uop.bits.mem_size, issue_slots[8].in_uop.bits.mem_size
connect slots_8.io.in_uop.bits.mem_cmd, issue_slots[8].in_uop.bits.mem_cmd
connect slots_8.io.in_uop.bits.bypassable, issue_slots[8].in_uop.bits.bypassable
connect slots_8.io.in_uop.bits.exc_cause, issue_slots[8].in_uop.bits.exc_cause
connect slots_8.io.in_uop.bits.exception, issue_slots[8].in_uop.bits.exception
connect slots_8.io.in_uop.bits.stale_pdst, issue_slots[8].in_uop.bits.stale_pdst
connect slots_8.io.in_uop.bits.ppred_busy, issue_slots[8].in_uop.bits.ppred_busy
connect slots_8.io.in_uop.bits.prs3_busy, issue_slots[8].in_uop.bits.prs3_busy
connect slots_8.io.in_uop.bits.prs2_busy, issue_slots[8].in_uop.bits.prs2_busy
connect slots_8.io.in_uop.bits.prs1_busy, issue_slots[8].in_uop.bits.prs1_busy
connect slots_8.io.in_uop.bits.ppred, issue_slots[8].in_uop.bits.ppred
connect slots_8.io.in_uop.bits.prs3, issue_slots[8].in_uop.bits.prs3
connect slots_8.io.in_uop.bits.prs2, issue_slots[8].in_uop.bits.prs2
connect slots_8.io.in_uop.bits.prs1, issue_slots[8].in_uop.bits.prs1
connect slots_8.io.in_uop.bits.pdst, issue_slots[8].in_uop.bits.pdst
connect slots_8.io.in_uop.bits.rxq_idx, issue_slots[8].in_uop.bits.rxq_idx
connect slots_8.io.in_uop.bits.stq_idx, issue_slots[8].in_uop.bits.stq_idx
connect slots_8.io.in_uop.bits.ldq_idx, issue_slots[8].in_uop.bits.ldq_idx
connect slots_8.io.in_uop.bits.rob_idx, issue_slots[8].in_uop.bits.rob_idx
connect slots_8.io.in_uop.bits.csr_addr, issue_slots[8].in_uop.bits.csr_addr
connect slots_8.io.in_uop.bits.imm_packed, issue_slots[8].in_uop.bits.imm_packed
connect slots_8.io.in_uop.bits.taken, issue_slots[8].in_uop.bits.taken
connect slots_8.io.in_uop.bits.pc_lob, issue_slots[8].in_uop.bits.pc_lob
connect slots_8.io.in_uop.bits.edge_inst, issue_slots[8].in_uop.bits.edge_inst
connect slots_8.io.in_uop.bits.ftq_idx, issue_slots[8].in_uop.bits.ftq_idx
connect slots_8.io.in_uop.bits.br_tag, issue_slots[8].in_uop.bits.br_tag
connect slots_8.io.in_uop.bits.br_mask, issue_slots[8].in_uop.bits.br_mask
connect slots_8.io.in_uop.bits.is_sfb, issue_slots[8].in_uop.bits.is_sfb
connect slots_8.io.in_uop.bits.is_jal, issue_slots[8].in_uop.bits.is_jal
connect slots_8.io.in_uop.bits.is_jalr, issue_slots[8].in_uop.bits.is_jalr
connect slots_8.io.in_uop.bits.is_br, issue_slots[8].in_uop.bits.is_br
connect slots_8.io.in_uop.bits.iw_p2_poisoned, issue_slots[8].in_uop.bits.iw_p2_poisoned
connect slots_8.io.in_uop.bits.iw_p1_poisoned, issue_slots[8].in_uop.bits.iw_p1_poisoned
connect slots_8.io.in_uop.bits.iw_state, issue_slots[8].in_uop.bits.iw_state
connect slots_8.io.in_uop.bits.ctrl.is_std, issue_slots[8].in_uop.bits.ctrl.is_std
connect slots_8.io.in_uop.bits.ctrl.is_sta, issue_slots[8].in_uop.bits.ctrl.is_sta
connect slots_8.io.in_uop.bits.ctrl.is_load, issue_slots[8].in_uop.bits.ctrl.is_load
connect slots_8.io.in_uop.bits.ctrl.csr_cmd, issue_slots[8].in_uop.bits.ctrl.csr_cmd
connect slots_8.io.in_uop.bits.ctrl.fcn_dw, issue_slots[8].in_uop.bits.ctrl.fcn_dw
connect slots_8.io.in_uop.bits.ctrl.op_fcn, issue_slots[8].in_uop.bits.ctrl.op_fcn
connect slots_8.io.in_uop.bits.ctrl.imm_sel, issue_slots[8].in_uop.bits.ctrl.imm_sel
connect slots_8.io.in_uop.bits.ctrl.op2_sel, issue_slots[8].in_uop.bits.ctrl.op2_sel
connect slots_8.io.in_uop.bits.ctrl.op1_sel, issue_slots[8].in_uop.bits.ctrl.op1_sel
connect slots_8.io.in_uop.bits.ctrl.br_type, issue_slots[8].in_uop.bits.ctrl.br_type
connect slots_8.io.in_uop.bits.fu_code, issue_slots[8].in_uop.bits.fu_code
connect slots_8.io.in_uop.bits.iq_type, issue_slots[8].in_uop.bits.iq_type
connect slots_8.io.in_uop.bits.debug_pc, issue_slots[8].in_uop.bits.debug_pc
connect slots_8.io.in_uop.bits.is_rvc, issue_slots[8].in_uop.bits.is_rvc
connect slots_8.io.in_uop.bits.debug_inst, issue_slots[8].in_uop.bits.debug_inst
connect slots_8.io.in_uop.bits.inst, issue_slots[8].in_uop.bits.inst
connect slots_8.io.in_uop.bits.uopc, issue_slots[8].in_uop.bits.uopc
connect slots_8.io.in_uop.valid, issue_slots[8].in_uop.valid
connect slots_8.io.spec_ld_wakeup[0].bits, issue_slots[8].spec_ld_wakeup[0].bits
connect slots_8.io.spec_ld_wakeup[0].valid, issue_slots[8].spec_ld_wakeup[0].valid
connect slots_8.io.pred_wakeup_port.bits, issue_slots[8].pred_wakeup_port.bits
connect slots_8.io.pred_wakeup_port.valid, issue_slots[8].pred_wakeup_port.valid
connect slots_8.io.wakeup_ports[0].bits.poisoned, issue_slots[8].wakeup_ports[0].bits.poisoned
connect slots_8.io.wakeup_ports[0].bits.pdst, issue_slots[8].wakeup_ports[0].bits.pdst
connect slots_8.io.wakeup_ports[0].valid, issue_slots[8].wakeup_ports[0].valid
connect slots_8.io.wakeup_ports[1].bits.poisoned, issue_slots[8].wakeup_ports[1].bits.poisoned
connect slots_8.io.wakeup_ports[1].bits.pdst, issue_slots[8].wakeup_ports[1].bits.pdst
connect slots_8.io.wakeup_ports[1].valid, issue_slots[8].wakeup_ports[1].valid
connect slots_8.io.ldspec_miss, issue_slots[8].ldspec_miss
connect slots_8.io.clear, issue_slots[8].clear
connect slots_8.io.kill, issue_slots[8].kill
connect slots_8.io.brupdate.b2.target_offset, issue_slots[8].brupdate.b2.target_offset
connect slots_8.io.brupdate.b2.jalr_target, issue_slots[8].brupdate.b2.jalr_target
connect slots_8.io.brupdate.b2.pc_sel, issue_slots[8].brupdate.b2.pc_sel
connect slots_8.io.brupdate.b2.cfi_type, issue_slots[8].brupdate.b2.cfi_type
connect slots_8.io.brupdate.b2.taken, issue_slots[8].brupdate.b2.taken
connect slots_8.io.brupdate.b2.mispredict, issue_slots[8].brupdate.b2.mispredict
connect slots_8.io.brupdate.b2.valid, issue_slots[8].brupdate.b2.valid
connect slots_8.io.brupdate.b2.uop.debug_tsrc, issue_slots[8].brupdate.b2.uop.debug_tsrc
connect slots_8.io.brupdate.b2.uop.debug_fsrc, issue_slots[8].brupdate.b2.uop.debug_fsrc
connect slots_8.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[8].brupdate.b2.uop.bp_xcpt_if
connect slots_8.io.brupdate.b2.uop.bp_debug_if, issue_slots[8].brupdate.b2.uop.bp_debug_if
connect slots_8.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[8].brupdate.b2.uop.xcpt_ma_if
connect slots_8.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[8].brupdate.b2.uop.xcpt_ae_if
connect slots_8.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[8].brupdate.b2.uop.xcpt_pf_if
connect slots_8.io.brupdate.b2.uop.fp_single, issue_slots[8].brupdate.b2.uop.fp_single
connect slots_8.io.brupdate.b2.uop.fp_val, issue_slots[8].brupdate.b2.uop.fp_val
connect slots_8.io.brupdate.b2.uop.frs3_en, issue_slots[8].brupdate.b2.uop.frs3_en
connect slots_8.io.brupdate.b2.uop.lrs2_rtype, issue_slots[8].brupdate.b2.uop.lrs2_rtype
connect slots_8.io.brupdate.b2.uop.lrs1_rtype, issue_slots[8].brupdate.b2.uop.lrs1_rtype
connect slots_8.io.brupdate.b2.uop.dst_rtype, issue_slots[8].brupdate.b2.uop.dst_rtype
connect slots_8.io.brupdate.b2.uop.ldst_val, issue_slots[8].brupdate.b2.uop.ldst_val
connect slots_8.io.brupdate.b2.uop.lrs3, issue_slots[8].brupdate.b2.uop.lrs3
connect slots_8.io.brupdate.b2.uop.lrs2, issue_slots[8].brupdate.b2.uop.lrs2
connect slots_8.io.brupdate.b2.uop.lrs1, issue_slots[8].brupdate.b2.uop.lrs1
connect slots_8.io.brupdate.b2.uop.ldst, issue_slots[8].brupdate.b2.uop.ldst
connect slots_8.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[8].brupdate.b2.uop.ldst_is_rs1
connect slots_8.io.brupdate.b2.uop.flush_on_commit, issue_slots[8].brupdate.b2.uop.flush_on_commit
connect slots_8.io.brupdate.b2.uop.is_unique, issue_slots[8].brupdate.b2.uop.is_unique
connect slots_8.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[8].brupdate.b2.uop.is_sys_pc2epc
connect slots_8.io.brupdate.b2.uop.uses_stq, issue_slots[8].brupdate.b2.uop.uses_stq
connect slots_8.io.brupdate.b2.uop.uses_ldq, issue_slots[8].brupdate.b2.uop.uses_ldq
connect slots_8.io.brupdate.b2.uop.is_amo, issue_slots[8].brupdate.b2.uop.is_amo
connect slots_8.io.brupdate.b2.uop.is_fencei, issue_slots[8].brupdate.b2.uop.is_fencei
connect slots_8.io.brupdate.b2.uop.is_fence, issue_slots[8].brupdate.b2.uop.is_fence
connect slots_8.io.brupdate.b2.uop.mem_signed, issue_slots[8].brupdate.b2.uop.mem_signed
connect slots_8.io.brupdate.b2.uop.mem_size, issue_slots[8].brupdate.b2.uop.mem_size
connect slots_8.io.brupdate.b2.uop.mem_cmd, issue_slots[8].brupdate.b2.uop.mem_cmd
connect slots_8.io.brupdate.b2.uop.bypassable, issue_slots[8].brupdate.b2.uop.bypassable
connect slots_8.io.brupdate.b2.uop.exc_cause, issue_slots[8].brupdate.b2.uop.exc_cause
connect slots_8.io.brupdate.b2.uop.exception, issue_slots[8].brupdate.b2.uop.exception
connect slots_8.io.brupdate.b2.uop.stale_pdst, issue_slots[8].brupdate.b2.uop.stale_pdst
connect slots_8.io.brupdate.b2.uop.ppred_busy, issue_slots[8].brupdate.b2.uop.ppred_busy
connect slots_8.io.brupdate.b2.uop.prs3_busy, issue_slots[8].brupdate.b2.uop.prs3_busy
connect slots_8.io.brupdate.b2.uop.prs2_busy, issue_slots[8].brupdate.b2.uop.prs2_busy
connect slots_8.io.brupdate.b2.uop.prs1_busy, issue_slots[8].brupdate.b2.uop.prs1_busy
connect slots_8.io.brupdate.b2.uop.ppred, issue_slots[8].brupdate.b2.uop.ppred
connect slots_8.io.brupdate.b2.uop.prs3, issue_slots[8].brupdate.b2.uop.prs3
connect slots_8.io.brupdate.b2.uop.prs2, issue_slots[8].brupdate.b2.uop.prs2
connect slots_8.io.brupdate.b2.uop.prs1, issue_slots[8].brupdate.b2.uop.prs1
connect slots_8.io.brupdate.b2.uop.pdst, issue_slots[8].brupdate.b2.uop.pdst
connect slots_8.io.brupdate.b2.uop.rxq_idx, issue_slots[8].brupdate.b2.uop.rxq_idx
connect slots_8.io.brupdate.b2.uop.stq_idx, issue_slots[8].brupdate.b2.uop.stq_idx
connect slots_8.io.brupdate.b2.uop.ldq_idx, issue_slots[8].brupdate.b2.uop.ldq_idx
connect slots_8.io.brupdate.b2.uop.rob_idx, issue_slots[8].brupdate.b2.uop.rob_idx
connect slots_8.io.brupdate.b2.uop.csr_addr, issue_slots[8].brupdate.b2.uop.csr_addr
connect slots_8.io.brupdate.b2.uop.imm_packed, issue_slots[8].brupdate.b2.uop.imm_packed
connect slots_8.io.brupdate.b2.uop.taken, issue_slots[8].brupdate.b2.uop.taken
connect slots_8.io.brupdate.b2.uop.pc_lob, issue_slots[8].brupdate.b2.uop.pc_lob
connect slots_8.io.brupdate.b2.uop.edge_inst, issue_slots[8].brupdate.b2.uop.edge_inst
connect slots_8.io.brupdate.b2.uop.ftq_idx, issue_slots[8].brupdate.b2.uop.ftq_idx
connect slots_8.io.brupdate.b2.uop.br_tag, issue_slots[8].brupdate.b2.uop.br_tag
connect slots_8.io.brupdate.b2.uop.br_mask, issue_slots[8].brupdate.b2.uop.br_mask
connect slots_8.io.brupdate.b2.uop.is_sfb, issue_slots[8].brupdate.b2.uop.is_sfb
connect slots_8.io.brupdate.b2.uop.is_jal, issue_slots[8].brupdate.b2.uop.is_jal
connect slots_8.io.brupdate.b2.uop.is_jalr, issue_slots[8].brupdate.b2.uop.is_jalr
connect slots_8.io.brupdate.b2.uop.is_br, issue_slots[8].brupdate.b2.uop.is_br
connect slots_8.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[8].brupdate.b2.uop.iw_p2_poisoned
connect slots_8.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[8].brupdate.b2.uop.iw_p1_poisoned
connect slots_8.io.brupdate.b2.uop.iw_state, issue_slots[8].brupdate.b2.uop.iw_state
connect slots_8.io.brupdate.b2.uop.ctrl.is_std, issue_slots[8].brupdate.b2.uop.ctrl.is_std
connect slots_8.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[8].brupdate.b2.uop.ctrl.is_sta
connect slots_8.io.brupdate.b2.uop.ctrl.is_load, issue_slots[8].brupdate.b2.uop.ctrl.is_load
connect slots_8.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[8].brupdate.b2.uop.ctrl.csr_cmd
connect slots_8.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[8].brupdate.b2.uop.ctrl.fcn_dw
connect slots_8.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[8].brupdate.b2.uop.ctrl.op_fcn
connect slots_8.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[8].brupdate.b2.uop.ctrl.imm_sel
connect slots_8.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[8].brupdate.b2.uop.ctrl.op2_sel
connect slots_8.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[8].brupdate.b2.uop.ctrl.op1_sel
connect slots_8.io.brupdate.b2.uop.ctrl.br_type, issue_slots[8].brupdate.b2.uop.ctrl.br_type
connect slots_8.io.brupdate.b2.uop.fu_code, issue_slots[8].brupdate.b2.uop.fu_code
connect slots_8.io.brupdate.b2.uop.iq_type, issue_slots[8].brupdate.b2.uop.iq_type
connect slots_8.io.brupdate.b2.uop.debug_pc, issue_slots[8].brupdate.b2.uop.debug_pc
connect slots_8.io.brupdate.b2.uop.is_rvc, issue_slots[8].brupdate.b2.uop.is_rvc
connect slots_8.io.brupdate.b2.uop.debug_inst, issue_slots[8].brupdate.b2.uop.debug_inst
connect slots_8.io.brupdate.b2.uop.inst, issue_slots[8].brupdate.b2.uop.inst
connect slots_8.io.brupdate.b2.uop.uopc, issue_slots[8].brupdate.b2.uop.uopc
connect slots_8.io.brupdate.b1.mispredict_mask, issue_slots[8].brupdate.b1.mispredict_mask
connect slots_8.io.brupdate.b1.resolve_mask, issue_slots[8].brupdate.b1.resolve_mask
connect slots_8.io.grant, issue_slots[8].grant
connect issue_slots[8].request_hp, slots_8.io.request_hp
connect issue_slots[8].request, slots_8.io.request
connect issue_slots[8].will_be_valid, slots_8.io.will_be_valid
connect issue_slots[8].valid, slots_8.io.valid
connect issue_slots[9].debug.state, slots_9.io.debug.state
connect issue_slots[9].debug.ppred, slots_9.io.debug.ppred
connect issue_slots[9].debug.p3, slots_9.io.debug.p3
connect issue_slots[9].debug.p2, slots_9.io.debug.p2
connect issue_slots[9].debug.p1, slots_9.io.debug.p1
connect issue_slots[9].uop.debug_tsrc, slots_9.io.uop.debug_tsrc
connect issue_slots[9].uop.debug_fsrc, slots_9.io.uop.debug_fsrc
connect issue_slots[9].uop.bp_xcpt_if, slots_9.io.uop.bp_xcpt_if
connect issue_slots[9].uop.bp_debug_if, slots_9.io.uop.bp_debug_if
connect issue_slots[9].uop.xcpt_ma_if, slots_9.io.uop.xcpt_ma_if
connect issue_slots[9].uop.xcpt_ae_if, slots_9.io.uop.xcpt_ae_if
connect issue_slots[9].uop.xcpt_pf_if, slots_9.io.uop.xcpt_pf_if
connect issue_slots[9].uop.fp_single, slots_9.io.uop.fp_single
connect issue_slots[9].uop.fp_val, slots_9.io.uop.fp_val
connect issue_slots[9].uop.frs3_en, slots_9.io.uop.frs3_en
connect issue_slots[9].uop.lrs2_rtype, slots_9.io.uop.lrs2_rtype
connect issue_slots[9].uop.lrs1_rtype, slots_9.io.uop.lrs1_rtype
connect issue_slots[9].uop.dst_rtype, slots_9.io.uop.dst_rtype
connect issue_slots[9].uop.ldst_val, slots_9.io.uop.ldst_val
connect issue_slots[9].uop.lrs3, slots_9.io.uop.lrs3
connect issue_slots[9].uop.lrs2, slots_9.io.uop.lrs2
connect issue_slots[9].uop.lrs1, slots_9.io.uop.lrs1
connect issue_slots[9].uop.ldst, slots_9.io.uop.ldst
connect issue_slots[9].uop.ldst_is_rs1, slots_9.io.uop.ldst_is_rs1
connect issue_slots[9].uop.flush_on_commit, slots_9.io.uop.flush_on_commit
connect issue_slots[9].uop.is_unique, slots_9.io.uop.is_unique
connect issue_slots[9].uop.is_sys_pc2epc, slots_9.io.uop.is_sys_pc2epc
connect issue_slots[9].uop.uses_stq, slots_9.io.uop.uses_stq
connect issue_slots[9].uop.uses_ldq, slots_9.io.uop.uses_ldq
connect issue_slots[9].uop.is_amo, slots_9.io.uop.is_amo
connect issue_slots[9].uop.is_fencei, slots_9.io.uop.is_fencei
connect issue_slots[9].uop.is_fence, slots_9.io.uop.is_fence
connect issue_slots[9].uop.mem_signed, slots_9.io.uop.mem_signed
connect issue_slots[9].uop.mem_size, slots_9.io.uop.mem_size
connect issue_slots[9].uop.mem_cmd, slots_9.io.uop.mem_cmd
connect issue_slots[9].uop.bypassable, slots_9.io.uop.bypassable
connect issue_slots[9].uop.exc_cause, slots_9.io.uop.exc_cause
connect issue_slots[9].uop.exception, slots_9.io.uop.exception
connect issue_slots[9].uop.stale_pdst, slots_9.io.uop.stale_pdst
connect issue_slots[9].uop.ppred_busy, slots_9.io.uop.ppred_busy
connect issue_slots[9].uop.prs3_busy, slots_9.io.uop.prs3_busy
connect issue_slots[9].uop.prs2_busy, slots_9.io.uop.prs2_busy
connect issue_slots[9].uop.prs1_busy, slots_9.io.uop.prs1_busy
connect issue_slots[9].uop.ppred, slots_9.io.uop.ppred
connect issue_slots[9].uop.prs3, slots_9.io.uop.prs3
connect issue_slots[9].uop.prs2, slots_9.io.uop.prs2
connect issue_slots[9].uop.prs1, slots_9.io.uop.prs1
connect issue_slots[9].uop.pdst, slots_9.io.uop.pdst
connect issue_slots[9].uop.rxq_idx, slots_9.io.uop.rxq_idx
connect issue_slots[9].uop.stq_idx, slots_9.io.uop.stq_idx
connect issue_slots[9].uop.ldq_idx, slots_9.io.uop.ldq_idx
connect issue_slots[9].uop.rob_idx, slots_9.io.uop.rob_idx
connect issue_slots[9].uop.csr_addr, slots_9.io.uop.csr_addr
connect issue_slots[9].uop.imm_packed, slots_9.io.uop.imm_packed
connect issue_slots[9].uop.taken, slots_9.io.uop.taken
connect issue_slots[9].uop.pc_lob, slots_9.io.uop.pc_lob
connect issue_slots[9].uop.edge_inst, slots_9.io.uop.edge_inst
connect issue_slots[9].uop.ftq_idx, slots_9.io.uop.ftq_idx
connect issue_slots[9].uop.br_tag, slots_9.io.uop.br_tag
connect issue_slots[9].uop.br_mask, slots_9.io.uop.br_mask
connect issue_slots[9].uop.is_sfb, slots_9.io.uop.is_sfb
connect issue_slots[9].uop.is_jal, slots_9.io.uop.is_jal
connect issue_slots[9].uop.is_jalr, slots_9.io.uop.is_jalr
connect issue_slots[9].uop.is_br, slots_9.io.uop.is_br
connect issue_slots[9].uop.iw_p2_poisoned, slots_9.io.uop.iw_p2_poisoned
connect issue_slots[9].uop.iw_p1_poisoned, slots_9.io.uop.iw_p1_poisoned
connect issue_slots[9].uop.iw_state, slots_9.io.uop.iw_state
connect issue_slots[9].uop.ctrl.is_std, slots_9.io.uop.ctrl.is_std
connect issue_slots[9].uop.ctrl.is_sta, slots_9.io.uop.ctrl.is_sta
connect issue_slots[9].uop.ctrl.is_load, slots_9.io.uop.ctrl.is_load
connect issue_slots[9].uop.ctrl.csr_cmd, slots_9.io.uop.ctrl.csr_cmd
connect issue_slots[9].uop.ctrl.fcn_dw, slots_9.io.uop.ctrl.fcn_dw
connect issue_slots[9].uop.ctrl.op_fcn, slots_9.io.uop.ctrl.op_fcn
connect issue_slots[9].uop.ctrl.imm_sel, slots_9.io.uop.ctrl.imm_sel
connect issue_slots[9].uop.ctrl.op2_sel, slots_9.io.uop.ctrl.op2_sel
connect issue_slots[9].uop.ctrl.op1_sel, slots_9.io.uop.ctrl.op1_sel
connect issue_slots[9].uop.ctrl.br_type, slots_9.io.uop.ctrl.br_type
connect issue_slots[9].uop.fu_code, slots_9.io.uop.fu_code
connect issue_slots[9].uop.iq_type, slots_9.io.uop.iq_type
connect issue_slots[9].uop.debug_pc, slots_9.io.uop.debug_pc
connect issue_slots[9].uop.is_rvc, slots_9.io.uop.is_rvc
connect issue_slots[9].uop.debug_inst, slots_9.io.uop.debug_inst
connect issue_slots[9].uop.inst, slots_9.io.uop.inst
connect issue_slots[9].uop.uopc, slots_9.io.uop.uopc
connect issue_slots[9].out_uop.debug_tsrc, slots_9.io.out_uop.debug_tsrc
connect issue_slots[9].out_uop.debug_fsrc, slots_9.io.out_uop.debug_fsrc
connect issue_slots[9].out_uop.bp_xcpt_if, slots_9.io.out_uop.bp_xcpt_if
connect issue_slots[9].out_uop.bp_debug_if, slots_9.io.out_uop.bp_debug_if
connect issue_slots[9].out_uop.xcpt_ma_if, slots_9.io.out_uop.xcpt_ma_if
connect issue_slots[9].out_uop.xcpt_ae_if, slots_9.io.out_uop.xcpt_ae_if
connect issue_slots[9].out_uop.xcpt_pf_if, slots_9.io.out_uop.xcpt_pf_if
connect issue_slots[9].out_uop.fp_single, slots_9.io.out_uop.fp_single
connect issue_slots[9].out_uop.fp_val, slots_9.io.out_uop.fp_val
connect issue_slots[9].out_uop.frs3_en, slots_9.io.out_uop.frs3_en
connect issue_slots[9].out_uop.lrs2_rtype, slots_9.io.out_uop.lrs2_rtype
connect issue_slots[9].out_uop.lrs1_rtype, slots_9.io.out_uop.lrs1_rtype
connect issue_slots[9].out_uop.dst_rtype, slots_9.io.out_uop.dst_rtype
connect issue_slots[9].out_uop.ldst_val, slots_9.io.out_uop.ldst_val
connect issue_slots[9].out_uop.lrs3, slots_9.io.out_uop.lrs3
connect issue_slots[9].out_uop.lrs2, slots_9.io.out_uop.lrs2
connect issue_slots[9].out_uop.lrs1, slots_9.io.out_uop.lrs1
connect issue_slots[9].out_uop.ldst, slots_9.io.out_uop.ldst
connect issue_slots[9].out_uop.ldst_is_rs1, slots_9.io.out_uop.ldst_is_rs1
connect issue_slots[9].out_uop.flush_on_commit, slots_9.io.out_uop.flush_on_commit
connect issue_slots[9].out_uop.is_unique, slots_9.io.out_uop.is_unique
connect issue_slots[9].out_uop.is_sys_pc2epc, slots_9.io.out_uop.is_sys_pc2epc
connect issue_slots[9].out_uop.uses_stq, slots_9.io.out_uop.uses_stq
connect issue_slots[9].out_uop.uses_ldq, slots_9.io.out_uop.uses_ldq
connect issue_slots[9].out_uop.is_amo, slots_9.io.out_uop.is_amo
connect issue_slots[9].out_uop.is_fencei, slots_9.io.out_uop.is_fencei
connect issue_slots[9].out_uop.is_fence, slots_9.io.out_uop.is_fence
connect issue_slots[9].out_uop.mem_signed, slots_9.io.out_uop.mem_signed
connect issue_slots[9].out_uop.mem_size, slots_9.io.out_uop.mem_size
connect issue_slots[9].out_uop.mem_cmd, slots_9.io.out_uop.mem_cmd
connect issue_slots[9].out_uop.bypassable, slots_9.io.out_uop.bypassable
connect issue_slots[9].out_uop.exc_cause, slots_9.io.out_uop.exc_cause
connect issue_slots[9].out_uop.exception, slots_9.io.out_uop.exception
connect issue_slots[9].out_uop.stale_pdst, slots_9.io.out_uop.stale_pdst
connect issue_slots[9].out_uop.ppred_busy, slots_9.io.out_uop.ppred_busy
connect issue_slots[9].out_uop.prs3_busy, slots_9.io.out_uop.prs3_busy
connect issue_slots[9].out_uop.prs2_busy, slots_9.io.out_uop.prs2_busy
connect issue_slots[9].out_uop.prs1_busy, slots_9.io.out_uop.prs1_busy
connect issue_slots[9].out_uop.ppred, slots_9.io.out_uop.ppred
connect issue_slots[9].out_uop.prs3, slots_9.io.out_uop.prs3
connect issue_slots[9].out_uop.prs2, slots_9.io.out_uop.prs2
connect issue_slots[9].out_uop.prs1, slots_9.io.out_uop.prs1
connect issue_slots[9].out_uop.pdst, slots_9.io.out_uop.pdst
connect issue_slots[9].out_uop.rxq_idx, slots_9.io.out_uop.rxq_idx
connect issue_slots[9].out_uop.stq_idx, slots_9.io.out_uop.stq_idx
connect issue_slots[9].out_uop.ldq_idx, slots_9.io.out_uop.ldq_idx
connect issue_slots[9].out_uop.rob_idx, slots_9.io.out_uop.rob_idx
connect issue_slots[9].out_uop.csr_addr, slots_9.io.out_uop.csr_addr
connect issue_slots[9].out_uop.imm_packed, slots_9.io.out_uop.imm_packed
connect issue_slots[9].out_uop.taken, slots_9.io.out_uop.taken
connect issue_slots[9].out_uop.pc_lob, slots_9.io.out_uop.pc_lob
connect issue_slots[9].out_uop.edge_inst, slots_9.io.out_uop.edge_inst
connect issue_slots[9].out_uop.ftq_idx, slots_9.io.out_uop.ftq_idx
connect issue_slots[9].out_uop.br_tag, slots_9.io.out_uop.br_tag
connect issue_slots[9].out_uop.br_mask, slots_9.io.out_uop.br_mask
connect issue_slots[9].out_uop.is_sfb, slots_9.io.out_uop.is_sfb
connect issue_slots[9].out_uop.is_jal, slots_9.io.out_uop.is_jal
connect issue_slots[9].out_uop.is_jalr, slots_9.io.out_uop.is_jalr
connect issue_slots[9].out_uop.is_br, slots_9.io.out_uop.is_br
connect issue_slots[9].out_uop.iw_p2_poisoned, slots_9.io.out_uop.iw_p2_poisoned
connect issue_slots[9].out_uop.iw_p1_poisoned, slots_9.io.out_uop.iw_p1_poisoned
connect issue_slots[9].out_uop.iw_state, slots_9.io.out_uop.iw_state
connect issue_slots[9].out_uop.ctrl.is_std, slots_9.io.out_uop.ctrl.is_std
connect issue_slots[9].out_uop.ctrl.is_sta, slots_9.io.out_uop.ctrl.is_sta
connect issue_slots[9].out_uop.ctrl.is_load, slots_9.io.out_uop.ctrl.is_load
connect issue_slots[9].out_uop.ctrl.csr_cmd, slots_9.io.out_uop.ctrl.csr_cmd
connect issue_slots[9].out_uop.ctrl.fcn_dw, slots_9.io.out_uop.ctrl.fcn_dw
connect issue_slots[9].out_uop.ctrl.op_fcn, slots_9.io.out_uop.ctrl.op_fcn
connect issue_slots[9].out_uop.ctrl.imm_sel, slots_9.io.out_uop.ctrl.imm_sel
connect issue_slots[9].out_uop.ctrl.op2_sel, slots_9.io.out_uop.ctrl.op2_sel
connect issue_slots[9].out_uop.ctrl.op1_sel, slots_9.io.out_uop.ctrl.op1_sel
connect issue_slots[9].out_uop.ctrl.br_type, slots_9.io.out_uop.ctrl.br_type
connect issue_slots[9].out_uop.fu_code, slots_9.io.out_uop.fu_code
connect issue_slots[9].out_uop.iq_type, slots_9.io.out_uop.iq_type
connect issue_slots[9].out_uop.debug_pc, slots_9.io.out_uop.debug_pc
connect issue_slots[9].out_uop.is_rvc, slots_9.io.out_uop.is_rvc
connect issue_slots[9].out_uop.debug_inst, slots_9.io.out_uop.debug_inst
connect issue_slots[9].out_uop.inst, slots_9.io.out_uop.inst
connect issue_slots[9].out_uop.uopc, slots_9.io.out_uop.uopc
connect slots_9.io.in_uop.bits.debug_tsrc, issue_slots[9].in_uop.bits.debug_tsrc
connect slots_9.io.in_uop.bits.debug_fsrc, issue_slots[9].in_uop.bits.debug_fsrc
connect slots_9.io.in_uop.bits.bp_xcpt_if, issue_slots[9].in_uop.bits.bp_xcpt_if
connect slots_9.io.in_uop.bits.bp_debug_if, issue_slots[9].in_uop.bits.bp_debug_if
connect slots_9.io.in_uop.bits.xcpt_ma_if, issue_slots[9].in_uop.bits.xcpt_ma_if
connect slots_9.io.in_uop.bits.xcpt_ae_if, issue_slots[9].in_uop.bits.xcpt_ae_if
connect slots_9.io.in_uop.bits.xcpt_pf_if, issue_slots[9].in_uop.bits.xcpt_pf_if
connect slots_9.io.in_uop.bits.fp_single, issue_slots[9].in_uop.bits.fp_single
connect slots_9.io.in_uop.bits.fp_val, issue_slots[9].in_uop.bits.fp_val
connect slots_9.io.in_uop.bits.frs3_en, issue_slots[9].in_uop.bits.frs3_en
connect slots_9.io.in_uop.bits.lrs2_rtype, issue_slots[9].in_uop.bits.lrs2_rtype
connect slots_9.io.in_uop.bits.lrs1_rtype, issue_slots[9].in_uop.bits.lrs1_rtype
connect slots_9.io.in_uop.bits.dst_rtype, issue_slots[9].in_uop.bits.dst_rtype
connect slots_9.io.in_uop.bits.ldst_val, issue_slots[9].in_uop.bits.ldst_val
connect slots_9.io.in_uop.bits.lrs3, issue_slots[9].in_uop.bits.lrs3
connect slots_9.io.in_uop.bits.lrs2, issue_slots[9].in_uop.bits.lrs2
connect slots_9.io.in_uop.bits.lrs1, issue_slots[9].in_uop.bits.lrs1
connect slots_9.io.in_uop.bits.ldst, issue_slots[9].in_uop.bits.ldst
connect slots_9.io.in_uop.bits.ldst_is_rs1, issue_slots[9].in_uop.bits.ldst_is_rs1
connect slots_9.io.in_uop.bits.flush_on_commit, issue_slots[9].in_uop.bits.flush_on_commit
connect slots_9.io.in_uop.bits.is_unique, issue_slots[9].in_uop.bits.is_unique
connect slots_9.io.in_uop.bits.is_sys_pc2epc, issue_slots[9].in_uop.bits.is_sys_pc2epc
connect slots_9.io.in_uop.bits.uses_stq, issue_slots[9].in_uop.bits.uses_stq
connect slots_9.io.in_uop.bits.uses_ldq, issue_slots[9].in_uop.bits.uses_ldq
connect slots_9.io.in_uop.bits.is_amo, issue_slots[9].in_uop.bits.is_amo
connect slots_9.io.in_uop.bits.is_fencei, issue_slots[9].in_uop.bits.is_fencei
connect slots_9.io.in_uop.bits.is_fence, issue_slots[9].in_uop.bits.is_fence
connect slots_9.io.in_uop.bits.mem_signed, issue_slots[9].in_uop.bits.mem_signed
connect slots_9.io.in_uop.bits.mem_size, issue_slots[9].in_uop.bits.mem_size
connect slots_9.io.in_uop.bits.mem_cmd, issue_slots[9].in_uop.bits.mem_cmd
connect slots_9.io.in_uop.bits.bypassable, issue_slots[9].in_uop.bits.bypassable
connect slots_9.io.in_uop.bits.exc_cause, issue_slots[9].in_uop.bits.exc_cause
connect slots_9.io.in_uop.bits.exception, issue_slots[9].in_uop.bits.exception
connect slots_9.io.in_uop.bits.stale_pdst, issue_slots[9].in_uop.bits.stale_pdst
connect slots_9.io.in_uop.bits.ppred_busy, issue_slots[9].in_uop.bits.ppred_busy
connect slots_9.io.in_uop.bits.prs3_busy, issue_slots[9].in_uop.bits.prs3_busy
connect slots_9.io.in_uop.bits.prs2_busy, issue_slots[9].in_uop.bits.prs2_busy
connect slots_9.io.in_uop.bits.prs1_busy, issue_slots[9].in_uop.bits.prs1_busy
connect slots_9.io.in_uop.bits.ppred, issue_slots[9].in_uop.bits.ppred
connect slots_9.io.in_uop.bits.prs3, issue_slots[9].in_uop.bits.prs3
connect slots_9.io.in_uop.bits.prs2, issue_slots[9].in_uop.bits.prs2
connect slots_9.io.in_uop.bits.prs1, issue_slots[9].in_uop.bits.prs1
connect slots_9.io.in_uop.bits.pdst, issue_slots[9].in_uop.bits.pdst
connect slots_9.io.in_uop.bits.rxq_idx, issue_slots[9].in_uop.bits.rxq_idx
connect slots_9.io.in_uop.bits.stq_idx, issue_slots[9].in_uop.bits.stq_idx
connect slots_9.io.in_uop.bits.ldq_idx, issue_slots[9].in_uop.bits.ldq_idx
connect slots_9.io.in_uop.bits.rob_idx, issue_slots[9].in_uop.bits.rob_idx
connect slots_9.io.in_uop.bits.csr_addr, issue_slots[9].in_uop.bits.csr_addr
connect slots_9.io.in_uop.bits.imm_packed, issue_slots[9].in_uop.bits.imm_packed
connect slots_9.io.in_uop.bits.taken, issue_slots[9].in_uop.bits.taken
connect slots_9.io.in_uop.bits.pc_lob, issue_slots[9].in_uop.bits.pc_lob
connect slots_9.io.in_uop.bits.edge_inst, issue_slots[9].in_uop.bits.edge_inst
connect slots_9.io.in_uop.bits.ftq_idx, issue_slots[9].in_uop.bits.ftq_idx
connect slots_9.io.in_uop.bits.br_tag, issue_slots[9].in_uop.bits.br_tag
connect slots_9.io.in_uop.bits.br_mask, issue_slots[9].in_uop.bits.br_mask
connect slots_9.io.in_uop.bits.is_sfb, issue_slots[9].in_uop.bits.is_sfb
connect slots_9.io.in_uop.bits.is_jal, issue_slots[9].in_uop.bits.is_jal
connect slots_9.io.in_uop.bits.is_jalr, issue_slots[9].in_uop.bits.is_jalr
connect slots_9.io.in_uop.bits.is_br, issue_slots[9].in_uop.bits.is_br
connect slots_9.io.in_uop.bits.iw_p2_poisoned, issue_slots[9].in_uop.bits.iw_p2_poisoned
connect slots_9.io.in_uop.bits.iw_p1_poisoned, issue_slots[9].in_uop.bits.iw_p1_poisoned
connect slots_9.io.in_uop.bits.iw_state, issue_slots[9].in_uop.bits.iw_state
connect slots_9.io.in_uop.bits.ctrl.is_std, issue_slots[9].in_uop.bits.ctrl.is_std
connect slots_9.io.in_uop.bits.ctrl.is_sta, issue_slots[9].in_uop.bits.ctrl.is_sta
connect slots_9.io.in_uop.bits.ctrl.is_load, issue_slots[9].in_uop.bits.ctrl.is_load
connect slots_9.io.in_uop.bits.ctrl.csr_cmd, issue_slots[9].in_uop.bits.ctrl.csr_cmd
connect slots_9.io.in_uop.bits.ctrl.fcn_dw, issue_slots[9].in_uop.bits.ctrl.fcn_dw
connect slots_9.io.in_uop.bits.ctrl.op_fcn, issue_slots[9].in_uop.bits.ctrl.op_fcn
connect slots_9.io.in_uop.bits.ctrl.imm_sel, issue_slots[9].in_uop.bits.ctrl.imm_sel
connect slots_9.io.in_uop.bits.ctrl.op2_sel, issue_slots[9].in_uop.bits.ctrl.op2_sel
connect slots_9.io.in_uop.bits.ctrl.op1_sel, issue_slots[9].in_uop.bits.ctrl.op1_sel
connect slots_9.io.in_uop.bits.ctrl.br_type, issue_slots[9].in_uop.bits.ctrl.br_type
connect slots_9.io.in_uop.bits.fu_code, issue_slots[9].in_uop.bits.fu_code
connect slots_9.io.in_uop.bits.iq_type, issue_slots[9].in_uop.bits.iq_type
connect slots_9.io.in_uop.bits.debug_pc, issue_slots[9].in_uop.bits.debug_pc
connect slots_9.io.in_uop.bits.is_rvc, issue_slots[9].in_uop.bits.is_rvc
connect slots_9.io.in_uop.bits.debug_inst, issue_slots[9].in_uop.bits.debug_inst
connect slots_9.io.in_uop.bits.inst, issue_slots[9].in_uop.bits.inst
connect slots_9.io.in_uop.bits.uopc, issue_slots[9].in_uop.bits.uopc
connect slots_9.io.in_uop.valid, issue_slots[9].in_uop.valid
connect slots_9.io.spec_ld_wakeup[0].bits, issue_slots[9].spec_ld_wakeup[0].bits
connect slots_9.io.spec_ld_wakeup[0].valid, issue_slots[9].spec_ld_wakeup[0].valid
connect slots_9.io.pred_wakeup_port.bits, issue_slots[9].pred_wakeup_port.bits
connect slots_9.io.pred_wakeup_port.valid, issue_slots[9].pred_wakeup_port.valid
connect slots_9.io.wakeup_ports[0].bits.poisoned, issue_slots[9].wakeup_ports[0].bits.poisoned
connect slots_9.io.wakeup_ports[0].bits.pdst, issue_slots[9].wakeup_ports[0].bits.pdst
connect slots_9.io.wakeup_ports[0].valid, issue_slots[9].wakeup_ports[0].valid
connect slots_9.io.wakeup_ports[1].bits.poisoned, issue_slots[9].wakeup_ports[1].bits.poisoned
connect slots_9.io.wakeup_ports[1].bits.pdst, issue_slots[9].wakeup_ports[1].bits.pdst
connect slots_9.io.wakeup_ports[1].valid, issue_slots[9].wakeup_ports[1].valid
connect slots_9.io.ldspec_miss, issue_slots[9].ldspec_miss
connect slots_9.io.clear, issue_slots[9].clear
connect slots_9.io.kill, issue_slots[9].kill
connect slots_9.io.brupdate.b2.target_offset, issue_slots[9].brupdate.b2.target_offset
connect slots_9.io.brupdate.b2.jalr_target, issue_slots[9].brupdate.b2.jalr_target
connect slots_9.io.brupdate.b2.pc_sel, issue_slots[9].brupdate.b2.pc_sel
connect slots_9.io.brupdate.b2.cfi_type, issue_slots[9].brupdate.b2.cfi_type
connect slots_9.io.brupdate.b2.taken, issue_slots[9].brupdate.b2.taken
connect slots_9.io.brupdate.b2.mispredict, issue_slots[9].brupdate.b2.mispredict
connect slots_9.io.brupdate.b2.valid, issue_slots[9].brupdate.b2.valid
connect slots_9.io.brupdate.b2.uop.debug_tsrc, issue_slots[9].brupdate.b2.uop.debug_tsrc
connect slots_9.io.brupdate.b2.uop.debug_fsrc, issue_slots[9].brupdate.b2.uop.debug_fsrc
connect slots_9.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[9].brupdate.b2.uop.bp_xcpt_if
connect slots_9.io.brupdate.b2.uop.bp_debug_if, issue_slots[9].brupdate.b2.uop.bp_debug_if
connect slots_9.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[9].brupdate.b2.uop.xcpt_ma_if
connect slots_9.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[9].brupdate.b2.uop.xcpt_ae_if
connect slots_9.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[9].brupdate.b2.uop.xcpt_pf_if
connect slots_9.io.brupdate.b2.uop.fp_single, issue_slots[9].brupdate.b2.uop.fp_single
connect slots_9.io.brupdate.b2.uop.fp_val, issue_slots[9].brupdate.b2.uop.fp_val
connect slots_9.io.brupdate.b2.uop.frs3_en, issue_slots[9].brupdate.b2.uop.frs3_en
connect slots_9.io.brupdate.b2.uop.lrs2_rtype, issue_slots[9].brupdate.b2.uop.lrs2_rtype
connect slots_9.io.brupdate.b2.uop.lrs1_rtype, issue_slots[9].brupdate.b2.uop.lrs1_rtype
connect slots_9.io.brupdate.b2.uop.dst_rtype, issue_slots[9].brupdate.b2.uop.dst_rtype
connect slots_9.io.brupdate.b2.uop.ldst_val, issue_slots[9].brupdate.b2.uop.ldst_val
connect slots_9.io.brupdate.b2.uop.lrs3, issue_slots[9].brupdate.b2.uop.lrs3
connect slots_9.io.brupdate.b2.uop.lrs2, issue_slots[9].brupdate.b2.uop.lrs2
connect slots_9.io.brupdate.b2.uop.lrs1, issue_slots[9].brupdate.b2.uop.lrs1
connect slots_9.io.brupdate.b2.uop.ldst, issue_slots[9].brupdate.b2.uop.ldst
connect slots_9.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[9].brupdate.b2.uop.ldst_is_rs1
connect slots_9.io.brupdate.b2.uop.flush_on_commit, issue_slots[9].brupdate.b2.uop.flush_on_commit
connect slots_9.io.brupdate.b2.uop.is_unique, issue_slots[9].brupdate.b2.uop.is_unique
connect slots_9.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[9].brupdate.b2.uop.is_sys_pc2epc
connect slots_9.io.brupdate.b2.uop.uses_stq, issue_slots[9].brupdate.b2.uop.uses_stq
connect slots_9.io.brupdate.b2.uop.uses_ldq, issue_slots[9].brupdate.b2.uop.uses_ldq
connect slots_9.io.brupdate.b2.uop.is_amo, issue_slots[9].brupdate.b2.uop.is_amo
connect slots_9.io.brupdate.b2.uop.is_fencei, issue_slots[9].brupdate.b2.uop.is_fencei
connect slots_9.io.brupdate.b2.uop.is_fence, issue_slots[9].brupdate.b2.uop.is_fence
connect slots_9.io.brupdate.b2.uop.mem_signed, issue_slots[9].brupdate.b2.uop.mem_signed
connect slots_9.io.brupdate.b2.uop.mem_size, issue_slots[9].brupdate.b2.uop.mem_size
connect slots_9.io.brupdate.b2.uop.mem_cmd, issue_slots[9].brupdate.b2.uop.mem_cmd
connect slots_9.io.brupdate.b2.uop.bypassable, issue_slots[9].brupdate.b2.uop.bypassable
connect slots_9.io.brupdate.b2.uop.exc_cause, issue_slots[9].brupdate.b2.uop.exc_cause
connect slots_9.io.brupdate.b2.uop.exception, issue_slots[9].brupdate.b2.uop.exception
connect slots_9.io.brupdate.b2.uop.stale_pdst, issue_slots[9].brupdate.b2.uop.stale_pdst
connect slots_9.io.brupdate.b2.uop.ppred_busy, issue_slots[9].brupdate.b2.uop.ppred_busy
connect slots_9.io.brupdate.b2.uop.prs3_busy, issue_slots[9].brupdate.b2.uop.prs3_busy
connect slots_9.io.brupdate.b2.uop.prs2_busy, issue_slots[9].brupdate.b2.uop.prs2_busy
connect slots_9.io.brupdate.b2.uop.prs1_busy, issue_slots[9].brupdate.b2.uop.prs1_busy
connect slots_9.io.brupdate.b2.uop.ppred, issue_slots[9].brupdate.b2.uop.ppred
connect slots_9.io.brupdate.b2.uop.prs3, issue_slots[9].brupdate.b2.uop.prs3
connect slots_9.io.brupdate.b2.uop.prs2, issue_slots[9].brupdate.b2.uop.prs2
connect slots_9.io.brupdate.b2.uop.prs1, issue_slots[9].brupdate.b2.uop.prs1
connect slots_9.io.brupdate.b2.uop.pdst, issue_slots[9].brupdate.b2.uop.pdst
connect slots_9.io.brupdate.b2.uop.rxq_idx, issue_slots[9].brupdate.b2.uop.rxq_idx
connect slots_9.io.brupdate.b2.uop.stq_idx, issue_slots[9].brupdate.b2.uop.stq_idx
connect slots_9.io.brupdate.b2.uop.ldq_idx, issue_slots[9].brupdate.b2.uop.ldq_idx
connect slots_9.io.brupdate.b2.uop.rob_idx, issue_slots[9].brupdate.b2.uop.rob_idx
connect slots_9.io.brupdate.b2.uop.csr_addr, issue_slots[9].brupdate.b2.uop.csr_addr
connect slots_9.io.brupdate.b2.uop.imm_packed, issue_slots[9].brupdate.b2.uop.imm_packed
connect slots_9.io.brupdate.b2.uop.taken, issue_slots[9].brupdate.b2.uop.taken
connect slots_9.io.brupdate.b2.uop.pc_lob, issue_slots[9].brupdate.b2.uop.pc_lob
connect slots_9.io.brupdate.b2.uop.edge_inst, issue_slots[9].brupdate.b2.uop.edge_inst
connect slots_9.io.brupdate.b2.uop.ftq_idx, issue_slots[9].brupdate.b2.uop.ftq_idx
connect slots_9.io.brupdate.b2.uop.br_tag, issue_slots[9].brupdate.b2.uop.br_tag
connect slots_9.io.brupdate.b2.uop.br_mask, issue_slots[9].brupdate.b2.uop.br_mask
connect slots_9.io.brupdate.b2.uop.is_sfb, issue_slots[9].brupdate.b2.uop.is_sfb
connect slots_9.io.brupdate.b2.uop.is_jal, issue_slots[9].brupdate.b2.uop.is_jal
connect slots_9.io.brupdate.b2.uop.is_jalr, issue_slots[9].brupdate.b2.uop.is_jalr
connect slots_9.io.brupdate.b2.uop.is_br, issue_slots[9].brupdate.b2.uop.is_br
connect slots_9.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[9].brupdate.b2.uop.iw_p2_poisoned
connect slots_9.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[9].brupdate.b2.uop.iw_p1_poisoned
connect slots_9.io.brupdate.b2.uop.iw_state, issue_slots[9].brupdate.b2.uop.iw_state
connect slots_9.io.brupdate.b2.uop.ctrl.is_std, issue_slots[9].brupdate.b2.uop.ctrl.is_std
connect slots_9.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[9].brupdate.b2.uop.ctrl.is_sta
connect slots_9.io.brupdate.b2.uop.ctrl.is_load, issue_slots[9].brupdate.b2.uop.ctrl.is_load
connect slots_9.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[9].brupdate.b2.uop.ctrl.csr_cmd
connect slots_9.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[9].brupdate.b2.uop.ctrl.fcn_dw
connect slots_9.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[9].brupdate.b2.uop.ctrl.op_fcn
connect slots_9.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[9].brupdate.b2.uop.ctrl.imm_sel
connect slots_9.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[9].brupdate.b2.uop.ctrl.op2_sel
connect slots_9.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[9].brupdate.b2.uop.ctrl.op1_sel
connect slots_9.io.brupdate.b2.uop.ctrl.br_type, issue_slots[9].brupdate.b2.uop.ctrl.br_type
connect slots_9.io.brupdate.b2.uop.fu_code, issue_slots[9].brupdate.b2.uop.fu_code
connect slots_9.io.brupdate.b2.uop.iq_type, issue_slots[9].brupdate.b2.uop.iq_type
connect slots_9.io.brupdate.b2.uop.debug_pc, issue_slots[9].brupdate.b2.uop.debug_pc
connect slots_9.io.brupdate.b2.uop.is_rvc, issue_slots[9].brupdate.b2.uop.is_rvc
connect slots_9.io.brupdate.b2.uop.debug_inst, issue_slots[9].brupdate.b2.uop.debug_inst
connect slots_9.io.brupdate.b2.uop.inst, issue_slots[9].brupdate.b2.uop.inst
connect slots_9.io.brupdate.b2.uop.uopc, issue_slots[9].brupdate.b2.uop.uopc
connect slots_9.io.brupdate.b1.mispredict_mask, issue_slots[9].brupdate.b1.mispredict_mask
connect slots_9.io.brupdate.b1.resolve_mask, issue_slots[9].brupdate.b1.resolve_mask
connect slots_9.io.grant, issue_slots[9].grant
connect issue_slots[9].request_hp, slots_9.io.request_hp
connect issue_slots[9].request, slots_9.io.request
connect issue_slots[9].will_be_valid, slots_9.io.will_be_valid
connect issue_slots[9].valid, slots_9.io.valid
connect issue_slots[10].debug.state, slots_10.io.debug.state
connect issue_slots[10].debug.ppred, slots_10.io.debug.ppred
connect issue_slots[10].debug.p3, slots_10.io.debug.p3
connect issue_slots[10].debug.p2, slots_10.io.debug.p2
connect issue_slots[10].debug.p1, slots_10.io.debug.p1
connect issue_slots[10].uop.debug_tsrc, slots_10.io.uop.debug_tsrc
connect issue_slots[10].uop.debug_fsrc, slots_10.io.uop.debug_fsrc
connect issue_slots[10].uop.bp_xcpt_if, slots_10.io.uop.bp_xcpt_if
connect issue_slots[10].uop.bp_debug_if, slots_10.io.uop.bp_debug_if
connect issue_slots[10].uop.xcpt_ma_if, slots_10.io.uop.xcpt_ma_if
connect issue_slots[10].uop.xcpt_ae_if, slots_10.io.uop.xcpt_ae_if
connect issue_slots[10].uop.xcpt_pf_if, slots_10.io.uop.xcpt_pf_if
connect issue_slots[10].uop.fp_single, slots_10.io.uop.fp_single
connect issue_slots[10].uop.fp_val, slots_10.io.uop.fp_val
connect issue_slots[10].uop.frs3_en, slots_10.io.uop.frs3_en
connect issue_slots[10].uop.lrs2_rtype, slots_10.io.uop.lrs2_rtype
connect issue_slots[10].uop.lrs1_rtype, slots_10.io.uop.lrs1_rtype
connect issue_slots[10].uop.dst_rtype, slots_10.io.uop.dst_rtype
connect issue_slots[10].uop.ldst_val, slots_10.io.uop.ldst_val
connect issue_slots[10].uop.lrs3, slots_10.io.uop.lrs3
connect issue_slots[10].uop.lrs2, slots_10.io.uop.lrs2
connect issue_slots[10].uop.lrs1, slots_10.io.uop.lrs1
connect issue_slots[10].uop.ldst, slots_10.io.uop.ldst
connect issue_slots[10].uop.ldst_is_rs1, slots_10.io.uop.ldst_is_rs1
connect issue_slots[10].uop.flush_on_commit, slots_10.io.uop.flush_on_commit
connect issue_slots[10].uop.is_unique, slots_10.io.uop.is_unique
connect issue_slots[10].uop.is_sys_pc2epc, slots_10.io.uop.is_sys_pc2epc
connect issue_slots[10].uop.uses_stq, slots_10.io.uop.uses_stq
connect issue_slots[10].uop.uses_ldq, slots_10.io.uop.uses_ldq
connect issue_slots[10].uop.is_amo, slots_10.io.uop.is_amo
connect issue_slots[10].uop.is_fencei, slots_10.io.uop.is_fencei
connect issue_slots[10].uop.is_fence, slots_10.io.uop.is_fence
connect issue_slots[10].uop.mem_signed, slots_10.io.uop.mem_signed
connect issue_slots[10].uop.mem_size, slots_10.io.uop.mem_size
connect issue_slots[10].uop.mem_cmd, slots_10.io.uop.mem_cmd
connect issue_slots[10].uop.bypassable, slots_10.io.uop.bypassable
connect issue_slots[10].uop.exc_cause, slots_10.io.uop.exc_cause
connect issue_slots[10].uop.exception, slots_10.io.uop.exception
connect issue_slots[10].uop.stale_pdst, slots_10.io.uop.stale_pdst
connect issue_slots[10].uop.ppred_busy, slots_10.io.uop.ppred_busy
connect issue_slots[10].uop.prs3_busy, slots_10.io.uop.prs3_busy
connect issue_slots[10].uop.prs2_busy, slots_10.io.uop.prs2_busy
connect issue_slots[10].uop.prs1_busy, slots_10.io.uop.prs1_busy
connect issue_slots[10].uop.ppred, slots_10.io.uop.ppred
connect issue_slots[10].uop.prs3, slots_10.io.uop.prs3
connect issue_slots[10].uop.prs2, slots_10.io.uop.prs2
connect issue_slots[10].uop.prs1, slots_10.io.uop.prs1
connect issue_slots[10].uop.pdst, slots_10.io.uop.pdst
connect issue_slots[10].uop.rxq_idx, slots_10.io.uop.rxq_idx
connect issue_slots[10].uop.stq_idx, slots_10.io.uop.stq_idx
connect issue_slots[10].uop.ldq_idx, slots_10.io.uop.ldq_idx
connect issue_slots[10].uop.rob_idx, slots_10.io.uop.rob_idx
connect issue_slots[10].uop.csr_addr, slots_10.io.uop.csr_addr
connect issue_slots[10].uop.imm_packed, slots_10.io.uop.imm_packed
connect issue_slots[10].uop.taken, slots_10.io.uop.taken
connect issue_slots[10].uop.pc_lob, slots_10.io.uop.pc_lob
connect issue_slots[10].uop.edge_inst, slots_10.io.uop.edge_inst
connect issue_slots[10].uop.ftq_idx, slots_10.io.uop.ftq_idx
connect issue_slots[10].uop.br_tag, slots_10.io.uop.br_tag
connect issue_slots[10].uop.br_mask, slots_10.io.uop.br_mask
connect issue_slots[10].uop.is_sfb, slots_10.io.uop.is_sfb
connect issue_slots[10].uop.is_jal, slots_10.io.uop.is_jal
connect issue_slots[10].uop.is_jalr, slots_10.io.uop.is_jalr
connect issue_slots[10].uop.is_br, slots_10.io.uop.is_br
connect issue_slots[10].uop.iw_p2_poisoned, slots_10.io.uop.iw_p2_poisoned
connect issue_slots[10].uop.iw_p1_poisoned, slots_10.io.uop.iw_p1_poisoned
connect issue_slots[10].uop.iw_state, slots_10.io.uop.iw_state
connect issue_slots[10].uop.ctrl.is_std, slots_10.io.uop.ctrl.is_std
connect issue_slots[10].uop.ctrl.is_sta, slots_10.io.uop.ctrl.is_sta
connect issue_slots[10].uop.ctrl.is_load, slots_10.io.uop.ctrl.is_load
connect issue_slots[10].uop.ctrl.csr_cmd, slots_10.io.uop.ctrl.csr_cmd
connect issue_slots[10].uop.ctrl.fcn_dw, slots_10.io.uop.ctrl.fcn_dw
connect issue_slots[10].uop.ctrl.op_fcn, slots_10.io.uop.ctrl.op_fcn
connect issue_slots[10].uop.ctrl.imm_sel, slots_10.io.uop.ctrl.imm_sel
connect issue_slots[10].uop.ctrl.op2_sel, slots_10.io.uop.ctrl.op2_sel
connect issue_slots[10].uop.ctrl.op1_sel, slots_10.io.uop.ctrl.op1_sel
connect issue_slots[10].uop.ctrl.br_type, slots_10.io.uop.ctrl.br_type
connect issue_slots[10].uop.fu_code, slots_10.io.uop.fu_code
connect issue_slots[10].uop.iq_type, slots_10.io.uop.iq_type
connect issue_slots[10].uop.debug_pc, slots_10.io.uop.debug_pc
connect issue_slots[10].uop.is_rvc, slots_10.io.uop.is_rvc
connect issue_slots[10].uop.debug_inst, slots_10.io.uop.debug_inst
connect issue_slots[10].uop.inst, slots_10.io.uop.inst
connect issue_slots[10].uop.uopc, slots_10.io.uop.uopc
connect issue_slots[10].out_uop.debug_tsrc, slots_10.io.out_uop.debug_tsrc
connect issue_slots[10].out_uop.debug_fsrc, slots_10.io.out_uop.debug_fsrc
connect issue_slots[10].out_uop.bp_xcpt_if, slots_10.io.out_uop.bp_xcpt_if
connect issue_slots[10].out_uop.bp_debug_if, slots_10.io.out_uop.bp_debug_if
connect issue_slots[10].out_uop.xcpt_ma_if, slots_10.io.out_uop.xcpt_ma_if
connect issue_slots[10].out_uop.xcpt_ae_if, slots_10.io.out_uop.xcpt_ae_if
connect issue_slots[10].out_uop.xcpt_pf_if, slots_10.io.out_uop.xcpt_pf_if
connect issue_slots[10].out_uop.fp_single, slots_10.io.out_uop.fp_single
connect issue_slots[10].out_uop.fp_val, slots_10.io.out_uop.fp_val
connect issue_slots[10].out_uop.frs3_en, slots_10.io.out_uop.frs3_en
connect issue_slots[10].out_uop.lrs2_rtype, slots_10.io.out_uop.lrs2_rtype
connect issue_slots[10].out_uop.lrs1_rtype, slots_10.io.out_uop.lrs1_rtype
connect issue_slots[10].out_uop.dst_rtype, slots_10.io.out_uop.dst_rtype
connect issue_slots[10].out_uop.ldst_val, slots_10.io.out_uop.ldst_val
connect issue_slots[10].out_uop.lrs3, slots_10.io.out_uop.lrs3
connect issue_slots[10].out_uop.lrs2, slots_10.io.out_uop.lrs2
connect issue_slots[10].out_uop.lrs1, slots_10.io.out_uop.lrs1
connect issue_slots[10].out_uop.ldst, slots_10.io.out_uop.ldst
connect issue_slots[10].out_uop.ldst_is_rs1, slots_10.io.out_uop.ldst_is_rs1
connect issue_slots[10].out_uop.flush_on_commit, slots_10.io.out_uop.flush_on_commit
connect issue_slots[10].out_uop.is_unique, slots_10.io.out_uop.is_unique
connect issue_slots[10].out_uop.is_sys_pc2epc, slots_10.io.out_uop.is_sys_pc2epc
connect issue_slots[10].out_uop.uses_stq, slots_10.io.out_uop.uses_stq
connect issue_slots[10].out_uop.uses_ldq, slots_10.io.out_uop.uses_ldq
connect issue_slots[10].out_uop.is_amo, slots_10.io.out_uop.is_amo
connect issue_slots[10].out_uop.is_fencei, slots_10.io.out_uop.is_fencei
connect issue_slots[10].out_uop.is_fence, slots_10.io.out_uop.is_fence
connect issue_slots[10].out_uop.mem_signed, slots_10.io.out_uop.mem_signed
connect issue_slots[10].out_uop.mem_size, slots_10.io.out_uop.mem_size
connect issue_slots[10].out_uop.mem_cmd, slots_10.io.out_uop.mem_cmd
connect issue_slots[10].out_uop.bypassable, slots_10.io.out_uop.bypassable
connect issue_slots[10].out_uop.exc_cause, slots_10.io.out_uop.exc_cause
connect issue_slots[10].out_uop.exception, slots_10.io.out_uop.exception
connect issue_slots[10].out_uop.stale_pdst, slots_10.io.out_uop.stale_pdst
connect issue_slots[10].out_uop.ppred_busy, slots_10.io.out_uop.ppred_busy
connect issue_slots[10].out_uop.prs3_busy, slots_10.io.out_uop.prs3_busy
connect issue_slots[10].out_uop.prs2_busy, slots_10.io.out_uop.prs2_busy
connect issue_slots[10].out_uop.prs1_busy, slots_10.io.out_uop.prs1_busy
connect issue_slots[10].out_uop.ppred, slots_10.io.out_uop.ppred
connect issue_slots[10].out_uop.prs3, slots_10.io.out_uop.prs3
connect issue_slots[10].out_uop.prs2, slots_10.io.out_uop.prs2
connect issue_slots[10].out_uop.prs1, slots_10.io.out_uop.prs1
connect issue_slots[10].out_uop.pdst, slots_10.io.out_uop.pdst
connect issue_slots[10].out_uop.rxq_idx, slots_10.io.out_uop.rxq_idx
connect issue_slots[10].out_uop.stq_idx, slots_10.io.out_uop.stq_idx
connect issue_slots[10].out_uop.ldq_idx, slots_10.io.out_uop.ldq_idx
connect issue_slots[10].out_uop.rob_idx, slots_10.io.out_uop.rob_idx
connect issue_slots[10].out_uop.csr_addr, slots_10.io.out_uop.csr_addr
connect issue_slots[10].out_uop.imm_packed, slots_10.io.out_uop.imm_packed
connect issue_slots[10].out_uop.taken, slots_10.io.out_uop.taken
connect issue_slots[10].out_uop.pc_lob, slots_10.io.out_uop.pc_lob
connect issue_slots[10].out_uop.edge_inst, slots_10.io.out_uop.edge_inst
connect issue_slots[10].out_uop.ftq_idx, slots_10.io.out_uop.ftq_idx
connect issue_slots[10].out_uop.br_tag, slots_10.io.out_uop.br_tag
connect issue_slots[10].out_uop.br_mask, slots_10.io.out_uop.br_mask
connect issue_slots[10].out_uop.is_sfb, slots_10.io.out_uop.is_sfb
connect issue_slots[10].out_uop.is_jal, slots_10.io.out_uop.is_jal
connect issue_slots[10].out_uop.is_jalr, slots_10.io.out_uop.is_jalr
connect issue_slots[10].out_uop.is_br, slots_10.io.out_uop.is_br
connect issue_slots[10].out_uop.iw_p2_poisoned, slots_10.io.out_uop.iw_p2_poisoned
connect issue_slots[10].out_uop.iw_p1_poisoned, slots_10.io.out_uop.iw_p1_poisoned
connect issue_slots[10].out_uop.iw_state, slots_10.io.out_uop.iw_state
connect issue_slots[10].out_uop.ctrl.is_std, slots_10.io.out_uop.ctrl.is_std
connect issue_slots[10].out_uop.ctrl.is_sta, slots_10.io.out_uop.ctrl.is_sta
connect issue_slots[10].out_uop.ctrl.is_load, slots_10.io.out_uop.ctrl.is_load
connect issue_slots[10].out_uop.ctrl.csr_cmd, slots_10.io.out_uop.ctrl.csr_cmd
connect issue_slots[10].out_uop.ctrl.fcn_dw, slots_10.io.out_uop.ctrl.fcn_dw
connect issue_slots[10].out_uop.ctrl.op_fcn, slots_10.io.out_uop.ctrl.op_fcn
connect issue_slots[10].out_uop.ctrl.imm_sel, slots_10.io.out_uop.ctrl.imm_sel
connect issue_slots[10].out_uop.ctrl.op2_sel, slots_10.io.out_uop.ctrl.op2_sel
connect issue_slots[10].out_uop.ctrl.op1_sel, slots_10.io.out_uop.ctrl.op1_sel
connect issue_slots[10].out_uop.ctrl.br_type, slots_10.io.out_uop.ctrl.br_type
connect issue_slots[10].out_uop.fu_code, slots_10.io.out_uop.fu_code
connect issue_slots[10].out_uop.iq_type, slots_10.io.out_uop.iq_type
connect issue_slots[10].out_uop.debug_pc, slots_10.io.out_uop.debug_pc
connect issue_slots[10].out_uop.is_rvc, slots_10.io.out_uop.is_rvc
connect issue_slots[10].out_uop.debug_inst, slots_10.io.out_uop.debug_inst
connect issue_slots[10].out_uop.inst, slots_10.io.out_uop.inst
connect issue_slots[10].out_uop.uopc, slots_10.io.out_uop.uopc
connect slots_10.io.in_uop.bits.debug_tsrc, issue_slots[10].in_uop.bits.debug_tsrc
connect slots_10.io.in_uop.bits.debug_fsrc, issue_slots[10].in_uop.bits.debug_fsrc
connect slots_10.io.in_uop.bits.bp_xcpt_if, issue_slots[10].in_uop.bits.bp_xcpt_if
connect slots_10.io.in_uop.bits.bp_debug_if, issue_slots[10].in_uop.bits.bp_debug_if
connect slots_10.io.in_uop.bits.xcpt_ma_if, issue_slots[10].in_uop.bits.xcpt_ma_if
connect slots_10.io.in_uop.bits.xcpt_ae_if, issue_slots[10].in_uop.bits.xcpt_ae_if
connect slots_10.io.in_uop.bits.xcpt_pf_if, issue_slots[10].in_uop.bits.xcpt_pf_if
connect slots_10.io.in_uop.bits.fp_single, issue_slots[10].in_uop.bits.fp_single
connect slots_10.io.in_uop.bits.fp_val, issue_slots[10].in_uop.bits.fp_val
connect slots_10.io.in_uop.bits.frs3_en, issue_slots[10].in_uop.bits.frs3_en
connect slots_10.io.in_uop.bits.lrs2_rtype, issue_slots[10].in_uop.bits.lrs2_rtype
connect slots_10.io.in_uop.bits.lrs1_rtype, issue_slots[10].in_uop.bits.lrs1_rtype
connect slots_10.io.in_uop.bits.dst_rtype, issue_slots[10].in_uop.bits.dst_rtype
connect slots_10.io.in_uop.bits.ldst_val, issue_slots[10].in_uop.bits.ldst_val
connect slots_10.io.in_uop.bits.lrs3, issue_slots[10].in_uop.bits.lrs3
connect slots_10.io.in_uop.bits.lrs2, issue_slots[10].in_uop.bits.lrs2
connect slots_10.io.in_uop.bits.lrs1, issue_slots[10].in_uop.bits.lrs1
connect slots_10.io.in_uop.bits.ldst, issue_slots[10].in_uop.bits.ldst
connect slots_10.io.in_uop.bits.ldst_is_rs1, issue_slots[10].in_uop.bits.ldst_is_rs1
connect slots_10.io.in_uop.bits.flush_on_commit, issue_slots[10].in_uop.bits.flush_on_commit
connect slots_10.io.in_uop.bits.is_unique, issue_slots[10].in_uop.bits.is_unique
connect slots_10.io.in_uop.bits.is_sys_pc2epc, issue_slots[10].in_uop.bits.is_sys_pc2epc
connect slots_10.io.in_uop.bits.uses_stq, issue_slots[10].in_uop.bits.uses_stq
connect slots_10.io.in_uop.bits.uses_ldq, issue_slots[10].in_uop.bits.uses_ldq
connect slots_10.io.in_uop.bits.is_amo, issue_slots[10].in_uop.bits.is_amo
connect slots_10.io.in_uop.bits.is_fencei, issue_slots[10].in_uop.bits.is_fencei
connect slots_10.io.in_uop.bits.is_fence, issue_slots[10].in_uop.bits.is_fence
connect slots_10.io.in_uop.bits.mem_signed, issue_slots[10].in_uop.bits.mem_signed
connect slots_10.io.in_uop.bits.mem_size, issue_slots[10].in_uop.bits.mem_size
connect slots_10.io.in_uop.bits.mem_cmd, issue_slots[10].in_uop.bits.mem_cmd
connect slots_10.io.in_uop.bits.bypassable, issue_slots[10].in_uop.bits.bypassable
connect slots_10.io.in_uop.bits.exc_cause, issue_slots[10].in_uop.bits.exc_cause
connect slots_10.io.in_uop.bits.exception, issue_slots[10].in_uop.bits.exception
connect slots_10.io.in_uop.bits.stale_pdst, issue_slots[10].in_uop.bits.stale_pdst
connect slots_10.io.in_uop.bits.ppred_busy, issue_slots[10].in_uop.bits.ppred_busy
connect slots_10.io.in_uop.bits.prs3_busy, issue_slots[10].in_uop.bits.prs3_busy
connect slots_10.io.in_uop.bits.prs2_busy, issue_slots[10].in_uop.bits.prs2_busy
connect slots_10.io.in_uop.bits.prs1_busy, issue_slots[10].in_uop.bits.prs1_busy
connect slots_10.io.in_uop.bits.ppred, issue_slots[10].in_uop.bits.ppred
connect slots_10.io.in_uop.bits.prs3, issue_slots[10].in_uop.bits.prs3
connect slots_10.io.in_uop.bits.prs2, issue_slots[10].in_uop.bits.prs2
connect slots_10.io.in_uop.bits.prs1, issue_slots[10].in_uop.bits.prs1
connect slots_10.io.in_uop.bits.pdst, issue_slots[10].in_uop.bits.pdst
connect slots_10.io.in_uop.bits.rxq_idx, issue_slots[10].in_uop.bits.rxq_idx
connect slots_10.io.in_uop.bits.stq_idx, issue_slots[10].in_uop.bits.stq_idx
connect slots_10.io.in_uop.bits.ldq_idx, issue_slots[10].in_uop.bits.ldq_idx
connect slots_10.io.in_uop.bits.rob_idx, issue_slots[10].in_uop.bits.rob_idx
connect slots_10.io.in_uop.bits.csr_addr, issue_slots[10].in_uop.bits.csr_addr
connect slots_10.io.in_uop.bits.imm_packed, issue_slots[10].in_uop.bits.imm_packed
connect slots_10.io.in_uop.bits.taken, issue_slots[10].in_uop.bits.taken
connect slots_10.io.in_uop.bits.pc_lob, issue_slots[10].in_uop.bits.pc_lob
connect slots_10.io.in_uop.bits.edge_inst, issue_slots[10].in_uop.bits.edge_inst
connect slots_10.io.in_uop.bits.ftq_idx, issue_slots[10].in_uop.bits.ftq_idx
connect slots_10.io.in_uop.bits.br_tag, issue_slots[10].in_uop.bits.br_tag
connect slots_10.io.in_uop.bits.br_mask, issue_slots[10].in_uop.bits.br_mask
connect slots_10.io.in_uop.bits.is_sfb, issue_slots[10].in_uop.bits.is_sfb
connect slots_10.io.in_uop.bits.is_jal, issue_slots[10].in_uop.bits.is_jal
connect slots_10.io.in_uop.bits.is_jalr, issue_slots[10].in_uop.bits.is_jalr
connect slots_10.io.in_uop.bits.is_br, issue_slots[10].in_uop.bits.is_br
connect slots_10.io.in_uop.bits.iw_p2_poisoned, issue_slots[10].in_uop.bits.iw_p2_poisoned
connect slots_10.io.in_uop.bits.iw_p1_poisoned, issue_slots[10].in_uop.bits.iw_p1_poisoned
connect slots_10.io.in_uop.bits.iw_state, issue_slots[10].in_uop.bits.iw_state
connect slots_10.io.in_uop.bits.ctrl.is_std, issue_slots[10].in_uop.bits.ctrl.is_std
connect slots_10.io.in_uop.bits.ctrl.is_sta, issue_slots[10].in_uop.bits.ctrl.is_sta
connect slots_10.io.in_uop.bits.ctrl.is_load, issue_slots[10].in_uop.bits.ctrl.is_load
connect slots_10.io.in_uop.bits.ctrl.csr_cmd, issue_slots[10].in_uop.bits.ctrl.csr_cmd
connect slots_10.io.in_uop.bits.ctrl.fcn_dw, issue_slots[10].in_uop.bits.ctrl.fcn_dw
connect slots_10.io.in_uop.bits.ctrl.op_fcn, issue_slots[10].in_uop.bits.ctrl.op_fcn
connect slots_10.io.in_uop.bits.ctrl.imm_sel, issue_slots[10].in_uop.bits.ctrl.imm_sel
connect slots_10.io.in_uop.bits.ctrl.op2_sel, issue_slots[10].in_uop.bits.ctrl.op2_sel
connect slots_10.io.in_uop.bits.ctrl.op1_sel, issue_slots[10].in_uop.bits.ctrl.op1_sel
connect slots_10.io.in_uop.bits.ctrl.br_type, issue_slots[10].in_uop.bits.ctrl.br_type
connect slots_10.io.in_uop.bits.fu_code, issue_slots[10].in_uop.bits.fu_code
connect slots_10.io.in_uop.bits.iq_type, issue_slots[10].in_uop.bits.iq_type
connect slots_10.io.in_uop.bits.debug_pc, issue_slots[10].in_uop.bits.debug_pc
connect slots_10.io.in_uop.bits.is_rvc, issue_slots[10].in_uop.bits.is_rvc
connect slots_10.io.in_uop.bits.debug_inst, issue_slots[10].in_uop.bits.debug_inst
connect slots_10.io.in_uop.bits.inst, issue_slots[10].in_uop.bits.inst
connect slots_10.io.in_uop.bits.uopc, issue_slots[10].in_uop.bits.uopc
connect slots_10.io.in_uop.valid, issue_slots[10].in_uop.valid
connect slots_10.io.spec_ld_wakeup[0].bits, issue_slots[10].spec_ld_wakeup[0].bits
connect slots_10.io.spec_ld_wakeup[0].valid, issue_slots[10].spec_ld_wakeup[0].valid
connect slots_10.io.pred_wakeup_port.bits, issue_slots[10].pred_wakeup_port.bits
connect slots_10.io.pred_wakeup_port.valid, issue_slots[10].pred_wakeup_port.valid
connect slots_10.io.wakeup_ports[0].bits.poisoned, issue_slots[10].wakeup_ports[0].bits.poisoned
connect slots_10.io.wakeup_ports[0].bits.pdst, issue_slots[10].wakeup_ports[0].bits.pdst
connect slots_10.io.wakeup_ports[0].valid, issue_slots[10].wakeup_ports[0].valid
connect slots_10.io.wakeup_ports[1].bits.poisoned, issue_slots[10].wakeup_ports[1].bits.poisoned
connect slots_10.io.wakeup_ports[1].bits.pdst, issue_slots[10].wakeup_ports[1].bits.pdst
connect slots_10.io.wakeup_ports[1].valid, issue_slots[10].wakeup_ports[1].valid
connect slots_10.io.ldspec_miss, issue_slots[10].ldspec_miss
connect slots_10.io.clear, issue_slots[10].clear
connect slots_10.io.kill, issue_slots[10].kill
connect slots_10.io.brupdate.b2.target_offset, issue_slots[10].brupdate.b2.target_offset
connect slots_10.io.brupdate.b2.jalr_target, issue_slots[10].brupdate.b2.jalr_target
connect slots_10.io.brupdate.b2.pc_sel, issue_slots[10].brupdate.b2.pc_sel
connect slots_10.io.brupdate.b2.cfi_type, issue_slots[10].brupdate.b2.cfi_type
connect slots_10.io.brupdate.b2.taken, issue_slots[10].brupdate.b2.taken
connect slots_10.io.brupdate.b2.mispredict, issue_slots[10].brupdate.b2.mispredict
connect slots_10.io.brupdate.b2.valid, issue_slots[10].brupdate.b2.valid
connect slots_10.io.brupdate.b2.uop.debug_tsrc, issue_slots[10].brupdate.b2.uop.debug_tsrc
connect slots_10.io.brupdate.b2.uop.debug_fsrc, issue_slots[10].brupdate.b2.uop.debug_fsrc
connect slots_10.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[10].brupdate.b2.uop.bp_xcpt_if
connect slots_10.io.brupdate.b2.uop.bp_debug_if, issue_slots[10].brupdate.b2.uop.bp_debug_if
connect slots_10.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[10].brupdate.b2.uop.xcpt_ma_if
connect slots_10.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[10].brupdate.b2.uop.xcpt_ae_if
connect slots_10.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[10].brupdate.b2.uop.xcpt_pf_if
connect slots_10.io.brupdate.b2.uop.fp_single, issue_slots[10].brupdate.b2.uop.fp_single
connect slots_10.io.brupdate.b2.uop.fp_val, issue_slots[10].brupdate.b2.uop.fp_val
connect slots_10.io.brupdate.b2.uop.frs3_en, issue_slots[10].brupdate.b2.uop.frs3_en
connect slots_10.io.brupdate.b2.uop.lrs2_rtype, issue_slots[10].brupdate.b2.uop.lrs2_rtype
connect slots_10.io.brupdate.b2.uop.lrs1_rtype, issue_slots[10].brupdate.b2.uop.lrs1_rtype
connect slots_10.io.brupdate.b2.uop.dst_rtype, issue_slots[10].brupdate.b2.uop.dst_rtype
connect slots_10.io.brupdate.b2.uop.ldst_val, issue_slots[10].brupdate.b2.uop.ldst_val
connect slots_10.io.brupdate.b2.uop.lrs3, issue_slots[10].brupdate.b2.uop.lrs3
connect slots_10.io.brupdate.b2.uop.lrs2, issue_slots[10].brupdate.b2.uop.lrs2
connect slots_10.io.brupdate.b2.uop.lrs1, issue_slots[10].brupdate.b2.uop.lrs1
connect slots_10.io.brupdate.b2.uop.ldst, issue_slots[10].brupdate.b2.uop.ldst
connect slots_10.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[10].brupdate.b2.uop.ldst_is_rs1
connect slots_10.io.brupdate.b2.uop.flush_on_commit, issue_slots[10].brupdate.b2.uop.flush_on_commit
connect slots_10.io.brupdate.b2.uop.is_unique, issue_slots[10].brupdate.b2.uop.is_unique
connect slots_10.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[10].brupdate.b2.uop.is_sys_pc2epc
connect slots_10.io.brupdate.b2.uop.uses_stq, issue_slots[10].brupdate.b2.uop.uses_stq
connect slots_10.io.brupdate.b2.uop.uses_ldq, issue_slots[10].brupdate.b2.uop.uses_ldq
connect slots_10.io.brupdate.b2.uop.is_amo, issue_slots[10].brupdate.b2.uop.is_amo
connect slots_10.io.brupdate.b2.uop.is_fencei, issue_slots[10].brupdate.b2.uop.is_fencei
connect slots_10.io.brupdate.b2.uop.is_fence, issue_slots[10].brupdate.b2.uop.is_fence
connect slots_10.io.brupdate.b2.uop.mem_signed, issue_slots[10].brupdate.b2.uop.mem_signed
connect slots_10.io.brupdate.b2.uop.mem_size, issue_slots[10].brupdate.b2.uop.mem_size
connect slots_10.io.brupdate.b2.uop.mem_cmd, issue_slots[10].brupdate.b2.uop.mem_cmd
connect slots_10.io.brupdate.b2.uop.bypassable, issue_slots[10].brupdate.b2.uop.bypassable
connect slots_10.io.brupdate.b2.uop.exc_cause, issue_slots[10].brupdate.b2.uop.exc_cause
connect slots_10.io.brupdate.b2.uop.exception, issue_slots[10].brupdate.b2.uop.exception
connect slots_10.io.brupdate.b2.uop.stale_pdst, issue_slots[10].brupdate.b2.uop.stale_pdst
connect slots_10.io.brupdate.b2.uop.ppred_busy, issue_slots[10].brupdate.b2.uop.ppred_busy
connect slots_10.io.brupdate.b2.uop.prs3_busy, issue_slots[10].brupdate.b2.uop.prs3_busy
connect slots_10.io.brupdate.b2.uop.prs2_busy, issue_slots[10].brupdate.b2.uop.prs2_busy
connect slots_10.io.brupdate.b2.uop.prs1_busy, issue_slots[10].brupdate.b2.uop.prs1_busy
connect slots_10.io.brupdate.b2.uop.ppred, issue_slots[10].brupdate.b2.uop.ppred
connect slots_10.io.brupdate.b2.uop.prs3, issue_slots[10].brupdate.b2.uop.prs3
connect slots_10.io.brupdate.b2.uop.prs2, issue_slots[10].brupdate.b2.uop.prs2
connect slots_10.io.brupdate.b2.uop.prs1, issue_slots[10].brupdate.b2.uop.prs1
connect slots_10.io.brupdate.b2.uop.pdst, issue_slots[10].brupdate.b2.uop.pdst
connect slots_10.io.brupdate.b2.uop.rxq_idx, issue_slots[10].brupdate.b2.uop.rxq_idx
connect slots_10.io.brupdate.b2.uop.stq_idx, issue_slots[10].brupdate.b2.uop.stq_idx
connect slots_10.io.brupdate.b2.uop.ldq_idx, issue_slots[10].brupdate.b2.uop.ldq_idx
connect slots_10.io.brupdate.b2.uop.rob_idx, issue_slots[10].brupdate.b2.uop.rob_idx
connect slots_10.io.brupdate.b2.uop.csr_addr, issue_slots[10].brupdate.b2.uop.csr_addr
connect slots_10.io.brupdate.b2.uop.imm_packed, issue_slots[10].brupdate.b2.uop.imm_packed
connect slots_10.io.brupdate.b2.uop.taken, issue_slots[10].brupdate.b2.uop.taken
connect slots_10.io.brupdate.b2.uop.pc_lob, issue_slots[10].brupdate.b2.uop.pc_lob
connect slots_10.io.brupdate.b2.uop.edge_inst, issue_slots[10].brupdate.b2.uop.edge_inst
connect slots_10.io.brupdate.b2.uop.ftq_idx, issue_slots[10].brupdate.b2.uop.ftq_idx
connect slots_10.io.brupdate.b2.uop.br_tag, issue_slots[10].brupdate.b2.uop.br_tag
connect slots_10.io.brupdate.b2.uop.br_mask, issue_slots[10].brupdate.b2.uop.br_mask
connect slots_10.io.brupdate.b2.uop.is_sfb, issue_slots[10].brupdate.b2.uop.is_sfb
connect slots_10.io.brupdate.b2.uop.is_jal, issue_slots[10].brupdate.b2.uop.is_jal
connect slots_10.io.brupdate.b2.uop.is_jalr, issue_slots[10].brupdate.b2.uop.is_jalr
connect slots_10.io.brupdate.b2.uop.is_br, issue_slots[10].brupdate.b2.uop.is_br
connect slots_10.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[10].brupdate.b2.uop.iw_p2_poisoned
connect slots_10.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[10].brupdate.b2.uop.iw_p1_poisoned
connect slots_10.io.brupdate.b2.uop.iw_state, issue_slots[10].brupdate.b2.uop.iw_state
connect slots_10.io.brupdate.b2.uop.ctrl.is_std, issue_slots[10].brupdate.b2.uop.ctrl.is_std
connect slots_10.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[10].brupdate.b2.uop.ctrl.is_sta
connect slots_10.io.brupdate.b2.uop.ctrl.is_load, issue_slots[10].brupdate.b2.uop.ctrl.is_load
connect slots_10.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[10].brupdate.b2.uop.ctrl.csr_cmd
connect slots_10.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[10].brupdate.b2.uop.ctrl.fcn_dw
connect slots_10.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[10].brupdate.b2.uop.ctrl.op_fcn
connect slots_10.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[10].brupdate.b2.uop.ctrl.imm_sel
connect slots_10.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[10].brupdate.b2.uop.ctrl.op2_sel
connect slots_10.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[10].brupdate.b2.uop.ctrl.op1_sel
connect slots_10.io.brupdate.b2.uop.ctrl.br_type, issue_slots[10].brupdate.b2.uop.ctrl.br_type
connect slots_10.io.brupdate.b2.uop.fu_code, issue_slots[10].brupdate.b2.uop.fu_code
connect slots_10.io.brupdate.b2.uop.iq_type, issue_slots[10].brupdate.b2.uop.iq_type
connect slots_10.io.brupdate.b2.uop.debug_pc, issue_slots[10].brupdate.b2.uop.debug_pc
connect slots_10.io.brupdate.b2.uop.is_rvc, issue_slots[10].brupdate.b2.uop.is_rvc
connect slots_10.io.brupdate.b2.uop.debug_inst, issue_slots[10].brupdate.b2.uop.debug_inst
connect slots_10.io.brupdate.b2.uop.inst, issue_slots[10].brupdate.b2.uop.inst
connect slots_10.io.brupdate.b2.uop.uopc, issue_slots[10].brupdate.b2.uop.uopc
connect slots_10.io.brupdate.b1.mispredict_mask, issue_slots[10].brupdate.b1.mispredict_mask
connect slots_10.io.brupdate.b1.resolve_mask, issue_slots[10].brupdate.b1.resolve_mask
connect slots_10.io.grant, issue_slots[10].grant
connect issue_slots[10].request_hp, slots_10.io.request_hp
connect issue_slots[10].request, slots_10.io.request
connect issue_slots[10].will_be_valid, slots_10.io.will_be_valid
connect issue_slots[10].valid, slots_10.io.valid
connect issue_slots[11].debug.state, slots_11.io.debug.state
connect issue_slots[11].debug.ppred, slots_11.io.debug.ppred
connect issue_slots[11].debug.p3, slots_11.io.debug.p3
connect issue_slots[11].debug.p2, slots_11.io.debug.p2
connect issue_slots[11].debug.p1, slots_11.io.debug.p1
connect issue_slots[11].uop.debug_tsrc, slots_11.io.uop.debug_tsrc
connect issue_slots[11].uop.debug_fsrc, slots_11.io.uop.debug_fsrc
connect issue_slots[11].uop.bp_xcpt_if, slots_11.io.uop.bp_xcpt_if
connect issue_slots[11].uop.bp_debug_if, slots_11.io.uop.bp_debug_if
connect issue_slots[11].uop.xcpt_ma_if, slots_11.io.uop.xcpt_ma_if
connect issue_slots[11].uop.xcpt_ae_if, slots_11.io.uop.xcpt_ae_if
connect issue_slots[11].uop.xcpt_pf_if, slots_11.io.uop.xcpt_pf_if
connect issue_slots[11].uop.fp_single, slots_11.io.uop.fp_single
connect issue_slots[11].uop.fp_val, slots_11.io.uop.fp_val
connect issue_slots[11].uop.frs3_en, slots_11.io.uop.frs3_en
connect issue_slots[11].uop.lrs2_rtype, slots_11.io.uop.lrs2_rtype
connect issue_slots[11].uop.lrs1_rtype, slots_11.io.uop.lrs1_rtype
connect issue_slots[11].uop.dst_rtype, slots_11.io.uop.dst_rtype
connect issue_slots[11].uop.ldst_val, slots_11.io.uop.ldst_val
connect issue_slots[11].uop.lrs3, slots_11.io.uop.lrs3
connect issue_slots[11].uop.lrs2, slots_11.io.uop.lrs2
connect issue_slots[11].uop.lrs1, slots_11.io.uop.lrs1
connect issue_slots[11].uop.ldst, slots_11.io.uop.ldst
connect issue_slots[11].uop.ldst_is_rs1, slots_11.io.uop.ldst_is_rs1
connect issue_slots[11].uop.flush_on_commit, slots_11.io.uop.flush_on_commit
connect issue_slots[11].uop.is_unique, slots_11.io.uop.is_unique
connect issue_slots[11].uop.is_sys_pc2epc, slots_11.io.uop.is_sys_pc2epc
connect issue_slots[11].uop.uses_stq, slots_11.io.uop.uses_stq
connect issue_slots[11].uop.uses_ldq, slots_11.io.uop.uses_ldq
connect issue_slots[11].uop.is_amo, slots_11.io.uop.is_amo
connect issue_slots[11].uop.is_fencei, slots_11.io.uop.is_fencei
connect issue_slots[11].uop.is_fence, slots_11.io.uop.is_fence
connect issue_slots[11].uop.mem_signed, slots_11.io.uop.mem_signed
connect issue_slots[11].uop.mem_size, slots_11.io.uop.mem_size
connect issue_slots[11].uop.mem_cmd, slots_11.io.uop.mem_cmd
connect issue_slots[11].uop.bypassable, slots_11.io.uop.bypassable
connect issue_slots[11].uop.exc_cause, slots_11.io.uop.exc_cause
connect issue_slots[11].uop.exception, slots_11.io.uop.exception
connect issue_slots[11].uop.stale_pdst, slots_11.io.uop.stale_pdst
connect issue_slots[11].uop.ppred_busy, slots_11.io.uop.ppred_busy
connect issue_slots[11].uop.prs3_busy, slots_11.io.uop.prs3_busy
connect issue_slots[11].uop.prs2_busy, slots_11.io.uop.prs2_busy
connect issue_slots[11].uop.prs1_busy, slots_11.io.uop.prs1_busy
connect issue_slots[11].uop.ppred, slots_11.io.uop.ppred
connect issue_slots[11].uop.prs3, slots_11.io.uop.prs3
connect issue_slots[11].uop.prs2, slots_11.io.uop.prs2
connect issue_slots[11].uop.prs1, slots_11.io.uop.prs1
connect issue_slots[11].uop.pdst, slots_11.io.uop.pdst
connect issue_slots[11].uop.rxq_idx, slots_11.io.uop.rxq_idx
connect issue_slots[11].uop.stq_idx, slots_11.io.uop.stq_idx
connect issue_slots[11].uop.ldq_idx, slots_11.io.uop.ldq_idx
connect issue_slots[11].uop.rob_idx, slots_11.io.uop.rob_idx
connect issue_slots[11].uop.csr_addr, slots_11.io.uop.csr_addr
connect issue_slots[11].uop.imm_packed, slots_11.io.uop.imm_packed
connect issue_slots[11].uop.taken, slots_11.io.uop.taken
connect issue_slots[11].uop.pc_lob, slots_11.io.uop.pc_lob
connect issue_slots[11].uop.edge_inst, slots_11.io.uop.edge_inst
connect issue_slots[11].uop.ftq_idx, slots_11.io.uop.ftq_idx
connect issue_slots[11].uop.br_tag, slots_11.io.uop.br_tag
connect issue_slots[11].uop.br_mask, slots_11.io.uop.br_mask
connect issue_slots[11].uop.is_sfb, slots_11.io.uop.is_sfb
connect issue_slots[11].uop.is_jal, slots_11.io.uop.is_jal
connect issue_slots[11].uop.is_jalr, slots_11.io.uop.is_jalr
connect issue_slots[11].uop.is_br, slots_11.io.uop.is_br
connect issue_slots[11].uop.iw_p2_poisoned, slots_11.io.uop.iw_p2_poisoned
connect issue_slots[11].uop.iw_p1_poisoned, slots_11.io.uop.iw_p1_poisoned
connect issue_slots[11].uop.iw_state, slots_11.io.uop.iw_state
connect issue_slots[11].uop.ctrl.is_std, slots_11.io.uop.ctrl.is_std
connect issue_slots[11].uop.ctrl.is_sta, slots_11.io.uop.ctrl.is_sta
connect issue_slots[11].uop.ctrl.is_load, slots_11.io.uop.ctrl.is_load
connect issue_slots[11].uop.ctrl.csr_cmd, slots_11.io.uop.ctrl.csr_cmd
connect issue_slots[11].uop.ctrl.fcn_dw, slots_11.io.uop.ctrl.fcn_dw
connect issue_slots[11].uop.ctrl.op_fcn, slots_11.io.uop.ctrl.op_fcn
connect issue_slots[11].uop.ctrl.imm_sel, slots_11.io.uop.ctrl.imm_sel
connect issue_slots[11].uop.ctrl.op2_sel, slots_11.io.uop.ctrl.op2_sel
connect issue_slots[11].uop.ctrl.op1_sel, slots_11.io.uop.ctrl.op1_sel
connect issue_slots[11].uop.ctrl.br_type, slots_11.io.uop.ctrl.br_type
connect issue_slots[11].uop.fu_code, slots_11.io.uop.fu_code
connect issue_slots[11].uop.iq_type, slots_11.io.uop.iq_type
connect issue_slots[11].uop.debug_pc, slots_11.io.uop.debug_pc
connect issue_slots[11].uop.is_rvc, slots_11.io.uop.is_rvc
connect issue_slots[11].uop.debug_inst, slots_11.io.uop.debug_inst
connect issue_slots[11].uop.inst, slots_11.io.uop.inst
connect issue_slots[11].uop.uopc, slots_11.io.uop.uopc
connect issue_slots[11].out_uop.debug_tsrc, slots_11.io.out_uop.debug_tsrc
connect issue_slots[11].out_uop.debug_fsrc, slots_11.io.out_uop.debug_fsrc
connect issue_slots[11].out_uop.bp_xcpt_if, slots_11.io.out_uop.bp_xcpt_if
connect issue_slots[11].out_uop.bp_debug_if, slots_11.io.out_uop.bp_debug_if
connect issue_slots[11].out_uop.xcpt_ma_if, slots_11.io.out_uop.xcpt_ma_if
connect issue_slots[11].out_uop.xcpt_ae_if, slots_11.io.out_uop.xcpt_ae_if
connect issue_slots[11].out_uop.xcpt_pf_if, slots_11.io.out_uop.xcpt_pf_if
connect issue_slots[11].out_uop.fp_single, slots_11.io.out_uop.fp_single
connect issue_slots[11].out_uop.fp_val, slots_11.io.out_uop.fp_val
connect issue_slots[11].out_uop.frs3_en, slots_11.io.out_uop.frs3_en
connect issue_slots[11].out_uop.lrs2_rtype, slots_11.io.out_uop.lrs2_rtype
connect issue_slots[11].out_uop.lrs1_rtype, slots_11.io.out_uop.lrs1_rtype
connect issue_slots[11].out_uop.dst_rtype, slots_11.io.out_uop.dst_rtype
connect issue_slots[11].out_uop.ldst_val, slots_11.io.out_uop.ldst_val
connect issue_slots[11].out_uop.lrs3, slots_11.io.out_uop.lrs3
connect issue_slots[11].out_uop.lrs2, slots_11.io.out_uop.lrs2
connect issue_slots[11].out_uop.lrs1, slots_11.io.out_uop.lrs1
connect issue_slots[11].out_uop.ldst, slots_11.io.out_uop.ldst
connect issue_slots[11].out_uop.ldst_is_rs1, slots_11.io.out_uop.ldst_is_rs1
connect issue_slots[11].out_uop.flush_on_commit, slots_11.io.out_uop.flush_on_commit
connect issue_slots[11].out_uop.is_unique, slots_11.io.out_uop.is_unique
connect issue_slots[11].out_uop.is_sys_pc2epc, slots_11.io.out_uop.is_sys_pc2epc
connect issue_slots[11].out_uop.uses_stq, slots_11.io.out_uop.uses_stq
connect issue_slots[11].out_uop.uses_ldq, slots_11.io.out_uop.uses_ldq
connect issue_slots[11].out_uop.is_amo, slots_11.io.out_uop.is_amo
connect issue_slots[11].out_uop.is_fencei, slots_11.io.out_uop.is_fencei
connect issue_slots[11].out_uop.is_fence, slots_11.io.out_uop.is_fence
connect issue_slots[11].out_uop.mem_signed, slots_11.io.out_uop.mem_signed
connect issue_slots[11].out_uop.mem_size, slots_11.io.out_uop.mem_size
connect issue_slots[11].out_uop.mem_cmd, slots_11.io.out_uop.mem_cmd
connect issue_slots[11].out_uop.bypassable, slots_11.io.out_uop.bypassable
connect issue_slots[11].out_uop.exc_cause, slots_11.io.out_uop.exc_cause
connect issue_slots[11].out_uop.exception, slots_11.io.out_uop.exception
connect issue_slots[11].out_uop.stale_pdst, slots_11.io.out_uop.stale_pdst
connect issue_slots[11].out_uop.ppred_busy, slots_11.io.out_uop.ppred_busy
connect issue_slots[11].out_uop.prs3_busy, slots_11.io.out_uop.prs3_busy
connect issue_slots[11].out_uop.prs2_busy, slots_11.io.out_uop.prs2_busy
connect issue_slots[11].out_uop.prs1_busy, slots_11.io.out_uop.prs1_busy
connect issue_slots[11].out_uop.ppred, slots_11.io.out_uop.ppred
connect issue_slots[11].out_uop.prs3, slots_11.io.out_uop.prs3
connect issue_slots[11].out_uop.prs2, slots_11.io.out_uop.prs2
connect issue_slots[11].out_uop.prs1, slots_11.io.out_uop.prs1
connect issue_slots[11].out_uop.pdst, slots_11.io.out_uop.pdst
connect issue_slots[11].out_uop.rxq_idx, slots_11.io.out_uop.rxq_idx
connect issue_slots[11].out_uop.stq_idx, slots_11.io.out_uop.stq_idx
connect issue_slots[11].out_uop.ldq_idx, slots_11.io.out_uop.ldq_idx
connect issue_slots[11].out_uop.rob_idx, slots_11.io.out_uop.rob_idx
connect issue_slots[11].out_uop.csr_addr, slots_11.io.out_uop.csr_addr
connect issue_slots[11].out_uop.imm_packed, slots_11.io.out_uop.imm_packed
connect issue_slots[11].out_uop.taken, slots_11.io.out_uop.taken
connect issue_slots[11].out_uop.pc_lob, slots_11.io.out_uop.pc_lob
connect issue_slots[11].out_uop.edge_inst, slots_11.io.out_uop.edge_inst
connect issue_slots[11].out_uop.ftq_idx, slots_11.io.out_uop.ftq_idx
connect issue_slots[11].out_uop.br_tag, slots_11.io.out_uop.br_tag
connect issue_slots[11].out_uop.br_mask, slots_11.io.out_uop.br_mask
connect issue_slots[11].out_uop.is_sfb, slots_11.io.out_uop.is_sfb
connect issue_slots[11].out_uop.is_jal, slots_11.io.out_uop.is_jal
connect issue_slots[11].out_uop.is_jalr, slots_11.io.out_uop.is_jalr
connect issue_slots[11].out_uop.is_br, slots_11.io.out_uop.is_br
connect issue_slots[11].out_uop.iw_p2_poisoned, slots_11.io.out_uop.iw_p2_poisoned
connect issue_slots[11].out_uop.iw_p1_poisoned, slots_11.io.out_uop.iw_p1_poisoned
connect issue_slots[11].out_uop.iw_state, slots_11.io.out_uop.iw_state
connect issue_slots[11].out_uop.ctrl.is_std, slots_11.io.out_uop.ctrl.is_std
connect issue_slots[11].out_uop.ctrl.is_sta, slots_11.io.out_uop.ctrl.is_sta
connect issue_slots[11].out_uop.ctrl.is_load, slots_11.io.out_uop.ctrl.is_load
connect issue_slots[11].out_uop.ctrl.csr_cmd, slots_11.io.out_uop.ctrl.csr_cmd
connect issue_slots[11].out_uop.ctrl.fcn_dw, slots_11.io.out_uop.ctrl.fcn_dw
connect issue_slots[11].out_uop.ctrl.op_fcn, slots_11.io.out_uop.ctrl.op_fcn
connect issue_slots[11].out_uop.ctrl.imm_sel, slots_11.io.out_uop.ctrl.imm_sel
connect issue_slots[11].out_uop.ctrl.op2_sel, slots_11.io.out_uop.ctrl.op2_sel
connect issue_slots[11].out_uop.ctrl.op1_sel, slots_11.io.out_uop.ctrl.op1_sel
connect issue_slots[11].out_uop.ctrl.br_type, slots_11.io.out_uop.ctrl.br_type
connect issue_slots[11].out_uop.fu_code, slots_11.io.out_uop.fu_code
connect issue_slots[11].out_uop.iq_type, slots_11.io.out_uop.iq_type
connect issue_slots[11].out_uop.debug_pc, slots_11.io.out_uop.debug_pc
connect issue_slots[11].out_uop.is_rvc, slots_11.io.out_uop.is_rvc
connect issue_slots[11].out_uop.debug_inst, slots_11.io.out_uop.debug_inst
connect issue_slots[11].out_uop.inst, slots_11.io.out_uop.inst
connect issue_slots[11].out_uop.uopc, slots_11.io.out_uop.uopc
connect slots_11.io.in_uop.bits.debug_tsrc, issue_slots[11].in_uop.bits.debug_tsrc
connect slots_11.io.in_uop.bits.debug_fsrc, issue_slots[11].in_uop.bits.debug_fsrc
connect slots_11.io.in_uop.bits.bp_xcpt_if, issue_slots[11].in_uop.bits.bp_xcpt_if
connect slots_11.io.in_uop.bits.bp_debug_if, issue_slots[11].in_uop.bits.bp_debug_if
connect slots_11.io.in_uop.bits.xcpt_ma_if, issue_slots[11].in_uop.bits.xcpt_ma_if
connect slots_11.io.in_uop.bits.xcpt_ae_if, issue_slots[11].in_uop.bits.xcpt_ae_if
connect slots_11.io.in_uop.bits.xcpt_pf_if, issue_slots[11].in_uop.bits.xcpt_pf_if
connect slots_11.io.in_uop.bits.fp_single, issue_slots[11].in_uop.bits.fp_single
connect slots_11.io.in_uop.bits.fp_val, issue_slots[11].in_uop.bits.fp_val
connect slots_11.io.in_uop.bits.frs3_en, issue_slots[11].in_uop.bits.frs3_en
connect slots_11.io.in_uop.bits.lrs2_rtype, issue_slots[11].in_uop.bits.lrs2_rtype
connect slots_11.io.in_uop.bits.lrs1_rtype, issue_slots[11].in_uop.bits.lrs1_rtype
connect slots_11.io.in_uop.bits.dst_rtype, issue_slots[11].in_uop.bits.dst_rtype
connect slots_11.io.in_uop.bits.ldst_val, issue_slots[11].in_uop.bits.ldst_val
connect slots_11.io.in_uop.bits.lrs3, issue_slots[11].in_uop.bits.lrs3
connect slots_11.io.in_uop.bits.lrs2, issue_slots[11].in_uop.bits.lrs2
connect slots_11.io.in_uop.bits.lrs1, issue_slots[11].in_uop.bits.lrs1
connect slots_11.io.in_uop.bits.ldst, issue_slots[11].in_uop.bits.ldst
connect slots_11.io.in_uop.bits.ldst_is_rs1, issue_slots[11].in_uop.bits.ldst_is_rs1
connect slots_11.io.in_uop.bits.flush_on_commit, issue_slots[11].in_uop.bits.flush_on_commit
connect slots_11.io.in_uop.bits.is_unique, issue_slots[11].in_uop.bits.is_unique
connect slots_11.io.in_uop.bits.is_sys_pc2epc, issue_slots[11].in_uop.bits.is_sys_pc2epc
connect slots_11.io.in_uop.bits.uses_stq, issue_slots[11].in_uop.bits.uses_stq
connect slots_11.io.in_uop.bits.uses_ldq, issue_slots[11].in_uop.bits.uses_ldq
connect slots_11.io.in_uop.bits.is_amo, issue_slots[11].in_uop.bits.is_amo
connect slots_11.io.in_uop.bits.is_fencei, issue_slots[11].in_uop.bits.is_fencei
connect slots_11.io.in_uop.bits.is_fence, issue_slots[11].in_uop.bits.is_fence
connect slots_11.io.in_uop.bits.mem_signed, issue_slots[11].in_uop.bits.mem_signed
connect slots_11.io.in_uop.bits.mem_size, issue_slots[11].in_uop.bits.mem_size
connect slots_11.io.in_uop.bits.mem_cmd, issue_slots[11].in_uop.bits.mem_cmd
connect slots_11.io.in_uop.bits.bypassable, issue_slots[11].in_uop.bits.bypassable
connect slots_11.io.in_uop.bits.exc_cause, issue_slots[11].in_uop.bits.exc_cause
connect slots_11.io.in_uop.bits.exception, issue_slots[11].in_uop.bits.exception
connect slots_11.io.in_uop.bits.stale_pdst, issue_slots[11].in_uop.bits.stale_pdst
connect slots_11.io.in_uop.bits.ppred_busy, issue_slots[11].in_uop.bits.ppred_busy
connect slots_11.io.in_uop.bits.prs3_busy, issue_slots[11].in_uop.bits.prs3_busy
connect slots_11.io.in_uop.bits.prs2_busy, issue_slots[11].in_uop.bits.prs2_busy
connect slots_11.io.in_uop.bits.prs1_busy, issue_slots[11].in_uop.bits.prs1_busy
connect slots_11.io.in_uop.bits.ppred, issue_slots[11].in_uop.bits.ppred
connect slots_11.io.in_uop.bits.prs3, issue_slots[11].in_uop.bits.prs3
connect slots_11.io.in_uop.bits.prs2, issue_slots[11].in_uop.bits.prs2
connect slots_11.io.in_uop.bits.prs1, issue_slots[11].in_uop.bits.prs1
connect slots_11.io.in_uop.bits.pdst, issue_slots[11].in_uop.bits.pdst
connect slots_11.io.in_uop.bits.rxq_idx, issue_slots[11].in_uop.bits.rxq_idx
connect slots_11.io.in_uop.bits.stq_idx, issue_slots[11].in_uop.bits.stq_idx
connect slots_11.io.in_uop.bits.ldq_idx, issue_slots[11].in_uop.bits.ldq_idx
connect slots_11.io.in_uop.bits.rob_idx, issue_slots[11].in_uop.bits.rob_idx
connect slots_11.io.in_uop.bits.csr_addr, issue_slots[11].in_uop.bits.csr_addr
connect slots_11.io.in_uop.bits.imm_packed, issue_slots[11].in_uop.bits.imm_packed
connect slots_11.io.in_uop.bits.taken, issue_slots[11].in_uop.bits.taken
connect slots_11.io.in_uop.bits.pc_lob, issue_slots[11].in_uop.bits.pc_lob
connect slots_11.io.in_uop.bits.edge_inst, issue_slots[11].in_uop.bits.edge_inst
connect slots_11.io.in_uop.bits.ftq_idx, issue_slots[11].in_uop.bits.ftq_idx
connect slots_11.io.in_uop.bits.br_tag, issue_slots[11].in_uop.bits.br_tag
connect slots_11.io.in_uop.bits.br_mask, issue_slots[11].in_uop.bits.br_mask
connect slots_11.io.in_uop.bits.is_sfb, issue_slots[11].in_uop.bits.is_sfb
connect slots_11.io.in_uop.bits.is_jal, issue_slots[11].in_uop.bits.is_jal
connect slots_11.io.in_uop.bits.is_jalr, issue_slots[11].in_uop.bits.is_jalr
connect slots_11.io.in_uop.bits.is_br, issue_slots[11].in_uop.bits.is_br
connect slots_11.io.in_uop.bits.iw_p2_poisoned, issue_slots[11].in_uop.bits.iw_p2_poisoned
connect slots_11.io.in_uop.bits.iw_p1_poisoned, issue_slots[11].in_uop.bits.iw_p1_poisoned
connect slots_11.io.in_uop.bits.iw_state, issue_slots[11].in_uop.bits.iw_state
connect slots_11.io.in_uop.bits.ctrl.is_std, issue_slots[11].in_uop.bits.ctrl.is_std
connect slots_11.io.in_uop.bits.ctrl.is_sta, issue_slots[11].in_uop.bits.ctrl.is_sta
connect slots_11.io.in_uop.bits.ctrl.is_load, issue_slots[11].in_uop.bits.ctrl.is_load
connect slots_11.io.in_uop.bits.ctrl.csr_cmd, issue_slots[11].in_uop.bits.ctrl.csr_cmd
connect slots_11.io.in_uop.bits.ctrl.fcn_dw, issue_slots[11].in_uop.bits.ctrl.fcn_dw
connect slots_11.io.in_uop.bits.ctrl.op_fcn, issue_slots[11].in_uop.bits.ctrl.op_fcn
connect slots_11.io.in_uop.bits.ctrl.imm_sel, issue_slots[11].in_uop.bits.ctrl.imm_sel
connect slots_11.io.in_uop.bits.ctrl.op2_sel, issue_slots[11].in_uop.bits.ctrl.op2_sel
connect slots_11.io.in_uop.bits.ctrl.op1_sel, issue_slots[11].in_uop.bits.ctrl.op1_sel
connect slots_11.io.in_uop.bits.ctrl.br_type, issue_slots[11].in_uop.bits.ctrl.br_type
connect slots_11.io.in_uop.bits.fu_code, issue_slots[11].in_uop.bits.fu_code
connect slots_11.io.in_uop.bits.iq_type, issue_slots[11].in_uop.bits.iq_type
connect slots_11.io.in_uop.bits.debug_pc, issue_slots[11].in_uop.bits.debug_pc
connect slots_11.io.in_uop.bits.is_rvc, issue_slots[11].in_uop.bits.is_rvc
connect slots_11.io.in_uop.bits.debug_inst, issue_slots[11].in_uop.bits.debug_inst
connect slots_11.io.in_uop.bits.inst, issue_slots[11].in_uop.bits.inst
connect slots_11.io.in_uop.bits.uopc, issue_slots[11].in_uop.bits.uopc
connect slots_11.io.in_uop.valid, issue_slots[11].in_uop.valid
connect slots_11.io.spec_ld_wakeup[0].bits, issue_slots[11].spec_ld_wakeup[0].bits
connect slots_11.io.spec_ld_wakeup[0].valid, issue_slots[11].spec_ld_wakeup[0].valid
connect slots_11.io.pred_wakeup_port.bits, issue_slots[11].pred_wakeup_port.bits
connect slots_11.io.pred_wakeup_port.valid, issue_slots[11].pred_wakeup_port.valid
connect slots_11.io.wakeup_ports[0].bits.poisoned, issue_slots[11].wakeup_ports[0].bits.poisoned
connect slots_11.io.wakeup_ports[0].bits.pdst, issue_slots[11].wakeup_ports[0].bits.pdst
connect slots_11.io.wakeup_ports[0].valid, issue_slots[11].wakeup_ports[0].valid
connect slots_11.io.wakeup_ports[1].bits.poisoned, issue_slots[11].wakeup_ports[1].bits.poisoned
connect slots_11.io.wakeup_ports[1].bits.pdst, issue_slots[11].wakeup_ports[1].bits.pdst
connect slots_11.io.wakeup_ports[1].valid, issue_slots[11].wakeup_ports[1].valid
connect slots_11.io.ldspec_miss, issue_slots[11].ldspec_miss
connect slots_11.io.clear, issue_slots[11].clear
connect slots_11.io.kill, issue_slots[11].kill
connect slots_11.io.brupdate.b2.target_offset, issue_slots[11].brupdate.b2.target_offset
connect slots_11.io.brupdate.b2.jalr_target, issue_slots[11].brupdate.b2.jalr_target
connect slots_11.io.brupdate.b2.pc_sel, issue_slots[11].brupdate.b2.pc_sel
connect slots_11.io.brupdate.b2.cfi_type, issue_slots[11].brupdate.b2.cfi_type
connect slots_11.io.brupdate.b2.taken, issue_slots[11].brupdate.b2.taken
connect slots_11.io.brupdate.b2.mispredict, issue_slots[11].brupdate.b2.mispredict
connect slots_11.io.brupdate.b2.valid, issue_slots[11].brupdate.b2.valid
connect slots_11.io.brupdate.b2.uop.debug_tsrc, issue_slots[11].brupdate.b2.uop.debug_tsrc
connect slots_11.io.brupdate.b2.uop.debug_fsrc, issue_slots[11].brupdate.b2.uop.debug_fsrc
connect slots_11.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[11].brupdate.b2.uop.bp_xcpt_if
connect slots_11.io.brupdate.b2.uop.bp_debug_if, issue_slots[11].brupdate.b2.uop.bp_debug_if
connect slots_11.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[11].brupdate.b2.uop.xcpt_ma_if
connect slots_11.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[11].brupdate.b2.uop.xcpt_ae_if
connect slots_11.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[11].brupdate.b2.uop.xcpt_pf_if
connect slots_11.io.brupdate.b2.uop.fp_single, issue_slots[11].brupdate.b2.uop.fp_single
connect slots_11.io.brupdate.b2.uop.fp_val, issue_slots[11].brupdate.b2.uop.fp_val
connect slots_11.io.brupdate.b2.uop.frs3_en, issue_slots[11].brupdate.b2.uop.frs3_en
connect slots_11.io.brupdate.b2.uop.lrs2_rtype, issue_slots[11].brupdate.b2.uop.lrs2_rtype
connect slots_11.io.brupdate.b2.uop.lrs1_rtype, issue_slots[11].brupdate.b2.uop.lrs1_rtype
connect slots_11.io.brupdate.b2.uop.dst_rtype, issue_slots[11].brupdate.b2.uop.dst_rtype
connect slots_11.io.brupdate.b2.uop.ldst_val, issue_slots[11].brupdate.b2.uop.ldst_val
connect slots_11.io.brupdate.b2.uop.lrs3, issue_slots[11].brupdate.b2.uop.lrs3
connect slots_11.io.brupdate.b2.uop.lrs2, issue_slots[11].brupdate.b2.uop.lrs2
connect slots_11.io.brupdate.b2.uop.lrs1, issue_slots[11].brupdate.b2.uop.lrs1
connect slots_11.io.brupdate.b2.uop.ldst, issue_slots[11].brupdate.b2.uop.ldst
connect slots_11.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[11].brupdate.b2.uop.ldst_is_rs1
connect slots_11.io.brupdate.b2.uop.flush_on_commit, issue_slots[11].brupdate.b2.uop.flush_on_commit
connect slots_11.io.brupdate.b2.uop.is_unique, issue_slots[11].brupdate.b2.uop.is_unique
connect slots_11.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[11].brupdate.b2.uop.is_sys_pc2epc
connect slots_11.io.brupdate.b2.uop.uses_stq, issue_slots[11].brupdate.b2.uop.uses_stq
connect slots_11.io.brupdate.b2.uop.uses_ldq, issue_slots[11].brupdate.b2.uop.uses_ldq
connect slots_11.io.brupdate.b2.uop.is_amo, issue_slots[11].brupdate.b2.uop.is_amo
connect slots_11.io.brupdate.b2.uop.is_fencei, issue_slots[11].brupdate.b2.uop.is_fencei
connect slots_11.io.brupdate.b2.uop.is_fence, issue_slots[11].brupdate.b2.uop.is_fence
connect slots_11.io.brupdate.b2.uop.mem_signed, issue_slots[11].brupdate.b2.uop.mem_signed
connect slots_11.io.brupdate.b2.uop.mem_size, issue_slots[11].brupdate.b2.uop.mem_size
connect slots_11.io.brupdate.b2.uop.mem_cmd, issue_slots[11].brupdate.b2.uop.mem_cmd
connect slots_11.io.brupdate.b2.uop.bypassable, issue_slots[11].brupdate.b2.uop.bypassable
connect slots_11.io.brupdate.b2.uop.exc_cause, issue_slots[11].brupdate.b2.uop.exc_cause
connect slots_11.io.brupdate.b2.uop.exception, issue_slots[11].brupdate.b2.uop.exception
connect slots_11.io.brupdate.b2.uop.stale_pdst, issue_slots[11].brupdate.b2.uop.stale_pdst
connect slots_11.io.brupdate.b2.uop.ppred_busy, issue_slots[11].brupdate.b2.uop.ppred_busy
connect slots_11.io.brupdate.b2.uop.prs3_busy, issue_slots[11].brupdate.b2.uop.prs3_busy
connect slots_11.io.brupdate.b2.uop.prs2_busy, issue_slots[11].brupdate.b2.uop.prs2_busy
connect slots_11.io.brupdate.b2.uop.prs1_busy, issue_slots[11].brupdate.b2.uop.prs1_busy
connect slots_11.io.brupdate.b2.uop.ppred, issue_slots[11].brupdate.b2.uop.ppred
connect slots_11.io.brupdate.b2.uop.prs3, issue_slots[11].brupdate.b2.uop.prs3
connect slots_11.io.brupdate.b2.uop.prs2, issue_slots[11].brupdate.b2.uop.prs2
connect slots_11.io.brupdate.b2.uop.prs1, issue_slots[11].brupdate.b2.uop.prs1
connect slots_11.io.brupdate.b2.uop.pdst, issue_slots[11].brupdate.b2.uop.pdst
connect slots_11.io.brupdate.b2.uop.rxq_idx, issue_slots[11].brupdate.b2.uop.rxq_idx
connect slots_11.io.brupdate.b2.uop.stq_idx, issue_slots[11].brupdate.b2.uop.stq_idx
connect slots_11.io.brupdate.b2.uop.ldq_idx, issue_slots[11].brupdate.b2.uop.ldq_idx
connect slots_11.io.brupdate.b2.uop.rob_idx, issue_slots[11].brupdate.b2.uop.rob_idx
connect slots_11.io.brupdate.b2.uop.csr_addr, issue_slots[11].brupdate.b2.uop.csr_addr
connect slots_11.io.brupdate.b2.uop.imm_packed, issue_slots[11].brupdate.b2.uop.imm_packed
connect slots_11.io.brupdate.b2.uop.taken, issue_slots[11].brupdate.b2.uop.taken
connect slots_11.io.brupdate.b2.uop.pc_lob, issue_slots[11].brupdate.b2.uop.pc_lob
connect slots_11.io.brupdate.b2.uop.edge_inst, issue_slots[11].brupdate.b2.uop.edge_inst
connect slots_11.io.brupdate.b2.uop.ftq_idx, issue_slots[11].brupdate.b2.uop.ftq_idx
connect slots_11.io.brupdate.b2.uop.br_tag, issue_slots[11].brupdate.b2.uop.br_tag
connect slots_11.io.brupdate.b2.uop.br_mask, issue_slots[11].brupdate.b2.uop.br_mask
connect slots_11.io.brupdate.b2.uop.is_sfb, issue_slots[11].brupdate.b2.uop.is_sfb
connect slots_11.io.brupdate.b2.uop.is_jal, issue_slots[11].brupdate.b2.uop.is_jal
connect slots_11.io.brupdate.b2.uop.is_jalr, issue_slots[11].brupdate.b2.uop.is_jalr
connect slots_11.io.brupdate.b2.uop.is_br, issue_slots[11].brupdate.b2.uop.is_br
connect slots_11.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[11].brupdate.b2.uop.iw_p2_poisoned
connect slots_11.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[11].brupdate.b2.uop.iw_p1_poisoned
connect slots_11.io.brupdate.b2.uop.iw_state, issue_slots[11].brupdate.b2.uop.iw_state
connect slots_11.io.brupdate.b2.uop.ctrl.is_std, issue_slots[11].brupdate.b2.uop.ctrl.is_std
connect slots_11.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[11].brupdate.b2.uop.ctrl.is_sta
connect slots_11.io.brupdate.b2.uop.ctrl.is_load, issue_slots[11].brupdate.b2.uop.ctrl.is_load
connect slots_11.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[11].brupdate.b2.uop.ctrl.csr_cmd
connect slots_11.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[11].brupdate.b2.uop.ctrl.fcn_dw
connect slots_11.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[11].brupdate.b2.uop.ctrl.op_fcn
connect slots_11.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[11].brupdate.b2.uop.ctrl.imm_sel
connect slots_11.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[11].brupdate.b2.uop.ctrl.op2_sel
connect slots_11.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[11].brupdate.b2.uop.ctrl.op1_sel
connect slots_11.io.brupdate.b2.uop.ctrl.br_type, issue_slots[11].brupdate.b2.uop.ctrl.br_type
connect slots_11.io.brupdate.b2.uop.fu_code, issue_slots[11].brupdate.b2.uop.fu_code
connect slots_11.io.brupdate.b2.uop.iq_type, issue_slots[11].brupdate.b2.uop.iq_type
connect slots_11.io.brupdate.b2.uop.debug_pc, issue_slots[11].brupdate.b2.uop.debug_pc
connect slots_11.io.brupdate.b2.uop.is_rvc, issue_slots[11].brupdate.b2.uop.is_rvc
connect slots_11.io.brupdate.b2.uop.debug_inst, issue_slots[11].brupdate.b2.uop.debug_inst
connect slots_11.io.brupdate.b2.uop.inst, issue_slots[11].brupdate.b2.uop.inst
connect slots_11.io.brupdate.b2.uop.uopc, issue_slots[11].brupdate.b2.uop.uopc
connect slots_11.io.brupdate.b1.mispredict_mask, issue_slots[11].brupdate.b1.mispredict_mask
connect slots_11.io.brupdate.b1.resolve_mask, issue_slots[11].brupdate.b1.resolve_mask
connect slots_11.io.grant, issue_slots[11].grant
connect issue_slots[11].request_hp, slots_11.io.request_hp
connect issue_slots[11].request, slots_11.io.request
connect issue_slots[11].will_be_valid, slots_11.io.will_be_valid
connect issue_slots[11].valid, slots_11.io.valid
connect issue_slots[12].debug.state, slots_12.io.debug.state
connect issue_slots[12].debug.ppred, slots_12.io.debug.ppred
connect issue_slots[12].debug.p3, slots_12.io.debug.p3
connect issue_slots[12].debug.p2, slots_12.io.debug.p2
connect issue_slots[12].debug.p1, slots_12.io.debug.p1
connect issue_slots[12].uop.debug_tsrc, slots_12.io.uop.debug_tsrc
connect issue_slots[12].uop.debug_fsrc, slots_12.io.uop.debug_fsrc
connect issue_slots[12].uop.bp_xcpt_if, slots_12.io.uop.bp_xcpt_if
connect issue_slots[12].uop.bp_debug_if, slots_12.io.uop.bp_debug_if
connect issue_slots[12].uop.xcpt_ma_if, slots_12.io.uop.xcpt_ma_if
connect issue_slots[12].uop.xcpt_ae_if, slots_12.io.uop.xcpt_ae_if
connect issue_slots[12].uop.xcpt_pf_if, slots_12.io.uop.xcpt_pf_if
connect issue_slots[12].uop.fp_single, slots_12.io.uop.fp_single
connect issue_slots[12].uop.fp_val, slots_12.io.uop.fp_val
connect issue_slots[12].uop.frs3_en, slots_12.io.uop.frs3_en
connect issue_slots[12].uop.lrs2_rtype, slots_12.io.uop.lrs2_rtype
connect issue_slots[12].uop.lrs1_rtype, slots_12.io.uop.lrs1_rtype
connect issue_slots[12].uop.dst_rtype, slots_12.io.uop.dst_rtype
connect issue_slots[12].uop.ldst_val, slots_12.io.uop.ldst_val
connect issue_slots[12].uop.lrs3, slots_12.io.uop.lrs3
connect issue_slots[12].uop.lrs2, slots_12.io.uop.lrs2
connect issue_slots[12].uop.lrs1, slots_12.io.uop.lrs1
connect issue_slots[12].uop.ldst, slots_12.io.uop.ldst
connect issue_slots[12].uop.ldst_is_rs1, slots_12.io.uop.ldst_is_rs1
connect issue_slots[12].uop.flush_on_commit, slots_12.io.uop.flush_on_commit
connect issue_slots[12].uop.is_unique, slots_12.io.uop.is_unique
connect issue_slots[12].uop.is_sys_pc2epc, slots_12.io.uop.is_sys_pc2epc
connect issue_slots[12].uop.uses_stq, slots_12.io.uop.uses_stq
connect issue_slots[12].uop.uses_ldq, slots_12.io.uop.uses_ldq
connect issue_slots[12].uop.is_amo, slots_12.io.uop.is_amo
connect issue_slots[12].uop.is_fencei, slots_12.io.uop.is_fencei
connect issue_slots[12].uop.is_fence, slots_12.io.uop.is_fence
connect issue_slots[12].uop.mem_signed, slots_12.io.uop.mem_signed
connect issue_slots[12].uop.mem_size, slots_12.io.uop.mem_size
connect issue_slots[12].uop.mem_cmd, slots_12.io.uop.mem_cmd
connect issue_slots[12].uop.bypassable, slots_12.io.uop.bypassable
connect issue_slots[12].uop.exc_cause, slots_12.io.uop.exc_cause
connect issue_slots[12].uop.exception, slots_12.io.uop.exception
connect issue_slots[12].uop.stale_pdst, slots_12.io.uop.stale_pdst
connect issue_slots[12].uop.ppred_busy, slots_12.io.uop.ppred_busy
connect issue_slots[12].uop.prs3_busy, slots_12.io.uop.prs3_busy
connect issue_slots[12].uop.prs2_busy, slots_12.io.uop.prs2_busy
connect issue_slots[12].uop.prs1_busy, slots_12.io.uop.prs1_busy
connect issue_slots[12].uop.ppred, slots_12.io.uop.ppred
connect issue_slots[12].uop.prs3, slots_12.io.uop.prs3
connect issue_slots[12].uop.prs2, slots_12.io.uop.prs2
connect issue_slots[12].uop.prs1, slots_12.io.uop.prs1
connect issue_slots[12].uop.pdst, slots_12.io.uop.pdst
connect issue_slots[12].uop.rxq_idx, slots_12.io.uop.rxq_idx
connect issue_slots[12].uop.stq_idx, slots_12.io.uop.stq_idx
connect issue_slots[12].uop.ldq_idx, slots_12.io.uop.ldq_idx
connect issue_slots[12].uop.rob_idx, slots_12.io.uop.rob_idx
connect issue_slots[12].uop.csr_addr, slots_12.io.uop.csr_addr
connect issue_slots[12].uop.imm_packed, slots_12.io.uop.imm_packed
connect issue_slots[12].uop.taken, slots_12.io.uop.taken
connect issue_slots[12].uop.pc_lob, slots_12.io.uop.pc_lob
connect issue_slots[12].uop.edge_inst, slots_12.io.uop.edge_inst
connect issue_slots[12].uop.ftq_idx, slots_12.io.uop.ftq_idx
connect issue_slots[12].uop.br_tag, slots_12.io.uop.br_tag
connect issue_slots[12].uop.br_mask, slots_12.io.uop.br_mask
connect issue_slots[12].uop.is_sfb, slots_12.io.uop.is_sfb
connect issue_slots[12].uop.is_jal, slots_12.io.uop.is_jal
connect issue_slots[12].uop.is_jalr, slots_12.io.uop.is_jalr
connect issue_slots[12].uop.is_br, slots_12.io.uop.is_br
connect issue_slots[12].uop.iw_p2_poisoned, slots_12.io.uop.iw_p2_poisoned
connect issue_slots[12].uop.iw_p1_poisoned, slots_12.io.uop.iw_p1_poisoned
connect issue_slots[12].uop.iw_state, slots_12.io.uop.iw_state
connect issue_slots[12].uop.ctrl.is_std, slots_12.io.uop.ctrl.is_std
connect issue_slots[12].uop.ctrl.is_sta, slots_12.io.uop.ctrl.is_sta
connect issue_slots[12].uop.ctrl.is_load, slots_12.io.uop.ctrl.is_load
connect issue_slots[12].uop.ctrl.csr_cmd, slots_12.io.uop.ctrl.csr_cmd
connect issue_slots[12].uop.ctrl.fcn_dw, slots_12.io.uop.ctrl.fcn_dw
connect issue_slots[12].uop.ctrl.op_fcn, slots_12.io.uop.ctrl.op_fcn
connect issue_slots[12].uop.ctrl.imm_sel, slots_12.io.uop.ctrl.imm_sel
connect issue_slots[12].uop.ctrl.op2_sel, slots_12.io.uop.ctrl.op2_sel
connect issue_slots[12].uop.ctrl.op1_sel, slots_12.io.uop.ctrl.op1_sel
connect issue_slots[12].uop.ctrl.br_type, slots_12.io.uop.ctrl.br_type
connect issue_slots[12].uop.fu_code, slots_12.io.uop.fu_code
connect issue_slots[12].uop.iq_type, slots_12.io.uop.iq_type
connect issue_slots[12].uop.debug_pc, slots_12.io.uop.debug_pc
connect issue_slots[12].uop.is_rvc, slots_12.io.uop.is_rvc
connect issue_slots[12].uop.debug_inst, slots_12.io.uop.debug_inst
connect issue_slots[12].uop.inst, slots_12.io.uop.inst
connect issue_slots[12].uop.uopc, slots_12.io.uop.uopc
connect issue_slots[12].out_uop.debug_tsrc, slots_12.io.out_uop.debug_tsrc
connect issue_slots[12].out_uop.debug_fsrc, slots_12.io.out_uop.debug_fsrc
connect issue_slots[12].out_uop.bp_xcpt_if, slots_12.io.out_uop.bp_xcpt_if
connect issue_slots[12].out_uop.bp_debug_if, slots_12.io.out_uop.bp_debug_if
connect issue_slots[12].out_uop.xcpt_ma_if, slots_12.io.out_uop.xcpt_ma_if
connect issue_slots[12].out_uop.xcpt_ae_if, slots_12.io.out_uop.xcpt_ae_if
connect issue_slots[12].out_uop.xcpt_pf_if, slots_12.io.out_uop.xcpt_pf_if
connect issue_slots[12].out_uop.fp_single, slots_12.io.out_uop.fp_single
connect issue_slots[12].out_uop.fp_val, slots_12.io.out_uop.fp_val
connect issue_slots[12].out_uop.frs3_en, slots_12.io.out_uop.frs3_en
connect issue_slots[12].out_uop.lrs2_rtype, slots_12.io.out_uop.lrs2_rtype
connect issue_slots[12].out_uop.lrs1_rtype, slots_12.io.out_uop.lrs1_rtype
connect issue_slots[12].out_uop.dst_rtype, slots_12.io.out_uop.dst_rtype
connect issue_slots[12].out_uop.ldst_val, slots_12.io.out_uop.ldst_val
connect issue_slots[12].out_uop.lrs3, slots_12.io.out_uop.lrs3
connect issue_slots[12].out_uop.lrs2, slots_12.io.out_uop.lrs2
connect issue_slots[12].out_uop.lrs1, slots_12.io.out_uop.lrs1
connect issue_slots[12].out_uop.ldst, slots_12.io.out_uop.ldst
connect issue_slots[12].out_uop.ldst_is_rs1, slots_12.io.out_uop.ldst_is_rs1
connect issue_slots[12].out_uop.flush_on_commit, slots_12.io.out_uop.flush_on_commit
connect issue_slots[12].out_uop.is_unique, slots_12.io.out_uop.is_unique
connect issue_slots[12].out_uop.is_sys_pc2epc, slots_12.io.out_uop.is_sys_pc2epc
connect issue_slots[12].out_uop.uses_stq, slots_12.io.out_uop.uses_stq
connect issue_slots[12].out_uop.uses_ldq, slots_12.io.out_uop.uses_ldq
connect issue_slots[12].out_uop.is_amo, slots_12.io.out_uop.is_amo
connect issue_slots[12].out_uop.is_fencei, slots_12.io.out_uop.is_fencei
connect issue_slots[12].out_uop.is_fence, slots_12.io.out_uop.is_fence
connect issue_slots[12].out_uop.mem_signed, slots_12.io.out_uop.mem_signed
connect issue_slots[12].out_uop.mem_size, slots_12.io.out_uop.mem_size
connect issue_slots[12].out_uop.mem_cmd, slots_12.io.out_uop.mem_cmd
connect issue_slots[12].out_uop.bypassable, slots_12.io.out_uop.bypassable
connect issue_slots[12].out_uop.exc_cause, slots_12.io.out_uop.exc_cause
connect issue_slots[12].out_uop.exception, slots_12.io.out_uop.exception
connect issue_slots[12].out_uop.stale_pdst, slots_12.io.out_uop.stale_pdst
connect issue_slots[12].out_uop.ppred_busy, slots_12.io.out_uop.ppred_busy
connect issue_slots[12].out_uop.prs3_busy, slots_12.io.out_uop.prs3_busy
connect issue_slots[12].out_uop.prs2_busy, slots_12.io.out_uop.prs2_busy
connect issue_slots[12].out_uop.prs1_busy, slots_12.io.out_uop.prs1_busy
connect issue_slots[12].out_uop.ppred, slots_12.io.out_uop.ppred
connect issue_slots[12].out_uop.prs3, slots_12.io.out_uop.prs3
connect issue_slots[12].out_uop.prs2, slots_12.io.out_uop.prs2
connect issue_slots[12].out_uop.prs1, slots_12.io.out_uop.prs1
connect issue_slots[12].out_uop.pdst, slots_12.io.out_uop.pdst
connect issue_slots[12].out_uop.rxq_idx, slots_12.io.out_uop.rxq_idx
connect issue_slots[12].out_uop.stq_idx, slots_12.io.out_uop.stq_idx
connect issue_slots[12].out_uop.ldq_idx, slots_12.io.out_uop.ldq_idx
connect issue_slots[12].out_uop.rob_idx, slots_12.io.out_uop.rob_idx
connect issue_slots[12].out_uop.csr_addr, slots_12.io.out_uop.csr_addr
connect issue_slots[12].out_uop.imm_packed, slots_12.io.out_uop.imm_packed
connect issue_slots[12].out_uop.taken, slots_12.io.out_uop.taken
connect issue_slots[12].out_uop.pc_lob, slots_12.io.out_uop.pc_lob
connect issue_slots[12].out_uop.edge_inst, slots_12.io.out_uop.edge_inst
connect issue_slots[12].out_uop.ftq_idx, slots_12.io.out_uop.ftq_idx
connect issue_slots[12].out_uop.br_tag, slots_12.io.out_uop.br_tag
connect issue_slots[12].out_uop.br_mask, slots_12.io.out_uop.br_mask
connect issue_slots[12].out_uop.is_sfb, slots_12.io.out_uop.is_sfb
connect issue_slots[12].out_uop.is_jal, slots_12.io.out_uop.is_jal
connect issue_slots[12].out_uop.is_jalr, slots_12.io.out_uop.is_jalr
connect issue_slots[12].out_uop.is_br, slots_12.io.out_uop.is_br
connect issue_slots[12].out_uop.iw_p2_poisoned, slots_12.io.out_uop.iw_p2_poisoned
connect issue_slots[12].out_uop.iw_p1_poisoned, slots_12.io.out_uop.iw_p1_poisoned
connect issue_slots[12].out_uop.iw_state, slots_12.io.out_uop.iw_state
connect issue_slots[12].out_uop.ctrl.is_std, slots_12.io.out_uop.ctrl.is_std
connect issue_slots[12].out_uop.ctrl.is_sta, slots_12.io.out_uop.ctrl.is_sta
connect issue_slots[12].out_uop.ctrl.is_load, slots_12.io.out_uop.ctrl.is_load
connect issue_slots[12].out_uop.ctrl.csr_cmd, slots_12.io.out_uop.ctrl.csr_cmd
connect issue_slots[12].out_uop.ctrl.fcn_dw, slots_12.io.out_uop.ctrl.fcn_dw
connect issue_slots[12].out_uop.ctrl.op_fcn, slots_12.io.out_uop.ctrl.op_fcn
connect issue_slots[12].out_uop.ctrl.imm_sel, slots_12.io.out_uop.ctrl.imm_sel
connect issue_slots[12].out_uop.ctrl.op2_sel, slots_12.io.out_uop.ctrl.op2_sel
connect issue_slots[12].out_uop.ctrl.op1_sel, slots_12.io.out_uop.ctrl.op1_sel
connect issue_slots[12].out_uop.ctrl.br_type, slots_12.io.out_uop.ctrl.br_type
connect issue_slots[12].out_uop.fu_code, slots_12.io.out_uop.fu_code
connect issue_slots[12].out_uop.iq_type, slots_12.io.out_uop.iq_type
connect issue_slots[12].out_uop.debug_pc, slots_12.io.out_uop.debug_pc
connect issue_slots[12].out_uop.is_rvc, slots_12.io.out_uop.is_rvc
connect issue_slots[12].out_uop.debug_inst, slots_12.io.out_uop.debug_inst
connect issue_slots[12].out_uop.inst, slots_12.io.out_uop.inst
connect issue_slots[12].out_uop.uopc, slots_12.io.out_uop.uopc
connect slots_12.io.in_uop.bits.debug_tsrc, issue_slots[12].in_uop.bits.debug_tsrc
connect slots_12.io.in_uop.bits.debug_fsrc, issue_slots[12].in_uop.bits.debug_fsrc
connect slots_12.io.in_uop.bits.bp_xcpt_if, issue_slots[12].in_uop.bits.bp_xcpt_if
connect slots_12.io.in_uop.bits.bp_debug_if, issue_slots[12].in_uop.bits.bp_debug_if
connect slots_12.io.in_uop.bits.xcpt_ma_if, issue_slots[12].in_uop.bits.xcpt_ma_if
connect slots_12.io.in_uop.bits.xcpt_ae_if, issue_slots[12].in_uop.bits.xcpt_ae_if
connect slots_12.io.in_uop.bits.xcpt_pf_if, issue_slots[12].in_uop.bits.xcpt_pf_if
connect slots_12.io.in_uop.bits.fp_single, issue_slots[12].in_uop.bits.fp_single
connect slots_12.io.in_uop.bits.fp_val, issue_slots[12].in_uop.bits.fp_val
connect slots_12.io.in_uop.bits.frs3_en, issue_slots[12].in_uop.bits.frs3_en
connect slots_12.io.in_uop.bits.lrs2_rtype, issue_slots[12].in_uop.bits.lrs2_rtype
connect slots_12.io.in_uop.bits.lrs1_rtype, issue_slots[12].in_uop.bits.lrs1_rtype
connect slots_12.io.in_uop.bits.dst_rtype, issue_slots[12].in_uop.bits.dst_rtype
connect slots_12.io.in_uop.bits.ldst_val, issue_slots[12].in_uop.bits.ldst_val
connect slots_12.io.in_uop.bits.lrs3, issue_slots[12].in_uop.bits.lrs3
connect slots_12.io.in_uop.bits.lrs2, issue_slots[12].in_uop.bits.lrs2
connect slots_12.io.in_uop.bits.lrs1, issue_slots[12].in_uop.bits.lrs1
connect slots_12.io.in_uop.bits.ldst, issue_slots[12].in_uop.bits.ldst
connect slots_12.io.in_uop.bits.ldst_is_rs1, issue_slots[12].in_uop.bits.ldst_is_rs1
connect slots_12.io.in_uop.bits.flush_on_commit, issue_slots[12].in_uop.bits.flush_on_commit
connect slots_12.io.in_uop.bits.is_unique, issue_slots[12].in_uop.bits.is_unique
connect slots_12.io.in_uop.bits.is_sys_pc2epc, issue_slots[12].in_uop.bits.is_sys_pc2epc
connect slots_12.io.in_uop.bits.uses_stq, issue_slots[12].in_uop.bits.uses_stq
connect slots_12.io.in_uop.bits.uses_ldq, issue_slots[12].in_uop.bits.uses_ldq
connect slots_12.io.in_uop.bits.is_amo, issue_slots[12].in_uop.bits.is_amo
connect slots_12.io.in_uop.bits.is_fencei, issue_slots[12].in_uop.bits.is_fencei
connect slots_12.io.in_uop.bits.is_fence, issue_slots[12].in_uop.bits.is_fence
connect slots_12.io.in_uop.bits.mem_signed, issue_slots[12].in_uop.bits.mem_signed
connect slots_12.io.in_uop.bits.mem_size, issue_slots[12].in_uop.bits.mem_size
connect slots_12.io.in_uop.bits.mem_cmd, issue_slots[12].in_uop.bits.mem_cmd
connect slots_12.io.in_uop.bits.bypassable, issue_slots[12].in_uop.bits.bypassable
connect slots_12.io.in_uop.bits.exc_cause, issue_slots[12].in_uop.bits.exc_cause
connect slots_12.io.in_uop.bits.exception, issue_slots[12].in_uop.bits.exception
connect slots_12.io.in_uop.bits.stale_pdst, issue_slots[12].in_uop.bits.stale_pdst
connect slots_12.io.in_uop.bits.ppred_busy, issue_slots[12].in_uop.bits.ppred_busy
connect slots_12.io.in_uop.bits.prs3_busy, issue_slots[12].in_uop.bits.prs3_busy
connect slots_12.io.in_uop.bits.prs2_busy, issue_slots[12].in_uop.bits.prs2_busy
connect slots_12.io.in_uop.bits.prs1_busy, issue_slots[12].in_uop.bits.prs1_busy
connect slots_12.io.in_uop.bits.ppred, issue_slots[12].in_uop.bits.ppred
connect slots_12.io.in_uop.bits.prs3, issue_slots[12].in_uop.bits.prs3
connect slots_12.io.in_uop.bits.prs2, issue_slots[12].in_uop.bits.prs2
connect slots_12.io.in_uop.bits.prs1, issue_slots[12].in_uop.bits.prs1
connect slots_12.io.in_uop.bits.pdst, issue_slots[12].in_uop.bits.pdst
connect slots_12.io.in_uop.bits.rxq_idx, issue_slots[12].in_uop.bits.rxq_idx
connect slots_12.io.in_uop.bits.stq_idx, issue_slots[12].in_uop.bits.stq_idx
connect slots_12.io.in_uop.bits.ldq_idx, issue_slots[12].in_uop.bits.ldq_idx
connect slots_12.io.in_uop.bits.rob_idx, issue_slots[12].in_uop.bits.rob_idx
connect slots_12.io.in_uop.bits.csr_addr, issue_slots[12].in_uop.bits.csr_addr
connect slots_12.io.in_uop.bits.imm_packed, issue_slots[12].in_uop.bits.imm_packed
connect slots_12.io.in_uop.bits.taken, issue_slots[12].in_uop.bits.taken
connect slots_12.io.in_uop.bits.pc_lob, issue_slots[12].in_uop.bits.pc_lob
connect slots_12.io.in_uop.bits.edge_inst, issue_slots[12].in_uop.bits.edge_inst
connect slots_12.io.in_uop.bits.ftq_idx, issue_slots[12].in_uop.bits.ftq_idx
connect slots_12.io.in_uop.bits.br_tag, issue_slots[12].in_uop.bits.br_tag
connect slots_12.io.in_uop.bits.br_mask, issue_slots[12].in_uop.bits.br_mask
connect slots_12.io.in_uop.bits.is_sfb, issue_slots[12].in_uop.bits.is_sfb
connect slots_12.io.in_uop.bits.is_jal, issue_slots[12].in_uop.bits.is_jal
connect slots_12.io.in_uop.bits.is_jalr, issue_slots[12].in_uop.bits.is_jalr
connect slots_12.io.in_uop.bits.is_br, issue_slots[12].in_uop.bits.is_br
connect slots_12.io.in_uop.bits.iw_p2_poisoned, issue_slots[12].in_uop.bits.iw_p2_poisoned
connect slots_12.io.in_uop.bits.iw_p1_poisoned, issue_slots[12].in_uop.bits.iw_p1_poisoned
connect slots_12.io.in_uop.bits.iw_state, issue_slots[12].in_uop.bits.iw_state
connect slots_12.io.in_uop.bits.ctrl.is_std, issue_slots[12].in_uop.bits.ctrl.is_std
connect slots_12.io.in_uop.bits.ctrl.is_sta, issue_slots[12].in_uop.bits.ctrl.is_sta
connect slots_12.io.in_uop.bits.ctrl.is_load, issue_slots[12].in_uop.bits.ctrl.is_load
connect slots_12.io.in_uop.bits.ctrl.csr_cmd, issue_slots[12].in_uop.bits.ctrl.csr_cmd
connect slots_12.io.in_uop.bits.ctrl.fcn_dw, issue_slots[12].in_uop.bits.ctrl.fcn_dw
connect slots_12.io.in_uop.bits.ctrl.op_fcn, issue_slots[12].in_uop.bits.ctrl.op_fcn
connect slots_12.io.in_uop.bits.ctrl.imm_sel, issue_slots[12].in_uop.bits.ctrl.imm_sel
connect slots_12.io.in_uop.bits.ctrl.op2_sel, issue_slots[12].in_uop.bits.ctrl.op2_sel
connect slots_12.io.in_uop.bits.ctrl.op1_sel, issue_slots[12].in_uop.bits.ctrl.op1_sel
connect slots_12.io.in_uop.bits.ctrl.br_type, issue_slots[12].in_uop.bits.ctrl.br_type
connect slots_12.io.in_uop.bits.fu_code, issue_slots[12].in_uop.bits.fu_code
connect slots_12.io.in_uop.bits.iq_type, issue_slots[12].in_uop.bits.iq_type
connect slots_12.io.in_uop.bits.debug_pc, issue_slots[12].in_uop.bits.debug_pc
connect slots_12.io.in_uop.bits.is_rvc, issue_slots[12].in_uop.bits.is_rvc
connect slots_12.io.in_uop.bits.debug_inst, issue_slots[12].in_uop.bits.debug_inst
connect slots_12.io.in_uop.bits.inst, issue_slots[12].in_uop.bits.inst
connect slots_12.io.in_uop.bits.uopc, issue_slots[12].in_uop.bits.uopc
connect slots_12.io.in_uop.valid, issue_slots[12].in_uop.valid
connect slots_12.io.spec_ld_wakeup[0].bits, issue_slots[12].spec_ld_wakeup[0].bits
connect slots_12.io.spec_ld_wakeup[0].valid, issue_slots[12].spec_ld_wakeup[0].valid
connect slots_12.io.pred_wakeup_port.bits, issue_slots[12].pred_wakeup_port.bits
connect slots_12.io.pred_wakeup_port.valid, issue_slots[12].pred_wakeup_port.valid
connect slots_12.io.wakeup_ports[0].bits.poisoned, issue_slots[12].wakeup_ports[0].bits.poisoned
connect slots_12.io.wakeup_ports[0].bits.pdst, issue_slots[12].wakeup_ports[0].bits.pdst
connect slots_12.io.wakeup_ports[0].valid, issue_slots[12].wakeup_ports[0].valid
connect slots_12.io.wakeup_ports[1].bits.poisoned, issue_slots[12].wakeup_ports[1].bits.poisoned
connect slots_12.io.wakeup_ports[1].bits.pdst, issue_slots[12].wakeup_ports[1].bits.pdst
connect slots_12.io.wakeup_ports[1].valid, issue_slots[12].wakeup_ports[1].valid
connect slots_12.io.ldspec_miss, issue_slots[12].ldspec_miss
connect slots_12.io.clear, issue_slots[12].clear
connect slots_12.io.kill, issue_slots[12].kill
connect slots_12.io.brupdate.b2.target_offset, issue_slots[12].brupdate.b2.target_offset
connect slots_12.io.brupdate.b2.jalr_target, issue_slots[12].brupdate.b2.jalr_target
connect slots_12.io.brupdate.b2.pc_sel, issue_slots[12].brupdate.b2.pc_sel
connect slots_12.io.brupdate.b2.cfi_type, issue_slots[12].brupdate.b2.cfi_type
connect slots_12.io.brupdate.b2.taken, issue_slots[12].brupdate.b2.taken
connect slots_12.io.brupdate.b2.mispredict, issue_slots[12].brupdate.b2.mispredict
connect slots_12.io.brupdate.b2.valid, issue_slots[12].brupdate.b2.valid
connect slots_12.io.brupdate.b2.uop.debug_tsrc, issue_slots[12].brupdate.b2.uop.debug_tsrc
connect slots_12.io.brupdate.b2.uop.debug_fsrc, issue_slots[12].brupdate.b2.uop.debug_fsrc
connect slots_12.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[12].brupdate.b2.uop.bp_xcpt_if
connect slots_12.io.brupdate.b2.uop.bp_debug_if, issue_slots[12].brupdate.b2.uop.bp_debug_if
connect slots_12.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[12].brupdate.b2.uop.xcpt_ma_if
connect slots_12.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[12].brupdate.b2.uop.xcpt_ae_if
connect slots_12.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[12].brupdate.b2.uop.xcpt_pf_if
connect slots_12.io.brupdate.b2.uop.fp_single, issue_slots[12].brupdate.b2.uop.fp_single
connect slots_12.io.brupdate.b2.uop.fp_val, issue_slots[12].brupdate.b2.uop.fp_val
connect slots_12.io.brupdate.b2.uop.frs3_en, issue_slots[12].brupdate.b2.uop.frs3_en
connect slots_12.io.brupdate.b2.uop.lrs2_rtype, issue_slots[12].brupdate.b2.uop.lrs2_rtype
connect slots_12.io.brupdate.b2.uop.lrs1_rtype, issue_slots[12].brupdate.b2.uop.lrs1_rtype
connect slots_12.io.brupdate.b2.uop.dst_rtype, issue_slots[12].brupdate.b2.uop.dst_rtype
connect slots_12.io.brupdate.b2.uop.ldst_val, issue_slots[12].brupdate.b2.uop.ldst_val
connect slots_12.io.brupdate.b2.uop.lrs3, issue_slots[12].brupdate.b2.uop.lrs3
connect slots_12.io.brupdate.b2.uop.lrs2, issue_slots[12].brupdate.b2.uop.lrs2
connect slots_12.io.brupdate.b2.uop.lrs1, issue_slots[12].brupdate.b2.uop.lrs1
connect slots_12.io.brupdate.b2.uop.ldst, issue_slots[12].brupdate.b2.uop.ldst
connect slots_12.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[12].brupdate.b2.uop.ldst_is_rs1
connect slots_12.io.brupdate.b2.uop.flush_on_commit, issue_slots[12].brupdate.b2.uop.flush_on_commit
connect slots_12.io.brupdate.b2.uop.is_unique, issue_slots[12].brupdate.b2.uop.is_unique
connect slots_12.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[12].brupdate.b2.uop.is_sys_pc2epc
connect slots_12.io.brupdate.b2.uop.uses_stq, issue_slots[12].brupdate.b2.uop.uses_stq
connect slots_12.io.brupdate.b2.uop.uses_ldq, issue_slots[12].brupdate.b2.uop.uses_ldq
connect slots_12.io.brupdate.b2.uop.is_amo, issue_slots[12].brupdate.b2.uop.is_amo
connect slots_12.io.brupdate.b2.uop.is_fencei, issue_slots[12].brupdate.b2.uop.is_fencei
connect slots_12.io.brupdate.b2.uop.is_fence, issue_slots[12].brupdate.b2.uop.is_fence
connect slots_12.io.brupdate.b2.uop.mem_signed, issue_slots[12].brupdate.b2.uop.mem_signed
connect slots_12.io.brupdate.b2.uop.mem_size, issue_slots[12].brupdate.b2.uop.mem_size
connect slots_12.io.brupdate.b2.uop.mem_cmd, issue_slots[12].brupdate.b2.uop.mem_cmd
connect slots_12.io.brupdate.b2.uop.bypassable, issue_slots[12].brupdate.b2.uop.bypassable
connect slots_12.io.brupdate.b2.uop.exc_cause, issue_slots[12].brupdate.b2.uop.exc_cause
connect slots_12.io.brupdate.b2.uop.exception, issue_slots[12].brupdate.b2.uop.exception
connect slots_12.io.brupdate.b2.uop.stale_pdst, issue_slots[12].brupdate.b2.uop.stale_pdst
connect slots_12.io.brupdate.b2.uop.ppred_busy, issue_slots[12].brupdate.b2.uop.ppred_busy
connect slots_12.io.brupdate.b2.uop.prs3_busy, issue_slots[12].brupdate.b2.uop.prs3_busy
connect slots_12.io.brupdate.b2.uop.prs2_busy, issue_slots[12].brupdate.b2.uop.prs2_busy
connect slots_12.io.brupdate.b2.uop.prs1_busy, issue_slots[12].brupdate.b2.uop.prs1_busy
connect slots_12.io.brupdate.b2.uop.ppred, issue_slots[12].brupdate.b2.uop.ppred
connect slots_12.io.brupdate.b2.uop.prs3, issue_slots[12].brupdate.b2.uop.prs3
connect slots_12.io.brupdate.b2.uop.prs2, issue_slots[12].brupdate.b2.uop.prs2
connect slots_12.io.brupdate.b2.uop.prs1, issue_slots[12].brupdate.b2.uop.prs1
connect slots_12.io.brupdate.b2.uop.pdst, issue_slots[12].brupdate.b2.uop.pdst
connect slots_12.io.brupdate.b2.uop.rxq_idx, issue_slots[12].brupdate.b2.uop.rxq_idx
connect slots_12.io.brupdate.b2.uop.stq_idx, issue_slots[12].brupdate.b2.uop.stq_idx
connect slots_12.io.brupdate.b2.uop.ldq_idx, issue_slots[12].brupdate.b2.uop.ldq_idx
connect slots_12.io.brupdate.b2.uop.rob_idx, issue_slots[12].brupdate.b2.uop.rob_idx
connect slots_12.io.brupdate.b2.uop.csr_addr, issue_slots[12].brupdate.b2.uop.csr_addr
connect slots_12.io.brupdate.b2.uop.imm_packed, issue_slots[12].brupdate.b2.uop.imm_packed
connect slots_12.io.brupdate.b2.uop.taken, issue_slots[12].brupdate.b2.uop.taken
connect slots_12.io.brupdate.b2.uop.pc_lob, issue_slots[12].brupdate.b2.uop.pc_lob
connect slots_12.io.brupdate.b2.uop.edge_inst, issue_slots[12].brupdate.b2.uop.edge_inst
connect slots_12.io.brupdate.b2.uop.ftq_idx, issue_slots[12].brupdate.b2.uop.ftq_idx
connect slots_12.io.brupdate.b2.uop.br_tag, issue_slots[12].brupdate.b2.uop.br_tag
connect slots_12.io.brupdate.b2.uop.br_mask, issue_slots[12].brupdate.b2.uop.br_mask
connect slots_12.io.brupdate.b2.uop.is_sfb, issue_slots[12].brupdate.b2.uop.is_sfb
connect slots_12.io.brupdate.b2.uop.is_jal, issue_slots[12].brupdate.b2.uop.is_jal
connect slots_12.io.brupdate.b2.uop.is_jalr, issue_slots[12].brupdate.b2.uop.is_jalr
connect slots_12.io.brupdate.b2.uop.is_br, issue_slots[12].brupdate.b2.uop.is_br
connect slots_12.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[12].brupdate.b2.uop.iw_p2_poisoned
connect slots_12.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[12].brupdate.b2.uop.iw_p1_poisoned
connect slots_12.io.brupdate.b2.uop.iw_state, issue_slots[12].brupdate.b2.uop.iw_state
connect slots_12.io.brupdate.b2.uop.ctrl.is_std, issue_slots[12].brupdate.b2.uop.ctrl.is_std
connect slots_12.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[12].brupdate.b2.uop.ctrl.is_sta
connect slots_12.io.brupdate.b2.uop.ctrl.is_load, issue_slots[12].brupdate.b2.uop.ctrl.is_load
connect slots_12.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[12].brupdate.b2.uop.ctrl.csr_cmd
connect slots_12.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[12].brupdate.b2.uop.ctrl.fcn_dw
connect slots_12.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[12].brupdate.b2.uop.ctrl.op_fcn
connect slots_12.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[12].brupdate.b2.uop.ctrl.imm_sel
connect slots_12.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[12].brupdate.b2.uop.ctrl.op2_sel
connect slots_12.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[12].brupdate.b2.uop.ctrl.op1_sel
connect slots_12.io.brupdate.b2.uop.ctrl.br_type, issue_slots[12].brupdate.b2.uop.ctrl.br_type
connect slots_12.io.brupdate.b2.uop.fu_code, issue_slots[12].brupdate.b2.uop.fu_code
connect slots_12.io.brupdate.b2.uop.iq_type, issue_slots[12].brupdate.b2.uop.iq_type
connect slots_12.io.brupdate.b2.uop.debug_pc, issue_slots[12].brupdate.b2.uop.debug_pc
connect slots_12.io.brupdate.b2.uop.is_rvc, issue_slots[12].brupdate.b2.uop.is_rvc
connect slots_12.io.brupdate.b2.uop.debug_inst, issue_slots[12].brupdate.b2.uop.debug_inst
connect slots_12.io.brupdate.b2.uop.inst, issue_slots[12].brupdate.b2.uop.inst
connect slots_12.io.brupdate.b2.uop.uopc, issue_slots[12].brupdate.b2.uop.uopc
connect slots_12.io.brupdate.b1.mispredict_mask, issue_slots[12].brupdate.b1.mispredict_mask
connect slots_12.io.brupdate.b1.resolve_mask, issue_slots[12].brupdate.b1.resolve_mask
connect slots_12.io.grant, issue_slots[12].grant
connect issue_slots[12].request_hp, slots_12.io.request_hp
connect issue_slots[12].request, slots_12.io.request
connect issue_slots[12].will_be_valid, slots_12.io.will_be_valid
connect issue_slots[12].valid, slots_12.io.valid
connect issue_slots[13].debug.state, slots_13.io.debug.state
connect issue_slots[13].debug.ppred, slots_13.io.debug.ppred
connect issue_slots[13].debug.p3, slots_13.io.debug.p3
connect issue_slots[13].debug.p2, slots_13.io.debug.p2
connect issue_slots[13].debug.p1, slots_13.io.debug.p1
connect issue_slots[13].uop.debug_tsrc, slots_13.io.uop.debug_tsrc
connect issue_slots[13].uop.debug_fsrc, slots_13.io.uop.debug_fsrc
connect issue_slots[13].uop.bp_xcpt_if, slots_13.io.uop.bp_xcpt_if
connect issue_slots[13].uop.bp_debug_if, slots_13.io.uop.bp_debug_if
connect issue_slots[13].uop.xcpt_ma_if, slots_13.io.uop.xcpt_ma_if
connect issue_slots[13].uop.xcpt_ae_if, slots_13.io.uop.xcpt_ae_if
connect issue_slots[13].uop.xcpt_pf_if, slots_13.io.uop.xcpt_pf_if
connect issue_slots[13].uop.fp_single, slots_13.io.uop.fp_single
connect issue_slots[13].uop.fp_val, slots_13.io.uop.fp_val
connect issue_slots[13].uop.frs3_en, slots_13.io.uop.frs3_en
connect issue_slots[13].uop.lrs2_rtype, slots_13.io.uop.lrs2_rtype
connect issue_slots[13].uop.lrs1_rtype, slots_13.io.uop.lrs1_rtype
connect issue_slots[13].uop.dst_rtype, slots_13.io.uop.dst_rtype
connect issue_slots[13].uop.ldst_val, slots_13.io.uop.ldst_val
connect issue_slots[13].uop.lrs3, slots_13.io.uop.lrs3
connect issue_slots[13].uop.lrs2, slots_13.io.uop.lrs2
connect issue_slots[13].uop.lrs1, slots_13.io.uop.lrs1
connect issue_slots[13].uop.ldst, slots_13.io.uop.ldst
connect issue_slots[13].uop.ldst_is_rs1, slots_13.io.uop.ldst_is_rs1
connect issue_slots[13].uop.flush_on_commit, slots_13.io.uop.flush_on_commit
connect issue_slots[13].uop.is_unique, slots_13.io.uop.is_unique
connect issue_slots[13].uop.is_sys_pc2epc, slots_13.io.uop.is_sys_pc2epc
connect issue_slots[13].uop.uses_stq, slots_13.io.uop.uses_stq
connect issue_slots[13].uop.uses_ldq, slots_13.io.uop.uses_ldq
connect issue_slots[13].uop.is_amo, slots_13.io.uop.is_amo
connect issue_slots[13].uop.is_fencei, slots_13.io.uop.is_fencei
connect issue_slots[13].uop.is_fence, slots_13.io.uop.is_fence
connect issue_slots[13].uop.mem_signed, slots_13.io.uop.mem_signed
connect issue_slots[13].uop.mem_size, slots_13.io.uop.mem_size
connect issue_slots[13].uop.mem_cmd, slots_13.io.uop.mem_cmd
connect issue_slots[13].uop.bypassable, slots_13.io.uop.bypassable
connect issue_slots[13].uop.exc_cause, slots_13.io.uop.exc_cause
connect issue_slots[13].uop.exception, slots_13.io.uop.exception
connect issue_slots[13].uop.stale_pdst, slots_13.io.uop.stale_pdst
connect issue_slots[13].uop.ppred_busy, slots_13.io.uop.ppred_busy
connect issue_slots[13].uop.prs3_busy, slots_13.io.uop.prs3_busy
connect issue_slots[13].uop.prs2_busy, slots_13.io.uop.prs2_busy
connect issue_slots[13].uop.prs1_busy, slots_13.io.uop.prs1_busy
connect issue_slots[13].uop.ppred, slots_13.io.uop.ppred
connect issue_slots[13].uop.prs3, slots_13.io.uop.prs3
connect issue_slots[13].uop.prs2, slots_13.io.uop.prs2
connect issue_slots[13].uop.prs1, slots_13.io.uop.prs1
connect issue_slots[13].uop.pdst, slots_13.io.uop.pdst
connect issue_slots[13].uop.rxq_idx, slots_13.io.uop.rxq_idx
connect issue_slots[13].uop.stq_idx, slots_13.io.uop.stq_idx
connect issue_slots[13].uop.ldq_idx, slots_13.io.uop.ldq_idx
connect issue_slots[13].uop.rob_idx, slots_13.io.uop.rob_idx
connect issue_slots[13].uop.csr_addr, slots_13.io.uop.csr_addr
connect issue_slots[13].uop.imm_packed, slots_13.io.uop.imm_packed
connect issue_slots[13].uop.taken, slots_13.io.uop.taken
connect issue_slots[13].uop.pc_lob, slots_13.io.uop.pc_lob
connect issue_slots[13].uop.edge_inst, slots_13.io.uop.edge_inst
connect issue_slots[13].uop.ftq_idx, slots_13.io.uop.ftq_idx
connect issue_slots[13].uop.br_tag, slots_13.io.uop.br_tag
connect issue_slots[13].uop.br_mask, slots_13.io.uop.br_mask
connect issue_slots[13].uop.is_sfb, slots_13.io.uop.is_sfb
connect issue_slots[13].uop.is_jal, slots_13.io.uop.is_jal
connect issue_slots[13].uop.is_jalr, slots_13.io.uop.is_jalr
connect issue_slots[13].uop.is_br, slots_13.io.uop.is_br
connect issue_slots[13].uop.iw_p2_poisoned, slots_13.io.uop.iw_p2_poisoned
connect issue_slots[13].uop.iw_p1_poisoned, slots_13.io.uop.iw_p1_poisoned
connect issue_slots[13].uop.iw_state, slots_13.io.uop.iw_state
connect issue_slots[13].uop.ctrl.is_std, slots_13.io.uop.ctrl.is_std
connect issue_slots[13].uop.ctrl.is_sta, slots_13.io.uop.ctrl.is_sta
connect issue_slots[13].uop.ctrl.is_load, slots_13.io.uop.ctrl.is_load
connect issue_slots[13].uop.ctrl.csr_cmd, slots_13.io.uop.ctrl.csr_cmd
connect issue_slots[13].uop.ctrl.fcn_dw, slots_13.io.uop.ctrl.fcn_dw
connect issue_slots[13].uop.ctrl.op_fcn, slots_13.io.uop.ctrl.op_fcn
connect issue_slots[13].uop.ctrl.imm_sel, slots_13.io.uop.ctrl.imm_sel
connect issue_slots[13].uop.ctrl.op2_sel, slots_13.io.uop.ctrl.op2_sel
connect issue_slots[13].uop.ctrl.op1_sel, slots_13.io.uop.ctrl.op1_sel
connect issue_slots[13].uop.ctrl.br_type, slots_13.io.uop.ctrl.br_type
connect issue_slots[13].uop.fu_code, slots_13.io.uop.fu_code
connect issue_slots[13].uop.iq_type, slots_13.io.uop.iq_type
connect issue_slots[13].uop.debug_pc, slots_13.io.uop.debug_pc
connect issue_slots[13].uop.is_rvc, slots_13.io.uop.is_rvc
connect issue_slots[13].uop.debug_inst, slots_13.io.uop.debug_inst
connect issue_slots[13].uop.inst, slots_13.io.uop.inst
connect issue_slots[13].uop.uopc, slots_13.io.uop.uopc
connect issue_slots[13].out_uop.debug_tsrc, slots_13.io.out_uop.debug_tsrc
connect issue_slots[13].out_uop.debug_fsrc, slots_13.io.out_uop.debug_fsrc
connect issue_slots[13].out_uop.bp_xcpt_if, slots_13.io.out_uop.bp_xcpt_if
connect issue_slots[13].out_uop.bp_debug_if, slots_13.io.out_uop.bp_debug_if
connect issue_slots[13].out_uop.xcpt_ma_if, slots_13.io.out_uop.xcpt_ma_if
connect issue_slots[13].out_uop.xcpt_ae_if, slots_13.io.out_uop.xcpt_ae_if
connect issue_slots[13].out_uop.xcpt_pf_if, slots_13.io.out_uop.xcpt_pf_if
connect issue_slots[13].out_uop.fp_single, slots_13.io.out_uop.fp_single
connect issue_slots[13].out_uop.fp_val, slots_13.io.out_uop.fp_val
connect issue_slots[13].out_uop.frs3_en, slots_13.io.out_uop.frs3_en
connect issue_slots[13].out_uop.lrs2_rtype, slots_13.io.out_uop.lrs2_rtype
connect issue_slots[13].out_uop.lrs1_rtype, slots_13.io.out_uop.lrs1_rtype
connect issue_slots[13].out_uop.dst_rtype, slots_13.io.out_uop.dst_rtype
connect issue_slots[13].out_uop.ldst_val, slots_13.io.out_uop.ldst_val
connect issue_slots[13].out_uop.lrs3, slots_13.io.out_uop.lrs3
connect issue_slots[13].out_uop.lrs2, slots_13.io.out_uop.lrs2
connect issue_slots[13].out_uop.lrs1, slots_13.io.out_uop.lrs1
connect issue_slots[13].out_uop.ldst, slots_13.io.out_uop.ldst
connect issue_slots[13].out_uop.ldst_is_rs1, slots_13.io.out_uop.ldst_is_rs1
connect issue_slots[13].out_uop.flush_on_commit, slots_13.io.out_uop.flush_on_commit
connect issue_slots[13].out_uop.is_unique, slots_13.io.out_uop.is_unique
connect issue_slots[13].out_uop.is_sys_pc2epc, slots_13.io.out_uop.is_sys_pc2epc
connect issue_slots[13].out_uop.uses_stq, slots_13.io.out_uop.uses_stq
connect issue_slots[13].out_uop.uses_ldq, slots_13.io.out_uop.uses_ldq
connect issue_slots[13].out_uop.is_amo, slots_13.io.out_uop.is_amo
connect issue_slots[13].out_uop.is_fencei, slots_13.io.out_uop.is_fencei
connect issue_slots[13].out_uop.is_fence, slots_13.io.out_uop.is_fence
connect issue_slots[13].out_uop.mem_signed, slots_13.io.out_uop.mem_signed
connect issue_slots[13].out_uop.mem_size, slots_13.io.out_uop.mem_size
connect issue_slots[13].out_uop.mem_cmd, slots_13.io.out_uop.mem_cmd
connect issue_slots[13].out_uop.bypassable, slots_13.io.out_uop.bypassable
connect issue_slots[13].out_uop.exc_cause, slots_13.io.out_uop.exc_cause
connect issue_slots[13].out_uop.exception, slots_13.io.out_uop.exception
connect issue_slots[13].out_uop.stale_pdst, slots_13.io.out_uop.stale_pdst
connect issue_slots[13].out_uop.ppred_busy, slots_13.io.out_uop.ppred_busy
connect issue_slots[13].out_uop.prs3_busy, slots_13.io.out_uop.prs3_busy
connect issue_slots[13].out_uop.prs2_busy, slots_13.io.out_uop.prs2_busy
connect issue_slots[13].out_uop.prs1_busy, slots_13.io.out_uop.prs1_busy
connect issue_slots[13].out_uop.ppred, slots_13.io.out_uop.ppred
connect issue_slots[13].out_uop.prs3, slots_13.io.out_uop.prs3
connect issue_slots[13].out_uop.prs2, slots_13.io.out_uop.prs2
connect issue_slots[13].out_uop.prs1, slots_13.io.out_uop.prs1
connect issue_slots[13].out_uop.pdst, slots_13.io.out_uop.pdst
connect issue_slots[13].out_uop.rxq_idx, slots_13.io.out_uop.rxq_idx
connect issue_slots[13].out_uop.stq_idx, slots_13.io.out_uop.stq_idx
connect issue_slots[13].out_uop.ldq_idx, slots_13.io.out_uop.ldq_idx
connect issue_slots[13].out_uop.rob_idx, slots_13.io.out_uop.rob_idx
connect issue_slots[13].out_uop.csr_addr, slots_13.io.out_uop.csr_addr
connect issue_slots[13].out_uop.imm_packed, slots_13.io.out_uop.imm_packed
connect issue_slots[13].out_uop.taken, slots_13.io.out_uop.taken
connect issue_slots[13].out_uop.pc_lob, slots_13.io.out_uop.pc_lob
connect issue_slots[13].out_uop.edge_inst, slots_13.io.out_uop.edge_inst
connect issue_slots[13].out_uop.ftq_idx, slots_13.io.out_uop.ftq_idx
connect issue_slots[13].out_uop.br_tag, slots_13.io.out_uop.br_tag
connect issue_slots[13].out_uop.br_mask, slots_13.io.out_uop.br_mask
connect issue_slots[13].out_uop.is_sfb, slots_13.io.out_uop.is_sfb
connect issue_slots[13].out_uop.is_jal, slots_13.io.out_uop.is_jal
connect issue_slots[13].out_uop.is_jalr, slots_13.io.out_uop.is_jalr
connect issue_slots[13].out_uop.is_br, slots_13.io.out_uop.is_br
connect issue_slots[13].out_uop.iw_p2_poisoned, slots_13.io.out_uop.iw_p2_poisoned
connect issue_slots[13].out_uop.iw_p1_poisoned, slots_13.io.out_uop.iw_p1_poisoned
connect issue_slots[13].out_uop.iw_state, slots_13.io.out_uop.iw_state
connect issue_slots[13].out_uop.ctrl.is_std, slots_13.io.out_uop.ctrl.is_std
connect issue_slots[13].out_uop.ctrl.is_sta, slots_13.io.out_uop.ctrl.is_sta
connect issue_slots[13].out_uop.ctrl.is_load, slots_13.io.out_uop.ctrl.is_load
connect issue_slots[13].out_uop.ctrl.csr_cmd, slots_13.io.out_uop.ctrl.csr_cmd
connect issue_slots[13].out_uop.ctrl.fcn_dw, slots_13.io.out_uop.ctrl.fcn_dw
connect issue_slots[13].out_uop.ctrl.op_fcn, slots_13.io.out_uop.ctrl.op_fcn
connect issue_slots[13].out_uop.ctrl.imm_sel, slots_13.io.out_uop.ctrl.imm_sel
connect issue_slots[13].out_uop.ctrl.op2_sel, slots_13.io.out_uop.ctrl.op2_sel
connect issue_slots[13].out_uop.ctrl.op1_sel, slots_13.io.out_uop.ctrl.op1_sel
connect issue_slots[13].out_uop.ctrl.br_type, slots_13.io.out_uop.ctrl.br_type
connect issue_slots[13].out_uop.fu_code, slots_13.io.out_uop.fu_code
connect issue_slots[13].out_uop.iq_type, slots_13.io.out_uop.iq_type
connect issue_slots[13].out_uop.debug_pc, slots_13.io.out_uop.debug_pc
connect issue_slots[13].out_uop.is_rvc, slots_13.io.out_uop.is_rvc
connect issue_slots[13].out_uop.debug_inst, slots_13.io.out_uop.debug_inst
connect issue_slots[13].out_uop.inst, slots_13.io.out_uop.inst
connect issue_slots[13].out_uop.uopc, slots_13.io.out_uop.uopc
connect slots_13.io.in_uop.bits.debug_tsrc, issue_slots[13].in_uop.bits.debug_tsrc
connect slots_13.io.in_uop.bits.debug_fsrc, issue_slots[13].in_uop.bits.debug_fsrc
connect slots_13.io.in_uop.bits.bp_xcpt_if, issue_slots[13].in_uop.bits.bp_xcpt_if
connect slots_13.io.in_uop.bits.bp_debug_if, issue_slots[13].in_uop.bits.bp_debug_if
connect slots_13.io.in_uop.bits.xcpt_ma_if, issue_slots[13].in_uop.bits.xcpt_ma_if
connect slots_13.io.in_uop.bits.xcpt_ae_if, issue_slots[13].in_uop.bits.xcpt_ae_if
connect slots_13.io.in_uop.bits.xcpt_pf_if, issue_slots[13].in_uop.bits.xcpt_pf_if
connect slots_13.io.in_uop.bits.fp_single, issue_slots[13].in_uop.bits.fp_single
connect slots_13.io.in_uop.bits.fp_val, issue_slots[13].in_uop.bits.fp_val
connect slots_13.io.in_uop.bits.frs3_en, issue_slots[13].in_uop.bits.frs3_en
connect slots_13.io.in_uop.bits.lrs2_rtype, issue_slots[13].in_uop.bits.lrs2_rtype
connect slots_13.io.in_uop.bits.lrs1_rtype, issue_slots[13].in_uop.bits.lrs1_rtype
connect slots_13.io.in_uop.bits.dst_rtype, issue_slots[13].in_uop.bits.dst_rtype
connect slots_13.io.in_uop.bits.ldst_val, issue_slots[13].in_uop.bits.ldst_val
connect slots_13.io.in_uop.bits.lrs3, issue_slots[13].in_uop.bits.lrs3
connect slots_13.io.in_uop.bits.lrs2, issue_slots[13].in_uop.bits.lrs2
connect slots_13.io.in_uop.bits.lrs1, issue_slots[13].in_uop.bits.lrs1
connect slots_13.io.in_uop.bits.ldst, issue_slots[13].in_uop.bits.ldst
connect slots_13.io.in_uop.bits.ldst_is_rs1, issue_slots[13].in_uop.bits.ldst_is_rs1
connect slots_13.io.in_uop.bits.flush_on_commit, issue_slots[13].in_uop.bits.flush_on_commit
connect slots_13.io.in_uop.bits.is_unique, issue_slots[13].in_uop.bits.is_unique
connect slots_13.io.in_uop.bits.is_sys_pc2epc, issue_slots[13].in_uop.bits.is_sys_pc2epc
connect slots_13.io.in_uop.bits.uses_stq, issue_slots[13].in_uop.bits.uses_stq
connect slots_13.io.in_uop.bits.uses_ldq, issue_slots[13].in_uop.bits.uses_ldq
connect slots_13.io.in_uop.bits.is_amo, issue_slots[13].in_uop.bits.is_amo
connect slots_13.io.in_uop.bits.is_fencei, issue_slots[13].in_uop.bits.is_fencei
connect slots_13.io.in_uop.bits.is_fence, issue_slots[13].in_uop.bits.is_fence
connect slots_13.io.in_uop.bits.mem_signed, issue_slots[13].in_uop.bits.mem_signed
connect slots_13.io.in_uop.bits.mem_size, issue_slots[13].in_uop.bits.mem_size
connect slots_13.io.in_uop.bits.mem_cmd, issue_slots[13].in_uop.bits.mem_cmd
connect slots_13.io.in_uop.bits.bypassable, issue_slots[13].in_uop.bits.bypassable
connect slots_13.io.in_uop.bits.exc_cause, issue_slots[13].in_uop.bits.exc_cause
connect slots_13.io.in_uop.bits.exception, issue_slots[13].in_uop.bits.exception
connect slots_13.io.in_uop.bits.stale_pdst, issue_slots[13].in_uop.bits.stale_pdst
connect slots_13.io.in_uop.bits.ppred_busy, issue_slots[13].in_uop.bits.ppred_busy
connect slots_13.io.in_uop.bits.prs3_busy, issue_slots[13].in_uop.bits.prs3_busy
connect slots_13.io.in_uop.bits.prs2_busy, issue_slots[13].in_uop.bits.prs2_busy
connect slots_13.io.in_uop.bits.prs1_busy, issue_slots[13].in_uop.bits.prs1_busy
connect slots_13.io.in_uop.bits.ppred, issue_slots[13].in_uop.bits.ppred
connect slots_13.io.in_uop.bits.prs3, issue_slots[13].in_uop.bits.prs3
connect slots_13.io.in_uop.bits.prs2, issue_slots[13].in_uop.bits.prs2
connect slots_13.io.in_uop.bits.prs1, issue_slots[13].in_uop.bits.prs1
connect slots_13.io.in_uop.bits.pdst, issue_slots[13].in_uop.bits.pdst
connect slots_13.io.in_uop.bits.rxq_idx, issue_slots[13].in_uop.bits.rxq_idx
connect slots_13.io.in_uop.bits.stq_idx, issue_slots[13].in_uop.bits.stq_idx
connect slots_13.io.in_uop.bits.ldq_idx, issue_slots[13].in_uop.bits.ldq_idx
connect slots_13.io.in_uop.bits.rob_idx, issue_slots[13].in_uop.bits.rob_idx
connect slots_13.io.in_uop.bits.csr_addr, issue_slots[13].in_uop.bits.csr_addr
connect slots_13.io.in_uop.bits.imm_packed, issue_slots[13].in_uop.bits.imm_packed
connect slots_13.io.in_uop.bits.taken, issue_slots[13].in_uop.bits.taken
connect slots_13.io.in_uop.bits.pc_lob, issue_slots[13].in_uop.bits.pc_lob
connect slots_13.io.in_uop.bits.edge_inst, issue_slots[13].in_uop.bits.edge_inst
connect slots_13.io.in_uop.bits.ftq_idx, issue_slots[13].in_uop.bits.ftq_idx
connect slots_13.io.in_uop.bits.br_tag, issue_slots[13].in_uop.bits.br_tag
connect slots_13.io.in_uop.bits.br_mask, issue_slots[13].in_uop.bits.br_mask
connect slots_13.io.in_uop.bits.is_sfb, issue_slots[13].in_uop.bits.is_sfb
connect slots_13.io.in_uop.bits.is_jal, issue_slots[13].in_uop.bits.is_jal
connect slots_13.io.in_uop.bits.is_jalr, issue_slots[13].in_uop.bits.is_jalr
connect slots_13.io.in_uop.bits.is_br, issue_slots[13].in_uop.bits.is_br
connect slots_13.io.in_uop.bits.iw_p2_poisoned, issue_slots[13].in_uop.bits.iw_p2_poisoned
connect slots_13.io.in_uop.bits.iw_p1_poisoned, issue_slots[13].in_uop.bits.iw_p1_poisoned
connect slots_13.io.in_uop.bits.iw_state, issue_slots[13].in_uop.bits.iw_state
connect slots_13.io.in_uop.bits.ctrl.is_std, issue_slots[13].in_uop.bits.ctrl.is_std
connect slots_13.io.in_uop.bits.ctrl.is_sta, issue_slots[13].in_uop.bits.ctrl.is_sta
connect slots_13.io.in_uop.bits.ctrl.is_load, issue_slots[13].in_uop.bits.ctrl.is_load
connect slots_13.io.in_uop.bits.ctrl.csr_cmd, issue_slots[13].in_uop.bits.ctrl.csr_cmd
connect slots_13.io.in_uop.bits.ctrl.fcn_dw, issue_slots[13].in_uop.bits.ctrl.fcn_dw
connect slots_13.io.in_uop.bits.ctrl.op_fcn, issue_slots[13].in_uop.bits.ctrl.op_fcn
connect slots_13.io.in_uop.bits.ctrl.imm_sel, issue_slots[13].in_uop.bits.ctrl.imm_sel
connect slots_13.io.in_uop.bits.ctrl.op2_sel, issue_slots[13].in_uop.bits.ctrl.op2_sel
connect slots_13.io.in_uop.bits.ctrl.op1_sel, issue_slots[13].in_uop.bits.ctrl.op1_sel
connect slots_13.io.in_uop.bits.ctrl.br_type, issue_slots[13].in_uop.bits.ctrl.br_type
connect slots_13.io.in_uop.bits.fu_code, issue_slots[13].in_uop.bits.fu_code
connect slots_13.io.in_uop.bits.iq_type, issue_slots[13].in_uop.bits.iq_type
connect slots_13.io.in_uop.bits.debug_pc, issue_slots[13].in_uop.bits.debug_pc
connect slots_13.io.in_uop.bits.is_rvc, issue_slots[13].in_uop.bits.is_rvc
connect slots_13.io.in_uop.bits.debug_inst, issue_slots[13].in_uop.bits.debug_inst
connect slots_13.io.in_uop.bits.inst, issue_slots[13].in_uop.bits.inst
connect slots_13.io.in_uop.bits.uopc, issue_slots[13].in_uop.bits.uopc
connect slots_13.io.in_uop.valid, issue_slots[13].in_uop.valid
connect slots_13.io.spec_ld_wakeup[0].bits, issue_slots[13].spec_ld_wakeup[0].bits
connect slots_13.io.spec_ld_wakeup[0].valid, issue_slots[13].spec_ld_wakeup[0].valid
connect slots_13.io.pred_wakeup_port.bits, issue_slots[13].pred_wakeup_port.bits
connect slots_13.io.pred_wakeup_port.valid, issue_slots[13].pred_wakeup_port.valid
connect slots_13.io.wakeup_ports[0].bits.poisoned, issue_slots[13].wakeup_ports[0].bits.poisoned
connect slots_13.io.wakeup_ports[0].bits.pdst, issue_slots[13].wakeup_ports[0].bits.pdst
connect slots_13.io.wakeup_ports[0].valid, issue_slots[13].wakeup_ports[0].valid
connect slots_13.io.wakeup_ports[1].bits.poisoned, issue_slots[13].wakeup_ports[1].bits.poisoned
connect slots_13.io.wakeup_ports[1].bits.pdst, issue_slots[13].wakeup_ports[1].bits.pdst
connect slots_13.io.wakeup_ports[1].valid, issue_slots[13].wakeup_ports[1].valid
connect slots_13.io.ldspec_miss, issue_slots[13].ldspec_miss
connect slots_13.io.clear, issue_slots[13].clear
connect slots_13.io.kill, issue_slots[13].kill
connect slots_13.io.brupdate.b2.target_offset, issue_slots[13].brupdate.b2.target_offset
connect slots_13.io.brupdate.b2.jalr_target, issue_slots[13].brupdate.b2.jalr_target
connect slots_13.io.brupdate.b2.pc_sel, issue_slots[13].brupdate.b2.pc_sel
connect slots_13.io.brupdate.b2.cfi_type, issue_slots[13].brupdate.b2.cfi_type
connect slots_13.io.brupdate.b2.taken, issue_slots[13].brupdate.b2.taken
connect slots_13.io.brupdate.b2.mispredict, issue_slots[13].brupdate.b2.mispredict
connect slots_13.io.brupdate.b2.valid, issue_slots[13].brupdate.b2.valid
connect slots_13.io.brupdate.b2.uop.debug_tsrc, issue_slots[13].brupdate.b2.uop.debug_tsrc
connect slots_13.io.brupdate.b2.uop.debug_fsrc, issue_slots[13].brupdate.b2.uop.debug_fsrc
connect slots_13.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[13].brupdate.b2.uop.bp_xcpt_if
connect slots_13.io.brupdate.b2.uop.bp_debug_if, issue_slots[13].brupdate.b2.uop.bp_debug_if
connect slots_13.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[13].brupdate.b2.uop.xcpt_ma_if
connect slots_13.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[13].brupdate.b2.uop.xcpt_ae_if
connect slots_13.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[13].brupdate.b2.uop.xcpt_pf_if
connect slots_13.io.brupdate.b2.uop.fp_single, issue_slots[13].brupdate.b2.uop.fp_single
connect slots_13.io.brupdate.b2.uop.fp_val, issue_slots[13].brupdate.b2.uop.fp_val
connect slots_13.io.brupdate.b2.uop.frs3_en, issue_slots[13].brupdate.b2.uop.frs3_en
connect slots_13.io.brupdate.b2.uop.lrs2_rtype, issue_slots[13].brupdate.b2.uop.lrs2_rtype
connect slots_13.io.brupdate.b2.uop.lrs1_rtype, issue_slots[13].brupdate.b2.uop.lrs1_rtype
connect slots_13.io.brupdate.b2.uop.dst_rtype, issue_slots[13].brupdate.b2.uop.dst_rtype
connect slots_13.io.brupdate.b2.uop.ldst_val, issue_slots[13].brupdate.b2.uop.ldst_val
connect slots_13.io.brupdate.b2.uop.lrs3, issue_slots[13].brupdate.b2.uop.lrs3
connect slots_13.io.brupdate.b2.uop.lrs2, issue_slots[13].brupdate.b2.uop.lrs2
connect slots_13.io.brupdate.b2.uop.lrs1, issue_slots[13].brupdate.b2.uop.lrs1
connect slots_13.io.brupdate.b2.uop.ldst, issue_slots[13].brupdate.b2.uop.ldst
connect slots_13.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[13].brupdate.b2.uop.ldst_is_rs1
connect slots_13.io.brupdate.b2.uop.flush_on_commit, issue_slots[13].brupdate.b2.uop.flush_on_commit
connect slots_13.io.brupdate.b2.uop.is_unique, issue_slots[13].brupdate.b2.uop.is_unique
connect slots_13.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[13].brupdate.b2.uop.is_sys_pc2epc
connect slots_13.io.brupdate.b2.uop.uses_stq, issue_slots[13].brupdate.b2.uop.uses_stq
connect slots_13.io.brupdate.b2.uop.uses_ldq, issue_slots[13].brupdate.b2.uop.uses_ldq
connect slots_13.io.brupdate.b2.uop.is_amo, issue_slots[13].brupdate.b2.uop.is_amo
connect slots_13.io.brupdate.b2.uop.is_fencei, issue_slots[13].brupdate.b2.uop.is_fencei
connect slots_13.io.brupdate.b2.uop.is_fence, issue_slots[13].brupdate.b2.uop.is_fence
connect slots_13.io.brupdate.b2.uop.mem_signed, issue_slots[13].brupdate.b2.uop.mem_signed
connect slots_13.io.brupdate.b2.uop.mem_size, issue_slots[13].brupdate.b2.uop.mem_size
connect slots_13.io.brupdate.b2.uop.mem_cmd, issue_slots[13].brupdate.b2.uop.mem_cmd
connect slots_13.io.brupdate.b2.uop.bypassable, issue_slots[13].brupdate.b2.uop.bypassable
connect slots_13.io.brupdate.b2.uop.exc_cause, issue_slots[13].brupdate.b2.uop.exc_cause
connect slots_13.io.brupdate.b2.uop.exception, issue_slots[13].brupdate.b2.uop.exception
connect slots_13.io.brupdate.b2.uop.stale_pdst, issue_slots[13].brupdate.b2.uop.stale_pdst
connect slots_13.io.brupdate.b2.uop.ppred_busy, issue_slots[13].brupdate.b2.uop.ppred_busy
connect slots_13.io.brupdate.b2.uop.prs3_busy, issue_slots[13].brupdate.b2.uop.prs3_busy
connect slots_13.io.brupdate.b2.uop.prs2_busy, issue_slots[13].brupdate.b2.uop.prs2_busy
connect slots_13.io.brupdate.b2.uop.prs1_busy, issue_slots[13].brupdate.b2.uop.prs1_busy
connect slots_13.io.brupdate.b2.uop.ppred, issue_slots[13].brupdate.b2.uop.ppred
connect slots_13.io.brupdate.b2.uop.prs3, issue_slots[13].brupdate.b2.uop.prs3
connect slots_13.io.brupdate.b2.uop.prs2, issue_slots[13].brupdate.b2.uop.prs2
connect slots_13.io.brupdate.b2.uop.prs1, issue_slots[13].brupdate.b2.uop.prs1
connect slots_13.io.brupdate.b2.uop.pdst, issue_slots[13].brupdate.b2.uop.pdst
connect slots_13.io.brupdate.b2.uop.rxq_idx, issue_slots[13].brupdate.b2.uop.rxq_idx
connect slots_13.io.brupdate.b2.uop.stq_idx, issue_slots[13].brupdate.b2.uop.stq_idx
connect slots_13.io.brupdate.b2.uop.ldq_idx, issue_slots[13].brupdate.b2.uop.ldq_idx
connect slots_13.io.brupdate.b2.uop.rob_idx, issue_slots[13].brupdate.b2.uop.rob_idx
connect slots_13.io.brupdate.b2.uop.csr_addr, issue_slots[13].brupdate.b2.uop.csr_addr
connect slots_13.io.brupdate.b2.uop.imm_packed, issue_slots[13].brupdate.b2.uop.imm_packed
connect slots_13.io.brupdate.b2.uop.taken, issue_slots[13].brupdate.b2.uop.taken
connect slots_13.io.brupdate.b2.uop.pc_lob, issue_slots[13].brupdate.b2.uop.pc_lob
connect slots_13.io.brupdate.b2.uop.edge_inst, issue_slots[13].brupdate.b2.uop.edge_inst
connect slots_13.io.brupdate.b2.uop.ftq_idx, issue_slots[13].brupdate.b2.uop.ftq_idx
connect slots_13.io.brupdate.b2.uop.br_tag, issue_slots[13].brupdate.b2.uop.br_tag
connect slots_13.io.brupdate.b2.uop.br_mask, issue_slots[13].brupdate.b2.uop.br_mask
connect slots_13.io.brupdate.b2.uop.is_sfb, issue_slots[13].brupdate.b2.uop.is_sfb
connect slots_13.io.brupdate.b2.uop.is_jal, issue_slots[13].brupdate.b2.uop.is_jal
connect slots_13.io.brupdate.b2.uop.is_jalr, issue_slots[13].brupdate.b2.uop.is_jalr
connect slots_13.io.brupdate.b2.uop.is_br, issue_slots[13].brupdate.b2.uop.is_br
connect slots_13.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[13].brupdate.b2.uop.iw_p2_poisoned
connect slots_13.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[13].brupdate.b2.uop.iw_p1_poisoned
connect slots_13.io.brupdate.b2.uop.iw_state, issue_slots[13].brupdate.b2.uop.iw_state
connect slots_13.io.brupdate.b2.uop.ctrl.is_std, issue_slots[13].brupdate.b2.uop.ctrl.is_std
connect slots_13.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[13].brupdate.b2.uop.ctrl.is_sta
connect slots_13.io.brupdate.b2.uop.ctrl.is_load, issue_slots[13].brupdate.b2.uop.ctrl.is_load
connect slots_13.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[13].brupdate.b2.uop.ctrl.csr_cmd
connect slots_13.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[13].brupdate.b2.uop.ctrl.fcn_dw
connect slots_13.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[13].brupdate.b2.uop.ctrl.op_fcn
connect slots_13.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[13].brupdate.b2.uop.ctrl.imm_sel
connect slots_13.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[13].brupdate.b2.uop.ctrl.op2_sel
connect slots_13.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[13].brupdate.b2.uop.ctrl.op1_sel
connect slots_13.io.brupdate.b2.uop.ctrl.br_type, issue_slots[13].brupdate.b2.uop.ctrl.br_type
connect slots_13.io.brupdate.b2.uop.fu_code, issue_slots[13].brupdate.b2.uop.fu_code
connect slots_13.io.brupdate.b2.uop.iq_type, issue_slots[13].brupdate.b2.uop.iq_type
connect slots_13.io.brupdate.b2.uop.debug_pc, issue_slots[13].brupdate.b2.uop.debug_pc
connect slots_13.io.brupdate.b2.uop.is_rvc, issue_slots[13].brupdate.b2.uop.is_rvc
connect slots_13.io.brupdate.b2.uop.debug_inst, issue_slots[13].brupdate.b2.uop.debug_inst
connect slots_13.io.brupdate.b2.uop.inst, issue_slots[13].brupdate.b2.uop.inst
connect slots_13.io.brupdate.b2.uop.uopc, issue_slots[13].brupdate.b2.uop.uopc
connect slots_13.io.brupdate.b1.mispredict_mask, issue_slots[13].brupdate.b1.mispredict_mask
connect slots_13.io.brupdate.b1.resolve_mask, issue_slots[13].brupdate.b1.resolve_mask
connect slots_13.io.grant, issue_slots[13].grant
connect issue_slots[13].request_hp, slots_13.io.request_hp
connect issue_slots[13].request, slots_13.io.request
connect issue_slots[13].will_be_valid, slots_13.io.will_be_valid
connect issue_slots[13].valid, slots_13.io.valid
connect issue_slots[14].debug.state, slots_14.io.debug.state
connect issue_slots[14].debug.ppred, slots_14.io.debug.ppred
connect issue_slots[14].debug.p3, slots_14.io.debug.p3
connect issue_slots[14].debug.p2, slots_14.io.debug.p2
connect issue_slots[14].debug.p1, slots_14.io.debug.p1
connect issue_slots[14].uop.debug_tsrc, slots_14.io.uop.debug_tsrc
connect issue_slots[14].uop.debug_fsrc, slots_14.io.uop.debug_fsrc
connect issue_slots[14].uop.bp_xcpt_if, slots_14.io.uop.bp_xcpt_if
connect issue_slots[14].uop.bp_debug_if, slots_14.io.uop.bp_debug_if
connect issue_slots[14].uop.xcpt_ma_if, slots_14.io.uop.xcpt_ma_if
connect issue_slots[14].uop.xcpt_ae_if, slots_14.io.uop.xcpt_ae_if
connect issue_slots[14].uop.xcpt_pf_if, slots_14.io.uop.xcpt_pf_if
connect issue_slots[14].uop.fp_single, slots_14.io.uop.fp_single
connect issue_slots[14].uop.fp_val, slots_14.io.uop.fp_val
connect issue_slots[14].uop.frs3_en, slots_14.io.uop.frs3_en
connect issue_slots[14].uop.lrs2_rtype, slots_14.io.uop.lrs2_rtype
connect issue_slots[14].uop.lrs1_rtype, slots_14.io.uop.lrs1_rtype
connect issue_slots[14].uop.dst_rtype, slots_14.io.uop.dst_rtype
connect issue_slots[14].uop.ldst_val, slots_14.io.uop.ldst_val
connect issue_slots[14].uop.lrs3, slots_14.io.uop.lrs3
connect issue_slots[14].uop.lrs2, slots_14.io.uop.lrs2
connect issue_slots[14].uop.lrs1, slots_14.io.uop.lrs1
connect issue_slots[14].uop.ldst, slots_14.io.uop.ldst
connect issue_slots[14].uop.ldst_is_rs1, slots_14.io.uop.ldst_is_rs1
connect issue_slots[14].uop.flush_on_commit, slots_14.io.uop.flush_on_commit
connect issue_slots[14].uop.is_unique, slots_14.io.uop.is_unique
connect issue_slots[14].uop.is_sys_pc2epc, slots_14.io.uop.is_sys_pc2epc
connect issue_slots[14].uop.uses_stq, slots_14.io.uop.uses_stq
connect issue_slots[14].uop.uses_ldq, slots_14.io.uop.uses_ldq
connect issue_slots[14].uop.is_amo, slots_14.io.uop.is_amo
connect issue_slots[14].uop.is_fencei, slots_14.io.uop.is_fencei
connect issue_slots[14].uop.is_fence, slots_14.io.uop.is_fence
connect issue_slots[14].uop.mem_signed, slots_14.io.uop.mem_signed
connect issue_slots[14].uop.mem_size, slots_14.io.uop.mem_size
connect issue_slots[14].uop.mem_cmd, slots_14.io.uop.mem_cmd
connect issue_slots[14].uop.bypassable, slots_14.io.uop.bypassable
connect issue_slots[14].uop.exc_cause, slots_14.io.uop.exc_cause
connect issue_slots[14].uop.exception, slots_14.io.uop.exception
connect issue_slots[14].uop.stale_pdst, slots_14.io.uop.stale_pdst
connect issue_slots[14].uop.ppred_busy, slots_14.io.uop.ppred_busy
connect issue_slots[14].uop.prs3_busy, slots_14.io.uop.prs3_busy
connect issue_slots[14].uop.prs2_busy, slots_14.io.uop.prs2_busy
connect issue_slots[14].uop.prs1_busy, slots_14.io.uop.prs1_busy
connect issue_slots[14].uop.ppred, slots_14.io.uop.ppred
connect issue_slots[14].uop.prs3, slots_14.io.uop.prs3
connect issue_slots[14].uop.prs2, slots_14.io.uop.prs2
connect issue_slots[14].uop.prs1, slots_14.io.uop.prs1
connect issue_slots[14].uop.pdst, slots_14.io.uop.pdst
connect issue_slots[14].uop.rxq_idx, slots_14.io.uop.rxq_idx
connect issue_slots[14].uop.stq_idx, slots_14.io.uop.stq_idx
connect issue_slots[14].uop.ldq_idx, slots_14.io.uop.ldq_idx
connect issue_slots[14].uop.rob_idx, slots_14.io.uop.rob_idx
connect issue_slots[14].uop.csr_addr, slots_14.io.uop.csr_addr
connect issue_slots[14].uop.imm_packed, slots_14.io.uop.imm_packed
connect issue_slots[14].uop.taken, slots_14.io.uop.taken
connect issue_slots[14].uop.pc_lob, slots_14.io.uop.pc_lob
connect issue_slots[14].uop.edge_inst, slots_14.io.uop.edge_inst
connect issue_slots[14].uop.ftq_idx, slots_14.io.uop.ftq_idx
connect issue_slots[14].uop.br_tag, slots_14.io.uop.br_tag
connect issue_slots[14].uop.br_mask, slots_14.io.uop.br_mask
connect issue_slots[14].uop.is_sfb, slots_14.io.uop.is_sfb
connect issue_slots[14].uop.is_jal, slots_14.io.uop.is_jal
connect issue_slots[14].uop.is_jalr, slots_14.io.uop.is_jalr
connect issue_slots[14].uop.is_br, slots_14.io.uop.is_br
connect issue_slots[14].uop.iw_p2_poisoned, slots_14.io.uop.iw_p2_poisoned
connect issue_slots[14].uop.iw_p1_poisoned, slots_14.io.uop.iw_p1_poisoned
connect issue_slots[14].uop.iw_state, slots_14.io.uop.iw_state
connect issue_slots[14].uop.ctrl.is_std, slots_14.io.uop.ctrl.is_std
connect issue_slots[14].uop.ctrl.is_sta, slots_14.io.uop.ctrl.is_sta
connect issue_slots[14].uop.ctrl.is_load, slots_14.io.uop.ctrl.is_load
connect issue_slots[14].uop.ctrl.csr_cmd, slots_14.io.uop.ctrl.csr_cmd
connect issue_slots[14].uop.ctrl.fcn_dw, slots_14.io.uop.ctrl.fcn_dw
connect issue_slots[14].uop.ctrl.op_fcn, slots_14.io.uop.ctrl.op_fcn
connect issue_slots[14].uop.ctrl.imm_sel, slots_14.io.uop.ctrl.imm_sel
connect issue_slots[14].uop.ctrl.op2_sel, slots_14.io.uop.ctrl.op2_sel
connect issue_slots[14].uop.ctrl.op1_sel, slots_14.io.uop.ctrl.op1_sel
connect issue_slots[14].uop.ctrl.br_type, slots_14.io.uop.ctrl.br_type
connect issue_slots[14].uop.fu_code, slots_14.io.uop.fu_code
connect issue_slots[14].uop.iq_type, slots_14.io.uop.iq_type
connect issue_slots[14].uop.debug_pc, slots_14.io.uop.debug_pc
connect issue_slots[14].uop.is_rvc, slots_14.io.uop.is_rvc
connect issue_slots[14].uop.debug_inst, slots_14.io.uop.debug_inst
connect issue_slots[14].uop.inst, slots_14.io.uop.inst
connect issue_slots[14].uop.uopc, slots_14.io.uop.uopc
connect issue_slots[14].out_uop.debug_tsrc, slots_14.io.out_uop.debug_tsrc
connect issue_slots[14].out_uop.debug_fsrc, slots_14.io.out_uop.debug_fsrc
connect issue_slots[14].out_uop.bp_xcpt_if, slots_14.io.out_uop.bp_xcpt_if
connect issue_slots[14].out_uop.bp_debug_if, slots_14.io.out_uop.bp_debug_if
connect issue_slots[14].out_uop.xcpt_ma_if, slots_14.io.out_uop.xcpt_ma_if
connect issue_slots[14].out_uop.xcpt_ae_if, slots_14.io.out_uop.xcpt_ae_if
connect issue_slots[14].out_uop.xcpt_pf_if, slots_14.io.out_uop.xcpt_pf_if
connect issue_slots[14].out_uop.fp_single, slots_14.io.out_uop.fp_single
connect issue_slots[14].out_uop.fp_val, slots_14.io.out_uop.fp_val
connect issue_slots[14].out_uop.frs3_en, slots_14.io.out_uop.frs3_en
connect issue_slots[14].out_uop.lrs2_rtype, slots_14.io.out_uop.lrs2_rtype
connect issue_slots[14].out_uop.lrs1_rtype, slots_14.io.out_uop.lrs1_rtype
connect issue_slots[14].out_uop.dst_rtype, slots_14.io.out_uop.dst_rtype
connect issue_slots[14].out_uop.ldst_val, slots_14.io.out_uop.ldst_val
connect issue_slots[14].out_uop.lrs3, slots_14.io.out_uop.lrs3
connect issue_slots[14].out_uop.lrs2, slots_14.io.out_uop.lrs2
connect issue_slots[14].out_uop.lrs1, slots_14.io.out_uop.lrs1
connect issue_slots[14].out_uop.ldst, slots_14.io.out_uop.ldst
connect issue_slots[14].out_uop.ldst_is_rs1, slots_14.io.out_uop.ldst_is_rs1
connect issue_slots[14].out_uop.flush_on_commit, slots_14.io.out_uop.flush_on_commit
connect issue_slots[14].out_uop.is_unique, slots_14.io.out_uop.is_unique
connect issue_slots[14].out_uop.is_sys_pc2epc, slots_14.io.out_uop.is_sys_pc2epc
connect issue_slots[14].out_uop.uses_stq, slots_14.io.out_uop.uses_stq
connect issue_slots[14].out_uop.uses_ldq, slots_14.io.out_uop.uses_ldq
connect issue_slots[14].out_uop.is_amo, slots_14.io.out_uop.is_amo
connect issue_slots[14].out_uop.is_fencei, slots_14.io.out_uop.is_fencei
connect issue_slots[14].out_uop.is_fence, slots_14.io.out_uop.is_fence
connect issue_slots[14].out_uop.mem_signed, slots_14.io.out_uop.mem_signed
connect issue_slots[14].out_uop.mem_size, slots_14.io.out_uop.mem_size
connect issue_slots[14].out_uop.mem_cmd, slots_14.io.out_uop.mem_cmd
connect issue_slots[14].out_uop.bypassable, slots_14.io.out_uop.bypassable
connect issue_slots[14].out_uop.exc_cause, slots_14.io.out_uop.exc_cause
connect issue_slots[14].out_uop.exception, slots_14.io.out_uop.exception
connect issue_slots[14].out_uop.stale_pdst, slots_14.io.out_uop.stale_pdst
connect issue_slots[14].out_uop.ppred_busy, slots_14.io.out_uop.ppred_busy
connect issue_slots[14].out_uop.prs3_busy, slots_14.io.out_uop.prs3_busy
connect issue_slots[14].out_uop.prs2_busy, slots_14.io.out_uop.prs2_busy
connect issue_slots[14].out_uop.prs1_busy, slots_14.io.out_uop.prs1_busy
connect issue_slots[14].out_uop.ppred, slots_14.io.out_uop.ppred
connect issue_slots[14].out_uop.prs3, slots_14.io.out_uop.prs3
connect issue_slots[14].out_uop.prs2, slots_14.io.out_uop.prs2
connect issue_slots[14].out_uop.prs1, slots_14.io.out_uop.prs1
connect issue_slots[14].out_uop.pdst, slots_14.io.out_uop.pdst
connect issue_slots[14].out_uop.rxq_idx, slots_14.io.out_uop.rxq_idx
connect issue_slots[14].out_uop.stq_idx, slots_14.io.out_uop.stq_idx
connect issue_slots[14].out_uop.ldq_idx, slots_14.io.out_uop.ldq_idx
connect issue_slots[14].out_uop.rob_idx, slots_14.io.out_uop.rob_idx
connect issue_slots[14].out_uop.csr_addr, slots_14.io.out_uop.csr_addr
connect issue_slots[14].out_uop.imm_packed, slots_14.io.out_uop.imm_packed
connect issue_slots[14].out_uop.taken, slots_14.io.out_uop.taken
connect issue_slots[14].out_uop.pc_lob, slots_14.io.out_uop.pc_lob
connect issue_slots[14].out_uop.edge_inst, slots_14.io.out_uop.edge_inst
connect issue_slots[14].out_uop.ftq_idx, slots_14.io.out_uop.ftq_idx
connect issue_slots[14].out_uop.br_tag, slots_14.io.out_uop.br_tag
connect issue_slots[14].out_uop.br_mask, slots_14.io.out_uop.br_mask
connect issue_slots[14].out_uop.is_sfb, slots_14.io.out_uop.is_sfb
connect issue_slots[14].out_uop.is_jal, slots_14.io.out_uop.is_jal
connect issue_slots[14].out_uop.is_jalr, slots_14.io.out_uop.is_jalr
connect issue_slots[14].out_uop.is_br, slots_14.io.out_uop.is_br
connect issue_slots[14].out_uop.iw_p2_poisoned, slots_14.io.out_uop.iw_p2_poisoned
connect issue_slots[14].out_uop.iw_p1_poisoned, slots_14.io.out_uop.iw_p1_poisoned
connect issue_slots[14].out_uop.iw_state, slots_14.io.out_uop.iw_state
connect issue_slots[14].out_uop.ctrl.is_std, slots_14.io.out_uop.ctrl.is_std
connect issue_slots[14].out_uop.ctrl.is_sta, slots_14.io.out_uop.ctrl.is_sta
connect issue_slots[14].out_uop.ctrl.is_load, slots_14.io.out_uop.ctrl.is_load
connect issue_slots[14].out_uop.ctrl.csr_cmd, slots_14.io.out_uop.ctrl.csr_cmd
connect issue_slots[14].out_uop.ctrl.fcn_dw, slots_14.io.out_uop.ctrl.fcn_dw
connect issue_slots[14].out_uop.ctrl.op_fcn, slots_14.io.out_uop.ctrl.op_fcn
connect issue_slots[14].out_uop.ctrl.imm_sel, slots_14.io.out_uop.ctrl.imm_sel
connect issue_slots[14].out_uop.ctrl.op2_sel, slots_14.io.out_uop.ctrl.op2_sel
connect issue_slots[14].out_uop.ctrl.op1_sel, slots_14.io.out_uop.ctrl.op1_sel
connect issue_slots[14].out_uop.ctrl.br_type, slots_14.io.out_uop.ctrl.br_type
connect issue_slots[14].out_uop.fu_code, slots_14.io.out_uop.fu_code
connect issue_slots[14].out_uop.iq_type, slots_14.io.out_uop.iq_type
connect issue_slots[14].out_uop.debug_pc, slots_14.io.out_uop.debug_pc
connect issue_slots[14].out_uop.is_rvc, slots_14.io.out_uop.is_rvc
connect issue_slots[14].out_uop.debug_inst, slots_14.io.out_uop.debug_inst
connect issue_slots[14].out_uop.inst, slots_14.io.out_uop.inst
connect issue_slots[14].out_uop.uopc, slots_14.io.out_uop.uopc
connect slots_14.io.in_uop.bits.debug_tsrc, issue_slots[14].in_uop.bits.debug_tsrc
connect slots_14.io.in_uop.bits.debug_fsrc, issue_slots[14].in_uop.bits.debug_fsrc
connect slots_14.io.in_uop.bits.bp_xcpt_if, issue_slots[14].in_uop.bits.bp_xcpt_if
connect slots_14.io.in_uop.bits.bp_debug_if, issue_slots[14].in_uop.bits.bp_debug_if
connect slots_14.io.in_uop.bits.xcpt_ma_if, issue_slots[14].in_uop.bits.xcpt_ma_if
connect slots_14.io.in_uop.bits.xcpt_ae_if, issue_slots[14].in_uop.bits.xcpt_ae_if
connect slots_14.io.in_uop.bits.xcpt_pf_if, issue_slots[14].in_uop.bits.xcpt_pf_if
connect slots_14.io.in_uop.bits.fp_single, issue_slots[14].in_uop.bits.fp_single
connect slots_14.io.in_uop.bits.fp_val, issue_slots[14].in_uop.bits.fp_val
connect slots_14.io.in_uop.bits.frs3_en, issue_slots[14].in_uop.bits.frs3_en
connect slots_14.io.in_uop.bits.lrs2_rtype, issue_slots[14].in_uop.bits.lrs2_rtype
connect slots_14.io.in_uop.bits.lrs1_rtype, issue_slots[14].in_uop.bits.lrs1_rtype
connect slots_14.io.in_uop.bits.dst_rtype, issue_slots[14].in_uop.bits.dst_rtype
connect slots_14.io.in_uop.bits.ldst_val, issue_slots[14].in_uop.bits.ldst_val
connect slots_14.io.in_uop.bits.lrs3, issue_slots[14].in_uop.bits.lrs3
connect slots_14.io.in_uop.bits.lrs2, issue_slots[14].in_uop.bits.lrs2
connect slots_14.io.in_uop.bits.lrs1, issue_slots[14].in_uop.bits.lrs1
connect slots_14.io.in_uop.bits.ldst, issue_slots[14].in_uop.bits.ldst
connect slots_14.io.in_uop.bits.ldst_is_rs1, issue_slots[14].in_uop.bits.ldst_is_rs1
connect slots_14.io.in_uop.bits.flush_on_commit, issue_slots[14].in_uop.bits.flush_on_commit
connect slots_14.io.in_uop.bits.is_unique, issue_slots[14].in_uop.bits.is_unique
connect slots_14.io.in_uop.bits.is_sys_pc2epc, issue_slots[14].in_uop.bits.is_sys_pc2epc
connect slots_14.io.in_uop.bits.uses_stq, issue_slots[14].in_uop.bits.uses_stq
connect slots_14.io.in_uop.bits.uses_ldq, issue_slots[14].in_uop.bits.uses_ldq
connect slots_14.io.in_uop.bits.is_amo, issue_slots[14].in_uop.bits.is_amo
connect slots_14.io.in_uop.bits.is_fencei, issue_slots[14].in_uop.bits.is_fencei
connect slots_14.io.in_uop.bits.is_fence, issue_slots[14].in_uop.bits.is_fence
connect slots_14.io.in_uop.bits.mem_signed, issue_slots[14].in_uop.bits.mem_signed
connect slots_14.io.in_uop.bits.mem_size, issue_slots[14].in_uop.bits.mem_size
connect slots_14.io.in_uop.bits.mem_cmd, issue_slots[14].in_uop.bits.mem_cmd
connect slots_14.io.in_uop.bits.bypassable, issue_slots[14].in_uop.bits.bypassable
connect slots_14.io.in_uop.bits.exc_cause, issue_slots[14].in_uop.bits.exc_cause
connect slots_14.io.in_uop.bits.exception, issue_slots[14].in_uop.bits.exception
connect slots_14.io.in_uop.bits.stale_pdst, issue_slots[14].in_uop.bits.stale_pdst
connect slots_14.io.in_uop.bits.ppred_busy, issue_slots[14].in_uop.bits.ppred_busy
connect slots_14.io.in_uop.bits.prs3_busy, issue_slots[14].in_uop.bits.prs3_busy
connect slots_14.io.in_uop.bits.prs2_busy, issue_slots[14].in_uop.bits.prs2_busy
connect slots_14.io.in_uop.bits.prs1_busy, issue_slots[14].in_uop.bits.prs1_busy
connect slots_14.io.in_uop.bits.ppred, issue_slots[14].in_uop.bits.ppred
connect slots_14.io.in_uop.bits.prs3, issue_slots[14].in_uop.bits.prs3
connect slots_14.io.in_uop.bits.prs2, issue_slots[14].in_uop.bits.prs2
connect slots_14.io.in_uop.bits.prs1, issue_slots[14].in_uop.bits.prs1
connect slots_14.io.in_uop.bits.pdst, issue_slots[14].in_uop.bits.pdst
connect slots_14.io.in_uop.bits.rxq_idx, issue_slots[14].in_uop.bits.rxq_idx
connect slots_14.io.in_uop.bits.stq_idx, issue_slots[14].in_uop.bits.stq_idx
connect slots_14.io.in_uop.bits.ldq_idx, issue_slots[14].in_uop.bits.ldq_idx
connect slots_14.io.in_uop.bits.rob_idx, issue_slots[14].in_uop.bits.rob_idx
connect slots_14.io.in_uop.bits.csr_addr, issue_slots[14].in_uop.bits.csr_addr
connect slots_14.io.in_uop.bits.imm_packed, issue_slots[14].in_uop.bits.imm_packed
connect slots_14.io.in_uop.bits.taken, issue_slots[14].in_uop.bits.taken
connect slots_14.io.in_uop.bits.pc_lob, issue_slots[14].in_uop.bits.pc_lob
connect slots_14.io.in_uop.bits.edge_inst, issue_slots[14].in_uop.bits.edge_inst
connect slots_14.io.in_uop.bits.ftq_idx, issue_slots[14].in_uop.bits.ftq_idx
connect slots_14.io.in_uop.bits.br_tag, issue_slots[14].in_uop.bits.br_tag
connect slots_14.io.in_uop.bits.br_mask, issue_slots[14].in_uop.bits.br_mask
connect slots_14.io.in_uop.bits.is_sfb, issue_slots[14].in_uop.bits.is_sfb
connect slots_14.io.in_uop.bits.is_jal, issue_slots[14].in_uop.bits.is_jal
connect slots_14.io.in_uop.bits.is_jalr, issue_slots[14].in_uop.bits.is_jalr
connect slots_14.io.in_uop.bits.is_br, issue_slots[14].in_uop.bits.is_br
connect slots_14.io.in_uop.bits.iw_p2_poisoned, issue_slots[14].in_uop.bits.iw_p2_poisoned
connect slots_14.io.in_uop.bits.iw_p1_poisoned, issue_slots[14].in_uop.bits.iw_p1_poisoned
connect slots_14.io.in_uop.bits.iw_state, issue_slots[14].in_uop.bits.iw_state
connect slots_14.io.in_uop.bits.ctrl.is_std, issue_slots[14].in_uop.bits.ctrl.is_std
connect slots_14.io.in_uop.bits.ctrl.is_sta, issue_slots[14].in_uop.bits.ctrl.is_sta
connect slots_14.io.in_uop.bits.ctrl.is_load, issue_slots[14].in_uop.bits.ctrl.is_load
connect slots_14.io.in_uop.bits.ctrl.csr_cmd, issue_slots[14].in_uop.bits.ctrl.csr_cmd
connect slots_14.io.in_uop.bits.ctrl.fcn_dw, issue_slots[14].in_uop.bits.ctrl.fcn_dw
connect slots_14.io.in_uop.bits.ctrl.op_fcn, issue_slots[14].in_uop.bits.ctrl.op_fcn
connect slots_14.io.in_uop.bits.ctrl.imm_sel, issue_slots[14].in_uop.bits.ctrl.imm_sel
connect slots_14.io.in_uop.bits.ctrl.op2_sel, issue_slots[14].in_uop.bits.ctrl.op2_sel
connect slots_14.io.in_uop.bits.ctrl.op1_sel, issue_slots[14].in_uop.bits.ctrl.op1_sel
connect slots_14.io.in_uop.bits.ctrl.br_type, issue_slots[14].in_uop.bits.ctrl.br_type
connect slots_14.io.in_uop.bits.fu_code, issue_slots[14].in_uop.bits.fu_code
connect slots_14.io.in_uop.bits.iq_type, issue_slots[14].in_uop.bits.iq_type
connect slots_14.io.in_uop.bits.debug_pc, issue_slots[14].in_uop.bits.debug_pc
connect slots_14.io.in_uop.bits.is_rvc, issue_slots[14].in_uop.bits.is_rvc
connect slots_14.io.in_uop.bits.debug_inst, issue_slots[14].in_uop.bits.debug_inst
connect slots_14.io.in_uop.bits.inst, issue_slots[14].in_uop.bits.inst
connect slots_14.io.in_uop.bits.uopc, issue_slots[14].in_uop.bits.uopc
connect slots_14.io.in_uop.valid, issue_slots[14].in_uop.valid
connect slots_14.io.spec_ld_wakeup[0].bits, issue_slots[14].spec_ld_wakeup[0].bits
connect slots_14.io.spec_ld_wakeup[0].valid, issue_slots[14].spec_ld_wakeup[0].valid
connect slots_14.io.pred_wakeup_port.bits, issue_slots[14].pred_wakeup_port.bits
connect slots_14.io.pred_wakeup_port.valid, issue_slots[14].pred_wakeup_port.valid
connect slots_14.io.wakeup_ports[0].bits.poisoned, issue_slots[14].wakeup_ports[0].bits.poisoned
connect slots_14.io.wakeup_ports[0].bits.pdst, issue_slots[14].wakeup_ports[0].bits.pdst
connect slots_14.io.wakeup_ports[0].valid, issue_slots[14].wakeup_ports[0].valid
connect slots_14.io.wakeup_ports[1].bits.poisoned, issue_slots[14].wakeup_ports[1].bits.poisoned
connect slots_14.io.wakeup_ports[1].bits.pdst, issue_slots[14].wakeup_ports[1].bits.pdst
connect slots_14.io.wakeup_ports[1].valid, issue_slots[14].wakeup_ports[1].valid
connect slots_14.io.ldspec_miss, issue_slots[14].ldspec_miss
connect slots_14.io.clear, issue_slots[14].clear
connect slots_14.io.kill, issue_slots[14].kill
connect slots_14.io.brupdate.b2.target_offset, issue_slots[14].brupdate.b2.target_offset
connect slots_14.io.brupdate.b2.jalr_target, issue_slots[14].brupdate.b2.jalr_target
connect slots_14.io.brupdate.b2.pc_sel, issue_slots[14].brupdate.b2.pc_sel
connect slots_14.io.brupdate.b2.cfi_type, issue_slots[14].brupdate.b2.cfi_type
connect slots_14.io.brupdate.b2.taken, issue_slots[14].brupdate.b2.taken
connect slots_14.io.brupdate.b2.mispredict, issue_slots[14].brupdate.b2.mispredict
connect slots_14.io.brupdate.b2.valid, issue_slots[14].brupdate.b2.valid
connect slots_14.io.brupdate.b2.uop.debug_tsrc, issue_slots[14].brupdate.b2.uop.debug_tsrc
connect slots_14.io.brupdate.b2.uop.debug_fsrc, issue_slots[14].brupdate.b2.uop.debug_fsrc
connect slots_14.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[14].brupdate.b2.uop.bp_xcpt_if
connect slots_14.io.brupdate.b2.uop.bp_debug_if, issue_slots[14].brupdate.b2.uop.bp_debug_if
connect slots_14.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[14].brupdate.b2.uop.xcpt_ma_if
connect slots_14.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[14].brupdate.b2.uop.xcpt_ae_if
connect slots_14.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[14].brupdate.b2.uop.xcpt_pf_if
connect slots_14.io.brupdate.b2.uop.fp_single, issue_slots[14].brupdate.b2.uop.fp_single
connect slots_14.io.brupdate.b2.uop.fp_val, issue_slots[14].brupdate.b2.uop.fp_val
connect slots_14.io.brupdate.b2.uop.frs3_en, issue_slots[14].brupdate.b2.uop.frs3_en
connect slots_14.io.brupdate.b2.uop.lrs2_rtype, issue_slots[14].brupdate.b2.uop.lrs2_rtype
connect slots_14.io.brupdate.b2.uop.lrs1_rtype, issue_slots[14].brupdate.b2.uop.lrs1_rtype
connect slots_14.io.brupdate.b2.uop.dst_rtype, issue_slots[14].brupdate.b2.uop.dst_rtype
connect slots_14.io.brupdate.b2.uop.ldst_val, issue_slots[14].brupdate.b2.uop.ldst_val
connect slots_14.io.brupdate.b2.uop.lrs3, issue_slots[14].brupdate.b2.uop.lrs3
connect slots_14.io.brupdate.b2.uop.lrs2, issue_slots[14].brupdate.b2.uop.lrs2
connect slots_14.io.brupdate.b2.uop.lrs1, issue_slots[14].brupdate.b2.uop.lrs1
connect slots_14.io.brupdate.b2.uop.ldst, issue_slots[14].brupdate.b2.uop.ldst
connect slots_14.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[14].brupdate.b2.uop.ldst_is_rs1
connect slots_14.io.brupdate.b2.uop.flush_on_commit, issue_slots[14].brupdate.b2.uop.flush_on_commit
connect slots_14.io.brupdate.b2.uop.is_unique, issue_slots[14].brupdate.b2.uop.is_unique
connect slots_14.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[14].brupdate.b2.uop.is_sys_pc2epc
connect slots_14.io.brupdate.b2.uop.uses_stq, issue_slots[14].brupdate.b2.uop.uses_stq
connect slots_14.io.brupdate.b2.uop.uses_ldq, issue_slots[14].brupdate.b2.uop.uses_ldq
connect slots_14.io.brupdate.b2.uop.is_amo, issue_slots[14].brupdate.b2.uop.is_amo
connect slots_14.io.brupdate.b2.uop.is_fencei, issue_slots[14].brupdate.b2.uop.is_fencei
connect slots_14.io.brupdate.b2.uop.is_fence, issue_slots[14].brupdate.b2.uop.is_fence
connect slots_14.io.brupdate.b2.uop.mem_signed, issue_slots[14].brupdate.b2.uop.mem_signed
connect slots_14.io.brupdate.b2.uop.mem_size, issue_slots[14].brupdate.b2.uop.mem_size
connect slots_14.io.brupdate.b2.uop.mem_cmd, issue_slots[14].brupdate.b2.uop.mem_cmd
connect slots_14.io.brupdate.b2.uop.bypassable, issue_slots[14].brupdate.b2.uop.bypassable
connect slots_14.io.brupdate.b2.uop.exc_cause, issue_slots[14].brupdate.b2.uop.exc_cause
connect slots_14.io.brupdate.b2.uop.exception, issue_slots[14].brupdate.b2.uop.exception
connect slots_14.io.brupdate.b2.uop.stale_pdst, issue_slots[14].brupdate.b2.uop.stale_pdst
connect slots_14.io.brupdate.b2.uop.ppred_busy, issue_slots[14].brupdate.b2.uop.ppred_busy
connect slots_14.io.brupdate.b2.uop.prs3_busy, issue_slots[14].brupdate.b2.uop.prs3_busy
connect slots_14.io.brupdate.b2.uop.prs2_busy, issue_slots[14].brupdate.b2.uop.prs2_busy
connect slots_14.io.brupdate.b2.uop.prs1_busy, issue_slots[14].brupdate.b2.uop.prs1_busy
connect slots_14.io.brupdate.b2.uop.ppred, issue_slots[14].brupdate.b2.uop.ppred
connect slots_14.io.brupdate.b2.uop.prs3, issue_slots[14].brupdate.b2.uop.prs3
connect slots_14.io.brupdate.b2.uop.prs2, issue_slots[14].brupdate.b2.uop.prs2
connect slots_14.io.brupdate.b2.uop.prs1, issue_slots[14].brupdate.b2.uop.prs1
connect slots_14.io.brupdate.b2.uop.pdst, issue_slots[14].brupdate.b2.uop.pdst
connect slots_14.io.brupdate.b2.uop.rxq_idx, issue_slots[14].brupdate.b2.uop.rxq_idx
connect slots_14.io.brupdate.b2.uop.stq_idx, issue_slots[14].brupdate.b2.uop.stq_idx
connect slots_14.io.brupdate.b2.uop.ldq_idx, issue_slots[14].brupdate.b2.uop.ldq_idx
connect slots_14.io.brupdate.b2.uop.rob_idx, issue_slots[14].brupdate.b2.uop.rob_idx
connect slots_14.io.brupdate.b2.uop.csr_addr, issue_slots[14].brupdate.b2.uop.csr_addr
connect slots_14.io.brupdate.b2.uop.imm_packed, issue_slots[14].brupdate.b2.uop.imm_packed
connect slots_14.io.brupdate.b2.uop.taken, issue_slots[14].brupdate.b2.uop.taken
connect slots_14.io.brupdate.b2.uop.pc_lob, issue_slots[14].brupdate.b2.uop.pc_lob
connect slots_14.io.brupdate.b2.uop.edge_inst, issue_slots[14].brupdate.b2.uop.edge_inst
connect slots_14.io.brupdate.b2.uop.ftq_idx, issue_slots[14].brupdate.b2.uop.ftq_idx
connect slots_14.io.brupdate.b2.uop.br_tag, issue_slots[14].brupdate.b2.uop.br_tag
connect slots_14.io.brupdate.b2.uop.br_mask, issue_slots[14].brupdate.b2.uop.br_mask
connect slots_14.io.brupdate.b2.uop.is_sfb, issue_slots[14].brupdate.b2.uop.is_sfb
connect slots_14.io.brupdate.b2.uop.is_jal, issue_slots[14].brupdate.b2.uop.is_jal
connect slots_14.io.brupdate.b2.uop.is_jalr, issue_slots[14].brupdate.b2.uop.is_jalr
connect slots_14.io.brupdate.b2.uop.is_br, issue_slots[14].brupdate.b2.uop.is_br
connect slots_14.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[14].brupdate.b2.uop.iw_p2_poisoned
connect slots_14.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[14].brupdate.b2.uop.iw_p1_poisoned
connect slots_14.io.brupdate.b2.uop.iw_state, issue_slots[14].brupdate.b2.uop.iw_state
connect slots_14.io.brupdate.b2.uop.ctrl.is_std, issue_slots[14].brupdate.b2.uop.ctrl.is_std
connect slots_14.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[14].brupdate.b2.uop.ctrl.is_sta
connect slots_14.io.brupdate.b2.uop.ctrl.is_load, issue_slots[14].brupdate.b2.uop.ctrl.is_load
connect slots_14.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[14].brupdate.b2.uop.ctrl.csr_cmd
connect slots_14.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[14].brupdate.b2.uop.ctrl.fcn_dw
connect slots_14.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[14].brupdate.b2.uop.ctrl.op_fcn
connect slots_14.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[14].brupdate.b2.uop.ctrl.imm_sel
connect slots_14.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[14].brupdate.b2.uop.ctrl.op2_sel
connect slots_14.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[14].brupdate.b2.uop.ctrl.op1_sel
connect slots_14.io.brupdate.b2.uop.ctrl.br_type, issue_slots[14].brupdate.b2.uop.ctrl.br_type
connect slots_14.io.brupdate.b2.uop.fu_code, issue_slots[14].brupdate.b2.uop.fu_code
connect slots_14.io.brupdate.b2.uop.iq_type, issue_slots[14].brupdate.b2.uop.iq_type
connect slots_14.io.brupdate.b2.uop.debug_pc, issue_slots[14].brupdate.b2.uop.debug_pc
connect slots_14.io.brupdate.b2.uop.is_rvc, issue_slots[14].brupdate.b2.uop.is_rvc
connect slots_14.io.brupdate.b2.uop.debug_inst, issue_slots[14].brupdate.b2.uop.debug_inst
connect slots_14.io.brupdate.b2.uop.inst, issue_slots[14].brupdate.b2.uop.inst
connect slots_14.io.brupdate.b2.uop.uopc, issue_slots[14].brupdate.b2.uop.uopc
connect slots_14.io.brupdate.b1.mispredict_mask, issue_slots[14].brupdate.b1.mispredict_mask
connect slots_14.io.brupdate.b1.resolve_mask, issue_slots[14].brupdate.b1.resolve_mask
connect slots_14.io.grant, issue_slots[14].grant
connect issue_slots[14].request_hp, slots_14.io.request_hp
connect issue_slots[14].request, slots_14.io.request
connect issue_slots[14].will_be_valid, slots_14.io.will_be_valid
connect issue_slots[14].valid, slots_14.io.valid
connect issue_slots[15].debug.state, slots_15.io.debug.state
connect issue_slots[15].debug.ppred, slots_15.io.debug.ppred
connect issue_slots[15].debug.p3, slots_15.io.debug.p3
connect issue_slots[15].debug.p2, slots_15.io.debug.p2
connect issue_slots[15].debug.p1, slots_15.io.debug.p1
connect issue_slots[15].uop.debug_tsrc, slots_15.io.uop.debug_tsrc
connect issue_slots[15].uop.debug_fsrc, slots_15.io.uop.debug_fsrc
connect issue_slots[15].uop.bp_xcpt_if, slots_15.io.uop.bp_xcpt_if
connect issue_slots[15].uop.bp_debug_if, slots_15.io.uop.bp_debug_if
connect issue_slots[15].uop.xcpt_ma_if, slots_15.io.uop.xcpt_ma_if
connect issue_slots[15].uop.xcpt_ae_if, slots_15.io.uop.xcpt_ae_if
connect issue_slots[15].uop.xcpt_pf_if, slots_15.io.uop.xcpt_pf_if
connect issue_slots[15].uop.fp_single, slots_15.io.uop.fp_single
connect issue_slots[15].uop.fp_val, slots_15.io.uop.fp_val
connect issue_slots[15].uop.frs3_en, slots_15.io.uop.frs3_en
connect issue_slots[15].uop.lrs2_rtype, slots_15.io.uop.lrs2_rtype
connect issue_slots[15].uop.lrs1_rtype, slots_15.io.uop.lrs1_rtype
connect issue_slots[15].uop.dst_rtype, slots_15.io.uop.dst_rtype
connect issue_slots[15].uop.ldst_val, slots_15.io.uop.ldst_val
connect issue_slots[15].uop.lrs3, slots_15.io.uop.lrs3
connect issue_slots[15].uop.lrs2, slots_15.io.uop.lrs2
connect issue_slots[15].uop.lrs1, slots_15.io.uop.lrs1
connect issue_slots[15].uop.ldst, slots_15.io.uop.ldst
connect issue_slots[15].uop.ldst_is_rs1, slots_15.io.uop.ldst_is_rs1
connect issue_slots[15].uop.flush_on_commit, slots_15.io.uop.flush_on_commit
connect issue_slots[15].uop.is_unique, slots_15.io.uop.is_unique
connect issue_slots[15].uop.is_sys_pc2epc, slots_15.io.uop.is_sys_pc2epc
connect issue_slots[15].uop.uses_stq, slots_15.io.uop.uses_stq
connect issue_slots[15].uop.uses_ldq, slots_15.io.uop.uses_ldq
connect issue_slots[15].uop.is_amo, slots_15.io.uop.is_amo
connect issue_slots[15].uop.is_fencei, slots_15.io.uop.is_fencei
connect issue_slots[15].uop.is_fence, slots_15.io.uop.is_fence
connect issue_slots[15].uop.mem_signed, slots_15.io.uop.mem_signed
connect issue_slots[15].uop.mem_size, slots_15.io.uop.mem_size
connect issue_slots[15].uop.mem_cmd, slots_15.io.uop.mem_cmd
connect issue_slots[15].uop.bypassable, slots_15.io.uop.bypassable
connect issue_slots[15].uop.exc_cause, slots_15.io.uop.exc_cause
connect issue_slots[15].uop.exception, slots_15.io.uop.exception
connect issue_slots[15].uop.stale_pdst, slots_15.io.uop.stale_pdst
connect issue_slots[15].uop.ppred_busy, slots_15.io.uop.ppred_busy
connect issue_slots[15].uop.prs3_busy, slots_15.io.uop.prs3_busy
connect issue_slots[15].uop.prs2_busy, slots_15.io.uop.prs2_busy
connect issue_slots[15].uop.prs1_busy, slots_15.io.uop.prs1_busy
connect issue_slots[15].uop.ppred, slots_15.io.uop.ppred
connect issue_slots[15].uop.prs3, slots_15.io.uop.prs3
connect issue_slots[15].uop.prs2, slots_15.io.uop.prs2
connect issue_slots[15].uop.prs1, slots_15.io.uop.prs1
connect issue_slots[15].uop.pdst, slots_15.io.uop.pdst
connect issue_slots[15].uop.rxq_idx, slots_15.io.uop.rxq_idx
connect issue_slots[15].uop.stq_idx, slots_15.io.uop.stq_idx
connect issue_slots[15].uop.ldq_idx, slots_15.io.uop.ldq_idx
connect issue_slots[15].uop.rob_idx, slots_15.io.uop.rob_idx
connect issue_slots[15].uop.csr_addr, slots_15.io.uop.csr_addr
connect issue_slots[15].uop.imm_packed, slots_15.io.uop.imm_packed
connect issue_slots[15].uop.taken, slots_15.io.uop.taken
connect issue_slots[15].uop.pc_lob, slots_15.io.uop.pc_lob
connect issue_slots[15].uop.edge_inst, slots_15.io.uop.edge_inst
connect issue_slots[15].uop.ftq_idx, slots_15.io.uop.ftq_idx
connect issue_slots[15].uop.br_tag, slots_15.io.uop.br_tag
connect issue_slots[15].uop.br_mask, slots_15.io.uop.br_mask
connect issue_slots[15].uop.is_sfb, slots_15.io.uop.is_sfb
connect issue_slots[15].uop.is_jal, slots_15.io.uop.is_jal
connect issue_slots[15].uop.is_jalr, slots_15.io.uop.is_jalr
connect issue_slots[15].uop.is_br, slots_15.io.uop.is_br
connect issue_slots[15].uop.iw_p2_poisoned, slots_15.io.uop.iw_p2_poisoned
connect issue_slots[15].uop.iw_p1_poisoned, slots_15.io.uop.iw_p1_poisoned
connect issue_slots[15].uop.iw_state, slots_15.io.uop.iw_state
connect issue_slots[15].uop.ctrl.is_std, slots_15.io.uop.ctrl.is_std
connect issue_slots[15].uop.ctrl.is_sta, slots_15.io.uop.ctrl.is_sta
connect issue_slots[15].uop.ctrl.is_load, slots_15.io.uop.ctrl.is_load
connect issue_slots[15].uop.ctrl.csr_cmd, slots_15.io.uop.ctrl.csr_cmd
connect issue_slots[15].uop.ctrl.fcn_dw, slots_15.io.uop.ctrl.fcn_dw
connect issue_slots[15].uop.ctrl.op_fcn, slots_15.io.uop.ctrl.op_fcn
connect issue_slots[15].uop.ctrl.imm_sel, slots_15.io.uop.ctrl.imm_sel
connect issue_slots[15].uop.ctrl.op2_sel, slots_15.io.uop.ctrl.op2_sel
connect issue_slots[15].uop.ctrl.op1_sel, slots_15.io.uop.ctrl.op1_sel
connect issue_slots[15].uop.ctrl.br_type, slots_15.io.uop.ctrl.br_type
connect issue_slots[15].uop.fu_code, slots_15.io.uop.fu_code
connect issue_slots[15].uop.iq_type, slots_15.io.uop.iq_type
connect issue_slots[15].uop.debug_pc, slots_15.io.uop.debug_pc
connect issue_slots[15].uop.is_rvc, slots_15.io.uop.is_rvc
connect issue_slots[15].uop.debug_inst, slots_15.io.uop.debug_inst
connect issue_slots[15].uop.inst, slots_15.io.uop.inst
connect issue_slots[15].uop.uopc, slots_15.io.uop.uopc
connect issue_slots[15].out_uop.debug_tsrc, slots_15.io.out_uop.debug_tsrc
connect issue_slots[15].out_uop.debug_fsrc, slots_15.io.out_uop.debug_fsrc
connect issue_slots[15].out_uop.bp_xcpt_if, slots_15.io.out_uop.bp_xcpt_if
connect issue_slots[15].out_uop.bp_debug_if, slots_15.io.out_uop.bp_debug_if
connect issue_slots[15].out_uop.xcpt_ma_if, slots_15.io.out_uop.xcpt_ma_if
connect issue_slots[15].out_uop.xcpt_ae_if, slots_15.io.out_uop.xcpt_ae_if
connect issue_slots[15].out_uop.xcpt_pf_if, slots_15.io.out_uop.xcpt_pf_if
connect issue_slots[15].out_uop.fp_single, slots_15.io.out_uop.fp_single
connect issue_slots[15].out_uop.fp_val, slots_15.io.out_uop.fp_val
connect issue_slots[15].out_uop.frs3_en, slots_15.io.out_uop.frs3_en
connect issue_slots[15].out_uop.lrs2_rtype, slots_15.io.out_uop.lrs2_rtype
connect issue_slots[15].out_uop.lrs1_rtype, slots_15.io.out_uop.lrs1_rtype
connect issue_slots[15].out_uop.dst_rtype, slots_15.io.out_uop.dst_rtype
connect issue_slots[15].out_uop.ldst_val, slots_15.io.out_uop.ldst_val
connect issue_slots[15].out_uop.lrs3, slots_15.io.out_uop.lrs3
connect issue_slots[15].out_uop.lrs2, slots_15.io.out_uop.lrs2
connect issue_slots[15].out_uop.lrs1, slots_15.io.out_uop.lrs1
connect issue_slots[15].out_uop.ldst, slots_15.io.out_uop.ldst
connect issue_slots[15].out_uop.ldst_is_rs1, slots_15.io.out_uop.ldst_is_rs1
connect issue_slots[15].out_uop.flush_on_commit, slots_15.io.out_uop.flush_on_commit
connect issue_slots[15].out_uop.is_unique, slots_15.io.out_uop.is_unique
connect issue_slots[15].out_uop.is_sys_pc2epc, slots_15.io.out_uop.is_sys_pc2epc
connect issue_slots[15].out_uop.uses_stq, slots_15.io.out_uop.uses_stq
connect issue_slots[15].out_uop.uses_ldq, slots_15.io.out_uop.uses_ldq
connect issue_slots[15].out_uop.is_amo, slots_15.io.out_uop.is_amo
connect issue_slots[15].out_uop.is_fencei, slots_15.io.out_uop.is_fencei
connect issue_slots[15].out_uop.is_fence, slots_15.io.out_uop.is_fence
connect issue_slots[15].out_uop.mem_signed, slots_15.io.out_uop.mem_signed
connect issue_slots[15].out_uop.mem_size, slots_15.io.out_uop.mem_size
connect issue_slots[15].out_uop.mem_cmd, slots_15.io.out_uop.mem_cmd
connect issue_slots[15].out_uop.bypassable, slots_15.io.out_uop.bypassable
connect issue_slots[15].out_uop.exc_cause, slots_15.io.out_uop.exc_cause
connect issue_slots[15].out_uop.exception, slots_15.io.out_uop.exception
connect issue_slots[15].out_uop.stale_pdst, slots_15.io.out_uop.stale_pdst
connect issue_slots[15].out_uop.ppred_busy, slots_15.io.out_uop.ppred_busy
connect issue_slots[15].out_uop.prs3_busy, slots_15.io.out_uop.prs3_busy
connect issue_slots[15].out_uop.prs2_busy, slots_15.io.out_uop.prs2_busy
connect issue_slots[15].out_uop.prs1_busy, slots_15.io.out_uop.prs1_busy
connect issue_slots[15].out_uop.ppred, slots_15.io.out_uop.ppred
connect issue_slots[15].out_uop.prs3, slots_15.io.out_uop.prs3
connect issue_slots[15].out_uop.prs2, slots_15.io.out_uop.prs2
connect issue_slots[15].out_uop.prs1, slots_15.io.out_uop.prs1
connect issue_slots[15].out_uop.pdst, slots_15.io.out_uop.pdst
connect issue_slots[15].out_uop.rxq_idx, slots_15.io.out_uop.rxq_idx
connect issue_slots[15].out_uop.stq_idx, slots_15.io.out_uop.stq_idx
connect issue_slots[15].out_uop.ldq_idx, slots_15.io.out_uop.ldq_idx
connect issue_slots[15].out_uop.rob_idx, slots_15.io.out_uop.rob_idx
connect issue_slots[15].out_uop.csr_addr, slots_15.io.out_uop.csr_addr
connect issue_slots[15].out_uop.imm_packed, slots_15.io.out_uop.imm_packed
connect issue_slots[15].out_uop.taken, slots_15.io.out_uop.taken
connect issue_slots[15].out_uop.pc_lob, slots_15.io.out_uop.pc_lob
connect issue_slots[15].out_uop.edge_inst, slots_15.io.out_uop.edge_inst
connect issue_slots[15].out_uop.ftq_idx, slots_15.io.out_uop.ftq_idx
connect issue_slots[15].out_uop.br_tag, slots_15.io.out_uop.br_tag
connect issue_slots[15].out_uop.br_mask, slots_15.io.out_uop.br_mask
connect issue_slots[15].out_uop.is_sfb, slots_15.io.out_uop.is_sfb
connect issue_slots[15].out_uop.is_jal, slots_15.io.out_uop.is_jal
connect issue_slots[15].out_uop.is_jalr, slots_15.io.out_uop.is_jalr
connect issue_slots[15].out_uop.is_br, slots_15.io.out_uop.is_br
connect issue_slots[15].out_uop.iw_p2_poisoned, slots_15.io.out_uop.iw_p2_poisoned
connect issue_slots[15].out_uop.iw_p1_poisoned, slots_15.io.out_uop.iw_p1_poisoned
connect issue_slots[15].out_uop.iw_state, slots_15.io.out_uop.iw_state
connect issue_slots[15].out_uop.ctrl.is_std, slots_15.io.out_uop.ctrl.is_std
connect issue_slots[15].out_uop.ctrl.is_sta, slots_15.io.out_uop.ctrl.is_sta
connect issue_slots[15].out_uop.ctrl.is_load, slots_15.io.out_uop.ctrl.is_load
connect issue_slots[15].out_uop.ctrl.csr_cmd, slots_15.io.out_uop.ctrl.csr_cmd
connect issue_slots[15].out_uop.ctrl.fcn_dw, slots_15.io.out_uop.ctrl.fcn_dw
connect issue_slots[15].out_uop.ctrl.op_fcn, slots_15.io.out_uop.ctrl.op_fcn
connect issue_slots[15].out_uop.ctrl.imm_sel, slots_15.io.out_uop.ctrl.imm_sel
connect issue_slots[15].out_uop.ctrl.op2_sel, slots_15.io.out_uop.ctrl.op2_sel
connect issue_slots[15].out_uop.ctrl.op1_sel, slots_15.io.out_uop.ctrl.op1_sel
connect issue_slots[15].out_uop.ctrl.br_type, slots_15.io.out_uop.ctrl.br_type
connect issue_slots[15].out_uop.fu_code, slots_15.io.out_uop.fu_code
connect issue_slots[15].out_uop.iq_type, slots_15.io.out_uop.iq_type
connect issue_slots[15].out_uop.debug_pc, slots_15.io.out_uop.debug_pc
connect issue_slots[15].out_uop.is_rvc, slots_15.io.out_uop.is_rvc
connect issue_slots[15].out_uop.debug_inst, slots_15.io.out_uop.debug_inst
connect issue_slots[15].out_uop.inst, slots_15.io.out_uop.inst
connect issue_slots[15].out_uop.uopc, slots_15.io.out_uop.uopc
connect slots_15.io.in_uop.bits.debug_tsrc, issue_slots[15].in_uop.bits.debug_tsrc
connect slots_15.io.in_uop.bits.debug_fsrc, issue_slots[15].in_uop.bits.debug_fsrc
connect slots_15.io.in_uop.bits.bp_xcpt_if, issue_slots[15].in_uop.bits.bp_xcpt_if
connect slots_15.io.in_uop.bits.bp_debug_if, issue_slots[15].in_uop.bits.bp_debug_if
connect slots_15.io.in_uop.bits.xcpt_ma_if, issue_slots[15].in_uop.bits.xcpt_ma_if
connect slots_15.io.in_uop.bits.xcpt_ae_if, issue_slots[15].in_uop.bits.xcpt_ae_if
connect slots_15.io.in_uop.bits.xcpt_pf_if, issue_slots[15].in_uop.bits.xcpt_pf_if
connect slots_15.io.in_uop.bits.fp_single, issue_slots[15].in_uop.bits.fp_single
connect slots_15.io.in_uop.bits.fp_val, issue_slots[15].in_uop.bits.fp_val
connect slots_15.io.in_uop.bits.frs3_en, issue_slots[15].in_uop.bits.frs3_en
connect slots_15.io.in_uop.bits.lrs2_rtype, issue_slots[15].in_uop.bits.lrs2_rtype
connect slots_15.io.in_uop.bits.lrs1_rtype, issue_slots[15].in_uop.bits.lrs1_rtype
connect slots_15.io.in_uop.bits.dst_rtype, issue_slots[15].in_uop.bits.dst_rtype
connect slots_15.io.in_uop.bits.ldst_val, issue_slots[15].in_uop.bits.ldst_val
connect slots_15.io.in_uop.bits.lrs3, issue_slots[15].in_uop.bits.lrs3
connect slots_15.io.in_uop.bits.lrs2, issue_slots[15].in_uop.bits.lrs2
connect slots_15.io.in_uop.bits.lrs1, issue_slots[15].in_uop.bits.lrs1
connect slots_15.io.in_uop.bits.ldst, issue_slots[15].in_uop.bits.ldst
connect slots_15.io.in_uop.bits.ldst_is_rs1, issue_slots[15].in_uop.bits.ldst_is_rs1
connect slots_15.io.in_uop.bits.flush_on_commit, issue_slots[15].in_uop.bits.flush_on_commit
connect slots_15.io.in_uop.bits.is_unique, issue_slots[15].in_uop.bits.is_unique
connect slots_15.io.in_uop.bits.is_sys_pc2epc, issue_slots[15].in_uop.bits.is_sys_pc2epc
connect slots_15.io.in_uop.bits.uses_stq, issue_slots[15].in_uop.bits.uses_stq
connect slots_15.io.in_uop.bits.uses_ldq, issue_slots[15].in_uop.bits.uses_ldq
connect slots_15.io.in_uop.bits.is_amo, issue_slots[15].in_uop.bits.is_amo
connect slots_15.io.in_uop.bits.is_fencei, issue_slots[15].in_uop.bits.is_fencei
connect slots_15.io.in_uop.bits.is_fence, issue_slots[15].in_uop.bits.is_fence
connect slots_15.io.in_uop.bits.mem_signed, issue_slots[15].in_uop.bits.mem_signed
connect slots_15.io.in_uop.bits.mem_size, issue_slots[15].in_uop.bits.mem_size
connect slots_15.io.in_uop.bits.mem_cmd, issue_slots[15].in_uop.bits.mem_cmd
connect slots_15.io.in_uop.bits.bypassable, issue_slots[15].in_uop.bits.bypassable
connect slots_15.io.in_uop.bits.exc_cause, issue_slots[15].in_uop.bits.exc_cause
connect slots_15.io.in_uop.bits.exception, issue_slots[15].in_uop.bits.exception
connect slots_15.io.in_uop.bits.stale_pdst, issue_slots[15].in_uop.bits.stale_pdst
connect slots_15.io.in_uop.bits.ppred_busy, issue_slots[15].in_uop.bits.ppred_busy
connect slots_15.io.in_uop.bits.prs3_busy, issue_slots[15].in_uop.bits.prs3_busy
connect slots_15.io.in_uop.bits.prs2_busy, issue_slots[15].in_uop.bits.prs2_busy
connect slots_15.io.in_uop.bits.prs1_busy, issue_slots[15].in_uop.bits.prs1_busy
connect slots_15.io.in_uop.bits.ppred, issue_slots[15].in_uop.bits.ppred
connect slots_15.io.in_uop.bits.prs3, issue_slots[15].in_uop.bits.prs3
connect slots_15.io.in_uop.bits.prs2, issue_slots[15].in_uop.bits.prs2
connect slots_15.io.in_uop.bits.prs1, issue_slots[15].in_uop.bits.prs1
connect slots_15.io.in_uop.bits.pdst, issue_slots[15].in_uop.bits.pdst
connect slots_15.io.in_uop.bits.rxq_idx, issue_slots[15].in_uop.bits.rxq_idx
connect slots_15.io.in_uop.bits.stq_idx, issue_slots[15].in_uop.bits.stq_idx
connect slots_15.io.in_uop.bits.ldq_idx, issue_slots[15].in_uop.bits.ldq_idx
connect slots_15.io.in_uop.bits.rob_idx, issue_slots[15].in_uop.bits.rob_idx
connect slots_15.io.in_uop.bits.csr_addr, issue_slots[15].in_uop.bits.csr_addr
connect slots_15.io.in_uop.bits.imm_packed, issue_slots[15].in_uop.bits.imm_packed
connect slots_15.io.in_uop.bits.taken, issue_slots[15].in_uop.bits.taken
connect slots_15.io.in_uop.bits.pc_lob, issue_slots[15].in_uop.bits.pc_lob
connect slots_15.io.in_uop.bits.edge_inst, issue_slots[15].in_uop.bits.edge_inst
connect slots_15.io.in_uop.bits.ftq_idx, issue_slots[15].in_uop.bits.ftq_idx
connect slots_15.io.in_uop.bits.br_tag, issue_slots[15].in_uop.bits.br_tag
connect slots_15.io.in_uop.bits.br_mask, issue_slots[15].in_uop.bits.br_mask
connect slots_15.io.in_uop.bits.is_sfb, issue_slots[15].in_uop.bits.is_sfb
connect slots_15.io.in_uop.bits.is_jal, issue_slots[15].in_uop.bits.is_jal
connect slots_15.io.in_uop.bits.is_jalr, issue_slots[15].in_uop.bits.is_jalr
connect slots_15.io.in_uop.bits.is_br, issue_slots[15].in_uop.bits.is_br
connect slots_15.io.in_uop.bits.iw_p2_poisoned, issue_slots[15].in_uop.bits.iw_p2_poisoned
connect slots_15.io.in_uop.bits.iw_p1_poisoned, issue_slots[15].in_uop.bits.iw_p1_poisoned
connect slots_15.io.in_uop.bits.iw_state, issue_slots[15].in_uop.bits.iw_state
connect slots_15.io.in_uop.bits.ctrl.is_std, issue_slots[15].in_uop.bits.ctrl.is_std
connect slots_15.io.in_uop.bits.ctrl.is_sta, issue_slots[15].in_uop.bits.ctrl.is_sta
connect slots_15.io.in_uop.bits.ctrl.is_load, issue_slots[15].in_uop.bits.ctrl.is_load
connect slots_15.io.in_uop.bits.ctrl.csr_cmd, issue_slots[15].in_uop.bits.ctrl.csr_cmd
connect slots_15.io.in_uop.bits.ctrl.fcn_dw, issue_slots[15].in_uop.bits.ctrl.fcn_dw
connect slots_15.io.in_uop.bits.ctrl.op_fcn, issue_slots[15].in_uop.bits.ctrl.op_fcn
connect slots_15.io.in_uop.bits.ctrl.imm_sel, issue_slots[15].in_uop.bits.ctrl.imm_sel
connect slots_15.io.in_uop.bits.ctrl.op2_sel, issue_slots[15].in_uop.bits.ctrl.op2_sel
connect slots_15.io.in_uop.bits.ctrl.op1_sel, issue_slots[15].in_uop.bits.ctrl.op1_sel
connect slots_15.io.in_uop.bits.ctrl.br_type, issue_slots[15].in_uop.bits.ctrl.br_type
connect slots_15.io.in_uop.bits.fu_code, issue_slots[15].in_uop.bits.fu_code
connect slots_15.io.in_uop.bits.iq_type, issue_slots[15].in_uop.bits.iq_type
connect slots_15.io.in_uop.bits.debug_pc, issue_slots[15].in_uop.bits.debug_pc
connect slots_15.io.in_uop.bits.is_rvc, issue_slots[15].in_uop.bits.is_rvc
connect slots_15.io.in_uop.bits.debug_inst, issue_slots[15].in_uop.bits.debug_inst
connect slots_15.io.in_uop.bits.inst, issue_slots[15].in_uop.bits.inst
connect slots_15.io.in_uop.bits.uopc, issue_slots[15].in_uop.bits.uopc
connect slots_15.io.in_uop.valid, issue_slots[15].in_uop.valid
connect slots_15.io.spec_ld_wakeup[0].bits, issue_slots[15].spec_ld_wakeup[0].bits
connect slots_15.io.spec_ld_wakeup[0].valid, issue_slots[15].spec_ld_wakeup[0].valid
connect slots_15.io.pred_wakeup_port.bits, issue_slots[15].pred_wakeup_port.bits
connect slots_15.io.pred_wakeup_port.valid, issue_slots[15].pred_wakeup_port.valid
connect slots_15.io.wakeup_ports[0].bits.poisoned, issue_slots[15].wakeup_ports[0].bits.poisoned
connect slots_15.io.wakeup_ports[0].bits.pdst, issue_slots[15].wakeup_ports[0].bits.pdst
connect slots_15.io.wakeup_ports[0].valid, issue_slots[15].wakeup_ports[0].valid
connect slots_15.io.wakeup_ports[1].bits.poisoned, issue_slots[15].wakeup_ports[1].bits.poisoned
connect slots_15.io.wakeup_ports[1].bits.pdst, issue_slots[15].wakeup_ports[1].bits.pdst
connect slots_15.io.wakeup_ports[1].valid, issue_slots[15].wakeup_ports[1].valid
connect slots_15.io.ldspec_miss, issue_slots[15].ldspec_miss
connect slots_15.io.clear, issue_slots[15].clear
connect slots_15.io.kill, issue_slots[15].kill
connect slots_15.io.brupdate.b2.target_offset, issue_slots[15].brupdate.b2.target_offset
connect slots_15.io.brupdate.b2.jalr_target, issue_slots[15].brupdate.b2.jalr_target
connect slots_15.io.brupdate.b2.pc_sel, issue_slots[15].brupdate.b2.pc_sel
connect slots_15.io.brupdate.b2.cfi_type, issue_slots[15].brupdate.b2.cfi_type
connect slots_15.io.brupdate.b2.taken, issue_slots[15].brupdate.b2.taken
connect slots_15.io.brupdate.b2.mispredict, issue_slots[15].brupdate.b2.mispredict
connect slots_15.io.brupdate.b2.valid, issue_slots[15].brupdate.b2.valid
connect slots_15.io.brupdate.b2.uop.debug_tsrc, issue_slots[15].brupdate.b2.uop.debug_tsrc
connect slots_15.io.brupdate.b2.uop.debug_fsrc, issue_slots[15].brupdate.b2.uop.debug_fsrc
connect slots_15.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[15].brupdate.b2.uop.bp_xcpt_if
connect slots_15.io.brupdate.b2.uop.bp_debug_if, issue_slots[15].brupdate.b2.uop.bp_debug_if
connect slots_15.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[15].brupdate.b2.uop.xcpt_ma_if
connect slots_15.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[15].brupdate.b2.uop.xcpt_ae_if
connect slots_15.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[15].brupdate.b2.uop.xcpt_pf_if
connect slots_15.io.brupdate.b2.uop.fp_single, issue_slots[15].brupdate.b2.uop.fp_single
connect slots_15.io.brupdate.b2.uop.fp_val, issue_slots[15].brupdate.b2.uop.fp_val
connect slots_15.io.brupdate.b2.uop.frs3_en, issue_slots[15].brupdate.b2.uop.frs3_en
connect slots_15.io.brupdate.b2.uop.lrs2_rtype, issue_slots[15].brupdate.b2.uop.lrs2_rtype
connect slots_15.io.brupdate.b2.uop.lrs1_rtype, issue_slots[15].brupdate.b2.uop.lrs1_rtype
connect slots_15.io.brupdate.b2.uop.dst_rtype, issue_slots[15].brupdate.b2.uop.dst_rtype
connect slots_15.io.brupdate.b2.uop.ldst_val, issue_slots[15].brupdate.b2.uop.ldst_val
connect slots_15.io.brupdate.b2.uop.lrs3, issue_slots[15].brupdate.b2.uop.lrs3
connect slots_15.io.brupdate.b2.uop.lrs2, issue_slots[15].brupdate.b2.uop.lrs2
connect slots_15.io.brupdate.b2.uop.lrs1, issue_slots[15].brupdate.b2.uop.lrs1
connect slots_15.io.brupdate.b2.uop.ldst, issue_slots[15].brupdate.b2.uop.ldst
connect slots_15.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[15].brupdate.b2.uop.ldst_is_rs1
connect slots_15.io.brupdate.b2.uop.flush_on_commit, issue_slots[15].brupdate.b2.uop.flush_on_commit
connect slots_15.io.brupdate.b2.uop.is_unique, issue_slots[15].brupdate.b2.uop.is_unique
connect slots_15.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[15].brupdate.b2.uop.is_sys_pc2epc
connect slots_15.io.brupdate.b2.uop.uses_stq, issue_slots[15].brupdate.b2.uop.uses_stq
connect slots_15.io.brupdate.b2.uop.uses_ldq, issue_slots[15].brupdate.b2.uop.uses_ldq
connect slots_15.io.brupdate.b2.uop.is_amo, issue_slots[15].brupdate.b2.uop.is_amo
connect slots_15.io.brupdate.b2.uop.is_fencei, issue_slots[15].brupdate.b2.uop.is_fencei
connect slots_15.io.brupdate.b2.uop.is_fence, issue_slots[15].brupdate.b2.uop.is_fence
connect slots_15.io.brupdate.b2.uop.mem_signed, issue_slots[15].brupdate.b2.uop.mem_signed
connect slots_15.io.brupdate.b2.uop.mem_size, issue_slots[15].brupdate.b2.uop.mem_size
connect slots_15.io.brupdate.b2.uop.mem_cmd, issue_slots[15].brupdate.b2.uop.mem_cmd
connect slots_15.io.brupdate.b2.uop.bypassable, issue_slots[15].brupdate.b2.uop.bypassable
connect slots_15.io.brupdate.b2.uop.exc_cause, issue_slots[15].brupdate.b2.uop.exc_cause
connect slots_15.io.brupdate.b2.uop.exception, issue_slots[15].brupdate.b2.uop.exception
connect slots_15.io.brupdate.b2.uop.stale_pdst, issue_slots[15].brupdate.b2.uop.stale_pdst
connect slots_15.io.brupdate.b2.uop.ppred_busy, issue_slots[15].brupdate.b2.uop.ppred_busy
connect slots_15.io.brupdate.b2.uop.prs3_busy, issue_slots[15].brupdate.b2.uop.prs3_busy
connect slots_15.io.brupdate.b2.uop.prs2_busy, issue_slots[15].brupdate.b2.uop.prs2_busy
connect slots_15.io.brupdate.b2.uop.prs1_busy, issue_slots[15].brupdate.b2.uop.prs1_busy
connect slots_15.io.brupdate.b2.uop.ppred, issue_slots[15].brupdate.b2.uop.ppred
connect slots_15.io.brupdate.b2.uop.prs3, issue_slots[15].brupdate.b2.uop.prs3
connect slots_15.io.brupdate.b2.uop.prs2, issue_slots[15].brupdate.b2.uop.prs2
connect slots_15.io.brupdate.b2.uop.prs1, issue_slots[15].brupdate.b2.uop.prs1
connect slots_15.io.brupdate.b2.uop.pdst, issue_slots[15].brupdate.b2.uop.pdst
connect slots_15.io.brupdate.b2.uop.rxq_idx, issue_slots[15].brupdate.b2.uop.rxq_idx
connect slots_15.io.brupdate.b2.uop.stq_idx, issue_slots[15].brupdate.b2.uop.stq_idx
connect slots_15.io.brupdate.b2.uop.ldq_idx, issue_slots[15].brupdate.b2.uop.ldq_idx
connect slots_15.io.brupdate.b2.uop.rob_idx, issue_slots[15].brupdate.b2.uop.rob_idx
connect slots_15.io.brupdate.b2.uop.csr_addr, issue_slots[15].brupdate.b2.uop.csr_addr
connect slots_15.io.brupdate.b2.uop.imm_packed, issue_slots[15].brupdate.b2.uop.imm_packed
connect slots_15.io.brupdate.b2.uop.taken, issue_slots[15].brupdate.b2.uop.taken
connect slots_15.io.brupdate.b2.uop.pc_lob, issue_slots[15].brupdate.b2.uop.pc_lob
connect slots_15.io.brupdate.b2.uop.edge_inst, issue_slots[15].brupdate.b2.uop.edge_inst
connect slots_15.io.brupdate.b2.uop.ftq_idx, issue_slots[15].brupdate.b2.uop.ftq_idx
connect slots_15.io.brupdate.b2.uop.br_tag, issue_slots[15].brupdate.b2.uop.br_tag
connect slots_15.io.brupdate.b2.uop.br_mask, issue_slots[15].brupdate.b2.uop.br_mask
connect slots_15.io.brupdate.b2.uop.is_sfb, issue_slots[15].brupdate.b2.uop.is_sfb
connect slots_15.io.brupdate.b2.uop.is_jal, issue_slots[15].brupdate.b2.uop.is_jal
connect slots_15.io.brupdate.b2.uop.is_jalr, issue_slots[15].brupdate.b2.uop.is_jalr
connect slots_15.io.brupdate.b2.uop.is_br, issue_slots[15].brupdate.b2.uop.is_br
connect slots_15.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[15].brupdate.b2.uop.iw_p2_poisoned
connect slots_15.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[15].brupdate.b2.uop.iw_p1_poisoned
connect slots_15.io.brupdate.b2.uop.iw_state, issue_slots[15].brupdate.b2.uop.iw_state
connect slots_15.io.brupdate.b2.uop.ctrl.is_std, issue_slots[15].brupdate.b2.uop.ctrl.is_std
connect slots_15.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[15].brupdate.b2.uop.ctrl.is_sta
connect slots_15.io.brupdate.b2.uop.ctrl.is_load, issue_slots[15].brupdate.b2.uop.ctrl.is_load
connect slots_15.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[15].brupdate.b2.uop.ctrl.csr_cmd
connect slots_15.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[15].brupdate.b2.uop.ctrl.fcn_dw
connect slots_15.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[15].brupdate.b2.uop.ctrl.op_fcn
connect slots_15.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[15].brupdate.b2.uop.ctrl.imm_sel
connect slots_15.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[15].brupdate.b2.uop.ctrl.op2_sel
connect slots_15.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[15].brupdate.b2.uop.ctrl.op1_sel
connect slots_15.io.brupdate.b2.uop.ctrl.br_type, issue_slots[15].brupdate.b2.uop.ctrl.br_type
connect slots_15.io.brupdate.b2.uop.fu_code, issue_slots[15].brupdate.b2.uop.fu_code
connect slots_15.io.brupdate.b2.uop.iq_type, issue_slots[15].brupdate.b2.uop.iq_type
connect slots_15.io.brupdate.b2.uop.debug_pc, issue_slots[15].brupdate.b2.uop.debug_pc
connect slots_15.io.brupdate.b2.uop.is_rvc, issue_slots[15].brupdate.b2.uop.is_rvc
connect slots_15.io.brupdate.b2.uop.debug_inst, issue_slots[15].brupdate.b2.uop.debug_inst
connect slots_15.io.brupdate.b2.uop.inst, issue_slots[15].brupdate.b2.uop.inst
connect slots_15.io.brupdate.b2.uop.uopc, issue_slots[15].brupdate.b2.uop.uopc
connect slots_15.io.brupdate.b1.mispredict_mask, issue_slots[15].brupdate.b1.mispredict_mask
connect slots_15.io.brupdate.b1.resolve_mask, issue_slots[15].brupdate.b1.resolve_mask
connect slots_15.io.grant, issue_slots[15].grant
connect issue_slots[15].request_hp, slots_15.io.request_hp
connect issue_slots[15].request, slots_15.io.request
connect issue_slots[15].will_be_valid, slots_15.io.will_be_valid
connect issue_slots[15].valid, slots_15.io.valid
connect issue_slots[16].debug.state, slots_16.io.debug.state
connect issue_slots[16].debug.ppred, slots_16.io.debug.ppred
connect issue_slots[16].debug.p3, slots_16.io.debug.p3
connect issue_slots[16].debug.p2, slots_16.io.debug.p2
connect issue_slots[16].debug.p1, slots_16.io.debug.p1
connect issue_slots[16].uop.debug_tsrc, slots_16.io.uop.debug_tsrc
connect issue_slots[16].uop.debug_fsrc, slots_16.io.uop.debug_fsrc
connect issue_slots[16].uop.bp_xcpt_if, slots_16.io.uop.bp_xcpt_if
connect issue_slots[16].uop.bp_debug_if, slots_16.io.uop.bp_debug_if
connect issue_slots[16].uop.xcpt_ma_if, slots_16.io.uop.xcpt_ma_if
connect issue_slots[16].uop.xcpt_ae_if, slots_16.io.uop.xcpt_ae_if
connect issue_slots[16].uop.xcpt_pf_if, slots_16.io.uop.xcpt_pf_if
connect issue_slots[16].uop.fp_single, slots_16.io.uop.fp_single
connect issue_slots[16].uop.fp_val, slots_16.io.uop.fp_val
connect issue_slots[16].uop.frs3_en, slots_16.io.uop.frs3_en
connect issue_slots[16].uop.lrs2_rtype, slots_16.io.uop.lrs2_rtype
connect issue_slots[16].uop.lrs1_rtype, slots_16.io.uop.lrs1_rtype
connect issue_slots[16].uop.dst_rtype, slots_16.io.uop.dst_rtype
connect issue_slots[16].uop.ldst_val, slots_16.io.uop.ldst_val
connect issue_slots[16].uop.lrs3, slots_16.io.uop.lrs3
connect issue_slots[16].uop.lrs2, slots_16.io.uop.lrs2
connect issue_slots[16].uop.lrs1, slots_16.io.uop.lrs1
connect issue_slots[16].uop.ldst, slots_16.io.uop.ldst
connect issue_slots[16].uop.ldst_is_rs1, slots_16.io.uop.ldst_is_rs1
connect issue_slots[16].uop.flush_on_commit, slots_16.io.uop.flush_on_commit
connect issue_slots[16].uop.is_unique, slots_16.io.uop.is_unique
connect issue_slots[16].uop.is_sys_pc2epc, slots_16.io.uop.is_sys_pc2epc
connect issue_slots[16].uop.uses_stq, slots_16.io.uop.uses_stq
connect issue_slots[16].uop.uses_ldq, slots_16.io.uop.uses_ldq
connect issue_slots[16].uop.is_amo, slots_16.io.uop.is_amo
connect issue_slots[16].uop.is_fencei, slots_16.io.uop.is_fencei
connect issue_slots[16].uop.is_fence, slots_16.io.uop.is_fence
connect issue_slots[16].uop.mem_signed, slots_16.io.uop.mem_signed
connect issue_slots[16].uop.mem_size, slots_16.io.uop.mem_size
connect issue_slots[16].uop.mem_cmd, slots_16.io.uop.mem_cmd
connect issue_slots[16].uop.bypassable, slots_16.io.uop.bypassable
connect issue_slots[16].uop.exc_cause, slots_16.io.uop.exc_cause
connect issue_slots[16].uop.exception, slots_16.io.uop.exception
connect issue_slots[16].uop.stale_pdst, slots_16.io.uop.stale_pdst
connect issue_slots[16].uop.ppred_busy, slots_16.io.uop.ppred_busy
connect issue_slots[16].uop.prs3_busy, slots_16.io.uop.prs3_busy
connect issue_slots[16].uop.prs2_busy, slots_16.io.uop.prs2_busy
connect issue_slots[16].uop.prs1_busy, slots_16.io.uop.prs1_busy
connect issue_slots[16].uop.ppred, slots_16.io.uop.ppred
connect issue_slots[16].uop.prs3, slots_16.io.uop.prs3
connect issue_slots[16].uop.prs2, slots_16.io.uop.prs2
connect issue_slots[16].uop.prs1, slots_16.io.uop.prs1
connect issue_slots[16].uop.pdst, slots_16.io.uop.pdst
connect issue_slots[16].uop.rxq_idx, slots_16.io.uop.rxq_idx
connect issue_slots[16].uop.stq_idx, slots_16.io.uop.stq_idx
connect issue_slots[16].uop.ldq_idx, slots_16.io.uop.ldq_idx
connect issue_slots[16].uop.rob_idx, slots_16.io.uop.rob_idx
connect issue_slots[16].uop.csr_addr, slots_16.io.uop.csr_addr
connect issue_slots[16].uop.imm_packed, slots_16.io.uop.imm_packed
connect issue_slots[16].uop.taken, slots_16.io.uop.taken
connect issue_slots[16].uop.pc_lob, slots_16.io.uop.pc_lob
connect issue_slots[16].uop.edge_inst, slots_16.io.uop.edge_inst
connect issue_slots[16].uop.ftq_idx, slots_16.io.uop.ftq_idx
connect issue_slots[16].uop.br_tag, slots_16.io.uop.br_tag
connect issue_slots[16].uop.br_mask, slots_16.io.uop.br_mask
connect issue_slots[16].uop.is_sfb, slots_16.io.uop.is_sfb
connect issue_slots[16].uop.is_jal, slots_16.io.uop.is_jal
connect issue_slots[16].uop.is_jalr, slots_16.io.uop.is_jalr
connect issue_slots[16].uop.is_br, slots_16.io.uop.is_br
connect issue_slots[16].uop.iw_p2_poisoned, slots_16.io.uop.iw_p2_poisoned
connect issue_slots[16].uop.iw_p1_poisoned, slots_16.io.uop.iw_p1_poisoned
connect issue_slots[16].uop.iw_state, slots_16.io.uop.iw_state
connect issue_slots[16].uop.ctrl.is_std, slots_16.io.uop.ctrl.is_std
connect issue_slots[16].uop.ctrl.is_sta, slots_16.io.uop.ctrl.is_sta
connect issue_slots[16].uop.ctrl.is_load, slots_16.io.uop.ctrl.is_load
connect issue_slots[16].uop.ctrl.csr_cmd, slots_16.io.uop.ctrl.csr_cmd
connect issue_slots[16].uop.ctrl.fcn_dw, slots_16.io.uop.ctrl.fcn_dw
connect issue_slots[16].uop.ctrl.op_fcn, slots_16.io.uop.ctrl.op_fcn
connect issue_slots[16].uop.ctrl.imm_sel, slots_16.io.uop.ctrl.imm_sel
connect issue_slots[16].uop.ctrl.op2_sel, slots_16.io.uop.ctrl.op2_sel
connect issue_slots[16].uop.ctrl.op1_sel, slots_16.io.uop.ctrl.op1_sel
connect issue_slots[16].uop.ctrl.br_type, slots_16.io.uop.ctrl.br_type
connect issue_slots[16].uop.fu_code, slots_16.io.uop.fu_code
connect issue_slots[16].uop.iq_type, slots_16.io.uop.iq_type
connect issue_slots[16].uop.debug_pc, slots_16.io.uop.debug_pc
connect issue_slots[16].uop.is_rvc, slots_16.io.uop.is_rvc
connect issue_slots[16].uop.debug_inst, slots_16.io.uop.debug_inst
connect issue_slots[16].uop.inst, slots_16.io.uop.inst
connect issue_slots[16].uop.uopc, slots_16.io.uop.uopc
connect issue_slots[16].out_uop.debug_tsrc, slots_16.io.out_uop.debug_tsrc
connect issue_slots[16].out_uop.debug_fsrc, slots_16.io.out_uop.debug_fsrc
connect issue_slots[16].out_uop.bp_xcpt_if, slots_16.io.out_uop.bp_xcpt_if
connect issue_slots[16].out_uop.bp_debug_if, slots_16.io.out_uop.bp_debug_if
connect issue_slots[16].out_uop.xcpt_ma_if, slots_16.io.out_uop.xcpt_ma_if
connect issue_slots[16].out_uop.xcpt_ae_if, slots_16.io.out_uop.xcpt_ae_if
connect issue_slots[16].out_uop.xcpt_pf_if, slots_16.io.out_uop.xcpt_pf_if
connect issue_slots[16].out_uop.fp_single, slots_16.io.out_uop.fp_single
connect issue_slots[16].out_uop.fp_val, slots_16.io.out_uop.fp_val
connect issue_slots[16].out_uop.frs3_en, slots_16.io.out_uop.frs3_en
connect issue_slots[16].out_uop.lrs2_rtype, slots_16.io.out_uop.lrs2_rtype
connect issue_slots[16].out_uop.lrs1_rtype, slots_16.io.out_uop.lrs1_rtype
connect issue_slots[16].out_uop.dst_rtype, slots_16.io.out_uop.dst_rtype
connect issue_slots[16].out_uop.ldst_val, slots_16.io.out_uop.ldst_val
connect issue_slots[16].out_uop.lrs3, slots_16.io.out_uop.lrs3
connect issue_slots[16].out_uop.lrs2, slots_16.io.out_uop.lrs2
connect issue_slots[16].out_uop.lrs1, slots_16.io.out_uop.lrs1
connect issue_slots[16].out_uop.ldst, slots_16.io.out_uop.ldst
connect issue_slots[16].out_uop.ldst_is_rs1, slots_16.io.out_uop.ldst_is_rs1
connect issue_slots[16].out_uop.flush_on_commit, slots_16.io.out_uop.flush_on_commit
connect issue_slots[16].out_uop.is_unique, slots_16.io.out_uop.is_unique
connect issue_slots[16].out_uop.is_sys_pc2epc, slots_16.io.out_uop.is_sys_pc2epc
connect issue_slots[16].out_uop.uses_stq, slots_16.io.out_uop.uses_stq
connect issue_slots[16].out_uop.uses_ldq, slots_16.io.out_uop.uses_ldq
connect issue_slots[16].out_uop.is_amo, slots_16.io.out_uop.is_amo
connect issue_slots[16].out_uop.is_fencei, slots_16.io.out_uop.is_fencei
connect issue_slots[16].out_uop.is_fence, slots_16.io.out_uop.is_fence
connect issue_slots[16].out_uop.mem_signed, slots_16.io.out_uop.mem_signed
connect issue_slots[16].out_uop.mem_size, slots_16.io.out_uop.mem_size
connect issue_slots[16].out_uop.mem_cmd, slots_16.io.out_uop.mem_cmd
connect issue_slots[16].out_uop.bypassable, slots_16.io.out_uop.bypassable
connect issue_slots[16].out_uop.exc_cause, slots_16.io.out_uop.exc_cause
connect issue_slots[16].out_uop.exception, slots_16.io.out_uop.exception
connect issue_slots[16].out_uop.stale_pdst, slots_16.io.out_uop.stale_pdst
connect issue_slots[16].out_uop.ppred_busy, slots_16.io.out_uop.ppred_busy
connect issue_slots[16].out_uop.prs3_busy, slots_16.io.out_uop.prs3_busy
connect issue_slots[16].out_uop.prs2_busy, slots_16.io.out_uop.prs2_busy
connect issue_slots[16].out_uop.prs1_busy, slots_16.io.out_uop.prs1_busy
connect issue_slots[16].out_uop.ppred, slots_16.io.out_uop.ppred
connect issue_slots[16].out_uop.prs3, slots_16.io.out_uop.prs3
connect issue_slots[16].out_uop.prs2, slots_16.io.out_uop.prs2
connect issue_slots[16].out_uop.prs1, slots_16.io.out_uop.prs1
connect issue_slots[16].out_uop.pdst, slots_16.io.out_uop.pdst
connect issue_slots[16].out_uop.rxq_idx, slots_16.io.out_uop.rxq_idx
connect issue_slots[16].out_uop.stq_idx, slots_16.io.out_uop.stq_idx
connect issue_slots[16].out_uop.ldq_idx, slots_16.io.out_uop.ldq_idx
connect issue_slots[16].out_uop.rob_idx, slots_16.io.out_uop.rob_idx
connect issue_slots[16].out_uop.csr_addr, slots_16.io.out_uop.csr_addr
connect issue_slots[16].out_uop.imm_packed, slots_16.io.out_uop.imm_packed
connect issue_slots[16].out_uop.taken, slots_16.io.out_uop.taken
connect issue_slots[16].out_uop.pc_lob, slots_16.io.out_uop.pc_lob
connect issue_slots[16].out_uop.edge_inst, slots_16.io.out_uop.edge_inst
connect issue_slots[16].out_uop.ftq_idx, slots_16.io.out_uop.ftq_idx
connect issue_slots[16].out_uop.br_tag, slots_16.io.out_uop.br_tag
connect issue_slots[16].out_uop.br_mask, slots_16.io.out_uop.br_mask
connect issue_slots[16].out_uop.is_sfb, slots_16.io.out_uop.is_sfb
connect issue_slots[16].out_uop.is_jal, slots_16.io.out_uop.is_jal
connect issue_slots[16].out_uop.is_jalr, slots_16.io.out_uop.is_jalr
connect issue_slots[16].out_uop.is_br, slots_16.io.out_uop.is_br
connect issue_slots[16].out_uop.iw_p2_poisoned, slots_16.io.out_uop.iw_p2_poisoned
connect issue_slots[16].out_uop.iw_p1_poisoned, slots_16.io.out_uop.iw_p1_poisoned
connect issue_slots[16].out_uop.iw_state, slots_16.io.out_uop.iw_state
connect issue_slots[16].out_uop.ctrl.is_std, slots_16.io.out_uop.ctrl.is_std
connect issue_slots[16].out_uop.ctrl.is_sta, slots_16.io.out_uop.ctrl.is_sta
connect issue_slots[16].out_uop.ctrl.is_load, slots_16.io.out_uop.ctrl.is_load
connect issue_slots[16].out_uop.ctrl.csr_cmd, slots_16.io.out_uop.ctrl.csr_cmd
connect issue_slots[16].out_uop.ctrl.fcn_dw, slots_16.io.out_uop.ctrl.fcn_dw
connect issue_slots[16].out_uop.ctrl.op_fcn, slots_16.io.out_uop.ctrl.op_fcn
connect issue_slots[16].out_uop.ctrl.imm_sel, slots_16.io.out_uop.ctrl.imm_sel
connect issue_slots[16].out_uop.ctrl.op2_sel, slots_16.io.out_uop.ctrl.op2_sel
connect issue_slots[16].out_uop.ctrl.op1_sel, slots_16.io.out_uop.ctrl.op1_sel
connect issue_slots[16].out_uop.ctrl.br_type, slots_16.io.out_uop.ctrl.br_type
connect issue_slots[16].out_uop.fu_code, slots_16.io.out_uop.fu_code
connect issue_slots[16].out_uop.iq_type, slots_16.io.out_uop.iq_type
connect issue_slots[16].out_uop.debug_pc, slots_16.io.out_uop.debug_pc
connect issue_slots[16].out_uop.is_rvc, slots_16.io.out_uop.is_rvc
connect issue_slots[16].out_uop.debug_inst, slots_16.io.out_uop.debug_inst
connect issue_slots[16].out_uop.inst, slots_16.io.out_uop.inst
connect issue_slots[16].out_uop.uopc, slots_16.io.out_uop.uopc
connect slots_16.io.in_uop.bits.debug_tsrc, issue_slots[16].in_uop.bits.debug_tsrc
connect slots_16.io.in_uop.bits.debug_fsrc, issue_slots[16].in_uop.bits.debug_fsrc
connect slots_16.io.in_uop.bits.bp_xcpt_if, issue_slots[16].in_uop.bits.bp_xcpt_if
connect slots_16.io.in_uop.bits.bp_debug_if, issue_slots[16].in_uop.bits.bp_debug_if
connect slots_16.io.in_uop.bits.xcpt_ma_if, issue_slots[16].in_uop.bits.xcpt_ma_if
connect slots_16.io.in_uop.bits.xcpt_ae_if, issue_slots[16].in_uop.bits.xcpt_ae_if
connect slots_16.io.in_uop.bits.xcpt_pf_if, issue_slots[16].in_uop.bits.xcpt_pf_if
connect slots_16.io.in_uop.bits.fp_single, issue_slots[16].in_uop.bits.fp_single
connect slots_16.io.in_uop.bits.fp_val, issue_slots[16].in_uop.bits.fp_val
connect slots_16.io.in_uop.bits.frs3_en, issue_slots[16].in_uop.bits.frs3_en
connect slots_16.io.in_uop.bits.lrs2_rtype, issue_slots[16].in_uop.bits.lrs2_rtype
connect slots_16.io.in_uop.bits.lrs1_rtype, issue_slots[16].in_uop.bits.lrs1_rtype
connect slots_16.io.in_uop.bits.dst_rtype, issue_slots[16].in_uop.bits.dst_rtype
connect slots_16.io.in_uop.bits.ldst_val, issue_slots[16].in_uop.bits.ldst_val
connect slots_16.io.in_uop.bits.lrs3, issue_slots[16].in_uop.bits.lrs3
connect slots_16.io.in_uop.bits.lrs2, issue_slots[16].in_uop.bits.lrs2
connect slots_16.io.in_uop.bits.lrs1, issue_slots[16].in_uop.bits.lrs1
connect slots_16.io.in_uop.bits.ldst, issue_slots[16].in_uop.bits.ldst
connect slots_16.io.in_uop.bits.ldst_is_rs1, issue_slots[16].in_uop.bits.ldst_is_rs1
connect slots_16.io.in_uop.bits.flush_on_commit, issue_slots[16].in_uop.bits.flush_on_commit
connect slots_16.io.in_uop.bits.is_unique, issue_slots[16].in_uop.bits.is_unique
connect slots_16.io.in_uop.bits.is_sys_pc2epc, issue_slots[16].in_uop.bits.is_sys_pc2epc
connect slots_16.io.in_uop.bits.uses_stq, issue_slots[16].in_uop.bits.uses_stq
connect slots_16.io.in_uop.bits.uses_ldq, issue_slots[16].in_uop.bits.uses_ldq
connect slots_16.io.in_uop.bits.is_amo, issue_slots[16].in_uop.bits.is_amo
connect slots_16.io.in_uop.bits.is_fencei, issue_slots[16].in_uop.bits.is_fencei
connect slots_16.io.in_uop.bits.is_fence, issue_slots[16].in_uop.bits.is_fence
connect slots_16.io.in_uop.bits.mem_signed, issue_slots[16].in_uop.bits.mem_signed
connect slots_16.io.in_uop.bits.mem_size, issue_slots[16].in_uop.bits.mem_size
connect slots_16.io.in_uop.bits.mem_cmd, issue_slots[16].in_uop.bits.mem_cmd
connect slots_16.io.in_uop.bits.bypassable, issue_slots[16].in_uop.bits.bypassable
connect slots_16.io.in_uop.bits.exc_cause, issue_slots[16].in_uop.bits.exc_cause
connect slots_16.io.in_uop.bits.exception, issue_slots[16].in_uop.bits.exception
connect slots_16.io.in_uop.bits.stale_pdst, issue_slots[16].in_uop.bits.stale_pdst
connect slots_16.io.in_uop.bits.ppred_busy, issue_slots[16].in_uop.bits.ppred_busy
connect slots_16.io.in_uop.bits.prs3_busy, issue_slots[16].in_uop.bits.prs3_busy
connect slots_16.io.in_uop.bits.prs2_busy, issue_slots[16].in_uop.bits.prs2_busy
connect slots_16.io.in_uop.bits.prs1_busy, issue_slots[16].in_uop.bits.prs1_busy
connect slots_16.io.in_uop.bits.ppred, issue_slots[16].in_uop.bits.ppred
connect slots_16.io.in_uop.bits.prs3, issue_slots[16].in_uop.bits.prs3
connect slots_16.io.in_uop.bits.prs2, issue_slots[16].in_uop.bits.prs2
connect slots_16.io.in_uop.bits.prs1, issue_slots[16].in_uop.bits.prs1
connect slots_16.io.in_uop.bits.pdst, issue_slots[16].in_uop.bits.pdst
connect slots_16.io.in_uop.bits.rxq_idx, issue_slots[16].in_uop.bits.rxq_idx
connect slots_16.io.in_uop.bits.stq_idx, issue_slots[16].in_uop.bits.stq_idx
connect slots_16.io.in_uop.bits.ldq_idx, issue_slots[16].in_uop.bits.ldq_idx
connect slots_16.io.in_uop.bits.rob_idx, issue_slots[16].in_uop.bits.rob_idx
connect slots_16.io.in_uop.bits.csr_addr, issue_slots[16].in_uop.bits.csr_addr
connect slots_16.io.in_uop.bits.imm_packed, issue_slots[16].in_uop.bits.imm_packed
connect slots_16.io.in_uop.bits.taken, issue_slots[16].in_uop.bits.taken
connect slots_16.io.in_uop.bits.pc_lob, issue_slots[16].in_uop.bits.pc_lob
connect slots_16.io.in_uop.bits.edge_inst, issue_slots[16].in_uop.bits.edge_inst
connect slots_16.io.in_uop.bits.ftq_idx, issue_slots[16].in_uop.bits.ftq_idx
connect slots_16.io.in_uop.bits.br_tag, issue_slots[16].in_uop.bits.br_tag
connect slots_16.io.in_uop.bits.br_mask, issue_slots[16].in_uop.bits.br_mask
connect slots_16.io.in_uop.bits.is_sfb, issue_slots[16].in_uop.bits.is_sfb
connect slots_16.io.in_uop.bits.is_jal, issue_slots[16].in_uop.bits.is_jal
connect slots_16.io.in_uop.bits.is_jalr, issue_slots[16].in_uop.bits.is_jalr
connect slots_16.io.in_uop.bits.is_br, issue_slots[16].in_uop.bits.is_br
connect slots_16.io.in_uop.bits.iw_p2_poisoned, issue_slots[16].in_uop.bits.iw_p2_poisoned
connect slots_16.io.in_uop.bits.iw_p1_poisoned, issue_slots[16].in_uop.bits.iw_p1_poisoned
connect slots_16.io.in_uop.bits.iw_state, issue_slots[16].in_uop.bits.iw_state
connect slots_16.io.in_uop.bits.ctrl.is_std, issue_slots[16].in_uop.bits.ctrl.is_std
connect slots_16.io.in_uop.bits.ctrl.is_sta, issue_slots[16].in_uop.bits.ctrl.is_sta
connect slots_16.io.in_uop.bits.ctrl.is_load, issue_slots[16].in_uop.bits.ctrl.is_load
connect slots_16.io.in_uop.bits.ctrl.csr_cmd, issue_slots[16].in_uop.bits.ctrl.csr_cmd
connect slots_16.io.in_uop.bits.ctrl.fcn_dw, issue_slots[16].in_uop.bits.ctrl.fcn_dw
connect slots_16.io.in_uop.bits.ctrl.op_fcn, issue_slots[16].in_uop.bits.ctrl.op_fcn
connect slots_16.io.in_uop.bits.ctrl.imm_sel, issue_slots[16].in_uop.bits.ctrl.imm_sel
connect slots_16.io.in_uop.bits.ctrl.op2_sel, issue_slots[16].in_uop.bits.ctrl.op2_sel
connect slots_16.io.in_uop.bits.ctrl.op1_sel, issue_slots[16].in_uop.bits.ctrl.op1_sel
connect slots_16.io.in_uop.bits.ctrl.br_type, issue_slots[16].in_uop.bits.ctrl.br_type
connect slots_16.io.in_uop.bits.fu_code, issue_slots[16].in_uop.bits.fu_code
connect slots_16.io.in_uop.bits.iq_type, issue_slots[16].in_uop.bits.iq_type
connect slots_16.io.in_uop.bits.debug_pc, issue_slots[16].in_uop.bits.debug_pc
connect slots_16.io.in_uop.bits.is_rvc, issue_slots[16].in_uop.bits.is_rvc
connect slots_16.io.in_uop.bits.debug_inst, issue_slots[16].in_uop.bits.debug_inst
connect slots_16.io.in_uop.bits.inst, issue_slots[16].in_uop.bits.inst
connect slots_16.io.in_uop.bits.uopc, issue_slots[16].in_uop.bits.uopc
connect slots_16.io.in_uop.valid, issue_slots[16].in_uop.valid
connect slots_16.io.spec_ld_wakeup[0].bits, issue_slots[16].spec_ld_wakeup[0].bits
connect slots_16.io.spec_ld_wakeup[0].valid, issue_slots[16].spec_ld_wakeup[0].valid
connect slots_16.io.pred_wakeup_port.bits, issue_slots[16].pred_wakeup_port.bits
connect slots_16.io.pred_wakeup_port.valid, issue_slots[16].pred_wakeup_port.valid
connect slots_16.io.wakeup_ports[0].bits.poisoned, issue_slots[16].wakeup_ports[0].bits.poisoned
connect slots_16.io.wakeup_ports[0].bits.pdst, issue_slots[16].wakeup_ports[0].bits.pdst
connect slots_16.io.wakeup_ports[0].valid, issue_slots[16].wakeup_ports[0].valid
connect slots_16.io.wakeup_ports[1].bits.poisoned, issue_slots[16].wakeup_ports[1].bits.poisoned
connect slots_16.io.wakeup_ports[1].bits.pdst, issue_slots[16].wakeup_ports[1].bits.pdst
connect slots_16.io.wakeup_ports[1].valid, issue_slots[16].wakeup_ports[1].valid
connect slots_16.io.ldspec_miss, issue_slots[16].ldspec_miss
connect slots_16.io.clear, issue_slots[16].clear
connect slots_16.io.kill, issue_slots[16].kill
connect slots_16.io.brupdate.b2.target_offset, issue_slots[16].brupdate.b2.target_offset
connect slots_16.io.brupdate.b2.jalr_target, issue_slots[16].brupdate.b2.jalr_target
connect slots_16.io.brupdate.b2.pc_sel, issue_slots[16].brupdate.b2.pc_sel
connect slots_16.io.brupdate.b2.cfi_type, issue_slots[16].brupdate.b2.cfi_type
connect slots_16.io.brupdate.b2.taken, issue_slots[16].brupdate.b2.taken
connect slots_16.io.brupdate.b2.mispredict, issue_slots[16].brupdate.b2.mispredict
connect slots_16.io.brupdate.b2.valid, issue_slots[16].brupdate.b2.valid
connect slots_16.io.brupdate.b2.uop.debug_tsrc, issue_slots[16].brupdate.b2.uop.debug_tsrc
connect slots_16.io.brupdate.b2.uop.debug_fsrc, issue_slots[16].brupdate.b2.uop.debug_fsrc
connect slots_16.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[16].brupdate.b2.uop.bp_xcpt_if
connect slots_16.io.brupdate.b2.uop.bp_debug_if, issue_slots[16].brupdate.b2.uop.bp_debug_if
connect slots_16.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[16].brupdate.b2.uop.xcpt_ma_if
connect slots_16.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[16].brupdate.b2.uop.xcpt_ae_if
connect slots_16.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[16].brupdate.b2.uop.xcpt_pf_if
connect slots_16.io.brupdate.b2.uop.fp_single, issue_slots[16].brupdate.b2.uop.fp_single
connect slots_16.io.brupdate.b2.uop.fp_val, issue_slots[16].brupdate.b2.uop.fp_val
connect slots_16.io.brupdate.b2.uop.frs3_en, issue_slots[16].brupdate.b2.uop.frs3_en
connect slots_16.io.brupdate.b2.uop.lrs2_rtype, issue_slots[16].brupdate.b2.uop.lrs2_rtype
connect slots_16.io.brupdate.b2.uop.lrs1_rtype, issue_slots[16].brupdate.b2.uop.lrs1_rtype
connect slots_16.io.brupdate.b2.uop.dst_rtype, issue_slots[16].brupdate.b2.uop.dst_rtype
connect slots_16.io.brupdate.b2.uop.ldst_val, issue_slots[16].brupdate.b2.uop.ldst_val
connect slots_16.io.brupdate.b2.uop.lrs3, issue_slots[16].brupdate.b2.uop.lrs3
connect slots_16.io.brupdate.b2.uop.lrs2, issue_slots[16].brupdate.b2.uop.lrs2
connect slots_16.io.brupdate.b2.uop.lrs1, issue_slots[16].brupdate.b2.uop.lrs1
connect slots_16.io.brupdate.b2.uop.ldst, issue_slots[16].brupdate.b2.uop.ldst
connect slots_16.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[16].brupdate.b2.uop.ldst_is_rs1
connect slots_16.io.brupdate.b2.uop.flush_on_commit, issue_slots[16].brupdate.b2.uop.flush_on_commit
connect slots_16.io.brupdate.b2.uop.is_unique, issue_slots[16].brupdate.b2.uop.is_unique
connect slots_16.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[16].brupdate.b2.uop.is_sys_pc2epc
connect slots_16.io.brupdate.b2.uop.uses_stq, issue_slots[16].brupdate.b2.uop.uses_stq
connect slots_16.io.brupdate.b2.uop.uses_ldq, issue_slots[16].brupdate.b2.uop.uses_ldq
connect slots_16.io.brupdate.b2.uop.is_amo, issue_slots[16].brupdate.b2.uop.is_amo
connect slots_16.io.brupdate.b2.uop.is_fencei, issue_slots[16].brupdate.b2.uop.is_fencei
connect slots_16.io.brupdate.b2.uop.is_fence, issue_slots[16].brupdate.b2.uop.is_fence
connect slots_16.io.brupdate.b2.uop.mem_signed, issue_slots[16].brupdate.b2.uop.mem_signed
connect slots_16.io.brupdate.b2.uop.mem_size, issue_slots[16].brupdate.b2.uop.mem_size
connect slots_16.io.brupdate.b2.uop.mem_cmd, issue_slots[16].brupdate.b2.uop.mem_cmd
connect slots_16.io.brupdate.b2.uop.bypassable, issue_slots[16].brupdate.b2.uop.bypassable
connect slots_16.io.brupdate.b2.uop.exc_cause, issue_slots[16].brupdate.b2.uop.exc_cause
connect slots_16.io.brupdate.b2.uop.exception, issue_slots[16].brupdate.b2.uop.exception
connect slots_16.io.brupdate.b2.uop.stale_pdst, issue_slots[16].brupdate.b2.uop.stale_pdst
connect slots_16.io.brupdate.b2.uop.ppred_busy, issue_slots[16].brupdate.b2.uop.ppred_busy
connect slots_16.io.brupdate.b2.uop.prs3_busy, issue_slots[16].brupdate.b2.uop.prs3_busy
connect slots_16.io.brupdate.b2.uop.prs2_busy, issue_slots[16].brupdate.b2.uop.prs2_busy
connect slots_16.io.brupdate.b2.uop.prs1_busy, issue_slots[16].brupdate.b2.uop.prs1_busy
connect slots_16.io.brupdate.b2.uop.ppred, issue_slots[16].brupdate.b2.uop.ppred
connect slots_16.io.brupdate.b2.uop.prs3, issue_slots[16].brupdate.b2.uop.prs3
connect slots_16.io.brupdate.b2.uop.prs2, issue_slots[16].brupdate.b2.uop.prs2
connect slots_16.io.brupdate.b2.uop.prs1, issue_slots[16].brupdate.b2.uop.prs1
connect slots_16.io.brupdate.b2.uop.pdst, issue_slots[16].brupdate.b2.uop.pdst
connect slots_16.io.brupdate.b2.uop.rxq_idx, issue_slots[16].brupdate.b2.uop.rxq_idx
connect slots_16.io.brupdate.b2.uop.stq_idx, issue_slots[16].brupdate.b2.uop.stq_idx
connect slots_16.io.brupdate.b2.uop.ldq_idx, issue_slots[16].brupdate.b2.uop.ldq_idx
connect slots_16.io.brupdate.b2.uop.rob_idx, issue_slots[16].brupdate.b2.uop.rob_idx
connect slots_16.io.brupdate.b2.uop.csr_addr, issue_slots[16].brupdate.b2.uop.csr_addr
connect slots_16.io.brupdate.b2.uop.imm_packed, issue_slots[16].brupdate.b2.uop.imm_packed
connect slots_16.io.brupdate.b2.uop.taken, issue_slots[16].brupdate.b2.uop.taken
connect slots_16.io.brupdate.b2.uop.pc_lob, issue_slots[16].brupdate.b2.uop.pc_lob
connect slots_16.io.brupdate.b2.uop.edge_inst, issue_slots[16].brupdate.b2.uop.edge_inst
connect slots_16.io.brupdate.b2.uop.ftq_idx, issue_slots[16].brupdate.b2.uop.ftq_idx
connect slots_16.io.brupdate.b2.uop.br_tag, issue_slots[16].brupdate.b2.uop.br_tag
connect slots_16.io.brupdate.b2.uop.br_mask, issue_slots[16].brupdate.b2.uop.br_mask
connect slots_16.io.brupdate.b2.uop.is_sfb, issue_slots[16].brupdate.b2.uop.is_sfb
connect slots_16.io.brupdate.b2.uop.is_jal, issue_slots[16].brupdate.b2.uop.is_jal
connect slots_16.io.brupdate.b2.uop.is_jalr, issue_slots[16].brupdate.b2.uop.is_jalr
connect slots_16.io.brupdate.b2.uop.is_br, issue_slots[16].brupdate.b2.uop.is_br
connect slots_16.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[16].brupdate.b2.uop.iw_p2_poisoned
connect slots_16.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[16].brupdate.b2.uop.iw_p1_poisoned
connect slots_16.io.brupdate.b2.uop.iw_state, issue_slots[16].brupdate.b2.uop.iw_state
connect slots_16.io.brupdate.b2.uop.ctrl.is_std, issue_slots[16].brupdate.b2.uop.ctrl.is_std
connect slots_16.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[16].brupdate.b2.uop.ctrl.is_sta
connect slots_16.io.brupdate.b2.uop.ctrl.is_load, issue_slots[16].brupdate.b2.uop.ctrl.is_load
connect slots_16.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[16].brupdate.b2.uop.ctrl.csr_cmd
connect slots_16.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[16].brupdate.b2.uop.ctrl.fcn_dw
connect slots_16.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[16].brupdate.b2.uop.ctrl.op_fcn
connect slots_16.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[16].brupdate.b2.uop.ctrl.imm_sel
connect slots_16.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[16].brupdate.b2.uop.ctrl.op2_sel
connect slots_16.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[16].brupdate.b2.uop.ctrl.op1_sel
connect slots_16.io.brupdate.b2.uop.ctrl.br_type, issue_slots[16].brupdate.b2.uop.ctrl.br_type
connect slots_16.io.brupdate.b2.uop.fu_code, issue_slots[16].brupdate.b2.uop.fu_code
connect slots_16.io.brupdate.b2.uop.iq_type, issue_slots[16].brupdate.b2.uop.iq_type
connect slots_16.io.brupdate.b2.uop.debug_pc, issue_slots[16].brupdate.b2.uop.debug_pc
connect slots_16.io.brupdate.b2.uop.is_rvc, issue_slots[16].brupdate.b2.uop.is_rvc
connect slots_16.io.brupdate.b2.uop.debug_inst, issue_slots[16].brupdate.b2.uop.debug_inst
connect slots_16.io.brupdate.b2.uop.inst, issue_slots[16].brupdate.b2.uop.inst
connect slots_16.io.brupdate.b2.uop.uopc, issue_slots[16].brupdate.b2.uop.uopc
connect slots_16.io.brupdate.b1.mispredict_mask, issue_slots[16].brupdate.b1.mispredict_mask
connect slots_16.io.brupdate.b1.resolve_mask, issue_slots[16].brupdate.b1.resolve_mask
connect slots_16.io.grant, issue_slots[16].grant
connect issue_slots[16].request_hp, slots_16.io.request_hp
connect issue_slots[16].request, slots_16.io.request
connect issue_slots[16].will_be_valid, slots_16.io.will_be_valid
connect issue_slots[16].valid, slots_16.io.valid
connect issue_slots[17].debug.state, slots_17.io.debug.state
connect issue_slots[17].debug.ppred, slots_17.io.debug.ppred
connect issue_slots[17].debug.p3, slots_17.io.debug.p3
connect issue_slots[17].debug.p2, slots_17.io.debug.p2
connect issue_slots[17].debug.p1, slots_17.io.debug.p1
connect issue_slots[17].uop.debug_tsrc, slots_17.io.uop.debug_tsrc
connect issue_slots[17].uop.debug_fsrc, slots_17.io.uop.debug_fsrc
connect issue_slots[17].uop.bp_xcpt_if, slots_17.io.uop.bp_xcpt_if
connect issue_slots[17].uop.bp_debug_if, slots_17.io.uop.bp_debug_if
connect issue_slots[17].uop.xcpt_ma_if, slots_17.io.uop.xcpt_ma_if
connect issue_slots[17].uop.xcpt_ae_if, slots_17.io.uop.xcpt_ae_if
connect issue_slots[17].uop.xcpt_pf_if, slots_17.io.uop.xcpt_pf_if
connect issue_slots[17].uop.fp_single, slots_17.io.uop.fp_single
connect issue_slots[17].uop.fp_val, slots_17.io.uop.fp_val
connect issue_slots[17].uop.frs3_en, slots_17.io.uop.frs3_en
connect issue_slots[17].uop.lrs2_rtype, slots_17.io.uop.lrs2_rtype
connect issue_slots[17].uop.lrs1_rtype, slots_17.io.uop.lrs1_rtype
connect issue_slots[17].uop.dst_rtype, slots_17.io.uop.dst_rtype
connect issue_slots[17].uop.ldst_val, slots_17.io.uop.ldst_val
connect issue_slots[17].uop.lrs3, slots_17.io.uop.lrs3
connect issue_slots[17].uop.lrs2, slots_17.io.uop.lrs2
connect issue_slots[17].uop.lrs1, slots_17.io.uop.lrs1
connect issue_slots[17].uop.ldst, slots_17.io.uop.ldst
connect issue_slots[17].uop.ldst_is_rs1, slots_17.io.uop.ldst_is_rs1
connect issue_slots[17].uop.flush_on_commit, slots_17.io.uop.flush_on_commit
connect issue_slots[17].uop.is_unique, slots_17.io.uop.is_unique
connect issue_slots[17].uop.is_sys_pc2epc, slots_17.io.uop.is_sys_pc2epc
connect issue_slots[17].uop.uses_stq, slots_17.io.uop.uses_stq
connect issue_slots[17].uop.uses_ldq, slots_17.io.uop.uses_ldq
connect issue_slots[17].uop.is_amo, slots_17.io.uop.is_amo
connect issue_slots[17].uop.is_fencei, slots_17.io.uop.is_fencei
connect issue_slots[17].uop.is_fence, slots_17.io.uop.is_fence
connect issue_slots[17].uop.mem_signed, slots_17.io.uop.mem_signed
connect issue_slots[17].uop.mem_size, slots_17.io.uop.mem_size
connect issue_slots[17].uop.mem_cmd, slots_17.io.uop.mem_cmd
connect issue_slots[17].uop.bypassable, slots_17.io.uop.bypassable
connect issue_slots[17].uop.exc_cause, slots_17.io.uop.exc_cause
connect issue_slots[17].uop.exception, slots_17.io.uop.exception
connect issue_slots[17].uop.stale_pdst, slots_17.io.uop.stale_pdst
connect issue_slots[17].uop.ppred_busy, slots_17.io.uop.ppred_busy
connect issue_slots[17].uop.prs3_busy, slots_17.io.uop.prs3_busy
connect issue_slots[17].uop.prs2_busy, slots_17.io.uop.prs2_busy
connect issue_slots[17].uop.prs1_busy, slots_17.io.uop.prs1_busy
connect issue_slots[17].uop.ppred, slots_17.io.uop.ppred
connect issue_slots[17].uop.prs3, slots_17.io.uop.prs3
connect issue_slots[17].uop.prs2, slots_17.io.uop.prs2
connect issue_slots[17].uop.prs1, slots_17.io.uop.prs1
connect issue_slots[17].uop.pdst, slots_17.io.uop.pdst
connect issue_slots[17].uop.rxq_idx, slots_17.io.uop.rxq_idx
connect issue_slots[17].uop.stq_idx, slots_17.io.uop.stq_idx
connect issue_slots[17].uop.ldq_idx, slots_17.io.uop.ldq_idx
connect issue_slots[17].uop.rob_idx, slots_17.io.uop.rob_idx
connect issue_slots[17].uop.csr_addr, slots_17.io.uop.csr_addr
connect issue_slots[17].uop.imm_packed, slots_17.io.uop.imm_packed
connect issue_slots[17].uop.taken, slots_17.io.uop.taken
connect issue_slots[17].uop.pc_lob, slots_17.io.uop.pc_lob
connect issue_slots[17].uop.edge_inst, slots_17.io.uop.edge_inst
connect issue_slots[17].uop.ftq_idx, slots_17.io.uop.ftq_idx
connect issue_slots[17].uop.br_tag, slots_17.io.uop.br_tag
connect issue_slots[17].uop.br_mask, slots_17.io.uop.br_mask
connect issue_slots[17].uop.is_sfb, slots_17.io.uop.is_sfb
connect issue_slots[17].uop.is_jal, slots_17.io.uop.is_jal
connect issue_slots[17].uop.is_jalr, slots_17.io.uop.is_jalr
connect issue_slots[17].uop.is_br, slots_17.io.uop.is_br
connect issue_slots[17].uop.iw_p2_poisoned, slots_17.io.uop.iw_p2_poisoned
connect issue_slots[17].uop.iw_p1_poisoned, slots_17.io.uop.iw_p1_poisoned
connect issue_slots[17].uop.iw_state, slots_17.io.uop.iw_state
connect issue_slots[17].uop.ctrl.is_std, slots_17.io.uop.ctrl.is_std
connect issue_slots[17].uop.ctrl.is_sta, slots_17.io.uop.ctrl.is_sta
connect issue_slots[17].uop.ctrl.is_load, slots_17.io.uop.ctrl.is_load
connect issue_slots[17].uop.ctrl.csr_cmd, slots_17.io.uop.ctrl.csr_cmd
connect issue_slots[17].uop.ctrl.fcn_dw, slots_17.io.uop.ctrl.fcn_dw
connect issue_slots[17].uop.ctrl.op_fcn, slots_17.io.uop.ctrl.op_fcn
connect issue_slots[17].uop.ctrl.imm_sel, slots_17.io.uop.ctrl.imm_sel
connect issue_slots[17].uop.ctrl.op2_sel, slots_17.io.uop.ctrl.op2_sel
connect issue_slots[17].uop.ctrl.op1_sel, slots_17.io.uop.ctrl.op1_sel
connect issue_slots[17].uop.ctrl.br_type, slots_17.io.uop.ctrl.br_type
connect issue_slots[17].uop.fu_code, slots_17.io.uop.fu_code
connect issue_slots[17].uop.iq_type, slots_17.io.uop.iq_type
connect issue_slots[17].uop.debug_pc, slots_17.io.uop.debug_pc
connect issue_slots[17].uop.is_rvc, slots_17.io.uop.is_rvc
connect issue_slots[17].uop.debug_inst, slots_17.io.uop.debug_inst
connect issue_slots[17].uop.inst, slots_17.io.uop.inst
connect issue_slots[17].uop.uopc, slots_17.io.uop.uopc
connect issue_slots[17].out_uop.debug_tsrc, slots_17.io.out_uop.debug_tsrc
connect issue_slots[17].out_uop.debug_fsrc, slots_17.io.out_uop.debug_fsrc
connect issue_slots[17].out_uop.bp_xcpt_if, slots_17.io.out_uop.bp_xcpt_if
connect issue_slots[17].out_uop.bp_debug_if, slots_17.io.out_uop.bp_debug_if
connect issue_slots[17].out_uop.xcpt_ma_if, slots_17.io.out_uop.xcpt_ma_if
connect issue_slots[17].out_uop.xcpt_ae_if, slots_17.io.out_uop.xcpt_ae_if
connect issue_slots[17].out_uop.xcpt_pf_if, slots_17.io.out_uop.xcpt_pf_if
connect issue_slots[17].out_uop.fp_single, slots_17.io.out_uop.fp_single
connect issue_slots[17].out_uop.fp_val, slots_17.io.out_uop.fp_val
connect issue_slots[17].out_uop.frs3_en, slots_17.io.out_uop.frs3_en
connect issue_slots[17].out_uop.lrs2_rtype, slots_17.io.out_uop.lrs2_rtype
connect issue_slots[17].out_uop.lrs1_rtype, slots_17.io.out_uop.lrs1_rtype
connect issue_slots[17].out_uop.dst_rtype, slots_17.io.out_uop.dst_rtype
connect issue_slots[17].out_uop.ldst_val, slots_17.io.out_uop.ldst_val
connect issue_slots[17].out_uop.lrs3, slots_17.io.out_uop.lrs3
connect issue_slots[17].out_uop.lrs2, slots_17.io.out_uop.lrs2
connect issue_slots[17].out_uop.lrs1, slots_17.io.out_uop.lrs1
connect issue_slots[17].out_uop.ldst, slots_17.io.out_uop.ldst
connect issue_slots[17].out_uop.ldst_is_rs1, slots_17.io.out_uop.ldst_is_rs1
connect issue_slots[17].out_uop.flush_on_commit, slots_17.io.out_uop.flush_on_commit
connect issue_slots[17].out_uop.is_unique, slots_17.io.out_uop.is_unique
connect issue_slots[17].out_uop.is_sys_pc2epc, slots_17.io.out_uop.is_sys_pc2epc
connect issue_slots[17].out_uop.uses_stq, slots_17.io.out_uop.uses_stq
connect issue_slots[17].out_uop.uses_ldq, slots_17.io.out_uop.uses_ldq
connect issue_slots[17].out_uop.is_amo, slots_17.io.out_uop.is_amo
connect issue_slots[17].out_uop.is_fencei, slots_17.io.out_uop.is_fencei
connect issue_slots[17].out_uop.is_fence, slots_17.io.out_uop.is_fence
connect issue_slots[17].out_uop.mem_signed, slots_17.io.out_uop.mem_signed
connect issue_slots[17].out_uop.mem_size, slots_17.io.out_uop.mem_size
connect issue_slots[17].out_uop.mem_cmd, slots_17.io.out_uop.mem_cmd
connect issue_slots[17].out_uop.bypassable, slots_17.io.out_uop.bypassable
connect issue_slots[17].out_uop.exc_cause, slots_17.io.out_uop.exc_cause
connect issue_slots[17].out_uop.exception, slots_17.io.out_uop.exception
connect issue_slots[17].out_uop.stale_pdst, slots_17.io.out_uop.stale_pdst
connect issue_slots[17].out_uop.ppred_busy, slots_17.io.out_uop.ppred_busy
connect issue_slots[17].out_uop.prs3_busy, slots_17.io.out_uop.prs3_busy
connect issue_slots[17].out_uop.prs2_busy, slots_17.io.out_uop.prs2_busy
connect issue_slots[17].out_uop.prs1_busy, slots_17.io.out_uop.prs1_busy
connect issue_slots[17].out_uop.ppred, slots_17.io.out_uop.ppred
connect issue_slots[17].out_uop.prs3, slots_17.io.out_uop.prs3
connect issue_slots[17].out_uop.prs2, slots_17.io.out_uop.prs2
connect issue_slots[17].out_uop.prs1, slots_17.io.out_uop.prs1
connect issue_slots[17].out_uop.pdst, slots_17.io.out_uop.pdst
connect issue_slots[17].out_uop.rxq_idx, slots_17.io.out_uop.rxq_idx
connect issue_slots[17].out_uop.stq_idx, slots_17.io.out_uop.stq_idx
connect issue_slots[17].out_uop.ldq_idx, slots_17.io.out_uop.ldq_idx
connect issue_slots[17].out_uop.rob_idx, slots_17.io.out_uop.rob_idx
connect issue_slots[17].out_uop.csr_addr, slots_17.io.out_uop.csr_addr
connect issue_slots[17].out_uop.imm_packed, slots_17.io.out_uop.imm_packed
connect issue_slots[17].out_uop.taken, slots_17.io.out_uop.taken
connect issue_slots[17].out_uop.pc_lob, slots_17.io.out_uop.pc_lob
connect issue_slots[17].out_uop.edge_inst, slots_17.io.out_uop.edge_inst
connect issue_slots[17].out_uop.ftq_idx, slots_17.io.out_uop.ftq_idx
connect issue_slots[17].out_uop.br_tag, slots_17.io.out_uop.br_tag
connect issue_slots[17].out_uop.br_mask, slots_17.io.out_uop.br_mask
connect issue_slots[17].out_uop.is_sfb, slots_17.io.out_uop.is_sfb
connect issue_slots[17].out_uop.is_jal, slots_17.io.out_uop.is_jal
connect issue_slots[17].out_uop.is_jalr, slots_17.io.out_uop.is_jalr
connect issue_slots[17].out_uop.is_br, slots_17.io.out_uop.is_br
connect issue_slots[17].out_uop.iw_p2_poisoned, slots_17.io.out_uop.iw_p2_poisoned
connect issue_slots[17].out_uop.iw_p1_poisoned, slots_17.io.out_uop.iw_p1_poisoned
connect issue_slots[17].out_uop.iw_state, slots_17.io.out_uop.iw_state
connect issue_slots[17].out_uop.ctrl.is_std, slots_17.io.out_uop.ctrl.is_std
connect issue_slots[17].out_uop.ctrl.is_sta, slots_17.io.out_uop.ctrl.is_sta
connect issue_slots[17].out_uop.ctrl.is_load, slots_17.io.out_uop.ctrl.is_load
connect issue_slots[17].out_uop.ctrl.csr_cmd, slots_17.io.out_uop.ctrl.csr_cmd
connect issue_slots[17].out_uop.ctrl.fcn_dw, slots_17.io.out_uop.ctrl.fcn_dw
connect issue_slots[17].out_uop.ctrl.op_fcn, slots_17.io.out_uop.ctrl.op_fcn
connect issue_slots[17].out_uop.ctrl.imm_sel, slots_17.io.out_uop.ctrl.imm_sel
connect issue_slots[17].out_uop.ctrl.op2_sel, slots_17.io.out_uop.ctrl.op2_sel
connect issue_slots[17].out_uop.ctrl.op1_sel, slots_17.io.out_uop.ctrl.op1_sel
connect issue_slots[17].out_uop.ctrl.br_type, slots_17.io.out_uop.ctrl.br_type
connect issue_slots[17].out_uop.fu_code, slots_17.io.out_uop.fu_code
connect issue_slots[17].out_uop.iq_type, slots_17.io.out_uop.iq_type
connect issue_slots[17].out_uop.debug_pc, slots_17.io.out_uop.debug_pc
connect issue_slots[17].out_uop.is_rvc, slots_17.io.out_uop.is_rvc
connect issue_slots[17].out_uop.debug_inst, slots_17.io.out_uop.debug_inst
connect issue_slots[17].out_uop.inst, slots_17.io.out_uop.inst
connect issue_slots[17].out_uop.uopc, slots_17.io.out_uop.uopc
connect slots_17.io.in_uop.bits.debug_tsrc, issue_slots[17].in_uop.bits.debug_tsrc
connect slots_17.io.in_uop.bits.debug_fsrc, issue_slots[17].in_uop.bits.debug_fsrc
connect slots_17.io.in_uop.bits.bp_xcpt_if, issue_slots[17].in_uop.bits.bp_xcpt_if
connect slots_17.io.in_uop.bits.bp_debug_if, issue_slots[17].in_uop.bits.bp_debug_if
connect slots_17.io.in_uop.bits.xcpt_ma_if, issue_slots[17].in_uop.bits.xcpt_ma_if
connect slots_17.io.in_uop.bits.xcpt_ae_if, issue_slots[17].in_uop.bits.xcpt_ae_if
connect slots_17.io.in_uop.bits.xcpt_pf_if, issue_slots[17].in_uop.bits.xcpt_pf_if
connect slots_17.io.in_uop.bits.fp_single, issue_slots[17].in_uop.bits.fp_single
connect slots_17.io.in_uop.bits.fp_val, issue_slots[17].in_uop.bits.fp_val
connect slots_17.io.in_uop.bits.frs3_en, issue_slots[17].in_uop.bits.frs3_en
connect slots_17.io.in_uop.bits.lrs2_rtype, issue_slots[17].in_uop.bits.lrs2_rtype
connect slots_17.io.in_uop.bits.lrs1_rtype, issue_slots[17].in_uop.bits.lrs1_rtype
connect slots_17.io.in_uop.bits.dst_rtype, issue_slots[17].in_uop.bits.dst_rtype
connect slots_17.io.in_uop.bits.ldst_val, issue_slots[17].in_uop.bits.ldst_val
connect slots_17.io.in_uop.bits.lrs3, issue_slots[17].in_uop.bits.lrs3
connect slots_17.io.in_uop.bits.lrs2, issue_slots[17].in_uop.bits.lrs2
connect slots_17.io.in_uop.bits.lrs1, issue_slots[17].in_uop.bits.lrs1
connect slots_17.io.in_uop.bits.ldst, issue_slots[17].in_uop.bits.ldst
connect slots_17.io.in_uop.bits.ldst_is_rs1, issue_slots[17].in_uop.bits.ldst_is_rs1
connect slots_17.io.in_uop.bits.flush_on_commit, issue_slots[17].in_uop.bits.flush_on_commit
connect slots_17.io.in_uop.bits.is_unique, issue_slots[17].in_uop.bits.is_unique
connect slots_17.io.in_uop.bits.is_sys_pc2epc, issue_slots[17].in_uop.bits.is_sys_pc2epc
connect slots_17.io.in_uop.bits.uses_stq, issue_slots[17].in_uop.bits.uses_stq
connect slots_17.io.in_uop.bits.uses_ldq, issue_slots[17].in_uop.bits.uses_ldq
connect slots_17.io.in_uop.bits.is_amo, issue_slots[17].in_uop.bits.is_amo
connect slots_17.io.in_uop.bits.is_fencei, issue_slots[17].in_uop.bits.is_fencei
connect slots_17.io.in_uop.bits.is_fence, issue_slots[17].in_uop.bits.is_fence
connect slots_17.io.in_uop.bits.mem_signed, issue_slots[17].in_uop.bits.mem_signed
connect slots_17.io.in_uop.bits.mem_size, issue_slots[17].in_uop.bits.mem_size
connect slots_17.io.in_uop.bits.mem_cmd, issue_slots[17].in_uop.bits.mem_cmd
connect slots_17.io.in_uop.bits.bypassable, issue_slots[17].in_uop.bits.bypassable
connect slots_17.io.in_uop.bits.exc_cause, issue_slots[17].in_uop.bits.exc_cause
connect slots_17.io.in_uop.bits.exception, issue_slots[17].in_uop.bits.exception
connect slots_17.io.in_uop.bits.stale_pdst, issue_slots[17].in_uop.bits.stale_pdst
connect slots_17.io.in_uop.bits.ppred_busy, issue_slots[17].in_uop.bits.ppred_busy
connect slots_17.io.in_uop.bits.prs3_busy, issue_slots[17].in_uop.bits.prs3_busy
connect slots_17.io.in_uop.bits.prs2_busy, issue_slots[17].in_uop.bits.prs2_busy
connect slots_17.io.in_uop.bits.prs1_busy, issue_slots[17].in_uop.bits.prs1_busy
connect slots_17.io.in_uop.bits.ppred, issue_slots[17].in_uop.bits.ppred
connect slots_17.io.in_uop.bits.prs3, issue_slots[17].in_uop.bits.prs3
connect slots_17.io.in_uop.bits.prs2, issue_slots[17].in_uop.bits.prs2
connect slots_17.io.in_uop.bits.prs1, issue_slots[17].in_uop.bits.prs1
connect slots_17.io.in_uop.bits.pdst, issue_slots[17].in_uop.bits.pdst
connect slots_17.io.in_uop.bits.rxq_idx, issue_slots[17].in_uop.bits.rxq_idx
connect slots_17.io.in_uop.bits.stq_idx, issue_slots[17].in_uop.bits.stq_idx
connect slots_17.io.in_uop.bits.ldq_idx, issue_slots[17].in_uop.bits.ldq_idx
connect slots_17.io.in_uop.bits.rob_idx, issue_slots[17].in_uop.bits.rob_idx
connect slots_17.io.in_uop.bits.csr_addr, issue_slots[17].in_uop.bits.csr_addr
connect slots_17.io.in_uop.bits.imm_packed, issue_slots[17].in_uop.bits.imm_packed
connect slots_17.io.in_uop.bits.taken, issue_slots[17].in_uop.bits.taken
connect slots_17.io.in_uop.bits.pc_lob, issue_slots[17].in_uop.bits.pc_lob
connect slots_17.io.in_uop.bits.edge_inst, issue_slots[17].in_uop.bits.edge_inst
connect slots_17.io.in_uop.bits.ftq_idx, issue_slots[17].in_uop.bits.ftq_idx
connect slots_17.io.in_uop.bits.br_tag, issue_slots[17].in_uop.bits.br_tag
connect slots_17.io.in_uop.bits.br_mask, issue_slots[17].in_uop.bits.br_mask
connect slots_17.io.in_uop.bits.is_sfb, issue_slots[17].in_uop.bits.is_sfb
connect slots_17.io.in_uop.bits.is_jal, issue_slots[17].in_uop.bits.is_jal
connect slots_17.io.in_uop.bits.is_jalr, issue_slots[17].in_uop.bits.is_jalr
connect slots_17.io.in_uop.bits.is_br, issue_slots[17].in_uop.bits.is_br
connect slots_17.io.in_uop.bits.iw_p2_poisoned, issue_slots[17].in_uop.bits.iw_p2_poisoned
connect slots_17.io.in_uop.bits.iw_p1_poisoned, issue_slots[17].in_uop.bits.iw_p1_poisoned
connect slots_17.io.in_uop.bits.iw_state, issue_slots[17].in_uop.bits.iw_state
connect slots_17.io.in_uop.bits.ctrl.is_std, issue_slots[17].in_uop.bits.ctrl.is_std
connect slots_17.io.in_uop.bits.ctrl.is_sta, issue_slots[17].in_uop.bits.ctrl.is_sta
connect slots_17.io.in_uop.bits.ctrl.is_load, issue_slots[17].in_uop.bits.ctrl.is_load
connect slots_17.io.in_uop.bits.ctrl.csr_cmd, issue_slots[17].in_uop.bits.ctrl.csr_cmd
connect slots_17.io.in_uop.bits.ctrl.fcn_dw, issue_slots[17].in_uop.bits.ctrl.fcn_dw
connect slots_17.io.in_uop.bits.ctrl.op_fcn, issue_slots[17].in_uop.bits.ctrl.op_fcn
connect slots_17.io.in_uop.bits.ctrl.imm_sel, issue_slots[17].in_uop.bits.ctrl.imm_sel
connect slots_17.io.in_uop.bits.ctrl.op2_sel, issue_slots[17].in_uop.bits.ctrl.op2_sel
connect slots_17.io.in_uop.bits.ctrl.op1_sel, issue_slots[17].in_uop.bits.ctrl.op1_sel
connect slots_17.io.in_uop.bits.ctrl.br_type, issue_slots[17].in_uop.bits.ctrl.br_type
connect slots_17.io.in_uop.bits.fu_code, issue_slots[17].in_uop.bits.fu_code
connect slots_17.io.in_uop.bits.iq_type, issue_slots[17].in_uop.bits.iq_type
connect slots_17.io.in_uop.bits.debug_pc, issue_slots[17].in_uop.bits.debug_pc
connect slots_17.io.in_uop.bits.is_rvc, issue_slots[17].in_uop.bits.is_rvc
connect slots_17.io.in_uop.bits.debug_inst, issue_slots[17].in_uop.bits.debug_inst
connect slots_17.io.in_uop.bits.inst, issue_slots[17].in_uop.bits.inst
connect slots_17.io.in_uop.bits.uopc, issue_slots[17].in_uop.bits.uopc
connect slots_17.io.in_uop.valid, issue_slots[17].in_uop.valid
connect slots_17.io.spec_ld_wakeup[0].bits, issue_slots[17].spec_ld_wakeup[0].bits
connect slots_17.io.spec_ld_wakeup[0].valid, issue_slots[17].spec_ld_wakeup[0].valid
connect slots_17.io.pred_wakeup_port.bits, issue_slots[17].pred_wakeup_port.bits
connect slots_17.io.pred_wakeup_port.valid, issue_slots[17].pred_wakeup_port.valid
connect slots_17.io.wakeup_ports[0].bits.poisoned, issue_slots[17].wakeup_ports[0].bits.poisoned
connect slots_17.io.wakeup_ports[0].bits.pdst, issue_slots[17].wakeup_ports[0].bits.pdst
connect slots_17.io.wakeup_ports[0].valid, issue_slots[17].wakeup_ports[0].valid
connect slots_17.io.wakeup_ports[1].bits.poisoned, issue_slots[17].wakeup_ports[1].bits.poisoned
connect slots_17.io.wakeup_ports[1].bits.pdst, issue_slots[17].wakeup_ports[1].bits.pdst
connect slots_17.io.wakeup_ports[1].valid, issue_slots[17].wakeup_ports[1].valid
connect slots_17.io.ldspec_miss, issue_slots[17].ldspec_miss
connect slots_17.io.clear, issue_slots[17].clear
connect slots_17.io.kill, issue_slots[17].kill
connect slots_17.io.brupdate.b2.target_offset, issue_slots[17].brupdate.b2.target_offset
connect slots_17.io.brupdate.b2.jalr_target, issue_slots[17].brupdate.b2.jalr_target
connect slots_17.io.brupdate.b2.pc_sel, issue_slots[17].brupdate.b2.pc_sel
connect slots_17.io.brupdate.b2.cfi_type, issue_slots[17].brupdate.b2.cfi_type
connect slots_17.io.brupdate.b2.taken, issue_slots[17].brupdate.b2.taken
connect slots_17.io.brupdate.b2.mispredict, issue_slots[17].brupdate.b2.mispredict
connect slots_17.io.brupdate.b2.valid, issue_slots[17].brupdate.b2.valid
connect slots_17.io.brupdate.b2.uop.debug_tsrc, issue_slots[17].brupdate.b2.uop.debug_tsrc
connect slots_17.io.brupdate.b2.uop.debug_fsrc, issue_slots[17].brupdate.b2.uop.debug_fsrc
connect slots_17.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[17].brupdate.b2.uop.bp_xcpt_if
connect slots_17.io.brupdate.b2.uop.bp_debug_if, issue_slots[17].brupdate.b2.uop.bp_debug_if
connect slots_17.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[17].brupdate.b2.uop.xcpt_ma_if
connect slots_17.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[17].brupdate.b2.uop.xcpt_ae_if
connect slots_17.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[17].brupdate.b2.uop.xcpt_pf_if
connect slots_17.io.brupdate.b2.uop.fp_single, issue_slots[17].brupdate.b2.uop.fp_single
connect slots_17.io.brupdate.b2.uop.fp_val, issue_slots[17].brupdate.b2.uop.fp_val
connect slots_17.io.brupdate.b2.uop.frs3_en, issue_slots[17].brupdate.b2.uop.frs3_en
connect slots_17.io.brupdate.b2.uop.lrs2_rtype, issue_slots[17].brupdate.b2.uop.lrs2_rtype
connect slots_17.io.brupdate.b2.uop.lrs1_rtype, issue_slots[17].brupdate.b2.uop.lrs1_rtype
connect slots_17.io.brupdate.b2.uop.dst_rtype, issue_slots[17].brupdate.b2.uop.dst_rtype
connect slots_17.io.brupdate.b2.uop.ldst_val, issue_slots[17].brupdate.b2.uop.ldst_val
connect slots_17.io.brupdate.b2.uop.lrs3, issue_slots[17].brupdate.b2.uop.lrs3
connect slots_17.io.brupdate.b2.uop.lrs2, issue_slots[17].brupdate.b2.uop.lrs2
connect slots_17.io.brupdate.b2.uop.lrs1, issue_slots[17].brupdate.b2.uop.lrs1
connect slots_17.io.brupdate.b2.uop.ldst, issue_slots[17].brupdate.b2.uop.ldst
connect slots_17.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[17].brupdate.b2.uop.ldst_is_rs1
connect slots_17.io.brupdate.b2.uop.flush_on_commit, issue_slots[17].brupdate.b2.uop.flush_on_commit
connect slots_17.io.brupdate.b2.uop.is_unique, issue_slots[17].brupdate.b2.uop.is_unique
connect slots_17.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[17].brupdate.b2.uop.is_sys_pc2epc
connect slots_17.io.brupdate.b2.uop.uses_stq, issue_slots[17].brupdate.b2.uop.uses_stq
connect slots_17.io.brupdate.b2.uop.uses_ldq, issue_slots[17].brupdate.b2.uop.uses_ldq
connect slots_17.io.brupdate.b2.uop.is_amo, issue_slots[17].brupdate.b2.uop.is_amo
connect slots_17.io.brupdate.b2.uop.is_fencei, issue_slots[17].brupdate.b2.uop.is_fencei
connect slots_17.io.brupdate.b2.uop.is_fence, issue_slots[17].brupdate.b2.uop.is_fence
connect slots_17.io.brupdate.b2.uop.mem_signed, issue_slots[17].brupdate.b2.uop.mem_signed
connect slots_17.io.brupdate.b2.uop.mem_size, issue_slots[17].brupdate.b2.uop.mem_size
connect slots_17.io.brupdate.b2.uop.mem_cmd, issue_slots[17].brupdate.b2.uop.mem_cmd
connect slots_17.io.brupdate.b2.uop.bypassable, issue_slots[17].brupdate.b2.uop.bypassable
connect slots_17.io.brupdate.b2.uop.exc_cause, issue_slots[17].brupdate.b2.uop.exc_cause
connect slots_17.io.brupdate.b2.uop.exception, issue_slots[17].brupdate.b2.uop.exception
connect slots_17.io.brupdate.b2.uop.stale_pdst, issue_slots[17].brupdate.b2.uop.stale_pdst
connect slots_17.io.brupdate.b2.uop.ppred_busy, issue_slots[17].brupdate.b2.uop.ppred_busy
connect slots_17.io.brupdate.b2.uop.prs3_busy, issue_slots[17].brupdate.b2.uop.prs3_busy
connect slots_17.io.brupdate.b2.uop.prs2_busy, issue_slots[17].brupdate.b2.uop.prs2_busy
connect slots_17.io.brupdate.b2.uop.prs1_busy, issue_slots[17].brupdate.b2.uop.prs1_busy
connect slots_17.io.brupdate.b2.uop.ppred, issue_slots[17].brupdate.b2.uop.ppred
connect slots_17.io.brupdate.b2.uop.prs3, issue_slots[17].brupdate.b2.uop.prs3
connect slots_17.io.brupdate.b2.uop.prs2, issue_slots[17].brupdate.b2.uop.prs2
connect slots_17.io.brupdate.b2.uop.prs1, issue_slots[17].brupdate.b2.uop.prs1
connect slots_17.io.brupdate.b2.uop.pdst, issue_slots[17].brupdate.b2.uop.pdst
connect slots_17.io.brupdate.b2.uop.rxq_idx, issue_slots[17].brupdate.b2.uop.rxq_idx
connect slots_17.io.brupdate.b2.uop.stq_idx, issue_slots[17].brupdate.b2.uop.stq_idx
connect slots_17.io.brupdate.b2.uop.ldq_idx, issue_slots[17].brupdate.b2.uop.ldq_idx
connect slots_17.io.brupdate.b2.uop.rob_idx, issue_slots[17].brupdate.b2.uop.rob_idx
connect slots_17.io.brupdate.b2.uop.csr_addr, issue_slots[17].brupdate.b2.uop.csr_addr
connect slots_17.io.brupdate.b2.uop.imm_packed, issue_slots[17].brupdate.b2.uop.imm_packed
connect slots_17.io.brupdate.b2.uop.taken, issue_slots[17].brupdate.b2.uop.taken
connect slots_17.io.brupdate.b2.uop.pc_lob, issue_slots[17].brupdate.b2.uop.pc_lob
connect slots_17.io.brupdate.b2.uop.edge_inst, issue_slots[17].brupdate.b2.uop.edge_inst
connect slots_17.io.brupdate.b2.uop.ftq_idx, issue_slots[17].brupdate.b2.uop.ftq_idx
connect slots_17.io.brupdate.b2.uop.br_tag, issue_slots[17].brupdate.b2.uop.br_tag
connect slots_17.io.brupdate.b2.uop.br_mask, issue_slots[17].brupdate.b2.uop.br_mask
connect slots_17.io.brupdate.b2.uop.is_sfb, issue_slots[17].brupdate.b2.uop.is_sfb
connect slots_17.io.brupdate.b2.uop.is_jal, issue_slots[17].brupdate.b2.uop.is_jal
connect slots_17.io.brupdate.b2.uop.is_jalr, issue_slots[17].brupdate.b2.uop.is_jalr
connect slots_17.io.brupdate.b2.uop.is_br, issue_slots[17].brupdate.b2.uop.is_br
connect slots_17.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[17].brupdate.b2.uop.iw_p2_poisoned
connect slots_17.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[17].brupdate.b2.uop.iw_p1_poisoned
connect slots_17.io.brupdate.b2.uop.iw_state, issue_slots[17].brupdate.b2.uop.iw_state
connect slots_17.io.brupdate.b2.uop.ctrl.is_std, issue_slots[17].brupdate.b2.uop.ctrl.is_std
connect slots_17.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[17].brupdate.b2.uop.ctrl.is_sta
connect slots_17.io.brupdate.b2.uop.ctrl.is_load, issue_slots[17].brupdate.b2.uop.ctrl.is_load
connect slots_17.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[17].brupdate.b2.uop.ctrl.csr_cmd
connect slots_17.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[17].brupdate.b2.uop.ctrl.fcn_dw
connect slots_17.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[17].brupdate.b2.uop.ctrl.op_fcn
connect slots_17.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[17].brupdate.b2.uop.ctrl.imm_sel
connect slots_17.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[17].brupdate.b2.uop.ctrl.op2_sel
connect slots_17.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[17].brupdate.b2.uop.ctrl.op1_sel
connect slots_17.io.brupdate.b2.uop.ctrl.br_type, issue_slots[17].brupdate.b2.uop.ctrl.br_type
connect slots_17.io.brupdate.b2.uop.fu_code, issue_slots[17].brupdate.b2.uop.fu_code
connect slots_17.io.brupdate.b2.uop.iq_type, issue_slots[17].brupdate.b2.uop.iq_type
connect slots_17.io.brupdate.b2.uop.debug_pc, issue_slots[17].brupdate.b2.uop.debug_pc
connect slots_17.io.brupdate.b2.uop.is_rvc, issue_slots[17].brupdate.b2.uop.is_rvc
connect slots_17.io.brupdate.b2.uop.debug_inst, issue_slots[17].brupdate.b2.uop.debug_inst
connect slots_17.io.brupdate.b2.uop.inst, issue_slots[17].brupdate.b2.uop.inst
connect slots_17.io.brupdate.b2.uop.uopc, issue_slots[17].brupdate.b2.uop.uopc
connect slots_17.io.brupdate.b1.mispredict_mask, issue_slots[17].brupdate.b1.mispredict_mask
connect slots_17.io.brupdate.b1.resolve_mask, issue_slots[17].brupdate.b1.resolve_mask
connect slots_17.io.grant, issue_slots[17].grant
connect issue_slots[17].request_hp, slots_17.io.request_hp
connect issue_slots[17].request, slots_17.io.request
connect issue_slots[17].will_be_valid, slots_17.io.will_be_valid
connect issue_slots[17].valid, slots_17.io.valid
connect issue_slots[18].debug.state, slots_18.io.debug.state
connect issue_slots[18].debug.ppred, slots_18.io.debug.ppred
connect issue_slots[18].debug.p3, slots_18.io.debug.p3
connect issue_slots[18].debug.p2, slots_18.io.debug.p2
connect issue_slots[18].debug.p1, slots_18.io.debug.p1
connect issue_slots[18].uop.debug_tsrc, slots_18.io.uop.debug_tsrc
connect issue_slots[18].uop.debug_fsrc, slots_18.io.uop.debug_fsrc
connect issue_slots[18].uop.bp_xcpt_if, slots_18.io.uop.bp_xcpt_if
connect issue_slots[18].uop.bp_debug_if, slots_18.io.uop.bp_debug_if
connect issue_slots[18].uop.xcpt_ma_if, slots_18.io.uop.xcpt_ma_if
connect issue_slots[18].uop.xcpt_ae_if, slots_18.io.uop.xcpt_ae_if
connect issue_slots[18].uop.xcpt_pf_if, slots_18.io.uop.xcpt_pf_if
connect issue_slots[18].uop.fp_single, slots_18.io.uop.fp_single
connect issue_slots[18].uop.fp_val, slots_18.io.uop.fp_val
connect issue_slots[18].uop.frs3_en, slots_18.io.uop.frs3_en
connect issue_slots[18].uop.lrs2_rtype, slots_18.io.uop.lrs2_rtype
connect issue_slots[18].uop.lrs1_rtype, slots_18.io.uop.lrs1_rtype
connect issue_slots[18].uop.dst_rtype, slots_18.io.uop.dst_rtype
connect issue_slots[18].uop.ldst_val, slots_18.io.uop.ldst_val
connect issue_slots[18].uop.lrs3, slots_18.io.uop.lrs3
connect issue_slots[18].uop.lrs2, slots_18.io.uop.lrs2
connect issue_slots[18].uop.lrs1, slots_18.io.uop.lrs1
connect issue_slots[18].uop.ldst, slots_18.io.uop.ldst
connect issue_slots[18].uop.ldst_is_rs1, slots_18.io.uop.ldst_is_rs1
connect issue_slots[18].uop.flush_on_commit, slots_18.io.uop.flush_on_commit
connect issue_slots[18].uop.is_unique, slots_18.io.uop.is_unique
connect issue_slots[18].uop.is_sys_pc2epc, slots_18.io.uop.is_sys_pc2epc
connect issue_slots[18].uop.uses_stq, slots_18.io.uop.uses_stq
connect issue_slots[18].uop.uses_ldq, slots_18.io.uop.uses_ldq
connect issue_slots[18].uop.is_amo, slots_18.io.uop.is_amo
connect issue_slots[18].uop.is_fencei, slots_18.io.uop.is_fencei
connect issue_slots[18].uop.is_fence, slots_18.io.uop.is_fence
connect issue_slots[18].uop.mem_signed, slots_18.io.uop.mem_signed
connect issue_slots[18].uop.mem_size, slots_18.io.uop.mem_size
connect issue_slots[18].uop.mem_cmd, slots_18.io.uop.mem_cmd
connect issue_slots[18].uop.bypassable, slots_18.io.uop.bypassable
connect issue_slots[18].uop.exc_cause, slots_18.io.uop.exc_cause
connect issue_slots[18].uop.exception, slots_18.io.uop.exception
connect issue_slots[18].uop.stale_pdst, slots_18.io.uop.stale_pdst
connect issue_slots[18].uop.ppred_busy, slots_18.io.uop.ppred_busy
connect issue_slots[18].uop.prs3_busy, slots_18.io.uop.prs3_busy
connect issue_slots[18].uop.prs2_busy, slots_18.io.uop.prs2_busy
connect issue_slots[18].uop.prs1_busy, slots_18.io.uop.prs1_busy
connect issue_slots[18].uop.ppred, slots_18.io.uop.ppred
connect issue_slots[18].uop.prs3, slots_18.io.uop.prs3
connect issue_slots[18].uop.prs2, slots_18.io.uop.prs2
connect issue_slots[18].uop.prs1, slots_18.io.uop.prs1
connect issue_slots[18].uop.pdst, slots_18.io.uop.pdst
connect issue_slots[18].uop.rxq_idx, slots_18.io.uop.rxq_idx
connect issue_slots[18].uop.stq_idx, slots_18.io.uop.stq_idx
connect issue_slots[18].uop.ldq_idx, slots_18.io.uop.ldq_idx
connect issue_slots[18].uop.rob_idx, slots_18.io.uop.rob_idx
connect issue_slots[18].uop.csr_addr, slots_18.io.uop.csr_addr
connect issue_slots[18].uop.imm_packed, slots_18.io.uop.imm_packed
connect issue_slots[18].uop.taken, slots_18.io.uop.taken
connect issue_slots[18].uop.pc_lob, slots_18.io.uop.pc_lob
connect issue_slots[18].uop.edge_inst, slots_18.io.uop.edge_inst
connect issue_slots[18].uop.ftq_idx, slots_18.io.uop.ftq_idx
connect issue_slots[18].uop.br_tag, slots_18.io.uop.br_tag
connect issue_slots[18].uop.br_mask, slots_18.io.uop.br_mask
connect issue_slots[18].uop.is_sfb, slots_18.io.uop.is_sfb
connect issue_slots[18].uop.is_jal, slots_18.io.uop.is_jal
connect issue_slots[18].uop.is_jalr, slots_18.io.uop.is_jalr
connect issue_slots[18].uop.is_br, slots_18.io.uop.is_br
connect issue_slots[18].uop.iw_p2_poisoned, slots_18.io.uop.iw_p2_poisoned
connect issue_slots[18].uop.iw_p1_poisoned, slots_18.io.uop.iw_p1_poisoned
connect issue_slots[18].uop.iw_state, slots_18.io.uop.iw_state
connect issue_slots[18].uop.ctrl.is_std, slots_18.io.uop.ctrl.is_std
connect issue_slots[18].uop.ctrl.is_sta, slots_18.io.uop.ctrl.is_sta
connect issue_slots[18].uop.ctrl.is_load, slots_18.io.uop.ctrl.is_load
connect issue_slots[18].uop.ctrl.csr_cmd, slots_18.io.uop.ctrl.csr_cmd
connect issue_slots[18].uop.ctrl.fcn_dw, slots_18.io.uop.ctrl.fcn_dw
connect issue_slots[18].uop.ctrl.op_fcn, slots_18.io.uop.ctrl.op_fcn
connect issue_slots[18].uop.ctrl.imm_sel, slots_18.io.uop.ctrl.imm_sel
connect issue_slots[18].uop.ctrl.op2_sel, slots_18.io.uop.ctrl.op2_sel
connect issue_slots[18].uop.ctrl.op1_sel, slots_18.io.uop.ctrl.op1_sel
connect issue_slots[18].uop.ctrl.br_type, slots_18.io.uop.ctrl.br_type
connect issue_slots[18].uop.fu_code, slots_18.io.uop.fu_code
connect issue_slots[18].uop.iq_type, slots_18.io.uop.iq_type
connect issue_slots[18].uop.debug_pc, slots_18.io.uop.debug_pc
connect issue_slots[18].uop.is_rvc, slots_18.io.uop.is_rvc
connect issue_slots[18].uop.debug_inst, slots_18.io.uop.debug_inst
connect issue_slots[18].uop.inst, slots_18.io.uop.inst
connect issue_slots[18].uop.uopc, slots_18.io.uop.uopc
connect issue_slots[18].out_uop.debug_tsrc, slots_18.io.out_uop.debug_tsrc
connect issue_slots[18].out_uop.debug_fsrc, slots_18.io.out_uop.debug_fsrc
connect issue_slots[18].out_uop.bp_xcpt_if, slots_18.io.out_uop.bp_xcpt_if
connect issue_slots[18].out_uop.bp_debug_if, slots_18.io.out_uop.bp_debug_if
connect issue_slots[18].out_uop.xcpt_ma_if, slots_18.io.out_uop.xcpt_ma_if
connect issue_slots[18].out_uop.xcpt_ae_if, slots_18.io.out_uop.xcpt_ae_if
connect issue_slots[18].out_uop.xcpt_pf_if, slots_18.io.out_uop.xcpt_pf_if
connect issue_slots[18].out_uop.fp_single, slots_18.io.out_uop.fp_single
connect issue_slots[18].out_uop.fp_val, slots_18.io.out_uop.fp_val
connect issue_slots[18].out_uop.frs3_en, slots_18.io.out_uop.frs3_en
connect issue_slots[18].out_uop.lrs2_rtype, slots_18.io.out_uop.lrs2_rtype
connect issue_slots[18].out_uop.lrs1_rtype, slots_18.io.out_uop.lrs1_rtype
connect issue_slots[18].out_uop.dst_rtype, slots_18.io.out_uop.dst_rtype
connect issue_slots[18].out_uop.ldst_val, slots_18.io.out_uop.ldst_val
connect issue_slots[18].out_uop.lrs3, slots_18.io.out_uop.lrs3
connect issue_slots[18].out_uop.lrs2, slots_18.io.out_uop.lrs2
connect issue_slots[18].out_uop.lrs1, slots_18.io.out_uop.lrs1
connect issue_slots[18].out_uop.ldst, slots_18.io.out_uop.ldst
connect issue_slots[18].out_uop.ldst_is_rs1, slots_18.io.out_uop.ldst_is_rs1
connect issue_slots[18].out_uop.flush_on_commit, slots_18.io.out_uop.flush_on_commit
connect issue_slots[18].out_uop.is_unique, slots_18.io.out_uop.is_unique
connect issue_slots[18].out_uop.is_sys_pc2epc, slots_18.io.out_uop.is_sys_pc2epc
connect issue_slots[18].out_uop.uses_stq, slots_18.io.out_uop.uses_stq
connect issue_slots[18].out_uop.uses_ldq, slots_18.io.out_uop.uses_ldq
connect issue_slots[18].out_uop.is_amo, slots_18.io.out_uop.is_amo
connect issue_slots[18].out_uop.is_fencei, slots_18.io.out_uop.is_fencei
connect issue_slots[18].out_uop.is_fence, slots_18.io.out_uop.is_fence
connect issue_slots[18].out_uop.mem_signed, slots_18.io.out_uop.mem_signed
connect issue_slots[18].out_uop.mem_size, slots_18.io.out_uop.mem_size
connect issue_slots[18].out_uop.mem_cmd, slots_18.io.out_uop.mem_cmd
connect issue_slots[18].out_uop.bypassable, slots_18.io.out_uop.bypassable
connect issue_slots[18].out_uop.exc_cause, slots_18.io.out_uop.exc_cause
connect issue_slots[18].out_uop.exception, slots_18.io.out_uop.exception
connect issue_slots[18].out_uop.stale_pdst, slots_18.io.out_uop.stale_pdst
connect issue_slots[18].out_uop.ppred_busy, slots_18.io.out_uop.ppred_busy
connect issue_slots[18].out_uop.prs3_busy, slots_18.io.out_uop.prs3_busy
connect issue_slots[18].out_uop.prs2_busy, slots_18.io.out_uop.prs2_busy
connect issue_slots[18].out_uop.prs1_busy, slots_18.io.out_uop.prs1_busy
connect issue_slots[18].out_uop.ppred, slots_18.io.out_uop.ppred
connect issue_slots[18].out_uop.prs3, slots_18.io.out_uop.prs3
connect issue_slots[18].out_uop.prs2, slots_18.io.out_uop.prs2
connect issue_slots[18].out_uop.prs1, slots_18.io.out_uop.prs1
connect issue_slots[18].out_uop.pdst, slots_18.io.out_uop.pdst
connect issue_slots[18].out_uop.rxq_idx, slots_18.io.out_uop.rxq_idx
connect issue_slots[18].out_uop.stq_idx, slots_18.io.out_uop.stq_idx
connect issue_slots[18].out_uop.ldq_idx, slots_18.io.out_uop.ldq_idx
connect issue_slots[18].out_uop.rob_idx, slots_18.io.out_uop.rob_idx
connect issue_slots[18].out_uop.csr_addr, slots_18.io.out_uop.csr_addr
connect issue_slots[18].out_uop.imm_packed, slots_18.io.out_uop.imm_packed
connect issue_slots[18].out_uop.taken, slots_18.io.out_uop.taken
connect issue_slots[18].out_uop.pc_lob, slots_18.io.out_uop.pc_lob
connect issue_slots[18].out_uop.edge_inst, slots_18.io.out_uop.edge_inst
connect issue_slots[18].out_uop.ftq_idx, slots_18.io.out_uop.ftq_idx
connect issue_slots[18].out_uop.br_tag, slots_18.io.out_uop.br_tag
connect issue_slots[18].out_uop.br_mask, slots_18.io.out_uop.br_mask
connect issue_slots[18].out_uop.is_sfb, slots_18.io.out_uop.is_sfb
connect issue_slots[18].out_uop.is_jal, slots_18.io.out_uop.is_jal
connect issue_slots[18].out_uop.is_jalr, slots_18.io.out_uop.is_jalr
connect issue_slots[18].out_uop.is_br, slots_18.io.out_uop.is_br
connect issue_slots[18].out_uop.iw_p2_poisoned, slots_18.io.out_uop.iw_p2_poisoned
connect issue_slots[18].out_uop.iw_p1_poisoned, slots_18.io.out_uop.iw_p1_poisoned
connect issue_slots[18].out_uop.iw_state, slots_18.io.out_uop.iw_state
connect issue_slots[18].out_uop.ctrl.is_std, slots_18.io.out_uop.ctrl.is_std
connect issue_slots[18].out_uop.ctrl.is_sta, slots_18.io.out_uop.ctrl.is_sta
connect issue_slots[18].out_uop.ctrl.is_load, slots_18.io.out_uop.ctrl.is_load
connect issue_slots[18].out_uop.ctrl.csr_cmd, slots_18.io.out_uop.ctrl.csr_cmd
connect issue_slots[18].out_uop.ctrl.fcn_dw, slots_18.io.out_uop.ctrl.fcn_dw
connect issue_slots[18].out_uop.ctrl.op_fcn, slots_18.io.out_uop.ctrl.op_fcn
connect issue_slots[18].out_uop.ctrl.imm_sel, slots_18.io.out_uop.ctrl.imm_sel
connect issue_slots[18].out_uop.ctrl.op2_sel, slots_18.io.out_uop.ctrl.op2_sel
connect issue_slots[18].out_uop.ctrl.op1_sel, slots_18.io.out_uop.ctrl.op1_sel
connect issue_slots[18].out_uop.ctrl.br_type, slots_18.io.out_uop.ctrl.br_type
connect issue_slots[18].out_uop.fu_code, slots_18.io.out_uop.fu_code
connect issue_slots[18].out_uop.iq_type, slots_18.io.out_uop.iq_type
connect issue_slots[18].out_uop.debug_pc, slots_18.io.out_uop.debug_pc
connect issue_slots[18].out_uop.is_rvc, slots_18.io.out_uop.is_rvc
connect issue_slots[18].out_uop.debug_inst, slots_18.io.out_uop.debug_inst
connect issue_slots[18].out_uop.inst, slots_18.io.out_uop.inst
connect issue_slots[18].out_uop.uopc, slots_18.io.out_uop.uopc
connect slots_18.io.in_uop.bits.debug_tsrc, issue_slots[18].in_uop.bits.debug_tsrc
connect slots_18.io.in_uop.bits.debug_fsrc, issue_slots[18].in_uop.bits.debug_fsrc
connect slots_18.io.in_uop.bits.bp_xcpt_if, issue_slots[18].in_uop.bits.bp_xcpt_if
connect slots_18.io.in_uop.bits.bp_debug_if, issue_slots[18].in_uop.bits.bp_debug_if
connect slots_18.io.in_uop.bits.xcpt_ma_if, issue_slots[18].in_uop.bits.xcpt_ma_if
connect slots_18.io.in_uop.bits.xcpt_ae_if, issue_slots[18].in_uop.bits.xcpt_ae_if
connect slots_18.io.in_uop.bits.xcpt_pf_if, issue_slots[18].in_uop.bits.xcpt_pf_if
connect slots_18.io.in_uop.bits.fp_single, issue_slots[18].in_uop.bits.fp_single
connect slots_18.io.in_uop.bits.fp_val, issue_slots[18].in_uop.bits.fp_val
connect slots_18.io.in_uop.bits.frs3_en, issue_slots[18].in_uop.bits.frs3_en
connect slots_18.io.in_uop.bits.lrs2_rtype, issue_slots[18].in_uop.bits.lrs2_rtype
connect slots_18.io.in_uop.bits.lrs1_rtype, issue_slots[18].in_uop.bits.lrs1_rtype
connect slots_18.io.in_uop.bits.dst_rtype, issue_slots[18].in_uop.bits.dst_rtype
connect slots_18.io.in_uop.bits.ldst_val, issue_slots[18].in_uop.bits.ldst_val
connect slots_18.io.in_uop.bits.lrs3, issue_slots[18].in_uop.bits.lrs3
connect slots_18.io.in_uop.bits.lrs2, issue_slots[18].in_uop.bits.lrs2
connect slots_18.io.in_uop.bits.lrs1, issue_slots[18].in_uop.bits.lrs1
connect slots_18.io.in_uop.bits.ldst, issue_slots[18].in_uop.bits.ldst
connect slots_18.io.in_uop.bits.ldst_is_rs1, issue_slots[18].in_uop.bits.ldst_is_rs1
connect slots_18.io.in_uop.bits.flush_on_commit, issue_slots[18].in_uop.bits.flush_on_commit
connect slots_18.io.in_uop.bits.is_unique, issue_slots[18].in_uop.bits.is_unique
connect slots_18.io.in_uop.bits.is_sys_pc2epc, issue_slots[18].in_uop.bits.is_sys_pc2epc
connect slots_18.io.in_uop.bits.uses_stq, issue_slots[18].in_uop.bits.uses_stq
connect slots_18.io.in_uop.bits.uses_ldq, issue_slots[18].in_uop.bits.uses_ldq
connect slots_18.io.in_uop.bits.is_amo, issue_slots[18].in_uop.bits.is_amo
connect slots_18.io.in_uop.bits.is_fencei, issue_slots[18].in_uop.bits.is_fencei
connect slots_18.io.in_uop.bits.is_fence, issue_slots[18].in_uop.bits.is_fence
connect slots_18.io.in_uop.bits.mem_signed, issue_slots[18].in_uop.bits.mem_signed
connect slots_18.io.in_uop.bits.mem_size, issue_slots[18].in_uop.bits.mem_size
connect slots_18.io.in_uop.bits.mem_cmd, issue_slots[18].in_uop.bits.mem_cmd
connect slots_18.io.in_uop.bits.bypassable, issue_slots[18].in_uop.bits.bypassable
connect slots_18.io.in_uop.bits.exc_cause, issue_slots[18].in_uop.bits.exc_cause
connect slots_18.io.in_uop.bits.exception, issue_slots[18].in_uop.bits.exception
connect slots_18.io.in_uop.bits.stale_pdst, issue_slots[18].in_uop.bits.stale_pdst
connect slots_18.io.in_uop.bits.ppred_busy, issue_slots[18].in_uop.bits.ppred_busy
connect slots_18.io.in_uop.bits.prs3_busy, issue_slots[18].in_uop.bits.prs3_busy
connect slots_18.io.in_uop.bits.prs2_busy, issue_slots[18].in_uop.bits.prs2_busy
connect slots_18.io.in_uop.bits.prs1_busy, issue_slots[18].in_uop.bits.prs1_busy
connect slots_18.io.in_uop.bits.ppred, issue_slots[18].in_uop.bits.ppred
connect slots_18.io.in_uop.bits.prs3, issue_slots[18].in_uop.bits.prs3
connect slots_18.io.in_uop.bits.prs2, issue_slots[18].in_uop.bits.prs2
connect slots_18.io.in_uop.bits.prs1, issue_slots[18].in_uop.bits.prs1
connect slots_18.io.in_uop.bits.pdst, issue_slots[18].in_uop.bits.pdst
connect slots_18.io.in_uop.bits.rxq_idx, issue_slots[18].in_uop.bits.rxq_idx
connect slots_18.io.in_uop.bits.stq_idx, issue_slots[18].in_uop.bits.stq_idx
connect slots_18.io.in_uop.bits.ldq_idx, issue_slots[18].in_uop.bits.ldq_idx
connect slots_18.io.in_uop.bits.rob_idx, issue_slots[18].in_uop.bits.rob_idx
connect slots_18.io.in_uop.bits.csr_addr, issue_slots[18].in_uop.bits.csr_addr
connect slots_18.io.in_uop.bits.imm_packed, issue_slots[18].in_uop.bits.imm_packed
connect slots_18.io.in_uop.bits.taken, issue_slots[18].in_uop.bits.taken
connect slots_18.io.in_uop.bits.pc_lob, issue_slots[18].in_uop.bits.pc_lob
connect slots_18.io.in_uop.bits.edge_inst, issue_slots[18].in_uop.bits.edge_inst
connect slots_18.io.in_uop.bits.ftq_idx, issue_slots[18].in_uop.bits.ftq_idx
connect slots_18.io.in_uop.bits.br_tag, issue_slots[18].in_uop.bits.br_tag
connect slots_18.io.in_uop.bits.br_mask, issue_slots[18].in_uop.bits.br_mask
connect slots_18.io.in_uop.bits.is_sfb, issue_slots[18].in_uop.bits.is_sfb
connect slots_18.io.in_uop.bits.is_jal, issue_slots[18].in_uop.bits.is_jal
connect slots_18.io.in_uop.bits.is_jalr, issue_slots[18].in_uop.bits.is_jalr
connect slots_18.io.in_uop.bits.is_br, issue_slots[18].in_uop.bits.is_br
connect slots_18.io.in_uop.bits.iw_p2_poisoned, issue_slots[18].in_uop.bits.iw_p2_poisoned
connect slots_18.io.in_uop.bits.iw_p1_poisoned, issue_slots[18].in_uop.bits.iw_p1_poisoned
connect slots_18.io.in_uop.bits.iw_state, issue_slots[18].in_uop.bits.iw_state
connect slots_18.io.in_uop.bits.ctrl.is_std, issue_slots[18].in_uop.bits.ctrl.is_std
connect slots_18.io.in_uop.bits.ctrl.is_sta, issue_slots[18].in_uop.bits.ctrl.is_sta
connect slots_18.io.in_uop.bits.ctrl.is_load, issue_slots[18].in_uop.bits.ctrl.is_load
connect slots_18.io.in_uop.bits.ctrl.csr_cmd, issue_slots[18].in_uop.bits.ctrl.csr_cmd
connect slots_18.io.in_uop.bits.ctrl.fcn_dw, issue_slots[18].in_uop.bits.ctrl.fcn_dw
connect slots_18.io.in_uop.bits.ctrl.op_fcn, issue_slots[18].in_uop.bits.ctrl.op_fcn
connect slots_18.io.in_uop.bits.ctrl.imm_sel, issue_slots[18].in_uop.bits.ctrl.imm_sel
connect slots_18.io.in_uop.bits.ctrl.op2_sel, issue_slots[18].in_uop.bits.ctrl.op2_sel
connect slots_18.io.in_uop.bits.ctrl.op1_sel, issue_slots[18].in_uop.bits.ctrl.op1_sel
connect slots_18.io.in_uop.bits.ctrl.br_type, issue_slots[18].in_uop.bits.ctrl.br_type
connect slots_18.io.in_uop.bits.fu_code, issue_slots[18].in_uop.bits.fu_code
connect slots_18.io.in_uop.bits.iq_type, issue_slots[18].in_uop.bits.iq_type
connect slots_18.io.in_uop.bits.debug_pc, issue_slots[18].in_uop.bits.debug_pc
connect slots_18.io.in_uop.bits.is_rvc, issue_slots[18].in_uop.bits.is_rvc
connect slots_18.io.in_uop.bits.debug_inst, issue_slots[18].in_uop.bits.debug_inst
connect slots_18.io.in_uop.bits.inst, issue_slots[18].in_uop.bits.inst
connect slots_18.io.in_uop.bits.uopc, issue_slots[18].in_uop.bits.uopc
connect slots_18.io.in_uop.valid, issue_slots[18].in_uop.valid
connect slots_18.io.spec_ld_wakeup[0].bits, issue_slots[18].spec_ld_wakeup[0].bits
connect slots_18.io.spec_ld_wakeup[0].valid, issue_slots[18].spec_ld_wakeup[0].valid
connect slots_18.io.pred_wakeup_port.bits, issue_slots[18].pred_wakeup_port.bits
connect slots_18.io.pred_wakeup_port.valid, issue_slots[18].pred_wakeup_port.valid
connect slots_18.io.wakeup_ports[0].bits.poisoned, issue_slots[18].wakeup_ports[0].bits.poisoned
connect slots_18.io.wakeup_ports[0].bits.pdst, issue_slots[18].wakeup_ports[0].bits.pdst
connect slots_18.io.wakeup_ports[0].valid, issue_slots[18].wakeup_ports[0].valid
connect slots_18.io.wakeup_ports[1].bits.poisoned, issue_slots[18].wakeup_ports[1].bits.poisoned
connect slots_18.io.wakeup_ports[1].bits.pdst, issue_slots[18].wakeup_ports[1].bits.pdst
connect slots_18.io.wakeup_ports[1].valid, issue_slots[18].wakeup_ports[1].valid
connect slots_18.io.ldspec_miss, issue_slots[18].ldspec_miss
connect slots_18.io.clear, issue_slots[18].clear
connect slots_18.io.kill, issue_slots[18].kill
connect slots_18.io.brupdate.b2.target_offset, issue_slots[18].brupdate.b2.target_offset
connect slots_18.io.brupdate.b2.jalr_target, issue_slots[18].brupdate.b2.jalr_target
connect slots_18.io.brupdate.b2.pc_sel, issue_slots[18].brupdate.b2.pc_sel
connect slots_18.io.brupdate.b2.cfi_type, issue_slots[18].brupdate.b2.cfi_type
connect slots_18.io.brupdate.b2.taken, issue_slots[18].brupdate.b2.taken
connect slots_18.io.brupdate.b2.mispredict, issue_slots[18].brupdate.b2.mispredict
connect slots_18.io.brupdate.b2.valid, issue_slots[18].brupdate.b2.valid
connect slots_18.io.brupdate.b2.uop.debug_tsrc, issue_slots[18].brupdate.b2.uop.debug_tsrc
connect slots_18.io.brupdate.b2.uop.debug_fsrc, issue_slots[18].brupdate.b2.uop.debug_fsrc
connect slots_18.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[18].brupdate.b2.uop.bp_xcpt_if
connect slots_18.io.brupdate.b2.uop.bp_debug_if, issue_slots[18].brupdate.b2.uop.bp_debug_if
connect slots_18.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[18].brupdate.b2.uop.xcpt_ma_if
connect slots_18.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[18].brupdate.b2.uop.xcpt_ae_if
connect slots_18.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[18].brupdate.b2.uop.xcpt_pf_if
connect slots_18.io.brupdate.b2.uop.fp_single, issue_slots[18].brupdate.b2.uop.fp_single
connect slots_18.io.brupdate.b2.uop.fp_val, issue_slots[18].brupdate.b2.uop.fp_val
connect slots_18.io.brupdate.b2.uop.frs3_en, issue_slots[18].brupdate.b2.uop.frs3_en
connect slots_18.io.brupdate.b2.uop.lrs2_rtype, issue_slots[18].brupdate.b2.uop.lrs2_rtype
connect slots_18.io.brupdate.b2.uop.lrs1_rtype, issue_slots[18].brupdate.b2.uop.lrs1_rtype
connect slots_18.io.brupdate.b2.uop.dst_rtype, issue_slots[18].brupdate.b2.uop.dst_rtype
connect slots_18.io.brupdate.b2.uop.ldst_val, issue_slots[18].brupdate.b2.uop.ldst_val
connect slots_18.io.brupdate.b2.uop.lrs3, issue_slots[18].brupdate.b2.uop.lrs3
connect slots_18.io.brupdate.b2.uop.lrs2, issue_slots[18].brupdate.b2.uop.lrs2
connect slots_18.io.brupdate.b2.uop.lrs1, issue_slots[18].brupdate.b2.uop.lrs1
connect slots_18.io.brupdate.b2.uop.ldst, issue_slots[18].brupdate.b2.uop.ldst
connect slots_18.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[18].brupdate.b2.uop.ldst_is_rs1
connect slots_18.io.brupdate.b2.uop.flush_on_commit, issue_slots[18].brupdate.b2.uop.flush_on_commit
connect slots_18.io.brupdate.b2.uop.is_unique, issue_slots[18].brupdate.b2.uop.is_unique
connect slots_18.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[18].brupdate.b2.uop.is_sys_pc2epc
connect slots_18.io.brupdate.b2.uop.uses_stq, issue_slots[18].brupdate.b2.uop.uses_stq
connect slots_18.io.brupdate.b2.uop.uses_ldq, issue_slots[18].brupdate.b2.uop.uses_ldq
connect slots_18.io.brupdate.b2.uop.is_amo, issue_slots[18].brupdate.b2.uop.is_amo
connect slots_18.io.brupdate.b2.uop.is_fencei, issue_slots[18].brupdate.b2.uop.is_fencei
connect slots_18.io.brupdate.b2.uop.is_fence, issue_slots[18].brupdate.b2.uop.is_fence
connect slots_18.io.brupdate.b2.uop.mem_signed, issue_slots[18].brupdate.b2.uop.mem_signed
connect slots_18.io.brupdate.b2.uop.mem_size, issue_slots[18].brupdate.b2.uop.mem_size
connect slots_18.io.brupdate.b2.uop.mem_cmd, issue_slots[18].brupdate.b2.uop.mem_cmd
connect slots_18.io.brupdate.b2.uop.bypassable, issue_slots[18].brupdate.b2.uop.bypassable
connect slots_18.io.brupdate.b2.uop.exc_cause, issue_slots[18].brupdate.b2.uop.exc_cause
connect slots_18.io.brupdate.b2.uop.exception, issue_slots[18].brupdate.b2.uop.exception
connect slots_18.io.brupdate.b2.uop.stale_pdst, issue_slots[18].brupdate.b2.uop.stale_pdst
connect slots_18.io.brupdate.b2.uop.ppred_busy, issue_slots[18].brupdate.b2.uop.ppred_busy
connect slots_18.io.brupdate.b2.uop.prs3_busy, issue_slots[18].brupdate.b2.uop.prs3_busy
connect slots_18.io.brupdate.b2.uop.prs2_busy, issue_slots[18].brupdate.b2.uop.prs2_busy
connect slots_18.io.brupdate.b2.uop.prs1_busy, issue_slots[18].brupdate.b2.uop.prs1_busy
connect slots_18.io.brupdate.b2.uop.ppred, issue_slots[18].brupdate.b2.uop.ppred
connect slots_18.io.brupdate.b2.uop.prs3, issue_slots[18].brupdate.b2.uop.prs3
connect slots_18.io.brupdate.b2.uop.prs2, issue_slots[18].brupdate.b2.uop.prs2
connect slots_18.io.brupdate.b2.uop.prs1, issue_slots[18].brupdate.b2.uop.prs1
connect slots_18.io.brupdate.b2.uop.pdst, issue_slots[18].brupdate.b2.uop.pdst
connect slots_18.io.brupdate.b2.uop.rxq_idx, issue_slots[18].brupdate.b2.uop.rxq_idx
connect slots_18.io.brupdate.b2.uop.stq_idx, issue_slots[18].brupdate.b2.uop.stq_idx
connect slots_18.io.brupdate.b2.uop.ldq_idx, issue_slots[18].brupdate.b2.uop.ldq_idx
connect slots_18.io.brupdate.b2.uop.rob_idx, issue_slots[18].brupdate.b2.uop.rob_idx
connect slots_18.io.brupdate.b2.uop.csr_addr, issue_slots[18].brupdate.b2.uop.csr_addr
connect slots_18.io.brupdate.b2.uop.imm_packed, issue_slots[18].brupdate.b2.uop.imm_packed
connect slots_18.io.brupdate.b2.uop.taken, issue_slots[18].brupdate.b2.uop.taken
connect slots_18.io.brupdate.b2.uop.pc_lob, issue_slots[18].brupdate.b2.uop.pc_lob
connect slots_18.io.brupdate.b2.uop.edge_inst, issue_slots[18].brupdate.b2.uop.edge_inst
connect slots_18.io.brupdate.b2.uop.ftq_idx, issue_slots[18].brupdate.b2.uop.ftq_idx
connect slots_18.io.brupdate.b2.uop.br_tag, issue_slots[18].brupdate.b2.uop.br_tag
connect slots_18.io.brupdate.b2.uop.br_mask, issue_slots[18].brupdate.b2.uop.br_mask
connect slots_18.io.brupdate.b2.uop.is_sfb, issue_slots[18].brupdate.b2.uop.is_sfb
connect slots_18.io.brupdate.b2.uop.is_jal, issue_slots[18].brupdate.b2.uop.is_jal
connect slots_18.io.brupdate.b2.uop.is_jalr, issue_slots[18].brupdate.b2.uop.is_jalr
connect slots_18.io.brupdate.b2.uop.is_br, issue_slots[18].brupdate.b2.uop.is_br
connect slots_18.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[18].brupdate.b2.uop.iw_p2_poisoned
connect slots_18.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[18].brupdate.b2.uop.iw_p1_poisoned
connect slots_18.io.brupdate.b2.uop.iw_state, issue_slots[18].brupdate.b2.uop.iw_state
connect slots_18.io.brupdate.b2.uop.ctrl.is_std, issue_slots[18].brupdate.b2.uop.ctrl.is_std
connect slots_18.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[18].brupdate.b2.uop.ctrl.is_sta
connect slots_18.io.brupdate.b2.uop.ctrl.is_load, issue_slots[18].brupdate.b2.uop.ctrl.is_load
connect slots_18.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[18].brupdate.b2.uop.ctrl.csr_cmd
connect slots_18.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[18].brupdate.b2.uop.ctrl.fcn_dw
connect slots_18.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[18].brupdate.b2.uop.ctrl.op_fcn
connect slots_18.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[18].brupdate.b2.uop.ctrl.imm_sel
connect slots_18.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[18].brupdate.b2.uop.ctrl.op2_sel
connect slots_18.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[18].brupdate.b2.uop.ctrl.op1_sel
connect slots_18.io.brupdate.b2.uop.ctrl.br_type, issue_slots[18].brupdate.b2.uop.ctrl.br_type
connect slots_18.io.brupdate.b2.uop.fu_code, issue_slots[18].brupdate.b2.uop.fu_code
connect slots_18.io.brupdate.b2.uop.iq_type, issue_slots[18].brupdate.b2.uop.iq_type
connect slots_18.io.brupdate.b2.uop.debug_pc, issue_slots[18].brupdate.b2.uop.debug_pc
connect slots_18.io.brupdate.b2.uop.is_rvc, issue_slots[18].brupdate.b2.uop.is_rvc
connect slots_18.io.brupdate.b2.uop.debug_inst, issue_slots[18].brupdate.b2.uop.debug_inst
connect slots_18.io.brupdate.b2.uop.inst, issue_slots[18].brupdate.b2.uop.inst
connect slots_18.io.brupdate.b2.uop.uopc, issue_slots[18].brupdate.b2.uop.uopc
connect slots_18.io.brupdate.b1.mispredict_mask, issue_slots[18].brupdate.b1.mispredict_mask
connect slots_18.io.brupdate.b1.resolve_mask, issue_slots[18].brupdate.b1.resolve_mask
connect slots_18.io.grant, issue_slots[18].grant
connect issue_slots[18].request_hp, slots_18.io.request_hp
connect issue_slots[18].request, slots_18.io.request
connect issue_slots[18].will_be_valid, slots_18.io.will_be_valid
connect issue_slots[18].valid, slots_18.io.valid
connect issue_slots[19].debug.state, slots_19.io.debug.state
connect issue_slots[19].debug.ppred, slots_19.io.debug.ppred
connect issue_slots[19].debug.p3, slots_19.io.debug.p3
connect issue_slots[19].debug.p2, slots_19.io.debug.p2
connect issue_slots[19].debug.p1, slots_19.io.debug.p1
connect issue_slots[19].uop.debug_tsrc, slots_19.io.uop.debug_tsrc
connect issue_slots[19].uop.debug_fsrc, slots_19.io.uop.debug_fsrc
connect issue_slots[19].uop.bp_xcpt_if, slots_19.io.uop.bp_xcpt_if
connect issue_slots[19].uop.bp_debug_if, slots_19.io.uop.bp_debug_if
connect issue_slots[19].uop.xcpt_ma_if, slots_19.io.uop.xcpt_ma_if
connect issue_slots[19].uop.xcpt_ae_if, slots_19.io.uop.xcpt_ae_if
connect issue_slots[19].uop.xcpt_pf_if, slots_19.io.uop.xcpt_pf_if
connect issue_slots[19].uop.fp_single, slots_19.io.uop.fp_single
connect issue_slots[19].uop.fp_val, slots_19.io.uop.fp_val
connect issue_slots[19].uop.frs3_en, slots_19.io.uop.frs3_en
connect issue_slots[19].uop.lrs2_rtype, slots_19.io.uop.lrs2_rtype
connect issue_slots[19].uop.lrs1_rtype, slots_19.io.uop.lrs1_rtype
connect issue_slots[19].uop.dst_rtype, slots_19.io.uop.dst_rtype
connect issue_slots[19].uop.ldst_val, slots_19.io.uop.ldst_val
connect issue_slots[19].uop.lrs3, slots_19.io.uop.lrs3
connect issue_slots[19].uop.lrs2, slots_19.io.uop.lrs2
connect issue_slots[19].uop.lrs1, slots_19.io.uop.lrs1
connect issue_slots[19].uop.ldst, slots_19.io.uop.ldst
connect issue_slots[19].uop.ldst_is_rs1, slots_19.io.uop.ldst_is_rs1
connect issue_slots[19].uop.flush_on_commit, slots_19.io.uop.flush_on_commit
connect issue_slots[19].uop.is_unique, slots_19.io.uop.is_unique
connect issue_slots[19].uop.is_sys_pc2epc, slots_19.io.uop.is_sys_pc2epc
connect issue_slots[19].uop.uses_stq, slots_19.io.uop.uses_stq
connect issue_slots[19].uop.uses_ldq, slots_19.io.uop.uses_ldq
connect issue_slots[19].uop.is_amo, slots_19.io.uop.is_amo
connect issue_slots[19].uop.is_fencei, slots_19.io.uop.is_fencei
connect issue_slots[19].uop.is_fence, slots_19.io.uop.is_fence
connect issue_slots[19].uop.mem_signed, slots_19.io.uop.mem_signed
connect issue_slots[19].uop.mem_size, slots_19.io.uop.mem_size
connect issue_slots[19].uop.mem_cmd, slots_19.io.uop.mem_cmd
connect issue_slots[19].uop.bypassable, slots_19.io.uop.bypassable
connect issue_slots[19].uop.exc_cause, slots_19.io.uop.exc_cause
connect issue_slots[19].uop.exception, slots_19.io.uop.exception
connect issue_slots[19].uop.stale_pdst, slots_19.io.uop.stale_pdst
connect issue_slots[19].uop.ppred_busy, slots_19.io.uop.ppred_busy
connect issue_slots[19].uop.prs3_busy, slots_19.io.uop.prs3_busy
connect issue_slots[19].uop.prs2_busy, slots_19.io.uop.prs2_busy
connect issue_slots[19].uop.prs1_busy, slots_19.io.uop.prs1_busy
connect issue_slots[19].uop.ppred, slots_19.io.uop.ppred
connect issue_slots[19].uop.prs3, slots_19.io.uop.prs3
connect issue_slots[19].uop.prs2, slots_19.io.uop.prs2
connect issue_slots[19].uop.prs1, slots_19.io.uop.prs1
connect issue_slots[19].uop.pdst, slots_19.io.uop.pdst
connect issue_slots[19].uop.rxq_idx, slots_19.io.uop.rxq_idx
connect issue_slots[19].uop.stq_idx, slots_19.io.uop.stq_idx
connect issue_slots[19].uop.ldq_idx, slots_19.io.uop.ldq_idx
connect issue_slots[19].uop.rob_idx, slots_19.io.uop.rob_idx
connect issue_slots[19].uop.csr_addr, slots_19.io.uop.csr_addr
connect issue_slots[19].uop.imm_packed, slots_19.io.uop.imm_packed
connect issue_slots[19].uop.taken, slots_19.io.uop.taken
connect issue_slots[19].uop.pc_lob, slots_19.io.uop.pc_lob
connect issue_slots[19].uop.edge_inst, slots_19.io.uop.edge_inst
connect issue_slots[19].uop.ftq_idx, slots_19.io.uop.ftq_idx
connect issue_slots[19].uop.br_tag, slots_19.io.uop.br_tag
connect issue_slots[19].uop.br_mask, slots_19.io.uop.br_mask
connect issue_slots[19].uop.is_sfb, slots_19.io.uop.is_sfb
connect issue_slots[19].uop.is_jal, slots_19.io.uop.is_jal
connect issue_slots[19].uop.is_jalr, slots_19.io.uop.is_jalr
connect issue_slots[19].uop.is_br, slots_19.io.uop.is_br
connect issue_slots[19].uop.iw_p2_poisoned, slots_19.io.uop.iw_p2_poisoned
connect issue_slots[19].uop.iw_p1_poisoned, slots_19.io.uop.iw_p1_poisoned
connect issue_slots[19].uop.iw_state, slots_19.io.uop.iw_state
connect issue_slots[19].uop.ctrl.is_std, slots_19.io.uop.ctrl.is_std
connect issue_slots[19].uop.ctrl.is_sta, slots_19.io.uop.ctrl.is_sta
connect issue_slots[19].uop.ctrl.is_load, slots_19.io.uop.ctrl.is_load
connect issue_slots[19].uop.ctrl.csr_cmd, slots_19.io.uop.ctrl.csr_cmd
connect issue_slots[19].uop.ctrl.fcn_dw, slots_19.io.uop.ctrl.fcn_dw
connect issue_slots[19].uop.ctrl.op_fcn, slots_19.io.uop.ctrl.op_fcn
connect issue_slots[19].uop.ctrl.imm_sel, slots_19.io.uop.ctrl.imm_sel
connect issue_slots[19].uop.ctrl.op2_sel, slots_19.io.uop.ctrl.op2_sel
connect issue_slots[19].uop.ctrl.op1_sel, slots_19.io.uop.ctrl.op1_sel
connect issue_slots[19].uop.ctrl.br_type, slots_19.io.uop.ctrl.br_type
connect issue_slots[19].uop.fu_code, slots_19.io.uop.fu_code
connect issue_slots[19].uop.iq_type, slots_19.io.uop.iq_type
connect issue_slots[19].uop.debug_pc, slots_19.io.uop.debug_pc
connect issue_slots[19].uop.is_rvc, slots_19.io.uop.is_rvc
connect issue_slots[19].uop.debug_inst, slots_19.io.uop.debug_inst
connect issue_slots[19].uop.inst, slots_19.io.uop.inst
connect issue_slots[19].uop.uopc, slots_19.io.uop.uopc
connect issue_slots[19].out_uop.debug_tsrc, slots_19.io.out_uop.debug_tsrc
connect issue_slots[19].out_uop.debug_fsrc, slots_19.io.out_uop.debug_fsrc
connect issue_slots[19].out_uop.bp_xcpt_if, slots_19.io.out_uop.bp_xcpt_if
connect issue_slots[19].out_uop.bp_debug_if, slots_19.io.out_uop.bp_debug_if
connect issue_slots[19].out_uop.xcpt_ma_if, slots_19.io.out_uop.xcpt_ma_if
connect issue_slots[19].out_uop.xcpt_ae_if, slots_19.io.out_uop.xcpt_ae_if
connect issue_slots[19].out_uop.xcpt_pf_if, slots_19.io.out_uop.xcpt_pf_if
connect issue_slots[19].out_uop.fp_single, slots_19.io.out_uop.fp_single
connect issue_slots[19].out_uop.fp_val, slots_19.io.out_uop.fp_val
connect issue_slots[19].out_uop.frs3_en, slots_19.io.out_uop.frs3_en
connect issue_slots[19].out_uop.lrs2_rtype, slots_19.io.out_uop.lrs2_rtype
connect issue_slots[19].out_uop.lrs1_rtype, slots_19.io.out_uop.lrs1_rtype
connect issue_slots[19].out_uop.dst_rtype, slots_19.io.out_uop.dst_rtype
connect issue_slots[19].out_uop.ldst_val, slots_19.io.out_uop.ldst_val
connect issue_slots[19].out_uop.lrs3, slots_19.io.out_uop.lrs3
connect issue_slots[19].out_uop.lrs2, slots_19.io.out_uop.lrs2
connect issue_slots[19].out_uop.lrs1, slots_19.io.out_uop.lrs1
connect issue_slots[19].out_uop.ldst, slots_19.io.out_uop.ldst
connect issue_slots[19].out_uop.ldst_is_rs1, slots_19.io.out_uop.ldst_is_rs1
connect issue_slots[19].out_uop.flush_on_commit, slots_19.io.out_uop.flush_on_commit
connect issue_slots[19].out_uop.is_unique, slots_19.io.out_uop.is_unique
connect issue_slots[19].out_uop.is_sys_pc2epc, slots_19.io.out_uop.is_sys_pc2epc
connect issue_slots[19].out_uop.uses_stq, slots_19.io.out_uop.uses_stq
connect issue_slots[19].out_uop.uses_ldq, slots_19.io.out_uop.uses_ldq
connect issue_slots[19].out_uop.is_amo, slots_19.io.out_uop.is_amo
connect issue_slots[19].out_uop.is_fencei, slots_19.io.out_uop.is_fencei
connect issue_slots[19].out_uop.is_fence, slots_19.io.out_uop.is_fence
connect issue_slots[19].out_uop.mem_signed, slots_19.io.out_uop.mem_signed
connect issue_slots[19].out_uop.mem_size, slots_19.io.out_uop.mem_size
connect issue_slots[19].out_uop.mem_cmd, slots_19.io.out_uop.mem_cmd
connect issue_slots[19].out_uop.bypassable, slots_19.io.out_uop.bypassable
connect issue_slots[19].out_uop.exc_cause, slots_19.io.out_uop.exc_cause
connect issue_slots[19].out_uop.exception, slots_19.io.out_uop.exception
connect issue_slots[19].out_uop.stale_pdst, slots_19.io.out_uop.stale_pdst
connect issue_slots[19].out_uop.ppred_busy, slots_19.io.out_uop.ppred_busy
connect issue_slots[19].out_uop.prs3_busy, slots_19.io.out_uop.prs3_busy
connect issue_slots[19].out_uop.prs2_busy, slots_19.io.out_uop.prs2_busy
connect issue_slots[19].out_uop.prs1_busy, slots_19.io.out_uop.prs1_busy
connect issue_slots[19].out_uop.ppred, slots_19.io.out_uop.ppred
connect issue_slots[19].out_uop.prs3, slots_19.io.out_uop.prs3
connect issue_slots[19].out_uop.prs2, slots_19.io.out_uop.prs2
connect issue_slots[19].out_uop.prs1, slots_19.io.out_uop.prs1
connect issue_slots[19].out_uop.pdst, slots_19.io.out_uop.pdst
connect issue_slots[19].out_uop.rxq_idx, slots_19.io.out_uop.rxq_idx
connect issue_slots[19].out_uop.stq_idx, slots_19.io.out_uop.stq_idx
connect issue_slots[19].out_uop.ldq_idx, slots_19.io.out_uop.ldq_idx
connect issue_slots[19].out_uop.rob_idx, slots_19.io.out_uop.rob_idx
connect issue_slots[19].out_uop.csr_addr, slots_19.io.out_uop.csr_addr
connect issue_slots[19].out_uop.imm_packed, slots_19.io.out_uop.imm_packed
connect issue_slots[19].out_uop.taken, slots_19.io.out_uop.taken
connect issue_slots[19].out_uop.pc_lob, slots_19.io.out_uop.pc_lob
connect issue_slots[19].out_uop.edge_inst, slots_19.io.out_uop.edge_inst
connect issue_slots[19].out_uop.ftq_idx, slots_19.io.out_uop.ftq_idx
connect issue_slots[19].out_uop.br_tag, slots_19.io.out_uop.br_tag
connect issue_slots[19].out_uop.br_mask, slots_19.io.out_uop.br_mask
connect issue_slots[19].out_uop.is_sfb, slots_19.io.out_uop.is_sfb
connect issue_slots[19].out_uop.is_jal, slots_19.io.out_uop.is_jal
connect issue_slots[19].out_uop.is_jalr, slots_19.io.out_uop.is_jalr
connect issue_slots[19].out_uop.is_br, slots_19.io.out_uop.is_br
connect issue_slots[19].out_uop.iw_p2_poisoned, slots_19.io.out_uop.iw_p2_poisoned
connect issue_slots[19].out_uop.iw_p1_poisoned, slots_19.io.out_uop.iw_p1_poisoned
connect issue_slots[19].out_uop.iw_state, slots_19.io.out_uop.iw_state
connect issue_slots[19].out_uop.ctrl.is_std, slots_19.io.out_uop.ctrl.is_std
connect issue_slots[19].out_uop.ctrl.is_sta, slots_19.io.out_uop.ctrl.is_sta
connect issue_slots[19].out_uop.ctrl.is_load, slots_19.io.out_uop.ctrl.is_load
connect issue_slots[19].out_uop.ctrl.csr_cmd, slots_19.io.out_uop.ctrl.csr_cmd
connect issue_slots[19].out_uop.ctrl.fcn_dw, slots_19.io.out_uop.ctrl.fcn_dw
connect issue_slots[19].out_uop.ctrl.op_fcn, slots_19.io.out_uop.ctrl.op_fcn
connect issue_slots[19].out_uop.ctrl.imm_sel, slots_19.io.out_uop.ctrl.imm_sel
connect issue_slots[19].out_uop.ctrl.op2_sel, slots_19.io.out_uop.ctrl.op2_sel
connect issue_slots[19].out_uop.ctrl.op1_sel, slots_19.io.out_uop.ctrl.op1_sel
connect issue_slots[19].out_uop.ctrl.br_type, slots_19.io.out_uop.ctrl.br_type
connect issue_slots[19].out_uop.fu_code, slots_19.io.out_uop.fu_code
connect issue_slots[19].out_uop.iq_type, slots_19.io.out_uop.iq_type
connect issue_slots[19].out_uop.debug_pc, slots_19.io.out_uop.debug_pc
connect issue_slots[19].out_uop.is_rvc, slots_19.io.out_uop.is_rvc
connect issue_slots[19].out_uop.debug_inst, slots_19.io.out_uop.debug_inst
connect issue_slots[19].out_uop.inst, slots_19.io.out_uop.inst
connect issue_slots[19].out_uop.uopc, slots_19.io.out_uop.uopc
connect slots_19.io.in_uop.bits.debug_tsrc, issue_slots[19].in_uop.bits.debug_tsrc
connect slots_19.io.in_uop.bits.debug_fsrc, issue_slots[19].in_uop.bits.debug_fsrc
connect slots_19.io.in_uop.bits.bp_xcpt_if, issue_slots[19].in_uop.bits.bp_xcpt_if
connect slots_19.io.in_uop.bits.bp_debug_if, issue_slots[19].in_uop.bits.bp_debug_if
connect slots_19.io.in_uop.bits.xcpt_ma_if, issue_slots[19].in_uop.bits.xcpt_ma_if
connect slots_19.io.in_uop.bits.xcpt_ae_if, issue_slots[19].in_uop.bits.xcpt_ae_if
connect slots_19.io.in_uop.bits.xcpt_pf_if, issue_slots[19].in_uop.bits.xcpt_pf_if
connect slots_19.io.in_uop.bits.fp_single, issue_slots[19].in_uop.bits.fp_single
connect slots_19.io.in_uop.bits.fp_val, issue_slots[19].in_uop.bits.fp_val
connect slots_19.io.in_uop.bits.frs3_en, issue_slots[19].in_uop.bits.frs3_en
connect slots_19.io.in_uop.bits.lrs2_rtype, issue_slots[19].in_uop.bits.lrs2_rtype
connect slots_19.io.in_uop.bits.lrs1_rtype, issue_slots[19].in_uop.bits.lrs1_rtype
connect slots_19.io.in_uop.bits.dst_rtype, issue_slots[19].in_uop.bits.dst_rtype
connect slots_19.io.in_uop.bits.ldst_val, issue_slots[19].in_uop.bits.ldst_val
connect slots_19.io.in_uop.bits.lrs3, issue_slots[19].in_uop.bits.lrs3
connect slots_19.io.in_uop.bits.lrs2, issue_slots[19].in_uop.bits.lrs2
connect slots_19.io.in_uop.bits.lrs1, issue_slots[19].in_uop.bits.lrs1
connect slots_19.io.in_uop.bits.ldst, issue_slots[19].in_uop.bits.ldst
connect slots_19.io.in_uop.bits.ldst_is_rs1, issue_slots[19].in_uop.bits.ldst_is_rs1
connect slots_19.io.in_uop.bits.flush_on_commit, issue_slots[19].in_uop.bits.flush_on_commit
connect slots_19.io.in_uop.bits.is_unique, issue_slots[19].in_uop.bits.is_unique
connect slots_19.io.in_uop.bits.is_sys_pc2epc, issue_slots[19].in_uop.bits.is_sys_pc2epc
connect slots_19.io.in_uop.bits.uses_stq, issue_slots[19].in_uop.bits.uses_stq
connect slots_19.io.in_uop.bits.uses_ldq, issue_slots[19].in_uop.bits.uses_ldq
connect slots_19.io.in_uop.bits.is_amo, issue_slots[19].in_uop.bits.is_amo
connect slots_19.io.in_uop.bits.is_fencei, issue_slots[19].in_uop.bits.is_fencei
connect slots_19.io.in_uop.bits.is_fence, issue_slots[19].in_uop.bits.is_fence
connect slots_19.io.in_uop.bits.mem_signed, issue_slots[19].in_uop.bits.mem_signed
connect slots_19.io.in_uop.bits.mem_size, issue_slots[19].in_uop.bits.mem_size
connect slots_19.io.in_uop.bits.mem_cmd, issue_slots[19].in_uop.bits.mem_cmd
connect slots_19.io.in_uop.bits.bypassable, issue_slots[19].in_uop.bits.bypassable
connect slots_19.io.in_uop.bits.exc_cause, issue_slots[19].in_uop.bits.exc_cause
connect slots_19.io.in_uop.bits.exception, issue_slots[19].in_uop.bits.exception
connect slots_19.io.in_uop.bits.stale_pdst, issue_slots[19].in_uop.bits.stale_pdst
connect slots_19.io.in_uop.bits.ppred_busy, issue_slots[19].in_uop.bits.ppred_busy
connect slots_19.io.in_uop.bits.prs3_busy, issue_slots[19].in_uop.bits.prs3_busy
connect slots_19.io.in_uop.bits.prs2_busy, issue_slots[19].in_uop.bits.prs2_busy
connect slots_19.io.in_uop.bits.prs1_busy, issue_slots[19].in_uop.bits.prs1_busy
connect slots_19.io.in_uop.bits.ppred, issue_slots[19].in_uop.bits.ppred
connect slots_19.io.in_uop.bits.prs3, issue_slots[19].in_uop.bits.prs3
connect slots_19.io.in_uop.bits.prs2, issue_slots[19].in_uop.bits.prs2
connect slots_19.io.in_uop.bits.prs1, issue_slots[19].in_uop.bits.prs1
connect slots_19.io.in_uop.bits.pdst, issue_slots[19].in_uop.bits.pdst
connect slots_19.io.in_uop.bits.rxq_idx, issue_slots[19].in_uop.bits.rxq_idx
connect slots_19.io.in_uop.bits.stq_idx, issue_slots[19].in_uop.bits.stq_idx
connect slots_19.io.in_uop.bits.ldq_idx, issue_slots[19].in_uop.bits.ldq_idx
connect slots_19.io.in_uop.bits.rob_idx, issue_slots[19].in_uop.bits.rob_idx
connect slots_19.io.in_uop.bits.csr_addr, issue_slots[19].in_uop.bits.csr_addr
connect slots_19.io.in_uop.bits.imm_packed, issue_slots[19].in_uop.bits.imm_packed
connect slots_19.io.in_uop.bits.taken, issue_slots[19].in_uop.bits.taken
connect slots_19.io.in_uop.bits.pc_lob, issue_slots[19].in_uop.bits.pc_lob
connect slots_19.io.in_uop.bits.edge_inst, issue_slots[19].in_uop.bits.edge_inst
connect slots_19.io.in_uop.bits.ftq_idx, issue_slots[19].in_uop.bits.ftq_idx
connect slots_19.io.in_uop.bits.br_tag, issue_slots[19].in_uop.bits.br_tag
connect slots_19.io.in_uop.bits.br_mask, issue_slots[19].in_uop.bits.br_mask
connect slots_19.io.in_uop.bits.is_sfb, issue_slots[19].in_uop.bits.is_sfb
connect slots_19.io.in_uop.bits.is_jal, issue_slots[19].in_uop.bits.is_jal
connect slots_19.io.in_uop.bits.is_jalr, issue_slots[19].in_uop.bits.is_jalr
connect slots_19.io.in_uop.bits.is_br, issue_slots[19].in_uop.bits.is_br
connect slots_19.io.in_uop.bits.iw_p2_poisoned, issue_slots[19].in_uop.bits.iw_p2_poisoned
connect slots_19.io.in_uop.bits.iw_p1_poisoned, issue_slots[19].in_uop.bits.iw_p1_poisoned
connect slots_19.io.in_uop.bits.iw_state, issue_slots[19].in_uop.bits.iw_state
connect slots_19.io.in_uop.bits.ctrl.is_std, issue_slots[19].in_uop.bits.ctrl.is_std
connect slots_19.io.in_uop.bits.ctrl.is_sta, issue_slots[19].in_uop.bits.ctrl.is_sta
connect slots_19.io.in_uop.bits.ctrl.is_load, issue_slots[19].in_uop.bits.ctrl.is_load
connect slots_19.io.in_uop.bits.ctrl.csr_cmd, issue_slots[19].in_uop.bits.ctrl.csr_cmd
connect slots_19.io.in_uop.bits.ctrl.fcn_dw, issue_slots[19].in_uop.bits.ctrl.fcn_dw
connect slots_19.io.in_uop.bits.ctrl.op_fcn, issue_slots[19].in_uop.bits.ctrl.op_fcn
connect slots_19.io.in_uop.bits.ctrl.imm_sel, issue_slots[19].in_uop.bits.ctrl.imm_sel
connect slots_19.io.in_uop.bits.ctrl.op2_sel, issue_slots[19].in_uop.bits.ctrl.op2_sel
connect slots_19.io.in_uop.bits.ctrl.op1_sel, issue_slots[19].in_uop.bits.ctrl.op1_sel
connect slots_19.io.in_uop.bits.ctrl.br_type, issue_slots[19].in_uop.bits.ctrl.br_type
connect slots_19.io.in_uop.bits.fu_code, issue_slots[19].in_uop.bits.fu_code
connect slots_19.io.in_uop.bits.iq_type, issue_slots[19].in_uop.bits.iq_type
connect slots_19.io.in_uop.bits.debug_pc, issue_slots[19].in_uop.bits.debug_pc
connect slots_19.io.in_uop.bits.is_rvc, issue_slots[19].in_uop.bits.is_rvc
connect slots_19.io.in_uop.bits.debug_inst, issue_slots[19].in_uop.bits.debug_inst
connect slots_19.io.in_uop.bits.inst, issue_slots[19].in_uop.bits.inst
connect slots_19.io.in_uop.bits.uopc, issue_slots[19].in_uop.bits.uopc
connect slots_19.io.in_uop.valid, issue_slots[19].in_uop.valid
connect slots_19.io.spec_ld_wakeup[0].bits, issue_slots[19].spec_ld_wakeup[0].bits
connect slots_19.io.spec_ld_wakeup[0].valid, issue_slots[19].spec_ld_wakeup[0].valid
connect slots_19.io.pred_wakeup_port.bits, issue_slots[19].pred_wakeup_port.bits
connect slots_19.io.pred_wakeup_port.valid, issue_slots[19].pred_wakeup_port.valid
connect slots_19.io.wakeup_ports[0].bits.poisoned, issue_slots[19].wakeup_ports[0].bits.poisoned
connect slots_19.io.wakeup_ports[0].bits.pdst, issue_slots[19].wakeup_ports[0].bits.pdst
connect slots_19.io.wakeup_ports[0].valid, issue_slots[19].wakeup_ports[0].valid
connect slots_19.io.wakeup_ports[1].bits.poisoned, issue_slots[19].wakeup_ports[1].bits.poisoned
connect slots_19.io.wakeup_ports[1].bits.pdst, issue_slots[19].wakeup_ports[1].bits.pdst
connect slots_19.io.wakeup_ports[1].valid, issue_slots[19].wakeup_ports[1].valid
connect slots_19.io.ldspec_miss, issue_slots[19].ldspec_miss
connect slots_19.io.clear, issue_slots[19].clear
connect slots_19.io.kill, issue_slots[19].kill
connect slots_19.io.brupdate.b2.target_offset, issue_slots[19].brupdate.b2.target_offset
connect slots_19.io.brupdate.b2.jalr_target, issue_slots[19].brupdate.b2.jalr_target
connect slots_19.io.brupdate.b2.pc_sel, issue_slots[19].brupdate.b2.pc_sel
connect slots_19.io.brupdate.b2.cfi_type, issue_slots[19].brupdate.b2.cfi_type
connect slots_19.io.brupdate.b2.taken, issue_slots[19].brupdate.b2.taken
connect slots_19.io.brupdate.b2.mispredict, issue_slots[19].brupdate.b2.mispredict
connect slots_19.io.brupdate.b2.valid, issue_slots[19].brupdate.b2.valid
connect slots_19.io.brupdate.b2.uop.debug_tsrc, issue_slots[19].brupdate.b2.uop.debug_tsrc
connect slots_19.io.brupdate.b2.uop.debug_fsrc, issue_slots[19].brupdate.b2.uop.debug_fsrc
connect slots_19.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[19].brupdate.b2.uop.bp_xcpt_if
connect slots_19.io.brupdate.b2.uop.bp_debug_if, issue_slots[19].brupdate.b2.uop.bp_debug_if
connect slots_19.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[19].brupdate.b2.uop.xcpt_ma_if
connect slots_19.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[19].brupdate.b2.uop.xcpt_ae_if
connect slots_19.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[19].brupdate.b2.uop.xcpt_pf_if
connect slots_19.io.brupdate.b2.uop.fp_single, issue_slots[19].brupdate.b2.uop.fp_single
connect slots_19.io.brupdate.b2.uop.fp_val, issue_slots[19].brupdate.b2.uop.fp_val
connect slots_19.io.brupdate.b2.uop.frs3_en, issue_slots[19].brupdate.b2.uop.frs3_en
connect slots_19.io.brupdate.b2.uop.lrs2_rtype, issue_slots[19].brupdate.b2.uop.lrs2_rtype
connect slots_19.io.brupdate.b2.uop.lrs1_rtype, issue_slots[19].brupdate.b2.uop.lrs1_rtype
connect slots_19.io.brupdate.b2.uop.dst_rtype, issue_slots[19].brupdate.b2.uop.dst_rtype
connect slots_19.io.brupdate.b2.uop.ldst_val, issue_slots[19].brupdate.b2.uop.ldst_val
connect slots_19.io.brupdate.b2.uop.lrs3, issue_slots[19].brupdate.b2.uop.lrs3
connect slots_19.io.brupdate.b2.uop.lrs2, issue_slots[19].brupdate.b2.uop.lrs2
connect slots_19.io.brupdate.b2.uop.lrs1, issue_slots[19].brupdate.b2.uop.lrs1
connect slots_19.io.brupdate.b2.uop.ldst, issue_slots[19].brupdate.b2.uop.ldst
connect slots_19.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[19].brupdate.b2.uop.ldst_is_rs1
connect slots_19.io.brupdate.b2.uop.flush_on_commit, issue_slots[19].brupdate.b2.uop.flush_on_commit
connect slots_19.io.brupdate.b2.uop.is_unique, issue_slots[19].brupdate.b2.uop.is_unique
connect slots_19.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[19].brupdate.b2.uop.is_sys_pc2epc
connect slots_19.io.brupdate.b2.uop.uses_stq, issue_slots[19].brupdate.b2.uop.uses_stq
connect slots_19.io.brupdate.b2.uop.uses_ldq, issue_slots[19].brupdate.b2.uop.uses_ldq
connect slots_19.io.brupdate.b2.uop.is_amo, issue_slots[19].brupdate.b2.uop.is_amo
connect slots_19.io.brupdate.b2.uop.is_fencei, issue_slots[19].brupdate.b2.uop.is_fencei
connect slots_19.io.brupdate.b2.uop.is_fence, issue_slots[19].brupdate.b2.uop.is_fence
connect slots_19.io.brupdate.b2.uop.mem_signed, issue_slots[19].brupdate.b2.uop.mem_signed
connect slots_19.io.brupdate.b2.uop.mem_size, issue_slots[19].brupdate.b2.uop.mem_size
connect slots_19.io.brupdate.b2.uop.mem_cmd, issue_slots[19].brupdate.b2.uop.mem_cmd
connect slots_19.io.brupdate.b2.uop.bypassable, issue_slots[19].brupdate.b2.uop.bypassable
connect slots_19.io.brupdate.b2.uop.exc_cause, issue_slots[19].brupdate.b2.uop.exc_cause
connect slots_19.io.brupdate.b2.uop.exception, issue_slots[19].brupdate.b2.uop.exception
connect slots_19.io.brupdate.b2.uop.stale_pdst, issue_slots[19].brupdate.b2.uop.stale_pdst
connect slots_19.io.brupdate.b2.uop.ppred_busy, issue_slots[19].brupdate.b2.uop.ppred_busy
connect slots_19.io.brupdate.b2.uop.prs3_busy, issue_slots[19].brupdate.b2.uop.prs3_busy
connect slots_19.io.brupdate.b2.uop.prs2_busy, issue_slots[19].brupdate.b2.uop.prs2_busy
connect slots_19.io.brupdate.b2.uop.prs1_busy, issue_slots[19].brupdate.b2.uop.prs1_busy
connect slots_19.io.brupdate.b2.uop.ppred, issue_slots[19].brupdate.b2.uop.ppred
connect slots_19.io.brupdate.b2.uop.prs3, issue_slots[19].brupdate.b2.uop.prs3
connect slots_19.io.brupdate.b2.uop.prs2, issue_slots[19].brupdate.b2.uop.prs2
connect slots_19.io.brupdate.b2.uop.prs1, issue_slots[19].brupdate.b2.uop.prs1
connect slots_19.io.brupdate.b2.uop.pdst, issue_slots[19].brupdate.b2.uop.pdst
connect slots_19.io.brupdate.b2.uop.rxq_idx, issue_slots[19].brupdate.b2.uop.rxq_idx
connect slots_19.io.brupdate.b2.uop.stq_idx, issue_slots[19].brupdate.b2.uop.stq_idx
connect slots_19.io.brupdate.b2.uop.ldq_idx, issue_slots[19].brupdate.b2.uop.ldq_idx
connect slots_19.io.brupdate.b2.uop.rob_idx, issue_slots[19].brupdate.b2.uop.rob_idx
connect slots_19.io.brupdate.b2.uop.csr_addr, issue_slots[19].brupdate.b2.uop.csr_addr
connect slots_19.io.brupdate.b2.uop.imm_packed, issue_slots[19].brupdate.b2.uop.imm_packed
connect slots_19.io.brupdate.b2.uop.taken, issue_slots[19].brupdate.b2.uop.taken
connect slots_19.io.brupdate.b2.uop.pc_lob, issue_slots[19].brupdate.b2.uop.pc_lob
connect slots_19.io.brupdate.b2.uop.edge_inst, issue_slots[19].brupdate.b2.uop.edge_inst
connect slots_19.io.brupdate.b2.uop.ftq_idx, issue_slots[19].brupdate.b2.uop.ftq_idx
connect slots_19.io.brupdate.b2.uop.br_tag, issue_slots[19].brupdate.b2.uop.br_tag
connect slots_19.io.brupdate.b2.uop.br_mask, issue_slots[19].brupdate.b2.uop.br_mask
connect slots_19.io.brupdate.b2.uop.is_sfb, issue_slots[19].brupdate.b2.uop.is_sfb
connect slots_19.io.brupdate.b2.uop.is_jal, issue_slots[19].brupdate.b2.uop.is_jal
connect slots_19.io.brupdate.b2.uop.is_jalr, issue_slots[19].brupdate.b2.uop.is_jalr
connect slots_19.io.brupdate.b2.uop.is_br, issue_slots[19].brupdate.b2.uop.is_br
connect slots_19.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[19].brupdate.b2.uop.iw_p2_poisoned
connect slots_19.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[19].brupdate.b2.uop.iw_p1_poisoned
connect slots_19.io.brupdate.b2.uop.iw_state, issue_slots[19].brupdate.b2.uop.iw_state
connect slots_19.io.brupdate.b2.uop.ctrl.is_std, issue_slots[19].brupdate.b2.uop.ctrl.is_std
connect slots_19.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[19].brupdate.b2.uop.ctrl.is_sta
connect slots_19.io.brupdate.b2.uop.ctrl.is_load, issue_slots[19].brupdate.b2.uop.ctrl.is_load
connect slots_19.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[19].brupdate.b2.uop.ctrl.csr_cmd
connect slots_19.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[19].brupdate.b2.uop.ctrl.fcn_dw
connect slots_19.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[19].brupdate.b2.uop.ctrl.op_fcn
connect slots_19.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[19].brupdate.b2.uop.ctrl.imm_sel
connect slots_19.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[19].brupdate.b2.uop.ctrl.op2_sel
connect slots_19.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[19].brupdate.b2.uop.ctrl.op1_sel
connect slots_19.io.brupdate.b2.uop.ctrl.br_type, issue_slots[19].brupdate.b2.uop.ctrl.br_type
connect slots_19.io.brupdate.b2.uop.fu_code, issue_slots[19].brupdate.b2.uop.fu_code
connect slots_19.io.brupdate.b2.uop.iq_type, issue_slots[19].brupdate.b2.uop.iq_type
connect slots_19.io.brupdate.b2.uop.debug_pc, issue_slots[19].brupdate.b2.uop.debug_pc
connect slots_19.io.brupdate.b2.uop.is_rvc, issue_slots[19].brupdate.b2.uop.is_rvc
connect slots_19.io.brupdate.b2.uop.debug_inst, issue_slots[19].brupdate.b2.uop.debug_inst
connect slots_19.io.brupdate.b2.uop.inst, issue_slots[19].brupdate.b2.uop.inst
connect slots_19.io.brupdate.b2.uop.uopc, issue_slots[19].brupdate.b2.uop.uopc
connect slots_19.io.brupdate.b1.mispredict_mask, issue_slots[19].brupdate.b1.mispredict_mask
connect slots_19.io.brupdate.b1.resolve_mask, issue_slots[19].brupdate.b1.resolve_mask
connect slots_19.io.grant, issue_slots[19].grant
connect issue_slots[19].request_hp, slots_19.io.request_hp
connect issue_slots[19].request, slots_19.io.request
connect issue_slots[19].will_be_valid, slots_19.io.will_be_valid
connect issue_slots[19].valid, slots_19.io.valid
connect issue_slots[20].debug.state, slots_20.io.debug.state
connect issue_slots[20].debug.ppred, slots_20.io.debug.ppred
connect issue_slots[20].debug.p3, slots_20.io.debug.p3
connect issue_slots[20].debug.p2, slots_20.io.debug.p2
connect issue_slots[20].debug.p1, slots_20.io.debug.p1
connect issue_slots[20].uop.debug_tsrc, slots_20.io.uop.debug_tsrc
connect issue_slots[20].uop.debug_fsrc, slots_20.io.uop.debug_fsrc
connect issue_slots[20].uop.bp_xcpt_if, slots_20.io.uop.bp_xcpt_if
connect issue_slots[20].uop.bp_debug_if, slots_20.io.uop.bp_debug_if
connect issue_slots[20].uop.xcpt_ma_if, slots_20.io.uop.xcpt_ma_if
connect issue_slots[20].uop.xcpt_ae_if, slots_20.io.uop.xcpt_ae_if
connect issue_slots[20].uop.xcpt_pf_if, slots_20.io.uop.xcpt_pf_if
connect issue_slots[20].uop.fp_single, slots_20.io.uop.fp_single
connect issue_slots[20].uop.fp_val, slots_20.io.uop.fp_val
connect issue_slots[20].uop.frs3_en, slots_20.io.uop.frs3_en
connect issue_slots[20].uop.lrs2_rtype, slots_20.io.uop.lrs2_rtype
connect issue_slots[20].uop.lrs1_rtype, slots_20.io.uop.lrs1_rtype
connect issue_slots[20].uop.dst_rtype, slots_20.io.uop.dst_rtype
connect issue_slots[20].uop.ldst_val, slots_20.io.uop.ldst_val
connect issue_slots[20].uop.lrs3, slots_20.io.uop.lrs3
connect issue_slots[20].uop.lrs2, slots_20.io.uop.lrs2
connect issue_slots[20].uop.lrs1, slots_20.io.uop.lrs1
connect issue_slots[20].uop.ldst, slots_20.io.uop.ldst
connect issue_slots[20].uop.ldst_is_rs1, slots_20.io.uop.ldst_is_rs1
connect issue_slots[20].uop.flush_on_commit, slots_20.io.uop.flush_on_commit
connect issue_slots[20].uop.is_unique, slots_20.io.uop.is_unique
connect issue_slots[20].uop.is_sys_pc2epc, slots_20.io.uop.is_sys_pc2epc
connect issue_slots[20].uop.uses_stq, slots_20.io.uop.uses_stq
connect issue_slots[20].uop.uses_ldq, slots_20.io.uop.uses_ldq
connect issue_slots[20].uop.is_amo, slots_20.io.uop.is_amo
connect issue_slots[20].uop.is_fencei, slots_20.io.uop.is_fencei
connect issue_slots[20].uop.is_fence, slots_20.io.uop.is_fence
connect issue_slots[20].uop.mem_signed, slots_20.io.uop.mem_signed
connect issue_slots[20].uop.mem_size, slots_20.io.uop.mem_size
connect issue_slots[20].uop.mem_cmd, slots_20.io.uop.mem_cmd
connect issue_slots[20].uop.bypassable, slots_20.io.uop.bypassable
connect issue_slots[20].uop.exc_cause, slots_20.io.uop.exc_cause
connect issue_slots[20].uop.exception, slots_20.io.uop.exception
connect issue_slots[20].uop.stale_pdst, slots_20.io.uop.stale_pdst
connect issue_slots[20].uop.ppred_busy, slots_20.io.uop.ppred_busy
connect issue_slots[20].uop.prs3_busy, slots_20.io.uop.prs3_busy
connect issue_slots[20].uop.prs2_busy, slots_20.io.uop.prs2_busy
connect issue_slots[20].uop.prs1_busy, slots_20.io.uop.prs1_busy
connect issue_slots[20].uop.ppred, slots_20.io.uop.ppred
connect issue_slots[20].uop.prs3, slots_20.io.uop.prs3
connect issue_slots[20].uop.prs2, slots_20.io.uop.prs2
connect issue_slots[20].uop.prs1, slots_20.io.uop.prs1
connect issue_slots[20].uop.pdst, slots_20.io.uop.pdst
connect issue_slots[20].uop.rxq_idx, slots_20.io.uop.rxq_idx
connect issue_slots[20].uop.stq_idx, slots_20.io.uop.stq_idx
connect issue_slots[20].uop.ldq_idx, slots_20.io.uop.ldq_idx
connect issue_slots[20].uop.rob_idx, slots_20.io.uop.rob_idx
connect issue_slots[20].uop.csr_addr, slots_20.io.uop.csr_addr
connect issue_slots[20].uop.imm_packed, slots_20.io.uop.imm_packed
connect issue_slots[20].uop.taken, slots_20.io.uop.taken
connect issue_slots[20].uop.pc_lob, slots_20.io.uop.pc_lob
connect issue_slots[20].uop.edge_inst, slots_20.io.uop.edge_inst
connect issue_slots[20].uop.ftq_idx, slots_20.io.uop.ftq_idx
connect issue_slots[20].uop.br_tag, slots_20.io.uop.br_tag
connect issue_slots[20].uop.br_mask, slots_20.io.uop.br_mask
connect issue_slots[20].uop.is_sfb, slots_20.io.uop.is_sfb
connect issue_slots[20].uop.is_jal, slots_20.io.uop.is_jal
connect issue_slots[20].uop.is_jalr, slots_20.io.uop.is_jalr
connect issue_slots[20].uop.is_br, slots_20.io.uop.is_br
connect issue_slots[20].uop.iw_p2_poisoned, slots_20.io.uop.iw_p2_poisoned
connect issue_slots[20].uop.iw_p1_poisoned, slots_20.io.uop.iw_p1_poisoned
connect issue_slots[20].uop.iw_state, slots_20.io.uop.iw_state
connect issue_slots[20].uop.ctrl.is_std, slots_20.io.uop.ctrl.is_std
connect issue_slots[20].uop.ctrl.is_sta, slots_20.io.uop.ctrl.is_sta
connect issue_slots[20].uop.ctrl.is_load, slots_20.io.uop.ctrl.is_load
connect issue_slots[20].uop.ctrl.csr_cmd, slots_20.io.uop.ctrl.csr_cmd
connect issue_slots[20].uop.ctrl.fcn_dw, slots_20.io.uop.ctrl.fcn_dw
connect issue_slots[20].uop.ctrl.op_fcn, slots_20.io.uop.ctrl.op_fcn
connect issue_slots[20].uop.ctrl.imm_sel, slots_20.io.uop.ctrl.imm_sel
connect issue_slots[20].uop.ctrl.op2_sel, slots_20.io.uop.ctrl.op2_sel
connect issue_slots[20].uop.ctrl.op1_sel, slots_20.io.uop.ctrl.op1_sel
connect issue_slots[20].uop.ctrl.br_type, slots_20.io.uop.ctrl.br_type
connect issue_slots[20].uop.fu_code, slots_20.io.uop.fu_code
connect issue_slots[20].uop.iq_type, slots_20.io.uop.iq_type
connect issue_slots[20].uop.debug_pc, slots_20.io.uop.debug_pc
connect issue_slots[20].uop.is_rvc, slots_20.io.uop.is_rvc
connect issue_slots[20].uop.debug_inst, slots_20.io.uop.debug_inst
connect issue_slots[20].uop.inst, slots_20.io.uop.inst
connect issue_slots[20].uop.uopc, slots_20.io.uop.uopc
connect issue_slots[20].out_uop.debug_tsrc, slots_20.io.out_uop.debug_tsrc
connect issue_slots[20].out_uop.debug_fsrc, slots_20.io.out_uop.debug_fsrc
connect issue_slots[20].out_uop.bp_xcpt_if, slots_20.io.out_uop.bp_xcpt_if
connect issue_slots[20].out_uop.bp_debug_if, slots_20.io.out_uop.bp_debug_if
connect issue_slots[20].out_uop.xcpt_ma_if, slots_20.io.out_uop.xcpt_ma_if
connect issue_slots[20].out_uop.xcpt_ae_if, slots_20.io.out_uop.xcpt_ae_if
connect issue_slots[20].out_uop.xcpt_pf_if, slots_20.io.out_uop.xcpt_pf_if
connect issue_slots[20].out_uop.fp_single, slots_20.io.out_uop.fp_single
connect issue_slots[20].out_uop.fp_val, slots_20.io.out_uop.fp_val
connect issue_slots[20].out_uop.frs3_en, slots_20.io.out_uop.frs3_en
connect issue_slots[20].out_uop.lrs2_rtype, slots_20.io.out_uop.lrs2_rtype
connect issue_slots[20].out_uop.lrs1_rtype, slots_20.io.out_uop.lrs1_rtype
connect issue_slots[20].out_uop.dst_rtype, slots_20.io.out_uop.dst_rtype
connect issue_slots[20].out_uop.ldst_val, slots_20.io.out_uop.ldst_val
connect issue_slots[20].out_uop.lrs3, slots_20.io.out_uop.lrs3
connect issue_slots[20].out_uop.lrs2, slots_20.io.out_uop.lrs2
connect issue_slots[20].out_uop.lrs1, slots_20.io.out_uop.lrs1
connect issue_slots[20].out_uop.ldst, slots_20.io.out_uop.ldst
connect issue_slots[20].out_uop.ldst_is_rs1, slots_20.io.out_uop.ldst_is_rs1
connect issue_slots[20].out_uop.flush_on_commit, slots_20.io.out_uop.flush_on_commit
connect issue_slots[20].out_uop.is_unique, slots_20.io.out_uop.is_unique
connect issue_slots[20].out_uop.is_sys_pc2epc, slots_20.io.out_uop.is_sys_pc2epc
connect issue_slots[20].out_uop.uses_stq, slots_20.io.out_uop.uses_stq
connect issue_slots[20].out_uop.uses_ldq, slots_20.io.out_uop.uses_ldq
connect issue_slots[20].out_uop.is_amo, slots_20.io.out_uop.is_amo
connect issue_slots[20].out_uop.is_fencei, slots_20.io.out_uop.is_fencei
connect issue_slots[20].out_uop.is_fence, slots_20.io.out_uop.is_fence
connect issue_slots[20].out_uop.mem_signed, slots_20.io.out_uop.mem_signed
connect issue_slots[20].out_uop.mem_size, slots_20.io.out_uop.mem_size
connect issue_slots[20].out_uop.mem_cmd, slots_20.io.out_uop.mem_cmd
connect issue_slots[20].out_uop.bypassable, slots_20.io.out_uop.bypassable
connect issue_slots[20].out_uop.exc_cause, slots_20.io.out_uop.exc_cause
connect issue_slots[20].out_uop.exception, slots_20.io.out_uop.exception
connect issue_slots[20].out_uop.stale_pdst, slots_20.io.out_uop.stale_pdst
connect issue_slots[20].out_uop.ppred_busy, slots_20.io.out_uop.ppred_busy
connect issue_slots[20].out_uop.prs3_busy, slots_20.io.out_uop.prs3_busy
connect issue_slots[20].out_uop.prs2_busy, slots_20.io.out_uop.prs2_busy
connect issue_slots[20].out_uop.prs1_busy, slots_20.io.out_uop.prs1_busy
connect issue_slots[20].out_uop.ppred, slots_20.io.out_uop.ppred
connect issue_slots[20].out_uop.prs3, slots_20.io.out_uop.prs3
connect issue_slots[20].out_uop.prs2, slots_20.io.out_uop.prs2
connect issue_slots[20].out_uop.prs1, slots_20.io.out_uop.prs1
connect issue_slots[20].out_uop.pdst, slots_20.io.out_uop.pdst
connect issue_slots[20].out_uop.rxq_idx, slots_20.io.out_uop.rxq_idx
connect issue_slots[20].out_uop.stq_idx, slots_20.io.out_uop.stq_idx
connect issue_slots[20].out_uop.ldq_idx, slots_20.io.out_uop.ldq_idx
connect issue_slots[20].out_uop.rob_idx, slots_20.io.out_uop.rob_idx
connect issue_slots[20].out_uop.csr_addr, slots_20.io.out_uop.csr_addr
connect issue_slots[20].out_uop.imm_packed, slots_20.io.out_uop.imm_packed
connect issue_slots[20].out_uop.taken, slots_20.io.out_uop.taken
connect issue_slots[20].out_uop.pc_lob, slots_20.io.out_uop.pc_lob
connect issue_slots[20].out_uop.edge_inst, slots_20.io.out_uop.edge_inst
connect issue_slots[20].out_uop.ftq_idx, slots_20.io.out_uop.ftq_idx
connect issue_slots[20].out_uop.br_tag, slots_20.io.out_uop.br_tag
connect issue_slots[20].out_uop.br_mask, slots_20.io.out_uop.br_mask
connect issue_slots[20].out_uop.is_sfb, slots_20.io.out_uop.is_sfb
connect issue_slots[20].out_uop.is_jal, slots_20.io.out_uop.is_jal
connect issue_slots[20].out_uop.is_jalr, slots_20.io.out_uop.is_jalr
connect issue_slots[20].out_uop.is_br, slots_20.io.out_uop.is_br
connect issue_slots[20].out_uop.iw_p2_poisoned, slots_20.io.out_uop.iw_p2_poisoned
connect issue_slots[20].out_uop.iw_p1_poisoned, slots_20.io.out_uop.iw_p1_poisoned
connect issue_slots[20].out_uop.iw_state, slots_20.io.out_uop.iw_state
connect issue_slots[20].out_uop.ctrl.is_std, slots_20.io.out_uop.ctrl.is_std
connect issue_slots[20].out_uop.ctrl.is_sta, slots_20.io.out_uop.ctrl.is_sta
connect issue_slots[20].out_uop.ctrl.is_load, slots_20.io.out_uop.ctrl.is_load
connect issue_slots[20].out_uop.ctrl.csr_cmd, slots_20.io.out_uop.ctrl.csr_cmd
connect issue_slots[20].out_uop.ctrl.fcn_dw, slots_20.io.out_uop.ctrl.fcn_dw
connect issue_slots[20].out_uop.ctrl.op_fcn, slots_20.io.out_uop.ctrl.op_fcn
connect issue_slots[20].out_uop.ctrl.imm_sel, slots_20.io.out_uop.ctrl.imm_sel
connect issue_slots[20].out_uop.ctrl.op2_sel, slots_20.io.out_uop.ctrl.op2_sel
connect issue_slots[20].out_uop.ctrl.op1_sel, slots_20.io.out_uop.ctrl.op1_sel
connect issue_slots[20].out_uop.ctrl.br_type, slots_20.io.out_uop.ctrl.br_type
connect issue_slots[20].out_uop.fu_code, slots_20.io.out_uop.fu_code
connect issue_slots[20].out_uop.iq_type, slots_20.io.out_uop.iq_type
connect issue_slots[20].out_uop.debug_pc, slots_20.io.out_uop.debug_pc
connect issue_slots[20].out_uop.is_rvc, slots_20.io.out_uop.is_rvc
connect issue_slots[20].out_uop.debug_inst, slots_20.io.out_uop.debug_inst
connect issue_slots[20].out_uop.inst, slots_20.io.out_uop.inst
connect issue_slots[20].out_uop.uopc, slots_20.io.out_uop.uopc
connect slots_20.io.in_uop.bits.debug_tsrc, issue_slots[20].in_uop.bits.debug_tsrc
connect slots_20.io.in_uop.bits.debug_fsrc, issue_slots[20].in_uop.bits.debug_fsrc
connect slots_20.io.in_uop.bits.bp_xcpt_if, issue_slots[20].in_uop.bits.bp_xcpt_if
connect slots_20.io.in_uop.bits.bp_debug_if, issue_slots[20].in_uop.bits.bp_debug_if
connect slots_20.io.in_uop.bits.xcpt_ma_if, issue_slots[20].in_uop.bits.xcpt_ma_if
connect slots_20.io.in_uop.bits.xcpt_ae_if, issue_slots[20].in_uop.bits.xcpt_ae_if
connect slots_20.io.in_uop.bits.xcpt_pf_if, issue_slots[20].in_uop.bits.xcpt_pf_if
connect slots_20.io.in_uop.bits.fp_single, issue_slots[20].in_uop.bits.fp_single
connect slots_20.io.in_uop.bits.fp_val, issue_slots[20].in_uop.bits.fp_val
connect slots_20.io.in_uop.bits.frs3_en, issue_slots[20].in_uop.bits.frs3_en
connect slots_20.io.in_uop.bits.lrs2_rtype, issue_slots[20].in_uop.bits.lrs2_rtype
connect slots_20.io.in_uop.bits.lrs1_rtype, issue_slots[20].in_uop.bits.lrs1_rtype
connect slots_20.io.in_uop.bits.dst_rtype, issue_slots[20].in_uop.bits.dst_rtype
connect slots_20.io.in_uop.bits.ldst_val, issue_slots[20].in_uop.bits.ldst_val
connect slots_20.io.in_uop.bits.lrs3, issue_slots[20].in_uop.bits.lrs3
connect slots_20.io.in_uop.bits.lrs2, issue_slots[20].in_uop.bits.lrs2
connect slots_20.io.in_uop.bits.lrs1, issue_slots[20].in_uop.bits.lrs1
connect slots_20.io.in_uop.bits.ldst, issue_slots[20].in_uop.bits.ldst
connect slots_20.io.in_uop.bits.ldst_is_rs1, issue_slots[20].in_uop.bits.ldst_is_rs1
connect slots_20.io.in_uop.bits.flush_on_commit, issue_slots[20].in_uop.bits.flush_on_commit
connect slots_20.io.in_uop.bits.is_unique, issue_slots[20].in_uop.bits.is_unique
connect slots_20.io.in_uop.bits.is_sys_pc2epc, issue_slots[20].in_uop.bits.is_sys_pc2epc
connect slots_20.io.in_uop.bits.uses_stq, issue_slots[20].in_uop.bits.uses_stq
connect slots_20.io.in_uop.bits.uses_ldq, issue_slots[20].in_uop.bits.uses_ldq
connect slots_20.io.in_uop.bits.is_amo, issue_slots[20].in_uop.bits.is_amo
connect slots_20.io.in_uop.bits.is_fencei, issue_slots[20].in_uop.bits.is_fencei
connect slots_20.io.in_uop.bits.is_fence, issue_slots[20].in_uop.bits.is_fence
connect slots_20.io.in_uop.bits.mem_signed, issue_slots[20].in_uop.bits.mem_signed
connect slots_20.io.in_uop.bits.mem_size, issue_slots[20].in_uop.bits.mem_size
connect slots_20.io.in_uop.bits.mem_cmd, issue_slots[20].in_uop.bits.mem_cmd
connect slots_20.io.in_uop.bits.bypassable, issue_slots[20].in_uop.bits.bypassable
connect slots_20.io.in_uop.bits.exc_cause, issue_slots[20].in_uop.bits.exc_cause
connect slots_20.io.in_uop.bits.exception, issue_slots[20].in_uop.bits.exception
connect slots_20.io.in_uop.bits.stale_pdst, issue_slots[20].in_uop.bits.stale_pdst
connect slots_20.io.in_uop.bits.ppred_busy, issue_slots[20].in_uop.bits.ppred_busy
connect slots_20.io.in_uop.bits.prs3_busy, issue_slots[20].in_uop.bits.prs3_busy
connect slots_20.io.in_uop.bits.prs2_busy, issue_slots[20].in_uop.bits.prs2_busy
connect slots_20.io.in_uop.bits.prs1_busy, issue_slots[20].in_uop.bits.prs1_busy
connect slots_20.io.in_uop.bits.ppred, issue_slots[20].in_uop.bits.ppred
connect slots_20.io.in_uop.bits.prs3, issue_slots[20].in_uop.bits.prs3
connect slots_20.io.in_uop.bits.prs2, issue_slots[20].in_uop.bits.prs2
connect slots_20.io.in_uop.bits.prs1, issue_slots[20].in_uop.bits.prs1
connect slots_20.io.in_uop.bits.pdst, issue_slots[20].in_uop.bits.pdst
connect slots_20.io.in_uop.bits.rxq_idx, issue_slots[20].in_uop.bits.rxq_idx
connect slots_20.io.in_uop.bits.stq_idx, issue_slots[20].in_uop.bits.stq_idx
connect slots_20.io.in_uop.bits.ldq_idx, issue_slots[20].in_uop.bits.ldq_idx
connect slots_20.io.in_uop.bits.rob_idx, issue_slots[20].in_uop.bits.rob_idx
connect slots_20.io.in_uop.bits.csr_addr, issue_slots[20].in_uop.bits.csr_addr
connect slots_20.io.in_uop.bits.imm_packed, issue_slots[20].in_uop.bits.imm_packed
connect slots_20.io.in_uop.bits.taken, issue_slots[20].in_uop.bits.taken
connect slots_20.io.in_uop.bits.pc_lob, issue_slots[20].in_uop.bits.pc_lob
connect slots_20.io.in_uop.bits.edge_inst, issue_slots[20].in_uop.bits.edge_inst
connect slots_20.io.in_uop.bits.ftq_idx, issue_slots[20].in_uop.bits.ftq_idx
connect slots_20.io.in_uop.bits.br_tag, issue_slots[20].in_uop.bits.br_tag
connect slots_20.io.in_uop.bits.br_mask, issue_slots[20].in_uop.bits.br_mask
connect slots_20.io.in_uop.bits.is_sfb, issue_slots[20].in_uop.bits.is_sfb
connect slots_20.io.in_uop.bits.is_jal, issue_slots[20].in_uop.bits.is_jal
connect slots_20.io.in_uop.bits.is_jalr, issue_slots[20].in_uop.bits.is_jalr
connect slots_20.io.in_uop.bits.is_br, issue_slots[20].in_uop.bits.is_br
connect slots_20.io.in_uop.bits.iw_p2_poisoned, issue_slots[20].in_uop.bits.iw_p2_poisoned
connect slots_20.io.in_uop.bits.iw_p1_poisoned, issue_slots[20].in_uop.bits.iw_p1_poisoned
connect slots_20.io.in_uop.bits.iw_state, issue_slots[20].in_uop.bits.iw_state
connect slots_20.io.in_uop.bits.ctrl.is_std, issue_slots[20].in_uop.bits.ctrl.is_std
connect slots_20.io.in_uop.bits.ctrl.is_sta, issue_slots[20].in_uop.bits.ctrl.is_sta
connect slots_20.io.in_uop.bits.ctrl.is_load, issue_slots[20].in_uop.bits.ctrl.is_load
connect slots_20.io.in_uop.bits.ctrl.csr_cmd, issue_slots[20].in_uop.bits.ctrl.csr_cmd
connect slots_20.io.in_uop.bits.ctrl.fcn_dw, issue_slots[20].in_uop.bits.ctrl.fcn_dw
connect slots_20.io.in_uop.bits.ctrl.op_fcn, issue_slots[20].in_uop.bits.ctrl.op_fcn
connect slots_20.io.in_uop.bits.ctrl.imm_sel, issue_slots[20].in_uop.bits.ctrl.imm_sel
connect slots_20.io.in_uop.bits.ctrl.op2_sel, issue_slots[20].in_uop.bits.ctrl.op2_sel
connect slots_20.io.in_uop.bits.ctrl.op1_sel, issue_slots[20].in_uop.bits.ctrl.op1_sel
connect slots_20.io.in_uop.bits.ctrl.br_type, issue_slots[20].in_uop.bits.ctrl.br_type
connect slots_20.io.in_uop.bits.fu_code, issue_slots[20].in_uop.bits.fu_code
connect slots_20.io.in_uop.bits.iq_type, issue_slots[20].in_uop.bits.iq_type
connect slots_20.io.in_uop.bits.debug_pc, issue_slots[20].in_uop.bits.debug_pc
connect slots_20.io.in_uop.bits.is_rvc, issue_slots[20].in_uop.bits.is_rvc
connect slots_20.io.in_uop.bits.debug_inst, issue_slots[20].in_uop.bits.debug_inst
connect slots_20.io.in_uop.bits.inst, issue_slots[20].in_uop.bits.inst
connect slots_20.io.in_uop.bits.uopc, issue_slots[20].in_uop.bits.uopc
connect slots_20.io.in_uop.valid, issue_slots[20].in_uop.valid
connect slots_20.io.spec_ld_wakeup[0].bits, issue_slots[20].spec_ld_wakeup[0].bits
connect slots_20.io.spec_ld_wakeup[0].valid, issue_slots[20].spec_ld_wakeup[0].valid
connect slots_20.io.pred_wakeup_port.bits, issue_slots[20].pred_wakeup_port.bits
connect slots_20.io.pred_wakeup_port.valid, issue_slots[20].pred_wakeup_port.valid
connect slots_20.io.wakeup_ports[0].bits.poisoned, issue_slots[20].wakeup_ports[0].bits.poisoned
connect slots_20.io.wakeup_ports[0].bits.pdst, issue_slots[20].wakeup_ports[0].bits.pdst
connect slots_20.io.wakeup_ports[0].valid, issue_slots[20].wakeup_ports[0].valid
connect slots_20.io.wakeup_ports[1].bits.poisoned, issue_slots[20].wakeup_ports[1].bits.poisoned
connect slots_20.io.wakeup_ports[1].bits.pdst, issue_slots[20].wakeup_ports[1].bits.pdst
connect slots_20.io.wakeup_ports[1].valid, issue_slots[20].wakeup_ports[1].valid
connect slots_20.io.ldspec_miss, issue_slots[20].ldspec_miss
connect slots_20.io.clear, issue_slots[20].clear
connect slots_20.io.kill, issue_slots[20].kill
connect slots_20.io.brupdate.b2.target_offset, issue_slots[20].brupdate.b2.target_offset
connect slots_20.io.brupdate.b2.jalr_target, issue_slots[20].brupdate.b2.jalr_target
connect slots_20.io.brupdate.b2.pc_sel, issue_slots[20].brupdate.b2.pc_sel
connect slots_20.io.brupdate.b2.cfi_type, issue_slots[20].brupdate.b2.cfi_type
connect slots_20.io.brupdate.b2.taken, issue_slots[20].brupdate.b2.taken
connect slots_20.io.brupdate.b2.mispredict, issue_slots[20].brupdate.b2.mispredict
connect slots_20.io.brupdate.b2.valid, issue_slots[20].brupdate.b2.valid
connect slots_20.io.brupdate.b2.uop.debug_tsrc, issue_slots[20].brupdate.b2.uop.debug_tsrc
connect slots_20.io.brupdate.b2.uop.debug_fsrc, issue_slots[20].brupdate.b2.uop.debug_fsrc
connect slots_20.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[20].brupdate.b2.uop.bp_xcpt_if
connect slots_20.io.brupdate.b2.uop.bp_debug_if, issue_slots[20].brupdate.b2.uop.bp_debug_if
connect slots_20.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[20].brupdate.b2.uop.xcpt_ma_if
connect slots_20.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[20].brupdate.b2.uop.xcpt_ae_if
connect slots_20.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[20].brupdate.b2.uop.xcpt_pf_if
connect slots_20.io.brupdate.b2.uop.fp_single, issue_slots[20].brupdate.b2.uop.fp_single
connect slots_20.io.brupdate.b2.uop.fp_val, issue_slots[20].brupdate.b2.uop.fp_val
connect slots_20.io.brupdate.b2.uop.frs3_en, issue_slots[20].brupdate.b2.uop.frs3_en
connect slots_20.io.brupdate.b2.uop.lrs2_rtype, issue_slots[20].brupdate.b2.uop.lrs2_rtype
connect slots_20.io.brupdate.b2.uop.lrs1_rtype, issue_slots[20].brupdate.b2.uop.lrs1_rtype
connect slots_20.io.brupdate.b2.uop.dst_rtype, issue_slots[20].brupdate.b2.uop.dst_rtype
connect slots_20.io.brupdate.b2.uop.ldst_val, issue_slots[20].brupdate.b2.uop.ldst_val
connect slots_20.io.brupdate.b2.uop.lrs3, issue_slots[20].brupdate.b2.uop.lrs3
connect slots_20.io.brupdate.b2.uop.lrs2, issue_slots[20].brupdate.b2.uop.lrs2
connect slots_20.io.brupdate.b2.uop.lrs1, issue_slots[20].brupdate.b2.uop.lrs1
connect slots_20.io.brupdate.b2.uop.ldst, issue_slots[20].brupdate.b2.uop.ldst
connect slots_20.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[20].brupdate.b2.uop.ldst_is_rs1
connect slots_20.io.brupdate.b2.uop.flush_on_commit, issue_slots[20].brupdate.b2.uop.flush_on_commit
connect slots_20.io.brupdate.b2.uop.is_unique, issue_slots[20].brupdate.b2.uop.is_unique
connect slots_20.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[20].brupdate.b2.uop.is_sys_pc2epc
connect slots_20.io.brupdate.b2.uop.uses_stq, issue_slots[20].brupdate.b2.uop.uses_stq
connect slots_20.io.brupdate.b2.uop.uses_ldq, issue_slots[20].brupdate.b2.uop.uses_ldq
connect slots_20.io.brupdate.b2.uop.is_amo, issue_slots[20].brupdate.b2.uop.is_amo
connect slots_20.io.brupdate.b2.uop.is_fencei, issue_slots[20].brupdate.b2.uop.is_fencei
connect slots_20.io.brupdate.b2.uop.is_fence, issue_slots[20].brupdate.b2.uop.is_fence
connect slots_20.io.brupdate.b2.uop.mem_signed, issue_slots[20].brupdate.b2.uop.mem_signed
connect slots_20.io.brupdate.b2.uop.mem_size, issue_slots[20].brupdate.b2.uop.mem_size
connect slots_20.io.brupdate.b2.uop.mem_cmd, issue_slots[20].brupdate.b2.uop.mem_cmd
connect slots_20.io.brupdate.b2.uop.bypassable, issue_slots[20].brupdate.b2.uop.bypassable
connect slots_20.io.brupdate.b2.uop.exc_cause, issue_slots[20].brupdate.b2.uop.exc_cause
connect slots_20.io.brupdate.b2.uop.exception, issue_slots[20].brupdate.b2.uop.exception
connect slots_20.io.brupdate.b2.uop.stale_pdst, issue_slots[20].brupdate.b2.uop.stale_pdst
connect slots_20.io.brupdate.b2.uop.ppred_busy, issue_slots[20].brupdate.b2.uop.ppred_busy
connect slots_20.io.brupdate.b2.uop.prs3_busy, issue_slots[20].brupdate.b2.uop.prs3_busy
connect slots_20.io.brupdate.b2.uop.prs2_busy, issue_slots[20].brupdate.b2.uop.prs2_busy
connect slots_20.io.brupdate.b2.uop.prs1_busy, issue_slots[20].brupdate.b2.uop.prs1_busy
connect slots_20.io.brupdate.b2.uop.ppred, issue_slots[20].brupdate.b2.uop.ppred
connect slots_20.io.brupdate.b2.uop.prs3, issue_slots[20].brupdate.b2.uop.prs3
connect slots_20.io.brupdate.b2.uop.prs2, issue_slots[20].brupdate.b2.uop.prs2
connect slots_20.io.brupdate.b2.uop.prs1, issue_slots[20].brupdate.b2.uop.prs1
connect slots_20.io.brupdate.b2.uop.pdst, issue_slots[20].brupdate.b2.uop.pdst
connect slots_20.io.brupdate.b2.uop.rxq_idx, issue_slots[20].brupdate.b2.uop.rxq_idx
connect slots_20.io.brupdate.b2.uop.stq_idx, issue_slots[20].brupdate.b2.uop.stq_idx
connect slots_20.io.brupdate.b2.uop.ldq_idx, issue_slots[20].brupdate.b2.uop.ldq_idx
connect slots_20.io.brupdate.b2.uop.rob_idx, issue_slots[20].brupdate.b2.uop.rob_idx
connect slots_20.io.brupdate.b2.uop.csr_addr, issue_slots[20].brupdate.b2.uop.csr_addr
connect slots_20.io.brupdate.b2.uop.imm_packed, issue_slots[20].brupdate.b2.uop.imm_packed
connect slots_20.io.brupdate.b2.uop.taken, issue_slots[20].brupdate.b2.uop.taken
connect slots_20.io.brupdate.b2.uop.pc_lob, issue_slots[20].brupdate.b2.uop.pc_lob
connect slots_20.io.brupdate.b2.uop.edge_inst, issue_slots[20].brupdate.b2.uop.edge_inst
connect slots_20.io.brupdate.b2.uop.ftq_idx, issue_slots[20].brupdate.b2.uop.ftq_idx
connect slots_20.io.brupdate.b2.uop.br_tag, issue_slots[20].brupdate.b2.uop.br_tag
connect slots_20.io.brupdate.b2.uop.br_mask, issue_slots[20].brupdate.b2.uop.br_mask
connect slots_20.io.brupdate.b2.uop.is_sfb, issue_slots[20].brupdate.b2.uop.is_sfb
connect slots_20.io.brupdate.b2.uop.is_jal, issue_slots[20].brupdate.b2.uop.is_jal
connect slots_20.io.brupdate.b2.uop.is_jalr, issue_slots[20].brupdate.b2.uop.is_jalr
connect slots_20.io.brupdate.b2.uop.is_br, issue_slots[20].brupdate.b2.uop.is_br
connect slots_20.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[20].brupdate.b2.uop.iw_p2_poisoned
connect slots_20.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[20].brupdate.b2.uop.iw_p1_poisoned
connect slots_20.io.brupdate.b2.uop.iw_state, issue_slots[20].brupdate.b2.uop.iw_state
connect slots_20.io.brupdate.b2.uop.ctrl.is_std, issue_slots[20].brupdate.b2.uop.ctrl.is_std
connect slots_20.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[20].brupdate.b2.uop.ctrl.is_sta
connect slots_20.io.brupdate.b2.uop.ctrl.is_load, issue_slots[20].brupdate.b2.uop.ctrl.is_load
connect slots_20.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[20].brupdate.b2.uop.ctrl.csr_cmd
connect slots_20.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[20].brupdate.b2.uop.ctrl.fcn_dw
connect slots_20.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[20].brupdate.b2.uop.ctrl.op_fcn
connect slots_20.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[20].brupdate.b2.uop.ctrl.imm_sel
connect slots_20.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[20].brupdate.b2.uop.ctrl.op2_sel
connect slots_20.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[20].brupdate.b2.uop.ctrl.op1_sel
connect slots_20.io.brupdate.b2.uop.ctrl.br_type, issue_slots[20].brupdate.b2.uop.ctrl.br_type
connect slots_20.io.brupdate.b2.uop.fu_code, issue_slots[20].brupdate.b2.uop.fu_code
connect slots_20.io.brupdate.b2.uop.iq_type, issue_slots[20].brupdate.b2.uop.iq_type
connect slots_20.io.brupdate.b2.uop.debug_pc, issue_slots[20].brupdate.b2.uop.debug_pc
connect slots_20.io.brupdate.b2.uop.is_rvc, issue_slots[20].brupdate.b2.uop.is_rvc
connect slots_20.io.brupdate.b2.uop.debug_inst, issue_slots[20].brupdate.b2.uop.debug_inst
connect slots_20.io.brupdate.b2.uop.inst, issue_slots[20].brupdate.b2.uop.inst
connect slots_20.io.brupdate.b2.uop.uopc, issue_slots[20].brupdate.b2.uop.uopc
connect slots_20.io.brupdate.b1.mispredict_mask, issue_slots[20].brupdate.b1.mispredict_mask
connect slots_20.io.brupdate.b1.resolve_mask, issue_slots[20].brupdate.b1.resolve_mask
connect slots_20.io.grant, issue_slots[20].grant
connect issue_slots[20].request_hp, slots_20.io.request_hp
connect issue_slots[20].request, slots_20.io.request
connect issue_slots[20].will_be_valid, slots_20.io.will_be_valid
connect issue_slots[20].valid, slots_20.io.valid
connect issue_slots[21].debug.state, slots_21.io.debug.state
connect issue_slots[21].debug.ppred, slots_21.io.debug.ppred
connect issue_slots[21].debug.p3, slots_21.io.debug.p3
connect issue_slots[21].debug.p2, slots_21.io.debug.p2
connect issue_slots[21].debug.p1, slots_21.io.debug.p1
connect issue_slots[21].uop.debug_tsrc, slots_21.io.uop.debug_tsrc
connect issue_slots[21].uop.debug_fsrc, slots_21.io.uop.debug_fsrc
connect issue_slots[21].uop.bp_xcpt_if, slots_21.io.uop.bp_xcpt_if
connect issue_slots[21].uop.bp_debug_if, slots_21.io.uop.bp_debug_if
connect issue_slots[21].uop.xcpt_ma_if, slots_21.io.uop.xcpt_ma_if
connect issue_slots[21].uop.xcpt_ae_if, slots_21.io.uop.xcpt_ae_if
connect issue_slots[21].uop.xcpt_pf_if, slots_21.io.uop.xcpt_pf_if
connect issue_slots[21].uop.fp_single, slots_21.io.uop.fp_single
connect issue_slots[21].uop.fp_val, slots_21.io.uop.fp_val
connect issue_slots[21].uop.frs3_en, slots_21.io.uop.frs3_en
connect issue_slots[21].uop.lrs2_rtype, slots_21.io.uop.lrs2_rtype
connect issue_slots[21].uop.lrs1_rtype, slots_21.io.uop.lrs1_rtype
connect issue_slots[21].uop.dst_rtype, slots_21.io.uop.dst_rtype
connect issue_slots[21].uop.ldst_val, slots_21.io.uop.ldst_val
connect issue_slots[21].uop.lrs3, slots_21.io.uop.lrs3
connect issue_slots[21].uop.lrs2, slots_21.io.uop.lrs2
connect issue_slots[21].uop.lrs1, slots_21.io.uop.lrs1
connect issue_slots[21].uop.ldst, slots_21.io.uop.ldst
connect issue_slots[21].uop.ldst_is_rs1, slots_21.io.uop.ldst_is_rs1
connect issue_slots[21].uop.flush_on_commit, slots_21.io.uop.flush_on_commit
connect issue_slots[21].uop.is_unique, slots_21.io.uop.is_unique
connect issue_slots[21].uop.is_sys_pc2epc, slots_21.io.uop.is_sys_pc2epc
connect issue_slots[21].uop.uses_stq, slots_21.io.uop.uses_stq
connect issue_slots[21].uop.uses_ldq, slots_21.io.uop.uses_ldq
connect issue_slots[21].uop.is_amo, slots_21.io.uop.is_amo
connect issue_slots[21].uop.is_fencei, slots_21.io.uop.is_fencei
connect issue_slots[21].uop.is_fence, slots_21.io.uop.is_fence
connect issue_slots[21].uop.mem_signed, slots_21.io.uop.mem_signed
connect issue_slots[21].uop.mem_size, slots_21.io.uop.mem_size
connect issue_slots[21].uop.mem_cmd, slots_21.io.uop.mem_cmd
connect issue_slots[21].uop.bypassable, slots_21.io.uop.bypassable
connect issue_slots[21].uop.exc_cause, slots_21.io.uop.exc_cause
connect issue_slots[21].uop.exception, slots_21.io.uop.exception
connect issue_slots[21].uop.stale_pdst, slots_21.io.uop.stale_pdst
connect issue_slots[21].uop.ppred_busy, slots_21.io.uop.ppred_busy
connect issue_slots[21].uop.prs3_busy, slots_21.io.uop.prs3_busy
connect issue_slots[21].uop.prs2_busy, slots_21.io.uop.prs2_busy
connect issue_slots[21].uop.prs1_busy, slots_21.io.uop.prs1_busy
connect issue_slots[21].uop.ppred, slots_21.io.uop.ppred
connect issue_slots[21].uop.prs3, slots_21.io.uop.prs3
connect issue_slots[21].uop.prs2, slots_21.io.uop.prs2
connect issue_slots[21].uop.prs1, slots_21.io.uop.prs1
connect issue_slots[21].uop.pdst, slots_21.io.uop.pdst
connect issue_slots[21].uop.rxq_idx, slots_21.io.uop.rxq_idx
connect issue_slots[21].uop.stq_idx, slots_21.io.uop.stq_idx
connect issue_slots[21].uop.ldq_idx, slots_21.io.uop.ldq_idx
connect issue_slots[21].uop.rob_idx, slots_21.io.uop.rob_idx
connect issue_slots[21].uop.csr_addr, slots_21.io.uop.csr_addr
connect issue_slots[21].uop.imm_packed, slots_21.io.uop.imm_packed
connect issue_slots[21].uop.taken, slots_21.io.uop.taken
connect issue_slots[21].uop.pc_lob, slots_21.io.uop.pc_lob
connect issue_slots[21].uop.edge_inst, slots_21.io.uop.edge_inst
connect issue_slots[21].uop.ftq_idx, slots_21.io.uop.ftq_idx
connect issue_slots[21].uop.br_tag, slots_21.io.uop.br_tag
connect issue_slots[21].uop.br_mask, slots_21.io.uop.br_mask
connect issue_slots[21].uop.is_sfb, slots_21.io.uop.is_sfb
connect issue_slots[21].uop.is_jal, slots_21.io.uop.is_jal
connect issue_slots[21].uop.is_jalr, slots_21.io.uop.is_jalr
connect issue_slots[21].uop.is_br, slots_21.io.uop.is_br
connect issue_slots[21].uop.iw_p2_poisoned, slots_21.io.uop.iw_p2_poisoned
connect issue_slots[21].uop.iw_p1_poisoned, slots_21.io.uop.iw_p1_poisoned
connect issue_slots[21].uop.iw_state, slots_21.io.uop.iw_state
connect issue_slots[21].uop.ctrl.is_std, slots_21.io.uop.ctrl.is_std
connect issue_slots[21].uop.ctrl.is_sta, slots_21.io.uop.ctrl.is_sta
connect issue_slots[21].uop.ctrl.is_load, slots_21.io.uop.ctrl.is_load
connect issue_slots[21].uop.ctrl.csr_cmd, slots_21.io.uop.ctrl.csr_cmd
connect issue_slots[21].uop.ctrl.fcn_dw, slots_21.io.uop.ctrl.fcn_dw
connect issue_slots[21].uop.ctrl.op_fcn, slots_21.io.uop.ctrl.op_fcn
connect issue_slots[21].uop.ctrl.imm_sel, slots_21.io.uop.ctrl.imm_sel
connect issue_slots[21].uop.ctrl.op2_sel, slots_21.io.uop.ctrl.op2_sel
connect issue_slots[21].uop.ctrl.op1_sel, slots_21.io.uop.ctrl.op1_sel
connect issue_slots[21].uop.ctrl.br_type, slots_21.io.uop.ctrl.br_type
connect issue_slots[21].uop.fu_code, slots_21.io.uop.fu_code
connect issue_slots[21].uop.iq_type, slots_21.io.uop.iq_type
connect issue_slots[21].uop.debug_pc, slots_21.io.uop.debug_pc
connect issue_slots[21].uop.is_rvc, slots_21.io.uop.is_rvc
connect issue_slots[21].uop.debug_inst, slots_21.io.uop.debug_inst
connect issue_slots[21].uop.inst, slots_21.io.uop.inst
connect issue_slots[21].uop.uopc, slots_21.io.uop.uopc
connect issue_slots[21].out_uop.debug_tsrc, slots_21.io.out_uop.debug_tsrc
connect issue_slots[21].out_uop.debug_fsrc, slots_21.io.out_uop.debug_fsrc
connect issue_slots[21].out_uop.bp_xcpt_if, slots_21.io.out_uop.bp_xcpt_if
connect issue_slots[21].out_uop.bp_debug_if, slots_21.io.out_uop.bp_debug_if
connect issue_slots[21].out_uop.xcpt_ma_if, slots_21.io.out_uop.xcpt_ma_if
connect issue_slots[21].out_uop.xcpt_ae_if, slots_21.io.out_uop.xcpt_ae_if
connect issue_slots[21].out_uop.xcpt_pf_if, slots_21.io.out_uop.xcpt_pf_if
connect issue_slots[21].out_uop.fp_single, slots_21.io.out_uop.fp_single
connect issue_slots[21].out_uop.fp_val, slots_21.io.out_uop.fp_val
connect issue_slots[21].out_uop.frs3_en, slots_21.io.out_uop.frs3_en
connect issue_slots[21].out_uop.lrs2_rtype, slots_21.io.out_uop.lrs2_rtype
connect issue_slots[21].out_uop.lrs1_rtype, slots_21.io.out_uop.lrs1_rtype
connect issue_slots[21].out_uop.dst_rtype, slots_21.io.out_uop.dst_rtype
connect issue_slots[21].out_uop.ldst_val, slots_21.io.out_uop.ldst_val
connect issue_slots[21].out_uop.lrs3, slots_21.io.out_uop.lrs3
connect issue_slots[21].out_uop.lrs2, slots_21.io.out_uop.lrs2
connect issue_slots[21].out_uop.lrs1, slots_21.io.out_uop.lrs1
connect issue_slots[21].out_uop.ldst, slots_21.io.out_uop.ldst
connect issue_slots[21].out_uop.ldst_is_rs1, slots_21.io.out_uop.ldst_is_rs1
connect issue_slots[21].out_uop.flush_on_commit, slots_21.io.out_uop.flush_on_commit
connect issue_slots[21].out_uop.is_unique, slots_21.io.out_uop.is_unique
connect issue_slots[21].out_uop.is_sys_pc2epc, slots_21.io.out_uop.is_sys_pc2epc
connect issue_slots[21].out_uop.uses_stq, slots_21.io.out_uop.uses_stq
connect issue_slots[21].out_uop.uses_ldq, slots_21.io.out_uop.uses_ldq
connect issue_slots[21].out_uop.is_amo, slots_21.io.out_uop.is_amo
connect issue_slots[21].out_uop.is_fencei, slots_21.io.out_uop.is_fencei
connect issue_slots[21].out_uop.is_fence, slots_21.io.out_uop.is_fence
connect issue_slots[21].out_uop.mem_signed, slots_21.io.out_uop.mem_signed
connect issue_slots[21].out_uop.mem_size, slots_21.io.out_uop.mem_size
connect issue_slots[21].out_uop.mem_cmd, slots_21.io.out_uop.mem_cmd
connect issue_slots[21].out_uop.bypassable, slots_21.io.out_uop.bypassable
connect issue_slots[21].out_uop.exc_cause, slots_21.io.out_uop.exc_cause
connect issue_slots[21].out_uop.exception, slots_21.io.out_uop.exception
connect issue_slots[21].out_uop.stale_pdst, slots_21.io.out_uop.stale_pdst
connect issue_slots[21].out_uop.ppred_busy, slots_21.io.out_uop.ppred_busy
connect issue_slots[21].out_uop.prs3_busy, slots_21.io.out_uop.prs3_busy
connect issue_slots[21].out_uop.prs2_busy, slots_21.io.out_uop.prs2_busy
connect issue_slots[21].out_uop.prs1_busy, slots_21.io.out_uop.prs1_busy
connect issue_slots[21].out_uop.ppred, slots_21.io.out_uop.ppred
connect issue_slots[21].out_uop.prs3, slots_21.io.out_uop.prs3
connect issue_slots[21].out_uop.prs2, slots_21.io.out_uop.prs2
connect issue_slots[21].out_uop.prs1, slots_21.io.out_uop.prs1
connect issue_slots[21].out_uop.pdst, slots_21.io.out_uop.pdst
connect issue_slots[21].out_uop.rxq_idx, slots_21.io.out_uop.rxq_idx
connect issue_slots[21].out_uop.stq_idx, slots_21.io.out_uop.stq_idx
connect issue_slots[21].out_uop.ldq_idx, slots_21.io.out_uop.ldq_idx
connect issue_slots[21].out_uop.rob_idx, slots_21.io.out_uop.rob_idx
connect issue_slots[21].out_uop.csr_addr, slots_21.io.out_uop.csr_addr
connect issue_slots[21].out_uop.imm_packed, slots_21.io.out_uop.imm_packed
connect issue_slots[21].out_uop.taken, slots_21.io.out_uop.taken
connect issue_slots[21].out_uop.pc_lob, slots_21.io.out_uop.pc_lob
connect issue_slots[21].out_uop.edge_inst, slots_21.io.out_uop.edge_inst
connect issue_slots[21].out_uop.ftq_idx, slots_21.io.out_uop.ftq_idx
connect issue_slots[21].out_uop.br_tag, slots_21.io.out_uop.br_tag
connect issue_slots[21].out_uop.br_mask, slots_21.io.out_uop.br_mask
connect issue_slots[21].out_uop.is_sfb, slots_21.io.out_uop.is_sfb
connect issue_slots[21].out_uop.is_jal, slots_21.io.out_uop.is_jal
connect issue_slots[21].out_uop.is_jalr, slots_21.io.out_uop.is_jalr
connect issue_slots[21].out_uop.is_br, slots_21.io.out_uop.is_br
connect issue_slots[21].out_uop.iw_p2_poisoned, slots_21.io.out_uop.iw_p2_poisoned
connect issue_slots[21].out_uop.iw_p1_poisoned, slots_21.io.out_uop.iw_p1_poisoned
connect issue_slots[21].out_uop.iw_state, slots_21.io.out_uop.iw_state
connect issue_slots[21].out_uop.ctrl.is_std, slots_21.io.out_uop.ctrl.is_std
connect issue_slots[21].out_uop.ctrl.is_sta, slots_21.io.out_uop.ctrl.is_sta
connect issue_slots[21].out_uop.ctrl.is_load, slots_21.io.out_uop.ctrl.is_load
connect issue_slots[21].out_uop.ctrl.csr_cmd, slots_21.io.out_uop.ctrl.csr_cmd
connect issue_slots[21].out_uop.ctrl.fcn_dw, slots_21.io.out_uop.ctrl.fcn_dw
connect issue_slots[21].out_uop.ctrl.op_fcn, slots_21.io.out_uop.ctrl.op_fcn
connect issue_slots[21].out_uop.ctrl.imm_sel, slots_21.io.out_uop.ctrl.imm_sel
connect issue_slots[21].out_uop.ctrl.op2_sel, slots_21.io.out_uop.ctrl.op2_sel
connect issue_slots[21].out_uop.ctrl.op1_sel, slots_21.io.out_uop.ctrl.op1_sel
connect issue_slots[21].out_uop.ctrl.br_type, slots_21.io.out_uop.ctrl.br_type
connect issue_slots[21].out_uop.fu_code, slots_21.io.out_uop.fu_code
connect issue_slots[21].out_uop.iq_type, slots_21.io.out_uop.iq_type
connect issue_slots[21].out_uop.debug_pc, slots_21.io.out_uop.debug_pc
connect issue_slots[21].out_uop.is_rvc, slots_21.io.out_uop.is_rvc
connect issue_slots[21].out_uop.debug_inst, slots_21.io.out_uop.debug_inst
connect issue_slots[21].out_uop.inst, slots_21.io.out_uop.inst
connect issue_slots[21].out_uop.uopc, slots_21.io.out_uop.uopc
connect slots_21.io.in_uop.bits.debug_tsrc, issue_slots[21].in_uop.bits.debug_tsrc
connect slots_21.io.in_uop.bits.debug_fsrc, issue_slots[21].in_uop.bits.debug_fsrc
connect slots_21.io.in_uop.bits.bp_xcpt_if, issue_slots[21].in_uop.bits.bp_xcpt_if
connect slots_21.io.in_uop.bits.bp_debug_if, issue_slots[21].in_uop.bits.bp_debug_if
connect slots_21.io.in_uop.bits.xcpt_ma_if, issue_slots[21].in_uop.bits.xcpt_ma_if
connect slots_21.io.in_uop.bits.xcpt_ae_if, issue_slots[21].in_uop.bits.xcpt_ae_if
connect slots_21.io.in_uop.bits.xcpt_pf_if, issue_slots[21].in_uop.bits.xcpt_pf_if
connect slots_21.io.in_uop.bits.fp_single, issue_slots[21].in_uop.bits.fp_single
connect slots_21.io.in_uop.bits.fp_val, issue_slots[21].in_uop.bits.fp_val
connect slots_21.io.in_uop.bits.frs3_en, issue_slots[21].in_uop.bits.frs3_en
connect slots_21.io.in_uop.bits.lrs2_rtype, issue_slots[21].in_uop.bits.lrs2_rtype
connect slots_21.io.in_uop.bits.lrs1_rtype, issue_slots[21].in_uop.bits.lrs1_rtype
connect slots_21.io.in_uop.bits.dst_rtype, issue_slots[21].in_uop.bits.dst_rtype
connect slots_21.io.in_uop.bits.ldst_val, issue_slots[21].in_uop.bits.ldst_val
connect slots_21.io.in_uop.bits.lrs3, issue_slots[21].in_uop.bits.lrs3
connect slots_21.io.in_uop.bits.lrs2, issue_slots[21].in_uop.bits.lrs2
connect slots_21.io.in_uop.bits.lrs1, issue_slots[21].in_uop.bits.lrs1
connect slots_21.io.in_uop.bits.ldst, issue_slots[21].in_uop.bits.ldst
connect slots_21.io.in_uop.bits.ldst_is_rs1, issue_slots[21].in_uop.bits.ldst_is_rs1
connect slots_21.io.in_uop.bits.flush_on_commit, issue_slots[21].in_uop.bits.flush_on_commit
connect slots_21.io.in_uop.bits.is_unique, issue_slots[21].in_uop.bits.is_unique
connect slots_21.io.in_uop.bits.is_sys_pc2epc, issue_slots[21].in_uop.bits.is_sys_pc2epc
connect slots_21.io.in_uop.bits.uses_stq, issue_slots[21].in_uop.bits.uses_stq
connect slots_21.io.in_uop.bits.uses_ldq, issue_slots[21].in_uop.bits.uses_ldq
connect slots_21.io.in_uop.bits.is_amo, issue_slots[21].in_uop.bits.is_amo
connect slots_21.io.in_uop.bits.is_fencei, issue_slots[21].in_uop.bits.is_fencei
connect slots_21.io.in_uop.bits.is_fence, issue_slots[21].in_uop.bits.is_fence
connect slots_21.io.in_uop.bits.mem_signed, issue_slots[21].in_uop.bits.mem_signed
connect slots_21.io.in_uop.bits.mem_size, issue_slots[21].in_uop.bits.mem_size
connect slots_21.io.in_uop.bits.mem_cmd, issue_slots[21].in_uop.bits.mem_cmd
connect slots_21.io.in_uop.bits.bypassable, issue_slots[21].in_uop.bits.bypassable
connect slots_21.io.in_uop.bits.exc_cause, issue_slots[21].in_uop.bits.exc_cause
connect slots_21.io.in_uop.bits.exception, issue_slots[21].in_uop.bits.exception
connect slots_21.io.in_uop.bits.stale_pdst, issue_slots[21].in_uop.bits.stale_pdst
connect slots_21.io.in_uop.bits.ppred_busy, issue_slots[21].in_uop.bits.ppred_busy
connect slots_21.io.in_uop.bits.prs3_busy, issue_slots[21].in_uop.bits.prs3_busy
connect slots_21.io.in_uop.bits.prs2_busy, issue_slots[21].in_uop.bits.prs2_busy
connect slots_21.io.in_uop.bits.prs1_busy, issue_slots[21].in_uop.bits.prs1_busy
connect slots_21.io.in_uop.bits.ppred, issue_slots[21].in_uop.bits.ppred
connect slots_21.io.in_uop.bits.prs3, issue_slots[21].in_uop.bits.prs3
connect slots_21.io.in_uop.bits.prs2, issue_slots[21].in_uop.bits.prs2
connect slots_21.io.in_uop.bits.prs1, issue_slots[21].in_uop.bits.prs1
connect slots_21.io.in_uop.bits.pdst, issue_slots[21].in_uop.bits.pdst
connect slots_21.io.in_uop.bits.rxq_idx, issue_slots[21].in_uop.bits.rxq_idx
connect slots_21.io.in_uop.bits.stq_idx, issue_slots[21].in_uop.bits.stq_idx
connect slots_21.io.in_uop.bits.ldq_idx, issue_slots[21].in_uop.bits.ldq_idx
connect slots_21.io.in_uop.bits.rob_idx, issue_slots[21].in_uop.bits.rob_idx
connect slots_21.io.in_uop.bits.csr_addr, issue_slots[21].in_uop.bits.csr_addr
connect slots_21.io.in_uop.bits.imm_packed, issue_slots[21].in_uop.bits.imm_packed
connect slots_21.io.in_uop.bits.taken, issue_slots[21].in_uop.bits.taken
connect slots_21.io.in_uop.bits.pc_lob, issue_slots[21].in_uop.bits.pc_lob
connect slots_21.io.in_uop.bits.edge_inst, issue_slots[21].in_uop.bits.edge_inst
connect slots_21.io.in_uop.bits.ftq_idx, issue_slots[21].in_uop.bits.ftq_idx
connect slots_21.io.in_uop.bits.br_tag, issue_slots[21].in_uop.bits.br_tag
connect slots_21.io.in_uop.bits.br_mask, issue_slots[21].in_uop.bits.br_mask
connect slots_21.io.in_uop.bits.is_sfb, issue_slots[21].in_uop.bits.is_sfb
connect slots_21.io.in_uop.bits.is_jal, issue_slots[21].in_uop.bits.is_jal
connect slots_21.io.in_uop.bits.is_jalr, issue_slots[21].in_uop.bits.is_jalr
connect slots_21.io.in_uop.bits.is_br, issue_slots[21].in_uop.bits.is_br
connect slots_21.io.in_uop.bits.iw_p2_poisoned, issue_slots[21].in_uop.bits.iw_p2_poisoned
connect slots_21.io.in_uop.bits.iw_p1_poisoned, issue_slots[21].in_uop.bits.iw_p1_poisoned
connect slots_21.io.in_uop.bits.iw_state, issue_slots[21].in_uop.bits.iw_state
connect slots_21.io.in_uop.bits.ctrl.is_std, issue_slots[21].in_uop.bits.ctrl.is_std
connect slots_21.io.in_uop.bits.ctrl.is_sta, issue_slots[21].in_uop.bits.ctrl.is_sta
connect slots_21.io.in_uop.bits.ctrl.is_load, issue_slots[21].in_uop.bits.ctrl.is_load
connect slots_21.io.in_uop.bits.ctrl.csr_cmd, issue_slots[21].in_uop.bits.ctrl.csr_cmd
connect slots_21.io.in_uop.bits.ctrl.fcn_dw, issue_slots[21].in_uop.bits.ctrl.fcn_dw
connect slots_21.io.in_uop.bits.ctrl.op_fcn, issue_slots[21].in_uop.bits.ctrl.op_fcn
connect slots_21.io.in_uop.bits.ctrl.imm_sel, issue_slots[21].in_uop.bits.ctrl.imm_sel
connect slots_21.io.in_uop.bits.ctrl.op2_sel, issue_slots[21].in_uop.bits.ctrl.op2_sel
connect slots_21.io.in_uop.bits.ctrl.op1_sel, issue_slots[21].in_uop.bits.ctrl.op1_sel
connect slots_21.io.in_uop.bits.ctrl.br_type, issue_slots[21].in_uop.bits.ctrl.br_type
connect slots_21.io.in_uop.bits.fu_code, issue_slots[21].in_uop.bits.fu_code
connect slots_21.io.in_uop.bits.iq_type, issue_slots[21].in_uop.bits.iq_type
connect slots_21.io.in_uop.bits.debug_pc, issue_slots[21].in_uop.bits.debug_pc
connect slots_21.io.in_uop.bits.is_rvc, issue_slots[21].in_uop.bits.is_rvc
connect slots_21.io.in_uop.bits.debug_inst, issue_slots[21].in_uop.bits.debug_inst
connect slots_21.io.in_uop.bits.inst, issue_slots[21].in_uop.bits.inst
connect slots_21.io.in_uop.bits.uopc, issue_slots[21].in_uop.bits.uopc
connect slots_21.io.in_uop.valid, issue_slots[21].in_uop.valid
connect slots_21.io.spec_ld_wakeup[0].bits, issue_slots[21].spec_ld_wakeup[0].bits
connect slots_21.io.spec_ld_wakeup[0].valid, issue_slots[21].spec_ld_wakeup[0].valid
connect slots_21.io.pred_wakeup_port.bits, issue_slots[21].pred_wakeup_port.bits
connect slots_21.io.pred_wakeup_port.valid, issue_slots[21].pred_wakeup_port.valid
connect slots_21.io.wakeup_ports[0].bits.poisoned, issue_slots[21].wakeup_ports[0].bits.poisoned
connect slots_21.io.wakeup_ports[0].bits.pdst, issue_slots[21].wakeup_ports[0].bits.pdst
connect slots_21.io.wakeup_ports[0].valid, issue_slots[21].wakeup_ports[0].valid
connect slots_21.io.wakeup_ports[1].bits.poisoned, issue_slots[21].wakeup_ports[1].bits.poisoned
connect slots_21.io.wakeup_ports[1].bits.pdst, issue_slots[21].wakeup_ports[1].bits.pdst
connect slots_21.io.wakeup_ports[1].valid, issue_slots[21].wakeup_ports[1].valid
connect slots_21.io.ldspec_miss, issue_slots[21].ldspec_miss
connect slots_21.io.clear, issue_slots[21].clear
connect slots_21.io.kill, issue_slots[21].kill
connect slots_21.io.brupdate.b2.target_offset, issue_slots[21].brupdate.b2.target_offset
connect slots_21.io.brupdate.b2.jalr_target, issue_slots[21].brupdate.b2.jalr_target
connect slots_21.io.brupdate.b2.pc_sel, issue_slots[21].brupdate.b2.pc_sel
connect slots_21.io.brupdate.b2.cfi_type, issue_slots[21].brupdate.b2.cfi_type
connect slots_21.io.brupdate.b2.taken, issue_slots[21].brupdate.b2.taken
connect slots_21.io.brupdate.b2.mispredict, issue_slots[21].brupdate.b2.mispredict
connect slots_21.io.brupdate.b2.valid, issue_slots[21].brupdate.b2.valid
connect slots_21.io.brupdate.b2.uop.debug_tsrc, issue_slots[21].brupdate.b2.uop.debug_tsrc
connect slots_21.io.brupdate.b2.uop.debug_fsrc, issue_slots[21].brupdate.b2.uop.debug_fsrc
connect slots_21.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[21].brupdate.b2.uop.bp_xcpt_if
connect slots_21.io.brupdate.b2.uop.bp_debug_if, issue_slots[21].brupdate.b2.uop.bp_debug_if
connect slots_21.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[21].brupdate.b2.uop.xcpt_ma_if
connect slots_21.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[21].brupdate.b2.uop.xcpt_ae_if
connect slots_21.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[21].brupdate.b2.uop.xcpt_pf_if
connect slots_21.io.brupdate.b2.uop.fp_single, issue_slots[21].brupdate.b2.uop.fp_single
connect slots_21.io.brupdate.b2.uop.fp_val, issue_slots[21].brupdate.b2.uop.fp_val
connect slots_21.io.brupdate.b2.uop.frs3_en, issue_slots[21].brupdate.b2.uop.frs3_en
connect slots_21.io.brupdate.b2.uop.lrs2_rtype, issue_slots[21].brupdate.b2.uop.lrs2_rtype
connect slots_21.io.brupdate.b2.uop.lrs1_rtype, issue_slots[21].brupdate.b2.uop.lrs1_rtype
connect slots_21.io.brupdate.b2.uop.dst_rtype, issue_slots[21].brupdate.b2.uop.dst_rtype
connect slots_21.io.brupdate.b2.uop.ldst_val, issue_slots[21].brupdate.b2.uop.ldst_val
connect slots_21.io.brupdate.b2.uop.lrs3, issue_slots[21].brupdate.b2.uop.lrs3
connect slots_21.io.brupdate.b2.uop.lrs2, issue_slots[21].brupdate.b2.uop.lrs2
connect slots_21.io.brupdate.b2.uop.lrs1, issue_slots[21].brupdate.b2.uop.lrs1
connect slots_21.io.brupdate.b2.uop.ldst, issue_slots[21].brupdate.b2.uop.ldst
connect slots_21.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[21].brupdate.b2.uop.ldst_is_rs1
connect slots_21.io.brupdate.b2.uop.flush_on_commit, issue_slots[21].brupdate.b2.uop.flush_on_commit
connect slots_21.io.brupdate.b2.uop.is_unique, issue_slots[21].brupdate.b2.uop.is_unique
connect slots_21.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[21].brupdate.b2.uop.is_sys_pc2epc
connect slots_21.io.brupdate.b2.uop.uses_stq, issue_slots[21].brupdate.b2.uop.uses_stq
connect slots_21.io.brupdate.b2.uop.uses_ldq, issue_slots[21].brupdate.b2.uop.uses_ldq
connect slots_21.io.brupdate.b2.uop.is_amo, issue_slots[21].brupdate.b2.uop.is_amo
connect slots_21.io.brupdate.b2.uop.is_fencei, issue_slots[21].brupdate.b2.uop.is_fencei
connect slots_21.io.brupdate.b2.uop.is_fence, issue_slots[21].brupdate.b2.uop.is_fence
connect slots_21.io.brupdate.b2.uop.mem_signed, issue_slots[21].brupdate.b2.uop.mem_signed
connect slots_21.io.brupdate.b2.uop.mem_size, issue_slots[21].brupdate.b2.uop.mem_size
connect slots_21.io.brupdate.b2.uop.mem_cmd, issue_slots[21].brupdate.b2.uop.mem_cmd
connect slots_21.io.brupdate.b2.uop.bypassable, issue_slots[21].brupdate.b2.uop.bypassable
connect slots_21.io.brupdate.b2.uop.exc_cause, issue_slots[21].brupdate.b2.uop.exc_cause
connect slots_21.io.brupdate.b2.uop.exception, issue_slots[21].brupdate.b2.uop.exception
connect slots_21.io.brupdate.b2.uop.stale_pdst, issue_slots[21].brupdate.b2.uop.stale_pdst
connect slots_21.io.brupdate.b2.uop.ppred_busy, issue_slots[21].brupdate.b2.uop.ppred_busy
connect slots_21.io.brupdate.b2.uop.prs3_busy, issue_slots[21].brupdate.b2.uop.prs3_busy
connect slots_21.io.brupdate.b2.uop.prs2_busy, issue_slots[21].brupdate.b2.uop.prs2_busy
connect slots_21.io.brupdate.b2.uop.prs1_busy, issue_slots[21].brupdate.b2.uop.prs1_busy
connect slots_21.io.brupdate.b2.uop.ppred, issue_slots[21].brupdate.b2.uop.ppred
connect slots_21.io.brupdate.b2.uop.prs3, issue_slots[21].brupdate.b2.uop.prs3
connect slots_21.io.brupdate.b2.uop.prs2, issue_slots[21].brupdate.b2.uop.prs2
connect slots_21.io.brupdate.b2.uop.prs1, issue_slots[21].brupdate.b2.uop.prs1
connect slots_21.io.brupdate.b2.uop.pdst, issue_slots[21].brupdate.b2.uop.pdst
connect slots_21.io.brupdate.b2.uop.rxq_idx, issue_slots[21].brupdate.b2.uop.rxq_idx
connect slots_21.io.brupdate.b2.uop.stq_idx, issue_slots[21].brupdate.b2.uop.stq_idx
connect slots_21.io.brupdate.b2.uop.ldq_idx, issue_slots[21].brupdate.b2.uop.ldq_idx
connect slots_21.io.brupdate.b2.uop.rob_idx, issue_slots[21].brupdate.b2.uop.rob_idx
connect slots_21.io.brupdate.b2.uop.csr_addr, issue_slots[21].brupdate.b2.uop.csr_addr
connect slots_21.io.brupdate.b2.uop.imm_packed, issue_slots[21].brupdate.b2.uop.imm_packed
connect slots_21.io.brupdate.b2.uop.taken, issue_slots[21].brupdate.b2.uop.taken
connect slots_21.io.brupdate.b2.uop.pc_lob, issue_slots[21].brupdate.b2.uop.pc_lob
connect slots_21.io.brupdate.b2.uop.edge_inst, issue_slots[21].brupdate.b2.uop.edge_inst
connect slots_21.io.brupdate.b2.uop.ftq_idx, issue_slots[21].brupdate.b2.uop.ftq_idx
connect slots_21.io.brupdate.b2.uop.br_tag, issue_slots[21].brupdate.b2.uop.br_tag
connect slots_21.io.brupdate.b2.uop.br_mask, issue_slots[21].brupdate.b2.uop.br_mask
connect slots_21.io.brupdate.b2.uop.is_sfb, issue_slots[21].brupdate.b2.uop.is_sfb
connect slots_21.io.brupdate.b2.uop.is_jal, issue_slots[21].brupdate.b2.uop.is_jal
connect slots_21.io.brupdate.b2.uop.is_jalr, issue_slots[21].brupdate.b2.uop.is_jalr
connect slots_21.io.brupdate.b2.uop.is_br, issue_slots[21].brupdate.b2.uop.is_br
connect slots_21.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[21].brupdate.b2.uop.iw_p2_poisoned
connect slots_21.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[21].brupdate.b2.uop.iw_p1_poisoned
connect slots_21.io.brupdate.b2.uop.iw_state, issue_slots[21].brupdate.b2.uop.iw_state
connect slots_21.io.brupdate.b2.uop.ctrl.is_std, issue_slots[21].brupdate.b2.uop.ctrl.is_std
connect slots_21.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[21].brupdate.b2.uop.ctrl.is_sta
connect slots_21.io.brupdate.b2.uop.ctrl.is_load, issue_slots[21].brupdate.b2.uop.ctrl.is_load
connect slots_21.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[21].brupdate.b2.uop.ctrl.csr_cmd
connect slots_21.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[21].brupdate.b2.uop.ctrl.fcn_dw
connect slots_21.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[21].brupdate.b2.uop.ctrl.op_fcn
connect slots_21.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[21].brupdate.b2.uop.ctrl.imm_sel
connect slots_21.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[21].brupdate.b2.uop.ctrl.op2_sel
connect slots_21.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[21].brupdate.b2.uop.ctrl.op1_sel
connect slots_21.io.brupdate.b2.uop.ctrl.br_type, issue_slots[21].brupdate.b2.uop.ctrl.br_type
connect slots_21.io.brupdate.b2.uop.fu_code, issue_slots[21].brupdate.b2.uop.fu_code
connect slots_21.io.brupdate.b2.uop.iq_type, issue_slots[21].brupdate.b2.uop.iq_type
connect slots_21.io.brupdate.b2.uop.debug_pc, issue_slots[21].brupdate.b2.uop.debug_pc
connect slots_21.io.brupdate.b2.uop.is_rvc, issue_slots[21].brupdate.b2.uop.is_rvc
connect slots_21.io.brupdate.b2.uop.debug_inst, issue_slots[21].brupdate.b2.uop.debug_inst
connect slots_21.io.brupdate.b2.uop.inst, issue_slots[21].brupdate.b2.uop.inst
connect slots_21.io.brupdate.b2.uop.uopc, issue_slots[21].brupdate.b2.uop.uopc
connect slots_21.io.brupdate.b1.mispredict_mask, issue_slots[21].brupdate.b1.mispredict_mask
connect slots_21.io.brupdate.b1.resolve_mask, issue_slots[21].brupdate.b1.resolve_mask
connect slots_21.io.grant, issue_slots[21].grant
connect issue_slots[21].request_hp, slots_21.io.request_hp
connect issue_slots[21].request, slots_21.io.request
connect issue_slots[21].will_be_valid, slots_21.io.will_be_valid
connect issue_slots[21].valid, slots_21.io.valid
connect issue_slots[22].debug.state, slots_22.io.debug.state
connect issue_slots[22].debug.ppred, slots_22.io.debug.ppred
connect issue_slots[22].debug.p3, slots_22.io.debug.p3
connect issue_slots[22].debug.p2, slots_22.io.debug.p2
connect issue_slots[22].debug.p1, slots_22.io.debug.p1
connect issue_slots[22].uop.debug_tsrc, slots_22.io.uop.debug_tsrc
connect issue_slots[22].uop.debug_fsrc, slots_22.io.uop.debug_fsrc
connect issue_slots[22].uop.bp_xcpt_if, slots_22.io.uop.bp_xcpt_if
connect issue_slots[22].uop.bp_debug_if, slots_22.io.uop.bp_debug_if
connect issue_slots[22].uop.xcpt_ma_if, slots_22.io.uop.xcpt_ma_if
connect issue_slots[22].uop.xcpt_ae_if, slots_22.io.uop.xcpt_ae_if
connect issue_slots[22].uop.xcpt_pf_if, slots_22.io.uop.xcpt_pf_if
connect issue_slots[22].uop.fp_single, slots_22.io.uop.fp_single
connect issue_slots[22].uop.fp_val, slots_22.io.uop.fp_val
connect issue_slots[22].uop.frs3_en, slots_22.io.uop.frs3_en
connect issue_slots[22].uop.lrs2_rtype, slots_22.io.uop.lrs2_rtype
connect issue_slots[22].uop.lrs1_rtype, slots_22.io.uop.lrs1_rtype
connect issue_slots[22].uop.dst_rtype, slots_22.io.uop.dst_rtype
connect issue_slots[22].uop.ldst_val, slots_22.io.uop.ldst_val
connect issue_slots[22].uop.lrs3, slots_22.io.uop.lrs3
connect issue_slots[22].uop.lrs2, slots_22.io.uop.lrs2
connect issue_slots[22].uop.lrs1, slots_22.io.uop.lrs1
connect issue_slots[22].uop.ldst, slots_22.io.uop.ldst
connect issue_slots[22].uop.ldst_is_rs1, slots_22.io.uop.ldst_is_rs1
connect issue_slots[22].uop.flush_on_commit, slots_22.io.uop.flush_on_commit
connect issue_slots[22].uop.is_unique, slots_22.io.uop.is_unique
connect issue_slots[22].uop.is_sys_pc2epc, slots_22.io.uop.is_sys_pc2epc
connect issue_slots[22].uop.uses_stq, slots_22.io.uop.uses_stq
connect issue_slots[22].uop.uses_ldq, slots_22.io.uop.uses_ldq
connect issue_slots[22].uop.is_amo, slots_22.io.uop.is_amo
connect issue_slots[22].uop.is_fencei, slots_22.io.uop.is_fencei
connect issue_slots[22].uop.is_fence, slots_22.io.uop.is_fence
connect issue_slots[22].uop.mem_signed, slots_22.io.uop.mem_signed
connect issue_slots[22].uop.mem_size, slots_22.io.uop.mem_size
connect issue_slots[22].uop.mem_cmd, slots_22.io.uop.mem_cmd
connect issue_slots[22].uop.bypassable, slots_22.io.uop.bypassable
connect issue_slots[22].uop.exc_cause, slots_22.io.uop.exc_cause
connect issue_slots[22].uop.exception, slots_22.io.uop.exception
connect issue_slots[22].uop.stale_pdst, slots_22.io.uop.stale_pdst
connect issue_slots[22].uop.ppred_busy, slots_22.io.uop.ppred_busy
connect issue_slots[22].uop.prs3_busy, slots_22.io.uop.prs3_busy
connect issue_slots[22].uop.prs2_busy, slots_22.io.uop.prs2_busy
connect issue_slots[22].uop.prs1_busy, slots_22.io.uop.prs1_busy
connect issue_slots[22].uop.ppred, slots_22.io.uop.ppred
connect issue_slots[22].uop.prs3, slots_22.io.uop.prs3
connect issue_slots[22].uop.prs2, slots_22.io.uop.prs2
connect issue_slots[22].uop.prs1, slots_22.io.uop.prs1
connect issue_slots[22].uop.pdst, slots_22.io.uop.pdst
connect issue_slots[22].uop.rxq_idx, slots_22.io.uop.rxq_idx
connect issue_slots[22].uop.stq_idx, slots_22.io.uop.stq_idx
connect issue_slots[22].uop.ldq_idx, slots_22.io.uop.ldq_idx
connect issue_slots[22].uop.rob_idx, slots_22.io.uop.rob_idx
connect issue_slots[22].uop.csr_addr, slots_22.io.uop.csr_addr
connect issue_slots[22].uop.imm_packed, slots_22.io.uop.imm_packed
connect issue_slots[22].uop.taken, slots_22.io.uop.taken
connect issue_slots[22].uop.pc_lob, slots_22.io.uop.pc_lob
connect issue_slots[22].uop.edge_inst, slots_22.io.uop.edge_inst
connect issue_slots[22].uop.ftq_idx, slots_22.io.uop.ftq_idx
connect issue_slots[22].uop.br_tag, slots_22.io.uop.br_tag
connect issue_slots[22].uop.br_mask, slots_22.io.uop.br_mask
connect issue_slots[22].uop.is_sfb, slots_22.io.uop.is_sfb
connect issue_slots[22].uop.is_jal, slots_22.io.uop.is_jal
connect issue_slots[22].uop.is_jalr, slots_22.io.uop.is_jalr
connect issue_slots[22].uop.is_br, slots_22.io.uop.is_br
connect issue_slots[22].uop.iw_p2_poisoned, slots_22.io.uop.iw_p2_poisoned
connect issue_slots[22].uop.iw_p1_poisoned, slots_22.io.uop.iw_p1_poisoned
connect issue_slots[22].uop.iw_state, slots_22.io.uop.iw_state
connect issue_slots[22].uop.ctrl.is_std, slots_22.io.uop.ctrl.is_std
connect issue_slots[22].uop.ctrl.is_sta, slots_22.io.uop.ctrl.is_sta
connect issue_slots[22].uop.ctrl.is_load, slots_22.io.uop.ctrl.is_load
connect issue_slots[22].uop.ctrl.csr_cmd, slots_22.io.uop.ctrl.csr_cmd
connect issue_slots[22].uop.ctrl.fcn_dw, slots_22.io.uop.ctrl.fcn_dw
connect issue_slots[22].uop.ctrl.op_fcn, slots_22.io.uop.ctrl.op_fcn
connect issue_slots[22].uop.ctrl.imm_sel, slots_22.io.uop.ctrl.imm_sel
connect issue_slots[22].uop.ctrl.op2_sel, slots_22.io.uop.ctrl.op2_sel
connect issue_slots[22].uop.ctrl.op1_sel, slots_22.io.uop.ctrl.op1_sel
connect issue_slots[22].uop.ctrl.br_type, slots_22.io.uop.ctrl.br_type
connect issue_slots[22].uop.fu_code, slots_22.io.uop.fu_code
connect issue_slots[22].uop.iq_type, slots_22.io.uop.iq_type
connect issue_slots[22].uop.debug_pc, slots_22.io.uop.debug_pc
connect issue_slots[22].uop.is_rvc, slots_22.io.uop.is_rvc
connect issue_slots[22].uop.debug_inst, slots_22.io.uop.debug_inst
connect issue_slots[22].uop.inst, slots_22.io.uop.inst
connect issue_slots[22].uop.uopc, slots_22.io.uop.uopc
connect issue_slots[22].out_uop.debug_tsrc, slots_22.io.out_uop.debug_tsrc
connect issue_slots[22].out_uop.debug_fsrc, slots_22.io.out_uop.debug_fsrc
connect issue_slots[22].out_uop.bp_xcpt_if, slots_22.io.out_uop.bp_xcpt_if
connect issue_slots[22].out_uop.bp_debug_if, slots_22.io.out_uop.bp_debug_if
connect issue_slots[22].out_uop.xcpt_ma_if, slots_22.io.out_uop.xcpt_ma_if
connect issue_slots[22].out_uop.xcpt_ae_if, slots_22.io.out_uop.xcpt_ae_if
connect issue_slots[22].out_uop.xcpt_pf_if, slots_22.io.out_uop.xcpt_pf_if
connect issue_slots[22].out_uop.fp_single, slots_22.io.out_uop.fp_single
connect issue_slots[22].out_uop.fp_val, slots_22.io.out_uop.fp_val
connect issue_slots[22].out_uop.frs3_en, slots_22.io.out_uop.frs3_en
connect issue_slots[22].out_uop.lrs2_rtype, slots_22.io.out_uop.lrs2_rtype
connect issue_slots[22].out_uop.lrs1_rtype, slots_22.io.out_uop.lrs1_rtype
connect issue_slots[22].out_uop.dst_rtype, slots_22.io.out_uop.dst_rtype
connect issue_slots[22].out_uop.ldst_val, slots_22.io.out_uop.ldst_val
connect issue_slots[22].out_uop.lrs3, slots_22.io.out_uop.lrs3
connect issue_slots[22].out_uop.lrs2, slots_22.io.out_uop.lrs2
connect issue_slots[22].out_uop.lrs1, slots_22.io.out_uop.lrs1
connect issue_slots[22].out_uop.ldst, slots_22.io.out_uop.ldst
connect issue_slots[22].out_uop.ldst_is_rs1, slots_22.io.out_uop.ldst_is_rs1
connect issue_slots[22].out_uop.flush_on_commit, slots_22.io.out_uop.flush_on_commit
connect issue_slots[22].out_uop.is_unique, slots_22.io.out_uop.is_unique
connect issue_slots[22].out_uop.is_sys_pc2epc, slots_22.io.out_uop.is_sys_pc2epc
connect issue_slots[22].out_uop.uses_stq, slots_22.io.out_uop.uses_stq
connect issue_slots[22].out_uop.uses_ldq, slots_22.io.out_uop.uses_ldq
connect issue_slots[22].out_uop.is_amo, slots_22.io.out_uop.is_amo
connect issue_slots[22].out_uop.is_fencei, slots_22.io.out_uop.is_fencei
connect issue_slots[22].out_uop.is_fence, slots_22.io.out_uop.is_fence
connect issue_slots[22].out_uop.mem_signed, slots_22.io.out_uop.mem_signed
connect issue_slots[22].out_uop.mem_size, slots_22.io.out_uop.mem_size
connect issue_slots[22].out_uop.mem_cmd, slots_22.io.out_uop.mem_cmd
connect issue_slots[22].out_uop.bypassable, slots_22.io.out_uop.bypassable
connect issue_slots[22].out_uop.exc_cause, slots_22.io.out_uop.exc_cause
connect issue_slots[22].out_uop.exception, slots_22.io.out_uop.exception
connect issue_slots[22].out_uop.stale_pdst, slots_22.io.out_uop.stale_pdst
connect issue_slots[22].out_uop.ppred_busy, slots_22.io.out_uop.ppred_busy
connect issue_slots[22].out_uop.prs3_busy, slots_22.io.out_uop.prs3_busy
connect issue_slots[22].out_uop.prs2_busy, slots_22.io.out_uop.prs2_busy
connect issue_slots[22].out_uop.prs1_busy, slots_22.io.out_uop.prs1_busy
connect issue_slots[22].out_uop.ppred, slots_22.io.out_uop.ppred
connect issue_slots[22].out_uop.prs3, slots_22.io.out_uop.prs3
connect issue_slots[22].out_uop.prs2, slots_22.io.out_uop.prs2
connect issue_slots[22].out_uop.prs1, slots_22.io.out_uop.prs1
connect issue_slots[22].out_uop.pdst, slots_22.io.out_uop.pdst
connect issue_slots[22].out_uop.rxq_idx, slots_22.io.out_uop.rxq_idx
connect issue_slots[22].out_uop.stq_idx, slots_22.io.out_uop.stq_idx
connect issue_slots[22].out_uop.ldq_idx, slots_22.io.out_uop.ldq_idx
connect issue_slots[22].out_uop.rob_idx, slots_22.io.out_uop.rob_idx
connect issue_slots[22].out_uop.csr_addr, slots_22.io.out_uop.csr_addr
connect issue_slots[22].out_uop.imm_packed, slots_22.io.out_uop.imm_packed
connect issue_slots[22].out_uop.taken, slots_22.io.out_uop.taken
connect issue_slots[22].out_uop.pc_lob, slots_22.io.out_uop.pc_lob
connect issue_slots[22].out_uop.edge_inst, slots_22.io.out_uop.edge_inst
connect issue_slots[22].out_uop.ftq_idx, slots_22.io.out_uop.ftq_idx
connect issue_slots[22].out_uop.br_tag, slots_22.io.out_uop.br_tag
connect issue_slots[22].out_uop.br_mask, slots_22.io.out_uop.br_mask
connect issue_slots[22].out_uop.is_sfb, slots_22.io.out_uop.is_sfb
connect issue_slots[22].out_uop.is_jal, slots_22.io.out_uop.is_jal
connect issue_slots[22].out_uop.is_jalr, slots_22.io.out_uop.is_jalr
connect issue_slots[22].out_uop.is_br, slots_22.io.out_uop.is_br
connect issue_slots[22].out_uop.iw_p2_poisoned, slots_22.io.out_uop.iw_p2_poisoned
connect issue_slots[22].out_uop.iw_p1_poisoned, slots_22.io.out_uop.iw_p1_poisoned
connect issue_slots[22].out_uop.iw_state, slots_22.io.out_uop.iw_state
connect issue_slots[22].out_uop.ctrl.is_std, slots_22.io.out_uop.ctrl.is_std
connect issue_slots[22].out_uop.ctrl.is_sta, slots_22.io.out_uop.ctrl.is_sta
connect issue_slots[22].out_uop.ctrl.is_load, slots_22.io.out_uop.ctrl.is_load
connect issue_slots[22].out_uop.ctrl.csr_cmd, slots_22.io.out_uop.ctrl.csr_cmd
connect issue_slots[22].out_uop.ctrl.fcn_dw, slots_22.io.out_uop.ctrl.fcn_dw
connect issue_slots[22].out_uop.ctrl.op_fcn, slots_22.io.out_uop.ctrl.op_fcn
connect issue_slots[22].out_uop.ctrl.imm_sel, slots_22.io.out_uop.ctrl.imm_sel
connect issue_slots[22].out_uop.ctrl.op2_sel, slots_22.io.out_uop.ctrl.op2_sel
connect issue_slots[22].out_uop.ctrl.op1_sel, slots_22.io.out_uop.ctrl.op1_sel
connect issue_slots[22].out_uop.ctrl.br_type, slots_22.io.out_uop.ctrl.br_type
connect issue_slots[22].out_uop.fu_code, slots_22.io.out_uop.fu_code
connect issue_slots[22].out_uop.iq_type, slots_22.io.out_uop.iq_type
connect issue_slots[22].out_uop.debug_pc, slots_22.io.out_uop.debug_pc
connect issue_slots[22].out_uop.is_rvc, slots_22.io.out_uop.is_rvc
connect issue_slots[22].out_uop.debug_inst, slots_22.io.out_uop.debug_inst
connect issue_slots[22].out_uop.inst, slots_22.io.out_uop.inst
connect issue_slots[22].out_uop.uopc, slots_22.io.out_uop.uopc
connect slots_22.io.in_uop.bits.debug_tsrc, issue_slots[22].in_uop.bits.debug_tsrc
connect slots_22.io.in_uop.bits.debug_fsrc, issue_slots[22].in_uop.bits.debug_fsrc
connect slots_22.io.in_uop.bits.bp_xcpt_if, issue_slots[22].in_uop.bits.bp_xcpt_if
connect slots_22.io.in_uop.bits.bp_debug_if, issue_slots[22].in_uop.bits.bp_debug_if
connect slots_22.io.in_uop.bits.xcpt_ma_if, issue_slots[22].in_uop.bits.xcpt_ma_if
connect slots_22.io.in_uop.bits.xcpt_ae_if, issue_slots[22].in_uop.bits.xcpt_ae_if
connect slots_22.io.in_uop.bits.xcpt_pf_if, issue_slots[22].in_uop.bits.xcpt_pf_if
connect slots_22.io.in_uop.bits.fp_single, issue_slots[22].in_uop.bits.fp_single
connect slots_22.io.in_uop.bits.fp_val, issue_slots[22].in_uop.bits.fp_val
connect slots_22.io.in_uop.bits.frs3_en, issue_slots[22].in_uop.bits.frs3_en
connect slots_22.io.in_uop.bits.lrs2_rtype, issue_slots[22].in_uop.bits.lrs2_rtype
connect slots_22.io.in_uop.bits.lrs1_rtype, issue_slots[22].in_uop.bits.lrs1_rtype
connect slots_22.io.in_uop.bits.dst_rtype, issue_slots[22].in_uop.bits.dst_rtype
connect slots_22.io.in_uop.bits.ldst_val, issue_slots[22].in_uop.bits.ldst_val
connect slots_22.io.in_uop.bits.lrs3, issue_slots[22].in_uop.bits.lrs3
connect slots_22.io.in_uop.bits.lrs2, issue_slots[22].in_uop.bits.lrs2
connect slots_22.io.in_uop.bits.lrs1, issue_slots[22].in_uop.bits.lrs1
connect slots_22.io.in_uop.bits.ldst, issue_slots[22].in_uop.bits.ldst
connect slots_22.io.in_uop.bits.ldst_is_rs1, issue_slots[22].in_uop.bits.ldst_is_rs1
connect slots_22.io.in_uop.bits.flush_on_commit, issue_slots[22].in_uop.bits.flush_on_commit
connect slots_22.io.in_uop.bits.is_unique, issue_slots[22].in_uop.bits.is_unique
connect slots_22.io.in_uop.bits.is_sys_pc2epc, issue_slots[22].in_uop.bits.is_sys_pc2epc
connect slots_22.io.in_uop.bits.uses_stq, issue_slots[22].in_uop.bits.uses_stq
connect slots_22.io.in_uop.bits.uses_ldq, issue_slots[22].in_uop.bits.uses_ldq
connect slots_22.io.in_uop.bits.is_amo, issue_slots[22].in_uop.bits.is_amo
connect slots_22.io.in_uop.bits.is_fencei, issue_slots[22].in_uop.bits.is_fencei
connect slots_22.io.in_uop.bits.is_fence, issue_slots[22].in_uop.bits.is_fence
connect slots_22.io.in_uop.bits.mem_signed, issue_slots[22].in_uop.bits.mem_signed
connect slots_22.io.in_uop.bits.mem_size, issue_slots[22].in_uop.bits.mem_size
connect slots_22.io.in_uop.bits.mem_cmd, issue_slots[22].in_uop.bits.mem_cmd
connect slots_22.io.in_uop.bits.bypassable, issue_slots[22].in_uop.bits.bypassable
connect slots_22.io.in_uop.bits.exc_cause, issue_slots[22].in_uop.bits.exc_cause
connect slots_22.io.in_uop.bits.exception, issue_slots[22].in_uop.bits.exception
connect slots_22.io.in_uop.bits.stale_pdst, issue_slots[22].in_uop.bits.stale_pdst
connect slots_22.io.in_uop.bits.ppred_busy, issue_slots[22].in_uop.bits.ppred_busy
connect slots_22.io.in_uop.bits.prs3_busy, issue_slots[22].in_uop.bits.prs3_busy
connect slots_22.io.in_uop.bits.prs2_busy, issue_slots[22].in_uop.bits.prs2_busy
connect slots_22.io.in_uop.bits.prs1_busy, issue_slots[22].in_uop.bits.prs1_busy
connect slots_22.io.in_uop.bits.ppred, issue_slots[22].in_uop.bits.ppred
connect slots_22.io.in_uop.bits.prs3, issue_slots[22].in_uop.bits.prs3
connect slots_22.io.in_uop.bits.prs2, issue_slots[22].in_uop.bits.prs2
connect slots_22.io.in_uop.bits.prs1, issue_slots[22].in_uop.bits.prs1
connect slots_22.io.in_uop.bits.pdst, issue_slots[22].in_uop.bits.pdst
connect slots_22.io.in_uop.bits.rxq_idx, issue_slots[22].in_uop.bits.rxq_idx
connect slots_22.io.in_uop.bits.stq_idx, issue_slots[22].in_uop.bits.stq_idx
connect slots_22.io.in_uop.bits.ldq_idx, issue_slots[22].in_uop.bits.ldq_idx
connect slots_22.io.in_uop.bits.rob_idx, issue_slots[22].in_uop.bits.rob_idx
connect slots_22.io.in_uop.bits.csr_addr, issue_slots[22].in_uop.bits.csr_addr
connect slots_22.io.in_uop.bits.imm_packed, issue_slots[22].in_uop.bits.imm_packed
connect slots_22.io.in_uop.bits.taken, issue_slots[22].in_uop.bits.taken
connect slots_22.io.in_uop.bits.pc_lob, issue_slots[22].in_uop.bits.pc_lob
connect slots_22.io.in_uop.bits.edge_inst, issue_slots[22].in_uop.bits.edge_inst
connect slots_22.io.in_uop.bits.ftq_idx, issue_slots[22].in_uop.bits.ftq_idx
connect slots_22.io.in_uop.bits.br_tag, issue_slots[22].in_uop.bits.br_tag
connect slots_22.io.in_uop.bits.br_mask, issue_slots[22].in_uop.bits.br_mask
connect slots_22.io.in_uop.bits.is_sfb, issue_slots[22].in_uop.bits.is_sfb
connect slots_22.io.in_uop.bits.is_jal, issue_slots[22].in_uop.bits.is_jal
connect slots_22.io.in_uop.bits.is_jalr, issue_slots[22].in_uop.bits.is_jalr
connect slots_22.io.in_uop.bits.is_br, issue_slots[22].in_uop.bits.is_br
connect slots_22.io.in_uop.bits.iw_p2_poisoned, issue_slots[22].in_uop.bits.iw_p2_poisoned
connect slots_22.io.in_uop.bits.iw_p1_poisoned, issue_slots[22].in_uop.bits.iw_p1_poisoned
connect slots_22.io.in_uop.bits.iw_state, issue_slots[22].in_uop.bits.iw_state
connect slots_22.io.in_uop.bits.ctrl.is_std, issue_slots[22].in_uop.bits.ctrl.is_std
connect slots_22.io.in_uop.bits.ctrl.is_sta, issue_slots[22].in_uop.bits.ctrl.is_sta
connect slots_22.io.in_uop.bits.ctrl.is_load, issue_slots[22].in_uop.bits.ctrl.is_load
connect slots_22.io.in_uop.bits.ctrl.csr_cmd, issue_slots[22].in_uop.bits.ctrl.csr_cmd
connect slots_22.io.in_uop.bits.ctrl.fcn_dw, issue_slots[22].in_uop.bits.ctrl.fcn_dw
connect slots_22.io.in_uop.bits.ctrl.op_fcn, issue_slots[22].in_uop.bits.ctrl.op_fcn
connect slots_22.io.in_uop.bits.ctrl.imm_sel, issue_slots[22].in_uop.bits.ctrl.imm_sel
connect slots_22.io.in_uop.bits.ctrl.op2_sel, issue_slots[22].in_uop.bits.ctrl.op2_sel
connect slots_22.io.in_uop.bits.ctrl.op1_sel, issue_slots[22].in_uop.bits.ctrl.op1_sel
connect slots_22.io.in_uop.bits.ctrl.br_type, issue_slots[22].in_uop.bits.ctrl.br_type
connect slots_22.io.in_uop.bits.fu_code, issue_slots[22].in_uop.bits.fu_code
connect slots_22.io.in_uop.bits.iq_type, issue_slots[22].in_uop.bits.iq_type
connect slots_22.io.in_uop.bits.debug_pc, issue_slots[22].in_uop.bits.debug_pc
connect slots_22.io.in_uop.bits.is_rvc, issue_slots[22].in_uop.bits.is_rvc
connect slots_22.io.in_uop.bits.debug_inst, issue_slots[22].in_uop.bits.debug_inst
connect slots_22.io.in_uop.bits.inst, issue_slots[22].in_uop.bits.inst
connect slots_22.io.in_uop.bits.uopc, issue_slots[22].in_uop.bits.uopc
connect slots_22.io.in_uop.valid, issue_slots[22].in_uop.valid
connect slots_22.io.spec_ld_wakeup[0].bits, issue_slots[22].spec_ld_wakeup[0].bits
connect slots_22.io.spec_ld_wakeup[0].valid, issue_slots[22].spec_ld_wakeup[0].valid
connect slots_22.io.pred_wakeup_port.bits, issue_slots[22].pred_wakeup_port.bits
connect slots_22.io.pred_wakeup_port.valid, issue_slots[22].pred_wakeup_port.valid
connect slots_22.io.wakeup_ports[0].bits.poisoned, issue_slots[22].wakeup_ports[0].bits.poisoned
connect slots_22.io.wakeup_ports[0].bits.pdst, issue_slots[22].wakeup_ports[0].bits.pdst
connect slots_22.io.wakeup_ports[0].valid, issue_slots[22].wakeup_ports[0].valid
connect slots_22.io.wakeup_ports[1].bits.poisoned, issue_slots[22].wakeup_ports[1].bits.poisoned
connect slots_22.io.wakeup_ports[1].bits.pdst, issue_slots[22].wakeup_ports[1].bits.pdst
connect slots_22.io.wakeup_ports[1].valid, issue_slots[22].wakeup_ports[1].valid
connect slots_22.io.ldspec_miss, issue_slots[22].ldspec_miss
connect slots_22.io.clear, issue_slots[22].clear
connect slots_22.io.kill, issue_slots[22].kill
connect slots_22.io.brupdate.b2.target_offset, issue_slots[22].brupdate.b2.target_offset
connect slots_22.io.brupdate.b2.jalr_target, issue_slots[22].brupdate.b2.jalr_target
connect slots_22.io.brupdate.b2.pc_sel, issue_slots[22].brupdate.b2.pc_sel
connect slots_22.io.brupdate.b2.cfi_type, issue_slots[22].brupdate.b2.cfi_type
connect slots_22.io.brupdate.b2.taken, issue_slots[22].brupdate.b2.taken
connect slots_22.io.brupdate.b2.mispredict, issue_slots[22].brupdate.b2.mispredict
connect slots_22.io.brupdate.b2.valid, issue_slots[22].brupdate.b2.valid
connect slots_22.io.brupdate.b2.uop.debug_tsrc, issue_slots[22].brupdate.b2.uop.debug_tsrc
connect slots_22.io.brupdate.b2.uop.debug_fsrc, issue_slots[22].brupdate.b2.uop.debug_fsrc
connect slots_22.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[22].brupdate.b2.uop.bp_xcpt_if
connect slots_22.io.brupdate.b2.uop.bp_debug_if, issue_slots[22].brupdate.b2.uop.bp_debug_if
connect slots_22.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[22].brupdate.b2.uop.xcpt_ma_if
connect slots_22.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[22].brupdate.b2.uop.xcpt_ae_if
connect slots_22.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[22].brupdate.b2.uop.xcpt_pf_if
connect slots_22.io.brupdate.b2.uop.fp_single, issue_slots[22].brupdate.b2.uop.fp_single
connect slots_22.io.brupdate.b2.uop.fp_val, issue_slots[22].brupdate.b2.uop.fp_val
connect slots_22.io.brupdate.b2.uop.frs3_en, issue_slots[22].brupdate.b2.uop.frs3_en
connect slots_22.io.brupdate.b2.uop.lrs2_rtype, issue_slots[22].brupdate.b2.uop.lrs2_rtype
connect slots_22.io.brupdate.b2.uop.lrs1_rtype, issue_slots[22].brupdate.b2.uop.lrs1_rtype
connect slots_22.io.brupdate.b2.uop.dst_rtype, issue_slots[22].brupdate.b2.uop.dst_rtype
connect slots_22.io.brupdate.b2.uop.ldst_val, issue_slots[22].brupdate.b2.uop.ldst_val
connect slots_22.io.brupdate.b2.uop.lrs3, issue_slots[22].brupdate.b2.uop.lrs3
connect slots_22.io.brupdate.b2.uop.lrs2, issue_slots[22].brupdate.b2.uop.lrs2
connect slots_22.io.brupdate.b2.uop.lrs1, issue_slots[22].brupdate.b2.uop.lrs1
connect slots_22.io.brupdate.b2.uop.ldst, issue_slots[22].brupdate.b2.uop.ldst
connect slots_22.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[22].brupdate.b2.uop.ldst_is_rs1
connect slots_22.io.brupdate.b2.uop.flush_on_commit, issue_slots[22].brupdate.b2.uop.flush_on_commit
connect slots_22.io.brupdate.b2.uop.is_unique, issue_slots[22].brupdate.b2.uop.is_unique
connect slots_22.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[22].brupdate.b2.uop.is_sys_pc2epc
connect slots_22.io.brupdate.b2.uop.uses_stq, issue_slots[22].brupdate.b2.uop.uses_stq
connect slots_22.io.brupdate.b2.uop.uses_ldq, issue_slots[22].brupdate.b2.uop.uses_ldq
connect slots_22.io.brupdate.b2.uop.is_amo, issue_slots[22].brupdate.b2.uop.is_amo
connect slots_22.io.brupdate.b2.uop.is_fencei, issue_slots[22].brupdate.b2.uop.is_fencei
connect slots_22.io.brupdate.b2.uop.is_fence, issue_slots[22].brupdate.b2.uop.is_fence
connect slots_22.io.brupdate.b2.uop.mem_signed, issue_slots[22].brupdate.b2.uop.mem_signed
connect slots_22.io.brupdate.b2.uop.mem_size, issue_slots[22].brupdate.b2.uop.mem_size
connect slots_22.io.brupdate.b2.uop.mem_cmd, issue_slots[22].brupdate.b2.uop.mem_cmd
connect slots_22.io.brupdate.b2.uop.bypassable, issue_slots[22].brupdate.b2.uop.bypassable
connect slots_22.io.brupdate.b2.uop.exc_cause, issue_slots[22].brupdate.b2.uop.exc_cause
connect slots_22.io.brupdate.b2.uop.exception, issue_slots[22].brupdate.b2.uop.exception
connect slots_22.io.brupdate.b2.uop.stale_pdst, issue_slots[22].brupdate.b2.uop.stale_pdst
connect slots_22.io.brupdate.b2.uop.ppred_busy, issue_slots[22].brupdate.b2.uop.ppred_busy
connect slots_22.io.brupdate.b2.uop.prs3_busy, issue_slots[22].brupdate.b2.uop.prs3_busy
connect slots_22.io.brupdate.b2.uop.prs2_busy, issue_slots[22].brupdate.b2.uop.prs2_busy
connect slots_22.io.brupdate.b2.uop.prs1_busy, issue_slots[22].brupdate.b2.uop.prs1_busy
connect slots_22.io.brupdate.b2.uop.ppred, issue_slots[22].brupdate.b2.uop.ppred
connect slots_22.io.brupdate.b2.uop.prs3, issue_slots[22].brupdate.b2.uop.prs3
connect slots_22.io.brupdate.b2.uop.prs2, issue_slots[22].brupdate.b2.uop.prs2
connect slots_22.io.brupdate.b2.uop.prs1, issue_slots[22].brupdate.b2.uop.prs1
connect slots_22.io.brupdate.b2.uop.pdst, issue_slots[22].brupdate.b2.uop.pdst
connect slots_22.io.brupdate.b2.uop.rxq_idx, issue_slots[22].brupdate.b2.uop.rxq_idx
connect slots_22.io.brupdate.b2.uop.stq_idx, issue_slots[22].brupdate.b2.uop.stq_idx
connect slots_22.io.brupdate.b2.uop.ldq_idx, issue_slots[22].brupdate.b2.uop.ldq_idx
connect slots_22.io.brupdate.b2.uop.rob_idx, issue_slots[22].brupdate.b2.uop.rob_idx
connect slots_22.io.brupdate.b2.uop.csr_addr, issue_slots[22].brupdate.b2.uop.csr_addr
connect slots_22.io.brupdate.b2.uop.imm_packed, issue_slots[22].brupdate.b2.uop.imm_packed
connect slots_22.io.brupdate.b2.uop.taken, issue_slots[22].brupdate.b2.uop.taken
connect slots_22.io.brupdate.b2.uop.pc_lob, issue_slots[22].brupdate.b2.uop.pc_lob
connect slots_22.io.brupdate.b2.uop.edge_inst, issue_slots[22].brupdate.b2.uop.edge_inst
connect slots_22.io.brupdate.b2.uop.ftq_idx, issue_slots[22].brupdate.b2.uop.ftq_idx
connect slots_22.io.brupdate.b2.uop.br_tag, issue_slots[22].brupdate.b2.uop.br_tag
connect slots_22.io.brupdate.b2.uop.br_mask, issue_slots[22].brupdate.b2.uop.br_mask
connect slots_22.io.brupdate.b2.uop.is_sfb, issue_slots[22].brupdate.b2.uop.is_sfb
connect slots_22.io.brupdate.b2.uop.is_jal, issue_slots[22].brupdate.b2.uop.is_jal
connect slots_22.io.brupdate.b2.uop.is_jalr, issue_slots[22].brupdate.b2.uop.is_jalr
connect slots_22.io.brupdate.b2.uop.is_br, issue_slots[22].brupdate.b2.uop.is_br
connect slots_22.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[22].brupdate.b2.uop.iw_p2_poisoned
connect slots_22.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[22].brupdate.b2.uop.iw_p1_poisoned
connect slots_22.io.brupdate.b2.uop.iw_state, issue_slots[22].brupdate.b2.uop.iw_state
connect slots_22.io.brupdate.b2.uop.ctrl.is_std, issue_slots[22].brupdate.b2.uop.ctrl.is_std
connect slots_22.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[22].brupdate.b2.uop.ctrl.is_sta
connect slots_22.io.brupdate.b2.uop.ctrl.is_load, issue_slots[22].brupdate.b2.uop.ctrl.is_load
connect slots_22.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[22].brupdate.b2.uop.ctrl.csr_cmd
connect slots_22.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[22].brupdate.b2.uop.ctrl.fcn_dw
connect slots_22.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[22].brupdate.b2.uop.ctrl.op_fcn
connect slots_22.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[22].brupdate.b2.uop.ctrl.imm_sel
connect slots_22.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[22].brupdate.b2.uop.ctrl.op2_sel
connect slots_22.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[22].brupdate.b2.uop.ctrl.op1_sel
connect slots_22.io.brupdate.b2.uop.ctrl.br_type, issue_slots[22].brupdate.b2.uop.ctrl.br_type
connect slots_22.io.brupdate.b2.uop.fu_code, issue_slots[22].brupdate.b2.uop.fu_code
connect slots_22.io.brupdate.b2.uop.iq_type, issue_slots[22].brupdate.b2.uop.iq_type
connect slots_22.io.brupdate.b2.uop.debug_pc, issue_slots[22].brupdate.b2.uop.debug_pc
connect slots_22.io.brupdate.b2.uop.is_rvc, issue_slots[22].brupdate.b2.uop.is_rvc
connect slots_22.io.brupdate.b2.uop.debug_inst, issue_slots[22].brupdate.b2.uop.debug_inst
connect slots_22.io.brupdate.b2.uop.inst, issue_slots[22].brupdate.b2.uop.inst
connect slots_22.io.brupdate.b2.uop.uopc, issue_slots[22].brupdate.b2.uop.uopc
connect slots_22.io.brupdate.b1.mispredict_mask, issue_slots[22].brupdate.b1.mispredict_mask
connect slots_22.io.brupdate.b1.resolve_mask, issue_slots[22].brupdate.b1.resolve_mask
connect slots_22.io.grant, issue_slots[22].grant
connect issue_slots[22].request_hp, slots_22.io.request_hp
connect issue_slots[22].request, slots_22.io.request
connect issue_slots[22].will_be_valid, slots_22.io.will_be_valid
connect issue_slots[22].valid, slots_22.io.valid
connect issue_slots[23].debug.state, slots_23.io.debug.state
connect issue_slots[23].debug.ppred, slots_23.io.debug.ppred
connect issue_slots[23].debug.p3, slots_23.io.debug.p3
connect issue_slots[23].debug.p2, slots_23.io.debug.p2
connect issue_slots[23].debug.p1, slots_23.io.debug.p1
connect issue_slots[23].uop.debug_tsrc, slots_23.io.uop.debug_tsrc
connect issue_slots[23].uop.debug_fsrc, slots_23.io.uop.debug_fsrc
connect issue_slots[23].uop.bp_xcpt_if, slots_23.io.uop.bp_xcpt_if
connect issue_slots[23].uop.bp_debug_if, slots_23.io.uop.bp_debug_if
connect issue_slots[23].uop.xcpt_ma_if, slots_23.io.uop.xcpt_ma_if
connect issue_slots[23].uop.xcpt_ae_if, slots_23.io.uop.xcpt_ae_if
connect issue_slots[23].uop.xcpt_pf_if, slots_23.io.uop.xcpt_pf_if
connect issue_slots[23].uop.fp_single, slots_23.io.uop.fp_single
connect issue_slots[23].uop.fp_val, slots_23.io.uop.fp_val
connect issue_slots[23].uop.frs3_en, slots_23.io.uop.frs3_en
connect issue_slots[23].uop.lrs2_rtype, slots_23.io.uop.lrs2_rtype
connect issue_slots[23].uop.lrs1_rtype, slots_23.io.uop.lrs1_rtype
connect issue_slots[23].uop.dst_rtype, slots_23.io.uop.dst_rtype
connect issue_slots[23].uop.ldst_val, slots_23.io.uop.ldst_val
connect issue_slots[23].uop.lrs3, slots_23.io.uop.lrs3
connect issue_slots[23].uop.lrs2, slots_23.io.uop.lrs2
connect issue_slots[23].uop.lrs1, slots_23.io.uop.lrs1
connect issue_slots[23].uop.ldst, slots_23.io.uop.ldst
connect issue_slots[23].uop.ldst_is_rs1, slots_23.io.uop.ldst_is_rs1
connect issue_slots[23].uop.flush_on_commit, slots_23.io.uop.flush_on_commit
connect issue_slots[23].uop.is_unique, slots_23.io.uop.is_unique
connect issue_slots[23].uop.is_sys_pc2epc, slots_23.io.uop.is_sys_pc2epc
connect issue_slots[23].uop.uses_stq, slots_23.io.uop.uses_stq
connect issue_slots[23].uop.uses_ldq, slots_23.io.uop.uses_ldq
connect issue_slots[23].uop.is_amo, slots_23.io.uop.is_amo
connect issue_slots[23].uop.is_fencei, slots_23.io.uop.is_fencei
connect issue_slots[23].uop.is_fence, slots_23.io.uop.is_fence
connect issue_slots[23].uop.mem_signed, slots_23.io.uop.mem_signed
connect issue_slots[23].uop.mem_size, slots_23.io.uop.mem_size
connect issue_slots[23].uop.mem_cmd, slots_23.io.uop.mem_cmd
connect issue_slots[23].uop.bypassable, slots_23.io.uop.bypassable
connect issue_slots[23].uop.exc_cause, slots_23.io.uop.exc_cause
connect issue_slots[23].uop.exception, slots_23.io.uop.exception
connect issue_slots[23].uop.stale_pdst, slots_23.io.uop.stale_pdst
connect issue_slots[23].uop.ppred_busy, slots_23.io.uop.ppred_busy
connect issue_slots[23].uop.prs3_busy, slots_23.io.uop.prs3_busy
connect issue_slots[23].uop.prs2_busy, slots_23.io.uop.prs2_busy
connect issue_slots[23].uop.prs1_busy, slots_23.io.uop.prs1_busy
connect issue_slots[23].uop.ppred, slots_23.io.uop.ppred
connect issue_slots[23].uop.prs3, slots_23.io.uop.prs3
connect issue_slots[23].uop.prs2, slots_23.io.uop.prs2
connect issue_slots[23].uop.prs1, slots_23.io.uop.prs1
connect issue_slots[23].uop.pdst, slots_23.io.uop.pdst
connect issue_slots[23].uop.rxq_idx, slots_23.io.uop.rxq_idx
connect issue_slots[23].uop.stq_idx, slots_23.io.uop.stq_idx
connect issue_slots[23].uop.ldq_idx, slots_23.io.uop.ldq_idx
connect issue_slots[23].uop.rob_idx, slots_23.io.uop.rob_idx
connect issue_slots[23].uop.csr_addr, slots_23.io.uop.csr_addr
connect issue_slots[23].uop.imm_packed, slots_23.io.uop.imm_packed
connect issue_slots[23].uop.taken, slots_23.io.uop.taken
connect issue_slots[23].uop.pc_lob, slots_23.io.uop.pc_lob
connect issue_slots[23].uop.edge_inst, slots_23.io.uop.edge_inst
connect issue_slots[23].uop.ftq_idx, slots_23.io.uop.ftq_idx
connect issue_slots[23].uop.br_tag, slots_23.io.uop.br_tag
connect issue_slots[23].uop.br_mask, slots_23.io.uop.br_mask
connect issue_slots[23].uop.is_sfb, slots_23.io.uop.is_sfb
connect issue_slots[23].uop.is_jal, slots_23.io.uop.is_jal
connect issue_slots[23].uop.is_jalr, slots_23.io.uop.is_jalr
connect issue_slots[23].uop.is_br, slots_23.io.uop.is_br
connect issue_slots[23].uop.iw_p2_poisoned, slots_23.io.uop.iw_p2_poisoned
connect issue_slots[23].uop.iw_p1_poisoned, slots_23.io.uop.iw_p1_poisoned
connect issue_slots[23].uop.iw_state, slots_23.io.uop.iw_state
connect issue_slots[23].uop.ctrl.is_std, slots_23.io.uop.ctrl.is_std
connect issue_slots[23].uop.ctrl.is_sta, slots_23.io.uop.ctrl.is_sta
connect issue_slots[23].uop.ctrl.is_load, slots_23.io.uop.ctrl.is_load
connect issue_slots[23].uop.ctrl.csr_cmd, slots_23.io.uop.ctrl.csr_cmd
connect issue_slots[23].uop.ctrl.fcn_dw, slots_23.io.uop.ctrl.fcn_dw
connect issue_slots[23].uop.ctrl.op_fcn, slots_23.io.uop.ctrl.op_fcn
connect issue_slots[23].uop.ctrl.imm_sel, slots_23.io.uop.ctrl.imm_sel
connect issue_slots[23].uop.ctrl.op2_sel, slots_23.io.uop.ctrl.op2_sel
connect issue_slots[23].uop.ctrl.op1_sel, slots_23.io.uop.ctrl.op1_sel
connect issue_slots[23].uop.ctrl.br_type, slots_23.io.uop.ctrl.br_type
connect issue_slots[23].uop.fu_code, slots_23.io.uop.fu_code
connect issue_slots[23].uop.iq_type, slots_23.io.uop.iq_type
connect issue_slots[23].uop.debug_pc, slots_23.io.uop.debug_pc
connect issue_slots[23].uop.is_rvc, slots_23.io.uop.is_rvc
connect issue_slots[23].uop.debug_inst, slots_23.io.uop.debug_inst
connect issue_slots[23].uop.inst, slots_23.io.uop.inst
connect issue_slots[23].uop.uopc, slots_23.io.uop.uopc
connect issue_slots[23].out_uop.debug_tsrc, slots_23.io.out_uop.debug_tsrc
connect issue_slots[23].out_uop.debug_fsrc, slots_23.io.out_uop.debug_fsrc
connect issue_slots[23].out_uop.bp_xcpt_if, slots_23.io.out_uop.bp_xcpt_if
connect issue_slots[23].out_uop.bp_debug_if, slots_23.io.out_uop.bp_debug_if
connect issue_slots[23].out_uop.xcpt_ma_if, slots_23.io.out_uop.xcpt_ma_if
connect issue_slots[23].out_uop.xcpt_ae_if, slots_23.io.out_uop.xcpt_ae_if
connect issue_slots[23].out_uop.xcpt_pf_if, slots_23.io.out_uop.xcpt_pf_if
connect issue_slots[23].out_uop.fp_single, slots_23.io.out_uop.fp_single
connect issue_slots[23].out_uop.fp_val, slots_23.io.out_uop.fp_val
connect issue_slots[23].out_uop.frs3_en, slots_23.io.out_uop.frs3_en
connect issue_slots[23].out_uop.lrs2_rtype, slots_23.io.out_uop.lrs2_rtype
connect issue_slots[23].out_uop.lrs1_rtype, slots_23.io.out_uop.lrs1_rtype
connect issue_slots[23].out_uop.dst_rtype, slots_23.io.out_uop.dst_rtype
connect issue_slots[23].out_uop.ldst_val, slots_23.io.out_uop.ldst_val
connect issue_slots[23].out_uop.lrs3, slots_23.io.out_uop.lrs3
connect issue_slots[23].out_uop.lrs2, slots_23.io.out_uop.lrs2
connect issue_slots[23].out_uop.lrs1, slots_23.io.out_uop.lrs1
connect issue_slots[23].out_uop.ldst, slots_23.io.out_uop.ldst
connect issue_slots[23].out_uop.ldst_is_rs1, slots_23.io.out_uop.ldst_is_rs1
connect issue_slots[23].out_uop.flush_on_commit, slots_23.io.out_uop.flush_on_commit
connect issue_slots[23].out_uop.is_unique, slots_23.io.out_uop.is_unique
connect issue_slots[23].out_uop.is_sys_pc2epc, slots_23.io.out_uop.is_sys_pc2epc
connect issue_slots[23].out_uop.uses_stq, slots_23.io.out_uop.uses_stq
connect issue_slots[23].out_uop.uses_ldq, slots_23.io.out_uop.uses_ldq
connect issue_slots[23].out_uop.is_amo, slots_23.io.out_uop.is_amo
connect issue_slots[23].out_uop.is_fencei, slots_23.io.out_uop.is_fencei
connect issue_slots[23].out_uop.is_fence, slots_23.io.out_uop.is_fence
connect issue_slots[23].out_uop.mem_signed, slots_23.io.out_uop.mem_signed
connect issue_slots[23].out_uop.mem_size, slots_23.io.out_uop.mem_size
connect issue_slots[23].out_uop.mem_cmd, slots_23.io.out_uop.mem_cmd
connect issue_slots[23].out_uop.bypassable, slots_23.io.out_uop.bypassable
connect issue_slots[23].out_uop.exc_cause, slots_23.io.out_uop.exc_cause
connect issue_slots[23].out_uop.exception, slots_23.io.out_uop.exception
connect issue_slots[23].out_uop.stale_pdst, slots_23.io.out_uop.stale_pdst
connect issue_slots[23].out_uop.ppred_busy, slots_23.io.out_uop.ppred_busy
connect issue_slots[23].out_uop.prs3_busy, slots_23.io.out_uop.prs3_busy
connect issue_slots[23].out_uop.prs2_busy, slots_23.io.out_uop.prs2_busy
connect issue_slots[23].out_uop.prs1_busy, slots_23.io.out_uop.prs1_busy
connect issue_slots[23].out_uop.ppred, slots_23.io.out_uop.ppred
connect issue_slots[23].out_uop.prs3, slots_23.io.out_uop.prs3
connect issue_slots[23].out_uop.prs2, slots_23.io.out_uop.prs2
connect issue_slots[23].out_uop.prs1, slots_23.io.out_uop.prs1
connect issue_slots[23].out_uop.pdst, slots_23.io.out_uop.pdst
connect issue_slots[23].out_uop.rxq_idx, slots_23.io.out_uop.rxq_idx
connect issue_slots[23].out_uop.stq_idx, slots_23.io.out_uop.stq_idx
connect issue_slots[23].out_uop.ldq_idx, slots_23.io.out_uop.ldq_idx
connect issue_slots[23].out_uop.rob_idx, slots_23.io.out_uop.rob_idx
connect issue_slots[23].out_uop.csr_addr, slots_23.io.out_uop.csr_addr
connect issue_slots[23].out_uop.imm_packed, slots_23.io.out_uop.imm_packed
connect issue_slots[23].out_uop.taken, slots_23.io.out_uop.taken
connect issue_slots[23].out_uop.pc_lob, slots_23.io.out_uop.pc_lob
connect issue_slots[23].out_uop.edge_inst, slots_23.io.out_uop.edge_inst
connect issue_slots[23].out_uop.ftq_idx, slots_23.io.out_uop.ftq_idx
connect issue_slots[23].out_uop.br_tag, slots_23.io.out_uop.br_tag
connect issue_slots[23].out_uop.br_mask, slots_23.io.out_uop.br_mask
connect issue_slots[23].out_uop.is_sfb, slots_23.io.out_uop.is_sfb
connect issue_slots[23].out_uop.is_jal, slots_23.io.out_uop.is_jal
connect issue_slots[23].out_uop.is_jalr, slots_23.io.out_uop.is_jalr
connect issue_slots[23].out_uop.is_br, slots_23.io.out_uop.is_br
connect issue_slots[23].out_uop.iw_p2_poisoned, slots_23.io.out_uop.iw_p2_poisoned
connect issue_slots[23].out_uop.iw_p1_poisoned, slots_23.io.out_uop.iw_p1_poisoned
connect issue_slots[23].out_uop.iw_state, slots_23.io.out_uop.iw_state
connect issue_slots[23].out_uop.ctrl.is_std, slots_23.io.out_uop.ctrl.is_std
connect issue_slots[23].out_uop.ctrl.is_sta, slots_23.io.out_uop.ctrl.is_sta
connect issue_slots[23].out_uop.ctrl.is_load, slots_23.io.out_uop.ctrl.is_load
connect issue_slots[23].out_uop.ctrl.csr_cmd, slots_23.io.out_uop.ctrl.csr_cmd
connect issue_slots[23].out_uop.ctrl.fcn_dw, slots_23.io.out_uop.ctrl.fcn_dw
connect issue_slots[23].out_uop.ctrl.op_fcn, slots_23.io.out_uop.ctrl.op_fcn
connect issue_slots[23].out_uop.ctrl.imm_sel, slots_23.io.out_uop.ctrl.imm_sel
connect issue_slots[23].out_uop.ctrl.op2_sel, slots_23.io.out_uop.ctrl.op2_sel
connect issue_slots[23].out_uop.ctrl.op1_sel, slots_23.io.out_uop.ctrl.op1_sel
connect issue_slots[23].out_uop.ctrl.br_type, slots_23.io.out_uop.ctrl.br_type
connect issue_slots[23].out_uop.fu_code, slots_23.io.out_uop.fu_code
connect issue_slots[23].out_uop.iq_type, slots_23.io.out_uop.iq_type
connect issue_slots[23].out_uop.debug_pc, slots_23.io.out_uop.debug_pc
connect issue_slots[23].out_uop.is_rvc, slots_23.io.out_uop.is_rvc
connect issue_slots[23].out_uop.debug_inst, slots_23.io.out_uop.debug_inst
connect issue_slots[23].out_uop.inst, slots_23.io.out_uop.inst
connect issue_slots[23].out_uop.uopc, slots_23.io.out_uop.uopc
connect slots_23.io.in_uop.bits.debug_tsrc, issue_slots[23].in_uop.bits.debug_tsrc
connect slots_23.io.in_uop.bits.debug_fsrc, issue_slots[23].in_uop.bits.debug_fsrc
connect slots_23.io.in_uop.bits.bp_xcpt_if, issue_slots[23].in_uop.bits.bp_xcpt_if
connect slots_23.io.in_uop.bits.bp_debug_if, issue_slots[23].in_uop.bits.bp_debug_if
connect slots_23.io.in_uop.bits.xcpt_ma_if, issue_slots[23].in_uop.bits.xcpt_ma_if
connect slots_23.io.in_uop.bits.xcpt_ae_if, issue_slots[23].in_uop.bits.xcpt_ae_if
connect slots_23.io.in_uop.bits.xcpt_pf_if, issue_slots[23].in_uop.bits.xcpt_pf_if
connect slots_23.io.in_uop.bits.fp_single, issue_slots[23].in_uop.bits.fp_single
connect slots_23.io.in_uop.bits.fp_val, issue_slots[23].in_uop.bits.fp_val
connect slots_23.io.in_uop.bits.frs3_en, issue_slots[23].in_uop.bits.frs3_en
connect slots_23.io.in_uop.bits.lrs2_rtype, issue_slots[23].in_uop.bits.lrs2_rtype
connect slots_23.io.in_uop.bits.lrs1_rtype, issue_slots[23].in_uop.bits.lrs1_rtype
connect slots_23.io.in_uop.bits.dst_rtype, issue_slots[23].in_uop.bits.dst_rtype
connect slots_23.io.in_uop.bits.ldst_val, issue_slots[23].in_uop.bits.ldst_val
connect slots_23.io.in_uop.bits.lrs3, issue_slots[23].in_uop.bits.lrs3
connect slots_23.io.in_uop.bits.lrs2, issue_slots[23].in_uop.bits.lrs2
connect slots_23.io.in_uop.bits.lrs1, issue_slots[23].in_uop.bits.lrs1
connect slots_23.io.in_uop.bits.ldst, issue_slots[23].in_uop.bits.ldst
connect slots_23.io.in_uop.bits.ldst_is_rs1, issue_slots[23].in_uop.bits.ldst_is_rs1
connect slots_23.io.in_uop.bits.flush_on_commit, issue_slots[23].in_uop.bits.flush_on_commit
connect slots_23.io.in_uop.bits.is_unique, issue_slots[23].in_uop.bits.is_unique
connect slots_23.io.in_uop.bits.is_sys_pc2epc, issue_slots[23].in_uop.bits.is_sys_pc2epc
connect slots_23.io.in_uop.bits.uses_stq, issue_slots[23].in_uop.bits.uses_stq
connect slots_23.io.in_uop.bits.uses_ldq, issue_slots[23].in_uop.bits.uses_ldq
connect slots_23.io.in_uop.bits.is_amo, issue_slots[23].in_uop.bits.is_amo
connect slots_23.io.in_uop.bits.is_fencei, issue_slots[23].in_uop.bits.is_fencei
connect slots_23.io.in_uop.bits.is_fence, issue_slots[23].in_uop.bits.is_fence
connect slots_23.io.in_uop.bits.mem_signed, issue_slots[23].in_uop.bits.mem_signed
connect slots_23.io.in_uop.bits.mem_size, issue_slots[23].in_uop.bits.mem_size
connect slots_23.io.in_uop.bits.mem_cmd, issue_slots[23].in_uop.bits.mem_cmd
connect slots_23.io.in_uop.bits.bypassable, issue_slots[23].in_uop.bits.bypassable
connect slots_23.io.in_uop.bits.exc_cause, issue_slots[23].in_uop.bits.exc_cause
connect slots_23.io.in_uop.bits.exception, issue_slots[23].in_uop.bits.exception
connect slots_23.io.in_uop.bits.stale_pdst, issue_slots[23].in_uop.bits.stale_pdst
connect slots_23.io.in_uop.bits.ppred_busy, issue_slots[23].in_uop.bits.ppred_busy
connect slots_23.io.in_uop.bits.prs3_busy, issue_slots[23].in_uop.bits.prs3_busy
connect slots_23.io.in_uop.bits.prs2_busy, issue_slots[23].in_uop.bits.prs2_busy
connect slots_23.io.in_uop.bits.prs1_busy, issue_slots[23].in_uop.bits.prs1_busy
connect slots_23.io.in_uop.bits.ppred, issue_slots[23].in_uop.bits.ppred
connect slots_23.io.in_uop.bits.prs3, issue_slots[23].in_uop.bits.prs3
connect slots_23.io.in_uop.bits.prs2, issue_slots[23].in_uop.bits.prs2
connect slots_23.io.in_uop.bits.prs1, issue_slots[23].in_uop.bits.prs1
connect slots_23.io.in_uop.bits.pdst, issue_slots[23].in_uop.bits.pdst
connect slots_23.io.in_uop.bits.rxq_idx, issue_slots[23].in_uop.bits.rxq_idx
connect slots_23.io.in_uop.bits.stq_idx, issue_slots[23].in_uop.bits.stq_idx
connect slots_23.io.in_uop.bits.ldq_idx, issue_slots[23].in_uop.bits.ldq_idx
connect slots_23.io.in_uop.bits.rob_idx, issue_slots[23].in_uop.bits.rob_idx
connect slots_23.io.in_uop.bits.csr_addr, issue_slots[23].in_uop.bits.csr_addr
connect slots_23.io.in_uop.bits.imm_packed, issue_slots[23].in_uop.bits.imm_packed
connect slots_23.io.in_uop.bits.taken, issue_slots[23].in_uop.bits.taken
connect slots_23.io.in_uop.bits.pc_lob, issue_slots[23].in_uop.bits.pc_lob
connect slots_23.io.in_uop.bits.edge_inst, issue_slots[23].in_uop.bits.edge_inst
connect slots_23.io.in_uop.bits.ftq_idx, issue_slots[23].in_uop.bits.ftq_idx
connect slots_23.io.in_uop.bits.br_tag, issue_slots[23].in_uop.bits.br_tag
connect slots_23.io.in_uop.bits.br_mask, issue_slots[23].in_uop.bits.br_mask
connect slots_23.io.in_uop.bits.is_sfb, issue_slots[23].in_uop.bits.is_sfb
connect slots_23.io.in_uop.bits.is_jal, issue_slots[23].in_uop.bits.is_jal
connect slots_23.io.in_uop.bits.is_jalr, issue_slots[23].in_uop.bits.is_jalr
connect slots_23.io.in_uop.bits.is_br, issue_slots[23].in_uop.bits.is_br
connect slots_23.io.in_uop.bits.iw_p2_poisoned, issue_slots[23].in_uop.bits.iw_p2_poisoned
connect slots_23.io.in_uop.bits.iw_p1_poisoned, issue_slots[23].in_uop.bits.iw_p1_poisoned
connect slots_23.io.in_uop.bits.iw_state, issue_slots[23].in_uop.bits.iw_state
connect slots_23.io.in_uop.bits.ctrl.is_std, issue_slots[23].in_uop.bits.ctrl.is_std
connect slots_23.io.in_uop.bits.ctrl.is_sta, issue_slots[23].in_uop.bits.ctrl.is_sta
connect slots_23.io.in_uop.bits.ctrl.is_load, issue_slots[23].in_uop.bits.ctrl.is_load
connect slots_23.io.in_uop.bits.ctrl.csr_cmd, issue_slots[23].in_uop.bits.ctrl.csr_cmd
connect slots_23.io.in_uop.bits.ctrl.fcn_dw, issue_slots[23].in_uop.bits.ctrl.fcn_dw
connect slots_23.io.in_uop.bits.ctrl.op_fcn, issue_slots[23].in_uop.bits.ctrl.op_fcn
connect slots_23.io.in_uop.bits.ctrl.imm_sel, issue_slots[23].in_uop.bits.ctrl.imm_sel
connect slots_23.io.in_uop.bits.ctrl.op2_sel, issue_slots[23].in_uop.bits.ctrl.op2_sel
connect slots_23.io.in_uop.bits.ctrl.op1_sel, issue_slots[23].in_uop.bits.ctrl.op1_sel
connect slots_23.io.in_uop.bits.ctrl.br_type, issue_slots[23].in_uop.bits.ctrl.br_type
connect slots_23.io.in_uop.bits.fu_code, issue_slots[23].in_uop.bits.fu_code
connect slots_23.io.in_uop.bits.iq_type, issue_slots[23].in_uop.bits.iq_type
connect slots_23.io.in_uop.bits.debug_pc, issue_slots[23].in_uop.bits.debug_pc
connect slots_23.io.in_uop.bits.is_rvc, issue_slots[23].in_uop.bits.is_rvc
connect slots_23.io.in_uop.bits.debug_inst, issue_slots[23].in_uop.bits.debug_inst
connect slots_23.io.in_uop.bits.inst, issue_slots[23].in_uop.bits.inst
connect slots_23.io.in_uop.bits.uopc, issue_slots[23].in_uop.bits.uopc
connect slots_23.io.in_uop.valid, issue_slots[23].in_uop.valid
connect slots_23.io.spec_ld_wakeup[0].bits, issue_slots[23].spec_ld_wakeup[0].bits
connect slots_23.io.spec_ld_wakeup[0].valid, issue_slots[23].spec_ld_wakeup[0].valid
connect slots_23.io.pred_wakeup_port.bits, issue_slots[23].pred_wakeup_port.bits
connect slots_23.io.pred_wakeup_port.valid, issue_slots[23].pred_wakeup_port.valid
connect slots_23.io.wakeup_ports[0].bits.poisoned, issue_slots[23].wakeup_ports[0].bits.poisoned
connect slots_23.io.wakeup_ports[0].bits.pdst, issue_slots[23].wakeup_ports[0].bits.pdst
connect slots_23.io.wakeup_ports[0].valid, issue_slots[23].wakeup_ports[0].valid
connect slots_23.io.wakeup_ports[1].bits.poisoned, issue_slots[23].wakeup_ports[1].bits.poisoned
connect slots_23.io.wakeup_ports[1].bits.pdst, issue_slots[23].wakeup_ports[1].bits.pdst
connect slots_23.io.wakeup_ports[1].valid, issue_slots[23].wakeup_ports[1].valid
connect slots_23.io.ldspec_miss, issue_slots[23].ldspec_miss
connect slots_23.io.clear, issue_slots[23].clear
connect slots_23.io.kill, issue_slots[23].kill
connect slots_23.io.brupdate.b2.target_offset, issue_slots[23].brupdate.b2.target_offset
connect slots_23.io.brupdate.b2.jalr_target, issue_slots[23].brupdate.b2.jalr_target
connect slots_23.io.brupdate.b2.pc_sel, issue_slots[23].brupdate.b2.pc_sel
connect slots_23.io.brupdate.b2.cfi_type, issue_slots[23].brupdate.b2.cfi_type
connect slots_23.io.brupdate.b2.taken, issue_slots[23].brupdate.b2.taken
connect slots_23.io.brupdate.b2.mispredict, issue_slots[23].brupdate.b2.mispredict
connect slots_23.io.brupdate.b2.valid, issue_slots[23].brupdate.b2.valid
connect slots_23.io.brupdate.b2.uop.debug_tsrc, issue_slots[23].brupdate.b2.uop.debug_tsrc
connect slots_23.io.brupdate.b2.uop.debug_fsrc, issue_slots[23].brupdate.b2.uop.debug_fsrc
connect slots_23.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[23].brupdate.b2.uop.bp_xcpt_if
connect slots_23.io.brupdate.b2.uop.bp_debug_if, issue_slots[23].brupdate.b2.uop.bp_debug_if
connect slots_23.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[23].brupdate.b2.uop.xcpt_ma_if
connect slots_23.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[23].brupdate.b2.uop.xcpt_ae_if
connect slots_23.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[23].brupdate.b2.uop.xcpt_pf_if
connect slots_23.io.brupdate.b2.uop.fp_single, issue_slots[23].brupdate.b2.uop.fp_single
connect slots_23.io.brupdate.b2.uop.fp_val, issue_slots[23].brupdate.b2.uop.fp_val
connect slots_23.io.brupdate.b2.uop.frs3_en, issue_slots[23].brupdate.b2.uop.frs3_en
connect slots_23.io.brupdate.b2.uop.lrs2_rtype, issue_slots[23].brupdate.b2.uop.lrs2_rtype
connect slots_23.io.brupdate.b2.uop.lrs1_rtype, issue_slots[23].brupdate.b2.uop.lrs1_rtype
connect slots_23.io.brupdate.b2.uop.dst_rtype, issue_slots[23].brupdate.b2.uop.dst_rtype
connect slots_23.io.brupdate.b2.uop.ldst_val, issue_slots[23].brupdate.b2.uop.ldst_val
connect slots_23.io.brupdate.b2.uop.lrs3, issue_slots[23].brupdate.b2.uop.lrs3
connect slots_23.io.brupdate.b2.uop.lrs2, issue_slots[23].brupdate.b2.uop.lrs2
connect slots_23.io.brupdate.b2.uop.lrs1, issue_slots[23].brupdate.b2.uop.lrs1
connect slots_23.io.brupdate.b2.uop.ldst, issue_slots[23].brupdate.b2.uop.ldst
connect slots_23.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[23].brupdate.b2.uop.ldst_is_rs1
connect slots_23.io.brupdate.b2.uop.flush_on_commit, issue_slots[23].brupdate.b2.uop.flush_on_commit
connect slots_23.io.brupdate.b2.uop.is_unique, issue_slots[23].brupdate.b2.uop.is_unique
connect slots_23.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[23].brupdate.b2.uop.is_sys_pc2epc
connect slots_23.io.brupdate.b2.uop.uses_stq, issue_slots[23].brupdate.b2.uop.uses_stq
connect slots_23.io.brupdate.b2.uop.uses_ldq, issue_slots[23].brupdate.b2.uop.uses_ldq
connect slots_23.io.brupdate.b2.uop.is_amo, issue_slots[23].brupdate.b2.uop.is_amo
connect slots_23.io.brupdate.b2.uop.is_fencei, issue_slots[23].brupdate.b2.uop.is_fencei
connect slots_23.io.brupdate.b2.uop.is_fence, issue_slots[23].brupdate.b2.uop.is_fence
connect slots_23.io.brupdate.b2.uop.mem_signed, issue_slots[23].brupdate.b2.uop.mem_signed
connect slots_23.io.brupdate.b2.uop.mem_size, issue_slots[23].brupdate.b2.uop.mem_size
connect slots_23.io.brupdate.b2.uop.mem_cmd, issue_slots[23].brupdate.b2.uop.mem_cmd
connect slots_23.io.brupdate.b2.uop.bypassable, issue_slots[23].brupdate.b2.uop.bypassable
connect slots_23.io.brupdate.b2.uop.exc_cause, issue_slots[23].brupdate.b2.uop.exc_cause
connect slots_23.io.brupdate.b2.uop.exception, issue_slots[23].brupdate.b2.uop.exception
connect slots_23.io.brupdate.b2.uop.stale_pdst, issue_slots[23].brupdate.b2.uop.stale_pdst
connect slots_23.io.brupdate.b2.uop.ppred_busy, issue_slots[23].brupdate.b2.uop.ppred_busy
connect slots_23.io.brupdate.b2.uop.prs3_busy, issue_slots[23].brupdate.b2.uop.prs3_busy
connect slots_23.io.brupdate.b2.uop.prs2_busy, issue_slots[23].brupdate.b2.uop.prs2_busy
connect slots_23.io.brupdate.b2.uop.prs1_busy, issue_slots[23].brupdate.b2.uop.prs1_busy
connect slots_23.io.brupdate.b2.uop.ppred, issue_slots[23].brupdate.b2.uop.ppred
connect slots_23.io.brupdate.b2.uop.prs3, issue_slots[23].brupdate.b2.uop.prs3
connect slots_23.io.brupdate.b2.uop.prs2, issue_slots[23].brupdate.b2.uop.prs2
connect slots_23.io.brupdate.b2.uop.prs1, issue_slots[23].brupdate.b2.uop.prs1
connect slots_23.io.brupdate.b2.uop.pdst, issue_slots[23].brupdate.b2.uop.pdst
connect slots_23.io.brupdate.b2.uop.rxq_idx, issue_slots[23].brupdate.b2.uop.rxq_idx
connect slots_23.io.brupdate.b2.uop.stq_idx, issue_slots[23].brupdate.b2.uop.stq_idx
connect slots_23.io.brupdate.b2.uop.ldq_idx, issue_slots[23].brupdate.b2.uop.ldq_idx
connect slots_23.io.brupdate.b2.uop.rob_idx, issue_slots[23].brupdate.b2.uop.rob_idx
connect slots_23.io.brupdate.b2.uop.csr_addr, issue_slots[23].brupdate.b2.uop.csr_addr
connect slots_23.io.brupdate.b2.uop.imm_packed, issue_slots[23].brupdate.b2.uop.imm_packed
connect slots_23.io.brupdate.b2.uop.taken, issue_slots[23].brupdate.b2.uop.taken
connect slots_23.io.brupdate.b2.uop.pc_lob, issue_slots[23].brupdate.b2.uop.pc_lob
connect slots_23.io.brupdate.b2.uop.edge_inst, issue_slots[23].brupdate.b2.uop.edge_inst
connect slots_23.io.brupdate.b2.uop.ftq_idx, issue_slots[23].brupdate.b2.uop.ftq_idx
connect slots_23.io.brupdate.b2.uop.br_tag, issue_slots[23].brupdate.b2.uop.br_tag
connect slots_23.io.brupdate.b2.uop.br_mask, issue_slots[23].brupdate.b2.uop.br_mask
connect slots_23.io.brupdate.b2.uop.is_sfb, issue_slots[23].brupdate.b2.uop.is_sfb
connect slots_23.io.brupdate.b2.uop.is_jal, issue_slots[23].brupdate.b2.uop.is_jal
connect slots_23.io.brupdate.b2.uop.is_jalr, issue_slots[23].brupdate.b2.uop.is_jalr
connect slots_23.io.brupdate.b2.uop.is_br, issue_slots[23].brupdate.b2.uop.is_br
connect slots_23.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[23].brupdate.b2.uop.iw_p2_poisoned
connect slots_23.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[23].brupdate.b2.uop.iw_p1_poisoned
connect slots_23.io.brupdate.b2.uop.iw_state, issue_slots[23].brupdate.b2.uop.iw_state
connect slots_23.io.brupdate.b2.uop.ctrl.is_std, issue_slots[23].brupdate.b2.uop.ctrl.is_std
connect slots_23.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[23].brupdate.b2.uop.ctrl.is_sta
connect slots_23.io.brupdate.b2.uop.ctrl.is_load, issue_slots[23].brupdate.b2.uop.ctrl.is_load
connect slots_23.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[23].brupdate.b2.uop.ctrl.csr_cmd
connect slots_23.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[23].brupdate.b2.uop.ctrl.fcn_dw
connect slots_23.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[23].brupdate.b2.uop.ctrl.op_fcn
connect slots_23.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[23].brupdate.b2.uop.ctrl.imm_sel
connect slots_23.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[23].brupdate.b2.uop.ctrl.op2_sel
connect slots_23.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[23].brupdate.b2.uop.ctrl.op1_sel
connect slots_23.io.brupdate.b2.uop.ctrl.br_type, issue_slots[23].brupdate.b2.uop.ctrl.br_type
connect slots_23.io.brupdate.b2.uop.fu_code, issue_slots[23].brupdate.b2.uop.fu_code
connect slots_23.io.brupdate.b2.uop.iq_type, issue_slots[23].brupdate.b2.uop.iq_type
connect slots_23.io.brupdate.b2.uop.debug_pc, issue_slots[23].brupdate.b2.uop.debug_pc
connect slots_23.io.brupdate.b2.uop.is_rvc, issue_slots[23].brupdate.b2.uop.is_rvc
connect slots_23.io.brupdate.b2.uop.debug_inst, issue_slots[23].brupdate.b2.uop.debug_inst
connect slots_23.io.brupdate.b2.uop.inst, issue_slots[23].brupdate.b2.uop.inst
connect slots_23.io.brupdate.b2.uop.uopc, issue_slots[23].brupdate.b2.uop.uopc
connect slots_23.io.brupdate.b1.mispredict_mask, issue_slots[23].brupdate.b1.mispredict_mask
connect slots_23.io.brupdate.b1.resolve_mask, issue_slots[23].brupdate.b1.resolve_mask
connect slots_23.io.grant, issue_slots[23].grant
connect issue_slots[23].request_hp, slots_23.io.request_hp
connect issue_slots[23].request, slots_23.io.request
connect issue_slots[23].will_be_valid, slots_23.io.will_be_valid
connect issue_slots[23].valid, slots_23.io.valid
connect issue_slots[0].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[0].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[0].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[0].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[0].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[0].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[0].ldspec_miss, io.ld_miss
connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[0].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[0].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[0].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[0].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[0].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[0].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[0].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[0].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[0].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[0].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[0].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[0].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[0].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[0].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[0].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[0].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[0].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[0].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[0].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[0].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[0].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[0].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[0].kill, io.flush_pipeline
connect issue_slots[1].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[1].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[1].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[1].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[1].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[1].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[1].ldspec_miss, io.ld_miss
connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[1].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[1].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[1].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[1].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[1].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[1].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[1].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[1].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[1].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[1].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[1].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[1].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[1].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[1].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[1].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[1].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[1].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[1].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[1].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[1].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[1].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[1].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[1].kill, io.flush_pipeline
connect issue_slots[2].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[2].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[2].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[2].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[2].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[2].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[2].ldspec_miss, io.ld_miss
connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[2].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[2].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[2].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[2].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[2].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[2].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[2].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[2].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[2].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[2].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[2].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[2].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[2].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[2].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[2].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[2].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[2].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[2].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[2].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[2].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[2].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[2].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[2].kill, io.flush_pipeline
connect issue_slots[3].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[3].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[3].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[3].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[3].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[3].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[3].ldspec_miss, io.ld_miss
connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[3].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[3].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[3].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[3].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[3].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[3].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[3].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[3].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[3].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[3].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[3].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[3].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[3].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[3].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[3].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[3].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[3].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[3].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[3].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[3].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[3].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[3].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[3].kill, io.flush_pipeline
connect issue_slots[4].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[4].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[4].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[4].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[4].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[4].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[4].ldspec_miss, io.ld_miss
connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[4].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[4].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[4].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[4].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[4].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[4].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[4].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[4].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[4].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[4].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[4].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[4].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[4].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[4].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[4].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[4].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[4].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[4].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[4].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[4].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[4].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[4].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[4].kill, io.flush_pipeline
connect issue_slots[5].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[5].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[5].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[5].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[5].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[5].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[5].ldspec_miss, io.ld_miss
connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[5].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[5].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[5].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[5].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[5].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[5].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[5].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[5].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[5].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[5].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[5].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[5].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[5].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[5].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[5].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[5].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[5].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[5].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[5].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[5].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[5].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[5].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[5].kill, io.flush_pipeline
connect issue_slots[6].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[6].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[6].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[6].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[6].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[6].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[6].ldspec_miss, io.ld_miss
connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[6].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[6].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[6].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[6].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[6].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[6].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[6].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[6].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[6].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[6].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[6].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[6].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[6].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[6].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[6].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[6].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[6].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[6].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[6].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[6].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[6].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[6].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[6].kill, io.flush_pipeline
connect issue_slots[7].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[7].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[7].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[7].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[7].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[7].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[7].ldspec_miss, io.ld_miss
connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[7].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[7].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[7].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[7].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[7].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[7].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[7].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[7].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[7].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[7].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[7].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[7].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[7].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[7].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[7].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[7].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[7].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[7].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[7].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[7].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[7].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[7].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[7].kill, io.flush_pipeline
connect issue_slots[8].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[8].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[8].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[8].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[8].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[8].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[8].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[8].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[8].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[8].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[8].ldspec_miss, io.ld_miss
connect issue_slots[8].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[8].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[8].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[8].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[8].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[8].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[8].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[8].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[8].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[8].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[8].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[8].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[8].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[8].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[8].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[8].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[8].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[8].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[8].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[8].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[8].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[8].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[8].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[8].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[8].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[8].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[8].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[8].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[8].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[8].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[8].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[8].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[8].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[8].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[8].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[8].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[8].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[8].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[8].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[8].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[8].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[8].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[8].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[8].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[8].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[8].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[8].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[8].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[8].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[8].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[8].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[8].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[8].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[8].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[8].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[8].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[8].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[8].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[8].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[8].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[8].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[8].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[8].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[8].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[8].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[8].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[8].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[8].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[8].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[8].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[8].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[8].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[8].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[8].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[8].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[8].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[8].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[8].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[8].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[8].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[8].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[8].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[8].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[8].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[8].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[8].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[8].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[8].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[8].kill, io.flush_pipeline
connect issue_slots[9].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[9].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[9].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[9].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[9].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[9].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[9].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[9].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[9].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[9].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[9].ldspec_miss, io.ld_miss
connect issue_slots[9].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[9].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[9].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[9].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[9].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[9].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[9].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[9].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[9].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[9].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[9].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[9].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[9].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[9].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[9].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[9].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[9].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[9].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[9].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[9].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[9].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[9].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[9].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[9].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[9].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[9].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[9].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[9].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[9].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[9].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[9].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[9].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[9].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[9].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[9].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[9].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[9].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[9].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[9].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[9].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[9].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[9].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[9].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[9].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[9].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[9].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[9].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[9].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[9].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[9].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[9].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[9].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[9].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[9].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[9].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[9].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[9].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[9].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[9].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[9].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[9].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[9].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[9].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[9].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[9].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[9].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[9].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[9].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[9].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[9].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[9].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[9].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[9].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[9].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[9].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[9].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[9].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[9].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[9].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[9].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[9].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[9].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[9].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[9].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[9].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[9].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[9].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[9].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[9].kill, io.flush_pipeline
connect issue_slots[10].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[10].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[10].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[10].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[10].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[10].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[10].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[10].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[10].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[10].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[10].ldspec_miss, io.ld_miss
connect issue_slots[10].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[10].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[10].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[10].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[10].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[10].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[10].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[10].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[10].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[10].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[10].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[10].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[10].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[10].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[10].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[10].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[10].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[10].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[10].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[10].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[10].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[10].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[10].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[10].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[10].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[10].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[10].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[10].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[10].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[10].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[10].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[10].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[10].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[10].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[10].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[10].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[10].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[10].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[10].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[10].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[10].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[10].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[10].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[10].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[10].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[10].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[10].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[10].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[10].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[10].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[10].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[10].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[10].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[10].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[10].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[10].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[10].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[10].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[10].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[10].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[10].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[10].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[10].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[10].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[10].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[10].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[10].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[10].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[10].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[10].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[10].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[10].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[10].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[10].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[10].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[10].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[10].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[10].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[10].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[10].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[10].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[10].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[10].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[10].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[10].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[10].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[10].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[10].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[10].kill, io.flush_pipeline
connect issue_slots[11].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[11].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[11].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[11].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[11].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[11].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[11].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[11].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[11].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[11].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[11].ldspec_miss, io.ld_miss
connect issue_slots[11].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[11].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[11].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[11].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[11].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[11].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[11].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[11].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[11].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[11].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[11].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[11].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[11].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[11].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[11].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[11].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[11].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[11].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[11].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[11].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[11].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[11].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[11].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[11].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[11].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[11].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[11].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[11].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[11].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[11].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[11].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[11].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[11].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[11].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[11].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[11].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[11].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[11].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[11].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[11].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[11].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[11].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[11].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[11].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[11].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[11].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[11].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[11].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[11].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[11].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[11].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[11].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[11].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[11].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[11].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[11].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[11].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[11].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[11].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[11].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[11].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[11].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[11].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[11].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[11].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[11].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[11].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[11].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[11].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[11].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[11].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[11].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[11].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[11].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[11].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[11].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[11].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[11].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[11].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[11].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[11].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[11].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[11].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[11].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[11].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[11].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[11].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[11].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[11].kill, io.flush_pipeline
connect issue_slots[12].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[12].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[12].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[12].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[12].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[12].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[12].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[12].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[12].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[12].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[12].ldspec_miss, io.ld_miss
connect issue_slots[12].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[12].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[12].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[12].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[12].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[12].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[12].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[12].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[12].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[12].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[12].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[12].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[12].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[12].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[12].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[12].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[12].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[12].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[12].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[12].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[12].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[12].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[12].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[12].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[12].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[12].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[12].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[12].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[12].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[12].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[12].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[12].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[12].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[12].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[12].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[12].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[12].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[12].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[12].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[12].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[12].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[12].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[12].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[12].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[12].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[12].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[12].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[12].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[12].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[12].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[12].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[12].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[12].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[12].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[12].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[12].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[12].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[12].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[12].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[12].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[12].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[12].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[12].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[12].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[12].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[12].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[12].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[12].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[12].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[12].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[12].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[12].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[12].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[12].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[12].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[12].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[12].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[12].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[12].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[12].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[12].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[12].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[12].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[12].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[12].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[12].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[12].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[12].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[12].kill, io.flush_pipeline
connect issue_slots[13].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[13].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[13].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[13].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[13].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[13].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[13].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[13].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[13].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[13].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[13].ldspec_miss, io.ld_miss
connect issue_slots[13].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[13].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[13].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[13].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[13].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[13].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[13].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[13].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[13].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[13].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[13].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[13].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[13].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[13].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[13].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[13].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[13].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[13].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[13].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[13].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[13].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[13].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[13].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[13].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[13].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[13].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[13].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[13].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[13].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[13].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[13].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[13].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[13].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[13].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[13].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[13].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[13].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[13].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[13].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[13].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[13].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[13].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[13].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[13].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[13].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[13].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[13].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[13].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[13].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[13].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[13].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[13].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[13].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[13].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[13].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[13].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[13].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[13].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[13].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[13].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[13].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[13].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[13].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[13].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[13].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[13].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[13].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[13].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[13].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[13].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[13].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[13].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[13].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[13].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[13].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[13].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[13].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[13].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[13].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[13].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[13].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[13].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[13].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[13].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[13].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[13].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[13].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[13].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[13].kill, io.flush_pipeline
connect issue_slots[14].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[14].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[14].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[14].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[14].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[14].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[14].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[14].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[14].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[14].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[14].ldspec_miss, io.ld_miss
connect issue_slots[14].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[14].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[14].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[14].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[14].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[14].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[14].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[14].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[14].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[14].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[14].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[14].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[14].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[14].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[14].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[14].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[14].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[14].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[14].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[14].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[14].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[14].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[14].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[14].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[14].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[14].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[14].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[14].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[14].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[14].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[14].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[14].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[14].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[14].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[14].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[14].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[14].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[14].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[14].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[14].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[14].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[14].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[14].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[14].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[14].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[14].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[14].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[14].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[14].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[14].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[14].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[14].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[14].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[14].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[14].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[14].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[14].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[14].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[14].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[14].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[14].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[14].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[14].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[14].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[14].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[14].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[14].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[14].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[14].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[14].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[14].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[14].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[14].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[14].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[14].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[14].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[14].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[14].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[14].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[14].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[14].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[14].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[14].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[14].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[14].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[14].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[14].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[14].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[14].kill, io.flush_pipeline
connect issue_slots[15].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[15].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[15].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[15].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[15].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[15].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[15].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[15].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[15].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[15].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[15].ldspec_miss, io.ld_miss
connect issue_slots[15].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[15].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[15].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[15].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[15].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[15].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[15].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[15].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[15].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[15].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[15].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[15].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[15].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[15].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[15].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[15].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[15].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[15].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[15].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[15].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[15].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[15].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[15].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[15].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[15].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[15].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[15].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[15].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[15].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[15].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[15].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[15].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[15].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[15].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[15].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[15].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[15].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[15].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[15].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[15].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[15].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[15].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[15].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[15].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[15].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[15].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[15].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[15].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[15].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[15].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[15].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[15].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[15].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[15].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[15].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[15].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[15].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[15].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[15].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[15].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[15].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[15].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[15].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[15].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[15].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[15].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[15].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[15].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[15].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[15].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[15].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[15].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[15].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[15].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[15].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[15].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[15].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[15].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[15].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[15].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[15].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[15].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[15].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[15].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[15].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[15].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[15].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[15].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[15].kill, io.flush_pipeline
connect issue_slots[16].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[16].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[16].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[16].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[16].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[16].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[16].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[16].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[16].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[16].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[16].ldspec_miss, io.ld_miss
connect issue_slots[16].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[16].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[16].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[16].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[16].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[16].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[16].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[16].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[16].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[16].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[16].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[16].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[16].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[16].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[16].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[16].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[16].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[16].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[16].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[16].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[16].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[16].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[16].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[16].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[16].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[16].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[16].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[16].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[16].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[16].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[16].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[16].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[16].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[16].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[16].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[16].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[16].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[16].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[16].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[16].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[16].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[16].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[16].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[16].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[16].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[16].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[16].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[16].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[16].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[16].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[16].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[16].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[16].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[16].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[16].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[16].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[16].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[16].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[16].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[16].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[16].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[16].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[16].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[16].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[16].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[16].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[16].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[16].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[16].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[16].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[16].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[16].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[16].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[16].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[16].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[16].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[16].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[16].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[16].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[16].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[16].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[16].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[16].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[16].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[16].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[16].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[16].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[16].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[16].kill, io.flush_pipeline
connect issue_slots[17].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[17].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[17].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[17].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[17].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[17].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[17].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[17].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[17].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[17].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[17].ldspec_miss, io.ld_miss
connect issue_slots[17].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[17].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[17].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[17].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[17].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[17].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[17].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[17].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[17].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[17].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[17].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[17].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[17].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[17].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[17].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[17].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[17].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[17].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[17].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[17].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[17].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[17].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[17].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[17].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[17].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[17].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[17].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[17].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[17].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[17].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[17].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[17].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[17].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[17].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[17].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[17].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[17].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[17].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[17].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[17].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[17].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[17].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[17].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[17].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[17].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[17].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[17].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[17].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[17].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[17].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[17].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[17].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[17].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[17].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[17].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[17].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[17].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[17].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[17].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[17].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[17].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[17].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[17].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[17].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[17].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[17].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[17].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[17].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[17].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[17].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[17].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[17].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[17].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[17].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[17].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[17].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[17].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[17].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[17].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[17].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[17].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[17].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[17].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[17].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[17].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[17].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[17].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[17].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[17].kill, io.flush_pipeline
connect issue_slots[18].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[18].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[18].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[18].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[18].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[18].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[18].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[18].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[18].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[18].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[18].ldspec_miss, io.ld_miss
connect issue_slots[18].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[18].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[18].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[18].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[18].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[18].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[18].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[18].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[18].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[18].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[18].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[18].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[18].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[18].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[18].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[18].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[18].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[18].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[18].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[18].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[18].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[18].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[18].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[18].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[18].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[18].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[18].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[18].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[18].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[18].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[18].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[18].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[18].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[18].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[18].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[18].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[18].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[18].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[18].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[18].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[18].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[18].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[18].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[18].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[18].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[18].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[18].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[18].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[18].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[18].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[18].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[18].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[18].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[18].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[18].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[18].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[18].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[18].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[18].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[18].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[18].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[18].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[18].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[18].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[18].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[18].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[18].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[18].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[18].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[18].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[18].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[18].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[18].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[18].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[18].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[18].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[18].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[18].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[18].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[18].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[18].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[18].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[18].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[18].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[18].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[18].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[18].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[18].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[18].kill, io.flush_pipeline
connect issue_slots[19].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[19].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[19].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[19].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[19].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[19].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[19].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[19].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[19].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[19].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[19].ldspec_miss, io.ld_miss
connect issue_slots[19].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[19].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[19].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[19].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[19].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[19].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[19].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[19].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[19].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[19].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[19].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[19].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[19].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[19].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[19].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[19].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[19].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[19].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[19].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[19].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[19].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[19].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[19].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[19].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[19].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[19].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[19].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[19].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[19].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[19].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[19].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[19].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[19].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[19].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[19].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[19].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[19].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[19].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[19].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[19].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[19].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[19].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[19].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[19].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[19].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[19].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[19].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[19].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[19].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[19].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[19].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[19].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[19].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[19].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[19].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[19].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[19].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[19].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[19].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[19].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[19].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[19].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[19].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[19].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[19].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[19].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[19].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[19].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[19].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[19].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[19].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[19].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[19].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[19].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[19].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[19].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[19].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[19].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[19].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[19].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[19].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[19].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[19].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[19].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[19].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[19].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[19].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[19].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[19].kill, io.flush_pipeline
connect issue_slots[20].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[20].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[20].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[20].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[20].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[20].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[20].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[20].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[20].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[20].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[20].ldspec_miss, io.ld_miss
connect issue_slots[20].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[20].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[20].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[20].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[20].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[20].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[20].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[20].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[20].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[20].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[20].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[20].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[20].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[20].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[20].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[20].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[20].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[20].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[20].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[20].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[20].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[20].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[20].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[20].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[20].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[20].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[20].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[20].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[20].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[20].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[20].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[20].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[20].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[20].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[20].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[20].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[20].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[20].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[20].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[20].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[20].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[20].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[20].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[20].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[20].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[20].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[20].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[20].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[20].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[20].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[20].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[20].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[20].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[20].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[20].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[20].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[20].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[20].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[20].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[20].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[20].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[20].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[20].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[20].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[20].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[20].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[20].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[20].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[20].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[20].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[20].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[20].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[20].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[20].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[20].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[20].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[20].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[20].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[20].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[20].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[20].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[20].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[20].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[20].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[20].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[20].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[20].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[20].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[20].kill, io.flush_pipeline
connect issue_slots[21].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[21].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[21].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[21].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[21].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[21].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[21].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[21].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[21].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[21].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[21].ldspec_miss, io.ld_miss
connect issue_slots[21].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[21].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[21].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[21].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[21].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[21].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[21].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[21].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[21].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[21].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[21].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[21].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[21].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[21].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[21].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[21].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[21].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[21].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[21].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[21].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[21].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[21].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[21].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[21].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[21].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[21].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[21].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[21].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[21].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[21].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[21].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[21].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[21].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[21].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[21].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[21].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[21].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[21].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[21].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[21].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[21].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[21].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[21].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[21].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[21].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[21].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[21].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[21].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[21].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[21].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[21].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[21].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[21].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[21].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[21].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[21].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[21].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[21].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[21].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[21].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[21].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[21].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[21].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[21].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[21].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[21].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[21].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[21].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[21].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[21].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[21].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[21].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[21].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[21].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[21].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[21].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[21].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[21].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[21].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[21].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[21].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[21].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[21].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[21].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[21].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[21].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[21].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[21].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[21].kill, io.flush_pipeline
connect issue_slots[22].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[22].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[22].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[22].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[22].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[22].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[22].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[22].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[22].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[22].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[22].ldspec_miss, io.ld_miss
connect issue_slots[22].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[22].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[22].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[22].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[22].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[22].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[22].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[22].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[22].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[22].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[22].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[22].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[22].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[22].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[22].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[22].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[22].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[22].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[22].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[22].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[22].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[22].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[22].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[22].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[22].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[22].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[22].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[22].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[22].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[22].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[22].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[22].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[22].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[22].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[22].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[22].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[22].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[22].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[22].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[22].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[22].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[22].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[22].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[22].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[22].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[22].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[22].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[22].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[22].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[22].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[22].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[22].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[22].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[22].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[22].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[22].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[22].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[22].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[22].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[22].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[22].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[22].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[22].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[22].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[22].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[22].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[22].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[22].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[22].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[22].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[22].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[22].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[22].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[22].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[22].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[22].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[22].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[22].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[22].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[22].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[22].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[22].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[22].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[22].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[22].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[22].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[22].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[22].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[22].kill, io.flush_pipeline
connect issue_slots[23].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[23].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[23].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[23].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[23].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[23].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[23].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[23].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[23].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[23].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[23].ldspec_miss, io.ld_miss
connect issue_slots[23].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[23].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[23].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[23].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[23].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[23].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[23].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[23].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[23].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[23].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[23].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[23].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[23].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[23].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[23].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[23].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[23].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[23].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[23].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[23].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[23].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[23].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[23].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[23].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[23].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[23].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[23].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[23].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[23].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[23].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[23].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[23].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[23].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[23].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[23].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[23].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[23].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[23].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[23].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[23].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[23].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[23].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[23].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[23].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[23].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[23].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[23].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[23].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[23].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[23].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[23].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[23].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[23].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[23].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[23].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[23].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[23].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[23].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[23].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[23].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[23].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[23].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[23].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[23].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[23].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[23].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[23].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[23].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[23].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[23].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[23].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[23].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[23].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[23].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[23].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[23].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[23].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[23].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[23].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[23].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[23].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[23].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[23].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[23].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[23].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[23].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[23].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[23].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[23].kill, io.flush_pipeline
node _io_event_empty_T = or(issue_slots[0].valid, issue_slots[1].valid)
node _io_event_empty_T_1 = or(_io_event_empty_T, issue_slots[2].valid)
node _io_event_empty_T_2 = or(_io_event_empty_T_1, issue_slots[3].valid)
node _io_event_empty_T_3 = or(_io_event_empty_T_2, issue_slots[4].valid)
node _io_event_empty_T_4 = or(_io_event_empty_T_3, issue_slots[5].valid)
node _io_event_empty_T_5 = or(_io_event_empty_T_4, issue_slots[6].valid)
node _io_event_empty_T_6 = or(_io_event_empty_T_5, issue_slots[7].valid)
node _io_event_empty_T_7 = or(_io_event_empty_T_6, issue_slots[8].valid)
node _io_event_empty_T_8 = or(_io_event_empty_T_7, issue_slots[9].valid)
node _io_event_empty_T_9 = or(_io_event_empty_T_8, issue_slots[10].valid)
node _io_event_empty_T_10 = or(_io_event_empty_T_9, issue_slots[11].valid)
node _io_event_empty_T_11 = or(_io_event_empty_T_10, issue_slots[12].valid)
node _io_event_empty_T_12 = or(_io_event_empty_T_11, issue_slots[13].valid)
node _io_event_empty_T_13 = or(_io_event_empty_T_12, issue_slots[14].valid)
node _io_event_empty_T_14 = or(_io_event_empty_T_13, issue_slots[15].valid)
node _io_event_empty_T_15 = or(_io_event_empty_T_14, issue_slots[16].valid)
node _io_event_empty_T_16 = or(_io_event_empty_T_15, issue_slots[17].valid)
node _io_event_empty_T_17 = or(_io_event_empty_T_16, issue_slots[18].valid)
node _io_event_empty_T_18 = or(_io_event_empty_T_17, issue_slots[19].valid)
node _io_event_empty_T_19 = or(_io_event_empty_T_18, issue_slots[20].valid)
node _io_event_empty_T_20 = or(_io_event_empty_T_19, issue_slots[21].valid)
node _io_event_empty_T_21 = or(_io_event_empty_T_20, issue_slots[22].valid)
node _io_event_empty_T_22 = or(_io_event_empty_T_21, issue_slots[23].valid)
node _io_event_empty_T_23 = eq(_io_event_empty_T_22, UInt<1>(0h0))
connect io.event_empty, _io_event_empty_T_23
node _count_T = add(slots_1.io.valid, slots_2.io.valid)
node _count_T_1 = bits(_count_T, 1, 0)
node _count_T_2 = add(slots_0.io.valid, _count_T_1)
node _count_T_3 = bits(_count_T_2, 1, 0)
node _count_T_4 = add(slots_4.io.valid, slots_5.io.valid)
node _count_T_5 = bits(_count_T_4, 1, 0)
node _count_T_6 = add(slots_3.io.valid, _count_T_5)
node _count_T_7 = bits(_count_T_6, 1, 0)
node _count_T_8 = add(_count_T_3, _count_T_7)
node _count_T_9 = bits(_count_T_8, 2, 0)
node _count_T_10 = add(slots_7.io.valid, slots_8.io.valid)
node _count_T_11 = bits(_count_T_10, 1, 0)
node _count_T_12 = add(slots_6.io.valid, _count_T_11)
node _count_T_13 = bits(_count_T_12, 1, 0)
node _count_T_14 = add(slots_10.io.valid, slots_11.io.valid)
node _count_T_15 = bits(_count_T_14, 1, 0)
node _count_T_16 = add(slots_9.io.valid, _count_T_15)
node _count_T_17 = bits(_count_T_16, 1, 0)
node _count_T_18 = add(_count_T_13, _count_T_17)
node _count_T_19 = bits(_count_T_18, 2, 0)
node _count_T_20 = add(_count_T_9, _count_T_19)
node _count_T_21 = bits(_count_T_20, 3, 0)
node _count_T_22 = add(slots_13.io.valid, slots_14.io.valid)
node _count_T_23 = bits(_count_T_22, 1, 0)
node _count_T_24 = add(slots_12.io.valid, _count_T_23)
node _count_T_25 = bits(_count_T_24, 1, 0)
node _count_T_26 = add(slots_16.io.valid, slots_17.io.valid)
node _count_T_27 = bits(_count_T_26, 1, 0)
node _count_T_28 = add(slots_15.io.valid, _count_T_27)
node _count_T_29 = bits(_count_T_28, 1, 0)
node _count_T_30 = add(_count_T_25, _count_T_29)
node _count_T_31 = bits(_count_T_30, 2, 0)
node _count_T_32 = add(slots_19.io.valid, slots_20.io.valid)
node _count_T_33 = bits(_count_T_32, 1, 0)
node _count_T_34 = add(slots_18.io.valid, _count_T_33)
node _count_T_35 = bits(_count_T_34, 1, 0)
node _count_T_36 = add(slots_22.io.valid, slots_23.io.valid)
node _count_T_37 = bits(_count_T_36, 1, 0)
node _count_T_38 = add(slots_21.io.valid, _count_T_37)
node _count_T_39 = bits(_count_T_38, 1, 0)
node _count_T_40 = add(_count_T_35, _count_T_39)
node _count_T_41 = bits(_count_T_40, 2, 0)
node _count_T_42 = add(_count_T_31, _count_T_41)
node _count_T_43 = bits(_count_T_42, 3, 0)
node _count_T_44 = add(_count_T_21, _count_T_43)
node count = bits(_count_T_44, 4, 0)
node _T_18 = add(issue_slots[1].grant, issue_slots[2].grant)
node _T_19 = bits(_T_18, 1, 0)
node _T_20 = add(issue_slots[0].grant, _T_19)
node _T_21 = bits(_T_20, 1, 0)
node _T_22 = add(issue_slots[4].grant, issue_slots[5].grant)
node _T_23 = bits(_T_22, 1, 0)
node _T_24 = add(issue_slots[3].grant, _T_23)
node _T_25 = bits(_T_24, 1, 0)
node _T_26 = add(_T_21, _T_25)
node _T_27 = bits(_T_26, 2, 0)
node _T_28 = add(issue_slots[7].grant, issue_slots[8].grant)
node _T_29 = bits(_T_28, 1, 0)
node _T_30 = add(issue_slots[6].grant, _T_29)
node _T_31 = bits(_T_30, 1, 0)
node _T_32 = add(issue_slots[10].grant, issue_slots[11].grant)
node _T_33 = bits(_T_32, 1, 0)
node _T_34 = add(issue_slots[9].grant, _T_33)
node _T_35 = bits(_T_34, 1, 0)
node _T_36 = add(_T_31, _T_35)
node _T_37 = bits(_T_36, 2, 0)
node _T_38 = add(_T_27, _T_37)
node _T_39 = bits(_T_38, 3, 0)
node _T_40 = add(issue_slots[13].grant, issue_slots[14].grant)
node _T_41 = bits(_T_40, 1, 0)
node _T_42 = add(issue_slots[12].grant, _T_41)
node _T_43 = bits(_T_42, 1, 0)
node _T_44 = add(issue_slots[16].grant, issue_slots[17].grant)
node _T_45 = bits(_T_44, 1, 0)
node _T_46 = add(issue_slots[15].grant, _T_45)
node _T_47 = bits(_T_46, 1, 0)
node _T_48 = add(_T_43, _T_47)
node _T_49 = bits(_T_48, 2, 0)
node _T_50 = add(issue_slots[19].grant, issue_slots[20].grant)
node _T_51 = bits(_T_50, 1, 0)
node _T_52 = add(issue_slots[18].grant, _T_51)
node _T_53 = bits(_T_52, 1, 0)
node _T_54 = add(issue_slots[22].grant, issue_slots[23].grant)
node _T_55 = bits(_T_54, 1, 0)
node _T_56 = add(issue_slots[21].grant, _T_55)
node _T_57 = bits(_T_56, 1, 0)
node _T_58 = add(_T_53, _T_57)
node _T_59 = bits(_T_58, 2, 0)
node _T_60 = add(_T_49, _T_59)
node _T_61 = bits(_T_60, 3, 0)
node _T_62 = add(_T_39, _T_61)
node _T_63 = bits(_T_62, 4, 0)
node _T_64 = leq(_T_63, UInt<1>(0h1))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit.scala:172 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf_3
assert(clock, _T_64, UInt<1>(0h1), "") : assert_3
node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0))
node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0))
node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0))
node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0))
node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0))
node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0))
node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0))
node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0))
node vacants_8 = eq(issue_slots[8].valid, UInt<1>(0h0))
node vacants_9 = eq(issue_slots[9].valid, UInt<1>(0h0))
node vacants_10 = eq(issue_slots[10].valid, UInt<1>(0h0))
node vacants_11 = eq(issue_slots[11].valid, UInt<1>(0h0))
node vacants_12 = eq(issue_slots[12].valid, UInt<1>(0h0))
node vacants_13 = eq(issue_slots[13].valid, UInt<1>(0h0))
node vacants_14 = eq(issue_slots[14].valid, UInt<1>(0h0))
node vacants_15 = eq(issue_slots[15].valid, UInt<1>(0h0))
node vacants_16 = eq(issue_slots[16].valid, UInt<1>(0h0))
node vacants_17 = eq(issue_slots[17].valid, UInt<1>(0h0))
node vacants_18 = eq(issue_slots[18].valid, UInt<1>(0h0))
node vacants_19 = eq(issue_slots[19].valid, UInt<1>(0h0))
node vacants_20 = eq(issue_slots[20].valid, UInt<1>(0h0))
node vacants_21 = eq(issue_slots[21].valid, UInt<1>(0h0))
node vacants_22 = eq(issue_slots[22].valid, UInt<1>(0h0))
node vacants_23 = eq(issue_slots[23].valid, UInt<1>(0h0))
node vacants_24 = eq(io.dis_uops[0].valid, UInt<1>(0h0))
node vacants_25 = eq(io.dis_uops[1].valid, UInt<1>(0h0))
node vacants_26 = eq(io.dis_uops[2].valid, UInt<1>(0h0))
wire _WIRE_3 : UInt<3>
wire _WIRE_4 : UInt<3>
wire _WIRE_5 : UInt<3>
wire _WIRE_6 : UInt<3>
wire _WIRE_7 : UInt<3>
wire _WIRE_8 : UInt<3>
wire _WIRE_9 : UInt<3>
wire _WIRE_10 : UInt<3>
wire _WIRE_11 : UInt<3>
wire _WIRE_12 : UInt<3>
wire _WIRE_13 : UInt<3>
wire _WIRE_14 : UInt<3>
wire _WIRE_15 : UInt<3>
wire _WIRE_16 : UInt<3>
wire _WIRE_17 : UInt<3>
wire _WIRE_18 : UInt<3>
wire _WIRE_19 : UInt<3>
wire _WIRE_20 : UInt<3>
wire _WIRE_21 : UInt<3>
wire _WIRE_22 : UInt<3>
wire _WIRE_23 : UInt<3>
wire _WIRE_24 : UInt<3>
wire _WIRE_25 : UInt<3>
wire _WIRE_26 : UInt<3>
wire _WIRE_27 : UInt<3>
wire _WIRE_28 : UInt<3>
wire _WIRE_29 : UInt<3>
connect _WIRE_3, UInt<1>(0h0)
wire next : UInt<3>
connect next, _WIRE_3
node _T_68 = eq(_WIRE_3, UInt<1>(0h0))
node _T_69 = and(_T_68, vacants_0)
when _T_69 :
connect next, UInt<1>(0h1)
else :
node _T_70 = bits(_WIRE_3, 2, 2)
node _T_71 = eq(_T_70, UInt<1>(0h0))
node _T_72 = and(_T_71, vacants_0)
when _T_72 :
node _next_T = dshl(_WIRE_3, UInt<1>(0h1))
connect next, _next_T
connect _WIRE_4, next
wire next_1 : UInt<3>
connect next_1, _WIRE_4
node _T_73 = eq(_WIRE_4, UInt<1>(0h0))
node _T_74 = and(_T_73, vacants_1)
when _T_74 :
connect next_1, UInt<1>(0h1)
else :
node _T_75 = bits(_WIRE_4, 2, 2)
node _T_76 = eq(_T_75, UInt<1>(0h0))
node _T_77 = and(_T_76, vacants_1)
when _T_77 :
node _next_T_1 = dshl(_WIRE_4, UInt<1>(0h1))
connect next_1, _next_T_1
connect _WIRE_5, next_1
wire next_2 : UInt<3>
connect next_2, _WIRE_5
node _T_78 = eq(_WIRE_5, UInt<1>(0h0))
node _T_79 = and(_T_78, vacants_2)
when _T_79 :
connect next_2, UInt<1>(0h1)
else :
node _T_80 = bits(_WIRE_5, 2, 2)
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = and(_T_81, vacants_2)
when _T_82 :
node _next_T_2 = dshl(_WIRE_5, UInt<1>(0h1))
connect next_2, _next_T_2
connect _WIRE_6, next_2
wire next_3 : UInt<3>
connect next_3, _WIRE_6
node _T_83 = eq(_WIRE_6, UInt<1>(0h0))
node _T_84 = and(_T_83, vacants_3)
when _T_84 :
connect next_3, UInt<1>(0h1)
else :
node _T_85 = bits(_WIRE_6, 2, 2)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = and(_T_86, vacants_3)
when _T_87 :
node _next_T_3 = dshl(_WIRE_6, UInt<1>(0h1))
connect next_3, _next_T_3
connect _WIRE_7, next_3
wire next_4 : UInt<3>
connect next_4, _WIRE_7
node _T_88 = eq(_WIRE_7, UInt<1>(0h0))
node _T_89 = and(_T_88, vacants_4)
when _T_89 :
connect next_4, UInt<1>(0h1)
else :
node _T_90 = bits(_WIRE_7, 2, 2)
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = and(_T_91, vacants_4)
when _T_92 :
node _next_T_4 = dshl(_WIRE_7, UInt<1>(0h1))
connect next_4, _next_T_4
connect _WIRE_8, next_4
wire next_5 : UInt<3>
connect next_5, _WIRE_8
node _T_93 = eq(_WIRE_8, UInt<1>(0h0))
node _T_94 = and(_T_93, vacants_5)
when _T_94 :
connect next_5, UInt<1>(0h1)
else :
node _T_95 = bits(_WIRE_8, 2, 2)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = and(_T_96, vacants_5)
when _T_97 :
node _next_T_5 = dshl(_WIRE_8, UInt<1>(0h1))
connect next_5, _next_T_5
connect _WIRE_9, next_5
wire next_6 : UInt<3>
connect next_6, _WIRE_9
node _T_98 = eq(_WIRE_9, UInt<1>(0h0))
node _T_99 = and(_T_98, vacants_6)
when _T_99 :
connect next_6, UInt<1>(0h1)
else :
node _T_100 = bits(_WIRE_9, 2, 2)
node _T_101 = eq(_T_100, UInt<1>(0h0))
node _T_102 = and(_T_101, vacants_6)
when _T_102 :
node _next_T_6 = dshl(_WIRE_9, UInt<1>(0h1))
connect next_6, _next_T_6
connect _WIRE_10, next_6
wire next_7 : UInt<3>
connect next_7, _WIRE_10
node _T_103 = eq(_WIRE_10, UInt<1>(0h0))
node _T_104 = and(_T_103, vacants_7)
when _T_104 :
connect next_7, UInt<1>(0h1)
else :
node _T_105 = bits(_WIRE_10, 2, 2)
node _T_106 = eq(_T_105, UInt<1>(0h0))
node _T_107 = and(_T_106, vacants_7)
when _T_107 :
node _next_T_7 = dshl(_WIRE_10, UInt<1>(0h1))
connect next_7, _next_T_7
connect _WIRE_11, next_7
wire next_8 : UInt<3>
connect next_8, _WIRE_11
node _T_108 = eq(_WIRE_11, UInt<1>(0h0))
node _T_109 = and(_T_108, vacants_8)
when _T_109 :
connect next_8, UInt<1>(0h1)
else :
node _T_110 = bits(_WIRE_11, 2, 2)
node _T_111 = eq(_T_110, UInt<1>(0h0))
node _T_112 = and(_T_111, vacants_8)
when _T_112 :
node _next_T_8 = dshl(_WIRE_11, UInt<1>(0h1))
connect next_8, _next_T_8
connect _WIRE_12, next_8
wire next_9 : UInt<3>
connect next_9, _WIRE_12
node _T_113 = eq(_WIRE_12, UInt<1>(0h0))
node _T_114 = and(_T_113, vacants_9)
when _T_114 :
connect next_9, UInt<1>(0h1)
else :
node _T_115 = bits(_WIRE_12, 2, 2)
node _T_116 = eq(_T_115, UInt<1>(0h0))
node _T_117 = and(_T_116, vacants_9)
when _T_117 :
node _next_T_9 = dshl(_WIRE_12, UInt<1>(0h1))
connect next_9, _next_T_9
connect _WIRE_13, next_9
wire next_10 : UInt<3>
connect next_10, _WIRE_13
node _T_118 = eq(_WIRE_13, UInt<1>(0h0))
node _T_119 = and(_T_118, vacants_10)
when _T_119 :
connect next_10, UInt<1>(0h1)
else :
node _T_120 = bits(_WIRE_13, 2, 2)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = and(_T_121, vacants_10)
when _T_122 :
node _next_T_10 = dshl(_WIRE_13, UInt<1>(0h1))
connect next_10, _next_T_10
connect _WIRE_14, next_10
wire next_11 : UInt<3>
connect next_11, _WIRE_14
node _T_123 = eq(_WIRE_14, UInt<1>(0h0))
node _T_124 = and(_T_123, vacants_11)
when _T_124 :
connect next_11, UInt<1>(0h1)
else :
node _T_125 = bits(_WIRE_14, 2, 2)
node _T_126 = eq(_T_125, UInt<1>(0h0))
node _T_127 = and(_T_126, vacants_11)
when _T_127 :
node _next_T_11 = dshl(_WIRE_14, UInt<1>(0h1))
connect next_11, _next_T_11
connect _WIRE_15, next_11
wire next_12 : UInt<3>
connect next_12, _WIRE_15
node _T_128 = eq(_WIRE_15, UInt<1>(0h0))
node _T_129 = and(_T_128, vacants_12)
when _T_129 :
connect next_12, UInt<1>(0h1)
else :
node _T_130 = bits(_WIRE_15, 2, 2)
node _T_131 = eq(_T_130, UInt<1>(0h0))
node _T_132 = and(_T_131, vacants_12)
when _T_132 :
node _next_T_12 = dshl(_WIRE_15, UInt<1>(0h1))
connect next_12, _next_T_12
connect _WIRE_16, next_12
wire next_13 : UInt<3>
connect next_13, _WIRE_16
node _T_133 = eq(_WIRE_16, UInt<1>(0h0))
node _T_134 = and(_T_133, vacants_13)
when _T_134 :
connect next_13, UInt<1>(0h1)
else :
node _T_135 = bits(_WIRE_16, 2, 2)
node _T_136 = eq(_T_135, UInt<1>(0h0))
node _T_137 = and(_T_136, vacants_13)
when _T_137 :
node _next_T_13 = dshl(_WIRE_16, UInt<1>(0h1))
connect next_13, _next_T_13
connect _WIRE_17, next_13
wire next_14 : UInt<3>
connect next_14, _WIRE_17
node _T_138 = eq(_WIRE_17, UInt<1>(0h0))
node _T_139 = and(_T_138, vacants_14)
when _T_139 :
connect next_14, UInt<1>(0h1)
else :
node _T_140 = bits(_WIRE_17, 2, 2)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = and(_T_141, vacants_14)
when _T_142 :
node _next_T_14 = dshl(_WIRE_17, UInt<1>(0h1))
connect next_14, _next_T_14
connect _WIRE_18, next_14
wire next_15 : UInt<3>
connect next_15, _WIRE_18
node _T_143 = eq(_WIRE_18, UInt<1>(0h0))
node _T_144 = and(_T_143, vacants_15)
when _T_144 :
connect next_15, UInt<1>(0h1)
else :
node _T_145 = bits(_WIRE_18, 2, 2)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = and(_T_146, vacants_15)
when _T_147 :
node _next_T_15 = dshl(_WIRE_18, UInt<1>(0h1))
connect next_15, _next_T_15
connect _WIRE_19, next_15
wire next_16 : UInt<3>
connect next_16, _WIRE_19
node _T_148 = eq(_WIRE_19, UInt<1>(0h0))
node _T_149 = and(_T_148, vacants_16)
when _T_149 :
connect next_16, UInt<1>(0h1)
else :
node _T_150 = bits(_WIRE_19, 2, 2)
node _T_151 = eq(_T_150, UInt<1>(0h0))
node _T_152 = and(_T_151, vacants_16)
when _T_152 :
node _next_T_16 = dshl(_WIRE_19, UInt<1>(0h1))
connect next_16, _next_T_16
connect _WIRE_20, next_16
wire next_17 : UInt<3>
connect next_17, _WIRE_20
node _T_153 = eq(_WIRE_20, UInt<1>(0h0))
node _T_154 = and(_T_153, vacants_17)
when _T_154 :
connect next_17, UInt<1>(0h1)
else :
node _T_155 = bits(_WIRE_20, 2, 2)
node _T_156 = eq(_T_155, UInt<1>(0h0))
node _T_157 = and(_T_156, vacants_17)
when _T_157 :
node _next_T_17 = dshl(_WIRE_20, UInt<1>(0h1))
connect next_17, _next_T_17
connect _WIRE_21, next_17
wire next_18 : UInt<3>
connect next_18, _WIRE_21
node _T_158 = eq(_WIRE_21, UInt<1>(0h0))
node _T_159 = and(_T_158, vacants_18)
when _T_159 :
connect next_18, UInt<1>(0h1)
else :
node _T_160 = bits(_WIRE_21, 2, 2)
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = and(_T_161, vacants_18)
when _T_162 :
node _next_T_18 = dshl(_WIRE_21, UInt<1>(0h1))
connect next_18, _next_T_18
connect _WIRE_22, next_18
wire next_19 : UInt<3>
connect next_19, _WIRE_22
node _T_163 = eq(_WIRE_22, UInt<1>(0h0))
node _T_164 = and(_T_163, vacants_19)
when _T_164 :
connect next_19, UInt<1>(0h1)
else :
node _T_165 = bits(_WIRE_22, 2, 2)
node _T_166 = eq(_T_165, UInt<1>(0h0))
node _T_167 = and(_T_166, vacants_19)
when _T_167 :
node _next_T_19 = dshl(_WIRE_22, UInt<1>(0h1))
connect next_19, _next_T_19
connect _WIRE_23, next_19
wire next_20 : UInt<3>
connect next_20, _WIRE_23
node _T_168 = eq(_WIRE_23, UInt<1>(0h0))
node _T_169 = and(_T_168, vacants_20)
when _T_169 :
connect next_20, UInt<1>(0h1)
else :
node _T_170 = bits(_WIRE_23, 2, 2)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = and(_T_171, vacants_20)
when _T_172 :
node _next_T_20 = dshl(_WIRE_23, UInt<1>(0h1))
connect next_20, _next_T_20
connect _WIRE_24, next_20
wire next_21 : UInt<3>
connect next_21, _WIRE_24
node _T_173 = eq(_WIRE_24, UInt<1>(0h0))
node _T_174 = and(_T_173, vacants_21)
when _T_174 :
connect next_21, UInt<1>(0h1)
else :
node _T_175 = bits(_WIRE_24, 2, 2)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = and(_T_176, vacants_21)
when _T_177 :
node _next_T_21 = dshl(_WIRE_24, UInt<1>(0h1))
connect next_21, _next_T_21
connect _WIRE_25, next_21
wire next_22 : UInt<3>
connect next_22, _WIRE_25
node _T_178 = eq(_WIRE_25, UInt<1>(0h0))
node _T_179 = and(_T_178, vacants_22)
when _T_179 :
connect next_22, UInt<1>(0h1)
else :
node _T_180 = bits(_WIRE_25, 2, 2)
node _T_181 = eq(_T_180, UInt<1>(0h0))
node _T_182 = and(_T_181, vacants_22)
when _T_182 :
node _next_T_22 = dshl(_WIRE_25, UInt<1>(0h1))
connect next_22, _next_T_22
connect _WIRE_26, next_22
wire next_23 : UInt<3>
connect next_23, _WIRE_26
node _T_183 = eq(_WIRE_26, UInt<1>(0h0))
node _T_184 = and(_T_183, vacants_23)
when _T_184 :
connect next_23, UInt<1>(0h1)
else :
node _T_185 = bits(_WIRE_26, 2, 2)
node _T_186 = eq(_T_185, UInt<1>(0h0))
node _T_187 = and(_T_186, vacants_23)
when _T_187 :
node _next_T_23 = dshl(_WIRE_26, UInt<1>(0h1))
connect next_23, _next_T_23
connect _WIRE_27, next_23
wire next_24 : UInt<3>
connect next_24, _WIRE_27
node _T_188 = eq(_WIRE_27, UInt<1>(0h0))
node _T_189 = and(_T_188, vacants_24)
when _T_189 :
connect next_24, UInt<1>(0h1)
else :
node _T_190 = bits(_WIRE_27, 2, 2)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = and(_T_191, vacants_24)
when _T_192 :
node _next_T_24 = dshl(_WIRE_27, UInt<1>(0h1))
connect next_24, _next_T_24
connect _WIRE_28, next_24
wire next_25 : UInt<3>
connect next_25, _WIRE_28
node _T_193 = eq(_WIRE_28, UInt<1>(0h0))
node _T_194 = and(_T_193, vacants_25)
when _T_194 :
connect next_25, UInt<1>(0h1)
else :
node _T_195 = bits(_WIRE_28, 2, 2)
node _T_196 = eq(_T_195, UInt<1>(0h0))
node _T_197 = and(_T_196, vacants_25)
when _T_197 :
node _next_T_25 = dshl(_WIRE_28, UInt<1>(0h1))
connect next_25, _next_T_25
connect _WIRE_29, next_25
node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0))
node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T)
node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0))
node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2)
node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0))
node will_be_valid_24 = and(_will_be_valid_T_3, _will_be_valid_T_4)
node _will_be_valid_T_5 = eq(_WIRE_1.exception, UInt<1>(0h0))
node _will_be_valid_T_6 = and(io.dis_uops[1].valid, _will_be_valid_T_5)
node _will_be_valid_T_7 = eq(_WIRE_1.is_fence, UInt<1>(0h0))
node _will_be_valid_T_8 = and(_will_be_valid_T_6, _will_be_valid_T_7)
node _will_be_valid_T_9 = eq(_WIRE_1.is_fencei, UInt<1>(0h0))
node will_be_valid_25 = and(_will_be_valid_T_8, _will_be_valid_T_9)
node _will_be_valid_T_10 = eq(_WIRE_2.exception, UInt<1>(0h0))
node _will_be_valid_T_11 = and(io.dis_uops[2].valid, _will_be_valid_T_10)
node _will_be_valid_T_12 = eq(_WIRE_2.is_fence, UInt<1>(0h0))
node _will_be_valid_T_13 = and(_will_be_valid_T_11, _will_be_valid_T_12)
node _will_be_valid_T_14 = eq(_WIRE_2.is_fencei, UInt<1>(0h0))
node will_be_valid_26 = and(_will_be_valid_T_13, _will_be_valid_T_14)
connect issue_slots[0].in_uop.valid, UInt<1>(0h0)
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal
connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr
connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br
connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned
connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned
connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state
connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std
connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta
connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load
connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd
connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw
connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn
connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel
connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel
connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel
connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type
connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code
connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst
connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc
node _T_198 = eq(_WIRE_4, UInt<1>(0h1))
when _T_198 :
connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal
connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr
connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br
connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned
connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned
connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state
connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std
connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta
connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load
connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd
connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw
connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn
connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel
connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel
connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel
connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type
connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code
connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst
connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc
node _T_199 = eq(_WIRE_5, UInt<2>(0h2))
when _T_199 :
connect issue_slots[0].in_uop.valid, issue_slots[2].will_be_valid
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal
connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr
connect issue_slots[0].in_uop.bits.is_br, issue_slots[2].out_uop.is_br
connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned
connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned
connect issue_slots[0].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state
connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std
connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta
connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load
connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd
connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw
connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn
connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel
connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel
connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel
connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type
connect issue_slots[0].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code
connect issue_slots[0].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[2].out_uop.inst
connect issue_slots[0].in_uop.bits.uopc, issue_slots[2].out_uop.uopc
node _T_200 = eq(_WIRE_6, UInt<3>(0h4))
when _T_200 :
connect issue_slots[0].in_uop.valid, issue_slots[3].will_be_valid
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal
connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr
connect issue_slots[0].in_uop.bits.is_br, issue_slots[3].out_uop.is_br
connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned
connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned
connect issue_slots[0].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state
connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std
connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta
connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load
connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd
connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw
connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn
connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel
connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel
connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel
connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type
connect issue_slots[0].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code
connect issue_slots[0].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[3].out_uop.inst
connect issue_slots[0].in_uop.bits.uopc, issue_slots[3].out_uop.uopc
node _issue_slots_0_clear_T = neq(_WIRE_3, UInt<1>(0h0))
connect issue_slots[0].clear, _issue_slots_0_clear_T
connect issue_slots[1].in_uop.valid, UInt<1>(0h0)
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal
connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr
connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br
connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned
connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned
connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state
connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std
connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta
connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load
connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd
connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw
connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn
connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel
connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel
connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel
connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type
connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code
connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst
connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc
node _T_201 = eq(_WIRE_5, UInt<1>(0h1))
when _T_201 :
connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal
connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr
connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br
connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned
connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned
connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state
connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std
connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta
connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load
connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd
connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw
connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn
connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel
connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel
connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel
connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type
connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code
connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst
connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc
node _T_202 = eq(_WIRE_6, UInt<2>(0h2))
when _T_202 :
connect issue_slots[1].in_uop.valid, issue_slots[3].will_be_valid
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal
connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr
connect issue_slots[1].in_uop.bits.is_br, issue_slots[3].out_uop.is_br
connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned
connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned
connect issue_slots[1].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state
connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std
connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta
connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load
connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd
connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw
connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn
connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel
connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel
connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel
connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type
connect issue_slots[1].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code
connect issue_slots[1].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[3].out_uop.inst
connect issue_slots[1].in_uop.bits.uopc, issue_slots[3].out_uop.uopc
node _T_203 = eq(_WIRE_7, UInt<3>(0h4))
when _T_203 :
connect issue_slots[1].in_uop.valid, issue_slots[4].will_be_valid
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal
connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr
connect issue_slots[1].in_uop.bits.is_br, issue_slots[4].out_uop.is_br
connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned
connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned
connect issue_slots[1].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state
connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std
connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta
connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load
connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd
connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw
connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn
connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel
connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel
connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel
connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type
connect issue_slots[1].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code
connect issue_slots[1].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[4].out_uop.inst
connect issue_slots[1].in_uop.bits.uopc, issue_slots[4].out_uop.uopc
node _issue_slots_1_clear_T = neq(_WIRE_4, UInt<1>(0h0))
connect issue_slots[1].clear, _issue_slots_1_clear_T
connect issue_slots[2].in_uop.valid, UInt<1>(0h0)
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal
connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr
connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br
connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned
connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned
connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state
connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std
connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta
connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load
connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd
connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw
connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn
connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel
connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel
connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel
connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type
connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code
connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst
connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc
node _T_204 = eq(_WIRE_6, UInt<1>(0h1))
when _T_204 :
connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal
connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr
connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br
connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned
connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned
connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state
connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std
connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta
connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load
connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd
connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw
connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn
connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel
connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel
connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel
connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type
connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code
connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst
connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc
node _T_205 = eq(_WIRE_7, UInt<2>(0h2))
when _T_205 :
connect issue_slots[2].in_uop.valid, issue_slots[4].will_be_valid
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal
connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr
connect issue_slots[2].in_uop.bits.is_br, issue_slots[4].out_uop.is_br
connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned
connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned
connect issue_slots[2].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state
connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std
connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta
connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load
connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd
connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw
connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn
connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel
connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel
connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel
connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type
connect issue_slots[2].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code
connect issue_slots[2].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[4].out_uop.inst
connect issue_slots[2].in_uop.bits.uopc, issue_slots[4].out_uop.uopc
node _T_206 = eq(_WIRE_8, UInt<3>(0h4))
when _T_206 :
connect issue_slots[2].in_uop.valid, issue_slots[5].will_be_valid
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal
connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr
connect issue_slots[2].in_uop.bits.is_br, issue_slots[5].out_uop.is_br
connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned
connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned
connect issue_slots[2].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state
connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std
connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta
connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load
connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd
connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw
connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn
connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel
connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel
connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel
connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type
connect issue_slots[2].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code
connect issue_slots[2].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[5].out_uop.inst
connect issue_slots[2].in_uop.bits.uopc, issue_slots[5].out_uop.uopc
node _issue_slots_2_clear_T = neq(_WIRE_5, UInt<1>(0h0))
connect issue_slots[2].clear, _issue_slots_2_clear_T
connect issue_slots[3].in_uop.valid, UInt<1>(0h0)
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal
connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr
connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br
connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned
connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned
connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state
connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std
connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta
connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load
connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd
connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw
connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn
connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel
connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel
connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel
connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type
connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code
connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst
connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc
node _T_207 = eq(_WIRE_7, UInt<1>(0h1))
when _T_207 :
connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal
connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr
connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br
connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned
connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned
connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state
connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std
connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta
connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load
connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd
connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw
connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn
connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel
connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel
connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel
connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type
connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code
connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst
connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc
node _T_208 = eq(_WIRE_8, UInt<2>(0h2))
when _T_208 :
connect issue_slots[3].in_uop.valid, issue_slots[5].will_be_valid
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal
connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr
connect issue_slots[3].in_uop.bits.is_br, issue_slots[5].out_uop.is_br
connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned
connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned
connect issue_slots[3].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state
connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std
connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta
connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load
connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd
connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw
connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn
connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel
connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel
connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel
connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type
connect issue_slots[3].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code
connect issue_slots[3].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[5].out_uop.inst
connect issue_slots[3].in_uop.bits.uopc, issue_slots[5].out_uop.uopc
node _T_209 = eq(_WIRE_9, UInt<3>(0h4))
when _T_209 :
connect issue_slots[3].in_uop.valid, issue_slots[6].will_be_valid
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal
connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr
connect issue_slots[3].in_uop.bits.is_br, issue_slots[6].out_uop.is_br
connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned
connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned
connect issue_slots[3].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state
connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std
connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta
connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load
connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd
connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw
connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn
connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel
connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel
connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel
connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type
connect issue_slots[3].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code
connect issue_slots[3].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[6].out_uop.inst
connect issue_slots[3].in_uop.bits.uopc, issue_slots[6].out_uop.uopc
node _issue_slots_3_clear_T = neq(_WIRE_6, UInt<1>(0h0))
connect issue_slots[3].clear, _issue_slots_3_clear_T
connect issue_slots[4].in_uop.valid, UInt<1>(0h0)
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal
connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr
connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br
connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned
connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned
connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state
connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std
connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta
connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load
connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd
connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw
connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn
connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel
connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel
connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel
connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type
connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code
connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst
connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc
node _T_210 = eq(_WIRE_8, UInt<1>(0h1))
when _T_210 :
connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal
connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr
connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br
connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned
connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned
connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state
connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std
connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta
connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load
connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd
connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw
connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn
connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel
connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel
connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel
connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type
connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code
connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst
connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc
node _T_211 = eq(_WIRE_9, UInt<2>(0h2))
when _T_211 :
connect issue_slots[4].in_uop.valid, issue_slots[6].will_be_valid
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal
connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr
connect issue_slots[4].in_uop.bits.is_br, issue_slots[6].out_uop.is_br
connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned
connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned
connect issue_slots[4].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state
connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std
connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta
connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load
connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd
connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw
connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn
connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel
connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel
connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel
connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type
connect issue_slots[4].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code
connect issue_slots[4].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[6].out_uop.inst
connect issue_slots[4].in_uop.bits.uopc, issue_slots[6].out_uop.uopc
node _T_212 = eq(_WIRE_10, UInt<3>(0h4))
when _T_212 :
connect issue_slots[4].in_uop.valid, issue_slots[7].will_be_valid
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal
connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr
connect issue_slots[4].in_uop.bits.is_br, issue_slots[7].out_uop.is_br
connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned
connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned
connect issue_slots[4].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state
connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std
connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta
connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load
connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd
connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw
connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn
connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel
connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel
connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel
connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type
connect issue_slots[4].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code
connect issue_slots[4].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[7].out_uop.inst
connect issue_slots[4].in_uop.bits.uopc, issue_slots[7].out_uop.uopc
node _issue_slots_4_clear_T = neq(_WIRE_7, UInt<1>(0h0))
connect issue_slots[4].clear, _issue_slots_4_clear_T
connect issue_slots[5].in_uop.valid, UInt<1>(0h0)
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal
connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr
connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br
connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned
connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned
connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state
connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std
connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta
connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load
connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd
connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw
connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn
connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel
connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel
connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel
connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type
connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code
connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst
connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc
node _T_213 = eq(_WIRE_9, UInt<1>(0h1))
when _T_213 :
connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal
connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr
connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br
connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned
connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned
connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state
connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std
connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta
connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load
connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd
connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw
connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn
connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel
connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel
connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel
connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type
connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code
connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst
connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc
node _T_214 = eq(_WIRE_10, UInt<2>(0h2))
when _T_214 :
connect issue_slots[5].in_uop.valid, issue_slots[7].will_be_valid
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal
connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr
connect issue_slots[5].in_uop.bits.is_br, issue_slots[7].out_uop.is_br
connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned
connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned
connect issue_slots[5].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state
connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std
connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta
connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load
connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd
connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw
connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn
connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel
connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel
connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel
connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type
connect issue_slots[5].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code
connect issue_slots[5].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[7].out_uop.inst
connect issue_slots[5].in_uop.bits.uopc, issue_slots[7].out_uop.uopc
node _T_215 = eq(_WIRE_11, UInt<3>(0h4))
when _T_215 :
connect issue_slots[5].in_uop.valid, issue_slots[8].will_be_valid
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[8].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[8].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[8].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[8].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[8].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[8].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[8].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.taken, issue_slots[8].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal
connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr
connect issue_slots[5].in_uop.bits.is_br, issue_slots[8].out_uop.is_br
connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned
connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned
connect issue_slots[5].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state
connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std
connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta
connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load
connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd
connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw
connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn
connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel
connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel
connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel
connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type
connect issue_slots[5].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code
connect issue_slots[5].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[8].out_uop.inst
connect issue_slots[5].in_uop.bits.uopc, issue_slots[8].out_uop.uopc
node _issue_slots_5_clear_T = neq(_WIRE_8, UInt<1>(0h0))
connect issue_slots[5].clear, _issue_slots_5_clear_T
connect issue_slots[6].in_uop.valid, UInt<1>(0h0)
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal
connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr
connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br
connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned
connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned
connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state
connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std
connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta
connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load
connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd
connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw
connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn
connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel
connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel
connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel
connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type
connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code
connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst
connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc
node _T_216 = eq(_WIRE_10, UInt<1>(0h1))
when _T_216 :
connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal
connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr
connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br
connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned
connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned
connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state
connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std
connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta
connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load
connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd
connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw
connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn
connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel
connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel
connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel
connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type
connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code
connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst
connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc
node _T_217 = eq(_WIRE_11, UInt<2>(0h2))
when _T_217 :
connect issue_slots[6].in_uop.valid, issue_slots[8].will_be_valid
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[8].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[8].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[8].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[8].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[8].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[8].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[8].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.taken, issue_slots[8].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal
connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr
connect issue_slots[6].in_uop.bits.is_br, issue_slots[8].out_uop.is_br
connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned
connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned
connect issue_slots[6].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state
connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std
connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta
connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load
connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd
connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw
connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn
connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel
connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel
connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel
connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type
connect issue_slots[6].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code
connect issue_slots[6].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[8].out_uop.inst
connect issue_slots[6].in_uop.bits.uopc, issue_slots[8].out_uop.uopc
node _T_218 = eq(_WIRE_12, UInt<3>(0h4))
when _T_218 :
connect issue_slots[6].in_uop.valid, issue_slots[9].will_be_valid
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[9].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[9].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[9].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[9].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[9].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[9].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[9].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.taken, issue_slots[9].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal
connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr
connect issue_slots[6].in_uop.bits.is_br, issue_slots[9].out_uop.is_br
connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned
connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned
connect issue_slots[6].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state
connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std
connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta
connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load
connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd
connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw
connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn
connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel
connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel
connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel
connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type
connect issue_slots[6].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code
connect issue_slots[6].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[9].out_uop.inst
connect issue_slots[6].in_uop.bits.uopc, issue_slots[9].out_uop.uopc
node _issue_slots_6_clear_T = neq(_WIRE_9, UInt<1>(0h0))
connect issue_slots[6].clear, _issue_slots_6_clear_T
connect issue_slots[7].in_uop.valid, UInt<1>(0h0)
connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single
connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val
connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype
connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val
connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3
connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2
connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1
connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1
connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq
connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo
connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence
connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd
connect issue_slots[7].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable
connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause
connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception
connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred
connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3
connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2
connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1
connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx
connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr
connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed
connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken
connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx
connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag
connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask
connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb
connect issue_slots[7].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal
connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr
connect issue_slots[7].in_uop.bits.is_br, issue_slots[8].out_uop.is_br
connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned
connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned
connect issue_slots[7].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state
connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std
connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta
connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load
connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd
connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw
connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn
connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel
connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel
connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel
connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type
connect issue_slots[7].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code
connect issue_slots[7].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type
connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst
connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst
connect issue_slots[7].in_uop.bits.uopc, issue_slots[8].out_uop.uopc
node _T_219 = eq(_WIRE_11, UInt<1>(0h1))
when _T_219 :
connect issue_slots[7].in_uop.valid, issue_slots[8].will_be_valid
connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single
connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val
connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype
connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val
connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3
connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2
connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1
connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1
connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq
connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo
connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence
connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd
connect issue_slots[7].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable
connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause
connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception
connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred
connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3
connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2
connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1
connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx
connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr
connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed
connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken
connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx
connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag
connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask
connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb
connect issue_slots[7].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal
connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr
connect issue_slots[7].in_uop.bits.is_br, issue_slots[8].out_uop.is_br
connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned
connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned
connect issue_slots[7].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state
connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std
connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta
connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load
connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd
connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw
connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn
connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel
connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel
connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel
connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type
connect issue_slots[7].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code
connect issue_slots[7].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type
connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst
connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst
connect issue_slots[7].in_uop.bits.uopc, issue_slots[8].out_uop.uopc
node _T_220 = eq(_WIRE_12, UInt<2>(0h2))
when _T_220 :
connect issue_slots[7].in_uop.valid, issue_slots[9].will_be_valid
connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single
connect issue_slots[7].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val
connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype
connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val
connect issue_slots[7].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3
connect issue_slots[7].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2
connect issue_slots[7].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1
connect issue_slots[7].in_uop.bits.ldst, issue_slots[9].out_uop.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1
connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq
connect issue_slots[7].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo
connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence
connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd
connect issue_slots[7].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable
connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause
connect issue_slots[7].in_uop.bits.exception, issue_slots[9].out_uop.exception
connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, issue_slots[9].out_uop.ppred
connect issue_slots[7].in_uop.bits.prs3, issue_slots[9].out_uop.prs3
connect issue_slots[7].in_uop.bits.prs2, issue_slots[9].out_uop.prs2
connect issue_slots[7].in_uop.bits.prs1, issue_slots[9].out_uop.prs1
connect issue_slots[7].in_uop.bits.pdst, issue_slots[9].out_uop.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx
connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr
connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed
connect issue_slots[7].in_uop.bits.taken, issue_slots[9].out_uop.taken
connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx
connect issue_slots[7].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag
connect issue_slots[7].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask
connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb
connect issue_slots[7].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal
connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr
connect issue_slots[7].in_uop.bits.is_br, issue_slots[9].out_uop.is_br
connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned
connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned
connect issue_slots[7].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state
connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std
connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta
connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load
connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd
connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw
connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn
connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel
connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel
connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel
connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type
connect issue_slots[7].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code
connect issue_slots[7].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type
connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst
connect issue_slots[7].in_uop.bits.inst, issue_slots[9].out_uop.inst
connect issue_slots[7].in_uop.bits.uopc, issue_slots[9].out_uop.uopc
node _T_221 = eq(_WIRE_13, UInt<3>(0h4))
when _T_221 :
connect issue_slots[7].in_uop.valid, issue_slots[10].will_be_valid
connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single
connect issue_slots[7].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val
connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype
connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val
connect issue_slots[7].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3
connect issue_slots[7].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2
connect issue_slots[7].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1
connect issue_slots[7].in_uop.bits.ldst, issue_slots[10].out_uop.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1
connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq
connect issue_slots[7].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo
connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence
connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd
connect issue_slots[7].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable
connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause
connect issue_slots[7].in_uop.bits.exception, issue_slots[10].out_uop.exception
connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, issue_slots[10].out_uop.ppred
connect issue_slots[7].in_uop.bits.prs3, issue_slots[10].out_uop.prs3
connect issue_slots[7].in_uop.bits.prs2, issue_slots[10].out_uop.prs2
connect issue_slots[7].in_uop.bits.prs1, issue_slots[10].out_uop.prs1
connect issue_slots[7].in_uop.bits.pdst, issue_slots[10].out_uop.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx
connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr
connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed
connect issue_slots[7].in_uop.bits.taken, issue_slots[10].out_uop.taken
connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx
connect issue_slots[7].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag
connect issue_slots[7].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask
connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb
connect issue_slots[7].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal
connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr
connect issue_slots[7].in_uop.bits.is_br, issue_slots[10].out_uop.is_br
connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned
connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned
connect issue_slots[7].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state
connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std
connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta
connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load
connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd
connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw
connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn
connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel
connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel
connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel
connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type
connect issue_slots[7].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code
connect issue_slots[7].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type
connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst
connect issue_slots[7].in_uop.bits.inst, issue_slots[10].out_uop.inst
connect issue_slots[7].in_uop.bits.uopc, issue_slots[10].out_uop.uopc
node _issue_slots_7_clear_T = neq(_WIRE_10, UInt<1>(0h0))
connect issue_slots[7].clear, _issue_slots_7_clear_T
connect issue_slots[8].in_uop.valid, UInt<1>(0h0)
connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc
connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc
connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if
connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if
connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if
connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if
connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if
connect issue_slots[8].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single
connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val
connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en
connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype
connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype
connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype
connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val
connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3
connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2
connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1
connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst
connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1
connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit
connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique
connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc
connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq
connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq
connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo
connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei
connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence
connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed
connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size
connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd
connect issue_slots[8].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable
connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause
connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception
connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst
connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy
connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy
connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy
connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy
connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred
connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3
connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2
connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1
connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst
connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx
connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx
connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx
connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx
connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr
connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed
connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken
connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob
connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst
connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx
connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag
connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask
connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb
connect issue_slots[8].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal
connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr
connect issue_slots[8].in_uop.bits.is_br, issue_slots[9].out_uop.is_br
connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned
connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned
connect issue_slots[8].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state
connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std
connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta
connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load
connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd
connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw
connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn
connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel
connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel
connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel
connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type
connect issue_slots[8].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code
connect issue_slots[8].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type
connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc
connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc
connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst
connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst
connect issue_slots[8].in_uop.bits.uopc, issue_slots[9].out_uop.uopc
node _T_222 = eq(_WIRE_12, UInt<1>(0h1))
when _T_222 :
connect issue_slots[8].in_uop.valid, issue_slots[9].will_be_valid
connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc
connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc
connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if
connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if
connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if
connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if
connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if
connect issue_slots[8].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single
connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val
connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en
connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype
connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype
connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype
connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val
connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3
connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2
connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1
connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst
connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1
connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit
connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique
connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc
connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq
connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq
connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo
connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei
connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence
connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed
connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size
connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd
connect issue_slots[8].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable
connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause
connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception
connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst
connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy
connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy
connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy
connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy
connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred
connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3
connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2
connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1
connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst
connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx
connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx
connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx
connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx
connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr
connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed
connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken
connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob
connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst
connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx
connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag
connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask
connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb
connect issue_slots[8].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal
connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr
connect issue_slots[8].in_uop.bits.is_br, issue_slots[9].out_uop.is_br
connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned
connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned
connect issue_slots[8].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state
connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std
connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta
connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load
connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd
connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw
connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn
connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel
connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel
connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel
connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type
connect issue_slots[8].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code
connect issue_slots[8].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type
connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc
connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc
connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst
connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst
connect issue_slots[8].in_uop.bits.uopc, issue_slots[9].out_uop.uopc
node _T_223 = eq(_WIRE_13, UInt<2>(0h2))
when _T_223 :
connect issue_slots[8].in_uop.valid, issue_slots[10].will_be_valid
connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc
connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc
connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if
connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if
connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if
connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if
connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if
connect issue_slots[8].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single
connect issue_slots[8].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val
connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en
connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype
connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype
connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype
connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val
connect issue_slots[8].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3
connect issue_slots[8].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2
connect issue_slots[8].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1
connect issue_slots[8].in_uop.bits.ldst, issue_slots[10].out_uop.ldst
connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1
connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit
connect issue_slots[8].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique
connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc
connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq
connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq
connect issue_slots[8].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo
connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei
connect issue_slots[8].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence
connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed
connect issue_slots[8].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size
connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd
connect issue_slots[8].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable
connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause
connect issue_slots[8].in_uop.bits.exception, issue_slots[10].out_uop.exception
connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst
connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy
connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy
connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy
connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy
connect issue_slots[8].in_uop.bits.ppred, issue_slots[10].out_uop.ppred
connect issue_slots[8].in_uop.bits.prs3, issue_slots[10].out_uop.prs3
connect issue_slots[8].in_uop.bits.prs2, issue_slots[10].out_uop.prs2
connect issue_slots[8].in_uop.bits.prs1, issue_slots[10].out_uop.prs1
connect issue_slots[8].in_uop.bits.pdst, issue_slots[10].out_uop.pdst
connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx
connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx
connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx
connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx
connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr
connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed
connect issue_slots[8].in_uop.bits.taken, issue_slots[10].out_uop.taken
connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob
connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst
connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx
connect issue_slots[8].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag
connect issue_slots[8].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask
connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb
connect issue_slots[8].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal
connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr
connect issue_slots[8].in_uop.bits.is_br, issue_slots[10].out_uop.is_br
connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned
connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned
connect issue_slots[8].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state
connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std
connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta
connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load
connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd
connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw
connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn
connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel
connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel
connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel
connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type
connect issue_slots[8].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code
connect issue_slots[8].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type
connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc
connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc
connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst
connect issue_slots[8].in_uop.bits.inst, issue_slots[10].out_uop.inst
connect issue_slots[8].in_uop.bits.uopc, issue_slots[10].out_uop.uopc
node _T_224 = eq(_WIRE_14, UInt<3>(0h4))
when _T_224 :
connect issue_slots[8].in_uop.valid, issue_slots[11].will_be_valid
connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc
connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc
connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if
connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if
connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if
connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if
connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if
connect issue_slots[8].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single
connect issue_slots[8].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val
connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en
connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype
connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype
connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype
connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val
connect issue_slots[8].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3
connect issue_slots[8].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2
connect issue_slots[8].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1
connect issue_slots[8].in_uop.bits.ldst, issue_slots[11].out_uop.ldst
connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1
connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit
connect issue_slots[8].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique
connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc
connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq
connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq
connect issue_slots[8].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo
connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei
connect issue_slots[8].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence
connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed
connect issue_slots[8].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size
connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd
connect issue_slots[8].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable
connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause
connect issue_slots[8].in_uop.bits.exception, issue_slots[11].out_uop.exception
connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst
connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy
connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy
connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy
connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy
connect issue_slots[8].in_uop.bits.ppred, issue_slots[11].out_uop.ppred
connect issue_slots[8].in_uop.bits.prs3, issue_slots[11].out_uop.prs3
connect issue_slots[8].in_uop.bits.prs2, issue_slots[11].out_uop.prs2
connect issue_slots[8].in_uop.bits.prs1, issue_slots[11].out_uop.prs1
connect issue_slots[8].in_uop.bits.pdst, issue_slots[11].out_uop.pdst
connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx
connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx
connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx
connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx
connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr
connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed
connect issue_slots[8].in_uop.bits.taken, issue_slots[11].out_uop.taken
connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob
connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst
connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx
connect issue_slots[8].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag
connect issue_slots[8].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask
connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb
connect issue_slots[8].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal
connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr
connect issue_slots[8].in_uop.bits.is_br, issue_slots[11].out_uop.is_br
connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned
connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned
connect issue_slots[8].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state
connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std
connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta
connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load
connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd
connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw
connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn
connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel
connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel
connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel
connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type
connect issue_slots[8].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code
connect issue_slots[8].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type
connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc
connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc
connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst
connect issue_slots[8].in_uop.bits.inst, issue_slots[11].out_uop.inst
connect issue_slots[8].in_uop.bits.uopc, issue_slots[11].out_uop.uopc
node _issue_slots_8_clear_T = neq(_WIRE_11, UInt<1>(0h0))
connect issue_slots[8].clear, _issue_slots_8_clear_T
connect issue_slots[9].in_uop.valid, UInt<1>(0h0)
connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc
connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc
connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if
connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if
connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if
connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if
connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if
connect issue_slots[9].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single
connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val
connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en
connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype
connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype
connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype
connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val
connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3
connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2
connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1
connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst
connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1
connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit
connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique
connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc
connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq
connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq
connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo
connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei
connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence
connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed
connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size
connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd
connect issue_slots[9].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable
connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause
connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception
connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst
connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy
connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy
connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy
connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy
connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred
connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3
connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2
connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1
connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst
connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx
connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx
connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx
connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx
connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr
connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed
connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken
connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob
connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst
connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx
connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag
connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask
connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb
connect issue_slots[9].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal
connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr
connect issue_slots[9].in_uop.bits.is_br, issue_slots[10].out_uop.is_br
connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned
connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned
connect issue_slots[9].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state
connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std
connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta
connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load
connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd
connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw
connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn
connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel
connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel
connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel
connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type
connect issue_slots[9].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code
connect issue_slots[9].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type
connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc
connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc
connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst
connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst
connect issue_slots[9].in_uop.bits.uopc, issue_slots[10].out_uop.uopc
node _T_225 = eq(_WIRE_13, UInt<1>(0h1))
when _T_225 :
connect issue_slots[9].in_uop.valid, issue_slots[10].will_be_valid
connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc
connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc
connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if
connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if
connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if
connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if
connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if
connect issue_slots[9].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single
connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val
connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en
connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype
connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype
connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype
connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val
connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3
connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2
connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1
connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst
connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1
connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit
connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique
connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc
connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq
connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq
connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo
connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei
connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence
connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed
connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size
connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd
connect issue_slots[9].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable
connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause
connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception
connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst
connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy
connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy
connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy
connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy
connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred
connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3
connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2
connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1
connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst
connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx
connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx
connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx
connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx
connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr
connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed
connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken
connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob
connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst
connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx
connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag
connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask
connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb
connect issue_slots[9].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal
connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr
connect issue_slots[9].in_uop.bits.is_br, issue_slots[10].out_uop.is_br
connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned
connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned
connect issue_slots[9].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state
connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std
connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta
connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load
connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd
connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw
connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn
connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel
connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel
connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel
connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type
connect issue_slots[9].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code
connect issue_slots[9].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type
connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc
connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc
connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst
connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst
connect issue_slots[9].in_uop.bits.uopc, issue_slots[10].out_uop.uopc
node _T_226 = eq(_WIRE_14, UInt<2>(0h2))
when _T_226 :
connect issue_slots[9].in_uop.valid, issue_slots[11].will_be_valid
connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc
connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc
connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if
connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if
connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if
connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if
connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if
connect issue_slots[9].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single
connect issue_slots[9].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val
connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en
connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype
connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype
connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype
connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val
connect issue_slots[9].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3
connect issue_slots[9].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2
connect issue_slots[9].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1
connect issue_slots[9].in_uop.bits.ldst, issue_slots[11].out_uop.ldst
connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1
connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit
connect issue_slots[9].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique
connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc
connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq
connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq
connect issue_slots[9].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo
connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei
connect issue_slots[9].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence
connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed
connect issue_slots[9].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size
connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd
connect issue_slots[9].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable
connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause
connect issue_slots[9].in_uop.bits.exception, issue_slots[11].out_uop.exception
connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst
connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy
connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy
connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy
connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy
connect issue_slots[9].in_uop.bits.ppred, issue_slots[11].out_uop.ppred
connect issue_slots[9].in_uop.bits.prs3, issue_slots[11].out_uop.prs3
connect issue_slots[9].in_uop.bits.prs2, issue_slots[11].out_uop.prs2
connect issue_slots[9].in_uop.bits.prs1, issue_slots[11].out_uop.prs1
connect issue_slots[9].in_uop.bits.pdst, issue_slots[11].out_uop.pdst
connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx
connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx
connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx
connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx
connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr
connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed
connect issue_slots[9].in_uop.bits.taken, issue_slots[11].out_uop.taken
connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob
connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst
connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx
connect issue_slots[9].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag
connect issue_slots[9].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask
connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb
connect issue_slots[9].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal
connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr
connect issue_slots[9].in_uop.bits.is_br, issue_slots[11].out_uop.is_br
connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned
connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned
connect issue_slots[9].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state
connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std
connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta
connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load
connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd
connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw
connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn
connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel
connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel
connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel
connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type
connect issue_slots[9].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code
connect issue_slots[9].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type
connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc
connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc
connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst
connect issue_slots[9].in_uop.bits.inst, issue_slots[11].out_uop.inst
connect issue_slots[9].in_uop.bits.uopc, issue_slots[11].out_uop.uopc
node _T_227 = eq(_WIRE_15, UInt<3>(0h4))
when _T_227 :
connect issue_slots[9].in_uop.valid, issue_slots[12].will_be_valid
connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc
connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc
connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if
connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if
connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if
connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if
connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if
connect issue_slots[9].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single
connect issue_slots[9].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val
connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en
connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype
connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype
connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype
connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val
connect issue_slots[9].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3
connect issue_slots[9].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2
connect issue_slots[9].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1
connect issue_slots[9].in_uop.bits.ldst, issue_slots[12].out_uop.ldst
connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1
connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit
connect issue_slots[9].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique
connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc
connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq
connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq
connect issue_slots[9].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo
connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei
connect issue_slots[9].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence
connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed
connect issue_slots[9].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size
connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd
connect issue_slots[9].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable
connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause
connect issue_slots[9].in_uop.bits.exception, issue_slots[12].out_uop.exception
connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst
connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy
connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy
connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy
connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy
connect issue_slots[9].in_uop.bits.ppred, issue_slots[12].out_uop.ppred
connect issue_slots[9].in_uop.bits.prs3, issue_slots[12].out_uop.prs3
connect issue_slots[9].in_uop.bits.prs2, issue_slots[12].out_uop.prs2
connect issue_slots[9].in_uop.bits.prs1, issue_slots[12].out_uop.prs1
connect issue_slots[9].in_uop.bits.pdst, issue_slots[12].out_uop.pdst
connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx
connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx
connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx
connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx
connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr
connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed
connect issue_slots[9].in_uop.bits.taken, issue_slots[12].out_uop.taken
connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob
connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst
connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx
connect issue_slots[9].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag
connect issue_slots[9].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask
connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb
connect issue_slots[9].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal
connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr
connect issue_slots[9].in_uop.bits.is_br, issue_slots[12].out_uop.is_br
connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned
connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned
connect issue_slots[9].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state
connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std
connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta
connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load
connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd
connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw
connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn
connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel
connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel
connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel
connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type
connect issue_slots[9].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code
connect issue_slots[9].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type
connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc
connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc
connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst
connect issue_slots[9].in_uop.bits.inst, issue_slots[12].out_uop.inst
connect issue_slots[9].in_uop.bits.uopc, issue_slots[12].out_uop.uopc
node _issue_slots_9_clear_T = neq(_WIRE_12, UInt<1>(0h0))
connect issue_slots[9].clear, _issue_slots_9_clear_T
connect issue_slots[10].in_uop.valid, UInt<1>(0h0)
connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc
connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc
connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if
connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if
connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if
connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if
connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if
connect issue_slots[10].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single
connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val
connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en
connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype
connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype
connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype
connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val
connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3
connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2
connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1
connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst
connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1
connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit
connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique
connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc
connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq
connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq
connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo
connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei
connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence
connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed
connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size
connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd
connect issue_slots[10].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable
connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause
connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception
connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst
connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy
connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy
connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy
connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy
connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred
connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3
connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2
connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1
connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst
connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx
connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx
connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx
connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx
connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr
connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed
connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken
connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob
connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst
connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx
connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag
connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask
connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb
connect issue_slots[10].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal
connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr
connect issue_slots[10].in_uop.bits.is_br, issue_slots[11].out_uop.is_br
connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned
connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned
connect issue_slots[10].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state
connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std
connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta
connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load
connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd
connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw
connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn
connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel
connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel
connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel
connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type
connect issue_slots[10].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code
connect issue_slots[10].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type
connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc
connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc
connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst
connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst
connect issue_slots[10].in_uop.bits.uopc, issue_slots[11].out_uop.uopc
node _T_228 = eq(_WIRE_14, UInt<1>(0h1))
when _T_228 :
connect issue_slots[10].in_uop.valid, issue_slots[11].will_be_valid
connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc
connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc
connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if
connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if
connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if
connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if
connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if
connect issue_slots[10].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single
connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val
connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en
connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype
connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype
connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype
connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val
connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3
connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2
connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1
connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst
connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1
connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit
connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique
connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc
connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq
connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq
connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo
connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei
connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence
connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed
connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size
connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd
connect issue_slots[10].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable
connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause
connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception
connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst
connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy
connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy
connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy
connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy
connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred
connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3
connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2
connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1
connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst
connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx
connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx
connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx
connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx
connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr
connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed
connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken
connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob
connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst
connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx
connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag
connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask
connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb
connect issue_slots[10].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal
connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr
connect issue_slots[10].in_uop.bits.is_br, issue_slots[11].out_uop.is_br
connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned
connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned
connect issue_slots[10].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state
connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std
connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta
connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load
connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd
connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw
connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn
connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel
connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel
connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel
connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type
connect issue_slots[10].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code
connect issue_slots[10].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type
connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc
connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc
connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst
connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst
connect issue_slots[10].in_uop.bits.uopc, issue_slots[11].out_uop.uopc
node _T_229 = eq(_WIRE_15, UInt<2>(0h2))
when _T_229 :
connect issue_slots[10].in_uop.valid, issue_slots[12].will_be_valid
connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc
connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc
connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if
connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if
connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if
connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if
connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if
connect issue_slots[10].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single
connect issue_slots[10].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val
connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en
connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype
connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype
connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype
connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val
connect issue_slots[10].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3
connect issue_slots[10].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2
connect issue_slots[10].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1
connect issue_slots[10].in_uop.bits.ldst, issue_slots[12].out_uop.ldst
connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1
connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit
connect issue_slots[10].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique
connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc
connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq
connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq
connect issue_slots[10].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo
connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei
connect issue_slots[10].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence
connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed
connect issue_slots[10].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size
connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd
connect issue_slots[10].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable
connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause
connect issue_slots[10].in_uop.bits.exception, issue_slots[12].out_uop.exception
connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst
connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy
connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy
connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy
connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy
connect issue_slots[10].in_uop.bits.ppred, issue_slots[12].out_uop.ppred
connect issue_slots[10].in_uop.bits.prs3, issue_slots[12].out_uop.prs3
connect issue_slots[10].in_uop.bits.prs2, issue_slots[12].out_uop.prs2
connect issue_slots[10].in_uop.bits.prs1, issue_slots[12].out_uop.prs1
connect issue_slots[10].in_uop.bits.pdst, issue_slots[12].out_uop.pdst
connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx
connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx
connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx
connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx
connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr
connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed
connect issue_slots[10].in_uop.bits.taken, issue_slots[12].out_uop.taken
connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob
connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst
connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx
connect issue_slots[10].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag
connect issue_slots[10].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask
connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb
connect issue_slots[10].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal
connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr
connect issue_slots[10].in_uop.bits.is_br, issue_slots[12].out_uop.is_br
connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned
connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned
connect issue_slots[10].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state
connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std
connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta
connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load
connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd
connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw
connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn
connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel
connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel
connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel
connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type
connect issue_slots[10].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code
connect issue_slots[10].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type
connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc
connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc
connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst
connect issue_slots[10].in_uop.bits.inst, issue_slots[12].out_uop.inst
connect issue_slots[10].in_uop.bits.uopc, issue_slots[12].out_uop.uopc
node _T_230 = eq(_WIRE_16, UInt<3>(0h4))
when _T_230 :
connect issue_slots[10].in_uop.valid, issue_slots[13].will_be_valid
connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc
connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc
connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if
connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if
connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if
connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if
connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if
connect issue_slots[10].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single
connect issue_slots[10].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val
connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en
connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype
connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype
connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype
connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val
connect issue_slots[10].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3
connect issue_slots[10].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2
connect issue_slots[10].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1
connect issue_slots[10].in_uop.bits.ldst, issue_slots[13].out_uop.ldst
connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1
connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit
connect issue_slots[10].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique
connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc
connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq
connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq
connect issue_slots[10].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo
connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei
connect issue_slots[10].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence
connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed
connect issue_slots[10].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size
connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd
connect issue_slots[10].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable
connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause
connect issue_slots[10].in_uop.bits.exception, issue_slots[13].out_uop.exception
connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst
connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy
connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy
connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy
connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy
connect issue_slots[10].in_uop.bits.ppred, issue_slots[13].out_uop.ppred
connect issue_slots[10].in_uop.bits.prs3, issue_slots[13].out_uop.prs3
connect issue_slots[10].in_uop.bits.prs2, issue_slots[13].out_uop.prs2
connect issue_slots[10].in_uop.bits.prs1, issue_slots[13].out_uop.prs1
connect issue_slots[10].in_uop.bits.pdst, issue_slots[13].out_uop.pdst
connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx
connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx
connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx
connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx
connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr
connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed
connect issue_slots[10].in_uop.bits.taken, issue_slots[13].out_uop.taken
connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob
connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst
connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx
connect issue_slots[10].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag
connect issue_slots[10].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask
connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb
connect issue_slots[10].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal
connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr
connect issue_slots[10].in_uop.bits.is_br, issue_slots[13].out_uop.is_br
connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned
connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned
connect issue_slots[10].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state
connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std
connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta
connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load
connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd
connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw
connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn
connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel
connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel
connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel
connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type
connect issue_slots[10].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code
connect issue_slots[10].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type
connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc
connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc
connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst
connect issue_slots[10].in_uop.bits.inst, issue_slots[13].out_uop.inst
connect issue_slots[10].in_uop.bits.uopc, issue_slots[13].out_uop.uopc
node _issue_slots_10_clear_T = neq(_WIRE_13, UInt<1>(0h0))
connect issue_slots[10].clear, _issue_slots_10_clear_T
connect issue_slots[11].in_uop.valid, UInt<1>(0h0)
connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc
connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc
connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if
connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if
connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if
connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if
connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if
connect issue_slots[11].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single
connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val
connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en
connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype
connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype
connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype
connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val
connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3
connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2
connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1
connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst
connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1
connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit
connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique
connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc
connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq
connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq
connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo
connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei
connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence
connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed
connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size
connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd
connect issue_slots[11].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable
connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause
connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception
connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst
connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy
connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy
connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy
connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy
connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred
connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3
connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2
connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1
connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst
connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx
connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx
connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx
connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx
connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr
connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed
connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken
connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob
connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst
connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx
connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag
connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask
connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb
connect issue_slots[11].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal
connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr
connect issue_slots[11].in_uop.bits.is_br, issue_slots[12].out_uop.is_br
connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned
connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned
connect issue_slots[11].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state
connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std
connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta
connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load
connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd
connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw
connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn
connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel
connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel
connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel
connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type
connect issue_slots[11].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code
connect issue_slots[11].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type
connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc
connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc
connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst
connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst
connect issue_slots[11].in_uop.bits.uopc, issue_slots[12].out_uop.uopc
node _T_231 = eq(_WIRE_15, UInt<1>(0h1))
when _T_231 :
connect issue_slots[11].in_uop.valid, issue_slots[12].will_be_valid
connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc
connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc
connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if
connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if
connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if
connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if
connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if
connect issue_slots[11].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single
connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val
connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en
connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype
connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype
connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype
connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val
connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3
connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2
connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1
connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst
connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1
connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit
connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique
connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc
connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq
connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq
connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo
connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei
connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence
connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed
connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size
connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd
connect issue_slots[11].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable
connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause
connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception
connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst
connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy
connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy
connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy
connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy
connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred
connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3
connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2
connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1
connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst
connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx
connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx
connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx
connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx
connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr
connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed
connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken
connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob
connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst
connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx
connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag
connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask
connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb
connect issue_slots[11].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal
connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr
connect issue_slots[11].in_uop.bits.is_br, issue_slots[12].out_uop.is_br
connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned
connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned
connect issue_slots[11].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state
connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std
connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta
connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load
connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd
connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw
connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn
connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel
connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel
connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel
connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type
connect issue_slots[11].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code
connect issue_slots[11].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type
connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc
connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc
connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst
connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst
connect issue_slots[11].in_uop.bits.uopc, issue_slots[12].out_uop.uopc
node _T_232 = eq(_WIRE_16, UInt<2>(0h2))
when _T_232 :
connect issue_slots[11].in_uop.valid, issue_slots[13].will_be_valid
connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc
connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc
connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if
connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if
connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if
connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if
connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if
connect issue_slots[11].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single
connect issue_slots[11].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val
connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en
connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype
connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype
connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype
connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val
connect issue_slots[11].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3
connect issue_slots[11].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2
connect issue_slots[11].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1
connect issue_slots[11].in_uop.bits.ldst, issue_slots[13].out_uop.ldst
connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1
connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit
connect issue_slots[11].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique
connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc
connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq
connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq
connect issue_slots[11].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo
connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei
connect issue_slots[11].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence
connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed
connect issue_slots[11].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size
connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd
connect issue_slots[11].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable
connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause
connect issue_slots[11].in_uop.bits.exception, issue_slots[13].out_uop.exception
connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst
connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy
connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy
connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy
connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy
connect issue_slots[11].in_uop.bits.ppred, issue_slots[13].out_uop.ppred
connect issue_slots[11].in_uop.bits.prs3, issue_slots[13].out_uop.prs3
connect issue_slots[11].in_uop.bits.prs2, issue_slots[13].out_uop.prs2
connect issue_slots[11].in_uop.bits.prs1, issue_slots[13].out_uop.prs1
connect issue_slots[11].in_uop.bits.pdst, issue_slots[13].out_uop.pdst
connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx
connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx
connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx
connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx
connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr
connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed
connect issue_slots[11].in_uop.bits.taken, issue_slots[13].out_uop.taken
connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob
connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst
connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx
connect issue_slots[11].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag
connect issue_slots[11].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask
connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb
connect issue_slots[11].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal
connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr
connect issue_slots[11].in_uop.bits.is_br, issue_slots[13].out_uop.is_br
connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned
connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned
connect issue_slots[11].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state
connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std
connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta
connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load
connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd
connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw
connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn
connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel
connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel
connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel
connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type
connect issue_slots[11].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code
connect issue_slots[11].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type
connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc
connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc
connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst
connect issue_slots[11].in_uop.bits.inst, issue_slots[13].out_uop.inst
connect issue_slots[11].in_uop.bits.uopc, issue_slots[13].out_uop.uopc
node _T_233 = eq(_WIRE_17, UInt<3>(0h4))
when _T_233 :
connect issue_slots[11].in_uop.valid, issue_slots[14].will_be_valid
connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc
connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc
connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if
connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if
connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if
connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if
connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if
connect issue_slots[11].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single
connect issue_slots[11].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val
connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en
connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype
connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype
connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype
connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val
connect issue_slots[11].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3
connect issue_slots[11].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2
connect issue_slots[11].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1
connect issue_slots[11].in_uop.bits.ldst, issue_slots[14].out_uop.ldst
connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1
connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit
connect issue_slots[11].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique
connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc
connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq
connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq
connect issue_slots[11].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo
connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei
connect issue_slots[11].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence
connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed
connect issue_slots[11].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size
connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd
connect issue_slots[11].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable
connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause
connect issue_slots[11].in_uop.bits.exception, issue_slots[14].out_uop.exception
connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst
connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy
connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy
connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy
connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy
connect issue_slots[11].in_uop.bits.ppred, issue_slots[14].out_uop.ppred
connect issue_slots[11].in_uop.bits.prs3, issue_slots[14].out_uop.prs3
connect issue_slots[11].in_uop.bits.prs2, issue_slots[14].out_uop.prs2
connect issue_slots[11].in_uop.bits.prs1, issue_slots[14].out_uop.prs1
connect issue_slots[11].in_uop.bits.pdst, issue_slots[14].out_uop.pdst
connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx
connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx
connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx
connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx
connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr
connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed
connect issue_slots[11].in_uop.bits.taken, issue_slots[14].out_uop.taken
connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob
connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst
connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx
connect issue_slots[11].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag
connect issue_slots[11].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask
connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb
connect issue_slots[11].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal
connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr
connect issue_slots[11].in_uop.bits.is_br, issue_slots[14].out_uop.is_br
connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned
connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned
connect issue_slots[11].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state
connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std
connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta
connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load
connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd
connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw
connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn
connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel
connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel
connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel
connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type
connect issue_slots[11].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code
connect issue_slots[11].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type
connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc
connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc
connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst
connect issue_slots[11].in_uop.bits.inst, issue_slots[14].out_uop.inst
connect issue_slots[11].in_uop.bits.uopc, issue_slots[14].out_uop.uopc
node _issue_slots_11_clear_T = neq(_WIRE_14, UInt<1>(0h0))
connect issue_slots[11].clear, _issue_slots_11_clear_T
connect issue_slots[12].in_uop.valid, UInt<1>(0h0)
connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc
connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc
connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if
connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if
connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if
connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if
connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if
connect issue_slots[12].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single
connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val
connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en
connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype
connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype
connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype
connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val
connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3
connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2
connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1
connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst
connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1
connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit
connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique
connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc
connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq
connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq
connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo
connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei
connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence
connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed
connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size
connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd
connect issue_slots[12].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable
connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause
connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception
connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst
connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy
connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy
connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy
connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy
connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred
connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3
connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2
connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1
connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst
connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx
connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx
connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx
connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx
connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr
connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed
connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken
connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob
connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst
connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx
connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag
connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask
connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb
connect issue_slots[12].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal
connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr
connect issue_slots[12].in_uop.bits.is_br, issue_slots[13].out_uop.is_br
connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned
connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned
connect issue_slots[12].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state
connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std
connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta
connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load
connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd
connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw
connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn
connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel
connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel
connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel
connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type
connect issue_slots[12].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code
connect issue_slots[12].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type
connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc
connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc
connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst
connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst
connect issue_slots[12].in_uop.bits.uopc, issue_slots[13].out_uop.uopc
node _T_234 = eq(_WIRE_16, UInt<1>(0h1))
when _T_234 :
connect issue_slots[12].in_uop.valid, issue_slots[13].will_be_valid
connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc
connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc
connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if
connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if
connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if
connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if
connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if
connect issue_slots[12].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single
connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val
connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en
connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype
connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype
connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype
connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val
connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3
connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2
connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1
connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst
connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1
connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit
connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique
connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc
connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq
connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq
connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo
connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei
connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence
connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed
connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size
connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd
connect issue_slots[12].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable
connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause
connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception
connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst
connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy
connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy
connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy
connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy
connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred
connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3
connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2
connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1
connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst
connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx
connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx
connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx
connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx
connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr
connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed
connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken
connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob
connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst
connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx
connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag
connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask
connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb
connect issue_slots[12].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal
connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr
connect issue_slots[12].in_uop.bits.is_br, issue_slots[13].out_uop.is_br
connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned
connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned
connect issue_slots[12].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state
connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std
connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta
connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load
connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd
connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw
connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn
connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel
connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel
connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel
connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type
connect issue_slots[12].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code
connect issue_slots[12].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type
connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc
connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc
connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst
connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst
connect issue_slots[12].in_uop.bits.uopc, issue_slots[13].out_uop.uopc
node _T_235 = eq(_WIRE_17, UInt<2>(0h2))
when _T_235 :
connect issue_slots[12].in_uop.valid, issue_slots[14].will_be_valid
connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc
connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc
connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if
connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if
connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if
connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if
connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if
connect issue_slots[12].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single
connect issue_slots[12].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val
connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en
connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype
connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype
connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype
connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val
connect issue_slots[12].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3
connect issue_slots[12].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2
connect issue_slots[12].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1
connect issue_slots[12].in_uop.bits.ldst, issue_slots[14].out_uop.ldst
connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1
connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit
connect issue_slots[12].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique
connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc
connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq
connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq
connect issue_slots[12].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo
connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei
connect issue_slots[12].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence
connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed
connect issue_slots[12].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size
connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd
connect issue_slots[12].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable
connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause
connect issue_slots[12].in_uop.bits.exception, issue_slots[14].out_uop.exception
connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst
connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy
connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy
connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy
connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy
connect issue_slots[12].in_uop.bits.ppred, issue_slots[14].out_uop.ppred
connect issue_slots[12].in_uop.bits.prs3, issue_slots[14].out_uop.prs3
connect issue_slots[12].in_uop.bits.prs2, issue_slots[14].out_uop.prs2
connect issue_slots[12].in_uop.bits.prs1, issue_slots[14].out_uop.prs1
connect issue_slots[12].in_uop.bits.pdst, issue_slots[14].out_uop.pdst
connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx
connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx
connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx
connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx
connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr
connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed
connect issue_slots[12].in_uop.bits.taken, issue_slots[14].out_uop.taken
connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob
connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst
connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx
connect issue_slots[12].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag
connect issue_slots[12].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask
connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb
connect issue_slots[12].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal
connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr
connect issue_slots[12].in_uop.bits.is_br, issue_slots[14].out_uop.is_br
connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned
connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned
connect issue_slots[12].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state
connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std
connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta
connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load
connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd
connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw
connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn
connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel
connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel
connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel
connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type
connect issue_slots[12].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code
connect issue_slots[12].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type
connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc
connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc
connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst
connect issue_slots[12].in_uop.bits.inst, issue_slots[14].out_uop.inst
connect issue_slots[12].in_uop.bits.uopc, issue_slots[14].out_uop.uopc
node _T_236 = eq(_WIRE_18, UInt<3>(0h4))
when _T_236 :
connect issue_slots[12].in_uop.valid, issue_slots[15].will_be_valid
connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc
connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc
connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if
connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if
connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if
connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if
connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if
connect issue_slots[12].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single
connect issue_slots[12].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val
connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en
connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype
connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype
connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype
connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val
connect issue_slots[12].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3
connect issue_slots[12].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2
connect issue_slots[12].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1
connect issue_slots[12].in_uop.bits.ldst, issue_slots[15].out_uop.ldst
connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1
connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit
connect issue_slots[12].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique
connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc
connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq
connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq
connect issue_slots[12].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo
connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei
connect issue_slots[12].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence
connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed
connect issue_slots[12].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size
connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd
connect issue_slots[12].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable
connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause
connect issue_slots[12].in_uop.bits.exception, issue_slots[15].out_uop.exception
connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst
connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy
connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy
connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy
connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy
connect issue_slots[12].in_uop.bits.ppred, issue_slots[15].out_uop.ppred
connect issue_slots[12].in_uop.bits.prs3, issue_slots[15].out_uop.prs3
connect issue_slots[12].in_uop.bits.prs2, issue_slots[15].out_uop.prs2
connect issue_slots[12].in_uop.bits.prs1, issue_slots[15].out_uop.prs1
connect issue_slots[12].in_uop.bits.pdst, issue_slots[15].out_uop.pdst
connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx
connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx
connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx
connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx
connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr
connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed
connect issue_slots[12].in_uop.bits.taken, issue_slots[15].out_uop.taken
connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob
connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst
connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx
connect issue_slots[12].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag
connect issue_slots[12].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask
connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb
connect issue_slots[12].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal
connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr
connect issue_slots[12].in_uop.bits.is_br, issue_slots[15].out_uop.is_br
connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned
connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned
connect issue_slots[12].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state
connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std
connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta
connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load
connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd
connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw
connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn
connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel
connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel
connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel
connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type
connect issue_slots[12].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code
connect issue_slots[12].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type
connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc
connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc
connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst
connect issue_slots[12].in_uop.bits.inst, issue_slots[15].out_uop.inst
connect issue_slots[12].in_uop.bits.uopc, issue_slots[15].out_uop.uopc
node _issue_slots_12_clear_T = neq(_WIRE_15, UInt<1>(0h0))
connect issue_slots[12].clear, _issue_slots_12_clear_T
connect issue_slots[13].in_uop.valid, UInt<1>(0h0)
connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc
connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc
connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if
connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if
connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if
connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if
connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if
connect issue_slots[13].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single
connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val
connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en
connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype
connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype
connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype
connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val
connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3
connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2
connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1
connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst
connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1
connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit
connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique
connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc
connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq
connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq
connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo
connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei
connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence
connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed
connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size
connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd
connect issue_slots[13].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable
connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause
connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception
connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst
connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy
connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy
connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy
connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy
connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred
connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3
connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2
connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1
connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst
connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx
connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx
connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx
connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx
connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr
connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed
connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken
connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob
connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst
connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx
connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag
connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask
connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb
connect issue_slots[13].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal
connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr
connect issue_slots[13].in_uop.bits.is_br, issue_slots[14].out_uop.is_br
connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned
connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned
connect issue_slots[13].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state
connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std
connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta
connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load
connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd
connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw
connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn
connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel
connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel
connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel
connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type
connect issue_slots[13].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code
connect issue_slots[13].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type
connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc
connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc
connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst
connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst
connect issue_slots[13].in_uop.bits.uopc, issue_slots[14].out_uop.uopc
node _T_237 = eq(_WIRE_17, UInt<1>(0h1))
when _T_237 :
connect issue_slots[13].in_uop.valid, issue_slots[14].will_be_valid
connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc
connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc
connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if
connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if
connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if
connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if
connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if
connect issue_slots[13].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single
connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val
connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en
connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype
connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype
connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype
connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val
connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3
connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2
connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1
connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst
connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1
connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit
connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique
connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc
connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq
connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq
connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo
connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei
connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence
connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed
connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size
connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd
connect issue_slots[13].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable
connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause
connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception
connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst
connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy
connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy
connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy
connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy
connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred
connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3
connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2
connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1
connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst
connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx
connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx
connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx
connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx
connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr
connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed
connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken
connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob
connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst
connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx
connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag
connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask
connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb
connect issue_slots[13].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal
connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr
connect issue_slots[13].in_uop.bits.is_br, issue_slots[14].out_uop.is_br
connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned
connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned
connect issue_slots[13].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state
connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std
connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta
connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load
connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd
connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw
connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn
connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel
connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel
connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel
connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type
connect issue_slots[13].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code
connect issue_slots[13].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type
connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc
connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc
connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst
connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst
connect issue_slots[13].in_uop.bits.uopc, issue_slots[14].out_uop.uopc
node _T_238 = eq(_WIRE_18, UInt<2>(0h2))
when _T_238 :
connect issue_slots[13].in_uop.valid, issue_slots[15].will_be_valid
connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc
connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc
connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if
connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if
connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if
connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if
connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if
connect issue_slots[13].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single
connect issue_slots[13].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val
connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en
connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype
connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype
connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype
connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val
connect issue_slots[13].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3
connect issue_slots[13].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2
connect issue_slots[13].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1
connect issue_slots[13].in_uop.bits.ldst, issue_slots[15].out_uop.ldst
connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1
connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit
connect issue_slots[13].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique
connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc
connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq
connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq
connect issue_slots[13].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo
connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei
connect issue_slots[13].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence
connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed
connect issue_slots[13].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size
connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd
connect issue_slots[13].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable
connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause
connect issue_slots[13].in_uop.bits.exception, issue_slots[15].out_uop.exception
connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst
connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy
connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy
connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy
connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy
connect issue_slots[13].in_uop.bits.ppred, issue_slots[15].out_uop.ppred
connect issue_slots[13].in_uop.bits.prs3, issue_slots[15].out_uop.prs3
connect issue_slots[13].in_uop.bits.prs2, issue_slots[15].out_uop.prs2
connect issue_slots[13].in_uop.bits.prs1, issue_slots[15].out_uop.prs1
connect issue_slots[13].in_uop.bits.pdst, issue_slots[15].out_uop.pdst
connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx
connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx
connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx
connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx
connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr
connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed
connect issue_slots[13].in_uop.bits.taken, issue_slots[15].out_uop.taken
connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob
connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst
connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx
connect issue_slots[13].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag
connect issue_slots[13].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask
connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb
connect issue_slots[13].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal
connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr
connect issue_slots[13].in_uop.bits.is_br, issue_slots[15].out_uop.is_br
connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned
connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned
connect issue_slots[13].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state
connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std
connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta
connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load
connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd
connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw
connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn
connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel
connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel
connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel
connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type
connect issue_slots[13].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code
connect issue_slots[13].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type
connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc
connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc
connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst
connect issue_slots[13].in_uop.bits.inst, issue_slots[15].out_uop.inst
connect issue_slots[13].in_uop.bits.uopc, issue_slots[15].out_uop.uopc
node _T_239 = eq(_WIRE_19, UInt<3>(0h4))
when _T_239 :
connect issue_slots[13].in_uop.valid, issue_slots[16].will_be_valid
connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc
connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc
connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if
connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if
connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if
connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if
connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if
connect issue_slots[13].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single
connect issue_slots[13].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val
connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en
connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype
connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype
connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype
connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val
connect issue_slots[13].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3
connect issue_slots[13].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2
connect issue_slots[13].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1
connect issue_slots[13].in_uop.bits.ldst, issue_slots[16].out_uop.ldst
connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1
connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit
connect issue_slots[13].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique
connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc
connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq
connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq
connect issue_slots[13].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo
connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei
connect issue_slots[13].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence
connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed
connect issue_slots[13].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size
connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd
connect issue_slots[13].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable
connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause
connect issue_slots[13].in_uop.bits.exception, issue_slots[16].out_uop.exception
connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst
connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy
connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy
connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy
connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy
connect issue_slots[13].in_uop.bits.ppred, issue_slots[16].out_uop.ppred
connect issue_slots[13].in_uop.bits.prs3, issue_slots[16].out_uop.prs3
connect issue_slots[13].in_uop.bits.prs2, issue_slots[16].out_uop.prs2
connect issue_slots[13].in_uop.bits.prs1, issue_slots[16].out_uop.prs1
connect issue_slots[13].in_uop.bits.pdst, issue_slots[16].out_uop.pdst
connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx
connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx
connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx
connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx
connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr
connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed
connect issue_slots[13].in_uop.bits.taken, issue_slots[16].out_uop.taken
connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob
connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst
connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx
connect issue_slots[13].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag
connect issue_slots[13].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask
connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb
connect issue_slots[13].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal
connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr
connect issue_slots[13].in_uop.bits.is_br, issue_slots[16].out_uop.is_br
connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned
connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned
connect issue_slots[13].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state
connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std
connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta
connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load
connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd
connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw
connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn
connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel
connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel
connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel
connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type
connect issue_slots[13].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code
connect issue_slots[13].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type
connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc
connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc
connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst
connect issue_slots[13].in_uop.bits.inst, issue_slots[16].out_uop.inst
connect issue_slots[13].in_uop.bits.uopc, issue_slots[16].out_uop.uopc
node _issue_slots_13_clear_T = neq(_WIRE_16, UInt<1>(0h0))
connect issue_slots[13].clear, _issue_slots_13_clear_T
connect issue_slots[14].in_uop.valid, UInt<1>(0h0)
connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc
connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc
connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if
connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if
connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if
connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if
connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if
connect issue_slots[14].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single
connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val
connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en
connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype
connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype
connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype
connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val
connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3
connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2
connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1
connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst
connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1
connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit
connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique
connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc
connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq
connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq
connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo
connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei
connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence
connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed
connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size
connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd
connect issue_slots[14].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable
connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause
connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception
connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst
connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy
connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy
connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy
connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy
connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred
connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3
connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2
connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1
connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst
connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx
connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx
connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx
connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx
connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr
connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed
connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken
connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob
connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst
connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx
connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag
connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask
connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb
connect issue_slots[14].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal
connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr
connect issue_slots[14].in_uop.bits.is_br, issue_slots[15].out_uop.is_br
connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned
connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned
connect issue_slots[14].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state
connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std
connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta
connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load
connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd
connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw
connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn
connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel
connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel
connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel
connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type
connect issue_slots[14].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code
connect issue_slots[14].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type
connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc
connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc
connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst
connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst
connect issue_slots[14].in_uop.bits.uopc, issue_slots[15].out_uop.uopc
node _T_240 = eq(_WIRE_18, UInt<1>(0h1))
when _T_240 :
connect issue_slots[14].in_uop.valid, issue_slots[15].will_be_valid
connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc
connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc
connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if
connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if
connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if
connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if
connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if
connect issue_slots[14].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single
connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val
connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en
connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype
connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype
connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype
connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val
connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3
connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2
connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1
connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst
connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1
connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit
connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique
connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc
connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq
connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq
connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo
connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei
connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence
connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed
connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size
connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd
connect issue_slots[14].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable
connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause
connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception
connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst
connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy
connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy
connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy
connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy
connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred
connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3
connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2
connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1
connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst
connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx
connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx
connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx
connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx
connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr
connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed
connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken
connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob
connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst
connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx
connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag
connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask
connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb
connect issue_slots[14].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal
connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr
connect issue_slots[14].in_uop.bits.is_br, issue_slots[15].out_uop.is_br
connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned
connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned
connect issue_slots[14].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state
connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std
connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta
connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load
connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd
connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw
connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn
connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel
connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel
connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel
connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type
connect issue_slots[14].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code
connect issue_slots[14].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type
connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc
connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc
connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst
connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst
connect issue_slots[14].in_uop.bits.uopc, issue_slots[15].out_uop.uopc
node _T_241 = eq(_WIRE_19, UInt<2>(0h2))
when _T_241 :
connect issue_slots[14].in_uop.valid, issue_slots[16].will_be_valid
connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc
connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc
connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if
connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if
connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if
connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if
connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if
connect issue_slots[14].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single
connect issue_slots[14].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val
connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en
connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype
connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype
connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype
connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val
connect issue_slots[14].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3
connect issue_slots[14].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2
connect issue_slots[14].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1
connect issue_slots[14].in_uop.bits.ldst, issue_slots[16].out_uop.ldst
connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1
connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit
connect issue_slots[14].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique
connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc
connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq
connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq
connect issue_slots[14].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo
connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei
connect issue_slots[14].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence
connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed
connect issue_slots[14].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size
connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd
connect issue_slots[14].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable
connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause
connect issue_slots[14].in_uop.bits.exception, issue_slots[16].out_uop.exception
connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst
connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy
connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy
connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy
connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy
connect issue_slots[14].in_uop.bits.ppred, issue_slots[16].out_uop.ppred
connect issue_slots[14].in_uop.bits.prs3, issue_slots[16].out_uop.prs3
connect issue_slots[14].in_uop.bits.prs2, issue_slots[16].out_uop.prs2
connect issue_slots[14].in_uop.bits.prs1, issue_slots[16].out_uop.prs1
connect issue_slots[14].in_uop.bits.pdst, issue_slots[16].out_uop.pdst
connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx
connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx
connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx
connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx
connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr
connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed
connect issue_slots[14].in_uop.bits.taken, issue_slots[16].out_uop.taken
connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob
connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst
connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx
connect issue_slots[14].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag
connect issue_slots[14].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask
connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb
connect issue_slots[14].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal
connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr
connect issue_slots[14].in_uop.bits.is_br, issue_slots[16].out_uop.is_br
connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned
connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned
connect issue_slots[14].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state
connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std
connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta
connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load
connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd
connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw
connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn
connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel
connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel
connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel
connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type
connect issue_slots[14].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code
connect issue_slots[14].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type
connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc
connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc
connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst
connect issue_slots[14].in_uop.bits.inst, issue_slots[16].out_uop.inst
connect issue_slots[14].in_uop.bits.uopc, issue_slots[16].out_uop.uopc
node _T_242 = eq(_WIRE_20, UInt<3>(0h4))
when _T_242 :
connect issue_slots[14].in_uop.valid, issue_slots[17].will_be_valid
connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc
connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc
connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if
connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if
connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if
connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if
connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if
connect issue_slots[14].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single
connect issue_slots[14].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val
connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en
connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype
connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype
connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype
connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val
connect issue_slots[14].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3
connect issue_slots[14].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2
connect issue_slots[14].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1
connect issue_slots[14].in_uop.bits.ldst, issue_slots[17].out_uop.ldst
connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1
connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit
connect issue_slots[14].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique
connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc
connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq
connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq
connect issue_slots[14].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo
connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei
connect issue_slots[14].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence
connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed
connect issue_slots[14].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size
connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd
connect issue_slots[14].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable
connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause
connect issue_slots[14].in_uop.bits.exception, issue_slots[17].out_uop.exception
connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst
connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy
connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy
connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy
connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy
connect issue_slots[14].in_uop.bits.ppred, issue_slots[17].out_uop.ppred
connect issue_slots[14].in_uop.bits.prs3, issue_slots[17].out_uop.prs3
connect issue_slots[14].in_uop.bits.prs2, issue_slots[17].out_uop.prs2
connect issue_slots[14].in_uop.bits.prs1, issue_slots[17].out_uop.prs1
connect issue_slots[14].in_uop.bits.pdst, issue_slots[17].out_uop.pdst
connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx
connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx
connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx
connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx
connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr
connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed
connect issue_slots[14].in_uop.bits.taken, issue_slots[17].out_uop.taken
connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob
connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst
connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx
connect issue_slots[14].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag
connect issue_slots[14].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask
connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb
connect issue_slots[14].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal
connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr
connect issue_slots[14].in_uop.bits.is_br, issue_slots[17].out_uop.is_br
connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned
connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned
connect issue_slots[14].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state
connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std
connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta
connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load
connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd
connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw
connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn
connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel
connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel
connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel
connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type
connect issue_slots[14].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code
connect issue_slots[14].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type
connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc
connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc
connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst
connect issue_slots[14].in_uop.bits.inst, issue_slots[17].out_uop.inst
connect issue_slots[14].in_uop.bits.uopc, issue_slots[17].out_uop.uopc
node _issue_slots_14_clear_T = neq(_WIRE_17, UInt<1>(0h0))
connect issue_slots[14].clear, _issue_slots_14_clear_T
connect issue_slots[15].in_uop.valid, UInt<1>(0h0)
connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc
connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc
connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if
connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if
connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if
connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if
connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if
connect issue_slots[15].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single
connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val
connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en
connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype
connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype
connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype
connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val
connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3
connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2
connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1
connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst
connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1
connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit
connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique
connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc
connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq
connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq
connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo
connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei
connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence
connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed
connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size
connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd
connect issue_slots[15].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable
connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause
connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception
connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst
connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy
connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy
connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy
connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy
connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred
connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3
connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2
connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1
connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst
connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx
connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx
connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx
connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx
connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr
connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed
connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken
connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob
connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst
connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx
connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag
connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask
connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb
connect issue_slots[15].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal
connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr
connect issue_slots[15].in_uop.bits.is_br, issue_slots[16].out_uop.is_br
connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned
connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned
connect issue_slots[15].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state
connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std
connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta
connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load
connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd
connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw
connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn
connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel
connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel
connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel
connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type
connect issue_slots[15].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code
connect issue_slots[15].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type
connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc
connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc
connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst
connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst
connect issue_slots[15].in_uop.bits.uopc, issue_slots[16].out_uop.uopc
node _T_243 = eq(_WIRE_19, UInt<1>(0h1))
when _T_243 :
connect issue_slots[15].in_uop.valid, issue_slots[16].will_be_valid
connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc
connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc
connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if
connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if
connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if
connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if
connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if
connect issue_slots[15].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single
connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val
connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en
connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype
connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype
connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype
connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val
connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3
connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2
connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1
connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst
connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1
connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit
connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique
connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc
connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq
connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq
connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo
connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei
connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence
connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed
connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size
connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd
connect issue_slots[15].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable
connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause
connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception
connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst
connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy
connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy
connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy
connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy
connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred
connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3
connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2
connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1
connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst
connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx
connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx
connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx
connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx
connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr
connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed
connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken
connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob
connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst
connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx
connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag
connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask
connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb
connect issue_slots[15].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal
connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr
connect issue_slots[15].in_uop.bits.is_br, issue_slots[16].out_uop.is_br
connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned
connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned
connect issue_slots[15].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state
connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std
connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta
connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load
connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd
connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw
connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn
connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel
connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel
connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel
connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type
connect issue_slots[15].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code
connect issue_slots[15].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type
connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc
connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc
connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst
connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst
connect issue_slots[15].in_uop.bits.uopc, issue_slots[16].out_uop.uopc
node _T_244 = eq(_WIRE_20, UInt<2>(0h2))
when _T_244 :
connect issue_slots[15].in_uop.valid, issue_slots[17].will_be_valid
connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc
connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc
connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if
connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if
connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if
connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if
connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if
connect issue_slots[15].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single
connect issue_slots[15].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val
connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en
connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype
connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype
connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype
connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val
connect issue_slots[15].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3
connect issue_slots[15].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2
connect issue_slots[15].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1
connect issue_slots[15].in_uop.bits.ldst, issue_slots[17].out_uop.ldst
connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1
connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit
connect issue_slots[15].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique
connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc
connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq
connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq
connect issue_slots[15].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo
connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei
connect issue_slots[15].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence
connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed
connect issue_slots[15].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size
connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd
connect issue_slots[15].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable
connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause
connect issue_slots[15].in_uop.bits.exception, issue_slots[17].out_uop.exception
connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst
connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy
connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy
connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy
connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy
connect issue_slots[15].in_uop.bits.ppred, issue_slots[17].out_uop.ppred
connect issue_slots[15].in_uop.bits.prs3, issue_slots[17].out_uop.prs3
connect issue_slots[15].in_uop.bits.prs2, issue_slots[17].out_uop.prs2
connect issue_slots[15].in_uop.bits.prs1, issue_slots[17].out_uop.prs1
connect issue_slots[15].in_uop.bits.pdst, issue_slots[17].out_uop.pdst
connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx
connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx
connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx
connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx
connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr
connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed
connect issue_slots[15].in_uop.bits.taken, issue_slots[17].out_uop.taken
connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob
connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst
connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx
connect issue_slots[15].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag
connect issue_slots[15].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask
connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb
connect issue_slots[15].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal
connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr
connect issue_slots[15].in_uop.bits.is_br, issue_slots[17].out_uop.is_br
connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned
connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned
connect issue_slots[15].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state
connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std
connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta
connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load
connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd
connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw
connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn
connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel
connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel
connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel
connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type
connect issue_slots[15].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code
connect issue_slots[15].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type
connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc
connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc
connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst
connect issue_slots[15].in_uop.bits.inst, issue_slots[17].out_uop.inst
connect issue_slots[15].in_uop.bits.uopc, issue_slots[17].out_uop.uopc
node _T_245 = eq(_WIRE_21, UInt<3>(0h4))
when _T_245 :
connect issue_slots[15].in_uop.valid, issue_slots[18].will_be_valid
connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc
connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc
connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if
connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if
connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if
connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if
connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if
connect issue_slots[15].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single
connect issue_slots[15].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val
connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en
connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype
connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype
connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype
connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val
connect issue_slots[15].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3
connect issue_slots[15].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2
connect issue_slots[15].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1
connect issue_slots[15].in_uop.bits.ldst, issue_slots[18].out_uop.ldst
connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1
connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit
connect issue_slots[15].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique
connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc
connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq
connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq
connect issue_slots[15].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo
connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei
connect issue_slots[15].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence
connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed
connect issue_slots[15].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size
connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd
connect issue_slots[15].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable
connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause
connect issue_slots[15].in_uop.bits.exception, issue_slots[18].out_uop.exception
connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst
connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy
connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy
connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy
connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy
connect issue_slots[15].in_uop.bits.ppred, issue_slots[18].out_uop.ppred
connect issue_slots[15].in_uop.bits.prs3, issue_slots[18].out_uop.prs3
connect issue_slots[15].in_uop.bits.prs2, issue_slots[18].out_uop.prs2
connect issue_slots[15].in_uop.bits.prs1, issue_slots[18].out_uop.prs1
connect issue_slots[15].in_uop.bits.pdst, issue_slots[18].out_uop.pdst
connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx
connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx
connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx
connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx
connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr
connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed
connect issue_slots[15].in_uop.bits.taken, issue_slots[18].out_uop.taken
connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob
connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst
connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx
connect issue_slots[15].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag
connect issue_slots[15].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask
connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb
connect issue_slots[15].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal
connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr
connect issue_slots[15].in_uop.bits.is_br, issue_slots[18].out_uop.is_br
connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned
connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned
connect issue_slots[15].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state
connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std
connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta
connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load
connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd
connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw
connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn
connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel
connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel
connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel
connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type
connect issue_slots[15].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code
connect issue_slots[15].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type
connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc
connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc
connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst
connect issue_slots[15].in_uop.bits.inst, issue_slots[18].out_uop.inst
connect issue_slots[15].in_uop.bits.uopc, issue_slots[18].out_uop.uopc
node _issue_slots_15_clear_T = neq(_WIRE_18, UInt<1>(0h0))
connect issue_slots[15].clear, _issue_slots_15_clear_T
connect issue_slots[16].in_uop.valid, UInt<1>(0h0)
connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc
connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc
connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if
connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if
connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if
connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if
connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if
connect issue_slots[16].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single
connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val
connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en
connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype
connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype
connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype
connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val
connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3
connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2
connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1
connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst
connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1
connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit
connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique
connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc
connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq
connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq
connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo
connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei
connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence
connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed
connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size
connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd
connect issue_slots[16].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable
connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause
connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception
connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst
connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy
connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy
connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy
connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy
connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred
connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3
connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2
connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1
connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst
connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx
connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx
connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx
connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx
connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr
connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed
connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken
connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob
connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst
connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx
connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag
connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask
connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb
connect issue_slots[16].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal
connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr
connect issue_slots[16].in_uop.bits.is_br, issue_slots[17].out_uop.is_br
connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned
connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned
connect issue_slots[16].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state
connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std
connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta
connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load
connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd
connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw
connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn
connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel
connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel
connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel
connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type
connect issue_slots[16].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code
connect issue_slots[16].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type
connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc
connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc
connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst
connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst
connect issue_slots[16].in_uop.bits.uopc, issue_slots[17].out_uop.uopc
node _T_246 = eq(_WIRE_20, UInt<1>(0h1))
when _T_246 :
connect issue_slots[16].in_uop.valid, issue_slots[17].will_be_valid
connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc
connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc
connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if
connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if
connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if
connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if
connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if
connect issue_slots[16].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single
connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val
connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en
connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype
connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype
connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype
connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val
connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3
connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2
connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1
connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst
connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1
connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit
connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique
connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc
connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq
connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq
connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo
connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei
connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence
connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed
connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size
connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd
connect issue_slots[16].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable
connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause
connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception
connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst
connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy
connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy
connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy
connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy
connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred
connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3
connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2
connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1
connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst
connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx
connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx
connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx
connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx
connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr
connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed
connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken
connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob
connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst
connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx
connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag
connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask
connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb
connect issue_slots[16].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal
connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr
connect issue_slots[16].in_uop.bits.is_br, issue_slots[17].out_uop.is_br
connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned
connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned
connect issue_slots[16].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state
connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std
connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta
connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load
connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd
connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw
connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn
connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel
connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel
connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel
connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type
connect issue_slots[16].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code
connect issue_slots[16].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type
connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc
connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc
connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst
connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst
connect issue_slots[16].in_uop.bits.uopc, issue_slots[17].out_uop.uopc
node _T_247 = eq(_WIRE_21, UInt<2>(0h2))
when _T_247 :
connect issue_slots[16].in_uop.valid, issue_slots[18].will_be_valid
connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc
connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc
connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if
connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if
connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if
connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if
connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if
connect issue_slots[16].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single
connect issue_slots[16].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val
connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en
connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype
connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype
connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype
connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val
connect issue_slots[16].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3
connect issue_slots[16].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2
connect issue_slots[16].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1
connect issue_slots[16].in_uop.bits.ldst, issue_slots[18].out_uop.ldst
connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1
connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit
connect issue_slots[16].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique
connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc
connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq
connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq
connect issue_slots[16].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo
connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei
connect issue_slots[16].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence
connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed
connect issue_slots[16].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size
connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd
connect issue_slots[16].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable
connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause
connect issue_slots[16].in_uop.bits.exception, issue_slots[18].out_uop.exception
connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst
connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy
connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy
connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy
connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy
connect issue_slots[16].in_uop.bits.ppred, issue_slots[18].out_uop.ppred
connect issue_slots[16].in_uop.bits.prs3, issue_slots[18].out_uop.prs3
connect issue_slots[16].in_uop.bits.prs2, issue_slots[18].out_uop.prs2
connect issue_slots[16].in_uop.bits.prs1, issue_slots[18].out_uop.prs1
connect issue_slots[16].in_uop.bits.pdst, issue_slots[18].out_uop.pdst
connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx
connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx
connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx
connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx
connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr
connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed
connect issue_slots[16].in_uop.bits.taken, issue_slots[18].out_uop.taken
connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob
connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst
connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx
connect issue_slots[16].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag
connect issue_slots[16].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask
connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb
connect issue_slots[16].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal
connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr
connect issue_slots[16].in_uop.bits.is_br, issue_slots[18].out_uop.is_br
connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned
connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned
connect issue_slots[16].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state
connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std
connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta
connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load
connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd
connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw
connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn
connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel
connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel
connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel
connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type
connect issue_slots[16].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code
connect issue_slots[16].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type
connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc
connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc
connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst
connect issue_slots[16].in_uop.bits.inst, issue_slots[18].out_uop.inst
connect issue_slots[16].in_uop.bits.uopc, issue_slots[18].out_uop.uopc
node _T_248 = eq(_WIRE_22, UInt<3>(0h4))
when _T_248 :
connect issue_slots[16].in_uop.valid, issue_slots[19].will_be_valid
connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc
connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc
connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if
connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if
connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if
connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if
connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if
connect issue_slots[16].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single
connect issue_slots[16].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val
connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en
connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype
connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype
connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype
connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val
connect issue_slots[16].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3
connect issue_slots[16].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2
connect issue_slots[16].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1
connect issue_slots[16].in_uop.bits.ldst, issue_slots[19].out_uop.ldst
connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1
connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit
connect issue_slots[16].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique
connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc
connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq
connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq
connect issue_slots[16].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo
connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei
connect issue_slots[16].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence
connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed
connect issue_slots[16].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size
connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd
connect issue_slots[16].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable
connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause
connect issue_slots[16].in_uop.bits.exception, issue_slots[19].out_uop.exception
connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst
connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy
connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy
connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy
connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy
connect issue_slots[16].in_uop.bits.ppred, issue_slots[19].out_uop.ppred
connect issue_slots[16].in_uop.bits.prs3, issue_slots[19].out_uop.prs3
connect issue_slots[16].in_uop.bits.prs2, issue_slots[19].out_uop.prs2
connect issue_slots[16].in_uop.bits.prs1, issue_slots[19].out_uop.prs1
connect issue_slots[16].in_uop.bits.pdst, issue_slots[19].out_uop.pdst
connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx
connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx
connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx
connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx
connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr
connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed
connect issue_slots[16].in_uop.bits.taken, issue_slots[19].out_uop.taken
connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob
connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst
connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx
connect issue_slots[16].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag
connect issue_slots[16].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask
connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb
connect issue_slots[16].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal
connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr
connect issue_slots[16].in_uop.bits.is_br, issue_slots[19].out_uop.is_br
connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned
connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned
connect issue_slots[16].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state
connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std
connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta
connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load
connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd
connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw
connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn
connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel
connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel
connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel
connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type
connect issue_slots[16].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code
connect issue_slots[16].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type
connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc
connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc
connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst
connect issue_slots[16].in_uop.bits.inst, issue_slots[19].out_uop.inst
connect issue_slots[16].in_uop.bits.uopc, issue_slots[19].out_uop.uopc
node _issue_slots_16_clear_T = neq(_WIRE_19, UInt<1>(0h0))
connect issue_slots[16].clear, _issue_slots_16_clear_T
connect issue_slots[17].in_uop.valid, UInt<1>(0h0)
connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc
connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc
connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if
connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if
connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if
connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if
connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if
connect issue_slots[17].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single
connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val
connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en
connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype
connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype
connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype
connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val
connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3
connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2
connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1
connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst
connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1
connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit
connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique
connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc
connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq
connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq
connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo
connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei
connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence
connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed
connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size
connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd
connect issue_slots[17].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable
connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause
connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception
connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst
connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy
connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy
connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy
connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy
connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred
connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3
connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2
connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1
connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst
connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx
connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx
connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx
connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx
connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr
connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed
connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken
connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob
connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst
connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx
connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag
connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask
connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb
connect issue_slots[17].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal
connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr
connect issue_slots[17].in_uop.bits.is_br, issue_slots[18].out_uop.is_br
connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned
connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned
connect issue_slots[17].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state
connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std
connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta
connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load
connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd
connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw
connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn
connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel
connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel
connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel
connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type
connect issue_slots[17].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code
connect issue_slots[17].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type
connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc
connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc
connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst
connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst
connect issue_slots[17].in_uop.bits.uopc, issue_slots[18].out_uop.uopc
node _T_249 = eq(_WIRE_21, UInt<1>(0h1))
when _T_249 :
connect issue_slots[17].in_uop.valid, issue_slots[18].will_be_valid
connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc
connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc
connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if
connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if
connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if
connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if
connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if
connect issue_slots[17].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single
connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val
connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en
connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype
connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype
connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype
connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val
connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3
connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2
connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1
connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst
connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1
connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit
connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique
connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc
connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq
connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq
connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo
connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei
connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence
connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed
connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size
connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd
connect issue_slots[17].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable
connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause
connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception
connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst
connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy
connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy
connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy
connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy
connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred
connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3
connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2
connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1
connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst
connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx
connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx
connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx
connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx
connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr
connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed
connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken
connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob
connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst
connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx
connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag
connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask
connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb
connect issue_slots[17].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal
connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr
connect issue_slots[17].in_uop.bits.is_br, issue_slots[18].out_uop.is_br
connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned
connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned
connect issue_slots[17].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state
connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std
connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta
connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load
connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd
connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw
connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn
connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel
connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel
connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel
connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type
connect issue_slots[17].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code
connect issue_slots[17].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type
connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc
connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc
connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst
connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst
connect issue_slots[17].in_uop.bits.uopc, issue_slots[18].out_uop.uopc
node _T_250 = eq(_WIRE_22, UInt<2>(0h2))
when _T_250 :
connect issue_slots[17].in_uop.valid, issue_slots[19].will_be_valid
connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc
connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc
connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if
connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if
connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if
connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if
connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if
connect issue_slots[17].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single
connect issue_slots[17].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val
connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en
connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype
connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype
connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype
connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val
connect issue_slots[17].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3
connect issue_slots[17].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2
connect issue_slots[17].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1
connect issue_slots[17].in_uop.bits.ldst, issue_slots[19].out_uop.ldst
connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1
connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit
connect issue_slots[17].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique
connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc
connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq
connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq
connect issue_slots[17].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo
connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei
connect issue_slots[17].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence
connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed
connect issue_slots[17].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size
connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd
connect issue_slots[17].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable
connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause
connect issue_slots[17].in_uop.bits.exception, issue_slots[19].out_uop.exception
connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst
connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy
connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy
connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy
connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy
connect issue_slots[17].in_uop.bits.ppred, issue_slots[19].out_uop.ppred
connect issue_slots[17].in_uop.bits.prs3, issue_slots[19].out_uop.prs3
connect issue_slots[17].in_uop.bits.prs2, issue_slots[19].out_uop.prs2
connect issue_slots[17].in_uop.bits.prs1, issue_slots[19].out_uop.prs1
connect issue_slots[17].in_uop.bits.pdst, issue_slots[19].out_uop.pdst
connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx
connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx
connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx
connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx
connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr
connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed
connect issue_slots[17].in_uop.bits.taken, issue_slots[19].out_uop.taken
connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob
connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst
connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx
connect issue_slots[17].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag
connect issue_slots[17].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask
connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb
connect issue_slots[17].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal
connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr
connect issue_slots[17].in_uop.bits.is_br, issue_slots[19].out_uop.is_br
connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned
connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned
connect issue_slots[17].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state
connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std
connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta
connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load
connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd
connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw
connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn
connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel
connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel
connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel
connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type
connect issue_slots[17].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code
connect issue_slots[17].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type
connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc
connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc
connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst
connect issue_slots[17].in_uop.bits.inst, issue_slots[19].out_uop.inst
connect issue_slots[17].in_uop.bits.uopc, issue_slots[19].out_uop.uopc
node _T_251 = eq(_WIRE_23, UInt<3>(0h4))
when _T_251 :
connect issue_slots[17].in_uop.valid, issue_slots[20].will_be_valid
connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc
connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc
connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if
connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if
connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if
connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if
connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if
connect issue_slots[17].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single
connect issue_slots[17].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val
connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en
connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype
connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype
connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype
connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val
connect issue_slots[17].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3
connect issue_slots[17].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2
connect issue_slots[17].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1
connect issue_slots[17].in_uop.bits.ldst, issue_slots[20].out_uop.ldst
connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1
connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit
connect issue_slots[17].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique
connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc
connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq
connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq
connect issue_slots[17].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo
connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei
connect issue_slots[17].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence
connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed
connect issue_slots[17].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size
connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd
connect issue_slots[17].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable
connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause
connect issue_slots[17].in_uop.bits.exception, issue_slots[20].out_uop.exception
connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst
connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy
connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy
connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy
connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy
connect issue_slots[17].in_uop.bits.ppred, issue_slots[20].out_uop.ppred
connect issue_slots[17].in_uop.bits.prs3, issue_slots[20].out_uop.prs3
connect issue_slots[17].in_uop.bits.prs2, issue_slots[20].out_uop.prs2
connect issue_slots[17].in_uop.bits.prs1, issue_slots[20].out_uop.prs1
connect issue_slots[17].in_uop.bits.pdst, issue_slots[20].out_uop.pdst
connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx
connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx
connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx
connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx
connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr
connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed
connect issue_slots[17].in_uop.bits.taken, issue_slots[20].out_uop.taken
connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob
connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst
connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx
connect issue_slots[17].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag
connect issue_slots[17].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask
connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb
connect issue_slots[17].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal
connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr
connect issue_slots[17].in_uop.bits.is_br, issue_slots[20].out_uop.is_br
connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned
connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned
connect issue_slots[17].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state
connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std
connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta
connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load
connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd
connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw
connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn
connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel
connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel
connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel
connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type
connect issue_slots[17].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code
connect issue_slots[17].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type
connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc
connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc
connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst
connect issue_slots[17].in_uop.bits.inst, issue_slots[20].out_uop.inst
connect issue_slots[17].in_uop.bits.uopc, issue_slots[20].out_uop.uopc
node _issue_slots_17_clear_T = neq(_WIRE_20, UInt<1>(0h0))
connect issue_slots[17].clear, _issue_slots_17_clear_T
connect issue_slots[18].in_uop.valid, UInt<1>(0h0)
connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc
connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc
connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if
connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if
connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if
connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if
connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if
connect issue_slots[18].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single
connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val
connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en
connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype
connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype
connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype
connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val
connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3
connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2
connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1
connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst
connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1
connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit
connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique
connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc
connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq
connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq
connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo
connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei
connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence
connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed
connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size
connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd
connect issue_slots[18].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable
connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause
connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception
connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst
connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy
connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy
connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy
connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy
connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred
connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3
connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2
connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1
connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst
connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx
connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx
connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx
connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx
connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr
connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed
connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken
connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob
connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst
connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx
connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag
connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask
connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb
connect issue_slots[18].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal
connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr
connect issue_slots[18].in_uop.bits.is_br, issue_slots[19].out_uop.is_br
connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned
connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned
connect issue_slots[18].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state
connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std
connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta
connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load
connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd
connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw
connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn
connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel
connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel
connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel
connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type
connect issue_slots[18].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code
connect issue_slots[18].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type
connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc
connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc
connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst
connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst
connect issue_slots[18].in_uop.bits.uopc, issue_slots[19].out_uop.uopc
node _T_252 = eq(_WIRE_22, UInt<1>(0h1))
when _T_252 :
connect issue_slots[18].in_uop.valid, issue_slots[19].will_be_valid
connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc
connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc
connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if
connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if
connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if
connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if
connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if
connect issue_slots[18].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single
connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val
connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en
connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype
connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype
connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype
connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val
connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3
connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2
connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1
connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst
connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1
connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit
connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique
connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc
connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq
connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq
connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo
connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei
connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence
connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed
connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size
connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd
connect issue_slots[18].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable
connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause
connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception
connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst
connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy
connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy
connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy
connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy
connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred
connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3
connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2
connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1
connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst
connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx
connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx
connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx
connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx
connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr
connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed
connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken
connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob
connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst
connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx
connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag
connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask
connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb
connect issue_slots[18].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal
connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr
connect issue_slots[18].in_uop.bits.is_br, issue_slots[19].out_uop.is_br
connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned
connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned
connect issue_slots[18].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state
connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std
connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta
connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load
connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd
connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw
connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn
connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel
connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel
connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel
connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type
connect issue_slots[18].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code
connect issue_slots[18].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type
connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc
connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc
connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst
connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst
connect issue_slots[18].in_uop.bits.uopc, issue_slots[19].out_uop.uopc
node _T_253 = eq(_WIRE_23, UInt<2>(0h2))
when _T_253 :
connect issue_slots[18].in_uop.valid, issue_slots[20].will_be_valid
connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc
connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc
connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if
connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if
connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if
connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if
connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if
connect issue_slots[18].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single
connect issue_slots[18].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val
connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en
connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype
connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype
connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype
connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val
connect issue_slots[18].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3
connect issue_slots[18].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2
connect issue_slots[18].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1
connect issue_slots[18].in_uop.bits.ldst, issue_slots[20].out_uop.ldst
connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1
connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit
connect issue_slots[18].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique
connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc
connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq
connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq
connect issue_slots[18].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo
connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei
connect issue_slots[18].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence
connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed
connect issue_slots[18].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size
connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd
connect issue_slots[18].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable
connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause
connect issue_slots[18].in_uop.bits.exception, issue_slots[20].out_uop.exception
connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst
connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy
connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy
connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy
connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy
connect issue_slots[18].in_uop.bits.ppred, issue_slots[20].out_uop.ppred
connect issue_slots[18].in_uop.bits.prs3, issue_slots[20].out_uop.prs3
connect issue_slots[18].in_uop.bits.prs2, issue_slots[20].out_uop.prs2
connect issue_slots[18].in_uop.bits.prs1, issue_slots[20].out_uop.prs1
connect issue_slots[18].in_uop.bits.pdst, issue_slots[20].out_uop.pdst
connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx
connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx
connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx
connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx
connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr
connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed
connect issue_slots[18].in_uop.bits.taken, issue_slots[20].out_uop.taken
connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob
connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst
connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx
connect issue_slots[18].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag
connect issue_slots[18].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask
connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb
connect issue_slots[18].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal
connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr
connect issue_slots[18].in_uop.bits.is_br, issue_slots[20].out_uop.is_br
connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned
connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned
connect issue_slots[18].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state
connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std
connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta
connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load
connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd
connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw
connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn
connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel
connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel
connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel
connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type
connect issue_slots[18].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code
connect issue_slots[18].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type
connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc
connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc
connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst
connect issue_slots[18].in_uop.bits.inst, issue_slots[20].out_uop.inst
connect issue_slots[18].in_uop.bits.uopc, issue_slots[20].out_uop.uopc
node _T_254 = eq(_WIRE_24, UInt<3>(0h4))
when _T_254 :
connect issue_slots[18].in_uop.valid, issue_slots[21].will_be_valid
connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc
connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc
connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if
connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if
connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if
connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if
connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if
connect issue_slots[18].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single
connect issue_slots[18].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val
connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en
connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype
connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype
connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype
connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val
connect issue_slots[18].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3
connect issue_slots[18].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2
connect issue_slots[18].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1
connect issue_slots[18].in_uop.bits.ldst, issue_slots[21].out_uop.ldst
connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1
connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit
connect issue_slots[18].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique
connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc
connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq
connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq
connect issue_slots[18].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo
connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei
connect issue_slots[18].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence
connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed
connect issue_slots[18].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size
connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd
connect issue_slots[18].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable
connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause
connect issue_slots[18].in_uop.bits.exception, issue_slots[21].out_uop.exception
connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst
connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy
connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy
connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy
connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy
connect issue_slots[18].in_uop.bits.ppred, issue_slots[21].out_uop.ppred
connect issue_slots[18].in_uop.bits.prs3, issue_slots[21].out_uop.prs3
connect issue_slots[18].in_uop.bits.prs2, issue_slots[21].out_uop.prs2
connect issue_slots[18].in_uop.bits.prs1, issue_slots[21].out_uop.prs1
connect issue_slots[18].in_uop.bits.pdst, issue_slots[21].out_uop.pdst
connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx
connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx
connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx
connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx
connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr
connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed
connect issue_slots[18].in_uop.bits.taken, issue_slots[21].out_uop.taken
connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob
connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst
connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx
connect issue_slots[18].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag
connect issue_slots[18].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask
connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb
connect issue_slots[18].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal
connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr
connect issue_slots[18].in_uop.bits.is_br, issue_slots[21].out_uop.is_br
connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned
connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned
connect issue_slots[18].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state
connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std
connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta
connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load
connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd
connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw
connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn
connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel
connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel
connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel
connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type
connect issue_slots[18].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code
connect issue_slots[18].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type
connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc
connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc
connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst
connect issue_slots[18].in_uop.bits.inst, issue_slots[21].out_uop.inst
connect issue_slots[18].in_uop.bits.uopc, issue_slots[21].out_uop.uopc
node _issue_slots_18_clear_T = neq(_WIRE_21, UInt<1>(0h0))
connect issue_slots[18].clear, _issue_slots_18_clear_T
connect issue_slots[19].in_uop.valid, UInt<1>(0h0)
connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc
connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc
connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if
connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if
connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if
connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if
connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if
connect issue_slots[19].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single
connect issue_slots[19].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val
connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en
connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype
connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype
connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype
connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val
connect issue_slots[19].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3
connect issue_slots[19].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2
connect issue_slots[19].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1
connect issue_slots[19].in_uop.bits.ldst, issue_slots[20].out_uop.ldst
connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1
connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit
connect issue_slots[19].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique
connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc
connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq
connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq
connect issue_slots[19].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo
connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei
connect issue_slots[19].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence
connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed
connect issue_slots[19].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size
connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd
connect issue_slots[19].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable
connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause
connect issue_slots[19].in_uop.bits.exception, issue_slots[20].out_uop.exception
connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst
connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy
connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy
connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy
connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy
connect issue_slots[19].in_uop.bits.ppred, issue_slots[20].out_uop.ppred
connect issue_slots[19].in_uop.bits.prs3, issue_slots[20].out_uop.prs3
connect issue_slots[19].in_uop.bits.prs2, issue_slots[20].out_uop.prs2
connect issue_slots[19].in_uop.bits.prs1, issue_slots[20].out_uop.prs1
connect issue_slots[19].in_uop.bits.pdst, issue_slots[20].out_uop.pdst
connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx
connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx
connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx
connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx
connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr
connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed
connect issue_slots[19].in_uop.bits.taken, issue_slots[20].out_uop.taken
connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob
connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst
connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx
connect issue_slots[19].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag
connect issue_slots[19].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask
connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb
connect issue_slots[19].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal
connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr
connect issue_slots[19].in_uop.bits.is_br, issue_slots[20].out_uop.is_br
connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned
connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned
connect issue_slots[19].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state
connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std
connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta
connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load
connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd
connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw
connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn
connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel
connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel
connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel
connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type
connect issue_slots[19].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code
connect issue_slots[19].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type
connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc
connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc
connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst
connect issue_slots[19].in_uop.bits.inst, issue_slots[20].out_uop.inst
connect issue_slots[19].in_uop.bits.uopc, issue_slots[20].out_uop.uopc
node _T_255 = eq(_WIRE_23, UInt<1>(0h1))
when _T_255 :
connect issue_slots[19].in_uop.valid, issue_slots[20].will_be_valid
connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc
connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc
connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if
connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if
connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if
connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if
connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if
connect issue_slots[19].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single
connect issue_slots[19].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val
connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en
connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype
connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype
connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype
connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val
connect issue_slots[19].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3
connect issue_slots[19].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2
connect issue_slots[19].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1
connect issue_slots[19].in_uop.bits.ldst, issue_slots[20].out_uop.ldst
connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1
connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit
connect issue_slots[19].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique
connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc
connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq
connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq
connect issue_slots[19].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo
connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei
connect issue_slots[19].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence
connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed
connect issue_slots[19].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size
connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd
connect issue_slots[19].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable
connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause
connect issue_slots[19].in_uop.bits.exception, issue_slots[20].out_uop.exception
connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst
connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy
connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy
connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy
connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy
connect issue_slots[19].in_uop.bits.ppred, issue_slots[20].out_uop.ppred
connect issue_slots[19].in_uop.bits.prs3, issue_slots[20].out_uop.prs3
connect issue_slots[19].in_uop.bits.prs2, issue_slots[20].out_uop.prs2
connect issue_slots[19].in_uop.bits.prs1, issue_slots[20].out_uop.prs1
connect issue_slots[19].in_uop.bits.pdst, issue_slots[20].out_uop.pdst
connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx
connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx
connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx
connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx
connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr
connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed
connect issue_slots[19].in_uop.bits.taken, issue_slots[20].out_uop.taken
connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob
connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst
connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx
connect issue_slots[19].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag
connect issue_slots[19].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask
connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb
connect issue_slots[19].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal
connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr
connect issue_slots[19].in_uop.bits.is_br, issue_slots[20].out_uop.is_br
connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned
connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned
connect issue_slots[19].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state
connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std
connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta
connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load
connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd
connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw
connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn
connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel
connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel
connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel
connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type
connect issue_slots[19].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code
connect issue_slots[19].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type
connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc
connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc
connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst
connect issue_slots[19].in_uop.bits.inst, issue_slots[20].out_uop.inst
connect issue_slots[19].in_uop.bits.uopc, issue_slots[20].out_uop.uopc
node _T_256 = eq(_WIRE_24, UInt<2>(0h2))
when _T_256 :
connect issue_slots[19].in_uop.valid, issue_slots[21].will_be_valid
connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc
connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc
connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if
connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if
connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if
connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if
connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if
connect issue_slots[19].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single
connect issue_slots[19].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val
connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en
connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype
connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype
connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype
connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val
connect issue_slots[19].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3
connect issue_slots[19].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2
connect issue_slots[19].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1
connect issue_slots[19].in_uop.bits.ldst, issue_slots[21].out_uop.ldst
connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1
connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit
connect issue_slots[19].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique
connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc
connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq
connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq
connect issue_slots[19].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo
connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei
connect issue_slots[19].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence
connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed
connect issue_slots[19].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size
connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd
connect issue_slots[19].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable
connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause
connect issue_slots[19].in_uop.bits.exception, issue_slots[21].out_uop.exception
connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst
connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy
connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy
connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy
connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy
connect issue_slots[19].in_uop.bits.ppred, issue_slots[21].out_uop.ppred
connect issue_slots[19].in_uop.bits.prs3, issue_slots[21].out_uop.prs3
connect issue_slots[19].in_uop.bits.prs2, issue_slots[21].out_uop.prs2
connect issue_slots[19].in_uop.bits.prs1, issue_slots[21].out_uop.prs1
connect issue_slots[19].in_uop.bits.pdst, issue_slots[21].out_uop.pdst
connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx
connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx
connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx
connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx
connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr
connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed
connect issue_slots[19].in_uop.bits.taken, issue_slots[21].out_uop.taken
connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob
connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst
connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx
connect issue_slots[19].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag
connect issue_slots[19].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask
connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb
connect issue_slots[19].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal
connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr
connect issue_slots[19].in_uop.bits.is_br, issue_slots[21].out_uop.is_br
connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned
connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned
connect issue_slots[19].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state
connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std
connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta
connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load
connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd
connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw
connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn
connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel
connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel
connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel
connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type
connect issue_slots[19].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code
connect issue_slots[19].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type
connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc
connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc
connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst
connect issue_slots[19].in_uop.bits.inst, issue_slots[21].out_uop.inst
connect issue_slots[19].in_uop.bits.uopc, issue_slots[21].out_uop.uopc
node _T_257 = eq(_WIRE_25, UInt<3>(0h4))
when _T_257 :
connect issue_slots[19].in_uop.valid, issue_slots[22].will_be_valid
connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc
connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc
connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if
connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if
connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if
connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if
connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if
connect issue_slots[19].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single
connect issue_slots[19].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val
connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en
connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype
connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype
connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype
connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val
connect issue_slots[19].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3
connect issue_slots[19].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2
connect issue_slots[19].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1
connect issue_slots[19].in_uop.bits.ldst, issue_slots[22].out_uop.ldst
connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1
connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit
connect issue_slots[19].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique
connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc
connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq
connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq
connect issue_slots[19].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo
connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei
connect issue_slots[19].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence
connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed
connect issue_slots[19].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size
connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd
connect issue_slots[19].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable
connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause
connect issue_slots[19].in_uop.bits.exception, issue_slots[22].out_uop.exception
connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst
connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy
connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy
connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy
connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy
connect issue_slots[19].in_uop.bits.ppred, issue_slots[22].out_uop.ppred
connect issue_slots[19].in_uop.bits.prs3, issue_slots[22].out_uop.prs3
connect issue_slots[19].in_uop.bits.prs2, issue_slots[22].out_uop.prs2
connect issue_slots[19].in_uop.bits.prs1, issue_slots[22].out_uop.prs1
connect issue_slots[19].in_uop.bits.pdst, issue_slots[22].out_uop.pdst
connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx
connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx
connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx
connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx
connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr
connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed
connect issue_slots[19].in_uop.bits.taken, issue_slots[22].out_uop.taken
connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob
connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst
connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx
connect issue_slots[19].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag
connect issue_slots[19].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask
connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb
connect issue_slots[19].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal
connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr
connect issue_slots[19].in_uop.bits.is_br, issue_slots[22].out_uop.is_br
connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned
connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned
connect issue_slots[19].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state
connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std
connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta
connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load
connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd
connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw
connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn
connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel
connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel
connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel
connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type
connect issue_slots[19].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code
connect issue_slots[19].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type
connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc
connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc
connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst
connect issue_slots[19].in_uop.bits.inst, issue_slots[22].out_uop.inst
connect issue_slots[19].in_uop.bits.uopc, issue_slots[22].out_uop.uopc
node _issue_slots_19_clear_T = neq(_WIRE_22, UInt<1>(0h0))
connect issue_slots[19].clear, _issue_slots_19_clear_T
connect issue_slots[20].in_uop.valid, UInt<1>(0h0)
connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc
connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc
connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if
connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if
connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if
connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if
connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if
connect issue_slots[20].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single
connect issue_slots[20].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val
connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en
connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype
connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype
connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype
connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val
connect issue_slots[20].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3
connect issue_slots[20].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2
connect issue_slots[20].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1
connect issue_slots[20].in_uop.bits.ldst, issue_slots[21].out_uop.ldst
connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1
connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit
connect issue_slots[20].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique
connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc
connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq
connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq
connect issue_slots[20].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo
connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei
connect issue_slots[20].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence
connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed
connect issue_slots[20].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size
connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd
connect issue_slots[20].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable
connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause
connect issue_slots[20].in_uop.bits.exception, issue_slots[21].out_uop.exception
connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst
connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy
connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy
connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy
connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy
connect issue_slots[20].in_uop.bits.ppred, issue_slots[21].out_uop.ppred
connect issue_slots[20].in_uop.bits.prs3, issue_slots[21].out_uop.prs3
connect issue_slots[20].in_uop.bits.prs2, issue_slots[21].out_uop.prs2
connect issue_slots[20].in_uop.bits.prs1, issue_slots[21].out_uop.prs1
connect issue_slots[20].in_uop.bits.pdst, issue_slots[21].out_uop.pdst
connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx
connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx
connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx
connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx
connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr
connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed
connect issue_slots[20].in_uop.bits.taken, issue_slots[21].out_uop.taken
connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob
connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst
connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx
connect issue_slots[20].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag
connect issue_slots[20].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask
connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb
connect issue_slots[20].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal
connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr
connect issue_slots[20].in_uop.bits.is_br, issue_slots[21].out_uop.is_br
connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned
connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned
connect issue_slots[20].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state
connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std
connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta
connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load
connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd
connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw
connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn
connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel
connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel
connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel
connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type
connect issue_slots[20].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code
connect issue_slots[20].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type
connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc
connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc
connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst
connect issue_slots[20].in_uop.bits.inst, issue_slots[21].out_uop.inst
connect issue_slots[20].in_uop.bits.uopc, issue_slots[21].out_uop.uopc
node _T_258 = eq(_WIRE_24, UInt<1>(0h1))
when _T_258 :
connect issue_slots[20].in_uop.valid, issue_slots[21].will_be_valid
connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc
connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc
connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if
connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if
connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if
connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if
connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if
connect issue_slots[20].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single
connect issue_slots[20].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val
connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en
connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype
connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype
connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype
connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val
connect issue_slots[20].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3
connect issue_slots[20].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2
connect issue_slots[20].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1
connect issue_slots[20].in_uop.bits.ldst, issue_slots[21].out_uop.ldst
connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1
connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit
connect issue_slots[20].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique
connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc
connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq
connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq
connect issue_slots[20].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo
connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei
connect issue_slots[20].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence
connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed
connect issue_slots[20].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size
connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd
connect issue_slots[20].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable
connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause
connect issue_slots[20].in_uop.bits.exception, issue_slots[21].out_uop.exception
connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst
connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy
connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy
connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy
connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy
connect issue_slots[20].in_uop.bits.ppred, issue_slots[21].out_uop.ppred
connect issue_slots[20].in_uop.bits.prs3, issue_slots[21].out_uop.prs3
connect issue_slots[20].in_uop.bits.prs2, issue_slots[21].out_uop.prs2
connect issue_slots[20].in_uop.bits.prs1, issue_slots[21].out_uop.prs1
connect issue_slots[20].in_uop.bits.pdst, issue_slots[21].out_uop.pdst
connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx
connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx
connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx
connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx
connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr
connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed
connect issue_slots[20].in_uop.bits.taken, issue_slots[21].out_uop.taken
connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob
connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst
connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx
connect issue_slots[20].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag
connect issue_slots[20].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask
connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb
connect issue_slots[20].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal
connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr
connect issue_slots[20].in_uop.bits.is_br, issue_slots[21].out_uop.is_br
connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned
connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned
connect issue_slots[20].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state
connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std
connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta
connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load
connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd
connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw
connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn
connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel
connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel
connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel
connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type
connect issue_slots[20].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code
connect issue_slots[20].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type
connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc
connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc
connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst
connect issue_slots[20].in_uop.bits.inst, issue_slots[21].out_uop.inst
connect issue_slots[20].in_uop.bits.uopc, issue_slots[21].out_uop.uopc
node _T_259 = eq(_WIRE_25, UInt<2>(0h2))
when _T_259 :
connect issue_slots[20].in_uop.valid, issue_slots[22].will_be_valid
connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc
connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc
connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if
connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if
connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if
connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if
connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if
connect issue_slots[20].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single
connect issue_slots[20].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val
connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en
connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype
connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype
connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype
connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val
connect issue_slots[20].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3
connect issue_slots[20].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2
connect issue_slots[20].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1
connect issue_slots[20].in_uop.bits.ldst, issue_slots[22].out_uop.ldst
connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1
connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit
connect issue_slots[20].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique
connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc
connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq
connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq
connect issue_slots[20].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo
connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei
connect issue_slots[20].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence
connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed
connect issue_slots[20].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size
connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd
connect issue_slots[20].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable
connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause
connect issue_slots[20].in_uop.bits.exception, issue_slots[22].out_uop.exception
connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst
connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy
connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy
connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy
connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy
connect issue_slots[20].in_uop.bits.ppred, issue_slots[22].out_uop.ppred
connect issue_slots[20].in_uop.bits.prs3, issue_slots[22].out_uop.prs3
connect issue_slots[20].in_uop.bits.prs2, issue_slots[22].out_uop.prs2
connect issue_slots[20].in_uop.bits.prs1, issue_slots[22].out_uop.prs1
connect issue_slots[20].in_uop.bits.pdst, issue_slots[22].out_uop.pdst
connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx
connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx
connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx
connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx
connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr
connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed
connect issue_slots[20].in_uop.bits.taken, issue_slots[22].out_uop.taken
connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob
connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst
connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx
connect issue_slots[20].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag
connect issue_slots[20].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask
connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb
connect issue_slots[20].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal
connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr
connect issue_slots[20].in_uop.bits.is_br, issue_slots[22].out_uop.is_br
connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned
connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned
connect issue_slots[20].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state
connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std
connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta
connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load
connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd
connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw
connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn
connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel
connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel
connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel
connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type
connect issue_slots[20].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code
connect issue_slots[20].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type
connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc
connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc
connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst
connect issue_slots[20].in_uop.bits.inst, issue_slots[22].out_uop.inst
connect issue_slots[20].in_uop.bits.uopc, issue_slots[22].out_uop.uopc
node _T_260 = eq(_WIRE_26, UInt<3>(0h4))
when _T_260 :
connect issue_slots[20].in_uop.valid, issue_slots[23].will_be_valid
connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc
connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc
connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if
connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if
connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if
connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if
connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if
connect issue_slots[20].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single
connect issue_slots[20].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val
connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en
connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype
connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype
connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype
connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val
connect issue_slots[20].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3
connect issue_slots[20].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2
connect issue_slots[20].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1
connect issue_slots[20].in_uop.bits.ldst, issue_slots[23].out_uop.ldst
connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1
connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit
connect issue_slots[20].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique
connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc
connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq
connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq
connect issue_slots[20].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo
connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei
connect issue_slots[20].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence
connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed
connect issue_slots[20].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size
connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd
connect issue_slots[20].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable
connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause
connect issue_slots[20].in_uop.bits.exception, issue_slots[23].out_uop.exception
connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst
connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy
connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy
connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy
connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy
connect issue_slots[20].in_uop.bits.ppred, issue_slots[23].out_uop.ppred
connect issue_slots[20].in_uop.bits.prs3, issue_slots[23].out_uop.prs3
connect issue_slots[20].in_uop.bits.prs2, issue_slots[23].out_uop.prs2
connect issue_slots[20].in_uop.bits.prs1, issue_slots[23].out_uop.prs1
connect issue_slots[20].in_uop.bits.pdst, issue_slots[23].out_uop.pdst
connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx
connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx
connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx
connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx
connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr
connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed
connect issue_slots[20].in_uop.bits.taken, issue_slots[23].out_uop.taken
connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob
connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst
connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx
connect issue_slots[20].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag
connect issue_slots[20].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask
connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb
connect issue_slots[20].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal
connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr
connect issue_slots[20].in_uop.bits.is_br, issue_slots[23].out_uop.is_br
connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned
connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned
connect issue_slots[20].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state
connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std
connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta
connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load
connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd
connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw
connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn
connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel
connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel
connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel
connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type
connect issue_slots[20].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code
connect issue_slots[20].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type
connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc
connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc
connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst
connect issue_slots[20].in_uop.bits.inst, issue_slots[23].out_uop.inst
connect issue_slots[20].in_uop.bits.uopc, issue_slots[23].out_uop.uopc
node _issue_slots_20_clear_T = neq(_WIRE_23, UInt<1>(0h0))
connect issue_slots[20].clear, _issue_slots_20_clear_T
connect issue_slots[21].in_uop.valid, UInt<1>(0h0)
connect issue_slots[21].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc
connect issue_slots[21].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc
connect issue_slots[21].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if
connect issue_slots[21].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if
connect issue_slots[21].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if
connect issue_slots[21].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if
connect issue_slots[21].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if
connect issue_slots[21].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single
connect issue_slots[21].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val
connect issue_slots[21].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en
connect issue_slots[21].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype
connect issue_slots[21].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype
connect issue_slots[21].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype
connect issue_slots[21].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val
connect issue_slots[21].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3
connect issue_slots[21].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2
connect issue_slots[21].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1
connect issue_slots[21].in_uop.bits.ldst, issue_slots[22].out_uop.ldst
connect issue_slots[21].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1
connect issue_slots[21].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit
connect issue_slots[21].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique
connect issue_slots[21].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc
connect issue_slots[21].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq
connect issue_slots[21].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq
connect issue_slots[21].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo
connect issue_slots[21].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei
connect issue_slots[21].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence
connect issue_slots[21].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed
connect issue_slots[21].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size
connect issue_slots[21].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd
connect issue_slots[21].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable
connect issue_slots[21].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause
connect issue_slots[21].in_uop.bits.exception, issue_slots[22].out_uop.exception
connect issue_slots[21].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst
connect issue_slots[21].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy
connect issue_slots[21].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy
connect issue_slots[21].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy
connect issue_slots[21].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy
connect issue_slots[21].in_uop.bits.ppred, issue_slots[22].out_uop.ppred
connect issue_slots[21].in_uop.bits.prs3, issue_slots[22].out_uop.prs3
connect issue_slots[21].in_uop.bits.prs2, issue_slots[22].out_uop.prs2
connect issue_slots[21].in_uop.bits.prs1, issue_slots[22].out_uop.prs1
connect issue_slots[21].in_uop.bits.pdst, issue_slots[22].out_uop.pdst
connect issue_slots[21].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx
connect issue_slots[21].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx
connect issue_slots[21].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx
connect issue_slots[21].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx
connect issue_slots[21].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr
connect issue_slots[21].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed
connect issue_slots[21].in_uop.bits.taken, issue_slots[22].out_uop.taken
connect issue_slots[21].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob
connect issue_slots[21].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst
connect issue_slots[21].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx
connect issue_slots[21].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag
connect issue_slots[21].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask
connect issue_slots[21].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb
connect issue_slots[21].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal
connect issue_slots[21].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr
connect issue_slots[21].in_uop.bits.is_br, issue_slots[22].out_uop.is_br
connect issue_slots[21].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned
connect issue_slots[21].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned
connect issue_slots[21].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state
connect issue_slots[21].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std
connect issue_slots[21].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta
connect issue_slots[21].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load
connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd
connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw
connect issue_slots[21].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn
connect issue_slots[21].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel
connect issue_slots[21].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel
connect issue_slots[21].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel
connect issue_slots[21].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type
connect issue_slots[21].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code
connect issue_slots[21].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type
connect issue_slots[21].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc
connect issue_slots[21].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc
connect issue_slots[21].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst
connect issue_slots[21].in_uop.bits.inst, issue_slots[22].out_uop.inst
connect issue_slots[21].in_uop.bits.uopc, issue_slots[22].out_uop.uopc
node _T_261 = eq(_WIRE_25, UInt<1>(0h1))
when _T_261 :
connect issue_slots[21].in_uop.valid, issue_slots[22].will_be_valid
connect issue_slots[21].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc
connect issue_slots[21].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc
connect issue_slots[21].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if
connect issue_slots[21].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if
connect issue_slots[21].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if
connect issue_slots[21].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if
connect issue_slots[21].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if
connect issue_slots[21].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single
connect issue_slots[21].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val
connect issue_slots[21].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en
connect issue_slots[21].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype
connect issue_slots[21].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype
connect issue_slots[21].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype
connect issue_slots[21].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val
connect issue_slots[21].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3
connect issue_slots[21].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2
connect issue_slots[21].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1
connect issue_slots[21].in_uop.bits.ldst, issue_slots[22].out_uop.ldst
connect issue_slots[21].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1
connect issue_slots[21].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit
connect issue_slots[21].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique
connect issue_slots[21].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc
connect issue_slots[21].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq
connect issue_slots[21].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq
connect issue_slots[21].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo
connect issue_slots[21].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei
connect issue_slots[21].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence
connect issue_slots[21].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed
connect issue_slots[21].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size
connect issue_slots[21].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd
connect issue_slots[21].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable
connect issue_slots[21].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause
connect issue_slots[21].in_uop.bits.exception, issue_slots[22].out_uop.exception
connect issue_slots[21].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst
connect issue_slots[21].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy
connect issue_slots[21].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy
connect issue_slots[21].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy
connect issue_slots[21].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy
connect issue_slots[21].in_uop.bits.ppred, issue_slots[22].out_uop.ppred
connect issue_slots[21].in_uop.bits.prs3, issue_slots[22].out_uop.prs3
connect issue_slots[21].in_uop.bits.prs2, issue_slots[22].out_uop.prs2
connect issue_slots[21].in_uop.bits.prs1, issue_slots[22].out_uop.prs1
connect issue_slots[21].in_uop.bits.pdst, issue_slots[22].out_uop.pdst
connect issue_slots[21].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx
connect issue_slots[21].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx
connect issue_slots[21].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx
connect issue_slots[21].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx
connect issue_slots[21].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr
connect issue_slots[21].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed
connect issue_slots[21].in_uop.bits.taken, issue_slots[22].out_uop.taken
connect issue_slots[21].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob
connect issue_slots[21].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst
connect issue_slots[21].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx
connect issue_slots[21].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag
connect issue_slots[21].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask
connect issue_slots[21].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb
connect issue_slots[21].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal
connect issue_slots[21].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr
connect issue_slots[21].in_uop.bits.is_br, issue_slots[22].out_uop.is_br
connect issue_slots[21].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned
connect issue_slots[21].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned
connect issue_slots[21].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state
connect issue_slots[21].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std
connect issue_slots[21].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta
connect issue_slots[21].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load
connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd
connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw
connect issue_slots[21].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn
connect issue_slots[21].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel
connect issue_slots[21].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel
connect issue_slots[21].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel
connect issue_slots[21].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type
connect issue_slots[21].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code
connect issue_slots[21].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type
connect issue_slots[21].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc
connect issue_slots[21].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc
connect issue_slots[21].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst
connect issue_slots[21].in_uop.bits.inst, issue_slots[22].out_uop.inst
connect issue_slots[21].in_uop.bits.uopc, issue_slots[22].out_uop.uopc
node _T_262 = eq(_WIRE_26, UInt<2>(0h2))
when _T_262 :
connect issue_slots[21].in_uop.valid, issue_slots[23].will_be_valid
connect issue_slots[21].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc
connect issue_slots[21].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc
connect issue_slots[21].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if
connect issue_slots[21].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if
connect issue_slots[21].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if
connect issue_slots[21].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if
connect issue_slots[21].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if
connect issue_slots[21].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single
connect issue_slots[21].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val
connect issue_slots[21].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en
connect issue_slots[21].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype
connect issue_slots[21].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype
connect issue_slots[21].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype
connect issue_slots[21].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val
connect issue_slots[21].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3
connect issue_slots[21].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2
connect issue_slots[21].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1
connect issue_slots[21].in_uop.bits.ldst, issue_slots[23].out_uop.ldst
connect issue_slots[21].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1
connect issue_slots[21].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit
connect issue_slots[21].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique
connect issue_slots[21].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc
connect issue_slots[21].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq
connect issue_slots[21].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq
connect issue_slots[21].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo
connect issue_slots[21].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei
connect issue_slots[21].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence
connect issue_slots[21].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed
connect issue_slots[21].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size
connect issue_slots[21].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd
connect issue_slots[21].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable
connect issue_slots[21].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause
connect issue_slots[21].in_uop.bits.exception, issue_slots[23].out_uop.exception
connect issue_slots[21].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst
connect issue_slots[21].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy
connect issue_slots[21].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy
connect issue_slots[21].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy
connect issue_slots[21].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy
connect issue_slots[21].in_uop.bits.ppred, issue_slots[23].out_uop.ppred
connect issue_slots[21].in_uop.bits.prs3, issue_slots[23].out_uop.prs3
connect issue_slots[21].in_uop.bits.prs2, issue_slots[23].out_uop.prs2
connect issue_slots[21].in_uop.bits.prs1, issue_slots[23].out_uop.prs1
connect issue_slots[21].in_uop.bits.pdst, issue_slots[23].out_uop.pdst
connect issue_slots[21].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx
connect issue_slots[21].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx
connect issue_slots[21].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx
connect issue_slots[21].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx
connect issue_slots[21].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr
connect issue_slots[21].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed
connect issue_slots[21].in_uop.bits.taken, issue_slots[23].out_uop.taken
connect issue_slots[21].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob
connect issue_slots[21].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst
connect issue_slots[21].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx
connect issue_slots[21].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag
connect issue_slots[21].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask
connect issue_slots[21].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb
connect issue_slots[21].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal
connect issue_slots[21].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr
connect issue_slots[21].in_uop.bits.is_br, issue_slots[23].out_uop.is_br
connect issue_slots[21].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned
connect issue_slots[21].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned
connect issue_slots[21].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state
connect issue_slots[21].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std
connect issue_slots[21].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta
connect issue_slots[21].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load
connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd
connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw
connect issue_slots[21].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn
connect issue_slots[21].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel
connect issue_slots[21].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel
connect issue_slots[21].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel
connect issue_slots[21].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type
connect issue_slots[21].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code
connect issue_slots[21].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type
connect issue_slots[21].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc
connect issue_slots[21].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc
connect issue_slots[21].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst
connect issue_slots[21].in_uop.bits.inst, issue_slots[23].out_uop.inst
connect issue_slots[21].in_uop.bits.uopc, issue_slots[23].out_uop.uopc
node _T_263 = eq(_WIRE_27, UInt<3>(0h4))
when _T_263 :
connect issue_slots[21].in_uop.valid, will_be_valid_24
connect issue_slots[21].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[21].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[21].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[21].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[21].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[21].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[21].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[21].in_uop.bits.fp_single, _WIRE.fp_single
connect issue_slots[21].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[21].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[21].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[21].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[21].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[21].in_uop.bits.ldst_val, _WIRE.ldst_val
connect issue_slots[21].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[21].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[21].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[21].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[21].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[21].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[21].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[21].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[21].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[21].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[21].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[21].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[21].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[21].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[21].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[21].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[21].in_uop.bits.bypassable, _WIRE.bypassable
connect issue_slots[21].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[21].in_uop.bits.exception, _WIRE.exception
connect issue_slots[21].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[21].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[21].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[21].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[21].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[21].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[21].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[21].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[21].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[21].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[21].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[21].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[21].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[21].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[21].in_uop.bits.csr_addr, _WIRE.csr_addr
connect issue_slots[21].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[21].in_uop.bits.taken, _WIRE.taken
connect issue_slots[21].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[21].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[21].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[21].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[21].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[21].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[21].in_uop.bits.is_jal, _WIRE.is_jal
connect issue_slots[21].in_uop.bits.is_jalr, _WIRE.is_jalr
connect issue_slots[21].in_uop.bits.is_br, _WIRE.is_br
connect issue_slots[21].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned
connect issue_slots[21].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned
connect issue_slots[21].in_uop.bits.iw_state, _WIRE.iw_state
connect issue_slots[21].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std
connect issue_slots[21].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta
connect issue_slots[21].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load
connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd
connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw
connect issue_slots[21].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn
connect issue_slots[21].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel
connect issue_slots[21].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel
connect issue_slots[21].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel
connect issue_slots[21].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type
connect issue_slots[21].in_uop.bits.fu_code, _WIRE.fu_code
connect issue_slots[21].in_uop.bits.iq_type, _WIRE.iq_type
connect issue_slots[21].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[21].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[21].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[21].in_uop.bits.inst, _WIRE.inst
connect issue_slots[21].in_uop.bits.uopc, _WIRE.uopc
node _issue_slots_21_clear_T = neq(_WIRE_24, UInt<1>(0h0))
connect issue_slots[21].clear, _issue_slots_21_clear_T
connect issue_slots[22].in_uop.valid, UInt<1>(0h0)
connect issue_slots[22].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc
connect issue_slots[22].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc
connect issue_slots[22].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if
connect issue_slots[22].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if
connect issue_slots[22].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if
connect issue_slots[22].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if
connect issue_slots[22].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if
connect issue_slots[22].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single
connect issue_slots[22].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val
connect issue_slots[22].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en
connect issue_slots[22].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype
connect issue_slots[22].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype
connect issue_slots[22].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype
connect issue_slots[22].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val
connect issue_slots[22].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3
connect issue_slots[22].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2
connect issue_slots[22].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1
connect issue_slots[22].in_uop.bits.ldst, issue_slots[23].out_uop.ldst
connect issue_slots[22].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1
connect issue_slots[22].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit
connect issue_slots[22].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique
connect issue_slots[22].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc
connect issue_slots[22].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq
connect issue_slots[22].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq
connect issue_slots[22].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo
connect issue_slots[22].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei
connect issue_slots[22].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence
connect issue_slots[22].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed
connect issue_slots[22].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size
connect issue_slots[22].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd
connect issue_slots[22].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable
connect issue_slots[22].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause
connect issue_slots[22].in_uop.bits.exception, issue_slots[23].out_uop.exception
connect issue_slots[22].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst
connect issue_slots[22].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy
connect issue_slots[22].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy
connect issue_slots[22].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy
connect issue_slots[22].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy
connect issue_slots[22].in_uop.bits.ppred, issue_slots[23].out_uop.ppred
connect issue_slots[22].in_uop.bits.prs3, issue_slots[23].out_uop.prs3
connect issue_slots[22].in_uop.bits.prs2, issue_slots[23].out_uop.prs2
connect issue_slots[22].in_uop.bits.prs1, issue_slots[23].out_uop.prs1
connect issue_slots[22].in_uop.bits.pdst, issue_slots[23].out_uop.pdst
connect issue_slots[22].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx
connect issue_slots[22].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx
connect issue_slots[22].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx
connect issue_slots[22].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx
connect issue_slots[22].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr
connect issue_slots[22].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed
connect issue_slots[22].in_uop.bits.taken, issue_slots[23].out_uop.taken
connect issue_slots[22].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob
connect issue_slots[22].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst
connect issue_slots[22].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx
connect issue_slots[22].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag
connect issue_slots[22].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask
connect issue_slots[22].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb
connect issue_slots[22].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal
connect issue_slots[22].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr
connect issue_slots[22].in_uop.bits.is_br, issue_slots[23].out_uop.is_br
connect issue_slots[22].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned
connect issue_slots[22].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned
connect issue_slots[22].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state
connect issue_slots[22].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std
connect issue_slots[22].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta
connect issue_slots[22].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load
connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd
connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw
connect issue_slots[22].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn
connect issue_slots[22].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel
connect issue_slots[22].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel
connect issue_slots[22].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel
connect issue_slots[22].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type
connect issue_slots[22].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code
connect issue_slots[22].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type
connect issue_slots[22].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc
connect issue_slots[22].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc
connect issue_slots[22].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst
connect issue_slots[22].in_uop.bits.inst, issue_slots[23].out_uop.inst
connect issue_slots[22].in_uop.bits.uopc, issue_slots[23].out_uop.uopc
node _T_264 = eq(_WIRE_26, UInt<1>(0h1))
when _T_264 :
connect issue_slots[22].in_uop.valid, issue_slots[23].will_be_valid
connect issue_slots[22].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc
connect issue_slots[22].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc
connect issue_slots[22].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if
connect issue_slots[22].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if
connect issue_slots[22].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if
connect issue_slots[22].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if
connect issue_slots[22].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if
connect issue_slots[22].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single
connect issue_slots[22].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val
connect issue_slots[22].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en
connect issue_slots[22].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype
connect issue_slots[22].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype
connect issue_slots[22].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype
connect issue_slots[22].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val
connect issue_slots[22].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3
connect issue_slots[22].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2
connect issue_slots[22].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1
connect issue_slots[22].in_uop.bits.ldst, issue_slots[23].out_uop.ldst
connect issue_slots[22].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1
connect issue_slots[22].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit
connect issue_slots[22].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique
connect issue_slots[22].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc
connect issue_slots[22].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq
connect issue_slots[22].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq
connect issue_slots[22].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo
connect issue_slots[22].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei
connect issue_slots[22].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence
connect issue_slots[22].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed
connect issue_slots[22].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size
connect issue_slots[22].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd
connect issue_slots[22].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable
connect issue_slots[22].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause
connect issue_slots[22].in_uop.bits.exception, issue_slots[23].out_uop.exception
connect issue_slots[22].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst
connect issue_slots[22].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy
connect issue_slots[22].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy
connect issue_slots[22].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy
connect issue_slots[22].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy
connect issue_slots[22].in_uop.bits.ppred, issue_slots[23].out_uop.ppred
connect issue_slots[22].in_uop.bits.prs3, issue_slots[23].out_uop.prs3
connect issue_slots[22].in_uop.bits.prs2, issue_slots[23].out_uop.prs2
connect issue_slots[22].in_uop.bits.prs1, issue_slots[23].out_uop.prs1
connect issue_slots[22].in_uop.bits.pdst, issue_slots[23].out_uop.pdst
connect issue_slots[22].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx
connect issue_slots[22].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx
connect issue_slots[22].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx
connect issue_slots[22].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx
connect issue_slots[22].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr
connect issue_slots[22].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed
connect issue_slots[22].in_uop.bits.taken, issue_slots[23].out_uop.taken
connect issue_slots[22].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob
connect issue_slots[22].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst
connect issue_slots[22].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx
connect issue_slots[22].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag
connect issue_slots[22].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask
connect issue_slots[22].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb
connect issue_slots[22].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal
connect issue_slots[22].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr
connect issue_slots[22].in_uop.bits.is_br, issue_slots[23].out_uop.is_br
connect issue_slots[22].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned
connect issue_slots[22].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned
connect issue_slots[22].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state
connect issue_slots[22].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std
connect issue_slots[22].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta
connect issue_slots[22].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load
connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd
connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw
connect issue_slots[22].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn
connect issue_slots[22].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel
connect issue_slots[22].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel
connect issue_slots[22].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel
connect issue_slots[22].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type
connect issue_slots[22].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code
connect issue_slots[22].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type
connect issue_slots[22].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc
connect issue_slots[22].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc
connect issue_slots[22].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst
connect issue_slots[22].in_uop.bits.inst, issue_slots[23].out_uop.inst
connect issue_slots[22].in_uop.bits.uopc, issue_slots[23].out_uop.uopc
node _T_265 = eq(_WIRE_27, UInt<2>(0h2))
when _T_265 :
connect issue_slots[22].in_uop.valid, will_be_valid_24
connect issue_slots[22].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[22].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[22].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[22].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[22].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[22].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[22].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[22].in_uop.bits.fp_single, _WIRE.fp_single
connect issue_slots[22].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[22].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[22].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[22].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[22].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[22].in_uop.bits.ldst_val, _WIRE.ldst_val
connect issue_slots[22].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[22].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[22].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[22].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[22].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[22].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[22].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[22].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[22].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[22].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[22].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[22].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[22].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[22].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[22].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[22].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[22].in_uop.bits.bypassable, _WIRE.bypassable
connect issue_slots[22].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[22].in_uop.bits.exception, _WIRE.exception
connect issue_slots[22].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[22].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[22].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[22].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[22].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[22].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[22].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[22].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[22].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[22].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[22].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[22].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[22].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[22].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[22].in_uop.bits.csr_addr, _WIRE.csr_addr
connect issue_slots[22].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[22].in_uop.bits.taken, _WIRE.taken
connect issue_slots[22].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[22].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[22].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[22].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[22].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[22].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[22].in_uop.bits.is_jal, _WIRE.is_jal
connect issue_slots[22].in_uop.bits.is_jalr, _WIRE.is_jalr
connect issue_slots[22].in_uop.bits.is_br, _WIRE.is_br
connect issue_slots[22].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned
connect issue_slots[22].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned
connect issue_slots[22].in_uop.bits.iw_state, _WIRE.iw_state
connect issue_slots[22].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std
connect issue_slots[22].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta
connect issue_slots[22].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load
connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd
connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw
connect issue_slots[22].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn
connect issue_slots[22].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel
connect issue_slots[22].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel
connect issue_slots[22].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel
connect issue_slots[22].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type
connect issue_slots[22].in_uop.bits.fu_code, _WIRE.fu_code
connect issue_slots[22].in_uop.bits.iq_type, _WIRE.iq_type
connect issue_slots[22].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[22].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[22].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[22].in_uop.bits.inst, _WIRE.inst
connect issue_slots[22].in_uop.bits.uopc, _WIRE.uopc
node _T_266 = eq(_WIRE_28, UInt<3>(0h4))
when _T_266 :
connect issue_slots[22].in_uop.valid, will_be_valid_25
connect issue_slots[22].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc
connect issue_slots[22].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc
connect issue_slots[22].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if
connect issue_slots[22].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if
connect issue_slots[22].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if
connect issue_slots[22].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if
connect issue_slots[22].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if
connect issue_slots[22].in_uop.bits.fp_single, _WIRE_1.fp_single
connect issue_slots[22].in_uop.bits.fp_val, _WIRE_1.fp_val
connect issue_slots[22].in_uop.bits.frs3_en, _WIRE_1.frs3_en
connect issue_slots[22].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype
connect issue_slots[22].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype
connect issue_slots[22].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype
connect issue_slots[22].in_uop.bits.ldst_val, _WIRE_1.ldst_val
connect issue_slots[22].in_uop.bits.lrs3, _WIRE_1.lrs3
connect issue_slots[22].in_uop.bits.lrs2, _WIRE_1.lrs2
connect issue_slots[22].in_uop.bits.lrs1, _WIRE_1.lrs1
connect issue_slots[22].in_uop.bits.ldst, _WIRE_1.ldst
connect issue_slots[22].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1
connect issue_slots[22].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit
connect issue_slots[22].in_uop.bits.is_unique, _WIRE_1.is_unique
connect issue_slots[22].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc
connect issue_slots[22].in_uop.bits.uses_stq, _WIRE_1.uses_stq
connect issue_slots[22].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq
connect issue_slots[22].in_uop.bits.is_amo, _WIRE_1.is_amo
connect issue_slots[22].in_uop.bits.is_fencei, _WIRE_1.is_fencei
connect issue_slots[22].in_uop.bits.is_fence, _WIRE_1.is_fence
connect issue_slots[22].in_uop.bits.mem_signed, _WIRE_1.mem_signed
connect issue_slots[22].in_uop.bits.mem_size, _WIRE_1.mem_size
connect issue_slots[22].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd
connect issue_slots[22].in_uop.bits.bypassable, _WIRE_1.bypassable
connect issue_slots[22].in_uop.bits.exc_cause, _WIRE_1.exc_cause
connect issue_slots[22].in_uop.bits.exception, _WIRE_1.exception
connect issue_slots[22].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst
connect issue_slots[22].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy
connect issue_slots[22].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy
connect issue_slots[22].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy
connect issue_slots[22].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy
connect issue_slots[22].in_uop.bits.ppred, _WIRE_1.ppred
connect issue_slots[22].in_uop.bits.prs3, _WIRE_1.prs3
connect issue_slots[22].in_uop.bits.prs2, _WIRE_1.prs2
connect issue_slots[22].in_uop.bits.prs1, _WIRE_1.prs1
connect issue_slots[22].in_uop.bits.pdst, _WIRE_1.pdst
connect issue_slots[22].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx
connect issue_slots[22].in_uop.bits.stq_idx, _WIRE_1.stq_idx
connect issue_slots[22].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx
connect issue_slots[22].in_uop.bits.rob_idx, _WIRE_1.rob_idx
connect issue_slots[22].in_uop.bits.csr_addr, _WIRE_1.csr_addr
connect issue_slots[22].in_uop.bits.imm_packed, _WIRE_1.imm_packed
connect issue_slots[22].in_uop.bits.taken, _WIRE_1.taken
connect issue_slots[22].in_uop.bits.pc_lob, _WIRE_1.pc_lob
connect issue_slots[22].in_uop.bits.edge_inst, _WIRE_1.edge_inst
connect issue_slots[22].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx
connect issue_slots[22].in_uop.bits.br_tag, _WIRE_1.br_tag
connect issue_slots[22].in_uop.bits.br_mask, _WIRE_1.br_mask
connect issue_slots[22].in_uop.bits.is_sfb, _WIRE_1.is_sfb
connect issue_slots[22].in_uop.bits.is_jal, _WIRE_1.is_jal
connect issue_slots[22].in_uop.bits.is_jalr, _WIRE_1.is_jalr
connect issue_slots[22].in_uop.bits.is_br, _WIRE_1.is_br
connect issue_slots[22].in_uop.bits.iw_p2_poisoned, _WIRE_1.iw_p2_poisoned
connect issue_slots[22].in_uop.bits.iw_p1_poisoned, _WIRE_1.iw_p1_poisoned
connect issue_slots[22].in_uop.bits.iw_state, _WIRE_1.iw_state
connect issue_slots[22].in_uop.bits.ctrl.is_std, _WIRE_1.ctrl.is_std
connect issue_slots[22].in_uop.bits.ctrl.is_sta, _WIRE_1.ctrl.is_sta
connect issue_slots[22].in_uop.bits.ctrl.is_load, _WIRE_1.ctrl.is_load
connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, _WIRE_1.ctrl.csr_cmd
connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, _WIRE_1.ctrl.fcn_dw
connect issue_slots[22].in_uop.bits.ctrl.op_fcn, _WIRE_1.ctrl.op_fcn
connect issue_slots[22].in_uop.bits.ctrl.imm_sel, _WIRE_1.ctrl.imm_sel
connect issue_slots[22].in_uop.bits.ctrl.op2_sel, _WIRE_1.ctrl.op2_sel
connect issue_slots[22].in_uop.bits.ctrl.op1_sel, _WIRE_1.ctrl.op1_sel
connect issue_slots[22].in_uop.bits.ctrl.br_type, _WIRE_1.ctrl.br_type
connect issue_slots[22].in_uop.bits.fu_code, _WIRE_1.fu_code
connect issue_slots[22].in_uop.bits.iq_type, _WIRE_1.iq_type
connect issue_slots[22].in_uop.bits.debug_pc, _WIRE_1.debug_pc
connect issue_slots[22].in_uop.bits.is_rvc, _WIRE_1.is_rvc
connect issue_slots[22].in_uop.bits.debug_inst, _WIRE_1.debug_inst
connect issue_slots[22].in_uop.bits.inst, _WIRE_1.inst
connect issue_slots[22].in_uop.bits.uopc, _WIRE_1.uopc
node _issue_slots_22_clear_T = neq(_WIRE_25, UInt<1>(0h0))
connect issue_slots[22].clear, _issue_slots_22_clear_T
connect issue_slots[23].in_uop.valid, UInt<1>(0h0)
connect issue_slots[23].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[23].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[23].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[23].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[23].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[23].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[23].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[23].in_uop.bits.fp_single, _WIRE.fp_single
connect issue_slots[23].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[23].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[23].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[23].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[23].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[23].in_uop.bits.ldst_val, _WIRE.ldst_val
connect issue_slots[23].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[23].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[23].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[23].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[23].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[23].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[23].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[23].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[23].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[23].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[23].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[23].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[23].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[23].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[23].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[23].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[23].in_uop.bits.bypassable, _WIRE.bypassable
connect issue_slots[23].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[23].in_uop.bits.exception, _WIRE.exception
connect issue_slots[23].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[23].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[23].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[23].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[23].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[23].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[23].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[23].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[23].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[23].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[23].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[23].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[23].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[23].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[23].in_uop.bits.csr_addr, _WIRE.csr_addr
connect issue_slots[23].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[23].in_uop.bits.taken, _WIRE.taken
connect issue_slots[23].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[23].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[23].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[23].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[23].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[23].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[23].in_uop.bits.is_jal, _WIRE.is_jal
connect issue_slots[23].in_uop.bits.is_jalr, _WIRE.is_jalr
connect issue_slots[23].in_uop.bits.is_br, _WIRE.is_br
connect issue_slots[23].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned
connect issue_slots[23].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned
connect issue_slots[23].in_uop.bits.iw_state, _WIRE.iw_state
connect issue_slots[23].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std
connect issue_slots[23].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta
connect issue_slots[23].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load
connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd
connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw
connect issue_slots[23].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn
connect issue_slots[23].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel
connect issue_slots[23].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel
connect issue_slots[23].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel
connect issue_slots[23].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type
connect issue_slots[23].in_uop.bits.fu_code, _WIRE.fu_code
connect issue_slots[23].in_uop.bits.iq_type, _WIRE.iq_type
connect issue_slots[23].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[23].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[23].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[23].in_uop.bits.inst, _WIRE.inst
connect issue_slots[23].in_uop.bits.uopc, _WIRE.uopc
node _T_267 = eq(_WIRE_27, UInt<1>(0h1))
when _T_267 :
connect issue_slots[23].in_uop.valid, will_be_valid_24
connect issue_slots[23].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[23].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[23].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[23].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[23].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[23].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[23].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[23].in_uop.bits.fp_single, _WIRE.fp_single
connect issue_slots[23].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[23].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[23].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[23].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[23].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[23].in_uop.bits.ldst_val, _WIRE.ldst_val
connect issue_slots[23].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[23].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[23].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[23].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[23].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[23].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[23].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[23].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[23].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[23].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[23].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[23].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[23].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[23].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[23].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[23].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[23].in_uop.bits.bypassable, _WIRE.bypassable
connect issue_slots[23].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[23].in_uop.bits.exception, _WIRE.exception
connect issue_slots[23].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[23].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[23].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[23].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[23].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[23].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[23].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[23].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[23].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[23].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[23].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[23].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[23].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[23].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[23].in_uop.bits.csr_addr, _WIRE.csr_addr
connect issue_slots[23].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[23].in_uop.bits.taken, _WIRE.taken
connect issue_slots[23].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[23].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[23].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[23].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[23].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[23].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[23].in_uop.bits.is_jal, _WIRE.is_jal
connect issue_slots[23].in_uop.bits.is_jalr, _WIRE.is_jalr
connect issue_slots[23].in_uop.bits.is_br, _WIRE.is_br
connect issue_slots[23].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned
connect issue_slots[23].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned
connect issue_slots[23].in_uop.bits.iw_state, _WIRE.iw_state
connect issue_slots[23].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std
connect issue_slots[23].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta
connect issue_slots[23].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load
connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd
connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw
connect issue_slots[23].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn
connect issue_slots[23].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel
connect issue_slots[23].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel
connect issue_slots[23].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel
connect issue_slots[23].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type
connect issue_slots[23].in_uop.bits.fu_code, _WIRE.fu_code
connect issue_slots[23].in_uop.bits.iq_type, _WIRE.iq_type
connect issue_slots[23].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[23].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[23].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[23].in_uop.bits.inst, _WIRE.inst
connect issue_slots[23].in_uop.bits.uopc, _WIRE.uopc
node _T_268 = eq(_WIRE_28, UInt<2>(0h2))
when _T_268 :
connect issue_slots[23].in_uop.valid, will_be_valid_25
connect issue_slots[23].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc
connect issue_slots[23].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc
connect issue_slots[23].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if
connect issue_slots[23].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if
connect issue_slots[23].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if
connect issue_slots[23].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if
connect issue_slots[23].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if
connect issue_slots[23].in_uop.bits.fp_single, _WIRE_1.fp_single
connect issue_slots[23].in_uop.bits.fp_val, _WIRE_1.fp_val
connect issue_slots[23].in_uop.bits.frs3_en, _WIRE_1.frs3_en
connect issue_slots[23].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype
connect issue_slots[23].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype
connect issue_slots[23].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype
connect issue_slots[23].in_uop.bits.ldst_val, _WIRE_1.ldst_val
connect issue_slots[23].in_uop.bits.lrs3, _WIRE_1.lrs3
connect issue_slots[23].in_uop.bits.lrs2, _WIRE_1.lrs2
connect issue_slots[23].in_uop.bits.lrs1, _WIRE_1.lrs1
connect issue_slots[23].in_uop.bits.ldst, _WIRE_1.ldst
connect issue_slots[23].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1
connect issue_slots[23].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit
connect issue_slots[23].in_uop.bits.is_unique, _WIRE_1.is_unique
connect issue_slots[23].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc
connect issue_slots[23].in_uop.bits.uses_stq, _WIRE_1.uses_stq
connect issue_slots[23].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq
connect issue_slots[23].in_uop.bits.is_amo, _WIRE_1.is_amo
connect issue_slots[23].in_uop.bits.is_fencei, _WIRE_1.is_fencei
connect issue_slots[23].in_uop.bits.is_fence, _WIRE_1.is_fence
connect issue_slots[23].in_uop.bits.mem_signed, _WIRE_1.mem_signed
connect issue_slots[23].in_uop.bits.mem_size, _WIRE_1.mem_size
connect issue_slots[23].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd
connect issue_slots[23].in_uop.bits.bypassable, _WIRE_1.bypassable
connect issue_slots[23].in_uop.bits.exc_cause, _WIRE_1.exc_cause
connect issue_slots[23].in_uop.bits.exception, _WIRE_1.exception
connect issue_slots[23].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst
connect issue_slots[23].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy
connect issue_slots[23].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy
connect issue_slots[23].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy
connect issue_slots[23].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy
connect issue_slots[23].in_uop.bits.ppred, _WIRE_1.ppred
connect issue_slots[23].in_uop.bits.prs3, _WIRE_1.prs3
connect issue_slots[23].in_uop.bits.prs2, _WIRE_1.prs2
connect issue_slots[23].in_uop.bits.prs1, _WIRE_1.prs1
connect issue_slots[23].in_uop.bits.pdst, _WIRE_1.pdst
connect issue_slots[23].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx
connect issue_slots[23].in_uop.bits.stq_idx, _WIRE_1.stq_idx
connect issue_slots[23].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx
connect issue_slots[23].in_uop.bits.rob_idx, _WIRE_1.rob_idx
connect issue_slots[23].in_uop.bits.csr_addr, _WIRE_1.csr_addr
connect issue_slots[23].in_uop.bits.imm_packed, _WIRE_1.imm_packed
connect issue_slots[23].in_uop.bits.taken, _WIRE_1.taken
connect issue_slots[23].in_uop.bits.pc_lob, _WIRE_1.pc_lob
connect issue_slots[23].in_uop.bits.edge_inst, _WIRE_1.edge_inst
connect issue_slots[23].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx
connect issue_slots[23].in_uop.bits.br_tag, _WIRE_1.br_tag
connect issue_slots[23].in_uop.bits.br_mask, _WIRE_1.br_mask
connect issue_slots[23].in_uop.bits.is_sfb, _WIRE_1.is_sfb
connect issue_slots[23].in_uop.bits.is_jal, _WIRE_1.is_jal
connect issue_slots[23].in_uop.bits.is_jalr, _WIRE_1.is_jalr
connect issue_slots[23].in_uop.bits.is_br, _WIRE_1.is_br
connect issue_slots[23].in_uop.bits.iw_p2_poisoned, _WIRE_1.iw_p2_poisoned
connect issue_slots[23].in_uop.bits.iw_p1_poisoned, _WIRE_1.iw_p1_poisoned
connect issue_slots[23].in_uop.bits.iw_state, _WIRE_1.iw_state
connect issue_slots[23].in_uop.bits.ctrl.is_std, _WIRE_1.ctrl.is_std
connect issue_slots[23].in_uop.bits.ctrl.is_sta, _WIRE_1.ctrl.is_sta
connect issue_slots[23].in_uop.bits.ctrl.is_load, _WIRE_1.ctrl.is_load
connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, _WIRE_1.ctrl.csr_cmd
connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, _WIRE_1.ctrl.fcn_dw
connect issue_slots[23].in_uop.bits.ctrl.op_fcn, _WIRE_1.ctrl.op_fcn
connect issue_slots[23].in_uop.bits.ctrl.imm_sel, _WIRE_1.ctrl.imm_sel
connect issue_slots[23].in_uop.bits.ctrl.op2_sel, _WIRE_1.ctrl.op2_sel
connect issue_slots[23].in_uop.bits.ctrl.op1_sel, _WIRE_1.ctrl.op1_sel
connect issue_slots[23].in_uop.bits.ctrl.br_type, _WIRE_1.ctrl.br_type
connect issue_slots[23].in_uop.bits.fu_code, _WIRE_1.fu_code
connect issue_slots[23].in_uop.bits.iq_type, _WIRE_1.iq_type
connect issue_slots[23].in_uop.bits.debug_pc, _WIRE_1.debug_pc
connect issue_slots[23].in_uop.bits.is_rvc, _WIRE_1.is_rvc
connect issue_slots[23].in_uop.bits.debug_inst, _WIRE_1.debug_inst
connect issue_slots[23].in_uop.bits.inst, _WIRE_1.inst
connect issue_slots[23].in_uop.bits.uopc, _WIRE_1.uopc
node _T_269 = eq(_WIRE_29, UInt<3>(0h4))
when _T_269 :
connect issue_slots[23].in_uop.valid, will_be_valid_26
connect issue_slots[23].in_uop.bits.debug_tsrc, _WIRE_2.debug_tsrc
connect issue_slots[23].in_uop.bits.debug_fsrc, _WIRE_2.debug_fsrc
connect issue_slots[23].in_uop.bits.bp_xcpt_if, _WIRE_2.bp_xcpt_if
connect issue_slots[23].in_uop.bits.bp_debug_if, _WIRE_2.bp_debug_if
connect issue_slots[23].in_uop.bits.xcpt_ma_if, _WIRE_2.xcpt_ma_if
connect issue_slots[23].in_uop.bits.xcpt_ae_if, _WIRE_2.xcpt_ae_if
connect issue_slots[23].in_uop.bits.xcpt_pf_if, _WIRE_2.xcpt_pf_if
connect issue_slots[23].in_uop.bits.fp_single, _WIRE_2.fp_single
connect issue_slots[23].in_uop.bits.fp_val, _WIRE_2.fp_val
connect issue_slots[23].in_uop.bits.frs3_en, _WIRE_2.frs3_en
connect issue_slots[23].in_uop.bits.lrs2_rtype, _WIRE_2.lrs2_rtype
connect issue_slots[23].in_uop.bits.lrs1_rtype, _WIRE_2.lrs1_rtype
connect issue_slots[23].in_uop.bits.dst_rtype, _WIRE_2.dst_rtype
connect issue_slots[23].in_uop.bits.ldst_val, _WIRE_2.ldst_val
connect issue_slots[23].in_uop.bits.lrs3, _WIRE_2.lrs3
connect issue_slots[23].in_uop.bits.lrs2, _WIRE_2.lrs2
connect issue_slots[23].in_uop.bits.lrs1, _WIRE_2.lrs1
connect issue_slots[23].in_uop.bits.ldst, _WIRE_2.ldst
connect issue_slots[23].in_uop.bits.ldst_is_rs1, _WIRE_2.ldst_is_rs1
connect issue_slots[23].in_uop.bits.flush_on_commit, _WIRE_2.flush_on_commit
connect issue_slots[23].in_uop.bits.is_unique, _WIRE_2.is_unique
connect issue_slots[23].in_uop.bits.is_sys_pc2epc, _WIRE_2.is_sys_pc2epc
connect issue_slots[23].in_uop.bits.uses_stq, _WIRE_2.uses_stq
connect issue_slots[23].in_uop.bits.uses_ldq, _WIRE_2.uses_ldq
connect issue_slots[23].in_uop.bits.is_amo, _WIRE_2.is_amo
connect issue_slots[23].in_uop.bits.is_fencei, _WIRE_2.is_fencei
connect issue_slots[23].in_uop.bits.is_fence, _WIRE_2.is_fence
connect issue_slots[23].in_uop.bits.mem_signed, _WIRE_2.mem_signed
connect issue_slots[23].in_uop.bits.mem_size, _WIRE_2.mem_size
connect issue_slots[23].in_uop.bits.mem_cmd, _WIRE_2.mem_cmd
connect issue_slots[23].in_uop.bits.bypassable, _WIRE_2.bypassable
connect issue_slots[23].in_uop.bits.exc_cause, _WIRE_2.exc_cause
connect issue_slots[23].in_uop.bits.exception, _WIRE_2.exception
connect issue_slots[23].in_uop.bits.stale_pdst, _WIRE_2.stale_pdst
connect issue_slots[23].in_uop.bits.ppred_busy, _WIRE_2.ppred_busy
connect issue_slots[23].in_uop.bits.prs3_busy, _WIRE_2.prs3_busy
connect issue_slots[23].in_uop.bits.prs2_busy, _WIRE_2.prs2_busy
connect issue_slots[23].in_uop.bits.prs1_busy, _WIRE_2.prs1_busy
connect issue_slots[23].in_uop.bits.ppred, _WIRE_2.ppred
connect issue_slots[23].in_uop.bits.prs3, _WIRE_2.prs3
connect issue_slots[23].in_uop.bits.prs2, _WIRE_2.prs2
connect issue_slots[23].in_uop.bits.prs1, _WIRE_2.prs1
connect issue_slots[23].in_uop.bits.pdst, _WIRE_2.pdst
connect issue_slots[23].in_uop.bits.rxq_idx, _WIRE_2.rxq_idx
connect issue_slots[23].in_uop.bits.stq_idx, _WIRE_2.stq_idx
connect issue_slots[23].in_uop.bits.ldq_idx, _WIRE_2.ldq_idx
connect issue_slots[23].in_uop.bits.rob_idx, _WIRE_2.rob_idx
connect issue_slots[23].in_uop.bits.csr_addr, _WIRE_2.csr_addr
connect issue_slots[23].in_uop.bits.imm_packed, _WIRE_2.imm_packed
connect issue_slots[23].in_uop.bits.taken, _WIRE_2.taken
connect issue_slots[23].in_uop.bits.pc_lob, _WIRE_2.pc_lob
connect issue_slots[23].in_uop.bits.edge_inst, _WIRE_2.edge_inst
connect issue_slots[23].in_uop.bits.ftq_idx, _WIRE_2.ftq_idx
connect issue_slots[23].in_uop.bits.br_tag, _WIRE_2.br_tag
connect issue_slots[23].in_uop.bits.br_mask, _WIRE_2.br_mask
connect issue_slots[23].in_uop.bits.is_sfb, _WIRE_2.is_sfb
connect issue_slots[23].in_uop.bits.is_jal, _WIRE_2.is_jal
connect issue_slots[23].in_uop.bits.is_jalr, _WIRE_2.is_jalr
connect issue_slots[23].in_uop.bits.is_br, _WIRE_2.is_br
connect issue_slots[23].in_uop.bits.iw_p2_poisoned, _WIRE_2.iw_p2_poisoned
connect issue_slots[23].in_uop.bits.iw_p1_poisoned, _WIRE_2.iw_p1_poisoned
connect issue_slots[23].in_uop.bits.iw_state, _WIRE_2.iw_state
connect issue_slots[23].in_uop.bits.ctrl.is_std, _WIRE_2.ctrl.is_std
connect issue_slots[23].in_uop.bits.ctrl.is_sta, _WIRE_2.ctrl.is_sta
connect issue_slots[23].in_uop.bits.ctrl.is_load, _WIRE_2.ctrl.is_load
connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, _WIRE_2.ctrl.csr_cmd
connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, _WIRE_2.ctrl.fcn_dw
connect issue_slots[23].in_uop.bits.ctrl.op_fcn, _WIRE_2.ctrl.op_fcn
connect issue_slots[23].in_uop.bits.ctrl.imm_sel, _WIRE_2.ctrl.imm_sel
connect issue_slots[23].in_uop.bits.ctrl.op2_sel, _WIRE_2.ctrl.op2_sel
connect issue_slots[23].in_uop.bits.ctrl.op1_sel, _WIRE_2.ctrl.op1_sel
connect issue_slots[23].in_uop.bits.ctrl.br_type, _WIRE_2.ctrl.br_type
connect issue_slots[23].in_uop.bits.fu_code, _WIRE_2.fu_code
connect issue_slots[23].in_uop.bits.iq_type, _WIRE_2.iq_type
connect issue_slots[23].in_uop.bits.debug_pc, _WIRE_2.debug_pc
connect issue_slots[23].in_uop.bits.is_rvc, _WIRE_2.is_rvc
connect issue_slots[23].in_uop.bits.debug_inst, _WIRE_2.debug_inst
connect issue_slots[23].in_uop.bits.inst, _WIRE_2.inst
connect issue_slots[23].in_uop.bits.uopc, _WIRE_2.uopc
node _issue_slots_23_clear_T = neq(_WIRE_26, UInt<1>(0h0))
connect issue_slots[23].clear, _issue_slots_23_clear_T
node _will_be_available_T = eq(issue_slots[0].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_1 = or(_will_be_available_T, issue_slots[0].clear)
node _will_be_available_T_2 = eq(issue_slots[0].in_uop.valid, UInt<1>(0h0))
node will_be_available_0 = and(_will_be_available_T_1, _will_be_available_T_2)
node _will_be_available_T_3 = eq(issue_slots[1].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_4 = or(_will_be_available_T_3, issue_slots[1].clear)
node _will_be_available_T_5 = eq(issue_slots[1].in_uop.valid, UInt<1>(0h0))
node will_be_available_1 = and(_will_be_available_T_4, _will_be_available_T_5)
node _will_be_available_T_6 = eq(issue_slots[2].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_7 = or(_will_be_available_T_6, issue_slots[2].clear)
node _will_be_available_T_8 = eq(issue_slots[2].in_uop.valid, UInt<1>(0h0))
node will_be_available_2 = and(_will_be_available_T_7, _will_be_available_T_8)
node _will_be_available_T_9 = eq(issue_slots[3].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_10 = or(_will_be_available_T_9, issue_slots[3].clear)
node _will_be_available_T_11 = eq(issue_slots[3].in_uop.valid, UInt<1>(0h0))
node will_be_available_3 = and(_will_be_available_T_10, _will_be_available_T_11)
node _will_be_available_T_12 = eq(issue_slots[4].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_13 = or(_will_be_available_T_12, issue_slots[4].clear)
node _will_be_available_T_14 = eq(issue_slots[4].in_uop.valid, UInt<1>(0h0))
node will_be_available_4 = and(_will_be_available_T_13, _will_be_available_T_14)
node _will_be_available_T_15 = eq(issue_slots[5].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_16 = or(_will_be_available_T_15, issue_slots[5].clear)
node _will_be_available_T_17 = eq(issue_slots[5].in_uop.valid, UInt<1>(0h0))
node will_be_available_5 = and(_will_be_available_T_16, _will_be_available_T_17)
node _will_be_available_T_18 = eq(issue_slots[6].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_19 = or(_will_be_available_T_18, issue_slots[6].clear)
node _will_be_available_T_20 = eq(issue_slots[6].in_uop.valid, UInt<1>(0h0))
node will_be_available_6 = and(_will_be_available_T_19, _will_be_available_T_20)
node _will_be_available_T_21 = eq(issue_slots[7].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_22 = or(_will_be_available_T_21, issue_slots[7].clear)
node _will_be_available_T_23 = eq(issue_slots[7].in_uop.valid, UInt<1>(0h0))
node will_be_available_7 = and(_will_be_available_T_22, _will_be_available_T_23)
node _will_be_available_T_24 = eq(issue_slots[8].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_25 = or(_will_be_available_T_24, issue_slots[8].clear)
node _will_be_available_T_26 = eq(issue_slots[8].in_uop.valid, UInt<1>(0h0))
node will_be_available_8 = and(_will_be_available_T_25, _will_be_available_T_26)
node _will_be_available_T_27 = eq(issue_slots[9].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_28 = or(_will_be_available_T_27, issue_slots[9].clear)
node _will_be_available_T_29 = eq(issue_slots[9].in_uop.valid, UInt<1>(0h0))
node will_be_available_9 = and(_will_be_available_T_28, _will_be_available_T_29)
node _will_be_available_T_30 = eq(issue_slots[10].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_31 = or(_will_be_available_T_30, issue_slots[10].clear)
node _will_be_available_T_32 = eq(issue_slots[10].in_uop.valid, UInt<1>(0h0))
node will_be_available_10 = and(_will_be_available_T_31, _will_be_available_T_32)
node _will_be_available_T_33 = eq(issue_slots[11].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_34 = or(_will_be_available_T_33, issue_slots[11].clear)
node _will_be_available_T_35 = eq(issue_slots[11].in_uop.valid, UInt<1>(0h0))
node will_be_available_11 = and(_will_be_available_T_34, _will_be_available_T_35)
node _will_be_available_T_36 = eq(issue_slots[12].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_37 = or(_will_be_available_T_36, issue_slots[12].clear)
node _will_be_available_T_38 = eq(issue_slots[12].in_uop.valid, UInt<1>(0h0))
node will_be_available_12 = and(_will_be_available_T_37, _will_be_available_T_38)
node _will_be_available_T_39 = eq(issue_slots[13].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_40 = or(_will_be_available_T_39, issue_slots[13].clear)
node _will_be_available_T_41 = eq(issue_slots[13].in_uop.valid, UInt<1>(0h0))
node will_be_available_13 = and(_will_be_available_T_40, _will_be_available_T_41)
node _will_be_available_T_42 = eq(issue_slots[14].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_43 = or(_will_be_available_T_42, issue_slots[14].clear)
node _will_be_available_T_44 = eq(issue_slots[14].in_uop.valid, UInt<1>(0h0))
node will_be_available_14 = and(_will_be_available_T_43, _will_be_available_T_44)
node _will_be_available_T_45 = eq(issue_slots[15].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_46 = or(_will_be_available_T_45, issue_slots[15].clear)
node _will_be_available_T_47 = eq(issue_slots[15].in_uop.valid, UInt<1>(0h0))
node will_be_available_15 = and(_will_be_available_T_46, _will_be_available_T_47)
node _will_be_available_T_48 = eq(issue_slots[16].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_49 = or(_will_be_available_T_48, issue_slots[16].clear)
node _will_be_available_T_50 = eq(issue_slots[16].in_uop.valid, UInt<1>(0h0))
node will_be_available_16 = and(_will_be_available_T_49, _will_be_available_T_50)
node _will_be_available_T_51 = eq(issue_slots[17].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_52 = or(_will_be_available_T_51, issue_slots[17].clear)
node _will_be_available_T_53 = eq(issue_slots[17].in_uop.valid, UInt<1>(0h0))
node will_be_available_17 = and(_will_be_available_T_52, _will_be_available_T_53)
node _will_be_available_T_54 = eq(issue_slots[18].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_55 = or(_will_be_available_T_54, issue_slots[18].clear)
node _will_be_available_T_56 = eq(issue_slots[18].in_uop.valid, UInt<1>(0h0))
node will_be_available_18 = and(_will_be_available_T_55, _will_be_available_T_56)
node _will_be_available_T_57 = eq(issue_slots[19].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_58 = or(_will_be_available_T_57, issue_slots[19].clear)
node _will_be_available_T_59 = eq(issue_slots[19].in_uop.valid, UInt<1>(0h0))
node will_be_available_19 = and(_will_be_available_T_58, _will_be_available_T_59)
node _will_be_available_T_60 = eq(issue_slots[20].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_61 = or(_will_be_available_T_60, issue_slots[20].clear)
node _will_be_available_T_62 = eq(issue_slots[20].in_uop.valid, UInt<1>(0h0))
node will_be_available_20 = and(_will_be_available_T_61, _will_be_available_T_62)
node _will_be_available_T_63 = eq(issue_slots[21].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_64 = or(_will_be_available_T_63, issue_slots[21].clear)
node _will_be_available_T_65 = eq(issue_slots[21].in_uop.valid, UInt<1>(0h0))
node will_be_available_21 = and(_will_be_available_T_64, _will_be_available_T_65)
node _will_be_available_T_66 = eq(issue_slots[22].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_67 = or(_will_be_available_T_66, issue_slots[22].clear)
node _will_be_available_T_68 = eq(issue_slots[22].in_uop.valid, UInt<1>(0h0))
node will_be_available_22 = and(_will_be_available_T_67, _will_be_available_T_68)
node _will_be_available_T_69 = eq(issue_slots[23].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_70 = or(_will_be_available_T_69, issue_slots[23].clear)
node _will_be_available_T_71 = eq(issue_slots[23].in_uop.valid, UInt<1>(0h0))
node will_be_available_23 = and(_will_be_available_T_70, _will_be_available_T_71)
node _num_available_T = add(will_be_available_1, will_be_available_2)
node _num_available_T_1 = bits(_num_available_T, 1, 0)
node _num_available_T_2 = add(will_be_available_0, _num_available_T_1)
node _num_available_T_3 = bits(_num_available_T_2, 1, 0)
node _num_available_T_4 = add(will_be_available_4, will_be_available_5)
node _num_available_T_5 = bits(_num_available_T_4, 1, 0)
node _num_available_T_6 = add(will_be_available_3, _num_available_T_5)
node _num_available_T_7 = bits(_num_available_T_6, 1, 0)
node _num_available_T_8 = add(_num_available_T_3, _num_available_T_7)
node _num_available_T_9 = bits(_num_available_T_8, 2, 0)
node _num_available_T_10 = add(will_be_available_7, will_be_available_8)
node _num_available_T_11 = bits(_num_available_T_10, 1, 0)
node _num_available_T_12 = add(will_be_available_6, _num_available_T_11)
node _num_available_T_13 = bits(_num_available_T_12, 1, 0)
node _num_available_T_14 = add(will_be_available_10, will_be_available_11)
node _num_available_T_15 = bits(_num_available_T_14, 1, 0)
node _num_available_T_16 = add(will_be_available_9, _num_available_T_15)
node _num_available_T_17 = bits(_num_available_T_16, 1, 0)
node _num_available_T_18 = add(_num_available_T_13, _num_available_T_17)
node _num_available_T_19 = bits(_num_available_T_18, 2, 0)
node _num_available_T_20 = add(_num_available_T_9, _num_available_T_19)
node _num_available_T_21 = bits(_num_available_T_20, 3, 0)
node _num_available_T_22 = add(will_be_available_13, will_be_available_14)
node _num_available_T_23 = bits(_num_available_T_22, 1, 0)
node _num_available_T_24 = add(will_be_available_12, _num_available_T_23)
node _num_available_T_25 = bits(_num_available_T_24, 1, 0)
node _num_available_T_26 = add(will_be_available_16, will_be_available_17)
node _num_available_T_27 = bits(_num_available_T_26, 1, 0)
node _num_available_T_28 = add(will_be_available_15, _num_available_T_27)
node _num_available_T_29 = bits(_num_available_T_28, 1, 0)
node _num_available_T_30 = add(_num_available_T_25, _num_available_T_29)
node _num_available_T_31 = bits(_num_available_T_30, 2, 0)
node _num_available_T_32 = add(will_be_available_19, will_be_available_20)
node _num_available_T_33 = bits(_num_available_T_32, 1, 0)
node _num_available_T_34 = add(will_be_available_18, _num_available_T_33)
node _num_available_T_35 = bits(_num_available_T_34, 1, 0)
node _num_available_T_36 = add(will_be_available_22, will_be_available_23)
node _num_available_T_37 = bits(_num_available_T_36, 1, 0)
node _num_available_T_38 = add(will_be_available_21, _num_available_T_37)
node _num_available_T_39 = bits(_num_available_T_38, 1, 0)
node _num_available_T_40 = add(_num_available_T_35, _num_available_T_39)
node _num_available_T_41 = bits(_num_available_T_40, 2, 0)
node _num_available_T_42 = add(_num_available_T_31, _num_available_T_41)
node _num_available_T_43 = bits(_num_available_T_42, 3, 0)
node _num_available_T_44 = add(_num_available_T_21, _num_available_T_43)
node num_available = bits(_num_available_T_44, 4, 0)
node _io_dis_uops_0_ready_T = gt(num_available, UInt<1>(0h0))
reg io_dis_uops_0_ready_REG : UInt<1>, clock
connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T
connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG
node _io_dis_uops_1_ready_T = gt(num_available, UInt<1>(0h1))
reg io_dis_uops_1_ready_REG : UInt<1>, clock
connect io_dis_uops_1_ready_REG, _io_dis_uops_1_ready_T
connect io.dis_uops[1].ready, io_dis_uops_1_ready_REG
node _io_dis_uops_2_ready_T = gt(num_available, UInt<2>(0h2))
reg io_dis_uops_2_ready_REG : UInt<1>, clock
connect io_dis_uops_2_ready_REG, _io_dis_uops_2_ready_T
connect io.dis_uops[2].ready, io_dis_uops_2_ready_REG
connect io.iss_valids[0], UInt<1>(0h0)
wire io_iss_uops_0_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate io_iss_uops_0_uop.debug_tsrc
invalidate io_iss_uops_0_uop.debug_fsrc
invalidate io_iss_uops_0_uop.bp_xcpt_if
invalidate io_iss_uops_0_uop.bp_debug_if
invalidate io_iss_uops_0_uop.xcpt_ma_if
invalidate io_iss_uops_0_uop.xcpt_ae_if
invalidate io_iss_uops_0_uop.xcpt_pf_if
invalidate io_iss_uops_0_uop.fp_single
invalidate io_iss_uops_0_uop.fp_val
invalidate io_iss_uops_0_uop.frs3_en
invalidate io_iss_uops_0_uop.lrs2_rtype
invalidate io_iss_uops_0_uop.lrs1_rtype
invalidate io_iss_uops_0_uop.dst_rtype
invalidate io_iss_uops_0_uop.ldst_val
invalidate io_iss_uops_0_uop.lrs3
invalidate io_iss_uops_0_uop.lrs2
invalidate io_iss_uops_0_uop.lrs1
invalidate io_iss_uops_0_uop.ldst
invalidate io_iss_uops_0_uop.ldst_is_rs1
invalidate io_iss_uops_0_uop.flush_on_commit
invalidate io_iss_uops_0_uop.is_unique
invalidate io_iss_uops_0_uop.is_sys_pc2epc
invalidate io_iss_uops_0_uop.uses_stq
invalidate io_iss_uops_0_uop.uses_ldq
invalidate io_iss_uops_0_uop.is_amo
invalidate io_iss_uops_0_uop.is_fencei
invalidate io_iss_uops_0_uop.is_fence
invalidate io_iss_uops_0_uop.mem_signed
invalidate io_iss_uops_0_uop.mem_size
invalidate io_iss_uops_0_uop.mem_cmd
invalidate io_iss_uops_0_uop.bypassable
invalidate io_iss_uops_0_uop.exc_cause
invalidate io_iss_uops_0_uop.exception
invalidate io_iss_uops_0_uop.stale_pdst
invalidate io_iss_uops_0_uop.ppred_busy
invalidate io_iss_uops_0_uop.prs3_busy
invalidate io_iss_uops_0_uop.prs2_busy
invalidate io_iss_uops_0_uop.prs1_busy
invalidate io_iss_uops_0_uop.ppred
invalidate io_iss_uops_0_uop.prs3
invalidate io_iss_uops_0_uop.prs2
invalidate io_iss_uops_0_uop.prs1
invalidate io_iss_uops_0_uop.pdst
invalidate io_iss_uops_0_uop.rxq_idx
invalidate io_iss_uops_0_uop.stq_idx
invalidate io_iss_uops_0_uop.ldq_idx
invalidate io_iss_uops_0_uop.rob_idx
invalidate io_iss_uops_0_uop.csr_addr
invalidate io_iss_uops_0_uop.imm_packed
invalidate io_iss_uops_0_uop.taken
invalidate io_iss_uops_0_uop.pc_lob
invalidate io_iss_uops_0_uop.edge_inst
invalidate io_iss_uops_0_uop.ftq_idx
invalidate io_iss_uops_0_uop.br_tag
invalidate io_iss_uops_0_uop.br_mask
invalidate io_iss_uops_0_uop.is_sfb
invalidate io_iss_uops_0_uop.is_jal
invalidate io_iss_uops_0_uop.is_jalr
invalidate io_iss_uops_0_uop.is_br
invalidate io_iss_uops_0_uop.iw_p2_poisoned
invalidate io_iss_uops_0_uop.iw_p1_poisoned
invalidate io_iss_uops_0_uop.iw_state
invalidate io_iss_uops_0_uop.ctrl.is_std
invalidate io_iss_uops_0_uop.ctrl.is_sta
invalidate io_iss_uops_0_uop.ctrl.is_load
invalidate io_iss_uops_0_uop.ctrl.csr_cmd
invalidate io_iss_uops_0_uop.ctrl.fcn_dw
invalidate io_iss_uops_0_uop.ctrl.op_fcn
invalidate io_iss_uops_0_uop.ctrl.imm_sel
invalidate io_iss_uops_0_uop.ctrl.op2_sel
invalidate io_iss_uops_0_uop.ctrl.op1_sel
invalidate io_iss_uops_0_uop.ctrl.br_type
invalidate io_iss_uops_0_uop.fu_code
invalidate io_iss_uops_0_uop.iq_type
invalidate io_iss_uops_0_uop.debug_pc
invalidate io_iss_uops_0_uop.is_rvc
invalidate io_iss_uops_0_uop.debug_inst
invalidate io_iss_uops_0_uop.inst
invalidate io_iss_uops_0_uop.uopc
connect io_iss_uops_0_uop.uopc, UInt<7>(0h0)
connect io_iss_uops_0_uop.bypassable, UInt<1>(0h0)
connect io_iss_uops_0_uop.fp_val, UInt<1>(0h0)
connect io_iss_uops_0_uop.uses_stq, UInt<1>(0h0)
connect io_iss_uops_0_uop.uses_ldq, UInt<1>(0h0)
connect io_iss_uops_0_uop.pdst, UInt<1>(0h0)
connect io_iss_uops_0_uop.dst_rtype, UInt<2>(0h2)
wire io_iss_uops_0_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate io_iss_uops_0_cs.is_std
invalidate io_iss_uops_0_cs.is_sta
invalidate io_iss_uops_0_cs.is_load
invalidate io_iss_uops_0_cs.csr_cmd
invalidate io_iss_uops_0_cs.fcn_dw
invalidate io_iss_uops_0_cs.op_fcn
invalidate io_iss_uops_0_cs.imm_sel
invalidate io_iss_uops_0_cs.op2_sel
invalidate io_iss_uops_0_cs.op1_sel
invalidate io_iss_uops_0_cs.br_type
connect io_iss_uops_0_cs.br_type, UInt<4>(0h0)
connect io_iss_uops_0_cs.csr_cmd, UInt<3>(0h0)
connect io_iss_uops_0_cs.is_load, UInt<1>(0h0)
connect io_iss_uops_0_cs.is_sta, UInt<1>(0h0)
connect io_iss_uops_0_cs.is_std, UInt<1>(0h0)
connect io_iss_uops_0_uop.ctrl, io_iss_uops_0_cs
connect io.iss_uops[0], io_iss_uops_0_uop
connect io.iss_uops[0].prs1, UInt<1>(0h0)
connect io.iss_uops[0].prs2, UInt<1>(0h0)
connect io.iss_uops[0].prs3, UInt<1>(0h0)
connect io.iss_uops[0].lrs1_rtype, UInt<2>(0h2)
connect io.iss_uops[0].lrs2_rtype, UInt<2>(0h2)
connect issue_slots[0].grant, UInt<1>(0h0)
node _can_allocate_T = and(issue_slots[0].uop.fu_code, io.fu_types[0])
node can_allocate = neq(_can_allocate_T, UInt<1>(0h0))
node _T_270 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = and(issue_slots[0].request, _T_270)
node _T_272 = and(_T_271, can_allocate)
node _T_273 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_274 = and(_T_272, _T_273)
when _T_274 :
connect issue_slots[0].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[0].uop
node _T_275 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_276 = and(issue_slots[0].request, _T_275)
node _T_277 = and(_T_276, can_allocate)
node _T_278 = or(_T_277, UInt<1>(0h0))
node _T_279 = and(issue_slots[0].request, can_allocate)
node _T_280 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_281 = and(_T_279, _T_280)
node _T_282 = or(_T_281, UInt<1>(0h0))
connect issue_slots[1].grant, UInt<1>(0h0)
node _can_allocate_T_1 = and(issue_slots[1].uop.fu_code, io.fu_types[0])
node can_allocate_1 = neq(_can_allocate_T_1, UInt<1>(0h0))
node _T_283 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_284 = and(issue_slots[1].request, _T_283)
node _T_285 = and(_T_284, can_allocate_1)
node _T_286 = eq(_T_278, UInt<1>(0h0))
node _T_287 = and(_T_285, _T_286)
when _T_287 :
connect issue_slots[1].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[1].uop
node _T_288 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_289 = and(issue_slots[1].request, _T_288)
node _T_290 = and(_T_289, can_allocate_1)
node _T_291 = or(_T_290, _T_278)
node _T_292 = and(issue_slots[1].request, can_allocate_1)
node _T_293 = eq(_T_278, UInt<1>(0h0))
node _T_294 = and(_T_292, _T_293)
node _T_295 = or(_T_294, UInt<1>(0h0))
connect issue_slots[2].grant, UInt<1>(0h0)
node _can_allocate_T_2 = and(issue_slots[2].uop.fu_code, io.fu_types[0])
node can_allocate_2 = neq(_can_allocate_T_2, UInt<1>(0h0))
node _T_296 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_297 = and(issue_slots[2].request, _T_296)
node _T_298 = and(_T_297, can_allocate_2)
node _T_299 = eq(_T_291, UInt<1>(0h0))
node _T_300 = and(_T_298, _T_299)
when _T_300 :
connect issue_slots[2].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[2].uop
node _T_301 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_302 = and(issue_slots[2].request, _T_301)
node _T_303 = and(_T_302, can_allocate_2)
node _T_304 = or(_T_303, _T_291)
node _T_305 = and(issue_slots[2].request, can_allocate_2)
node _T_306 = eq(_T_291, UInt<1>(0h0))
node _T_307 = and(_T_305, _T_306)
node _T_308 = or(_T_307, UInt<1>(0h0))
connect issue_slots[3].grant, UInt<1>(0h0)
node _can_allocate_T_3 = and(issue_slots[3].uop.fu_code, io.fu_types[0])
node can_allocate_3 = neq(_can_allocate_T_3, UInt<1>(0h0))
node _T_309 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_310 = and(issue_slots[3].request, _T_309)
node _T_311 = and(_T_310, can_allocate_3)
node _T_312 = eq(_T_304, UInt<1>(0h0))
node _T_313 = and(_T_311, _T_312)
when _T_313 :
connect issue_slots[3].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[3].uop
node _T_314 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_315 = and(issue_slots[3].request, _T_314)
node _T_316 = and(_T_315, can_allocate_3)
node _T_317 = or(_T_316, _T_304)
node _T_318 = and(issue_slots[3].request, can_allocate_3)
node _T_319 = eq(_T_304, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(_T_320, UInt<1>(0h0))
connect issue_slots[4].grant, UInt<1>(0h0)
node _can_allocate_T_4 = and(issue_slots[4].uop.fu_code, io.fu_types[0])
node can_allocate_4 = neq(_can_allocate_T_4, UInt<1>(0h0))
node _T_322 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_323 = and(issue_slots[4].request, _T_322)
node _T_324 = and(_T_323, can_allocate_4)
node _T_325 = eq(_T_317, UInt<1>(0h0))
node _T_326 = and(_T_324, _T_325)
when _T_326 :
connect issue_slots[4].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[4].uop
node _T_327 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_328 = and(issue_slots[4].request, _T_327)
node _T_329 = and(_T_328, can_allocate_4)
node _T_330 = or(_T_329, _T_317)
node _T_331 = and(issue_slots[4].request, can_allocate_4)
node _T_332 = eq(_T_317, UInt<1>(0h0))
node _T_333 = and(_T_331, _T_332)
node _T_334 = or(_T_333, UInt<1>(0h0))
connect issue_slots[5].grant, UInt<1>(0h0)
node _can_allocate_T_5 = and(issue_slots[5].uop.fu_code, io.fu_types[0])
node can_allocate_5 = neq(_can_allocate_T_5, UInt<1>(0h0))
node _T_335 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = and(issue_slots[5].request, _T_335)
node _T_337 = and(_T_336, can_allocate_5)
node _T_338 = eq(_T_330, UInt<1>(0h0))
node _T_339 = and(_T_337, _T_338)
when _T_339 :
connect issue_slots[5].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[5].uop
node _T_340 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = and(issue_slots[5].request, _T_340)
node _T_342 = and(_T_341, can_allocate_5)
node _T_343 = or(_T_342, _T_330)
node _T_344 = and(issue_slots[5].request, can_allocate_5)
node _T_345 = eq(_T_330, UInt<1>(0h0))
node _T_346 = and(_T_344, _T_345)
node _T_347 = or(_T_346, UInt<1>(0h0))
connect issue_slots[6].grant, UInt<1>(0h0)
node _can_allocate_T_6 = and(issue_slots[6].uop.fu_code, io.fu_types[0])
node can_allocate_6 = neq(_can_allocate_T_6, UInt<1>(0h0))
node _T_348 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_349 = and(issue_slots[6].request, _T_348)
node _T_350 = and(_T_349, can_allocate_6)
node _T_351 = eq(_T_343, UInt<1>(0h0))
node _T_352 = and(_T_350, _T_351)
when _T_352 :
connect issue_slots[6].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[6].uop
node _T_353 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_354 = and(issue_slots[6].request, _T_353)
node _T_355 = and(_T_354, can_allocate_6)
node _T_356 = or(_T_355, _T_343)
node _T_357 = and(issue_slots[6].request, can_allocate_6)
node _T_358 = eq(_T_343, UInt<1>(0h0))
node _T_359 = and(_T_357, _T_358)
node _T_360 = or(_T_359, UInt<1>(0h0))
connect issue_slots[7].grant, UInt<1>(0h0)
node _can_allocate_T_7 = and(issue_slots[7].uop.fu_code, io.fu_types[0])
node can_allocate_7 = neq(_can_allocate_T_7, UInt<1>(0h0))
node _T_361 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = and(issue_slots[7].request, _T_361)
node _T_363 = and(_T_362, can_allocate_7)
node _T_364 = eq(_T_356, UInt<1>(0h0))
node _T_365 = and(_T_363, _T_364)
when _T_365 :
connect issue_slots[7].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[7].uop
node _T_366 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_367 = and(issue_slots[7].request, _T_366)
node _T_368 = and(_T_367, can_allocate_7)
node _T_369 = or(_T_368, _T_356)
node _T_370 = and(issue_slots[7].request, can_allocate_7)
node _T_371 = eq(_T_356, UInt<1>(0h0))
node _T_372 = and(_T_370, _T_371)
node _T_373 = or(_T_372, UInt<1>(0h0))
connect issue_slots[8].grant, UInt<1>(0h0)
node _can_allocate_T_8 = and(issue_slots[8].uop.fu_code, io.fu_types[0])
node can_allocate_8 = neq(_can_allocate_T_8, UInt<1>(0h0))
node _T_374 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_375 = and(issue_slots[8].request, _T_374)
node _T_376 = and(_T_375, can_allocate_8)
node _T_377 = eq(_T_369, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
when _T_378 :
connect issue_slots[8].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[8].uop
node _T_379 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_380 = and(issue_slots[8].request, _T_379)
node _T_381 = and(_T_380, can_allocate_8)
node _T_382 = or(_T_381, _T_369)
node _T_383 = and(issue_slots[8].request, can_allocate_8)
node _T_384 = eq(_T_369, UInt<1>(0h0))
node _T_385 = and(_T_383, _T_384)
node _T_386 = or(_T_385, UInt<1>(0h0))
connect issue_slots[9].grant, UInt<1>(0h0)
node _can_allocate_T_9 = and(issue_slots[9].uop.fu_code, io.fu_types[0])
node can_allocate_9 = neq(_can_allocate_T_9, UInt<1>(0h0))
node _T_387 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_388 = and(issue_slots[9].request, _T_387)
node _T_389 = and(_T_388, can_allocate_9)
node _T_390 = eq(_T_382, UInt<1>(0h0))
node _T_391 = and(_T_389, _T_390)
when _T_391 :
connect issue_slots[9].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[9].uop
node _T_392 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_393 = and(issue_slots[9].request, _T_392)
node _T_394 = and(_T_393, can_allocate_9)
node _T_395 = or(_T_394, _T_382)
node _T_396 = and(issue_slots[9].request, can_allocate_9)
node _T_397 = eq(_T_382, UInt<1>(0h0))
node _T_398 = and(_T_396, _T_397)
node _T_399 = or(_T_398, UInt<1>(0h0))
connect issue_slots[10].grant, UInt<1>(0h0)
node _can_allocate_T_10 = and(issue_slots[10].uop.fu_code, io.fu_types[0])
node can_allocate_10 = neq(_can_allocate_T_10, UInt<1>(0h0))
node _T_400 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_401 = and(issue_slots[10].request, _T_400)
node _T_402 = and(_T_401, can_allocate_10)
node _T_403 = eq(_T_395, UInt<1>(0h0))
node _T_404 = and(_T_402, _T_403)
when _T_404 :
connect issue_slots[10].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[10].uop
node _T_405 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_406 = and(issue_slots[10].request, _T_405)
node _T_407 = and(_T_406, can_allocate_10)
node _T_408 = or(_T_407, _T_395)
node _T_409 = and(issue_slots[10].request, can_allocate_10)
node _T_410 = eq(_T_395, UInt<1>(0h0))
node _T_411 = and(_T_409, _T_410)
node _T_412 = or(_T_411, UInt<1>(0h0))
connect issue_slots[11].grant, UInt<1>(0h0)
node _can_allocate_T_11 = and(issue_slots[11].uop.fu_code, io.fu_types[0])
node can_allocate_11 = neq(_can_allocate_T_11, UInt<1>(0h0))
node _T_413 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_414 = and(issue_slots[11].request, _T_413)
node _T_415 = and(_T_414, can_allocate_11)
node _T_416 = eq(_T_408, UInt<1>(0h0))
node _T_417 = and(_T_415, _T_416)
when _T_417 :
connect issue_slots[11].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[11].uop
node _T_418 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = and(issue_slots[11].request, _T_418)
node _T_420 = and(_T_419, can_allocate_11)
node _T_421 = or(_T_420, _T_408)
node _T_422 = and(issue_slots[11].request, can_allocate_11)
node _T_423 = eq(_T_408, UInt<1>(0h0))
node _T_424 = and(_T_422, _T_423)
node _T_425 = or(_T_424, UInt<1>(0h0))
connect issue_slots[12].grant, UInt<1>(0h0)
node _can_allocate_T_12 = and(issue_slots[12].uop.fu_code, io.fu_types[0])
node can_allocate_12 = neq(_can_allocate_T_12, UInt<1>(0h0))
node _T_426 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = and(issue_slots[12].request, _T_426)
node _T_428 = and(_T_427, can_allocate_12)
node _T_429 = eq(_T_421, UInt<1>(0h0))
node _T_430 = and(_T_428, _T_429)
when _T_430 :
connect issue_slots[12].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[12].uop
node _T_431 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_432 = and(issue_slots[12].request, _T_431)
node _T_433 = and(_T_432, can_allocate_12)
node _T_434 = or(_T_433, _T_421)
node _T_435 = and(issue_slots[12].request, can_allocate_12)
node _T_436 = eq(_T_421, UInt<1>(0h0))
node _T_437 = and(_T_435, _T_436)
node _T_438 = or(_T_437, UInt<1>(0h0))
connect issue_slots[13].grant, UInt<1>(0h0)
node _can_allocate_T_13 = and(issue_slots[13].uop.fu_code, io.fu_types[0])
node can_allocate_13 = neq(_can_allocate_T_13, UInt<1>(0h0))
node _T_439 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_440 = and(issue_slots[13].request, _T_439)
node _T_441 = and(_T_440, can_allocate_13)
node _T_442 = eq(_T_434, UInt<1>(0h0))
node _T_443 = and(_T_441, _T_442)
when _T_443 :
connect issue_slots[13].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[13].uop
node _T_444 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_445 = and(issue_slots[13].request, _T_444)
node _T_446 = and(_T_445, can_allocate_13)
node _T_447 = or(_T_446, _T_434)
node _T_448 = and(issue_slots[13].request, can_allocate_13)
node _T_449 = eq(_T_434, UInt<1>(0h0))
node _T_450 = and(_T_448, _T_449)
node _T_451 = or(_T_450, UInt<1>(0h0))
connect issue_slots[14].grant, UInt<1>(0h0)
node _can_allocate_T_14 = and(issue_slots[14].uop.fu_code, io.fu_types[0])
node can_allocate_14 = neq(_can_allocate_T_14, UInt<1>(0h0))
node _T_452 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_453 = and(issue_slots[14].request, _T_452)
node _T_454 = and(_T_453, can_allocate_14)
node _T_455 = eq(_T_447, UInt<1>(0h0))
node _T_456 = and(_T_454, _T_455)
when _T_456 :
connect issue_slots[14].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[14].uop
node _T_457 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_458 = and(issue_slots[14].request, _T_457)
node _T_459 = and(_T_458, can_allocate_14)
node _T_460 = or(_T_459, _T_447)
node _T_461 = and(issue_slots[14].request, can_allocate_14)
node _T_462 = eq(_T_447, UInt<1>(0h0))
node _T_463 = and(_T_461, _T_462)
node _T_464 = or(_T_463, UInt<1>(0h0))
connect issue_slots[15].grant, UInt<1>(0h0)
node _can_allocate_T_15 = and(issue_slots[15].uop.fu_code, io.fu_types[0])
node can_allocate_15 = neq(_can_allocate_T_15, UInt<1>(0h0))
node _T_465 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_466 = and(issue_slots[15].request, _T_465)
node _T_467 = and(_T_466, can_allocate_15)
node _T_468 = eq(_T_460, UInt<1>(0h0))
node _T_469 = and(_T_467, _T_468)
when _T_469 :
connect issue_slots[15].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[15].uop
node _T_470 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_471 = and(issue_slots[15].request, _T_470)
node _T_472 = and(_T_471, can_allocate_15)
node _T_473 = or(_T_472, _T_460)
node _T_474 = and(issue_slots[15].request, can_allocate_15)
node _T_475 = eq(_T_460, UInt<1>(0h0))
node _T_476 = and(_T_474, _T_475)
node _T_477 = or(_T_476, UInt<1>(0h0))
connect issue_slots[16].grant, UInt<1>(0h0)
node _can_allocate_T_16 = and(issue_slots[16].uop.fu_code, io.fu_types[0])
node can_allocate_16 = neq(_can_allocate_T_16, UInt<1>(0h0))
node _T_478 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_479 = and(issue_slots[16].request, _T_478)
node _T_480 = and(_T_479, can_allocate_16)
node _T_481 = eq(_T_473, UInt<1>(0h0))
node _T_482 = and(_T_480, _T_481)
when _T_482 :
connect issue_slots[16].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[16].uop
node _T_483 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_484 = and(issue_slots[16].request, _T_483)
node _T_485 = and(_T_484, can_allocate_16)
node _T_486 = or(_T_485, _T_473)
node _T_487 = and(issue_slots[16].request, can_allocate_16)
node _T_488 = eq(_T_473, UInt<1>(0h0))
node _T_489 = and(_T_487, _T_488)
node _T_490 = or(_T_489, UInt<1>(0h0))
connect issue_slots[17].grant, UInt<1>(0h0)
node _can_allocate_T_17 = and(issue_slots[17].uop.fu_code, io.fu_types[0])
node can_allocate_17 = neq(_can_allocate_T_17, UInt<1>(0h0))
node _T_491 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_492 = and(issue_slots[17].request, _T_491)
node _T_493 = and(_T_492, can_allocate_17)
node _T_494 = eq(_T_486, UInt<1>(0h0))
node _T_495 = and(_T_493, _T_494)
when _T_495 :
connect issue_slots[17].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[17].uop
node _T_496 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_497 = and(issue_slots[17].request, _T_496)
node _T_498 = and(_T_497, can_allocate_17)
node _T_499 = or(_T_498, _T_486)
node _T_500 = and(issue_slots[17].request, can_allocate_17)
node _T_501 = eq(_T_486, UInt<1>(0h0))
node _T_502 = and(_T_500, _T_501)
node _T_503 = or(_T_502, UInt<1>(0h0))
connect issue_slots[18].grant, UInt<1>(0h0)
node _can_allocate_T_18 = and(issue_slots[18].uop.fu_code, io.fu_types[0])
node can_allocate_18 = neq(_can_allocate_T_18, UInt<1>(0h0))
node _T_504 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_505 = and(issue_slots[18].request, _T_504)
node _T_506 = and(_T_505, can_allocate_18)
node _T_507 = eq(_T_499, UInt<1>(0h0))
node _T_508 = and(_T_506, _T_507)
when _T_508 :
connect issue_slots[18].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[18].uop
node _T_509 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_510 = and(issue_slots[18].request, _T_509)
node _T_511 = and(_T_510, can_allocate_18)
node _T_512 = or(_T_511, _T_499)
node _T_513 = and(issue_slots[18].request, can_allocate_18)
node _T_514 = eq(_T_499, UInt<1>(0h0))
node _T_515 = and(_T_513, _T_514)
node _T_516 = or(_T_515, UInt<1>(0h0))
connect issue_slots[19].grant, UInt<1>(0h0)
node _can_allocate_T_19 = and(issue_slots[19].uop.fu_code, io.fu_types[0])
node can_allocate_19 = neq(_can_allocate_T_19, UInt<1>(0h0))
node _T_517 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_518 = and(issue_slots[19].request, _T_517)
node _T_519 = and(_T_518, can_allocate_19)
node _T_520 = eq(_T_512, UInt<1>(0h0))
node _T_521 = and(_T_519, _T_520)
when _T_521 :
connect issue_slots[19].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[19].uop
node _T_522 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_523 = and(issue_slots[19].request, _T_522)
node _T_524 = and(_T_523, can_allocate_19)
node _T_525 = or(_T_524, _T_512)
node _T_526 = and(issue_slots[19].request, can_allocate_19)
node _T_527 = eq(_T_512, UInt<1>(0h0))
node _T_528 = and(_T_526, _T_527)
node _T_529 = or(_T_528, UInt<1>(0h0))
connect issue_slots[20].grant, UInt<1>(0h0)
node _can_allocate_T_20 = and(issue_slots[20].uop.fu_code, io.fu_types[0])
node can_allocate_20 = neq(_can_allocate_T_20, UInt<1>(0h0))
node _T_530 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_531 = and(issue_slots[20].request, _T_530)
node _T_532 = and(_T_531, can_allocate_20)
node _T_533 = eq(_T_525, UInt<1>(0h0))
node _T_534 = and(_T_532, _T_533)
when _T_534 :
connect issue_slots[20].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[20].uop
node _T_535 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_536 = and(issue_slots[20].request, _T_535)
node _T_537 = and(_T_536, can_allocate_20)
node _T_538 = or(_T_537, _T_525)
node _T_539 = and(issue_slots[20].request, can_allocate_20)
node _T_540 = eq(_T_525, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(_T_541, UInt<1>(0h0))
connect issue_slots[21].grant, UInt<1>(0h0)
node _can_allocate_T_21 = and(issue_slots[21].uop.fu_code, io.fu_types[0])
node can_allocate_21 = neq(_can_allocate_T_21, UInt<1>(0h0))
node _T_543 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_544 = and(issue_slots[21].request, _T_543)
node _T_545 = and(_T_544, can_allocate_21)
node _T_546 = eq(_T_538, UInt<1>(0h0))
node _T_547 = and(_T_545, _T_546)
when _T_547 :
connect issue_slots[21].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[21].uop
node _T_548 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_549 = and(issue_slots[21].request, _T_548)
node _T_550 = and(_T_549, can_allocate_21)
node _T_551 = or(_T_550, _T_538)
node _T_552 = and(issue_slots[21].request, can_allocate_21)
node _T_553 = eq(_T_538, UInt<1>(0h0))
node _T_554 = and(_T_552, _T_553)
node _T_555 = or(_T_554, UInt<1>(0h0))
connect issue_slots[22].grant, UInt<1>(0h0)
node _can_allocate_T_22 = and(issue_slots[22].uop.fu_code, io.fu_types[0])
node can_allocate_22 = neq(_can_allocate_T_22, UInt<1>(0h0))
node _T_556 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_557 = and(issue_slots[22].request, _T_556)
node _T_558 = and(_T_557, can_allocate_22)
node _T_559 = eq(_T_551, UInt<1>(0h0))
node _T_560 = and(_T_558, _T_559)
when _T_560 :
connect issue_slots[22].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[22].uop
node _T_561 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_562 = and(issue_slots[22].request, _T_561)
node _T_563 = and(_T_562, can_allocate_22)
node _T_564 = or(_T_563, _T_551)
node _T_565 = and(issue_slots[22].request, can_allocate_22)
node _T_566 = eq(_T_551, UInt<1>(0h0))
node _T_567 = and(_T_565, _T_566)
node _T_568 = or(_T_567, UInt<1>(0h0))
connect issue_slots[23].grant, UInt<1>(0h0)
node _can_allocate_T_23 = and(issue_slots[23].uop.fu_code, io.fu_types[0])
node can_allocate_23 = neq(_can_allocate_T_23, UInt<1>(0h0))
node _T_569 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_570 = and(issue_slots[23].request, _T_569)
node _T_571 = and(_T_570, can_allocate_23)
node _T_572 = eq(_T_564, UInt<1>(0h0))
node _T_573 = and(_T_571, _T_572)
when _T_573 :
connect issue_slots[23].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[23].uop
node _T_574 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_575 = and(issue_slots[23].request, _T_574)
node _T_576 = and(_T_575, can_allocate_23)
node _T_577 = or(_T_576, _T_564)
node _T_578 = and(issue_slots[23].request, can_allocate_23)
node _T_579 = eq(_T_564, UInt<1>(0h0))
node _T_580 = and(_T_578, _T_579)
node _T_581 = or(_T_580, UInt<1>(0h0)) | module IssueUnitCollapsing( // @[issue-unit-age-ordered.scala:29:7]
input clock, // @[issue-unit-age-ordered.scala:29:7]
input reset, // @[issue-unit-age-ordered.scala:29:7]
output io_dis_uops_0_ready, // @[issue-unit.scala:112:14]
input io_dis_uops_0_valid, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_dis_uops_0_bits_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_0_bits_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_iw_state, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_br, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_jalr, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_jal, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_taken, // @[issue-unit.scala:112:14]
input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_dis_uops_0_bits_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_exception, // @[issue-unit.scala:112:14]
input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_fp_single, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:112:14]
output io_dis_uops_1_ready, // @[issue-unit.scala:112:14]
input io_dis_uops_1_valid, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_dis_uops_1_bits_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_1_bits_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_iw_state, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_br, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_jalr, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_jal, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_taken, // @[issue-unit.scala:112:14]
input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_dis_uops_1_bits_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_exception, // @[issue-unit.scala:112:14]
input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_fp_single, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:112:14]
output io_dis_uops_2_ready, // @[issue-unit.scala:112:14]
input io_dis_uops_2_valid, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_dis_uops_2_bits_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_2_bits_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_iw_state, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_br, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_jalr, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_jal, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_taken, // @[issue-unit.scala:112:14]
input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_dis_uops_2_bits_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_exception, // @[issue-unit.scala:112:14]
input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_fp_single, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:112:14]
output io_iss_valids_0, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_uopc, // @[issue-unit.scala:112:14]
output [31:0] io_iss_uops_0_inst, // @[issue-unit.scala:112:14]
output [31:0] io_iss_uops_0_debug_inst, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_rvc, // @[issue-unit.scala:112:14]
output [39:0] io_iss_uops_0_debug_pc, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_iq_type, // @[issue-unit.scala:112:14]
output [9:0] io_iss_uops_0_fu_code, // @[issue-unit.scala:112:14]
output [3:0] io_iss_uops_0_ctrl_br_type, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_ctrl_op1_sel, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_op2_sel, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_imm_sel, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ctrl_op_fcn, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_load, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_sta, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_std, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_iw_state, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_br, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_jalr, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_jal, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_sfb, // @[issue-unit.scala:112:14]
output [15:0] io_iss_uops_0_br_mask, // @[issue-unit.scala:112:14]
output [3:0] io_iss_uops_0_br_tag, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ftq_idx, // @[issue-unit.scala:112:14]
output io_iss_uops_0_edge_inst, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_pc_lob, // @[issue-unit.scala:112:14]
output io_iss_uops_0_taken, // @[issue-unit.scala:112:14]
output [19:0] io_iss_uops_0_imm_packed, // @[issue-unit.scala:112:14]
output [11:0] io_iss_uops_0_csr_addr, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_rob_idx, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ldq_idx, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_stq_idx, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_rxq_idx, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_pdst, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_prs1, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_prs2, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_prs3, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ppred, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs1_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs2_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs3_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ppred_busy, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_stale_pdst, // @[issue-unit.scala:112:14]
output io_iss_uops_0_exception, // @[issue-unit.scala:112:14]
output [63:0] io_iss_uops_0_exc_cause, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bypassable, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_mem_cmd, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_mem_size, // @[issue-unit.scala:112:14]
output io_iss_uops_0_mem_signed, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_fence, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_fencei, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_amo, // @[issue-unit.scala:112:14]
output io_iss_uops_0_uses_ldq, // @[issue-unit.scala:112:14]
output io_iss_uops_0_uses_stq, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_sys_pc2epc, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_unique, // @[issue-unit.scala:112:14]
output io_iss_uops_0_flush_on_commit, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ldst_is_rs1, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_ldst, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs1, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs2, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs3, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ldst_val, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_dst_rtype, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_lrs1_rtype, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_lrs2_rtype, // @[issue-unit.scala:112:14]
output io_iss_uops_0_frs3_en, // @[issue-unit.scala:112:14]
output io_iss_uops_0_fp_val, // @[issue-unit.scala:112:14]
output io_iss_uops_0_fp_single, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_pf_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_ae_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_ma_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bp_debug_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bp_xcpt_if, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_debug_fsrc, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_debug_tsrc, // @[issue-unit.scala:112:14]
input io_wakeup_ports_0_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_1_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-unit.scala:112:14]
input [9:0] io_fu_types_0, // @[issue-unit.scala:112:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:112:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:112:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_br, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_jal, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_taken, // @[issue-unit.scala:112:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_exception, // @[issue-unit.scala:112:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_fp_single, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:112:14]
input io_brupdate_b2_valid, // @[issue-unit.scala:112:14]
input io_brupdate_b2_mispredict, // @[issue-unit.scala:112:14]
input io_brupdate_b2_taken, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:112:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:112:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:112:14]
input io_flush_pipeline, // @[issue-unit.scala:112:14]
input [63:0] io_tsc_reg // @[issue-unit.scala:112:14]
);
wire _slots_23_io_valid; // @[issue-unit.scala:153:73]
wire _slots_22_io_valid; // @[issue-unit.scala:153:73]
wire _slots_21_io_valid; // @[issue-unit.scala:153:73]
wire _slots_20_io_valid; // @[issue-unit.scala:153:73]
wire _slots_19_io_valid; // @[issue-unit.scala:153:73]
wire _slots_18_io_valid; // @[issue-unit.scala:153:73]
wire _slots_17_io_valid; // @[issue-unit.scala:153:73]
wire _slots_16_io_valid; // @[issue-unit.scala:153:73]
wire _slots_15_io_valid; // @[issue-unit.scala:153:73]
wire _slots_14_io_valid; // @[issue-unit.scala:153:73]
wire _slots_13_io_valid; // @[issue-unit.scala:153:73]
wire _slots_12_io_valid; // @[issue-unit.scala:153:73]
wire _slots_11_io_valid; // @[issue-unit.scala:153:73]
wire _slots_10_io_valid; // @[issue-unit.scala:153:73]
wire _slots_9_io_valid; // @[issue-unit.scala:153:73]
wire _slots_8_io_valid; // @[issue-unit.scala:153:73]
wire _slots_7_io_valid; // @[issue-unit.scala:153:73]
wire _slots_6_io_valid; // @[issue-unit.scala:153:73]
wire _slots_5_io_valid; // @[issue-unit.scala:153:73]
wire _slots_4_io_valid; // @[issue-unit.scala:153:73]
wire _slots_3_io_valid; // @[issue-unit.scala:153:73]
wire _slots_2_io_valid; // @[issue-unit.scala:153:73]
wire _slots_1_io_valid; // @[issue-unit.scala:153:73]
wire _slots_0_io_valid; // @[issue-unit.scala:153:73]
wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_uopc_0 = io_dis_uops_0_bits_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_iq_type_0 = io_dis_uops_0_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_dis_uops_0_bits_fu_code_0 = io_dis_uops_0_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_0_bits_ctrl_br_type_0 = io_dis_uops_0_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_ctrl_op1_sel_0 = io_dis_uops_0_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_op2_sel_0 = io_dis_uops_0_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_imm_sel_0 = io_dis_uops_0_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_ctrl_op_fcn_0 = io_dis_uops_0_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_fcn_dw_0 = io_dis_uops_0_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_csr_cmd_0 = io_dis_uops_0_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_load_0 = io_dis_uops_0_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_sta_0 = io_dis_uops_0_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_std_0 = io_dis_uops_0_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_iw_state_0 = io_dis_uops_0_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_iw_p1_poisoned_0 = io_dis_uops_0_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_iw_p2_poisoned_0 = io_dis_uops_0_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_br_0 = io_dis_uops_0_bits_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_jalr_0 = io_dis_uops_0_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_jal_0 = io_dis_uops_0_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_dis_uops_0_bits_csr_addr_0 = io_dis_uops_0_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bypassable_0 = io_dis_uops_0_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ldst_val_0 = io_dis_uops_0_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_fp_single_0 = io_dis_uops_0_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_uopc_0 = io_dis_uops_1_bits_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_iq_type_0 = io_dis_uops_1_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_dis_uops_1_bits_fu_code_0 = io_dis_uops_1_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_1_bits_ctrl_br_type_0 = io_dis_uops_1_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_ctrl_op1_sel_0 = io_dis_uops_1_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_ctrl_op2_sel_0 = io_dis_uops_1_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_ctrl_imm_sel_0 = io_dis_uops_1_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ctrl_op_fcn_0 = io_dis_uops_1_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_fcn_dw_0 = io_dis_uops_1_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_ctrl_csr_cmd_0 = io_dis_uops_1_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_is_load_0 = io_dis_uops_1_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_is_sta_0 = io_dis_uops_1_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_is_std_0 = io_dis_uops_1_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_iw_state_0 = io_dis_uops_1_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_iw_p1_poisoned_0 = io_dis_uops_1_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_iw_p2_poisoned_0 = io_dis_uops_1_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_br_0 = io_dis_uops_1_bits_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_jalr_0 = io_dis_uops_1_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_jal_0 = io_dis_uops_1_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_dis_uops_1_bits_csr_addr_0 = io_dis_uops_1_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_bypassable_0 = io_dis_uops_1_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ldst_val_0 = io_dis_uops_1_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_fp_single_0 = io_dis_uops_1_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_uopc_0 = io_dis_uops_2_bits_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_iq_type_0 = io_dis_uops_2_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_dis_uops_2_bits_fu_code_0 = io_dis_uops_2_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_2_bits_ctrl_br_type_0 = io_dis_uops_2_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_ctrl_op1_sel_0 = io_dis_uops_2_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_ctrl_op2_sel_0 = io_dis_uops_2_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_ctrl_imm_sel_0 = io_dis_uops_2_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ctrl_op_fcn_0 = io_dis_uops_2_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_fcn_dw_0 = io_dis_uops_2_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_ctrl_csr_cmd_0 = io_dis_uops_2_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_is_load_0 = io_dis_uops_2_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_is_sta_0 = io_dis_uops_2_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_is_std_0 = io_dis_uops_2_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_iw_state_0 = io_dis_uops_2_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_iw_p1_poisoned_0 = io_dis_uops_2_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_iw_p2_poisoned_0 = io_dis_uops_2_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_br_0 = io_dis_uops_2_bits_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_jalr_0 = io_dis_uops_2_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_jal_0 = io_dis_uops_2_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_dis_uops_2_bits_csr_addr_0 = io_dis_uops_2_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_bypassable_0 = io_dis_uops_2_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ldst_val_0 = io_dis_uops_2_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_fp_single_0 = io_dis_uops_2_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_fu_types_0_0 = io_fu_types_0; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:29:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:29:7]
wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_iw_p1_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_iw_p2_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_ld_miss = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire issue_slots_0_clear = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_ppred_busy = 1'h0; // @[issue-unit.scala:154:28]
wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:76:49]
wire io_iss_uops_0_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_taken = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_exception = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_dis_uops_0_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_in_uop_bits_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_in_uop_bits_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_out_uop_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_uop_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] io_iss_uops_0_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] issue_slots_23_in_uop_bits_iw_state = 2'h1; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_iw_state = 2'h1; // @[issue-unit.scala:154:28]
wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] issue_slots_0_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_spec_ld_wakeup_0_bits = 7'h0; // @[issue-unit.scala:154:28]
wire [6:0] io_iss_uops_0_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] io_iss_uops_0_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] _next_T = 4'h0; // @[issue-unit-age-ordered.scala:48:26]
wire [3:0] io_iss_uops_0_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] io_iss_uops_0_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] io_iss_uops_0_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] io_iss_uops_0_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] io_iss_uops_0_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] io_iss_uops_0_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] io_iss_uops_0_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] io_iss_uops_0_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] io_iss_uops_0_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] io_iss_uops_0_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] io_iss_uops_0_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] io_iss_uops_0_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_16_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_17_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_18_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_19_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_20_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_21_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_22_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_23_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_16_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_17_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_18_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_19_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_20_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_21_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_22_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_23_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_16_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_17_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_18_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_19_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_20_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_21_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_22_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_23_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_16_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_17_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_18_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_19_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_20_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_21_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_22_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_23_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_16_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_17_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_18_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_19_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_20_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_21_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_22_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_23_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_16_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_17_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_18_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_19_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_20_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_21_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_22_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_23_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_16_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_17_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_18_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_19_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_20_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_21_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_22_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_23_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_16_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_17_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_18_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_19_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_20_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_21_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_22_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_23_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_16_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_17_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_18_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_19_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_20_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_21_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_22_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_23_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_16_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_17_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_18_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_19_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_20_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_21_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_22_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_23_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_16_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_17_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_18_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_19_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_20_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_21_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_22_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_23_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire _io_event_empty_T_23; // @[issue-unit.scala:165:21]
wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_valids_0_0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_iss_uops_0_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_uopc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_iss_uops_0_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_iss_uops_0_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_iss_uops_0_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_iq_type_0; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_iss_uops_0_fu_code_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_iw_state_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_br_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_jal_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_iss_uops_0_br_mask_0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_iss_uops_0_br_tag_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_taken_0; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_iss_uops_0_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_iss_uops_0_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_pdst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_prs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_prs2_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_prs3_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ppred_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_exception_0; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_iss_uops_0_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bypassable_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_mem_size_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_fence_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_amo_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_unique_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_ldst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs2_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs3_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_fp_val_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_fp_single_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_event_empty; // @[issue-unit-age-ordered.scala:29:7]
wire _T = io_dis_uops_0_bits_uopc_0 == 7'h2; // @[issue-unit.scala:138:38]
wire [1:0] _WIRE_lrs1_rtype = _T ? 2'h2 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit.scala:120:17, :138:{38,50}, :139:32]
wire _WIRE_prs1_busy = ~_T & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit.scala:120:17, :138:{38,50}, :140:32]
wire _T_6 = io_dis_uops_1_bits_uopc_0 == 7'h2; // @[issue-unit.scala:138:38]
wire [1:0] _WIRE_1_lrs1_rtype = _T_6 ? 2'h2 : io_dis_uops_1_bits_lrs1_rtype_0; // @[issue-unit.scala:120:17, :138:{38,50}, :139:32]
wire _WIRE_1_prs1_busy = ~_T_6 & io_dis_uops_1_bits_prs1_busy_0; // @[issue-unit.scala:120:17, :138:{38,50}, :140:32]
wire _T_12 = io_dis_uops_2_bits_uopc_0 == 7'h2; // @[issue-unit.scala:138:38]
wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_20_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_21_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_22_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_23_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [3:0] issue_slots_0_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_valid; // @[issue-unit.scala:154:28]
wire issue_slots_0_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_0_request; // @[issue-unit.scala:154:28]
wire issue_slots_0_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_0_grant; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_valid; // @[issue-unit.scala:154:28]
wire issue_slots_1_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_1_request; // @[issue-unit.scala:154:28]
wire issue_slots_1_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_1_grant; // @[issue-unit.scala:154:28]
wire issue_slots_1_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_valid; // @[issue-unit.scala:154:28]
wire issue_slots_2_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_2_request; // @[issue-unit.scala:154:28]
wire issue_slots_2_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_2_grant; // @[issue-unit.scala:154:28]
wire issue_slots_2_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_valid; // @[issue-unit.scala:154:28]
wire issue_slots_3_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_3_request; // @[issue-unit.scala:154:28]
wire issue_slots_3_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_3_grant; // @[issue-unit.scala:154:28]
wire issue_slots_3_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_valid; // @[issue-unit.scala:154:28]
wire issue_slots_4_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_4_request; // @[issue-unit.scala:154:28]
wire issue_slots_4_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_4_grant; // @[issue-unit.scala:154:28]
wire issue_slots_4_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_valid; // @[issue-unit.scala:154:28]
wire issue_slots_5_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_5_request; // @[issue-unit.scala:154:28]
wire issue_slots_5_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_5_grant; // @[issue-unit.scala:154:28]
wire issue_slots_5_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_valid; // @[issue-unit.scala:154:28]
wire issue_slots_6_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_6_request; // @[issue-unit.scala:154:28]
wire issue_slots_6_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_6_grant; // @[issue-unit.scala:154:28]
wire issue_slots_6_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_valid; // @[issue-unit.scala:154:28]
wire issue_slots_7_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_7_request; // @[issue-unit.scala:154:28]
wire issue_slots_7_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_7_grant; // @[issue-unit.scala:154:28]
wire issue_slots_7_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_valid; // @[issue-unit.scala:154:28]
wire issue_slots_8_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_8_request; // @[issue-unit.scala:154:28]
wire issue_slots_8_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_8_grant; // @[issue-unit.scala:154:28]
wire issue_slots_8_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_valid; // @[issue-unit.scala:154:28]
wire issue_slots_9_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_9_request; // @[issue-unit.scala:154:28]
wire issue_slots_9_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_9_grant; // @[issue-unit.scala:154:28]
wire issue_slots_9_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_valid; // @[issue-unit.scala:154:28]
wire issue_slots_10_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_10_request; // @[issue-unit.scala:154:28]
wire issue_slots_10_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_10_grant; // @[issue-unit.scala:154:28]
wire issue_slots_10_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_valid; // @[issue-unit.scala:154:28]
wire issue_slots_11_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_11_request; // @[issue-unit.scala:154:28]
wire issue_slots_11_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_11_grant; // @[issue-unit.scala:154:28]
wire issue_slots_11_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_valid; // @[issue-unit.scala:154:28]
wire issue_slots_12_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_12_request; // @[issue-unit.scala:154:28]
wire issue_slots_12_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_12_grant; // @[issue-unit.scala:154:28]
wire issue_slots_12_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_valid; // @[issue-unit.scala:154:28]
wire issue_slots_13_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_13_request; // @[issue-unit.scala:154:28]
wire issue_slots_13_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_13_grant; // @[issue-unit.scala:154:28]
wire issue_slots_13_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_valid; // @[issue-unit.scala:154:28]
wire issue_slots_14_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_14_request; // @[issue-unit.scala:154:28]
wire issue_slots_14_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_14_grant; // @[issue-unit.scala:154:28]
wire issue_slots_14_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_valid; // @[issue-unit.scala:154:28]
wire issue_slots_15_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_15_request; // @[issue-unit.scala:154:28]
wire issue_slots_15_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_15_grant; // @[issue-unit.scala:154:28]
wire issue_slots_15_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_16_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_16_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_16_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_16_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_16_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_16_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_16_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_16_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_16_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_16_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_16_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_16_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_16_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_16_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_16_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_16_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_16_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_16_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_16_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_16_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_16_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_16_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_16_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_16_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_16_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_16_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_16_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_16_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_16_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_16_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_16_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_16_valid; // @[issue-unit.scala:154:28]
wire issue_slots_16_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_16_request; // @[issue-unit.scala:154:28]
wire issue_slots_16_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_16_grant; // @[issue-unit.scala:154:28]
wire issue_slots_16_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_17_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_17_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_17_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_17_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_17_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_17_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_17_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_17_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_17_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_17_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_17_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_17_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_17_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_17_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_17_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_17_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_17_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_17_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_17_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_17_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_17_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_17_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_17_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_17_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_17_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_17_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_17_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_17_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_17_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_17_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_17_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_17_valid; // @[issue-unit.scala:154:28]
wire issue_slots_17_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_17_request; // @[issue-unit.scala:154:28]
wire issue_slots_17_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_17_grant; // @[issue-unit.scala:154:28]
wire issue_slots_17_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_18_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_18_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_18_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_18_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_18_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_18_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_18_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_18_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_18_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_18_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_18_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_18_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_18_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_18_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_18_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_18_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_18_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_18_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_18_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_18_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_18_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_18_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_18_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_18_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_18_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_18_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_18_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_18_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_18_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_18_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_18_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_18_valid; // @[issue-unit.scala:154:28]
wire issue_slots_18_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_18_request; // @[issue-unit.scala:154:28]
wire issue_slots_18_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_18_grant; // @[issue-unit.scala:154:28]
wire issue_slots_18_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_19_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_19_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_19_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_19_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_19_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_19_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_19_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_19_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_19_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_19_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_19_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_19_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_19_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_19_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_19_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_19_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_19_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_19_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_19_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_19_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_19_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_19_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_19_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_19_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_19_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_19_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_19_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_19_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_19_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_19_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_19_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_19_valid; // @[issue-unit.scala:154:28]
wire issue_slots_19_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_19_request; // @[issue-unit.scala:154:28]
wire issue_slots_19_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_19_grant; // @[issue-unit.scala:154:28]
wire issue_slots_19_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_20_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_20_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_20_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_20_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_20_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_20_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_20_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_20_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_20_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_20_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_20_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_20_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_20_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_20_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_20_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_20_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_20_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_20_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_20_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_20_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_20_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_20_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_20_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_20_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_20_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_20_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_20_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_20_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_20_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_20_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_20_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_20_valid; // @[issue-unit.scala:154:28]
wire issue_slots_20_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_20_request; // @[issue-unit.scala:154:28]
wire issue_slots_20_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_20_grant; // @[issue-unit.scala:154:28]
wire issue_slots_20_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_21_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_21_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_21_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_21_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_21_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_21_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_21_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_21_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_21_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_21_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_21_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_21_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_21_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_21_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_21_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_21_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_21_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_21_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_21_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_21_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_21_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_21_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_21_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_21_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_21_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_21_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_21_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_21_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_21_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_21_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_21_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_21_valid; // @[issue-unit.scala:154:28]
wire issue_slots_21_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_21_request; // @[issue-unit.scala:154:28]
wire issue_slots_21_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_21_grant; // @[issue-unit.scala:154:28]
wire issue_slots_21_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_22_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_22_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_22_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_22_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_22_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_22_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_22_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_22_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_22_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_22_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_22_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_22_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_22_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_22_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_22_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_22_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_22_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_22_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_22_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_22_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_22_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_22_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_22_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_22_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_22_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_22_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_22_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_22_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_22_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_22_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_22_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_22_valid; // @[issue-unit.scala:154:28]
wire issue_slots_22_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_22_request; // @[issue-unit.scala:154:28]
wire issue_slots_22_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_22_grant; // @[issue-unit.scala:154:28]
wire issue_slots_22_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_23_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_23_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_23_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_23_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_23_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_23_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_23_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_23_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_23_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_23_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_23_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_23_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_out_uop_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_23_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_23_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_23_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_23_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_23_uop_fu_code; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_23_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_23_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_23_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_23_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_uop_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_23_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_23_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_23_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_23_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_23_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_23_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_23_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_23_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_23_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_23_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_23_valid; // @[issue-unit.scala:154:28]
wire issue_slots_23_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_23_request; // @[issue-unit.scala:154:28]
wire issue_slots_23_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_23_grant; // @[issue-unit.scala:154:28]
wire issue_slots_23_clear; // @[issue-unit.scala:154:28]
wire _io_event_empty_T = issue_slots_0_valid | issue_slots_1_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_1 = _io_event_empty_T | issue_slots_2_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_2 = _io_event_empty_T_1 | issue_slots_3_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_3 = _io_event_empty_T_2 | issue_slots_4_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_4 = _io_event_empty_T_3 | issue_slots_5_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_5 = _io_event_empty_T_4 | issue_slots_6_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_6 = _io_event_empty_T_5 | issue_slots_7_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_7 = _io_event_empty_T_6 | issue_slots_8_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_8 = _io_event_empty_T_7 | issue_slots_9_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_9 = _io_event_empty_T_8 | issue_slots_10_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_10 = _io_event_empty_T_9 | issue_slots_11_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_11 = _io_event_empty_T_10 | issue_slots_12_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_12 = _io_event_empty_T_11 | issue_slots_13_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_13 = _io_event_empty_T_12 | issue_slots_14_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_14 = _io_event_empty_T_13 | issue_slots_15_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_15 = _io_event_empty_T_14 | issue_slots_16_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_16 = _io_event_empty_T_15 | issue_slots_17_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_17 = _io_event_empty_T_16 | issue_slots_18_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_18 = _io_event_empty_T_17 | issue_slots_19_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_19 = _io_event_empty_T_18 | issue_slots_20_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_20 = _io_event_empty_T_19 | issue_slots_21_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_21 = _io_event_empty_T_20 | issue_slots_22_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_22 = _io_event_empty_T_21 | issue_slots_23_valid; // @[issue-unit.scala:154:28, :165:61]
assign _io_event_empty_T_23 = ~_io_event_empty_T_22; // @[issue-unit.scala:165:{21,61}]
assign io_event_empty = _io_event_empty_T_23; // @[issue-unit.scala:165:21]
wire [1:0] _count_T = {1'h0, _slots_1_io_valid} + {1'h0, _slots_2_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_1 = _count_T; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_2 = {2'h0, _slots_0_io_valid} + {1'h0, _count_T_1}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_3 = _count_T_2[1:0]; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_4 = {1'h0, _slots_4_io_valid} + {1'h0, _slots_5_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_5 = _count_T_4; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_6 = {2'h0, _slots_3_io_valid} + {1'h0, _count_T_5}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_8 = {1'h0, _count_T_3} + {1'h0, _count_T_7}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_9 = _count_T_8; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_10 = {1'h0, _slots_7_io_valid} + {1'h0, _slots_8_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_11 = _count_T_10; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_12 = {2'h0, _slots_6_io_valid} + {1'h0, _count_T_11}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_13 = _count_T_12[1:0]; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_14 = {1'h0, _slots_10_io_valid} + {1'h0, _slots_11_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_15 = _count_T_14; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_16 = {2'h0, _slots_9_io_valid} + {1'h0, _count_T_15}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_17 = _count_T_16[1:0]; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_18 = {1'h0, _count_T_13} + {1'h0, _count_T_17}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_19 = _count_T_18; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_20 = {1'h0, _count_T_9} + {1'h0, _count_T_19}; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_21 = _count_T_20; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_22 = {1'h0, _slots_13_io_valid} + {1'h0, _slots_14_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_23 = _count_T_22; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_24 = {2'h0, _slots_12_io_valid} + {1'h0, _count_T_23}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_25 = _count_T_24[1:0]; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_26 = {1'h0, _slots_16_io_valid} + {1'h0, _slots_17_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_27 = _count_T_26; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_28 = {2'h0, _slots_15_io_valid} + {1'h0, _count_T_27}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_29 = _count_T_28[1:0]; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_30 = {1'h0, _count_T_25} + {1'h0, _count_T_29}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_31 = _count_T_30; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_32 = {1'h0, _slots_19_io_valid} + {1'h0, _slots_20_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_33 = _count_T_32; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_34 = {2'h0, _slots_18_io_valid} + {1'h0, _count_T_33}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_35 = _count_T_34[1:0]; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_36 = {1'h0, _slots_22_io_valid} + {1'h0, _slots_23_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_37 = _count_T_36; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_38 = {2'h0, _slots_21_io_valid} + {1'h0, _count_T_37}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_39 = _count_T_38[1:0]; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_40 = {1'h0, _count_T_35} + {1'h0, _count_T_39}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_41 = _count_T_40; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_42 = {1'h0, _count_T_31} + {1'h0, _count_T_41}; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_43 = _count_T_42; // @[issue-unit.scala:167:23]
wire [4:0] _count_T_44 = {1'h0, _count_T_21} + {1'h0, _count_T_43}; // @[issue-unit.scala:167:23]
wire [4:0] count = _count_T_44; // @[issue-unit.scala:167:23] |
Generate the Verilog code corresponding to this FIRRTL code module RenameStage_3 :
input clock : Clock
input reset : Reset
output io : { ren_stalls : UInt<1>[1], flip kill : UInt<1>, flip dec_fire : UInt<1>[1], flip dec_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], ren2_mask : UInt<1>[1], ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip dis_fire : UInt<1>[1], flip dis_ready : UInt<1>, flip wakeups : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[2], flip com_valids : UInt<1>[1], flip com_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip rbk_valids : UInt<1>[1], flip rollback : UInt<1>, flip debug_rob_empty : UInt<1>, debug : { freelist : UInt<48>, isprlist : UInt<48>, busytable : UInt<48>}}
connect io.ren_stalls[0], UInt<1>(0h0)
invalidate io.debug.busytable
invalidate io.debug.isprlist
invalidate io.debug.freelist
wire ren1_fire : UInt<1>[1]
wire ren1_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
wire ren2_valids : UInt<1>[1]
wire ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
wire ren2_alloc_reqs : UInt<1>[1]
connect ren1_fire[0], io.dec_fire[0]
connect ren1_uops[0], io.dec_uops[0]
regreset r_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire next_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect next_uop, r_uop
when io.kill :
connect r_valid, UInt<1>(0h0)
else :
when io.dis_ready :
connect r_valid, ren1_fire[0]
connect next_uop, ren1_uops[0]
else :
node _r_valid_T = eq(io.dis_fire[0], UInt<1>(0h0))
node _r_valid_T_1 = and(r_valid, _r_valid_T)
connect r_valid, _r_valid_T_1
connect next_uop, r_uop
wire r_uop_bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_bypassed_uop, next_uop
node _r_uop_bypass_hits_rs1_T = eq(ren2_uops[0].ldst, next_uop.lrs1)
node r_uop_bypass_hits_rs1_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs1_T)
node _r_uop_bypass_hits_rs2_T = eq(ren2_uops[0].ldst, next_uop.lrs2)
node r_uop_bypass_hits_rs2_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs2_T)
node _r_uop_bypass_hits_rs3_T = eq(ren2_uops[0].ldst, next_uop.lrs3)
node r_uop_bypass_hits_rs3_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_rs3_T)
node _r_uop_bypass_hits_dst_T = eq(ren2_uops[0].ldst, next_uop.ldst)
node r_uop_bypass_hits_dst_0 = and(ren2_alloc_reqs[0], _r_uop_bypass_hits_dst_T)
node r_uop_bypass_sel_rs1_enc = mux(r_uop_bypass_hits_rs1_0, UInt<1>(0h1), UInt<1>(0h0))
node r_uop_bypass_sel_rs1_0 = bits(r_uop_bypass_sel_rs1_enc, 0, 0)
node r_uop_bypass_sel_rs2_enc = mux(r_uop_bypass_hits_rs2_0, UInt<1>(0h1), UInt<1>(0h0))
node r_uop_bypass_sel_rs2_0 = bits(r_uop_bypass_sel_rs2_enc, 0, 0)
node r_uop_bypass_sel_rs3_enc = mux(r_uop_bypass_hits_rs3_0, UInt<1>(0h1), UInt<1>(0h0))
node r_uop_bypass_sel_rs3_0 = bits(r_uop_bypass_sel_rs3_enc, 0, 0)
node r_uop_bypass_sel_dst_enc = mux(r_uop_bypass_hits_dst_0, UInt<1>(0h1), UInt<1>(0h0))
node r_uop_bypass_sel_dst_0 = bits(r_uop_bypass_sel_dst_enc, 0, 0)
when r_uop_bypass_hits_rs1_0 :
connect r_uop_bypassed_uop.prs1, ren2_uops[0].pdst
when r_uop_bypass_hits_rs2_0 :
connect r_uop_bypassed_uop.prs2, ren2_uops[0].pdst
when r_uop_bypass_hits_rs3_0 :
connect r_uop_bypassed_uop.prs3, ren2_uops[0].pdst
when r_uop_bypass_hits_dst_0 :
connect r_uop_bypassed_uop.stale_pdst, ren2_uops[0].pdst
node _r_uop_bypassed_uop_prs1_busy_T = or(next_uop.prs1_busy, r_uop_bypass_hits_rs1_0)
connect r_uop_bypassed_uop.prs1_busy, _r_uop_bypassed_uop_prs1_busy_T
node _r_uop_bypassed_uop_prs2_busy_T = or(next_uop.prs2_busy, r_uop_bypass_hits_rs2_0)
connect r_uop_bypassed_uop.prs2_busy, _r_uop_bypassed_uop_prs2_busy_T
node _r_uop_bypassed_uop_prs3_busy_T = or(next_uop.prs3_busy, r_uop_bypass_hits_rs3_0)
connect r_uop_bypassed_uop.prs3_busy, _r_uop_bypassed_uop_prs3_busy_T
wire r_uop_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_newuop, r_uop_bypassed_uop
node _r_uop_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uop_newuop_br_mask_T_1 = and(r_uop_bypassed_uop.br_mask, _r_uop_newuop_br_mask_T)
connect r_uop_newuop.br_mask, _r_uop_newuop_br_mask_T_1
connect r_uop, r_uop_newuop
connect ren2_valids[0], r_valid
connect ren2_uops[0], r_uop
connect io.ren2_mask, ren2_valids
inst maptable of RenameMapTable_3
connect maptable.clock, clock
connect maptable.reset, reset
inst freelist of RenameFreeList_3
connect freelist.clock, clock
connect freelist.reset, reset
inst busytable of RenameBusyTable_3
connect busytable.clock, clock
connect busytable.reset, reset
wire ren2_br_tags : { valid : UInt<1>, bits : UInt<3>}[1]
wire com_valids : UInt<1>[1]
wire rbk_valids : UInt<1>[1]
node _ren2_alloc_reqs_0_T = eq(ren2_uops[0].dst_rtype, UInt<2>(0h1))
node _ren2_alloc_reqs_0_T_1 = and(ren2_uops[0].ldst_val, _ren2_alloc_reqs_0_T)
node _ren2_alloc_reqs_0_T_2 = and(_ren2_alloc_reqs_0_T_1, io.dis_fire[0])
connect ren2_alloc_reqs[0], _ren2_alloc_reqs_0_T_2
node _ren2_br_tags_0_valid_T = eq(ren2_uops[0].is_sfb, UInt<1>(0h0))
node _ren2_br_tags_0_valid_T_1 = and(ren2_uops[0].is_br, _ren2_br_tags_0_valid_T)
node _ren2_br_tags_0_valid_T_2 = or(_ren2_br_tags_0_valid_T_1, ren2_uops[0].is_jalr)
node _ren2_br_tags_0_valid_T_3 = and(io.dis_fire[0], _ren2_br_tags_0_valid_T_2)
connect ren2_br_tags[0].valid, _ren2_br_tags_0_valid_T_3
node _com_valids_0_T = eq(io.com_uops[0].dst_rtype, UInt<2>(0h1))
node _com_valids_0_T_1 = and(io.com_uops[0].ldst_val, _com_valids_0_T)
node _com_valids_0_T_2 = and(_com_valids_0_T_1, io.com_valids[0])
connect com_valids[0], _com_valids_0_T_2
node _rbk_valids_0_T = eq(io.com_uops[0].dst_rtype, UInt<2>(0h1))
node _rbk_valids_0_T_1 = and(io.com_uops[0].ldst_val, _rbk_valids_0_T)
node _rbk_valids_0_T_2 = and(_rbk_valids_0_T_1, io.rbk_valids[0])
connect rbk_valids[0], _rbk_valids_0_T_2
connect ren2_br_tags[0].bits, ren2_uops[0].br_tag
wire map_reqs : { lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst : UInt<6>}[1]
wire remap_reqs : { ldst : UInt<6>, pdst : UInt<6>, valid : UInt<1>}[1]
connect map_reqs[0].lrs1, ren1_uops[0].lrs1
connect map_reqs[0].lrs2, ren1_uops[0].lrs2
connect map_reqs[0].lrs3, ren1_uops[0].lrs3
connect map_reqs[0].ldst, ren1_uops[0].ldst
node _remap_reqs_0_ldst_T = mux(io.rollback, io.com_uops[0].ldst, ren2_uops[0].ldst)
connect remap_reqs[0].ldst, _remap_reqs_0_ldst_T
node _remap_reqs_0_pdst_T = mux(io.rollback, io.com_uops[0].stale_pdst, ren2_uops[0].pdst)
connect remap_reqs[0].pdst, _remap_reqs_0_pdst_T
node _remap_reqs_0_valid_T = or(ren2_alloc_reqs[0], rbk_valids[0])
connect remap_reqs[0].valid, _remap_reqs_0_valid_T
connect maptable.io.map_reqs[0].ldst, map_reqs[0].ldst
connect maptable.io.map_reqs[0].lrs3, map_reqs[0].lrs3
connect maptable.io.map_reqs[0].lrs2, map_reqs[0].lrs2
connect maptable.io.map_reqs[0].lrs1, map_reqs[0].lrs1
connect maptable.io.remap_reqs[0].valid, remap_reqs[0].valid
connect maptable.io.remap_reqs[0].pdst, remap_reqs[0].pdst
connect maptable.io.remap_reqs[0].ldst, remap_reqs[0].ldst
connect maptable.io.ren_br_tags[0].bits, ren2_br_tags[0].bits
connect maptable.io.ren_br_tags[0].valid, ren2_br_tags[0].valid
connect maptable.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect maptable.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect maptable.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect maptable.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect maptable.io.brupdate.b2.taken, io.brupdate.b2.taken
connect maptable.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect maptable.io.brupdate.b2.valid, io.brupdate.b2.valid
connect maptable.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect maptable.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect maptable.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect maptable.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect maptable.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect maptable.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect maptable.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect maptable.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect maptable.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect maptable.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect maptable.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect maptable.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect maptable.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect maptable.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect maptable.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect maptable.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect maptable.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect maptable.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect maptable.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect maptable.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect maptable.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect maptable.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect maptable.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect maptable.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect maptable.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect maptable.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect maptable.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect maptable.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect maptable.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect maptable.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect maptable.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect maptable.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect maptable.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect maptable.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect maptable.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect maptable.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect maptable.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect maptable.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect maptable.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect maptable.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect maptable.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect maptable.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect maptable.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect maptable.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect maptable.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect maptable.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect maptable.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect maptable.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect maptable.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect maptable.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect maptable.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect maptable.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect maptable.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect maptable.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect maptable.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect maptable.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect maptable.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect maptable.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect maptable.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect maptable.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect maptable.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect maptable.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect maptable.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect maptable.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect maptable.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect maptable.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect maptable.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect maptable.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect maptable.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect maptable.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect maptable.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect maptable.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect maptable.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect maptable.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect maptable.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect maptable.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect maptable.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect maptable.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect maptable.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect maptable.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect maptable.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect maptable.io.rollback, io.rollback
connect ren1_uops[0].prs1, maptable.io.map_resps[0].prs1
connect ren1_uops[0].prs2, maptable.io.map_resps[0].prs2
connect ren1_uops[0].prs3, maptable.io.map_resps[0].prs3
connect ren1_uops[0].stale_pdst, maptable.io.map_resps[0].stale_pdst
connect freelist.io.reqs[0], ren2_alloc_reqs[0]
node _freelist_io_dealloc_pregs_0_valid_T = or(com_valids[0], rbk_valids[0])
connect freelist.io.dealloc_pregs[0].valid, _freelist_io_dealloc_pregs_0_valid_T
node _freelist_io_dealloc_pregs_0_bits_T = mux(io.rollback, io.com_uops[0].pdst, io.com_uops[0].stale_pdst)
connect freelist.io.dealloc_pregs[0].bits, _freelist_io_dealloc_pregs_0_bits_T
connect freelist.io.ren_br_tags[0].bits, ren2_br_tags[0].bits
connect freelist.io.ren_br_tags[0].valid, ren2_br_tags[0].valid
connect freelist.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect freelist.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect freelist.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect freelist.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect freelist.io.brupdate.b2.taken, io.brupdate.b2.taken
connect freelist.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect freelist.io.brupdate.b2.valid, io.brupdate.b2.valid
connect freelist.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect freelist.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect freelist.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect freelist.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect freelist.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect freelist.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect freelist.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect freelist.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect freelist.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect freelist.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect freelist.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect freelist.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect freelist.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect freelist.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect freelist.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect freelist.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect freelist.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect freelist.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect freelist.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect freelist.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect freelist.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect freelist.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect freelist.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect freelist.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect freelist.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect freelist.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect freelist.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect freelist.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect freelist.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect freelist.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect freelist.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect freelist.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect freelist.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect freelist.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect freelist.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect freelist.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect freelist.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect freelist.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect freelist.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect freelist.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect freelist.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect freelist.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect freelist.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect freelist.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect freelist.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect freelist.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect freelist.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect freelist.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect freelist.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect freelist.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect freelist.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect freelist.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect freelist.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect freelist.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect freelist.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect freelist.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect freelist.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect freelist.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect freelist.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect freelist.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect freelist.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect freelist.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect freelist.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect freelist.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect freelist.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect freelist.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect freelist.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect freelist.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect freelist.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect freelist.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect freelist.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect freelist.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect freelist.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect freelist.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect freelist.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect freelist.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect freelist.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect freelist.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect freelist.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect freelist.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect freelist.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect freelist.io.debug.pipeline_empty, io.debug_rob_empty
node _T = eq(ren2_alloc_reqs[0], UInt<1>(0h0))
node _T_1 = neq(freelist.io.alloc_pregs[0].bits, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename-stage] A uop is trying to allocate the zero physical register.\n at rename-stage.scala:300 assert (ren2_alloc_reqs zip freelist.io.alloc_pregs map {case (r,p) => !r || p.bits =/= 0.U} reduce (_&&_),\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _ren2_uops_0_pdst_T = neq(ren2_uops[0].ldst, UInt<1>(0h0))
node _ren2_uops_0_pdst_T_1 = or(_ren2_uops_0_pdst_T, UInt<1>(0h1))
node _ren2_uops_0_pdst_T_2 = mux(_ren2_uops_0_pdst_T_1, freelist.io.alloc_pregs[0].bits, UInt<1>(0h0))
connect ren2_uops[0].pdst, _ren2_uops_0_pdst_T_2
connect busytable.io.ren_uops[0].debug_tsrc, ren2_uops[0].debug_tsrc
connect busytable.io.ren_uops[0].debug_fsrc, ren2_uops[0].debug_fsrc
connect busytable.io.ren_uops[0].bp_xcpt_if, ren2_uops[0].bp_xcpt_if
connect busytable.io.ren_uops[0].bp_debug_if, ren2_uops[0].bp_debug_if
connect busytable.io.ren_uops[0].xcpt_ma_if, ren2_uops[0].xcpt_ma_if
connect busytable.io.ren_uops[0].xcpt_ae_if, ren2_uops[0].xcpt_ae_if
connect busytable.io.ren_uops[0].xcpt_pf_if, ren2_uops[0].xcpt_pf_if
connect busytable.io.ren_uops[0].fp_single, ren2_uops[0].fp_single
connect busytable.io.ren_uops[0].fp_val, ren2_uops[0].fp_val
connect busytable.io.ren_uops[0].frs3_en, ren2_uops[0].frs3_en
connect busytable.io.ren_uops[0].lrs2_rtype, ren2_uops[0].lrs2_rtype
connect busytable.io.ren_uops[0].lrs1_rtype, ren2_uops[0].lrs1_rtype
connect busytable.io.ren_uops[0].dst_rtype, ren2_uops[0].dst_rtype
connect busytable.io.ren_uops[0].ldst_val, ren2_uops[0].ldst_val
connect busytable.io.ren_uops[0].lrs3, ren2_uops[0].lrs3
connect busytable.io.ren_uops[0].lrs2, ren2_uops[0].lrs2
connect busytable.io.ren_uops[0].lrs1, ren2_uops[0].lrs1
connect busytable.io.ren_uops[0].ldst, ren2_uops[0].ldst
connect busytable.io.ren_uops[0].ldst_is_rs1, ren2_uops[0].ldst_is_rs1
connect busytable.io.ren_uops[0].flush_on_commit, ren2_uops[0].flush_on_commit
connect busytable.io.ren_uops[0].is_unique, ren2_uops[0].is_unique
connect busytable.io.ren_uops[0].is_sys_pc2epc, ren2_uops[0].is_sys_pc2epc
connect busytable.io.ren_uops[0].uses_stq, ren2_uops[0].uses_stq
connect busytable.io.ren_uops[0].uses_ldq, ren2_uops[0].uses_ldq
connect busytable.io.ren_uops[0].is_amo, ren2_uops[0].is_amo
connect busytable.io.ren_uops[0].is_fencei, ren2_uops[0].is_fencei
connect busytable.io.ren_uops[0].is_fence, ren2_uops[0].is_fence
connect busytable.io.ren_uops[0].mem_signed, ren2_uops[0].mem_signed
connect busytable.io.ren_uops[0].mem_size, ren2_uops[0].mem_size
connect busytable.io.ren_uops[0].mem_cmd, ren2_uops[0].mem_cmd
connect busytable.io.ren_uops[0].bypassable, ren2_uops[0].bypassable
connect busytable.io.ren_uops[0].exc_cause, ren2_uops[0].exc_cause
connect busytable.io.ren_uops[0].exception, ren2_uops[0].exception
connect busytable.io.ren_uops[0].stale_pdst, ren2_uops[0].stale_pdst
connect busytable.io.ren_uops[0].ppred_busy, ren2_uops[0].ppred_busy
connect busytable.io.ren_uops[0].prs3_busy, ren2_uops[0].prs3_busy
connect busytable.io.ren_uops[0].prs2_busy, ren2_uops[0].prs2_busy
connect busytable.io.ren_uops[0].prs1_busy, ren2_uops[0].prs1_busy
connect busytable.io.ren_uops[0].ppred, ren2_uops[0].ppred
connect busytable.io.ren_uops[0].prs3, ren2_uops[0].prs3
connect busytable.io.ren_uops[0].prs2, ren2_uops[0].prs2
connect busytable.io.ren_uops[0].prs1, ren2_uops[0].prs1
connect busytable.io.ren_uops[0].pdst, ren2_uops[0].pdst
connect busytable.io.ren_uops[0].rxq_idx, ren2_uops[0].rxq_idx
connect busytable.io.ren_uops[0].stq_idx, ren2_uops[0].stq_idx
connect busytable.io.ren_uops[0].ldq_idx, ren2_uops[0].ldq_idx
connect busytable.io.ren_uops[0].rob_idx, ren2_uops[0].rob_idx
connect busytable.io.ren_uops[0].csr_addr, ren2_uops[0].csr_addr
connect busytable.io.ren_uops[0].imm_packed, ren2_uops[0].imm_packed
connect busytable.io.ren_uops[0].taken, ren2_uops[0].taken
connect busytable.io.ren_uops[0].pc_lob, ren2_uops[0].pc_lob
connect busytable.io.ren_uops[0].edge_inst, ren2_uops[0].edge_inst
connect busytable.io.ren_uops[0].ftq_idx, ren2_uops[0].ftq_idx
connect busytable.io.ren_uops[0].br_tag, ren2_uops[0].br_tag
connect busytable.io.ren_uops[0].br_mask, ren2_uops[0].br_mask
connect busytable.io.ren_uops[0].is_sfb, ren2_uops[0].is_sfb
connect busytable.io.ren_uops[0].is_jal, ren2_uops[0].is_jal
connect busytable.io.ren_uops[0].is_jalr, ren2_uops[0].is_jalr
connect busytable.io.ren_uops[0].is_br, ren2_uops[0].is_br
connect busytable.io.ren_uops[0].iw_p2_poisoned, ren2_uops[0].iw_p2_poisoned
connect busytable.io.ren_uops[0].iw_p1_poisoned, ren2_uops[0].iw_p1_poisoned
connect busytable.io.ren_uops[0].iw_state, ren2_uops[0].iw_state
connect busytable.io.ren_uops[0].ctrl.is_std, ren2_uops[0].ctrl.is_std
connect busytable.io.ren_uops[0].ctrl.is_sta, ren2_uops[0].ctrl.is_sta
connect busytable.io.ren_uops[0].ctrl.is_load, ren2_uops[0].ctrl.is_load
connect busytable.io.ren_uops[0].ctrl.csr_cmd, ren2_uops[0].ctrl.csr_cmd
connect busytable.io.ren_uops[0].ctrl.fcn_dw, ren2_uops[0].ctrl.fcn_dw
connect busytable.io.ren_uops[0].ctrl.op_fcn, ren2_uops[0].ctrl.op_fcn
connect busytable.io.ren_uops[0].ctrl.imm_sel, ren2_uops[0].ctrl.imm_sel
connect busytable.io.ren_uops[0].ctrl.op2_sel, ren2_uops[0].ctrl.op2_sel
connect busytable.io.ren_uops[0].ctrl.op1_sel, ren2_uops[0].ctrl.op1_sel
connect busytable.io.ren_uops[0].ctrl.br_type, ren2_uops[0].ctrl.br_type
connect busytable.io.ren_uops[0].fu_code, ren2_uops[0].fu_code
connect busytable.io.ren_uops[0].iq_type, ren2_uops[0].iq_type
connect busytable.io.ren_uops[0].debug_pc, ren2_uops[0].debug_pc
connect busytable.io.ren_uops[0].is_rvc, ren2_uops[0].is_rvc
connect busytable.io.ren_uops[0].debug_inst, ren2_uops[0].debug_inst
connect busytable.io.ren_uops[0].inst, ren2_uops[0].inst
connect busytable.io.ren_uops[0].uopc, ren2_uops[0].uopc
connect busytable.io.rebusy_reqs[0], ren2_alloc_reqs[0]
connect busytable.io.wb_valids[0], io.wakeups[0].valid
connect busytable.io.wb_valids[1], io.wakeups[1].valid
connect busytable.io.wb_pdsts[0], io.wakeups[0].bits.uop.pdst
connect busytable.io.wb_pdsts[1], io.wakeups[1].bits.uop.pdst
node _T_6 = neq(io.wakeups[0].bits.uop.dst_rtype, UInt<2>(0h1))
node _T_7 = and(io.wakeups[0].valid, _T_6)
node _T_8 = neq(io.wakeups[1].bits.uop.dst_rtype, UInt<2>(0h1))
node _T_9 = and(io.wakeups[1].valid, _T_8)
node _T_10 = or(_T_7, _T_9)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] Wakeup has wrong rtype.\n at rename-stage.scala:317 assert (!(io.wakeups.map(x => x.valid && x.bits.uop.dst_rtype =/= rtype).reduce(_||_)),\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _ren2_uops_0_prs1_busy_T = eq(ren2_uops[0].lrs1_rtype, UInt<2>(0h1))
node _ren2_uops_0_prs1_busy_T_1 = and(_ren2_uops_0_prs1_busy_T, busytable.io.busy_resps[0].prs1_busy)
connect ren2_uops[0].prs1_busy, _ren2_uops_0_prs1_busy_T_1
node _ren2_uops_0_prs2_busy_T = eq(ren2_uops[0].lrs2_rtype, UInt<2>(0h1))
node _ren2_uops_0_prs2_busy_T_1 = and(_ren2_uops_0_prs2_busy_T, busytable.io.busy_resps[0].prs2_busy)
connect ren2_uops[0].prs2_busy, _ren2_uops_0_prs2_busy_T_1
node _ren2_uops_0_prs3_busy_T = and(ren2_uops[0].frs3_en, busytable.io.busy_resps[0].prs3_busy)
connect ren2_uops[0].prs3_busy, _ren2_uops_0_prs3_busy_T
node _T_15 = and(ren2_valids[0], busytable.io.busy_resps[0].prs1_busy)
node _T_16 = eq(UInt<2>(0h1), UInt<2>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(ren2_uops[0].lrs1, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(_T_19, UInt<1>(0h0))
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:328 assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n") : printf_2
assert(clock, _T_20, UInt<1>(0h1), "") : assert_2
node _T_24 = and(ren2_valids[0], busytable.io.busy_resps[0].prs2_busy)
node _T_25 = eq(UInt<2>(0h1), UInt<2>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(ren2_uops[0].lrs2, UInt<1>(0h0))
node _T_28 = and(_T_26, _T_27)
node _T_29 = eq(_T_28, UInt<1>(0h0))
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rename] x0 is busy??\n at rename-stage.scala:329 assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n") : printf_3
assert(clock, _T_29, UInt<1>(0h1), "") : assert_3
node _io_ren_stalls_0_T = eq(ren2_uops[0].dst_rtype, UInt<2>(0h1))
node _io_ren_stalls_0_T_1 = eq(freelist.io.alloc_pregs[0].valid, UInt<1>(0h0))
node _io_ren_stalls_0_T_2 = and(_io_ren_stalls_0_T, _io_ren_stalls_0_T_1)
connect io.ren_stalls[0], _io_ren_stalls_0_T_2
wire bypassed_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect bypassed_uop, ren2_uops[0]
wire io_ren2_uops_0_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect io_ren2_uops_0_newuop, bypassed_uop
node _io_ren2_uops_0_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_ren2_uops_0_newuop_br_mask_T_1 = and(bypassed_uop.br_mask, _io_ren2_uops_0_newuop_br_mask_T)
connect io_ren2_uops_0_newuop.br_mask, _io_ren2_uops_0_newuop_br_mask_T_1
connect io.ren2_uops[0], io_ren2_uops_0_newuop
connect io.debug.freelist, freelist.io.debug.freelist
connect io.debug.isprlist, freelist.io.debug.isprlist
connect io.debug.busytable, busytable.io.debug.busytable | module RenameStage_3( // @[rename-stage.scala:160:7]
input clock, // @[rename-stage.scala:160:7]
input reset, // @[rename-stage.scala:160:7]
output io_ren_stalls_0, // @[rename-stage.scala:60:14]
input io_kill, // @[rename-stage.scala:60:14]
input io_dec_fire_0, // @[rename-stage.scala:60:14]
input [6:0] io_dec_uops_0_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_0_inst, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_0_debug_inst, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_dec_uops_0_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_dec_uops_0_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_dec_uops_0_fu_code, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_br, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_jalr, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_jal, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_dec_uops_0_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_dec_uops_0_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_dec_uops_0_ftq_idx, // @[rename-stage.scala:60:14]
input io_dec_uops_0_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_pc_lob, // @[rename-stage.scala:60:14]
input io_dec_uops_0_taken, // @[rename-stage.scala:60:14]
input [19:0] io_dec_uops_0_imm_packed, // @[rename-stage.scala:60:14]
input io_dec_uops_0_exception, // @[rename-stage.scala:60:14]
input [63:0] io_dec_uops_0_exc_cause, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_0_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_mem_size, // @[rename-stage.scala:60:14]
input io_dec_uops_0_mem_signed, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_fence, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_fencei, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_amo, // @[rename-stage.scala:60:14]
input io_dec_uops_0_uses_ldq, // @[rename-stage.scala:60:14]
input io_dec_uops_0_uses_stq, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_unique, // @[rename-stage.scala:60:14]
input io_dec_uops_0_flush_on_commit, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs3, // @[rename-stage.scala:60:14]
input io_dec_uops_0_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_dec_uops_0_frs3_en, // @[rename-stage.scala:60:14]
input io_dec_uops_0_fp_val, // @[rename-stage.scala:60:14]
input io_dec_uops_0_fp_single, // @[rename-stage.scala:60:14]
input io_dec_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bp_debug_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_debug_fsrc, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_pdst, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_prs1, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_prs2, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_prs3, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_prs1_busy, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_prs2_busy, // @[rename-stage.scala:60:14]
output io_ren2_uops_0_prs3_busy, // @[rename-stage.scala:60:14]
output [5:0] io_ren2_uops_0_stale_pdst, // @[rename-stage.scala:60:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[rename-stage.scala:60:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_br, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_jal, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_fence, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_amo, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_unique, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_fp_val, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_fp_single, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_brupdate_b2_valid, // @[rename-stage.scala:60:14]
input io_brupdate_b2_mispredict, // @[rename-stage.scala:60:14]
input io_brupdate_b2_taken, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rename-stage.scala:60:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rename-stage.scala:60:14]
input [20:0] io_brupdate_b2_target_offset, // @[rename-stage.scala:60:14]
input io_dis_fire_0, // @[rename-stage.scala:60:14]
input io_dis_ready, // @[rename-stage.scala:60:14]
input io_wakeups_0_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_0_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_wakeups_0_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_0_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_0_bits_data, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_predicated, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_0_bits_fflags_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_fflags_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_0_bits_fflags_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_0_bits_fflags_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_0_bits_fflags_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_wakeups_0_bits_fflags_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_fflags_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_0_bits_fflags_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_0_bits_fflags_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_0_bits_fflags_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_0_bits_fflags_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_0_bits_fflags_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_0_bits_fflags_bits_flags, // @[rename-stage.scala:60:14]
input io_wakeups_1_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_1_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_wakeups_1_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_1_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_1_bits_data, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_valid, // @[rename-stage.scala:60:14]
input [6:0] io_wakeups_1_bits_fflags_bits_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_1_bits_fflags_bits_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_wakeups_1_bits_fflags_bits_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_wakeups_1_bits_fflags_bits_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_fflags_bits_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_wakeups_1_bits_fflags_bits_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_iw_state, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_br, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_jal, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_wakeups_1_bits_fflags_bits_uop_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_fflags_bits_uop_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_fflags_bits_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_wakeups_1_bits_fflags_bits_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_wakeups_1_bits_fflags_bits_uop_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_fflags_bits_uop_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_fflags_bits_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_wakeups_1_bits_fflags_bits_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_wakeups_1_bits_fflags_bits_uop_ppred, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_wakeups_1_bits_fflags_bits_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_fflags_bits_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_mem_size, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_fence, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_amo, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_is_unique, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs3, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_fp_val, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_fp_single, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input [4:0] io_wakeups_1_bits_fflags_bits_flags, // @[rename-stage.scala:60:14]
input io_com_valids_0, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_0_inst, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_0_debug_inst, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_com_uops_0_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_com_uops_0_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_iw_state, // @[rename-stage.scala:60:14]
input io_com_uops_0_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_0_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_br, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_jalr, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_jal, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_com_uops_0_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_ftq_idx, // @[rename-stage.scala:60:14]
input io_com_uops_0_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_pc_lob, // @[rename-stage.scala:60:14]
input io_com_uops_0_taken, // @[rename-stage.scala:60:14]
input [19:0] io_com_uops_0_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_com_uops_0_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_ppred, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs1_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs2_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs3_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_stale_pdst, // @[rename-stage.scala:60:14]
input io_com_uops_0_exception, // @[rename-stage.scala:60:14]
input [63:0] io_com_uops_0_exc_cause, // @[rename-stage.scala:60:14]
input io_com_uops_0_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_mem_size, // @[rename-stage.scala:60:14]
input io_com_uops_0_mem_signed, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_fence, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_fencei, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_amo, // @[rename-stage.scala:60:14]
input io_com_uops_0_uses_ldq, // @[rename-stage.scala:60:14]
input io_com_uops_0_uses_stq, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_unique, // @[rename-stage.scala:60:14]
input io_com_uops_0_flush_on_commit, // @[rename-stage.scala:60:14]
input io_com_uops_0_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs3, // @[rename-stage.scala:60:14]
input io_com_uops_0_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_com_uops_0_frs3_en, // @[rename-stage.scala:60:14]
input io_com_uops_0_fp_val, // @[rename-stage.scala:60:14]
input io_com_uops_0_fp_single, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_bp_debug_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_debug_tsrc, // @[rename-stage.scala:60:14]
input io_rbk_valids_0, // @[rename-stage.scala:60:14]
input io_rollback, // @[rename-stage.scala:60:14]
input io_debug_rob_empty // @[rename-stage.scala:60:14]
);
wire [5:0] r_uop_bypassed_uop_stale_pdst; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_prs3_busy; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_prs2_busy; // @[rename-stage.scala:174:28]
wire r_uop_bypassed_uop_prs1_busy; // @[rename-stage.scala:174:28]
wire [5:0] r_uop_bypassed_uop_prs3; // @[rename-stage.scala:174:28]
wire [5:0] r_uop_bypassed_uop_prs2; // @[rename-stage.scala:174:28]
wire [5:0] r_uop_bypassed_uop_prs1; // @[rename-stage.scala:174:28]
wire [1:0] next_uop_debug_tsrc; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_debug_fsrc; // @[rename-stage.scala:123:24]
wire next_uop_bp_xcpt_if; // @[rename-stage.scala:123:24]
wire next_uop_bp_debug_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_ma_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_ae_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_pf_if; // @[rename-stage.scala:123:24]
wire next_uop_fp_single; // @[rename-stage.scala:123:24]
wire next_uop_fp_val; // @[rename-stage.scala:123:24]
wire next_uop_frs3_en; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_lrs2_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_lrs1_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_dst_rtype; // @[rename-stage.scala:123:24]
wire next_uop_ldst_val; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs3; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs2; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs1; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_ldst; // @[rename-stage.scala:123:24]
wire next_uop_ldst_is_rs1; // @[rename-stage.scala:123:24]
wire next_uop_flush_on_commit; // @[rename-stage.scala:123:24]
wire next_uop_is_unique; // @[rename-stage.scala:123:24]
wire next_uop_is_sys_pc2epc; // @[rename-stage.scala:123:24]
wire next_uop_uses_stq; // @[rename-stage.scala:123:24]
wire next_uop_uses_ldq; // @[rename-stage.scala:123:24]
wire next_uop_is_amo; // @[rename-stage.scala:123:24]
wire next_uop_is_fencei; // @[rename-stage.scala:123:24]
wire next_uop_is_fence; // @[rename-stage.scala:123:24]
wire next_uop_mem_signed; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_mem_size; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_mem_cmd; // @[rename-stage.scala:123:24]
wire next_uop_bypassable; // @[rename-stage.scala:123:24]
wire [63:0] next_uop_exc_cause; // @[rename-stage.scala:123:24]
wire next_uop_exception; // @[rename-stage.scala:123:24]
wire next_uop_ppred_busy; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_ppred; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_pdst; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_rxq_idx; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_stq_idx; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ldq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_rob_idx; // @[rename-stage.scala:123:24]
wire [11:0] next_uop_csr_addr; // @[rename-stage.scala:123:24]
wire [19:0] next_uop_imm_packed; // @[rename-stage.scala:123:24]
wire next_uop_taken; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_pc_lob; // @[rename-stage.scala:123:24]
wire next_uop_edge_inst; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_ftq_idx; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_br_tag; // @[rename-stage.scala:123:24]
wire [7:0] next_uop_br_mask; // @[rename-stage.scala:123:24]
wire next_uop_is_sfb; // @[rename-stage.scala:123:24]
wire next_uop_is_jal; // @[rename-stage.scala:123:24]
wire next_uop_is_jalr; // @[rename-stage.scala:123:24]
wire next_uop_is_br; // @[rename-stage.scala:123:24]
wire next_uop_iw_p2_poisoned; // @[rename-stage.scala:123:24]
wire next_uop_iw_p1_poisoned; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_iw_state; // @[rename-stage.scala:123:24]
wire [9:0] next_uop_fu_code; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_iq_type; // @[rename-stage.scala:123:24]
wire [39:0] next_uop_debug_pc; // @[rename-stage.scala:123:24]
wire next_uop_is_rvc; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_debug_inst; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_inst; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_uopc; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_std; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_sta; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_load; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_csr_cmd; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_fcn_dw; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_ctrl_op_fcn; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_imm_sel; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_op2_sel; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_ctrl_op1_sel; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_ctrl_br_type; // @[rename-stage.scala:123:24]
wire [1:0] ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_fp_single; // @[rename-stage.scala:108:29]
wire ren2_uops_0_fp_val; // @[rename-stage.scala:108:29]
wire ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs3; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs2; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_ldst; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29]
wire ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_unique; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29]
wire ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_amo; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_fence; // @[rename-stage.scala:108:29]
wire ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_mem_size; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bypassable; // @[rename-stage.scala:108:29]
wire [63:0] ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29]
wire ren2_uops_0_exception; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs3_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_ppred; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_prs3; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_prs2; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_prs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_pdst; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29]
wire [11:0] ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29]
wire [19:0] ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29]
wire ren2_uops_0_taken; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29]
wire ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_br_tag; // @[rename-stage.scala:108:29]
wire [7:0] ren2_uops_0_br_mask; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_jal; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_br; // @[rename-stage.scala:108:29]
wire ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29]
wire ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_iw_state; // @[rename-stage.scala:108:29]
wire [9:0] ren2_uops_0_fu_code; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_iq_type; // @[rename-stage.scala:108:29]
wire [39:0] ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_0_inst; // @[rename-stage.scala:108:29]
wire [6:0] ren2_uops_0_uopc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29]
wire _busytable_io_busy_resps_0_prs1_busy; // @[rename-stage.scala:224:25]
wire _busytable_io_busy_resps_0_prs2_busy; // @[rename-stage.scala:224:25]
wire _busytable_io_busy_resps_0_prs3_busy; // @[rename-stage.scala:224:25]
wire _freelist_io_alloc_pregs_0_valid; // @[rename-stage.scala:220:24]
wire [5:0] _freelist_io_alloc_pregs_0_bits; // @[rename-stage.scala:220:24]
wire io_kill_0 = io_kill; // @[rename-stage.scala:160:7]
wire io_dec_fire_0_0 = io_dec_fire_0; // @[rename-stage.scala:160:7]
wire [6:0] io_dec_uops_0_uopc_0 = io_dec_uops_0_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_0_inst_0 = io_dec_uops_0_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_dec_uops_0_debug_inst_0 = io_dec_uops_0_debug_inst; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_rvc_0 = io_dec_uops_0_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_dec_uops_0_debug_pc_0 = io_dec_uops_0_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_iq_type_0 = io_dec_uops_0_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_dec_uops_0_fu_code_0 = io_dec_uops_0_fu_code; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_br_0 = io_dec_uops_0_is_br; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_jalr_0 = io_dec_uops_0_is_jalr; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_jal_0 = io_dec_uops_0_is_jal; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_sfb_0 = io_dec_uops_0_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_dec_uops_0_br_mask_0 = io_dec_uops_0_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_br_tag_0 = io_dec_uops_0_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_0_ftq_idx_0 = io_dec_uops_0_ftq_idx; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_edge_inst_0 = io_dec_uops_0_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_pc_lob_0 = io_dec_uops_0_pc_lob; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_taken_0 = io_dec_uops_0_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_dec_uops_0_imm_packed_0 = io_dec_uops_0_imm_packed; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_exception_0 = io_dec_uops_0_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_dec_uops_0_exc_cause_0 = io_dec_uops_0_exc_cause; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_bypassable_0 = io_dec_uops_0_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_0_mem_cmd_0 = io_dec_uops_0_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_mem_size_0 = io_dec_uops_0_mem_size; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_mem_signed_0 = io_dec_uops_0_mem_signed; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_fence_0 = io_dec_uops_0_is_fence; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_fencei_0 = io_dec_uops_0_is_fencei; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_amo_0 = io_dec_uops_0_is_amo; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_uses_ldq_0 = io_dec_uops_0_uses_ldq; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_uses_stq_0 = io_dec_uops_0_uses_stq; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_sys_pc2epc_0 = io_dec_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_is_unique_0 = io_dec_uops_0_is_unique; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_flush_on_commit_0 = io_dec_uops_0_flush_on_commit; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_ldst_0 = io_dec_uops_0_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_lrs1_0 = io_dec_uops_0_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_lrs2_0 = io_dec_uops_0_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_lrs3_0 = io_dec_uops_0_lrs3; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ldst_val_0 = io_dec_uops_0_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_dst_rtype_0 = io_dec_uops_0_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_lrs1_rtype_0 = io_dec_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_lrs2_rtype_0 = io_dec_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_frs3_en_0 = io_dec_uops_0_frs3_en; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_fp_val_0 = io_dec_uops_0_fp_val; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_fp_single_0 = io_dec_uops_0_fp_single; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_xcpt_pf_if_0 = io_dec_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_xcpt_ae_if_0 = io_dec_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_bp_debug_if_0 = io_dec_uops_0_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_bp_xcpt_if_0 = io_dec_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_debug_fsrc_0 = io_dec_uops_0_debug_fsrc; // @[rename-stage.scala:160:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-stage.scala:160:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-stage.scala:160:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-stage.scala:160:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-stage.scala:160:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-stage.scala:160:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-stage.scala:160:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-stage.scala:160:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-stage.scala:160:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-stage.scala:160:7]
wire io_dis_fire_0_0 = io_dis_fire_0; // @[rename-stage.scala:160:7]
wire io_dis_ready_0 = io_dis_ready; // @[rename-stage.scala:160:7]
wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_uop_uopc_0 = io_wakeups_0_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_iq_type_0 = io_wakeups_0_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_0_bits_uop_fu_code_0 = io_wakeups_0_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_uop_ctrl_br_type_0 = io_wakeups_0_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_ctrl_op1_sel_0 = io_wakeups_0_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_op2_sel_0 = io_wakeups_0_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_imm_sel_0 = io_wakeups_0_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_ctrl_op_fcn_0 = io_wakeups_0_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_fcn_dw_0 = io_wakeups_0_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_csr_cmd_0 = io_wakeups_0_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_is_load_0 = io_wakeups_0_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_is_sta_0 = io_wakeups_0_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ctrl_is_std_0 = io_wakeups_0_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_iw_state_0 = io_wakeups_0_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_iw_p1_poisoned_0 = io_wakeups_0_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_iw_p2_poisoned_0 = io_wakeups_0_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_br_0 = io_wakeups_0_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_jalr_0 = io_wakeups_0_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_jal_0 = io_wakeups_0_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_0_bits_uop_csr_addr_0 = io_wakeups_0_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_bypassable_0 = io_wakeups_0_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_ldst_val_0 = io_wakeups_0_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_fp_single_0 = io_wakeups_0_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_0_bits_data_0 = io_wakeups_0_bits_data; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_predicated_0 = io_wakeups_0_bits_predicated; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_valid_0 = io_wakeups_0_bits_fflags_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_uopc_0 = io_wakeups_0_bits_fflags_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_fflags_bits_uop_inst_0 = io_wakeups_0_bits_fflags_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_0_bits_fflags_bits_uop_debug_inst_0 = io_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_rvc_0 = io_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_0_bits_fflags_bits_uop_debug_pc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_iq_type_0 = io_wakeups_0_bits_fflags_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_0_bits_fflags_bits_uop_fu_code_0 = io_wakeups_0_bits_fflags_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std_0 = io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_iw_state_0 = io_wakeups_0_bits_fflags_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_br_0 = io_wakeups_0_bits_fflags_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_jalr_0 = io_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_jal_0 = io_wakeups_0_bits_fflags_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_sfb_0 = io_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_wakeups_0_bits_fflags_bits_uop_br_mask_0 = io_wakeups_0_bits_fflags_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_br_tag_0 = io_wakeups_0_bits_fflags_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ftq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_edge_inst_0 = io_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_pc_lob_0 = io_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_taken_0 = io_wakeups_0_bits_fflags_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_0_bits_fflags_bits_uop_imm_packed_0 = io_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_0_bits_fflags_bits_uop_csr_addr_0 = io_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_rob_idx_0 = io_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ldq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_stq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_rxq_idx_0 = io_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_pdst_0 = io_wakeups_0_bits_fflags_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_prs1_0 = io_wakeups_0_bits_fflags_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_prs2_0 = io_wakeups_0_bits_fflags_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_prs3_0 = io_wakeups_0_bits_fflags_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ppred_0 = io_wakeups_0_bits_fflags_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs1_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs2_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs3_busy_0 = io_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ppred_busy_0 = io_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_stale_pdst_0 = io_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_exception_0 = io_wakeups_0_bits_fflags_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_0_bits_fflags_bits_uop_exc_cause_0 = io_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_bypassable_0 = io_wakeups_0_bits_fflags_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_mem_cmd_0 = io_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_mem_size_0 = io_wakeups_0_bits_fflags_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_mem_signed_0 = io_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_fence_0 = io_wakeups_0_bits_fflags_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_fencei_0 = io_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_amo_0 = io_wakeups_0_bits_fflags_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_uses_ldq_0 = io_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_uses_stq_0 = io_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_unique_0 = io_wakeups_0_bits_fflags_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_ldst_0 = io_wakeups_0_bits_fflags_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_0 = io_wakeups_0_bits_fflags_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_0 = io_wakeups_0_bits_fflags_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs3_0 = io_wakeups_0_bits_fflags_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_ldst_val_0 = io_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_dst_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_frs3_en_0 = io_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_fp_val_0 = io_wakeups_0_bits_fflags_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_fp_single_0 = io_wakeups_0_bits_fflags_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_flags_0 = io_wakeups_0_bits_fflags_bits_flags; // @[rename-stage.scala:160:7]
wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_uop_uopc_0 = io_wakeups_1_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_iq_type_0 = io_wakeups_1_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_1_bits_uop_fu_code_0 = io_wakeups_1_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_uop_ctrl_br_type_0 = io_wakeups_1_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_ctrl_op1_sel_0 = io_wakeups_1_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_ctrl_op2_sel_0 = io_wakeups_1_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_ctrl_imm_sel_0 = io_wakeups_1_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_ctrl_op_fcn_0 = io_wakeups_1_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_fcn_dw_0 = io_wakeups_1_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_ctrl_csr_cmd_0 = io_wakeups_1_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_is_load_0 = io_wakeups_1_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_is_sta_0 = io_wakeups_1_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ctrl_is_std_0 = io_wakeups_1_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_iw_state_0 = io_wakeups_1_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_iw_p1_poisoned_0 = io_wakeups_1_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_iw_p2_poisoned_0 = io_wakeups_1_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_br_0 = io_wakeups_1_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_jalr_0 = io_wakeups_1_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_jal_0 = io_wakeups_1_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_1_bits_uop_csr_addr_0 = io_wakeups_1_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_bypassable_0 = io_wakeups_1_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_ldst_val_0 = io_wakeups_1_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_fp_single_0 = io_wakeups_1_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_1_bits_data_0 = io_wakeups_1_bits_data; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_valid_0 = io_wakeups_1_bits_fflags_valid; // @[rename-stage.scala:160:7]
wire [6:0] io_wakeups_1_bits_fflags_bits_uop_uopc_0 = io_wakeups_1_bits_fflags_bits_uop_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_fflags_bits_uop_inst_0 = io_wakeups_1_bits_fflags_bits_uop_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_wakeups_1_bits_fflags_bits_uop_debug_inst_0 = io_wakeups_1_bits_fflags_bits_uop_debug_inst; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_rvc_0 = io_wakeups_1_bits_fflags_bits_uop_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_wakeups_1_bits_fflags_bits_uop_debug_pc_0 = io_wakeups_1_bits_fflags_bits_uop_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_iq_type_0 = io_wakeups_1_bits_fflags_bits_uop_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_wakeups_1_bits_fflags_bits_uop_fu_code_0 = io_wakeups_1_bits_fflags_bits_uop_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std_0 = io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_iw_state_0 = io_wakeups_1_bits_fflags_bits_uop_iw_state; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_br_0 = io_wakeups_1_bits_fflags_bits_uop_is_br; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_jalr_0 = io_wakeups_1_bits_fflags_bits_uop_is_jalr; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_jal_0 = io_wakeups_1_bits_fflags_bits_uop_is_jal; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_sfb_0 = io_wakeups_1_bits_fflags_bits_uop_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_wakeups_1_bits_fflags_bits_uop_br_mask_0 = io_wakeups_1_bits_fflags_bits_uop_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_br_tag_0 = io_wakeups_1_bits_fflags_bits_uop_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_fflags_bits_uop_ftq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_ftq_idx; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_edge_inst_0 = io_wakeups_1_bits_fflags_bits_uop_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_pc_lob_0 = io_wakeups_1_bits_fflags_bits_uop_pc_lob; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_taken_0 = io_wakeups_1_bits_fflags_bits_uop_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_wakeups_1_bits_fflags_bits_uop_imm_packed_0 = io_wakeups_1_bits_fflags_bits_uop_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_wakeups_1_bits_fflags_bits_uop_csr_addr_0 = io_wakeups_1_bits_fflags_bits_uop_csr_addr; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_rob_idx_0 = io_wakeups_1_bits_fflags_bits_uop_rob_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_ldq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_ldq_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_wakeups_1_bits_fflags_bits_uop_stq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_rxq_idx_0 = io_wakeups_1_bits_fflags_bits_uop_rxq_idx; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_pdst_0 = io_wakeups_1_bits_fflags_bits_uop_pdst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_prs1_0 = io_wakeups_1_bits_fflags_bits_uop_prs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_prs2_0 = io_wakeups_1_bits_fflags_bits_uop_prs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_prs3_0 = io_wakeups_1_bits_fflags_bits_uop_prs3; // @[rename-stage.scala:160:7]
wire [3:0] io_wakeups_1_bits_fflags_bits_uop_ppred_0 = io_wakeups_1_bits_fflags_bits_uop_ppred; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_prs1_busy_0 = io_wakeups_1_bits_fflags_bits_uop_prs1_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_prs2_busy_0 = io_wakeups_1_bits_fflags_bits_uop_prs2_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_prs3_busy_0 = io_wakeups_1_bits_fflags_bits_uop_prs3_busy; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ppred_busy_0 = io_wakeups_1_bits_fflags_bits_uop_ppred_busy; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_stale_pdst_0 = io_wakeups_1_bits_fflags_bits_uop_stale_pdst; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_exception_0 = io_wakeups_1_bits_fflags_bits_uop_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_wakeups_1_bits_fflags_bits_uop_exc_cause_0 = io_wakeups_1_bits_fflags_bits_uop_exc_cause; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_bypassable_0 = io_wakeups_1_bits_fflags_bits_uop_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_uop_mem_cmd_0 = io_wakeups_1_bits_fflags_bits_uop_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_mem_size_0 = io_wakeups_1_bits_fflags_bits_uop_mem_size; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_mem_signed_0 = io_wakeups_1_bits_fflags_bits_uop_mem_signed; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_fence_0 = io_wakeups_1_bits_fflags_bits_uop_is_fence; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_fencei_0 = io_wakeups_1_bits_fflags_bits_uop_is_fencei; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_amo_0 = io_wakeups_1_bits_fflags_bits_uop_is_amo; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_uses_ldq_0 = io_wakeups_1_bits_fflags_bits_uop_uses_ldq; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_uses_stq_0 = io_wakeups_1_bits_fflags_bits_uop_uses_stq; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_is_unique_0 = io_wakeups_1_bits_fflags_bits_uop_is_unique; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_fflags_bits_uop_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_ldst_0 = io_wakeups_1_bits_fflags_bits_uop_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs1_0 = io_wakeups_1_bits_fflags_bits_uop_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs2_0 = io_wakeups_1_bits_fflags_bits_uop_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_wakeups_1_bits_fflags_bits_uop_lrs3_0 = io_wakeups_1_bits_fflags_bits_uop_lrs3; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_ldst_val_0 = io_wakeups_1_bits_fflags_bits_uop_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_dst_rtype_0 = io_wakeups_1_bits_fflags_bits_uop_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_frs3_en_0 = io_wakeups_1_bits_fflags_bits_uop_frs3_en; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_fp_val_0 = io_wakeups_1_bits_fflags_bits_uop_fp_val; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_fp_single_0 = io_wakeups_1_bits_fflags_bits_uop_fp_single; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_fflags_bits_uop_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_fflags_bits_uop_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_wakeups_1_bits_fflags_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_fflags_bits_uop_debug_tsrc; // @[rename-stage.scala:160:7]
wire [4:0] io_wakeups_1_bits_fflags_bits_flags_0 = io_wakeups_1_bits_fflags_bits_flags; // @[rename-stage.scala:160:7]
wire io_com_valids_0_0 = io_com_valids_0; // @[rename-stage.scala:160:7]
wire [6:0] io_com_uops_0_uopc_0 = io_com_uops_0_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_0_inst_0 = io_com_uops_0_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_com_uops_0_debug_inst_0 = io_com_uops_0_debug_inst; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_rvc_0 = io_com_uops_0_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_com_uops_0_debug_pc_0 = io_com_uops_0_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_iq_type_0 = io_com_uops_0_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_com_uops_0_fu_code_0 = io_com_uops_0_fu_code; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_0_ctrl_br_type_0 = io_com_uops_0_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_ctrl_op1_sel_0 = io_com_uops_0_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_ctrl_op2_sel_0 = io_com_uops_0_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_ctrl_imm_sel_0 = io_com_uops_0_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_ctrl_op_fcn_0 = io_com_uops_0_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_fcn_dw_0 = io_com_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_ctrl_csr_cmd_0 = io_com_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_is_load_0 = io_com_uops_0_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_is_sta_0 = io_com_uops_0_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ctrl_is_std_0 = io_com_uops_0_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_iw_state_0 = io_com_uops_0_iw_state; // @[rename-stage.scala:160:7]
wire io_com_uops_0_iw_p1_poisoned_0 = io_com_uops_0_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_0_iw_p2_poisoned_0 = io_com_uops_0_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_br_0 = io_com_uops_0_is_br; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_jalr_0 = io_com_uops_0_is_jalr; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_jal_0 = io_com_uops_0_is_jal; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_sfb_0 = io_com_uops_0_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_com_uops_0_br_mask_0 = io_com_uops_0_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_br_tag_0 = io_com_uops_0_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_0_ftq_idx_0 = io_com_uops_0_ftq_idx; // @[rename-stage.scala:160:7]
wire io_com_uops_0_edge_inst_0 = io_com_uops_0_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_pc_lob_0 = io_com_uops_0_pc_lob; // @[rename-stage.scala:160:7]
wire io_com_uops_0_taken_0 = io_com_uops_0_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_com_uops_0_imm_packed_0 = io_com_uops_0_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_com_uops_0_csr_addr_0 = io_com_uops_0_csr_addr; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_rob_idx_0 = io_com_uops_0_rob_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_ldq_idx_0 = io_com_uops_0_ldq_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_com_uops_0_stq_idx_0 = io_com_uops_0_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_rxq_idx_0 = io_com_uops_0_rxq_idx; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_pdst_0 = io_com_uops_0_pdst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_prs1_0 = io_com_uops_0_prs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_prs2_0 = io_com_uops_0_prs2; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_prs3_0 = io_com_uops_0_prs3; // @[rename-stage.scala:160:7]
wire [3:0] io_com_uops_0_ppred_0 = io_com_uops_0_ppred; // @[rename-stage.scala:160:7]
wire io_com_uops_0_prs1_busy_0 = io_com_uops_0_prs1_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_0_prs2_busy_0 = io_com_uops_0_prs2_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_0_prs3_busy_0 = io_com_uops_0_prs3_busy; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ppred_busy_0 = io_com_uops_0_ppred_busy; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_stale_pdst_0 = io_com_uops_0_stale_pdst; // @[rename-stage.scala:160:7]
wire io_com_uops_0_exception_0 = io_com_uops_0_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_com_uops_0_exc_cause_0 = io_com_uops_0_exc_cause; // @[rename-stage.scala:160:7]
wire io_com_uops_0_bypassable_0 = io_com_uops_0_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_com_uops_0_mem_cmd_0 = io_com_uops_0_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_mem_size_0 = io_com_uops_0_mem_size; // @[rename-stage.scala:160:7]
wire io_com_uops_0_mem_signed_0 = io_com_uops_0_mem_signed; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_fence_0 = io_com_uops_0_is_fence; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_fencei_0 = io_com_uops_0_is_fencei; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_amo_0 = io_com_uops_0_is_amo; // @[rename-stage.scala:160:7]
wire io_com_uops_0_uses_ldq_0 = io_com_uops_0_uses_ldq; // @[rename-stage.scala:160:7]
wire io_com_uops_0_uses_stq_0 = io_com_uops_0_uses_stq; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_sys_pc2epc_0 = io_com_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_com_uops_0_is_unique_0 = io_com_uops_0_is_unique; // @[rename-stage.scala:160:7]
wire io_com_uops_0_flush_on_commit_0 = io_com_uops_0_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ldst_is_rs1_0 = io_com_uops_0_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_ldst_0 = io_com_uops_0_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_lrs1_0 = io_com_uops_0_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_lrs2_0 = io_com_uops_0_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_com_uops_0_lrs3_0 = io_com_uops_0_lrs3; // @[rename-stage.scala:160:7]
wire io_com_uops_0_ldst_val_0 = io_com_uops_0_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_dst_rtype_0 = io_com_uops_0_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_lrs1_rtype_0 = io_com_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_lrs2_rtype_0 = io_com_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_com_uops_0_frs3_en_0 = io_com_uops_0_frs3_en; // @[rename-stage.scala:160:7]
wire io_com_uops_0_fp_val_0 = io_com_uops_0_fp_val; // @[rename-stage.scala:160:7]
wire io_com_uops_0_fp_single_0 = io_com_uops_0_fp_single; // @[rename-stage.scala:160:7]
wire io_com_uops_0_xcpt_pf_if_0 = io_com_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_xcpt_ae_if_0 = io_com_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_xcpt_ma_if_0 = io_com_uops_0_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_bp_debug_if_0 = io_com_uops_0_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_com_uops_0_bp_xcpt_if_0 = io_com_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_debug_fsrc_0 = io_com_uops_0_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_com_uops_0_debug_tsrc_0 = io_com_uops_0_debug_tsrc; // @[rename-stage.scala:160:7]
wire io_rbk_valids_0_0 = io_rbk_valids_0; // @[rename-stage.scala:160:7]
wire io_rollback_0 = io_rollback; // @[rename-stage.scala:160:7]
wire io_debug_rob_empty_0 = io_debug_rob_empty; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] io_dec_uops_0_ppred = 4'h0; // @[rename-stage.scala:160:7]
wire [3:0] ren1_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29]
wire [3:0] ren1_uops_0_ppred = 4'h0; // @[rename-stage.scala:101:29]
wire [1:0] io_dec_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_iw_state = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] io_dec_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:160:7]
wire [1:0] ren1_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_iw_state = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29]
wire [2:0] io_dec_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_ldq_idx = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] io_dec_uops_0_stq_idx = 3'h0; // @[rename-stage.scala:160:7]
wire [2:0] ren1_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ldq_idx = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_stq_idx = 3'h0; // @[rename-stage.scala:101:29]
wire [4:0] io_dec_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] io_dec_uops_0_rob_idx = 5'h0; // @[rename-stage.scala:160:7]
wire [4:0] ren1_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_0_rob_idx = 5'h0; // @[rename-stage.scala:101:29]
wire io_dec_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:160:7]
wire io_dec_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:160:7]
wire io_wakeups_1_bits_predicated = 1'h0; // @[rename-stage.scala:160:7]
wire ren1_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29]
wire [11:0] io_dec_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:160:7]
wire [11:0] ren1_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:101:29]
wire [5:0] io_dec_uops_0_pdst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_prs1 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_prs2 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_prs3 = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] io_dec_uops_0_stale_pdst = 6'h0; // @[rename-stage.scala:160:7]
wire [5:0] ren1_uops_0_pdst = 6'h0; // @[rename-stage.scala:101:29]
wire [47:0] io_debug_isprlist = 48'h0; // @[rename-stage.scala:160:7]
wire _ren2_uops_0_pdst_T_1 = 1'h1; // @[rename-stage.scala:306:38]
wire _io_ren_stalls_0_T_2; // @[rename-stage.scala:339:60]
wire ren1_fire_0 = io_dec_fire_0_0; // @[rename-stage.scala:100:29, :160:7]
wire [6:0] ren1_uops_0_uopc = io_dec_uops_0_uopc_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_0_inst = io_dec_uops_0_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [31:0] ren1_uops_0_debug_inst = io_dec_uops_0_debug_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_rvc = io_dec_uops_0_is_rvc_0; // @[rename-stage.scala:101:29, :160:7]
wire [39:0] ren1_uops_0_debug_pc = io_dec_uops_0_debug_pc_0; // @[rename-stage.scala:101:29, :160:7]
wire [2:0] ren1_uops_0_iq_type = io_dec_uops_0_iq_type_0; // @[rename-stage.scala:101:29, :160:7]
wire [9:0] ren1_uops_0_fu_code = io_dec_uops_0_fu_code_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_br = io_dec_uops_0_is_br_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_jalr = io_dec_uops_0_is_jalr_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_jal = io_dec_uops_0_is_jal_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_sfb = io_dec_uops_0_is_sfb_0; // @[rename-stage.scala:101:29, :160:7]
wire [7:0] ren1_uops_0_br_mask = io_dec_uops_0_br_mask_0; // @[rename-stage.scala:101:29, :160:7]
wire [2:0] ren1_uops_0_br_tag = io_dec_uops_0_br_tag_0; // @[rename-stage.scala:101:29, :160:7]
wire [3:0] ren1_uops_0_ftq_idx = io_dec_uops_0_ftq_idx_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_edge_inst = io_dec_uops_0_edge_inst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_pc_lob = io_dec_uops_0_pc_lob_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_taken = io_dec_uops_0_taken_0; // @[rename-stage.scala:101:29, :160:7]
wire [19:0] ren1_uops_0_imm_packed = io_dec_uops_0_imm_packed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_exception = io_dec_uops_0_exception_0; // @[rename-stage.scala:101:29, :160:7]
wire [63:0] ren1_uops_0_exc_cause = io_dec_uops_0_exc_cause_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_bypassable = io_dec_uops_0_bypassable_0; // @[rename-stage.scala:101:29, :160:7]
wire [4:0] ren1_uops_0_mem_cmd = io_dec_uops_0_mem_cmd_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_mem_size = io_dec_uops_0_mem_size_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_mem_signed = io_dec_uops_0_mem_signed_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_fence = io_dec_uops_0_is_fence_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_fencei = io_dec_uops_0_is_fencei_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_amo = io_dec_uops_0_is_amo_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_uses_ldq = io_dec_uops_0_uses_ldq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_uses_stq = io_dec_uops_0_uses_stq_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_sys_pc2epc = io_dec_uops_0_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_is_unique = io_dec_uops_0_is_unique_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_flush_on_commit = io_dec_uops_0_flush_on_commit_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_ldst = io_dec_uops_0_ldst_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_lrs1 = io_dec_uops_0_lrs1_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_lrs2 = io_dec_uops_0_lrs2_0; // @[rename-stage.scala:101:29, :160:7]
wire [5:0] ren1_uops_0_lrs3 = io_dec_uops_0_lrs3_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_ldst_val = io_dec_uops_0_ldst_val_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_dst_rtype = io_dec_uops_0_dst_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_lrs1_rtype = io_dec_uops_0_lrs1_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_lrs2_rtype = io_dec_uops_0_lrs2_rtype_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_frs3_en = io_dec_uops_0_frs3_en_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_fp_val = io_dec_uops_0_fp_val_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_fp_single = io_dec_uops_0_fp_single_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_xcpt_pf_if = io_dec_uops_0_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_xcpt_ae_if = io_dec_uops_0_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_bp_debug_if = io_dec_uops_0_bp_debug_if_0; // @[rename-stage.scala:101:29, :160:7]
wire ren1_uops_0_bp_xcpt_if = io_dec_uops_0_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :160:7]
wire [1:0] ren1_uops_0_debug_fsrc = io_dec_uops_0_debug_fsrc_0; // @[rename-stage.scala:101:29, :160:7]
wire ren2_valids_0; // @[rename-stage.scala:107:29]
wire [6:0] io_ren2_uops_0_newuop_uopc; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_0_newuop_inst; // @[util.scala:73:26]
wire [31:0] io_ren2_uops_0_newuop_debug_inst; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_rvc; // @[util.scala:73:26]
wire [39:0] io_ren2_uops_0_newuop_debug_pc; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_iq_type; // @[util.scala:73:26]
wire [9:0] io_ren2_uops_0_newuop_fu_code; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_0_newuop_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_ctrl_op_fcn; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_ctrl_csr_cmd; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_is_load; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_is_sta; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_iw_state; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_iw_p1_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_iw_p2_poisoned; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_br; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_jalr; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_jal; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_sfb; // @[util.scala:73:26]
wire [7:0] io_ren2_uops_0_newuop_br_mask; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_br_tag; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_0_newuop_ftq_idx; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_edge_inst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_pc_lob; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_taken; // @[util.scala:73:26]
wire [19:0] io_ren2_uops_0_newuop_imm_packed; // @[util.scala:73:26]
wire [11:0] io_ren2_uops_0_newuop_csr_addr; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_rob_idx; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_ldq_idx; // @[util.scala:73:26]
wire [2:0] io_ren2_uops_0_newuop_stq_idx; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_rxq_idx; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_pdst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_prs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_prs2; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_prs3; // @[util.scala:73:26]
wire [3:0] io_ren2_uops_0_newuop_ppred; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_prs1_busy; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_prs2_busy; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_prs3_busy; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ppred_busy; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_stale_pdst; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_exception; // @[util.scala:73:26]
wire [63:0] io_ren2_uops_0_newuop_exc_cause; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_bypassable; // @[util.scala:73:26]
wire [4:0] io_ren2_uops_0_newuop_mem_cmd; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_mem_size; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_mem_signed; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_fence; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_fencei; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_amo; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_uses_ldq; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_uses_stq; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_sys_pc2epc; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_is_unique; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_flush_on_commit; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_ldst; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_lrs1; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_lrs2; // @[util.scala:73:26]
wire [5:0] io_ren2_uops_0_newuop_lrs3; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_ldst_val; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_dst_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_lrs2_rtype; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_frs3_en; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_fp_val; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_fp_single; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_xcpt_pf_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_xcpt_ae_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_xcpt_ma_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_bp_debug_if; // @[util.scala:73:26]
wire io_ren2_uops_0_newuop_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_debug_fsrc; // @[util.scala:73:26]
wire [1:0] io_ren2_uops_0_newuop_debug_tsrc; // @[util.scala:73:26]
wire io_ren_stalls_0_0; // @[rename-stage.scala:160:7]
wire io_ren2_mask_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:160:7]
wire [6:0] io_ren2_uops_0_uopc; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_0_inst; // @[rename-stage.scala:160:7]
wire [31:0] io_ren2_uops_0_debug_inst; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_rvc; // @[rename-stage.scala:160:7]
wire [39:0] io_ren2_uops_0_debug_pc; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_iq_type; // @[rename-stage.scala:160:7]
wire [9:0] io_ren2_uops_0_fu_code; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_iw_state; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_br; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_jalr; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_jal; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_sfb; // @[rename-stage.scala:160:7]
wire [7:0] io_ren2_uops_0_br_mask; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_br_tag; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_0_ftq_idx; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_edge_inst; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_pc_lob; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_taken; // @[rename-stage.scala:160:7]
wire [19:0] io_ren2_uops_0_imm_packed; // @[rename-stage.scala:160:7]
wire [11:0] io_ren2_uops_0_csr_addr; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_rob_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_ldq_idx; // @[rename-stage.scala:160:7]
wire [2:0] io_ren2_uops_0_stq_idx; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_rxq_idx; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_pdst_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_prs1_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_prs2_0; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_prs3_0; // @[rename-stage.scala:160:7]
wire [3:0] io_ren2_uops_0_ppred; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_prs1_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_prs2_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_prs3_busy_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ppred_busy; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_stale_pdst_0; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_exception; // @[rename-stage.scala:160:7]
wire [63:0] io_ren2_uops_0_exc_cause; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_bypassable; // @[rename-stage.scala:160:7]
wire [4:0] io_ren2_uops_0_mem_cmd; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_mem_size; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_mem_signed; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_fence; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_fencei; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_amo; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_uses_ldq; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_uses_stq; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_is_unique; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_flush_on_commit; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_ldst; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_lrs1; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_lrs2; // @[rename-stage.scala:160:7]
wire [5:0] io_ren2_uops_0_lrs3; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_ldst_val; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_dst_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_frs3_en; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_fp_val; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_fp_single; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_bp_debug_if; // @[rename-stage.scala:160:7]
wire io_ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_debug_fsrc; // @[rename-stage.scala:160:7]
wire [1:0] io_ren2_uops_0_debug_tsrc; // @[rename-stage.scala:160:7]
wire [47:0] io_debug_freelist; // @[rename-stage.scala:160:7]
wire [47:0] io_debug_busytable; // @[rename-stage.scala:160:7]
wire [5:0] map_reqs_0_ldst = ren1_uops_0_ldst; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_0_lrs1 = ren1_uops_0_lrs1; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_0_lrs2 = ren1_uops_0_lrs2; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] map_reqs_0_lrs3 = ren1_uops_0_lrs3; // @[rename-stage.scala:101:29, :252:24]
wire [5:0] ren1_uops_0_prs1; // @[rename-stage.scala:101:29]
wire [5:0] ren1_uops_0_prs2; // @[rename-stage.scala:101:29]
wire [5:0] ren1_uops_0_prs3; // @[rename-stage.scala:101:29]
wire [5:0] ren1_uops_0_stale_pdst; // @[rename-stage.scala:101:29]
assign io_ren2_mask_0 = ren2_valids_0; // @[rename-stage.scala:107:29, :160:7]
wire [6:0] bypassed_uop_uopc = ren2_uops_0_uopc; // @[rename-stage.scala:108:29, :341:28]
wire [31:0] bypassed_uop_inst = ren2_uops_0_inst; // @[rename-stage.scala:108:29, :341:28]
wire [31:0] bypassed_uop_debug_inst = ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_rvc = ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29, :341:28]
wire [39:0] bypassed_uop_debug_pc = ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_iq_type = ren2_uops_0_iq_type; // @[rename-stage.scala:108:29, :341:28]
wire [9:0] bypassed_uop_fu_code = ren2_uops_0_fu_code; // @[rename-stage.scala:108:29, :341:28]
wire [3:0] bypassed_uop_ctrl_br_type = ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_ctrl_op1_sel = ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_ctrl_op2_sel = ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_ctrl_imm_sel = ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_ctrl_op_fcn = ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_fcn_dw = ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_ctrl_csr_cmd = ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_is_load = ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_is_sta = ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ctrl_is_std = ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_iw_state = ren2_uops_0_iw_state; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_iw_p1_poisoned = ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_iw_p2_poisoned = ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_br = ren2_uops_0_is_br; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_jalr = ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_jal = ren2_uops_0_is_jal; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_sfb = ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29, :341:28]
wire [7:0] bypassed_uop_br_mask = ren2_uops_0_br_mask; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] ren2_br_tags_0_bits = ren2_uops_0_br_tag; // @[rename-stage.scala:108:29, :233:29]
wire [2:0] bypassed_uop_br_tag = ren2_uops_0_br_tag; // @[rename-stage.scala:108:29, :341:28]
wire [3:0] bypassed_uop_ftq_idx = ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_edge_inst = ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_pc_lob = ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_taken = ren2_uops_0_taken; // @[rename-stage.scala:108:29, :341:28]
wire [19:0] bypassed_uop_imm_packed = ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29, :341:28]
wire [11:0] bypassed_uop_csr_addr = ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_rob_idx = ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_ldq_idx = ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29, :341:28]
wire [2:0] bypassed_uop_stq_idx = ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] _ren2_uops_0_pdst_T_2; // @[rename-stage.scala:306:20]
wire [1:0] bypassed_uop_rxq_idx = ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_pdst = ren2_uops_0_pdst; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_prs1 = ren2_uops_0_prs1; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_prs2 = ren2_uops_0_prs2; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_prs3 = ren2_uops_0_prs3; // @[rename-stage.scala:108:29, :341:28]
wire _ren2_uops_0_prs1_busy_T_1; // @[rename-stage.scala:323:47]
wire [3:0] bypassed_uop_ppred = ren2_uops_0_ppred; // @[rename-stage.scala:108:29, :341:28]
wire _ren2_uops_0_prs2_busy_T_1; // @[rename-stage.scala:324:47]
wire bypassed_uop_prs1_busy = ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29, :341:28]
wire _ren2_uops_0_prs3_busy_T; // @[rename-stage.scala:325:34]
wire bypassed_uop_prs2_busy = ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_prs3_busy = ren2_uops_0_prs3_busy; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ppred_busy = ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_stale_pdst = ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_exception = ren2_uops_0_exception; // @[rename-stage.scala:108:29, :341:28]
wire [63:0] bypassed_uop_exc_cause = ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_bypassable = ren2_uops_0_bypassable; // @[rename-stage.scala:108:29, :341:28]
wire [4:0] bypassed_uop_mem_cmd = ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_mem_size = ren2_uops_0_mem_size; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_mem_signed = ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_fence = ren2_uops_0_is_fence; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_fencei = ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_amo = ren2_uops_0_is_amo; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_uses_ldq = ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_uses_stq = ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_sys_pc2epc = ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_is_unique = ren2_uops_0_is_unique; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_flush_on_commit = ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ldst_is_rs1 = ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_ldst = ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_lrs1 = ren2_uops_0_lrs1; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_lrs2 = ren2_uops_0_lrs2; // @[rename-stage.scala:108:29, :341:28]
wire [5:0] bypassed_uop_lrs3 = ren2_uops_0_lrs3; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_ldst_val = ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_dst_rtype = ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_lrs1_rtype = ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_lrs2_rtype = ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_frs3_en = ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_fp_val = ren2_uops_0_fp_val; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_fp_single = ren2_uops_0_fp_single; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_xcpt_pf_if = ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_xcpt_ae_if = ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_xcpt_ma_if = ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_bp_debug_if = ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29, :341:28]
wire bypassed_uop_bp_xcpt_if = ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_debug_fsrc = ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29, :341:28]
wire [1:0] bypassed_uop_debug_tsrc = ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29, :341:28]
wire _ren2_alloc_reqs_0_T_2; // @[rename-stage.scala:240:88]
wire ren2_alloc_reqs_0; // @[rename-stage.scala:109:29]
reg r_valid; // @[rename-stage.scala:121:27]
assign ren2_valids_0 = r_valid; // @[rename-stage.scala:107:29, :121:27]
reg [6:0] r_uop_uopc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uopc = r_uop_uopc; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_inst = r_uop_inst; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_debug_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_inst = r_uop_debug_inst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_rvc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_rvc = r_uop_is_rvc; // @[rename-stage.scala:108:29, :122:23]
reg [39:0] r_uop_debug_pc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_pc = r_uop_debug_pc; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_iq_type; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iq_type = r_uop_iq_type; // @[rename-stage.scala:108:29, :122:23]
reg [9:0] r_uop_fu_code; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fu_code = r_uop_fu_code; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_ctrl_br_type; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_br_type = r_uop_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_ctrl_op1_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op1_sel = r_uop_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_op2_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op2_sel = r_uop_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_imm_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_imm_sel = r_uop_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_ctrl_op_fcn; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op_fcn = r_uop_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_fcn_dw = r_uop_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_csr_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_csr_cmd = r_uop_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_load; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_load = r_uop_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_sta = r_uop_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_std; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_std = r_uop_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_iw_state; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_state = r_uop_iw_state; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_p1_poisoned = r_uop_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_p2_poisoned = r_uop_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_br; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_br = r_uop_is_br; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_jalr; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_jalr = r_uop_is_jalr; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_jal; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_jal = r_uop_is_jal; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_sfb; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_sfb = r_uop_is_sfb; // @[rename-stage.scala:108:29, :122:23]
reg [7:0] r_uop_br_mask; // @[rename-stage.scala:122:23]
assign ren2_uops_0_br_mask = r_uop_br_mask; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_br_tag; // @[rename-stage.scala:122:23]
assign ren2_uops_0_br_tag = r_uop_br_tag; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_ftq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ftq_idx = r_uop_ftq_idx; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_edge_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_edge_inst = r_uop_edge_inst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_pc_lob; // @[rename-stage.scala:122:23]
assign ren2_uops_0_pc_lob = r_uop_pc_lob; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_taken; // @[rename-stage.scala:122:23]
assign ren2_uops_0_taken = r_uop_taken; // @[rename-stage.scala:108:29, :122:23]
reg [19:0] r_uop_imm_packed; // @[rename-stage.scala:122:23]
assign ren2_uops_0_imm_packed = r_uop_imm_packed; // @[rename-stage.scala:108:29, :122:23]
reg [11:0] r_uop_csr_addr; // @[rename-stage.scala:122:23]
assign ren2_uops_0_csr_addr = r_uop_csr_addr; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_rob_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_rob_idx = r_uop_rob_idx; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ldq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldq_idx = r_uop_ldq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_stq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_stq_idx = r_uop_stq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_rxq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_rxq_idx = r_uop_rxq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_pdst; // @[rename-stage.scala:122:23]
reg [5:0] r_uop_prs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs1 = r_uop_prs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_prs2; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs2 = r_uop_prs2; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_prs3; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs3 = r_uop_prs3; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_ppred; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ppred = r_uop_ppred; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_prs1_busy; // @[rename-stage.scala:122:23]
reg r_uop_prs2_busy; // @[rename-stage.scala:122:23]
reg r_uop_prs3_busy; // @[rename-stage.scala:122:23]
reg r_uop_ppred_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ppred_busy = r_uop_ppred_busy; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_stale_pdst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_stale_pdst = r_uop_stale_pdst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_exception; // @[rename-stage.scala:122:23]
assign ren2_uops_0_exception = r_uop_exception; // @[rename-stage.scala:108:29, :122:23]
reg [63:0] r_uop_exc_cause; // @[rename-stage.scala:122:23]
assign ren2_uops_0_exc_cause = r_uop_exc_cause; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bypassable; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bypassable = r_uop_bypassable; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_mem_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_cmd = r_uop_mem_cmd; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_mem_size; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_size = r_uop_mem_size; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_mem_signed; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_signed = r_uop_mem_signed; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_fence; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_fence = r_uop_is_fence; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_fencei; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_fencei = r_uop_is_fencei; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_amo; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_amo = r_uop_is_amo; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_uses_ldq; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uses_ldq = r_uop_uses_ldq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_uses_stq; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uses_stq = r_uop_uses_stq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_sys_pc2epc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_sys_pc2epc = r_uop_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_unique; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_unique = r_uop_is_unique; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_flush_on_commit; // @[rename-stage.scala:122:23]
assign ren2_uops_0_flush_on_commit = r_uop_flush_on_commit; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst_is_rs1 = r_uop_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_ldst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst = r_uop_ldst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs1 = r_uop_lrs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs2; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs2 = r_uop_lrs2; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs3; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs3 = r_uop_lrs3; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ldst_val; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst_val = r_uop_ldst_val; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_dst_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_dst_rtype = r_uop_dst_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_lrs1_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs1_rtype = r_uop_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_lrs2_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs2_rtype = r_uop_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_frs3_en; // @[rename-stage.scala:122:23]
assign ren2_uops_0_frs3_en = r_uop_frs3_en; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_fp_val; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fp_val = r_uop_fp_val; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_fp_single; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fp_single = r_uop_fp_single; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_pf_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_pf_if = r_uop_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_ae_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_ae_if = r_uop_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_ma_if = r_uop_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bp_debug_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bp_debug_if = r_uop_bp_debug_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bp_xcpt_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bp_xcpt_if = r_uop_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_debug_fsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_fsrc = r_uop_debug_fsrc; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_debug_tsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_tsrc = r_uop_debug_tsrc; // @[rename-stage.scala:108:29, :122:23]
wire [6:0] r_uop_bypassed_uop_uopc = next_uop_uopc; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_inst = next_uop_inst; // @[rename-stage.scala:123:24, :174:28]
wire [31:0] r_uop_bypassed_uop_debug_inst = next_uop_debug_inst; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_rvc = next_uop_is_rvc; // @[rename-stage.scala:123:24, :174:28]
wire [39:0] r_uop_bypassed_uop_debug_pc = next_uop_debug_pc; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_iq_type = next_uop_iq_type; // @[rename-stage.scala:123:24, :174:28]
wire [9:0] r_uop_bypassed_uop_fu_code = next_uop_fu_code; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_ctrl_br_type = next_uop_ctrl_br_type; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_ctrl_op1_sel = next_uop_ctrl_op1_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_ctrl_op2_sel = next_uop_ctrl_op2_sel; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_ctrl_imm_sel = next_uop_ctrl_imm_sel; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_ctrl_op_fcn = next_uop_ctrl_op_fcn; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_fcn_dw = next_uop_ctrl_fcn_dw; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_ctrl_csr_cmd = next_uop_ctrl_csr_cmd; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_is_load = next_uop_ctrl_is_load; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_is_sta = next_uop_ctrl_is_sta; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ctrl_is_std = next_uop_ctrl_is_std; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_iw_state = next_uop_iw_state; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_iw_p1_poisoned = next_uop_iw_p1_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_iw_p2_poisoned = next_uop_iw_p2_poisoned; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_br = next_uop_is_br; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_jalr = next_uop_is_jalr; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_jal = next_uop_is_jal; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_sfb = next_uop_is_sfb; // @[rename-stage.scala:123:24, :174:28]
wire [7:0] r_uop_bypassed_uop_br_mask = next_uop_br_mask; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_br_tag = next_uop_br_tag; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_ftq_idx = next_uop_ftq_idx; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_edge_inst = next_uop_edge_inst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_pc_lob = next_uop_pc_lob; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_taken = next_uop_taken; // @[rename-stage.scala:123:24, :174:28]
wire [19:0] r_uop_bypassed_uop_imm_packed = next_uop_imm_packed; // @[rename-stage.scala:123:24, :174:28]
wire [11:0] r_uop_bypassed_uop_csr_addr = next_uop_csr_addr; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_rob_idx = next_uop_rob_idx; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_ldq_idx = next_uop_ldq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [2:0] r_uop_bypassed_uop_stq_idx = next_uop_stq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_rxq_idx = next_uop_rxq_idx; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_pdst = next_uop_pdst; // @[rename-stage.scala:123:24, :174:28]
wire [3:0] r_uop_bypassed_uop_ppred = next_uop_ppred; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ppred_busy = next_uop_ppred_busy; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_exception = next_uop_exception; // @[rename-stage.scala:123:24, :174:28]
wire [63:0] r_uop_bypassed_uop_exc_cause = next_uop_exc_cause; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_bypassable = next_uop_bypassable; // @[rename-stage.scala:123:24, :174:28]
wire [4:0] r_uop_bypassed_uop_mem_cmd = next_uop_mem_cmd; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_mem_size = next_uop_mem_size; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_mem_signed = next_uop_mem_signed; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_fence = next_uop_is_fence; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_fencei = next_uop_is_fencei; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_amo = next_uop_is_amo; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_uses_ldq = next_uop_uses_ldq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_uses_stq = next_uop_uses_stq; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_sys_pc2epc = next_uop_is_sys_pc2epc; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_is_unique = next_uop_is_unique; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_flush_on_commit = next_uop_flush_on_commit; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ldst_is_rs1 = next_uop_ldst_is_rs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_ldst = next_uop_ldst; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_lrs1 = next_uop_lrs1; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_lrs2 = next_uop_lrs2; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] r_uop_bypassed_uop_lrs3 = next_uop_lrs3; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_ldst_val = next_uop_ldst_val; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_dst_rtype = next_uop_dst_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_lrs1_rtype = next_uop_lrs1_rtype; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_lrs2_rtype = next_uop_lrs2_rtype; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_frs3_en = next_uop_frs3_en; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_fp_val = next_uop_fp_val; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_fp_single = next_uop_fp_single; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_xcpt_pf_if = next_uop_xcpt_pf_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_xcpt_ae_if = next_uop_xcpt_ae_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_xcpt_ma_if = next_uop_xcpt_ma_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_bp_debug_if = next_uop_bp_debug_if; // @[rename-stage.scala:123:24, :174:28]
wire r_uop_bypassed_uop_bp_xcpt_if = next_uop_bp_xcpt_if; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_debug_fsrc = next_uop_debug_fsrc; // @[rename-stage.scala:123:24, :174:28]
wire [1:0] r_uop_bypassed_uop_debug_tsrc = next_uop_debug_tsrc; // @[rename-stage.scala:123:24, :174:28]
wire [5:0] next_uop_prs1; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_prs2; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_prs3; // @[rename-stage.scala:123:24]
wire next_uop_prs1_busy; // @[rename-stage.scala:123:24]
wire next_uop_prs2_busy; // @[rename-stage.scala:123:24]
wire next_uop_prs3_busy; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_stale_pdst; // @[rename-stage.scala:123:24]
wire _r_valid_T = ~io_dis_fire_0_0; // @[rename-stage.scala:133:29, :160:7]
wire _r_valid_T_1 = r_valid & _r_valid_T; // @[rename-stage.scala:121:27, :133:{26,29}]
wire _GEN = io_kill_0 | ~io_dis_ready_0; // @[rename-stage.scala:125:14, :127:20, :129:30, :160:7]
assign next_uop_uopc = _GEN ? r_uop_uopc : ren1_uops_0_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_inst = _GEN ? r_uop_inst : ren1_uops_0_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_inst = _GEN ? r_uop_debug_inst : ren1_uops_0_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_rvc = _GEN ? r_uop_is_rvc : ren1_uops_0_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_pc = _GEN ? r_uop_debug_pc : ren1_uops_0_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iq_type = _GEN ? r_uop_iq_type : ren1_uops_0_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fu_code = _GEN ? r_uop_fu_code : ren1_uops_0_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_br_type = _GEN ? r_uop_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op1_sel = _GEN ? r_uop_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op2_sel = _GEN ? r_uop_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_imm_sel = _GEN ? r_uop_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op_fcn = _GEN ? r_uop_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_fcn_dw = _GEN & r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_csr_cmd = _GEN ? r_uop_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_load = _GEN & r_uop_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_sta = _GEN & r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_std = _GEN & r_uop_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_state = _GEN ? r_uop_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_p1_poisoned = _GEN & r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_p2_poisoned = _GEN & r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_br = _GEN ? r_uop_is_br : ren1_uops_0_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_jalr = _GEN ? r_uop_is_jalr : ren1_uops_0_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_jal = _GEN ? r_uop_is_jal : ren1_uops_0_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_sfb = _GEN ? r_uop_is_sfb : ren1_uops_0_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_br_mask = _GEN ? r_uop_br_mask : ren1_uops_0_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_br_tag = _GEN ? r_uop_br_tag : ren1_uops_0_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ftq_idx = _GEN ? r_uop_ftq_idx : ren1_uops_0_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_edge_inst = _GEN ? r_uop_edge_inst : ren1_uops_0_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_pc_lob = _GEN ? r_uop_pc_lob : ren1_uops_0_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_taken = _GEN ? r_uop_taken : ren1_uops_0_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_imm_packed = _GEN ? r_uop_imm_packed : ren1_uops_0_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_csr_addr = _GEN ? r_uop_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_rob_idx = _GEN ? r_uop_rob_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldq_idx = _GEN ? r_uop_ldq_idx : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_stq_idx = _GEN ? r_uop_stq_idx : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_rxq_idx = _GEN ? r_uop_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_pdst = _GEN ? r_uop_pdst : 6'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs1 = _GEN ? r_uop_prs1 : ren1_uops_0_prs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs2 = _GEN ? r_uop_prs2 : ren1_uops_0_prs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs3 = _GEN ? r_uop_prs3 : ren1_uops_0_prs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ppred = _GEN ? r_uop_ppred : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs1_busy = _GEN & r_uop_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs2_busy = _GEN & r_uop_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs3_busy = _GEN & r_uop_prs3_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ppred_busy = _GEN & r_uop_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_stale_pdst = _GEN ? r_uop_stale_pdst : ren1_uops_0_stale_pdst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_exception = _GEN ? r_uop_exception : ren1_uops_0_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_exc_cause = _GEN ? r_uop_exc_cause : ren1_uops_0_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bypassable = _GEN ? r_uop_bypassable : ren1_uops_0_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_cmd = _GEN ? r_uop_mem_cmd : ren1_uops_0_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_size = _GEN ? r_uop_mem_size : ren1_uops_0_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_signed = _GEN ? r_uop_mem_signed : ren1_uops_0_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_fence = _GEN ? r_uop_is_fence : ren1_uops_0_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_fencei = _GEN ? r_uop_is_fencei : ren1_uops_0_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_amo = _GEN ? r_uop_is_amo : ren1_uops_0_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_uses_ldq = _GEN ? r_uop_uses_ldq : ren1_uops_0_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_uses_stq = _GEN ? r_uop_uses_stq : ren1_uops_0_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_sys_pc2epc = _GEN ? r_uop_is_sys_pc2epc : ren1_uops_0_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_unique = _GEN ? r_uop_is_unique : ren1_uops_0_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_flush_on_commit = _GEN ? r_uop_flush_on_commit : ren1_uops_0_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst_is_rs1 = _GEN & r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst = _GEN ? r_uop_ldst : ren1_uops_0_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs1 = _GEN ? r_uop_lrs1 : ren1_uops_0_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs2 = _GEN ? r_uop_lrs2 : ren1_uops_0_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs3 = _GEN ? r_uop_lrs3 : ren1_uops_0_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst_val = _GEN ? r_uop_ldst_val : ren1_uops_0_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_dst_rtype = _GEN ? r_uop_dst_rtype : ren1_uops_0_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs1_rtype = _GEN ? r_uop_lrs1_rtype : ren1_uops_0_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs2_rtype = _GEN ? r_uop_lrs2_rtype : ren1_uops_0_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_frs3_en = _GEN ? r_uop_frs3_en : ren1_uops_0_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fp_val = _GEN ? r_uop_fp_val : ren1_uops_0_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fp_single = _GEN ? r_uop_fp_single : ren1_uops_0_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_pf_if = _GEN ? r_uop_xcpt_pf_if : ren1_uops_0_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_ae_if = _GEN ? r_uop_xcpt_ae_if : ren1_uops_0_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_ma_if = _GEN & r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bp_debug_if = _GEN ? r_uop_bp_debug_if : ren1_uops_0_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bp_xcpt_if = _GEN ? r_uop_bp_xcpt_if : ren1_uops_0_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_fsrc = _GEN ? r_uop_debug_fsrc : ren1_uops_0_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_tsrc = _GEN ? r_uop_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
wire [6:0] r_uop_newuop_uopc = r_uop_bypassed_uop_uopc; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_inst = r_uop_bypassed_uop_inst; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_debug_inst = r_uop_bypassed_uop_debug_inst; // @[util.scala:73:26]
wire r_uop_newuop_is_rvc = r_uop_bypassed_uop_is_rvc; // @[util.scala:73:26]
wire [39:0] r_uop_newuop_debug_pc = r_uop_bypassed_uop_debug_pc; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_iq_type = r_uop_bypassed_uop_iq_type; // @[util.scala:73:26]
wire [9:0] r_uop_newuop_fu_code = r_uop_bypassed_uop_fu_code; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_ctrl_br_type = r_uop_bypassed_uop_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_ctrl_op1_sel = r_uop_bypassed_uop_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_op2_sel = r_uop_bypassed_uop_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_imm_sel = r_uop_bypassed_uop_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_ctrl_op_fcn = r_uop_bypassed_uop_ctrl_op_fcn; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_fcn_dw = r_uop_bypassed_uop_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_csr_cmd = r_uop_bypassed_uop_ctrl_csr_cmd; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_load = r_uop_bypassed_uop_ctrl_is_load; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_sta = r_uop_bypassed_uop_ctrl_is_sta; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_std = r_uop_bypassed_uop_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_iw_state = r_uop_bypassed_uop_iw_state; // @[util.scala:73:26]
wire r_uop_newuop_iw_p1_poisoned = r_uop_bypassed_uop_iw_p1_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_iw_p2_poisoned = r_uop_bypassed_uop_iw_p2_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_is_br = r_uop_bypassed_uop_is_br; // @[util.scala:73:26]
wire r_uop_newuop_is_jalr = r_uop_bypassed_uop_is_jalr; // @[util.scala:73:26]
wire r_uop_newuop_is_jal = r_uop_bypassed_uop_is_jal; // @[util.scala:73:26]
wire r_uop_newuop_is_sfb = r_uop_bypassed_uop_is_sfb; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_br_tag = r_uop_bypassed_uop_br_tag; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_ftq_idx = r_uop_bypassed_uop_ftq_idx; // @[util.scala:73:26]
wire r_uop_newuop_edge_inst = r_uop_bypassed_uop_edge_inst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_pc_lob = r_uop_bypassed_uop_pc_lob; // @[util.scala:73:26]
wire r_uop_newuop_taken = r_uop_bypassed_uop_taken; // @[util.scala:73:26]
wire [19:0] r_uop_newuop_imm_packed = r_uop_bypassed_uop_imm_packed; // @[util.scala:73:26]
wire [11:0] r_uop_newuop_csr_addr = r_uop_bypassed_uop_csr_addr; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_rob_idx = r_uop_bypassed_uop_rob_idx; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ldq_idx = r_uop_bypassed_uop_ldq_idx; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_stq_idx = r_uop_bypassed_uop_stq_idx; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_rxq_idx = r_uop_bypassed_uop_rxq_idx; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_pdst = r_uop_bypassed_uop_pdst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_prs1 = r_uop_bypassed_uop_prs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_prs2 = r_uop_bypassed_uop_prs2; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_prs3 = r_uop_bypassed_uop_prs3; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs1_busy_T; // @[rename-stage.scala:199:45]
wire [3:0] r_uop_newuop_ppred = r_uop_bypassed_uop_ppred; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs2_busy_T; // @[rename-stage.scala:200:45]
wire r_uop_newuop_prs1_busy = r_uop_bypassed_uop_prs1_busy; // @[util.scala:73:26]
wire _r_uop_bypassed_uop_prs3_busy_T; // @[rename-stage.scala:201:45]
wire r_uop_newuop_prs2_busy = r_uop_bypassed_uop_prs2_busy; // @[util.scala:73:26]
wire r_uop_newuop_prs3_busy = r_uop_bypassed_uop_prs3_busy; // @[util.scala:73:26]
wire r_uop_newuop_ppred_busy = r_uop_bypassed_uop_ppred_busy; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_stale_pdst = r_uop_bypassed_uop_stale_pdst; // @[util.scala:73:26]
wire r_uop_newuop_exception = r_uop_bypassed_uop_exception; // @[util.scala:73:26]
wire [63:0] r_uop_newuop_exc_cause = r_uop_bypassed_uop_exc_cause; // @[util.scala:73:26]
wire r_uop_newuop_bypassable = r_uop_bypassed_uop_bypassable; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_mem_cmd = r_uop_bypassed_uop_mem_cmd; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_mem_size = r_uop_bypassed_uop_mem_size; // @[util.scala:73:26]
wire r_uop_newuop_mem_signed = r_uop_bypassed_uop_mem_signed; // @[util.scala:73:26]
wire r_uop_newuop_is_fence = r_uop_bypassed_uop_is_fence; // @[util.scala:73:26]
wire r_uop_newuop_is_fencei = r_uop_bypassed_uop_is_fencei; // @[util.scala:73:26]
wire r_uop_newuop_is_amo = r_uop_bypassed_uop_is_amo; // @[util.scala:73:26]
wire r_uop_newuop_uses_ldq = r_uop_bypassed_uop_uses_ldq; // @[util.scala:73:26]
wire r_uop_newuop_uses_stq = r_uop_bypassed_uop_uses_stq; // @[util.scala:73:26]
wire r_uop_newuop_is_sys_pc2epc = r_uop_bypassed_uop_is_sys_pc2epc; // @[util.scala:73:26]
wire r_uop_newuop_is_unique = r_uop_bypassed_uop_is_unique; // @[util.scala:73:26]
wire r_uop_newuop_flush_on_commit = r_uop_bypassed_uop_flush_on_commit; // @[util.scala:73:26]
wire r_uop_newuop_ldst_is_rs1 = r_uop_bypassed_uop_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_ldst = r_uop_bypassed_uop_ldst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs1 = r_uop_bypassed_uop_lrs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs2 = r_uop_bypassed_uop_lrs2; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs3 = r_uop_bypassed_uop_lrs3; // @[util.scala:73:26]
wire r_uop_newuop_ldst_val = r_uop_bypassed_uop_ldst_val; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_dst_rtype = r_uop_bypassed_uop_dst_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_lrs1_rtype = r_uop_bypassed_uop_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_lrs2_rtype = r_uop_bypassed_uop_lrs2_rtype; // @[util.scala:73:26]
wire r_uop_newuop_frs3_en = r_uop_bypassed_uop_frs3_en; // @[util.scala:73:26]
wire r_uop_newuop_fp_val = r_uop_bypassed_uop_fp_val; // @[util.scala:73:26]
wire r_uop_newuop_fp_single = r_uop_bypassed_uop_fp_single; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_pf_if = r_uop_bypassed_uop_xcpt_pf_if; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_ae_if = r_uop_bypassed_uop_xcpt_ae_if; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_ma_if = r_uop_bypassed_uop_xcpt_ma_if; // @[util.scala:73:26]
wire r_uop_newuop_bp_debug_if = r_uop_bypassed_uop_bp_debug_if; // @[util.scala:73:26]
wire r_uop_newuop_bp_xcpt_if = r_uop_bypassed_uop_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_debug_fsrc = r_uop_bypassed_uop_debug_fsrc; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_debug_tsrc = r_uop_bypassed_uop_debug_tsrc; // @[util.scala:73:26]
wire _r_uop_bypass_hits_rs1_T = ren2_uops_0_ldst == next_uop_lrs1; // @[rename-stage.scala:108:29, :123:24, :177:87]
wire r_uop_bypass_hits_rs1_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs1_T; // @[rename-stage.scala:109:29, :177:{77,87}]
wire r_uop_bypass_sel_rs1_enc = r_uop_bypass_hits_rs1_0; // @[Mux.scala:50:70]
wire _r_uop_bypass_hits_rs2_T = ren2_uops_0_ldst == next_uop_lrs2; // @[rename-stage.scala:108:29, :123:24, :178:87]
wire r_uop_bypass_hits_rs2_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs2_T; // @[rename-stage.scala:109:29, :178:{77,87}]
wire r_uop_bypass_sel_rs2_enc = r_uop_bypass_hits_rs2_0; // @[Mux.scala:50:70]
wire _r_uop_bypass_hits_rs3_T = ren2_uops_0_ldst == next_uop_lrs3; // @[rename-stage.scala:108:29, :123:24, :179:87]
wire r_uop_bypass_hits_rs3_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_rs3_T; // @[rename-stage.scala:109:29, :179:{77,87}]
wire r_uop_bypass_sel_rs3_enc = r_uop_bypass_hits_rs3_0; // @[Mux.scala:50:70]
wire _r_uop_bypass_hits_dst_T = ren2_uops_0_ldst == next_uop_ldst; // @[rename-stage.scala:108:29, :123:24, :180:87]
wire r_uop_bypass_hits_dst_0 = ren2_alloc_reqs_0 & _r_uop_bypass_hits_dst_T; // @[rename-stage.scala:109:29, :180:{77,87}]
wire r_uop_bypass_sel_dst_enc = r_uop_bypass_hits_dst_0; // @[Mux.scala:50:70]
wire r_uop_bypass_sel_rs1_0 = r_uop_bypass_sel_rs1_enc; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs2_0 = r_uop_bypass_sel_rs2_enc; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_rs3_0 = r_uop_bypass_sel_rs3_enc; // @[OneHot.scala:83:30]
wire r_uop_bypass_sel_dst_0 = r_uop_bypass_sel_dst_enc; // @[OneHot.scala:83:30]
assign r_uop_bypassed_uop_prs1 = r_uop_bypass_hits_rs1_0 ? ren2_uops_0_pdst : next_uop_prs1; // @[rename-stage.scala:108:29, :123:24, :174:28, :175:18, :177:77, :194:{26,52}]
assign r_uop_bypassed_uop_prs2 = r_uop_bypass_hits_rs2_0 ? ren2_uops_0_pdst : next_uop_prs2; // @[rename-stage.scala:108:29, :123:24, :174:28, :175:18, :178:77, :195:{26,52}]
assign r_uop_bypassed_uop_prs3 = r_uop_bypass_hits_rs3_0 ? ren2_uops_0_pdst : next_uop_prs3; // @[rename-stage.scala:108:29, :123:24, :174:28, :175:18, :179:77, :196:{26,52}]
assign r_uop_bypassed_uop_stale_pdst = r_uop_bypass_hits_dst_0 ? ren2_uops_0_pdst : next_uop_stale_pdst; // @[rename-stage.scala:108:29, :123:24, :174:28, :175:18, :180:77, :197:{26,52}]
assign _r_uop_bypassed_uop_prs1_busy_T = next_uop_prs1_busy | r_uop_bypass_hits_rs1_0; // @[rename-stage.scala:123:24, :177:77, :199:45]
assign r_uop_bypassed_uop_prs1_busy = _r_uop_bypassed_uop_prs1_busy_T; // @[rename-stage.scala:174:28, :199:45]
assign _r_uop_bypassed_uop_prs2_busy_T = next_uop_prs2_busy | r_uop_bypass_hits_rs2_0; // @[rename-stage.scala:123:24, :178:77, :200:45]
assign r_uop_bypassed_uop_prs2_busy = _r_uop_bypassed_uop_prs2_busy_T; // @[rename-stage.scala:174:28, :200:45]
assign _r_uop_bypassed_uop_prs3_busy_T = next_uop_prs3_busy | r_uop_bypass_hits_rs3_0; // @[rename-stage.scala:123:24, :179:77, :201:45]
assign r_uop_bypassed_uop_prs3_busy = _r_uop_bypassed_uop_prs3_busy_T; // @[rename-stage.scala:174:28, :201:45]
wire [7:0] _r_uop_newuop_br_mask_T_1; // @[util.scala:74:35]
wire [7:0] r_uop_newuop_br_mask; // @[util.scala:73:26]
wire [7:0] _r_uop_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37]
assign _r_uop_newuop_br_mask_T_1 = r_uop_bypassed_uop_br_mask & _r_uop_newuop_br_mask_T; // @[util.scala:74:{35,37}]
assign r_uop_newuop_br_mask = _r_uop_newuop_br_mask_T_1; // @[util.scala:73:26, :74:35]
wire _ren2_br_tags_0_valid_T_3; // @[rename-stage.scala:241:43]
wire ren2_br_tags_0_valid; // @[rename-stage.scala:233:29]
wire _com_valids_0_T_2; // @[rename-stage.scala:243:92]
wire com_valids_0; // @[rename-stage.scala:236:29]
wire _rbk_valids_0_T_2; // @[rename-stage.scala:244:92]
wire rbk_valids_0; // @[rename-stage.scala:237:29]
wire _GEN_0 = ren2_uops_0_dst_rtype == 2'h1; // @[rename-stage.scala:108:29, :240:78]
wire _ren2_alloc_reqs_0_T; // @[rename-stage.scala:240:78]
assign _ren2_alloc_reqs_0_T = _GEN_0; // @[rename-stage.scala:240:78]
wire _io_ren_stalls_0_T; // @[rename-stage.scala:339:49]
assign _io_ren_stalls_0_T = _GEN_0; // @[rename-stage.scala:240:78, :339:49]
wire _ren2_alloc_reqs_0_T_1 = ren2_uops_0_ldst_val & _ren2_alloc_reqs_0_T; // @[rename-stage.scala:108:29, :240:{52,78}]
assign _ren2_alloc_reqs_0_T_2 = _ren2_alloc_reqs_0_T_1 & io_dis_fire_0_0; // @[rename-stage.scala:160:7, :240:{52,88}]
assign ren2_alloc_reqs_0 = _ren2_alloc_reqs_0_T_2; // @[rename-stage.scala:109:29, :240:88]
wire _ren2_br_tags_0_valid_T = ~ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_0_valid_T_1 = ren2_uops_0_is_br & _ren2_br_tags_0_valid_T; // @[rename-stage.scala:108:29]
wire _ren2_br_tags_0_valid_T_2 = _ren2_br_tags_0_valid_T_1 | ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29]
assign _ren2_br_tags_0_valid_T_3 = io_dis_fire_0_0 & _ren2_br_tags_0_valid_T_2; // @[rename-stage.scala:160:7, :241:43]
assign ren2_br_tags_0_valid = _ren2_br_tags_0_valid_T_3; // @[rename-stage.scala:233:29, :241:43]
wire _GEN_1 = io_com_uops_0_dst_rtype_0 == 2'h1; // @[rename-stage.scala:160:7, :243:82]
wire _com_valids_0_T; // @[rename-stage.scala:243:82]
assign _com_valids_0_T = _GEN_1; // @[rename-stage.scala:243:82]
wire _rbk_valids_0_T; // @[rename-stage.scala:244:82]
assign _rbk_valids_0_T = _GEN_1; // @[rename-stage.scala:243:82, :244:82]
wire _com_valids_0_T_1 = io_com_uops_0_ldst_val_0 & _com_valids_0_T; // @[rename-stage.scala:160:7, :243:{54,82}]
assign _com_valids_0_T_2 = _com_valids_0_T_1 & io_com_valids_0_0; // @[rename-stage.scala:160:7, :243:{54,92}]
assign com_valids_0 = _com_valids_0_T_2; // @[rename-stage.scala:236:29, :243:92]
wire _rbk_valids_0_T_1 = io_com_uops_0_ldst_val_0 & _rbk_valids_0_T; // @[rename-stage.scala:160:7, :244:{54,82}]
assign _rbk_valids_0_T_2 = _rbk_valids_0_T_1 & io_rbk_valids_0_0; // @[rename-stage.scala:160:7, :244:{54,92}]
assign rbk_valids_0 = _rbk_valids_0_T_2; // @[rename-stage.scala:237:29, :244:92]
wire [5:0] _remap_reqs_0_ldst_T; // @[rename-stage.scala:262:30]
wire [5:0] _remap_reqs_0_pdst_T; // @[rename-stage.scala:263:30]
wire _remap_reqs_0_valid_T; // @[rename-stage.scala:266:38]
wire [5:0] remap_reqs_0_ldst; // @[rename-stage.scala:253:24]
wire [5:0] remap_reqs_0_pdst; // @[rename-stage.scala:253:24]
wire remap_reqs_0_valid; // @[rename-stage.scala:253:24]
assign _remap_reqs_0_ldst_T = io_rollback_0 ? io_com_uops_0_ldst_0 : ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :160:7, :262:30]
assign remap_reqs_0_ldst = _remap_reqs_0_ldst_T; // @[rename-stage.scala:253:24, :262:30]
assign _remap_reqs_0_pdst_T = io_rollback_0 ? io_com_uops_0_stale_pdst_0 : ren2_uops_0_pdst; // @[rename-stage.scala:108:29, :160:7, :263:30]
assign remap_reqs_0_pdst = _remap_reqs_0_pdst_T; // @[rename-stage.scala:253:24, :263:30]
assign _remap_reqs_0_valid_T = ren2_alloc_reqs_0 | rbk_valids_0; // @[rename-stage.scala:109:29, :237:29, :266:38]
assign remap_reqs_0_valid = _remap_reqs_0_valid_T; // @[rename-stage.scala:253:24, :266:38]
wire _freelist_io_dealloc_pregs_0_valid_T = com_valids_0 | rbk_valids_0; // @[rename-stage.scala:236:29, :237:29, :293:37]
wire [5:0] _freelist_io_dealloc_pregs_0_bits_T = io_rollback_0 ? io_com_uops_0_pdst_0 : io_com_uops_0_stale_pdst_0; // @[rename-stage.scala:160:7, :295:33]
wire _ren2_uops_0_pdst_T = |ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :306:30]
assign ren2_uops_0_pdst = _ren2_uops_0_pdst_T_2; // @[rename-stage.scala:108:29, :306:20] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s4k1z3u_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_53
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a28d64s4k1z3u_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a28d64s4k1z3u_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a28d64s4k1z3u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_53 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a28d64s4k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a28d64s4k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_23 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<4>, vc_free : UInt<4>}}
wire _in_flight_WIRE : UInt<1>[4]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
regreset in_flight : UInt<1>[4], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_89 = and(_T_87, _T_88)
node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_126 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_133 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_140 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_173 = and(_T_171, _T_172)
node _T_174 = or(_T_12, _T_19)
node _T_175 = or(_T_174, _T_26)
node _T_176 = or(_T_175, _T_33)
node _T_177 = or(_T_176, _T_40)
node _T_178 = or(_T_177, _T_47)
node _T_179 = or(_T_178, _T_54)
node _T_180 = or(_T_179, _T_61)
node _T_181 = or(_T_180, _T_68)
node _T_182 = or(_T_181, _T_75)
node _T_183 = or(_T_182, _T_82)
node _T_184 = or(_T_183, _T_89)
node _T_185 = or(_T_184, _T_96)
node _T_186 = or(_T_185, _T_103)
node _T_187 = or(_T_186, _T_110)
node _T_188 = or(_T_187, _T_117)
node _T_189 = or(_T_188, _T_124)
node _T_190 = or(_T_189, _T_131)
node _T_191 = or(_T_190, _T_138)
node _T_192 = or(_T_191, _T_145)
node _T_193 = or(_T_192, _T_152)
node _T_194 = or(_T_193, _T_159)
node _T_195 = or(_T_194, _T_166)
node _T_196 = or(_T_195, _T_173)
node _T_197 = or(_T_5, _T_196)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_197, UInt<1>(0h1), "") : assert_1
node _T_201 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_202 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_203 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_204 = and(_T_202, _T_203)
node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_206 = and(_T_204, _T_205)
node _T_207 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_208 = and(_T_206, _T_207)
node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_210 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_211 = and(_T_209, _T_210)
node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_213 = and(_T_211, _T_212)
node _T_214 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_215 = and(_T_213, _T_214)
node _T_216 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_217 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_218 = and(_T_216, _T_217)
node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_220 = and(_T_218, _T_219)
node _T_221 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_224 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_227 = and(_T_225, _T_226)
node _T_228 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_229 = and(_T_227, _T_228)
node _T_230 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_231 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_232 = and(_T_230, _T_231)
node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_236 = and(_T_234, _T_235)
node _T_237 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_238 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_239 = and(_T_237, _T_238)
node _T_240 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_241 = and(_T_239, _T_240)
node _T_242 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_243 = and(_T_241, _T_242)
node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_245 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_313 = and(_T_311, _T_312)
node _T_314 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_315 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_316 = and(_T_314, _T_315)
node _T_317 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_322 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_329 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_330 = and(_T_328, _T_329)
node _T_331 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_332 = and(_T_330, _T_331)
node _T_333 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_336 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_339 = and(_T_337, _T_338)
node _T_340 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_341 = and(_T_339, _T_340)
node _T_342 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_343 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_346 = and(_T_344, _T_345)
node _T_347 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_348 = and(_T_346, _T_347)
node _T_349 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_350 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_353 = and(_T_351, _T_352)
node _T_354 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_355 = and(_T_353, _T_354)
node _T_356 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_357 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_364 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_369 = and(_T_367, _T_368)
node _T_370 = or(_T_208, _T_215)
node _T_371 = or(_T_370, _T_222)
node _T_372 = or(_T_371, _T_229)
node _T_373 = or(_T_372, _T_236)
node _T_374 = or(_T_373, _T_243)
node _T_375 = or(_T_374, _T_250)
node _T_376 = or(_T_375, _T_257)
node _T_377 = or(_T_376, _T_264)
node _T_378 = or(_T_377, _T_271)
node _T_379 = or(_T_378, _T_278)
node _T_380 = or(_T_379, _T_285)
node _T_381 = or(_T_380, _T_292)
node _T_382 = or(_T_381, _T_299)
node _T_383 = or(_T_382, _T_306)
node _T_384 = or(_T_383, _T_313)
node _T_385 = or(_T_384, _T_320)
node _T_386 = or(_T_385, _T_327)
node _T_387 = or(_T_386, _T_334)
node _T_388 = or(_T_387, _T_341)
node _T_389 = or(_T_388, _T_348)
node _T_390 = or(_T_389, _T_355)
node _T_391 = or(_T_390, _T_362)
node _T_392 = or(_T_391, _T_369)
node _T_393 = or(_T_201, _T_392)
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_393, UInt<1>(0h1), "") : assert_2
node _T_397 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_398 = or(_T_397, UInt<1>(0h0))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_398, UInt<1>(0h1), "") : assert_3
node _T_402 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_404 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_411 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_414 = and(_T_412, _T_413)
node _T_415 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_418 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_423 = and(_T_421, _T_422)
node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_425 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_430 = and(_T_428, _T_429)
node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_435 = and(_T_433, _T_434)
node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_437 = and(_T_435, _T_436)
node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_449 = and(_T_447, _T_448)
node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_456 = and(_T_454, _T_455)
node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = or(_T_409, _T_416)
node _T_460 = or(_T_459, _T_423)
node _T_461 = or(_T_460, _T_430)
node _T_462 = or(_T_461, _T_437)
node _T_463 = or(_T_462, _T_444)
node _T_464 = or(_T_463, _T_451)
node _T_465 = or(_T_464, _T_458)
node _T_466 = or(_T_402, _T_465)
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_466, UInt<1>(0h1), "") : assert_4 | module NoCMonitor_23( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h2; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_101 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_101( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_24 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], chosen_oh : UInt<4>[1]}
regreset lock_0 : UInt<4>, clock, reset, UInt<4>(0h0)
node unassigned_lo = cat(io.in[1].valid, io.in[0].valid)
node unassigned_hi = cat(io.in[3].valid, io.in[2].valid)
node _unassigned_T = cat(unassigned_hi, unassigned_lo)
node _unassigned_T_1 = not(lock_0)
node unassigned = and(_unassigned_T, _unassigned_T_1)
regreset mask : UInt<4>, clock, reset, UInt<4>(0h0)
wire choices : UInt<4>[1]
node _sel_T = not(mask)
node _sel_T_1 = and(unassigned, _sel_T)
node _sel_T_2 = cat(unassigned, _sel_T_1)
node _sel_T_3 = bits(_sel_T_2, 0, 0)
node _sel_T_4 = bits(_sel_T_2, 1, 1)
node _sel_T_5 = bits(_sel_T_2, 2, 2)
node _sel_T_6 = bits(_sel_T_2, 3, 3)
node _sel_T_7 = bits(_sel_T_2, 4, 4)
node _sel_T_8 = bits(_sel_T_2, 5, 5)
node _sel_T_9 = bits(_sel_T_2, 6, 6)
node _sel_T_10 = bits(_sel_T_2, 7, 7)
node _sel_T_11 = mux(_sel_T_10, UInt<8>(0h80), UInt<8>(0h0))
node _sel_T_12 = mux(_sel_T_9, UInt<8>(0h40), _sel_T_11)
node _sel_T_13 = mux(_sel_T_8, UInt<8>(0h20), _sel_T_12)
node _sel_T_14 = mux(_sel_T_7, UInt<8>(0h10), _sel_T_13)
node _sel_T_15 = mux(_sel_T_6, UInt<8>(0h8), _sel_T_14)
node _sel_T_16 = mux(_sel_T_5, UInt<8>(0h4), _sel_T_15)
node _sel_T_17 = mux(_sel_T_4, UInt<8>(0h2), _sel_T_16)
node sel = mux(_sel_T_3, UInt<8>(0h1), _sel_T_17)
node _choices_0_T = shr(sel, 4)
node _choices_0_T_1 = or(sel, _choices_0_T)
connect choices[0], _choices_0_T_1
node _T = not(choices[0])
node _T_1 = and(unassigned, _T)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = bits(_T_1, 1, 1)
node _T_4 = bits(_T_1, 2, 2)
node _T_5 = bits(_T_1, 3, 3)
node _T_6 = mux(_T_5, UInt<4>(0h8), UInt<4>(0h0))
node _T_7 = mux(_T_4, UInt<4>(0h4), _T_6)
node _T_8 = mux(_T_3, UInt<4>(0h2), _T_7)
node _T_9 = mux(_T_2, UInt<4>(0h1), _T_8)
connect io.in[0].ready, UInt<1>(0h0)
connect io.in[1].ready, UInt<1>(0h0)
connect io.in[2].ready, UInt<1>(0h0)
connect io.in[3].ready, UInt<1>(0h0)
node in_tails_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail)
node in_tails_hi = cat(io.in[3].bits.tail, io.in[2].bits.tail)
node in_tails = cat(in_tails_hi, in_tails_lo)
node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T)
node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2)
node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4)
node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6)
node in_valids_lo = cat(_in_valids_T_3, _in_valids_T_1)
node in_valids_hi = cat(_in_valids_T_7, _in_valids_T_5)
node in_valids = cat(in_valids_hi, in_valids_lo)
node _chosen_T = and(in_valids, lock_0)
node _chosen_T_1 = not(UInt<4>(0h0))
node _chosen_T_2 = and(_chosen_T, _chosen_T_1)
node _chosen_T_3 = orr(_chosen_T_2)
node chosen = mux(_chosen_T_3, lock_0, choices[0])
connect io.chosen_oh[0], chosen
node _io_out_0_valid_T = and(in_valids, chosen)
node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T)
connect io.out[0].valid, _io_out_0_valid_T_1
node _io_out_0_bits_T = bits(chosen, 0, 0)
node _io_out_0_bits_T_1 = bits(chosen, 1, 1)
node _io_out_0_bits_T_2 = bits(chosen, 2, 2)
node _io_out_0_bits_T_3 = bits(chosen, 3, 3)
wire _io_out_0_bits_WIRE : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}
node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_7 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_8 = or(_io_out_0_bits_T_4, _io_out_0_bits_T_5)
node _io_out_0_bits_T_9 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_6)
node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_9, _io_out_0_bits_T_7)
wire _io_out_0_bits_WIRE_1 : UInt<1>
connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_10
connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1
wire _io_out_0_bits_WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_out_0_bits_WIRE_3 : UInt<1>[3]
node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_15 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_12)
node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_15, _io_out_0_bits_T_13)
node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_14)
wire _io_out_0_bits_WIRE_4 : UInt<1>
connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_17
connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4
node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_21 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19)
node _io_out_0_bits_T_23 = or(_io_out_0_bits_T_22, _io_out_0_bits_T_20)
node _io_out_0_bits_T_24 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_21)
wire _io_out_0_bits_WIRE_5 : UInt<1>
connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_24
connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5
node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_29 = or(_io_out_0_bits_T_25, _io_out_0_bits_T_26)
node _io_out_0_bits_T_30 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_27)
node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_30, _io_out_0_bits_T_28)
wire _io_out_0_bits_WIRE_6 : UInt<1>
connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_31
connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6
connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3
wire _io_out_0_bits_WIRE_7 : UInt<1>[3]
node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_33)
node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_34)
node _io_out_0_bits_T_38 = or(_io_out_0_bits_T_37, _io_out_0_bits_T_35)
wire _io_out_0_bits_WIRE_8 : UInt<1>
connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_38
connect _io_out_0_bits_WIRE_7[0], _io_out_0_bits_WIRE_8
node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_41 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_42 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_43 = or(_io_out_0_bits_T_39, _io_out_0_bits_T_40)
node _io_out_0_bits_T_44 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_41)
node _io_out_0_bits_T_45 = or(_io_out_0_bits_T_44, _io_out_0_bits_T_42)
wire _io_out_0_bits_WIRE_9 : UInt<1>
connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_45
connect _io_out_0_bits_WIRE_7[1], _io_out_0_bits_WIRE_9
node _io_out_0_bits_T_46 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_47 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[2], UInt<1>(0h0))
node _io_out_0_bits_T_50 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_47)
node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_50, _io_out_0_bits_T_48)
node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_49)
wire _io_out_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_52
connect _io_out_0_bits_WIRE_7[2], _io_out_0_bits_WIRE_10
connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_7
wire _io_out_0_bits_WIRE_11 : UInt<1>[1]
node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_56 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54)
node _io_out_0_bits_T_58 = or(_io_out_0_bits_T_57, _io_out_0_bits_T_55)
node _io_out_0_bits_T_59 = or(_io_out_0_bits_T_58, _io_out_0_bits_T_56)
wire _io_out_0_bits_WIRE_12 : UInt<1>
connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_59
connect _io_out_0_bits_WIRE_11[0], _io_out_0_bits_WIRE_12
connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_11
connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2
connect io.out[0].bits, _io_out_0_bits_WIRE
node _T_10 = bits(chosen, 0, 0)
node _T_11 = and(_T_10, io.out[0].ready)
when _T_11 :
connect io.in[0].ready, UInt<1>(0h1)
node _T_12 = bits(chosen, 1, 1)
node _T_13 = and(_T_12, io.out[0].ready)
when _T_13 :
connect io.in[1].ready, UInt<1>(0h1)
node _T_14 = bits(chosen, 2, 2)
node _T_15 = and(_T_14, io.out[0].ready)
when _T_15 :
connect io.in[2].ready, UInt<1>(0h1)
node _T_16 = bits(chosen, 3, 3)
node _T_17 = and(_T_16, io.out[0].ready)
when _T_17 :
connect io.in[3].ready, UInt<1>(0h1)
node _T_18 = or(UInt<4>(0h0), chosen)
node _T_19 = and(io.out[0].ready, io.out[0].valid)
when _T_19 :
node _lock_0_T = not(in_tails)
node _lock_0_T_1 = and(chosen, _lock_0_T)
connect lock_0, _lock_0_T_1
node _T_20 = and(io.out[0].ready, io.out[0].valid)
when _T_20 :
node _mask_T = shr(io.chosen_oh[0], 0)
node _mask_T_1 = shr(io.chosen_oh[0], 1)
node _mask_T_2 = shr(io.chosen_oh[0], 2)
node _mask_T_3 = shr(io.chosen_oh[0], 3)
node _mask_T_4 = or(_mask_T, _mask_T_1)
node _mask_T_5 = or(_mask_T_4, _mask_T_2)
node _mask_T_6 = or(_mask_T_5, _mask_T_3)
connect mask, _mask_T_6
else :
node _mask_T_7 = not(mask)
node _mask_T_8 = eq(_mask_T_7, UInt<1>(0h0))
node _mask_T_9 = shl(mask, 1)
node _mask_T_10 = or(_mask_T_9, UInt<1>(0h1))
node _mask_T_11 = mux(_mask_T_8, UInt<1>(0h0), _mask_T_10)
connect mask, _mask_T_11 | module SwitchArbiter_24( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_1_ready, // @[SwitchAllocator.scala:18:14]
input io_in_1_valid, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_2_ready, // @[SwitchAllocator.scala:18:14]
input io_in_2_valid, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_3_ready, // @[SwitchAllocator.scala:18:14]
input io_in_3_valid, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [3:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [3:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [3:0] unassigned = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [3:0] mask; // @[SwitchAllocator.scala:27:21]
wire [3:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [7:0] sel = _sel_T_1[0] ? 8'h1 : _sel_T_1[1] ? 8'h2 : _sel_T_1[2] ? 8'h4 : _sel_T_1[3] ? 8'h8 : unassigned[0] ? 8'h10 : unassigned[1] ? 8'h20 : unassigned[2] ? 8'h40 : {unassigned[3], 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] in_valids = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24]
wire [3:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[3:0] | sel[7:4]; // @[Mux.scala:50:70]
wire [3:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire [2:0] _GEN = chosen[2:0] | chosen[3:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [1:0] _GEN_0 = _GEN[1:0] | chosen[3:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 4'h0; // @[SwitchAllocator.scala:24:38]
mask <= 4'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}]
lock_0 <= chosen & ~{io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= (|_io_out_0_valid_T) ? {chosen[3], _GEN[2], _GEN_0[1], _GEN_0[0] | chosen[3]} : (&mask) ? 4'h0 : {mask[2:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BoomNonBlockingDCache_1 :
input clock : Clock
input reset : Reset
output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
output io : { flip lsu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1]}, s1_kill : UInt<1>[1], flip resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1], flip nack : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, exception : UInt<1>, rob_pnr_idx : UInt<5>, rob_head_idx : UInt<5>, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, force_order : UInt<1>, flip ordered : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>}}}
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
inst wb of BoomWritebackUnit_1
connect wb.clock, clock
connect wb.reset, reset
inst prober of BoomProbeUnit_1
connect prober.clock, clock
connect prober.reset, reset
inst mshrs of BoomMSHRFile_1
connect mshrs.clock, clock
connect mshrs.reset, reset
connect mshrs.io.clear_all, io.lsu.force_order
connect mshrs.io.brupdate.b2.target_offset, io.lsu.brupdate.b2.target_offset
connect mshrs.io.brupdate.b2.jalr_target, io.lsu.brupdate.b2.jalr_target
connect mshrs.io.brupdate.b2.pc_sel, io.lsu.brupdate.b2.pc_sel
connect mshrs.io.brupdate.b2.cfi_type, io.lsu.brupdate.b2.cfi_type
connect mshrs.io.brupdate.b2.taken, io.lsu.brupdate.b2.taken
connect mshrs.io.brupdate.b2.mispredict, io.lsu.brupdate.b2.mispredict
connect mshrs.io.brupdate.b2.valid, io.lsu.brupdate.b2.valid
connect mshrs.io.brupdate.b2.uop.debug_tsrc, io.lsu.brupdate.b2.uop.debug_tsrc
connect mshrs.io.brupdate.b2.uop.debug_fsrc, io.lsu.brupdate.b2.uop.debug_fsrc
connect mshrs.io.brupdate.b2.uop.bp_xcpt_if, io.lsu.brupdate.b2.uop.bp_xcpt_if
connect mshrs.io.brupdate.b2.uop.bp_debug_if, io.lsu.brupdate.b2.uop.bp_debug_if
connect mshrs.io.brupdate.b2.uop.xcpt_ma_if, io.lsu.brupdate.b2.uop.xcpt_ma_if
connect mshrs.io.brupdate.b2.uop.xcpt_ae_if, io.lsu.brupdate.b2.uop.xcpt_ae_if
connect mshrs.io.brupdate.b2.uop.xcpt_pf_if, io.lsu.brupdate.b2.uop.xcpt_pf_if
connect mshrs.io.brupdate.b2.uop.fp_single, io.lsu.brupdate.b2.uop.fp_single
connect mshrs.io.brupdate.b2.uop.fp_val, io.lsu.brupdate.b2.uop.fp_val
connect mshrs.io.brupdate.b2.uop.frs3_en, io.lsu.brupdate.b2.uop.frs3_en
connect mshrs.io.brupdate.b2.uop.lrs2_rtype, io.lsu.brupdate.b2.uop.lrs2_rtype
connect mshrs.io.brupdate.b2.uop.lrs1_rtype, io.lsu.brupdate.b2.uop.lrs1_rtype
connect mshrs.io.brupdate.b2.uop.dst_rtype, io.lsu.brupdate.b2.uop.dst_rtype
connect mshrs.io.brupdate.b2.uop.ldst_val, io.lsu.brupdate.b2.uop.ldst_val
connect mshrs.io.brupdate.b2.uop.lrs3, io.lsu.brupdate.b2.uop.lrs3
connect mshrs.io.brupdate.b2.uop.lrs2, io.lsu.brupdate.b2.uop.lrs2
connect mshrs.io.brupdate.b2.uop.lrs1, io.lsu.brupdate.b2.uop.lrs1
connect mshrs.io.brupdate.b2.uop.ldst, io.lsu.brupdate.b2.uop.ldst
connect mshrs.io.brupdate.b2.uop.ldst_is_rs1, io.lsu.brupdate.b2.uop.ldst_is_rs1
connect mshrs.io.brupdate.b2.uop.flush_on_commit, io.lsu.brupdate.b2.uop.flush_on_commit
connect mshrs.io.brupdate.b2.uop.is_unique, io.lsu.brupdate.b2.uop.is_unique
connect mshrs.io.brupdate.b2.uop.is_sys_pc2epc, io.lsu.brupdate.b2.uop.is_sys_pc2epc
connect mshrs.io.brupdate.b2.uop.uses_stq, io.lsu.brupdate.b2.uop.uses_stq
connect mshrs.io.brupdate.b2.uop.uses_ldq, io.lsu.brupdate.b2.uop.uses_ldq
connect mshrs.io.brupdate.b2.uop.is_amo, io.lsu.brupdate.b2.uop.is_amo
connect mshrs.io.brupdate.b2.uop.is_fencei, io.lsu.brupdate.b2.uop.is_fencei
connect mshrs.io.brupdate.b2.uop.is_fence, io.lsu.brupdate.b2.uop.is_fence
connect mshrs.io.brupdate.b2.uop.mem_signed, io.lsu.brupdate.b2.uop.mem_signed
connect mshrs.io.brupdate.b2.uop.mem_size, io.lsu.brupdate.b2.uop.mem_size
connect mshrs.io.brupdate.b2.uop.mem_cmd, io.lsu.brupdate.b2.uop.mem_cmd
connect mshrs.io.brupdate.b2.uop.bypassable, io.lsu.brupdate.b2.uop.bypassable
connect mshrs.io.brupdate.b2.uop.exc_cause, io.lsu.brupdate.b2.uop.exc_cause
connect mshrs.io.brupdate.b2.uop.exception, io.lsu.brupdate.b2.uop.exception
connect mshrs.io.brupdate.b2.uop.stale_pdst, io.lsu.brupdate.b2.uop.stale_pdst
connect mshrs.io.brupdate.b2.uop.ppred_busy, io.lsu.brupdate.b2.uop.ppred_busy
connect mshrs.io.brupdate.b2.uop.prs3_busy, io.lsu.brupdate.b2.uop.prs3_busy
connect mshrs.io.brupdate.b2.uop.prs2_busy, io.lsu.brupdate.b2.uop.prs2_busy
connect mshrs.io.brupdate.b2.uop.prs1_busy, io.lsu.brupdate.b2.uop.prs1_busy
connect mshrs.io.brupdate.b2.uop.ppred, io.lsu.brupdate.b2.uop.ppred
connect mshrs.io.brupdate.b2.uop.prs3, io.lsu.brupdate.b2.uop.prs3
connect mshrs.io.brupdate.b2.uop.prs2, io.lsu.brupdate.b2.uop.prs2
connect mshrs.io.brupdate.b2.uop.prs1, io.lsu.brupdate.b2.uop.prs1
connect mshrs.io.brupdate.b2.uop.pdst, io.lsu.brupdate.b2.uop.pdst
connect mshrs.io.brupdate.b2.uop.rxq_idx, io.lsu.brupdate.b2.uop.rxq_idx
connect mshrs.io.brupdate.b2.uop.stq_idx, io.lsu.brupdate.b2.uop.stq_idx
connect mshrs.io.brupdate.b2.uop.ldq_idx, io.lsu.brupdate.b2.uop.ldq_idx
connect mshrs.io.brupdate.b2.uop.rob_idx, io.lsu.brupdate.b2.uop.rob_idx
connect mshrs.io.brupdate.b2.uop.csr_addr, io.lsu.brupdate.b2.uop.csr_addr
connect mshrs.io.brupdate.b2.uop.imm_packed, io.lsu.brupdate.b2.uop.imm_packed
connect mshrs.io.brupdate.b2.uop.taken, io.lsu.brupdate.b2.uop.taken
connect mshrs.io.brupdate.b2.uop.pc_lob, io.lsu.brupdate.b2.uop.pc_lob
connect mshrs.io.brupdate.b2.uop.edge_inst, io.lsu.brupdate.b2.uop.edge_inst
connect mshrs.io.brupdate.b2.uop.ftq_idx, io.lsu.brupdate.b2.uop.ftq_idx
connect mshrs.io.brupdate.b2.uop.br_tag, io.lsu.brupdate.b2.uop.br_tag
connect mshrs.io.brupdate.b2.uop.br_mask, io.lsu.brupdate.b2.uop.br_mask
connect mshrs.io.brupdate.b2.uop.is_sfb, io.lsu.brupdate.b2.uop.is_sfb
connect mshrs.io.brupdate.b2.uop.is_jal, io.lsu.brupdate.b2.uop.is_jal
connect mshrs.io.brupdate.b2.uop.is_jalr, io.lsu.brupdate.b2.uop.is_jalr
connect mshrs.io.brupdate.b2.uop.is_br, io.lsu.brupdate.b2.uop.is_br
connect mshrs.io.brupdate.b2.uop.iw_p2_poisoned, io.lsu.brupdate.b2.uop.iw_p2_poisoned
connect mshrs.io.brupdate.b2.uop.iw_p1_poisoned, io.lsu.brupdate.b2.uop.iw_p1_poisoned
connect mshrs.io.brupdate.b2.uop.iw_state, io.lsu.brupdate.b2.uop.iw_state
connect mshrs.io.brupdate.b2.uop.ctrl.is_std, io.lsu.brupdate.b2.uop.ctrl.is_std
connect mshrs.io.brupdate.b2.uop.ctrl.is_sta, io.lsu.brupdate.b2.uop.ctrl.is_sta
connect mshrs.io.brupdate.b2.uop.ctrl.is_load, io.lsu.brupdate.b2.uop.ctrl.is_load
connect mshrs.io.brupdate.b2.uop.ctrl.csr_cmd, io.lsu.brupdate.b2.uop.ctrl.csr_cmd
connect mshrs.io.brupdate.b2.uop.ctrl.fcn_dw, io.lsu.brupdate.b2.uop.ctrl.fcn_dw
connect mshrs.io.brupdate.b2.uop.ctrl.op_fcn, io.lsu.brupdate.b2.uop.ctrl.op_fcn
connect mshrs.io.brupdate.b2.uop.ctrl.imm_sel, io.lsu.brupdate.b2.uop.ctrl.imm_sel
connect mshrs.io.brupdate.b2.uop.ctrl.op2_sel, io.lsu.brupdate.b2.uop.ctrl.op2_sel
connect mshrs.io.brupdate.b2.uop.ctrl.op1_sel, io.lsu.brupdate.b2.uop.ctrl.op1_sel
connect mshrs.io.brupdate.b2.uop.ctrl.br_type, io.lsu.brupdate.b2.uop.ctrl.br_type
connect mshrs.io.brupdate.b2.uop.fu_code, io.lsu.brupdate.b2.uop.fu_code
connect mshrs.io.brupdate.b2.uop.iq_type, io.lsu.brupdate.b2.uop.iq_type
connect mshrs.io.brupdate.b2.uop.debug_pc, io.lsu.brupdate.b2.uop.debug_pc
connect mshrs.io.brupdate.b2.uop.is_rvc, io.lsu.brupdate.b2.uop.is_rvc
connect mshrs.io.brupdate.b2.uop.debug_inst, io.lsu.brupdate.b2.uop.debug_inst
connect mshrs.io.brupdate.b2.uop.inst, io.lsu.brupdate.b2.uop.inst
connect mshrs.io.brupdate.b2.uop.uopc, io.lsu.brupdate.b2.uop.uopc
connect mshrs.io.brupdate.b1.mispredict_mask, io.lsu.brupdate.b1.mispredict_mask
connect mshrs.io.brupdate.b1.resolve_mask, io.lsu.brupdate.b1.resolve_mask
connect mshrs.io.exception, io.lsu.exception
connect mshrs.io.rob_pnr_idx, io.lsu.rob_pnr_idx
connect mshrs.io.rob_head_idx, io.lsu.rob_head_idx
inst meta_0 of L1MetadataArray_1
connect meta_0.clock, clock
connect meta_0.reset, reset
inst metaWriteArb of Arbiter2_L1MetaWriteReq_3
connect metaWriteArb.clock, clock
connect metaWriteArb.reset, reset
inst metaReadArb of Arbiter6_BoomL1MetaReadReq_1
connect metaReadArb.clock, clock
connect metaReadArb.reset, reset
invalidate metaReadArb.io.in[0].bits.req[0].tag
invalidate metaReadArb.io.in[0].bits.req[0].way_en
invalidate metaReadArb.io.in[0].bits.req[0].idx
invalidate metaReadArb.io.in[0].valid
invalidate metaReadArb.io.in[0].ready
invalidate metaReadArb.io.in[1].bits.req[0].tag
invalidate metaReadArb.io.in[1].bits.req[0].way_en
invalidate metaReadArb.io.in[1].bits.req[0].idx
invalidate metaReadArb.io.in[1].valid
invalidate metaReadArb.io.in[1].ready
invalidate metaReadArb.io.in[2].bits.req[0].tag
invalidate metaReadArb.io.in[2].bits.req[0].way_en
invalidate metaReadArb.io.in[2].bits.req[0].idx
invalidate metaReadArb.io.in[2].valid
invalidate metaReadArb.io.in[2].ready
invalidate metaReadArb.io.in[3].bits.req[0].tag
invalidate metaReadArb.io.in[3].bits.req[0].way_en
invalidate metaReadArb.io.in[3].bits.req[0].idx
invalidate metaReadArb.io.in[3].valid
invalidate metaReadArb.io.in[3].ready
invalidate metaReadArb.io.in[4].bits.req[0].tag
invalidate metaReadArb.io.in[4].bits.req[0].way_en
invalidate metaReadArb.io.in[4].bits.req[0].idx
invalidate metaReadArb.io.in[4].valid
invalidate metaReadArb.io.in[4].ready
invalidate metaReadArb.io.in[5].bits.req[0].tag
invalidate metaReadArb.io.in[5].bits.req[0].way_en
invalidate metaReadArb.io.in[5].bits.req[0].idx
invalidate metaReadArb.io.in[5].valid
invalidate metaReadArb.io.in[5].ready
node _meta_0_io_write_valid_T = and(metaWriteArb.io.out.ready, metaWriteArb.io.out.valid)
connect meta_0.io.write.valid, _meta_0_io_write_valid_T
connect meta_0.io.write.bits.data.tag, metaWriteArb.io.out.bits.data.tag
connect meta_0.io.write.bits.data.coh.state, metaWriteArb.io.out.bits.data.coh.state
connect meta_0.io.write.bits.tag, metaWriteArb.io.out.bits.tag
connect meta_0.io.write.bits.way_en, metaWriteArb.io.out.bits.way_en
connect meta_0.io.write.bits.idx, metaWriteArb.io.out.bits.idx
connect meta_0.io.read.valid, metaReadArb.io.out.valid
connect meta_0.io.read.bits.tag, metaReadArb.io.out.bits.req[0].tag
connect meta_0.io.read.bits.way_en, metaReadArb.io.out.bits.req[0].way_en
connect meta_0.io.read.bits.idx, metaReadArb.io.out.bits.req[0].idx
connect metaReadArb.io.out.ready, meta_0.io.read.ready
connect metaWriteArb.io.out.ready, meta_0.io.write.ready
inst data of BoomDuplicatedDataArray_1
connect data.clock, clock
connect data.reset, reset
inst dataWriteArb of Arbiter2_L1DataWriteReq_3
connect dataWriteArb.clock, clock
connect dataWriteArb.reset, reset
inst dataReadArb of Arbiter3_BoomL1DataReadReq_1
connect dataReadArb.clock, clock
connect dataReadArb.reset, reset
invalidate dataReadArb.io.in[0].bits.valid[0]
invalidate dataReadArb.io.in[0].bits.req[0].addr
invalidate dataReadArb.io.in[0].bits.req[0].way_en
invalidate dataReadArb.io.in[0].valid
invalidate dataReadArb.io.in[0].ready
invalidate dataReadArb.io.in[1].bits.valid[0]
invalidate dataReadArb.io.in[1].bits.req[0].addr
invalidate dataReadArb.io.in[1].bits.req[0].way_en
invalidate dataReadArb.io.in[1].valid
invalidate dataReadArb.io.in[1].ready
invalidate dataReadArb.io.in[2].bits.valid[0]
invalidate dataReadArb.io.in[2].bits.req[0].addr
invalidate dataReadArb.io.in[2].bits.req[0].way_en
invalidate dataReadArb.io.in[2].valid
invalidate dataReadArb.io.in[2].ready
node _data_io_read_0_valid_T = and(dataReadArb.io.out.bits.valid[0], dataReadArb.io.out.valid)
connect data.io.read[0].valid, _data_io_read_0_valid_T
connect data.io.read[0].bits.addr, dataReadArb.io.out.bits.req[0].addr
connect data.io.read[0].bits.way_en, dataReadArb.io.out.bits.req[0].way_en
connect dataReadArb.io.out.ready, UInt<1>(0h1)
node _data_io_write_valid_T = and(dataWriteArb.io.out.ready, dataWriteArb.io.out.valid)
connect data.io.write.valid, _data_io_write_valid_T
connect data.io.write.bits.data, dataWriteArb.io.out.bits.data
connect data.io.write.bits.wmask, dataWriteArb.io.out.bits.wmask
connect data.io.write.bits.addr, dataWriteArb.io.out.bits.addr
connect data.io.write.bits.way_en, dataWriteArb.io.out.bits.way_en
connect dataWriteArb.io.out.ready, UInt<1>(0h1)
node _io_lsu_req_ready_T = and(metaReadArb.io.in[4].ready, dataReadArb.io.in[2].ready)
connect io.lsu.req.ready, _io_lsu_req_ready_T
connect metaReadArb.io.in[4].valid, io.lsu.req.valid
connect dataReadArb.io.in[2].valid, io.lsu.req.valid
node _metaReadArb_io_in_4_bits_req_0_idx_T = shr(io.lsu.req.bits[0].bits.addr, 6)
connect metaReadArb.io.in[4].bits.req[0].idx, _metaReadArb_io_in_4_bits_req_0_idx_T
invalidate metaReadArb.io.in[4].bits.req[0].way_en
invalidate metaReadArb.io.in[4].bits.req[0].tag
connect dataReadArb.io.in[2].bits.valid[0], io.lsu.req.bits[0].valid
connect dataReadArb.io.in[2].bits.req[0].addr, io.lsu.req.bits[0].bits.addr
node _dataReadArb_io_in_2_bits_req_0_way_en_T = not(UInt<4>(0h0))
connect dataReadArb.io.in[2].bits.req[0].way_en, _dataReadArb_io_in_2_bits_req_0_way_en_T
wire replay_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate replay_req[0].is_hella
invalidate replay_req[0].data
invalidate replay_req[0].addr
invalidate replay_req[0].uop.debug_tsrc
invalidate replay_req[0].uop.debug_fsrc
invalidate replay_req[0].uop.bp_xcpt_if
invalidate replay_req[0].uop.bp_debug_if
invalidate replay_req[0].uop.xcpt_ma_if
invalidate replay_req[0].uop.xcpt_ae_if
invalidate replay_req[0].uop.xcpt_pf_if
invalidate replay_req[0].uop.fp_single
invalidate replay_req[0].uop.fp_val
invalidate replay_req[0].uop.frs3_en
invalidate replay_req[0].uop.lrs2_rtype
invalidate replay_req[0].uop.lrs1_rtype
invalidate replay_req[0].uop.dst_rtype
invalidate replay_req[0].uop.ldst_val
invalidate replay_req[0].uop.lrs3
invalidate replay_req[0].uop.lrs2
invalidate replay_req[0].uop.lrs1
invalidate replay_req[0].uop.ldst
invalidate replay_req[0].uop.ldst_is_rs1
invalidate replay_req[0].uop.flush_on_commit
invalidate replay_req[0].uop.is_unique
invalidate replay_req[0].uop.is_sys_pc2epc
invalidate replay_req[0].uop.uses_stq
invalidate replay_req[0].uop.uses_ldq
invalidate replay_req[0].uop.is_amo
invalidate replay_req[0].uop.is_fencei
invalidate replay_req[0].uop.is_fence
invalidate replay_req[0].uop.mem_signed
invalidate replay_req[0].uop.mem_size
invalidate replay_req[0].uop.mem_cmd
invalidate replay_req[0].uop.bypassable
invalidate replay_req[0].uop.exc_cause
invalidate replay_req[0].uop.exception
invalidate replay_req[0].uop.stale_pdst
invalidate replay_req[0].uop.ppred_busy
invalidate replay_req[0].uop.prs3_busy
invalidate replay_req[0].uop.prs2_busy
invalidate replay_req[0].uop.prs1_busy
invalidate replay_req[0].uop.ppred
invalidate replay_req[0].uop.prs3
invalidate replay_req[0].uop.prs2
invalidate replay_req[0].uop.prs1
invalidate replay_req[0].uop.pdst
invalidate replay_req[0].uop.rxq_idx
invalidate replay_req[0].uop.stq_idx
invalidate replay_req[0].uop.ldq_idx
invalidate replay_req[0].uop.rob_idx
invalidate replay_req[0].uop.csr_addr
invalidate replay_req[0].uop.imm_packed
invalidate replay_req[0].uop.taken
invalidate replay_req[0].uop.pc_lob
invalidate replay_req[0].uop.edge_inst
invalidate replay_req[0].uop.ftq_idx
invalidate replay_req[0].uop.br_tag
invalidate replay_req[0].uop.br_mask
invalidate replay_req[0].uop.is_sfb
invalidate replay_req[0].uop.is_jal
invalidate replay_req[0].uop.is_jalr
invalidate replay_req[0].uop.is_br
invalidate replay_req[0].uop.iw_p2_poisoned
invalidate replay_req[0].uop.iw_p1_poisoned
invalidate replay_req[0].uop.iw_state
invalidate replay_req[0].uop.ctrl.is_std
invalidate replay_req[0].uop.ctrl.is_sta
invalidate replay_req[0].uop.ctrl.is_load
invalidate replay_req[0].uop.ctrl.csr_cmd
invalidate replay_req[0].uop.ctrl.fcn_dw
invalidate replay_req[0].uop.ctrl.op_fcn
invalidate replay_req[0].uop.ctrl.imm_sel
invalidate replay_req[0].uop.ctrl.op2_sel
invalidate replay_req[0].uop.ctrl.op1_sel
invalidate replay_req[0].uop.ctrl.br_type
invalidate replay_req[0].uop.fu_code
invalidate replay_req[0].uop.iq_type
invalidate replay_req[0].uop.debug_pc
invalidate replay_req[0].uop.is_rvc
invalidate replay_req[0].uop.debug_inst
invalidate replay_req[0].uop.inst
invalidate replay_req[0].uop.uopc
connect replay_req[0].uop, mshrs.io.replay.bits.uop
connect replay_req[0].addr, mshrs.io.replay.bits.addr
connect replay_req[0].data, mshrs.io.replay.bits.data
connect replay_req[0].is_hella, mshrs.io.replay.bits.is_hella
node _mshrs_io_replay_ready_T = and(metaReadArb.io.in[0].ready, dataReadArb.io.in[0].ready)
connect mshrs.io.replay.ready, _mshrs_io_replay_ready_T
connect metaReadArb.io.in[0].valid, mshrs.io.replay.valid
node _metaReadArb_io_in_0_bits_req_0_idx_T = shr(mshrs.io.replay.bits.addr, 6)
connect metaReadArb.io.in[0].bits.req[0].idx, _metaReadArb_io_in_0_bits_req_0_idx_T
invalidate metaReadArb.io.in[0].bits.req[0].way_en
invalidate metaReadArb.io.in[0].bits.req[0].tag
connect dataReadArb.io.in[0].valid, mshrs.io.replay.valid
connect dataReadArb.io.in[0].bits.req[0].addr, mshrs.io.replay.bits.addr
connect dataReadArb.io.in[0].bits.req[0].way_en, mshrs.io.replay.bits.way_en
wire _WIRE : UInt<1>[1]
connect _WIRE[0], UInt<1>(0h1)
connect dataReadArb.io.in[0].bits.valid[0], _WIRE[0]
wire mshr_read_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate mshr_read_req[0].is_hella
invalidate mshr_read_req[0].data
invalidate mshr_read_req[0].addr
invalidate mshr_read_req[0].uop.debug_tsrc
invalidate mshr_read_req[0].uop.debug_fsrc
invalidate mshr_read_req[0].uop.bp_xcpt_if
invalidate mshr_read_req[0].uop.bp_debug_if
invalidate mshr_read_req[0].uop.xcpt_ma_if
invalidate mshr_read_req[0].uop.xcpt_ae_if
invalidate mshr_read_req[0].uop.xcpt_pf_if
invalidate mshr_read_req[0].uop.fp_single
invalidate mshr_read_req[0].uop.fp_val
invalidate mshr_read_req[0].uop.frs3_en
invalidate mshr_read_req[0].uop.lrs2_rtype
invalidate mshr_read_req[0].uop.lrs1_rtype
invalidate mshr_read_req[0].uop.dst_rtype
invalidate mshr_read_req[0].uop.ldst_val
invalidate mshr_read_req[0].uop.lrs3
invalidate mshr_read_req[0].uop.lrs2
invalidate mshr_read_req[0].uop.lrs1
invalidate mshr_read_req[0].uop.ldst
invalidate mshr_read_req[0].uop.ldst_is_rs1
invalidate mshr_read_req[0].uop.flush_on_commit
invalidate mshr_read_req[0].uop.is_unique
invalidate mshr_read_req[0].uop.is_sys_pc2epc
invalidate mshr_read_req[0].uop.uses_stq
invalidate mshr_read_req[0].uop.uses_ldq
invalidate mshr_read_req[0].uop.is_amo
invalidate mshr_read_req[0].uop.is_fencei
invalidate mshr_read_req[0].uop.is_fence
invalidate mshr_read_req[0].uop.mem_signed
invalidate mshr_read_req[0].uop.mem_size
invalidate mshr_read_req[0].uop.mem_cmd
invalidate mshr_read_req[0].uop.bypassable
invalidate mshr_read_req[0].uop.exc_cause
invalidate mshr_read_req[0].uop.exception
invalidate mshr_read_req[0].uop.stale_pdst
invalidate mshr_read_req[0].uop.ppred_busy
invalidate mshr_read_req[0].uop.prs3_busy
invalidate mshr_read_req[0].uop.prs2_busy
invalidate mshr_read_req[0].uop.prs1_busy
invalidate mshr_read_req[0].uop.ppred
invalidate mshr_read_req[0].uop.prs3
invalidate mshr_read_req[0].uop.prs2
invalidate mshr_read_req[0].uop.prs1
invalidate mshr_read_req[0].uop.pdst
invalidate mshr_read_req[0].uop.rxq_idx
invalidate mshr_read_req[0].uop.stq_idx
invalidate mshr_read_req[0].uop.ldq_idx
invalidate mshr_read_req[0].uop.rob_idx
invalidate mshr_read_req[0].uop.csr_addr
invalidate mshr_read_req[0].uop.imm_packed
invalidate mshr_read_req[0].uop.taken
invalidate mshr_read_req[0].uop.pc_lob
invalidate mshr_read_req[0].uop.edge_inst
invalidate mshr_read_req[0].uop.ftq_idx
invalidate mshr_read_req[0].uop.br_tag
invalidate mshr_read_req[0].uop.br_mask
invalidate mshr_read_req[0].uop.is_sfb
invalidate mshr_read_req[0].uop.is_jal
invalidate mshr_read_req[0].uop.is_jalr
invalidate mshr_read_req[0].uop.is_br
invalidate mshr_read_req[0].uop.iw_p2_poisoned
invalidate mshr_read_req[0].uop.iw_p1_poisoned
invalidate mshr_read_req[0].uop.iw_state
invalidate mshr_read_req[0].uop.ctrl.is_std
invalidate mshr_read_req[0].uop.ctrl.is_sta
invalidate mshr_read_req[0].uop.ctrl.is_load
invalidate mshr_read_req[0].uop.ctrl.csr_cmd
invalidate mshr_read_req[0].uop.ctrl.fcn_dw
invalidate mshr_read_req[0].uop.ctrl.op_fcn
invalidate mshr_read_req[0].uop.ctrl.imm_sel
invalidate mshr_read_req[0].uop.ctrl.op2_sel
invalidate mshr_read_req[0].uop.ctrl.op1_sel
invalidate mshr_read_req[0].uop.ctrl.br_type
invalidate mshr_read_req[0].uop.fu_code
invalidate mshr_read_req[0].uop.iq_type
invalidate mshr_read_req[0].uop.debug_pc
invalidate mshr_read_req[0].uop.is_rvc
invalidate mshr_read_req[0].uop.debug_inst
invalidate mshr_read_req[0].uop.inst
invalidate mshr_read_req[0].uop.uopc
wire mshr_read_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate mshr_read_req_0_uop_uop.debug_tsrc
invalidate mshr_read_req_0_uop_uop.debug_fsrc
invalidate mshr_read_req_0_uop_uop.bp_xcpt_if
invalidate mshr_read_req_0_uop_uop.bp_debug_if
invalidate mshr_read_req_0_uop_uop.xcpt_ma_if
invalidate mshr_read_req_0_uop_uop.xcpt_ae_if
invalidate mshr_read_req_0_uop_uop.xcpt_pf_if
invalidate mshr_read_req_0_uop_uop.fp_single
invalidate mshr_read_req_0_uop_uop.fp_val
invalidate mshr_read_req_0_uop_uop.frs3_en
invalidate mshr_read_req_0_uop_uop.lrs2_rtype
invalidate mshr_read_req_0_uop_uop.lrs1_rtype
invalidate mshr_read_req_0_uop_uop.dst_rtype
invalidate mshr_read_req_0_uop_uop.ldst_val
invalidate mshr_read_req_0_uop_uop.lrs3
invalidate mshr_read_req_0_uop_uop.lrs2
invalidate mshr_read_req_0_uop_uop.lrs1
invalidate mshr_read_req_0_uop_uop.ldst
invalidate mshr_read_req_0_uop_uop.ldst_is_rs1
invalidate mshr_read_req_0_uop_uop.flush_on_commit
invalidate mshr_read_req_0_uop_uop.is_unique
invalidate mshr_read_req_0_uop_uop.is_sys_pc2epc
invalidate mshr_read_req_0_uop_uop.uses_stq
invalidate mshr_read_req_0_uop_uop.uses_ldq
invalidate mshr_read_req_0_uop_uop.is_amo
invalidate mshr_read_req_0_uop_uop.is_fencei
invalidate mshr_read_req_0_uop_uop.is_fence
invalidate mshr_read_req_0_uop_uop.mem_signed
invalidate mshr_read_req_0_uop_uop.mem_size
invalidate mshr_read_req_0_uop_uop.mem_cmd
invalidate mshr_read_req_0_uop_uop.bypassable
invalidate mshr_read_req_0_uop_uop.exc_cause
invalidate mshr_read_req_0_uop_uop.exception
invalidate mshr_read_req_0_uop_uop.stale_pdst
invalidate mshr_read_req_0_uop_uop.ppred_busy
invalidate mshr_read_req_0_uop_uop.prs3_busy
invalidate mshr_read_req_0_uop_uop.prs2_busy
invalidate mshr_read_req_0_uop_uop.prs1_busy
invalidate mshr_read_req_0_uop_uop.ppred
invalidate mshr_read_req_0_uop_uop.prs3
invalidate mshr_read_req_0_uop_uop.prs2
invalidate mshr_read_req_0_uop_uop.prs1
invalidate mshr_read_req_0_uop_uop.pdst
invalidate mshr_read_req_0_uop_uop.rxq_idx
invalidate mshr_read_req_0_uop_uop.stq_idx
invalidate mshr_read_req_0_uop_uop.ldq_idx
invalidate mshr_read_req_0_uop_uop.rob_idx
invalidate mshr_read_req_0_uop_uop.csr_addr
invalidate mshr_read_req_0_uop_uop.imm_packed
invalidate mshr_read_req_0_uop_uop.taken
invalidate mshr_read_req_0_uop_uop.pc_lob
invalidate mshr_read_req_0_uop_uop.edge_inst
invalidate mshr_read_req_0_uop_uop.ftq_idx
invalidate mshr_read_req_0_uop_uop.br_tag
invalidate mshr_read_req_0_uop_uop.br_mask
invalidate mshr_read_req_0_uop_uop.is_sfb
invalidate mshr_read_req_0_uop_uop.is_jal
invalidate mshr_read_req_0_uop_uop.is_jalr
invalidate mshr_read_req_0_uop_uop.is_br
invalidate mshr_read_req_0_uop_uop.iw_p2_poisoned
invalidate mshr_read_req_0_uop_uop.iw_p1_poisoned
invalidate mshr_read_req_0_uop_uop.iw_state
invalidate mshr_read_req_0_uop_uop.ctrl.is_std
invalidate mshr_read_req_0_uop_uop.ctrl.is_sta
invalidate mshr_read_req_0_uop_uop.ctrl.is_load
invalidate mshr_read_req_0_uop_uop.ctrl.csr_cmd
invalidate mshr_read_req_0_uop_uop.ctrl.fcn_dw
invalidate mshr_read_req_0_uop_uop.ctrl.op_fcn
invalidate mshr_read_req_0_uop_uop.ctrl.imm_sel
invalidate mshr_read_req_0_uop_uop.ctrl.op2_sel
invalidate mshr_read_req_0_uop_uop.ctrl.op1_sel
invalidate mshr_read_req_0_uop_uop.ctrl.br_type
invalidate mshr_read_req_0_uop_uop.fu_code
invalidate mshr_read_req_0_uop_uop.iq_type
invalidate mshr_read_req_0_uop_uop.debug_pc
invalidate mshr_read_req_0_uop_uop.is_rvc
invalidate mshr_read_req_0_uop_uop.debug_inst
invalidate mshr_read_req_0_uop_uop.inst
invalidate mshr_read_req_0_uop_uop.uopc
connect mshr_read_req_0_uop_uop.uopc, UInt<7>(0h0)
connect mshr_read_req_0_uop_uop.bypassable, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.fp_val, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.uses_stq, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.uses_ldq, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.pdst, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.dst_rtype, UInt<2>(0h2)
wire mshr_read_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate mshr_read_req_0_uop_cs.is_std
invalidate mshr_read_req_0_uop_cs.is_sta
invalidate mshr_read_req_0_uop_cs.is_load
invalidate mshr_read_req_0_uop_cs.csr_cmd
invalidate mshr_read_req_0_uop_cs.fcn_dw
invalidate mshr_read_req_0_uop_cs.op_fcn
invalidate mshr_read_req_0_uop_cs.imm_sel
invalidate mshr_read_req_0_uop_cs.op2_sel
invalidate mshr_read_req_0_uop_cs.op1_sel
invalidate mshr_read_req_0_uop_cs.br_type
connect mshr_read_req_0_uop_cs.br_type, UInt<4>(0h0)
connect mshr_read_req_0_uop_cs.csr_cmd, UInt<3>(0h0)
connect mshr_read_req_0_uop_cs.is_load, UInt<1>(0h0)
connect mshr_read_req_0_uop_cs.is_sta, UInt<1>(0h0)
connect mshr_read_req_0_uop_cs.is_std, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.ctrl, mshr_read_req_0_uop_cs
connect mshr_read_req[0].uop, mshr_read_req_0_uop_uop
node _mshr_read_req_0_addr_T = cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx)
node _mshr_read_req_0_addr_T_1 = shl(_mshr_read_req_0_addr_T, 6)
connect mshr_read_req[0].addr, _mshr_read_req_0_addr_T_1
invalidate mshr_read_req[0].data
connect mshr_read_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[3].valid, mshrs.io.meta_read.valid
connect metaReadArb.io.in[3].bits.req[0].tag, mshrs.io.meta_read.bits.tag
connect metaReadArb.io.in[3].bits.req[0].way_en, mshrs.io.meta_read.bits.way_en
connect metaReadArb.io.in[3].bits.req[0].idx, mshrs.io.meta_read.bits.idx
connect mshrs.io.meta_read.ready, metaReadArb.io.in[3].ready
node _wb_fire_T = and(wb.io.meta_read.ready, wb.io.meta_read.valid)
node _wb_fire_T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid)
node wb_fire = and(_wb_fire_T, _wb_fire_T_1)
wire wb_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate wb_req[0].is_hella
invalidate wb_req[0].data
invalidate wb_req[0].addr
invalidate wb_req[0].uop.debug_tsrc
invalidate wb_req[0].uop.debug_fsrc
invalidate wb_req[0].uop.bp_xcpt_if
invalidate wb_req[0].uop.bp_debug_if
invalidate wb_req[0].uop.xcpt_ma_if
invalidate wb_req[0].uop.xcpt_ae_if
invalidate wb_req[0].uop.xcpt_pf_if
invalidate wb_req[0].uop.fp_single
invalidate wb_req[0].uop.fp_val
invalidate wb_req[0].uop.frs3_en
invalidate wb_req[0].uop.lrs2_rtype
invalidate wb_req[0].uop.lrs1_rtype
invalidate wb_req[0].uop.dst_rtype
invalidate wb_req[0].uop.ldst_val
invalidate wb_req[0].uop.lrs3
invalidate wb_req[0].uop.lrs2
invalidate wb_req[0].uop.lrs1
invalidate wb_req[0].uop.ldst
invalidate wb_req[0].uop.ldst_is_rs1
invalidate wb_req[0].uop.flush_on_commit
invalidate wb_req[0].uop.is_unique
invalidate wb_req[0].uop.is_sys_pc2epc
invalidate wb_req[0].uop.uses_stq
invalidate wb_req[0].uop.uses_ldq
invalidate wb_req[0].uop.is_amo
invalidate wb_req[0].uop.is_fencei
invalidate wb_req[0].uop.is_fence
invalidate wb_req[0].uop.mem_signed
invalidate wb_req[0].uop.mem_size
invalidate wb_req[0].uop.mem_cmd
invalidate wb_req[0].uop.bypassable
invalidate wb_req[0].uop.exc_cause
invalidate wb_req[0].uop.exception
invalidate wb_req[0].uop.stale_pdst
invalidate wb_req[0].uop.ppred_busy
invalidate wb_req[0].uop.prs3_busy
invalidate wb_req[0].uop.prs2_busy
invalidate wb_req[0].uop.prs1_busy
invalidate wb_req[0].uop.ppred
invalidate wb_req[0].uop.prs3
invalidate wb_req[0].uop.prs2
invalidate wb_req[0].uop.prs1
invalidate wb_req[0].uop.pdst
invalidate wb_req[0].uop.rxq_idx
invalidate wb_req[0].uop.stq_idx
invalidate wb_req[0].uop.ldq_idx
invalidate wb_req[0].uop.rob_idx
invalidate wb_req[0].uop.csr_addr
invalidate wb_req[0].uop.imm_packed
invalidate wb_req[0].uop.taken
invalidate wb_req[0].uop.pc_lob
invalidate wb_req[0].uop.edge_inst
invalidate wb_req[0].uop.ftq_idx
invalidate wb_req[0].uop.br_tag
invalidate wb_req[0].uop.br_mask
invalidate wb_req[0].uop.is_sfb
invalidate wb_req[0].uop.is_jal
invalidate wb_req[0].uop.is_jalr
invalidate wb_req[0].uop.is_br
invalidate wb_req[0].uop.iw_p2_poisoned
invalidate wb_req[0].uop.iw_p1_poisoned
invalidate wb_req[0].uop.iw_state
invalidate wb_req[0].uop.ctrl.is_std
invalidate wb_req[0].uop.ctrl.is_sta
invalidate wb_req[0].uop.ctrl.is_load
invalidate wb_req[0].uop.ctrl.csr_cmd
invalidate wb_req[0].uop.ctrl.fcn_dw
invalidate wb_req[0].uop.ctrl.op_fcn
invalidate wb_req[0].uop.ctrl.imm_sel
invalidate wb_req[0].uop.ctrl.op2_sel
invalidate wb_req[0].uop.ctrl.op1_sel
invalidate wb_req[0].uop.ctrl.br_type
invalidate wb_req[0].uop.fu_code
invalidate wb_req[0].uop.iq_type
invalidate wb_req[0].uop.debug_pc
invalidate wb_req[0].uop.is_rvc
invalidate wb_req[0].uop.debug_inst
invalidate wb_req[0].uop.inst
invalidate wb_req[0].uop.uopc
wire wb_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate wb_req_0_uop_uop.debug_tsrc
invalidate wb_req_0_uop_uop.debug_fsrc
invalidate wb_req_0_uop_uop.bp_xcpt_if
invalidate wb_req_0_uop_uop.bp_debug_if
invalidate wb_req_0_uop_uop.xcpt_ma_if
invalidate wb_req_0_uop_uop.xcpt_ae_if
invalidate wb_req_0_uop_uop.xcpt_pf_if
invalidate wb_req_0_uop_uop.fp_single
invalidate wb_req_0_uop_uop.fp_val
invalidate wb_req_0_uop_uop.frs3_en
invalidate wb_req_0_uop_uop.lrs2_rtype
invalidate wb_req_0_uop_uop.lrs1_rtype
invalidate wb_req_0_uop_uop.dst_rtype
invalidate wb_req_0_uop_uop.ldst_val
invalidate wb_req_0_uop_uop.lrs3
invalidate wb_req_0_uop_uop.lrs2
invalidate wb_req_0_uop_uop.lrs1
invalidate wb_req_0_uop_uop.ldst
invalidate wb_req_0_uop_uop.ldst_is_rs1
invalidate wb_req_0_uop_uop.flush_on_commit
invalidate wb_req_0_uop_uop.is_unique
invalidate wb_req_0_uop_uop.is_sys_pc2epc
invalidate wb_req_0_uop_uop.uses_stq
invalidate wb_req_0_uop_uop.uses_ldq
invalidate wb_req_0_uop_uop.is_amo
invalidate wb_req_0_uop_uop.is_fencei
invalidate wb_req_0_uop_uop.is_fence
invalidate wb_req_0_uop_uop.mem_signed
invalidate wb_req_0_uop_uop.mem_size
invalidate wb_req_0_uop_uop.mem_cmd
invalidate wb_req_0_uop_uop.bypassable
invalidate wb_req_0_uop_uop.exc_cause
invalidate wb_req_0_uop_uop.exception
invalidate wb_req_0_uop_uop.stale_pdst
invalidate wb_req_0_uop_uop.ppred_busy
invalidate wb_req_0_uop_uop.prs3_busy
invalidate wb_req_0_uop_uop.prs2_busy
invalidate wb_req_0_uop_uop.prs1_busy
invalidate wb_req_0_uop_uop.ppred
invalidate wb_req_0_uop_uop.prs3
invalidate wb_req_0_uop_uop.prs2
invalidate wb_req_0_uop_uop.prs1
invalidate wb_req_0_uop_uop.pdst
invalidate wb_req_0_uop_uop.rxq_idx
invalidate wb_req_0_uop_uop.stq_idx
invalidate wb_req_0_uop_uop.ldq_idx
invalidate wb_req_0_uop_uop.rob_idx
invalidate wb_req_0_uop_uop.csr_addr
invalidate wb_req_0_uop_uop.imm_packed
invalidate wb_req_0_uop_uop.taken
invalidate wb_req_0_uop_uop.pc_lob
invalidate wb_req_0_uop_uop.edge_inst
invalidate wb_req_0_uop_uop.ftq_idx
invalidate wb_req_0_uop_uop.br_tag
invalidate wb_req_0_uop_uop.br_mask
invalidate wb_req_0_uop_uop.is_sfb
invalidate wb_req_0_uop_uop.is_jal
invalidate wb_req_0_uop_uop.is_jalr
invalidate wb_req_0_uop_uop.is_br
invalidate wb_req_0_uop_uop.iw_p2_poisoned
invalidate wb_req_0_uop_uop.iw_p1_poisoned
invalidate wb_req_0_uop_uop.iw_state
invalidate wb_req_0_uop_uop.ctrl.is_std
invalidate wb_req_0_uop_uop.ctrl.is_sta
invalidate wb_req_0_uop_uop.ctrl.is_load
invalidate wb_req_0_uop_uop.ctrl.csr_cmd
invalidate wb_req_0_uop_uop.ctrl.fcn_dw
invalidate wb_req_0_uop_uop.ctrl.op_fcn
invalidate wb_req_0_uop_uop.ctrl.imm_sel
invalidate wb_req_0_uop_uop.ctrl.op2_sel
invalidate wb_req_0_uop_uop.ctrl.op1_sel
invalidate wb_req_0_uop_uop.ctrl.br_type
invalidate wb_req_0_uop_uop.fu_code
invalidate wb_req_0_uop_uop.iq_type
invalidate wb_req_0_uop_uop.debug_pc
invalidate wb_req_0_uop_uop.is_rvc
invalidate wb_req_0_uop_uop.debug_inst
invalidate wb_req_0_uop_uop.inst
invalidate wb_req_0_uop_uop.uopc
connect wb_req_0_uop_uop.uopc, UInt<7>(0h0)
connect wb_req_0_uop_uop.bypassable, UInt<1>(0h0)
connect wb_req_0_uop_uop.fp_val, UInt<1>(0h0)
connect wb_req_0_uop_uop.uses_stq, UInt<1>(0h0)
connect wb_req_0_uop_uop.uses_ldq, UInt<1>(0h0)
connect wb_req_0_uop_uop.pdst, UInt<1>(0h0)
connect wb_req_0_uop_uop.dst_rtype, UInt<2>(0h2)
wire wb_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate wb_req_0_uop_cs.is_std
invalidate wb_req_0_uop_cs.is_sta
invalidate wb_req_0_uop_cs.is_load
invalidate wb_req_0_uop_cs.csr_cmd
invalidate wb_req_0_uop_cs.fcn_dw
invalidate wb_req_0_uop_cs.op_fcn
invalidate wb_req_0_uop_cs.imm_sel
invalidate wb_req_0_uop_cs.op2_sel
invalidate wb_req_0_uop_cs.op1_sel
invalidate wb_req_0_uop_cs.br_type
connect wb_req_0_uop_cs.br_type, UInt<4>(0h0)
connect wb_req_0_uop_cs.csr_cmd, UInt<3>(0h0)
connect wb_req_0_uop_cs.is_load, UInt<1>(0h0)
connect wb_req_0_uop_cs.is_sta, UInt<1>(0h0)
connect wb_req_0_uop_cs.is_std, UInt<1>(0h0)
connect wb_req_0_uop_uop.ctrl, wb_req_0_uop_cs
connect wb_req[0].uop, wb_req_0_uop_uop
node _wb_req_0_addr_T = cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)
connect wb_req[0].addr, _wb_req_0_addr_T
invalidate wb_req[0].data
connect wb_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[2].valid, wb.io.meta_read.valid
connect metaReadArb.io.in[2].bits.req[0].tag, wb.io.meta_read.bits.tag
connect metaReadArb.io.in[2].bits.req[0].way_en, wb.io.meta_read.bits.way_en
connect metaReadArb.io.in[2].bits.req[0].idx, wb.io.meta_read.bits.idx
node _wb_io_meta_read_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready)
connect wb.io.meta_read.ready, _wb_io_meta_read_ready_T
connect dataReadArb.io.in[1].valid, wb.io.data_req.valid
connect dataReadArb.io.in[1].bits.req[0].addr, wb.io.data_req.bits.addr
connect dataReadArb.io.in[1].bits.req[0].way_en, wb.io.data_req.bits.way_en
wire _WIRE_1 : UInt<1>[1]
connect _WIRE_1[0], UInt<1>(0h1)
connect dataReadArb.io.in[1].bits.valid[0], _WIRE_1[0]
node _wb_io_data_req_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready)
connect wb.io.data_req.ready, _wb_io_data_req_ready_T
node _T = and(wb.io.meta_read.ready, wb.io.meta_read.valid)
node _T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid)
node _T_2 = xor(_T, _T_1)
node _T_3 = eq(_T_2, UInt<1>(0h0))
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:548 assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node prober_fire = and(prober.io.meta_read.ready, prober.io.meta_read.valid)
wire prober_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate prober_req[0].is_hella
invalidate prober_req[0].data
invalidate prober_req[0].addr
invalidate prober_req[0].uop.debug_tsrc
invalidate prober_req[0].uop.debug_fsrc
invalidate prober_req[0].uop.bp_xcpt_if
invalidate prober_req[0].uop.bp_debug_if
invalidate prober_req[0].uop.xcpt_ma_if
invalidate prober_req[0].uop.xcpt_ae_if
invalidate prober_req[0].uop.xcpt_pf_if
invalidate prober_req[0].uop.fp_single
invalidate prober_req[0].uop.fp_val
invalidate prober_req[0].uop.frs3_en
invalidate prober_req[0].uop.lrs2_rtype
invalidate prober_req[0].uop.lrs1_rtype
invalidate prober_req[0].uop.dst_rtype
invalidate prober_req[0].uop.ldst_val
invalidate prober_req[0].uop.lrs3
invalidate prober_req[0].uop.lrs2
invalidate prober_req[0].uop.lrs1
invalidate prober_req[0].uop.ldst
invalidate prober_req[0].uop.ldst_is_rs1
invalidate prober_req[0].uop.flush_on_commit
invalidate prober_req[0].uop.is_unique
invalidate prober_req[0].uop.is_sys_pc2epc
invalidate prober_req[0].uop.uses_stq
invalidate prober_req[0].uop.uses_ldq
invalidate prober_req[0].uop.is_amo
invalidate prober_req[0].uop.is_fencei
invalidate prober_req[0].uop.is_fence
invalidate prober_req[0].uop.mem_signed
invalidate prober_req[0].uop.mem_size
invalidate prober_req[0].uop.mem_cmd
invalidate prober_req[0].uop.bypassable
invalidate prober_req[0].uop.exc_cause
invalidate prober_req[0].uop.exception
invalidate prober_req[0].uop.stale_pdst
invalidate prober_req[0].uop.ppred_busy
invalidate prober_req[0].uop.prs3_busy
invalidate prober_req[0].uop.prs2_busy
invalidate prober_req[0].uop.prs1_busy
invalidate prober_req[0].uop.ppred
invalidate prober_req[0].uop.prs3
invalidate prober_req[0].uop.prs2
invalidate prober_req[0].uop.prs1
invalidate prober_req[0].uop.pdst
invalidate prober_req[0].uop.rxq_idx
invalidate prober_req[0].uop.stq_idx
invalidate prober_req[0].uop.ldq_idx
invalidate prober_req[0].uop.rob_idx
invalidate prober_req[0].uop.csr_addr
invalidate prober_req[0].uop.imm_packed
invalidate prober_req[0].uop.taken
invalidate prober_req[0].uop.pc_lob
invalidate prober_req[0].uop.edge_inst
invalidate prober_req[0].uop.ftq_idx
invalidate prober_req[0].uop.br_tag
invalidate prober_req[0].uop.br_mask
invalidate prober_req[0].uop.is_sfb
invalidate prober_req[0].uop.is_jal
invalidate prober_req[0].uop.is_jalr
invalidate prober_req[0].uop.is_br
invalidate prober_req[0].uop.iw_p2_poisoned
invalidate prober_req[0].uop.iw_p1_poisoned
invalidate prober_req[0].uop.iw_state
invalidate prober_req[0].uop.ctrl.is_std
invalidate prober_req[0].uop.ctrl.is_sta
invalidate prober_req[0].uop.ctrl.is_load
invalidate prober_req[0].uop.ctrl.csr_cmd
invalidate prober_req[0].uop.ctrl.fcn_dw
invalidate prober_req[0].uop.ctrl.op_fcn
invalidate prober_req[0].uop.ctrl.imm_sel
invalidate prober_req[0].uop.ctrl.op2_sel
invalidate prober_req[0].uop.ctrl.op1_sel
invalidate prober_req[0].uop.ctrl.br_type
invalidate prober_req[0].uop.fu_code
invalidate prober_req[0].uop.iq_type
invalidate prober_req[0].uop.debug_pc
invalidate prober_req[0].uop.is_rvc
invalidate prober_req[0].uop.debug_inst
invalidate prober_req[0].uop.inst
invalidate prober_req[0].uop.uopc
wire prober_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate prober_req_0_uop_uop.debug_tsrc
invalidate prober_req_0_uop_uop.debug_fsrc
invalidate prober_req_0_uop_uop.bp_xcpt_if
invalidate prober_req_0_uop_uop.bp_debug_if
invalidate prober_req_0_uop_uop.xcpt_ma_if
invalidate prober_req_0_uop_uop.xcpt_ae_if
invalidate prober_req_0_uop_uop.xcpt_pf_if
invalidate prober_req_0_uop_uop.fp_single
invalidate prober_req_0_uop_uop.fp_val
invalidate prober_req_0_uop_uop.frs3_en
invalidate prober_req_0_uop_uop.lrs2_rtype
invalidate prober_req_0_uop_uop.lrs1_rtype
invalidate prober_req_0_uop_uop.dst_rtype
invalidate prober_req_0_uop_uop.ldst_val
invalidate prober_req_0_uop_uop.lrs3
invalidate prober_req_0_uop_uop.lrs2
invalidate prober_req_0_uop_uop.lrs1
invalidate prober_req_0_uop_uop.ldst
invalidate prober_req_0_uop_uop.ldst_is_rs1
invalidate prober_req_0_uop_uop.flush_on_commit
invalidate prober_req_0_uop_uop.is_unique
invalidate prober_req_0_uop_uop.is_sys_pc2epc
invalidate prober_req_0_uop_uop.uses_stq
invalidate prober_req_0_uop_uop.uses_ldq
invalidate prober_req_0_uop_uop.is_amo
invalidate prober_req_0_uop_uop.is_fencei
invalidate prober_req_0_uop_uop.is_fence
invalidate prober_req_0_uop_uop.mem_signed
invalidate prober_req_0_uop_uop.mem_size
invalidate prober_req_0_uop_uop.mem_cmd
invalidate prober_req_0_uop_uop.bypassable
invalidate prober_req_0_uop_uop.exc_cause
invalidate prober_req_0_uop_uop.exception
invalidate prober_req_0_uop_uop.stale_pdst
invalidate prober_req_0_uop_uop.ppred_busy
invalidate prober_req_0_uop_uop.prs3_busy
invalidate prober_req_0_uop_uop.prs2_busy
invalidate prober_req_0_uop_uop.prs1_busy
invalidate prober_req_0_uop_uop.ppred
invalidate prober_req_0_uop_uop.prs3
invalidate prober_req_0_uop_uop.prs2
invalidate prober_req_0_uop_uop.prs1
invalidate prober_req_0_uop_uop.pdst
invalidate prober_req_0_uop_uop.rxq_idx
invalidate prober_req_0_uop_uop.stq_idx
invalidate prober_req_0_uop_uop.ldq_idx
invalidate prober_req_0_uop_uop.rob_idx
invalidate prober_req_0_uop_uop.csr_addr
invalidate prober_req_0_uop_uop.imm_packed
invalidate prober_req_0_uop_uop.taken
invalidate prober_req_0_uop_uop.pc_lob
invalidate prober_req_0_uop_uop.edge_inst
invalidate prober_req_0_uop_uop.ftq_idx
invalidate prober_req_0_uop_uop.br_tag
invalidate prober_req_0_uop_uop.br_mask
invalidate prober_req_0_uop_uop.is_sfb
invalidate prober_req_0_uop_uop.is_jal
invalidate prober_req_0_uop_uop.is_jalr
invalidate prober_req_0_uop_uop.is_br
invalidate prober_req_0_uop_uop.iw_p2_poisoned
invalidate prober_req_0_uop_uop.iw_p1_poisoned
invalidate prober_req_0_uop_uop.iw_state
invalidate prober_req_0_uop_uop.ctrl.is_std
invalidate prober_req_0_uop_uop.ctrl.is_sta
invalidate prober_req_0_uop_uop.ctrl.is_load
invalidate prober_req_0_uop_uop.ctrl.csr_cmd
invalidate prober_req_0_uop_uop.ctrl.fcn_dw
invalidate prober_req_0_uop_uop.ctrl.op_fcn
invalidate prober_req_0_uop_uop.ctrl.imm_sel
invalidate prober_req_0_uop_uop.ctrl.op2_sel
invalidate prober_req_0_uop_uop.ctrl.op1_sel
invalidate prober_req_0_uop_uop.ctrl.br_type
invalidate prober_req_0_uop_uop.fu_code
invalidate prober_req_0_uop_uop.iq_type
invalidate prober_req_0_uop_uop.debug_pc
invalidate prober_req_0_uop_uop.is_rvc
invalidate prober_req_0_uop_uop.debug_inst
invalidate prober_req_0_uop_uop.inst
invalidate prober_req_0_uop_uop.uopc
connect prober_req_0_uop_uop.uopc, UInt<7>(0h0)
connect prober_req_0_uop_uop.bypassable, UInt<1>(0h0)
connect prober_req_0_uop_uop.fp_val, UInt<1>(0h0)
connect prober_req_0_uop_uop.uses_stq, UInt<1>(0h0)
connect prober_req_0_uop_uop.uses_ldq, UInt<1>(0h0)
connect prober_req_0_uop_uop.pdst, UInt<1>(0h0)
connect prober_req_0_uop_uop.dst_rtype, UInt<2>(0h2)
wire prober_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate prober_req_0_uop_cs.is_std
invalidate prober_req_0_uop_cs.is_sta
invalidate prober_req_0_uop_cs.is_load
invalidate prober_req_0_uop_cs.csr_cmd
invalidate prober_req_0_uop_cs.fcn_dw
invalidate prober_req_0_uop_cs.op_fcn
invalidate prober_req_0_uop_cs.imm_sel
invalidate prober_req_0_uop_cs.op2_sel
invalidate prober_req_0_uop_cs.op1_sel
invalidate prober_req_0_uop_cs.br_type
connect prober_req_0_uop_cs.br_type, UInt<4>(0h0)
connect prober_req_0_uop_cs.csr_cmd, UInt<3>(0h0)
connect prober_req_0_uop_cs.is_load, UInt<1>(0h0)
connect prober_req_0_uop_cs.is_sta, UInt<1>(0h0)
connect prober_req_0_uop_cs.is_std, UInt<1>(0h0)
connect prober_req_0_uop_uop.ctrl, prober_req_0_uop_cs
connect prober_req[0].uop, prober_req_0_uop_uop
node _prober_req_0_addr_T = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx)
node _prober_req_0_addr_T_1 = shl(_prober_req_0_addr_T, 6)
connect prober_req[0].addr, _prober_req_0_addr_T_1
invalidate prober_req[0].data
connect prober_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[1].valid, prober.io.meta_read.valid
connect metaReadArb.io.in[1].bits.req[0].tag, prober.io.meta_read.bits.tag
connect metaReadArb.io.in[1].bits.req[0].way_en, prober.io.meta_read.bits.way_en
connect metaReadArb.io.in[1].bits.req[0].idx, prober.io.meta_read.bits.idx
connect prober.io.meta_read.ready, metaReadArb.io.in[1].ready
node prefetch_fire = and(mshrs.io.prefetch.ready, mshrs.io.prefetch.valid)
wire prefetch_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate prefetch_req[0].is_hella
invalidate prefetch_req[0].data
invalidate prefetch_req[0].addr
invalidate prefetch_req[0].uop.debug_tsrc
invalidate prefetch_req[0].uop.debug_fsrc
invalidate prefetch_req[0].uop.bp_xcpt_if
invalidate prefetch_req[0].uop.bp_debug_if
invalidate prefetch_req[0].uop.xcpt_ma_if
invalidate prefetch_req[0].uop.xcpt_ae_if
invalidate prefetch_req[0].uop.xcpt_pf_if
invalidate prefetch_req[0].uop.fp_single
invalidate prefetch_req[0].uop.fp_val
invalidate prefetch_req[0].uop.frs3_en
invalidate prefetch_req[0].uop.lrs2_rtype
invalidate prefetch_req[0].uop.lrs1_rtype
invalidate prefetch_req[0].uop.dst_rtype
invalidate prefetch_req[0].uop.ldst_val
invalidate prefetch_req[0].uop.lrs3
invalidate prefetch_req[0].uop.lrs2
invalidate prefetch_req[0].uop.lrs1
invalidate prefetch_req[0].uop.ldst
invalidate prefetch_req[0].uop.ldst_is_rs1
invalidate prefetch_req[0].uop.flush_on_commit
invalidate prefetch_req[0].uop.is_unique
invalidate prefetch_req[0].uop.is_sys_pc2epc
invalidate prefetch_req[0].uop.uses_stq
invalidate prefetch_req[0].uop.uses_ldq
invalidate prefetch_req[0].uop.is_amo
invalidate prefetch_req[0].uop.is_fencei
invalidate prefetch_req[0].uop.is_fence
invalidate prefetch_req[0].uop.mem_signed
invalidate prefetch_req[0].uop.mem_size
invalidate prefetch_req[0].uop.mem_cmd
invalidate prefetch_req[0].uop.bypassable
invalidate prefetch_req[0].uop.exc_cause
invalidate prefetch_req[0].uop.exception
invalidate prefetch_req[0].uop.stale_pdst
invalidate prefetch_req[0].uop.ppred_busy
invalidate prefetch_req[0].uop.prs3_busy
invalidate prefetch_req[0].uop.prs2_busy
invalidate prefetch_req[0].uop.prs1_busy
invalidate prefetch_req[0].uop.ppred
invalidate prefetch_req[0].uop.prs3
invalidate prefetch_req[0].uop.prs2
invalidate prefetch_req[0].uop.prs1
invalidate prefetch_req[0].uop.pdst
invalidate prefetch_req[0].uop.rxq_idx
invalidate prefetch_req[0].uop.stq_idx
invalidate prefetch_req[0].uop.ldq_idx
invalidate prefetch_req[0].uop.rob_idx
invalidate prefetch_req[0].uop.csr_addr
invalidate prefetch_req[0].uop.imm_packed
invalidate prefetch_req[0].uop.taken
invalidate prefetch_req[0].uop.pc_lob
invalidate prefetch_req[0].uop.edge_inst
invalidate prefetch_req[0].uop.ftq_idx
invalidate prefetch_req[0].uop.br_tag
invalidate prefetch_req[0].uop.br_mask
invalidate prefetch_req[0].uop.is_sfb
invalidate prefetch_req[0].uop.is_jal
invalidate prefetch_req[0].uop.is_jalr
invalidate prefetch_req[0].uop.is_br
invalidate prefetch_req[0].uop.iw_p2_poisoned
invalidate prefetch_req[0].uop.iw_p1_poisoned
invalidate prefetch_req[0].uop.iw_state
invalidate prefetch_req[0].uop.ctrl.is_std
invalidate prefetch_req[0].uop.ctrl.is_sta
invalidate prefetch_req[0].uop.ctrl.is_load
invalidate prefetch_req[0].uop.ctrl.csr_cmd
invalidate prefetch_req[0].uop.ctrl.fcn_dw
invalidate prefetch_req[0].uop.ctrl.op_fcn
invalidate prefetch_req[0].uop.ctrl.imm_sel
invalidate prefetch_req[0].uop.ctrl.op2_sel
invalidate prefetch_req[0].uop.ctrl.op1_sel
invalidate prefetch_req[0].uop.ctrl.br_type
invalidate prefetch_req[0].uop.fu_code
invalidate prefetch_req[0].uop.iq_type
invalidate prefetch_req[0].uop.debug_pc
invalidate prefetch_req[0].uop.is_rvc
invalidate prefetch_req[0].uop.debug_inst
invalidate prefetch_req[0].uop.inst
invalidate prefetch_req[0].uop.uopc
connect prefetch_req[0], mshrs.io.prefetch.bits
connect metaReadArb.io.in[5].valid, mshrs.io.prefetch.valid
node _metaReadArb_io_in_5_bits_req_0_idx_T = shr(mshrs.io.prefetch.bits.addr, 6)
connect metaReadArb.io.in[5].bits.req[0].idx, _metaReadArb_io_in_5_bits_req_0_idx_T
invalidate metaReadArb.io.in[5].bits.req[0].way_en
invalidate metaReadArb.io.in[5].bits.req[0].tag
connect mshrs.io.prefetch.ready, metaReadArb.io.in[5].ready
node _s0_valid_T = and(io.lsu.req.ready, io.lsu.req.valid)
wire _s0_valid_WIRE : UInt<1>[1]
connect _s0_valid_WIRE[0], io.lsu.req.bits[0].valid
node _s0_valid_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid)
node _s0_valid_T_2 = or(_s0_valid_T_1, wb_fire)
node _s0_valid_T_3 = or(_s0_valid_T_2, prober_fire)
node _s0_valid_T_4 = or(_s0_valid_T_3, prefetch_fire)
node _s0_valid_T_5 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_valid_T_6 = or(_s0_valid_T_4, _s0_valid_T_5)
wire _s0_valid_WIRE_1 : UInt<1>[1]
connect _s0_valid_WIRE_1[0], UInt<1>(0h1)
wire _s0_valid_WIRE_2 : UInt<1>[1]
connect _s0_valid_WIRE_2[0], UInt<1>(0h0)
node _s0_valid_T_7 = mux(_s0_valid_T_6, _s0_valid_WIRE_1, _s0_valid_WIRE_2)
node s0_valid = mux(_s0_valid_T, _s0_valid_WIRE, _s0_valid_T_7)
node _s0_req_T = and(io.lsu.req.ready, io.lsu.req.valid)
wire _s0_req_WIRE : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1]
connect _s0_req_WIRE[0], io.lsu.req.bits[0].bits
node _s0_req_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_req_T_2 = mux(_s0_req_T_1, mshr_read_req, replay_req)
node _s0_req_T_3 = mux(prefetch_fire, prefetch_req, _s0_req_T_2)
node _s0_req_T_4 = mux(prober_fire, prober_req, _s0_req_T_3)
node _s0_req_T_5 = mux(wb_fire, wb_req, _s0_req_T_4)
node s0_req = mux(_s0_req_T, _s0_req_WIRE, _s0_req_T_5)
node _s0_type_T = and(io.lsu.req.ready, io.lsu.req.valid)
node _s0_type_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_type_T_2 = mux(_s0_type_T_1, UInt<3>(0h3), UInt<3>(0h0))
node _s0_type_T_3 = mux(prefetch_fire, UInt<3>(0h5), _s0_type_T_2)
node _s0_type_T_4 = mux(prober_fire, UInt<3>(0h1), _s0_type_T_3)
node _s0_type_T_5 = mux(wb_fire, UInt<3>(0h2), _s0_type_T_4)
node s0_type = mux(_s0_type_T, UInt<3>(0h4), _s0_type_T_5)
node _s0_send_resp_or_nack_T = and(io.lsu.req.ready, io.lsu.req.valid)
node _s0_send_resp_or_nack_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid)
node _s0_send_resp_or_nack_T_2 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<1>(0h0))
node _s0_send_resp_or_nack_T_3 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<5>(0h10))
node _s0_send_resp_or_nack_T_4 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h6))
node _s0_send_resp_or_nack_T_5 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h7))
node _s0_send_resp_or_nack_T_6 = or(_s0_send_resp_or_nack_T_2, _s0_send_resp_or_nack_T_3)
node _s0_send_resp_or_nack_T_7 = or(_s0_send_resp_or_nack_T_6, _s0_send_resp_or_nack_T_4)
node _s0_send_resp_or_nack_T_8 = or(_s0_send_resp_or_nack_T_7, _s0_send_resp_or_nack_T_5)
node _s0_send_resp_or_nack_T_9 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h4))
node _s0_send_resp_or_nack_T_10 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h9))
node _s0_send_resp_or_nack_T_11 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0ha))
node _s0_send_resp_or_nack_T_12 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hb))
node _s0_send_resp_or_nack_T_13 = or(_s0_send_resp_or_nack_T_9, _s0_send_resp_or_nack_T_10)
node _s0_send_resp_or_nack_T_14 = or(_s0_send_resp_or_nack_T_13, _s0_send_resp_or_nack_T_11)
node _s0_send_resp_or_nack_T_15 = or(_s0_send_resp_or_nack_T_14, _s0_send_resp_or_nack_T_12)
node _s0_send_resp_or_nack_T_16 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h8))
node _s0_send_resp_or_nack_T_17 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hc))
node _s0_send_resp_or_nack_T_18 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hd))
node _s0_send_resp_or_nack_T_19 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0he))
node _s0_send_resp_or_nack_T_20 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hf))
node _s0_send_resp_or_nack_T_21 = or(_s0_send_resp_or_nack_T_16, _s0_send_resp_or_nack_T_17)
node _s0_send_resp_or_nack_T_22 = or(_s0_send_resp_or_nack_T_21, _s0_send_resp_or_nack_T_18)
node _s0_send_resp_or_nack_T_23 = or(_s0_send_resp_or_nack_T_22, _s0_send_resp_or_nack_T_19)
node _s0_send_resp_or_nack_T_24 = or(_s0_send_resp_or_nack_T_23, _s0_send_resp_or_nack_T_20)
node _s0_send_resp_or_nack_T_25 = or(_s0_send_resp_or_nack_T_15, _s0_send_resp_or_nack_T_24)
node _s0_send_resp_or_nack_T_26 = or(_s0_send_resp_or_nack_T_8, _s0_send_resp_or_nack_T_25)
node _s0_send_resp_or_nack_T_27 = and(_s0_send_resp_or_nack_T_1, _s0_send_resp_or_nack_T_26)
node _s0_send_resp_or_nack_T_28 = mux(_s0_send_resp_or_nack_T_27, UInt<1>(0h1), UInt<1>(0h0))
node _s0_send_resp_or_nack_T_29 = bits(_s0_send_resp_or_nack_T_28, 0, 0)
wire _s0_send_resp_or_nack_WIRE : UInt<1>[1]
connect _s0_send_resp_or_nack_WIRE[0], _s0_send_resp_or_nack_T_29
node s0_send_resp_or_nack = mux(_s0_send_resp_or_nack_T, s0_valid, _s0_send_resp_or_nack_WIRE)
reg s1_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1], clock
connect s1_req, s0_req
node _s1_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _s1_req_0_uop_br_mask_T_1 = and(s0_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T)
connect s1_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T_1
wire s2_store_failed : UInt<1>
node _s1_valid_T = and(io.lsu.brupdate.b1.mispredict_mask, s0_req[0].uop.br_mask)
node _s1_valid_T_1 = neq(_s1_valid_T, UInt<1>(0h0))
node _s1_valid_T_2 = eq(_s1_valid_T_1, UInt<1>(0h0))
node _s1_valid_T_3 = and(s0_valid[0], _s1_valid_T_2)
node _s1_valid_T_4 = and(io.lsu.exception, s0_req[0].uop.uses_ldq)
node _s1_valid_T_5 = eq(_s1_valid_T_4, UInt<1>(0h0))
node _s1_valid_T_6 = and(_s1_valid_T_3, _s1_valid_T_5)
node _s1_valid_T_7 = and(io.lsu.req.ready, io.lsu.req.valid)
node _s1_valid_T_8 = and(s2_store_failed, _s1_valid_T_7)
node _s1_valid_T_9 = and(_s1_valid_T_8, s0_req[0].uop.uses_stq)
node _s1_valid_T_10 = eq(_s1_valid_T_9, UInt<1>(0h0))
node _s1_valid_T_11 = and(_s1_valid_T_6, _s1_valid_T_10)
regreset s1_valid_REG : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_valid_REG, _s1_valid_T_11
wire s1_valid : UInt<1>[1]
connect s1_valid[0], s1_valid_REG
node _T_7 = and(io.lsu.req.ready, io.lsu.req.valid)
reg REG : UInt<1>, clock
connect REG, _T_7
node _T_8 = eq(REG, UInt<1>(0h0))
node _T_9 = and(io.lsu.s1_kill[0], _T_8)
reg REG_1 : UInt<1>, clock
connect REG_1, io.lsu.req.bits[0].valid
node _T_10 = eq(REG_1, UInt<1>(0h0))
node _T_11 = and(_T_9, _T_10)
node _T_12 = eq(_T_11, UInt<1>(0h0))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:611 assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))\n") : printf_1
assert(clock, _T_12, UInt<1>(0h1), "") : assert_1
node _s1_nack_T = bits(s1_req[0].addr, 11, 6)
node _s1_nack_T_1 = eq(_s1_nack_T, prober.io.meta_write.bits.idx)
node _s1_nack_T_2 = eq(prober.io.req.ready, UInt<1>(0h0))
node s1_nack_0 = and(_s1_nack_T_1, _s1_nack_T_2)
reg s1_send_resp_or_nack : UInt<1>[1], clock
connect s1_send_resp_or_nack, s0_send_resp_or_nack
reg s1_type : UInt, clock
connect s1_type, s0_type
reg s1_mshr_meta_read_way_en : UInt, clock
connect s1_mshr_meta_read_way_en, mshrs.io.meta_read.bits.way_en
reg s1_replay_way_en : UInt, clock
connect s1_replay_way_en, mshrs.io.replay.bits.way_en
reg s1_wb_way_en : UInt, clock
connect s1_wb_way_en, wb.io.data_req.bits.way_en
node _s1_tag_eq_way_T = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_1 = eq(meta_0.io.resp[0].tag, _s1_tag_eq_way_T)
node _s1_tag_eq_way_T_2 = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_3 = eq(meta_0.io.resp[1].tag, _s1_tag_eq_way_T_2)
node _s1_tag_eq_way_T_4 = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_5 = eq(meta_0.io.resp[2].tag, _s1_tag_eq_way_T_4)
node _s1_tag_eq_way_T_6 = shr(s1_req[0].addr, 12)
node _s1_tag_eq_way_T_7 = eq(meta_0.io.resp[3].tag, _s1_tag_eq_way_T_6)
wire _s1_tag_eq_way_WIRE : UInt<1>[4]
connect _s1_tag_eq_way_WIRE[0], _s1_tag_eq_way_T_1
connect _s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_T_3
connect _s1_tag_eq_way_WIRE[2], _s1_tag_eq_way_T_5
connect _s1_tag_eq_way_WIRE[3], _s1_tag_eq_way_T_7
node s1_tag_eq_way_lo = cat(_s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_WIRE[0])
node s1_tag_eq_way_hi = cat(_s1_tag_eq_way_WIRE[3], _s1_tag_eq_way_WIRE[2])
node _s1_tag_eq_way_T_8 = cat(s1_tag_eq_way_hi, s1_tag_eq_way_lo)
wire s1_tag_eq_way : UInt<4>[1]
connect s1_tag_eq_way[0], _s1_tag_eq_way_T_8
node _s1_tag_match_way_T = eq(s1_type, UInt<3>(0h0))
node _s1_tag_match_way_T_1 = eq(s1_type, UInt<3>(0h2))
node _s1_tag_match_way_T_2 = eq(s1_type, UInt<3>(0h3))
node _s1_tag_match_way_T_3 = bits(s1_tag_eq_way[0], 0, 0)
node _s1_tag_match_way_T_4 = gt(meta_0.io.resp[0].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_5 = and(_s1_tag_match_way_T_3, _s1_tag_match_way_T_4)
node _s1_tag_match_way_T_6 = bits(s1_tag_eq_way[0], 1, 1)
node _s1_tag_match_way_T_7 = gt(meta_0.io.resp[1].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_8 = and(_s1_tag_match_way_T_6, _s1_tag_match_way_T_7)
node _s1_tag_match_way_T_9 = bits(s1_tag_eq_way[0], 2, 2)
node _s1_tag_match_way_T_10 = gt(meta_0.io.resp[2].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_11 = and(_s1_tag_match_way_T_9, _s1_tag_match_way_T_10)
node _s1_tag_match_way_T_12 = bits(s1_tag_eq_way[0], 3, 3)
node _s1_tag_match_way_T_13 = gt(meta_0.io.resp[3].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_14 = and(_s1_tag_match_way_T_12, _s1_tag_match_way_T_13)
wire _s1_tag_match_way_WIRE : UInt<1>[4]
connect _s1_tag_match_way_WIRE[0], _s1_tag_match_way_T_5
connect _s1_tag_match_way_WIRE[1], _s1_tag_match_way_T_8
connect _s1_tag_match_way_WIRE[2], _s1_tag_match_way_T_11
connect _s1_tag_match_way_WIRE[3], _s1_tag_match_way_T_14
node s1_tag_match_way_lo = cat(_s1_tag_match_way_WIRE[1], _s1_tag_match_way_WIRE[0])
node s1_tag_match_way_hi = cat(_s1_tag_match_way_WIRE[3], _s1_tag_match_way_WIRE[2])
node _s1_tag_match_way_T_15 = cat(s1_tag_match_way_hi, s1_tag_match_way_lo)
node _s1_tag_match_way_T_16 = mux(_s1_tag_match_way_T_2, s1_mshr_meta_read_way_en, _s1_tag_match_way_T_15)
node _s1_tag_match_way_T_17 = mux(_s1_tag_match_way_T_1, s1_wb_way_en, _s1_tag_match_way_T_16)
node _s1_tag_match_way_T_18 = mux(_s1_tag_match_way_T, s1_replay_way_en, _s1_tag_match_way_T_17)
wire s1_tag_match_way : UInt[1]
connect s1_tag_match_way[0], _s1_tag_match_way_T_18
node _s1_wb_idx_matches_T = bits(s1_req[0].addr, 11, 6)
node _s1_wb_idx_matches_T_1 = eq(_s1_wb_idx_matches_T, wb.io.idx.bits)
node _s1_wb_idx_matches_T_2 = and(_s1_wb_idx_matches_T_1, wb.io.idx.valid)
wire s1_wb_idx_matches : UInt<1>[1]
connect s1_wb_idx_matches[0], _s1_wb_idx_matches_T_2
reg s2_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}[1], clock
connect s2_req, s1_req
reg s2_type : UInt, clock
connect s2_type, s1_type
node _s2_valid_T = eq(io.lsu.s1_kill[0], UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid[0], _s2_valid_T)
node _s2_valid_T_2 = and(io.lsu.brupdate.b1.mispredict_mask, s1_req[0].uop.br_mask)
node _s2_valid_T_3 = neq(_s2_valid_T_2, UInt<1>(0h0))
node _s2_valid_T_4 = eq(_s2_valid_T_3, UInt<1>(0h0))
node _s2_valid_T_5 = and(_s2_valid_T_1, _s2_valid_T_4)
node _s2_valid_T_6 = and(io.lsu.exception, s1_req[0].uop.uses_ldq)
node _s2_valid_T_7 = eq(_s2_valid_T_6, UInt<1>(0h0))
node _s2_valid_T_8 = and(_s2_valid_T_5, _s2_valid_T_7)
node _s2_valid_T_9 = eq(s1_type, UInt<3>(0h4))
node _s2_valid_T_10 = and(s2_store_failed, _s2_valid_T_9)
node _s2_valid_T_11 = and(_s2_valid_T_10, s1_req[0].uop.uses_stq)
node _s2_valid_T_12 = eq(_s2_valid_T_11, UInt<1>(0h0))
node _s2_valid_T_13 = and(_s2_valid_T_8, _s2_valid_T_12)
reg s2_valid_REG : UInt<1>, clock
connect s2_valid_REG, _s2_valid_T_13
wire s2_valid : UInt<1>[1]
connect s2_valid[0], s2_valid_REG
node _s2_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _s2_req_0_uop_br_mask_T_1 = and(s1_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T)
connect s2_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T_1
reg s2_tag_match_way : UInt[1], clock
connect s2_tag_match_way, s1_tag_match_way
node s2_tag_match_0 = orr(s2_tag_match_way[0])
reg s2_hit_state_REG : { state : UInt<2>}, clock
connect s2_hit_state_REG, meta_0.io.resp[0].coh
reg s2_hit_state_REG_1 : { state : UInt<2>}, clock
connect s2_hit_state_REG_1, meta_0.io.resp[1].coh
reg s2_hit_state_REG_2 : { state : UInt<2>}, clock
connect s2_hit_state_REG_2, meta_0.io.resp[2].coh
reg s2_hit_state_REG_3 : { state : UInt<2>}, clock
connect s2_hit_state_REG_3, meta_0.io.resp[3].coh
wire _s2_hit_state_WIRE : { state : UInt<2>}[4]
connect _s2_hit_state_WIRE[0], s2_hit_state_REG
connect _s2_hit_state_WIRE[1], s2_hit_state_REG_1
connect _s2_hit_state_WIRE[2], s2_hit_state_REG_2
connect _s2_hit_state_WIRE[3], s2_hit_state_REG_3
node _s2_hit_state_T = bits(s2_tag_match_way[0], 0, 0)
node _s2_hit_state_T_1 = bits(s2_tag_match_way[0], 1, 1)
node _s2_hit_state_T_2 = bits(s2_tag_match_way[0], 2, 2)
node _s2_hit_state_T_3 = bits(s2_tag_match_way[0], 3, 3)
wire _s2_hit_state_WIRE_1 : { state : UInt<2>}
node _s2_hit_state_T_4 = mux(_s2_hit_state_T, _s2_hit_state_WIRE[0].state, UInt<1>(0h0))
node _s2_hit_state_T_5 = mux(_s2_hit_state_T_1, _s2_hit_state_WIRE[1].state, UInt<1>(0h0))
node _s2_hit_state_T_6 = mux(_s2_hit_state_T_2, _s2_hit_state_WIRE[2].state, UInt<1>(0h0))
node _s2_hit_state_T_7 = mux(_s2_hit_state_T_3, _s2_hit_state_WIRE[3].state, UInt<1>(0h0))
node _s2_hit_state_T_8 = or(_s2_hit_state_T_4, _s2_hit_state_T_5)
node _s2_hit_state_T_9 = or(_s2_hit_state_T_8, _s2_hit_state_T_6)
node _s2_hit_state_T_10 = or(_s2_hit_state_T_9, _s2_hit_state_T_7)
wire _s2_hit_state_WIRE_2 : UInt<2>
connect _s2_hit_state_WIRE_2, _s2_hit_state_T_10
connect _s2_hit_state_WIRE_1.state, _s2_hit_state_WIRE_2
wire s2_hit_state : { state : UInt<2>}[1]
connect s2_hit_state[0], _s2_hit_state_WIRE_1
node _s2_has_permission_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_has_permission_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_has_permission_r_c_cat_T_2 = or(_s2_has_permission_r_c_cat_T, _s2_has_permission_r_c_cat_T_1)
node _s2_has_permission_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_has_permission_r_c_cat_T_4 = or(_s2_has_permission_r_c_cat_T_2, _s2_has_permission_r_c_cat_T_3)
node _s2_has_permission_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_has_permission_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_has_permission_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_has_permission_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_has_permission_r_c_cat_T_9 = or(_s2_has_permission_r_c_cat_T_5, _s2_has_permission_r_c_cat_T_6)
node _s2_has_permission_r_c_cat_T_10 = or(_s2_has_permission_r_c_cat_T_9, _s2_has_permission_r_c_cat_T_7)
node _s2_has_permission_r_c_cat_T_11 = or(_s2_has_permission_r_c_cat_T_10, _s2_has_permission_r_c_cat_T_8)
node _s2_has_permission_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_has_permission_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_has_permission_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_has_permission_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_has_permission_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_has_permission_r_c_cat_T_17 = or(_s2_has_permission_r_c_cat_T_12, _s2_has_permission_r_c_cat_T_13)
node _s2_has_permission_r_c_cat_T_18 = or(_s2_has_permission_r_c_cat_T_17, _s2_has_permission_r_c_cat_T_14)
node _s2_has_permission_r_c_cat_T_19 = or(_s2_has_permission_r_c_cat_T_18, _s2_has_permission_r_c_cat_T_15)
node _s2_has_permission_r_c_cat_T_20 = or(_s2_has_permission_r_c_cat_T_19, _s2_has_permission_r_c_cat_T_16)
node _s2_has_permission_r_c_cat_T_21 = or(_s2_has_permission_r_c_cat_T_11, _s2_has_permission_r_c_cat_T_20)
node _s2_has_permission_r_c_cat_T_22 = or(_s2_has_permission_r_c_cat_T_4, _s2_has_permission_r_c_cat_T_21)
node _s2_has_permission_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_has_permission_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_has_permission_r_c_cat_T_25 = or(_s2_has_permission_r_c_cat_T_23, _s2_has_permission_r_c_cat_T_24)
node _s2_has_permission_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_has_permission_r_c_cat_T_27 = or(_s2_has_permission_r_c_cat_T_25, _s2_has_permission_r_c_cat_T_26)
node _s2_has_permission_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_has_permission_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_has_permission_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_has_permission_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_has_permission_r_c_cat_T_32 = or(_s2_has_permission_r_c_cat_T_28, _s2_has_permission_r_c_cat_T_29)
node _s2_has_permission_r_c_cat_T_33 = or(_s2_has_permission_r_c_cat_T_32, _s2_has_permission_r_c_cat_T_30)
node _s2_has_permission_r_c_cat_T_34 = or(_s2_has_permission_r_c_cat_T_33, _s2_has_permission_r_c_cat_T_31)
node _s2_has_permission_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_has_permission_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_has_permission_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_has_permission_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_has_permission_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_has_permission_r_c_cat_T_40 = or(_s2_has_permission_r_c_cat_T_35, _s2_has_permission_r_c_cat_T_36)
node _s2_has_permission_r_c_cat_T_41 = or(_s2_has_permission_r_c_cat_T_40, _s2_has_permission_r_c_cat_T_37)
node _s2_has_permission_r_c_cat_T_42 = or(_s2_has_permission_r_c_cat_T_41, _s2_has_permission_r_c_cat_T_38)
node _s2_has_permission_r_c_cat_T_43 = or(_s2_has_permission_r_c_cat_T_42, _s2_has_permission_r_c_cat_T_39)
node _s2_has_permission_r_c_cat_T_44 = or(_s2_has_permission_r_c_cat_T_34, _s2_has_permission_r_c_cat_T_43)
node _s2_has_permission_r_c_cat_T_45 = or(_s2_has_permission_r_c_cat_T_27, _s2_has_permission_r_c_cat_T_44)
node _s2_has_permission_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _s2_has_permission_r_c_cat_T_47 = or(_s2_has_permission_r_c_cat_T_45, _s2_has_permission_r_c_cat_T_46)
node _s2_has_permission_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_has_permission_r_c_cat_T_49 = or(_s2_has_permission_r_c_cat_T_47, _s2_has_permission_r_c_cat_T_48)
node s2_has_permission_r_c = cat(_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49)
node _s2_has_permission_r_T = cat(s2_has_permission_r_c, s2_hit_state[0].state)
node _s2_has_permission_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_2 = cat(_s2_has_permission_r_T_1, UInt<2>(0h3))
node _s2_has_permission_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_4 = cat(_s2_has_permission_r_T_3, UInt<2>(0h2))
node _s2_has_permission_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_6 = cat(_s2_has_permission_r_T_5, UInt<2>(0h1))
node _s2_has_permission_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_8 = cat(_s2_has_permission_r_T_7, UInt<2>(0h3))
node _s2_has_permission_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_10 = cat(_s2_has_permission_r_T_9, UInt<2>(0h2))
node _s2_has_permission_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_12 = cat(_s2_has_permission_r_T_11, UInt<2>(0h3))
node _s2_has_permission_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_14 = cat(_s2_has_permission_r_T_13, UInt<2>(0h2))
node _s2_has_permission_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_16 = cat(_s2_has_permission_r_T_15, UInt<2>(0h0))
node _s2_has_permission_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_18 = cat(_s2_has_permission_r_T_17, UInt<2>(0h1))
node _s2_has_permission_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_20 = cat(_s2_has_permission_r_T_19, UInt<2>(0h0))
node _s2_has_permission_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_22 = cat(_s2_has_permission_r_T_21, UInt<2>(0h1))
node _s2_has_permission_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_24 = cat(_s2_has_permission_r_T_23, UInt<2>(0h0))
node _s2_has_permission_r_T_25 = eq(_s2_has_permission_r_T_24, _s2_has_permission_r_T)
node _s2_has_permission_r_T_26 = mux(_s2_has_permission_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_27 = mux(_s2_has_permission_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _s2_has_permission_r_T_28 = eq(_s2_has_permission_r_T_22, _s2_has_permission_r_T)
node _s2_has_permission_r_T_29 = mux(_s2_has_permission_r_T_28, UInt<1>(0h0), _s2_has_permission_r_T_26)
node _s2_has_permission_r_T_30 = mux(_s2_has_permission_r_T_28, UInt<2>(0h2), _s2_has_permission_r_T_27)
node _s2_has_permission_r_T_31 = eq(_s2_has_permission_r_T_20, _s2_has_permission_r_T)
node _s2_has_permission_r_T_32 = mux(_s2_has_permission_r_T_31, UInt<1>(0h0), _s2_has_permission_r_T_29)
node _s2_has_permission_r_T_33 = mux(_s2_has_permission_r_T_31, UInt<2>(0h1), _s2_has_permission_r_T_30)
node _s2_has_permission_r_T_34 = eq(_s2_has_permission_r_T_18, _s2_has_permission_r_T)
node _s2_has_permission_r_T_35 = mux(_s2_has_permission_r_T_34, UInt<1>(0h0), _s2_has_permission_r_T_32)
node _s2_has_permission_r_T_36 = mux(_s2_has_permission_r_T_34, UInt<2>(0h2), _s2_has_permission_r_T_33)
node _s2_has_permission_r_T_37 = eq(_s2_has_permission_r_T_16, _s2_has_permission_r_T)
node _s2_has_permission_r_T_38 = mux(_s2_has_permission_r_T_37, UInt<1>(0h0), _s2_has_permission_r_T_35)
node _s2_has_permission_r_T_39 = mux(_s2_has_permission_r_T_37, UInt<2>(0h0), _s2_has_permission_r_T_36)
node _s2_has_permission_r_T_40 = eq(_s2_has_permission_r_T_14, _s2_has_permission_r_T)
node _s2_has_permission_r_T_41 = mux(_s2_has_permission_r_T_40, UInt<1>(0h1), _s2_has_permission_r_T_38)
node _s2_has_permission_r_T_42 = mux(_s2_has_permission_r_T_40, UInt<2>(0h3), _s2_has_permission_r_T_39)
node _s2_has_permission_r_T_43 = eq(_s2_has_permission_r_T_12, _s2_has_permission_r_T)
node _s2_has_permission_r_T_44 = mux(_s2_has_permission_r_T_43, UInt<1>(0h1), _s2_has_permission_r_T_41)
node _s2_has_permission_r_T_45 = mux(_s2_has_permission_r_T_43, UInt<2>(0h3), _s2_has_permission_r_T_42)
node _s2_has_permission_r_T_46 = eq(_s2_has_permission_r_T_10, _s2_has_permission_r_T)
node _s2_has_permission_r_T_47 = mux(_s2_has_permission_r_T_46, UInt<1>(0h1), _s2_has_permission_r_T_44)
node _s2_has_permission_r_T_48 = mux(_s2_has_permission_r_T_46, UInt<2>(0h2), _s2_has_permission_r_T_45)
node _s2_has_permission_r_T_49 = eq(_s2_has_permission_r_T_8, _s2_has_permission_r_T)
node _s2_has_permission_r_T_50 = mux(_s2_has_permission_r_T_49, UInt<1>(0h1), _s2_has_permission_r_T_47)
node _s2_has_permission_r_T_51 = mux(_s2_has_permission_r_T_49, UInt<2>(0h3), _s2_has_permission_r_T_48)
node _s2_has_permission_r_T_52 = eq(_s2_has_permission_r_T_6, _s2_has_permission_r_T)
node _s2_has_permission_r_T_53 = mux(_s2_has_permission_r_T_52, UInt<1>(0h1), _s2_has_permission_r_T_50)
node _s2_has_permission_r_T_54 = mux(_s2_has_permission_r_T_52, UInt<2>(0h1), _s2_has_permission_r_T_51)
node _s2_has_permission_r_T_55 = eq(_s2_has_permission_r_T_4, _s2_has_permission_r_T)
node _s2_has_permission_r_T_56 = mux(_s2_has_permission_r_T_55, UInt<1>(0h1), _s2_has_permission_r_T_53)
node _s2_has_permission_r_T_57 = mux(_s2_has_permission_r_T_55, UInt<2>(0h2), _s2_has_permission_r_T_54)
node _s2_has_permission_r_T_58 = eq(_s2_has_permission_r_T_2, _s2_has_permission_r_T)
node s2_has_permission_r_1 = mux(_s2_has_permission_r_T_58, UInt<1>(0h1), _s2_has_permission_r_T_56)
node s2_has_permission_r_2 = mux(_s2_has_permission_r_T_58, UInt<2>(0h3), _s2_has_permission_r_T_57)
wire s2_has_permission_meta : { state : UInt<2>}
connect s2_has_permission_meta.state, s2_has_permission_r_2
wire s2_has_permission : UInt<1>[1]
connect s2_has_permission[0], s2_has_permission_r_1
node _s2_new_hit_state_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_new_hit_state_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_new_hit_state_r_c_cat_T_2 = or(_s2_new_hit_state_r_c_cat_T, _s2_new_hit_state_r_c_cat_T_1)
node _s2_new_hit_state_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_new_hit_state_r_c_cat_T_4 = or(_s2_new_hit_state_r_c_cat_T_2, _s2_new_hit_state_r_c_cat_T_3)
node _s2_new_hit_state_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_new_hit_state_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_new_hit_state_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_new_hit_state_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_new_hit_state_r_c_cat_T_9 = or(_s2_new_hit_state_r_c_cat_T_5, _s2_new_hit_state_r_c_cat_T_6)
node _s2_new_hit_state_r_c_cat_T_10 = or(_s2_new_hit_state_r_c_cat_T_9, _s2_new_hit_state_r_c_cat_T_7)
node _s2_new_hit_state_r_c_cat_T_11 = or(_s2_new_hit_state_r_c_cat_T_10, _s2_new_hit_state_r_c_cat_T_8)
node _s2_new_hit_state_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_new_hit_state_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_new_hit_state_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_new_hit_state_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_new_hit_state_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_new_hit_state_r_c_cat_T_17 = or(_s2_new_hit_state_r_c_cat_T_12, _s2_new_hit_state_r_c_cat_T_13)
node _s2_new_hit_state_r_c_cat_T_18 = or(_s2_new_hit_state_r_c_cat_T_17, _s2_new_hit_state_r_c_cat_T_14)
node _s2_new_hit_state_r_c_cat_T_19 = or(_s2_new_hit_state_r_c_cat_T_18, _s2_new_hit_state_r_c_cat_T_15)
node _s2_new_hit_state_r_c_cat_T_20 = or(_s2_new_hit_state_r_c_cat_T_19, _s2_new_hit_state_r_c_cat_T_16)
node _s2_new_hit_state_r_c_cat_T_21 = or(_s2_new_hit_state_r_c_cat_T_11, _s2_new_hit_state_r_c_cat_T_20)
node _s2_new_hit_state_r_c_cat_T_22 = or(_s2_new_hit_state_r_c_cat_T_4, _s2_new_hit_state_r_c_cat_T_21)
node _s2_new_hit_state_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_new_hit_state_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_new_hit_state_r_c_cat_T_25 = or(_s2_new_hit_state_r_c_cat_T_23, _s2_new_hit_state_r_c_cat_T_24)
node _s2_new_hit_state_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_new_hit_state_r_c_cat_T_27 = or(_s2_new_hit_state_r_c_cat_T_25, _s2_new_hit_state_r_c_cat_T_26)
node _s2_new_hit_state_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_new_hit_state_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_new_hit_state_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_new_hit_state_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_new_hit_state_r_c_cat_T_32 = or(_s2_new_hit_state_r_c_cat_T_28, _s2_new_hit_state_r_c_cat_T_29)
node _s2_new_hit_state_r_c_cat_T_33 = or(_s2_new_hit_state_r_c_cat_T_32, _s2_new_hit_state_r_c_cat_T_30)
node _s2_new_hit_state_r_c_cat_T_34 = or(_s2_new_hit_state_r_c_cat_T_33, _s2_new_hit_state_r_c_cat_T_31)
node _s2_new_hit_state_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_new_hit_state_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_new_hit_state_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_new_hit_state_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_new_hit_state_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_new_hit_state_r_c_cat_T_40 = or(_s2_new_hit_state_r_c_cat_T_35, _s2_new_hit_state_r_c_cat_T_36)
node _s2_new_hit_state_r_c_cat_T_41 = or(_s2_new_hit_state_r_c_cat_T_40, _s2_new_hit_state_r_c_cat_T_37)
node _s2_new_hit_state_r_c_cat_T_42 = or(_s2_new_hit_state_r_c_cat_T_41, _s2_new_hit_state_r_c_cat_T_38)
node _s2_new_hit_state_r_c_cat_T_43 = or(_s2_new_hit_state_r_c_cat_T_42, _s2_new_hit_state_r_c_cat_T_39)
node _s2_new_hit_state_r_c_cat_T_44 = or(_s2_new_hit_state_r_c_cat_T_34, _s2_new_hit_state_r_c_cat_T_43)
node _s2_new_hit_state_r_c_cat_T_45 = or(_s2_new_hit_state_r_c_cat_T_27, _s2_new_hit_state_r_c_cat_T_44)
node _s2_new_hit_state_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _s2_new_hit_state_r_c_cat_T_47 = or(_s2_new_hit_state_r_c_cat_T_45, _s2_new_hit_state_r_c_cat_T_46)
node _s2_new_hit_state_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_new_hit_state_r_c_cat_T_49 = or(_s2_new_hit_state_r_c_cat_T_47, _s2_new_hit_state_r_c_cat_T_48)
node s2_new_hit_state_r_c = cat(_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49)
node _s2_new_hit_state_r_T = cat(s2_new_hit_state_r_c, s2_hit_state[0].state)
node _s2_new_hit_state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_2 = cat(_s2_new_hit_state_r_T_1, UInt<2>(0h3))
node _s2_new_hit_state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_4 = cat(_s2_new_hit_state_r_T_3, UInt<2>(0h2))
node _s2_new_hit_state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_6 = cat(_s2_new_hit_state_r_T_5, UInt<2>(0h1))
node _s2_new_hit_state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_8 = cat(_s2_new_hit_state_r_T_7, UInt<2>(0h3))
node _s2_new_hit_state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_10 = cat(_s2_new_hit_state_r_T_9, UInt<2>(0h2))
node _s2_new_hit_state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_12 = cat(_s2_new_hit_state_r_T_11, UInt<2>(0h3))
node _s2_new_hit_state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_14 = cat(_s2_new_hit_state_r_T_13, UInt<2>(0h2))
node _s2_new_hit_state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_16 = cat(_s2_new_hit_state_r_T_15, UInt<2>(0h0))
node _s2_new_hit_state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_18 = cat(_s2_new_hit_state_r_T_17, UInt<2>(0h1))
node _s2_new_hit_state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_20 = cat(_s2_new_hit_state_r_T_19, UInt<2>(0h0))
node _s2_new_hit_state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_22 = cat(_s2_new_hit_state_r_T_21, UInt<2>(0h1))
node _s2_new_hit_state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_24 = cat(_s2_new_hit_state_r_T_23, UInt<2>(0h0))
node _s2_new_hit_state_r_T_25 = eq(_s2_new_hit_state_r_T_24, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_26 = mux(_s2_new_hit_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_27 = mux(_s2_new_hit_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _s2_new_hit_state_r_T_28 = eq(_s2_new_hit_state_r_T_22, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_29 = mux(_s2_new_hit_state_r_T_28, UInt<1>(0h0), _s2_new_hit_state_r_T_26)
node _s2_new_hit_state_r_T_30 = mux(_s2_new_hit_state_r_T_28, UInt<2>(0h2), _s2_new_hit_state_r_T_27)
node _s2_new_hit_state_r_T_31 = eq(_s2_new_hit_state_r_T_20, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_32 = mux(_s2_new_hit_state_r_T_31, UInt<1>(0h0), _s2_new_hit_state_r_T_29)
node _s2_new_hit_state_r_T_33 = mux(_s2_new_hit_state_r_T_31, UInt<2>(0h1), _s2_new_hit_state_r_T_30)
node _s2_new_hit_state_r_T_34 = eq(_s2_new_hit_state_r_T_18, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_35 = mux(_s2_new_hit_state_r_T_34, UInt<1>(0h0), _s2_new_hit_state_r_T_32)
node _s2_new_hit_state_r_T_36 = mux(_s2_new_hit_state_r_T_34, UInt<2>(0h2), _s2_new_hit_state_r_T_33)
node _s2_new_hit_state_r_T_37 = eq(_s2_new_hit_state_r_T_16, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_38 = mux(_s2_new_hit_state_r_T_37, UInt<1>(0h0), _s2_new_hit_state_r_T_35)
node _s2_new_hit_state_r_T_39 = mux(_s2_new_hit_state_r_T_37, UInt<2>(0h0), _s2_new_hit_state_r_T_36)
node _s2_new_hit_state_r_T_40 = eq(_s2_new_hit_state_r_T_14, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_41 = mux(_s2_new_hit_state_r_T_40, UInt<1>(0h1), _s2_new_hit_state_r_T_38)
node _s2_new_hit_state_r_T_42 = mux(_s2_new_hit_state_r_T_40, UInt<2>(0h3), _s2_new_hit_state_r_T_39)
node _s2_new_hit_state_r_T_43 = eq(_s2_new_hit_state_r_T_12, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_44 = mux(_s2_new_hit_state_r_T_43, UInt<1>(0h1), _s2_new_hit_state_r_T_41)
node _s2_new_hit_state_r_T_45 = mux(_s2_new_hit_state_r_T_43, UInt<2>(0h3), _s2_new_hit_state_r_T_42)
node _s2_new_hit_state_r_T_46 = eq(_s2_new_hit_state_r_T_10, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_47 = mux(_s2_new_hit_state_r_T_46, UInt<1>(0h1), _s2_new_hit_state_r_T_44)
node _s2_new_hit_state_r_T_48 = mux(_s2_new_hit_state_r_T_46, UInt<2>(0h2), _s2_new_hit_state_r_T_45)
node _s2_new_hit_state_r_T_49 = eq(_s2_new_hit_state_r_T_8, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_50 = mux(_s2_new_hit_state_r_T_49, UInt<1>(0h1), _s2_new_hit_state_r_T_47)
node _s2_new_hit_state_r_T_51 = mux(_s2_new_hit_state_r_T_49, UInt<2>(0h3), _s2_new_hit_state_r_T_48)
node _s2_new_hit_state_r_T_52 = eq(_s2_new_hit_state_r_T_6, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_53 = mux(_s2_new_hit_state_r_T_52, UInt<1>(0h1), _s2_new_hit_state_r_T_50)
node _s2_new_hit_state_r_T_54 = mux(_s2_new_hit_state_r_T_52, UInt<2>(0h1), _s2_new_hit_state_r_T_51)
node _s2_new_hit_state_r_T_55 = eq(_s2_new_hit_state_r_T_4, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_56 = mux(_s2_new_hit_state_r_T_55, UInt<1>(0h1), _s2_new_hit_state_r_T_53)
node _s2_new_hit_state_r_T_57 = mux(_s2_new_hit_state_r_T_55, UInt<2>(0h2), _s2_new_hit_state_r_T_54)
node _s2_new_hit_state_r_T_58 = eq(_s2_new_hit_state_r_T_2, _s2_new_hit_state_r_T)
node s2_new_hit_state_r_1 = mux(_s2_new_hit_state_r_T_58, UInt<1>(0h1), _s2_new_hit_state_r_T_56)
node s2_new_hit_state_r_2 = mux(_s2_new_hit_state_r_T_58, UInt<2>(0h3), _s2_new_hit_state_r_T_57)
wire s2_new_hit_state_meta : { state : UInt<2>}
connect s2_new_hit_state_meta.state, s2_new_hit_state_r_2
wire s2_new_hit_state : { state : UInt<2>}[1]
connect s2_new_hit_state[0], s2_new_hit_state_meta
node _s2_hit_T = and(s2_tag_match_0, s2_has_permission[0])
node _s2_hit_T_1 = eq(s2_hit_state[0].state, s2_new_hit_state[0].state)
node _s2_hit_T_2 = and(_s2_hit_T, _s2_hit_T_1)
node _s2_hit_T_3 = eq(mshrs.io.block_hit[0], UInt<1>(0h0))
node _s2_hit_T_4 = and(_s2_hit_T_2, _s2_hit_T_3)
node _s2_hit_T_5 = eq(s2_type, UInt<3>(0h0))
node _s2_hit_T_6 = eq(s2_type, UInt<3>(0h2))
node _s2_hit_T_7 = or(_s2_hit_T_5, _s2_hit_T_6)
node _s2_hit_T_8 = or(_s2_hit_T_4, _s2_hit_T_7)
wire s2_hit : UInt<1>[1]
connect s2_hit[0], _s2_hit_T_8
wire s2_nack : UInt<1>[1]
node _T_16 = eq(s2_type, UInt<3>(0h0))
node _T_17 = eq(s2_hit[0], UInt<1>(0h0))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed: Replays should always hit\n at dcache.scala:651 assert(!(s2_type === t_replay && !s2_hit(0)), \"Replays should always hit\")\n") : printf_2
assert(clock, _T_19, UInt<1>(0h1), "") : assert_2
node _T_23 = eq(s2_type, UInt<3>(0h2))
node _T_24 = eq(s2_hit[0], UInt<1>(0h0))
node _T_25 = and(_T_23, _T_24)
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed: Writeback should always see data hit\n at dcache.scala:652 assert(!(s2_type === t_wb && !s2_hit(0)), \"Writeback should always see data hit\")\n") : printf_3
assert(clock, _T_26, UInt<1>(0h1), "") : assert_3
reg s2_wb_idx_matches : UInt<1>[1], clock
connect s2_wb_idx_matches, s1_wb_idx_matches
regreset debug_sc_fail_addr : UInt, clock, reset, UInt<1>(0h0)
regreset debug_sc_fail_cnt : UInt<8>, clock, reset, UInt<8>(0h0)
regreset lrsc_count : UInt<7>, clock, reset, UInt<7>(0h0)
node lrsc_valid = gt(lrsc_count, UInt<2>(0h3))
reg lrsc_addr : UInt, clock
node _s2_lr_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
reg s2_lr_REG : UInt<1>, clock
connect s2_lr_REG, s1_nack_0
node _s2_lr_T_1 = eq(s2_lr_REG, UInt<1>(0h0))
node _s2_lr_T_2 = eq(s2_type, UInt<3>(0h0))
node _s2_lr_T_3 = or(_s2_lr_T_1, _s2_lr_T_2)
node s2_lr = and(_s2_lr_T, _s2_lr_T_3)
node _s2_sc_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
reg s2_sc_REG : UInt<1>, clock
connect s2_sc_REG, s1_nack_0
node _s2_sc_T_1 = eq(s2_sc_REG, UInt<1>(0h0))
node _s2_sc_T_2 = eq(s2_type, UInt<3>(0h0))
node _s2_sc_T_3 = or(_s2_sc_T_1, _s2_sc_T_2)
node s2_sc = and(_s2_sc_T, _s2_sc_T_3)
node _s2_lrsc_addr_match_T = shr(s2_req[0].addr, 6)
node _s2_lrsc_addr_match_T_1 = eq(lrsc_addr, _s2_lrsc_addr_match_T)
node _s2_lrsc_addr_match_T_2 = and(lrsc_valid, _s2_lrsc_addr_match_T_1)
wire s2_lrsc_addr_match : UInt<1>[1]
connect s2_lrsc_addr_match[0], _s2_lrsc_addr_match_T_2
node _s2_sc_fail_T = eq(s2_lrsc_addr_match[0], UInt<1>(0h0))
node s2_sc_fail = and(s2_sc, _s2_sc_fail_T)
node _T_30 = gt(lrsc_count, UInt<1>(0h0))
when _T_30 :
node _lrsc_count_T = sub(lrsc_count, UInt<1>(0h1))
node _lrsc_count_T_1 = tail(_lrsc_count_T, 1)
connect lrsc_count, _lrsc_count_T_1
node _T_31 = eq(s2_type, UInt<3>(0h4))
node _T_32 = and(_T_31, s2_hit[0])
node _T_33 = eq(s2_nack[0], UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(s2_type, UInt<3>(0h0))
node _T_36 = neq(s2_req[0].uop.mem_cmd, UInt<3>(0h5))
node _T_37 = and(_T_35, _T_36)
node _T_38 = or(_T_34, _T_37)
node _T_39 = and(s2_valid[0], _T_38)
when _T_39 :
when s2_lr :
connect lrsc_count, UInt<7>(0h4f)
node _lrsc_addr_T = shr(s2_req[0].addr, 6)
connect lrsc_addr, _lrsc_addr_T
node _T_40 = gt(lrsc_count, UInt<1>(0h0))
when _T_40 :
connect lrsc_count, UInt<1>(0h0)
node _T_41 = eq(s2_type, UInt<3>(0h4))
node _T_42 = and(s2_valid[0], _T_41)
node _T_43 = eq(s2_hit[0], UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = and(s2_has_permission[0], s2_tag_match_0)
node _T_46 = eq(_T_45, UInt<1>(0h0))
node _T_47 = and(_T_44, _T_46)
node _T_48 = and(_T_47, s2_lrsc_addr_match[0])
node _T_49 = eq(s2_nack[0], UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
when _T_50 :
connect lrsc_count, UInt<1>(0h0)
when s2_valid[0] :
node _T_51 = eq(s2_req[0].addr, debug_sc_fail_addr)
when _T_51 :
when s2_sc_fail :
node _debug_sc_fail_cnt_T = add(debug_sc_fail_cnt, UInt<1>(0h1))
node _debug_sc_fail_cnt_T_1 = tail(_debug_sc_fail_cnt_T, 1)
connect debug_sc_fail_cnt, _debug_sc_fail_cnt_T_1
else :
when s2_sc :
connect debug_sc_fail_cnt, UInt<1>(0h0)
else :
when s2_sc_fail :
connect debug_sc_fail_addr, s2_req[0].addr
connect debug_sc_fail_cnt, UInt<1>(0h1)
node _T_52 = lt(debug_sc_fail_cnt, UInt<7>(0h64))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: L1DCache failed too many SCs in a row\n at dcache.scala:703 assert(debug_sc_fail_cnt < 100.U, \"L1DCache failed too many SCs in a row\")\n") : printf_4
assert(clock, _T_52, UInt<1>(0h1), "") : assert_4
wire s2_data : UInt<64>[4][1]
connect s2_data[0][0], data.io.resp[0][0]
connect s2_data[0][1], data.io.resp[0][1]
connect s2_data[0][2], data.io.resp[0][2]
connect s2_data[0][3], data.io.resp[0][3]
node _s2_data_muxed_T = bits(s2_tag_match_way[0], 0, 0)
node _s2_data_muxed_T_1 = bits(s2_tag_match_way[0], 1, 1)
node _s2_data_muxed_T_2 = bits(s2_tag_match_way[0], 2, 2)
node _s2_data_muxed_T_3 = bits(s2_tag_match_way[0], 3, 3)
node _s2_data_muxed_T_4 = mux(_s2_data_muxed_T, s2_data[0][0], UInt<1>(0h0))
node _s2_data_muxed_T_5 = mux(_s2_data_muxed_T_1, s2_data[0][1], UInt<1>(0h0))
node _s2_data_muxed_T_6 = mux(_s2_data_muxed_T_2, s2_data[0][2], UInt<1>(0h0))
node _s2_data_muxed_T_7 = mux(_s2_data_muxed_T_3, s2_data[0][3], UInt<1>(0h0))
node _s2_data_muxed_T_8 = or(_s2_data_muxed_T_4, _s2_data_muxed_T_5)
node _s2_data_muxed_T_9 = or(_s2_data_muxed_T_8, _s2_data_muxed_T_6)
node _s2_data_muxed_T_10 = or(_s2_data_muxed_T_9, _s2_data_muxed_T_7)
wire _s2_data_muxed_WIRE : UInt<64>
connect _s2_data_muxed_WIRE, _s2_data_muxed_T_10
wire s2_data_muxed : UInt<64>[1]
connect s2_data_muxed[0], _s2_data_muxed_WIRE
wire s2_word_idx : UInt<1>[1]
connect s2_word_idx[0], UInt<1>(0h0)
wire replace : UInt<1>
connect replace, UInt<1>(0h0)
inst lfsr_prng of MaxPeriodFibonacciLFSR_7
connect lfsr_prng.clock, clock
connect lfsr_prng.reset, reset
connect lfsr_prng.io.seed.valid, UInt<1>(0h0)
invalidate lfsr_prng.io.seed.bits[0]
invalidate lfsr_prng.io.seed.bits[1]
invalidate lfsr_prng.io.seed.bits[2]
invalidate lfsr_prng.io.seed.bits[3]
invalidate lfsr_prng.io.seed.bits[4]
invalidate lfsr_prng.io.seed.bits[5]
invalidate lfsr_prng.io.seed.bits[6]
invalidate lfsr_prng.io.seed.bits[7]
invalidate lfsr_prng.io.seed.bits[8]
invalidate lfsr_prng.io.seed.bits[9]
invalidate lfsr_prng.io.seed.bits[10]
invalidate lfsr_prng.io.seed.bits[11]
invalidate lfsr_prng.io.seed.bits[12]
invalidate lfsr_prng.io.seed.bits[13]
invalidate lfsr_prng.io.seed.bits[14]
invalidate lfsr_prng.io.seed.bits[15]
connect lfsr_prng.io.increment, replace
node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0])
node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2])
node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo)
node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4])
node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6])
node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo)
node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo)
node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8])
node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10])
node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo)
node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12])
node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14])
node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo)
node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo)
node lfsr = cat(lfsr_hi, lfsr_lo)
node _s1_replaced_way_en_T = bits(lfsr, 1, 0)
node s1_replaced_way_en = dshl(UInt<1>(0h1), _s1_replaced_way_en_T)
node _s2_replaced_way_en_T = bits(lfsr, 1, 0)
reg s2_replaced_way_en_REG : UInt, clock
connect s2_replaced_way_en_REG, _s2_replaced_way_en_T
node s2_replaced_way_en = dshl(UInt<1>(0h1), s2_replaced_way_en_REG)
reg s2_repl_meta_REG : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG, meta_0.io.resp[0]
reg s2_repl_meta_REG_1 : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG_1, meta_0.io.resp[1]
reg s2_repl_meta_REG_2 : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG_2, meta_0.io.resp[2]
reg s2_repl_meta_REG_3 : { coh : { state : UInt<2>}, tag : UInt<20>}, clock
connect s2_repl_meta_REG_3, meta_0.io.resp[3]
wire _s2_repl_meta_WIRE : { coh : { state : UInt<2>}, tag : UInt<20>}[4]
connect _s2_repl_meta_WIRE[0], s2_repl_meta_REG
connect _s2_repl_meta_WIRE[1], s2_repl_meta_REG_1
connect _s2_repl_meta_WIRE[2], s2_repl_meta_REG_2
connect _s2_repl_meta_WIRE[3], s2_repl_meta_REG_3
node _s2_repl_meta_T = bits(s2_replaced_way_en, 0, 0)
node _s2_repl_meta_T_1 = bits(s2_replaced_way_en, 1, 1)
node _s2_repl_meta_T_2 = bits(s2_replaced_way_en, 2, 2)
node _s2_repl_meta_T_3 = bits(s2_replaced_way_en, 3, 3)
wire _s2_repl_meta_WIRE_1 : { coh : { state : UInt<2>}, tag : UInt<20>}
node _s2_repl_meta_T_4 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].tag, UInt<1>(0h0))
node _s2_repl_meta_T_5 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].tag, UInt<1>(0h0))
node _s2_repl_meta_T_6 = mux(_s2_repl_meta_T_2, _s2_repl_meta_WIRE[2].tag, UInt<1>(0h0))
node _s2_repl_meta_T_7 = mux(_s2_repl_meta_T_3, _s2_repl_meta_WIRE[3].tag, UInt<1>(0h0))
node _s2_repl_meta_T_8 = or(_s2_repl_meta_T_4, _s2_repl_meta_T_5)
node _s2_repl_meta_T_9 = or(_s2_repl_meta_T_8, _s2_repl_meta_T_6)
node _s2_repl_meta_T_10 = or(_s2_repl_meta_T_9, _s2_repl_meta_T_7)
wire _s2_repl_meta_WIRE_2 : UInt<20>
connect _s2_repl_meta_WIRE_2, _s2_repl_meta_T_10
connect _s2_repl_meta_WIRE_1.tag, _s2_repl_meta_WIRE_2
wire _s2_repl_meta_WIRE_3 : { state : UInt<2>}
node _s2_repl_meta_T_11 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_12 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_13 = mux(_s2_repl_meta_T_2, _s2_repl_meta_WIRE[2].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_14 = mux(_s2_repl_meta_T_3, _s2_repl_meta_WIRE[3].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_15 = or(_s2_repl_meta_T_11, _s2_repl_meta_T_12)
node _s2_repl_meta_T_16 = or(_s2_repl_meta_T_15, _s2_repl_meta_T_13)
node _s2_repl_meta_T_17 = or(_s2_repl_meta_T_16, _s2_repl_meta_T_14)
wire _s2_repl_meta_WIRE_4 : UInt<2>
connect _s2_repl_meta_WIRE_4, _s2_repl_meta_T_17
connect _s2_repl_meta_WIRE_3.state, _s2_repl_meta_WIRE_4
connect _s2_repl_meta_WIRE_1.coh, _s2_repl_meta_WIRE_3
wire s2_repl_meta : { coh : { state : UInt<2>}, tag : UInt<20>}[1]
connect s2_repl_meta[0], _s2_repl_meta_WIRE_1
wire _s2_nack_hit_WIRE : UInt<1>[1]
connect _s2_nack_hit_WIRE[0], s1_nack_0
reg s2_nack_hit : UInt<1>[1], clock
connect s2_nack_hit, _s2_nack_hit_WIRE
node _s2_nack_victim_T = and(s2_valid[0], s2_hit[0])
node _s2_nack_victim_T_1 = and(_s2_nack_victim_T, mshrs.io.secondary_miss[0])
wire s2_nack_victim : UInt<1>[1]
connect s2_nack_victim[0], _s2_nack_victim_T_1
node _s2_nack_miss_T = eq(s2_hit[0], UInt<1>(0h0))
node _s2_nack_miss_T_1 = and(s2_valid[0], _s2_nack_miss_T)
node _s2_nack_miss_T_2 = eq(mshrs.io.req[0].ready, UInt<1>(0h0))
node _s2_nack_miss_T_3 = and(_s2_nack_miss_T_1, _s2_nack_miss_T_2)
wire s2_nack_miss : UInt<1>[1]
connect s2_nack_miss[0], _s2_nack_miss_T_3
wire s2_nack_data : UInt<1>[1]
connect s2_nack_data[0], data.io.nacks[0]
node _s2_nack_wb_T = eq(s2_hit[0], UInt<1>(0h0))
node _s2_nack_wb_T_1 = and(s2_valid[0], _s2_nack_wb_T)
node _s2_nack_wb_T_2 = and(_s2_nack_wb_T_1, s2_wb_idx_matches[0])
wire s2_nack_wb : UInt<1>[1]
connect s2_nack_wb[0], _s2_nack_wb_T_2
node _T_56 = or(s2_nack_miss[0], s2_nack_hit[0])
node _T_57 = or(_T_56, s2_nack_victim[0])
node _T_58 = or(_T_57, s2_nack_data[0])
node _T_59 = or(_T_58, s2_nack_wb[0])
node _T_60 = neq(s2_type, UInt<3>(0h0))
node _T_61 = and(_T_59, _T_60)
wire _WIRE_2 : UInt<1>[1]
connect _WIRE_2[0], _T_61
connect s2_nack, _WIRE_2
reg s2_send_resp_REG : UInt<1>, clock
connect s2_send_resp_REG, s1_send_resp_or_nack[0]
node _s2_send_resp_T = eq(s2_nack[0], UInt<1>(0h0))
node _s2_send_resp_T_1 = and(s2_send_resp_REG, _s2_send_resp_T)
node _s2_send_resp_T_2 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid)
node _s2_send_resp_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_send_resp_T_4 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_send_resp_T_5 = or(_s2_send_resp_T_3, _s2_send_resp_T_4)
node _s2_send_resp_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_send_resp_T_7 = or(_s2_send_resp_T_5, _s2_send_resp_T_6)
node _s2_send_resp_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_send_resp_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_send_resp_T_10 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_send_resp_T_11 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_send_resp_T_12 = or(_s2_send_resp_T_8, _s2_send_resp_T_9)
node _s2_send_resp_T_13 = or(_s2_send_resp_T_12, _s2_send_resp_T_10)
node _s2_send_resp_T_14 = or(_s2_send_resp_T_13, _s2_send_resp_T_11)
node _s2_send_resp_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_send_resp_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_send_resp_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_send_resp_T_18 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_send_resp_T_19 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_send_resp_T_20 = or(_s2_send_resp_T_15, _s2_send_resp_T_16)
node _s2_send_resp_T_21 = or(_s2_send_resp_T_20, _s2_send_resp_T_17)
node _s2_send_resp_T_22 = or(_s2_send_resp_T_21, _s2_send_resp_T_18)
node _s2_send_resp_T_23 = or(_s2_send_resp_T_22, _s2_send_resp_T_19)
node _s2_send_resp_T_24 = or(_s2_send_resp_T_14, _s2_send_resp_T_23)
node _s2_send_resp_T_25 = or(_s2_send_resp_T_7, _s2_send_resp_T_24)
node _s2_send_resp_T_26 = and(_s2_send_resp_T_2, _s2_send_resp_T_25)
node _s2_send_resp_T_27 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0))
node _s2_send_resp_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10))
node _s2_send_resp_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_send_resp_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_send_resp_T_31 = or(_s2_send_resp_T_27, _s2_send_resp_T_28)
node _s2_send_resp_T_32 = or(_s2_send_resp_T_31, _s2_send_resp_T_29)
node _s2_send_resp_T_33 = or(_s2_send_resp_T_32, _s2_send_resp_T_30)
node _s2_send_resp_T_34 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_send_resp_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_send_resp_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_send_resp_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_send_resp_T_38 = or(_s2_send_resp_T_34, _s2_send_resp_T_35)
node _s2_send_resp_T_39 = or(_s2_send_resp_T_38, _s2_send_resp_T_36)
node _s2_send_resp_T_40 = or(_s2_send_resp_T_39, _s2_send_resp_T_37)
node _s2_send_resp_T_41 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_send_resp_T_42 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_send_resp_T_43 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_send_resp_T_44 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_send_resp_T_45 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_send_resp_T_46 = or(_s2_send_resp_T_41, _s2_send_resp_T_42)
node _s2_send_resp_T_47 = or(_s2_send_resp_T_46, _s2_send_resp_T_43)
node _s2_send_resp_T_48 = or(_s2_send_resp_T_47, _s2_send_resp_T_44)
node _s2_send_resp_T_49 = or(_s2_send_resp_T_48, _s2_send_resp_T_45)
node _s2_send_resp_T_50 = or(_s2_send_resp_T_40, _s2_send_resp_T_49)
node _s2_send_resp_T_51 = or(_s2_send_resp_T_33, _s2_send_resp_T_50)
node _s2_send_resp_T_52 = eq(_s2_send_resp_T_51, UInt<1>(0h0))
node _s2_send_resp_T_53 = and(_s2_send_resp_T_26, _s2_send_resp_T_52)
node _s2_send_resp_T_54 = or(s2_hit[0], _s2_send_resp_T_53)
node _s2_send_resp_T_55 = and(_s2_send_resp_T_1, _s2_send_resp_T_54)
wire s2_send_resp : UInt<1>[1]
connect s2_send_resp[0], _s2_send_resp_T_55
reg s2_send_nack_REG : UInt<1>, clock
connect s2_send_nack_REG, s1_send_resp_or_nack[0]
node _s2_send_nack_T = and(s2_send_nack_REG, s2_nack[0])
wire s2_send_nack : UInt<1>[1]
connect s2_send_nack[0], _s2_send_nack_T
node _T_62 = and(s2_send_resp[0], s2_send_nack[0])
node _T_63 = eq(_T_62, UInt<1>(0h0))
node _T_64 = asUInt(reset)
node _T_65 = eq(_T_64, UInt<1>(0h0))
when _T_65 :
node _T_66 = eq(_T_63, UInt<1>(0h0))
when _T_66 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:737 assert(!(s2_send_resp(w) && s2_send_nack(w)))\n") : printf_5
assert(clock, _T_63, UInt<1>(0h1), "") : assert_5
node _s2_store_failed_T = and(s2_valid[0], s2_nack[0])
node _s2_store_failed_T_1 = and(_s2_store_failed_T, s2_send_nack[0])
node _s2_store_failed_T_2 = and(_s2_store_failed_T_1, s2_req[0].uop.uses_stq)
connect s2_store_failed, _s2_store_failed_T_2
node _mshrs_io_req_0_valid_T = eq(s2_hit[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_1 = and(s2_valid[0], _mshrs_io_req_0_valid_T)
node _mshrs_io_req_0_valid_T_2 = eq(s2_nack_hit[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_3 = and(_mshrs_io_req_0_valid_T_1, _mshrs_io_req_0_valid_T_2)
node _mshrs_io_req_0_valid_T_4 = eq(s2_nack_victim[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_5 = and(_mshrs_io_req_0_valid_T_3, _mshrs_io_req_0_valid_T_4)
node _mshrs_io_req_0_valid_T_6 = eq(s2_nack_data[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_7 = and(_mshrs_io_req_0_valid_T_5, _mshrs_io_req_0_valid_T_6)
node _mshrs_io_req_0_valid_T_8 = eq(s2_nack_wb[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_9 = and(_mshrs_io_req_0_valid_T_7, _mshrs_io_req_0_valid_T_8)
node _mshrs_io_req_0_valid_T_10 = eq(s2_type, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_11 = eq(s2_type, UInt<3>(0h5))
node _mshrs_io_req_0_valid_T_12 = or(_mshrs_io_req_0_valid_T_10, _mshrs_io_req_0_valid_T_11)
node _mshrs_io_req_0_valid_T_13 = and(_mshrs_io_req_0_valid_T_9, _mshrs_io_req_0_valid_T_12)
node _mshrs_io_req_0_valid_T_14 = and(io.lsu.brupdate.b1.mispredict_mask, s2_req[0].uop.br_mask)
node _mshrs_io_req_0_valid_T_15 = neq(_mshrs_io_req_0_valid_T_14, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_16 = eq(_mshrs_io_req_0_valid_T_15, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_17 = and(_mshrs_io_req_0_valid_T_13, _mshrs_io_req_0_valid_T_16)
node _mshrs_io_req_0_valid_T_18 = and(io.lsu.exception, s2_req[0].uop.uses_ldq)
node _mshrs_io_req_0_valid_T_19 = eq(_mshrs_io_req_0_valid_T_18, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_20 = and(_mshrs_io_req_0_valid_T_17, _mshrs_io_req_0_valid_T_19)
node _mshrs_io_req_0_valid_T_21 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h2))
node _mshrs_io_req_0_valid_T_22 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _mshrs_io_req_0_valid_T_23 = or(_mshrs_io_req_0_valid_T_21, _mshrs_io_req_0_valid_T_22)
node _mshrs_io_req_0_valid_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_25 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10))
node _mshrs_io_req_0_valid_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _mshrs_io_req_0_valid_T_27 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _mshrs_io_req_0_valid_T_28 = or(_mshrs_io_req_0_valid_T_24, _mshrs_io_req_0_valid_T_25)
node _mshrs_io_req_0_valid_T_29 = or(_mshrs_io_req_0_valid_T_28, _mshrs_io_req_0_valid_T_26)
node _mshrs_io_req_0_valid_T_30 = or(_mshrs_io_req_0_valid_T_29, _mshrs_io_req_0_valid_T_27)
node _mshrs_io_req_0_valid_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_32 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _mshrs_io_req_0_valid_T_33 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _mshrs_io_req_0_valid_T_34 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _mshrs_io_req_0_valid_T_35 = or(_mshrs_io_req_0_valid_T_31, _mshrs_io_req_0_valid_T_32)
node _mshrs_io_req_0_valid_T_36 = or(_mshrs_io_req_0_valid_T_35, _mshrs_io_req_0_valid_T_33)
node _mshrs_io_req_0_valid_T_37 = or(_mshrs_io_req_0_valid_T_36, _mshrs_io_req_0_valid_T_34)
node _mshrs_io_req_0_valid_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _mshrs_io_req_0_valid_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _mshrs_io_req_0_valid_T_40 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _mshrs_io_req_0_valid_T_41 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _mshrs_io_req_0_valid_T_42 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _mshrs_io_req_0_valid_T_43 = or(_mshrs_io_req_0_valid_T_38, _mshrs_io_req_0_valid_T_39)
node _mshrs_io_req_0_valid_T_44 = or(_mshrs_io_req_0_valid_T_43, _mshrs_io_req_0_valid_T_40)
node _mshrs_io_req_0_valid_T_45 = or(_mshrs_io_req_0_valid_T_44, _mshrs_io_req_0_valid_T_41)
node _mshrs_io_req_0_valid_T_46 = or(_mshrs_io_req_0_valid_T_45, _mshrs_io_req_0_valid_T_42)
node _mshrs_io_req_0_valid_T_47 = or(_mshrs_io_req_0_valid_T_37, _mshrs_io_req_0_valid_T_46)
node _mshrs_io_req_0_valid_T_48 = or(_mshrs_io_req_0_valid_T_30, _mshrs_io_req_0_valid_T_47)
node _mshrs_io_req_0_valid_T_49 = or(_mshrs_io_req_0_valid_T_23, _mshrs_io_req_0_valid_T_48)
node _mshrs_io_req_0_valid_T_50 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _mshrs_io_req_0_valid_T_51 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _mshrs_io_req_0_valid_T_52 = or(_mshrs_io_req_0_valid_T_50, _mshrs_io_req_0_valid_T_51)
node _mshrs_io_req_0_valid_T_53 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _mshrs_io_req_0_valid_T_54 = or(_mshrs_io_req_0_valid_T_52, _mshrs_io_req_0_valid_T_53)
node _mshrs_io_req_0_valid_T_55 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_56 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _mshrs_io_req_0_valid_T_57 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _mshrs_io_req_0_valid_T_58 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _mshrs_io_req_0_valid_T_59 = or(_mshrs_io_req_0_valid_T_55, _mshrs_io_req_0_valid_T_56)
node _mshrs_io_req_0_valid_T_60 = or(_mshrs_io_req_0_valid_T_59, _mshrs_io_req_0_valid_T_57)
node _mshrs_io_req_0_valid_T_61 = or(_mshrs_io_req_0_valid_T_60, _mshrs_io_req_0_valid_T_58)
node _mshrs_io_req_0_valid_T_62 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _mshrs_io_req_0_valid_T_63 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _mshrs_io_req_0_valid_T_64 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _mshrs_io_req_0_valid_T_65 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _mshrs_io_req_0_valid_T_66 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _mshrs_io_req_0_valid_T_67 = or(_mshrs_io_req_0_valid_T_62, _mshrs_io_req_0_valid_T_63)
node _mshrs_io_req_0_valid_T_68 = or(_mshrs_io_req_0_valid_T_67, _mshrs_io_req_0_valid_T_64)
node _mshrs_io_req_0_valid_T_69 = or(_mshrs_io_req_0_valid_T_68, _mshrs_io_req_0_valid_T_65)
node _mshrs_io_req_0_valid_T_70 = or(_mshrs_io_req_0_valid_T_69, _mshrs_io_req_0_valid_T_66)
node _mshrs_io_req_0_valid_T_71 = or(_mshrs_io_req_0_valid_T_61, _mshrs_io_req_0_valid_T_70)
node _mshrs_io_req_0_valid_T_72 = or(_mshrs_io_req_0_valid_T_54, _mshrs_io_req_0_valid_T_71)
node _mshrs_io_req_0_valid_T_73 = or(_mshrs_io_req_0_valid_T_49, _mshrs_io_req_0_valid_T_72)
node _mshrs_io_req_0_valid_T_74 = and(_mshrs_io_req_0_valid_T_20, _mshrs_io_req_0_valid_T_73)
connect mshrs.io.req[0].valid, _mshrs_io_req_0_valid_T_74
node _T_67 = eq(s2_type, UInt<3>(0h0))
node _T_68 = and(mshrs.io.req[0].valid, _T_67)
node _T_69 = eq(_T_68, UInt<1>(0h0))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: Replays should not need to go back into MSHRs\n at dcache.scala:758 assert(!(mshrs.io.req(w).valid && s2_type === t_replay), \"Replays should not need to go back into MSHRs\")\n") : printf_6
assert(clock, _T_69, UInt<1>(0h1), "") : assert_6
invalidate mshrs.io.req[0].bits.sdq_id
invalidate mshrs.io.req[0].bits.way_en
invalidate mshrs.io.req[0].bits.old_meta.tag
invalidate mshrs.io.req[0].bits.old_meta.coh.state
invalidate mshrs.io.req[0].bits.tag_match
invalidate mshrs.io.req[0].bits.is_hella
invalidate mshrs.io.req[0].bits.data
invalidate mshrs.io.req[0].bits.addr
invalidate mshrs.io.req[0].bits.uop.debug_tsrc
invalidate mshrs.io.req[0].bits.uop.debug_fsrc
invalidate mshrs.io.req[0].bits.uop.bp_xcpt_if
invalidate mshrs.io.req[0].bits.uop.bp_debug_if
invalidate mshrs.io.req[0].bits.uop.xcpt_ma_if
invalidate mshrs.io.req[0].bits.uop.xcpt_ae_if
invalidate mshrs.io.req[0].bits.uop.xcpt_pf_if
invalidate mshrs.io.req[0].bits.uop.fp_single
invalidate mshrs.io.req[0].bits.uop.fp_val
invalidate mshrs.io.req[0].bits.uop.frs3_en
invalidate mshrs.io.req[0].bits.uop.lrs2_rtype
invalidate mshrs.io.req[0].bits.uop.lrs1_rtype
invalidate mshrs.io.req[0].bits.uop.dst_rtype
invalidate mshrs.io.req[0].bits.uop.ldst_val
invalidate mshrs.io.req[0].bits.uop.lrs3
invalidate mshrs.io.req[0].bits.uop.lrs2
invalidate mshrs.io.req[0].bits.uop.lrs1
invalidate mshrs.io.req[0].bits.uop.ldst
invalidate mshrs.io.req[0].bits.uop.ldst_is_rs1
invalidate mshrs.io.req[0].bits.uop.flush_on_commit
invalidate mshrs.io.req[0].bits.uop.is_unique
invalidate mshrs.io.req[0].bits.uop.is_sys_pc2epc
invalidate mshrs.io.req[0].bits.uop.uses_stq
invalidate mshrs.io.req[0].bits.uop.uses_ldq
invalidate mshrs.io.req[0].bits.uop.is_amo
invalidate mshrs.io.req[0].bits.uop.is_fencei
invalidate mshrs.io.req[0].bits.uop.is_fence
invalidate mshrs.io.req[0].bits.uop.mem_signed
invalidate mshrs.io.req[0].bits.uop.mem_size
invalidate mshrs.io.req[0].bits.uop.mem_cmd
invalidate mshrs.io.req[0].bits.uop.bypassable
invalidate mshrs.io.req[0].bits.uop.exc_cause
invalidate mshrs.io.req[0].bits.uop.exception
invalidate mshrs.io.req[0].bits.uop.stale_pdst
invalidate mshrs.io.req[0].bits.uop.ppred_busy
invalidate mshrs.io.req[0].bits.uop.prs3_busy
invalidate mshrs.io.req[0].bits.uop.prs2_busy
invalidate mshrs.io.req[0].bits.uop.prs1_busy
invalidate mshrs.io.req[0].bits.uop.ppred
invalidate mshrs.io.req[0].bits.uop.prs3
invalidate mshrs.io.req[0].bits.uop.prs2
invalidate mshrs.io.req[0].bits.uop.prs1
invalidate mshrs.io.req[0].bits.uop.pdst
invalidate mshrs.io.req[0].bits.uop.rxq_idx
invalidate mshrs.io.req[0].bits.uop.stq_idx
invalidate mshrs.io.req[0].bits.uop.ldq_idx
invalidate mshrs.io.req[0].bits.uop.rob_idx
invalidate mshrs.io.req[0].bits.uop.csr_addr
invalidate mshrs.io.req[0].bits.uop.imm_packed
invalidate mshrs.io.req[0].bits.uop.taken
invalidate mshrs.io.req[0].bits.uop.pc_lob
invalidate mshrs.io.req[0].bits.uop.edge_inst
invalidate mshrs.io.req[0].bits.uop.ftq_idx
invalidate mshrs.io.req[0].bits.uop.br_tag
invalidate mshrs.io.req[0].bits.uop.br_mask
invalidate mshrs.io.req[0].bits.uop.is_sfb
invalidate mshrs.io.req[0].bits.uop.is_jal
invalidate mshrs.io.req[0].bits.uop.is_jalr
invalidate mshrs.io.req[0].bits.uop.is_br
invalidate mshrs.io.req[0].bits.uop.iw_p2_poisoned
invalidate mshrs.io.req[0].bits.uop.iw_p1_poisoned
invalidate mshrs.io.req[0].bits.uop.iw_state
invalidate mshrs.io.req[0].bits.uop.ctrl.is_std
invalidate mshrs.io.req[0].bits.uop.ctrl.is_sta
invalidate mshrs.io.req[0].bits.uop.ctrl.is_load
invalidate mshrs.io.req[0].bits.uop.ctrl.csr_cmd
invalidate mshrs.io.req[0].bits.uop.ctrl.fcn_dw
invalidate mshrs.io.req[0].bits.uop.ctrl.op_fcn
invalidate mshrs.io.req[0].bits.uop.ctrl.imm_sel
invalidate mshrs.io.req[0].bits.uop.ctrl.op2_sel
invalidate mshrs.io.req[0].bits.uop.ctrl.op1_sel
invalidate mshrs.io.req[0].bits.uop.ctrl.br_type
invalidate mshrs.io.req[0].bits.uop.fu_code
invalidate mshrs.io.req[0].bits.uop.iq_type
invalidate mshrs.io.req[0].bits.uop.debug_pc
invalidate mshrs.io.req[0].bits.uop.is_rvc
invalidate mshrs.io.req[0].bits.uop.debug_inst
invalidate mshrs.io.req[0].bits.uop.inst
invalidate mshrs.io.req[0].bits.uop.uopc
connect mshrs.io.req[0].bits.uop.debug_tsrc, s2_req[0].uop.debug_tsrc
connect mshrs.io.req[0].bits.uop.debug_fsrc, s2_req[0].uop.debug_fsrc
connect mshrs.io.req[0].bits.uop.bp_xcpt_if, s2_req[0].uop.bp_xcpt_if
connect mshrs.io.req[0].bits.uop.bp_debug_if, s2_req[0].uop.bp_debug_if
connect mshrs.io.req[0].bits.uop.xcpt_ma_if, s2_req[0].uop.xcpt_ma_if
connect mshrs.io.req[0].bits.uop.xcpt_ae_if, s2_req[0].uop.xcpt_ae_if
connect mshrs.io.req[0].bits.uop.xcpt_pf_if, s2_req[0].uop.xcpt_pf_if
connect mshrs.io.req[0].bits.uop.fp_single, s2_req[0].uop.fp_single
connect mshrs.io.req[0].bits.uop.fp_val, s2_req[0].uop.fp_val
connect mshrs.io.req[0].bits.uop.frs3_en, s2_req[0].uop.frs3_en
connect mshrs.io.req[0].bits.uop.lrs2_rtype, s2_req[0].uop.lrs2_rtype
connect mshrs.io.req[0].bits.uop.lrs1_rtype, s2_req[0].uop.lrs1_rtype
connect mshrs.io.req[0].bits.uop.dst_rtype, s2_req[0].uop.dst_rtype
connect mshrs.io.req[0].bits.uop.ldst_val, s2_req[0].uop.ldst_val
connect mshrs.io.req[0].bits.uop.lrs3, s2_req[0].uop.lrs3
connect mshrs.io.req[0].bits.uop.lrs2, s2_req[0].uop.lrs2
connect mshrs.io.req[0].bits.uop.lrs1, s2_req[0].uop.lrs1
connect mshrs.io.req[0].bits.uop.ldst, s2_req[0].uop.ldst
connect mshrs.io.req[0].bits.uop.ldst_is_rs1, s2_req[0].uop.ldst_is_rs1
connect mshrs.io.req[0].bits.uop.flush_on_commit, s2_req[0].uop.flush_on_commit
connect mshrs.io.req[0].bits.uop.is_unique, s2_req[0].uop.is_unique
connect mshrs.io.req[0].bits.uop.is_sys_pc2epc, s2_req[0].uop.is_sys_pc2epc
connect mshrs.io.req[0].bits.uop.uses_stq, s2_req[0].uop.uses_stq
connect mshrs.io.req[0].bits.uop.uses_ldq, s2_req[0].uop.uses_ldq
connect mshrs.io.req[0].bits.uop.is_amo, s2_req[0].uop.is_amo
connect mshrs.io.req[0].bits.uop.is_fencei, s2_req[0].uop.is_fencei
connect mshrs.io.req[0].bits.uop.is_fence, s2_req[0].uop.is_fence
connect mshrs.io.req[0].bits.uop.mem_signed, s2_req[0].uop.mem_signed
connect mshrs.io.req[0].bits.uop.mem_size, s2_req[0].uop.mem_size
connect mshrs.io.req[0].bits.uop.mem_cmd, s2_req[0].uop.mem_cmd
connect mshrs.io.req[0].bits.uop.bypassable, s2_req[0].uop.bypassable
connect mshrs.io.req[0].bits.uop.exc_cause, s2_req[0].uop.exc_cause
connect mshrs.io.req[0].bits.uop.exception, s2_req[0].uop.exception
connect mshrs.io.req[0].bits.uop.stale_pdst, s2_req[0].uop.stale_pdst
connect mshrs.io.req[0].bits.uop.ppred_busy, s2_req[0].uop.ppred_busy
connect mshrs.io.req[0].bits.uop.prs3_busy, s2_req[0].uop.prs3_busy
connect mshrs.io.req[0].bits.uop.prs2_busy, s2_req[0].uop.prs2_busy
connect mshrs.io.req[0].bits.uop.prs1_busy, s2_req[0].uop.prs1_busy
connect mshrs.io.req[0].bits.uop.ppred, s2_req[0].uop.ppred
connect mshrs.io.req[0].bits.uop.prs3, s2_req[0].uop.prs3
connect mshrs.io.req[0].bits.uop.prs2, s2_req[0].uop.prs2
connect mshrs.io.req[0].bits.uop.prs1, s2_req[0].uop.prs1
connect mshrs.io.req[0].bits.uop.pdst, s2_req[0].uop.pdst
connect mshrs.io.req[0].bits.uop.rxq_idx, s2_req[0].uop.rxq_idx
connect mshrs.io.req[0].bits.uop.stq_idx, s2_req[0].uop.stq_idx
connect mshrs.io.req[0].bits.uop.ldq_idx, s2_req[0].uop.ldq_idx
connect mshrs.io.req[0].bits.uop.rob_idx, s2_req[0].uop.rob_idx
connect mshrs.io.req[0].bits.uop.csr_addr, s2_req[0].uop.csr_addr
connect mshrs.io.req[0].bits.uop.imm_packed, s2_req[0].uop.imm_packed
connect mshrs.io.req[0].bits.uop.taken, s2_req[0].uop.taken
connect mshrs.io.req[0].bits.uop.pc_lob, s2_req[0].uop.pc_lob
connect mshrs.io.req[0].bits.uop.edge_inst, s2_req[0].uop.edge_inst
connect mshrs.io.req[0].bits.uop.ftq_idx, s2_req[0].uop.ftq_idx
connect mshrs.io.req[0].bits.uop.br_tag, s2_req[0].uop.br_tag
connect mshrs.io.req[0].bits.uop.br_mask, s2_req[0].uop.br_mask
connect mshrs.io.req[0].bits.uop.is_sfb, s2_req[0].uop.is_sfb
connect mshrs.io.req[0].bits.uop.is_jal, s2_req[0].uop.is_jal
connect mshrs.io.req[0].bits.uop.is_jalr, s2_req[0].uop.is_jalr
connect mshrs.io.req[0].bits.uop.is_br, s2_req[0].uop.is_br
connect mshrs.io.req[0].bits.uop.iw_p2_poisoned, s2_req[0].uop.iw_p2_poisoned
connect mshrs.io.req[0].bits.uop.iw_p1_poisoned, s2_req[0].uop.iw_p1_poisoned
connect mshrs.io.req[0].bits.uop.iw_state, s2_req[0].uop.iw_state
connect mshrs.io.req[0].bits.uop.ctrl.is_std, s2_req[0].uop.ctrl.is_std
connect mshrs.io.req[0].bits.uop.ctrl.is_sta, s2_req[0].uop.ctrl.is_sta
connect mshrs.io.req[0].bits.uop.ctrl.is_load, s2_req[0].uop.ctrl.is_load
connect mshrs.io.req[0].bits.uop.ctrl.csr_cmd, s2_req[0].uop.ctrl.csr_cmd
connect mshrs.io.req[0].bits.uop.ctrl.fcn_dw, s2_req[0].uop.ctrl.fcn_dw
connect mshrs.io.req[0].bits.uop.ctrl.op_fcn, s2_req[0].uop.ctrl.op_fcn
connect mshrs.io.req[0].bits.uop.ctrl.imm_sel, s2_req[0].uop.ctrl.imm_sel
connect mshrs.io.req[0].bits.uop.ctrl.op2_sel, s2_req[0].uop.ctrl.op2_sel
connect mshrs.io.req[0].bits.uop.ctrl.op1_sel, s2_req[0].uop.ctrl.op1_sel
connect mshrs.io.req[0].bits.uop.ctrl.br_type, s2_req[0].uop.ctrl.br_type
connect mshrs.io.req[0].bits.uop.fu_code, s2_req[0].uop.fu_code
connect mshrs.io.req[0].bits.uop.iq_type, s2_req[0].uop.iq_type
connect mshrs.io.req[0].bits.uop.debug_pc, s2_req[0].uop.debug_pc
connect mshrs.io.req[0].bits.uop.is_rvc, s2_req[0].uop.is_rvc
connect mshrs.io.req[0].bits.uop.debug_inst, s2_req[0].uop.debug_inst
connect mshrs.io.req[0].bits.uop.inst, s2_req[0].uop.inst
connect mshrs.io.req[0].bits.uop.uopc, s2_req[0].uop.uopc
node _mshrs_io_req_0_bits_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _mshrs_io_req_0_bits_uop_br_mask_T_1 = and(s2_req[0].uop.br_mask, _mshrs_io_req_0_bits_uop_br_mask_T)
connect mshrs.io.req[0].bits.uop.br_mask, _mshrs_io_req_0_bits_uop_br_mask_T_1
connect mshrs.io.req[0].bits.addr, s2_req[0].addr
connect mshrs.io.req[0].bits.tag_match, s2_tag_match_0
wire mshrs_io_req_0_bits_old_meta_meta : { coh : { state : UInt<2>}, tag : UInt<20>}
connect mshrs_io_req_0_bits_old_meta_meta.tag, s2_repl_meta[0].tag
connect mshrs_io_req_0_bits_old_meta_meta.coh, s2_hit_state[0]
node _mshrs_io_req_0_bits_old_meta_T = mux(s2_tag_match_0, mshrs_io_req_0_bits_old_meta_meta, s2_repl_meta[0])
connect mshrs.io.req[0].bits.old_meta.tag, _mshrs_io_req_0_bits_old_meta_T.tag
connect mshrs.io.req[0].bits.old_meta.coh.state, _mshrs_io_req_0_bits_old_meta_T.coh.state
node _mshrs_io_req_0_bits_way_en_T = mux(s2_tag_match_0, s2_tag_match_way[0], s2_replaced_way_en)
connect mshrs.io.req[0].bits.way_en, _mshrs_io_req_0_bits_way_en_T
connect mshrs.io.req[0].bits.data, s2_req[0].data
connect mshrs.io.req[0].bits.is_hella, s2_req[0].is_hella
node _mshrs_io_req_is_probe_0_T = eq(s2_type, UInt<3>(0h1))
node _mshrs_io_req_is_probe_0_T_1 = and(_mshrs_io_req_is_probe_0_T, s2_valid[0])
connect mshrs.io.req_is_probe[0], _mshrs_io_req_is_probe_0_T_1
node _mshrs_io_meta_resp_valid_T = eq(s2_nack_hit[0], UInt<1>(0h0))
node _mshrs_io_meta_resp_valid_T_1 = or(_mshrs_io_meta_resp_valid_T, prober.io.mshr_wb_rdy)
connect mshrs.io.meta_resp.valid, _mshrs_io_meta_resp_valid_T_1
reg mshrs_io_meta_resp_bits_REG : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock
connect mshrs_io_meta_resp_bits_REG, meta_0.io.resp
node _mshrs_io_meta_resp_bits_T = bits(s2_tag_match_way[0], 0, 0)
node _mshrs_io_meta_resp_bits_T_1 = bits(s2_tag_match_way[0], 1, 1)
node _mshrs_io_meta_resp_bits_T_2 = bits(s2_tag_match_way[0], 2, 2)
node _mshrs_io_meta_resp_bits_T_3 = bits(s2_tag_match_way[0], 3, 3)
wire _mshrs_io_meta_resp_bits_WIRE : { coh : { state : UInt<2>}, tag : UInt<20>}
node _mshrs_io_meta_resp_bits_T_4 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_5 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_6 = mux(_mshrs_io_meta_resp_bits_T_2, mshrs_io_meta_resp_bits_REG[2].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_7 = mux(_mshrs_io_meta_resp_bits_T_3, mshrs_io_meta_resp_bits_REG[3].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_8 = or(_mshrs_io_meta_resp_bits_T_4, _mshrs_io_meta_resp_bits_T_5)
node _mshrs_io_meta_resp_bits_T_9 = or(_mshrs_io_meta_resp_bits_T_8, _mshrs_io_meta_resp_bits_T_6)
node _mshrs_io_meta_resp_bits_T_10 = or(_mshrs_io_meta_resp_bits_T_9, _mshrs_io_meta_resp_bits_T_7)
wire _mshrs_io_meta_resp_bits_WIRE_1 : UInt<20>
connect _mshrs_io_meta_resp_bits_WIRE_1, _mshrs_io_meta_resp_bits_T_10
connect _mshrs_io_meta_resp_bits_WIRE.tag, _mshrs_io_meta_resp_bits_WIRE_1
wire _mshrs_io_meta_resp_bits_WIRE_2 : { state : UInt<2>}
node _mshrs_io_meta_resp_bits_T_11 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_12 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_13 = mux(_mshrs_io_meta_resp_bits_T_2, mshrs_io_meta_resp_bits_REG[2].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_14 = mux(_mshrs_io_meta_resp_bits_T_3, mshrs_io_meta_resp_bits_REG[3].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_15 = or(_mshrs_io_meta_resp_bits_T_11, _mshrs_io_meta_resp_bits_T_12)
node _mshrs_io_meta_resp_bits_T_16 = or(_mshrs_io_meta_resp_bits_T_15, _mshrs_io_meta_resp_bits_T_13)
node _mshrs_io_meta_resp_bits_T_17 = or(_mshrs_io_meta_resp_bits_T_16, _mshrs_io_meta_resp_bits_T_14)
wire _mshrs_io_meta_resp_bits_WIRE_3 : UInt<2>
connect _mshrs_io_meta_resp_bits_WIRE_3, _mshrs_io_meta_resp_bits_T_17
connect _mshrs_io_meta_resp_bits_WIRE_2.state, _mshrs_io_meta_resp_bits_WIRE_3
connect _mshrs_io_meta_resp_bits_WIRE.coh, _mshrs_io_meta_resp_bits_WIRE_2
connect mshrs.io.meta_resp.bits.tag, _mshrs_io_meta_resp_bits_WIRE.tag
connect mshrs.io.meta_resp.bits.coh.state, _mshrs_io_meta_resp_bits_WIRE.coh.state
node _T_73 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid)
when _T_73 :
connect replace, UInt<1>(0h1)
connect nodeOut.a.bits, mshrs.io.mem_acquire.bits
connect nodeOut.a.valid, mshrs.io.mem_acquire.valid
connect mshrs.io.mem_acquire.ready, nodeOut.a.ready
node _prober_io_req_valid_T = eq(lrsc_valid, UInt<1>(0h0))
node _prober_io_req_valid_T_1 = and(nodeOut.b.valid, _prober_io_req_valid_T)
connect prober.io.req.valid, _prober_io_req_valid_T_1
node _nodeOut_b_ready_T = eq(lrsc_valid, UInt<1>(0h0))
node _nodeOut_b_ready_T_1 = and(prober.io.req.ready, _nodeOut_b_ready_T)
connect nodeOut.b.ready, _nodeOut_b_ready_T_1
connect prober.io.req.bits.corrupt, nodeOut.b.bits.corrupt
connect prober.io.req.bits.data, nodeOut.b.bits.data
connect prober.io.req.bits.mask, nodeOut.b.bits.mask
connect prober.io.req.bits.address, nodeOut.b.bits.address
connect prober.io.req.bits.source, nodeOut.b.bits.source
connect prober.io.req.bits.size, nodeOut.b.bits.size
connect prober.io.req.bits.param, nodeOut.b.bits.param
connect prober.io.req.bits.opcode, nodeOut.b.bits.opcode
connect prober.io.way_en, s2_tag_match_way[0]
connect prober.io.block_state.state, s2_hit_state[0].state
connect metaWriteArb.io.in[1], prober.io.meta_write
connect prober.io.mshr_rdy, mshrs.io.probe_rdy
node _prober_io_wb_rdy_T = neq(prober.io.meta_write.bits.idx, wb.io.idx.bits)
node _prober_io_wb_rdy_T_1 = eq(wb.io.idx.valid, UInt<1>(0h0))
node _prober_io_wb_rdy_T_2 = or(_prober_io_wb_rdy_T, _prober_io_wb_rdy_T_1)
connect prober.io.wb_rdy, _prober_io_wb_rdy_T_2
connect mshrs.io.prober_state.bits, prober.io.state.bits
connect mshrs.io.prober_state.valid, prober.io.state.valid
node _T_74 = eq(nodeOut.d.bits.source, UInt<2>(0h2))
when _T_74 :
connect nodeOut.d.ready, UInt<1>(0h1)
connect mshrs.io.mem_grant.valid, UInt<1>(0h0)
invalidate mshrs.io.mem_grant.bits.corrupt
invalidate mshrs.io.mem_grant.bits.data
invalidate mshrs.io.mem_grant.bits.denied
invalidate mshrs.io.mem_grant.bits.sink
invalidate mshrs.io.mem_grant.bits.source
invalidate mshrs.io.mem_grant.bits.size
invalidate mshrs.io.mem_grant.bits.param
invalidate mshrs.io.mem_grant.bits.opcode
else :
connect mshrs.io.mem_grant, nodeOut.d
connect dataWriteArb.io.in[1], mshrs.io.refill
connect metaWriteArb.io.in[0], mshrs.io.meta_write
connect nodeOut.e.bits, mshrs.io.mem_finish.bits
connect nodeOut.e.valid, mshrs.io.mem_finish.valid
connect mshrs.io.mem_finish.ready, nodeOut.e.ready
inst wbArb of Arbiter2_WritebackReq_3
connect wbArb.clock, clock
connect wbArb.reset, reset
connect wbArb.io.in[0], prober.io.wb_req
connect wbArb.io.in[1], mshrs.io.wb_req
connect wb.io.req, wbArb.io.out
connect wb.io.data_resp, s2_data_muxed[0]
connect mshrs.io.wb_resp, wb.io.resp
node _wb_io_mem_grant_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _wb_io_mem_grant_T_1 = eq(nodeOut.d.bits.source, UInt<2>(0h2))
node _wb_io_mem_grant_T_2 = and(_wb_io_mem_grant_T, _wb_io_mem_grant_T_1)
connect wb.io.mem_grant, _wb_io_mem_grant_T_2
inst lsu_release_arb of Arbiter2_TLBundleC_a32d64s2k3z4c_1
connect lsu_release_arb.clock, clock
connect lsu_release_arb.reset, reset
connect io.lsu.release.bits, lsu_release_arb.io.out.bits
connect io.lsu.release.valid, lsu_release_arb.io.out.valid
connect lsu_release_arb.io.out.ready, io.lsu.release.ready
connect lsu_release_arb.io.in[0], wb.io.lsu_release
connect lsu_release_arb.io.in[1], prober.io.lsu_release
node _decode_T = dshl(UInt<12>(0hfff), wb.io.release.bits.size)
node _decode_T_1 = bits(_decode_T, 11, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node opdata = bits(wb.io.release.bits.opcode, 0, 0)
node _T_75 = mux(opdata, decode, UInt<1>(0h0))
node _decode_T_3 = dshl(UInt<12>(0hfff), prober.io.rep.bits.size)
node _decode_T_4 = bits(_decode_T_3, 11, 0)
node _decode_T_5 = not(_decode_T_4)
node decode_1 = shr(_decode_T_5, 3)
node opdata_1 = bits(prober.io.rep.bits.opcode, 0, 0)
node _T_76 = mux(opdata_1, decode_1, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.c.ready)
node _readys_T = cat(prober.io.rep.valid, wb.io.release.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], wb.io.release.valid)
node _winner_T_1 = and(readys[1], prober.io.rep.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_77 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_78 = eq(winner[0], UInt<1>(0h0))
node _T_79 = or(_T_77, _T_78)
node _T_80 = eq(prefixOR_1, UInt<1>(0h0))
node _T_81 = eq(winner[1], UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
node _T_83 = and(_T_79, _T_82)
node _T_84 = asUInt(reset)
node _T_85 = eq(_T_84, UInt<1>(0h0))
when _T_85 :
node _T_86 = eq(_T_83, UInt<1>(0h0))
when _T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_7
assert(clock, _T_83, UInt<1>(0h1), "") : assert_7
node _T_87 = or(wb.io.release.valid, prober.io.rep.valid)
node _T_88 = eq(_T_87, UInt<1>(0h0))
node _T_89 = or(winner[0], winner[1])
node _T_90 = or(_T_88, _T_89)
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_8
assert(clock, _T_90, UInt<1>(0h1), "") : assert_8
node maskedBeats_0 = mux(winner[0], _T_75, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_76, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _wb_io_release_ready_T = and(nodeOut.c.ready, allowed[0])
connect wb.io.release.ready, _wb_io_release_ready_T
node _prober_io_rep_ready_T = and(nodeOut.c.ready, allowed[1])
connect prober.io.rep.ready, _prober_io_rep_ready_T
node _nodeOut_c_valid_T = or(wb.io.release.valid, prober.io.rep.valid)
node _nodeOut_c_valid_T_1 = mux(state[0], wb.io.release.valid, UInt<1>(0h0))
node _nodeOut_c_valid_T_2 = mux(state[1], prober.io.rep.valid, UInt<1>(0h0))
node _nodeOut_c_valid_T_3 = or(_nodeOut_c_valid_T_1, _nodeOut_c_valid_T_2)
wire _nodeOut_c_valid_WIRE : UInt<1>
connect _nodeOut_c_valid_WIRE, _nodeOut_c_valid_T_3
node _nodeOut_c_valid_T_4 = mux(idle, _nodeOut_c_valid_T, _nodeOut_c_valid_WIRE)
connect nodeOut.c.valid, _nodeOut_c_valid_T_4
wire _nodeOut_c_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_c_bits_T = mux(muxState[0], wb.io.release.bits.corrupt, UInt<1>(0h0))
node _nodeOut_c_bits_T_1 = mux(muxState[1], prober.io.rep.bits.corrupt, UInt<1>(0h0))
node _nodeOut_c_bits_T_2 = or(_nodeOut_c_bits_T, _nodeOut_c_bits_T_1)
wire _nodeOut_c_bits_WIRE_1 : UInt<1>
connect _nodeOut_c_bits_WIRE_1, _nodeOut_c_bits_T_2
connect _nodeOut_c_bits_WIRE.corrupt, _nodeOut_c_bits_WIRE_1
node _nodeOut_c_bits_T_3 = mux(muxState[0], wb.io.release.bits.data, UInt<1>(0h0))
node _nodeOut_c_bits_T_4 = mux(muxState[1], prober.io.rep.bits.data, UInt<1>(0h0))
node _nodeOut_c_bits_T_5 = or(_nodeOut_c_bits_T_3, _nodeOut_c_bits_T_4)
wire _nodeOut_c_bits_WIRE_2 : UInt<64>
connect _nodeOut_c_bits_WIRE_2, _nodeOut_c_bits_T_5
connect _nodeOut_c_bits_WIRE.data, _nodeOut_c_bits_WIRE_2
wire _nodeOut_c_bits_WIRE_3 : { }
connect _nodeOut_c_bits_WIRE.echo, _nodeOut_c_bits_WIRE_3
wire _nodeOut_c_bits_WIRE_4 : { }
connect _nodeOut_c_bits_WIRE.user, _nodeOut_c_bits_WIRE_4
node _nodeOut_c_bits_T_6 = mux(muxState[0], wb.io.release.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_T_7 = mux(muxState[1], prober.io.rep.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_T_8 = or(_nodeOut_c_bits_T_6, _nodeOut_c_bits_T_7)
wire _nodeOut_c_bits_WIRE_5 : UInt<32>
connect _nodeOut_c_bits_WIRE_5, _nodeOut_c_bits_T_8
connect _nodeOut_c_bits_WIRE.address, _nodeOut_c_bits_WIRE_5
node _nodeOut_c_bits_T_9 = mux(muxState[0], wb.io.release.bits.source, UInt<1>(0h0))
node _nodeOut_c_bits_T_10 = mux(muxState[1], prober.io.rep.bits.source, UInt<1>(0h0))
node _nodeOut_c_bits_T_11 = or(_nodeOut_c_bits_T_9, _nodeOut_c_bits_T_10)
wire _nodeOut_c_bits_WIRE_6 : UInt<2>
connect _nodeOut_c_bits_WIRE_6, _nodeOut_c_bits_T_11
connect _nodeOut_c_bits_WIRE.source, _nodeOut_c_bits_WIRE_6
node _nodeOut_c_bits_T_12 = mux(muxState[0], wb.io.release.bits.size, UInt<1>(0h0))
node _nodeOut_c_bits_T_13 = mux(muxState[1], prober.io.rep.bits.size, UInt<1>(0h0))
node _nodeOut_c_bits_T_14 = or(_nodeOut_c_bits_T_12, _nodeOut_c_bits_T_13)
wire _nodeOut_c_bits_WIRE_7 : UInt<4>
connect _nodeOut_c_bits_WIRE_7, _nodeOut_c_bits_T_14
connect _nodeOut_c_bits_WIRE.size, _nodeOut_c_bits_WIRE_7
node _nodeOut_c_bits_T_15 = mux(muxState[0], wb.io.release.bits.param, UInt<1>(0h0))
node _nodeOut_c_bits_T_16 = mux(muxState[1], prober.io.rep.bits.param, UInt<1>(0h0))
node _nodeOut_c_bits_T_17 = or(_nodeOut_c_bits_T_15, _nodeOut_c_bits_T_16)
wire _nodeOut_c_bits_WIRE_8 : UInt<3>
connect _nodeOut_c_bits_WIRE_8, _nodeOut_c_bits_T_17
connect _nodeOut_c_bits_WIRE.param, _nodeOut_c_bits_WIRE_8
node _nodeOut_c_bits_T_18 = mux(muxState[0], wb.io.release.bits.opcode, UInt<1>(0h0))
node _nodeOut_c_bits_T_19 = mux(muxState[1], prober.io.rep.bits.opcode, UInt<1>(0h0))
node _nodeOut_c_bits_T_20 = or(_nodeOut_c_bits_T_18, _nodeOut_c_bits_T_19)
wire _nodeOut_c_bits_WIRE_9 : UInt<3>
connect _nodeOut_c_bits_WIRE_9, _nodeOut_c_bits_T_20
connect _nodeOut_c_bits_WIRE.opcode, _nodeOut_c_bits_WIRE_9
connect nodeOut.c.bits.corrupt, _nodeOut_c_bits_WIRE.corrupt
connect nodeOut.c.bits.data, _nodeOut_c_bits_WIRE.data
connect nodeOut.c.bits.address, _nodeOut_c_bits_WIRE.address
connect nodeOut.c.bits.source, _nodeOut_c_bits_WIRE.source
connect nodeOut.c.bits.size, _nodeOut_c_bits_WIRE.size
connect nodeOut.c.bits.param, _nodeOut_c_bits_WIRE.param
connect nodeOut.c.bits.opcode, _nodeOut_c_bits_WIRE.opcode
node _io_lsu_perf_release_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _io_lsu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.c.bits.size)
node _io_lsu_perf_release_beats1_decode_T_1 = bits(_io_lsu_perf_release_beats1_decode_T, 11, 0)
node _io_lsu_perf_release_beats1_decode_T_2 = not(_io_lsu_perf_release_beats1_decode_T_1)
node io_lsu_perf_release_beats1_decode = shr(_io_lsu_perf_release_beats1_decode_T_2, 3)
node io_lsu_perf_release_beats1_opdata = bits(nodeOut.c.bits.opcode, 0, 0)
node io_lsu_perf_release_beats1 = mux(io_lsu_perf_release_beats1_opdata, io_lsu_perf_release_beats1_decode, UInt<1>(0h0))
regreset io_lsu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_lsu_perf_release_counter1_T = sub(io_lsu_perf_release_counter, UInt<1>(0h1))
node io_lsu_perf_release_counter1 = tail(_io_lsu_perf_release_counter1_T, 1)
node io_lsu_perf_release_first = eq(io_lsu_perf_release_counter, UInt<1>(0h0))
node _io_lsu_perf_release_last_T = eq(io_lsu_perf_release_counter, UInt<1>(0h1))
node _io_lsu_perf_release_last_T_1 = eq(io_lsu_perf_release_beats1, UInt<1>(0h0))
node io_lsu_perf_release_last = or(_io_lsu_perf_release_last_T, _io_lsu_perf_release_last_T_1)
node io_lsu_perf_release_done = and(io_lsu_perf_release_last, _io_lsu_perf_release_T)
node _io_lsu_perf_release_count_T = not(io_lsu_perf_release_counter1)
node io_lsu_perf_release_count = and(io_lsu_perf_release_beats1, _io_lsu_perf_release_count_T)
when _io_lsu_perf_release_T :
node _io_lsu_perf_release_counter_T = mux(io_lsu_perf_release_first, io_lsu_perf_release_beats1, io_lsu_perf_release_counter1)
connect io_lsu_perf_release_counter, _io_lsu_perf_release_counter_T
connect io.lsu.perf.release, io_lsu_perf_release_done
node _io_lsu_perf_acquire_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _io_lsu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.a.bits.size)
node _io_lsu_perf_acquire_beats1_decode_T_1 = bits(_io_lsu_perf_acquire_beats1_decode_T, 11, 0)
node _io_lsu_perf_acquire_beats1_decode_T_2 = not(_io_lsu_perf_acquire_beats1_decode_T_1)
node io_lsu_perf_acquire_beats1_decode = shr(_io_lsu_perf_acquire_beats1_decode_T_2, 3)
node _io_lsu_perf_acquire_beats1_opdata_T = bits(nodeOut.a.bits.opcode, 2, 2)
node io_lsu_perf_acquire_beats1_opdata = eq(_io_lsu_perf_acquire_beats1_opdata_T, UInt<1>(0h0))
node io_lsu_perf_acquire_beats1 = mux(io_lsu_perf_acquire_beats1_opdata, io_lsu_perf_acquire_beats1_decode, UInt<1>(0h0))
regreset io_lsu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_lsu_perf_acquire_counter1_T = sub(io_lsu_perf_acquire_counter, UInt<1>(0h1))
node io_lsu_perf_acquire_counter1 = tail(_io_lsu_perf_acquire_counter1_T, 1)
node io_lsu_perf_acquire_first = eq(io_lsu_perf_acquire_counter, UInt<1>(0h0))
node _io_lsu_perf_acquire_last_T = eq(io_lsu_perf_acquire_counter, UInt<1>(0h1))
node _io_lsu_perf_acquire_last_T_1 = eq(io_lsu_perf_acquire_beats1, UInt<1>(0h0))
node io_lsu_perf_acquire_last = or(_io_lsu_perf_acquire_last_T, _io_lsu_perf_acquire_last_T_1)
node io_lsu_perf_acquire_done = and(io_lsu_perf_acquire_last, _io_lsu_perf_acquire_T)
node _io_lsu_perf_acquire_count_T = not(io_lsu_perf_acquire_counter1)
node io_lsu_perf_acquire_count = and(io_lsu_perf_acquire_beats1, _io_lsu_perf_acquire_count_T)
when _io_lsu_perf_acquire_T :
node _io_lsu_perf_acquire_counter_T = mux(io_lsu_perf_acquire_first, io_lsu_perf_acquire_beats1, io_lsu_perf_acquire_counter1)
connect io_lsu_perf_acquire_counter, _io_lsu_perf_acquire_counter_T
connect io.lsu.perf.acquire, io_lsu_perf_acquire_done
node _s2_data_word_prebypass_T = cat(s2_word_idx[0], UInt<6>(0h0))
node _s2_data_word_prebypass_T_1 = dshr(s2_data_muxed[0], _s2_data_word_prebypass_T)
wire s2_data_word_prebypass : UInt<64>[1]
connect s2_data_word_prebypass[0], _s2_data_word_prebypass_T_1
wire s2_data_word : UInt[1]
node _T_94 = and(s2_sc, UInt<1>(0h1))
wire size : UInt<2>
connect size, s2_req[0].uop.mem_size
node size_dat_padded = pad(s2_data_word[0], 64)
wire cache_resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1]
node _cache_resp_0_valid_T = and(s2_valid[0], s2_send_resp[0])
connect cache_resp[0].valid, _cache_resp_0_valid_T
connect cache_resp[0].bits.uop, s2_req[0].uop
node _cache_resp_0_bits_data_shifted_T = bits(s2_req[0].addr, 2, 2)
node _cache_resp_0_bits_data_shifted_T_1 = bits(s2_data_word[0], 63, 32)
node _cache_resp_0_bits_data_shifted_T_2 = bits(s2_data_word[0], 31, 0)
node cache_resp_0_bits_data_shifted = mux(_cache_resp_0_bits_data_shifted_T, _cache_resp_0_bits_data_shifted_T_1, _cache_resp_0_bits_data_shifted_T_2)
node cache_resp_0_bits_data_doZero = and(UInt<1>(0h0), _T_94)
node cache_resp_0_bits_data_zeroed = mux(cache_resp_0_bits_data_doZero, UInt<1>(0h0), cache_resp_0_bits_data_shifted)
node _cache_resp_0_bits_data_T = eq(size, UInt<2>(0h2))
node _cache_resp_0_bits_data_T_1 = or(_cache_resp_0_bits_data_T, cache_resp_0_bits_data_doZero)
node _cache_resp_0_bits_data_T_2 = bits(cache_resp_0_bits_data_zeroed, 31, 31)
node _cache_resp_0_bits_data_T_3 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_2)
node _cache_resp_0_bits_data_T_4 = mux(_cache_resp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _cache_resp_0_bits_data_T_5 = bits(s2_data_word[0], 63, 32)
node _cache_resp_0_bits_data_T_6 = mux(_cache_resp_0_bits_data_T_1, _cache_resp_0_bits_data_T_4, _cache_resp_0_bits_data_T_5)
node _cache_resp_0_bits_data_T_7 = cat(_cache_resp_0_bits_data_T_6, cache_resp_0_bits_data_zeroed)
node _cache_resp_0_bits_data_shifted_T_3 = bits(s2_req[0].addr, 1, 1)
node _cache_resp_0_bits_data_shifted_T_4 = bits(_cache_resp_0_bits_data_T_7, 31, 16)
node _cache_resp_0_bits_data_shifted_T_5 = bits(_cache_resp_0_bits_data_T_7, 15, 0)
node cache_resp_0_bits_data_shifted_1 = mux(_cache_resp_0_bits_data_shifted_T_3, _cache_resp_0_bits_data_shifted_T_4, _cache_resp_0_bits_data_shifted_T_5)
node cache_resp_0_bits_data_doZero_1 = and(UInt<1>(0h0), _T_94)
node cache_resp_0_bits_data_zeroed_1 = mux(cache_resp_0_bits_data_doZero_1, UInt<1>(0h0), cache_resp_0_bits_data_shifted_1)
node _cache_resp_0_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _cache_resp_0_bits_data_T_9 = or(_cache_resp_0_bits_data_T_8, cache_resp_0_bits_data_doZero_1)
node _cache_resp_0_bits_data_T_10 = bits(cache_resp_0_bits_data_zeroed_1, 15, 15)
node _cache_resp_0_bits_data_T_11 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_10)
node _cache_resp_0_bits_data_T_12 = mux(_cache_resp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _cache_resp_0_bits_data_T_13 = bits(_cache_resp_0_bits_data_T_7, 63, 16)
node _cache_resp_0_bits_data_T_14 = mux(_cache_resp_0_bits_data_T_9, _cache_resp_0_bits_data_T_12, _cache_resp_0_bits_data_T_13)
node _cache_resp_0_bits_data_T_15 = cat(_cache_resp_0_bits_data_T_14, cache_resp_0_bits_data_zeroed_1)
node _cache_resp_0_bits_data_shifted_T_6 = bits(s2_req[0].addr, 0, 0)
node _cache_resp_0_bits_data_shifted_T_7 = bits(_cache_resp_0_bits_data_T_15, 15, 8)
node _cache_resp_0_bits_data_shifted_T_8 = bits(_cache_resp_0_bits_data_T_15, 7, 0)
node cache_resp_0_bits_data_shifted_2 = mux(_cache_resp_0_bits_data_shifted_T_6, _cache_resp_0_bits_data_shifted_T_7, _cache_resp_0_bits_data_shifted_T_8)
node cache_resp_0_bits_data_doZero_2 = and(UInt<1>(0h1), _T_94)
node cache_resp_0_bits_data_zeroed_2 = mux(cache_resp_0_bits_data_doZero_2, UInt<1>(0h0), cache_resp_0_bits_data_shifted_2)
node _cache_resp_0_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _cache_resp_0_bits_data_T_17 = or(_cache_resp_0_bits_data_T_16, cache_resp_0_bits_data_doZero_2)
node _cache_resp_0_bits_data_T_18 = bits(cache_resp_0_bits_data_zeroed_2, 7, 7)
node _cache_resp_0_bits_data_T_19 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_18)
node _cache_resp_0_bits_data_T_20 = mux(_cache_resp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _cache_resp_0_bits_data_T_21 = bits(_cache_resp_0_bits_data_T_15, 63, 8)
node _cache_resp_0_bits_data_T_22 = mux(_cache_resp_0_bits_data_T_17, _cache_resp_0_bits_data_T_20, _cache_resp_0_bits_data_T_21)
node _cache_resp_0_bits_data_T_23 = cat(_cache_resp_0_bits_data_T_22, cache_resp_0_bits_data_zeroed_2)
node _cache_resp_0_bits_data_T_24 = or(_cache_resp_0_bits_data_T_23, s2_sc_fail)
connect cache_resp[0].bits.data, _cache_resp_0_bits_data_T_24
connect cache_resp[0].bits.is_hella, s2_req[0].is_hella
wire uncache_resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}
connect uncache_resp.bits, mshrs.io.resp.bits
connect uncache_resp.valid, mshrs.io.resp.valid
node _mshrs_io_resp_ready_T = eq(cache_resp[0].valid, UInt<1>(0h0))
connect mshrs.io.resp.ready, _mshrs_io_resp_ready_T
wire resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1]
connect resp, cache_resp
node _uncache_respond_T = eq(cache_resp[0].valid, UInt<1>(0h0))
node _uncache_respond_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node uncache_respond = and(_uncache_respond_T, _uncache_respond_T_1)
when uncache_respond :
connect resp[0], uncache_resp
node _T_95 = or(UInt<1>(0h0), uncache_respond)
node _io_lsu_resp_0_valid_T = and(io.lsu.exception, resp[0].bits.uop.uses_ldq)
node _io_lsu_resp_0_valid_T_1 = eq(_io_lsu_resp_0_valid_T, UInt<1>(0h0))
node _io_lsu_resp_0_valid_T_2 = and(resp[0].valid, _io_lsu_resp_0_valid_T_1)
node _io_lsu_resp_0_valid_T_3 = and(io.lsu.brupdate.b1.mispredict_mask, resp[0].bits.uop.br_mask)
node _io_lsu_resp_0_valid_T_4 = neq(_io_lsu_resp_0_valid_T_3, UInt<1>(0h0))
node _io_lsu_resp_0_valid_T_5 = eq(_io_lsu_resp_0_valid_T_4, UInt<1>(0h0))
node _io_lsu_resp_0_valid_T_6 = and(_io_lsu_resp_0_valid_T_2, _io_lsu_resp_0_valid_T_5)
connect io.lsu.resp[0].valid, _io_lsu_resp_0_valid_T_6
wire io_lsu_resp_0_bits_out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}
connect io_lsu_resp_0_bits_out, resp[0].bits
node _io_lsu_resp_0_bits_out_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _io_lsu_resp_0_bits_out_uop_br_mask_T_1 = and(resp[0].bits.uop.br_mask, _io_lsu_resp_0_bits_out_uop_br_mask_T)
connect io_lsu_resp_0_bits_out.uop.br_mask, _io_lsu_resp_0_bits_out_uop_br_mask_T_1
connect io.lsu.resp[0].bits, io_lsu_resp_0_bits_out
node _io_lsu_nack_0_valid_T = and(s2_valid[0], s2_send_nack[0])
node _io_lsu_nack_0_valid_T_1 = and(io.lsu.exception, s2_req[0].uop.uses_ldq)
node _io_lsu_nack_0_valid_T_2 = eq(_io_lsu_nack_0_valid_T_1, UInt<1>(0h0))
node _io_lsu_nack_0_valid_T_3 = and(_io_lsu_nack_0_valid_T, _io_lsu_nack_0_valid_T_2)
node _io_lsu_nack_0_valid_T_4 = and(io.lsu.brupdate.b1.mispredict_mask, s2_req[0].uop.br_mask)
node _io_lsu_nack_0_valid_T_5 = neq(_io_lsu_nack_0_valid_T_4, UInt<1>(0h0))
node _io_lsu_nack_0_valid_T_6 = eq(_io_lsu_nack_0_valid_T_5, UInt<1>(0h0))
node _io_lsu_nack_0_valid_T_7 = and(_io_lsu_nack_0_valid_T_3, _io_lsu_nack_0_valid_T_6)
connect io.lsu.nack[0].valid, _io_lsu_nack_0_valid_T_7
wire io_lsu_nack_0_bits_out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}
connect io_lsu_nack_0_bits_out, s2_req[0]
node _io_lsu_nack_0_bits_out_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _io_lsu_nack_0_bits_out_uop_br_mask_T_1 = and(s2_req[0].uop.br_mask, _io_lsu_nack_0_bits_out_uop_br_mask_T)
connect io_lsu_nack_0_bits_out.uop.br_mask, _io_lsu_nack_0_bits_out_uop_br_mask_T_1
connect io.lsu.nack[0].bits, io_lsu_nack_0_bits_out
node _T_96 = neq(s2_type, UInt<3>(0h4))
node _T_97 = and(io.lsu.nack[0].valid, _T_96)
node _T_98 = eq(_T_97, UInt<1>(0h0))
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:866 assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))\n") : printf_9
assert(clock, _T_98, UInt<1>(0h1), "") : assert_9
reg s3_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s3_req, s2_req[0]
node _s3_valid_T = and(s2_valid[0], s2_hit[0])
node _s3_valid_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s3_valid_T_2 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s3_valid_T_3 = or(_s3_valid_T_1, _s3_valid_T_2)
node _s3_valid_T_4 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s3_valid_T_5 = or(_s3_valid_T_3, _s3_valid_T_4)
node _s3_valid_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s3_valid_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s3_valid_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s3_valid_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s3_valid_T_10 = or(_s3_valid_T_6, _s3_valid_T_7)
node _s3_valid_T_11 = or(_s3_valid_T_10, _s3_valid_T_8)
node _s3_valid_T_12 = or(_s3_valid_T_11, _s3_valid_T_9)
node _s3_valid_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s3_valid_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s3_valid_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s3_valid_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s3_valid_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s3_valid_T_18 = or(_s3_valid_T_13, _s3_valid_T_14)
node _s3_valid_T_19 = or(_s3_valid_T_18, _s3_valid_T_15)
node _s3_valid_T_20 = or(_s3_valid_T_19, _s3_valid_T_16)
node _s3_valid_T_21 = or(_s3_valid_T_20, _s3_valid_T_17)
node _s3_valid_T_22 = or(_s3_valid_T_12, _s3_valid_T_21)
node _s3_valid_T_23 = or(_s3_valid_T_5, _s3_valid_T_22)
node _s3_valid_T_24 = and(_s3_valid_T, _s3_valid_T_23)
node _s3_valid_T_25 = eq(s2_sc_fail, UInt<1>(0h0))
node _s3_valid_T_26 = and(_s3_valid_T_24, _s3_valid_T_25)
node _s3_valid_T_27 = and(s2_send_nack[0], s2_nack[0])
node _s3_valid_T_28 = eq(_s3_valid_T_27, UInt<1>(0h0))
node _s3_valid_T_29 = and(_s3_valid_T_26, _s3_valid_T_28)
reg s3_valid : UInt<1>, clock
connect s3_valid, _s3_valid_T_29
reg s4_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s4_req, s3_req
reg s4_valid : UInt<1>, clock
connect s4_valid, s3_valid
reg s5_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s5_req, s4_req
reg s5_valid : UInt<1>, clock
connect s5_valid, s4_valid
node _s3_bypass_T = shr(s2_req[0].addr, 3)
node _s3_bypass_T_1 = shr(s3_req.addr, 3)
node _s3_bypass_T_2 = eq(_s3_bypass_T, _s3_bypass_T_1)
node _s3_bypass_T_3 = and(s3_valid, _s3_bypass_T_2)
wire s3_bypass : UInt<1>[1]
connect s3_bypass[0], _s3_bypass_T_3
node _s4_bypass_T = shr(s2_req[0].addr, 3)
node _s4_bypass_T_1 = shr(s4_req.addr, 3)
node _s4_bypass_T_2 = eq(_s4_bypass_T, _s4_bypass_T_1)
node _s4_bypass_T_3 = and(s4_valid, _s4_bypass_T_2)
wire s4_bypass : UInt<1>[1]
connect s4_bypass[0], _s4_bypass_T_3
node _s5_bypass_T = shr(s2_req[0].addr, 3)
node _s5_bypass_T_1 = shr(s5_req.addr, 3)
node _s5_bypass_T_2 = eq(_s5_bypass_T, _s5_bypass_T_1)
node _s5_bypass_T_3 = and(s5_valid, _s5_bypass_T_2)
wire s5_bypass : UInt<1>[1]
connect s5_bypass[0], _s5_bypass_T_3
node _s2_data_word_0_T = mux(s5_bypass[0], s5_req.data, s2_data_word_prebypass[0])
node _s2_data_word_0_T_1 = mux(s4_bypass[0], s4_req.data, _s2_data_word_0_T)
node _s2_data_word_0_T_2 = mux(s3_bypass[0], s3_req.data, _s2_data_word_0_T_1)
connect s2_data_word[0], _s2_data_word_0_T_2
inst amoalu of AMOALU_1
connect amoalu.clock, clock
connect amoalu.reset, reset
wire amoalu_io_mask_size : UInt<2>
connect amoalu_io_mask_size, s2_req[0].uop.mem_size
node _amoalu_io_mask_upper_T = bits(s2_req[0].addr, 0, 0)
node _amoalu_io_mask_upper_T_1 = mux(_amoalu_io_mask_upper_T, UInt<1>(0h1), UInt<1>(0h0))
node _amoalu_io_mask_upper_T_2 = geq(amoalu_io_mask_size, UInt<1>(0h1))
node _amoalu_io_mask_upper_T_3 = mux(_amoalu_io_mask_upper_T_2, UInt<1>(0h1), UInt<1>(0h0))
node amoalu_io_mask_upper = or(_amoalu_io_mask_upper_T_1, _amoalu_io_mask_upper_T_3)
node _amoalu_io_mask_lower_T = bits(s2_req[0].addr, 0, 0)
node amoalu_io_mask_lower = mux(_amoalu_io_mask_lower_T, UInt<1>(0h0), UInt<1>(0h1))
node _amoalu_io_mask_T = cat(amoalu_io_mask_upper, amoalu_io_mask_lower)
node _amoalu_io_mask_upper_T_4 = bits(s2_req[0].addr, 1, 1)
node _amoalu_io_mask_upper_T_5 = mux(_amoalu_io_mask_upper_T_4, _amoalu_io_mask_T, UInt<1>(0h0))
node _amoalu_io_mask_upper_T_6 = geq(amoalu_io_mask_size, UInt<2>(0h2))
node _amoalu_io_mask_upper_T_7 = mux(_amoalu_io_mask_upper_T_6, UInt<2>(0h3), UInt<1>(0h0))
node amoalu_io_mask_upper_1 = or(_amoalu_io_mask_upper_T_5, _amoalu_io_mask_upper_T_7)
node _amoalu_io_mask_lower_T_1 = bits(s2_req[0].addr, 1, 1)
node amoalu_io_mask_lower_1 = mux(_amoalu_io_mask_lower_T_1, UInt<1>(0h0), _amoalu_io_mask_T)
node _amoalu_io_mask_T_1 = cat(amoalu_io_mask_upper_1, amoalu_io_mask_lower_1)
node _amoalu_io_mask_upper_T_8 = bits(s2_req[0].addr, 2, 2)
node _amoalu_io_mask_upper_T_9 = mux(_amoalu_io_mask_upper_T_8, _amoalu_io_mask_T_1, UInt<1>(0h0))
node _amoalu_io_mask_upper_T_10 = geq(amoalu_io_mask_size, UInt<2>(0h3))
node _amoalu_io_mask_upper_T_11 = mux(_amoalu_io_mask_upper_T_10, UInt<4>(0hf), UInt<1>(0h0))
node amoalu_io_mask_upper_2 = or(_amoalu_io_mask_upper_T_9, _amoalu_io_mask_upper_T_11)
node _amoalu_io_mask_lower_T_2 = bits(s2_req[0].addr, 2, 2)
node amoalu_io_mask_lower_2 = mux(_amoalu_io_mask_lower_T_2, UInt<1>(0h0), _amoalu_io_mask_T_1)
node _amoalu_io_mask_T_2 = cat(amoalu_io_mask_upper_2, amoalu_io_mask_lower_2)
connect amoalu.io.mask, _amoalu_io_mask_T_2
connect amoalu.io.cmd, s2_req[0].uop.mem_cmd
connect amoalu.io.lhs, s2_data_word[0]
connect amoalu.io.rhs, s2_req[0].data
connect s3_req.data, amoalu.io.out
reg s3_way : UInt, clock
connect s3_way, s2_tag_match_way[0]
connect dataWriteArb.io.in[0].valid, s3_valid
connect dataWriteArb.io.in[0].bits.addr, s3_req.addr
node _dataWriteArb_io_in_0_bits_wmask_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect dataWriteArb.io.in[0].bits.wmask, _dataWriteArb_io_in_0_bits_wmask_T
connect dataWriteArb.io.in[0].bits.data, s3_req.data
connect dataWriteArb.io.in[0].bits.way_en, s3_way
node _io_lsu_ordered_T = eq(s1_valid[0], UInt<1>(0h0))
node _io_lsu_ordered_T_1 = and(mshrs.io.fence_rdy, _io_lsu_ordered_T)
node _io_lsu_ordered_T_2 = eq(s2_valid[0], UInt<1>(0h0))
node _io_lsu_ordered_T_3 = and(_io_lsu_ordered_T_1, _io_lsu_ordered_T_2)
connect io.lsu.ordered, _io_lsu_ordered_T_3 | module BoomNonBlockingDCache_1( // @[dcache.scala:413:7]
input clock, // @[dcache.scala:413:7]
input reset, // @[dcache.scala:413:7]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output io_lsu_req_ready, // @[dcache.scala:419:14]
input io_lsu_req_valid, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_valid, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_uopc, // @[dcache.scala:419:14]
input [31:0] io_lsu_req_bits_0_bits_uop_inst, // @[dcache.scala:419:14]
input [31:0] io_lsu_req_bits_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
input [39:0] io_lsu_req_bits_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_iq_type, // @[dcache.scala:419:14]
input [9:0] io_lsu_req_bits_0_bits_uop_fu_code, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_iw_state, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_br, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_jal, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
input [7:0] io_lsu_req_bits_0_bits_uop_br_mask, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_br_tag, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_taken, // @[dcache.scala:419:14]
input [19:0] io_lsu_req_bits_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
input [11:0] io_lsu_req_bits_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_pdst, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_prs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_prs2, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_prs3, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ppred, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_exception, // @[dcache.scala:419:14]
input [63:0] io_lsu_req_bits_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bypassable, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_mem_size, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_fence, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_amo, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_unique, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_ldst, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs2, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs3, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_fp_val, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_fp_single, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
input [39:0] io_lsu_req_bits_0_bits_addr, // @[dcache.scala:419:14]
input [63:0] io_lsu_req_bits_0_bits_data, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_is_hella, // @[dcache.scala:419:14]
input io_lsu_s1_kill_0, // @[dcache.scala:419:14]
output io_lsu_resp_0_valid, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_uopc, // @[dcache.scala:419:14]
output [31:0] io_lsu_resp_0_bits_uop_inst, // @[dcache.scala:419:14]
output [31:0] io_lsu_resp_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
output [39:0] io_lsu_resp_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_iq_type, // @[dcache.scala:419:14]
output [9:0] io_lsu_resp_0_bits_uop_fu_code, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_iw_state, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_br, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_jal, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
output [7:0] io_lsu_resp_0_bits_uop_br_mask, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_br_tag, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_taken, // @[dcache.scala:419:14]
output [19:0] io_lsu_resp_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
output [11:0] io_lsu_resp_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_pdst, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_prs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_prs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_prs3, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ppred, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_exception, // @[dcache.scala:419:14]
output [63:0] io_lsu_resp_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bypassable, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_mem_size, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_fence, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_amo, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_unique, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_ldst, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs3, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_fp_val, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_fp_single, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
output [63:0] io_lsu_resp_0_bits_data, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_is_hella, // @[dcache.scala:419:14]
output io_lsu_nack_0_valid, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_uopc, // @[dcache.scala:419:14]
output [31:0] io_lsu_nack_0_bits_uop_inst, // @[dcache.scala:419:14]
output [31:0] io_lsu_nack_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
output [39:0] io_lsu_nack_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_iq_type, // @[dcache.scala:419:14]
output [9:0] io_lsu_nack_0_bits_uop_fu_code, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_iw_state, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_br, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_jal, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
output [7:0] io_lsu_nack_0_bits_uop_br_mask, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_br_tag, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_taken, // @[dcache.scala:419:14]
output [19:0] io_lsu_nack_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
output [11:0] io_lsu_nack_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_pdst, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_prs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_prs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_prs3, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ppred, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_exception, // @[dcache.scala:419:14]
output [63:0] io_lsu_nack_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bypassable, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_mem_size, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_fence, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_amo, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_unique, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_ldst, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs3, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_fp_val, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_fp_single, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
output [39:0] io_lsu_nack_0_bits_addr, // @[dcache.scala:419:14]
output [63:0] io_lsu_nack_0_bits_data, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_is_hella, // @[dcache.scala:419:14]
input [7:0] io_lsu_brupdate_b1_resolve_mask, // @[dcache.scala:419:14]
input [7:0] io_lsu_brupdate_b1_mispredict_mask, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_uopc, // @[dcache.scala:419:14]
input [31:0] io_lsu_brupdate_b2_uop_inst, // @[dcache.scala:419:14]
input [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_rvc, // @[dcache.scala:419:14]
input [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_iq_type, // @[dcache.scala:419:14]
input [9:0] io_lsu_brupdate_b2_uop_fu_code, // @[dcache.scala:419:14]
input [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_is_load, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_is_sta, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_is_std, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_iw_state, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_br, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_jalr, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_jal, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_sfb, // @[dcache.scala:419:14]
input [7:0] io_lsu_brupdate_b2_uop_br_mask, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_br_tag, // @[dcache.scala:419:14]
input [3:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_edge_inst, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_taken, // @[dcache.scala:419:14]
input [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[dcache.scala:419:14]
input [11:0] io_lsu_brupdate_b2_uop_csr_addr, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_rob_idx, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_stq_idx, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_pdst, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_prs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_prs2, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_prs3, // @[dcache.scala:419:14]
input [3:0] io_lsu_brupdate_b2_uop_ppred, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_prs1_busy, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_prs2_busy, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_prs3_busy, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ppred_busy, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_exception, // @[dcache.scala:419:14]
input [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_bypassable, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_mem_signed, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_fence, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_fencei, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_amo, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_uses_ldq, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_uses_stq, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_unique, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_flush_on_commit, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_ldst, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ldst_val, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_frs3_en, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_fp_val, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_fp_single, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_bp_debug_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_valid, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_mispredict, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_taken, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_cfi_type, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_pc_sel, // @[dcache.scala:419:14]
input [39:0] io_lsu_brupdate_b2_jalr_target, // @[dcache.scala:419:14]
input [20:0] io_lsu_brupdate_b2_target_offset, // @[dcache.scala:419:14]
input io_lsu_exception, // @[dcache.scala:419:14]
input [4:0] io_lsu_rob_pnr_idx, // @[dcache.scala:419:14]
input [4:0] io_lsu_rob_head_idx, // @[dcache.scala:419:14]
input io_lsu_release_ready, // @[dcache.scala:419:14]
output io_lsu_release_valid, // @[dcache.scala:419:14]
output [2:0] io_lsu_release_bits_opcode, // @[dcache.scala:419:14]
output [2:0] io_lsu_release_bits_param, // @[dcache.scala:419:14]
output [3:0] io_lsu_release_bits_size, // @[dcache.scala:419:14]
output [1:0] io_lsu_release_bits_source, // @[dcache.scala:419:14]
output [31:0] io_lsu_release_bits_address, // @[dcache.scala:419:14]
output [63:0] io_lsu_release_bits_data, // @[dcache.scala:419:14]
input io_lsu_force_order, // @[dcache.scala:419:14]
output io_lsu_ordered, // @[dcache.scala:419:14]
output io_lsu_perf_acquire, // @[dcache.scala:419:14]
output io_lsu_perf_release // @[dcache.scala:419:14]
);
wire resp_0_bits_is_hella; // @[dcache.scala:846:22]
wire [63:0] resp_0_bits_data; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_debug_tsrc; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_debug_fsrc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bp_xcpt_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bp_debug_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_ma_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_ae_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_pf_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_fp_single; // @[dcache.scala:846:22]
wire resp_0_bits_uop_fp_val; // @[dcache.scala:846:22]
wire resp_0_bits_uop_frs3_en; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_lrs2_rtype; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_lrs1_rtype; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_dst_rtype; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ldst_val; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs3; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs2; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs1; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_ldst; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ldst_is_rs1; // @[dcache.scala:846:22]
wire resp_0_bits_uop_flush_on_commit; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_unique; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_uses_stq; // @[dcache.scala:846:22]
wire resp_0_bits_uop_uses_ldq; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_amo; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_fencei; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_fence; // @[dcache.scala:846:22]
wire resp_0_bits_uop_mem_signed; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_mem_size; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_mem_cmd; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bypassable; // @[dcache.scala:846:22]
wire [63:0] resp_0_bits_uop_exc_cause; // @[dcache.scala:846:22]
wire resp_0_bits_uop_exception; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_stale_pdst; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ppred_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs3_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs2_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs1_busy; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ppred; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_prs3; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_prs2; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_prs1; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_pdst; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_rxq_idx; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_stq_idx; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ldq_idx; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_rob_idx; // @[dcache.scala:846:22]
wire [11:0] resp_0_bits_uop_csr_addr; // @[dcache.scala:846:22]
wire [19:0] resp_0_bits_uop_imm_packed; // @[dcache.scala:846:22]
wire resp_0_bits_uop_taken; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_pc_lob; // @[dcache.scala:846:22]
wire resp_0_bits_uop_edge_inst; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ftq_idx; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_br_tag; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_sfb; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_jal; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_jalr; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_br; // @[dcache.scala:846:22]
wire resp_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:846:22]
wire resp_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_iw_state; // @[dcache.scala:846:22]
wire [9:0] resp_0_bits_uop_fu_code; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_iq_type; // @[dcache.scala:846:22]
wire [39:0] resp_0_bits_uop_debug_pc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_rvc; // @[dcache.scala:846:22]
wire [31:0] resp_0_bits_uop_debug_inst; // @[dcache.scala:846:22]
wire [31:0] resp_0_bits_uop_inst; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_uopc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_std; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_sta; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_load; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ctrl_br_type; // @[dcache.scala:846:22]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire [63:0] _amoalu_io_out; // @[dcache.scala:896:24]
wire _lsu_release_arb_io_in_0_ready; // @[dcache.scala:814:31]
wire _lsu_release_arb_io_in_1_ready; // @[dcache.scala:814:31]
wire _wbArb_io_in_0_ready; // @[dcache.scala:805:21]
wire _wbArb_io_in_1_ready; // @[dcache.scala:805:21]
wire _wbArb_io_out_valid; // @[dcache.scala:805:21]
wire [19:0] _wbArb_io_out_bits_tag; // @[dcache.scala:805:21]
wire [5:0] _wbArb_io_out_bits_idx; // @[dcache.scala:805:21]
wire [1:0] _wbArb_io_out_bits_source; // @[dcache.scala:805:21]
wire [2:0] _wbArb_io_out_bits_param; // @[dcache.scala:805:21]
wire [3:0] _wbArb_io_out_bits_way_en; // @[dcache.scala:805:21]
wire _wbArb_io_out_bits_voluntary; // @[dcache.scala:805:21]
wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22]
wire _dataReadArb_io_in_1_ready; // @[dcache.scala:463:27]
wire _dataReadArb_io_in_2_ready; // @[dcache.scala:463:27]
wire _dataReadArb_io_out_valid; // @[dcache.scala:463:27]
wire [3:0] _dataReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:463:27]
wire [11:0] _dataReadArb_io_out_bits_req_0_addr; // @[dcache.scala:463:27]
wire _dataReadArb_io_out_bits_valid_0; // @[dcache.scala:463:27]
wire _dataWriteArb_io_in_1_ready; // @[dcache.scala:461:28]
wire [3:0] _dataWriteArb_io_out_bits_way_en; // @[dcache.scala:461:28]
wire [11:0] _dataWriteArb_io_out_bits_addr; // @[dcache.scala:461:28]
wire [63:0] _dataWriteArb_io_out_bits_data; // @[dcache.scala:461:28]
wire _metaReadArb_io_in_1_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_2_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_3_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_4_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_5_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_out_valid; // @[dcache.scala:445:27]
wire [5:0] _metaReadArb_io_out_bits_req_0_idx; // @[dcache.scala:445:27]
wire [3:0] _metaReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:445:27]
wire [19:0] _metaReadArb_io_out_bits_req_0_tag; // @[dcache.scala:445:27]
wire _metaWriteArb_io_in_0_ready; // @[dcache.scala:443:28]
wire _metaWriteArb_io_in_1_ready; // @[dcache.scala:443:28]
wire _metaWriteArb_io_out_valid; // @[dcache.scala:443:28]
wire [5:0] _metaWriteArb_io_out_bits_idx; // @[dcache.scala:443:28]
wire [3:0] _metaWriteArb_io_out_bits_way_en; // @[dcache.scala:443:28]
wire [19:0] _metaWriteArb_io_out_bits_tag; // @[dcache.scala:443:28]
wire [1:0] _metaWriteArb_io_out_bits_data_coh_state; // @[dcache.scala:443:28]
wire [19:0] _metaWriteArb_io_out_bits_data_tag; // @[dcache.scala:443:28]
wire _meta_0_io_read_ready; // @[dcache.scala:442:41]
wire _meta_0_io_write_ready; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_0_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_0_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_1_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_1_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_2_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_2_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_3_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_3_tag; // @[dcache.scala:442:41]
wire _mshrs_io_req_0_ready; // @[dcache.scala:433:21]
wire _mshrs_io_secondary_miss_0; // @[dcache.scala:433:21]
wire _mshrs_io_block_hit_0; // @[dcache.scala:433:21]
wire _mshrs_io_mem_grant_ready; // @[dcache.scala:433:21]
wire _mshrs_io_refill_valid; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_refill_bits_way_en; // @[dcache.scala:433:21]
wire [11:0] _mshrs_io_refill_bits_addr; // @[dcache.scala:433:21]
wire [63:0] _mshrs_io_refill_bits_data; // @[dcache.scala:433:21]
wire _mshrs_io_meta_write_valid; // @[dcache.scala:433:21]
wire [5:0] _mshrs_io_meta_write_bits_idx; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_meta_write_bits_way_en; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_meta_write_bits_data_coh_state; // @[dcache.scala:433:21]
wire [19:0] _mshrs_io_meta_write_bits_data_tag; // @[dcache.scala:433:21]
wire _mshrs_io_meta_read_valid; // @[dcache.scala:433:21]
wire [5:0] _mshrs_io_meta_read_bits_idx; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_meta_read_bits_way_en; // @[dcache.scala:433:21]
wire [19:0] _mshrs_io_meta_read_bits_tag; // @[dcache.scala:433:21]
wire _mshrs_io_replay_valid; // @[dcache.scala:433:21]
wire [4:0] _mshrs_io_replay_bits_uop_mem_cmd; // @[dcache.scala:433:21]
wire [39:0] _mshrs_io_replay_bits_addr; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_replay_bits_way_en; // @[dcache.scala:433:21]
wire _mshrs_io_wb_req_valid; // @[dcache.scala:433:21]
wire [19:0] _mshrs_io_wb_req_bits_tag; // @[dcache.scala:433:21]
wire [5:0] _mshrs_io_wb_req_bits_idx; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_wb_req_bits_source; // @[dcache.scala:433:21]
wire [2:0] _mshrs_io_wb_req_bits_param; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_wb_req_bits_way_en; // @[dcache.scala:433:21]
wire _mshrs_io_fence_rdy; // @[dcache.scala:433:21]
wire _mshrs_io_probe_rdy; // @[dcache.scala:433:21]
wire _prober_io_req_ready; // @[dcache.scala:432:22]
wire _prober_io_rep_valid; // @[dcache.scala:432:22]
wire [2:0] _prober_io_rep_bits_param; // @[dcache.scala:432:22]
wire [3:0] _prober_io_rep_bits_size; // @[dcache.scala:432:22]
wire [1:0] _prober_io_rep_bits_source; // @[dcache.scala:432:22]
wire [31:0] _prober_io_rep_bits_address; // @[dcache.scala:432:22]
wire _prober_io_meta_read_valid; // @[dcache.scala:432:22]
wire [5:0] _prober_io_meta_read_bits_idx; // @[dcache.scala:432:22]
wire [19:0] _prober_io_meta_read_bits_tag; // @[dcache.scala:432:22]
wire _prober_io_meta_write_valid; // @[dcache.scala:432:22]
wire [5:0] _prober_io_meta_write_bits_idx; // @[dcache.scala:432:22]
wire [3:0] _prober_io_meta_write_bits_way_en; // @[dcache.scala:432:22]
wire [19:0] _prober_io_meta_write_bits_tag; // @[dcache.scala:432:22]
wire [1:0] _prober_io_meta_write_bits_data_coh_state; // @[dcache.scala:432:22]
wire [19:0] _prober_io_meta_write_bits_data_tag; // @[dcache.scala:432:22]
wire _prober_io_wb_req_valid; // @[dcache.scala:432:22]
wire [19:0] _prober_io_wb_req_bits_tag; // @[dcache.scala:432:22]
wire [5:0] _prober_io_wb_req_bits_idx; // @[dcache.scala:432:22]
wire [1:0] _prober_io_wb_req_bits_source; // @[dcache.scala:432:22]
wire [2:0] _prober_io_wb_req_bits_param; // @[dcache.scala:432:22]
wire [3:0] _prober_io_wb_req_bits_way_en; // @[dcache.scala:432:22]
wire _prober_io_mshr_wb_rdy; // @[dcache.scala:432:22]
wire _prober_io_lsu_release_valid; // @[dcache.scala:432:22]
wire [2:0] _prober_io_lsu_release_bits_param; // @[dcache.scala:432:22]
wire [3:0] _prober_io_lsu_release_bits_size; // @[dcache.scala:432:22]
wire [1:0] _prober_io_lsu_release_bits_source; // @[dcache.scala:432:22]
wire [31:0] _prober_io_lsu_release_bits_address; // @[dcache.scala:432:22]
wire _prober_io_state_valid; // @[dcache.scala:432:22]
wire [39:0] _prober_io_state_bits; // @[dcache.scala:432:22]
wire _wb_io_req_ready; // @[dcache.scala:431:18]
wire _wb_io_meta_read_valid; // @[dcache.scala:431:18]
wire [5:0] _wb_io_meta_read_bits_idx; // @[dcache.scala:431:18]
wire [19:0] _wb_io_meta_read_bits_tag; // @[dcache.scala:431:18]
wire _wb_io_resp; // @[dcache.scala:431:18]
wire _wb_io_idx_valid; // @[dcache.scala:431:18]
wire [5:0] _wb_io_idx_bits; // @[dcache.scala:431:18]
wire _wb_io_data_req_valid; // @[dcache.scala:431:18]
wire [3:0] _wb_io_data_req_bits_way_en; // @[dcache.scala:431:18]
wire [11:0] _wb_io_data_req_bits_addr; // @[dcache.scala:431:18]
wire _wb_io_release_valid; // @[dcache.scala:431:18]
wire [2:0] _wb_io_release_bits_opcode; // @[dcache.scala:431:18]
wire [2:0] _wb_io_release_bits_param; // @[dcache.scala:431:18]
wire [31:0] _wb_io_release_bits_address; // @[dcache.scala:431:18]
wire [63:0] _wb_io_release_bits_data; // @[dcache.scala:431:18]
wire _wb_io_lsu_release_valid; // @[dcache.scala:431:18]
wire [2:0] _wb_io_lsu_release_bits_param; // @[dcache.scala:431:18]
wire [31:0] _wb_io_lsu_release_bits_address; // @[dcache.scala:431:18]
wire [63:0] _wb_io_lsu_release_bits_data; // @[dcache.scala:431:18]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[dcache.scala:413:7]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[dcache.scala:413:7]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[dcache.scala:413:7]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[dcache.scala:413:7]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[dcache.scala:413:7]
wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[dcache.scala:413:7]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[dcache.scala:413:7]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[dcache.scala:413:7]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[dcache.scala:413:7]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[dcache.scala:413:7]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[dcache.scala:413:7]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[dcache.scala:413:7]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[dcache.scala:413:7]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[dcache.scala:413:7]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[dcache.scala:413:7]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[dcache.scala:413:7]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[dcache.scala:413:7]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[dcache.scala:413:7]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[dcache.scala:413:7]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[dcache.scala:413:7]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[dcache.scala:413:7]
wire io_lsu_req_valid_0 = io_lsu_req_valid; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_valid_0 = io_lsu_req_bits_0_valid; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_uopc_0 = io_lsu_req_bits_0_bits_uop_uopc; // @[dcache.scala:413:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_inst_0 = io_lsu_req_bits_0_bits_uop_inst; // @[dcache.scala:413:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_debug_inst_0 = io_lsu_req_bits_0_bits_uop_debug_inst; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_rvc_0 = io_lsu_req_bits_0_bits_uop_is_rvc; // @[dcache.scala:413:7]
wire [39:0] io_lsu_req_bits_0_bits_uop_debug_pc_0 = io_lsu_req_bits_0_bits_uop_debug_pc; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_iq_type_0 = io_lsu_req_bits_0_bits_uop_iq_type; // @[dcache.scala:413:7]
wire [9:0] io_lsu_req_bits_0_bits_uop_fu_code_0 = io_lsu_req_bits_0_bits_uop_fu_code; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type_0 = io_lsu_req_bits_0_bits_uop_ctrl_br_type; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0 = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_load_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_load; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_sta; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_std_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_std; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_iw_state_0 = io_lsu_req_bits_0_bits_uop_iw_state; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_br_0 = io_lsu_req_bits_0_bits_uop_is_br; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_jalr_0 = io_lsu_req_bits_0_bits_uop_is_jalr; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_jal_0 = io_lsu_req_bits_0_bits_uop_is_jal; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_sfb_0 = io_lsu_req_bits_0_bits_uop_is_sfb; // @[dcache.scala:413:7]
wire [7:0] io_lsu_req_bits_0_bits_uop_br_mask_0 = io_lsu_req_bits_0_bits_uop_br_mask; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_br_tag_0 = io_lsu_req_bits_0_bits_uop_br_tag; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ftq_idx_0 = io_lsu_req_bits_0_bits_uop_ftq_idx; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_edge_inst_0 = io_lsu_req_bits_0_bits_uop_edge_inst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_pc_lob_0 = io_lsu_req_bits_0_bits_uop_pc_lob; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_taken_0 = io_lsu_req_bits_0_bits_uop_taken; // @[dcache.scala:413:7]
wire [19:0] io_lsu_req_bits_0_bits_uop_imm_packed_0 = io_lsu_req_bits_0_bits_uop_imm_packed; // @[dcache.scala:413:7]
wire [11:0] io_lsu_req_bits_0_bits_uop_csr_addr_0 = io_lsu_req_bits_0_bits_uop_csr_addr; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_rob_idx_0 = io_lsu_req_bits_0_bits_uop_rob_idx; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ldq_idx_0 = io_lsu_req_bits_0_bits_uop_ldq_idx; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_stq_idx_0 = io_lsu_req_bits_0_bits_uop_stq_idx; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx_0 = io_lsu_req_bits_0_bits_uop_rxq_idx; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_pdst_0 = io_lsu_req_bits_0_bits_uop_pdst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_prs1_0 = io_lsu_req_bits_0_bits_uop_prs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_prs2_0 = io_lsu_req_bits_0_bits_uop_prs2; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_prs3_0 = io_lsu_req_bits_0_bits_uop_prs3; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ppred_0 = io_lsu_req_bits_0_bits_uop_ppred; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs1_busy_0 = io_lsu_req_bits_0_bits_uop_prs1_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs2_busy_0 = io_lsu_req_bits_0_bits_uop_prs2_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs3_busy_0 = io_lsu_req_bits_0_bits_uop_prs3_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ppred_busy_0 = io_lsu_req_bits_0_bits_uop_ppred_busy; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_stale_pdst_0 = io_lsu_req_bits_0_bits_uop_stale_pdst; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_exception_0 = io_lsu_req_bits_0_bits_uop_exception; // @[dcache.scala:413:7]
wire [63:0] io_lsu_req_bits_0_bits_uop_exc_cause_0 = io_lsu_req_bits_0_bits_uop_exc_cause; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bypassable_0 = io_lsu_req_bits_0_bits_uop_bypassable; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd_0 = io_lsu_req_bits_0_bits_uop_mem_cmd; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_mem_size_0 = io_lsu_req_bits_0_bits_uop_mem_size; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_mem_signed_0 = io_lsu_req_bits_0_bits_uop_mem_signed; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_fence_0 = io_lsu_req_bits_0_bits_uop_is_fence; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_fencei_0 = io_lsu_req_bits_0_bits_uop_is_fencei; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_amo_0 = io_lsu_req_bits_0_bits_uop_is_amo; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_uses_ldq_0 = io_lsu_req_bits_0_bits_uop_uses_ldq; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_uses_stq_0 = io_lsu_req_bits_0_bits_uop_uses_stq; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0 = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_unique_0 = io_lsu_req_bits_0_bits_uop_is_unique; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_flush_on_commit_0 = io_lsu_req_bits_0_bits_uop_flush_on_commit; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_ldst_0 = io_lsu_req_bits_0_bits_uop_ldst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs1_0 = io_lsu_req_bits_0_bits_uop_lrs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs2_0 = io_lsu_req_bits_0_bits_uop_lrs2; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs3_0 = io_lsu_req_bits_0_bits_uop_lrs3; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ldst_val_0 = io_lsu_req_bits_0_bits_uop_ldst_val; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype_0 = io_lsu_req_bits_0_bits_uop_dst_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs1_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs2_rtype; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_frs3_en_0 = io_lsu_req_bits_0_bits_uop_frs3_en; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_fp_val_0 = io_lsu_req_bits_0_bits_uop_fp_val; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_fp_single_0 = io_lsu_req_bits_0_bits_uop_fp_single; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_pf_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ae_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ma_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bp_debug_if_0 = io_lsu_req_bits_0_bits_uop_bp_debug_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0 = io_lsu_req_bits_0_bits_uop_bp_xcpt_if; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc_0 = io_lsu_req_bits_0_bits_uop_debug_fsrc; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc_0 = io_lsu_req_bits_0_bits_uop_debug_tsrc; // @[dcache.scala:413:7]
wire [39:0] io_lsu_req_bits_0_bits_addr_0 = io_lsu_req_bits_0_bits_addr; // @[dcache.scala:413:7]
wire [63:0] io_lsu_req_bits_0_bits_data_0 = io_lsu_req_bits_0_bits_data; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_is_hella_0 = io_lsu_req_bits_0_bits_is_hella; // @[dcache.scala:413:7]
wire io_lsu_s1_kill_0_0 = io_lsu_s1_kill_0; // @[dcache.scala:413:7]
wire [7:0] io_lsu_brupdate_b1_resolve_mask_0 = io_lsu_brupdate_b1_resolve_mask; // @[dcache.scala:413:7]
wire [7:0] io_lsu_brupdate_b1_mispredict_mask_0 = io_lsu_brupdate_b1_mispredict_mask; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_uopc_0 = io_lsu_brupdate_b2_uop_uopc; // @[dcache.scala:413:7]
wire [31:0] io_lsu_brupdate_b2_uop_inst_0 = io_lsu_brupdate_b2_uop_inst; // @[dcache.scala:413:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0 = io_lsu_brupdate_b2_uop_debug_inst; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_rvc_0 = io_lsu_brupdate_b2_uop_is_rvc; // @[dcache.scala:413:7]
wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0 = io_lsu_brupdate_b2_uop_debug_pc; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_iq_type_0 = io_lsu_brupdate_b2_uop_iq_type; // @[dcache.scala:413:7]
wire [9:0] io_lsu_brupdate_b2_uop_fu_code_0 = io_lsu_brupdate_b2_uop_fu_code; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type_0 = io_lsu_brupdate_b2_uop_ctrl_br_type; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel_0 = io_lsu_brupdate_b2_uop_ctrl_op1_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel_0 = io_lsu_brupdate_b2_uop_ctrl_op2_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel_0 = io_lsu_brupdate_b2_uop_ctrl_imm_sel; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn_0 = io_lsu_brupdate_b2_uop_ctrl_op_fcn; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0 = io_lsu_brupdate_b2_uop_ctrl_fcn_dw; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0 = io_lsu_brupdate_b2_uop_ctrl_csr_cmd; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_load_0 = io_lsu_brupdate_b2_uop_ctrl_is_load; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_sta_0 = io_lsu_brupdate_b2_uop_ctrl_is_sta; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_std_0 = io_lsu_brupdate_b2_uop_ctrl_is_std; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_state_0 = io_lsu_brupdate_b2_uop_iw_state; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_iw_p1_poisoned_0 = io_lsu_brupdate_b2_uop_iw_p1_poisoned; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_iw_p2_poisoned_0 = io_lsu_brupdate_b2_uop_iw_p2_poisoned; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_br_0 = io_lsu_brupdate_b2_uop_is_br; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_jalr_0 = io_lsu_brupdate_b2_uop_is_jalr; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_jal_0 = io_lsu_brupdate_b2_uop_is_jal; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_sfb_0 = io_lsu_brupdate_b2_uop_is_sfb; // @[dcache.scala:413:7]
wire [7:0] io_lsu_brupdate_b2_uop_br_mask_0 = io_lsu_brupdate_b2_uop_br_mask; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_br_tag_0 = io_lsu_brupdate_b2_uop_br_tag; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx_0 = io_lsu_brupdate_b2_uop_ftq_idx; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_edge_inst_0 = io_lsu_brupdate_b2_uop_edge_inst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0 = io_lsu_brupdate_b2_uop_pc_lob; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_taken_0 = io_lsu_brupdate_b2_uop_taken; // @[dcache.scala:413:7]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0 = io_lsu_brupdate_b2_uop_imm_packed; // @[dcache.scala:413:7]
wire [11:0] io_lsu_brupdate_b2_uop_csr_addr_0 = io_lsu_brupdate_b2_uop_csr_addr; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_rob_idx_0 = io_lsu_brupdate_b2_uop_rob_idx; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ldq_idx_0 = io_lsu_brupdate_b2_uop_ldq_idx; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_stq_idx_0 = io_lsu_brupdate_b2_uop_stq_idx; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0 = io_lsu_brupdate_b2_uop_rxq_idx; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_pdst_0 = io_lsu_brupdate_b2_uop_pdst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs1_0 = io_lsu_brupdate_b2_uop_prs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs2_0 = io_lsu_brupdate_b2_uop_prs2; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs3_0 = io_lsu_brupdate_b2_uop_prs3; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ppred_0 = io_lsu_brupdate_b2_uop_ppred; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs1_busy_0 = io_lsu_brupdate_b2_uop_prs1_busy; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs2_busy_0 = io_lsu_brupdate_b2_uop_prs2_busy; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs3_busy_0 = io_lsu_brupdate_b2_uop_prs3_busy; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ppred_busy_0 = io_lsu_brupdate_b2_uop_ppred_busy; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_stale_pdst_0 = io_lsu_brupdate_b2_uop_stale_pdst; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_exception_0 = io_lsu_brupdate_b2_uop_exception; // @[dcache.scala:413:7]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0 = io_lsu_brupdate_b2_uop_exc_cause; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bypassable_0 = io_lsu_brupdate_b2_uop_bypassable; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0 = io_lsu_brupdate_b2_uop_mem_cmd; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0 = io_lsu_brupdate_b2_uop_mem_size; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_mem_signed_0 = io_lsu_brupdate_b2_uop_mem_signed; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_fence_0 = io_lsu_brupdate_b2_uop_is_fence; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_fencei_0 = io_lsu_brupdate_b2_uop_is_fencei; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_amo_0 = io_lsu_brupdate_b2_uop_is_amo; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_uses_ldq_0 = io_lsu_brupdate_b2_uop_uses_ldq; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_uses_stq_0 = io_lsu_brupdate_b2_uop_uses_stq; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_unique_0 = io_lsu_brupdate_b2_uop_is_unique; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit_0 = io_lsu_brupdate_b2_uop_flush_on_commit; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst_0 = io_lsu_brupdate_b2_uop_ldst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0 = io_lsu_brupdate_b2_uop_lrs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0 = io_lsu_brupdate_b2_uop_lrs2; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0 = io_lsu_brupdate_b2_uop_lrs3; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ldst_val_0 = io_lsu_brupdate_b2_uop_ldst_val; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0 = io_lsu_brupdate_b2_uop_dst_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0 = io_lsu_brupdate_b2_uop_lrs1_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0 = io_lsu_brupdate_b2_uop_lrs2_rtype; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_frs3_en_0 = io_lsu_brupdate_b2_uop_frs3_en; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_fp_val_0 = io_lsu_brupdate_b2_uop_fp_val; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_fp_single_0 = io_lsu_brupdate_b2_uop_fp_single; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if_0 = io_lsu_brupdate_b2_uop_bp_debug_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc_0 = io_lsu_brupdate_b2_uop_debug_fsrc; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc_0 = io_lsu_brupdate_b2_uop_debug_tsrc; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_valid_0 = io_lsu_brupdate_b2_valid; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_mispredict_0 = io_lsu_brupdate_b2_mispredict; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_taken_0 = io_lsu_brupdate_b2_taken; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type_0 = io_lsu_brupdate_b2_cfi_type; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel_0 = io_lsu_brupdate_b2_pc_sel; // @[dcache.scala:413:7]
wire [39:0] io_lsu_brupdate_b2_jalr_target_0 = io_lsu_brupdate_b2_jalr_target; // @[dcache.scala:413:7]
wire [20:0] io_lsu_brupdate_b2_target_offset_0 = io_lsu_brupdate_b2_target_offset; // @[dcache.scala:413:7]
wire io_lsu_exception_0 = io_lsu_exception; // @[dcache.scala:413:7]
wire [4:0] io_lsu_rob_pnr_idx_0 = io_lsu_rob_pnr_idx; // @[dcache.scala:413:7]
wire [4:0] io_lsu_rob_head_idx_0 = io_lsu_rob_head_idx; // @[dcache.scala:413:7]
wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:413:7]
wire io_lsu_force_order_0 = io_lsu_force_order; // @[dcache.scala:413:7]
wire auto_out_a_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire auto_out_c_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire mshr_read_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_br = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_jal = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_taken = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_exception = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bypassable = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_fence = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_amo = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_unique = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_fp_val = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_fp_single = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_is_hella = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_br = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_jal = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_taken = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_exception = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bypassable = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_fence = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_amo = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_unique = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_fp_val = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_fp_single = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_is_hella = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_br = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_jal = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_taken = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_exception = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bypassable = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_fence = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_amo = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_unique = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_fp_val = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_fp_single = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_is_hella = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire prefetch_fire = 1'h0; // @[Decoupled.scala:51:35]
wire prefetch_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_br = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_jal = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_taken = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_exception = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bypassable = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_fence = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_amo = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_unique = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_fp_val = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_fp_single = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_is_hella = 1'h0; // @[dcache.scala:568:27]
wire _s0_valid_WIRE_2_0 = 1'h0; // @[dcache.scala:581:82]
wire _s2_has_permission_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire s2_word_idx_0 = 1'h0; // @[dcache.scala:427:49]
wire s2_nack_data_0 = 1'h0; // @[dcache.scala:427:49]
wire opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _nodeOut_c_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire cache_resp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire cache_resp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire _s0_valid_WIRE_1_0 = 1'h1; // @[dcache.scala:581:48]
wire _mshrs_io_req_0_valid_T_6 = 1'h1; // @[dcache.scala:750:29]
wire _uncache_respond_T_1 = 1'h1; // @[dcache.scala:849:51]
wire [6:0] mshr_read_req_0_uop_uopc = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uopc = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uopc = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] prefetch_req_0_uop_uopc = 7'h0; // @[dcache.scala:568:27]
wire [6:0] _s2_data_word_prebypass_T = 7'h0; // @[dcache.scala:825:69]
wire [63:0] mshr_read_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:517:27]
wire [63:0] mshr_read_req_0_data = 64'h0; // @[dcache.scala:517:27]
wire [63:0] mshr_read_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] wb_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:532:20]
wire [63:0] wb_req_0_data = 64'h0; // @[dcache.scala:532:20]
wire [63:0] wb_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] prober_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:553:26]
wire [63:0] prober_req_0_data = 64'h0; // @[dcache.scala:553:26]
wire [63:0] prober_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] prefetch_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:568:27]
wire [63:0] prefetch_req_0_data = 64'h0; // @[dcache.scala:568:27]
wire [63:0] _nodeOut_c_bits_T_4 = 64'h0; // @[Mux.scala:30:73]
wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69]
wire [8:0] decode = 9'h7; // @[Edges.scala:220:59]
wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [1:0] mshr_read_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [3:0] _s2_has_permission_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_new_hit_state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_has_permission_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_new_hit_state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_has_permission_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_new_hit_state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_has_permission_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_new_hit_state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_has_permission_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _s2_new_hit_state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] mshr_read_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_ppred = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] wb_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_ppred = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] prober_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_ppred = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] prefetch_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_ppred = 4'h0; // @[dcache.scala:568:27]
wire [3:0] _s2_has_permission_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _s2_new_hit_state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [1:0] mshr_read_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_iw_state = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_mem_size = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] wb_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_iw_state = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_mem_size = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] prober_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_iw_state = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_mem_size = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] prefetch_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_iw_state = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_mem_size = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:568:27]
wire [1:0] _s2_has_permission_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [3:0] _s2_has_permission_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _s2_new_hit_state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _dataReadArb_io_in_2_bits_req_0_way_en_T = 4'hF; // @[dcache.scala:491:48]
wire [3:0] _s2_has_permission_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _s2_new_hit_state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _s2_has_permission_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_new_hit_state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_has_permission_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_new_hit_state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_has_permission_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_new_hit_state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_has_permission_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _s2_new_hit_state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [33:0] _metaReadArb_io_in_5_bits_req_0_idx_T = 34'h0; // @[dcache.scala:573:74]
wire [39:0] mshr_read_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:517:27]
wire [39:0] mshr_read_req_0_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] wb_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:532:20]
wire [39:0] wb_req_0_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] prober_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:553:26]
wire [39:0] prober_req_0_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] prefetch_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:568:27]
wire [39:0] prefetch_req_0_addr = 40'h0; // @[dcache.scala:568:27]
wire [5:0] mshr_read_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_pdst = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_prs1 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_prs2 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_prs3 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_stale_pdst = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_ldst = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_pdst = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_prs1 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_prs2 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_prs3 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_stale_pdst = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_ldst = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_pdst = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_prs1 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_prs2 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_prs3 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_stale_pdst = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_ldst = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prefetch_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_pdst = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_prs1 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_prs2 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_prs3 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_stale_pdst = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_ldst = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:568:27]
wire [4:0] mshr_read_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_rob_idx = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] wb_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_rob_idx = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] prober_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_rob_idx = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] prefetch_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_rob_idx = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:568:27]
wire [2:0] mshr_read_req_0_uop_iq_type = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_br_tag = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ldq_idx = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_stq_idx = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] mshr_read_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] mshr_read_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_iq_type = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_br_tag = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ldq_idx = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_stq_idx = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_iq_type = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_br_tag = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ldq_idx = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_stq_idx = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] prefetch_req_0_uop_iq_type = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_br_tag = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ldq_idx = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_stq_idx = 3'h0; // @[dcache.scala:568:27]
wire [11:0] mshr_read_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:517:27]
wire [11:0] mshr_read_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] wb_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:532:20]
wire [11:0] wb_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] prober_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:553:26]
wire [11:0] prober_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] prefetch_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:568:27]
wire [19:0] mshr_read_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:517:27]
wire [19:0] mshr_read_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] wb_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:532:20]
wire [19:0] wb_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] prober_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:553:26]
wire [19:0] prober_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] prefetch_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:568:27]
wire [7:0] mshr_read_req_0_uop_br_mask = 8'h0; // @[dcache.scala:517:27]
wire [7:0] mshr_read_req_0_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [7:0] wb_req_0_uop_br_mask = 8'h0; // @[dcache.scala:532:20]
wire [7:0] wb_req_0_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [7:0] prober_req_0_uop_br_mask = 8'h0; // @[dcache.scala:553:26]
wire [7:0] prober_req_0_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [7:0] prefetch_req_0_uop_br_mask = 8'h0; // @[dcache.scala:568:27]
wire [9:0] mshr_read_req_0_uop_fu_code = 10'h0; // @[dcache.scala:517:27]
wire [9:0] mshr_read_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] wb_req_0_uop_fu_code = 10'h0; // @[dcache.scala:532:20]
wire [9:0] wb_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] prober_req_0_uop_fu_code = 10'h0; // @[dcache.scala:553:26]
wire [9:0] prober_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] prefetch_req_0_uop_fu_code = 10'h0; // @[dcache.scala:568:27]
wire [31:0] mshr_read_req_0_uop_inst = 32'h0; // @[dcache.scala:517:27]
wire [31:0] mshr_read_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:517:27]
wire [31:0] mshr_read_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] mshr_read_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] wb_req_0_uop_inst = 32'h0; // @[dcache.scala:532:20]
wire [31:0] wb_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:532:20]
wire [31:0] wb_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] wb_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prober_req_0_uop_inst = 32'h0; // @[dcache.scala:553:26]
wire [31:0] prober_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:553:26]
wire [31:0] prober_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prober_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prefetch_req_0_uop_inst = 32'h0; // @[dcache.scala:568:27]
wire [31:0] prefetch_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:568:27]
wire [1:0] _s2_has_permission_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _dataWriteArb_io_in_0_bits_wmask_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _s2_has_permission_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _io_lsu_req_ready_T; // @[dcache.scala:480:50]
wire _s0_valid_WIRE_0 = io_lsu_req_bits_0_valid_0; // @[dcache.scala:413:7, :579:46]
wire [6:0] _s0_req_WIRE_0_uop_uopc = io_lsu_req_bits_0_bits_uop_uopc_0; // @[dcache.scala:413:7, :582:54]
wire [31:0] _s0_req_WIRE_0_uop_inst = io_lsu_req_bits_0_bits_uop_inst_0; // @[dcache.scala:413:7, :582:54]
wire [31:0] _s0_req_WIRE_0_uop_debug_inst = io_lsu_req_bits_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_rvc = io_lsu_req_bits_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7, :582:54]
wire [39:0] _s0_req_WIRE_0_uop_debug_pc = io_lsu_req_bits_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_iq_type = io_lsu_req_bits_0_bits_uop_iq_type_0; // @[dcache.scala:413:7, :582:54]
wire [9:0] _s0_req_WIRE_0_uop_fu_code = io_lsu_req_bits_0_bits_uop_fu_code_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ctrl_br_type = io_lsu_req_bits_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_ctrl_op1_sel = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_op2_sel = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_imm_sel = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_ctrl_op_fcn = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_fcn_dw = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_csr_cmd = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_load = io_lsu_req_bits_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_sta = io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_std = io_lsu_req_bits_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_iw_state = io_lsu_req_bits_0_bits_uop_iw_state_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_iw_p1_poisoned = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_iw_p2_poisoned = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_br = io_lsu_req_bits_0_bits_uop_is_br_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_jalr = io_lsu_req_bits_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_jal = io_lsu_req_bits_0_bits_uop_is_jal_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_sfb = io_lsu_req_bits_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7, :582:54]
wire [7:0] _s0_req_WIRE_0_uop_br_mask = io_lsu_req_bits_0_bits_uop_br_mask_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_br_tag = io_lsu_req_bits_0_bits_uop_br_tag_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ftq_idx = io_lsu_req_bits_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_edge_inst = io_lsu_req_bits_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_pc_lob = io_lsu_req_bits_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_taken = io_lsu_req_bits_0_bits_uop_taken_0; // @[dcache.scala:413:7, :582:54]
wire [19:0] _s0_req_WIRE_0_uop_imm_packed = io_lsu_req_bits_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7, :582:54]
wire [11:0] _s0_req_WIRE_0_uop_csr_addr = io_lsu_req_bits_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_rob_idx = io_lsu_req_bits_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ldq_idx = io_lsu_req_bits_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_stq_idx = io_lsu_req_bits_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_rxq_idx = io_lsu_req_bits_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_pdst = io_lsu_req_bits_0_bits_uop_pdst_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_prs1 = io_lsu_req_bits_0_bits_uop_prs1_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_prs2 = io_lsu_req_bits_0_bits_uop_prs2_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_prs3 = io_lsu_req_bits_0_bits_uop_prs3_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ppred = io_lsu_req_bits_0_bits_uop_ppred_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs1_busy = io_lsu_req_bits_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs2_busy = io_lsu_req_bits_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs3_busy = io_lsu_req_bits_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ppred_busy = io_lsu_req_bits_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_stale_pdst = io_lsu_req_bits_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_exception = io_lsu_req_bits_0_bits_uop_exception_0; // @[dcache.scala:413:7, :582:54]
wire [63:0] _s0_req_WIRE_0_uop_exc_cause = io_lsu_req_bits_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bypassable = io_lsu_req_bits_0_bits_uop_bypassable_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_mem_cmd = io_lsu_req_bits_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_mem_size = io_lsu_req_bits_0_bits_uop_mem_size_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_mem_signed = io_lsu_req_bits_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_fence = io_lsu_req_bits_0_bits_uop_is_fence_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_fencei = io_lsu_req_bits_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_amo = io_lsu_req_bits_0_bits_uop_is_amo_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_uses_ldq = io_lsu_req_bits_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_uses_stq = io_lsu_req_bits_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_sys_pc2epc = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_unique = io_lsu_req_bits_0_bits_uop_is_unique_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_flush_on_commit = io_lsu_req_bits_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ldst_is_rs1 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_ldst = io_lsu_req_bits_0_bits_uop_ldst_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs1 = io_lsu_req_bits_0_bits_uop_lrs1_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs2 = io_lsu_req_bits_0_bits_uop_lrs2_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs3 = io_lsu_req_bits_0_bits_uop_lrs3_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ldst_val = io_lsu_req_bits_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_dst_rtype = io_lsu_req_bits_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_lrs1_rtype = io_lsu_req_bits_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_lrs2_rtype = io_lsu_req_bits_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_frs3_en = io_lsu_req_bits_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_fp_val = io_lsu_req_bits_0_bits_uop_fp_val_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_fp_single = io_lsu_req_bits_0_bits_uop_fp_single_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_pf_if = io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_ae_if = io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_ma_if = io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bp_debug_if = io_lsu_req_bits_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bp_xcpt_if = io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_debug_fsrc = io_lsu_req_bits_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_debug_tsrc = io_lsu_req_bits_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7, :582:54]
wire [39:0] _s0_req_WIRE_0_addr = io_lsu_req_bits_0_bits_addr_0; // @[dcache.scala:413:7, :582:54]
wire [63:0] _s0_req_WIRE_0_data = io_lsu_req_bits_0_bits_data_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_is_hella = io_lsu_req_bits_0_bits_is_hella_0; // @[dcache.scala:413:7, :582:54]
wire _io_lsu_resp_0_valid_T_6; // @[dcache.scala:858:78]
wire [6:0] io_lsu_resp_0_bits_out_uop_uopc; // @[util.scala:101:23]
wire [31:0] io_lsu_resp_0_bits_out_uop_inst; // @[util.scala:101:23]
wire [31:0] io_lsu_resp_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
wire [39:0] io_lsu_resp_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_iq_type; // @[util.scala:101:23]
wire [9:0] io_lsu_resp_0_bits_out_uop_fu_code; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_iw_state; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_br; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_jal; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [7:0] io_lsu_resp_0_bits_out_uop_br_mask; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_br_tag; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_taken; // @[util.scala:101:23]
wire [19:0] io_lsu_resp_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
wire [11:0] io_lsu_resp_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_pdst; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_prs1; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_prs2; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_prs3; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ppred; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_exception; // @[util.scala:101:23]
wire [63:0] io_lsu_resp_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bypassable; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_mem_size; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_fence; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_amo; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_unique; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_ldst; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs1; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs2; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs3; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_fp_val; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_fp_single; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
wire [63:0] io_lsu_resp_0_bits_out_data; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_is_hella; // @[util.scala:101:23]
wire _io_lsu_nack_0_valid_T_7; // @[dcache.scala:863:75]
wire [6:0] io_lsu_nack_0_bits_out_uop_uopc; // @[util.scala:101:23]
wire [31:0] io_lsu_nack_0_bits_out_uop_inst; // @[util.scala:101:23]
wire [31:0] io_lsu_nack_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
wire [39:0] io_lsu_nack_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_iq_type; // @[util.scala:101:23]
wire [9:0] io_lsu_nack_0_bits_out_uop_fu_code; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_iw_state; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_br; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_jal; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [7:0] io_lsu_nack_0_bits_out_uop_br_mask; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_br_tag; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_taken; // @[util.scala:101:23]
wire [19:0] io_lsu_nack_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
wire [11:0] io_lsu_nack_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_pdst; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_prs1; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_prs2; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_prs3; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ppred; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_exception; // @[util.scala:101:23]
wire [63:0] io_lsu_nack_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bypassable; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_mem_size; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_fence; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_amo; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_unique; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_ldst; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs1; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs2; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs3; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_fp_val; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_fp_single; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
wire [39:0] io_lsu_nack_0_bits_out_addr; // @[util.scala:101:23]
wire [63:0] io_lsu_nack_0_bits_out_data; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_is_hella; // @[util.scala:101:23]
wire _io_lsu_ordered_T_3; // @[dcache.scala:913:66]
wire io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [2:0] auto_out_a_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_a_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_a_bits_size_0; // @[dcache.scala:413:7]
wire [1:0] auto_out_a_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] auto_out_a_bits_address_0; // @[dcache.scala:413:7]
wire [7:0] auto_out_a_bits_mask_0; // @[dcache.scala:413:7]
wire [63:0] auto_out_a_bits_data_0; // @[dcache.scala:413:7]
wire auto_out_a_valid_0; // @[dcache.scala:413:7]
wire auto_out_b_ready_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_c_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_c_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_c_bits_size_0; // @[dcache.scala:413:7]
wire [1:0] auto_out_c_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] auto_out_c_bits_address_0; // @[dcache.scala:413:7]
wire [63:0] auto_out_c_bits_data_0; // @[dcache.scala:413:7]
wire auto_out_c_valid_0; // @[dcache.scala:413:7]
wire auto_out_d_ready_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_e_bits_sink_0; // @[dcache.scala:413:7]
wire auto_out_e_valid_0; // @[dcache.scala:413:7]
wire io_lsu_req_ready_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_uopc_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_resp_0_bits_uop_inst_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_resp_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7]
wire [39:0] io_lsu_resp_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_iq_type_0; // @[dcache.scala:413:7]
wire [9:0] io_lsu_resp_0_bits_uop_fu_code_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_iw_state_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_br_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_jal_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7]
wire [7:0] io_lsu_resp_0_bits_uop_br_mask_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_br_tag_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_taken_0; // @[dcache.scala:413:7]
wire [19:0] io_lsu_resp_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7]
wire [11:0] io_lsu_resp_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_pdst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_prs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_prs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_prs3_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ppred_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_exception_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_resp_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bypassable_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_mem_size_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_fence_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_amo_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_unique_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_ldst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs3_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_fp_val_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_fp_single_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_resp_0_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_is_hella_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_valid_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_uopc_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_nack_0_bits_uop_inst_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_nack_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7]
wire [39:0] io_lsu_nack_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_iq_type_0; // @[dcache.scala:413:7]
wire [9:0] io_lsu_nack_0_bits_uop_fu_code_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_iw_state_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_br_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_jal_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7]
wire [7:0] io_lsu_nack_0_bits_uop_br_mask_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_br_tag_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_taken_0; // @[dcache.scala:413:7]
wire [19:0] io_lsu_nack_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7]
wire [11:0] io_lsu_nack_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_pdst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_prs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_prs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_prs3_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ppred_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_exception_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_nack_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bypassable_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_mem_size_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_fence_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_amo_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_unique_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_ldst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs3_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_fp_val_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_fp_single_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7]
wire [39:0] io_lsu_nack_0_bits_addr_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_nack_0_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_is_hella_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_valid_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_release_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_release_bits_size_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_release_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_release_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_release_valid_0; // @[dcache.scala:413:7]
wire io_lsu_perf_acquire_0; // @[dcache.scala:413:7]
wire io_lsu_perf_release_0; // @[dcache.scala:413:7]
wire io_lsu_ordered_0; // @[dcache.scala:413:7]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T_1; // @[dcache.scala:779:48]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _meta_0_io_write_valid_T = _meta_0_io_write_ready & _metaWriteArb_io_out_valid; // @[Decoupled.scala:51:35]
wire _data_io_read_0_valid_T = _dataReadArb_io_out_bits_valid_0 & _dataReadArb_io_out_valid; // @[dcache.scala:463:27, :468:63]
assign _io_lsu_req_ready_T = _metaReadArb_io_in_4_ready & _dataReadArb_io_in_2_ready; // @[dcache.scala:445:27, :463:27, :480:50]
assign io_lsu_req_ready_0 = _io_lsu_req_ready_T; // @[dcache.scala:413:7, :480:50]
wire [33:0] _metaReadArb_io_in_4_bits_req_0_idx_T = io_lsu_req_bits_0_bits_addr_0[39:6]; // @[dcache.scala:413:7, :485:77]
wire [3:0] replay_req_0_uop_ctrl_br_type; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_ctrl_op1_sel; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_op2_sel; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_imm_sel; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_ctrl_op_fcn; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_load; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_sta; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_std; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_uopc; // @[dcache.scala:496:24]
wire [31:0] replay_req_0_uop_inst; // @[dcache.scala:496:24]
wire [31:0] replay_req_0_uop_debug_inst; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_rvc; // @[dcache.scala:496:24]
wire [39:0] replay_req_0_uop_debug_pc; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_iq_type; // @[dcache.scala:496:24]
wire [9:0] replay_req_0_uop_fu_code; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_iw_state; // @[dcache.scala:496:24]
wire replay_req_0_uop_iw_p1_poisoned; // @[dcache.scala:496:24]
wire replay_req_0_uop_iw_p2_poisoned; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_br; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_jalr; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_jal; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_sfb; // @[dcache.scala:496:24]
wire [7:0] replay_req_0_uop_br_mask; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_br_tag; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_ftq_idx; // @[dcache.scala:496:24]
wire replay_req_0_uop_edge_inst; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_pc_lob; // @[dcache.scala:496:24]
wire replay_req_0_uop_taken; // @[dcache.scala:496:24]
wire [19:0] replay_req_0_uop_imm_packed; // @[dcache.scala:496:24]
wire [11:0] replay_req_0_uop_csr_addr; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_rob_idx; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ldq_idx; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_stq_idx; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_rxq_idx; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_pdst; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_prs1; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_prs2; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_prs3; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_ppred; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs1_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs2_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs3_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_ppred_busy; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_stale_pdst; // @[dcache.scala:496:24]
wire replay_req_0_uop_exception; // @[dcache.scala:496:24]
wire [63:0] replay_req_0_uop_exc_cause; // @[dcache.scala:496:24]
wire replay_req_0_uop_bypassable; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_mem_cmd; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_mem_size; // @[dcache.scala:496:24]
wire replay_req_0_uop_mem_signed; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_fence; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_fencei; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_amo; // @[dcache.scala:496:24]
wire replay_req_0_uop_uses_ldq; // @[dcache.scala:496:24]
wire replay_req_0_uop_uses_stq; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_sys_pc2epc; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_unique; // @[dcache.scala:496:24]
wire replay_req_0_uop_flush_on_commit; // @[dcache.scala:496:24]
wire replay_req_0_uop_ldst_is_rs1; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_ldst; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs1; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs2; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs3; // @[dcache.scala:496:24]
wire replay_req_0_uop_ldst_val; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_dst_rtype; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_lrs1_rtype; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_lrs2_rtype; // @[dcache.scala:496:24]
wire replay_req_0_uop_frs3_en; // @[dcache.scala:496:24]
wire replay_req_0_uop_fp_val; // @[dcache.scala:496:24]
wire replay_req_0_uop_fp_single; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_pf_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_ae_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_ma_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_bp_debug_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_bp_xcpt_if; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_debug_fsrc; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_debug_tsrc; // @[dcache.scala:496:24]
wire [39:0] replay_req_0_addr; // @[dcache.scala:496:24]
wire [63:0] replay_req_0_data; // @[dcache.scala:496:24]
wire replay_req_0_is_hella; // @[dcache.scala:496:24]
wire [33:0] _metaReadArb_io_in_0_bits_req_0_idx_T = _mshrs_io_replay_bits_addr[39:6]; // @[dcache.scala:433:21, :506:72]
wire [39:0] mshr_read_req_0_addr; // @[dcache.scala:517:27]
wire [25:0] _mshr_read_req_0_addr_T = {_mshrs_io_meta_read_bits_tag, _mshrs_io_meta_read_bits_idx}; // @[dcache.scala:433:21, :520:35]
wire [31:0] _mshr_read_req_0_addr_T_1 = {_mshr_read_req_0_addr_T, 6'h0}; // @[dcache.scala:520:{35,94}]
assign mshr_read_req_0_addr = {8'h0, _mshr_read_req_0_addr_T_1}; // @[dcache.scala:517:27, :520:{29,94}]
wire _wb_io_meta_read_ready_T; // @[dcache.scala:542:55]
wire _wb_fire_T = _wb_io_meta_read_ready_T & _wb_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _wb_io_data_req_ready_T; // @[dcache.scala:547:55]
wire _wb_fire_T_1 = _wb_io_data_req_ready_T & _wb_io_data_req_valid; // @[Decoupled.scala:51:35]
wire wb_fire = _wb_fire_T & _wb_fire_T_1; // @[Decoupled.scala:51:35]
wire [39:0] wb_req_0_addr; // @[dcache.scala:532:20]
wire [31:0] _wb_req_0_addr_T = {_wb_io_meta_read_bits_tag, _wb_io_data_req_bits_addr}; // @[dcache.scala:431:18, :535:28]
assign wb_req_0_addr = {8'h0, _wb_req_0_addr_T}; // @[dcache.scala:532:20, :535:{22,28}]
wire _GEN = _metaReadArb_io_in_2_ready & _dataReadArb_io_in_1_ready; // @[dcache.scala:445:27, :463:27, :542:55]
assign _wb_io_meta_read_ready_T = _GEN; // @[dcache.scala:542:55]
assign _wb_io_data_req_ready_T = _GEN; // @[dcache.scala:542:55, :547:55]
wire prober_fire = _metaReadArb_io_in_1_ready & _prober_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire [39:0] prober_req_0_addr; // @[dcache.scala:553:26]
wire [25:0] _prober_req_0_addr_T = {_prober_io_meta_read_bits_tag, _prober_io_meta_read_bits_idx}; // @[dcache.scala:432:22, :556:32]
wire [31:0] _prober_req_0_addr_T_1 = {_prober_req_0_addr_T, 6'h0}; // @[dcache.scala:556:{32,93}]
assign prober_req_0_addr = {8'h0, _prober_req_0_addr_T_1}; // @[dcache.scala:553:26, :556:{26,93}]
wire _T_7 = io_lsu_req_ready_0 & io_lsu_req_valid_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T; // @[Decoupled.scala:51:35]
assign _s0_valid_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_req_T; // @[Decoupled.scala:51:35]
assign _s0_req_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_type_T; // @[Decoupled.scala:51:35]
assign _s0_type_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T = _T_7; // @[Decoupled.scala:51:35]
wire _s1_valid_T_7; // @[Decoupled.scala:51:35]
assign _s1_valid_T_7 = _T_7; // @[Decoupled.scala:51:35]
wire _mshrs_io_replay_ready_T; // @[dcache.scala:502:58]
wire _GEN_0 = _mshrs_io_replay_ready_T & _mshrs_io_replay_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_1; // @[Decoupled.scala:51:35]
assign _s0_valid_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_1; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T_2 = _s0_valid_T_1 | wb_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_3 = _s0_valid_T_2 | prober_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_4 = _s0_valid_T_3; // @[dcache.scala:580:{54,69}]
wire _GEN_1 = _metaReadArb_io_in_3_ready & _mshrs_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_5; // @[Decoupled.scala:51:35]
assign _s0_valid_T_5 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_1; // @[Decoupled.scala:51:35]
assign _s0_req_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_type_T_1; // @[Decoupled.scala:51:35]
assign _s0_type_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_valid_T_6 = _s0_valid_T_4 | _s0_valid_T_5; // @[Decoupled.scala:51:35]
wire _s0_valid_T_7_0 = _s0_valid_T_6; // @[dcache.scala:580:{21,86}]
wire s0_valid_0 = _s0_valid_T ? _s0_valid_WIRE_0 : _s0_valid_T_7_0; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_uopc = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_debug_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_rvc = ~_s0_req_T_1 & replay_req_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_2_0_uop_debug_pc = _s0_req_T_1 ? 40'h0 : replay_req_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_iq_type = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] _s0_req_T_2_0_uop_fu_code = _s0_req_T_1 ? 10'h0 : replay_req_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ctrl_br_type = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_ctrl_op1_sel = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_op2_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_imm_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ctrl_op_fcn = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_fcn_dw = ~_s0_req_T_1 & replay_req_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_csr_cmd = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_load = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_sta = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_std = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_iw_state = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p1_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p2_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_br = ~_s0_req_T_1 & replay_req_0_uop_is_br; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_jalr = ~_s0_req_T_1 & replay_req_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_jal = ~_s0_req_T_1 & replay_req_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sfb = ~_s0_req_T_1 & replay_req_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [7:0] _s0_req_T_2_0_uop_br_mask = _s0_req_T_1 ? 8'h0 : replay_req_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_br_tag = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ftq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_edge_inst = ~_s0_req_T_1 & replay_req_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_pc_lob = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_taken = ~_s0_req_T_1 & replay_req_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_2_0_uop_imm_packed = _s0_req_T_1 ? 20'h0 : replay_req_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_2_0_uop_csr_addr = _s0_req_T_1 ? 12'h0 : replay_req_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_rob_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ldq_idx = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_stq_idx = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_rxq_idx = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_pdst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_prs1 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_prs2 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_prs3 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ppred = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs1_busy = ~_s0_req_T_1 & replay_req_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs2_busy = ~_s0_req_T_1 & replay_req_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs3_busy = ~_s0_req_T_1 & replay_req_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ppred_busy = ~_s0_req_T_1 & replay_req_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_stale_pdst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_exception = ~_s0_req_T_1 & replay_req_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_uop_exc_cause = _s0_req_T_1 ? 64'h0 : replay_req_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bypassable = ~_s0_req_T_1 & replay_req_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_mem_cmd = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_mem_size = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_mem_signed = ~_s0_req_T_1 & replay_req_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fence = ~_s0_req_T_1 & replay_req_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fencei = ~_s0_req_T_1 & replay_req_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_amo = ~_s0_req_T_1 & replay_req_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_ldq = ~_s0_req_T_1 & replay_req_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_stq = ~_s0_req_T_1 & replay_req_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sys_pc2epc = ~_s0_req_T_1 & replay_req_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_unique = ~_s0_req_T_1 & replay_req_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_flush_on_commit = ~_s0_req_T_1 & replay_req_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ldst_is_rs1 = ~_s0_req_T_1 & replay_req_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_ldst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs1 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs2 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs3 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ldst_val = ~_s0_req_T_1 & replay_req_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_dst_rtype = _s0_req_T_1 ? 2'h2 : replay_req_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs1_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs2_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_frs3_en = ~_s0_req_T_1 & replay_req_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_val = ~_s0_req_T_1 & replay_req_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_single = ~_s0_req_T_1 & replay_req_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_pf_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ae_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ma_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_debug_if = ~_s0_req_T_1 & replay_req_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_xcpt_if = ~_s0_req_T_1 & replay_req_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_debug_fsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_debug_tsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_2_0_addr = _s0_req_T_1 ? mshr_read_req_0_addr : replay_req_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_data = _s0_req_T_1 ? 64'h0 : replay_req_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_is_hella = ~_s0_req_T_1 & replay_req_0_is_hella; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_3_0_uop_uopc = _s0_req_T_2_0_uop_uopc; // @[dcache.scala:585:21, :586:21]
wire [31:0] _s0_req_T_3_0_uop_inst = _s0_req_T_2_0_uop_inst; // @[dcache.scala:585:21, :586:21]
wire [31:0] _s0_req_T_3_0_uop_debug_inst = _s0_req_T_2_0_uop_debug_inst; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_rvc = _s0_req_T_2_0_uop_is_rvc; // @[dcache.scala:585:21, :586:21]
wire [39:0] _s0_req_T_3_0_uop_debug_pc = _s0_req_T_2_0_uop_debug_pc; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_iq_type = _s0_req_T_2_0_uop_iq_type; // @[dcache.scala:585:21, :586:21]
wire [9:0] _s0_req_T_3_0_uop_fu_code = _s0_req_T_2_0_uop_fu_code; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ctrl_br_type = _s0_req_T_2_0_uop_ctrl_br_type; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_ctrl_op1_sel = _s0_req_T_2_0_uop_ctrl_op1_sel; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_op2_sel = _s0_req_T_2_0_uop_ctrl_op2_sel; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_imm_sel = _s0_req_T_2_0_uop_ctrl_imm_sel; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_ctrl_op_fcn = _s0_req_T_2_0_uop_ctrl_op_fcn; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_fcn_dw = _s0_req_T_2_0_uop_ctrl_fcn_dw; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_csr_cmd = _s0_req_T_2_0_uop_ctrl_csr_cmd; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_load = _s0_req_T_2_0_uop_ctrl_is_load; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_sta = _s0_req_T_2_0_uop_ctrl_is_sta; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_std = _s0_req_T_2_0_uop_ctrl_is_std; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_iw_state = _s0_req_T_2_0_uop_iw_state; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_iw_p1_poisoned = _s0_req_T_2_0_uop_iw_p1_poisoned; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_iw_p2_poisoned = _s0_req_T_2_0_uop_iw_p2_poisoned; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_br = _s0_req_T_2_0_uop_is_br; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_jalr = _s0_req_T_2_0_uop_is_jalr; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_jal = _s0_req_T_2_0_uop_is_jal; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_sfb = _s0_req_T_2_0_uop_is_sfb; // @[dcache.scala:585:21, :586:21]
wire [7:0] _s0_req_T_3_0_uop_br_mask = _s0_req_T_2_0_uop_br_mask; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_br_tag = _s0_req_T_2_0_uop_br_tag; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ftq_idx = _s0_req_T_2_0_uop_ftq_idx; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_edge_inst = _s0_req_T_2_0_uop_edge_inst; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_pc_lob = _s0_req_T_2_0_uop_pc_lob; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_taken = _s0_req_T_2_0_uop_taken; // @[dcache.scala:585:21, :586:21]
wire [19:0] _s0_req_T_3_0_uop_imm_packed = _s0_req_T_2_0_uop_imm_packed; // @[dcache.scala:585:21, :586:21]
wire [11:0] _s0_req_T_3_0_uop_csr_addr = _s0_req_T_2_0_uop_csr_addr; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_rob_idx = _s0_req_T_2_0_uop_rob_idx; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ldq_idx = _s0_req_T_2_0_uop_ldq_idx; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_stq_idx = _s0_req_T_2_0_uop_stq_idx; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_rxq_idx = _s0_req_T_2_0_uop_rxq_idx; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_pdst = _s0_req_T_2_0_uop_pdst; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_prs1 = _s0_req_T_2_0_uop_prs1; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_prs2 = _s0_req_T_2_0_uop_prs2; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_prs3 = _s0_req_T_2_0_uop_prs3; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ppred = _s0_req_T_2_0_uop_ppred; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs1_busy = _s0_req_T_2_0_uop_prs1_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs2_busy = _s0_req_T_2_0_uop_prs2_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs3_busy = _s0_req_T_2_0_uop_prs3_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ppred_busy = _s0_req_T_2_0_uop_ppred_busy; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_stale_pdst = _s0_req_T_2_0_uop_stale_pdst; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_exception = _s0_req_T_2_0_uop_exception; // @[dcache.scala:585:21, :586:21]
wire [63:0] _s0_req_T_3_0_uop_exc_cause = _s0_req_T_2_0_uop_exc_cause; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bypassable = _s0_req_T_2_0_uop_bypassable; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_mem_cmd = _s0_req_T_2_0_uop_mem_cmd; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_mem_size = _s0_req_T_2_0_uop_mem_size; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_mem_signed = _s0_req_T_2_0_uop_mem_signed; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_fence = _s0_req_T_2_0_uop_is_fence; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_fencei = _s0_req_T_2_0_uop_is_fencei; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_amo = _s0_req_T_2_0_uop_is_amo; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_uses_ldq = _s0_req_T_2_0_uop_uses_ldq; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_uses_stq = _s0_req_T_2_0_uop_uses_stq; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_sys_pc2epc = _s0_req_T_2_0_uop_is_sys_pc2epc; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_unique = _s0_req_T_2_0_uop_is_unique; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_flush_on_commit = _s0_req_T_2_0_uop_flush_on_commit; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ldst_is_rs1 = _s0_req_T_2_0_uop_ldst_is_rs1; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_ldst = _s0_req_T_2_0_uop_ldst; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs1 = _s0_req_T_2_0_uop_lrs1; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs2 = _s0_req_T_2_0_uop_lrs2; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs3 = _s0_req_T_2_0_uop_lrs3; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ldst_val = _s0_req_T_2_0_uop_ldst_val; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_dst_rtype = _s0_req_T_2_0_uop_dst_rtype; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_lrs1_rtype = _s0_req_T_2_0_uop_lrs1_rtype; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_lrs2_rtype = _s0_req_T_2_0_uop_lrs2_rtype; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_frs3_en = _s0_req_T_2_0_uop_frs3_en; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_fp_val = _s0_req_T_2_0_uop_fp_val; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_fp_single = _s0_req_T_2_0_uop_fp_single; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_pf_if = _s0_req_T_2_0_uop_xcpt_pf_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_ae_if = _s0_req_T_2_0_uop_xcpt_ae_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_ma_if = _s0_req_T_2_0_uop_xcpt_ma_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bp_debug_if = _s0_req_T_2_0_uop_bp_debug_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bp_xcpt_if = _s0_req_T_2_0_uop_bp_xcpt_if; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_debug_fsrc = _s0_req_T_2_0_uop_debug_fsrc; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_debug_tsrc = _s0_req_T_2_0_uop_debug_tsrc; // @[dcache.scala:585:21, :586:21]
wire [39:0] _s0_req_T_3_0_addr = _s0_req_T_2_0_addr; // @[dcache.scala:585:21, :586:21]
wire [63:0] _s0_req_T_3_0_data = _s0_req_T_2_0_data; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_is_hella = _s0_req_T_2_0_is_hella; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_4_0_uop_uopc = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_4_0_uop_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_4_0_uop_debug_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_rvc = ~prober_fire & _s0_req_T_3_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_4_0_uop_debug_pc = prober_fire ? 40'h0 : _s0_req_T_3_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_iq_type = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] _s0_req_T_4_0_uop_fu_code = prober_fire ? 10'h0 : _s0_req_T_3_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ctrl_br_type = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_ctrl_op1_sel = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_op2_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_imm_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ctrl_op_fcn = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_fcn_dw = ~prober_fire & _s0_req_T_3_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_csr_cmd = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_load = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_sta = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_std = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_iw_state = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p1_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p2_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_br = ~prober_fire & _s0_req_T_3_0_uop_is_br; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_jalr = ~prober_fire & _s0_req_T_3_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_jal = ~prober_fire & _s0_req_T_3_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sfb = ~prober_fire & _s0_req_T_3_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [7:0] _s0_req_T_4_0_uop_br_mask = prober_fire ? 8'h0 : _s0_req_T_3_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_br_tag = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ftq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_edge_inst = ~prober_fire & _s0_req_T_3_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_pc_lob = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_taken = ~prober_fire & _s0_req_T_3_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_4_0_uop_imm_packed = prober_fire ? 20'h0 : _s0_req_T_3_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_4_0_uop_csr_addr = prober_fire ? 12'h0 : _s0_req_T_3_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_rob_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ldq_idx = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_stq_idx = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_rxq_idx = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_pdst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_prs1 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_prs2 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_prs3 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ppred = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs1_busy = ~prober_fire & _s0_req_T_3_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs2_busy = ~prober_fire & _s0_req_T_3_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs3_busy = ~prober_fire & _s0_req_T_3_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ppred_busy = ~prober_fire & _s0_req_T_3_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_stale_pdst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_exception = ~prober_fire & _s0_req_T_3_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_uop_exc_cause = prober_fire ? 64'h0 : _s0_req_T_3_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bypassable = ~prober_fire & _s0_req_T_3_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_mem_cmd = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_mem_size = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_mem_signed = ~prober_fire & _s0_req_T_3_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fence = ~prober_fire & _s0_req_T_3_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fencei = ~prober_fire & _s0_req_T_3_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_amo = ~prober_fire & _s0_req_T_3_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_ldq = ~prober_fire & _s0_req_T_3_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_stq = ~prober_fire & _s0_req_T_3_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sys_pc2epc = ~prober_fire & _s0_req_T_3_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_unique = ~prober_fire & _s0_req_T_3_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_flush_on_commit = ~prober_fire & _s0_req_T_3_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ldst_is_rs1 = ~prober_fire & _s0_req_T_3_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_ldst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs1 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs2 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs3 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ldst_val = ~prober_fire & _s0_req_T_3_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_dst_rtype = prober_fire ? 2'h2 : _s0_req_T_3_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs1_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs2_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_frs3_en = ~prober_fire & _s0_req_T_3_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_val = ~prober_fire & _s0_req_T_3_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_single = ~prober_fire & _s0_req_T_3_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_pf_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ae_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ma_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_debug_if = ~prober_fire & _s0_req_T_3_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_xcpt_if = ~prober_fire & _s0_req_T_3_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_debug_fsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_debug_tsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_4_0_addr = prober_fire ? prober_req_0_addr : _s0_req_T_3_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_data = prober_fire ? 64'h0 : _s0_req_T_3_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_is_hella = ~prober_fire & _s0_req_T_3_0_is_hella; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_5_0_uop_uopc = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_uopc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [31:0] _s0_req_T_5_0_uop_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [31:0] _s0_req_T_5_0_uop_debug_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_debug_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_rvc = ~wb_fire & _s0_req_T_4_0_uop_is_rvc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [39:0] _s0_req_T_5_0_uop_debug_pc = wb_fire ? 40'h0 : _s0_req_T_4_0_uop_debug_pc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_iq_type = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_iq_type; // @[dcache.scala:531:38, :583:21, :584:21]
wire [9:0] _s0_req_T_5_0_uop_fu_code = wb_fire ? 10'h0 : _s0_req_T_4_0_uop_fu_code; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ctrl_br_type = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ctrl_br_type; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_ctrl_op1_sel = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_ctrl_op1_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_op2_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_op2_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_imm_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_imm_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_ctrl_op_fcn = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ctrl_op_fcn; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_fcn_dw = ~wb_fire & _s0_req_T_4_0_uop_ctrl_fcn_dw; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_csr_cmd = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_csr_cmd; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_load = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_load; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_sta = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_sta; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_std = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_std; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_iw_state = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_iw_state; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_iw_p1_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p1_poisoned; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_iw_p2_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p2_poisoned; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_br = ~wb_fire & _s0_req_T_4_0_uop_is_br; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_jalr = ~wb_fire & _s0_req_T_4_0_uop_is_jalr; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_jal = ~wb_fire & _s0_req_T_4_0_uop_is_jal; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_sfb = ~wb_fire & _s0_req_T_4_0_uop_is_sfb; // @[dcache.scala:531:38, :583:21, :584:21]
wire [7:0] _s0_req_T_5_0_uop_br_mask = wb_fire ? 8'h0 : _s0_req_T_4_0_uop_br_mask; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_br_tag = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_br_tag; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ftq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ftq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_edge_inst = ~wb_fire & _s0_req_T_4_0_uop_edge_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_pc_lob = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_pc_lob; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_taken = ~wb_fire & _s0_req_T_4_0_uop_taken; // @[dcache.scala:531:38, :583:21, :584:21]
wire [19:0] _s0_req_T_5_0_uop_imm_packed = wb_fire ? 20'h0 : _s0_req_T_4_0_uop_imm_packed; // @[dcache.scala:531:38, :583:21, :584:21]
wire [11:0] _s0_req_T_5_0_uop_csr_addr = wb_fire ? 12'h0 : _s0_req_T_4_0_uop_csr_addr; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_rob_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_rob_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ldq_idx = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ldq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_stq_idx = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_stq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_rxq_idx = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_rxq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_pdst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_pdst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_prs1 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_prs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_prs2 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_prs2; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_prs3 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_prs3; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ppred = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ppred; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs1_busy = ~wb_fire & _s0_req_T_4_0_uop_prs1_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs2_busy = ~wb_fire & _s0_req_T_4_0_uop_prs2_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs3_busy = ~wb_fire & _s0_req_T_4_0_uop_prs3_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ppred_busy = ~wb_fire & _s0_req_T_4_0_uop_ppred_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_stale_pdst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_stale_pdst; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_exception = ~wb_fire & _s0_req_T_4_0_uop_exception; // @[dcache.scala:531:38, :583:21, :584:21]
wire [63:0] _s0_req_T_5_0_uop_exc_cause = wb_fire ? 64'h0 : _s0_req_T_4_0_uop_exc_cause; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bypassable = ~wb_fire & _s0_req_T_4_0_uop_bypassable; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_mem_cmd = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_mem_cmd; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_mem_size = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_mem_size; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_mem_signed = ~wb_fire & _s0_req_T_4_0_uop_mem_signed; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_fence = ~wb_fire & _s0_req_T_4_0_uop_is_fence; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_fencei = ~wb_fire & _s0_req_T_4_0_uop_is_fencei; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_amo = ~wb_fire & _s0_req_T_4_0_uop_is_amo; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_uses_ldq = ~wb_fire & _s0_req_T_4_0_uop_uses_ldq; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_uses_stq = ~wb_fire & _s0_req_T_4_0_uop_uses_stq; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_sys_pc2epc = ~wb_fire & _s0_req_T_4_0_uop_is_sys_pc2epc; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_unique = ~wb_fire & _s0_req_T_4_0_uop_is_unique; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_flush_on_commit = ~wb_fire & _s0_req_T_4_0_uop_flush_on_commit; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ldst_is_rs1 = ~wb_fire & _s0_req_T_4_0_uop_ldst_is_rs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_ldst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_ldst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs1 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs2 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs2; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs3 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs3; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ldst_val = ~wb_fire & _s0_req_T_4_0_uop_ldst_val; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_dst_rtype = wb_fire ? 2'h2 : _s0_req_T_4_0_uop_dst_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_lrs1_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs1_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_lrs2_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs2_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_frs3_en = ~wb_fire & _s0_req_T_4_0_uop_frs3_en; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_fp_val = ~wb_fire & _s0_req_T_4_0_uop_fp_val; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_fp_single = ~wb_fire & _s0_req_T_4_0_uop_fp_single; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_pf_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_pf_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_ae_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ae_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_ma_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ma_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bp_debug_if = ~wb_fire & _s0_req_T_4_0_uop_bp_debug_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bp_xcpt_if = ~wb_fire & _s0_req_T_4_0_uop_bp_xcpt_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_debug_fsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_fsrc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_debug_tsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_tsrc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [39:0] _s0_req_T_5_0_addr = wb_fire ? wb_req_0_addr : _s0_req_T_4_0_addr; // @[dcache.scala:531:38, :532:20, :583:21, :584:21]
wire [63:0] _s0_req_T_5_0_data = wb_fire ? 64'h0 : _s0_req_T_4_0_data; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_is_hella = ~wb_fire & _s0_req_T_4_0_is_hella; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] s0_req_0_uop_uopc = _s0_req_T ? _s0_req_WIRE_0_uop_uopc : _s0_req_T_5_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] s0_req_0_uop_inst = _s0_req_T ? _s0_req_WIRE_0_uop_inst : _s0_req_T_5_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] s0_req_0_uop_debug_inst = _s0_req_T ? _s0_req_WIRE_0_uop_debug_inst : _s0_req_T_5_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_rvc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rvc : _s0_req_T_5_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] s0_req_0_uop_debug_pc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_pc : _s0_req_T_5_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_iq_type = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type : _s0_req_T_5_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] s0_req_0_uop_fu_code = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code : _s0_req_T_5_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ctrl_br_type = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_br_type : _s0_req_T_5_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_ctrl_op1_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op1_sel : _s0_req_T_5_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_op2_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op2_sel : _s0_req_T_5_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_imm_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_imm_sel : _s0_req_T_5_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ctrl_op_fcn = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op_fcn : _s0_req_T_5_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_fcn_dw = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_fcn_dw : _s0_req_T_5_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_csr_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_csr_cmd : _s0_req_T_5_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_load = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_load : _s0_req_T_5_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_sta = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_sta : _s0_req_T_5_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_std = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_std : _s0_req_T_5_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_iw_state = _s0_req_T ? _s0_req_WIRE_0_uop_iw_state : _s0_req_T_5_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p1_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_poisoned : _s0_req_T_5_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p2_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_poisoned : _s0_req_T_5_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_br = _s0_req_T ? _s0_req_WIRE_0_uop_is_br : _s0_req_T_5_0_uop_is_br; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_jalr = _s0_req_T ? _s0_req_WIRE_0_uop_is_jalr : _s0_req_T_5_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_jal = _s0_req_T ? _s0_req_WIRE_0_uop_is_jal : _s0_req_T_5_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sfb = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfb : _s0_req_T_5_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [7:0] s0_req_0_uop_br_mask = _s0_req_T ? _s0_req_WIRE_0_uop_br_mask : _s0_req_T_5_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_br_tag = _s0_req_T ? _s0_req_WIRE_0_uop_br_tag : _s0_req_T_5_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ftq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ftq_idx : _s0_req_T_5_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_edge_inst = _s0_req_T ? _s0_req_WIRE_0_uop_edge_inst : _s0_req_T_5_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_pc_lob = _s0_req_T ? _s0_req_WIRE_0_uop_pc_lob : _s0_req_T_5_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_taken = _s0_req_T ? _s0_req_WIRE_0_uop_taken : _s0_req_T_5_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] s0_req_0_uop_imm_packed = _s0_req_T ? _s0_req_WIRE_0_uop_imm_packed : _s0_req_T_5_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] s0_req_0_uop_csr_addr = _s0_req_T ? _s0_req_WIRE_0_uop_csr_addr : _s0_req_T_5_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_rob_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rob_idx : _s0_req_T_5_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ldq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ldq_idx : _s0_req_T_5_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_stq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_stq_idx : _s0_req_T_5_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_rxq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rxq_idx : _s0_req_T_5_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_pdst : _s0_req_T_5_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_prs1 = _s0_req_T ? _s0_req_WIRE_0_uop_prs1 : _s0_req_T_5_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_prs2 = _s0_req_T ? _s0_req_WIRE_0_uop_prs2 : _s0_req_T_5_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_prs3 = _s0_req_T ? _s0_req_WIRE_0_uop_prs3 : _s0_req_T_5_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ppred = _s0_req_T ? _s0_req_WIRE_0_uop_ppred : _s0_req_T_5_0_uop_ppred; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs1_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs1_busy : _s0_req_T_5_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs2_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs2_busy : _s0_req_T_5_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs3_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs3_busy : _s0_req_T_5_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ppred_busy = _s0_req_T ? _s0_req_WIRE_0_uop_ppred_busy : _s0_req_T_5_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_stale_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_stale_pdst : _s0_req_T_5_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_exception = _s0_req_T ? _s0_req_WIRE_0_uop_exception : _s0_req_T_5_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_uop_exc_cause = _s0_req_T ? _s0_req_WIRE_0_uop_exc_cause : _s0_req_T_5_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bypassable = _s0_req_T ? _s0_req_WIRE_0_uop_bypassable : _s0_req_T_5_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_mem_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_mem_cmd : _s0_req_T_5_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_mem_size = _s0_req_T ? _s0_req_WIRE_0_uop_mem_size : _s0_req_T_5_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_mem_signed = _s0_req_T ? _s0_req_WIRE_0_uop_mem_signed : _s0_req_T_5_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fence = _s0_req_T ? _s0_req_WIRE_0_uop_is_fence : _s0_req_T_5_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fencei = _s0_req_T ? _s0_req_WIRE_0_uop_is_fencei : _s0_req_T_5_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_amo = _s0_req_T ? _s0_req_WIRE_0_uop_is_amo : _s0_req_T_5_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_ldq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_ldq : _s0_req_T_5_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_stq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_stq : _s0_req_T_5_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sys_pc2epc = _s0_req_T ? _s0_req_WIRE_0_uop_is_sys_pc2epc : _s0_req_T_5_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_unique = _s0_req_T ? _s0_req_WIRE_0_uop_is_unique : _s0_req_T_5_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_flush_on_commit = _s0_req_T ? _s0_req_WIRE_0_uop_flush_on_commit : _s0_req_T_5_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ldst_is_rs1 = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_is_rs1 : _s0_req_T_5_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_ldst : _s0_req_T_5_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs1 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1 : _s0_req_T_5_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs2 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2 : _s0_req_T_5_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs3 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs3 : _s0_req_T_5_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ldst_val = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_val : _s0_req_T_5_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_dst_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_dst_rtype : _s0_req_T_5_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs1_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1_rtype : _s0_req_T_5_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs2_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2_rtype : _s0_req_T_5_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_frs3_en = _s0_req_T ? _s0_req_WIRE_0_uop_frs3_en : _s0_req_T_5_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_val = _s0_req_T ? _s0_req_WIRE_0_uop_fp_val : _s0_req_T_5_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_single = _s0_req_T ? _s0_req_WIRE_0_uop_fp_single : _s0_req_T_5_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_pf_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_pf_if : _s0_req_T_5_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ae_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ae_if : _s0_req_T_5_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ma_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ma_if : _s0_req_T_5_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_debug_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_debug_if : _s0_req_T_5_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_xcpt_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_xcpt_if : _s0_req_T_5_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_debug_fsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_fsrc : _s0_req_T_5_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_debug_tsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_tsrc : _s0_req_T_5_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] s0_req_0_addr = _s0_req_T ? _s0_req_WIRE_0_addr : _s0_req_T_5_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_data = _s0_req_T ? _s0_req_WIRE_0_data : _s0_req_T_5_0_data; // @[Decoupled.scala:51:35]
wire s0_req_0_is_hella = _s0_req_T ? _s0_req_WIRE_0_is_hella : _s0_req_T_5_0_is_hella; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_2 = _s0_type_T_1 ? 3'h3 : 3'h0; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_3 = _s0_type_T_2; // @[dcache.scala:591:21, :592:21]
wire [2:0] _s0_type_T_4 = prober_fire ? 3'h1 : _s0_type_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_5 = wb_fire ? 3'h2 : _s0_type_T_4; // @[dcache.scala:531:38, :589:21, :590:21]
wire [2:0] s0_type = _s0_type_T ? 3'h4 : _s0_type_T_5; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_2 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_3 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_4 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_5 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_6 = _s0_send_resp_or_nack_T_2 | _s0_send_resp_or_nack_T_3; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_7 = _s0_send_resp_or_nack_T_6 | _s0_send_resp_or_nack_T_4; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_8 = _s0_send_resp_or_nack_T_7 | _s0_send_resp_or_nack_T_5; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_9 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_10 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_11 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_12 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_13 = _s0_send_resp_or_nack_T_9 | _s0_send_resp_or_nack_T_10; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_14 = _s0_send_resp_or_nack_T_13 | _s0_send_resp_or_nack_T_11; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_15 = _s0_send_resp_or_nack_T_14 | _s0_send_resp_or_nack_T_12; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_16 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_17 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_18 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_19 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_20 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_21 = _s0_send_resp_or_nack_T_16 | _s0_send_resp_or_nack_T_17; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_22 = _s0_send_resp_or_nack_T_21 | _s0_send_resp_or_nack_T_18; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_23 = _s0_send_resp_or_nack_T_22 | _s0_send_resp_or_nack_T_19; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_24 = _s0_send_resp_or_nack_T_23 | _s0_send_resp_or_nack_T_20; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_25 = _s0_send_resp_or_nack_T_15 | _s0_send_resp_or_nack_T_24; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_26 = _s0_send_resp_or_nack_T_8 | _s0_send_resp_or_nack_T_25; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_27 = _s0_send_resp_or_nack_T_1 & _s0_send_resp_or_nack_T_26; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_28 = _s0_send_resp_or_nack_T_27; // @[dcache.scala:597:{16,38}]
wire _s0_send_resp_or_nack_T_29 = _s0_send_resp_or_nack_T_28; // @[dcache.scala:597:{16,117}]
wire _s0_send_resp_or_nack_WIRE_0 = _s0_send_resp_or_nack_T_29; // @[dcache.scala:597:{12,117}]
wire s0_send_resp_or_nack_0 = _s0_send_resp_or_nack_T ? s0_valid_0 : _s0_send_resp_or_nack_WIRE_0; // @[Decoupled.scala:51:35]
reg [6:0] s1_req_0_uop_uopc; // @[dcache.scala:600:32]
reg [31:0] s1_req_0_uop_inst; // @[dcache.scala:600:32]
reg [31:0] s1_req_0_uop_debug_inst; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_rvc; // @[dcache.scala:600:32]
reg [39:0] s1_req_0_uop_debug_pc; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_iq_type; // @[dcache.scala:600:32]
reg [9:0] s1_req_0_uop_fu_code; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ctrl_br_type; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_ctrl_op1_sel; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_op2_sel; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_imm_sel; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_ctrl_op_fcn; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_load; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_sta; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_std; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_iw_state; // @[dcache.scala:600:32]
reg s1_req_0_uop_iw_p1_poisoned; // @[dcache.scala:600:32]
reg s1_req_0_uop_iw_p2_poisoned; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_br; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_jalr; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_jal; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_sfb; // @[dcache.scala:600:32]
reg [7:0] s1_req_0_uop_br_mask; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_br_tag; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ftq_idx; // @[dcache.scala:600:32]
reg s1_req_0_uop_edge_inst; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_pc_lob; // @[dcache.scala:600:32]
reg s1_req_0_uop_taken; // @[dcache.scala:600:32]
reg [19:0] s1_req_0_uop_imm_packed; // @[dcache.scala:600:32]
reg [11:0] s1_req_0_uop_csr_addr; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_rob_idx; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ldq_idx; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_stq_idx; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_rxq_idx; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_pdst; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_prs1; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_prs2; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_prs3; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ppred; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs1_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs2_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs3_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_ppred_busy; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_stale_pdst; // @[dcache.scala:600:32]
reg s1_req_0_uop_exception; // @[dcache.scala:600:32]
reg [63:0] s1_req_0_uop_exc_cause; // @[dcache.scala:600:32]
reg s1_req_0_uop_bypassable; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_mem_cmd; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_mem_size; // @[dcache.scala:600:32]
reg s1_req_0_uop_mem_signed; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_fence; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_fencei; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_amo; // @[dcache.scala:600:32]
reg s1_req_0_uop_uses_ldq; // @[dcache.scala:600:32]
reg s1_req_0_uop_uses_stq; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_sys_pc2epc; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_unique; // @[dcache.scala:600:32]
reg s1_req_0_uop_flush_on_commit; // @[dcache.scala:600:32]
reg s1_req_0_uop_ldst_is_rs1; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_ldst; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs1; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs2; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs3; // @[dcache.scala:600:32]
reg s1_req_0_uop_ldst_val; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_dst_rtype; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_lrs1_rtype; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_lrs2_rtype; // @[dcache.scala:600:32]
reg s1_req_0_uop_frs3_en; // @[dcache.scala:600:32]
reg s1_req_0_uop_fp_val; // @[dcache.scala:600:32]
reg s1_req_0_uop_fp_single; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_pf_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_ae_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_ma_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_bp_debug_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_bp_xcpt_if; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_debug_fsrc; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_debug_tsrc; // @[dcache.scala:600:32]
reg [39:0] s1_req_0_addr; // @[dcache.scala:600:32]
reg [63:0] s1_req_0_data; // @[dcache.scala:600:32]
reg s1_req_0_is_hella; // @[dcache.scala:600:32]
wire [7:0] _s1_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _s1_req_0_uop_br_mask_T_1 = s0_req_0_uop_br_mask & _s1_req_0_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire _s2_store_failed_T_2; // @[dcache.scala:742:67]
wire s2_store_failed; // @[dcache.scala:603:29]
wire [7:0] _s1_valid_T = io_lsu_brupdate_b1_mispredict_mask_0 & s0_req_0_uop_br_mask; // @[util.scala:118:51]
wire _s1_valid_T_1 = |_s1_valid_T; // @[util.scala:118:{51,59}]
wire _s1_valid_T_2 = ~_s1_valid_T_1; // @[util.scala:118:59]
wire _s1_valid_T_3 = s0_valid_0 & _s1_valid_T_2; // @[dcache.scala:579:21, :605:74, :606:26]
wire _s1_valid_T_4 = io_lsu_exception_0 & s0_req_0_uop_uses_ldq; // @[dcache.scala:413:7, :582:21, :607:45]
wire _s1_valid_T_5 = ~_s1_valid_T_4; // @[dcache.scala:607:{26,45}]
wire _s1_valid_T_6 = _s1_valid_T_3 & _s1_valid_T_5; // @[dcache.scala:605:74, :606:76, :607:26]
wire _s1_valid_T_8 = s2_store_failed & _s1_valid_T_7; // @[Decoupled.scala:51:35]
wire _s1_valid_T_9 = _s1_valid_T_8 & s0_req_0_uop_uses_stq; // @[dcache.scala:582:21, :608:{44,63}]
wire _s1_valid_T_10 = ~_s1_valid_T_9; // @[dcache.scala:608:{26,63}]
wire _s1_valid_T_11 = _s1_valid_T_6 & _s1_valid_T_10; // @[dcache.scala:606:76, :607:74, :608:26]
reg s1_valid_REG; // @[dcache.scala:605:25]
wire s1_valid_0 = s1_valid_REG; // @[dcache.scala:427:49, :605:25]
reg REG; // @[dcache.scala:611:43]
reg REG_1; // @[dcache.scala:611:72]
wire [5:0] _s1_nack_T = s1_req_0_addr[11:6]; // @[dcache.scala:600:32, :613:43]
wire [5:0] _s1_wb_idx_matches_T = s1_req_0_addr[11:6]; // @[dcache.scala:600:32, :613:43, :630:52]
wire _s1_nack_T_1 = _s1_nack_T == _prober_io_meta_write_bits_idx; // @[dcache.scala:432:22, :613:{43,59}]
wire _s1_nack_T_2 = ~_prober_io_req_ready; // @[dcache.scala:432:22, :613:96]
wire s1_nack_0 = _s1_nack_T_1 & _s1_nack_T_2; // @[dcache.scala:613:{59,93,96}]
wire _s2_nack_hit_WIRE_0 = s1_nack_0; // @[dcache.scala:613:93, :722:39]
reg s1_send_resp_or_nack_0; // @[dcache.scala:614:37]
reg [2:0] s1_type; // @[dcache.scala:615:32]
reg [3:0] s1_mshr_meta_read_way_en; // @[dcache.scala:617:41]
reg [3:0] s1_replay_way_en; // @[dcache.scala:618:41]
reg [3:0] s1_wb_way_en; // @[dcache.scala:619:41]
wire [27:0] _s1_tag_eq_way_T = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_2 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_4 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_6 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire _s1_tag_eq_way_T_1 = {8'h0, _meta_0_io_resp_0_tag} == _s1_tag_eq_way_T; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_0 = _s1_tag_eq_way_T_1; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_3 = {8'h0, _meta_0_io_resp_1_tag} == _s1_tag_eq_way_T_2; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_1 = _s1_tag_eq_way_T_3; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_5 = {8'h0, _meta_0_io_resp_2_tag} == _s1_tag_eq_way_T_4; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_2 = _s1_tag_eq_way_T_5; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_7 = {8'h0, _meta_0_io_resp_3_tag} == _s1_tag_eq_way_T_6; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_3 = _s1_tag_eq_way_T_7; // @[dcache.scala:622:47, :623:79]
wire [1:0] s1_tag_eq_way_lo = {_s1_tag_eq_way_WIRE_1, _s1_tag_eq_way_WIRE_0}; // @[dcache.scala:622:47, :623:110]
wire [1:0] s1_tag_eq_way_hi = {_s1_tag_eq_way_WIRE_3, _s1_tag_eq_way_WIRE_2}; // @[dcache.scala:622:47, :623:110]
wire [3:0] _s1_tag_eq_way_T_8 = {s1_tag_eq_way_hi, s1_tag_eq_way_lo}; // @[dcache.scala:623:110]
wire [3:0] s1_tag_eq_way_0 = _s1_tag_eq_way_T_8; // @[dcache.scala:427:49, :623:110]
wire _s1_tag_match_way_T = s1_type == 3'h0; // @[dcache.scala:615:32, :625:38]
wire _s1_tag_match_way_T_1 = s1_type == 3'h2; // @[dcache.scala:615:32, :626:38]
wire _s1_tag_match_way_T_2 = s1_type == 3'h3; // @[dcache.scala:615:32, :627:38]
wire _s1_tag_match_way_T_3 = s1_tag_eq_way_0[0]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_4 = |_meta_0_io_resp_0_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_5 = _s1_tag_match_way_T_3 & _s1_tag_match_way_T_4; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_0 = _s1_tag_match_way_T_5; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_6 = s1_tag_eq_way_0[1]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_7 = |_meta_0_io_resp_1_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_8 = _s1_tag_match_way_T_6 & _s1_tag_match_way_T_7; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_1 = _s1_tag_match_way_T_8; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_9 = s1_tag_eq_way_0[2]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_10 = |_meta_0_io_resp_2_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_11 = _s1_tag_match_way_T_9 & _s1_tag_match_way_T_10; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_2 = _s1_tag_match_way_T_11; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_12 = s1_tag_eq_way_0[3]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_13 = |_meta_0_io_resp_3_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_14 = _s1_tag_match_way_T_12 & _s1_tag_match_way_T_13; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_3 = _s1_tag_match_way_T_14; // @[dcache.scala:622:47, :628:67]
wire [1:0] s1_tag_match_way_lo = {_s1_tag_match_way_WIRE_1, _s1_tag_match_way_WIRE_0}; // @[dcache.scala:622:47, :628:104]
wire [1:0] s1_tag_match_way_hi = {_s1_tag_match_way_WIRE_3, _s1_tag_match_way_WIRE_2}; // @[dcache.scala:622:47, :628:104]
wire [3:0] _s1_tag_match_way_T_15 = {s1_tag_match_way_hi, s1_tag_match_way_lo}; // @[dcache.scala:628:104]
wire [3:0] _s1_tag_match_way_T_16 = _s1_tag_match_way_T_2 ? s1_mshr_meta_read_way_en : _s1_tag_match_way_T_15; // @[dcache.scala:617:41, :627:{29,38}, :628:104]
wire [3:0] _s1_tag_match_way_T_17 = _s1_tag_match_way_T_1 ? s1_wb_way_en : _s1_tag_match_way_T_16; // @[dcache.scala:619:41, :626:{29,38}, :627:29]
wire [3:0] _s1_tag_match_way_T_18 = _s1_tag_match_way_T ? s1_replay_way_en : _s1_tag_match_way_T_17; // @[dcache.scala:618:41, :625:{29,38}, :626:29]
wire [3:0] s1_tag_match_way_0 = _s1_tag_match_way_T_18; // @[dcache.scala:427:49, :625:29]
wire _s1_wb_idx_matches_T_1 = _s1_wb_idx_matches_T == _wb_io_idx_bits; // @[dcache.scala:431:18, :630:{52,79}]
wire _s1_wb_idx_matches_T_2 = _s1_wb_idx_matches_T_1 & _wb_io_idx_valid; // @[dcache.scala:431:18, :630:{79,99}]
wire s1_wb_idx_matches_0 = _s1_wb_idx_matches_T_2; // @[dcache.scala:427:49, :630:99]
reg [6:0] s2_req_0_uop_uopc; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_uopc = s2_req_0_uop_uopc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uopc = s2_req_0_uop_uopc; // @[util.scala:101:23]
reg [31:0] s2_req_0_uop_inst; // @[dcache.scala:632:25]
wire [31:0] cache_resp_0_bits_uop_inst = s2_req_0_uop_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_inst = s2_req_0_uop_inst; // @[util.scala:101:23]
reg [31:0] s2_req_0_uop_debug_inst; // @[dcache.scala:632:25]
wire [31:0] cache_resp_0_bits_uop_debug_inst = s2_req_0_uop_debug_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_inst = s2_req_0_uop_debug_inst; // @[util.scala:101:23]
reg s2_req_0_uop_is_rvc; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_rvc = s2_req_0_uop_is_rvc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_rvc = s2_req_0_uop_is_rvc; // @[util.scala:101:23]
reg [39:0] s2_req_0_uop_debug_pc; // @[dcache.scala:632:25]
wire [39:0] cache_resp_0_bits_uop_debug_pc = s2_req_0_uop_debug_pc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_pc = s2_req_0_uop_debug_pc; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_iq_type; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_iq_type = s2_req_0_uop_iq_type; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iq_type = s2_req_0_uop_iq_type; // @[util.scala:101:23]
reg [9:0] s2_req_0_uop_fu_code; // @[dcache.scala:632:25]
wire [9:0] cache_resp_0_bits_uop_fu_code = s2_req_0_uop_fu_code; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fu_code = s2_req_0_uop_fu_code; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ctrl_br_type; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_ctrl_op1_sel; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_op2_sel; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_imm_sel; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_ctrl_op_fcn; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_load; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_sta; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_std; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_iw_state; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_iw_state = s2_req_0_uop_iw_state; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_state = s2_req_0_uop_iw_state; // @[util.scala:101:23]
reg s2_req_0_uop_iw_p1_poisoned; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned; // @[util.scala:101:23]
reg s2_req_0_uop_iw_p2_poisoned; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned; // @[util.scala:101:23]
reg s2_req_0_uop_is_br; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_br = s2_req_0_uop_is_br; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_br = s2_req_0_uop_is_br; // @[util.scala:101:23]
reg s2_req_0_uop_is_jalr; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_jalr = s2_req_0_uop_is_jalr; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_jalr = s2_req_0_uop_is_jalr; // @[util.scala:101:23]
reg s2_req_0_uop_is_jal; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_jal = s2_req_0_uop_is_jal; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_jal = s2_req_0_uop_is_jal; // @[util.scala:101:23]
reg s2_req_0_uop_is_sfb; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_sfb = s2_req_0_uop_is_sfb; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_sfb = s2_req_0_uop_is_sfb; // @[util.scala:101:23]
reg [7:0] s2_req_0_uop_br_mask; // @[dcache.scala:632:25]
wire [7:0] cache_resp_0_bits_uop_br_mask = s2_req_0_uop_br_mask; // @[dcache.scala:632:25, :833:26]
reg [2:0] s2_req_0_uop_br_tag; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_br_tag = s2_req_0_uop_br_tag; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_br_tag = s2_req_0_uop_br_tag; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ftq_idx; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ftq_idx = s2_req_0_uop_ftq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ftq_idx = s2_req_0_uop_ftq_idx; // @[util.scala:101:23]
reg s2_req_0_uop_edge_inst; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_edge_inst = s2_req_0_uop_edge_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_edge_inst = s2_req_0_uop_edge_inst; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_pc_lob; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_pc_lob = s2_req_0_uop_pc_lob; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_pc_lob = s2_req_0_uop_pc_lob; // @[util.scala:101:23]
reg s2_req_0_uop_taken; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_taken = s2_req_0_uop_taken; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_taken = s2_req_0_uop_taken; // @[util.scala:101:23]
reg [19:0] s2_req_0_uop_imm_packed; // @[dcache.scala:632:25]
wire [19:0] cache_resp_0_bits_uop_imm_packed = s2_req_0_uop_imm_packed; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_imm_packed = s2_req_0_uop_imm_packed; // @[util.scala:101:23]
reg [11:0] s2_req_0_uop_csr_addr; // @[dcache.scala:632:25]
wire [11:0] cache_resp_0_bits_uop_csr_addr = s2_req_0_uop_csr_addr; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_csr_addr = s2_req_0_uop_csr_addr; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_rob_idx; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_rob_idx = s2_req_0_uop_rob_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_rob_idx = s2_req_0_uop_rob_idx; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ldq_idx; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ldq_idx = s2_req_0_uop_ldq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldq_idx = s2_req_0_uop_ldq_idx; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_stq_idx; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_stq_idx = s2_req_0_uop_stq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_stq_idx = s2_req_0_uop_stq_idx; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_rxq_idx; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_rxq_idx = s2_req_0_uop_rxq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_rxq_idx = s2_req_0_uop_rxq_idx; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_pdst; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_pdst = s2_req_0_uop_pdst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_pdst = s2_req_0_uop_pdst; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_prs1; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_prs1 = s2_req_0_uop_prs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs1 = s2_req_0_uop_prs1; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_prs2; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_prs2 = s2_req_0_uop_prs2; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs2 = s2_req_0_uop_prs2; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_prs3; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_prs3 = s2_req_0_uop_prs3; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs3 = s2_req_0_uop_prs3; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ppred; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ppred = s2_req_0_uop_ppred; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ppred = s2_req_0_uop_ppred; // @[util.scala:101:23]
reg s2_req_0_uop_prs1_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs1_busy = s2_req_0_uop_prs1_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs1_busy = s2_req_0_uop_prs1_busy; // @[util.scala:101:23]
reg s2_req_0_uop_prs2_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs2_busy = s2_req_0_uop_prs2_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs2_busy = s2_req_0_uop_prs2_busy; // @[util.scala:101:23]
reg s2_req_0_uop_prs3_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs3_busy = s2_req_0_uop_prs3_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs3_busy = s2_req_0_uop_prs3_busy; // @[util.scala:101:23]
reg s2_req_0_uop_ppred_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ppred_busy = s2_req_0_uop_ppred_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ppred_busy = s2_req_0_uop_ppred_busy; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_stale_pdst; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_stale_pdst = s2_req_0_uop_stale_pdst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_stale_pdst = s2_req_0_uop_stale_pdst; // @[util.scala:101:23]
reg s2_req_0_uop_exception; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_exception = s2_req_0_uop_exception; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_exception = s2_req_0_uop_exception; // @[util.scala:101:23]
reg [63:0] s2_req_0_uop_exc_cause; // @[dcache.scala:632:25]
wire [63:0] cache_resp_0_bits_uop_exc_cause = s2_req_0_uop_exc_cause; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_exc_cause = s2_req_0_uop_exc_cause; // @[util.scala:101:23]
reg s2_req_0_uop_bypassable; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bypassable = s2_req_0_uop_bypassable; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bypassable = s2_req_0_uop_bypassable; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_mem_cmd; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_mem_cmd = s2_req_0_uop_mem_cmd; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_cmd = s2_req_0_uop_mem_cmd; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_mem_size; // @[dcache.scala:632:25]
wire [1:0] size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18]
wire [1:0] cache_resp_0_bits_uop_mem_size = s2_req_0_uop_mem_size; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_size = s2_req_0_uop_mem_size; // @[util.scala:101:23]
wire [1:0] amoalu_io_mask_size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18]
reg s2_req_0_uop_mem_signed; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_mem_signed = s2_req_0_uop_mem_signed; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_signed = s2_req_0_uop_mem_signed; // @[util.scala:101:23]
reg s2_req_0_uop_is_fence; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_fence = s2_req_0_uop_is_fence; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_fence = s2_req_0_uop_is_fence; // @[util.scala:101:23]
reg s2_req_0_uop_is_fencei; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_fencei = s2_req_0_uop_is_fencei; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_fencei = s2_req_0_uop_is_fencei; // @[util.scala:101:23]
reg s2_req_0_uop_is_amo; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_amo = s2_req_0_uop_is_amo; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_amo = s2_req_0_uop_is_amo; // @[util.scala:101:23]
reg s2_req_0_uop_uses_ldq; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_uses_ldq = s2_req_0_uop_uses_ldq; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uses_ldq = s2_req_0_uop_uses_ldq; // @[util.scala:101:23]
reg s2_req_0_uop_uses_stq; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_uses_stq = s2_req_0_uop_uses_stq; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uses_stq = s2_req_0_uop_uses_stq; // @[util.scala:101:23]
reg s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc; // @[util.scala:101:23]
reg s2_req_0_uop_is_unique; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_unique = s2_req_0_uop_is_unique; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_unique = s2_req_0_uop_is_unique; // @[util.scala:101:23]
reg s2_req_0_uop_flush_on_commit; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_flush_on_commit = s2_req_0_uop_flush_on_commit; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_flush_on_commit = s2_req_0_uop_flush_on_commit; // @[util.scala:101:23]
reg s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_ldst; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_ldst = s2_req_0_uop_ldst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst = s2_req_0_uop_ldst; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs1; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs1 = s2_req_0_uop_lrs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs1 = s2_req_0_uop_lrs1; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs2; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs2 = s2_req_0_uop_lrs2; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs2 = s2_req_0_uop_lrs2; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs3; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs3 = s2_req_0_uop_lrs3; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs3 = s2_req_0_uop_lrs3; // @[util.scala:101:23]
reg s2_req_0_uop_ldst_val; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ldst_val = s2_req_0_uop_ldst_val; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst_val = s2_req_0_uop_ldst_val; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_dst_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_dst_rtype = s2_req_0_uop_dst_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_dst_rtype = s2_req_0_uop_dst_rtype; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_lrs1_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_lrs2_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype; // @[util.scala:101:23]
reg s2_req_0_uop_frs3_en; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_frs3_en = s2_req_0_uop_frs3_en; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_frs3_en = s2_req_0_uop_frs3_en; // @[util.scala:101:23]
reg s2_req_0_uop_fp_val; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_fp_val = s2_req_0_uop_fp_val; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fp_val = s2_req_0_uop_fp_val; // @[util.scala:101:23]
reg s2_req_0_uop_fp_single; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_fp_single = s2_req_0_uop_fp_single; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fp_single = s2_req_0_uop_fp_single; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if; // @[util.scala:101:23]
reg s2_req_0_uop_bp_debug_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bp_debug_if = s2_req_0_uop_bp_debug_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bp_debug_if = s2_req_0_uop_bp_debug_if; // @[util.scala:101:23]
reg s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_debug_fsrc; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_debug_fsrc = s2_req_0_uop_debug_fsrc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_fsrc = s2_req_0_uop_debug_fsrc; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_debug_tsrc; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_debug_tsrc = s2_req_0_uop_debug_tsrc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_tsrc = s2_req_0_uop_debug_tsrc; // @[util.scala:101:23]
reg [39:0] s2_req_0_addr; // @[dcache.scala:632:25]
assign io_lsu_nack_0_bits_out_addr = s2_req_0_addr; // @[util.scala:101:23]
reg [63:0] s2_req_0_data; // @[dcache.scala:632:25]
assign io_lsu_nack_0_bits_out_data = s2_req_0_data; // @[util.scala:101:23]
reg s2_req_0_is_hella; // @[dcache.scala:632:25]
wire cache_resp_0_bits_is_hella = s2_req_0_is_hella; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_is_hella = s2_req_0_is_hella; // @[util.scala:101:23]
reg [2:0] s2_type; // @[dcache.scala:633:25]
wire _s2_valid_T = ~io_lsu_s1_kill_0_0; // @[dcache.scala:413:7, :636:26]
wire _s2_valid_T_1 = s1_valid_0 & _s2_valid_T; // @[dcache.scala:427:49, :635:39, :636:26]
wire [7:0] _s2_valid_T_2 = io_lsu_brupdate_b1_mispredict_mask_0 & s1_req_0_uop_br_mask; // @[util.scala:118:51]
wire _s2_valid_T_3 = |_s2_valid_T_2; // @[util.scala:118:{51,59}]
wire _s2_valid_T_4 = ~_s2_valid_T_3; // @[util.scala:118:59]
wire _s2_valid_T_5 = _s2_valid_T_1 & _s2_valid_T_4; // @[dcache.scala:635:39, :636:45, :637:26]
wire _s2_valid_T_6 = io_lsu_exception_0 & s1_req_0_uop_uses_ldq; // @[dcache.scala:413:7, :600:32, :638:45]
wire _s2_valid_T_7 = ~_s2_valid_T_6; // @[dcache.scala:638:{26,45}]
wire _s2_valid_T_8 = _s2_valid_T_5 & _s2_valid_T_7; // @[dcache.scala:636:45, :637:76, :638:26]
wire _s2_valid_T_9 = s1_type == 3'h4; // @[dcache.scala:615:32, :639:56]
wire _s2_valid_T_10 = s2_store_failed & _s2_valid_T_9; // @[dcache.scala:603:29, :639:{44,56}]
wire _s2_valid_T_11 = _s2_valid_T_10 & s1_req_0_uop_uses_stq; // @[dcache.scala:600:32, :639:{44,67}]
wire _s2_valid_T_12 = ~_s2_valid_T_11; // @[dcache.scala:639:{26,67}]
wire _s2_valid_T_13 = _s2_valid_T_8 & _s2_valid_T_12; // @[dcache.scala:637:76, :638:72, :639:26]
reg s2_valid_REG; // @[dcache.scala:635:26]
wire s2_valid_0 = s2_valid_REG; // @[dcache.scala:427:49, :635:26]
wire [7:0] _s2_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _s2_req_0_uop_br_mask_T_1 = s1_req_0_uop_br_mask & _s2_req_0_uop_br_mask_T; // @[util.scala:85:{25,27}]
reg [3:0] s2_tag_match_way_0; // @[dcache.scala:643:33]
wire s2_tag_match_0 = |s2_tag_match_way_0; // @[dcache.scala:643:33, :644:49]
reg [1:0] s2_hit_state_REG_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_0_state = s2_hit_state_REG_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_1_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_1_state_0 = s2_hit_state_REG_1_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_2_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_2_state = s2_hit_state_REG_2_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_3_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_3_state = s2_hit_state_REG_3_state; // @[dcache.scala:622:47, :645:93]
wire _s2_hit_state_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire [1:0] _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_hit_state_0_state = _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_4 = _s2_hit_state_T ? _s2_hit_state_WIRE_0_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_5 = _s2_hit_state_T_1 ? _s2_hit_state_WIRE_1_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_6 = _s2_hit_state_T_2 ? _s2_hit_state_WIRE_2_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_7 = _s2_hit_state_T_3 ? _s2_hit_state_WIRE_3_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_8 = _s2_hit_state_T_4 | _s2_hit_state_T_5; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_9 = _s2_hit_state_T_8 | _s2_hit_state_T_6; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_10 = _s2_hit_state_T_9 | _s2_hit_state_T_7; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_2 = _s2_hit_state_T_10; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_1_state = _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] mshrs_io_req_0_bits_old_meta_meta_coh_state = s2_hit_state_0_state; // @[HellaCache.scala:305:20]
wire _GEN_2 = s2_req_0_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_send_resp_T_3; // @[Consts.scala:90:32]
assign _s2_send_resp_T_3 = _GEN_2; // @[Consts.scala:90:32]
wire _mshrs_io_req_0_valid_T_50; // @[Consts.scala:90:32]
assign _mshrs_io_req_0_valid_T_50 = _GEN_2; // @[Consts.scala:90:32]
wire _s3_valid_T_1; // @[Consts.scala:90:32]
assign _s3_valid_T_1 = _GEN_2; // @[Consts.scala:90:32]
wire _GEN_3 = s2_req_0_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_send_resp_T_4; // @[Consts.scala:90:49]
assign _s2_send_resp_T_4 = _GEN_3; // @[Consts.scala:90:49]
wire _mshrs_io_req_0_valid_T_51; // @[Consts.scala:90:49]
assign _mshrs_io_req_0_valid_T_51 = _GEN_3; // @[Consts.scala:90:49]
wire _s3_valid_T_2; // @[Consts.scala:90:49]
assign _s3_valid_T_2 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_2 = _s2_has_permission_r_c_cat_T | _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_4 = s2_req_0_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_sc_T; // @[dcache.scala:664:37]
assign _s2_sc_T = _GEN_4; // @[Consts.scala:90:66]
wire _s2_send_resp_T_6; // @[Consts.scala:90:66]
assign _s2_send_resp_T_6 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_send_resp_T_30; // @[package.scala:16:47]
assign _s2_send_resp_T_30 = _GEN_4; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_27 = _GEN_4; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_53; // @[Consts.scala:90:66]
assign _mshrs_io_req_0_valid_T_53 = _GEN_4; // @[Consts.scala:90:66]
wire _s3_valid_T_4; // @[Consts.scala:90:66]
assign _s3_valid_T_4 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_4 = _s2_has_permission_r_c_cat_T_2 | _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_5 = s2_req_0_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_resp_T_8; // @[package.scala:16:47]
assign _s2_send_resp_T_8 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_resp_T_34; // @[package.scala:16:47]
assign _s2_send_resp_T_34 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_31; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_31 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_55; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_55 = _GEN_5; // @[package.scala:16:47]
wire _s3_valid_T_6; // @[package.scala:16:47]
assign _s3_valid_T_6 = _GEN_5; // @[package.scala:16:47]
wire _GEN_6 = s2_req_0_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_resp_T_9; // @[package.scala:16:47]
assign _s2_send_resp_T_9 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_resp_T_35; // @[package.scala:16:47]
assign _s2_send_resp_T_35 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_32; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_32 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_56; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_56 = _GEN_6; // @[package.scala:16:47]
wire _s3_valid_T_7; // @[package.scala:16:47]
assign _s3_valid_T_7 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = s2_req_0_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_resp_T_10; // @[package.scala:16:47]
assign _s2_send_resp_T_10 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_resp_T_36; // @[package.scala:16:47]
assign _s2_send_resp_T_36 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_33; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_33 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_57; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_57 = _GEN_7; // @[package.scala:16:47]
wire _s3_valid_T_8; // @[package.scala:16:47]
assign _s3_valid_T_8 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = s2_req_0_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_resp_T_11; // @[package.scala:16:47]
assign _s2_send_resp_T_11 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_resp_T_37; // @[package.scala:16:47]
assign _s2_send_resp_T_37 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_34 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_58 = _GEN_8; // @[package.scala:16:47]
wire _s3_valid_T_9; // @[package.scala:16:47]
assign _s3_valid_T_9 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_9 = _s2_has_permission_r_c_cat_T_5 | _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_10 = _s2_has_permission_r_c_cat_T_9 | _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_11 = _s2_has_permission_r_c_cat_T_10 | _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_9 = s2_req_0_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_resp_T_15; // @[package.scala:16:47]
assign _s2_send_resp_T_15 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_resp_T_41; // @[package.scala:16:47]
assign _s2_send_resp_T_41 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_38; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_38 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_62; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_62 = _GEN_9; // @[package.scala:16:47]
wire _s3_valid_T_13; // @[package.scala:16:47]
assign _s3_valid_T_13 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = s2_req_0_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_resp_T_16; // @[package.scala:16:47]
assign _s2_send_resp_T_16 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_resp_T_42; // @[package.scala:16:47]
assign _s2_send_resp_T_42 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_39; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_39 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_63; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_63 = _GEN_10; // @[package.scala:16:47]
wire _s3_valid_T_14; // @[package.scala:16:47]
assign _s3_valid_T_14 = _GEN_10; // @[package.scala:16:47]
wire _GEN_11 = s2_req_0_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_resp_T_17; // @[package.scala:16:47]
assign _s2_send_resp_T_17 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_resp_T_43; // @[package.scala:16:47]
assign _s2_send_resp_T_43 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_40; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_40 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_64; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_64 = _GEN_11; // @[package.scala:16:47]
wire _s3_valid_T_15; // @[package.scala:16:47]
assign _s3_valid_T_15 = _GEN_11; // @[package.scala:16:47]
wire _GEN_12 = s2_req_0_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_resp_T_18; // @[package.scala:16:47]
assign _s2_send_resp_T_18 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_resp_T_44; // @[package.scala:16:47]
assign _s2_send_resp_T_44 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_41; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_41 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_65; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_65 = _GEN_12; // @[package.scala:16:47]
wire _s3_valid_T_16; // @[package.scala:16:47]
assign _s3_valid_T_16 = _GEN_12; // @[package.scala:16:47]
wire _GEN_13 = s2_req_0_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_resp_T_19; // @[package.scala:16:47]
assign _s2_send_resp_T_19 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_resp_T_45; // @[package.scala:16:47]
assign _s2_send_resp_T_45 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_42; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_42 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_66; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_66 = _GEN_13; // @[package.scala:16:47]
wire _s3_valid_T_17; // @[package.scala:16:47]
assign _s3_valid_T_17 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_17 = _s2_has_permission_r_c_cat_T_12 | _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_18 = _s2_has_permission_r_c_cat_T_17 | _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_19 = _s2_has_permission_r_c_cat_T_18 | _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_20 = _s2_has_permission_r_c_cat_T_19 | _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_21 = _s2_has_permission_r_c_cat_T_11 | _s2_has_permission_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_22 = _s2_has_permission_r_c_cat_T_4 | _s2_has_permission_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_has_permission_r_c_cat_T_25 = _s2_has_permission_r_c_cat_T_23 | _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_has_permission_r_c_cat_T_27 = _s2_has_permission_r_c_cat_T_25 | _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_has_permission_r_c_cat_T_32 = _s2_has_permission_r_c_cat_T_28 | _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_33 = _s2_has_permission_r_c_cat_T_32 | _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_34 = _s2_has_permission_r_c_cat_T_33 | _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_40 = _s2_has_permission_r_c_cat_T_35 | _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_41 = _s2_has_permission_r_c_cat_T_40 | _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_42 = _s2_has_permission_r_c_cat_T_41 | _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_43 = _s2_has_permission_r_c_cat_T_42 | _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_44 = _s2_has_permission_r_c_cat_T_34 | _s2_has_permission_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_45 = _s2_has_permission_r_c_cat_T_27 | _s2_has_permission_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_14 = s2_req_0_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_has_permission_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_new_hit_state_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _mshrs_io_req_0_valid_T_22; // @[Consts.scala:88:52]
assign _mshrs_io_req_0_valid_T_22 = _GEN_14; // @[Consts.scala:88:52, :91:54]
wire _s2_has_permission_r_c_cat_T_47 = _s2_has_permission_r_c_cat_T_45 | _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_15 = s2_req_0_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_has_permission_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_new_hit_state_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_lr_T; // @[dcache.scala:663:37]
assign _s2_lr_T = _GEN_15; // @[Consts.scala:91:71]
wire _s2_send_resp_T_29; // @[package.scala:16:47]
assign _s2_send_resp_T_29 = _GEN_15; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_26; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_26 = _GEN_15; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_49 = _s2_has_permission_r_c_cat_T_47 | _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_has_permission_r_c = {_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_has_permission_r_T = {s2_has_permission_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_has_permission_r_T_25 = _s2_has_permission_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_27 = {1'h0, _s2_has_permission_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_28 = _s2_has_permission_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_30 = _s2_has_permission_r_T_28 ? 2'h2 : _s2_has_permission_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_31 = _s2_has_permission_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_33 = _s2_has_permission_r_T_31 ? 2'h1 : _s2_has_permission_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_34 = _s2_has_permission_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_36 = _s2_has_permission_r_T_34 ? 2'h2 : _s2_has_permission_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_37 = _s2_has_permission_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_39 = _s2_has_permission_r_T_37 ? 2'h0 : _s2_has_permission_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_40 = _s2_has_permission_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_41 = _s2_has_permission_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_42 = _s2_has_permission_r_T_40 ? 2'h3 : _s2_has_permission_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_43 = &_s2_has_permission_r_T; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_44 = _s2_has_permission_r_T_43 | _s2_has_permission_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_45 = _s2_has_permission_r_T_43 ? 2'h3 : _s2_has_permission_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_46 = _s2_has_permission_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_47 = _s2_has_permission_r_T_46 | _s2_has_permission_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_48 = _s2_has_permission_r_T_46 ? 2'h2 : _s2_has_permission_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_49 = _s2_has_permission_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_50 = _s2_has_permission_r_T_49 | _s2_has_permission_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_51 = _s2_has_permission_r_T_49 ? 2'h3 : _s2_has_permission_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_52 = _s2_has_permission_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_53 = _s2_has_permission_r_T_52 | _s2_has_permission_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_54 = _s2_has_permission_r_T_52 ? 2'h1 : _s2_has_permission_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_55 = _s2_has_permission_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_56 = _s2_has_permission_r_T_55 | _s2_has_permission_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_57 = _s2_has_permission_r_T_55 ? 2'h2 : _s2_has_permission_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_58 = _s2_has_permission_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_has_permission_r_1 = _s2_has_permission_r_T_58 | _s2_has_permission_r_T_56; // @[Misc.scala:35:9, :49:20]
wire s2_has_permission_0 = s2_has_permission_r_1; // @[Misc.scala:35:9]
wire [1:0] s2_has_permission_r_2 = _s2_has_permission_r_T_58 ? 2'h3 : _s2_has_permission_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_has_permission_meta_state = s2_has_permission_r_2; // @[Misc.scala:35:36]
wire _s2_new_hit_state_r_c_cat_T_2 = _s2_new_hit_state_r_c_cat_T | _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_4 = _s2_new_hit_state_r_c_cat_T_2 | _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_9 = _s2_new_hit_state_r_c_cat_T_5 | _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_10 = _s2_new_hit_state_r_c_cat_T_9 | _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_11 = _s2_new_hit_state_r_c_cat_T_10 | _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_17 = _s2_new_hit_state_r_c_cat_T_12 | _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_18 = _s2_new_hit_state_r_c_cat_T_17 | _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_19 = _s2_new_hit_state_r_c_cat_T_18 | _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_20 = _s2_new_hit_state_r_c_cat_T_19 | _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_21 = _s2_new_hit_state_r_c_cat_T_11 | _s2_new_hit_state_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_22 = _s2_new_hit_state_r_c_cat_T_4 | _s2_new_hit_state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_25 = _s2_new_hit_state_r_c_cat_T_23 | _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_27 = _s2_new_hit_state_r_c_cat_T_25 | _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_32 = _s2_new_hit_state_r_c_cat_T_28 | _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_33 = _s2_new_hit_state_r_c_cat_T_32 | _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_34 = _s2_new_hit_state_r_c_cat_T_33 | _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_40 = _s2_new_hit_state_r_c_cat_T_35 | _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_41 = _s2_new_hit_state_r_c_cat_T_40 | _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_42 = _s2_new_hit_state_r_c_cat_T_41 | _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_43 = _s2_new_hit_state_r_c_cat_T_42 | _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_44 = _s2_new_hit_state_r_c_cat_T_34 | _s2_new_hit_state_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_45 = _s2_new_hit_state_r_c_cat_T_27 | _s2_new_hit_state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_47 = _s2_new_hit_state_r_c_cat_T_45 | _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _s2_new_hit_state_r_c_cat_T_49 = _s2_new_hit_state_r_c_cat_T_47 | _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_new_hit_state_r_c = {_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_new_hit_state_r_T = {s2_new_hit_state_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_new_hit_state_r_T_25 = _s2_new_hit_state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_27 = {1'h0, _s2_new_hit_state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_28 = _s2_new_hit_state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_30 = _s2_new_hit_state_r_T_28 ? 2'h2 : _s2_new_hit_state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_31 = _s2_new_hit_state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_33 = _s2_new_hit_state_r_T_31 ? 2'h1 : _s2_new_hit_state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_34 = _s2_new_hit_state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_36 = _s2_new_hit_state_r_T_34 ? 2'h2 : _s2_new_hit_state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_37 = _s2_new_hit_state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_39 = _s2_new_hit_state_r_T_37 ? 2'h0 : _s2_new_hit_state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_40 = _s2_new_hit_state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_41 = _s2_new_hit_state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_42 = _s2_new_hit_state_r_T_40 ? 2'h3 : _s2_new_hit_state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_43 = &_s2_new_hit_state_r_T; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_44 = _s2_new_hit_state_r_T_43 | _s2_new_hit_state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_45 = _s2_new_hit_state_r_T_43 ? 2'h3 : _s2_new_hit_state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_46 = _s2_new_hit_state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_47 = _s2_new_hit_state_r_T_46 | _s2_new_hit_state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_48 = _s2_new_hit_state_r_T_46 ? 2'h2 : _s2_new_hit_state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_49 = _s2_new_hit_state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_50 = _s2_new_hit_state_r_T_49 | _s2_new_hit_state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_51 = _s2_new_hit_state_r_T_49 ? 2'h3 : _s2_new_hit_state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_52 = _s2_new_hit_state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_53 = _s2_new_hit_state_r_T_52 | _s2_new_hit_state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_54 = _s2_new_hit_state_r_T_52 ? 2'h1 : _s2_new_hit_state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_55 = _s2_new_hit_state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_56 = _s2_new_hit_state_r_T_55 | _s2_new_hit_state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_57 = _s2_new_hit_state_r_T_55 ? 2'h2 : _s2_new_hit_state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_58 = _s2_new_hit_state_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_new_hit_state_r_1 = _s2_new_hit_state_r_T_58 | _s2_new_hit_state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] s2_new_hit_state_r_2 = _s2_new_hit_state_r_T_58 ? 2'h3 : _s2_new_hit_state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_new_hit_state_meta_state = s2_new_hit_state_r_2; // @[Misc.scala:35:36]
wire [1:0] s2_new_hit_state_0_state = s2_new_hit_state_meta_state; // @[Metadata.scala:160:20]
wire _s2_hit_T = s2_tag_match_0 & s2_has_permission_0; // @[dcache.scala:427:49, :644:49, :649:47]
wire _s2_hit_T_1 = s2_hit_state_0_state == s2_new_hit_state_0_state; // @[Metadata.scala:46:46]
wire _s2_hit_T_2 = _s2_hit_T & _s2_hit_T_1; // @[Metadata.scala:46:46]
wire _s2_hit_T_3 = ~_mshrs_io_block_hit_0; // @[dcache.scala:433:21, :649:117]
wire _s2_hit_T_4 = _s2_hit_T_2 & _s2_hit_T_3; // @[dcache.scala:649:{71,114,117}]
wire _T_67 = s2_type == 3'h0; // @[package.scala:16:47]
wire _s2_hit_T_5; // @[package.scala:16:47]
assign _s2_hit_T_5 = _T_67; // @[package.scala:16:47]
wire _s2_lr_T_2; // @[dcache.scala:663:83]
assign _s2_lr_T_2 = _T_67; // @[package.scala:16:47]
wire _s2_sc_T_2; // @[dcache.scala:664:83]
assign _s2_sc_T_2 = _T_67; // @[package.scala:16:47]
wire _s2_hit_T_6 = s2_type == 3'h2; // @[package.scala:16:47]
wire _s2_hit_T_7 = _s2_hit_T_5 | _s2_hit_T_6; // @[package.scala:16:47, :81:59]
wire _s2_hit_T_8 = _s2_hit_T_4 | _s2_hit_T_7; // @[package.scala:81:59]
wire s2_hit_0 = _s2_hit_T_8; // @[dcache.scala:427:49, :649:141]
wire s2_nack_0; // @[dcache.scala:650:21]
reg s2_wb_idx_matches_0; // @[dcache.scala:654:34]
reg [39:0] debug_sc_fail_addr; // @[dcache.scala:657:35]
reg [7:0] debug_sc_fail_cnt; // @[dcache.scala:658:35]
reg [6:0] lrsc_count; // @[dcache.scala:660:27]
wire lrsc_valid = |(lrsc_count[6:2]); // @[dcache.scala:660:27, :661:31]
reg [33:0] lrsc_addr; // @[dcache.scala:662:23]
reg s2_lr_REG; // @[dcache.scala:663:59]
wire _s2_lr_T_1 = ~s2_lr_REG; // @[dcache.scala:663:{51,59}]
wire _s2_lr_T_3 = _s2_lr_T_1 | _s2_lr_T_2; // @[dcache.scala:663:{51,72,83}]
wire s2_lr = _s2_lr_T & _s2_lr_T_3; // @[dcache.scala:663:{37,47,72}]
reg s2_sc_REG; // @[dcache.scala:664:59]
wire _s2_sc_T_1 = ~s2_sc_REG; // @[dcache.scala:664:{51,59}]
wire _s2_sc_T_3 = _s2_sc_T_1 | _s2_sc_T_2; // @[dcache.scala:664:{51,72,83}]
wire s2_sc = _s2_sc_T & _s2_sc_T_3; // @[dcache.scala:664:{37,47,72}]
wire cache_resp_0_bits_data_doZero_2 = s2_sc; // @[AMOALU.scala:43:31]
wire [33:0] _s2_lrsc_addr_match_T = s2_req_0_addr[39:6]; // @[dcache.scala:632:25, :665:86]
wire [33:0] _lrsc_addr_T = s2_req_0_addr[39:6]; // @[dcache.scala:632:25, :665:86, :672:35]
wire _s2_lrsc_addr_match_T_1 = lrsc_addr == _s2_lrsc_addr_match_T; // @[dcache.scala:662:23, :665:{66,86}]
wire _s2_lrsc_addr_match_T_2 = lrsc_valid & _s2_lrsc_addr_match_T_1; // @[dcache.scala:661:31, :665:{53,66}]
wire s2_lrsc_addr_match_0 = _s2_lrsc_addr_match_T_2; // @[dcache.scala:427:49, :665:53]
wire _s2_sc_fail_T = ~s2_lrsc_addr_match_0; // @[dcache.scala:427:49, :666:29]
wire s2_sc_fail = s2_sc & _s2_sc_fail_T; // @[dcache.scala:664:47, :666:{26,29}]
wire [7:0] _lrsc_count_T = {1'h0, lrsc_count} - 8'h1; // @[dcache.scala:660:27, :667:54]
wire [6:0] _lrsc_count_T_1 = _lrsc_count_T[6:0]; // @[dcache.scala:667:54]
wire _mshrs_io_req_0_valid_T_10 = s2_type == 3'h4; // @[package.scala:16:47]
wire [8:0] _debug_sc_fail_cnt_T = {1'h0, debug_sc_fail_cnt} + 9'h1; // @[dcache.scala:658:35, :692:48]
wire [7:0] _debug_sc_fail_cnt_T_1 = _debug_sc_fail_cnt_T[7:0]; // @[dcache.scala:692:48]
wire [63:0] s2_data_0_0; // @[dcache.scala:705:21]
wire [63:0] s2_data_0_1; // @[dcache.scala:705:21]
wire [63:0] s2_data_0_2; // @[dcache.scala:705:21]
wire [63:0] s2_data_0_3; // @[dcache.scala:705:21]
wire [63:0] _s2_data_muxed_T_4 = _s2_data_muxed_T ? s2_data_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_5 = _s2_data_muxed_T_1 ? s2_data_0_1 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_6 = _s2_data_muxed_T_2 ? s2_data_0_2 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_7 = _s2_data_muxed_T_3 ? s2_data_0_3 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_8 = _s2_data_muxed_T_4 | _s2_data_muxed_T_5; // @[Mux.scala:30:73]
wire [63:0] _s2_data_muxed_T_9 = _s2_data_muxed_T_8 | _s2_data_muxed_T_6; // @[Mux.scala:30:73]
wire [63:0] _s2_data_muxed_T_10 = _s2_data_muxed_T_9 | _s2_data_muxed_T_7; // @[Mux.scala:30:73]
wire [63:0] _s2_data_muxed_WIRE = _s2_data_muxed_T_10; // @[Mux.scala:30:73]
wire [63:0] s2_data_muxed_0 = _s2_data_muxed_WIRE; // @[Mux.scala:30:73]
wire [63:0] _s2_data_word_prebypass_T_1 = s2_data_muxed_0; // @[dcache.scala:427:49, :825:63]
wire replace; // @[Replacement.scala:37:29]
wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17]
wire [1:0] _s1_replaced_way_en_T = lfsr[1:0]; // @[PRNG.scala:95:17]
wire [1:0] _s2_replaced_way_en_T = lfsr[1:0]; // @[PRNG.scala:95:17]
wire [3:0] s1_replaced_way_en = 4'h1 << _s1_replaced_way_en_T; // @[OneHot.scala:58:35]
reg [1:0] s2_replaced_way_en_REG; // @[dcache.scala:718:44]
wire [3:0] s2_replaced_way_en = 4'h1 << s2_replaced_way_en_REG; // @[OneHot.scala:58:35]
reg [1:0] s2_repl_meta_REG_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_0_coh_state = s2_repl_meta_REG_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_0_tag = s2_repl_meta_REG_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_1_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state_0 = s2_repl_meta_REG_1_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_1_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_1_tag_0 = s2_repl_meta_REG_1_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_2_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_2_coh_state = s2_repl_meta_REG_2_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_2_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_2_tag = s2_repl_meta_REG_2_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_3_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_3_coh_state = s2_repl_meta_REG_3_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_3_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_3_tag = s2_repl_meta_REG_3_tag; // @[dcache.scala:622:47, :719:88]
wire _s2_repl_meta_T = s2_replaced_way_en[0]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_1 = s2_replaced_way_en[1]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_2 = s2_replaced_way_en[2]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_3 = s2_replaced_way_en[3]; // @[OneHot.scala:58:35]
wire [1:0] _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_repl_meta_0_coh_state = _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [19:0] s2_repl_meta_0_tag = _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_4 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_5 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_tag_0 : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_6 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_7 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_8 = _s2_repl_meta_T_4 | _s2_repl_meta_T_5; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_9 = _s2_repl_meta_T_8 | _s2_repl_meta_T_6; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_10 = _s2_repl_meta_T_9 | _s2_repl_meta_T_7; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_2 = _s2_repl_meta_T_10; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_tag = _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_coh_state = _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_11 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_12 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_coh_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_13 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_14 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_15 = _s2_repl_meta_T_11 | _s2_repl_meta_T_12; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_16 = _s2_repl_meta_T_15 | _s2_repl_meta_T_13; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_17 = _s2_repl_meta_T_16 | _s2_repl_meta_T_14; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_4 = _s2_repl_meta_T_17; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_3_state = _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
wire [19:0] mshrs_io_req_0_bits_old_meta_meta_tag = s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
reg s2_nack_hit_0; // @[dcache.scala:722:31]
wire _GEN_16 = s2_valid_0 & s2_hit_0; // @[dcache.scala:427:49, :724:50]
wire _s2_nack_victim_T; // @[dcache.scala:724:50]
assign _s2_nack_victim_T = _GEN_16; // @[dcache.scala:724:50]
wire _s3_valid_T; // @[dcache.scala:871:38]
assign _s3_valid_T = _GEN_16; // @[dcache.scala:724:50, :871:38]
wire _s2_nack_victim_T_1 = _s2_nack_victim_T & _mshrs_io_secondary_miss_0; // @[dcache.scala:433:21, :724:{50,64}]
wire s2_nack_victim_0 = _s2_nack_victim_T_1; // @[dcache.scala:427:49, :724:64]
wire _s2_nack_miss_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :726:53]
wire _s2_nack_miss_T_1 = s2_valid_0 & _s2_nack_miss_T; // @[dcache.scala:427:49, :726:{50,53}]
wire _s2_nack_miss_T_2 = ~_mshrs_io_req_0_ready; // @[dcache.scala:433:21, :726:67]
wire _s2_nack_miss_T_3 = _s2_nack_miss_T_1 & _s2_nack_miss_T_2; // @[dcache.scala:726:{50,64,67}]
wire s2_nack_miss_0 = _s2_nack_miss_T_3; // @[dcache.scala:427:49, :726:64]
wire _s2_nack_wb_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :730:53]
wire _s2_nack_wb_T_1 = s2_valid_0 & _s2_nack_wb_T; // @[dcache.scala:427:49, :730:{50,53}]
wire _s2_nack_wb_T_2 = _s2_nack_wb_T_1 & s2_wb_idx_matches_0; // @[dcache.scala:654:34, :730:{50,64}]
wire s2_nack_wb_0 = _s2_nack_wb_T_2; // @[dcache.scala:427:49, :730:64]
assign s2_nack_0 = (s2_nack_miss_0 | s2_nack_hit_0 | s2_nack_victim_0 | s2_nack_wb_0) & (|s2_type); // @[dcache.scala:427:49, :633:25, :650:21, :722:31, :732:{55,73,113,131,142}]
reg s2_send_resp_REG; // @[dcache.scala:733:44]
wire _s2_send_resp_T = ~s2_nack_0; // @[dcache.scala:650:21, :668:60, :733:73]
wire _s2_send_resp_T_1 = s2_send_resp_REG & _s2_send_resp_T; // @[dcache.scala:733:{44,70,73}]
wire _mshrs_io_req_0_valid_T_74; // @[dcache.scala:754:77]
wire _T_73 = _mshrs_io_req_0_ready & _mshrs_io_req_0_valid_T_74; // @[Decoupled.scala:51:35]
assign replace = _T_73; // @[Decoupled.scala:51:35]
wire _s2_send_resp_T_2; // @[Decoupled.scala:51:35]
assign _s2_send_resp_T_2 = _T_73; // @[Decoupled.scala:51:35]
wire _s2_send_resp_T_5 = _s2_send_resp_T_3 | _s2_send_resp_T_4; // @[Consts.scala:90:{32,42,49}]
wire _s2_send_resp_T_7 = _s2_send_resp_T_5 | _s2_send_resp_T_6; // @[Consts.scala:90:{42,59,66}]
wire _s2_send_resp_T_12 = _s2_send_resp_T_8 | _s2_send_resp_T_9; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_13 = _s2_send_resp_T_12 | _s2_send_resp_T_10; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_14 = _s2_send_resp_T_13 | _s2_send_resp_T_11; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_20 = _s2_send_resp_T_15 | _s2_send_resp_T_16; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_21 = _s2_send_resp_T_20 | _s2_send_resp_T_17; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_22 = _s2_send_resp_T_21 | _s2_send_resp_T_18; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_23 = _s2_send_resp_T_22 | _s2_send_resp_T_19; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_24 = _s2_send_resp_T_14 | _s2_send_resp_T_23; // @[package.scala:81:59]
wire _s2_send_resp_T_25 = _s2_send_resp_T_7 | _s2_send_resp_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_send_resp_T_26 = _s2_send_resp_T_2 & _s2_send_resp_T_25; // @[Decoupled.scala:51:35]
wire _GEN_17 = s2_req_0_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s2_send_resp_T_27; // @[package.scala:16:47]
assign _s2_send_resp_T_27 = _GEN_17; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_24; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_24 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = s2_req_0_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s2_send_resp_T_28; // @[package.scala:16:47]
assign _s2_send_resp_T_28 = _GEN_18; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_25; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_25 = _GEN_18; // @[package.scala:16:47]
wire _s2_send_resp_T_31 = _s2_send_resp_T_27 | _s2_send_resp_T_28; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_32 = _s2_send_resp_T_31 | _s2_send_resp_T_29; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_33 = _s2_send_resp_T_32 | _s2_send_resp_T_30; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_38 = _s2_send_resp_T_34 | _s2_send_resp_T_35; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_39 = _s2_send_resp_T_38 | _s2_send_resp_T_36; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_40 = _s2_send_resp_T_39 | _s2_send_resp_T_37; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_46 = _s2_send_resp_T_41 | _s2_send_resp_T_42; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_47 = _s2_send_resp_T_46 | _s2_send_resp_T_43; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_48 = _s2_send_resp_T_47 | _s2_send_resp_T_44; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_49 = _s2_send_resp_T_48 | _s2_send_resp_T_45; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_50 = _s2_send_resp_T_40 | _s2_send_resp_T_49; // @[package.scala:81:59]
wire _s2_send_resp_T_51 = _s2_send_resp_T_33 | _s2_send_resp_T_50; // @[package.scala:81:59]
wire _s2_send_resp_T_52 = ~_s2_send_resp_T_51; // @[Consts.scala:89:68]
wire _s2_send_resp_T_53 = _s2_send_resp_T_26 & _s2_send_resp_T_52; // @[dcache.scala:734:{59,93,96}]
wire _s2_send_resp_T_54 = s2_hit_0 | _s2_send_resp_T_53; // @[dcache.scala:427:49, :734:{34,93}]
wire _s2_send_resp_T_55 = _s2_send_resp_T_1 & _s2_send_resp_T_54; // @[dcache.scala:733:{70,85}, :734:34]
wire s2_send_resp_0 = _s2_send_resp_T_55; // @[dcache.scala:427:49, :733:85]
reg s2_send_nack_REG; // @[dcache.scala:735:44]
wire _s2_send_nack_T = s2_send_nack_REG & s2_nack_0; // @[dcache.scala:650:21, :735:{44,70}]
wire s2_send_nack_0 = _s2_send_nack_T; // @[dcache.scala:427:49, :735:70]
wire _s2_store_failed_T = s2_valid_0 & s2_nack_0; // @[dcache.scala:427:49, :650:21, :742:34]
wire _s2_store_failed_T_1 = _s2_store_failed_T & s2_send_nack_0; // @[dcache.scala:427:49, :742:{34,48}]
assign _s2_store_failed_T_2 = _s2_store_failed_T_1 & s2_req_0_uop_uses_stq; // @[dcache.scala:632:25, :742:{48,67}]
assign s2_store_failed = _s2_store_failed_T_2; // @[dcache.scala:603:29, :742:67]
wire _mshrs_io_req_0_valid_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :747:29]
wire _mshrs_io_req_0_valid_T_1 = s2_valid_0 & _mshrs_io_req_0_valid_T; // @[dcache.scala:427:49, :746:51, :747:29]
wire _mshrs_io_req_0_valid_T_2 = ~s2_nack_hit_0; // @[dcache.scala:722:31, :748:29]
wire _mshrs_io_req_0_valid_T_3 = _mshrs_io_req_0_valid_T_1 & _mshrs_io_req_0_valid_T_2; // @[dcache.scala:746:51, :747:51, :748:29]
wire _mshrs_io_req_0_valid_T_4 = ~s2_nack_victim_0; // @[dcache.scala:427:49, :749:29]
wire _mshrs_io_req_0_valid_T_5 = _mshrs_io_req_0_valid_T_3 & _mshrs_io_req_0_valid_T_4; // @[dcache.scala:747:51, :748:51, :749:29]
wire _mshrs_io_req_0_valid_T_7 = _mshrs_io_req_0_valid_T_5; // @[dcache.scala:748:51, :749:51]
wire _mshrs_io_req_0_valid_T_8 = ~s2_nack_wb_0; // @[dcache.scala:427:49, :751:29]
wire _mshrs_io_req_0_valid_T_9 = _mshrs_io_req_0_valid_T_7 & _mshrs_io_req_0_valid_T_8; // @[dcache.scala:749:51, :750:51, :751:29]
wire _mshrs_io_req_0_valid_T_11 = s2_type == 3'h5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_12 = _mshrs_io_req_0_valid_T_10 | _mshrs_io_req_0_valid_T_11; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_13 = _mshrs_io_req_0_valid_T_9 & _mshrs_io_req_0_valid_T_12; // @[package.scala:81:59]
wire [7:0] _GEN_19 = io_lsu_brupdate_b1_mispredict_mask_0 & s2_req_0_uop_br_mask; // @[util.scala:118:51]
wire [7:0] _mshrs_io_req_0_valid_T_14; // @[util.scala:118:51]
assign _mshrs_io_req_0_valid_T_14 = _GEN_19; // @[util.scala:118:51]
wire [7:0] _io_lsu_nack_0_valid_T_4; // @[util.scala:118:51]
assign _io_lsu_nack_0_valid_T_4 = _GEN_19; // @[util.scala:118:51]
wire _mshrs_io_req_0_valid_T_15 = |_mshrs_io_req_0_valid_T_14; // @[util.scala:118:{51,59}]
wire _mshrs_io_req_0_valid_T_16 = ~_mshrs_io_req_0_valid_T_15; // @[util.scala:118:59]
wire _mshrs_io_req_0_valid_T_17 = _mshrs_io_req_0_valid_T_13 & _mshrs_io_req_0_valid_T_16; // @[dcache.scala:751:51, :752:77, :753:29]
wire _GEN_20 = io_lsu_exception_0 & s2_req_0_uop_uses_ldq; // @[dcache.scala:413:7, :632:25, :754:48]
wire _mshrs_io_req_0_valid_T_18; // @[dcache.scala:754:48]
assign _mshrs_io_req_0_valid_T_18 = _GEN_20; // @[dcache.scala:754:48]
wire _io_lsu_nack_0_valid_T_1; // @[dcache.scala:863:48]
assign _io_lsu_nack_0_valid_T_1 = _GEN_20; // @[dcache.scala:754:48, :863:48]
wire _mshrs_io_req_0_valid_T_19 = ~_mshrs_io_req_0_valid_T_18; // @[dcache.scala:754:{29,48}]
wire _mshrs_io_req_0_valid_T_20 = _mshrs_io_req_0_valid_T_17 & _mshrs_io_req_0_valid_T_19; // @[dcache.scala:752:77, :753:79, :754:29]
wire _mshrs_io_req_0_valid_T_21 = s2_req_0_uop_mem_cmd == 5'h2; // @[Consts.scala:88:35]
wire _mshrs_io_req_0_valid_T_23 = _mshrs_io_req_0_valid_T_21 | _mshrs_io_req_0_valid_T_22; // @[Consts.scala:88:{35,45,52}]
wire _mshrs_io_req_0_valid_T_28 = _mshrs_io_req_0_valid_T_24 | _mshrs_io_req_0_valid_T_25; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_29 = _mshrs_io_req_0_valid_T_28 | _mshrs_io_req_0_valid_T_26; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_30 = _mshrs_io_req_0_valid_T_29 | _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_35 = _mshrs_io_req_0_valid_T_31 | _mshrs_io_req_0_valid_T_32; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_36 = _mshrs_io_req_0_valid_T_35 | _mshrs_io_req_0_valid_T_33; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_37 = _mshrs_io_req_0_valid_T_36 | _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_43 = _mshrs_io_req_0_valid_T_38 | _mshrs_io_req_0_valid_T_39; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_44 = _mshrs_io_req_0_valid_T_43 | _mshrs_io_req_0_valid_T_40; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_45 = _mshrs_io_req_0_valid_T_44 | _mshrs_io_req_0_valid_T_41; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_46 = _mshrs_io_req_0_valid_T_45 | _mshrs_io_req_0_valid_T_42; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_47 = _mshrs_io_req_0_valid_T_37 | _mshrs_io_req_0_valid_T_46; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_48 = _mshrs_io_req_0_valid_T_30 | _mshrs_io_req_0_valid_T_47; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_49 = _mshrs_io_req_0_valid_T_23 | _mshrs_io_req_0_valid_T_48; // @[Consts.scala:88:45, :89:68]
wire _mshrs_io_req_0_valid_T_52 = _mshrs_io_req_0_valid_T_50 | _mshrs_io_req_0_valid_T_51; // @[Consts.scala:90:{32,42,49}]
wire _mshrs_io_req_0_valid_T_54 = _mshrs_io_req_0_valid_T_52 | _mshrs_io_req_0_valid_T_53; // @[Consts.scala:90:{42,59,66}]
wire _mshrs_io_req_0_valid_T_59 = _mshrs_io_req_0_valid_T_55 | _mshrs_io_req_0_valid_T_56; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_60 = _mshrs_io_req_0_valid_T_59 | _mshrs_io_req_0_valid_T_57; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_61 = _mshrs_io_req_0_valid_T_60 | _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_67 = _mshrs_io_req_0_valid_T_62 | _mshrs_io_req_0_valid_T_63; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_68 = _mshrs_io_req_0_valid_T_67 | _mshrs_io_req_0_valid_T_64; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_69 = _mshrs_io_req_0_valid_T_68 | _mshrs_io_req_0_valid_T_65; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_70 = _mshrs_io_req_0_valid_T_69 | _mshrs_io_req_0_valid_T_66; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_71 = _mshrs_io_req_0_valid_T_61 | _mshrs_io_req_0_valid_T_70; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_72 = _mshrs_io_req_0_valid_T_54 | _mshrs_io_req_0_valid_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _mshrs_io_req_0_valid_T_73 = _mshrs_io_req_0_valid_T_49 | _mshrs_io_req_0_valid_T_72; // @[Consts.scala:90:76]
assign _mshrs_io_req_0_valid_T_74 = _mshrs_io_req_0_valid_T_20 & _mshrs_io_req_0_valid_T_73; // @[dcache.scala:753:79, :754:77, :756:65]
wire [7:0] _mshrs_io_req_0_bits_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _mshrs_io_req_0_bits_uop_br_mask_T_1 = s2_req_0_uop_br_mask & _mshrs_io_req_0_bits_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire [1:0] _mshrs_io_req_0_bits_old_meta_T_coh_state = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_coh_state : s2_repl_meta_0_coh_state; // @[HellaCache.scala:305:20]
wire [19:0] _mshrs_io_req_0_bits_old_meta_T_tag = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_tag : s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
wire [3:0] _mshrs_io_req_0_bits_way_en_T = s2_tag_match_0 ? s2_tag_match_way_0 : s2_replaced_way_en; // @[OneHot.scala:58:35]
wire _mshrs_io_req_is_probe_0_T = s2_type == 3'h1; // @[dcache.scala:633:25, :769:49]
wire _mshrs_io_req_is_probe_0_T_1 = _mshrs_io_req_is_probe_0_T & s2_valid_0; // @[dcache.scala:427:49, :769:{49,61}]
wire _mshrs_io_meta_resp_valid_T = ~s2_nack_hit_0; // @[dcache.scala:722:31, :748:29, :772:36]
wire _mshrs_io_meta_resp_valid_T_1 = _mshrs_io_meta_resp_valid_T | _prober_io_mshr_wb_rdy; // @[dcache.scala:432:22, :772:{36,52}]
reg [1:0] mshrs_io_meta_resp_bits_REG_0_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_0_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_1_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_1_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_2_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_2_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_3_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_3_tag; // @[dcache.scala:773:70]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_4 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_5 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_6 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_7 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_8 = _mshrs_io_meta_resp_bits_T_4 | _mshrs_io_meta_resp_bits_T_5; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_9 = _mshrs_io_meta_resp_bits_T_8 | _mshrs_io_meta_resp_bits_T_6; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_10 = _mshrs_io_meta_resp_bits_T_9 | _mshrs_io_meta_resp_bits_T_7; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_1 = _mshrs_io_meta_resp_bits_T_10; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_WIRE_tag = _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_coh_state = _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_11 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_12 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_13 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_14 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_15 = _mshrs_io_meta_resp_bits_T_11 | _mshrs_io_meta_resp_bits_T_12; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_16 = _mshrs_io_meta_resp_bits_T_15 | _mshrs_io_meta_resp_bits_T_13; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_17 = _mshrs_io_meta_resp_bits_T_16 | _mshrs_io_meta_resp_bits_T_14; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_3 = _mshrs_io_meta_resp_bits_T_17; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_2_state = _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire _prober_io_req_valid_T = ~lrsc_valid; // @[dcache.scala:661:31, :778:46]
wire _prober_io_req_valid_T_1 = nodeOut_b_valid & _prober_io_req_valid_T; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T = ~lrsc_valid; // @[dcache.scala:661:31, :778:46, :779:51]
assign _nodeOut_b_ready_T_1 = _prober_io_req_ready & _nodeOut_b_ready_T; // @[dcache.scala:432:22, :779:{48,51}]
assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[MixedNode.scala:542:17]
wire _prober_io_wb_rdy_T = _prober_io_meta_write_bits_idx != _wb_io_idx_bits; // @[dcache.scala:431:18, :432:22, :785:59]
wire _prober_io_wb_rdy_T_1 = ~_wb_io_idx_valid; // @[dcache.scala:431:18, :785:82]
wire _prober_io_wb_rdy_T_2 = _prober_io_wb_rdy_T | _prober_io_wb_rdy_T_1; // @[dcache.scala:785:{59,79,82}]
wire _wb_io_mem_grant_T_1 = nodeOut_d_bits_source == 2'h2; // @[MixedNode.scala:542:17]
assign nodeOut_d_ready = _wb_io_mem_grant_T_1 | _mshrs_io_mem_grant_ready; // @[MixedNode.scala:542:17]
wire _wb_io_mem_grant_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _wb_io_mem_grant_T_2 = _wb_io_mem_grant_T & _wb_io_mem_grant_T_1; // @[Decoupled.scala:51:35]
wire opdata = _wb_io_release_bits_opcode[0]; // @[Edges.scala:102:36]
wire [26:0] _decode_T_3 = 27'hFFF << _prober_io_rep_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_4 = _decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] decode_1 = _decode_T_5[11:3]; // @[package.scala:243:46]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_c_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {_prober_io_rep_valid, _wb_io_release_valid}; // @[Arbiter.scala:68:51]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & _wb_io_release_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & _prober_io_rep_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_c_valid_T = _wb_io_release_valid | _prober_io_rep_valid; // @[Arbiter.scala:79:31, :96:46]
wire [8:0] maskedBeats_0 = winner_0 & opdata ? 9'h7 : 9'h0; // @[Edges.scala:102:36, :221:14]
wire [8:0] initBeats = maskedBeats_0; // @[Arbiter.scala:82:69, :84:44]
wire _GEN_21 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35]
wire _beatsLeft_T; // @[Decoupled.scala:51:35]
assign _beatsLeft_T = _GEN_21; // @[Decoupled.scala:51:35]
wire _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign _io_lsu_perf_release_T = _GEN_21; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire _wb_io_release_ready_T = nodeOut_c_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31]
wire _prober_io_rep_ready_T = nodeOut_c_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31]
wire _nodeOut_c_valid_T_1 = state_0 & _wb_io_release_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_2 = state_1 & _prober_io_rep_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_3 = _nodeOut_c_valid_T_1 | _nodeOut_c_valid_T_2; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_WIRE = _nodeOut_c_valid_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_valid_T_4 = idle ? _nodeOut_c_valid_T : _nodeOut_c_valid_WIRE; // @[Mux.scala:30:73]
assign nodeOut_c_valid = _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
assign nodeOut_c_bits_opcode = _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
assign nodeOut_c_bits_param = _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
assign nodeOut_c_bits_size = _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
assign nodeOut_c_bits_source = _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
assign nodeOut_c_bits_address = _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
assign nodeOut_c_bits_data = _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_T_3 = muxState_0 ? _wb_io_release_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_T_5 = _nodeOut_c_bits_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_2 = _nodeOut_c_bits_T_5; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_data = _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_6 = muxState_0 ? _wb_io_release_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_7 = muxState_1 ? _prober_io_rep_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_8 = _nodeOut_c_bits_T_6 | _nodeOut_c_bits_T_7; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_5 = _nodeOut_c_bits_T_8; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_address = _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_T_9 = {muxState_0, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_T_10 = muxState_1 ? _prober_io_rep_bits_source : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _nodeOut_c_bits_T_11 = _nodeOut_c_bits_T_9 | _nodeOut_c_bits_T_10; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_6 = _nodeOut_c_bits_T_11; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_source = _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_12 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_13 = muxState_1 ? _prober_io_rep_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_14 = _nodeOut_c_bits_T_12 | _nodeOut_c_bits_T_13; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_7 = _nodeOut_c_bits_T_14; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_size = _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_15 = muxState_0 ? _wb_io_release_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_16 = muxState_1 ? _prober_io_rep_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_17 = _nodeOut_c_bits_T_15 | _nodeOut_c_bits_T_16; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_8 = _nodeOut_c_bits_T_17; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_param = _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_18 = muxState_0 ? _wb_io_release_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_19 = {muxState_1, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_20 = _nodeOut_c_bits_T_18 | _nodeOut_c_bits_T_19; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_9 = _nodeOut_c_bits_T_20; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_opcode = _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
wire [26:0] _io_lsu_perf_release_beats1_decode_T = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_1 = _io_lsu_perf_release_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_2 = ~_io_lsu_perf_release_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] io_lsu_perf_release_beats1_decode = _io_lsu_perf_release_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire io_lsu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36]
wire [8:0] io_lsu_perf_release_beats1 = io_lsu_perf_release_beats1_opdata ? io_lsu_perf_release_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] io_lsu_perf_release_counter; // @[Edges.scala:229:27]
wire [9:0] _io_lsu_perf_release_counter1_T = {1'h0, io_lsu_perf_release_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] io_lsu_perf_release_counter1 = _io_lsu_perf_release_counter1_T[8:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_release_first = io_lsu_perf_release_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_release_last_T = io_lsu_perf_release_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_release_last_T_1 = io_lsu_perf_release_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_release_last = _io_lsu_perf_release_last_T | _io_lsu_perf_release_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_release_done = io_lsu_perf_release_last & _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_release_0 = io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [8:0] _io_lsu_perf_release_count_T = ~io_lsu_perf_release_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] io_lsu_perf_release_count = io_lsu_perf_release_beats1 & _io_lsu_perf_release_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _io_lsu_perf_release_counter_T = io_lsu_perf_release_first ? io_lsu_perf_release_beats1 : io_lsu_perf_release_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _io_lsu_perf_acquire_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] _io_lsu_perf_acquire_beats1_decode_T = 27'hFFF << nodeOut_a_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_1 = _io_lsu_perf_acquire_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_2 = ~_io_lsu_perf_acquire_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] io_lsu_perf_acquire_beats1_decode = _io_lsu_perf_acquire_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _io_lsu_perf_acquire_beats1_opdata_T = nodeOut_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire io_lsu_perf_acquire_beats1_opdata = ~_io_lsu_perf_acquire_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] io_lsu_perf_acquire_beats1 = io_lsu_perf_acquire_beats1_opdata ? io_lsu_perf_acquire_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] io_lsu_perf_acquire_counter; // @[Edges.scala:229:27]
wire [9:0] _io_lsu_perf_acquire_counter1_T = {1'h0, io_lsu_perf_acquire_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] io_lsu_perf_acquire_counter1 = _io_lsu_perf_acquire_counter1_T[8:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_acquire_first = io_lsu_perf_acquire_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_acquire_last_T = io_lsu_perf_acquire_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_acquire_last_T_1 = io_lsu_perf_acquire_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_acquire_last = _io_lsu_perf_acquire_last_T | _io_lsu_perf_acquire_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_acquire_done = io_lsu_perf_acquire_last & _io_lsu_perf_acquire_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_acquire_0 = io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire [8:0] _io_lsu_perf_acquire_count_T = ~io_lsu_perf_acquire_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] io_lsu_perf_acquire_count = io_lsu_perf_acquire_beats1 & _io_lsu_perf_acquire_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _io_lsu_perf_acquire_counter_T = io_lsu_perf_acquire_first ? io_lsu_perf_acquire_beats1 : io_lsu_perf_acquire_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [63:0] s2_data_word_prebypass_0 = _s2_data_word_prebypass_T_1; // @[dcache.scala:427:49, :825:63]
wire [63:0] _s2_data_word_0_T_2; // @[dcache.scala:891:27]
wire [63:0] s2_data_word_0; // @[dcache.scala:826:26]
wire [63:0] size_dat_padded = s2_data_word_0; // @[AMOALU.scala:13:27]
wire _cache_resp_0_valid_T; // @[dcache.scala:835:48]
wire [63:0] _cache_resp_0_bits_data_T_24; // @[dcache.scala:837:52]
wire [63:0] cache_resp_0_bits_data; // @[dcache.scala:833:26]
wire cache_resp_0_valid; // @[dcache.scala:833:26]
assign _cache_resp_0_valid_T = s2_valid_0 & s2_send_resp_0; // @[dcache.scala:427:49, :835:48]
assign cache_resp_0_valid = _cache_resp_0_valid_T; // @[dcache.scala:833:26, :835:48]
wire _cache_resp_0_bits_data_shifted_T = s2_req_0_addr[2]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T_8 = s2_req_0_addr[2]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T_2 = s2_req_0_addr[2]; // @[AMOALU.scala:21:27, :42:29]
wire [31:0] _cache_resp_0_bits_data_shifted_T_1 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _cache_resp_0_bits_data_T_5 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _cache_resp_0_bits_data_shifted_T_2 = s2_data_word_0[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] cache_resp_0_bits_data_shifted = _cache_resp_0_bits_data_shifted_T ? _cache_resp_0_bits_data_shifted_T_1 : _cache_resp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] cache_resp_0_bits_data_zeroed = cache_resp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _cache_resp_0_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_1 = _cache_resp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _cache_resp_0_bits_data_T_2 = cache_resp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_3 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _cache_resp_0_bits_data_T_4 = {32{_cache_resp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _cache_resp_0_bits_data_T_6 = _cache_resp_0_bits_data_T_1 ? _cache_resp_0_bits_data_T_4 : _cache_resp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_7 = {_cache_resp_0_bits_data_T_6, cache_resp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _cache_resp_0_bits_data_shifted_T_3 = s2_req_0_addr[1]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T_4 = s2_req_0_addr[1]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T_1 = s2_req_0_addr[1]; // @[AMOALU.scala:21:27, :42:29]
wire [15:0] _cache_resp_0_bits_data_shifted_T_4 = _cache_resp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _cache_resp_0_bits_data_shifted_T_5 = _cache_resp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] cache_resp_0_bits_data_shifted_1 = _cache_resp_0_bits_data_shifted_T_3 ? _cache_resp_0_bits_data_shifted_T_4 : _cache_resp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] cache_resp_0_bits_data_zeroed_1 = cache_resp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _cache_resp_0_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_9 = _cache_resp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _cache_resp_0_bits_data_T_10 = cache_resp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_11 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _cache_resp_0_bits_data_T_12 = {48{_cache_resp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _cache_resp_0_bits_data_T_13 = _cache_resp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _cache_resp_0_bits_data_T_14 = _cache_resp_0_bits_data_T_9 ? _cache_resp_0_bits_data_T_12 : _cache_resp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_15 = {_cache_resp_0_bits_data_T_14, cache_resp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _cache_resp_0_bits_data_shifted_T_6 = s2_req_0_addr[0]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T = s2_req_0_addr[0]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T = s2_req_0_addr[0]; // @[AMOALU.scala:21:27, :42:29]
wire [7:0] _cache_resp_0_bits_data_shifted_T_7 = _cache_resp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _cache_resp_0_bits_data_shifted_T_8 = _cache_resp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] cache_resp_0_bits_data_shifted_2 = _cache_resp_0_bits_data_shifted_T_6 ? _cache_resp_0_bits_data_shifted_T_7 : _cache_resp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] cache_resp_0_bits_data_zeroed_2 = cache_resp_0_bits_data_doZero_2 ? 8'h0 : cache_resp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :43:31, :44:23]
wire _cache_resp_0_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_17 = _cache_resp_0_bits_data_T_16 | cache_resp_0_bits_data_doZero_2; // @[AMOALU.scala:43:31, :45:{26,34}]
wire _cache_resp_0_bits_data_T_18 = cache_resp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_19 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _cache_resp_0_bits_data_T_20 = {56{_cache_resp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _cache_resp_0_bits_data_T_21 = _cache_resp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _cache_resp_0_bits_data_T_22 = _cache_resp_0_bits_data_T_17 ? _cache_resp_0_bits_data_T_20 : _cache_resp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_23 = {_cache_resp_0_bits_data_T_22, cache_resp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign _cache_resp_0_bits_data_T_24 = {_cache_resp_0_bits_data_T_23[63:1], _cache_resp_0_bits_data_T_23[0] | s2_sc_fail}; // @[AMOALU.scala:45:16]
assign cache_resp_0_bits_data = _cache_resp_0_bits_data_T_24; // @[dcache.scala:833:26, :837:52]
wire [3:0] uncache_resp_bits_uop_ctrl_br_type; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_ctrl_op1_sel; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_op2_sel; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_imm_sel; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_ctrl_op_fcn; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_fcn_dw; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_csr_cmd; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_load; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_sta; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_std; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_uopc; // @[dcache.scala:841:26]
wire [31:0] uncache_resp_bits_uop_inst; // @[dcache.scala:841:26]
wire [31:0] uncache_resp_bits_uop_debug_inst; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_rvc; // @[dcache.scala:841:26]
wire [39:0] uncache_resp_bits_uop_debug_pc; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_iq_type; // @[dcache.scala:841:26]
wire [9:0] uncache_resp_bits_uop_fu_code; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_iw_state; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_iw_p1_poisoned; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_iw_p2_poisoned; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_br; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_jalr; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_jal; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_sfb; // @[dcache.scala:841:26]
wire [7:0] uncache_resp_bits_uop_br_mask; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_br_tag; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_ftq_idx; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_edge_inst; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_pc_lob; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_taken; // @[dcache.scala:841:26]
wire [19:0] uncache_resp_bits_uop_imm_packed; // @[dcache.scala:841:26]
wire [11:0] uncache_resp_bits_uop_csr_addr; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_rob_idx; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ldq_idx; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_stq_idx; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_rxq_idx; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_pdst; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_prs1; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_prs2; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_prs3; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_ppred; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs1_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs2_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs3_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ppred_busy; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_stale_pdst; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_exception; // @[dcache.scala:841:26]
wire [63:0] uncache_resp_bits_uop_exc_cause; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bypassable; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_mem_cmd; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_mem_size; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_mem_signed; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_fence; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_fencei; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_amo; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_uses_ldq; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_uses_stq; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_sys_pc2epc; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_unique; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_flush_on_commit; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ldst_is_rs1; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_ldst; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs1; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs2; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs3; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ldst_val; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_dst_rtype; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_lrs1_rtype; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_lrs2_rtype; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_frs3_en; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_fp_val; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_fp_single; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_pf_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_ae_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_ma_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bp_debug_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bp_xcpt_if; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_debug_fsrc; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_debug_tsrc; // @[dcache.scala:841:26]
wire [63:0] uncache_resp_bits_data; // @[dcache.scala:841:26]
wire uncache_resp_bits_is_hella; // @[dcache.scala:841:26]
wire uncache_resp_valid; // @[dcache.scala:841:26]
wire _mshrs_io_resp_ready_T = ~cache_resp_0_valid; // @[dcache.scala:833:26, :844:26]
assign io_lsu_resp_0_bits_out_uop_uopc = resp_0_bits_uop_uopc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_inst = resp_0_bits_uop_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_inst = resp_0_bits_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_rvc = resp_0_bits_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_pc = resp_0_bits_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iq_type = resp_0_bits_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fu_code = resp_0_bits_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_br_type = resp_0_bits_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op1_sel = resp_0_bits_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op2_sel = resp_0_bits_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_imm_sel = resp_0_bits_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op_fcn = resp_0_bits_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw = resp_0_bits_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd = resp_0_bits_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_load = resp_0_bits_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_sta = resp_0_bits_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_std = resp_0_bits_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_state = resp_0_bits_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_p1_poisoned = resp_0_bits_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_p2_poisoned = resp_0_bits_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_br = resp_0_bits_uop_is_br; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_jalr = resp_0_bits_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_jal = resp_0_bits_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_sfb = resp_0_bits_uop_is_sfb; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_br_tag = resp_0_bits_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ftq_idx = resp_0_bits_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_edge_inst = resp_0_bits_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_pc_lob = resp_0_bits_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_taken = resp_0_bits_uop_taken; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_imm_packed = resp_0_bits_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_csr_addr = resp_0_bits_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_rob_idx = resp_0_bits_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldq_idx = resp_0_bits_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_stq_idx = resp_0_bits_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_rxq_idx = resp_0_bits_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_pdst = resp_0_bits_uop_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs1 = resp_0_bits_uop_prs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs2 = resp_0_bits_uop_prs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs3 = resp_0_bits_uop_prs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ppred = resp_0_bits_uop_ppred; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs1_busy = resp_0_bits_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs2_busy = resp_0_bits_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs3_busy = resp_0_bits_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ppred_busy = resp_0_bits_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_stale_pdst = resp_0_bits_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_exception = resp_0_bits_uop_exception; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_exc_cause = resp_0_bits_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bypassable = resp_0_bits_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_cmd = resp_0_bits_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_size = resp_0_bits_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_signed = resp_0_bits_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_fence = resp_0_bits_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_fencei = resp_0_bits_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_amo = resp_0_bits_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_uses_ldq = resp_0_bits_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_uses_stq = resp_0_bits_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_sys_pc2epc = resp_0_bits_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_unique = resp_0_bits_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_flush_on_commit = resp_0_bits_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst_is_rs1 = resp_0_bits_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst = resp_0_bits_uop_ldst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs1 = resp_0_bits_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs2 = resp_0_bits_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs3 = resp_0_bits_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst_val = resp_0_bits_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_dst_rtype = resp_0_bits_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs1_rtype = resp_0_bits_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs2_rtype = resp_0_bits_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_frs3_en = resp_0_bits_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fp_val = resp_0_bits_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fp_single = resp_0_bits_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_pf_if = resp_0_bits_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_ae_if = resp_0_bits_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_ma_if = resp_0_bits_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bp_debug_if = resp_0_bits_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bp_xcpt_if = resp_0_bits_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_fsrc = resp_0_bits_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_tsrc = resp_0_bits_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_data = resp_0_bits_data; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_is_hella = resp_0_bits_is_hella; // @[util.scala:101:23]
wire [7:0] resp_0_bits_uop_br_mask; // @[dcache.scala:846:22]
wire resp_0_valid; // @[dcache.scala:846:22]
wire _uncache_respond_T = ~cache_resp_0_valid; // @[dcache.scala:833:26, :844:26, :849:27]
wire uncache_respond = _uncache_respond_T; // @[dcache.scala:849:{27,48}]
assign resp_0_valid = uncache_respond ? uncache_resp_valid : cache_resp_0_valid; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uopc = uncache_respond ? uncache_resp_bits_uop_uopc : cache_resp_0_bits_uop_uopc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_inst = uncache_respond ? uncache_resp_bits_uop_inst : cache_resp_0_bits_uop_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_inst = uncache_respond ? uncache_resp_bits_uop_debug_inst : cache_resp_0_bits_uop_debug_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_rvc = uncache_respond ? uncache_resp_bits_uop_is_rvc : cache_resp_0_bits_uop_is_rvc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_pc = uncache_respond ? uncache_resp_bits_uop_debug_pc : cache_resp_0_bits_uop_debug_pc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iq_type = uncache_respond ? uncache_resp_bits_uop_iq_type : cache_resp_0_bits_uop_iq_type; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fu_code = uncache_respond ? uncache_resp_bits_uop_fu_code : cache_resp_0_bits_uop_fu_code; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_br_type = uncache_respond ? uncache_resp_bits_uop_ctrl_br_type : cache_resp_0_bits_uop_ctrl_br_type; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op1_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op1_sel : cache_resp_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op2_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op2_sel : cache_resp_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_imm_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_imm_sel : cache_resp_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op_fcn = uncache_respond ? uncache_resp_bits_uop_ctrl_op_fcn : cache_resp_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_fcn_dw = uncache_respond ? uncache_resp_bits_uop_ctrl_fcn_dw : cache_resp_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_csr_cmd = uncache_respond ? uncache_resp_bits_uop_ctrl_csr_cmd : cache_resp_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_load = uncache_respond ? uncache_resp_bits_uop_ctrl_is_load : cache_resp_0_bits_uop_ctrl_is_load; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_sta = uncache_respond ? uncache_resp_bits_uop_ctrl_is_sta : cache_resp_0_bits_uop_ctrl_is_sta; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_std = uncache_respond ? uncache_resp_bits_uop_ctrl_is_std : cache_resp_0_bits_uop_ctrl_is_std; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_state = uncache_respond ? uncache_resp_bits_uop_iw_state : cache_resp_0_bits_uop_iw_state; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_p1_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p1_poisoned : cache_resp_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_p2_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p2_poisoned : cache_resp_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_br = uncache_respond ? uncache_resp_bits_uop_is_br : cache_resp_0_bits_uop_is_br; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_jalr = uncache_respond ? uncache_resp_bits_uop_is_jalr : cache_resp_0_bits_uop_is_jalr; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_jal = uncache_respond ? uncache_resp_bits_uop_is_jal : cache_resp_0_bits_uop_is_jal; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_sfb = uncache_respond ? uncache_resp_bits_uop_is_sfb : cache_resp_0_bits_uop_is_sfb; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_br_mask = uncache_respond ? uncache_resp_bits_uop_br_mask : cache_resp_0_bits_uop_br_mask; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_br_tag = uncache_respond ? uncache_resp_bits_uop_br_tag : cache_resp_0_bits_uop_br_tag; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ftq_idx = uncache_respond ? uncache_resp_bits_uop_ftq_idx : cache_resp_0_bits_uop_ftq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_edge_inst = uncache_respond ? uncache_resp_bits_uop_edge_inst : cache_resp_0_bits_uop_edge_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_pc_lob = uncache_respond ? uncache_resp_bits_uop_pc_lob : cache_resp_0_bits_uop_pc_lob; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_taken = uncache_respond ? uncache_resp_bits_uop_taken : cache_resp_0_bits_uop_taken; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_imm_packed = uncache_respond ? uncache_resp_bits_uop_imm_packed : cache_resp_0_bits_uop_imm_packed; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_csr_addr = uncache_respond ? uncache_resp_bits_uop_csr_addr : cache_resp_0_bits_uop_csr_addr; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_rob_idx = uncache_respond ? uncache_resp_bits_uop_rob_idx : cache_resp_0_bits_uop_rob_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldq_idx = uncache_respond ? uncache_resp_bits_uop_ldq_idx : cache_resp_0_bits_uop_ldq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_stq_idx = uncache_respond ? uncache_resp_bits_uop_stq_idx : cache_resp_0_bits_uop_stq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_rxq_idx = uncache_respond ? uncache_resp_bits_uop_rxq_idx : cache_resp_0_bits_uop_rxq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_pdst = uncache_respond ? uncache_resp_bits_uop_pdst : cache_resp_0_bits_uop_pdst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs1 = uncache_respond ? uncache_resp_bits_uop_prs1 : cache_resp_0_bits_uop_prs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs2 = uncache_respond ? uncache_resp_bits_uop_prs2 : cache_resp_0_bits_uop_prs2; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs3 = uncache_respond ? uncache_resp_bits_uop_prs3 : cache_resp_0_bits_uop_prs3; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ppred = uncache_respond ? uncache_resp_bits_uop_ppred : cache_resp_0_bits_uop_ppred; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs1_busy = uncache_respond ? uncache_resp_bits_uop_prs1_busy : cache_resp_0_bits_uop_prs1_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs2_busy = uncache_respond ? uncache_resp_bits_uop_prs2_busy : cache_resp_0_bits_uop_prs2_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs3_busy = uncache_respond ? uncache_resp_bits_uop_prs3_busy : cache_resp_0_bits_uop_prs3_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ppred_busy = uncache_respond ? uncache_resp_bits_uop_ppred_busy : cache_resp_0_bits_uop_ppred_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_stale_pdst = uncache_respond ? uncache_resp_bits_uop_stale_pdst : cache_resp_0_bits_uop_stale_pdst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_exception = uncache_respond ? uncache_resp_bits_uop_exception : cache_resp_0_bits_uop_exception; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_exc_cause = uncache_respond ? uncache_resp_bits_uop_exc_cause : cache_resp_0_bits_uop_exc_cause; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bypassable = uncache_respond ? uncache_resp_bits_uop_bypassable : cache_resp_0_bits_uop_bypassable; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_cmd = uncache_respond ? uncache_resp_bits_uop_mem_cmd : cache_resp_0_bits_uop_mem_cmd; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_size = uncache_respond ? uncache_resp_bits_uop_mem_size : cache_resp_0_bits_uop_mem_size; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_signed = uncache_respond ? uncache_resp_bits_uop_mem_signed : cache_resp_0_bits_uop_mem_signed; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_fence = uncache_respond ? uncache_resp_bits_uop_is_fence : cache_resp_0_bits_uop_is_fence; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_fencei = uncache_respond ? uncache_resp_bits_uop_is_fencei : cache_resp_0_bits_uop_is_fencei; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_amo = uncache_respond ? uncache_resp_bits_uop_is_amo : cache_resp_0_bits_uop_is_amo; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uses_ldq = uncache_respond ? uncache_resp_bits_uop_uses_ldq : cache_resp_0_bits_uop_uses_ldq; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uses_stq = uncache_respond ? uncache_resp_bits_uop_uses_stq : cache_resp_0_bits_uop_uses_stq; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_sys_pc2epc = uncache_respond ? uncache_resp_bits_uop_is_sys_pc2epc : cache_resp_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_unique = uncache_respond ? uncache_resp_bits_uop_is_unique : cache_resp_0_bits_uop_is_unique; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_flush_on_commit = uncache_respond ? uncache_resp_bits_uop_flush_on_commit : cache_resp_0_bits_uop_flush_on_commit; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst_is_rs1 = uncache_respond ? uncache_resp_bits_uop_ldst_is_rs1 : cache_resp_0_bits_uop_ldst_is_rs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst = uncache_respond ? uncache_resp_bits_uop_ldst : cache_resp_0_bits_uop_ldst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs1 = uncache_respond ? uncache_resp_bits_uop_lrs1 : cache_resp_0_bits_uop_lrs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs2 = uncache_respond ? uncache_resp_bits_uop_lrs2 : cache_resp_0_bits_uop_lrs2; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs3 = uncache_respond ? uncache_resp_bits_uop_lrs3 : cache_resp_0_bits_uop_lrs3; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst_val = uncache_respond ? uncache_resp_bits_uop_ldst_val : cache_resp_0_bits_uop_ldst_val; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_dst_rtype = uncache_respond ? uncache_resp_bits_uop_dst_rtype : cache_resp_0_bits_uop_dst_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs1_rtype = uncache_respond ? uncache_resp_bits_uop_lrs1_rtype : cache_resp_0_bits_uop_lrs1_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs2_rtype = uncache_respond ? uncache_resp_bits_uop_lrs2_rtype : cache_resp_0_bits_uop_lrs2_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_frs3_en = uncache_respond ? uncache_resp_bits_uop_frs3_en : cache_resp_0_bits_uop_frs3_en; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fp_val = uncache_respond ? uncache_resp_bits_uop_fp_val : cache_resp_0_bits_uop_fp_val; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fp_single = uncache_respond ? uncache_resp_bits_uop_fp_single : cache_resp_0_bits_uop_fp_single; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_pf_if = uncache_respond ? uncache_resp_bits_uop_xcpt_pf_if : cache_resp_0_bits_uop_xcpt_pf_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_ae_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ae_if : cache_resp_0_bits_uop_xcpt_ae_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_ma_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ma_if : cache_resp_0_bits_uop_xcpt_ma_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bp_debug_if = uncache_respond ? uncache_resp_bits_uop_bp_debug_if : cache_resp_0_bits_uop_bp_debug_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bp_xcpt_if = uncache_respond ? uncache_resp_bits_uop_bp_xcpt_if : cache_resp_0_bits_uop_bp_xcpt_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_fsrc = uncache_respond ? uncache_resp_bits_uop_debug_fsrc : cache_resp_0_bits_uop_debug_fsrc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_tsrc = uncache_respond ? uncache_resp_bits_uop_debug_tsrc : cache_resp_0_bits_uop_debug_tsrc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_data = uncache_respond ? uncache_resp_bits_data : cache_resp_0_bits_data; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_is_hella = uncache_respond ? uncache_resp_bits_is_hella : cache_resp_0_bits_is_hella; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
wire _io_lsu_resp_0_valid_T = io_lsu_exception_0 & resp_0_bits_uop_uses_ldq; // @[dcache.scala:413:7, :846:22, :858:48]
wire _io_lsu_resp_0_valid_T_1 = ~_io_lsu_resp_0_valid_T; // @[dcache.scala:858:{29,48}]
wire _io_lsu_resp_0_valid_T_2 = resp_0_valid & _io_lsu_resp_0_valid_T_1; // @[dcache.scala:846:22, :857:43, :858:29]
wire [7:0] _io_lsu_resp_0_valid_T_3 = io_lsu_brupdate_b1_mispredict_mask_0 & resp_0_bits_uop_br_mask; // @[util.scala:118:51]
wire _io_lsu_resp_0_valid_T_4 = |_io_lsu_resp_0_valid_T_3; // @[util.scala:118:{51,59}]
wire _io_lsu_resp_0_valid_T_5 = ~_io_lsu_resp_0_valid_T_4; // @[util.scala:118:59]
assign _io_lsu_resp_0_valid_T_6 = _io_lsu_resp_0_valid_T_2 & _io_lsu_resp_0_valid_T_5; // @[dcache.scala:857:43, :858:78, :859:29]
assign io_lsu_resp_0_valid_0 = _io_lsu_resp_0_valid_T_6; // @[dcache.scala:413:7, :858:78]
assign io_lsu_resp_0_bits_uop_uopc_0 = io_lsu_resp_0_bits_out_uop_uopc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_inst_0 = io_lsu_resp_0_bits_out_uop_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_inst_0 = io_lsu_resp_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_rvc_0 = io_lsu_resp_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_pc_0 = io_lsu_resp_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iq_type_0 = io_lsu_resp_0_bits_out_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fu_code_0 = io_lsu_resp_0_bits_out_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_br_type_0 = io_lsu_resp_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op1_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op2_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_imm_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op_fcn_0 = io_lsu_resp_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_load_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_sta_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_std_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_state_0 = io_lsu_resp_0_bits_out_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_p1_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_p2_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_br_0 = io_lsu_resp_0_bits_out_uop_is_br; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_jalr_0 = io_lsu_resp_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_jal_0 = io_lsu_resp_0_bits_out_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_sfb_0 = io_lsu_resp_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [7:0] _io_lsu_resp_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21]
assign io_lsu_resp_0_bits_uop_br_mask_0 = io_lsu_resp_0_bits_out_uop_br_mask; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_br_tag_0 = io_lsu_resp_0_bits_out_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ftq_idx_0 = io_lsu_resp_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_edge_inst_0 = io_lsu_resp_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_pc_lob_0 = io_lsu_resp_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_taken_0 = io_lsu_resp_0_bits_out_uop_taken; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_imm_packed_0 = io_lsu_resp_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_csr_addr_0 = io_lsu_resp_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_rob_idx_0 = io_lsu_resp_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldq_idx_0 = io_lsu_resp_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_stq_idx_0 = io_lsu_resp_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_rxq_idx_0 = io_lsu_resp_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_pdst_0 = io_lsu_resp_0_bits_out_uop_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs1_0 = io_lsu_resp_0_bits_out_uop_prs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs2_0 = io_lsu_resp_0_bits_out_uop_prs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs3_0 = io_lsu_resp_0_bits_out_uop_prs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ppred_0 = io_lsu_resp_0_bits_out_uop_ppred; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs1_busy_0 = io_lsu_resp_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs2_busy_0 = io_lsu_resp_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs3_busy_0 = io_lsu_resp_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ppred_busy_0 = io_lsu_resp_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_stale_pdst_0 = io_lsu_resp_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_exception_0 = io_lsu_resp_0_bits_out_uop_exception; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_exc_cause_0 = io_lsu_resp_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bypassable_0 = io_lsu_resp_0_bits_out_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_cmd_0 = io_lsu_resp_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_size_0 = io_lsu_resp_0_bits_out_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_signed_0 = io_lsu_resp_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_fence_0 = io_lsu_resp_0_bits_out_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_fencei_0 = io_lsu_resp_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_amo_0 = io_lsu_resp_0_bits_out_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_uses_ldq_0 = io_lsu_resp_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_uses_stq_0 = io_lsu_resp_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_resp_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_unique_0 = io_lsu_resp_0_bits_out_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_flush_on_commit_0 = io_lsu_resp_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_is_rs1_0 = io_lsu_resp_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_0 = io_lsu_resp_0_bits_out_uop_ldst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs1_0 = io_lsu_resp_0_bits_out_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs2_0 = io_lsu_resp_0_bits_out_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs3_0 = io_lsu_resp_0_bits_out_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_val_0 = io_lsu_resp_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_dst_rtype_0 = io_lsu_resp_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs1_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs2_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_frs3_en_0 = io_lsu_resp_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fp_val_0 = io_lsu_resp_0_bits_out_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fp_single_0 = io_lsu_resp_0_bits_out_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_pf_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_ae_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_ma_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bp_debug_if_0 = io_lsu_resp_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bp_xcpt_if_0 = io_lsu_resp_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_fsrc_0 = io_lsu_resp_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_tsrc_0 = io_lsu_resp_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_data_0 = io_lsu_resp_0_bits_out_data; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_is_hella_0 = io_lsu_resp_0_bits_out_is_hella; // @[util.scala:101:23]
wire [7:0] _io_lsu_resp_0_bits_out_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _io_lsu_resp_0_bits_out_uop_br_mask_T_1 = resp_0_bits_uop_br_mask & _io_lsu_resp_0_bits_out_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign io_lsu_resp_0_bits_out_uop_br_mask = _io_lsu_resp_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21, :101:23]
wire _io_lsu_nack_0_valid_T = s2_valid_0 & s2_send_nack_0; // @[dcache.scala:427:49, :862:41]
wire _io_lsu_nack_0_valid_T_2 = ~_io_lsu_nack_0_valid_T_1; // @[dcache.scala:863:{29,48}]
wire _io_lsu_nack_0_valid_T_3 = _io_lsu_nack_0_valid_T & _io_lsu_nack_0_valid_T_2; // @[dcache.scala:862:{41,60}, :863:29]
wire _io_lsu_nack_0_valid_T_5 = |_io_lsu_nack_0_valid_T_4; // @[util.scala:118:{51,59}]
wire _io_lsu_nack_0_valid_T_6 = ~_io_lsu_nack_0_valid_T_5; // @[util.scala:118:59]
assign _io_lsu_nack_0_valid_T_7 = _io_lsu_nack_0_valid_T_3 & _io_lsu_nack_0_valid_T_6; // @[dcache.scala:862:60, :863:75, :864:29]
assign io_lsu_nack_0_valid_0 = _io_lsu_nack_0_valid_T_7; // @[dcache.scala:413:7, :863:75]
assign io_lsu_nack_0_bits_uop_uopc_0 = io_lsu_nack_0_bits_out_uop_uopc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_inst_0 = io_lsu_nack_0_bits_out_uop_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_inst_0 = io_lsu_nack_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_rvc_0 = io_lsu_nack_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_pc_0 = io_lsu_nack_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iq_type_0 = io_lsu_nack_0_bits_out_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fu_code_0 = io_lsu_nack_0_bits_out_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_br_type_0 = io_lsu_nack_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op1_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op2_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_imm_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op_fcn_0 = io_lsu_nack_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_load_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_sta_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_std_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_state_0 = io_lsu_nack_0_bits_out_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_p1_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_p2_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_br_0 = io_lsu_nack_0_bits_out_uop_is_br; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_jalr_0 = io_lsu_nack_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_jal_0 = io_lsu_nack_0_bits_out_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_sfb_0 = io_lsu_nack_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [7:0] _io_lsu_nack_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21]
assign io_lsu_nack_0_bits_uop_br_mask_0 = io_lsu_nack_0_bits_out_uop_br_mask; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_br_tag_0 = io_lsu_nack_0_bits_out_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ftq_idx_0 = io_lsu_nack_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_edge_inst_0 = io_lsu_nack_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_pc_lob_0 = io_lsu_nack_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_taken_0 = io_lsu_nack_0_bits_out_uop_taken; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_imm_packed_0 = io_lsu_nack_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_csr_addr_0 = io_lsu_nack_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_rob_idx_0 = io_lsu_nack_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldq_idx_0 = io_lsu_nack_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_stq_idx_0 = io_lsu_nack_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_rxq_idx_0 = io_lsu_nack_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_pdst_0 = io_lsu_nack_0_bits_out_uop_pdst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs1_0 = io_lsu_nack_0_bits_out_uop_prs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs2_0 = io_lsu_nack_0_bits_out_uop_prs2; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs3_0 = io_lsu_nack_0_bits_out_uop_prs3; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ppred_0 = io_lsu_nack_0_bits_out_uop_ppred; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs1_busy_0 = io_lsu_nack_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs2_busy_0 = io_lsu_nack_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs3_busy_0 = io_lsu_nack_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ppred_busy_0 = io_lsu_nack_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_stale_pdst_0 = io_lsu_nack_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_exception_0 = io_lsu_nack_0_bits_out_uop_exception; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_exc_cause_0 = io_lsu_nack_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bypassable_0 = io_lsu_nack_0_bits_out_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_cmd_0 = io_lsu_nack_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_size_0 = io_lsu_nack_0_bits_out_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_signed_0 = io_lsu_nack_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_fence_0 = io_lsu_nack_0_bits_out_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_fencei_0 = io_lsu_nack_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_amo_0 = io_lsu_nack_0_bits_out_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_uses_ldq_0 = io_lsu_nack_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_uses_stq_0 = io_lsu_nack_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_sys_pc2epc_0 = io_lsu_nack_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_unique_0 = io_lsu_nack_0_bits_out_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_flush_on_commit_0 = io_lsu_nack_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_is_rs1_0 = io_lsu_nack_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_0 = io_lsu_nack_0_bits_out_uop_ldst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs1_0 = io_lsu_nack_0_bits_out_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs2_0 = io_lsu_nack_0_bits_out_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs3_0 = io_lsu_nack_0_bits_out_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_val_0 = io_lsu_nack_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_dst_rtype_0 = io_lsu_nack_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs1_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs2_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_frs3_en_0 = io_lsu_nack_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fp_val_0 = io_lsu_nack_0_bits_out_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fp_single_0 = io_lsu_nack_0_bits_out_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_pf_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_ae_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_ma_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bp_debug_if_0 = io_lsu_nack_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bp_xcpt_if_0 = io_lsu_nack_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_fsrc_0 = io_lsu_nack_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_tsrc_0 = io_lsu_nack_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_addr_0 = io_lsu_nack_0_bits_out_addr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_data_0 = io_lsu_nack_0_bits_out_data; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_is_hella_0 = io_lsu_nack_0_bits_out_is_hella; // @[util.scala:101:23]
wire [7:0] _io_lsu_nack_0_bits_out_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _io_lsu_nack_0_bits_out_uop_br_mask_T_1 = s2_req_0_uop_br_mask & _io_lsu_nack_0_bits_out_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign io_lsu_nack_0_bits_out_uop_br_mask = _io_lsu_nack_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21, :101:23] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_30 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_30
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_30( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_30 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FixedClockBroadcast_7_2 :
output auto : { flip anon_in : { clock : Clock, reset : Reset}, anon_out_6 : { clock : Clock, reset : Reset}, anon_out_5 : { clock : Clock, reset : Reset}, anon_out_4 : { clock : Clock, reset : Reset}, anon_out_3 : { clock : Clock, reset : Reset}, anon_out_2 : { clock : Clock, reset : Reset}, anon_out_1 : { clock : Clock, reset : Reset}, anon_out_0 : { clock : Clock, reset : Reset}}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire anonIn : { clock : Clock, reset : Reset}
invalidate anonIn.reset
invalidate anonIn.clock
wire anonOut : { clock : Clock, reset : Reset}
invalidate anonOut.reset
invalidate anonOut.clock
wire x1_anonOut : { clock : Clock, reset : Reset}
invalidate x1_anonOut.reset
invalidate x1_anonOut.clock
wire x1_anonOut_1 : { clock : Clock, reset : Reset}
invalidate x1_anonOut_1.reset
invalidate x1_anonOut_1.clock
wire x1_anonOut_2 : { clock : Clock, reset : Reset}
invalidate x1_anonOut_2.reset
invalidate x1_anonOut_2.clock
wire x1_anonOut_3 : { clock : Clock, reset : Reset}
invalidate x1_anonOut_3.reset
invalidate x1_anonOut_3.clock
wire x1_anonOut_4 : { clock : Clock, reset : Reset}
invalidate x1_anonOut_4.reset
invalidate x1_anonOut_4.clock
wire x1_anonOut_5 : { clock : Clock, reset : Reset}
invalidate x1_anonOut_5.reset
invalidate x1_anonOut_5.clock
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect auto.anon_out_2, x1_anonOut_1
connect auto.anon_out_3, x1_anonOut_2
connect auto.anon_out_4, x1_anonOut_3
connect auto.anon_out_5, x1_anonOut_4
connect auto.anon_out_6, x1_anonOut_5
connect anonIn, auto.anon_in
connect anonOut, anonIn
connect x1_anonOut, anonIn
connect x1_anonOut_1, anonIn
connect x1_anonOut_2, anonIn
connect x1_anonOut_3, anonIn
connect x1_anonOut_4, anonIn
connect x1_anonOut_5, anonIn | module FixedClockBroadcast_7_2( // @[ClockGroup.scala:104:9]
input auto_anon_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_clock_0 = auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire auto_anon_in_reset_0 = auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_clock = auto_anon_in_clock_0; // @[ClockGroup.scala:104:9]
wire anonIn_reset = auto_anon_in_reset_0; // @[ClockGroup.scala:104:9]
wire x1_anonOut_5_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_5_reset; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_reset; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_reset; // @[MixedNode.scala:542:17]
wire x1_anonOut_2_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_2_reset; // @[MixedNode.scala:542:17]
wire x1_anonOut_1_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_1_reset; // @[MixedNode.scala:542:17]
wire x1_anonOut_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_reset; // @[MixedNode.scala:542:17]
wire anonOut_clock; // @[MixedNode.scala:542:17]
wire anonOut_reset; // @[MixedNode.scala:542:17]
wire auto_anon_out_6_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_6_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_5_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_5_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_4_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_4_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_3_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_3_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_2_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_2_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_1_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_1_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_0_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_0_reset_0; // @[ClockGroup.scala:104:9]
assign anonOut_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_1_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_2_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_3_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_4_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_5_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_1_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_2_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_3_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_4_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_5_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_clock_0 = anonOut_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_reset_0 = anonOut_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_clock_0 = x1_anonOut_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_reset_0 = x1_anonOut_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_clock_0 = x1_anonOut_1_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_reset_0 = x1_anonOut_1_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_3_clock_0 = x1_anonOut_2_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_3_reset_0 = x1_anonOut_2_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_4_clock_0 = x1_anonOut_3_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_4_reset_0 = x1_anonOut_3_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_5_clock_0 = x1_anonOut_4_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_5_reset_0 = x1_anonOut_4_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_6_clock_0 = x1_anonOut_5_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_6_reset_0 = x1_anonOut_5_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_6_clock = auto_anon_out_6_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_6_reset = auto_anon_out_6_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_5_clock = auto_anon_out_5_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_5_reset = auto_anon_out_5_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_4_clock = auto_anon_out_4_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_4_reset = auto_anon_out_4_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_3_clock = auto_anon_out_3_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_3_reset = auto_anon_out_3_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_clock = auto_anon_out_2_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_reset = auto_anon_out_2_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_clock = auto_anon_out_1_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_reset = auto_anon_out_1_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_clock = auto_anon_out_0_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_reset = auto_anon_out_0_reset_0; // @[ClockGroup.scala:104:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_509 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_509( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_305 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_305( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BoomWritebackUnit :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, resp : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, data_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>}}, flip data_resp : UInt<128>, flip mem_grant : UInt<1>, release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, lsu_release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
reg req : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}, clock
regreset state : UInt<3>, clock, reset, UInt<3>(0h0)
regreset r1_data_req_fired : UInt<1>, clock, reset, UInt<1>(0h0)
regreset r2_data_req_fired : UInt<1>, clock, reset, UInt<1>(0h0)
reg r1_data_req_cnt : UInt<3>, clock
reg r2_data_req_cnt : UInt<3>, clock
regreset data_req_cnt : UInt<3>, clock, reset, UInt<3>(0h0)
node _T = and(io.release.ready, io.release.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.release.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 4)
node r_beats1_opdata = bits(io.release.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node last_beat = or(_r_last_T, _r_last_T_1)
node all_beats_done = and(last_beat, _T)
node _r_count_T = not(r_counter1)
node beat_count = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
reg wb_buffer : UInt<128>[4], clock
regreset acked : UInt<1>, clock, reset, UInt<1>(0h0)
node _io_idx_valid_T = neq(state, UInt<3>(0h0))
connect io.idx.valid, _io_idx_valid_T
connect io.idx.bits, req.idx
connect io.release.valid, UInt<1>(0h0)
invalidate io.release.bits.corrupt
invalidate io.release.bits.data
invalidate io.release.bits.address
invalidate io.release.bits.source
invalidate io.release.bits.size
invalidate io.release.bits.param
invalidate io.release.bits.opcode
connect io.req.ready, UInt<1>(0h0)
connect io.meta_read.valid, UInt<1>(0h0)
invalidate io.meta_read.bits.tag
invalidate io.meta_read.bits.way_en
invalidate io.meta_read.bits.idx
connect io.data_req.valid, UInt<1>(0h0)
invalidate io.data_req.bits.addr
invalidate io.data_req.bits.way_en
connect io.resp, UInt<1>(0h0)
connect io.lsu_release.valid, UInt<1>(0h0)
invalidate io.lsu_release.bits.corrupt
invalidate io.lsu_release.bits.data
invalidate io.lsu_release.bits.address
invalidate io.lsu_release.bits.source
invalidate io.lsu_release.bits.size
invalidate io.lsu_release.bits.param
invalidate io.lsu_release.bits.opcode
node _r_address_T = cat(req.tag, req.idx)
node r_address = shl(_r_address_T, 6)
node _probeResponse_T = bits(data_req_cnt, 1, 0)
wire probeResponse : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}
connect probeResponse.opcode, UInt<3>(0h5)
connect probeResponse.param, req.param
connect probeResponse.size, UInt<3>(0h6)
connect probeResponse.source, req.source
connect probeResponse.address, r_address
connect probeResponse.data, wb_buffer[_probeResponse_T]
connect probeResponse.corrupt, UInt<1>(0h0)
node _voluntaryRelease_T = bits(data_req_cnt, 1, 0)
node _voluntaryRelease_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _voluntaryRelease_legal_T_1 = xor(r_address, UInt<1>(0h0))
node _voluntaryRelease_legal_T_2 = cvt(_voluntaryRelease_legal_T_1)
node _voluntaryRelease_legal_T_3 = and(_voluntaryRelease_legal_T_2, asSInt(UInt<33>(0h8c000000)))
node _voluntaryRelease_legal_T_4 = asSInt(_voluntaryRelease_legal_T_3)
node _voluntaryRelease_legal_T_5 = eq(_voluntaryRelease_legal_T_4, asSInt(UInt<1>(0h0)))
node _voluntaryRelease_legal_T_6 = xor(r_address, UInt<17>(0h10000))
node _voluntaryRelease_legal_T_7 = cvt(_voluntaryRelease_legal_T_6)
node _voluntaryRelease_legal_T_8 = and(_voluntaryRelease_legal_T_7, asSInt(UInt<33>(0h8c011000)))
node _voluntaryRelease_legal_T_9 = asSInt(_voluntaryRelease_legal_T_8)
node _voluntaryRelease_legal_T_10 = eq(_voluntaryRelease_legal_T_9, asSInt(UInt<1>(0h0)))
node _voluntaryRelease_legal_T_11 = xor(r_address, UInt<28>(0hc000000))
node _voluntaryRelease_legal_T_12 = cvt(_voluntaryRelease_legal_T_11)
node _voluntaryRelease_legal_T_13 = and(_voluntaryRelease_legal_T_12, asSInt(UInt<33>(0h8c000000)))
node _voluntaryRelease_legal_T_14 = asSInt(_voluntaryRelease_legal_T_13)
node _voluntaryRelease_legal_T_15 = eq(_voluntaryRelease_legal_T_14, asSInt(UInt<1>(0h0)))
node _voluntaryRelease_legal_T_16 = or(_voluntaryRelease_legal_T_5, _voluntaryRelease_legal_T_10)
node _voluntaryRelease_legal_T_17 = or(_voluntaryRelease_legal_T_16, _voluntaryRelease_legal_T_15)
node _voluntaryRelease_legal_T_18 = and(_voluntaryRelease_legal_T, _voluntaryRelease_legal_T_17)
node _voluntaryRelease_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _voluntaryRelease_legal_T_20 = or(UInt<1>(0h0), _voluntaryRelease_legal_T_19)
node _voluntaryRelease_legal_T_21 = xor(r_address, UInt<28>(0h8000000))
node _voluntaryRelease_legal_T_22 = cvt(_voluntaryRelease_legal_T_21)
node _voluntaryRelease_legal_T_23 = and(_voluntaryRelease_legal_T_22, asSInt(UInt<33>(0h8c010000)))
node _voluntaryRelease_legal_T_24 = asSInt(_voluntaryRelease_legal_T_23)
node _voluntaryRelease_legal_T_25 = eq(_voluntaryRelease_legal_T_24, asSInt(UInt<1>(0h0)))
node _voluntaryRelease_legal_T_26 = xor(r_address, UInt<32>(0h80000000))
node _voluntaryRelease_legal_T_27 = cvt(_voluntaryRelease_legal_T_26)
node _voluntaryRelease_legal_T_28 = and(_voluntaryRelease_legal_T_27, asSInt(UInt<33>(0h80000000)))
node _voluntaryRelease_legal_T_29 = asSInt(_voluntaryRelease_legal_T_28)
node _voluntaryRelease_legal_T_30 = eq(_voluntaryRelease_legal_T_29, asSInt(UInt<1>(0h0)))
node _voluntaryRelease_legal_T_31 = or(_voluntaryRelease_legal_T_25, _voluntaryRelease_legal_T_30)
node _voluntaryRelease_legal_T_32 = and(_voluntaryRelease_legal_T_20, _voluntaryRelease_legal_T_31)
node _voluntaryRelease_legal_T_33 = or(UInt<1>(0h0), _voluntaryRelease_legal_T_18)
node voluntaryRelease_legal = or(_voluntaryRelease_legal_T_33, _voluntaryRelease_legal_T_32)
wire voluntaryRelease : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}
connect voluntaryRelease.opcode, UInt<3>(0h7)
connect voluntaryRelease.param, req.param
connect voluntaryRelease.size, UInt<3>(0h6)
connect voluntaryRelease.source, UInt<3>(0h4)
connect voluntaryRelease.address, r_address
connect voluntaryRelease.data, wb_buffer[_voluntaryRelease_T]
connect voluntaryRelease.corrupt, UInt<1>(0h0)
node _T_1 = eq(state, UInt<3>(0h0))
when _T_1 :
connect io.req.ready, UInt<1>(0h1)
node _T_2 = and(io.req.ready, io.req.valid)
when _T_2 :
connect state, UInt<3>(0h1)
connect data_req_cnt, UInt<1>(0h0)
connect req, io.req.bits
connect acked, UInt<1>(0h0)
else :
node _T_3 = eq(state, UInt<3>(0h1))
when _T_3 :
node _io_meta_read_valid_T = lt(data_req_cnt, UInt<3>(0h4))
connect io.meta_read.valid, _io_meta_read_valid_T
connect io.meta_read.bits.idx, req.idx
connect io.meta_read.bits.tag, req.tag
node _io_data_req_valid_T = lt(data_req_cnt, UInt<3>(0h4))
connect io.data_req.valid, _io_data_req_valid_T
connect io.data_req.bits.way_en, req.way_en
node _io_data_req_bits_addr_T = bits(data_req_cnt, 1, 0)
node _io_data_req_bits_addr_T_1 = cat(req.idx, _io_data_req_bits_addr_T)
node _io_data_req_bits_addr_T_2 = shl(_io_data_req_bits_addr_T_1, 4)
connect io.data_req.bits.addr, _io_data_req_bits_addr_T_2
connect r1_data_req_fired, UInt<1>(0h0)
connect r1_data_req_cnt, UInt<1>(0h0)
connect r2_data_req_fired, r1_data_req_fired
connect r2_data_req_cnt, r1_data_req_cnt
node _T_4 = and(io.data_req.ready, io.data_req.valid)
node _T_5 = and(io.meta_read.ready, io.meta_read.valid)
node _T_6 = and(_T_4, _T_5)
when _T_6 :
connect r1_data_req_fired, UInt<1>(0h1)
connect r1_data_req_cnt, data_req_cnt
node _data_req_cnt_T = add(data_req_cnt, UInt<1>(0h1))
node _data_req_cnt_T_1 = tail(_data_req_cnt_T, 1)
connect data_req_cnt, _data_req_cnt_T_1
when r2_data_req_fired :
node _T_7 = bits(r2_data_req_cnt, 1, 0)
connect wb_buffer[_T_7], io.data_resp
node _T_8 = eq(r2_data_req_cnt, UInt<2>(0h3))
when _T_8 :
connect io.resp, UInt<1>(0h1)
connect state, UInt<3>(0h2)
connect data_req_cnt, UInt<1>(0h0)
else :
node _T_9 = eq(state, UInt<3>(0h2))
when _T_9 :
connect io.lsu_release.valid, UInt<1>(0h1)
connect io.lsu_release.bits, probeResponse
node _T_10 = and(io.lsu_release.ready, io.lsu_release.valid)
when _T_10 :
connect state, UInt<3>(0h3)
else :
node _T_11 = eq(state, UInt<3>(0h3))
when _T_11 :
node _io_release_valid_T = lt(data_req_cnt, UInt<3>(0h4))
connect io.release.valid, _io_release_valid_T
node _io_release_bits_T = mux(req.voluntary, voluntaryRelease, probeResponse)
connect io.release.bits, _io_release_bits_T
when io.mem_grant :
connect acked, UInt<1>(0h1)
node _T_12 = and(io.release.ready, io.release.valid)
when _T_12 :
node _data_req_cnt_T_2 = add(data_req_cnt, UInt<1>(0h1))
node _data_req_cnt_T_3 = tail(_data_req_cnt_T_2, 1)
connect data_req_cnt, _data_req_cnt_T_3
node _T_13 = eq(data_req_cnt, UInt<2>(0h3))
node _T_14 = and(io.release.ready, io.release.valid)
node _T_15 = and(_T_13, _T_14)
when _T_15 :
node _state_T = mux(req.voluntary, UInt<3>(0h4), UInt<3>(0h0))
connect state, _state_T
else :
node _T_16 = eq(state, UInt<3>(0h4))
when _T_16 :
when io.mem_grant :
connect acked, UInt<1>(0h1)
when acked :
connect state, UInt<3>(0h0) | module BoomWritebackUnit( // @[dcache.scala:24:7]
input clock, // @[dcache.scala:24:7]
input reset, // @[dcache.scala:24:7]
output io_req_ready, // @[dcache.scala:25:14]
input io_req_valid, // @[dcache.scala:25:14]
input [19:0] io_req_bits_tag, // @[dcache.scala:25:14]
input [5:0] io_req_bits_idx, // @[dcache.scala:25:14]
input [2:0] io_req_bits_source, // @[dcache.scala:25:14]
input [2:0] io_req_bits_param, // @[dcache.scala:25:14]
input [7:0] io_req_bits_way_en, // @[dcache.scala:25:14]
input io_req_bits_voluntary, // @[dcache.scala:25:14]
input io_meta_read_ready, // @[dcache.scala:25:14]
output io_meta_read_valid, // @[dcache.scala:25:14]
output [5:0] io_meta_read_bits_idx, // @[dcache.scala:25:14]
output [19:0] io_meta_read_bits_tag, // @[dcache.scala:25:14]
output io_resp, // @[dcache.scala:25:14]
output io_idx_valid, // @[dcache.scala:25:14]
output [5:0] io_idx_bits, // @[dcache.scala:25:14]
input io_data_req_ready, // @[dcache.scala:25:14]
output io_data_req_valid, // @[dcache.scala:25:14]
output [7:0] io_data_req_bits_way_en, // @[dcache.scala:25:14]
output [11:0] io_data_req_bits_addr, // @[dcache.scala:25:14]
input [127:0] io_data_resp, // @[dcache.scala:25:14]
input io_mem_grant, // @[dcache.scala:25:14]
input io_release_ready, // @[dcache.scala:25:14]
output io_release_valid, // @[dcache.scala:25:14]
output [2:0] io_release_bits_opcode, // @[dcache.scala:25:14]
output [2:0] io_release_bits_param, // @[dcache.scala:25:14]
output [2:0] io_release_bits_source, // @[dcache.scala:25:14]
output [31:0] io_release_bits_address, // @[dcache.scala:25:14]
output [127:0] io_release_bits_data, // @[dcache.scala:25:14]
input io_lsu_release_ready, // @[dcache.scala:25:14]
output io_lsu_release_valid, // @[dcache.scala:25:14]
output [2:0] io_lsu_release_bits_param, // @[dcache.scala:25:14]
output [2:0] io_lsu_release_bits_source, // @[dcache.scala:25:14]
output [31:0] io_lsu_release_bits_address, // @[dcache.scala:25:14]
output [127:0] io_lsu_release_bits_data // @[dcache.scala:25:14]
);
reg [2:0] state; // @[dcache.scala:39:22]
wire io_req_valid_0 = io_req_valid; // @[dcache.scala:24:7]
wire [19:0] io_req_bits_tag_0 = io_req_bits_tag; // @[dcache.scala:24:7]
wire [5:0] io_req_bits_idx_0 = io_req_bits_idx; // @[dcache.scala:24:7]
wire [2:0] io_req_bits_source_0 = io_req_bits_source; // @[dcache.scala:24:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[dcache.scala:24:7]
wire [7:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[dcache.scala:24:7]
wire io_req_bits_voluntary_0 = io_req_bits_voluntary; // @[dcache.scala:24:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[dcache.scala:24:7]
wire io_data_req_ready_0 = io_data_req_ready; // @[dcache.scala:24:7]
wire [127:0] io_data_resp_0 = io_data_resp; // @[dcache.scala:24:7]
wire io_mem_grant_0 = io_mem_grant; // @[dcache.scala:24:7]
wire io_release_ready_0 = io_release_ready; // @[dcache.scala:24:7]
wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:24:7]
wire [26:0] _r_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _r_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [7:0] r_beats1_decode = 8'h3; // @[Edges.scala:220:59]
wire _voluntaryRelease_legal_T_19 = 1'h1; // @[Parameters.scala:91:44]
wire _voluntaryRelease_legal_T_20 = 1'h1; // @[Parameters.scala:684:29]
wire [2:0] voluntaryRelease_opcode = 3'h7; // @[Edges.scala:396:17]
wire [2:0] voluntaryRelease_source = 3'h4; // @[Edges.scala:396:17]
wire [2:0] io_lsu_release_bits_opcode = 3'h5; // @[dcache.scala:24:7]
wire [2:0] probeResponse_opcode = 3'h5; // @[Edges.scala:433:17]
wire io_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7]
wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:24:7]
wire probeResponse_corrupt = 1'h0; // @[Edges.scala:433:17]
wire _voluntaryRelease_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _voluntaryRelease_legal_T_18 = 1'h0; // @[Parameters.scala:684:54]
wire _voluntaryRelease_legal_T_33 = 1'h0; // @[Parameters.scala:686:26]
wire voluntaryRelease_corrupt = 1'h0; // @[Edges.scala:396:17]
wire _io_release_bits_T_corrupt = 1'h0; // @[dcache.scala:124:27]
wire [3:0] io_release_bits_size = 4'h6; // @[dcache.scala:24:7]
wire [3:0] io_lsu_release_bits_size = 4'h6; // @[dcache.scala:24:7]
wire [3:0] probeResponse_size = 4'h6; // @[Edges.scala:433:17]
wire [3:0] voluntaryRelease_size = 4'h6; // @[Edges.scala:396:17]
wire [3:0] _io_release_bits_T_size = 4'h6; // @[dcache.scala:124:27]
wire [7:0] io_meta_read_bits_way_en = 8'h0; // @[dcache.scala:24:7]
wire io_req_ready_0 = ~(|state); // @[dcache.scala:24:7, :39:22, :49:31, :80:15]
wire _io_idx_valid_T; // @[dcache.scala:49:31]
wire [11:0] _io_data_req_bits_addr_T_2; // @[dcache.scala:97:43]
wire [2:0] _io_release_bits_T_opcode; // @[dcache.scala:124:27]
wire [2:0] _io_release_bits_T_param; // @[dcache.scala:124:27]
wire [2:0] _io_release_bits_T_source; // @[dcache.scala:124:27]
wire [31:0] _io_release_bits_T_address; // @[dcache.scala:124:27]
wire [127:0] _io_release_bits_T_data; // @[dcache.scala:124:27]
wire [2:0] probeResponse_param; // @[Edges.scala:433:17]
wire [2:0] probeResponse_source; // @[Edges.scala:433:17]
wire [31:0] probeResponse_address; // @[Edges.scala:433:17]
wire [127:0] probeResponse_data; // @[Edges.scala:433:17]
wire [5:0] io_meta_read_bits_idx_0; // @[dcache.scala:24:7]
wire [19:0] io_meta_read_bits_tag_0; // @[dcache.scala:24:7]
wire io_meta_read_valid_0; // @[dcache.scala:24:7]
wire io_idx_valid_0; // @[dcache.scala:24:7]
wire [5:0] io_idx_bits_0; // @[dcache.scala:24:7]
wire [7:0] io_data_req_bits_way_en_0; // @[dcache.scala:24:7]
wire [11:0] io_data_req_bits_addr_0; // @[dcache.scala:24:7]
wire io_data_req_valid_0; // @[dcache.scala:24:7]
wire [2:0] io_release_bits_opcode_0; // @[dcache.scala:24:7]
wire [2:0] io_release_bits_param_0; // @[dcache.scala:24:7]
wire [2:0] io_release_bits_source_0; // @[dcache.scala:24:7]
wire [31:0] io_release_bits_address_0; // @[dcache.scala:24:7]
wire [127:0] io_release_bits_data_0; // @[dcache.scala:24:7]
wire io_release_valid_0; // @[dcache.scala:24:7]
wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:24:7]
wire [2:0] io_lsu_release_bits_source_0; // @[dcache.scala:24:7]
wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:24:7]
wire [127:0] io_lsu_release_bits_data_0; // @[dcache.scala:24:7]
wire io_lsu_release_valid_0; // @[dcache.scala:24:7]
wire io_resp_0; // @[dcache.scala:24:7]
reg [19:0] req_tag; // @[dcache.scala:37:16]
assign io_meta_read_bits_tag_0 = req_tag; // @[dcache.scala:24:7, :37:16]
reg [5:0] req_idx; // @[dcache.scala:37:16]
assign io_meta_read_bits_idx_0 = req_idx; // @[dcache.scala:24:7, :37:16]
assign io_idx_bits_0 = req_idx; // @[dcache.scala:24:7, :37:16]
reg [2:0] req_source; // @[dcache.scala:37:16]
assign probeResponse_source = req_source; // @[Edges.scala:433:17]
reg [2:0] req_param; // @[dcache.scala:37:16]
assign probeResponse_param = req_param; // @[Edges.scala:433:17]
wire [2:0] voluntaryRelease_param = req_param; // @[Edges.scala:396:17]
reg [7:0] req_way_en; // @[dcache.scala:37:16]
assign io_data_req_bits_way_en_0 = req_way_en; // @[dcache.scala:24:7, :37:16]
reg req_voluntary; // @[dcache.scala:37:16]
reg r1_data_req_fired; // @[dcache.scala:40:34]
reg r2_data_req_fired; // @[dcache.scala:41:34]
reg [2:0] r1_data_req_cnt; // @[dcache.scala:42:28]
reg [2:0] r2_data_req_cnt; // @[dcache.scala:43:28]
reg [2:0] data_req_cnt; // @[dcache.scala:44:29]
wire _T_14 = io_release_ready_0 & io_release_valid_0; // @[Decoupled.scala:51:35]
wire r_beats1_opdata = io_release_bits_opcode_0[0]; // @[Edges.scala:102:36]
wire [7:0] r_beats1 = r_beats1_opdata ? 8'h3 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [7:0] r_counter; // @[Edges.scala:229:27]
wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28]
wire r_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire last_beat = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire all_beats_done = last_beat & _T_14; // @[Decoupled.scala:51:35]
wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] beat_count = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [127:0] wb_buffer_0; // @[dcache.scala:46:22]
reg [127:0] wb_buffer_1; // @[dcache.scala:46:22]
reg [127:0] wb_buffer_2; // @[dcache.scala:46:22]
reg [127:0] wb_buffer_3; // @[dcache.scala:46:22]
reg acked; // @[dcache.scala:47:22]
assign _io_idx_valid_T = |state; // @[dcache.scala:39:22, :49:31]
assign io_idx_valid_0 = _io_idx_valid_T; // @[dcache.scala:24:7, :49:31]
wire [25:0] _r_address_T = {req_tag, req_idx}; // @[dcache.scala:37:16, :63:22]
wire [31:0] r_address = {_r_address_T, 6'h0}; // @[dcache.scala:63:{22,41}]
assign probeResponse_address = r_address; // @[Edges.scala:433:17]
wire [31:0] _voluntaryRelease_legal_T_1 = r_address; // @[Parameters.scala:137:31]
wire [31:0] voluntaryRelease_address = r_address; // @[Edges.scala:396:17]
wire [1:0] _probeResponse_T = data_req_cnt[1:0]; // @[dcache.scala:44:29]
wire [1:0] _voluntaryRelease_T = data_req_cnt[1:0]; // @[dcache.scala:44:29]
wire [1:0] _io_data_req_bits_addr_T = data_req_cnt[1:0]; // @[dcache.scala:44:29, :96:56]
assign io_lsu_release_bits_param_0 = probeResponse_param; // @[Edges.scala:433:17]
assign io_lsu_release_bits_source_0 = probeResponse_source; // @[Edges.scala:433:17]
assign io_lsu_release_bits_address_0 = probeResponse_address; // @[Edges.scala:433:17]
assign io_lsu_release_bits_data_0 = probeResponse_data; // @[Edges.scala:433:17]
wire [3:0][127:0] _GEN = {{wb_buffer_3}, {wb_buffer_2}, {wb_buffer_1}, {wb_buffer_0}}; // @[Edges.scala:441:15]
assign probeResponse_data = _GEN[_probeResponse_T]; // @[Edges.scala:433:17, :441:15]
wire [32:0] _voluntaryRelease_legal_T_2 = {1'h0, _voluntaryRelease_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _voluntaryRelease_legal_T_3 = _voluntaryRelease_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _voluntaryRelease_legal_T_4 = _voluntaryRelease_legal_T_3; // @[Parameters.scala:137:46]
wire _voluntaryRelease_legal_T_5 = _voluntaryRelease_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _voluntaryRelease_legal_T_6 = {r_address[31:17], r_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] _voluntaryRelease_legal_T_7 = {1'h0, _voluntaryRelease_legal_T_6}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _voluntaryRelease_legal_T_8 = _voluntaryRelease_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _voluntaryRelease_legal_T_9 = _voluntaryRelease_legal_T_8; // @[Parameters.scala:137:46]
wire _voluntaryRelease_legal_T_10 = _voluntaryRelease_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _voluntaryRelease_legal_T_11 = {r_address[31:28], r_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] _voluntaryRelease_legal_T_12 = {1'h0, _voluntaryRelease_legal_T_11}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _voluntaryRelease_legal_T_13 = _voluntaryRelease_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _voluntaryRelease_legal_T_14 = _voluntaryRelease_legal_T_13; // @[Parameters.scala:137:46]
wire _voluntaryRelease_legal_T_15 = _voluntaryRelease_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _voluntaryRelease_legal_T_16 = _voluntaryRelease_legal_T_5 | _voluntaryRelease_legal_T_10; // @[Parameters.scala:685:42]
wire _voluntaryRelease_legal_T_17 = _voluntaryRelease_legal_T_16 | _voluntaryRelease_legal_T_15; // @[Parameters.scala:685:42]
wire [31:0] _voluntaryRelease_legal_T_21 = {r_address[31:28], r_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] _voluntaryRelease_legal_T_22 = {1'h0, _voluntaryRelease_legal_T_21}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _voluntaryRelease_legal_T_23 = _voluntaryRelease_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _voluntaryRelease_legal_T_24 = _voluntaryRelease_legal_T_23; // @[Parameters.scala:137:46]
wire _voluntaryRelease_legal_T_25 = _voluntaryRelease_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _voluntaryRelease_legal_T_26 = r_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] _voluntaryRelease_legal_T_27 = {1'h0, _voluntaryRelease_legal_T_26}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _voluntaryRelease_legal_T_28 = _voluntaryRelease_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _voluntaryRelease_legal_T_29 = _voluntaryRelease_legal_T_28; // @[Parameters.scala:137:46]
wire _voluntaryRelease_legal_T_30 = _voluntaryRelease_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _voluntaryRelease_legal_T_31 = _voluntaryRelease_legal_T_25 | _voluntaryRelease_legal_T_30; // @[Parameters.scala:685:42]
wire _voluntaryRelease_legal_T_32 = _voluntaryRelease_legal_T_31; // @[Parameters.scala:684:54, :685:42]
wire voluntaryRelease_legal = _voluntaryRelease_legal_T_32; // @[Parameters.scala:684:54, :686:26]
wire [127:0] voluntaryRelease_data; // @[Edges.scala:396:17]
assign voluntaryRelease_data = _GEN[_voluntaryRelease_T]; // @[Edges.scala:396:17, :404:15, :441:15]
wire _T_3 = state == 3'h1; // @[dcache.scala:39:22, :88:22]
wire _io_meta_read_valid_T = ~(data_req_cnt[2]); // @[dcache.scala:44:29, :89:40]
assign io_meta_read_valid_0 = (|state) & _T_3 & _io_meta_read_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :54:22, :80:30, :88:{22,41}, :89:{24,40}]
wire _io_data_req_valid_T = ~(data_req_cnt[2]); // @[dcache.scala:44:29, :89:40, :93:39]
assign io_data_req_valid_0 = (|state) & _T_3 & _io_data_req_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :56:22, :80:30, :88:{22,41}, :93:{23,39}]
wire [7:0] _io_data_req_bits_addr_T_1 = {req_idx, _io_data_req_bits_addr_T}; // @[dcache.scala:37:16, :96:{34,56}]
assign _io_data_req_bits_addr_T_2 = {_io_data_req_bits_addr_T_1, 4'h0}; // @[dcache.scala:96:34, :97:43]
assign io_data_req_bits_addr_0 = _io_data_req_bits_addr_T_2; // @[dcache.scala:24:7, :97:43]
wire [3:0] _GEN_0 = {1'h0, data_req_cnt} + 4'h1; // @[dcache.scala:44:29, :106:36]
wire [3:0] _data_req_cnt_T; // @[dcache.scala:106:36]
assign _data_req_cnt_T = _GEN_0; // @[dcache.scala:106:36]
wire [3:0] _data_req_cnt_T_2; // @[dcache.scala:130:36]
assign _data_req_cnt_T_2 = _GEN_0; // @[dcache.scala:106:36, :130:36]
wire [2:0] _data_req_cnt_T_1 = _data_req_cnt_T[2:0]; // @[dcache.scala:106:36]
wire _T_8 = r2_data_req_cnt == 3'h3; // @[dcache.scala:43:28, :110:29]
assign io_resp_0 = (|state) & _T_3 & r2_data_req_fired & _T_8; // @[dcache.scala:24:7, :39:22, :41:34, :49:31, :58:22, :80:30, :88:{22,41}, :108:30, :110:{29,53}]
wire _T_9 = state == 3'h2; // @[dcache.scala:39:22, :116:22]
assign io_lsu_release_valid_0 = ~(~(|state) | _T_3) & _T_9; // @[dcache.scala:24:7, :39:22, :49:31, :59:24, :80:{15,30}, :88:{22,41}, :116:{22,41}]
wire _T_11 = state == 3'h3; // @[dcache.scala:39:22, :110:29, :122:22]
wire _io_release_valid_T = ~(data_req_cnt[2]); // @[dcache.scala:44:29, :89:40, :123:38]
wire _GEN_1 = _T_3 | _T_9; // @[dcache.scala:51:22, :88:{22,41}, :116:{22,41}, :122:36]
assign io_release_valid_0 = ~(~(|state) | _GEN_1) & _T_11 & _io_release_valid_T; // @[dcache.scala:24:7, :39:22, :49:31, :51:22, :80:{15,30}, :88:41, :116:41, :122:{22,36}, :123:{22,38}]
assign _io_release_bits_T_opcode = {1'h1, req_voluntary, 1'h1}; // @[dcache.scala:37:16, :124:27]
assign _io_release_bits_T_param = req_voluntary ? voluntaryRelease_param : probeResponse_param; // @[Edges.scala:396:17, :433:17]
assign _io_release_bits_T_source = req_voluntary ? 3'h4 : probeResponse_source; // @[Edges.scala:433:17]
assign _io_release_bits_T_address = req_voluntary ? voluntaryRelease_address : probeResponse_address; // @[Edges.scala:396:17, :433:17]
assign _io_release_bits_T_data = req_voluntary ? voluntaryRelease_data : probeResponse_data; // @[Edges.scala:396:17, :433:17]
assign io_release_bits_opcode_0 = _io_release_bits_T_opcode; // @[dcache.scala:24:7, :124:27]
assign io_release_bits_param_0 = _io_release_bits_T_param; // @[dcache.scala:24:7, :124:27]
assign io_release_bits_source_0 = _io_release_bits_T_source; // @[dcache.scala:24:7, :124:27]
assign io_release_bits_address_0 = _io_release_bits_T_address; // @[dcache.scala:24:7, :124:27]
assign io_release_bits_data_0 = _io_release_bits_T_data; // @[dcache.scala:24:7, :124:27]
wire [2:0] _data_req_cnt_T_3 = _data_req_cnt_T_2[2:0]; // @[dcache.scala:130:36]
wire [2:0] _state_T = {req_voluntary, 2'h0}; // @[dcache.scala:37:16, :133:19]
wire _T_16 = state == 3'h4; // @[dcache.scala:39:22, :135:22]
wire _T_2 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_2 = (|state) & _T_3; // @[dcache.scala:39:22, :41:34, :49:31, :80:30, :88:{22,41}]
wire _T_6 = io_data_req_ready_0 & io_data_req_valid_0 & io_meta_read_ready_0 & io_meta_read_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[dcache.scala:24:7]
if (~(|state) & _T_2) begin // @[Decoupled.scala:51:35]
req_tag <= io_req_bits_tag_0; // @[dcache.scala:24:7, :37:16]
req_idx <= io_req_bits_idx_0; // @[dcache.scala:24:7, :37:16]
req_source <= io_req_bits_source_0; // @[dcache.scala:24:7, :37:16]
req_param <= io_req_bits_param_0; // @[dcache.scala:24:7, :37:16]
req_way_en <= io_req_bits_way_en_0; // @[dcache.scala:24:7, :37:16]
req_voluntary <= io_req_bits_voluntary_0; // @[dcache.scala:24:7, :37:16]
end
if (_GEN_2) begin // @[dcache.scala:41:34, :43:28, :80:30, :88:41]
r1_data_req_cnt <= _T_6 ? data_req_cnt : 3'h0; // @[Decoupled.scala:51:35]
r2_data_req_cnt <= r1_data_req_cnt; // @[dcache.scala:42:28, :43:28]
end
if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[1:0] == 2'h0) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34]
wb_buffer_0 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22]
if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[1:0] == 2'h1) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34]
wb_buffer_1 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22]
if ((|state) & _T_3 & r2_data_req_fired & r2_data_req_cnt[1:0] == 2'h2) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34]
wb_buffer_2 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22]
if ((|state) & _T_3 & r2_data_req_fired & (&(r2_data_req_cnt[1:0]))) // @[dcache.scala:39:22, :41:34, :43:28, :46:22, :49:31, :80:30, :88:{22,41}, :108:30, :109:34]
wb_buffer_3 <= io_data_resp_0; // @[dcache.scala:24:7, :46:22]
if (reset) begin // @[dcache.scala:24:7]
state <= 3'h0; // @[dcache.scala:39:22]
r1_data_req_fired <= 1'h0; // @[dcache.scala:40:34]
r2_data_req_fired <= 1'h0; // @[dcache.scala:41:34]
data_req_cnt <= 3'h0; // @[dcache.scala:44:29]
r_counter <= 8'h0; // @[Edges.scala:229:27]
acked <= 1'h0; // @[dcache.scala:47:22]
end
else begin // @[dcache.scala:24:7]
if (|state) begin // @[dcache.scala:39:22, :49:31]
if (_T_3) begin // @[dcache.scala:88:22]
if (r2_data_req_fired & _T_8) begin // @[dcache.scala:39:22, :41:34, :108:30, :110:{29,53}, :112:15]
state <= 3'h2; // @[dcache.scala:39:22]
data_req_cnt <= 3'h0; // @[dcache.scala:44:29]
end
else if (_T_6) // @[Decoupled.scala:51:35]
data_req_cnt <= _data_req_cnt_T_1; // @[dcache.scala:44:29, :106:36]
end
else begin // @[dcache.scala:88:22]
if (_T_9) begin // @[dcache.scala:116:22]
if (io_lsu_release_ready_0 & io_lsu_release_valid_0) // @[Decoupled.scala:51:35]
state <= 3'h3; // @[dcache.scala:39:22, :110:29]
end
else if (_T_11) begin // @[dcache.scala:122:22]
if (data_req_cnt == 3'h3 & _T_14) // @[Decoupled.scala:51:35]
state <= _state_T; // @[dcache.scala:39:22, :133:19]
end
else if (_T_16 & acked) // @[dcache.scala:39:22, :47:22, :135:{22,35}, :139:18, :140:13]
state <= 3'h0; // @[dcache.scala:39:22]
if (_T_9 | ~(_T_11 & _T_14)) begin // @[Decoupled.scala:51:35]
end
else // @[dcache.scala:44:29, :116:41, :122:36]
data_req_cnt <= _data_req_cnt_T_3; // @[dcache.scala:44:29, :130:36]
end
if (~_GEN_1) // @[dcache.scala:51:22, :88:41, :116:41, :122:36]
acked <= _T_11 ? io_mem_grant_0 | acked : _T_16 & io_mem_grant_0 | acked; // @[dcache.scala:24:7, :47:22, :122:{22,36}, :126:25, :127:13, :135:{22,35}, :136:25, :137:13]
end
else begin // @[dcache.scala:49:31]
if (_T_2) begin // @[Decoupled.scala:51:35]
state <= 3'h1; // @[dcache.scala:39:22]
data_req_cnt <= 3'h0; // @[dcache.scala:44:29]
end
acked <= ~_T_2 & acked; // @[Decoupled.scala:51:35]
end
if (_GEN_2) begin // @[dcache.scala:41:34, :80:30, :88:41]
r1_data_req_fired <= _T_6; // @[Decoupled.scala:51:35]
r2_data_req_fired <= r1_data_req_fired; // @[dcache.scala:40:34, :41:34]
end
if (_T_14) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
end
always @(posedge)
assign io_req_ready = io_req_ready_0; // @[dcache.scala:24:7]
assign io_meta_read_valid = io_meta_read_valid_0; // @[dcache.scala:24:7]
assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[dcache.scala:24:7]
assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[dcache.scala:24:7]
assign io_resp = io_resp_0; // @[dcache.scala:24:7]
assign io_idx_valid = io_idx_valid_0; // @[dcache.scala:24:7]
assign io_idx_bits = io_idx_bits_0; // @[dcache.scala:24:7]
assign io_data_req_valid = io_data_req_valid_0; // @[dcache.scala:24:7]
assign io_data_req_bits_way_en = io_data_req_bits_way_en_0; // @[dcache.scala:24:7]
assign io_data_req_bits_addr = io_data_req_bits_addr_0; // @[dcache.scala:24:7]
assign io_release_valid = io_release_valid_0; // @[dcache.scala:24:7]
assign io_release_bits_opcode = io_release_bits_opcode_0; // @[dcache.scala:24:7]
assign io_release_bits_param = io_release_bits_param_0; // @[dcache.scala:24:7]
assign io_release_bits_source = io_release_bits_source_0; // @[dcache.scala:24:7]
assign io_release_bits_address = io_release_bits_address_0; // @[dcache.scala:24:7]
assign io_release_bits_data = io_release_bits_data_0; // @[dcache.scala:24:7]
assign io_lsu_release_valid = io_lsu_release_valid_0; // @[dcache.scala:24:7]
assign io_lsu_release_bits_param = io_lsu_release_bits_param_0; // @[dcache.scala:24:7]
assign io_lsu_release_bits_source = io_lsu_release_bits_source_0; // @[dcache.scala:24:7]
assign io_lsu_release_bits_address = io_lsu_release_bits_address_0; // @[dcache.scala:24:7]
assign io_lsu_release_bits_data = io_lsu_release_bits_data_0; // @[dcache.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AccPipe_9 :
input clock : Clock
input reset : Reset
output io : { flip op1 : SInt<32>, flip op2 : SInt<32>, sum : SInt<32>}
node _io_sum_T = add(io.op1, io.op2)
node _io_sum_T_1 = tail(_io_sum_T, 1)
node _io_sum_T_2 = asSInt(_io_sum_T_1)
reg io_sum_r : SInt<32>, clock
when UInt<1>(0h1) :
connect io_sum_r, _io_sum_T_2
connect io.sum, io_sum_r | module AccPipe_9( // @[AccumulatorMem.scala:63:7]
input clock, // @[AccumulatorMem.scala:63:7]
input reset, // @[AccumulatorMem.scala:63:7]
input [31:0] io_op1, // @[AccumulatorMem.scala:64:14]
input [31:0] io_op2, // @[AccumulatorMem.scala:64:14]
output [31:0] io_sum // @[AccumulatorMem.scala:64:14]
);
wire [31:0] io_op1_0 = io_op1; // @[AccumulatorMem.scala:63:7]
wire [31:0] io_op2_0 = io_op2; // @[AccumulatorMem.scala:63:7]
wire [31:0] io_sum_0; // @[AccumulatorMem.scala:63:7]
wire [32:0] _io_sum_T = {io_op1_0[31], io_op1_0} + {io_op2_0[31], io_op2_0}; // @[Arithmetic.scala:94:38]
wire [31:0] _io_sum_T_1 = _io_sum_T[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _io_sum_T_2 = _io_sum_T_1; // @[Arithmetic.scala:94:38]
reg [31:0] io_sum_r; // @[AccumulatorMem.scala:70:26]
assign io_sum_0 = io_sum_r; // @[AccumulatorMem.scala:63:7, :70:26]
always @(posedge clock) // @[AccumulatorMem.scala:63:7]
io_sum_r <= _io_sum_T_2; // @[Arithmetic.scala:94:38]
assign io_sum = io_sum_0; // @[AccumulatorMem.scala:63:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_331 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_75
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_331( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_75 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_43 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_95
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate destNodesIn_1.vc_free
invalidate destNodesIn_1.credit_return
invalidate destNodesIn_1.flit[0].bits.virt_channel_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node
invalidate destNodesIn_1.flit[0].bits.flow.vnet_id
invalidate destNodesIn_1.flit[0].bits.payload
invalidate destNodesIn_1.flit[0].bits.tail
invalidate destNodesIn_1.flit[0].bits.head
invalidate destNodesIn_1.flit[0].valid
inst monitor_1 of NoCMonitor_96
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free
connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return
connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node
connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id
connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node
connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id
connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload
connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail
connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head
connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid
wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate destNodesIn_2.vc_free
invalidate destNodesIn_2.credit_return
invalidate destNodesIn_2.flit[0].bits.virt_channel_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node
invalidate destNodesIn_2.flit[0].bits.flow.vnet_id
invalidate destNodesIn_2.flit[0].bits.payload
invalidate destNodesIn_2.flit[0].bits.tail
invalidate destNodesIn_2.flit[0].bits.head
invalidate destNodesIn_2.flit[0].valid
inst monitor_2 of NoCMonitor_97
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free
connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return
connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node
connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id
connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node
connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id
connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload
connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail
connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head
connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate sourceNodesOut_1.vc_free
invalidate sourceNodesOut_1.credit_return
invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_1.flit[0].bits.payload
invalidate sourceNodesOut_1.flit[0].bits.tail
invalidate sourceNodesOut_1.flit[0].bits.head
invalidate sourceNodesOut_1.flit[0].valid
wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate sourceNodesOut_2.vc_free
invalidate sourceNodesOut_2.credit_return
invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_2.flit[0].bits.payload
invalidate sourceNodesOut_2.flit[0].bits.tail
invalidate sourceNodesOut_2.flit[0].bits.head
invalidate sourceNodesOut_2.flit[0].valid
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in_0
connect destNodesIn_1, auto.dest_nodes_in_1
connect destNodesIn_2, auto.dest_nodes_in_2
connect auto.source_nodes_out_0, sourceNodesOut
connect auto.source_nodes_out_1, sourceNodesOut_1
connect auto.source_nodes_out_2, sourceNodesOut_2
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_5 of InputUnit_95
connect input_unit_0_from_5.clock, clock
connect input_unit_0_from_5.reset, reset
inst input_unit_1_from_13 of InputUnit_96
connect input_unit_1_from_13.clock, clock
connect input_unit_1_from_13.reset, reset
inst input_unit_2_from_15 of InputUnit_97
connect input_unit_2_from_15.clock, clock
connect input_unit_2_from_15.reset, reset
inst output_unit_0_to_5 of OutputUnit_95
connect output_unit_0_to_5.clock, clock
connect output_unit_0_to_5.reset, reset
inst output_unit_1_to_13 of OutputUnit_96
connect output_unit_1_to_13.clock, clock
connect output_unit_1_to_13.reset, reset
inst output_unit_2_to_15 of OutputUnit_97
connect output_unit_2_to_15.clock, clock
connect output_unit_2_to_15.reset, reset
inst switch of Switch_43
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_43
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_43
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_43
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_5.io.in, destNodesIn
connect input_unit_1_from_13.io.in, destNodesIn_1
connect input_unit_2_from_15.io.in, destNodesIn_2
connect output_unit_0_to_5.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_5.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_5.io.out.flit
connect output_unit_1_to_13.io.out.vc_free, sourceNodesOut_1.vc_free
connect output_unit_1_to_13.io.out.credit_return, sourceNodesOut_1.credit_return
connect sourceNodesOut_1.flit, output_unit_1_to_13.io.out.flit
connect output_unit_2_to_15.io.out.vc_free, sourceNodesOut_2.vc_free
connect output_unit_2_to_15.io.out.credit_return, sourceNodesOut_2.credit_return
connect sourceNodesOut_2.flit, output_unit_2_to_15.io.out.flit
connect route_computer.io.req.`0`, input_unit_0_from_5.io.router_req
connect route_computer.io.req.`1`, input_unit_1_from_13.io.router_req
connect route_computer.io.req.`2`, input_unit_2_from_15.io.router_req
connect input_unit_0_from_5.io.router_resp, route_computer.io.resp.`0`
connect input_unit_1_from_13.io.router_resp, route_computer.io.resp.`1`
connect input_unit_2_from_15.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_5.io.vcalloc_req
connect vc_allocator.io.req.`1`, input_unit_1_from_13.io.vcalloc_req
connect vc_allocator.io.req.`2`, input_unit_2_from_15.io.vcalloc_req
connect input_unit_0_from_5.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect input_unit_1_from_13.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect input_unit_2_from_15.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_5.io.allocs, vc_allocator.io.out_allocs.`0`
connect output_unit_1_to_13.io.allocs, vc_allocator.io.out_allocs.`1`
connect output_unit_2_to_15.io.allocs, vc_allocator.io.out_allocs.`2`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_5.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_5.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_5.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_5.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_5.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_5.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_5.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_5.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_5.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_5.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_5.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_5.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_5.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_5.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_5.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_5.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_5.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_5.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_5.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_5.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_5.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_5.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_5.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_5.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_5.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_13.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_13.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_13.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_13.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_13.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_13.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_13.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_13.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_13.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_13.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_13.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_13.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_13.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_13.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_13.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_13.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_13.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_13.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_13.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_13.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_13.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_13.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_13.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_13.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_13.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_13.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_15.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_15.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_15.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_15.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_15.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_15.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_15.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_15.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_15.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_15.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_15.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_15.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_15.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_15.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_15.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_15.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_15.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_15.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_15.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_15.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_15.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_15.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_15.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_15.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_15.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_15.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_15.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_15.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_15.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_15.io.channel_status[4].occupied
connect input_unit_0_from_5.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0]
connect input_unit_0_from_5.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1]
connect input_unit_0_from_5.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2]
connect input_unit_0_from_5.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3]
connect input_unit_0_from_5.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4]
connect input_unit_0_from_5.io.out_credit_available.`1`[0], output_unit_1_to_13.io.credit_available[0]
connect input_unit_0_from_5.io.out_credit_available.`1`[1], output_unit_1_to_13.io.credit_available[1]
connect input_unit_0_from_5.io.out_credit_available.`1`[2], output_unit_1_to_13.io.credit_available[2]
connect input_unit_0_from_5.io.out_credit_available.`1`[3], output_unit_1_to_13.io.credit_available[3]
connect input_unit_0_from_5.io.out_credit_available.`1`[4], output_unit_1_to_13.io.credit_available[4]
connect input_unit_0_from_5.io.out_credit_available.`2`[0], output_unit_2_to_15.io.credit_available[0]
connect input_unit_0_from_5.io.out_credit_available.`2`[1], output_unit_2_to_15.io.credit_available[1]
connect input_unit_0_from_5.io.out_credit_available.`2`[2], output_unit_2_to_15.io.credit_available[2]
connect input_unit_0_from_5.io.out_credit_available.`2`[3], output_unit_2_to_15.io.credit_available[3]
connect input_unit_0_from_5.io.out_credit_available.`2`[4], output_unit_2_to_15.io.credit_available[4]
connect input_unit_1_from_13.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0]
connect input_unit_1_from_13.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1]
connect input_unit_1_from_13.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2]
connect input_unit_1_from_13.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3]
connect input_unit_1_from_13.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4]
connect input_unit_1_from_13.io.out_credit_available.`1`[0], output_unit_1_to_13.io.credit_available[0]
connect input_unit_1_from_13.io.out_credit_available.`1`[1], output_unit_1_to_13.io.credit_available[1]
connect input_unit_1_from_13.io.out_credit_available.`1`[2], output_unit_1_to_13.io.credit_available[2]
connect input_unit_1_from_13.io.out_credit_available.`1`[3], output_unit_1_to_13.io.credit_available[3]
connect input_unit_1_from_13.io.out_credit_available.`1`[4], output_unit_1_to_13.io.credit_available[4]
connect input_unit_1_from_13.io.out_credit_available.`2`[0], output_unit_2_to_15.io.credit_available[0]
connect input_unit_1_from_13.io.out_credit_available.`2`[1], output_unit_2_to_15.io.credit_available[1]
connect input_unit_1_from_13.io.out_credit_available.`2`[2], output_unit_2_to_15.io.credit_available[2]
connect input_unit_1_from_13.io.out_credit_available.`2`[3], output_unit_2_to_15.io.credit_available[3]
connect input_unit_1_from_13.io.out_credit_available.`2`[4], output_unit_2_to_15.io.credit_available[4]
connect input_unit_2_from_15.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0]
connect input_unit_2_from_15.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1]
connect input_unit_2_from_15.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2]
connect input_unit_2_from_15.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3]
connect input_unit_2_from_15.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4]
connect input_unit_2_from_15.io.out_credit_available.`1`[0], output_unit_1_to_13.io.credit_available[0]
connect input_unit_2_from_15.io.out_credit_available.`1`[1], output_unit_1_to_13.io.credit_available[1]
connect input_unit_2_from_15.io.out_credit_available.`1`[2], output_unit_1_to_13.io.credit_available[2]
connect input_unit_2_from_15.io.out_credit_available.`1`[3], output_unit_1_to_13.io.credit_available[3]
connect input_unit_2_from_15.io.out_credit_available.`1`[4], output_unit_1_to_13.io.credit_available[4]
connect input_unit_2_from_15.io.out_credit_available.`2`[0], output_unit_2_to_15.io.credit_available[0]
connect input_unit_2_from_15.io.out_credit_available.`2`[1], output_unit_2_to_15.io.credit_available[1]
connect input_unit_2_from_15.io.out_credit_available.`2`[2], output_unit_2_to_15.io.credit_available[2]
connect input_unit_2_from_15.io.out_credit_available.`2`[3], output_unit_2_to_15.io.credit_available[3]
connect input_unit_2_from_15.io.out_credit_available.`2`[4], output_unit_2_to_15.io.credit_available[4]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_5.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], input_unit_1_from_13.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], input_unit_2_from_15.io.salloc_req[0]
connect output_unit_0_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_5.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_5.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_5.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_5.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_5.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_5.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_5.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_5.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_1_to_13.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect output_unit_1_to_13.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect output_unit_1_to_13.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail
connect output_unit_1_to_13.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc
connect output_unit_1_to_13.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail
connect output_unit_1_to_13.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc
connect output_unit_1_to_13.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail
connect output_unit_1_to_13.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc
connect output_unit_1_to_13.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail
connect output_unit_1_to_13.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc
connect output_unit_2_to_15.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect output_unit_2_to_15.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect output_unit_2_to_15.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail
connect output_unit_2_to_15.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc
connect output_unit_2_to_15.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail
connect output_unit_2_to_15.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc
connect output_unit_2_to_15.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail
connect output_unit_2_to_15.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc
connect output_unit_2_to_15.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail
connect output_unit_2_to_15.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc
connect switch.io.in.`0`[0], input_unit_0_from_5.io.out[0]
connect switch.io.in.`1`[0], input_unit_1_from_13.io.out[0]
connect switch.io.in.`2`[0], input_unit_2_from_15.io.out[0]
connect output_unit_0_to_5.io.in, switch.io.out.`0`
connect output_unit_1_to_13.io.in, switch.io.out.`1`
connect output_unit_2_to_15.io.in, switch.io.out.`2`
reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect input_unit_0_from_5.io.block, UInt<1>(0h0)
connect input_unit_1_from_13.io.block, UInt<1>(0h0)
connect input_unit_2_from_15.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_5.io.debug.va_stall
connect debugNodeOut.va_stall[1], input_unit_1_from_13.io.debug.va_stall
connect debugNodeOut.va_stall[2], input_unit_2_from_15.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_5.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], input_unit_1_from_13.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], input_unit_2_from_15.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_91
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 5 14 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid)
connect fired_1, _fired_T_1
node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_13 = tail(_T_12, 1)
node _T_14 = eq(debug_sample, _T_13)
node _T_15 = and(_T_11, _T_14)
node _T_16 = and(_T_15, fired_1)
when _T_16 :
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "nocsample %d 13 14 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, destNodesIn_1.flit[0].valid
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid)
connect fired_2, _fired_T_2
node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = eq(debug_sample, _T_21)
node _T_23 = and(_T_19, _T_22)
node _T_24 = and(_T_23, fired_2)
when _T_24 :
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "nocsample %d 15 14 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, destNodesIn_2.flit[0].valid | module Router_43( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _output_unit_2_to_15_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_2_to_15_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_13_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_1_to_13_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_5_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_5_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire [2:0] _input_unit_2_from_15_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_15_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_15_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_15_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_15_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_15_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_2_from_15_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_2_from_15_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_15_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_15_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_15_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_15_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_15_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_15_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_13_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_13_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_13_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_13_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_13_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_13_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_13_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_1_from_13_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_13_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_13_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_13_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_15_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[18]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
node _source_ok_T_38 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[2])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[3])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[4])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[5])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[6])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[7])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[8])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[9])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[10])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[11])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[12])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[13])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[14])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[15])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[16])
node source_ok = or(_source_ok_T_53, _source_ok_WIRE[17])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = and(_T_11, _T_24)
node _T_169 = and(_T_168, _T_37)
node _T_170 = and(_T_169, _T_50)
node _T_171 = and(_T_170, _T_63)
node _T_172 = and(_T_171, _T_71)
node _T_173 = and(_T_172, _T_79)
node _T_174 = and(_T_173, _T_87)
node _T_175 = and(_T_174, _T_95)
node _T_176 = and(_T_175, _T_103)
node _T_177 = and(_T_176, _T_111)
node _T_178 = and(_T_177, _T_119)
node _T_179 = and(_T_178, _T_127)
node _T_180 = and(_T_179, _T_135)
node _T_181 = and(_T_180, _T_143)
node _T_182 = and(_T_181, _T_151)
node _T_183 = and(_T_182, _T_159)
node _T_184 = and(_T_183, _T_167)
node _T_185 = asUInt(reset)
node _T_186 = eq(_T_185, UInt<1>(0h0))
when _T_186 :
node _T_187 = eq(_T_184, UInt<1>(0h0))
when _T_187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_184, UInt<1>(0h1), "") : assert_1
node _T_188 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_188 :
node _T_189 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_190 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_193 = shr(io.in.a.bits.source, 2)
node _T_194 = eq(_T_193, UInt<1>(0h0))
node _T_195 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_196 = and(_T_194, _T_195)
node _T_197 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_199 = shr(io.in.a.bits.source, 2)
node _T_200 = eq(_T_199, UInt<1>(0h1))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_204 = and(_T_202, _T_203)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<2>(0h2))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<2>(0h3))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_226 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_227 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_228 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_230 = or(_T_192, _T_198)
node _T_231 = or(_T_230, _T_204)
node _T_232 = or(_T_231, _T_210)
node _T_233 = or(_T_232, _T_216)
node _T_234 = or(_T_233, _T_217)
node _T_235 = or(_T_234, _T_218)
node _T_236 = or(_T_235, _T_219)
node _T_237 = or(_T_236, _T_220)
node _T_238 = or(_T_237, _T_221)
node _T_239 = or(_T_238, _T_222)
node _T_240 = or(_T_239, _T_223)
node _T_241 = or(_T_240, _T_224)
node _T_242 = or(_T_241, _T_225)
node _T_243 = or(_T_242, _T_226)
node _T_244 = or(_T_243, _T_227)
node _T_245 = or(_T_244, _T_228)
node _T_246 = or(_T_245, _T_229)
node _T_247 = and(_T_191, _T_246)
node _T_248 = or(UInt<1>(0h0), _T_247)
node _T_249 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<27>(0h4000000)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = and(_T_249, _T_254)
node _T_256 = or(UInt<1>(0h0), _T_255)
node _T_257 = and(_T_248, _T_256)
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_T_257, UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_257, UInt<1>(0h1), "") : assert_2
node _T_261 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_262 = shr(io.in.a.bits.source, 2)
node _T_263 = eq(_T_262, UInt<1>(0h0))
node _T_264 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_265 = and(_T_263, _T_264)
node _T_266 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_267 = and(_T_265, _T_266)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_268 = shr(io.in.a.bits.source, 2)
node _T_269 = eq(_T_268, UInt<1>(0h1))
node _T_270 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_271 = and(_T_269, _T_270)
node _T_272 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_273 = and(_T_271, _T_272)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_274 = shr(io.in.a.bits.source, 2)
node _T_275 = eq(_T_274, UInt<2>(0h2))
node _T_276 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_277 = and(_T_275, _T_276)
node _T_278 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_279 = and(_T_277, _T_278)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_280 = shr(io.in.a.bits.source, 2)
node _T_281 = eq(_T_280, UInt<2>(0h3))
node _T_282 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_283 = and(_T_281, _T_282)
node _T_284 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_287 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_289 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_290 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_294 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_295 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_298 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[18]
connect _WIRE[0], _T_261
connect _WIRE[1], _T_267
connect _WIRE[2], _T_273
connect _WIRE[3], _T_279
connect _WIRE[4], _T_285
connect _WIRE[5], _T_286
connect _WIRE[6], _T_287
connect _WIRE[7], _T_288
connect _WIRE[8], _T_289
connect _WIRE[9], _T_290
connect _WIRE[10], _T_291
connect _WIRE[11], _T_292
connect _WIRE[12], _T_293
connect _WIRE[13], _T_294
connect _WIRE[14], _T_295
connect _WIRE[15], _T_296
connect _WIRE[16], _T_297
connect _WIRE[17], _T_298
node _T_299 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_300 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_301 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_302 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_303 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_304 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_305 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_306 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_307 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_308 = mux(_WIRE[5], _T_299, UInt<1>(0h0))
node _T_309 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_310 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_311 = mux(_WIRE[8], _T_300, UInt<1>(0h0))
node _T_312 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_313 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_314 = mux(_WIRE[11], _T_301, UInt<1>(0h0))
node _T_315 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_316 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_317 = mux(_WIRE[14], _T_302, UInt<1>(0h0))
node _T_318 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_320 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_321 = or(_T_303, _T_304)
node _T_322 = or(_T_321, _T_305)
node _T_323 = or(_T_322, _T_306)
node _T_324 = or(_T_323, _T_307)
node _T_325 = or(_T_324, _T_308)
node _T_326 = or(_T_325, _T_309)
node _T_327 = or(_T_326, _T_310)
node _T_328 = or(_T_327, _T_311)
node _T_329 = or(_T_328, _T_312)
node _T_330 = or(_T_329, _T_313)
node _T_331 = or(_T_330, _T_314)
node _T_332 = or(_T_331, _T_315)
node _T_333 = or(_T_332, _T_316)
node _T_334 = or(_T_333, _T_317)
node _T_335 = or(_T_334, _T_318)
node _T_336 = or(_T_335, _T_319)
node _T_337 = or(_T_336, _T_320)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_337
node _T_338 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_339 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_340 = and(_T_338, _T_339)
node _T_341 = or(UInt<1>(0h0), _T_340)
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = and(_T_341, _T_346)
node _T_348 = or(UInt<1>(0h0), _T_347)
node _T_349 = and(_WIRE_1, _T_348)
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(_T_349, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_349, UInt<1>(0h1), "") : assert_3
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(source_ok, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_356, UInt<1>(0h1), "") : assert_5
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(is_aligned, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_363, UInt<1>(0h1), "") : assert_7
node _T_367 = not(io.in.a.bits.mask)
node _T_368 = eq(_T_367, UInt<1>(0h0))
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_368, UInt<1>(0h1), "") : assert_8
node _T_372 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_T_372, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_372, UInt<1>(0h1), "") : assert_9
node _T_376 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_376 :
node _T_377 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_378 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<1>(0h0))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<1>(0h1))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<2>(0h2))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_399 = shr(io.in.a.bits.source, 2)
node _T_400 = eq(_T_399, UInt<2>(0h3))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_404 = and(_T_402, _T_403)
node _T_405 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_406 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_407 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_408 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_409 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_410 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_411 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_412 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_414 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_415 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_416 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_417 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_418 = or(_T_380, _T_386)
node _T_419 = or(_T_418, _T_392)
node _T_420 = or(_T_419, _T_398)
node _T_421 = or(_T_420, _T_404)
node _T_422 = or(_T_421, _T_405)
node _T_423 = or(_T_422, _T_406)
node _T_424 = or(_T_423, _T_407)
node _T_425 = or(_T_424, _T_408)
node _T_426 = or(_T_425, _T_409)
node _T_427 = or(_T_426, _T_410)
node _T_428 = or(_T_427, _T_411)
node _T_429 = or(_T_428, _T_412)
node _T_430 = or(_T_429, _T_413)
node _T_431 = or(_T_430, _T_414)
node _T_432 = or(_T_431, _T_415)
node _T_433 = or(_T_432, _T_416)
node _T_434 = or(_T_433, _T_417)
node _T_435 = and(_T_379, _T_434)
node _T_436 = or(UInt<1>(0h0), _T_435)
node _T_437 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_438 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<27>(0h4000000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = and(_T_437, _T_442)
node _T_444 = or(UInt<1>(0h0), _T_443)
node _T_445 = and(_T_436, _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_445, UInt<1>(0h1), "") : assert_10
node _T_449 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_450 = shr(io.in.a.bits.source, 2)
node _T_451 = eq(_T_450, UInt<1>(0h0))
node _T_452 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_453 = and(_T_451, _T_452)
node _T_454 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_455 = and(_T_453, _T_454)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_456 = shr(io.in.a.bits.source, 2)
node _T_457 = eq(_T_456, UInt<1>(0h1))
node _T_458 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_459 = and(_T_457, _T_458)
node _T_460 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_461 = and(_T_459, _T_460)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_462 = shr(io.in.a.bits.source, 2)
node _T_463 = eq(_T_462, UInt<2>(0h2))
node _T_464 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_465 = and(_T_463, _T_464)
node _T_466 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_467 = and(_T_465, _T_466)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_468 = shr(io.in.a.bits.source, 2)
node _T_469 = eq(_T_468, UInt<2>(0h3))
node _T_470 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_471 = and(_T_469, _T_470)
node _T_472 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_484 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_485 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_486 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[18]
connect _WIRE_2[0], _T_449
connect _WIRE_2[1], _T_455
connect _WIRE_2[2], _T_461
connect _WIRE_2[3], _T_467
connect _WIRE_2[4], _T_473
connect _WIRE_2[5], _T_474
connect _WIRE_2[6], _T_475
connect _WIRE_2[7], _T_476
connect _WIRE_2[8], _T_477
connect _WIRE_2[9], _T_478
connect _WIRE_2[10], _T_479
connect _WIRE_2[11], _T_480
connect _WIRE_2[12], _T_481
connect _WIRE_2[13], _T_482
connect _WIRE_2[14], _T_483
connect _WIRE_2[15], _T_484
connect _WIRE_2[16], _T_485
connect _WIRE_2[17], _T_486
node _T_487 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_488 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_489 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_490 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_491 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_492 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_493 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_494 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_495 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_496 = mux(_WIRE_2[5], _T_487, UInt<1>(0h0))
node _T_497 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_498 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_499 = mux(_WIRE_2[8], _T_488, UInt<1>(0h0))
node _T_500 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_501 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_502 = mux(_WIRE_2[11], _T_489, UInt<1>(0h0))
node _T_503 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_504 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_505 = mux(_WIRE_2[14], _T_490, UInt<1>(0h0))
node _T_506 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_507 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_508 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_509 = or(_T_491, _T_492)
node _T_510 = or(_T_509, _T_493)
node _T_511 = or(_T_510, _T_494)
node _T_512 = or(_T_511, _T_495)
node _T_513 = or(_T_512, _T_496)
node _T_514 = or(_T_513, _T_497)
node _T_515 = or(_T_514, _T_498)
node _T_516 = or(_T_515, _T_499)
node _T_517 = or(_T_516, _T_500)
node _T_518 = or(_T_517, _T_501)
node _T_519 = or(_T_518, _T_502)
node _T_520 = or(_T_519, _T_503)
node _T_521 = or(_T_520, _T_504)
node _T_522 = or(_T_521, _T_505)
node _T_523 = or(_T_522, _T_506)
node _T_524 = or(_T_523, _T_507)
node _T_525 = or(_T_524, _T_508)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_525
node _T_526 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_527 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_528 = and(_T_526, _T_527)
node _T_529 = or(UInt<1>(0h0), _T_528)
node _T_530 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_531 = cvt(_T_530)
node _T_532 = and(_T_531, asSInt(UInt<27>(0h4000000)))
node _T_533 = asSInt(_T_532)
node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0)))
node _T_535 = and(_T_529, _T_534)
node _T_536 = or(UInt<1>(0h0), _T_535)
node _T_537 = and(_WIRE_3, _T_536)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_537, UInt<1>(0h1), "") : assert_11
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(source_ok, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_544 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_544, UInt<1>(0h1), "") : assert_13
node _T_548 = asUInt(reset)
node _T_549 = eq(_T_548, UInt<1>(0h0))
when _T_549 :
node _T_550 = eq(is_aligned, UInt<1>(0h0))
when _T_550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_551 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_551, UInt<1>(0h1), "") : assert_15
node _T_555 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_T_555, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_555, UInt<1>(0h1), "") : assert_16
node _T_559 = not(io.in.a.bits.mask)
node _T_560 = eq(_T_559, UInt<1>(0h0))
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_560, UInt<1>(0h1), "") : assert_17
node _T_564 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_564, UInt<1>(0h1), "") : assert_18
node _T_568 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_568 :
node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_570 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_571 = and(_T_569, _T_570)
node _T_572 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_573 = shr(io.in.a.bits.source, 2)
node _T_574 = eq(_T_573, UInt<1>(0h0))
node _T_575 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_576 = and(_T_574, _T_575)
node _T_577 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_578 = and(_T_576, _T_577)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_579 = shr(io.in.a.bits.source, 2)
node _T_580 = eq(_T_579, UInt<1>(0h1))
node _T_581 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_582 = and(_T_580, _T_581)
node _T_583 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_584 = and(_T_582, _T_583)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_585 = shr(io.in.a.bits.source, 2)
node _T_586 = eq(_T_585, UInt<2>(0h2))
node _T_587 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_588 = and(_T_586, _T_587)
node _T_589 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_590 = and(_T_588, _T_589)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<2>(0h3))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_602 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_603 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_609 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_610 = or(_T_572, _T_578)
node _T_611 = or(_T_610, _T_584)
node _T_612 = or(_T_611, _T_590)
node _T_613 = or(_T_612, _T_596)
node _T_614 = or(_T_613, _T_597)
node _T_615 = or(_T_614, _T_598)
node _T_616 = or(_T_615, _T_599)
node _T_617 = or(_T_616, _T_600)
node _T_618 = or(_T_617, _T_601)
node _T_619 = or(_T_618, _T_602)
node _T_620 = or(_T_619, _T_603)
node _T_621 = or(_T_620, _T_604)
node _T_622 = or(_T_621, _T_605)
node _T_623 = or(_T_622, _T_606)
node _T_624 = or(_T_623, _T_607)
node _T_625 = or(_T_624, _T_608)
node _T_626 = or(_T_625, _T_609)
node _T_627 = and(_T_571, _T_626)
node _T_628 = or(UInt<1>(0h0), _T_627)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_628, UInt<1>(0h1), "") : assert_19
node _T_632 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_633 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_634 = and(_T_632, _T_633)
node _T_635 = or(UInt<1>(0h0), _T_634)
node _T_636 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_637 = cvt(_T_636)
node _T_638 = and(_T_637, asSInt(UInt<27>(0h4000000)))
node _T_639 = asSInt(_T_638)
node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0)))
node _T_641 = and(_T_635, _T_640)
node _T_642 = or(UInt<1>(0h0), _T_641)
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_642, UInt<1>(0h1), "") : assert_20
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(source_ok, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(is_aligned, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_652 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_652, UInt<1>(0h1), "") : assert_23
node _T_656 = eq(io.in.a.bits.mask, mask)
node _T_657 = asUInt(reset)
node _T_658 = eq(_T_657, UInt<1>(0h0))
when _T_658 :
node _T_659 = eq(_T_656, UInt<1>(0h0))
when _T_659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_656, UInt<1>(0h1), "") : assert_24
node _T_660 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_660, UInt<1>(0h1), "") : assert_25
node _T_664 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_664 :
node _T_665 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_666 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_667 = and(_T_665, _T_666)
node _T_668 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_669 = shr(io.in.a.bits.source, 2)
node _T_670 = eq(_T_669, UInt<1>(0h0))
node _T_671 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_672 = and(_T_670, _T_671)
node _T_673 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_674 = and(_T_672, _T_673)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_675 = shr(io.in.a.bits.source, 2)
node _T_676 = eq(_T_675, UInt<1>(0h1))
node _T_677 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_678 = and(_T_676, _T_677)
node _T_679 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_680 = and(_T_678, _T_679)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_681 = shr(io.in.a.bits.source, 2)
node _T_682 = eq(_T_681, UInt<2>(0h2))
node _T_683 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_684 = and(_T_682, _T_683)
node _T_685 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_686 = and(_T_684, _T_685)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_687 = shr(io.in.a.bits.source, 2)
node _T_688 = eq(_T_687, UInt<2>(0h3))
node _T_689 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_690 = and(_T_688, _T_689)
node _T_691 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_692 = and(_T_690, _T_691)
node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_702 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_703 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_704 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_705 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_706 = or(_T_668, _T_674)
node _T_707 = or(_T_706, _T_680)
node _T_708 = or(_T_707, _T_686)
node _T_709 = or(_T_708, _T_692)
node _T_710 = or(_T_709, _T_693)
node _T_711 = or(_T_710, _T_694)
node _T_712 = or(_T_711, _T_695)
node _T_713 = or(_T_712, _T_696)
node _T_714 = or(_T_713, _T_697)
node _T_715 = or(_T_714, _T_698)
node _T_716 = or(_T_715, _T_699)
node _T_717 = or(_T_716, _T_700)
node _T_718 = or(_T_717, _T_701)
node _T_719 = or(_T_718, _T_702)
node _T_720 = or(_T_719, _T_703)
node _T_721 = or(_T_720, _T_704)
node _T_722 = or(_T_721, _T_705)
node _T_723 = and(_T_667, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_726 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_727 = and(_T_725, _T_726)
node _T_728 = or(UInt<1>(0h0), _T_727)
node _T_729 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_730 = cvt(_T_729)
node _T_731 = and(_T_730, asSInt(UInt<27>(0h4000000)))
node _T_732 = asSInt(_T_731)
node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0)))
node _T_734 = and(_T_728, _T_733)
node _T_735 = or(UInt<1>(0h0), _T_734)
node _T_736 = and(_T_724, _T_735)
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_736, UInt<1>(0h1), "") : assert_26
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(source_ok, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(is_aligned, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_746 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_T_746, UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_746, UInt<1>(0h1), "") : assert_29
node _T_750 = eq(io.in.a.bits.mask, mask)
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_750, UInt<1>(0h1), "") : assert_30
node _T_754 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_754 :
node _T_755 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_756 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_757 = and(_T_755, _T_756)
node _T_758 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_759 = shr(io.in.a.bits.source, 2)
node _T_760 = eq(_T_759, UInt<1>(0h0))
node _T_761 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_762 = and(_T_760, _T_761)
node _T_763 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_764 = and(_T_762, _T_763)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_765 = shr(io.in.a.bits.source, 2)
node _T_766 = eq(_T_765, UInt<1>(0h1))
node _T_767 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_768 = and(_T_766, _T_767)
node _T_769 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_770 = and(_T_768, _T_769)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_771 = shr(io.in.a.bits.source, 2)
node _T_772 = eq(_T_771, UInt<2>(0h2))
node _T_773 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_774 = and(_T_772, _T_773)
node _T_775 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_776 = and(_T_774, _T_775)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_777 = shr(io.in.a.bits.source, 2)
node _T_778 = eq(_T_777, UInt<2>(0h3))
node _T_779 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_780 = and(_T_778, _T_779)
node _T_781 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_782 = and(_T_780, _T_781)
node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_785 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_786 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_787 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_792 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_793 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_794 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_795 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_796 = or(_T_758, _T_764)
node _T_797 = or(_T_796, _T_770)
node _T_798 = or(_T_797, _T_776)
node _T_799 = or(_T_798, _T_782)
node _T_800 = or(_T_799, _T_783)
node _T_801 = or(_T_800, _T_784)
node _T_802 = or(_T_801, _T_785)
node _T_803 = or(_T_802, _T_786)
node _T_804 = or(_T_803, _T_787)
node _T_805 = or(_T_804, _T_788)
node _T_806 = or(_T_805, _T_789)
node _T_807 = or(_T_806, _T_790)
node _T_808 = or(_T_807, _T_791)
node _T_809 = or(_T_808, _T_792)
node _T_810 = or(_T_809, _T_793)
node _T_811 = or(_T_810, _T_794)
node _T_812 = or(_T_811, _T_795)
node _T_813 = and(_T_757, _T_812)
node _T_814 = or(UInt<1>(0h0), _T_813)
node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_816 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_817 = and(_T_815, _T_816)
node _T_818 = or(UInt<1>(0h0), _T_817)
node _T_819 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<27>(0h4000000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = and(_T_818, _T_823)
node _T_825 = or(UInt<1>(0h0), _T_824)
node _T_826 = and(_T_814, _T_825)
node _T_827 = asUInt(reset)
node _T_828 = eq(_T_827, UInt<1>(0h0))
when _T_828 :
node _T_829 = eq(_T_826, UInt<1>(0h0))
when _T_829 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_826, UInt<1>(0h1), "") : assert_31
node _T_830 = asUInt(reset)
node _T_831 = eq(_T_830, UInt<1>(0h0))
when _T_831 :
node _T_832 = eq(source_ok, UInt<1>(0h0))
when _T_832 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(is_aligned, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_836 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_836, UInt<1>(0h1), "") : assert_34
node _T_840 = not(mask)
node _T_841 = and(io.in.a.bits.mask, _T_840)
node _T_842 = eq(_T_841, UInt<1>(0h0))
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_842, UInt<1>(0h1), "") : assert_35
node _T_846 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_846 :
node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<1>(0h0))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_857 = shr(io.in.a.bits.source, 2)
node _T_858 = eq(_T_857, UInt<1>(0h1))
node _T_859 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_860 = and(_T_858, _T_859)
node _T_861 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_862 = and(_T_860, _T_861)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_863 = shr(io.in.a.bits.source, 2)
node _T_864 = eq(_T_863, UInt<2>(0h2))
node _T_865 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_866 = and(_T_864, _T_865)
node _T_867 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_868 = and(_T_866, _T_867)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_869 = shr(io.in.a.bits.source, 2)
node _T_870 = eq(_T_869, UInt<2>(0h3))
node _T_871 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_872 = and(_T_870, _T_871)
node _T_873 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_877 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_887 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_888 = or(_T_850, _T_856)
node _T_889 = or(_T_888, _T_862)
node _T_890 = or(_T_889, _T_868)
node _T_891 = or(_T_890, _T_874)
node _T_892 = or(_T_891, _T_875)
node _T_893 = or(_T_892, _T_876)
node _T_894 = or(_T_893, _T_877)
node _T_895 = or(_T_894, _T_878)
node _T_896 = or(_T_895, _T_879)
node _T_897 = or(_T_896, _T_880)
node _T_898 = or(_T_897, _T_881)
node _T_899 = or(_T_898, _T_882)
node _T_900 = or(_T_899, _T_883)
node _T_901 = or(_T_900, _T_884)
node _T_902 = or(_T_901, _T_885)
node _T_903 = or(_T_902, _T_886)
node _T_904 = or(_T_903, _T_887)
node _T_905 = and(_T_849, _T_904)
node _T_906 = or(UInt<1>(0h0), _T_905)
node _T_907 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_908 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_909 = cvt(_T_908)
node _T_910 = and(_T_909, asSInt(UInt<27>(0h4000000)))
node _T_911 = asSInt(_T_910)
node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0)))
node _T_913 = and(_T_907, _T_912)
node _T_914 = or(UInt<1>(0h0), _T_913)
node _T_915 = and(_T_906, _T_914)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_915, UInt<1>(0h1), "") : assert_36
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(source_ok, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(is_aligned, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_925 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_925, UInt<1>(0h1), "") : assert_39
node _T_929 = eq(io.in.a.bits.mask, mask)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_929, UInt<1>(0h1), "") : assert_40
node _T_933 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_933 :
node _T_934 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_935 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_936 = and(_T_934, _T_935)
node _T_937 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_938 = shr(io.in.a.bits.source, 2)
node _T_939 = eq(_T_938, UInt<1>(0h0))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_943 = and(_T_941, _T_942)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_944 = shr(io.in.a.bits.source, 2)
node _T_945 = eq(_T_944, UInt<1>(0h1))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_950 = shr(io.in.a.bits.source, 2)
node _T_951 = eq(_T_950, UInt<2>(0h2))
node _T_952 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_953 = and(_T_951, _T_952)
node _T_954 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_955 = and(_T_953, _T_954)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_956 = shr(io.in.a.bits.source, 2)
node _T_957 = eq(_T_956, UInt<2>(0h3))
node _T_958 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_959 = and(_T_957, _T_958)
node _T_960 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_961 = and(_T_959, _T_960)
node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_974 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_975 = or(_T_937, _T_943)
node _T_976 = or(_T_975, _T_949)
node _T_977 = or(_T_976, _T_955)
node _T_978 = or(_T_977, _T_961)
node _T_979 = or(_T_978, _T_962)
node _T_980 = or(_T_979, _T_963)
node _T_981 = or(_T_980, _T_964)
node _T_982 = or(_T_981, _T_965)
node _T_983 = or(_T_982, _T_966)
node _T_984 = or(_T_983, _T_967)
node _T_985 = or(_T_984, _T_968)
node _T_986 = or(_T_985, _T_969)
node _T_987 = or(_T_986, _T_970)
node _T_988 = or(_T_987, _T_971)
node _T_989 = or(_T_988, _T_972)
node _T_990 = or(_T_989, _T_973)
node _T_991 = or(_T_990, _T_974)
node _T_992 = and(_T_936, _T_991)
node _T_993 = or(UInt<1>(0h0), _T_992)
node _T_994 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_995 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_996 = cvt(_T_995)
node _T_997 = and(_T_996, asSInt(UInt<27>(0h4000000)))
node _T_998 = asSInt(_T_997)
node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0)))
node _T_1000 = and(_T_994, _T_999)
node _T_1001 = or(UInt<1>(0h0), _T_1000)
node _T_1002 = and(_T_993, _T_1001)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_41
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(source_ok, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(is_aligned, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1012 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_44
node _T_1016 = eq(io.in.a.bits.mask, mask)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_45
node _T_1020 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1020 :
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1025 = shr(io.in.a.bits.source, 2)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
node _T_1027 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1030 = and(_T_1028, _T_1029)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1031 = shr(io.in.a.bits.source, 2)
node _T_1032 = eq(_T_1031, UInt<1>(0h1))
node _T_1033 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1034 = and(_T_1032, _T_1033)
node _T_1035 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1036 = and(_T_1034, _T_1035)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1037 = shr(io.in.a.bits.source, 2)
node _T_1038 = eq(_T_1037, UInt<2>(0h2))
node _T_1039 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1042 = and(_T_1040, _T_1041)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<2>(0h3))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _T_1049 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1050 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1051 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1052 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1053 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1054 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1055 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1056 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1057 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1058 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1059 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1060 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1061 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1062 = or(_T_1024, _T_1030)
node _T_1063 = or(_T_1062, _T_1036)
node _T_1064 = or(_T_1063, _T_1042)
node _T_1065 = or(_T_1064, _T_1048)
node _T_1066 = or(_T_1065, _T_1049)
node _T_1067 = or(_T_1066, _T_1050)
node _T_1068 = or(_T_1067, _T_1051)
node _T_1069 = or(_T_1068, _T_1052)
node _T_1070 = or(_T_1069, _T_1053)
node _T_1071 = or(_T_1070, _T_1054)
node _T_1072 = or(_T_1071, _T_1055)
node _T_1073 = or(_T_1072, _T_1056)
node _T_1074 = or(_T_1073, _T_1057)
node _T_1075 = or(_T_1074, _T_1058)
node _T_1076 = or(_T_1075, _T_1059)
node _T_1077 = or(_T_1076, _T_1060)
node _T_1078 = or(_T_1077, _T_1061)
node _T_1079 = and(_T_1023, _T_1078)
node _T_1080 = or(UInt<1>(0h0), _T_1079)
node _T_1081 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1082 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1083 = cvt(_T_1082)
node _T_1084 = and(_T_1083, asSInt(UInt<27>(0h4000000)))
node _T_1085 = asSInt(_T_1084)
node _T_1086 = eq(_T_1085, asSInt(UInt<1>(0h0)))
node _T_1087 = and(_T_1081, _T_1086)
node _T_1088 = or(UInt<1>(0h0), _T_1087)
node _T_1089 = and(_T_1080, _T_1088)
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_T_1089, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1089, UInt<1>(0h1), "") : assert_46
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(source_ok, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1096 = asUInt(reset)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(is_aligned, UInt<1>(0h0))
when _T_1098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1099 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_49
node _T_1103 = eq(io.in.a.bits.mask, mask)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_50
node _T_1107 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1111 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_52
node _source_ok_T_54 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<1>(0h0))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h1))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<2>(0h2))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_73 = shr(io.in.d.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h3))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_80 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_81 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_82 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[18]
connect _source_ok_WIRE_1[0], _source_ok_T_54
connect _source_ok_WIRE_1[1], _source_ok_T_60
connect _source_ok_WIRE_1[2], _source_ok_T_66
connect _source_ok_WIRE_1[3], _source_ok_T_72
connect _source_ok_WIRE_1[4], _source_ok_T_78
connect _source_ok_WIRE_1[5], _source_ok_T_79
connect _source_ok_WIRE_1[6], _source_ok_T_80
connect _source_ok_WIRE_1[7], _source_ok_T_81
connect _source_ok_WIRE_1[8], _source_ok_T_82
connect _source_ok_WIRE_1[9], _source_ok_T_83
connect _source_ok_WIRE_1[10], _source_ok_T_84
connect _source_ok_WIRE_1[11], _source_ok_T_85
connect _source_ok_WIRE_1[12], _source_ok_T_86
connect _source_ok_WIRE_1[13], _source_ok_T_87
connect _source_ok_WIRE_1[14], _source_ok_T_88
connect _source_ok_WIRE_1[15], _source_ok_T_89
connect _source_ok_WIRE_1[16], _source_ok_T_90
connect _source_ok_WIRE_1[17], _source_ok_T_91
node _source_ok_T_92 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[2])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[3])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[4])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[5])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[6])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[7])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[8])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[9])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[10])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[11])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[12])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[13])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[14])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[15])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[16])
node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[17])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1115 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1115 :
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(source_ok_1, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_54
node _T_1123 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_55
node _T_1127 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_56
node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_57
node _T_1135 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1135 :
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(source_ok_1, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(sink_ok, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1142 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_60
node _T_1146 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_61
node _T_1150 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_62
node _T_1154 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_63
node _T_1158 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1159 = or(UInt<1>(0h0), _T_1158)
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_64
node _T_1163 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1163 :
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(source_ok_1, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(sink_ok, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1170 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_67
node _T_1174 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_68
node _T_1178 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_69
node _T_1182 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1183 = or(_T_1182, io.in.d.bits.corrupt)
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(_T_1183, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1183, UInt<1>(0h1), "") : assert_70
node _T_1187 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1188 = or(UInt<1>(0h0), _T_1187)
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_71
node _T_1192 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(source_ok_1, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1196 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1197 = asUInt(reset)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
when _T_1198 :
node _T_1199 = eq(_T_1196, UInt<1>(0h0))
when _T_1199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1196, UInt<1>(0h1), "") : assert_73
node _T_1200 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1201 = asUInt(reset)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
when _T_1202 :
node _T_1203 = eq(_T_1200, UInt<1>(0h0))
when _T_1203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1200, UInt<1>(0h1), "") : assert_74
node _T_1204 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1205 = or(UInt<1>(0h0), _T_1204)
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_75
node _T_1209 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1209 :
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(source_ok_1, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1213 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_77
node _T_1217 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1218 = or(_T_1217, io.in.d.bits.corrupt)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_78
node _T_1222 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1223 = or(UInt<1>(0h0), _T_1222)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_79
node _T_1227 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1227 :
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(source_ok_1, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1231 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_81
node _T_1235 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_82
node _T_1239 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1240 = or(UInt<1>(0h0), _T_1239)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<28>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1244 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1248 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1252 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1256 = eq(a_first, UInt<1>(0h0))
node _T_1257 = and(io.in.a.valid, _T_1256)
when _T_1257 :
node _T_1258 = eq(io.in.a.bits.opcode, opcode)
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(_T_1258, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1258, UInt<1>(0h1), "") : assert_87
node _T_1262 = eq(io.in.a.bits.param, param)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_88
node _T_1266 = eq(io.in.a.bits.size, size)
node _T_1267 = asUInt(reset)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
when _T_1268 :
node _T_1269 = eq(_T_1266, UInt<1>(0h0))
when _T_1269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1266, UInt<1>(0h1), "") : assert_89
node _T_1270 = eq(io.in.a.bits.source, source)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_90
node _T_1274 = eq(io.in.a.bits.address, address)
node _T_1275 = asUInt(reset)
node _T_1276 = eq(_T_1275, UInt<1>(0h0))
when _T_1276 :
node _T_1277 = eq(_T_1274, UInt<1>(0h0))
when _T_1277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1274, UInt<1>(0h1), "") : assert_91
node _T_1278 = and(io.in.a.ready, io.in.a.valid)
node _T_1279 = and(_T_1278, a_first)
when _T_1279 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1280 = eq(d_first, UInt<1>(0h0))
node _T_1281 = and(io.in.d.valid, _T_1280)
when _T_1281 :
node _T_1282 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_92
node _T_1286 = eq(io.in.d.bits.param, param_1)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_93
node _T_1290 = eq(io.in.d.bits.size, size_1)
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(_T_1290, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1290, UInt<1>(0h1), "") : assert_94
node _T_1294 = eq(io.in.d.bits.source, source_1)
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_95
node _T_1298 = eq(io.in.d.bits.sink, sink)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_96
node _T_1302 = eq(io.in.d.bits.denied, denied)
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_97
node _T_1306 = and(io.in.d.ready, io.in.d.valid)
node _T_1307 = and(_T_1306, d_first)
when _T_1307 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1308 = and(io.in.a.valid, a_first_1)
node _T_1309 = and(_T_1308, UInt<1>(0h1))
when _T_1309 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1310 = and(io.in.a.ready, io.in.a.valid)
node _T_1311 = and(_T_1310, a_first_1)
node _T_1312 = and(_T_1311, UInt<1>(0h1))
when _T_1312 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1313 = dshr(inflight, io.in.a.bits.source)
node _T_1314 = bits(_T_1313, 0, 0)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1319 = and(io.in.d.valid, d_first_1)
node _T_1320 = and(_T_1319, UInt<1>(0h1))
node _T_1321 = eq(d_release_ack, UInt<1>(0h0))
node _T_1322 = and(_T_1320, _T_1321)
when _T_1322 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1323 = and(io.in.d.ready, io.in.d.valid)
node _T_1324 = and(_T_1323, d_first_1)
node _T_1325 = and(_T_1324, UInt<1>(0h1))
node _T_1326 = eq(d_release_ack, UInt<1>(0h0))
node _T_1327 = and(_T_1325, _T_1326)
when _T_1327 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1328 = and(io.in.d.valid, d_first_1)
node _T_1329 = and(_T_1328, UInt<1>(0h1))
node _T_1330 = eq(d_release_ack, UInt<1>(0h0))
node _T_1331 = and(_T_1329, _T_1330)
when _T_1331 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1332 = dshr(inflight, io.in.d.bits.source)
node _T_1333 = bits(_T_1332, 0, 0)
node _T_1334 = or(_T_1333, same_cycle_resp)
node _T_1335 = asUInt(reset)
node _T_1336 = eq(_T_1335, UInt<1>(0h0))
when _T_1336 :
node _T_1337 = eq(_T_1334, UInt<1>(0h0))
when _T_1337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1334, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1338 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1339 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1340 = or(_T_1338, _T_1339)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_100
node _T_1344 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1345 = asUInt(reset)
node _T_1346 = eq(_T_1345, UInt<1>(0h0))
when _T_1346 :
node _T_1347 = eq(_T_1344, UInt<1>(0h0))
when _T_1347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1344, UInt<1>(0h1), "") : assert_101
else :
node _T_1348 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1349 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1350 = or(_T_1348, _T_1349)
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_102
node _T_1354 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_103
node _T_1358 = and(io.in.d.valid, d_first_1)
node _T_1359 = and(_T_1358, a_first_1)
node _T_1360 = and(_T_1359, io.in.a.valid)
node _T_1361 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1362 = and(_T_1360, _T_1361)
node _T_1363 = eq(d_release_ack, UInt<1>(0h0))
node _T_1364 = and(_T_1362, _T_1363)
when _T_1364 :
node _T_1365 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1366 = or(_T_1365, io.in.a.ready)
node _T_1367 = asUInt(reset)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
when _T_1368 :
node _T_1369 = eq(_T_1366, UInt<1>(0h0))
when _T_1369 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1366, UInt<1>(0h1), "") : assert_104
node _T_1370 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1371 = orr(a_set_wo_ready)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
node _T_1373 = or(_T_1370, _T_1372)
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(_T_1373, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1373, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_63
node _T_1377 = orr(inflight)
node _T_1378 = eq(_T_1377, UInt<1>(0h0))
node _T_1379 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1380 = or(_T_1378, _T_1379)
node _T_1381 = lt(watchdog, plusarg_reader.out)
node _T_1382 = or(_T_1380, _T_1381)
node _T_1383 = asUInt(reset)
node _T_1384 = eq(_T_1383, UInt<1>(0h0))
when _T_1384 :
node _T_1385 = eq(_T_1382, UInt<1>(0h0))
when _T_1385 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1382, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1386 = and(io.in.a.ready, io.in.a.valid)
node _T_1387 = and(io.in.d.ready, io.in.d.valid)
node _T_1388 = or(_T_1386, _T_1387)
when _T_1388 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1389 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1390 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1391 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1392 = and(_T_1390, _T_1391)
node _T_1393 = and(_T_1389, _T_1392)
when _T_1393 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1394 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1395 = and(_T_1394, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1396 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1397 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1398 = and(_T_1396, _T_1397)
node _T_1399 = and(_T_1395, _T_1398)
when _T_1399 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1400 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1401 = bits(_T_1400, 0, 0)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1406 = and(io.in.d.valid, d_first_2)
node _T_1407 = and(_T_1406, UInt<1>(0h1))
node _T_1408 = and(_T_1407, d_release_ack_1)
when _T_1408 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = and(_T_1409, d_first_2)
node _T_1411 = and(_T_1410, UInt<1>(0h1))
node _T_1412 = and(_T_1411, d_release_ack_1)
when _T_1412 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1413 = and(io.in.d.valid, d_first_2)
node _T_1414 = and(_T_1413, UInt<1>(0h1))
node _T_1415 = and(_T_1414, d_release_ack_1)
when _T_1415 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1416 = dshr(inflight_1, io.in.d.bits.source)
node _T_1417 = bits(_T_1416, 0, 0)
node _T_1418 = or(_T_1417, same_cycle_resp_1)
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1422 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1423 = asUInt(reset)
node _T_1424 = eq(_T_1423, UInt<1>(0h0))
when _T_1424 :
node _T_1425 = eq(_T_1422, UInt<1>(0h0))
when _T_1425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1422, UInt<1>(0h1), "") : assert_109
else :
node _T_1426 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1427 = asUInt(reset)
node _T_1428 = eq(_T_1427, UInt<1>(0h0))
when _T_1428 :
node _T_1429 = eq(_T_1426, UInt<1>(0h0))
when _T_1429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1426, UInt<1>(0h1), "") : assert_110
node _T_1430 = and(io.in.d.valid, d_first_2)
node _T_1431 = and(_T_1430, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1432 = and(_T_1431, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1433 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1434 = and(_T_1432, _T_1433)
node _T_1435 = and(_T_1434, d_release_ack_1)
node _T_1436 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1437 = and(_T_1435, _T_1436)
when _T_1437 :
node _T_1438 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<28>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1439 = or(_T_1438, _WIRE_27.ready)
node _T_1440 = asUInt(reset)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
node _T_1442 = eq(_T_1439, UInt<1>(0h0))
when _T_1442 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1439, UInt<1>(0h1), "") : assert_111
node _T_1443 = orr(c_set_wo_ready)
when _T_1443 :
node _T_1444 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1445 = asUInt(reset)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
when _T_1446 :
node _T_1447 = eq(_T_1444, UInt<1>(0h0))
when _T_1447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1444, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_64
node _T_1448 = orr(inflight_1)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
node _T_1450 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1451 = or(_T_1449, _T_1450)
node _T_1452 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1453 = or(_T_1451, _T_1452)
node _T_1454 = asUInt(reset)
node _T_1455 = eq(_T_1454, UInt<1>(0h0))
when _T_1455 :
node _T_1456 = eq(_T_1453, UInt<1>(0h0))
when _T_1456 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1453, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<28>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1457 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1458 = and(io.in.d.ready, io.in.d.valid)
node _T_1459 = or(_T_1457, _T_1458)
when _T_1459 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_27( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module Mul54 :
input clock : Clock
input reset : Reset
output io : { flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>}
reg val_s1 : UInt<1>, clock
reg val_s2 : UInt<1>, clock
reg reg_a_s1 : UInt<54>, clock
reg reg_b_s1 : UInt<54>, clock
reg reg_a_s2 : UInt<54>, clock
reg reg_b_s2 : UInt<54>, clock
reg reg_result_s3 : UInt<105>, clock
connect val_s1, io.val_s0
connect val_s2, val_s1
when io.val_s0 :
when io.latch_a_s0 :
connect reg_a_s1, io.a_s0
when io.latch_b_s0 :
connect reg_b_s1, io.b_s0
when val_s1 :
connect reg_a_s2, reg_a_s1
connect reg_b_s2, reg_b_s1
when val_s2 :
node _reg_result_s3_T = mul(reg_a_s2, reg_b_s2)
node _reg_result_s3_T_1 = bits(_reg_result_s3_T, 104, 0)
node _reg_result_s3_T_2 = add(_reg_result_s3_T_1, io.c_s2)
node _reg_result_s3_T_3 = tail(_reg_result_s3_T_2, 1)
connect reg_result_s3, _reg_result_s3_T_3
connect io.result_s3, reg_result_s3 | module Mul54( // @[DivSqrtRecF64.scala:85:7]
input clock, // @[DivSqrtRecF64.scala:85:7]
input reset, // @[DivSqrtRecF64.scala:85:7]
input io_val_s0, // @[DivSqrtRecF64.scala:87:16]
input io_latch_a_s0, // @[DivSqrtRecF64.scala:87:16]
input [53:0] io_a_s0, // @[DivSqrtRecF64.scala:87:16]
input io_latch_b_s0, // @[DivSqrtRecF64.scala:87:16]
input [53:0] io_b_s0, // @[DivSqrtRecF64.scala:87:16]
input [104:0] io_c_s2, // @[DivSqrtRecF64.scala:87:16]
output [104:0] io_result_s3 // @[DivSqrtRecF64.scala:87:16]
);
wire io_val_s0_0 = io_val_s0; // @[DivSqrtRecF64.scala:85:7]
wire io_latch_a_s0_0 = io_latch_a_s0; // @[DivSqrtRecF64.scala:85:7]
wire [53:0] io_a_s0_0 = io_a_s0; // @[DivSqrtRecF64.scala:85:7]
wire io_latch_b_s0_0 = io_latch_b_s0; // @[DivSqrtRecF64.scala:85:7]
wire [53:0] io_b_s0_0 = io_b_s0; // @[DivSqrtRecF64.scala:85:7]
wire [104:0] io_c_s2_0 = io_c_s2; // @[DivSqrtRecF64.scala:85:7]
wire [104:0] io_result_s3_0; // @[DivSqrtRecF64.scala:85:7]
reg val_s1; // @[DivSqrtRecF64.scala:97:21]
reg val_s2; // @[DivSqrtRecF64.scala:98:21]
reg [53:0] reg_a_s1; // @[DivSqrtRecF64.scala:99:23]
reg [53:0] reg_b_s1; // @[DivSqrtRecF64.scala:100:23]
reg [53:0] reg_a_s2; // @[DivSqrtRecF64.scala:101:23]
reg [53:0] reg_b_s2; // @[DivSqrtRecF64.scala:102:23]
reg [104:0] reg_result_s3; // @[DivSqrtRecF64.scala:103:28]
assign io_result_s3_0 = reg_result_s3; // @[DivSqrtRecF64.scala:85:7, :103:28]
wire [107:0] _reg_result_s3_T = {54'h0, reg_a_s2} * {54'h0, reg_b_s2}; // @[DivSqrtRecF64.scala:101:23, :102:23, :123:36]
wire [104:0] _reg_result_s3_T_1 = _reg_result_s3_T[104:0]; // @[DivSqrtRecF64.scala:123:{36,47}]
wire [105:0] _reg_result_s3_T_2 = {1'h0, _reg_result_s3_T_1} + {1'h0, io_c_s2_0}; // @[DivSqrtRecF64.scala:85:7, :123:{47,55}]
wire [104:0] _reg_result_s3_T_3 = _reg_result_s3_T_2[104:0]; // @[DivSqrtRecF64.scala:123:55]
always @(posedge clock) begin // @[DivSqrtRecF64.scala:85:7]
val_s1 <= io_val_s0_0; // @[DivSqrtRecF64.scala:85:7, :97:21]
val_s2 <= val_s1; // @[DivSqrtRecF64.scala:97:21, :98:21]
if (io_val_s0_0 & io_latch_a_s0_0) // @[DivSqrtRecF64.scala:85:7, :99:23, :108:22, :109:30, :110:22]
reg_a_s1 <= io_a_s0_0; // @[DivSqrtRecF64.scala:85:7, :99:23]
if (io_val_s0_0 & io_latch_b_s0_0) // @[DivSqrtRecF64.scala:85:7, :100:23, :108:22, :112:30, :113:22]
reg_b_s1 <= io_b_s0_0; // @[DivSqrtRecF64.scala:85:7, :100:23]
if (val_s1) begin // @[DivSqrtRecF64.scala:97:21]
reg_a_s2 <= reg_a_s1; // @[DivSqrtRecF64.scala:99:23, :101:23]
reg_b_s2 <= reg_b_s1; // @[DivSqrtRecF64.scala:100:23, :102:23]
end
if (val_s2) // @[DivSqrtRecF64.scala:98:21]
reg_result_s3 <= _reg_result_s3_T_3; // @[DivSqrtRecF64.scala:103:28, :123:55]
always @(posedge)
assign io_result_s3 = io_result_s3_0; // @[DivSqrtRecF64.scala:85:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCToBeat_SerialRAM_a64d64s8k8z8c :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}}
inst q of Queue1_TLBundleC_a64d64s8k8z8c
connect q.clock, clock
connect q.reset, reset
connect q.io.enq, io.protocol
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node head_beats1 = mux(UInt<1>(0h0), head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node tail_beats1 = mux(UInt<1>(0h0), tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.beat.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.beat.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_beat_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_beat_bits_head_T_1 = and(head, _io_beat_bits_head_T)
connect io.beat.bits.head, _io_beat_bits_head_T_1
node _io_beat_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_beat_bits_tail_T_1 = or(is_body, _io_beat_bits_tail_T)
node _io_beat_bits_tail_T_2 = and(tail, _io_beat_bits_tail_T_1)
connect io.beat.bits.tail, _io_beat_bits_tail_T_2
node _io_beat_bits_payload_T = mux(is_body, body, const)
connect io.beat.bits.payload, _io_beat_bits_payload_T
node _T = and(io.beat.ready, io.beat.valid)
node _T_1 = and(_T, io.beat.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.beat.ready, io.beat.valid)
node _T_3 = and(_T_2, io.beat.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0)
connect has_body, UInt<1>(0h0) | module TLCToBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:124:7]
input clock, // @[TLChannelCompactor.scala:124:7]
input reset, // @[TLChannelCompactor.scala:124:7]
output io_beat_bits_head // @[TLChannelCompactor.scala:40:14]
);
assign io_beat_bits_head = 1'h1; // @[TLChannelCompactor.scala:124:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i32_e8_s24_9 :
output io : { flip signedIn : UInt<1>, flip in : UInt<32>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 31, 31)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<32>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 31, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2)
node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3)
node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4)
node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5)
node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6)
node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7)
node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8)
node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9)
node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10)
node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11)
node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12)
node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13)
node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14)
node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15)
node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16)
node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17)
node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18)
node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19)
node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20)
node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21)
node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22)
node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23)
node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24)
node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25)
node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26)
node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27)
node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28)
node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29)
node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30)
node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31)
node _intAsRawFloat_adjustedNormDist_T_32 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<5>(0h1e), UInt<5>(0h1f))
node _intAsRawFloat_adjustedNormDist_T_33 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_32)
node _intAsRawFloat_adjustedNormDist_T_34 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_33)
node _intAsRawFloat_adjustedNormDist_T_35 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_34)
node _intAsRawFloat_adjustedNormDist_T_36 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_35)
node _intAsRawFloat_adjustedNormDist_T_37 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_36)
node _intAsRawFloat_adjustedNormDist_T_38 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_37)
node _intAsRawFloat_adjustedNormDist_T_39 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_38)
node _intAsRawFloat_adjustedNormDist_T_40 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_39)
node _intAsRawFloat_adjustedNormDist_T_41 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_40)
node _intAsRawFloat_adjustedNormDist_T_42 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_41)
node _intAsRawFloat_adjustedNormDist_T_43 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_42)
node _intAsRawFloat_adjustedNormDist_T_44 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_43)
node _intAsRawFloat_adjustedNormDist_T_45 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_44)
node _intAsRawFloat_adjustedNormDist_T_46 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_45)
node _intAsRawFloat_adjustedNormDist_T_47 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_46)
node _intAsRawFloat_adjustedNormDist_T_48 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_47)
node _intAsRawFloat_adjustedNormDist_T_49 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_48)
node _intAsRawFloat_adjustedNormDist_T_50 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_49)
node _intAsRawFloat_adjustedNormDist_T_51 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_50)
node _intAsRawFloat_adjustedNormDist_T_52 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_51)
node _intAsRawFloat_adjustedNormDist_T_53 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_52)
node _intAsRawFloat_adjustedNormDist_T_54 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_53)
node _intAsRawFloat_adjustedNormDist_T_55 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_54)
node _intAsRawFloat_adjustedNormDist_T_56 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_55)
node _intAsRawFloat_adjustedNormDist_T_57 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_56)
node _intAsRawFloat_adjustedNormDist_T_58 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_57)
node _intAsRawFloat_adjustedNormDist_T_59 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_58)
node _intAsRawFloat_adjustedNormDist_T_60 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_59)
node _intAsRawFloat_adjustedNormDist_T_61 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_60)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_61)
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 31, 0)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 31, 31)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 4, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_9
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i32_e8_s24_9( // @[INToRecFN.scala:43:7]
input [31:0] io_in, // @[INToRecFN.scala:46:16]
output [32:0] io_out // @[INToRecFN.scala:46:16]
);
wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [32:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31]
wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70]
wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_9 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_25 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = and(_T_11, _T_24)
node _T_105 = and(_T_104, _T_37)
node _T_106 = and(_T_105, _T_50)
node _T_107 = and(_T_106, _T_63)
node _T_108 = and(_T_107, _T_71)
node _T_109 = and(_T_108, _T_79)
node _T_110 = and(_T_109, _T_87)
node _T_111 = and(_T_110, _T_95)
node _T_112 = and(_T_111, _T_103)
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(_T_112, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_112, UInt<1>(0h1), "") : assert_1
node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_116 :
node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_121 = shr(io.in.a.bits.source, 2)
node _T_122 = eq(_T_121, UInt<1>(0h0))
node _T_123 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_124 = and(_T_122, _T_123)
node _T_125 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_126 = and(_T_124, _T_125)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<1>(0h1))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<2>(0h2))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<2>(0h3))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_120, _T_126)
node _T_151 = or(_T_150, _T_132)
node _T_152 = or(_T_151, _T_138)
node _T_153 = or(_T_152, _T_144)
node _T_154 = or(_T_153, _T_145)
node _T_155 = or(_T_154, _T_146)
node _T_156 = or(_T_155, _T_147)
node _T_157 = or(_T_156, _T_148)
node _T_158 = or(_T_157, _T_149)
node _T_159 = and(_T_119, _T_158)
node _T_160 = or(UInt<1>(0h0), _T_159)
node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<27>(0h4000000)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = and(_T_161, _T_166)
node _T_168 = or(UInt<1>(0h0), _T_167)
node _T_169 = and(_T_160, _T_168)
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_169, UInt<1>(0h1), "") : assert_2
node _T_173 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_174 = shr(io.in.a.bits.source, 2)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_177 = and(_T_175, _T_176)
node _T_178 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_179 = and(_T_177, _T_178)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_180 = shr(io.in.a.bits.source, 2)
node _T_181 = eq(_T_180, UInt<1>(0h1))
node _T_182 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_183 = and(_T_181, _T_182)
node _T_184 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_185 = and(_T_183, _T_184)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_186 = shr(io.in.a.bits.source, 2)
node _T_187 = eq(_T_186, UInt<2>(0h2))
node _T_188 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_189 = and(_T_187, _T_188)
node _T_190 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_191 = and(_T_189, _T_190)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_192 = shr(io.in.a.bits.source, 2)
node _T_193 = eq(_T_192, UInt<2>(0h3))
node _T_194 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_195 = and(_T_193, _T_194)
node _T_196 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_201 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_202 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[10]
connect _WIRE[0], _T_173
connect _WIRE[1], _T_179
connect _WIRE[2], _T_185
connect _WIRE[3], _T_191
connect _WIRE[4], _T_197
connect _WIRE[5], _T_198
connect _WIRE[6], _T_199
connect _WIRE[7], _T_200
connect _WIRE[8], _T_201
connect _WIRE[9], _T_202
node _T_203 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_204 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_205 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_207 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[6], _T_203, UInt<1>(0h0))
node _T_211 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_213 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_214 = or(_T_204, _T_205)
node _T_215 = or(_T_214, _T_206)
node _T_216 = or(_T_215, _T_207)
node _T_217 = or(_T_216, _T_208)
node _T_218 = or(_T_217, _T_209)
node _T_219 = or(_T_218, _T_210)
node _T_220 = or(_T_219, _T_211)
node _T_221 = or(_T_220, _T_212)
node _T_222 = or(_T_221, _T_213)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_222
node _T_223 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_224 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_225 = and(_T_223, _T_224)
node _T_226 = or(UInt<1>(0h0), _T_225)
node _T_227 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_228 = cvt(_T_227)
node _T_229 = and(_T_228, asSInt(UInt<27>(0h4000000)))
node _T_230 = asSInt(_T_229)
node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0)))
node _T_232 = and(_T_226, _T_231)
node _T_233 = or(UInt<1>(0h0), _T_232)
node _T_234 = and(_WIRE_1, _T_233)
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_234, UInt<1>(0h1), "") : assert_3
node _T_238 = asUInt(reset)
node _T_239 = eq(_T_238, UInt<1>(0h0))
when _T_239 :
node _T_240 = eq(source_ok, UInt<1>(0h0))
when _T_240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_242 = asUInt(reset)
node _T_243 = eq(_T_242, UInt<1>(0h0))
when _T_243 :
node _T_244 = eq(_T_241, UInt<1>(0h0))
when _T_244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_241, UInt<1>(0h1), "") : assert_5
node _T_245 = asUInt(reset)
node _T_246 = eq(_T_245, UInt<1>(0h0))
when _T_246 :
node _T_247 = eq(is_aligned, UInt<1>(0h0))
when _T_247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_248, UInt<1>(0h1), "") : assert_7
node _T_252 = not(io.in.a.bits.mask)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_253, UInt<1>(0h1), "") : assert_8
node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_T_257, UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_257, UInt<1>(0h1), "") : assert_9
node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_261 :
node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<1>(0h1))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h2))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<2>(0h3))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_295 = or(_T_265, _T_271)
node _T_296 = or(_T_295, _T_277)
node _T_297 = or(_T_296, _T_283)
node _T_298 = or(_T_297, _T_289)
node _T_299 = or(_T_298, _T_290)
node _T_300 = or(_T_299, _T_291)
node _T_301 = or(_T_300, _T_292)
node _T_302 = or(_T_301, _T_293)
node _T_303 = or(_T_302, _T_294)
node _T_304 = and(_T_264, _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_307 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<27>(0h4000000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = and(_T_306, _T_311)
node _T_313 = or(UInt<1>(0h0), _T_312)
node _T_314 = and(_T_305, _T_313)
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(_T_314, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_314, UInt<1>(0h1), "") : assert_10
node _T_318 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_319 = shr(io.in.a.bits.source, 2)
node _T_320 = eq(_T_319, UInt<1>(0h0))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_325 = shr(io.in.a.bits.source, 2)
node _T_326 = eq(_T_325, UInt<1>(0h1))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_330 = and(_T_328, _T_329)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<2>(0h2))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<2>(0h3))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[10]
connect _WIRE_2[0], _T_318
connect _WIRE_2[1], _T_324
connect _WIRE_2[2], _T_330
connect _WIRE_2[3], _T_336
connect _WIRE_2[4], _T_342
connect _WIRE_2[5], _T_343
connect _WIRE_2[6], _T_344
connect _WIRE_2[7], _T_345
connect _WIRE_2[8], _T_346
connect _WIRE_2[9], _T_347
node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_349 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_350 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_352 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_353 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_354 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_355 = mux(_WIRE_2[6], _T_348, UInt<1>(0h0))
node _T_356 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_357 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = or(_T_349, _T_350)
node _T_360 = or(_T_359, _T_351)
node _T_361 = or(_T_360, _T_352)
node _T_362 = or(_T_361, _T_353)
node _T_363 = or(_T_362, _T_354)
node _T_364 = or(_T_363, _T_355)
node _T_365 = or(_T_364, _T_356)
node _T_366 = or(_T_365, _T_357)
node _T_367 = or(_T_366, _T_358)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_367
node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_370 = and(_T_368, _T_369)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<27>(0h4000000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = and(_T_371, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = and(_WIRE_3, _T_378)
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_379, UInt<1>(0h1), "") : assert_11
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(source_ok, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_386, UInt<1>(0h1), "") : assert_13
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(is_aligned, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_393, UInt<1>(0h1), "") : assert_15
node _T_397 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_397, UInt<1>(0h1), "") : assert_16
node _T_401 = not(io.in.a.bits.mask)
node _T_402 = eq(_T_401, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_402, UInt<1>(0h1), "") : assert_17
node _T_406 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_406, UInt<1>(0h1), "") : assert_18
node _T_410 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_410 :
node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_413 = and(_T_411, _T_412)
node _T_414 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_415 = shr(io.in.a.bits.source, 2)
node _T_416 = eq(_T_415, UInt<1>(0h0))
node _T_417 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_418 = and(_T_416, _T_417)
node _T_419 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h1))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<2>(0h2))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h3))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_444 = or(_T_414, _T_420)
node _T_445 = or(_T_444, _T_426)
node _T_446 = or(_T_445, _T_432)
node _T_447 = or(_T_446, _T_438)
node _T_448 = or(_T_447, _T_439)
node _T_449 = or(_T_448, _T_440)
node _T_450 = or(_T_449, _T_441)
node _T_451 = or(_T_450, _T_442)
node _T_452 = or(_T_451, _T_443)
node _T_453 = and(_T_413, _T_452)
node _T_454 = or(UInt<1>(0h0), _T_453)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_454, UInt<1>(0h1), "") : assert_19
node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_459 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_460 = and(_T_458, _T_459)
node _T_461 = or(UInt<1>(0h0), _T_460)
node _T_462 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<27>(0h4000000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = and(_T_461, _T_466)
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_468, UInt<1>(0h1), "") : assert_20
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(source_ok, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(is_aligned, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_478 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_478, UInt<1>(0h1), "") : assert_23
node _T_482 = eq(io.in.a.bits.mask, mask)
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_482, UInt<1>(0h1), "") : assert_24
node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_486, UInt<1>(0h1), "") : assert_25
node _T_490 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_490 :
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_495 = shr(io.in.a.bits.source, 2)
node _T_496 = eq(_T_495, UInt<1>(0h0))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<1>(0h1))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<2>(0h2))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<2>(0h3))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_524 = or(_T_494, _T_500)
node _T_525 = or(_T_524, _T_506)
node _T_526 = or(_T_525, _T_512)
node _T_527 = or(_T_526, _T_518)
node _T_528 = or(_T_527, _T_519)
node _T_529 = or(_T_528, _T_520)
node _T_530 = or(_T_529, _T_521)
node _T_531 = or(_T_530, _T_522)
node _T_532 = or(_T_531, _T_523)
node _T_533 = and(_T_493, _T_532)
node _T_534 = or(UInt<1>(0h0), _T_533)
node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_536 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_537 = and(_T_535, _T_536)
node _T_538 = or(UInt<1>(0h0), _T_537)
node _T_539 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<27>(0h4000000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = and(_T_538, _T_543)
node _T_545 = or(UInt<1>(0h0), _T_544)
node _T_546 = and(_T_534, _T_545)
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_546, UInt<1>(0h1), "") : assert_26
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(source_ok, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(is_aligned, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_556 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_556, UInt<1>(0h1), "") : assert_29
node _T_560 = eq(io.in.a.bits.mask, mask)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_560, UInt<1>(0h1), "") : assert_30
node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_564 :
node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_567 = and(_T_565, _T_566)
node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_569 = shr(io.in.a.bits.source, 2)
node _T_570 = eq(_T_569, UInt<1>(0h0))
node _T_571 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_572 = and(_T_570, _T_571)
node _T_573 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_574 = and(_T_572, _T_573)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_575 = shr(io.in.a.bits.source, 2)
node _T_576 = eq(_T_575, UInt<1>(0h1))
node _T_577 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_578 = and(_T_576, _T_577)
node _T_579 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_580 = and(_T_578, _T_579)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<2>(0h2))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<2>(0h3))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_598 = or(_T_568, _T_574)
node _T_599 = or(_T_598, _T_580)
node _T_600 = or(_T_599, _T_586)
node _T_601 = or(_T_600, _T_592)
node _T_602 = or(_T_601, _T_593)
node _T_603 = or(_T_602, _T_594)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_596)
node _T_606 = or(_T_605, _T_597)
node _T_607 = and(_T_567, _T_606)
node _T_608 = or(UInt<1>(0h0), _T_607)
node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_611 = and(_T_609, _T_610)
node _T_612 = or(UInt<1>(0h0), _T_611)
node _T_613 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<27>(0h4000000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = and(_T_612, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_618)
node _T_620 = and(_T_608, _T_619)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_620, UInt<1>(0h1), "") : assert_31
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(source_ok, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(is_aligned, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_630 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_630, UInt<1>(0h1), "") : assert_34
node _T_634 = not(mask)
node _T_635 = and(io.in.a.bits.mask, _T_634)
node _T_636 = eq(_T_635, UInt<1>(0h0))
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_636, UInt<1>(0h1), "") : assert_35
node _T_640 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_640 :
node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_645 = shr(io.in.a.bits.source, 2)
node _T_646 = eq(_T_645, UInt<1>(0h0))
node _T_647 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_648 = and(_T_646, _T_647)
node _T_649 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_650 = and(_T_648, _T_649)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_651 = shr(io.in.a.bits.source, 2)
node _T_652 = eq(_T_651, UInt<1>(0h1))
node _T_653 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_654 = and(_T_652, _T_653)
node _T_655 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_656 = and(_T_654, _T_655)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_657 = shr(io.in.a.bits.source, 2)
node _T_658 = eq(_T_657, UInt<2>(0h2))
node _T_659 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_660 = and(_T_658, _T_659)
node _T_661 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_662 = and(_T_660, _T_661)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_663 = shr(io.in.a.bits.source, 2)
node _T_664 = eq(_T_663, UInt<2>(0h3))
node _T_665 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_666 = and(_T_664, _T_665)
node _T_667 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_668 = and(_T_666, _T_667)
node _T_669 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_673 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_674 = or(_T_644, _T_650)
node _T_675 = or(_T_674, _T_656)
node _T_676 = or(_T_675, _T_662)
node _T_677 = or(_T_676, _T_668)
node _T_678 = or(_T_677, _T_669)
node _T_679 = or(_T_678, _T_670)
node _T_680 = or(_T_679, _T_671)
node _T_681 = or(_T_680, _T_672)
node _T_682 = or(_T_681, _T_673)
node _T_683 = and(_T_643, _T_682)
node _T_684 = or(UInt<1>(0h0), _T_683)
node _T_685 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_686 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_687 = cvt(_T_686)
node _T_688 = and(_T_687, asSInt(UInt<27>(0h4000000)))
node _T_689 = asSInt(_T_688)
node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0)))
node _T_691 = and(_T_685, _T_690)
node _T_692 = or(UInt<1>(0h0), _T_691)
node _T_693 = and(_T_684, _T_692)
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_693, UInt<1>(0h1), "") : assert_36
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(source_ok, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(is_aligned, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_703 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_703, UInt<1>(0h1), "") : assert_39
node _T_707 = eq(io.in.a.bits.mask, mask)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_707, UInt<1>(0h1), "") : assert_40
node _T_711 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_711 :
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_714 = and(_T_712, _T_713)
node _T_715 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_716 = shr(io.in.a.bits.source, 2)
node _T_717 = eq(_T_716, UInt<1>(0h0))
node _T_718 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_719 = and(_T_717, _T_718)
node _T_720 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_722 = shr(io.in.a.bits.source, 2)
node _T_723 = eq(_T_722, UInt<1>(0h1))
node _T_724 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_725 = and(_T_723, _T_724)
node _T_726 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_727 = and(_T_725, _T_726)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_728 = shr(io.in.a.bits.source, 2)
node _T_729 = eq(_T_728, UInt<2>(0h2))
node _T_730 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_731 = and(_T_729, _T_730)
node _T_732 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_733 = and(_T_731, _T_732)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<2>(0h3))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _T_740 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_744 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_745 = or(_T_715, _T_721)
node _T_746 = or(_T_745, _T_727)
node _T_747 = or(_T_746, _T_733)
node _T_748 = or(_T_747, _T_739)
node _T_749 = or(_T_748, _T_740)
node _T_750 = or(_T_749, _T_741)
node _T_751 = or(_T_750, _T_742)
node _T_752 = or(_T_751, _T_743)
node _T_753 = or(_T_752, _T_744)
node _T_754 = and(_T_714, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_757 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_758 = cvt(_T_757)
node _T_759 = and(_T_758, asSInt(UInt<27>(0h4000000)))
node _T_760 = asSInt(_T_759)
node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0)))
node _T_762 = and(_T_756, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_762)
node _T_764 = and(_T_755, _T_763)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_764, UInt<1>(0h1), "") : assert_41
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(source_ok, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(is_aligned, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_774 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_774, UInt<1>(0h1), "") : assert_44
node _T_778 = eq(io.in.a.bits.mask, mask)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_778, UInt<1>(0h1), "") : assert_45
node _T_782 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_782 :
node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_787 = shr(io.in.a.bits.source, 2)
node _T_788 = eq(_T_787, UInt<1>(0h0))
node _T_789 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_790 = and(_T_788, _T_789)
node _T_791 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_792 = and(_T_790, _T_791)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_793 = shr(io.in.a.bits.source, 2)
node _T_794 = eq(_T_793, UInt<1>(0h1))
node _T_795 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_796 = and(_T_794, _T_795)
node _T_797 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_798 = and(_T_796, _T_797)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_799 = shr(io.in.a.bits.source, 2)
node _T_800 = eq(_T_799, UInt<2>(0h2))
node _T_801 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_802 = and(_T_800, _T_801)
node _T_803 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_804 = and(_T_802, _T_803)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_805 = shr(io.in.a.bits.source, 2)
node _T_806 = eq(_T_805, UInt<2>(0h3))
node _T_807 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_808 = and(_T_806, _T_807)
node _T_809 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_810 = and(_T_808, _T_809)
node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_816 = or(_T_786, _T_792)
node _T_817 = or(_T_816, _T_798)
node _T_818 = or(_T_817, _T_804)
node _T_819 = or(_T_818, _T_810)
node _T_820 = or(_T_819, _T_811)
node _T_821 = or(_T_820, _T_812)
node _T_822 = or(_T_821, _T_813)
node _T_823 = or(_T_822, _T_814)
node _T_824 = or(_T_823, _T_815)
node _T_825 = and(_T_785, _T_824)
node _T_826 = or(UInt<1>(0h0), _T_825)
node _T_827 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_828 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<27>(0h4000000)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = and(_T_827, _T_832)
node _T_834 = or(UInt<1>(0h0), _T_833)
node _T_835 = and(_T_826, _T_834)
node _T_836 = asUInt(reset)
node _T_837 = eq(_T_836, UInt<1>(0h0))
when _T_837 :
node _T_838 = eq(_T_835, UInt<1>(0h0))
when _T_838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_835, UInt<1>(0h1), "") : assert_46
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(source_ok, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(is_aligned, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_845 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_845, UInt<1>(0h1), "") : assert_49
node _T_849 = eq(io.in.a.bits.mask, mask)
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_849, UInt<1>(0h1), "") : assert_50
node _T_853 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_853, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_857 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(_T_857, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_857, UInt<1>(0h1), "") : assert_52
node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_38
connect _source_ok_WIRE_1[1], _source_ok_T_44
connect _source_ok_WIRE_1[2], _source_ok_T_50
connect _source_ok_WIRE_1[3], _source_ok_T_56
connect _source_ok_WIRE_1[4], _source_ok_T_62
connect _source_ok_WIRE_1[5], _source_ok_T_63
connect _source_ok_WIRE_1[6], _source_ok_T_64
connect _source_ok_WIRE_1[7], _source_ok_T_65
connect _source_ok_WIRE_1[8], _source_ok_T_66
connect _source_ok_WIRE_1[9], _source_ok_T_67
node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_861 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_861 :
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(source_ok_1, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_865, UInt<1>(0h1), "") : assert_54
node _T_869 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_869, UInt<1>(0h1), "") : assert_55
node _T_873 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_873, UInt<1>(0h1), "") : assert_56
node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_877, UInt<1>(0h1), "") : assert_57
node _T_881 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_881 :
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(source_ok_1, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(sink_ok, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_888 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(_T_888, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_888, UInt<1>(0h1), "") : assert_60
node _T_892 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_892, UInt<1>(0h1), "") : assert_61
node _T_896 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_896, UInt<1>(0h1), "") : assert_62
node _T_900 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_900, UInt<1>(0h1), "") : assert_63
node _T_904 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_905 = or(UInt<1>(0h0), _T_904)
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(_T_905, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_905, UInt<1>(0h1), "") : assert_64
node _T_909 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_909 :
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(source_ok_1, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(sink_ok, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_916 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_916, UInt<1>(0h1), "") : assert_67
node _T_920 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_920, UInt<1>(0h1), "") : assert_68
node _T_924 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_924, UInt<1>(0h1), "") : assert_69
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(_T_928, io.in.d.bits.corrupt)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_929, UInt<1>(0h1), "") : assert_70
node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_934 = or(UInt<1>(0h0), _T_933)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_934, UInt<1>(0h1), "") : assert_71
node _T_938 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_938 :
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(source_ok_1, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_942 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_942, UInt<1>(0h1), "") : assert_73
node _T_946 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_946, UInt<1>(0h1), "") : assert_74
node _T_950 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_951 = or(UInt<1>(0h0), _T_950)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_951, UInt<1>(0h1), "") : assert_75
node _T_955 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_955 :
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(source_ok_1, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_959, UInt<1>(0h1), "") : assert_77
node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_964 = or(_T_963, io.in.d.bits.corrupt)
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_964, UInt<1>(0h1), "") : assert_78
node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_969, UInt<1>(0h1), "") : assert_79
node _T_973 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_973 :
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(source_ok_1, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_978 = asUInt(reset)
node _T_979 = eq(_T_978, UInt<1>(0h0))
when _T_979 :
node _T_980 = eq(_T_977, UInt<1>(0h0))
when _T_980 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_977, UInt<1>(0h1), "") : assert_81
node _T_981 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(_T_981, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_981, UInt<1>(0h1), "") : assert_82
node _T_985 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_986 = or(UInt<1>(0h0), _T_985)
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_986, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<28>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_990 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_990, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_994 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_994, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_998 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_998, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1002 = eq(a_first, UInt<1>(0h0))
node _T_1003 = and(io.in.a.valid, _T_1002)
when _T_1003 :
node _T_1004 = eq(io.in.a.bits.opcode, opcode)
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_87
node _T_1008 = eq(io.in.a.bits.param, param)
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(_T_1008, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1008, UInt<1>(0h1), "") : assert_88
node _T_1012 = eq(io.in.a.bits.size, size)
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_89
node _T_1016 = eq(io.in.a.bits.source, source)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_90
node _T_1020 = eq(io.in.a.bits.address, address)
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_91
node _T_1024 = and(io.in.a.ready, io.in.a.valid)
node _T_1025 = and(_T_1024, a_first)
when _T_1025 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1026 = eq(d_first, UInt<1>(0h0))
node _T_1027 = and(io.in.d.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_92
node _T_1032 = eq(io.in.d.bits.param, param_1)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_93
node _T_1036 = eq(io.in.d.bits.size, size_1)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_94
node _T_1040 = eq(io.in.d.bits.source, source_1)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_95
node _T_1044 = eq(io.in.d.bits.sink, sink)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_96
node _T_1048 = eq(io.in.d.bits.denied, denied)
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_97
node _T_1052 = and(io.in.d.ready, io.in.d.valid)
node _T_1053 = and(_T_1052, d_first)
when _T_1053 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1054 = and(io.in.a.valid, a_first_1)
node _T_1055 = and(_T_1054, UInt<1>(0h1))
when _T_1055 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1056 = and(io.in.a.ready, io.in.a.valid)
node _T_1057 = and(_T_1056, a_first_1)
node _T_1058 = and(_T_1057, UInt<1>(0h1))
when _T_1058 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1059 = dshr(inflight, io.in.a.bits.source)
node _T_1060 = bits(_T_1059, 0, 0)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1065 = and(io.in.d.valid, d_first_1)
node _T_1066 = and(_T_1065, UInt<1>(0h1))
node _T_1067 = eq(d_release_ack, UInt<1>(0h0))
node _T_1068 = and(_T_1066, _T_1067)
when _T_1068 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1069 = and(io.in.d.ready, io.in.d.valid)
node _T_1070 = and(_T_1069, d_first_1)
node _T_1071 = and(_T_1070, UInt<1>(0h1))
node _T_1072 = eq(d_release_ack, UInt<1>(0h0))
node _T_1073 = and(_T_1071, _T_1072)
when _T_1073 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1074 = and(io.in.d.valid, d_first_1)
node _T_1075 = and(_T_1074, UInt<1>(0h1))
node _T_1076 = eq(d_release_ack, UInt<1>(0h0))
node _T_1077 = and(_T_1075, _T_1076)
when _T_1077 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1078 = dshr(inflight, io.in.d.bits.source)
node _T_1079 = bits(_T_1078, 0, 0)
node _T_1080 = or(_T_1079, same_cycle_resp)
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1084 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1085 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1086 = or(_T_1084, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_100
node _T_1090 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_101
else :
node _T_1094 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1095 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1096 = or(_T_1094, _T_1095)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_102
node _T_1100 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_103
node _T_1104 = and(io.in.d.valid, d_first_1)
node _T_1105 = and(_T_1104, a_first_1)
node _T_1106 = and(_T_1105, io.in.a.valid)
node _T_1107 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = eq(d_release_ack, UInt<1>(0h0))
node _T_1110 = and(_T_1108, _T_1109)
when _T_1110 :
node _T_1111 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1112 = or(_T_1111, io.in.a.ready)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_104
node _T_1116 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1117 = orr(a_set_wo_ready)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
node _T_1119 = or(_T_1116, _T_1118)
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_50
node _T_1123 = orr(inflight)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
node _T_1125 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1126 = or(_T_1124, _T_1125)
node _T_1127 = lt(watchdog, plusarg_reader.out)
node _T_1128 = or(_T_1126, _T_1127)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1132 = and(io.in.a.ready, io.in.a.valid)
node _T_1133 = and(io.in.d.ready, io.in.d.valid)
node _T_1134 = or(_T_1132, _T_1133)
when _T_1134 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1135 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1136 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1137 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1138 = and(_T_1136, _T_1137)
node _T_1139 = and(_T_1135, _T_1138)
when _T_1139 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1140 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1141 = and(_T_1140, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1142 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1143 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1144 = and(_T_1142, _T_1143)
node _T_1145 = and(_T_1141, _T_1144)
when _T_1145 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1146 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1147 = bits(_T_1146, 0, 0)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1152 = and(io.in.d.valid, d_first_2)
node _T_1153 = and(_T_1152, UInt<1>(0h1))
node _T_1154 = and(_T_1153, d_release_ack_1)
when _T_1154 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1155 = and(io.in.d.ready, io.in.d.valid)
node _T_1156 = and(_T_1155, d_first_2)
node _T_1157 = and(_T_1156, UInt<1>(0h1))
node _T_1158 = and(_T_1157, d_release_ack_1)
when _T_1158 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1159 = and(io.in.d.valid, d_first_2)
node _T_1160 = and(_T_1159, UInt<1>(0h1))
node _T_1161 = and(_T_1160, d_release_ack_1)
when _T_1161 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1162 = dshr(inflight_1, io.in.d.bits.source)
node _T_1163 = bits(_T_1162, 0, 0)
node _T_1164 = or(_T_1163, same_cycle_resp_1)
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1168 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1169 = asUInt(reset)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
when _T_1170 :
node _T_1171 = eq(_T_1168, UInt<1>(0h0))
when _T_1171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1168, UInt<1>(0h1), "") : assert_109
else :
node _T_1172 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_110
node _T_1176 = and(io.in.d.valid, d_first_2)
node _T_1177 = and(_T_1176, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1178 = and(_T_1177, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1179 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = and(_T_1180, d_release_ack_1)
node _T_1182 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1183 = and(_T_1181, _T_1182)
when _T_1183 :
node _T_1184 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<28>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1185 = or(_T_1184, _WIRE_27.ready)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_111
node _T_1189 = orr(c_set_wo_ready)
when _T_1189 :
node _T_1190 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_51
node _T_1194 = orr(inflight_1)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
node _T_1196 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1197 = or(_T_1195, _T_1196)
node _T_1198 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1199 = or(_T_1197, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<28>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1203 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1204 = and(io.in.d.ready, io.in.d.valid)
node _T_1205 = or(_T_1203, _T_1204)
when _T_1205 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_25( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_43 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_43( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LSU :
input clock : Clock
input reset : Reset
output io : { ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}, core : { exe : { flip req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}}[1], flip dis_uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[3], dis_ldq_idx : UInt<5>[3], dis_stq_idx : UInt<5>[3], ldq_full : UInt<1>[3], stq_full : UInt<1>[3], flip fp_stdata : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, flip commit : { valids : UInt<1>[3], arch_valids : UInt<1>[3], uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[3], rbk_valids : UInt<1>[3], rollback : UInt<1>, debug_wdata : UInt<64>[3]}, flip commit_load_at_rob_head : UInt<1>, clr_bsy : { valid : UInt<1>, bits : UInt<7>}[2], clr_unsafe : { valid : UInt<1>, bits : UInt<7>}[1], flip fence_dmem : UInt<1>, spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], ld_miss : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip exception : UInt<1>, fencei_rdy : UInt<1>, lxcpt : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<40>}}, flip tsc_reg : UInt, perf : { acquire : UInt<1>, release : UInt<1>, tlbMiss : UInt<1>}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1]}, s1_kill : UInt<1>[1], flip resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1], flip nack : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, exception : UInt<1>, rob_pnr_idx : UInt<7>, rob_head_idx : UInt<7>, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, force_order : UInt<1>, flip ordered : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>}}, flip hellacache : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}}
invalidate io.hellacache.clock_enabled
invalidate io.hellacache.keep_clock_enabled
invalidate io.hellacache.perf.storeBufferEmptyAfterStore
invalidate io.hellacache.perf.storeBufferEmptyAfterLoad
invalidate io.hellacache.perf.canAcceptLoadThenLoad
invalidate io.hellacache.perf.canAcceptStoreThenRMW
invalidate io.hellacache.perf.canAcceptStoreThenLoad
invalidate io.hellacache.perf.blocked
invalidate io.hellacache.perf.tlbMiss
invalidate io.hellacache.perf.grant
invalidate io.hellacache.perf.release
invalidate io.hellacache.perf.acquire
invalidate io.hellacache.store_pending
invalidate io.hellacache.ordered
invalidate io.hellacache.s2_gpa_is_pte
invalidate io.hellacache.s2_gpa
invalidate io.hellacache.s2_xcpt.ae.st
invalidate io.hellacache.s2_xcpt.ae.ld
invalidate io.hellacache.s2_xcpt.gf.st
invalidate io.hellacache.s2_xcpt.gf.ld
invalidate io.hellacache.s2_xcpt.pf.st
invalidate io.hellacache.s2_xcpt.pf.ld
invalidate io.hellacache.s2_xcpt.ma.st
invalidate io.hellacache.s2_xcpt.ma.ld
invalidate io.hellacache.replay_next
invalidate io.hellacache.resp.bits.store_data
invalidate io.hellacache.resp.bits.data_raw
invalidate io.hellacache.resp.bits.data_word_bypass
invalidate io.hellacache.resp.bits.has_data
invalidate io.hellacache.resp.bits.replay
invalidate io.hellacache.resp.bits.mask
invalidate io.hellacache.resp.bits.data
invalidate io.hellacache.resp.bits.dv
invalidate io.hellacache.resp.bits.dprv
invalidate io.hellacache.resp.bits.signed
invalidate io.hellacache.resp.bits.size
invalidate io.hellacache.resp.bits.cmd
invalidate io.hellacache.resp.bits.tag
invalidate io.hellacache.resp.bits.addr
invalidate io.hellacache.resp.valid
invalidate io.hellacache.s2_paddr
invalidate io.hellacache.s2_uncached
invalidate io.hellacache.s2_kill
invalidate io.hellacache.s2_nack_cause_raw
invalidate io.hellacache.s2_nack
invalidate io.hellacache.s1_data.mask
invalidate io.hellacache.s1_data.data
invalidate io.hellacache.s1_kill
invalidate io.hellacache.req.bits.mask
invalidate io.hellacache.req.bits.data
invalidate io.hellacache.req.bits.no_xcpt
invalidate io.hellacache.req.bits.no_alloc
invalidate io.hellacache.req.bits.no_resp
invalidate io.hellacache.req.bits.phys
invalidate io.hellacache.req.bits.dv
invalidate io.hellacache.req.bits.dprv
invalidate io.hellacache.req.bits.signed
invalidate io.hellacache.req.bits.size
invalidate io.hellacache.req.bits.cmd
invalidate io.hellacache.req.bits.tag
invalidate io.hellacache.req.bits.addr
invalidate io.hellacache.req.valid
invalidate io.hellacache.req.ready
reg ldq : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[24], clock
reg stq : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}[24], clock
reg ldq_head : UInt<5>, clock
reg ldq_tail : UInt<5>, clock
reg stq_head : UInt<5>, clock
reg stq_tail : UInt<5>, clock
reg stq_commit_head : UInt<5>, clock
reg stq_execute_head : UInt<5>, clock
node _T = or(io.core.brupdate.b2.mispredict, stq[stq_execute_head].valid)
node _T_1 = eq(stq_head, stq_execute_head)
node _T_2 = or(_T, _T_1)
node _T_3 = eq(stq_tail, stq_execute_head)
node _T_4 = or(_T_2, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed: stq_execute_head got off track.\n at lsu.scala:222 assert (io.core.brupdate.b2.mispredict ||\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
regreset hella_state : UInt<3>, clock, reset, UInt<3>(0h0)
reg hella_req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
reg hella_data : { data : UInt<64>, mask : UInt<8>}, clock
reg hella_paddr : UInt<32>, clock
reg hella_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, clock
inst dtlb of NBDTLB
connect dtlb.clock, clock
connect dtlb.reset, reset
connect dtlb.io.ptw.customCSRs, io.ptw.customCSRs
connect dtlb.io.ptw.pmp[0], io.ptw.pmp[0]
connect dtlb.io.ptw.pmp[1], io.ptw.pmp[1]
connect dtlb.io.ptw.pmp[2], io.ptw.pmp[2]
connect dtlb.io.ptw.pmp[3], io.ptw.pmp[3]
connect dtlb.io.ptw.pmp[4], io.ptw.pmp[4]
connect dtlb.io.ptw.pmp[5], io.ptw.pmp[5]
connect dtlb.io.ptw.pmp[6], io.ptw.pmp[6]
connect dtlb.io.ptw.pmp[7], io.ptw.pmp[7]
connect dtlb.io.ptw.gstatus, io.ptw.gstatus
connect dtlb.io.ptw.hstatus, io.ptw.hstatus
connect dtlb.io.ptw.status, io.ptw.status
connect dtlb.io.ptw.vsatp, io.ptw.vsatp
connect dtlb.io.ptw.hgatp, io.ptw.hgatp
connect dtlb.io.ptw.ptbr, io.ptw.ptbr
connect dtlb.io.ptw.resp, io.ptw.resp
connect io.ptw.req.bits, dtlb.io.ptw.req.bits
connect io.ptw.req.valid, dtlb.io.ptw.req.valid
connect dtlb.io.ptw.req.ready, io.ptw.req.ready
node _io_core_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid)
connect io.core.perf.tlbMiss, _io_core_perf_tlbMiss_T
connect io.core.perf.acquire, io.dmem.perf.acquire
connect io.core.perf.release, io.dmem.perf.release
wire clear_store : UInt<1>
connect clear_store, UInt<1>(0h0)
regreset live_store_mask : UInt<24>, clock, reset, UInt<24>(0h0)
node _next_live_store_mask_T = dshl(UInt<1>(0h1), stq_head)
node _next_live_store_mask_T_1 = not(_next_live_store_mask_T)
node _next_live_store_mask_T_2 = and(live_store_mask, _next_live_store_mask_T_1)
node next_live_store_mask = mux(clear_store, _next_live_store_mask_T_2, live_store_mask)
when clear_store :
node _ldq_0_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_0_bits_st_dep_mask_T_1 = not(_ldq_0_bits_st_dep_mask_T)
node _ldq_0_bits_st_dep_mask_T_2 = and(ldq[0].bits.st_dep_mask, _ldq_0_bits_st_dep_mask_T_1)
connect ldq[0].bits.st_dep_mask, _ldq_0_bits_st_dep_mask_T_2
when clear_store :
node _ldq_1_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_1_bits_st_dep_mask_T_1 = not(_ldq_1_bits_st_dep_mask_T)
node _ldq_1_bits_st_dep_mask_T_2 = and(ldq[1].bits.st_dep_mask, _ldq_1_bits_st_dep_mask_T_1)
connect ldq[1].bits.st_dep_mask, _ldq_1_bits_st_dep_mask_T_2
when clear_store :
node _ldq_2_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_2_bits_st_dep_mask_T_1 = not(_ldq_2_bits_st_dep_mask_T)
node _ldq_2_bits_st_dep_mask_T_2 = and(ldq[2].bits.st_dep_mask, _ldq_2_bits_st_dep_mask_T_1)
connect ldq[2].bits.st_dep_mask, _ldq_2_bits_st_dep_mask_T_2
when clear_store :
node _ldq_3_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_3_bits_st_dep_mask_T_1 = not(_ldq_3_bits_st_dep_mask_T)
node _ldq_3_bits_st_dep_mask_T_2 = and(ldq[3].bits.st_dep_mask, _ldq_3_bits_st_dep_mask_T_1)
connect ldq[3].bits.st_dep_mask, _ldq_3_bits_st_dep_mask_T_2
when clear_store :
node _ldq_4_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_4_bits_st_dep_mask_T_1 = not(_ldq_4_bits_st_dep_mask_T)
node _ldq_4_bits_st_dep_mask_T_2 = and(ldq[4].bits.st_dep_mask, _ldq_4_bits_st_dep_mask_T_1)
connect ldq[4].bits.st_dep_mask, _ldq_4_bits_st_dep_mask_T_2
when clear_store :
node _ldq_5_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_5_bits_st_dep_mask_T_1 = not(_ldq_5_bits_st_dep_mask_T)
node _ldq_5_bits_st_dep_mask_T_2 = and(ldq[5].bits.st_dep_mask, _ldq_5_bits_st_dep_mask_T_1)
connect ldq[5].bits.st_dep_mask, _ldq_5_bits_st_dep_mask_T_2
when clear_store :
node _ldq_6_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_6_bits_st_dep_mask_T_1 = not(_ldq_6_bits_st_dep_mask_T)
node _ldq_6_bits_st_dep_mask_T_2 = and(ldq[6].bits.st_dep_mask, _ldq_6_bits_st_dep_mask_T_1)
connect ldq[6].bits.st_dep_mask, _ldq_6_bits_st_dep_mask_T_2
when clear_store :
node _ldq_7_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_7_bits_st_dep_mask_T_1 = not(_ldq_7_bits_st_dep_mask_T)
node _ldq_7_bits_st_dep_mask_T_2 = and(ldq[7].bits.st_dep_mask, _ldq_7_bits_st_dep_mask_T_1)
connect ldq[7].bits.st_dep_mask, _ldq_7_bits_st_dep_mask_T_2
when clear_store :
node _ldq_8_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_8_bits_st_dep_mask_T_1 = not(_ldq_8_bits_st_dep_mask_T)
node _ldq_8_bits_st_dep_mask_T_2 = and(ldq[8].bits.st_dep_mask, _ldq_8_bits_st_dep_mask_T_1)
connect ldq[8].bits.st_dep_mask, _ldq_8_bits_st_dep_mask_T_2
when clear_store :
node _ldq_9_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_9_bits_st_dep_mask_T_1 = not(_ldq_9_bits_st_dep_mask_T)
node _ldq_9_bits_st_dep_mask_T_2 = and(ldq[9].bits.st_dep_mask, _ldq_9_bits_st_dep_mask_T_1)
connect ldq[9].bits.st_dep_mask, _ldq_9_bits_st_dep_mask_T_2
when clear_store :
node _ldq_10_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_10_bits_st_dep_mask_T_1 = not(_ldq_10_bits_st_dep_mask_T)
node _ldq_10_bits_st_dep_mask_T_2 = and(ldq[10].bits.st_dep_mask, _ldq_10_bits_st_dep_mask_T_1)
connect ldq[10].bits.st_dep_mask, _ldq_10_bits_st_dep_mask_T_2
when clear_store :
node _ldq_11_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_11_bits_st_dep_mask_T_1 = not(_ldq_11_bits_st_dep_mask_T)
node _ldq_11_bits_st_dep_mask_T_2 = and(ldq[11].bits.st_dep_mask, _ldq_11_bits_st_dep_mask_T_1)
connect ldq[11].bits.st_dep_mask, _ldq_11_bits_st_dep_mask_T_2
when clear_store :
node _ldq_12_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_12_bits_st_dep_mask_T_1 = not(_ldq_12_bits_st_dep_mask_T)
node _ldq_12_bits_st_dep_mask_T_2 = and(ldq[12].bits.st_dep_mask, _ldq_12_bits_st_dep_mask_T_1)
connect ldq[12].bits.st_dep_mask, _ldq_12_bits_st_dep_mask_T_2
when clear_store :
node _ldq_13_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_13_bits_st_dep_mask_T_1 = not(_ldq_13_bits_st_dep_mask_T)
node _ldq_13_bits_st_dep_mask_T_2 = and(ldq[13].bits.st_dep_mask, _ldq_13_bits_st_dep_mask_T_1)
connect ldq[13].bits.st_dep_mask, _ldq_13_bits_st_dep_mask_T_2
when clear_store :
node _ldq_14_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_14_bits_st_dep_mask_T_1 = not(_ldq_14_bits_st_dep_mask_T)
node _ldq_14_bits_st_dep_mask_T_2 = and(ldq[14].bits.st_dep_mask, _ldq_14_bits_st_dep_mask_T_1)
connect ldq[14].bits.st_dep_mask, _ldq_14_bits_st_dep_mask_T_2
when clear_store :
node _ldq_15_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_15_bits_st_dep_mask_T_1 = not(_ldq_15_bits_st_dep_mask_T)
node _ldq_15_bits_st_dep_mask_T_2 = and(ldq[15].bits.st_dep_mask, _ldq_15_bits_st_dep_mask_T_1)
connect ldq[15].bits.st_dep_mask, _ldq_15_bits_st_dep_mask_T_2
when clear_store :
node _ldq_16_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_16_bits_st_dep_mask_T_1 = not(_ldq_16_bits_st_dep_mask_T)
node _ldq_16_bits_st_dep_mask_T_2 = and(ldq[16].bits.st_dep_mask, _ldq_16_bits_st_dep_mask_T_1)
connect ldq[16].bits.st_dep_mask, _ldq_16_bits_st_dep_mask_T_2
when clear_store :
node _ldq_17_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_17_bits_st_dep_mask_T_1 = not(_ldq_17_bits_st_dep_mask_T)
node _ldq_17_bits_st_dep_mask_T_2 = and(ldq[17].bits.st_dep_mask, _ldq_17_bits_st_dep_mask_T_1)
connect ldq[17].bits.st_dep_mask, _ldq_17_bits_st_dep_mask_T_2
when clear_store :
node _ldq_18_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_18_bits_st_dep_mask_T_1 = not(_ldq_18_bits_st_dep_mask_T)
node _ldq_18_bits_st_dep_mask_T_2 = and(ldq[18].bits.st_dep_mask, _ldq_18_bits_st_dep_mask_T_1)
connect ldq[18].bits.st_dep_mask, _ldq_18_bits_st_dep_mask_T_2
when clear_store :
node _ldq_19_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_19_bits_st_dep_mask_T_1 = not(_ldq_19_bits_st_dep_mask_T)
node _ldq_19_bits_st_dep_mask_T_2 = and(ldq[19].bits.st_dep_mask, _ldq_19_bits_st_dep_mask_T_1)
connect ldq[19].bits.st_dep_mask, _ldq_19_bits_st_dep_mask_T_2
when clear_store :
node _ldq_20_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_20_bits_st_dep_mask_T_1 = not(_ldq_20_bits_st_dep_mask_T)
node _ldq_20_bits_st_dep_mask_T_2 = and(ldq[20].bits.st_dep_mask, _ldq_20_bits_st_dep_mask_T_1)
connect ldq[20].bits.st_dep_mask, _ldq_20_bits_st_dep_mask_T_2
when clear_store :
node _ldq_21_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_21_bits_st_dep_mask_T_1 = not(_ldq_21_bits_st_dep_mask_T)
node _ldq_21_bits_st_dep_mask_T_2 = and(ldq[21].bits.st_dep_mask, _ldq_21_bits_st_dep_mask_T_1)
connect ldq[21].bits.st_dep_mask, _ldq_21_bits_st_dep_mask_T_2
when clear_store :
node _ldq_22_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_22_bits_st_dep_mask_T_1 = not(_ldq_22_bits_st_dep_mask_T)
node _ldq_22_bits_st_dep_mask_T_2 = and(ldq[22].bits.st_dep_mask, _ldq_22_bits_st_dep_mask_T_1)
connect ldq[22].bits.st_dep_mask, _ldq_22_bits_st_dep_mask_T_2
when clear_store :
node _ldq_23_bits_st_dep_mask_T = dshl(UInt<1>(0h1), stq_head)
node _ldq_23_bits_st_dep_mask_T_1 = not(_ldq_23_bits_st_dep_mask_T)
node _ldq_23_bits_st_dep_mask_T_2 = and(ldq[23].bits.st_dep_mask, _ldq_23_bits_st_dep_mask_T_1)
connect ldq[23].bits.st_dep_mask, _ldq_23_bits_st_dep_mask_T_2
node _stq_nonempty_T = or(stq[0].valid, stq[1].valid)
node _stq_nonempty_T_1 = or(_stq_nonempty_T, stq[2].valid)
node _stq_nonempty_T_2 = or(_stq_nonempty_T_1, stq[3].valid)
node _stq_nonempty_T_3 = or(_stq_nonempty_T_2, stq[4].valid)
node _stq_nonempty_T_4 = or(_stq_nonempty_T_3, stq[5].valid)
node _stq_nonempty_T_5 = or(_stq_nonempty_T_4, stq[6].valid)
node _stq_nonempty_T_6 = or(_stq_nonempty_T_5, stq[7].valid)
node _stq_nonempty_T_7 = or(_stq_nonempty_T_6, stq[8].valid)
node _stq_nonempty_T_8 = or(_stq_nonempty_T_7, stq[9].valid)
node _stq_nonempty_T_9 = or(_stq_nonempty_T_8, stq[10].valid)
node _stq_nonempty_T_10 = or(_stq_nonempty_T_9, stq[11].valid)
node _stq_nonempty_T_11 = or(_stq_nonempty_T_10, stq[12].valid)
node _stq_nonempty_T_12 = or(_stq_nonempty_T_11, stq[13].valid)
node _stq_nonempty_T_13 = or(_stq_nonempty_T_12, stq[14].valid)
node _stq_nonempty_T_14 = or(_stq_nonempty_T_13, stq[15].valid)
node _stq_nonempty_T_15 = or(_stq_nonempty_T_14, stq[16].valid)
node _stq_nonempty_T_16 = or(_stq_nonempty_T_15, stq[17].valid)
node _stq_nonempty_T_17 = or(_stq_nonempty_T_16, stq[18].valid)
node _stq_nonempty_T_18 = or(_stq_nonempty_T_17, stq[19].valid)
node _stq_nonempty_T_19 = or(_stq_nonempty_T_18, stq[20].valid)
node _stq_nonempty_T_20 = or(_stq_nonempty_T_19, stq[21].valid)
node _stq_nonempty_T_21 = or(_stq_nonempty_T_20, stq[22].valid)
node _stq_nonempty_T_22 = or(_stq_nonempty_T_21, stq[23].valid)
node stq_nonempty = neq(_stq_nonempty_T_22, UInt<1>(0h0))
node wrap = eq(ldq_tail, UInt<5>(0h17))
node _T_8 = add(ldq_tail, UInt<1>(0h1))
node _T_9 = tail(_T_8, 1)
node _T_10 = mux(wrap, UInt<1>(0h0), _T_9)
node _T_11 = eq(_T_10, ldq_head)
connect io.core.ldq_full[0], _T_11
connect io.core.dis_ldq_idx[0], ldq_tail
node wrap_1 = eq(stq_tail, UInt<5>(0h17))
node _T_12 = add(stq_tail, UInt<1>(0h1))
node _T_13 = tail(_T_12, 1)
node _T_14 = mux(wrap_1, UInt<1>(0h0), _T_13)
node _T_15 = eq(_T_14, stq_head)
connect io.core.stq_full[0], _T_15
connect io.core.dis_stq_idx[0], stq_tail
node _dis_ld_val_T = and(io.core.dis_uops[0].valid, io.core.dis_uops[0].bits.uses_ldq)
node _dis_ld_val_T_1 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0))
node dis_ld_val = and(_dis_ld_val_T, _dis_ld_val_T_1)
node _dis_st_val_T = and(io.core.dis_uops[0].valid, io.core.dis_uops[0].bits.uses_stq)
node _dis_st_val_T_1 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0))
node dis_st_val = and(_dis_st_val_T, _dis_st_val_T_1)
when dis_ld_val :
connect ldq[ldq_tail].valid, UInt<1>(0h1)
connect ldq[ldq_tail].bits.uop, io.core.dis_uops[0].bits
connect ldq[ldq_tail].bits.youngest_stq_idx, stq_tail
connect ldq[ldq_tail].bits.st_dep_mask, next_live_store_mask
connect ldq[ldq_tail].bits.addr.valid, UInt<1>(0h0)
connect ldq[ldq_tail].bits.executed, UInt<1>(0h0)
connect ldq[ldq_tail].bits.succeeded, UInt<1>(0h0)
connect ldq[ldq_tail].bits.order_fail, UInt<1>(0h0)
connect ldq[ldq_tail].bits.observed, UInt<1>(0h0)
connect ldq[ldq_tail].bits.forward_std_val, UInt<1>(0h0)
node _T_16 = eq(ldq_tail, io.core.dis_uops[0].bits.ldq_idx)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:316 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(ldq[ldq_tail].valid, UInt<1>(0h0))
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:317 assert (!ldq(ld_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_2
assert(clock, _T_20, UInt<1>(0h1), "") : assert_2
else :
when dis_st_val :
connect stq[stq_tail].valid, UInt<1>(0h1)
connect stq[stq_tail].bits.uop, io.core.dis_uops[0].bits
connect stq[stq_tail].bits.addr.valid, UInt<1>(0h0)
connect stq[stq_tail].bits.data.valid, UInt<1>(0h0)
connect stq[stq_tail].bits.committed, UInt<1>(0h0)
connect stq[stq_tail].bits.succeeded, UInt<1>(0h0)
node _T_24 = eq(stq_tail, io.core.dis_uops[0].bits.stq_idx)
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
node _T_27 = eq(_T_24, UInt<1>(0h0))
when _T_27 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:328 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_3
assert(clock, _T_24, UInt<1>(0h1), "") : assert_3
node _T_28 = eq(stq[stq_tail].valid, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:329 assert (!stq(st_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_4
assert(clock, _T_28, UInt<1>(0h1), "") : assert_4
node wrap_2 = eq(ldq_tail, UInt<5>(0h17))
node _T_32 = add(ldq_tail, UInt<1>(0h1))
node _T_33 = tail(_T_32, 1)
node _T_34 = mux(wrap_2, UInt<1>(0h0), _T_33)
node _T_35 = mux(dis_ld_val, _T_34, ldq_tail)
node _T_36 = dshl(UInt<1>(0h1), stq_tail)
node _T_37 = or(next_live_store_mask, _T_36)
node _T_38 = mux(dis_st_val, _T_37, next_live_store_mask)
node wrap_3 = eq(stq_tail, UInt<5>(0h17))
node _T_39 = add(stq_tail, UInt<1>(0h1))
node _T_40 = tail(_T_39, 1)
node _T_41 = mux(wrap_3, UInt<1>(0h0), _T_40)
node _T_42 = mux(dis_st_val, _T_41, stq_tail)
node _T_43 = and(dis_ld_val, dis_st_val)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
node _T_47 = eq(_T_44, UInt<1>(0h0))
when _T_47 :
printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:340 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_5
assert(clock, _T_44, UInt<1>(0h1), "") : assert_5
node wrap_4 = eq(_T_35, UInt<5>(0h17))
node _T_48 = add(_T_35, UInt<1>(0h1))
node _T_49 = tail(_T_48, 1)
node _T_50 = mux(wrap_4, UInt<1>(0h0), _T_49)
node _T_51 = eq(_T_50, ldq_head)
connect io.core.ldq_full[1], _T_51
connect io.core.dis_ldq_idx[1], _T_35
node wrap_5 = eq(_T_42, UInt<5>(0h17))
node _T_52 = add(_T_42, UInt<1>(0h1))
node _T_53 = tail(_T_52, 1)
node _T_54 = mux(wrap_5, UInt<1>(0h0), _T_53)
node _T_55 = eq(_T_54, stq_head)
connect io.core.stq_full[1], _T_55
connect io.core.dis_stq_idx[1], _T_42
node _dis_ld_val_T_2 = and(io.core.dis_uops[1].valid, io.core.dis_uops[1].bits.uses_ldq)
node _dis_ld_val_T_3 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0))
node dis_ld_val_1 = and(_dis_ld_val_T_2, _dis_ld_val_T_3)
node _dis_st_val_T_2 = and(io.core.dis_uops[1].valid, io.core.dis_uops[1].bits.uses_stq)
node _dis_st_val_T_3 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0))
node dis_st_val_1 = and(_dis_st_val_T_2, _dis_st_val_T_3)
when dis_ld_val_1 :
connect ldq[_T_35].valid, UInt<1>(0h1)
connect ldq[_T_35].bits.uop, io.core.dis_uops[1].bits
connect ldq[_T_35].bits.youngest_stq_idx, _T_42
connect ldq[_T_35].bits.st_dep_mask, _T_38
connect ldq[_T_35].bits.addr.valid, UInt<1>(0h0)
connect ldq[_T_35].bits.executed, UInt<1>(0h0)
connect ldq[_T_35].bits.succeeded, UInt<1>(0h0)
connect ldq[_T_35].bits.order_fail, UInt<1>(0h0)
connect ldq[_T_35].bits.observed, UInt<1>(0h0)
connect ldq[_T_35].bits.forward_std_val, UInt<1>(0h0)
node _T_56 = eq(_T_35, io.core.dis_uops[1].bits.ldq_idx)
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:316 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf_6
assert(clock, _T_56, UInt<1>(0h1), "") : assert_6
node _T_60 = eq(ldq[_T_35].valid, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:317 assert (!ldq(ld_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_7
assert(clock, _T_60, UInt<1>(0h1), "") : assert_7
else :
when dis_st_val_1 :
connect stq[_T_42].valid, UInt<1>(0h1)
connect stq[_T_42].bits.uop, io.core.dis_uops[1].bits
connect stq[_T_42].bits.addr.valid, UInt<1>(0h0)
connect stq[_T_42].bits.data.valid, UInt<1>(0h0)
connect stq[_T_42].bits.committed, UInt<1>(0h0)
connect stq[_T_42].bits.succeeded, UInt<1>(0h0)
node _T_64 = eq(_T_42, io.core.dis_uops[1].bits.stq_idx)
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:328 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_8
assert(clock, _T_64, UInt<1>(0h1), "") : assert_8
node _T_68 = eq(stq[_T_42].valid, UInt<1>(0h0))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:329 assert (!stq(st_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_9
assert(clock, _T_68, UInt<1>(0h1), "") : assert_9
node wrap_6 = eq(_T_35, UInt<5>(0h17))
node _T_72 = add(_T_35, UInt<1>(0h1))
node _T_73 = tail(_T_72, 1)
node _T_74 = mux(wrap_6, UInt<1>(0h0), _T_73)
node _T_75 = mux(dis_ld_val_1, _T_74, _T_35)
node _T_76 = dshl(UInt<1>(0h1), _T_42)
node _T_77 = or(_T_38, _T_76)
node _T_78 = mux(dis_st_val_1, _T_77, _T_38)
node wrap_7 = eq(_T_42, UInt<5>(0h17))
node _T_79 = add(_T_42, UInt<1>(0h1))
node _T_80 = tail(_T_79, 1)
node _T_81 = mux(wrap_7, UInt<1>(0h0), _T_80)
node _T_82 = mux(dis_st_val_1, _T_81, _T_42)
node _T_83 = and(dis_ld_val_1, dis_st_val_1)
node _T_84 = eq(_T_83, UInt<1>(0h0))
node _T_85 = asUInt(reset)
node _T_86 = eq(_T_85, UInt<1>(0h0))
when _T_86 :
node _T_87 = eq(_T_84, UInt<1>(0h0))
when _T_87 :
printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:340 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_10
assert(clock, _T_84, UInt<1>(0h1), "") : assert_10
node wrap_8 = eq(_T_75, UInt<5>(0h17))
node _T_88 = add(_T_75, UInt<1>(0h1))
node _T_89 = tail(_T_88, 1)
node _T_90 = mux(wrap_8, UInt<1>(0h0), _T_89)
node _T_91 = eq(_T_90, ldq_head)
connect io.core.ldq_full[2], _T_91
connect io.core.dis_ldq_idx[2], _T_75
node wrap_9 = eq(_T_82, UInt<5>(0h17))
node _T_92 = add(_T_82, UInt<1>(0h1))
node _T_93 = tail(_T_92, 1)
node _T_94 = mux(wrap_9, UInt<1>(0h0), _T_93)
node _T_95 = eq(_T_94, stq_head)
connect io.core.stq_full[2], _T_95
connect io.core.dis_stq_idx[2], _T_82
node _dis_ld_val_T_4 = and(io.core.dis_uops[2].valid, io.core.dis_uops[2].bits.uses_ldq)
node _dis_ld_val_T_5 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0))
node dis_ld_val_2 = and(_dis_ld_val_T_4, _dis_ld_val_T_5)
node _dis_st_val_T_4 = and(io.core.dis_uops[2].valid, io.core.dis_uops[2].bits.uses_stq)
node _dis_st_val_T_5 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0))
node dis_st_val_2 = and(_dis_st_val_T_4, _dis_st_val_T_5)
when dis_ld_val_2 :
connect ldq[_T_75].valid, UInt<1>(0h1)
connect ldq[_T_75].bits.uop, io.core.dis_uops[2].bits
connect ldq[_T_75].bits.youngest_stq_idx, _T_82
connect ldq[_T_75].bits.st_dep_mask, _T_78
connect ldq[_T_75].bits.addr.valid, UInt<1>(0h0)
connect ldq[_T_75].bits.executed, UInt<1>(0h0)
connect ldq[_T_75].bits.succeeded, UInt<1>(0h0)
connect ldq[_T_75].bits.order_fail, UInt<1>(0h0)
connect ldq[_T_75].bits.observed, UInt<1>(0h0)
connect ldq[_T_75].bits.forward_std_val, UInt<1>(0h0)
node _T_96 = eq(_T_75, io.core.dis_uops[2].bits.ldq_idx)
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:316 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf_11
assert(clock, _T_96, UInt<1>(0h1), "") : assert_11
node _T_100 = eq(ldq[_T_75].valid, UInt<1>(0h0))
node _T_101 = asUInt(reset)
node _T_102 = eq(_T_101, UInt<1>(0h0))
when _T_102 :
node _T_103 = eq(_T_100, UInt<1>(0h0))
when _T_103 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:317 assert (!ldq(ld_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_12
assert(clock, _T_100, UInt<1>(0h1), "") : assert_12
else :
when dis_st_val_2 :
connect stq[_T_82].valid, UInt<1>(0h1)
connect stq[_T_82].bits.uop, io.core.dis_uops[2].bits
connect stq[_T_82].bits.addr.valid, UInt<1>(0h0)
connect stq[_T_82].bits.data.valid, UInt<1>(0h0)
connect stq[_T_82].bits.committed, UInt<1>(0h0)
connect stq[_T_82].bits.succeeded, UInt<1>(0h0)
node _T_104 = eq(_T_82, io.core.dis_uops[2].bits.stq_idx)
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:328 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(stq[_T_82].valid, UInt<1>(0h0))
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:329 assert (!stq(st_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_14
assert(clock, _T_108, UInt<1>(0h1), "") : assert_14
node wrap_10 = eq(_T_75, UInt<5>(0h17))
node _T_112 = add(_T_75, UInt<1>(0h1))
node _T_113 = tail(_T_112, 1)
node _T_114 = mux(wrap_10, UInt<1>(0h0), _T_113)
node _T_115 = mux(dis_ld_val_2, _T_114, _T_75)
node _T_116 = dshl(UInt<1>(0h1), _T_82)
node _T_117 = or(_T_78, _T_116)
node _T_118 = mux(dis_st_val_2, _T_117, _T_78)
node wrap_11 = eq(_T_82, UInt<5>(0h17))
node _T_119 = add(_T_82, UInt<1>(0h1))
node _T_120 = tail(_T_119, 1)
node _T_121 = mux(wrap_11, UInt<1>(0h0), _T_120)
node _T_122 = mux(dis_st_val_2, _T_121, _T_82)
node _T_123 = and(dis_ld_val_2, dis_st_val_2)
node _T_124 = eq(_T_123, UInt<1>(0h0))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:340 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_15
assert(clock, _T_124, UInt<1>(0h1), "") : assert_15
connect ldq_tail, _T_115
connect stq_tail, _T_122
connect io.dmem.force_order, io.core.fence_dmem
node _io_core_fencei_rdy_T = eq(stq_nonempty, UInt<1>(0h0))
node _io_core_fencei_rdy_T_1 = and(_io_core_fencei_rdy_T, io.dmem.ordered)
connect io.core.fencei_rdy, _io_core_fencei_rdy_T_1
wire mem_xcpt_valid : UInt<1>
wire mem_xcpt_cause : UInt
wire mem_xcpt_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
wire mem_xcpt_vaddr : UInt
wire will_fire_load_incoming : UInt<1>[1]
wire will_fire_stad_incoming : UInt<1>[1]
wire will_fire_sta_incoming : UInt<1>[1]
wire will_fire_std_incoming : UInt<1>[1]
wire will_fire_sfence : UInt<1>[1]
wire will_fire_hella_incoming : UInt<1>[1]
wire will_fire_hella_wakeup : UInt<1>[1]
wire will_fire_release : UInt<1>[1]
wire will_fire_load_retry : UInt<1>[1]
wire will_fire_sta_retry : UInt<1>[1]
wire will_fire_store_commit : UInt<1>[1]
wire will_fire_load_wakeup : UInt<1>[1]
wire _exe_req_WIRE : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}[1]
connect _exe_req_WIRE[0], io.core.exe[0].req
wire exe_req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}[1]
connect exe_req[0].bits.sfence.bits.hg, _exe_req_WIRE[0].bits.sfence.bits.hg
connect exe_req[0].bits.sfence.bits.hv, _exe_req_WIRE[0].bits.sfence.bits.hv
connect exe_req[0].bits.sfence.bits.asid, _exe_req_WIRE[0].bits.sfence.bits.asid
connect exe_req[0].bits.sfence.bits.addr, _exe_req_WIRE[0].bits.sfence.bits.addr
connect exe_req[0].bits.sfence.bits.rs2, _exe_req_WIRE[0].bits.sfence.bits.rs2
connect exe_req[0].bits.sfence.bits.rs1, _exe_req_WIRE[0].bits.sfence.bits.rs1
connect exe_req[0].bits.sfence.valid, _exe_req_WIRE[0].bits.sfence.valid
connect exe_req[0].bits.mxcpt.bits, _exe_req_WIRE[0].bits.mxcpt.bits
connect exe_req[0].bits.mxcpt.valid, _exe_req_WIRE[0].bits.mxcpt.valid
connect exe_req[0].bits.addr, _exe_req_WIRE[0].bits.addr
connect exe_req[0].bits.fflags.bits.flags, _exe_req_WIRE[0].bits.fflags.bits.flags
connect exe_req[0].bits.fflags.bits.uop.debug_tsrc, _exe_req_WIRE[0].bits.fflags.bits.uop.debug_tsrc
connect exe_req[0].bits.fflags.bits.uop.debug_fsrc, _exe_req_WIRE[0].bits.fflags.bits.uop.debug_fsrc
connect exe_req[0].bits.fflags.bits.uop.bp_xcpt_if, _exe_req_WIRE[0].bits.fflags.bits.uop.bp_xcpt_if
connect exe_req[0].bits.fflags.bits.uop.bp_debug_if, _exe_req_WIRE[0].bits.fflags.bits.uop.bp_debug_if
connect exe_req[0].bits.fflags.bits.uop.xcpt_ma_if, _exe_req_WIRE[0].bits.fflags.bits.uop.xcpt_ma_if
connect exe_req[0].bits.fflags.bits.uop.xcpt_ae_if, _exe_req_WIRE[0].bits.fflags.bits.uop.xcpt_ae_if
connect exe_req[0].bits.fflags.bits.uop.xcpt_pf_if, _exe_req_WIRE[0].bits.fflags.bits.uop.xcpt_pf_if
connect exe_req[0].bits.fflags.bits.uop.fp_single, _exe_req_WIRE[0].bits.fflags.bits.uop.fp_single
connect exe_req[0].bits.fflags.bits.uop.fp_val, _exe_req_WIRE[0].bits.fflags.bits.uop.fp_val
connect exe_req[0].bits.fflags.bits.uop.frs3_en, _exe_req_WIRE[0].bits.fflags.bits.uop.frs3_en
connect exe_req[0].bits.fflags.bits.uop.lrs2_rtype, _exe_req_WIRE[0].bits.fflags.bits.uop.lrs2_rtype
connect exe_req[0].bits.fflags.bits.uop.lrs1_rtype, _exe_req_WIRE[0].bits.fflags.bits.uop.lrs1_rtype
connect exe_req[0].bits.fflags.bits.uop.dst_rtype, _exe_req_WIRE[0].bits.fflags.bits.uop.dst_rtype
connect exe_req[0].bits.fflags.bits.uop.ldst_val, _exe_req_WIRE[0].bits.fflags.bits.uop.ldst_val
connect exe_req[0].bits.fflags.bits.uop.lrs3, _exe_req_WIRE[0].bits.fflags.bits.uop.lrs3
connect exe_req[0].bits.fflags.bits.uop.lrs2, _exe_req_WIRE[0].bits.fflags.bits.uop.lrs2
connect exe_req[0].bits.fflags.bits.uop.lrs1, _exe_req_WIRE[0].bits.fflags.bits.uop.lrs1
connect exe_req[0].bits.fflags.bits.uop.ldst, _exe_req_WIRE[0].bits.fflags.bits.uop.ldst
connect exe_req[0].bits.fflags.bits.uop.ldst_is_rs1, _exe_req_WIRE[0].bits.fflags.bits.uop.ldst_is_rs1
connect exe_req[0].bits.fflags.bits.uop.flush_on_commit, _exe_req_WIRE[0].bits.fflags.bits.uop.flush_on_commit
connect exe_req[0].bits.fflags.bits.uop.is_unique, _exe_req_WIRE[0].bits.fflags.bits.uop.is_unique
connect exe_req[0].bits.fflags.bits.uop.is_sys_pc2epc, _exe_req_WIRE[0].bits.fflags.bits.uop.is_sys_pc2epc
connect exe_req[0].bits.fflags.bits.uop.uses_stq, _exe_req_WIRE[0].bits.fflags.bits.uop.uses_stq
connect exe_req[0].bits.fflags.bits.uop.uses_ldq, _exe_req_WIRE[0].bits.fflags.bits.uop.uses_ldq
connect exe_req[0].bits.fflags.bits.uop.is_amo, _exe_req_WIRE[0].bits.fflags.bits.uop.is_amo
connect exe_req[0].bits.fflags.bits.uop.is_fencei, _exe_req_WIRE[0].bits.fflags.bits.uop.is_fencei
connect exe_req[0].bits.fflags.bits.uop.is_fence, _exe_req_WIRE[0].bits.fflags.bits.uop.is_fence
connect exe_req[0].bits.fflags.bits.uop.mem_signed, _exe_req_WIRE[0].bits.fflags.bits.uop.mem_signed
connect exe_req[0].bits.fflags.bits.uop.mem_size, _exe_req_WIRE[0].bits.fflags.bits.uop.mem_size
connect exe_req[0].bits.fflags.bits.uop.mem_cmd, _exe_req_WIRE[0].bits.fflags.bits.uop.mem_cmd
connect exe_req[0].bits.fflags.bits.uop.bypassable, _exe_req_WIRE[0].bits.fflags.bits.uop.bypassable
connect exe_req[0].bits.fflags.bits.uop.exc_cause, _exe_req_WIRE[0].bits.fflags.bits.uop.exc_cause
connect exe_req[0].bits.fflags.bits.uop.exception, _exe_req_WIRE[0].bits.fflags.bits.uop.exception
connect exe_req[0].bits.fflags.bits.uop.stale_pdst, _exe_req_WIRE[0].bits.fflags.bits.uop.stale_pdst
connect exe_req[0].bits.fflags.bits.uop.ppred_busy, _exe_req_WIRE[0].bits.fflags.bits.uop.ppred_busy
connect exe_req[0].bits.fflags.bits.uop.prs3_busy, _exe_req_WIRE[0].bits.fflags.bits.uop.prs3_busy
connect exe_req[0].bits.fflags.bits.uop.prs2_busy, _exe_req_WIRE[0].bits.fflags.bits.uop.prs2_busy
connect exe_req[0].bits.fflags.bits.uop.prs1_busy, _exe_req_WIRE[0].bits.fflags.bits.uop.prs1_busy
connect exe_req[0].bits.fflags.bits.uop.ppred, _exe_req_WIRE[0].bits.fflags.bits.uop.ppred
connect exe_req[0].bits.fflags.bits.uop.prs3, _exe_req_WIRE[0].bits.fflags.bits.uop.prs3
connect exe_req[0].bits.fflags.bits.uop.prs2, _exe_req_WIRE[0].bits.fflags.bits.uop.prs2
connect exe_req[0].bits.fflags.bits.uop.prs1, _exe_req_WIRE[0].bits.fflags.bits.uop.prs1
connect exe_req[0].bits.fflags.bits.uop.pdst, _exe_req_WIRE[0].bits.fflags.bits.uop.pdst
connect exe_req[0].bits.fflags.bits.uop.rxq_idx, _exe_req_WIRE[0].bits.fflags.bits.uop.rxq_idx
connect exe_req[0].bits.fflags.bits.uop.stq_idx, _exe_req_WIRE[0].bits.fflags.bits.uop.stq_idx
connect exe_req[0].bits.fflags.bits.uop.ldq_idx, _exe_req_WIRE[0].bits.fflags.bits.uop.ldq_idx
connect exe_req[0].bits.fflags.bits.uop.rob_idx, _exe_req_WIRE[0].bits.fflags.bits.uop.rob_idx
connect exe_req[0].bits.fflags.bits.uop.csr_addr, _exe_req_WIRE[0].bits.fflags.bits.uop.csr_addr
connect exe_req[0].bits.fflags.bits.uop.imm_packed, _exe_req_WIRE[0].bits.fflags.bits.uop.imm_packed
connect exe_req[0].bits.fflags.bits.uop.taken, _exe_req_WIRE[0].bits.fflags.bits.uop.taken
connect exe_req[0].bits.fflags.bits.uop.pc_lob, _exe_req_WIRE[0].bits.fflags.bits.uop.pc_lob
connect exe_req[0].bits.fflags.bits.uop.edge_inst, _exe_req_WIRE[0].bits.fflags.bits.uop.edge_inst
connect exe_req[0].bits.fflags.bits.uop.ftq_idx, _exe_req_WIRE[0].bits.fflags.bits.uop.ftq_idx
connect exe_req[0].bits.fflags.bits.uop.br_tag, _exe_req_WIRE[0].bits.fflags.bits.uop.br_tag
connect exe_req[0].bits.fflags.bits.uop.br_mask, _exe_req_WIRE[0].bits.fflags.bits.uop.br_mask
connect exe_req[0].bits.fflags.bits.uop.is_sfb, _exe_req_WIRE[0].bits.fflags.bits.uop.is_sfb
connect exe_req[0].bits.fflags.bits.uop.is_jal, _exe_req_WIRE[0].bits.fflags.bits.uop.is_jal
connect exe_req[0].bits.fflags.bits.uop.is_jalr, _exe_req_WIRE[0].bits.fflags.bits.uop.is_jalr
connect exe_req[0].bits.fflags.bits.uop.is_br, _exe_req_WIRE[0].bits.fflags.bits.uop.is_br
connect exe_req[0].bits.fflags.bits.uop.iw_p2_poisoned, _exe_req_WIRE[0].bits.fflags.bits.uop.iw_p2_poisoned
connect exe_req[0].bits.fflags.bits.uop.iw_p1_poisoned, _exe_req_WIRE[0].bits.fflags.bits.uop.iw_p1_poisoned
connect exe_req[0].bits.fflags.bits.uop.iw_state, _exe_req_WIRE[0].bits.fflags.bits.uop.iw_state
connect exe_req[0].bits.fflags.bits.uop.ctrl.is_std, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.is_std
connect exe_req[0].bits.fflags.bits.uop.ctrl.is_sta, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.is_sta
connect exe_req[0].bits.fflags.bits.uop.ctrl.is_load, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.is_load
connect exe_req[0].bits.fflags.bits.uop.ctrl.csr_cmd, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.csr_cmd
connect exe_req[0].bits.fflags.bits.uop.ctrl.fcn_dw, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.fcn_dw
connect exe_req[0].bits.fflags.bits.uop.ctrl.op_fcn, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.op_fcn
connect exe_req[0].bits.fflags.bits.uop.ctrl.imm_sel, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.imm_sel
connect exe_req[0].bits.fflags.bits.uop.ctrl.op2_sel, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.op2_sel
connect exe_req[0].bits.fflags.bits.uop.ctrl.op1_sel, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.op1_sel
connect exe_req[0].bits.fflags.bits.uop.ctrl.br_type, _exe_req_WIRE[0].bits.fflags.bits.uop.ctrl.br_type
connect exe_req[0].bits.fflags.bits.uop.fu_code, _exe_req_WIRE[0].bits.fflags.bits.uop.fu_code
connect exe_req[0].bits.fflags.bits.uop.iq_type, _exe_req_WIRE[0].bits.fflags.bits.uop.iq_type
connect exe_req[0].bits.fflags.bits.uop.debug_pc, _exe_req_WIRE[0].bits.fflags.bits.uop.debug_pc
connect exe_req[0].bits.fflags.bits.uop.is_rvc, _exe_req_WIRE[0].bits.fflags.bits.uop.is_rvc
connect exe_req[0].bits.fflags.bits.uop.debug_inst, _exe_req_WIRE[0].bits.fflags.bits.uop.debug_inst
connect exe_req[0].bits.fflags.bits.uop.inst, _exe_req_WIRE[0].bits.fflags.bits.uop.inst
connect exe_req[0].bits.fflags.bits.uop.uopc, _exe_req_WIRE[0].bits.fflags.bits.uop.uopc
connect exe_req[0].bits.fflags.valid, _exe_req_WIRE[0].bits.fflags.valid
connect exe_req[0].bits.data, _exe_req_WIRE[0].bits.data
connect exe_req[0].bits.predicated, _exe_req_WIRE[0].bits.predicated
connect exe_req[0].bits.uop.debug_tsrc, _exe_req_WIRE[0].bits.uop.debug_tsrc
connect exe_req[0].bits.uop.debug_fsrc, _exe_req_WIRE[0].bits.uop.debug_fsrc
connect exe_req[0].bits.uop.bp_xcpt_if, _exe_req_WIRE[0].bits.uop.bp_xcpt_if
connect exe_req[0].bits.uop.bp_debug_if, _exe_req_WIRE[0].bits.uop.bp_debug_if
connect exe_req[0].bits.uop.xcpt_ma_if, _exe_req_WIRE[0].bits.uop.xcpt_ma_if
connect exe_req[0].bits.uop.xcpt_ae_if, _exe_req_WIRE[0].bits.uop.xcpt_ae_if
connect exe_req[0].bits.uop.xcpt_pf_if, _exe_req_WIRE[0].bits.uop.xcpt_pf_if
connect exe_req[0].bits.uop.fp_single, _exe_req_WIRE[0].bits.uop.fp_single
connect exe_req[0].bits.uop.fp_val, _exe_req_WIRE[0].bits.uop.fp_val
connect exe_req[0].bits.uop.frs3_en, _exe_req_WIRE[0].bits.uop.frs3_en
connect exe_req[0].bits.uop.lrs2_rtype, _exe_req_WIRE[0].bits.uop.lrs2_rtype
connect exe_req[0].bits.uop.lrs1_rtype, _exe_req_WIRE[0].bits.uop.lrs1_rtype
connect exe_req[0].bits.uop.dst_rtype, _exe_req_WIRE[0].bits.uop.dst_rtype
connect exe_req[0].bits.uop.ldst_val, _exe_req_WIRE[0].bits.uop.ldst_val
connect exe_req[0].bits.uop.lrs3, _exe_req_WIRE[0].bits.uop.lrs3
connect exe_req[0].bits.uop.lrs2, _exe_req_WIRE[0].bits.uop.lrs2
connect exe_req[0].bits.uop.lrs1, _exe_req_WIRE[0].bits.uop.lrs1
connect exe_req[0].bits.uop.ldst, _exe_req_WIRE[0].bits.uop.ldst
connect exe_req[0].bits.uop.ldst_is_rs1, _exe_req_WIRE[0].bits.uop.ldst_is_rs1
connect exe_req[0].bits.uop.flush_on_commit, _exe_req_WIRE[0].bits.uop.flush_on_commit
connect exe_req[0].bits.uop.is_unique, _exe_req_WIRE[0].bits.uop.is_unique
connect exe_req[0].bits.uop.is_sys_pc2epc, _exe_req_WIRE[0].bits.uop.is_sys_pc2epc
connect exe_req[0].bits.uop.uses_stq, _exe_req_WIRE[0].bits.uop.uses_stq
connect exe_req[0].bits.uop.uses_ldq, _exe_req_WIRE[0].bits.uop.uses_ldq
connect exe_req[0].bits.uop.is_amo, _exe_req_WIRE[0].bits.uop.is_amo
connect exe_req[0].bits.uop.is_fencei, _exe_req_WIRE[0].bits.uop.is_fencei
connect exe_req[0].bits.uop.is_fence, _exe_req_WIRE[0].bits.uop.is_fence
connect exe_req[0].bits.uop.mem_signed, _exe_req_WIRE[0].bits.uop.mem_signed
connect exe_req[0].bits.uop.mem_size, _exe_req_WIRE[0].bits.uop.mem_size
connect exe_req[0].bits.uop.mem_cmd, _exe_req_WIRE[0].bits.uop.mem_cmd
connect exe_req[0].bits.uop.bypassable, _exe_req_WIRE[0].bits.uop.bypassable
connect exe_req[0].bits.uop.exc_cause, _exe_req_WIRE[0].bits.uop.exc_cause
connect exe_req[0].bits.uop.exception, _exe_req_WIRE[0].bits.uop.exception
connect exe_req[0].bits.uop.stale_pdst, _exe_req_WIRE[0].bits.uop.stale_pdst
connect exe_req[0].bits.uop.ppred_busy, _exe_req_WIRE[0].bits.uop.ppred_busy
connect exe_req[0].bits.uop.prs3_busy, _exe_req_WIRE[0].bits.uop.prs3_busy
connect exe_req[0].bits.uop.prs2_busy, _exe_req_WIRE[0].bits.uop.prs2_busy
connect exe_req[0].bits.uop.prs1_busy, _exe_req_WIRE[0].bits.uop.prs1_busy
connect exe_req[0].bits.uop.ppred, _exe_req_WIRE[0].bits.uop.ppred
connect exe_req[0].bits.uop.prs3, _exe_req_WIRE[0].bits.uop.prs3
connect exe_req[0].bits.uop.prs2, _exe_req_WIRE[0].bits.uop.prs2
connect exe_req[0].bits.uop.prs1, _exe_req_WIRE[0].bits.uop.prs1
connect exe_req[0].bits.uop.pdst, _exe_req_WIRE[0].bits.uop.pdst
connect exe_req[0].bits.uop.rxq_idx, _exe_req_WIRE[0].bits.uop.rxq_idx
connect exe_req[0].bits.uop.stq_idx, _exe_req_WIRE[0].bits.uop.stq_idx
connect exe_req[0].bits.uop.ldq_idx, _exe_req_WIRE[0].bits.uop.ldq_idx
connect exe_req[0].bits.uop.rob_idx, _exe_req_WIRE[0].bits.uop.rob_idx
connect exe_req[0].bits.uop.csr_addr, _exe_req_WIRE[0].bits.uop.csr_addr
connect exe_req[0].bits.uop.imm_packed, _exe_req_WIRE[0].bits.uop.imm_packed
connect exe_req[0].bits.uop.taken, _exe_req_WIRE[0].bits.uop.taken
connect exe_req[0].bits.uop.pc_lob, _exe_req_WIRE[0].bits.uop.pc_lob
connect exe_req[0].bits.uop.edge_inst, _exe_req_WIRE[0].bits.uop.edge_inst
connect exe_req[0].bits.uop.ftq_idx, _exe_req_WIRE[0].bits.uop.ftq_idx
connect exe_req[0].bits.uop.br_tag, _exe_req_WIRE[0].bits.uop.br_tag
connect exe_req[0].bits.uop.br_mask, _exe_req_WIRE[0].bits.uop.br_mask
connect exe_req[0].bits.uop.is_sfb, _exe_req_WIRE[0].bits.uop.is_sfb
connect exe_req[0].bits.uop.is_jal, _exe_req_WIRE[0].bits.uop.is_jal
connect exe_req[0].bits.uop.is_jalr, _exe_req_WIRE[0].bits.uop.is_jalr
connect exe_req[0].bits.uop.is_br, _exe_req_WIRE[0].bits.uop.is_br
connect exe_req[0].bits.uop.iw_p2_poisoned, _exe_req_WIRE[0].bits.uop.iw_p2_poisoned
connect exe_req[0].bits.uop.iw_p1_poisoned, _exe_req_WIRE[0].bits.uop.iw_p1_poisoned
connect exe_req[0].bits.uop.iw_state, _exe_req_WIRE[0].bits.uop.iw_state
connect exe_req[0].bits.uop.ctrl.is_std, _exe_req_WIRE[0].bits.uop.ctrl.is_std
connect exe_req[0].bits.uop.ctrl.is_sta, _exe_req_WIRE[0].bits.uop.ctrl.is_sta
connect exe_req[0].bits.uop.ctrl.is_load, _exe_req_WIRE[0].bits.uop.ctrl.is_load
connect exe_req[0].bits.uop.ctrl.csr_cmd, _exe_req_WIRE[0].bits.uop.ctrl.csr_cmd
connect exe_req[0].bits.uop.ctrl.fcn_dw, _exe_req_WIRE[0].bits.uop.ctrl.fcn_dw
connect exe_req[0].bits.uop.ctrl.op_fcn, _exe_req_WIRE[0].bits.uop.ctrl.op_fcn
connect exe_req[0].bits.uop.ctrl.imm_sel, _exe_req_WIRE[0].bits.uop.ctrl.imm_sel
connect exe_req[0].bits.uop.ctrl.op2_sel, _exe_req_WIRE[0].bits.uop.ctrl.op2_sel
connect exe_req[0].bits.uop.ctrl.op1_sel, _exe_req_WIRE[0].bits.uop.ctrl.op1_sel
connect exe_req[0].bits.uop.ctrl.br_type, _exe_req_WIRE[0].bits.uop.ctrl.br_type
connect exe_req[0].bits.uop.fu_code, _exe_req_WIRE[0].bits.uop.fu_code
connect exe_req[0].bits.uop.iq_type, _exe_req_WIRE[0].bits.uop.iq_type
connect exe_req[0].bits.uop.debug_pc, _exe_req_WIRE[0].bits.uop.debug_pc
connect exe_req[0].bits.uop.is_rvc, _exe_req_WIRE[0].bits.uop.is_rvc
connect exe_req[0].bits.uop.debug_inst, _exe_req_WIRE[0].bits.uop.debug_inst
connect exe_req[0].bits.uop.inst, _exe_req_WIRE[0].bits.uop.inst
connect exe_req[0].bits.uop.uopc, _exe_req_WIRE[0].bits.uop.uopc
connect exe_req[0].valid, _exe_req_WIRE[0].valid
when io.core.exe[0].req.bits.sfence.valid :
wire _WIRE : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}[1]
connect _WIRE[0], io.core.exe[0].req
connect exe_req[0].bits.sfence.bits.hg, _WIRE[0].bits.sfence.bits.hg
connect exe_req[0].bits.sfence.bits.hv, _WIRE[0].bits.sfence.bits.hv
connect exe_req[0].bits.sfence.bits.asid, _WIRE[0].bits.sfence.bits.asid
connect exe_req[0].bits.sfence.bits.addr, _WIRE[0].bits.sfence.bits.addr
connect exe_req[0].bits.sfence.bits.rs2, _WIRE[0].bits.sfence.bits.rs2
connect exe_req[0].bits.sfence.bits.rs1, _WIRE[0].bits.sfence.bits.rs1
connect exe_req[0].bits.sfence.valid, _WIRE[0].bits.sfence.valid
connect exe_req[0].bits.mxcpt.bits, _WIRE[0].bits.mxcpt.bits
connect exe_req[0].bits.mxcpt.valid, _WIRE[0].bits.mxcpt.valid
connect exe_req[0].bits.addr, _WIRE[0].bits.addr
connect exe_req[0].bits.fflags.bits.flags, _WIRE[0].bits.fflags.bits.flags
connect exe_req[0].bits.fflags.bits.uop.debug_tsrc, _WIRE[0].bits.fflags.bits.uop.debug_tsrc
connect exe_req[0].bits.fflags.bits.uop.debug_fsrc, _WIRE[0].bits.fflags.bits.uop.debug_fsrc
connect exe_req[0].bits.fflags.bits.uop.bp_xcpt_if, _WIRE[0].bits.fflags.bits.uop.bp_xcpt_if
connect exe_req[0].bits.fflags.bits.uop.bp_debug_if, _WIRE[0].bits.fflags.bits.uop.bp_debug_if
connect exe_req[0].bits.fflags.bits.uop.xcpt_ma_if, _WIRE[0].bits.fflags.bits.uop.xcpt_ma_if
connect exe_req[0].bits.fflags.bits.uop.xcpt_ae_if, _WIRE[0].bits.fflags.bits.uop.xcpt_ae_if
connect exe_req[0].bits.fflags.bits.uop.xcpt_pf_if, _WIRE[0].bits.fflags.bits.uop.xcpt_pf_if
connect exe_req[0].bits.fflags.bits.uop.fp_single, _WIRE[0].bits.fflags.bits.uop.fp_single
connect exe_req[0].bits.fflags.bits.uop.fp_val, _WIRE[0].bits.fflags.bits.uop.fp_val
connect exe_req[0].bits.fflags.bits.uop.frs3_en, _WIRE[0].bits.fflags.bits.uop.frs3_en
connect exe_req[0].bits.fflags.bits.uop.lrs2_rtype, _WIRE[0].bits.fflags.bits.uop.lrs2_rtype
connect exe_req[0].bits.fflags.bits.uop.lrs1_rtype, _WIRE[0].bits.fflags.bits.uop.lrs1_rtype
connect exe_req[0].bits.fflags.bits.uop.dst_rtype, _WIRE[0].bits.fflags.bits.uop.dst_rtype
connect exe_req[0].bits.fflags.bits.uop.ldst_val, _WIRE[0].bits.fflags.bits.uop.ldst_val
connect exe_req[0].bits.fflags.bits.uop.lrs3, _WIRE[0].bits.fflags.bits.uop.lrs3
connect exe_req[0].bits.fflags.bits.uop.lrs2, _WIRE[0].bits.fflags.bits.uop.lrs2
connect exe_req[0].bits.fflags.bits.uop.lrs1, _WIRE[0].bits.fflags.bits.uop.lrs1
connect exe_req[0].bits.fflags.bits.uop.ldst, _WIRE[0].bits.fflags.bits.uop.ldst
connect exe_req[0].bits.fflags.bits.uop.ldst_is_rs1, _WIRE[0].bits.fflags.bits.uop.ldst_is_rs1
connect exe_req[0].bits.fflags.bits.uop.flush_on_commit, _WIRE[0].bits.fflags.bits.uop.flush_on_commit
connect exe_req[0].bits.fflags.bits.uop.is_unique, _WIRE[0].bits.fflags.bits.uop.is_unique
connect exe_req[0].bits.fflags.bits.uop.is_sys_pc2epc, _WIRE[0].bits.fflags.bits.uop.is_sys_pc2epc
connect exe_req[0].bits.fflags.bits.uop.uses_stq, _WIRE[0].bits.fflags.bits.uop.uses_stq
connect exe_req[0].bits.fflags.bits.uop.uses_ldq, _WIRE[0].bits.fflags.bits.uop.uses_ldq
connect exe_req[0].bits.fflags.bits.uop.is_amo, _WIRE[0].bits.fflags.bits.uop.is_amo
connect exe_req[0].bits.fflags.bits.uop.is_fencei, _WIRE[0].bits.fflags.bits.uop.is_fencei
connect exe_req[0].bits.fflags.bits.uop.is_fence, _WIRE[0].bits.fflags.bits.uop.is_fence
connect exe_req[0].bits.fflags.bits.uop.mem_signed, _WIRE[0].bits.fflags.bits.uop.mem_signed
connect exe_req[0].bits.fflags.bits.uop.mem_size, _WIRE[0].bits.fflags.bits.uop.mem_size
connect exe_req[0].bits.fflags.bits.uop.mem_cmd, _WIRE[0].bits.fflags.bits.uop.mem_cmd
connect exe_req[0].bits.fflags.bits.uop.bypassable, _WIRE[0].bits.fflags.bits.uop.bypassable
connect exe_req[0].bits.fflags.bits.uop.exc_cause, _WIRE[0].bits.fflags.bits.uop.exc_cause
connect exe_req[0].bits.fflags.bits.uop.exception, _WIRE[0].bits.fflags.bits.uop.exception
connect exe_req[0].bits.fflags.bits.uop.stale_pdst, _WIRE[0].bits.fflags.bits.uop.stale_pdst
connect exe_req[0].bits.fflags.bits.uop.ppred_busy, _WIRE[0].bits.fflags.bits.uop.ppred_busy
connect exe_req[0].bits.fflags.bits.uop.prs3_busy, _WIRE[0].bits.fflags.bits.uop.prs3_busy
connect exe_req[0].bits.fflags.bits.uop.prs2_busy, _WIRE[0].bits.fflags.bits.uop.prs2_busy
connect exe_req[0].bits.fflags.bits.uop.prs1_busy, _WIRE[0].bits.fflags.bits.uop.prs1_busy
connect exe_req[0].bits.fflags.bits.uop.ppred, _WIRE[0].bits.fflags.bits.uop.ppred
connect exe_req[0].bits.fflags.bits.uop.prs3, _WIRE[0].bits.fflags.bits.uop.prs3
connect exe_req[0].bits.fflags.bits.uop.prs2, _WIRE[0].bits.fflags.bits.uop.prs2
connect exe_req[0].bits.fflags.bits.uop.prs1, _WIRE[0].bits.fflags.bits.uop.prs1
connect exe_req[0].bits.fflags.bits.uop.pdst, _WIRE[0].bits.fflags.bits.uop.pdst
connect exe_req[0].bits.fflags.bits.uop.rxq_idx, _WIRE[0].bits.fflags.bits.uop.rxq_idx
connect exe_req[0].bits.fflags.bits.uop.stq_idx, _WIRE[0].bits.fflags.bits.uop.stq_idx
connect exe_req[0].bits.fflags.bits.uop.ldq_idx, _WIRE[0].bits.fflags.bits.uop.ldq_idx
connect exe_req[0].bits.fflags.bits.uop.rob_idx, _WIRE[0].bits.fflags.bits.uop.rob_idx
connect exe_req[0].bits.fflags.bits.uop.csr_addr, _WIRE[0].bits.fflags.bits.uop.csr_addr
connect exe_req[0].bits.fflags.bits.uop.imm_packed, _WIRE[0].bits.fflags.bits.uop.imm_packed
connect exe_req[0].bits.fflags.bits.uop.taken, _WIRE[0].bits.fflags.bits.uop.taken
connect exe_req[0].bits.fflags.bits.uop.pc_lob, _WIRE[0].bits.fflags.bits.uop.pc_lob
connect exe_req[0].bits.fflags.bits.uop.edge_inst, _WIRE[0].bits.fflags.bits.uop.edge_inst
connect exe_req[0].bits.fflags.bits.uop.ftq_idx, _WIRE[0].bits.fflags.bits.uop.ftq_idx
connect exe_req[0].bits.fflags.bits.uop.br_tag, _WIRE[0].bits.fflags.bits.uop.br_tag
connect exe_req[0].bits.fflags.bits.uop.br_mask, _WIRE[0].bits.fflags.bits.uop.br_mask
connect exe_req[0].bits.fflags.bits.uop.is_sfb, _WIRE[0].bits.fflags.bits.uop.is_sfb
connect exe_req[0].bits.fflags.bits.uop.is_jal, _WIRE[0].bits.fflags.bits.uop.is_jal
connect exe_req[0].bits.fflags.bits.uop.is_jalr, _WIRE[0].bits.fflags.bits.uop.is_jalr
connect exe_req[0].bits.fflags.bits.uop.is_br, _WIRE[0].bits.fflags.bits.uop.is_br
connect exe_req[0].bits.fflags.bits.uop.iw_p2_poisoned, _WIRE[0].bits.fflags.bits.uop.iw_p2_poisoned
connect exe_req[0].bits.fflags.bits.uop.iw_p1_poisoned, _WIRE[0].bits.fflags.bits.uop.iw_p1_poisoned
connect exe_req[0].bits.fflags.bits.uop.iw_state, _WIRE[0].bits.fflags.bits.uop.iw_state
connect exe_req[0].bits.fflags.bits.uop.ctrl.is_std, _WIRE[0].bits.fflags.bits.uop.ctrl.is_std
connect exe_req[0].bits.fflags.bits.uop.ctrl.is_sta, _WIRE[0].bits.fflags.bits.uop.ctrl.is_sta
connect exe_req[0].bits.fflags.bits.uop.ctrl.is_load, _WIRE[0].bits.fflags.bits.uop.ctrl.is_load
connect exe_req[0].bits.fflags.bits.uop.ctrl.csr_cmd, _WIRE[0].bits.fflags.bits.uop.ctrl.csr_cmd
connect exe_req[0].bits.fflags.bits.uop.ctrl.fcn_dw, _WIRE[0].bits.fflags.bits.uop.ctrl.fcn_dw
connect exe_req[0].bits.fflags.bits.uop.ctrl.op_fcn, _WIRE[0].bits.fflags.bits.uop.ctrl.op_fcn
connect exe_req[0].bits.fflags.bits.uop.ctrl.imm_sel, _WIRE[0].bits.fflags.bits.uop.ctrl.imm_sel
connect exe_req[0].bits.fflags.bits.uop.ctrl.op2_sel, _WIRE[0].bits.fflags.bits.uop.ctrl.op2_sel
connect exe_req[0].bits.fflags.bits.uop.ctrl.op1_sel, _WIRE[0].bits.fflags.bits.uop.ctrl.op1_sel
connect exe_req[0].bits.fflags.bits.uop.ctrl.br_type, _WIRE[0].bits.fflags.bits.uop.ctrl.br_type
connect exe_req[0].bits.fflags.bits.uop.fu_code, _WIRE[0].bits.fflags.bits.uop.fu_code
connect exe_req[0].bits.fflags.bits.uop.iq_type, _WIRE[0].bits.fflags.bits.uop.iq_type
connect exe_req[0].bits.fflags.bits.uop.debug_pc, _WIRE[0].bits.fflags.bits.uop.debug_pc
connect exe_req[0].bits.fflags.bits.uop.is_rvc, _WIRE[0].bits.fflags.bits.uop.is_rvc
connect exe_req[0].bits.fflags.bits.uop.debug_inst, _WIRE[0].bits.fflags.bits.uop.debug_inst
connect exe_req[0].bits.fflags.bits.uop.inst, _WIRE[0].bits.fflags.bits.uop.inst
connect exe_req[0].bits.fflags.bits.uop.uopc, _WIRE[0].bits.fflags.bits.uop.uopc
connect exe_req[0].bits.fflags.valid, _WIRE[0].bits.fflags.valid
connect exe_req[0].bits.data, _WIRE[0].bits.data
connect exe_req[0].bits.predicated, _WIRE[0].bits.predicated
connect exe_req[0].bits.uop.debug_tsrc, _WIRE[0].bits.uop.debug_tsrc
connect exe_req[0].bits.uop.debug_fsrc, _WIRE[0].bits.uop.debug_fsrc
connect exe_req[0].bits.uop.bp_xcpt_if, _WIRE[0].bits.uop.bp_xcpt_if
connect exe_req[0].bits.uop.bp_debug_if, _WIRE[0].bits.uop.bp_debug_if
connect exe_req[0].bits.uop.xcpt_ma_if, _WIRE[0].bits.uop.xcpt_ma_if
connect exe_req[0].bits.uop.xcpt_ae_if, _WIRE[0].bits.uop.xcpt_ae_if
connect exe_req[0].bits.uop.xcpt_pf_if, _WIRE[0].bits.uop.xcpt_pf_if
connect exe_req[0].bits.uop.fp_single, _WIRE[0].bits.uop.fp_single
connect exe_req[0].bits.uop.fp_val, _WIRE[0].bits.uop.fp_val
connect exe_req[0].bits.uop.frs3_en, _WIRE[0].bits.uop.frs3_en
connect exe_req[0].bits.uop.lrs2_rtype, _WIRE[0].bits.uop.lrs2_rtype
connect exe_req[0].bits.uop.lrs1_rtype, _WIRE[0].bits.uop.lrs1_rtype
connect exe_req[0].bits.uop.dst_rtype, _WIRE[0].bits.uop.dst_rtype
connect exe_req[0].bits.uop.ldst_val, _WIRE[0].bits.uop.ldst_val
connect exe_req[0].bits.uop.lrs3, _WIRE[0].bits.uop.lrs3
connect exe_req[0].bits.uop.lrs2, _WIRE[0].bits.uop.lrs2
connect exe_req[0].bits.uop.lrs1, _WIRE[0].bits.uop.lrs1
connect exe_req[0].bits.uop.ldst, _WIRE[0].bits.uop.ldst
connect exe_req[0].bits.uop.ldst_is_rs1, _WIRE[0].bits.uop.ldst_is_rs1
connect exe_req[0].bits.uop.flush_on_commit, _WIRE[0].bits.uop.flush_on_commit
connect exe_req[0].bits.uop.is_unique, _WIRE[0].bits.uop.is_unique
connect exe_req[0].bits.uop.is_sys_pc2epc, _WIRE[0].bits.uop.is_sys_pc2epc
connect exe_req[0].bits.uop.uses_stq, _WIRE[0].bits.uop.uses_stq
connect exe_req[0].bits.uop.uses_ldq, _WIRE[0].bits.uop.uses_ldq
connect exe_req[0].bits.uop.is_amo, _WIRE[0].bits.uop.is_amo
connect exe_req[0].bits.uop.is_fencei, _WIRE[0].bits.uop.is_fencei
connect exe_req[0].bits.uop.is_fence, _WIRE[0].bits.uop.is_fence
connect exe_req[0].bits.uop.mem_signed, _WIRE[0].bits.uop.mem_signed
connect exe_req[0].bits.uop.mem_size, _WIRE[0].bits.uop.mem_size
connect exe_req[0].bits.uop.mem_cmd, _WIRE[0].bits.uop.mem_cmd
connect exe_req[0].bits.uop.bypassable, _WIRE[0].bits.uop.bypassable
connect exe_req[0].bits.uop.exc_cause, _WIRE[0].bits.uop.exc_cause
connect exe_req[0].bits.uop.exception, _WIRE[0].bits.uop.exception
connect exe_req[0].bits.uop.stale_pdst, _WIRE[0].bits.uop.stale_pdst
connect exe_req[0].bits.uop.ppred_busy, _WIRE[0].bits.uop.ppred_busy
connect exe_req[0].bits.uop.prs3_busy, _WIRE[0].bits.uop.prs3_busy
connect exe_req[0].bits.uop.prs2_busy, _WIRE[0].bits.uop.prs2_busy
connect exe_req[0].bits.uop.prs1_busy, _WIRE[0].bits.uop.prs1_busy
connect exe_req[0].bits.uop.ppred, _WIRE[0].bits.uop.ppred
connect exe_req[0].bits.uop.prs3, _WIRE[0].bits.uop.prs3
connect exe_req[0].bits.uop.prs2, _WIRE[0].bits.uop.prs2
connect exe_req[0].bits.uop.prs1, _WIRE[0].bits.uop.prs1
connect exe_req[0].bits.uop.pdst, _WIRE[0].bits.uop.pdst
connect exe_req[0].bits.uop.rxq_idx, _WIRE[0].bits.uop.rxq_idx
connect exe_req[0].bits.uop.stq_idx, _WIRE[0].bits.uop.stq_idx
connect exe_req[0].bits.uop.ldq_idx, _WIRE[0].bits.uop.ldq_idx
connect exe_req[0].bits.uop.rob_idx, _WIRE[0].bits.uop.rob_idx
connect exe_req[0].bits.uop.csr_addr, _WIRE[0].bits.uop.csr_addr
connect exe_req[0].bits.uop.imm_packed, _WIRE[0].bits.uop.imm_packed
connect exe_req[0].bits.uop.taken, _WIRE[0].bits.uop.taken
connect exe_req[0].bits.uop.pc_lob, _WIRE[0].bits.uop.pc_lob
connect exe_req[0].bits.uop.edge_inst, _WIRE[0].bits.uop.edge_inst
connect exe_req[0].bits.uop.ftq_idx, _WIRE[0].bits.uop.ftq_idx
connect exe_req[0].bits.uop.br_tag, _WIRE[0].bits.uop.br_tag
connect exe_req[0].bits.uop.br_mask, _WIRE[0].bits.uop.br_mask
connect exe_req[0].bits.uop.is_sfb, _WIRE[0].bits.uop.is_sfb
connect exe_req[0].bits.uop.is_jal, _WIRE[0].bits.uop.is_jal
connect exe_req[0].bits.uop.is_jalr, _WIRE[0].bits.uop.is_jalr
connect exe_req[0].bits.uop.is_br, _WIRE[0].bits.uop.is_br
connect exe_req[0].bits.uop.iw_p2_poisoned, _WIRE[0].bits.uop.iw_p2_poisoned
connect exe_req[0].bits.uop.iw_p1_poisoned, _WIRE[0].bits.uop.iw_p1_poisoned
connect exe_req[0].bits.uop.iw_state, _WIRE[0].bits.uop.iw_state
connect exe_req[0].bits.uop.ctrl.is_std, _WIRE[0].bits.uop.ctrl.is_std
connect exe_req[0].bits.uop.ctrl.is_sta, _WIRE[0].bits.uop.ctrl.is_sta
connect exe_req[0].bits.uop.ctrl.is_load, _WIRE[0].bits.uop.ctrl.is_load
connect exe_req[0].bits.uop.ctrl.csr_cmd, _WIRE[0].bits.uop.ctrl.csr_cmd
connect exe_req[0].bits.uop.ctrl.fcn_dw, _WIRE[0].bits.uop.ctrl.fcn_dw
connect exe_req[0].bits.uop.ctrl.op_fcn, _WIRE[0].bits.uop.ctrl.op_fcn
connect exe_req[0].bits.uop.ctrl.imm_sel, _WIRE[0].bits.uop.ctrl.imm_sel
connect exe_req[0].bits.uop.ctrl.op2_sel, _WIRE[0].bits.uop.ctrl.op2_sel
connect exe_req[0].bits.uop.ctrl.op1_sel, _WIRE[0].bits.uop.ctrl.op1_sel
connect exe_req[0].bits.uop.ctrl.br_type, _WIRE[0].bits.uop.ctrl.br_type
connect exe_req[0].bits.uop.fu_code, _WIRE[0].bits.uop.fu_code
connect exe_req[0].bits.uop.iq_type, _WIRE[0].bits.uop.iq_type
connect exe_req[0].bits.uop.debug_pc, _WIRE[0].bits.uop.debug_pc
connect exe_req[0].bits.uop.is_rvc, _WIRE[0].bits.uop.is_rvc
connect exe_req[0].bits.uop.debug_inst, _WIRE[0].bits.uop.debug_inst
connect exe_req[0].bits.uop.inst, _WIRE[0].bits.uop.inst
connect exe_req[0].bits.uop.uopc, _WIRE[0].bits.uop.uopc
connect exe_req[0].valid, _WIRE[0].valid
wire _block_load_mask_WIRE : UInt<1>[24]
connect _block_load_mask_WIRE[0], UInt<1>(0h0)
connect _block_load_mask_WIRE[1], UInt<1>(0h0)
connect _block_load_mask_WIRE[2], UInt<1>(0h0)
connect _block_load_mask_WIRE[3], UInt<1>(0h0)
connect _block_load_mask_WIRE[4], UInt<1>(0h0)
connect _block_load_mask_WIRE[5], UInt<1>(0h0)
connect _block_load_mask_WIRE[6], UInt<1>(0h0)
connect _block_load_mask_WIRE[7], UInt<1>(0h0)
connect _block_load_mask_WIRE[8], UInt<1>(0h0)
connect _block_load_mask_WIRE[9], UInt<1>(0h0)
connect _block_load_mask_WIRE[10], UInt<1>(0h0)
connect _block_load_mask_WIRE[11], UInt<1>(0h0)
connect _block_load_mask_WIRE[12], UInt<1>(0h0)
connect _block_load_mask_WIRE[13], UInt<1>(0h0)
connect _block_load_mask_WIRE[14], UInt<1>(0h0)
connect _block_load_mask_WIRE[15], UInt<1>(0h0)
connect _block_load_mask_WIRE[16], UInt<1>(0h0)
connect _block_load_mask_WIRE[17], UInt<1>(0h0)
connect _block_load_mask_WIRE[18], UInt<1>(0h0)
connect _block_load_mask_WIRE[19], UInt<1>(0h0)
connect _block_load_mask_WIRE[20], UInt<1>(0h0)
connect _block_load_mask_WIRE[21], UInt<1>(0h0)
connect _block_load_mask_WIRE[22], UInt<1>(0h0)
connect _block_load_mask_WIRE[23], UInt<1>(0h0)
wire block_load_mask : UInt<1>[24]
connect block_load_mask, _block_load_mask_WIRE
reg p1_block_load_mask : UInt<1>[24], clock
connect p1_block_load_mask, block_load_mask
reg p2_block_load_mask : UInt<1>[24], clock
connect p2_block_load_mask, p1_block_load_mask
node stq_almost_full_wrap = eq(_T_122, UInt<5>(0h17))
node _stq_almost_full_T = add(_T_122, UInt<1>(0h1))
node _stq_almost_full_T_1 = tail(_stq_almost_full_T, 1)
node _stq_almost_full_T_2 = mux(stq_almost_full_wrap, UInt<1>(0h0), _stq_almost_full_T_1)
node stq_almost_full_wrap_1 = eq(_stq_almost_full_T_2, UInt<5>(0h17))
node _stq_almost_full_T_3 = add(_stq_almost_full_T_2, UInt<1>(0h1))
node _stq_almost_full_T_4 = tail(_stq_almost_full_T_3, 1)
node _stq_almost_full_T_5 = mux(stq_almost_full_wrap_1, UInt<1>(0h0), _stq_almost_full_T_4)
node _stq_almost_full_T_6 = eq(_stq_almost_full_T_5, stq_head)
node stq_almost_full_wrap_2 = eq(_T_122, UInt<5>(0h17))
node _stq_almost_full_T_7 = add(_T_122, UInt<1>(0h1))
node _stq_almost_full_T_8 = tail(_stq_almost_full_T_7, 1)
node _stq_almost_full_T_9 = mux(stq_almost_full_wrap_2, UInt<1>(0h0), _stq_almost_full_T_8)
node _stq_almost_full_T_10 = eq(_stq_almost_full_T_9, stq_head)
node _stq_almost_full_T_11 = or(_stq_almost_full_T_6, _stq_almost_full_T_10)
reg stq_almost_full : UInt<1>, clock
connect stq_almost_full, _stq_almost_full_T_11
wire store_needs_order : UInt<1>
connect store_needs_order, UInt<1>(0h0)
wire ldq_incoming_idx : UInt<5>[1]
connect ldq_incoming_idx[0], exe_req[0].bits.uop.ldq_idx
wire ldq_incoming_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1]
connect ldq_incoming_e[0], ldq[ldq_incoming_idx[0]]
wire stq_incoming_idx : UInt<5>[1]
connect stq_incoming_idx[0], exe_req[0].bits.uop.stq_idx
wire stq_incoming_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}[1]
connect stq_incoming_e[0], stq[stq_incoming_idx[0]]
node ldq_retry_idx_block = or(block_load_mask[0], p1_block_load_mask[0])
node _ldq_retry_idx_T = and(ldq[0].bits.addr.valid, ldq[0].bits.addr_is_virtual)
node _ldq_retry_idx_T_1 = eq(ldq_retry_idx_block, UInt<1>(0h0))
node _ldq_retry_idx_T_2 = and(_ldq_retry_idx_T, _ldq_retry_idx_T_1)
node ldq_retry_idx_block_1 = or(block_load_mask[1], p1_block_load_mask[1])
node _ldq_retry_idx_T_3 = and(ldq[1].bits.addr.valid, ldq[1].bits.addr_is_virtual)
node _ldq_retry_idx_T_4 = eq(ldq_retry_idx_block_1, UInt<1>(0h0))
node _ldq_retry_idx_T_5 = and(_ldq_retry_idx_T_3, _ldq_retry_idx_T_4)
node ldq_retry_idx_block_2 = or(block_load_mask[2], p1_block_load_mask[2])
node _ldq_retry_idx_T_6 = and(ldq[2].bits.addr.valid, ldq[2].bits.addr_is_virtual)
node _ldq_retry_idx_T_7 = eq(ldq_retry_idx_block_2, UInt<1>(0h0))
node _ldq_retry_idx_T_8 = and(_ldq_retry_idx_T_6, _ldq_retry_idx_T_7)
node ldq_retry_idx_block_3 = or(block_load_mask[3], p1_block_load_mask[3])
node _ldq_retry_idx_T_9 = and(ldq[3].bits.addr.valid, ldq[3].bits.addr_is_virtual)
node _ldq_retry_idx_T_10 = eq(ldq_retry_idx_block_3, UInt<1>(0h0))
node _ldq_retry_idx_T_11 = and(_ldq_retry_idx_T_9, _ldq_retry_idx_T_10)
node ldq_retry_idx_block_4 = or(block_load_mask[4], p1_block_load_mask[4])
node _ldq_retry_idx_T_12 = and(ldq[4].bits.addr.valid, ldq[4].bits.addr_is_virtual)
node _ldq_retry_idx_T_13 = eq(ldq_retry_idx_block_4, UInt<1>(0h0))
node _ldq_retry_idx_T_14 = and(_ldq_retry_idx_T_12, _ldq_retry_idx_T_13)
node ldq_retry_idx_block_5 = or(block_load_mask[5], p1_block_load_mask[5])
node _ldq_retry_idx_T_15 = and(ldq[5].bits.addr.valid, ldq[5].bits.addr_is_virtual)
node _ldq_retry_idx_T_16 = eq(ldq_retry_idx_block_5, UInt<1>(0h0))
node _ldq_retry_idx_T_17 = and(_ldq_retry_idx_T_15, _ldq_retry_idx_T_16)
node ldq_retry_idx_block_6 = or(block_load_mask[6], p1_block_load_mask[6])
node _ldq_retry_idx_T_18 = and(ldq[6].bits.addr.valid, ldq[6].bits.addr_is_virtual)
node _ldq_retry_idx_T_19 = eq(ldq_retry_idx_block_6, UInt<1>(0h0))
node _ldq_retry_idx_T_20 = and(_ldq_retry_idx_T_18, _ldq_retry_idx_T_19)
node ldq_retry_idx_block_7 = or(block_load_mask[7], p1_block_load_mask[7])
node _ldq_retry_idx_T_21 = and(ldq[7].bits.addr.valid, ldq[7].bits.addr_is_virtual)
node _ldq_retry_idx_T_22 = eq(ldq_retry_idx_block_7, UInt<1>(0h0))
node _ldq_retry_idx_T_23 = and(_ldq_retry_idx_T_21, _ldq_retry_idx_T_22)
node ldq_retry_idx_block_8 = or(block_load_mask[8], p1_block_load_mask[8])
node _ldq_retry_idx_T_24 = and(ldq[8].bits.addr.valid, ldq[8].bits.addr_is_virtual)
node _ldq_retry_idx_T_25 = eq(ldq_retry_idx_block_8, UInt<1>(0h0))
node _ldq_retry_idx_T_26 = and(_ldq_retry_idx_T_24, _ldq_retry_idx_T_25)
node ldq_retry_idx_block_9 = or(block_load_mask[9], p1_block_load_mask[9])
node _ldq_retry_idx_T_27 = and(ldq[9].bits.addr.valid, ldq[9].bits.addr_is_virtual)
node _ldq_retry_idx_T_28 = eq(ldq_retry_idx_block_9, UInt<1>(0h0))
node _ldq_retry_idx_T_29 = and(_ldq_retry_idx_T_27, _ldq_retry_idx_T_28)
node ldq_retry_idx_block_10 = or(block_load_mask[10], p1_block_load_mask[10])
node _ldq_retry_idx_T_30 = and(ldq[10].bits.addr.valid, ldq[10].bits.addr_is_virtual)
node _ldq_retry_idx_T_31 = eq(ldq_retry_idx_block_10, UInt<1>(0h0))
node _ldq_retry_idx_T_32 = and(_ldq_retry_idx_T_30, _ldq_retry_idx_T_31)
node ldq_retry_idx_block_11 = or(block_load_mask[11], p1_block_load_mask[11])
node _ldq_retry_idx_T_33 = and(ldq[11].bits.addr.valid, ldq[11].bits.addr_is_virtual)
node _ldq_retry_idx_T_34 = eq(ldq_retry_idx_block_11, UInt<1>(0h0))
node _ldq_retry_idx_T_35 = and(_ldq_retry_idx_T_33, _ldq_retry_idx_T_34)
node ldq_retry_idx_block_12 = or(block_load_mask[12], p1_block_load_mask[12])
node _ldq_retry_idx_T_36 = and(ldq[12].bits.addr.valid, ldq[12].bits.addr_is_virtual)
node _ldq_retry_idx_T_37 = eq(ldq_retry_idx_block_12, UInt<1>(0h0))
node _ldq_retry_idx_T_38 = and(_ldq_retry_idx_T_36, _ldq_retry_idx_T_37)
node ldq_retry_idx_block_13 = or(block_load_mask[13], p1_block_load_mask[13])
node _ldq_retry_idx_T_39 = and(ldq[13].bits.addr.valid, ldq[13].bits.addr_is_virtual)
node _ldq_retry_idx_T_40 = eq(ldq_retry_idx_block_13, UInt<1>(0h0))
node _ldq_retry_idx_T_41 = and(_ldq_retry_idx_T_39, _ldq_retry_idx_T_40)
node ldq_retry_idx_block_14 = or(block_load_mask[14], p1_block_load_mask[14])
node _ldq_retry_idx_T_42 = and(ldq[14].bits.addr.valid, ldq[14].bits.addr_is_virtual)
node _ldq_retry_idx_T_43 = eq(ldq_retry_idx_block_14, UInt<1>(0h0))
node _ldq_retry_idx_T_44 = and(_ldq_retry_idx_T_42, _ldq_retry_idx_T_43)
node ldq_retry_idx_block_15 = or(block_load_mask[15], p1_block_load_mask[15])
node _ldq_retry_idx_T_45 = and(ldq[15].bits.addr.valid, ldq[15].bits.addr_is_virtual)
node _ldq_retry_idx_T_46 = eq(ldq_retry_idx_block_15, UInt<1>(0h0))
node _ldq_retry_idx_T_47 = and(_ldq_retry_idx_T_45, _ldq_retry_idx_T_46)
node ldq_retry_idx_block_16 = or(block_load_mask[16], p1_block_load_mask[16])
node _ldq_retry_idx_T_48 = and(ldq[16].bits.addr.valid, ldq[16].bits.addr_is_virtual)
node _ldq_retry_idx_T_49 = eq(ldq_retry_idx_block_16, UInt<1>(0h0))
node _ldq_retry_idx_T_50 = and(_ldq_retry_idx_T_48, _ldq_retry_idx_T_49)
node ldq_retry_idx_block_17 = or(block_load_mask[17], p1_block_load_mask[17])
node _ldq_retry_idx_T_51 = and(ldq[17].bits.addr.valid, ldq[17].bits.addr_is_virtual)
node _ldq_retry_idx_T_52 = eq(ldq_retry_idx_block_17, UInt<1>(0h0))
node _ldq_retry_idx_T_53 = and(_ldq_retry_idx_T_51, _ldq_retry_idx_T_52)
node ldq_retry_idx_block_18 = or(block_load_mask[18], p1_block_load_mask[18])
node _ldq_retry_idx_T_54 = and(ldq[18].bits.addr.valid, ldq[18].bits.addr_is_virtual)
node _ldq_retry_idx_T_55 = eq(ldq_retry_idx_block_18, UInt<1>(0h0))
node _ldq_retry_idx_T_56 = and(_ldq_retry_idx_T_54, _ldq_retry_idx_T_55)
node ldq_retry_idx_block_19 = or(block_load_mask[19], p1_block_load_mask[19])
node _ldq_retry_idx_T_57 = and(ldq[19].bits.addr.valid, ldq[19].bits.addr_is_virtual)
node _ldq_retry_idx_T_58 = eq(ldq_retry_idx_block_19, UInt<1>(0h0))
node _ldq_retry_idx_T_59 = and(_ldq_retry_idx_T_57, _ldq_retry_idx_T_58)
node ldq_retry_idx_block_20 = or(block_load_mask[20], p1_block_load_mask[20])
node _ldq_retry_idx_T_60 = and(ldq[20].bits.addr.valid, ldq[20].bits.addr_is_virtual)
node _ldq_retry_idx_T_61 = eq(ldq_retry_idx_block_20, UInt<1>(0h0))
node _ldq_retry_idx_T_62 = and(_ldq_retry_idx_T_60, _ldq_retry_idx_T_61)
node ldq_retry_idx_block_21 = or(block_load_mask[21], p1_block_load_mask[21])
node _ldq_retry_idx_T_63 = and(ldq[21].bits.addr.valid, ldq[21].bits.addr_is_virtual)
node _ldq_retry_idx_T_64 = eq(ldq_retry_idx_block_21, UInt<1>(0h0))
node _ldq_retry_idx_T_65 = and(_ldq_retry_idx_T_63, _ldq_retry_idx_T_64)
node ldq_retry_idx_block_22 = or(block_load_mask[22], p1_block_load_mask[22])
node _ldq_retry_idx_T_66 = and(ldq[22].bits.addr.valid, ldq[22].bits.addr_is_virtual)
node _ldq_retry_idx_T_67 = eq(ldq_retry_idx_block_22, UInt<1>(0h0))
node _ldq_retry_idx_T_68 = and(_ldq_retry_idx_T_66, _ldq_retry_idx_T_67)
node ldq_retry_idx_block_23 = or(block_load_mask[23], p1_block_load_mask[23])
node _ldq_retry_idx_T_69 = and(ldq[23].bits.addr.valid, ldq[23].bits.addr_is_virtual)
node _ldq_retry_idx_T_70 = eq(ldq_retry_idx_block_23, UInt<1>(0h0))
node _ldq_retry_idx_T_71 = and(_ldq_retry_idx_T_69, _ldq_retry_idx_T_70)
node _ldq_retry_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head)
node ldq_retry_idx_temp_vec_0 = and(_ldq_retry_idx_T_2, _ldq_retry_idx_temp_vec_T)
node _ldq_retry_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head)
node ldq_retry_idx_temp_vec_1 = and(_ldq_retry_idx_T_5, _ldq_retry_idx_temp_vec_T_1)
node _ldq_retry_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head)
node ldq_retry_idx_temp_vec_2 = and(_ldq_retry_idx_T_8, _ldq_retry_idx_temp_vec_T_2)
node _ldq_retry_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head)
node ldq_retry_idx_temp_vec_3 = and(_ldq_retry_idx_T_11, _ldq_retry_idx_temp_vec_T_3)
node _ldq_retry_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head)
node ldq_retry_idx_temp_vec_4 = and(_ldq_retry_idx_T_14, _ldq_retry_idx_temp_vec_T_4)
node _ldq_retry_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head)
node ldq_retry_idx_temp_vec_5 = and(_ldq_retry_idx_T_17, _ldq_retry_idx_temp_vec_T_5)
node _ldq_retry_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head)
node ldq_retry_idx_temp_vec_6 = and(_ldq_retry_idx_T_20, _ldq_retry_idx_temp_vec_T_6)
node _ldq_retry_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head)
node ldq_retry_idx_temp_vec_7 = and(_ldq_retry_idx_T_23, _ldq_retry_idx_temp_vec_T_7)
node _ldq_retry_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head)
node ldq_retry_idx_temp_vec_8 = and(_ldq_retry_idx_T_26, _ldq_retry_idx_temp_vec_T_8)
node _ldq_retry_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head)
node ldq_retry_idx_temp_vec_9 = and(_ldq_retry_idx_T_29, _ldq_retry_idx_temp_vec_T_9)
node _ldq_retry_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head)
node ldq_retry_idx_temp_vec_10 = and(_ldq_retry_idx_T_32, _ldq_retry_idx_temp_vec_T_10)
node _ldq_retry_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head)
node ldq_retry_idx_temp_vec_11 = and(_ldq_retry_idx_T_35, _ldq_retry_idx_temp_vec_T_11)
node _ldq_retry_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head)
node ldq_retry_idx_temp_vec_12 = and(_ldq_retry_idx_T_38, _ldq_retry_idx_temp_vec_T_12)
node _ldq_retry_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head)
node ldq_retry_idx_temp_vec_13 = and(_ldq_retry_idx_T_41, _ldq_retry_idx_temp_vec_T_13)
node _ldq_retry_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head)
node ldq_retry_idx_temp_vec_14 = and(_ldq_retry_idx_T_44, _ldq_retry_idx_temp_vec_T_14)
node _ldq_retry_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head)
node ldq_retry_idx_temp_vec_15 = and(_ldq_retry_idx_T_47, _ldq_retry_idx_temp_vec_T_15)
node _ldq_retry_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head)
node ldq_retry_idx_temp_vec_16 = and(_ldq_retry_idx_T_50, _ldq_retry_idx_temp_vec_T_16)
node _ldq_retry_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head)
node ldq_retry_idx_temp_vec_17 = and(_ldq_retry_idx_T_53, _ldq_retry_idx_temp_vec_T_17)
node _ldq_retry_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head)
node ldq_retry_idx_temp_vec_18 = and(_ldq_retry_idx_T_56, _ldq_retry_idx_temp_vec_T_18)
node _ldq_retry_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head)
node ldq_retry_idx_temp_vec_19 = and(_ldq_retry_idx_T_59, _ldq_retry_idx_temp_vec_T_19)
node _ldq_retry_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head)
node ldq_retry_idx_temp_vec_20 = and(_ldq_retry_idx_T_62, _ldq_retry_idx_temp_vec_T_20)
node _ldq_retry_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head)
node ldq_retry_idx_temp_vec_21 = and(_ldq_retry_idx_T_65, _ldq_retry_idx_temp_vec_T_21)
node _ldq_retry_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head)
node ldq_retry_idx_temp_vec_22 = and(_ldq_retry_idx_T_68, _ldq_retry_idx_temp_vec_T_22)
node _ldq_retry_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head)
node ldq_retry_idx_temp_vec_23 = and(_ldq_retry_idx_T_71, _ldq_retry_idx_temp_vec_T_23)
node _ldq_retry_idx_idx_T = mux(_ldq_retry_idx_T_68, UInt<6>(0h36), UInt<6>(0h37))
node _ldq_retry_idx_idx_T_1 = mux(_ldq_retry_idx_T_65, UInt<6>(0h35), _ldq_retry_idx_idx_T)
node _ldq_retry_idx_idx_T_2 = mux(_ldq_retry_idx_T_62, UInt<6>(0h34), _ldq_retry_idx_idx_T_1)
node _ldq_retry_idx_idx_T_3 = mux(_ldq_retry_idx_T_59, UInt<6>(0h33), _ldq_retry_idx_idx_T_2)
node _ldq_retry_idx_idx_T_4 = mux(_ldq_retry_idx_T_56, UInt<6>(0h32), _ldq_retry_idx_idx_T_3)
node _ldq_retry_idx_idx_T_5 = mux(_ldq_retry_idx_T_53, UInt<6>(0h31), _ldq_retry_idx_idx_T_4)
node _ldq_retry_idx_idx_T_6 = mux(_ldq_retry_idx_T_50, UInt<6>(0h30), _ldq_retry_idx_idx_T_5)
node _ldq_retry_idx_idx_T_7 = mux(_ldq_retry_idx_T_47, UInt<6>(0h2f), _ldq_retry_idx_idx_T_6)
node _ldq_retry_idx_idx_T_8 = mux(_ldq_retry_idx_T_44, UInt<6>(0h2e), _ldq_retry_idx_idx_T_7)
node _ldq_retry_idx_idx_T_9 = mux(_ldq_retry_idx_T_41, UInt<6>(0h2d), _ldq_retry_idx_idx_T_8)
node _ldq_retry_idx_idx_T_10 = mux(_ldq_retry_idx_T_38, UInt<6>(0h2c), _ldq_retry_idx_idx_T_9)
node _ldq_retry_idx_idx_T_11 = mux(_ldq_retry_idx_T_35, UInt<6>(0h2b), _ldq_retry_idx_idx_T_10)
node _ldq_retry_idx_idx_T_12 = mux(_ldq_retry_idx_T_32, UInt<6>(0h2a), _ldq_retry_idx_idx_T_11)
node _ldq_retry_idx_idx_T_13 = mux(_ldq_retry_idx_T_29, UInt<6>(0h29), _ldq_retry_idx_idx_T_12)
node _ldq_retry_idx_idx_T_14 = mux(_ldq_retry_idx_T_26, UInt<6>(0h28), _ldq_retry_idx_idx_T_13)
node _ldq_retry_idx_idx_T_15 = mux(_ldq_retry_idx_T_23, UInt<6>(0h27), _ldq_retry_idx_idx_T_14)
node _ldq_retry_idx_idx_T_16 = mux(_ldq_retry_idx_T_20, UInt<6>(0h26), _ldq_retry_idx_idx_T_15)
node _ldq_retry_idx_idx_T_17 = mux(_ldq_retry_idx_T_17, UInt<6>(0h25), _ldq_retry_idx_idx_T_16)
node _ldq_retry_idx_idx_T_18 = mux(_ldq_retry_idx_T_14, UInt<6>(0h24), _ldq_retry_idx_idx_T_17)
node _ldq_retry_idx_idx_T_19 = mux(_ldq_retry_idx_T_11, UInt<6>(0h23), _ldq_retry_idx_idx_T_18)
node _ldq_retry_idx_idx_T_20 = mux(_ldq_retry_idx_T_8, UInt<6>(0h22), _ldq_retry_idx_idx_T_19)
node _ldq_retry_idx_idx_T_21 = mux(_ldq_retry_idx_T_5, UInt<6>(0h21), _ldq_retry_idx_idx_T_20)
node _ldq_retry_idx_idx_T_22 = mux(_ldq_retry_idx_T_2, UInt<6>(0h20), _ldq_retry_idx_idx_T_21)
node _ldq_retry_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _ldq_retry_idx_idx_T_22)
node _ldq_retry_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _ldq_retry_idx_idx_T_23)
node _ldq_retry_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _ldq_retry_idx_idx_T_24)
node _ldq_retry_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _ldq_retry_idx_idx_T_25)
node _ldq_retry_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _ldq_retry_idx_idx_T_26)
node _ldq_retry_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _ldq_retry_idx_idx_T_27)
node _ldq_retry_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _ldq_retry_idx_idx_T_28)
node _ldq_retry_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _ldq_retry_idx_idx_T_29)
node _ldq_retry_idx_idx_T_31 = mux(ldq_retry_idx_temp_vec_23, UInt<5>(0h17), _ldq_retry_idx_idx_T_30)
node _ldq_retry_idx_idx_T_32 = mux(ldq_retry_idx_temp_vec_22, UInt<5>(0h16), _ldq_retry_idx_idx_T_31)
node _ldq_retry_idx_idx_T_33 = mux(ldq_retry_idx_temp_vec_21, UInt<5>(0h15), _ldq_retry_idx_idx_T_32)
node _ldq_retry_idx_idx_T_34 = mux(ldq_retry_idx_temp_vec_20, UInt<5>(0h14), _ldq_retry_idx_idx_T_33)
node _ldq_retry_idx_idx_T_35 = mux(ldq_retry_idx_temp_vec_19, UInt<5>(0h13), _ldq_retry_idx_idx_T_34)
node _ldq_retry_idx_idx_T_36 = mux(ldq_retry_idx_temp_vec_18, UInt<5>(0h12), _ldq_retry_idx_idx_T_35)
node _ldq_retry_idx_idx_T_37 = mux(ldq_retry_idx_temp_vec_17, UInt<5>(0h11), _ldq_retry_idx_idx_T_36)
node _ldq_retry_idx_idx_T_38 = mux(ldq_retry_idx_temp_vec_16, UInt<5>(0h10), _ldq_retry_idx_idx_T_37)
node _ldq_retry_idx_idx_T_39 = mux(ldq_retry_idx_temp_vec_15, UInt<4>(0hf), _ldq_retry_idx_idx_T_38)
node _ldq_retry_idx_idx_T_40 = mux(ldq_retry_idx_temp_vec_14, UInt<4>(0he), _ldq_retry_idx_idx_T_39)
node _ldq_retry_idx_idx_T_41 = mux(ldq_retry_idx_temp_vec_13, UInt<4>(0hd), _ldq_retry_idx_idx_T_40)
node _ldq_retry_idx_idx_T_42 = mux(ldq_retry_idx_temp_vec_12, UInt<4>(0hc), _ldq_retry_idx_idx_T_41)
node _ldq_retry_idx_idx_T_43 = mux(ldq_retry_idx_temp_vec_11, UInt<4>(0hb), _ldq_retry_idx_idx_T_42)
node _ldq_retry_idx_idx_T_44 = mux(ldq_retry_idx_temp_vec_10, UInt<4>(0ha), _ldq_retry_idx_idx_T_43)
node _ldq_retry_idx_idx_T_45 = mux(ldq_retry_idx_temp_vec_9, UInt<4>(0h9), _ldq_retry_idx_idx_T_44)
node _ldq_retry_idx_idx_T_46 = mux(ldq_retry_idx_temp_vec_8, UInt<4>(0h8), _ldq_retry_idx_idx_T_45)
node _ldq_retry_idx_idx_T_47 = mux(ldq_retry_idx_temp_vec_7, UInt<3>(0h7), _ldq_retry_idx_idx_T_46)
node _ldq_retry_idx_idx_T_48 = mux(ldq_retry_idx_temp_vec_6, UInt<3>(0h6), _ldq_retry_idx_idx_T_47)
node _ldq_retry_idx_idx_T_49 = mux(ldq_retry_idx_temp_vec_5, UInt<3>(0h5), _ldq_retry_idx_idx_T_48)
node _ldq_retry_idx_idx_T_50 = mux(ldq_retry_idx_temp_vec_4, UInt<3>(0h4), _ldq_retry_idx_idx_T_49)
node _ldq_retry_idx_idx_T_51 = mux(ldq_retry_idx_temp_vec_3, UInt<2>(0h3), _ldq_retry_idx_idx_T_50)
node _ldq_retry_idx_idx_T_52 = mux(ldq_retry_idx_temp_vec_2, UInt<2>(0h2), _ldq_retry_idx_idx_T_51)
node _ldq_retry_idx_idx_T_53 = mux(ldq_retry_idx_temp_vec_1, UInt<1>(0h1), _ldq_retry_idx_idx_T_52)
node ldq_retry_idx_idx = mux(ldq_retry_idx_temp_vec_0, UInt<1>(0h0), _ldq_retry_idx_idx_T_53)
node _ldq_retry_idx_T_72 = bits(ldq_retry_idx_idx, 4, 0)
reg ldq_retry_idx : UInt, clock
connect ldq_retry_idx, _ldq_retry_idx_T_72
node _ldq_retry_e_T = or(ldq_retry_idx, UInt<5>(0h0))
node _ldq_retry_e_T_1 = bits(_ldq_retry_e_T, 4, 0)
node _stq_retry_idx_T = and(stq[0].bits.addr.valid, stq[0].bits.addr_is_virtual)
node _stq_retry_idx_T_1 = and(stq[1].bits.addr.valid, stq[1].bits.addr_is_virtual)
node _stq_retry_idx_T_2 = and(stq[2].bits.addr.valid, stq[2].bits.addr_is_virtual)
node _stq_retry_idx_T_3 = and(stq[3].bits.addr.valid, stq[3].bits.addr_is_virtual)
node _stq_retry_idx_T_4 = and(stq[4].bits.addr.valid, stq[4].bits.addr_is_virtual)
node _stq_retry_idx_T_5 = and(stq[5].bits.addr.valid, stq[5].bits.addr_is_virtual)
node _stq_retry_idx_T_6 = and(stq[6].bits.addr.valid, stq[6].bits.addr_is_virtual)
node _stq_retry_idx_T_7 = and(stq[7].bits.addr.valid, stq[7].bits.addr_is_virtual)
node _stq_retry_idx_T_8 = and(stq[8].bits.addr.valid, stq[8].bits.addr_is_virtual)
node _stq_retry_idx_T_9 = and(stq[9].bits.addr.valid, stq[9].bits.addr_is_virtual)
node _stq_retry_idx_T_10 = and(stq[10].bits.addr.valid, stq[10].bits.addr_is_virtual)
node _stq_retry_idx_T_11 = and(stq[11].bits.addr.valid, stq[11].bits.addr_is_virtual)
node _stq_retry_idx_T_12 = and(stq[12].bits.addr.valid, stq[12].bits.addr_is_virtual)
node _stq_retry_idx_T_13 = and(stq[13].bits.addr.valid, stq[13].bits.addr_is_virtual)
node _stq_retry_idx_T_14 = and(stq[14].bits.addr.valid, stq[14].bits.addr_is_virtual)
node _stq_retry_idx_T_15 = and(stq[15].bits.addr.valid, stq[15].bits.addr_is_virtual)
node _stq_retry_idx_T_16 = and(stq[16].bits.addr.valid, stq[16].bits.addr_is_virtual)
node _stq_retry_idx_T_17 = and(stq[17].bits.addr.valid, stq[17].bits.addr_is_virtual)
node _stq_retry_idx_T_18 = and(stq[18].bits.addr.valid, stq[18].bits.addr_is_virtual)
node _stq_retry_idx_T_19 = and(stq[19].bits.addr.valid, stq[19].bits.addr_is_virtual)
node _stq_retry_idx_T_20 = and(stq[20].bits.addr.valid, stq[20].bits.addr_is_virtual)
node _stq_retry_idx_T_21 = and(stq[21].bits.addr.valid, stq[21].bits.addr_is_virtual)
node _stq_retry_idx_T_22 = and(stq[22].bits.addr.valid, stq[22].bits.addr_is_virtual)
node _stq_retry_idx_T_23 = and(stq[23].bits.addr.valid, stq[23].bits.addr_is_virtual)
node _stq_retry_idx_temp_vec_T = geq(UInt<1>(0h0), stq_commit_head)
node stq_retry_idx_temp_vec_0 = and(_stq_retry_idx_T, _stq_retry_idx_temp_vec_T)
node _stq_retry_idx_temp_vec_T_1 = geq(UInt<1>(0h1), stq_commit_head)
node stq_retry_idx_temp_vec_1 = and(_stq_retry_idx_T_1, _stq_retry_idx_temp_vec_T_1)
node _stq_retry_idx_temp_vec_T_2 = geq(UInt<2>(0h2), stq_commit_head)
node stq_retry_idx_temp_vec_2 = and(_stq_retry_idx_T_2, _stq_retry_idx_temp_vec_T_2)
node _stq_retry_idx_temp_vec_T_3 = geq(UInt<2>(0h3), stq_commit_head)
node stq_retry_idx_temp_vec_3 = and(_stq_retry_idx_T_3, _stq_retry_idx_temp_vec_T_3)
node _stq_retry_idx_temp_vec_T_4 = geq(UInt<3>(0h4), stq_commit_head)
node stq_retry_idx_temp_vec_4 = and(_stq_retry_idx_T_4, _stq_retry_idx_temp_vec_T_4)
node _stq_retry_idx_temp_vec_T_5 = geq(UInt<3>(0h5), stq_commit_head)
node stq_retry_idx_temp_vec_5 = and(_stq_retry_idx_T_5, _stq_retry_idx_temp_vec_T_5)
node _stq_retry_idx_temp_vec_T_6 = geq(UInt<3>(0h6), stq_commit_head)
node stq_retry_idx_temp_vec_6 = and(_stq_retry_idx_T_6, _stq_retry_idx_temp_vec_T_6)
node _stq_retry_idx_temp_vec_T_7 = geq(UInt<3>(0h7), stq_commit_head)
node stq_retry_idx_temp_vec_7 = and(_stq_retry_idx_T_7, _stq_retry_idx_temp_vec_T_7)
node _stq_retry_idx_temp_vec_T_8 = geq(UInt<4>(0h8), stq_commit_head)
node stq_retry_idx_temp_vec_8 = and(_stq_retry_idx_T_8, _stq_retry_idx_temp_vec_T_8)
node _stq_retry_idx_temp_vec_T_9 = geq(UInt<4>(0h9), stq_commit_head)
node stq_retry_idx_temp_vec_9 = and(_stq_retry_idx_T_9, _stq_retry_idx_temp_vec_T_9)
node _stq_retry_idx_temp_vec_T_10 = geq(UInt<4>(0ha), stq_commit_head)
node stq_retry_idx_temp_vec_10 = and(_stq_retry_idx_T_10, _stq_retry_idx_temp_vec_T_10)
node _stq_retry_idx_temp_vec_T_11 = geq(UInt<4>(0hb), stq_commit_head)
node stq_retry_idx_temp_vec_11 = and(_stq_retry_idx_T_11, _stq_retry_idx_temp_vec_T_11)
node _stq_retry_idx_temp_vec_T_12 = geq(UInt<4>(0hc), stq_commit_head)
node stq_retry_idx_temp_vec_12 = and(_stq_retry_idx_T_12, _stq_retry_idx_temp_vec_T_12)
node _stq_retry_idx_temp_vec_T_13 = geq(UInt<4>(0hd), stq_commit_head)
node stq_retry_idx_temp_vec_13 = and(_stq_retry_idx_T_13, _stq_retry_idx_temp_vec_T_13)
node _stq_retry_idx_temp_vec_T_14 = geq(UInt<4>(0he), stq_commit_head)
node stq_retry_idx_temp_vec_14 = and(_stq_retry_idx_T_14, _stq_retry_idx_temp_vec_T_14)
node _stq_retry_idx_temp_vec_T_15 = geq(UInt<4>(0hf), stq_commit_head)
node stq_retry_idx_temp_vec_15 = and(_stq_retry_idx_T_15, _stq_retry_idx_temp_vec_T_15)
node _stq_retry_idx_temp_vec_T_16 = geq(UInt<5>(0h10), stq_commit_head)
node stq_retry_idx_temp_vec_16 = and(_stq_retry_idx_T_16, _stq_retry_idx_temp_vec_T_16)
node _stq_retry_idx_temp_vec_T_17 = geq(UInt<5>(0h11), stq_commit_head)
node stq_retry_idx_temp_vec_17 = and(_stq_retry_idx_T_17, _stq_retry_idx_temp_vec_T_17)
node _stq_retry_idx_temp_vec_T_18 = geq(UInt<5>(0h12), stq_commit_head)
node stq_retry_idx_temp_vec_18 = and(_stq_retry_idx_T_18, _stq_retry_idx_temp_vec_T_18)
node _stq_retry_idx_temp_vec_T_19 = geq(UInt<5>(0h13), stq_commit_head)
node stq_retry_idx_temp_vec_19 = and(_stq_retry_idx_T_19, _stq_retry_idx_temp_vec_T_19)
node _stq_retry_idx_temp_vec_T_20 = geq(UInt<5>(0h14), stq_commit_head)
node stq_retry_idx_temp_vec_20 = and(_stq_retry_idx_T_20, _stq_retry_idx_temp_vec_T_20)
node _stq_retry_idx_temp_vec_T_21 = geq(UInt<5>(0h15), stq_commit_head)
node stq_retry_idx_temp_vec_21 = and(_stq_retry_idx_T_21, _stq_retry_idx_temp_vec_T_21)
node _stq_retry_idx_temp_vec_T_22 = geq(UInt<5>(0h16), stq_commit_head)
node stq_retry_idx_temp_vec_22 = and(_stq_retry_idx_T_22, _stq_retry_idx_temp_vec_T_22)
node _stq_retry_idx_temp_vec_T_23 = geq(UInt<5>(0h17), stq_commit_head)
node stq_retry_idx_temp_vec_23 = and(_stq_retry_idx_T_23, _stq_retry_idx_temp_vec_T_23)
node _stq_retry_idx_idx_T = mux(_stq_retry_idx_T_22, UInt<6>(0h36), UInt<6>(0h37))
node _stq_retry_idx_idx_T_1 = mux(_stq_retry_idx_T_21, UInt<6>(0h35), _stq_retry_idx_idx_T)
node _stq_retry_idx_idx_T_2 = mux(_stq_retry_idx_T_20, UInt<6>(0h34), _stq_retry_idx_idx_T_1)
node _stq_retry_idx_idx_T_3 = mux(_stq_retry_idx_T_19, UInt<6>(0h33), _stq_retry_idx_idx_T_2)
node _stq_retry_idx_idx_T_4 = mux(_stq_retry_idx_T_18, UInt<6>(0h32), _stq_retry_idx_idx_T_3)
node _stq_retry_idx_idx_T_5 = mux(_stq_retry_idx_T_17, UInt<6>(0h31), _stq_retry_idx_idx_T_4)
node _stq_retry_idx_idx_T_6 = mux(_stq_retry_idx_T_16, UInt<6>(0h30), _stq_retry_idx_idx_T_5)
node _stq_retry_idx_idx_T_7 = mux(_stq_retry_idx_T_15, UInt<6>(0h2f), _stq_retry_idx_idx_T_6)
node _stq_retry_idx_idx_T_8 = mux(_stq_retry_idx_T_14, UInt<6>(0h2e), _stq_retry_idx_idx_T_7)
node _stq_retry_idx_idx_T_9 = mux(_stq_retry_idx_T_13, UInt<6>(0h2d), _stq_retry_idx_idx_T_8)
node _stq_retry_idx_idx_T_10 = mux(_stq_retry_idx_T_12, UInt<6>(0h2c), _stq_retry_idx_idx_T_9)
node _stq_retry_idx_idx_T_11 = mux(_stq_retry_idx_T_11, UInt<6>(0h2b), _stq_retry_idx_idx_T_10)
node _stq_retry_idx_idx_T_12 = mux(_stq_retry_idx_T_10, UInt<6>(0h2a), _stq_retry_idx_idx_T_11)
node _stq_retry_idx_idx_T_13 = mux(_stq_retry_idx_T_9, UInt<6>(0h29), _stq_retry_idx_idx_T_12)
node _stq_retry_idx_idx_T_14 = mux(_stq_retry_idx_T_8, UInt<6>(0h28), _stq_retry_idx_idx_T_13)
node _stq_retry_idx_idx_T_15 = mux(_stq_retry_idx_T_7, UInt<6>(0h27), _stq_retry_idx_idx_T_14)
node _stq_retry_idx_idx_T_16 = mux(_stq_retry_idx_T_6, UInt<6>(0h26), _stq_retry_idx_idx_T_15)
node _stq_retry_idx_idx_T_17 = mux(_stq_retry_idx_T_5, UInt<6>(0h25), _stq_retry_idx_idx_T_16)
node _stq_retry_idx_idx_T_18 = mux(_stq_retry_idx_T_4, UInt<6>(0h24), _stq_retry_idx_idx_T_17)
node _stq_retry_idx_idx_T_19 = mux(_stq_retry_idx_T_3, UInt<6>(0h23), _stq_retry_idx_idx_T_18)
node _stq_retry_idx_idx_T_20 = mux(_stq_retry_idx_T_2, UInt<6>(0h22), _stq_retry_idx_idx_T_19)
node _stq_retry_idx_idx_T_21 = mux(_stq_retry_idx_T_1, UInt<6>(0h21), _stq_retry_idx_idx_T_20)
node _stq_retry_idx_idx_T_22 = mux(_stq_retry_idx_T, UInt<6>(0h20), _stq_retry_idx_idx_T_21)
node _stq_retry_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _stq_retry_idx_idx_T_22)
node _stq_retry_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _stq_retry_idx_idx_T_23)
node _stq_retry_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _stq_retry_idx_idx_T_24)
node _stq_retry_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _stq_retry_idx_idx_T_25)
node _stq_retry_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _stq_retry_idx_idx_T_26)
node _stq_retry_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _stq_retry_idx_idx_T_27)
node _stq_retry_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _stq_retry_idx_idx_T_28)
node _stq_retry_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _stq_retry_idx_idx_T_29)
node _stq_retry_idx_idx_T_31 = mux(stq_retry_idx_temp_vec_23, UInt<5>(0h17), _stq_retry_idx_idx_T_30)
node _stq_retry_idx_idx_T_32 = mux(stq_retry_idx_temp_vec_22, UInt<5>(0h16), _stq_retry_idx_idx_T_31)
node _stq_retry_idx_idx_T_33 = mux(stq_retry_idx_temp_vec_21, UInt<5>(0h15), _stq_retry_idx_idx_T_32)
node _stq_retry_idx_idx_T_34 = mux(stq_retry_idx_temp_vec_20, UInt<5>(0h14), _stq_retry_idx_idx_T_33)
node _stq_retry_idx_idx_T_35 = mux(stq_retry_idx_temp_vec_19, UInt<5>(0h13), _stq_retry_idx_idx_T_34)
node _stq_retry_idx_idx_T_36 = mux(stq_retry_idx_temp_vec_18, UInt<5>(0h12), _stq_retry_idx_idx_T_35)
node _stq_retry_idx_idx_T_37 = mux(stq_retry_idx_temp_vec_17, UInt<5>(0h11), _stq_retry_idx_idx_T_36)
node _stq_retry_idx_idx_T_38 = mux(stq_retry_idx_temp_vec_16, UInt<5>(0h10), _stq_retry_idx_idx_T_37)
node _stq_retry_idx_idx_T_39 = mux(stq_retry_idx_temp_vec_15, UInt<4>(0hf), _stq_retry_idx_idx_T_38)
node _stq_retry_idx_idx_T_40 = mux(stq_retry_idx_temp_vec_14, UInt<4>(0he), _stq_retry_idx_idx_T_39)
node _stq_retry_idx_idx_T_41 = mux(stq_retry_idx_temp_vec_13, UInt<4>(0hd), _stq_retry_idx_idx_T_40)
node _stq_retry_idx_idx_T_42 = mux(stq_retry_idx_temp_vec_12, UInt<4>(0hc), _stq_retry_idx_idx_T_41)
node _stq_retry_idx_idx_T_43 = mux(stq_retry_idx_temp_vec_11, UInt<4>(0hb), _stq_retry_idx_idx_T_42)
node _stq_retry_idx_idx_T_44 = mux(stq_retry_idx_temp_vec_10, UInt<4>(0ha), _stq_retry_idx_idx_T_43)
node _stq_retry_idx_idx_T_45 = mux(stq_retry_idx_temp_vec_9, UInt<4>(0h9), _stq_retry_idx_idx_T_44)
node _stq_retry_idx_idx_T_46 = mux(stq_retry_idx_temp_vec_8, UInt<4>(0h8), _stq_retry_idx_idx_T_45)
node _stq_retry_idx_idx_T_47 = mux(stq_retry_idx_temp_vec_7, UInt<3>(0h7), _stq_retry_idx_idx_T_46)
node _stq_retry_idx_idx_T_48 = mux(stq_retry_idx_temp_vec_6, UInt<3>(0h6), _stq_retry_idx_idx_T_47)
node _stq_retry_idx_idx_T_49 = mux(stq_retry_idx_temp_vec_5, UInt<3>(0h5), _stq_retry_idx_idx_T_48)
node _stq_retry_idx_idx_T_50 = mux(stq_retry_idx_temp_vec_4, UInt<3>(0h4), _stq_retry_idx_idx_T_49)
node _stq_retry_idx_idx_T_51 = mux(stq_retry_idx_temp_vec_3, UInt<2>(0h3), _stq_retry_idx_idx_T_50)
node _stq_retry_idx_idx_T_52 = mux(stq_retry_idx_temp_vec_2, UInt<2>(0h2), _stq_retry_idx_idx_T_51)
node _stq_retry_idx_idx_T_53 = mux(stq_retry_idx_temp_vec_1, UInt<1>(0h1), _stq_retry_idx_idx_T_52)
node stq_retry_idx_idx = mux(stq_retry_idx_temp_vec_0, UInt<1>(0h0), _stq_retry_idx_idx_T_53)
node _stq_retry_idx_T_24 = bits(stq_retry_idx_idx, 4, 0)
reg stq_retry_idx : UInt, clock
connect stq_retry_idx, _stq_retry_idx_T_24
node _stq_retry_e_T = or(stq_retry_idx, UInt<5>(0h0))
node _stq_retry_e_T_1 = bits(_stq_retry_e_T, 4, 0)
node ldq_wakeup_idx_block = or(block_load_mask[0], p1_block_load_mask[0])
node _ldq_wakeup_idx_T = eq(ldq[0].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_1 = and(ldq[0].bits.addr.valid, _ldq_wakeup_idx_T)
node _ldq_wakeup_idx_T_2 = eq(ldq[0].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_3 = and(_ldq_wakeup_idx_T_1, _ldq_wakeup_idx_T_2)
node _ldq_wakeup_idx_T_4 = eq(ldq[0].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_5 = and(_ldq_wakeup_idx_T_3, _ldq_wakeup_idx_T_4)
node _ldq_wakeup_idx_T_6 = eq(ldq_wakeup_idx_block, UInt<1>(0h0))
node _ldq_wakeup_idx_T_7 = and(_ldq_wakeup_idx_T_5, _ldq_wakeup_idx_T_6)
node ldq_wakeup_idx_block_1 = or(block_load_mask[1], p1_block_load_mask[1])
node _ldq_wakeup_idx_T_8 = eq(ldq[1].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_9 = and(ldq[1].bits.addr.valid, _ldq_wakeup_idx_T_8)
node _ldq_wakeup_idx_T_10 = eq(ldq[1].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_11 = and(_ldq_wakeup_idx_T_9, _ldq_wakeup_idx_T_10)
node _ldq_wakeup_idx_T_12 = eq(ldq[1].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_13 = and(_ldq_wakeup_idx_T_11, _ldq_wakeup_idx_T_12)
node _ldq_wakeup_idx_T_14 = eq(ldq_wakeup_idx_block_1, UInt<1>(0h0))
node _ldq_wakeup_idx_T_15 = and(_ldq_wakeup_idx_T_13, _ldq_wakeup_idx_T_14)
node ldq_wakeup_idx_block_2 = or(block_load_mask[2], p1_block_load_mask[2])
node _ldq_wakeup_idx_T_16 = eq(ldq[2].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_17 = and(ldq[2].bits.addr.valid, _ldq_wakeup_idx_T_16)
node _ldq_wakeup_idx_T_18 = eq(ldq[2].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_19 = and(_ldq_wakeup_idx_T_17, _ldq_wakeup_idx_T_18)
node _ldq_wakeup_idx_T_20 = eq(ldq[2].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_21 = and(_ldq_wakeup_idx_T_19, _ldq_wakeup_idx_T_20)
node _ldq_wakeup_idx_T_22 = eq(ldq_wakeup_idx_block_2, UInt<1>(0h0))
node _ldq_wakeup_idx_T_23 = and(_ldq_wakeup_idx_T_21, _ldq_wakeup_idx_T_22)
node ldq_wakeup_idx_block_3 = or(block_load_mask[3], p1_block_load_mask[3])
node _ldq_wakeup_idx_T_24 = eq(ldq[3].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_25 = and(ldq[3].bits.addr.valid, _ldq_wakeup_idx_T_24)
node _ldq_wakeup_idx_T_26 = eq(ldq[3].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_27 = and(_ldq_wakeup_idx_T_25, _ldq_wakeup_idx_T_26)
node _ldq_wakeup_idx_T_28 = eq(ldq[3].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_29 = and(_ldq_wakeup_idx_T_27, _ldq_wakeup_idx_T_28)
node _ldq_wakeup_idx_T_30 = eq(ldq_wakeup_idx_block_3, UInt<1>(0h0))
node _ldq_wakeup_idx_T_31 = and(_ldq_wakeup_idx_T_29, _ldq_wakeup_idx_T_30)
node ldq_wakeup_idx_block_4 = or(block_load_mask[4], p1_block_load_mask[4])
node _ldq_wakeup_idx_T_32 = eq(ldq[4].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_33 = and(ldq[4].bits.addr.valid, _ldq_wakeup_idx_T_32)
node _ldq_wakeup_idx_T_34 = eq(ldq[4].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_35 = and(_ldq_wakeup_idx_T_33, _ldq_wakeup_idx_T_34)
node _ldq_wakeup_idx_T_36 = eq(ldq[4].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_37 = and(_ldq_wakeup_idx_T_35, _ldq_wakeup_idx_T_36)
node _ldq_wakeup_idx_T_38 = eq(ldq_wakeup_idx_block_4, UInt<1>(0h0))
node _ldq_wakeup_idx_T_39 = and(_ldq_wakeup_idx_T_37, _ldq_wakeup_idx_T_38)
node ldq_wakeup_idx_block_5 = or(block_load_mask[5], p1_block_load_mask[5])
node _ldq_wakeup_idx_T_40 = eq(ldq[5].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_41 = and(ldq[5].bits.addr.valid, _ldq_wakeup_idx_T_40)
node _ldq_wakeup_idx_T_42 = eq(ldq[5].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_43 = and(_ldq_wakeup_idx_T_41, _ldq_wakeup_idx_T_42)
node _ldq_wakeup_idx_T_44 = eq(ldq[5].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_45 = and(_ldq_wakeup_idx_T_43, _ldq_wakeup_idx_T_44)
node _ldq_wakeup_idx_T_46 = eq(ldq_wakeup_idx_block_5, UInt<1>(0h0))
node _ldq_wakeup_idx_T_47 = and(_ldq_wakeup_idx_T_45, _ldq_wakeup_idx_T_46)
node ldq_wakeup_idx_block_6 = or(block_load_mask[6], p1_block_load_mask[6])
node _ldq_wakeup_idx_T_48 = eq(ldq[6].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_49 = and(ldq[6].bits.addr.valid, _ldq_wakeup_idx_T_48)
node _ldq_wakeup_idx_T_50 = eq(ldq[6].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_51 = and(_ldq_wakeup_idx_T_49, _ldq_wakeup_idx_T_50)
node _ldq_wakeup_idx_T_52 = eq(ldq[6].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_53 = and(_ldq_wakeup_idx_T_51, _ldq_wakeup_idx_T_52)
node _ldq_wakeup_idx_T_54 = eq(ldq_wakeup_idx_block_6, UInt<1>(0h0))
node _ldq_wakeup_idx_T_55 = and(_ldq_wakeup_idx_T_53, _ldq_wakeup_idx_T_54)
node ldq_wakeup_idx_block_7 = or(block_load_mask[7], p1_block_load_mask[7])
node _ldq_wakeup_idx_T_56 = eq(ldq[7].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_57 = and(ldq[7].bits.addr.valid, _ldq_wakeup_idx_T_56)
node _ldq_wakeup_idx_T_58 = eq(ldq[7].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_59 = and(_ldq_wakeup_idx_T_57, _ldq_wakeup_idx_T_58)
node _ldq_wakeup_idx_T_60 = eq(ldq[7].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_61 = and(_ldq_wakeup_idx_T_59, _ldq_wakeup_idx_T_60)
node _ldq_wakeup_idx_T_62 = eq(ldq_wakeup_idx_block_7, UInt<1>(0h0))
node _ldq_wakeup_idx_T_63 = and(_ldq_wakeup_idx_T_61, _ldq_wakeup_idx_T_62)
node ldq_wakeup_idx_block_8 = or(block_load_mask[8], p1_block_load_mask[8])
node _ldq_wakeup_idx_T_64 = eq(ldq[8].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_65 = and(ldq[8].bits.addr.valid, _ldq_wakeup_idx_T_64)
node _ldq_wakeup_idx_T_66 = eq(ldq[8].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_67 = and(_ldq_wakeup_idx_T_65, _ldq_wakeup_idx_T_66)
node _ldq_wakeup_idx_T_68 = eq(ldq[8].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_69 = and(_ldq_wakeup_idx_T_67, _ldq_wakeup_idx_T_68)
node _ldq_wakeup_idx_T_70 = eq(ldq_wakeup_idx_block_8, UInt<1>(0h0))
node _ldq_wakeup_idx_T_71 = and(_ldq_wakeup_idx_T_69, _ldq_wakeup_idx_T_70)
node ldq_wakeup_idx_block_9 = or(block_load_mask[9], p1_block_load_mask[9])
node _ldq_wakeup_idx_T_72 = eq(ldq[9].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_73 = and(ldq[9].bits.addr.valid, _ldq_wakeup_idx_T_72)
node _ldq_wakeup_idx_T_74 = eq(ldq[9].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_75 = and(_ldq_wakeup_idx_T_73, _ldq_wakeup_idx_T_74)
node _ldq_wakeup_idx_T_76 = eq(ldq[9].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_77 = and(_ldq_wakeup_idx_T_75, _ldq_wakeup_idx_T_76)
node _ldq_wakeup_idx_T_78 = eq(ldq_wakeup_idx_block_9, UInt<1>(0h0))
node _ldq_wakeup_idx_T_79 = and(_ldq_wakeup_idx_T_77, _ldq_wakeup_idx_T_78)
node ldq_wakeup_idx_block_10 = or(block_load_mask[10], p1_block_load_mask[10])
node _ldq_wakeup_idx_T_80 = eq(ldq[10].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_81 = and(ldq[10].bits.addr.valid, _ldq_wakeup_idx_T_80)
node _ldq_wakeup_idx_T_82 = eq(ldq[10].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_83 = and(_ldq_wakeup_idx_T_81, _ldq_wakeup_idx_T_82)
node _ldq_wakeup_idx_T_84 = eq(ldq[10].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_85 = and(_ldq_wakeup_idx_T_83, _ldq_wakeup_idx_T_84)
node _ldq_wakeup_idx_T_86 = eq(ldq_wakeup_idx_block_10, UInt<1>(0h0))
node _ldq_wakeup_idx_T_87 = and(_ldq_wakeup_idx_T_85, _ldq_wakeup_idx_T_86)
node ldq_wakeup_idx_block_11 = or(block_load_mask[11], p1_block_load_mask[11])
node _ldq_wakeup_idx_T_88 = eq(ldq[11].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_89 = and(ldq[11].bits.addr.valid, _ldq_wakeup_idx_T_88)
node _ldq_wakeup_idx_T_90 = eq(ldq[11].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_91 = and(_ldq_wakeup_idx_T_89, _ldq_wakeup_idx_T_90)
node _ldq_wakeup_idx_T_92 = eq(ldq[11].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_93 = and(_ldq_wakeup_idx_T_91, _ldq_wakeup_idx_T_92)
node _ldq_wakeup_idx_T_94 = eq(ldq_wakeup_idx_block_11, UInt<1>(0h0))
node _ldq_wakeup_idx_T_95 = and(_ldq_wakeup_idx_T_93, _ldq_wakeup_idx_T_94)
node ldq_wakeup_idx_block_12 = or(block_load_mask[12], p1_block_load_mask[12])
node _ldq_wakeup_idx_T_96 = eq(ldq[12].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_97 = and(ldq[12].bits.addr.valid, _ldq_wakeup_idx_T_96)
node _ldq_wakeup_idx_T_98 = eq(ldq[12].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_99 = and(_ldq_wakeup_idx_T_97, _ldq_wakeup_idx_T_98)
node _ldq_wakeup_idx_T_100 = eq(ldq[12].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_101 = and(_ldq_wakeup_idx_T_99, _ldq_wakeup_idx_T_100)
node _ldq_wakeup_idx_T_102 = eq(ldq_wakeup_idx_block_12, UInt<1>(0h0))
node _ldq_wakeup_idx_T_103 = and(_ldq_wakeup_idx_T_101, _ldq_wakeup_idx_T_102)
node ldq_wakeup_idx_block_13 = or(block_load_mask[13], p1_block_load_mask[13])
node _ldq_wakeup_idx_T_104 = eq(ldq[13].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_105 = and(ldq[13].bits.addr.valid, _ldq_wakeup_idx_T_104)
node _ldq_wakeup_idx_T_106 = eq(ldq[13].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_107 = and(_ldq_wakeup_idx_T_105, _ldq_wakeup_idx_T_106)
node _ldq_wakeup_idx_T_108 = eq(ldq[13].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_109 = and(_ldq_wakeup_idx_T_107, _ldq_wakeup_idx_T_108)
node _ldq_wakeup_idx_T_110 = eq(ldq_wakeup_idx_block_13, UInt<1>(0h0))
node _ldq_wakeup_idx_T_111 = and(_ldq_wakeup_idx_T_109, _ldq_wakeup_idx_T_110)
node ldq_wakeup_idx_block_14 = or(block_load_mask[14], p1_block_load_mask[14])
node _ldq_wakeup_idx_T_112 = eq(ldq[14].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_113 = and(ldq[14].bits.addr.valid, _ldq_wakeup_idx_T_112)
node _ldq_wakeup_idx_T_114 = eq(ldq[14].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_115 = and(_ldq_wakeup_idx_T_113, _ldq_wakeup_idx_T_114)
node _ldq_wakeup_idx_T_116 = eq(ldq[14].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_117 = and(_ldq_wakeup_idx_T_115, _ldq_wakeup_idx_T_116)
node _ldq_wakeup_idx_T_118 = eq(ldq_wakeup_idx_block_14, UInt<1>(0h0))
node _ldq_wakeup_idx_T_119 = and(_ldq_wakeup_idx_T_117, _ldq_wakeup_idx_T_118)
node ldq_wakeup_idx_block_15 = or(block_load_mask[15], p1_block_load_mask[15])
node _ldq_wakeup_idx_T_120 = eq(ldq[15].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_121 = and(ldq[15].bits.addr.valid, _ldq_wakeup_idx_T_120)
node _ldq_wakeup_idx_T_122 = eq(ldq[15].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_123 = and(_ldq_wakeup_idx_T_121, _ldq_wakeup_idx_T_122)
node _ldq_wakeup_idx_T_124 = eq(ldq[15].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_125 = and(_ldq_wakeup_idx_T_123, _ldq_wakeup_idx_T_124)
node _ldq_wakeup_idx_T_126 = eq(ldq_wakeup_idx_block_15, UInt<1>(0h0))
node _ldq_wakeup_idx_T_127 = and(_ldq_wakeup_idx_T_125, _ldq_wakeup_idx_T_126)
node ldq_wakeup_idx_block_16 = or(block_load_mask[16], p1_block_load_mask[16])
node _ldq_wakeup_idx_T_128 = eq(ldq[16].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_129 = and(ldq[16].bits.addr.valid, _ldq_wakeup_idx_T_128)
node _ldq_wakeup_idx_T_130 = eq(ldq[16].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_131 = and(_ldq_wakeup_idx_T_129, _ldq_wakeup_idx_T_130)
node _ldq_wakeup_idx_T_132 = eq(ldq[16].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_133 = and(_ldq_wakeup_idx_T_131, _ldq_wakeup_idx_T_132)
node _ldq_wakeup_idx_T_134 = eq(ldq_wakeup_idx_block_16, UInt<1>(0h0))
node _ldq_wakeup_idx_T_135 = and(_ldq_wakeup_idx_T_133, _ldq_wakeup_idx_T_134)
node ldq_wakeup_idx_block_17 = or(block_load_mask[17], p1_block_load_mask[17])
node _ldq_wakeup_idx_T_136 = eq(ldq[17].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_137 = and(ldq[17].bits.addr.valid, _ldq_wakeup_idx_T_136)
node _ldq_wakeup_idx_T_138 = eq(ldq[17].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_139 = and(_ldq_wakeup_idx_T_137, _ldq_wakeup_idx_T_138)
node _ldq_wakeup_idx_T_140 = eq(ldq[17].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_141 = and(_ldq_wakeup_idx_T_139, _ldq_wakeup_idx_T_140)
node _ldq_wakeup_idx_T_142 = eq(ldq_wakeup_idx_block_17, UInt<1>(0h0))
node _ldq_wakeup_idx_T_143 = and(_ldq_wakeup_idx_T_141, _ldq_wakeup_idx_T_142)
node ldq_wakeup_idx_block_18 = or(block_load_mask[18], p1_block_load_mask[18])
node _ldq_wakeup_idx_T_144 = eq(ldq[18].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_145 = and(ldq[18].bits.addr.valid, _ldq_wakeup_idx_T_144)
node _ldq_wakeup_idx_T_146 = eq(ldq[18].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_147 = and(_ldq_wakeup_idx_T_145, _ldq_wakeup_idx_T_146)
node _ldq_wakeup_idx_T_148 = eq(ldq[18].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_149 = and(_ldq_wakeup_idx_T_147, _ldq_wakeup_idx_T_148)
node _ldq_wakeup_idx_T_150 = eq(ldq_wakeup_idx_block_18, UInt<1>(0h0))
node _ldq_wakeup_idx_T_151 = and(_ldq_wakeup_idx_T_149, _ldq_wakeup_idx_T_150)
node ldq_wakeup_idx_block_19 = or(block_load_mask[19], p1_block_load_mask[19])
node _ldq_wakeup_idx_T_152 = eq(ldq[19].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_153 = and(ldq[19].bits.addr.valid, _ldq_wakeup_idx_T_152)
node _ldq_wakeup_idx_T_154 = eq(ldq[19].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_155 = and(_ldq_wakeup_idx_T_153, _ldq_wakeup_idx_T_154)
node _ldq_wakeup_idx_T_156 = eq(ldq[19].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_157 = and(_ldq_wakeup_idx_T_155, _ldq_wakeup_idx_T_156)
node _ldq_wakeup_idx_T_158 = eq(ldq_wakeup_idx_block_19, UInt<1>(0h0))
node _ldq_wakeup_idx_T_159 = and(_ldq_wakeup_idx_T_157, _ldq_wakeup_idx_T_158)
node ldq_wakeup_idx_block_20 = or(block_load_mask[20], p1_block_load_mask[20])
node _ldq_wakeup_idx_T_160 = eq(ldq[20].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_161 = and(ldq[20].bits.addr.valid, _ldq_wakeup_idx_T_160)
node _ldq_wakeup_idx_T_162 = eq(ldq[20].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_163 = and(_ldq_wakeup_idx_T_161, _ldq_wakeup_idx_T_162)
node _ldq_wakeup_idx_T_164 = eq(ldq[20].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_165 = and(_ldq_wakeup_idx_T_163, _ldq_wakeup_idx_T_164)
node _ldq_wakeup_idx_T_166 = eq(ldq_wakeup_idx_block_20, UInt<1>(0h0))
node _ldq_wakeup_idx_T_167 = and(_ldq_wakeup_idx_T_165, _ldq_wakeup_idx_T_166)
node ldq_wakeup_idx_block_21 = or(block_load_mask[21], p1_block_load_mask[21])
node _ldq_wakeup_idx_T_168 = eq(ldq[21].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_169 = and(ldq[21].bits.addr.valid, _ldq_wakeup_idx_T_168)
node _ldq_wakeup_idx_T_170 = eq(ldq[21].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_171 = and(_ldq_wakeup_idx_T_169, _ldq_wakeup_idx_T_170)
node _ldq_wakeup_idx_T_172 = eq(ldq[21].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_173 = and(_ldq_wakeup_idx_T_171, _ldq_wakeup_idx_T_172)
node _ldq_wakeup_idx_T_174 = eq(ldq_wakeup_idx_block_21, UInt<1>(0h0))
node _ldq_wakeup_idx_T_175 = and(_ldq_wakeup_idx_T_173, _ldq_wakeup_idx_T_174)
node ldq_wakeup_idx_block_22 = or(block_load_mask[22], p1_block_load_mask[22])
node _ldq_wakeup_idx_T_176 = eq(ldq[22].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_177 = and(ldq[22].bits.addr.valid, _ldq_wakeup_idx_T_176)
node _ldq_wakeup_idx_T_178 = eq(ldq[22].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_179 = and(_ldq_wakeup_idx_T_177, _ldq_wakeup_idx_T_178)
node _ldq_wakeup_idx_T_180 = eq(ldq[22].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_181 = and(_ldq_wakeup_idx_T_179, _ldq_wakeup_idx_T_180)
node _ldq_wakeup_idx_T_182 = eq(ldq_wakeup_idx_block_22, UInt<1>(0h0))
node _ldq_wakeup_idx_T_183 = and(_ldq_wakeup_idx_T_181, _ldq_wakeup_idx_T_182)
node ldq_wakeup_idx_block_23 = or(block_load_mask[23], p1_block_load_mask[23])
node _ldq_wakeup_idx_T_184 = eq(ldq[23].bits.executed, UInt<1>(0h0))
node _ldq_wakeup_idx_T_185 = and(ldq[23].bits.addr.valid, _ldq_wakeup_idx_T_184)
node _ldq_wakeup_idx_T_186 = eq(ldq[23].bits.succeeded, UInt<1>(0h0))
node _ldq_wakeup_idx_T_187 = and(_ldq_wakeup_idx_T_185, _ldq_wakeup_idx_T_186)
node _ldq_wakeup_idx_T_188 = eq(ldq[23].bits.addr_is_virtual, UInt<1>(0h0))
node _ldq_wakeup_idx_T_189 = and(_ldq_wakeup_idx_T_187, _ldq_wakeup_idx_T_188)
node _ldq_wakeup_idx_T_190 = eq(ldq_wakeup_idx_block_23, UInt<1>(0h0))
node _ldq_wakeup_idx_T_191 = and(_ldq_wakeup_idx_T_189, _ldq_wakeup_idx_T_190)
node _ldq_wakeup_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head)
node ldq_wakeup_idx_temp_vec_0 = and(_ldq_wakeup_idx_T_7, _ldq_wakeup_idx_temp_vec_T)
node _ldq_wakeup_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head)
node ldq_wakeup_idx_temp_vec_1 = and(_ldq_wakeup_idx_T_15, _ldq_wakeup_idx_temp_vec_T_1)
node _ldq_wakeup_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head)
node ldq_wakeup_idx_temp_vec_2 = and(_ldq_wakeup_idx_T_23, _ldq_wakeup_idx_temp_vec_T_2)
node _ldq_wakeup_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head)
node ldq_wakeup_idx_temp_vec_3 = and(_ldq_wakeup_idx_T_31, _ldq_wakeup_idx_temp_vec_T_3)
node _ldq_wakeup_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head)
node ldq_wakeup_idx_temp_vec_4 = and(_ldq_wakeup_idx_T_39, _ldq_wakeup_idx_temp_vec_T_4)
node _ldq_wakeup_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head)
node ldq_wakeup_idx_temp_vec_5 = and(_ldq_wakeup_idx_T_47, _ldq_wakeup_idx_temp_vec_T_5)
node _ldq_wakeup_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head)
node ldq_wakeup_idx_temp_vec_6 = and(_ldq_wakeup_idx_T_55, _ldq_wakeup_idx_temp_vec_T_6)
node _ldq_wakeup_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head)
node ldq_wakeup_idx_temp_vec_7 = and(_ldq_wakeup_idx_T_63, _ldq_wakeup_idx_temp_vec_T_7)
node _ldq_wakeup_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head)
node ldq_wakeup_idx_temp_vec_8 = and(_ldq_wakeup_idx_T_71, _ldq_wakeup_idx_temp_vec_T_8)
node _ldq_wakeup_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head)
node ldq_wakeup_idx_temp_vec_9 = and(_ldq_wakeup_idx_T_79, _ldq_wakeup_idx_temp_vec_T_9)
node _ldq_wakeup_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head)
node ldq_wakeup_idx_temp_vec_10 = and(_ldq_wakeup_idx_T_87, _ldq_wakeup_idx_temp_vec_T_10)
node _ldq_wakeup_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head)
node ldq_wakeup_idx_temp_vec_11 = and(_ldq_wakeup_idx_T_95, _ldq_wakeup_idx_temp_vec_T_11)
node _ldq_wakeup_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head)
node ldq_wakeup_idx_temp_vec_12 = and(_ldq_wakeup_idx_T_103, _ldq_wakeup_idx_temp_vec_T_12)
node _ldq_wakeup_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head)
node ldq_wakeup_idx_temp_vec_13 = and(_ldq_wakeup_idx_T_111, _ldq_wakeup_idx_temp_vec_T_13)
node _ldq_wakeup_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head)
node ldq_wakeup_idx_temp_vec_14 = and(_ldq_wakeup_idx_T_119, _ldq_wakeup_idx_temp_vec_T_14)
node _ldq_wakeup_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head)
node ldq_wakeup_idx_temp_vec_15 = and(_ldq_wakeup_idx_T_127, _ldq_wakeup_idx_temp_vec_T_15)
node _ldq_wakeup_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head)
node ldq_wakeup_idx_temp_vec_16 = and(_ldq_wakeup_idx_T_135, _ldq_wakeup_idx_temp_vec_T_16)
node _ldq_wakeup_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head)
node ldq_wakeup_idx_temp_vec_17 = and(_ldq_wakeup_idx_T_143, _ldq_wakeup_idx_temp_vec_T_17)
node _ldq_wakeup_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head)
node ldq_wakeup_idx_temp_vec_18 = and(_ldq_wakeup_idx_T_151, _ldq_wakeup_idx_temp_vec_T_18)
node _ldq_wakeup_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head)
node ldq_wakeup_idx_temp_vec_19 = and(_ldq_wakeup_idx_T_159, _ldq_wakeup_idx_temp_vec_T_19)
node _ldq_wakeup_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head)
node ldq_wakeup_idx_temp_vec_20 = and(_ldq_wakeup_idx_T_167, _ldq_wakeup_idx_temp_vec_T_20)
node _ldq_wakeup_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head)
node ldq_wakeup_idx_temp_vec_21 = and(_ldq_wakeup_idx_T_175, _ldq_wakeup_idx_temp_vec_T_21)
node _ldq_wakeup_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head)
node ldq_wakeup_idx_temp_vec_22 = and(_ldq_wakeup_idx_T_183, _ldq_wakeup_idx_temp_vec_T_22)
node _ldq_wakeup_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head)
node ldq_wakeup_idx_temp_vec_23 = and(_ldq_wakeup_idx_T_191, _ldq_wakeup_idx_temp_vec_T_23)
node _ldq_wakeup_idx_idx_T = mux(_ldq_wakeup_idx_T_183, UInt<6>(0h36), UInt<6>(0h37))
node _ldq_wakeup_idx_idx_T_1 = mux(_ldq_wakeup_idx_T_175, UInt<6>(0h35), _ldq_wakeup_idx_idx_T)
node _ldq_wakeup_idx_idx_T_2 = mux(_ldq_wakeup_idx_T_167, UInt<6>(0h34), _ldq_wakeup_idx_idx_T_1)
node _ldq_wakeup_idx_idx_T_3 = mux(_ldq_wakeup_idx_T_159, UInt<6>(0h33), _ldq_wakeup_idx_idx_T_2)
node _ldq_wakeup_idx_idx_T_4 = mux(_ldq_wakeup_idx_T_151, UInt<6>(0h32), _ldq_wakeup_idx_idx_T_3)
node _ldq_wakeup_idx_idx_T_5 = mux(_ldq_wakeup_idx_T_143, UInt<6>(0h31), _ldq_wakeup_idx_idx_T_4)
node _ldq_wakeup_idx_idx_T_6 = mux(_ldq_wakeup_idx_T_135, UInt<6>(0h30), _ldq_wakeup_idx_idx_T_5)
node _ldq_wakeup_idx_idx_T_7 = mux(_ldq_wakeup_idx_T_127, UInt<6>(0h2f), _ldq_wakeup_idx_idx_T_6)
node _ldq_wakeup_idx_idx_T_8 = mux(_ldq_wakeup_idx_T_119, UInt<6>(0h2e), _ldq_wakeup_idx_idx_T_7)
node _ldq_wakeup_idx_idx_T_9 = mux(_ldq_wakeup_idx_T_111, UInt<6>(0h2d), _ldq_wakeup_idx_idx_T_8)
node _ldq_wakeup_idx_idx_T_10 = mux(_ldq_wakeup_idx_T_103, UInt<6>(0h2c), _ldq_wakeup_idx_idx_T_9)
node _ldq_wakeup_idx_idx_T_11 = mux(_ldq_wakeup_idx_T_95, UInt<6>(0h2b), _ldq_wakeup_idx_idx_T_10)
node _ldq_wakeup_idx_idx_T_12 = mux(_ldq_wakeup_idx_T_87, UInt<6>(0h2a), _ldq_wakeup_idx_idx_T_11)
node _ldq_wakeup_idx_idx_T_13 = mux(_ldq_wakeup_idx_T_79, UInt<6>(0h29), _ldq_wakeup_idx_idx_T_12)
node _ldq_wakeup_idx_idx_T_14 = mux(_ldq_wakeup_idx_T_71, UInt<6>(0h28), _ldq_wakeup_idx_idx_T_13)
node _ldq_wakeup_idx_idx_T_15 = mux(_ldq_wakeup_idx_T_63, UInt<6>(0h27), _ldq_wakeup_idx_idx_T_14)
node _ldq_wakeup_idx_idx_T_16 = mux(_ldq_wakeup_idx_T_55, UInt<6>(0h26), _ldq_wakeup_idx_idx_T_15)
node _ldq_wakeup_idx_idx_T_17 = mux(_ldq_wakeup_idx_T_47, UInt<6>(0h25), _ldq_wakeup_idx_idx_T_16)
node _ldq_wakeup_idx_idx_T_18 = mux(_ldq_wakeup_idx_T_39, UInt<6>(0h24), _ldq_wakeup_idx_idx_T_17)
node _ldq_wakeup_idx_idx_T_19 = mux(_ldq_wakeup_idx_T_31, UInt<6>(0h23), _ldq_wakeup_idx_idx_T_18)
node _ldq_wakeup_idx_idx_T_20 = mux(_ldq_wakeup_idx_T_23, UInt<6>(0h22), _ldq_wakeup_idx_idx_T_19)
node _ldq_wakeup_idx_idx_T_21 = mux(_ldq_wakeup_idx_T_15, UInt<6>(0h21), _ldq_wakeup_idx_idx_T_20)
node _ldq_wakeup_idx_idx_T_22 = mux(_ldq_wakeup_idx_T_7, UInt<6>(0h20), _ldq_wakeup_idx_idx_T_21)
node _ldq_wakeup_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _ldq_wakeup_idx_idx_T_22)
node _ldq_wakeup_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _ldq_wakeup_idx_idx_T_23)
node _ldq_wakeup_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _ldq_wakeup_idx_idx_T_24)
node _ldq_wakeup_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _ldq_wakeup_idx_idx_T_25)
node _ldq_wakeup_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _ldq_wakeup_idx_idx_T_26)
node _ldq_wakeup_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _ldq_wakeup_idx_idx_T_27)
node _ldq_wakeup_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _ldq_wakeup_idx_idx_T_28)
node _ldq_wakeup_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _ldq_wakeup_idx_idx_T_29)
node _ldq_wakeup_idx_idx_T_31 = mux(ldq_wakeup_idx_temp_vec_23, UInt<5>(0h17), _ldq_wakeup_idx_idx_T_30)
node _ldq_wakeup_idx_idx_T_32 = mux(ldq_wakeup_idx_temp_vec_22, UInt<5>(0h16), _ldq_wakeup_idx_idx_T_31)
node _ldq_wakeup_idx_idx_T_33 = mux(ldq_wakeup_idx_temp_vec_21, UInt<5>(0h15), _ldq_wakeup_idx_idx_T_32)
node _ldq_wakeup_idx_idx_T_34 = mux(ldq_wakeup_idx_temp_vec_20, UInt<5>(0h14), _ldq_wakeup_idx_idx_T_33)
node _ldq_wakeup_idx_idx_T_35 = mux(ldq_wakeup_idx_temp_vec_19, UInt<5>(0h13), _ldq_wakeup_idx_idx_T_34)
node _ldq_wakeup_idx_idx_T_36 = mux(ldq_wakeup_idx_temp_vec_18, UInt<5>(0h12), _ldq_wakeup_idx_idx_T_35)
node _ldq_wakeup_idx_idx_T_37 = mux(ldq_wakeup_idx_temp_vec_17, UInt<5>(0h11), _ldq_wakeup_idx_idx_T_36)
node _ldq_wakeup_idx_idx_T_38 = mux(ldq_wakeup_idx_temp_vec_16, UInt<5>(0h10), _ldq_wakeup_idx_idx_T_37)
node _ldq_wakeup_idx_idx_T_39 = mux(ldq_wakeup_idx_temp_vec_15, UInt<4>(0hf), _ldq_wakeup_idx_idx_T_38)
node _ldq_wakeup_idx_idx_T_40 = mux(ldq_wakeup_idx_temp_vec_14, UInt<4>(0he), _ldq_wakeup_idx_idx_T_39)
node _ldq_wakeup_idx_idx_T_41 = mux(ldq_wakeup_idx_temp_vec_13, UInt<4>(0hd), _ldq_wakeup_idx_idx_T_40)
node _ldq_wakeup_idx_idx_T_42 = mux(ldq_wakeup_idx_temp_vec_12, UInt<4>(0hc), _ldq_wakeup_idx_idx_T_41)
node _ldq_wakeup_idx_idx_T_43 = mux(ldq_wakeup_idx_temp_vec_11, UInt<4>(0hb), _ldq_wakeup_idx_idx_T_42)
node _ldq_wakeup_idx_idx_T_44 = mux(ldq_wakeup_idx_temp_vec_10, UInt<4>(0ha), _ldq_wakeup_idx_idx_T_43)
node _ldq_wakeup_idx_idx_T_45 = mux(ldq_wakeup_idx_temp_vec_9, UInt<4>(0h9), _ldq_wakeup_idx_idx_T_44)
node _ldq_wakeup_idx_idx_T_46 = mux(ldq_wakeup_idx_temp_vec_8, UInt<4>(0h8), _ldq_wakeup_idx_idx_T_45)
node _ldq_wakeup_idx_idx_T_47 = mux(ldq_wakeup_idx_temp_vec_7, UInt<3>(0h7), _ldq_wakeup_idx_idx_T_46)
node _ldq_wakeup_idx_idx_T_48 = mux(ldq_wakeup_idx_temp_vec_6, UInt<3>(0h6), _ldq_wakeup_idx_idx_T_47)
node _ldq_wakeup_idx_idx_T_49 = mux(ldq_wakeup_idx_temp_vec_5, UInt<3>(0h5), _ldq_wakeup_idx_idx_T_48)
node _ldq_wakeup_idx_idx_T_50 = mux(ldq_wakeup_idx_temp_vec_4, UInt<3>(0h4), _ldq_wakeup_idx_idx_T_49)
node _ldq_wakeup_idx_idx_T_51 = mux(ldq_wakeup_idx_temp_vec_3, UInt<2>(0h3), _ldq_wakeup_idx_idx_T_50)
node _ldq_wakeup_idx_idx_T_52 = mux(ldq_wakeup_idx_temp_vec_2, UInt<2>(0h2), _ldq_wakeup_idx_idx_T_51)
node _ldq_wakeup_idx_idx_T_53 = mux(ldq_wakeup_idx_temp_vec_1, UInt<1>(0h1), _ldq_wakeup_idx_idx_T_52)
node ldq_wakeup_idx_idx = mux(ldq_wakeup_idx_temp_vec_0, UInt<1>(0h0), _ldq_wakeup_idx_idx_T_53)
node _ldq_wakeup_idx_T_192 = bits(ldq_wakeup_idx_idx, 4, 0)
reg ldq_wakeup_idx : UInt, clock
connect ldq_wakeup_idx, _ldq_wakeup_idx_T_192
node _ldq_wakeup_e_T = or(ldq_wakeup_idx, UInt<5>(0h0))
node _ldq_wakeup_e_T_1 = bits(_ldq_wakeup_e_T, 4, 0)
node _can_fire_load_incoming_T = and(exe_req[0].valid, exe_req[0].bits.uop.ctrl.is_load)
wire can_fire_load_incoming : UInt<1>[1]
connect can_fire_load_incoming[0], _can_fire_load_incoming_T
node _can_fire_stad_incoming_T = and(exe_req[0].valid, exe_req[0].bits.uop.ctrl.is_sta)
node _can_fire_stad_incoming_T_1 = and(_can_fire_stad_incoming_T, exe_req[0].bits.uop.ctrl.is_std)
wire can_fire_stad_incoming : UInt<1>[1]
connect can_fire_stad_incoming[0], _can_fire_stad_incoming_T_1
node _can_fire_sta_incoming_T = and(exe_req[0].valid, exe_req[0].bits.uop.ctrl.is_sta)
node _can_fire_sta_incoming_T_1 = eq(exe_req[0].bits.uop.ctrl.is_std, UInt<1>(0h0))
node _can_fire_sta_incoming_T_2 = and(_can_fire_sta_incoming_T, _can_fire_sta_incoming_T_1)
wire can_fire_sta_incoming : UInt<1>[1]
connect can_fire_sta_incoming[0], _can_fire_sta_incoming_T_2
node _can_fire_std_incoming_T = and(exe_req[0].valid, exe_req[0].bits.uop.ctrl.is_std)
node _can_fire_std_incoming_T_1 = eq(exe_req[0].bits.uop.ctrl.is_sta, UInt<1>(0h0))
node _can_fire_std_incoming_T_2 = and(_can_fire_std_incoming_T, _can_fire_std_incoming_T_1)
wire can_fire_std_incoming : UInt<1>[1]
connect can_fire_std_incoming[0], _can_fire_std_incoming_T_2
node _can_fire_sfence_T = and(exe_req[0].valid, exe_req[0].bits.sfence.valid)
wire can_fire_sfence : UInt<1>[1]
connect can_fire_sfence[0], _can_fire_sfence_T
node _can_fire_release_T = and(UInt<1>(0h1), io.dmem.release.valid)
wire can_fire_release : UInt<1>[1]
connect can_fire_release[0], _can_fire_release_T
connect io.dmem.release.ready, will_fire_release[0]
node _can_fire_load_retry_T = and(ldq[_ldq_retry_e_T_1].valid, ldq[_ldq_retry_e_T_1].bits.addr.valid)
node _can_fire_load_retry_T_1 = and(_can_fire_load_retry_T, ldq[_ldq_retry_e_T_1].bits.addr_is_virtual)
node _can_fire_load_retry_T_2 = or(ldq_retry_idx, UInt<5>(0h0))
node _can_fire_load_retry_T_3 = bits(_can_fire_load_retry_T_2, 4, 0)
node _can_fire_load_retry_T_4 = eq(p1_block_load_mask[_can_fire_load_retry_T_3], UInt<1>(0h0))
node _can_fire_load_retry_T_5 = and(_can_fire_load_retry_T_1, _can_fire_load_retry_T_4)
node _can_fire_load_retry_T_6 = or(ldq_retry_idx, UInt<5>(0h0))
node _can_fire_load_retry_T_7 = bits(_can_fire_load_retry_T_6, 4, 0)
node _can_fire_load_retry_T_8 = eq(p2_block_load_mask[_can_fire_load_retry_T_7], UInt<1>(0h0))
node _can_fire_load_retry_T_9 = and(_can_fire_load_retry_T_5, _can_fire_load_retry_T_8)
reg can_fire_load_retry_REG : UInt<1>, clock
connect can_fire_load_retry_REG, dtlb.io.miss_rdy
node _can_fire_load_retry_T_10 = and(_can_fire_load_retry_T_9, can_fire_load_retry_REG)
node _can_fire_load_retry_T_11 = eq(store_needs_order, UInt<1>(0h0))
node _can_fire_load_retry_T_12 = and(_can_fire_load_retry_T_10, _can_fire_load_retry_T_11)
node _can_fire_load_retry_T_13 = and(_can_fire_load_retry_T_12, UInt<1>(0h1))
node _can_fire_load_retry_T_14 = eq(ldq[_ldq_retry_e_T_1].bits.order_fail, UInt<1>(0h0))
node _can_fire_load_retry_T_15 = and(_can_fire_load_retry_T_13, _can_fire_load_retry_T_14)
wire can_fire_load_retry : UInt<1>[1]
connect can_fire_load_retry[0], _can_fire_load_retry_T_15
node _can_fire_sta_retry_T = and(stq[_stq_retry_e_T_1].valid, stq[_stq_retry_e_T_1].bits.addr.valid)
node _can_fire_sta_retry_T_1 = and(_can_fire_sta_retry_T, stq[_stq_retry_e_T_1].bits.addr_is_virtual)
node _can_fire_sta_retry_T_2 = and(_can_fire_sta_retry_T_1, UInt<1>(0h1))
reg can_fire_sta_retry_REG : UInt<1>, clock
connect can_fire_sta_retry_REG, dtlb.io.miss_rdy
node _can_fire_sta_retry_T_3 = and(_can_fire_sta_retry_T_2, can_fire_sta_retry_REG)
node _can_fire_sta_retry_T_4 = and(UInt<1>(0h0), can_fire_std_incoming[0])
node _can_fire_sta_retry_T_5 = eq(stq_incoming_idx[0], stq_retry_idx)
node _can_fire_sta_retry_T_6 = and(_can_fire_sta_retry_T_4, _can_fire_sta_retry_T_5)
wire _can_fire_sta_retry_WIRE : UInt<1>[1]
connect _can_fire_sta_retry_WIRE[0], _can_fire_sta_retry_T_6
node _can_fire_sta_retry_T_7 = eq(_can_fire_sta_retry_WIRE[0], UInt<1>(0h0))
node _can_fire_sta_retry_T_8 = and(_can_fire_sta_retry_T_3, _can_fire_sta_retry_T_7)
wire can_fire_sta_retry : UInt<1>[1]
connect can_fire_sta_retry[0], _can_fire_sta_retry_T_8
node _can_fire_store_commit_T = eq(stq[stq_execute_head].bits.uop.is_fence, UInt<1>(0h0))
node _can_fire_store_commit_T_1 = and(stq[stq_execute_head].valid, _can_fire_store_commit_T)
node _can_fire_store_commit_T_2 = eq(mem_xcpt_valid, UInt<1>(0h0))
node _can_fire_store_commit_T_3 = and(_can_fire_store_commit_T_1, _can_fire_store_commit_T_2)
node _can_fire_store_commit_T_4 = eq(stq[stq_execute_head].bits.uop.exception, UInt<1>(0h0))
node _can_fire_store_commit_T_5 = and(_can_fire_store_commit_T_3, _can_fire_store_commit_T_4)
node _can_fire_store_commit_T_6 = and(_can_fire_store_commit_T_5, UInt<1>(0h1))
node _can_fire_store_commit_T_7 = and(stq[stq_execute_head].bits.uop.is_amo, stq[stq_execute_head].bits.addr.valid)
node _can_fire_store_commit_T_8 = eq(stq[stq_execute_head].bits.addr_is_virtual, UInt<1>(0h0))
node _can_fire_store_commit_T_9 = and(_can_fire_store_commit_T_7, _can_fire_store_commit_T_8)
node _can_fire_store_commit_T_10 = and(_can_fire_store_commit_T_9, stq[stq_execute_head].bits.data.valid)
node _can_fire_store_commit_T_11 = or(stq[stq_execute_head].bits.committed, _can_fire_store_commit_T_10)
node _can_fire_store_commit_T_12 = and(_can_fire_store_commit_T_6, _can_fire_store_commit_T_11)
wire can_fire_store_commit : UInt<1>[1]
connect can_fire_store_commit[0], _can_fire_store_commit_T_12
wire block_load_wakeup : UInt<1>
connect block_load_wakeup, UInt<1>(0h0)
node _can_fire_load_wakeup_T = and(ldq[_ldq_wakeup_e_T_1].valid, ldq[_ldq_wakeup_e_T_1].bits.addr.valid)
node _can_fire_load_wakeup_T_1 = eq(ldq[_ldq_wakeup_e_T_1].bits.succeeded, UInt<1>(0h0))
node _can_fire_load_wakeup_T_2 = and(_can_fire_load_wakeup_T, _can_fire_load_wakeup_T_1)
node _can_fire_load_wakeup_T_3 = eq(ldq[_ldq_wakeup_e_T_1].bits.addr_is_virtual, UInt<1>(0h0))
node _can_fire_load_wakeup_T_4 = and(_can_fire_load_wakeup_T_2, _can_fire_load_wakeup_T_3)
node _can_fire_load_wakeup_T_5 = eq(ldq[_ldq_wakeup_e_T_1].bits.executed, UInt<1>(0h0))
node _can_fire_load_wakeup_T_6 = and(_can_fire_load_wakeup_T_4, _can_fire_load_wakeup_T_5)
node _can_fire_load_wakeup_T_7 = eq(ldq[_ldq_wakeup_e_T_1].bits.order_fail, UInt<1>(0h0))
node _can_fire_load_wakeup_T_8 = and(_can_fire_load_wakeup_T_6, _can_fire_load_wakeup_T_7)
node _can_fire_load_wakeup_T_9 = or(ldq_wakeup_idx, UInt<5>(0h0))
node _can_fire_load_wakeup_T_10 = bits(_can_fire_load_wakeup_T_9, 4, 0)
node _can_fire_load_wakeup_T_11 = eq(p1_block_load_mask[_can_fire_load_wakeup_T_10], UInt<1>(0h0))
node _can_fire_load_wakeup_T_12 = and(_can_fire_load_wakeup_T_8, _can_fire_load_wakeup_T_11)
node _can_fire_load_wakeup_T_13 = or(ldq_wakeup_idx, UInt<5>(0h0))
node _can_fire_load_wakeup_T_14 = bits(_can_fire_load_wakeup_T_13, 4, 0)
node _can_fire_load_wakeup_T_15 = eq(p2_block_load_mask[_can_fire_load_wakeup_T_14], UInt<1>(0h0))
node _can_fire_load_wakeup_T_16 = and(_can_fire_load_wakeup_T_12, _can_fire_load_wakeup_T_15)
node _can_fire_load_wakeup_T_17 = eq(store_needs_order, UInt<1>(0h0))
node _can_fire_load_wakeup_T_18 = and(_can_fire_load_wakeup_T_16, _can_fire_load_wakeup_T_17)
node _can_fire_load_wakeup_T_19 = eq(block_load_wakeup, UInt<1>(0h0))
node _can_fire_load_wakeup_T_20 = and(_can_fire_load_wakeup_T_18, _can_fire_load_wakeup_T_19)
node _can_fire_load_wakeup_T_21 = and(_can_fire_load_wakeup_T_20, UInt<1>(0h1))
node _can_fire_load_wakeup_T_22 = eq(ldq[_ldq_wakeup_e_T_1].bits.addr_is_uncacheable, UInt<1>(0h0))
node _can_fire_load_wakeup_T_23 = eq(ldq_head, ldq_wakeup_idx)
node _can_fire_load_wakeup_T_24 = and(io.core.commit_load_at_rob_head, _can_fire_load_wakeup_T_23)
node _can_fire_load_wakeup_T_25 = eq(ldq[_ldq_wakeup_e_T_1].bits.st_dep_mask, UInt<1>(0h0))
node _can_fire_load_wakeup_T_26 = and(_can_fire_load_wakeup_T_24, _can_fire_load_wakeup_T_25)
node _can_fire_load_wakeup_T_27 = or(_can_fire_load_wakeup_T_22, _can_fire_load_wakeup_T_26)
node _can_fire_load_wakeup_T_28 = and(_can_fire_load_wakeup_T_21, _can_fire_load_wakeup_T_27)
wire can_fire_load_wakeup : UInt<1>[1]
connect can_fire_load_wakeup[0], _can_fire_load_wakeup_T_28
wire _can_fire_hella_incoming_WIRE : UInt<1>[1]
connect _can_fire_hella_incoming_WIRE[0], UInt<1>(0h0)
wire can_fire_hella_incoming : UInt<1>[1]
connect can_fire_hella_incoming, _can_fire_hella_incoming_WIRE
wire _can_fire_hella_wakeup_WIRE : UInt<1>[1]
connect _can_fire_hella_wakeup_WIRE[0], UInt<1>(0h0)
wire can_fire_hella_wakeup : UInt<1>[1]
connect can_fire_hella_wakeup, _can_fire_hella_wakeup_WIRE
wire exe_tlb_valid : UInt<1>[1]
node _will_fire_load_incoming_0_will_fire_T = eq(UInt<1>(0h1), UInt<1>(0h0))
node _will_fire_load_incoming_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_incoming_0_will_fire_T)
node _will_fire_load_incoming_0_will_fire_T_2 = eq(_will_fire_load_incoming_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_load_incoming_0_will_fire_T_3 = and(can_fire_load_incoming[0], _will_fire_load_incoming_0_will_fire_T_2)
node _will_fire_load_incoming_0_will_fire_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _will_fire_load_incoming_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_incoming_0_will_fire_T_4)
node _will_fire_load_incoming_0_will_fire_T_6 = eq(_will_fire_load_incoming_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_load_incoming_0_will_fire_T_7 = and(_will_fire_load_incoming_0_will_fire_T_3, _will_fire_load_incoming_0_will_fire_T_6)
node _will_fire_load_incoming_0_will_fire_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _will_fire_load_incoming_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_incoming_0_will_fire_T_8)
node _will_fire_load_incoming_0_will_fire_T_10 = eq(_will_fire_load_incoming_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_load_incoming_0_will_fire_T_11 = and(_will_fire_load_incoming_0_will_fire_T_7, _will_fire_load_incoming_0_will_fire_T_10)
node _will_fire_load_incoming_0_will_fire_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _will_fire_load_incoming_0_will_fire_T_13 = and(UInt<1>(0h0), _will_fire_load_incoming_0_will_fire_T_12)
node _will_fire_load_incoming_0_will_fire_T_14 = eq(_will_fire_load_incoming_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_load_incoming_0_will_fire = and(_will_fire_load_incoming_0_will_fire_T_11, _will_fire_load_incoming_0_will_fire_T_14)
node _will_fire_load_incoming_0_T = and(will_fire_load_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_load_incoming_0_T_1 = eq(_will_fire_load_incoming_0_T, UInt<1>(0h0))
node _will_fire_load_incoming_0_T_2 = and(UInt<1>(0h1), _will_fire_load_incoming_0_T_1)
node _will_fire_load_incoming_0_T_3 = and(will_fire_load_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_load_incoming_0_T_4 = eq(_will_fire_load_incoming_0_T_3, UInt<1>(0h0))
node _will_fire_load_incoming_0_T_5 = and(UInt<1>(0h1), _will_fire_load_incoming_0_T_4)
node _will_fire_load_incoming_0_T_6 = and(will_fire_load_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_load_incoming_0_T_7 = eq(_will_fire_load_incoming_0_T_6, UInt<1>(0h0))
node _will_fire_load_incoming_0_T_8 = and(UInt<1>(0h1), _will_fire_load_incoming_0_T_7)
node _will_fire_load_incoming_0_T_9 = and(will_fire_load_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_load_incoming_0_T_10 = eq(_will_fire_load_incoming_0_T_9, UInt<1>(0h0))
node _will_fire_load_incoming_0_T_11 = and(UInt<1>(0h1), _will_fire_load_incoming_0_T_10)
connect will_fire_load_incoming[0], will_fire_load_incoming_0_will_fire
node _will_fire_stad_incoming_0_will_fire_T = eq(_will_fire_load_incoming_0_T_2, UInt<1>(0h0))
node _will_fire_stad_incoming_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_stad_incoming_0_will_fire_T)
node _will_fire_stad_incoming_0_will_fire_T_2 = eq(_will_fire_stad_incoming_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_stad_incoming_0_will_fire_T_3 = and(can_fire_stad_incoming[0], _will_fire_stad_incoming_0_will_fire_T_2)
node _will_fire_stad_incoming_0_will_fire_T_4 = eq(_will_fire_load_incoming_0_T_5, UInt<1>(0h0))
node _will_fire_stad_incoming_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_stad_incoming_0_will_fire_T_4)
node _will_fire_stad_incoming_0_will_fire_T_6 = eq(_will_fire_stad_incoming_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_stad_incoming_0_will_fire_T_7 = and(_will_fire_stad_incoming_0_will_fire_T_3, _will_fire_stad_incoming_0_will_fire_T_6)
node _will_fire_stad_incoming_0_will_fire_T_8 = eq(_will_fire_load_incoming_0_T_8, UInt<1>(0h0))
node _will_fire_stad_incoming_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_stad_incoming_0_will_fire_T_8)
node _will_fire_stad_incoming_0_will_fire_T_10 = eq(_will_fire_stad_incoming_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_stad_incoming_0_will_fire_T_11 = and(_will_fire_stad_incoming_0_will_fire_T_7, _will_fire_stad_incoming_0_will_fire_T_10)
node _will_fire_stad_incoming_0_will_fire_T_12 = eq(_will_fire_load_incoming_0_T_11, UInt<1>(0h0))
node _will_fire_stad_incoming_0_will_fire_T_13 = and(UInt<1>(0h1), _will_fire_stad_incoming_0_will_fire_T_12)
node _will_fire_stad_incoming_0_will_fire_T_14 = eq(_will_fire_stad_incoming_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_stad_incoming_0_will_fire = and(_will_fire_stad_incoming_0_will_fire_T_11, _will_fire_stad_incoming_0_will_fire_T_14)
node _will_fire_stad_incoming_0_T = and(will_fire_stad_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_stad_incoming_0_T_1 = eq(_will_fire_stad_incoming_0_T, UInt<1>(0h0))
node _will_fire_stad_incoming_0_T_2 = and(_will_fire_load_incoming_0_T_2, _will_fire_stad_incoming_0_T_1)
node _will_fire_stad_incoming_0_T_3 = and(will_fire_stad_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_stad_incoming_0_T_4 = eq(_will_fire_stad_incoming_0_T_3, UInt<1>(0h0))
node _will_fire_stad_incoming_0_T_5 = and(_will_fire_load_incoming_0_T_5, _will_fire_stad_incoming_0_T_4)
node _will_fire_stad_incoming_0_T_6 = and(will_fire_stad_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_stad_incoming_0_T_7 = eq(_will_fire_stad_incoming_0_T_6, UInt<1>(0h0))
node _will_fire_stad_incoming_0_T_8 = and(_will_fire_load_incoming_0_T_8, _will_fire_stad_incoming_0_T_7)
node _will_fire_stad_incoming_0_T_9 = and(will_fire_stad_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_stad_incoming_0_T_10 = eq(_will_fire_stad_incoming_0_T_9, UInt<1>(0h0))
node _will_fire_stad_incoming_0_T_11 = and(_will_fire_load_incoming_0_T_11, _will_fire_stad_incoming_0_T_10)
connect will_fire_stad_incoming[0], will_fire_stad_incoming_0_will_fire
node _will_fire_sta_incoming_0_will_fire_T = eq(_will_fire_stad_incoming_0_T_2, UInt<1>(0h0))
node _will_fire_sta_incoming_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_sta_incoming_0_will_fire_T)
node _will_fire_sta_incoming_0_will_fire_T_2 = eq(_will_fire_sta_incoming_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_sta_incoming_0_will_fire_T_3 = and(can_fire_sta_incoming[0], _will_fire_sta_incoming_0_will_fire_T_2)
node _will_fire_sta_incoming_0_will_fire_T_4 = eq(_will_fire_stad_incoming_0_T_5, UInt<1>(0h0))
node _will_fire_sta_incoming_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_sta_incoming_0_will_fire_T_4)
node _will_fire_sta_incoming_0_will_fire_T_6 = eq(_will_fire_sta_incoming_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_sta_incoming_0_will_fire_T_7 = and(_will_fire_sta_incoming_0_will_fire_T_3, _will_fire_sta_incoming_0_will_fire_T_6)
node _will_fire_sta_incoming_0_will_fire_T_8 = eq(_will_fire_stad_incoming_0_T_8, UInt<1>(0h0))
node _will_fire_sta_incoming_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_sta_incoming_0_will_fire_T_8)
node _will_fire_sta_incoming_0_will_fire_T_10 = eq(_will_fire_sta_incoming_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_sta_incoming_0_will_fire_T_11 = and(_will_fire_sta_incoming_0_will_fire_T_7, _will_fire_sta_incoming_0_will_fire_T_10)
node _will_fire_sta_incoming_0_will_fire_T_12 = eq(_will_fire_stad_incoming_0_T_11, UInt<1>(0h0))
node _will_fire_sta_incoming_0_will_fire_T_13 = and(UInt<1>(0h1), _will_fire_sta_incoming_0_will_fire_T_12)
node _will_fire_sta_incoming_0_will_fire_T_14 = eq(_will_fire_sta_incoming_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_sta_incoming_0_will_fire = and(_will_fire_sta_incoming_0_will_fire_T_11, _will_fire_sta_incoming_0_will_fire_T_14)
node _will_fire_sta_incoming_0_T = and(will_fire_sta_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_sta_incoming_0_T_1 = eq(_will_fire_sta_incoming_0_T, UInt<1>(0h0))
node _will_fire_sta_incoming_0_T_2 = and(_will_fire_stad_incoming_0_T_2, _will_fire_sta_incoming_0_T_1)
node _will_fire_sta_incoming_0_T_3 = and(will_fire_sta_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_sta_incoming_0_T_4 = eq(_will_fire_sta_incoming_0_T_3, UInt<1>(0h0))
node _will_fire_sta_incoming_0_T_5 = and(_will_fire_stad_incoming_0_T_5, _will_fire_sta_incoming_0_T_4)
node _will_fire_sta_incoming_0_T_6 = and(will_fire_sta_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_sta_incoming_0_T_7 = eq(_will_fire_sta_incoming_0_T_6, UInt<1>(0h0))
node _will_fire_sta_incoming_0_T_8 = and(_will_fire_stad_incoming_0_T_8, _will_fire_sta_incoming_0_T_7)
node _will_fire_sta_incoming_0_T_9 = and(will_fire_sta_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_sta_incoming_0_T_10 = eq(_will_fire_sta_incoming_0_T_9, UInt<1>(0h0))
node _will_fire_sta_incoming_0_T_11 = and(_will_fire_stad_incoming_0_T_11, _will_fire_sta_incoming_0_T_10)
connect will_fire_sta_incoming[0], will_fire_sta_incoming_0_will_fire
node _will_fire_std_incoming_0_will_fire_T = eq(_will_fire_sta_incoming_0_T_2, UInt<1>(0h0))
node _will_fire_std_incoming_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_std_incoming_0_will_fire_T)
node _will_fire_std_incoming_0_will_fire_T_2 = eq(_will_fire_std_incoming_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_std_incoming_0_will_fire_T_3 = and(can_fire_std_incoming[0], _will_fire_std_incoming_0_will_fire_T_2)
node _will_fire_std_incoming_0_will_fire_T_4 = eq(_will_fire_sta_incoming_0_T_5, UInt<1>(0h0))
node _will_fire_std_incoming_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_std_incoming_0_will_fire_T_4)
node _will_fire_std_incoming_0_will_fire_T_6 = eq(_will_fire_std_incoming_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_std_incoming_0_will_fire_T_7 = and(_will_fire_std_incoming_0_will_fire_T_3, _will_fire_std_incoming_0_will_fire_T_6)
node _will_fire_std_incoming_0_will_fire_T_8 = eq(_will_fire_sta_incoming_0_T_8, UInt<1>(0h0))
node _will_fire_std_incoming_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_std_incoming_0_will_fire_T_8)
node _will_fire_std_incoming_0_will_fire_T_10 = eq(_will_fire_std_incoming_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_std_incoming_0_will_fire_T_11 = and(_will_fire_std_incoming_0_will_fire_T_7, _will_fire_std_incoming_0_will_fire_T_10)
node _will_fire_std_incoming_0_will_fire_T_12 = eq(_will_fire_sta_incoming_0_T_11, UInt<1>(0h0))
node _will_fire_std_incoming_0_will_fire_T_13 = and(UInt<1>(0h1), _will_fire_std_incoming_0_will_fire_T_12)
node _will_fire_std_incoming_0_will_fire_T_14 = eq(_will_fire_std_incoming_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_std_incoming_0_will_fire = and(_will_fire_std_incoming_0_will_fire_T_11, _will_fire_std_incoming_0_will_fire_T_14)
node _will_fire_std_incoming_0_T = and(will_fire_std_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_std_incoming_0_T_1 = eq(_will_fire_std_incoming_0_T, UInt<1>(0h0))
node _will_fire_std_incoming_0_T_2 = and(_will_fire_sta_incoming_0_T_2, _will_fire_std_incoming_0_T_1)
node _will_fire_std_incoming_0_T_3 = and(will_fire_std_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_std_incoming_0_T_4 = eq(_will_fire_std_incoming_0_T_3, UInt<1>(0h0))
node _will_fire_std_incoming_0_T_5 = and(_will_fire_sta_incoming_0_T_5, _will_fire_std_incoming_0_T_4)
node _will_fire_std_incoming_0_T_6 = and(will_fire_std_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_std_incoming_0_T_7 = eq(_will_fire_std_incoming_0_T_6, UInt<1>(0h0))
node _will_fire_std_incoming_0_T_8 = and(_will_fire_sta_incoming_0_T_8, _will_fire_std_incoming_0_T_7)
node _will_fire_std_incoming_0_T_9 = and(will_fire_std_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_std_incoming_0_T_10 = eq(_will_fire_std_incoming_0_T_9, UInt<1>(0h0))
node _will_fire_std_incoming_0_T_11 = and(_will_fire_sta_incoming_0_T_11, _will_fire_std_incoming_0_T_10)
connect will_fire_std_incoming[0], will_fire_std_incoming_0_will_fire
node _will_fire_sfence_0_will_fire_T = eq(_will_fire_std_incoming_0_T_2, UInt<1>(0h0))
node _will_fire_sfence_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_sfence_0_will_fire_T)
node _will_fire_sfence_0_will_fire_T_2 = eq(_will_fire_sfence_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_sfence_0_will_fire_T_3 = and(can_fire_sfence[0], _will_fire_sfence_0_will_fire_T_2)
node _will_fire_sfence_0_will_fire_T_4 = eq(_will_fire_std_incoming_0_T_5, UInt<1>(0h0))
node _will_fire_sfence_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_sfence_0_will_fire_T_4)
node _will_fire_sfence_0_will_fire_T_6 = eq(_will_fire_sfence_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_sfence_0_will_fire_T_7 = and(_will_fire_sfence_0_will_fire_T_3, _will_fire_sfence_0_will_fire_T_6)
node _will_fire_sfence_0_will_fire_T_8 = eq(_will_fire_std_incoming_0_T_8, UInt<1>(0h0))
node _will_fire_sfence_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_sfence_0_will_fire_T_8)
node _will_fire_sfence_0_will_fire_T_10 = eq(_will_fire_sfence_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_sfence_0_will_fire_T_11 = and(_will_fire_sfence_0_will_fire_T_7, _will_fire_sfence_0_will_fire_T_10)
node _will_fire_sfence_0_will_fire_T_12 = eq(_will_fire_std_incoming_0_T_11, UInt<1>(0h0))
node _will_fire_sfence_0_will_fire_T_13 = and(UInt<1>(0h1), _will_fire_sfence_0_will_fire_T_12)
node _will_fire_sfence_0_will_fire_T_14 = eq(_will_fire_sfence_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_sfence_0_will_fire = and(_will_fire_sfence_0_will_fire_T_11, _will_fire_sfence_0_will_fire_T_14)
node _will_fire_sfence_0_T = and(will_fire_sfence_0_will_fire, UInt<1>(0h1))
node _will_fire_sfence_0_T_1 = eq(_will_fire_sfence_0_T, UInt<1>(0h0))
node _will_fire_sfence_0_T_2 = and(_will_fire_std_incoming_0_T_2, _will_fire_sfence_0_T_1)
node _will_fire_sfence_0_T_3 = and(will_fire_sfence_0_will_fire, UInt<1>(0h0))
node _will_fire_sfence_0_T_4 = eq(_will_fire_sfence_0_T_3, UInt<1>(0h0))
node _will_fire_sfence_0_T_5 = and(_will_fire_std_incoming_0_T_5, _will_fire_sfence_0_T_4)
node _will_fire_sfence_0_T_6 = and(will_fire_sfence_0_will_fire, UInt<1>(0h0))
node _will_fire_sfence_0_T_7 = eq(_will_fire_sfence_0_T_6, UInt<1>(0h0))
node _will_fire_sfence_0_T_8 = and(_will_fire_std_incoming_0_T_8, _will_fire_sfence_0_T_7)
node _will_fire_sfence_0_T_9 = and(will_fire_sfence_0_will_fire, UInt<1>(0h1))
node _will_fire_sfence_0_T_10 = eq(_will_fire_sfence_0_T_9, UInt<1>(0h0))
node _will_fire_sfence_0_T_11 = and(_will_fire_std_incoming_0_T_11, _will_fire_sfence_0_T_10)
connect will_fire_sfence[0], will_fire_sfence_0_will_fire
node _will_fire_release_0_will_fire_T = eq(_will_fire_sfence_0_T_2, UInt<1>(0h0))
node _will_fire_release_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_release_0_will_fire_T)
node _will_fire_release_0_will_fire_T_2 = eq(_will_fire_release_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_release_0_will_fire_T_3 = and(can_fire_release[0], _will_fire_release_0_will_fire_T_2)
node _will_fire_release_0_will_fire_T_4 = eq(_will_fire_sfence_0_T_5, UInt<1>(0h0))
node _will_fire_release_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_release_0_will_fire_T_4)
node _will_fire_release_0_will_fire_T_6 = eq(_will_fire_release_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_release_0_will_fire_T_7 = and(_will_fire_release_0_will_fire_T_3, _will_fire_release_0_will_fire_T_6)
node _will_fire_release_0_will_fire_T_8 = eq(_will_fire_sfence_0_T_8, UInt<1>(0h0))
node _will_fire_release_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_release_0_will_fire_T_8)
node _will_fire_release_0_will_fire_T_10 = eq(_will_fire_release_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_release_0_will_fire_T_11 = and(_will_fire_release_0_will_fire_T_7, _will_fire_release_0_will_fire_T_10)
node _will_fire_release_0_will_fire_T_12 = eq(_will_fire_sfence_0_T_11, UInt<1>(0h0))
node _will_fire_release_0_will_fire_T_13 = and(UInt<1>(0h0), _will_fire_release_0_will_fire_T_12)
node _will_fire_release_0_will_fire_T_14 = eq(_will_fire_release_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_release_0_will_fire = and(_will_fire_release_0_will_fire_T_11, _will_fire_release_0_will_fire_T_14)
node _will_fire_release_0_T = and(will_fire_release_0_will_fire, UInt<1>(0h0))
node _will_fire_release_0_T_1 = eq(_will_fire_release_0_T, UInt<1>(0h0))
node _will_fire_release_0_T_2 = and(_will_fire_sfence_0_T_2, _will_fire_release_0_T_1)
node _will_fire_release_0_T_3 = and(will_fire_release_0_will_fire, UInt<1>(0h1))
node _will_fire_release_0_T_4 = eq(_will_fire_release_0_T_3, UInt<1>(0h0))
node _will_fire_release_0_T_5 = and(_will_fire_sfence_0_T_5, _will_fire_release_0_T_4)
node _will_fire_release_0_T_6 = and(will_fire_release_0_will_fire, UInt<1>(0h0))
node _will_fire_release_0_T_7 = eq(_will_fire_release_0_T_6, UInt<1>(0h0))
node _will_fire_release_0_T_8 = and(_will_fire_sfence_0_T_8, _will_fire_release_0_T_7)
node _will_fire_release_0_T_9 = and(will_fire_release_0_will_fire, UInt<1>(0h0))
node _will_fire_release_0_T_10 = eq(_will_fire_release_0_T_9, UInt<1>(0h0))
node _will_fire_release_0_T_11 = and(_will_fire_sfence_0_T_11, _will_fire_release_0_T_10)
connect will_fire_release[0], will_fire_release_0_will_fire
node _will_fire_hella_incoming_0_will_fire_T = eq(_will_fire_release_0_T_2, UInt<1>(0h0))
node _will_fire_hella_incoming_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_hella_incoming_0_will_fire_T)
node _will_fire_hella_incoming_0_will_fire_T_2 = eq(_will_fire_hella_incoming_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_hella_incoming_0_will_fire_T_3 = and(can_fire_hella_incoming[0], _will_fire_hella_incoming_0_will_fire_T_2)
node _will_fire_hella_incoming_0_will_fire_T_4 = eq(_will_fire_release_0_T_5, UInt<1>(0h0))
node _will_fire_hella_incoming_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_hella_incoming_0_will_fire_T_4)
node _will_fire_hella_incoming_0_will_fire_T_6 = eq(_will_fire_hella_incoming_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_hella_incoming_0_will_fire_T_7 = and(_will_fire_hella_incoming_0_will_fire_T_3, _will_fire_hella_incoming_0_will_fire_T_6)
node _will_fire_hella_incoming_0_will_fire_T_8 = eq(_will_fire_release_0_T_8, UInt<1>(0h0))
node _will_fire_hella_incoming_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_hella_incoming_0_will_fire_T_8)
node _will_fire_hella_incoming_0_will_fire_T_10 = eq(_will_fire_hella_incoming_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_hella_incoming_0_will_fire_T_11 = and(_will_fire_hella_incoming_0_will_fire_T_7, _will_fire_hella_incoming_0_will_fire_T_10)
node _will_fire_hella_incoming_0_will_fire_T_12 = eq(_will_fire_release_0_T_11, UInt<1>(0h0))
node _will_fire_hella_incoming_0_will_fire_T_13 = and(UInt<1>(0h0), _will_fire_hella_incoming_0_will_fire_T_12)
node _will_fire_hella_incoming_0_will_fire_T_14 = eq(_will_fire_hella_incoming_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_hella_incoming_0_will_fire = and(_will_fire_hella_incoming_0_will_fire_T_11, _will_fire_hella_incoming_0_will_fire_T_14)
node _will_fire_hella_incoming_0_T = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_hella_incoming_0_T_1 = eq(_will_fire_hella_incoming_0_T, UInt<1>(0h0))
node _will_fire_hella_incoming_0_T_2 = and(_will_fire_release_0_T_2, _will_fire_hella_incoming_0_T_1)
node _will_fire_hella_incoming_0_T_3 = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_hella_incoming_0_T_4 = eq(_will_fire_hella_incoming_0_T_3, UInt<1>(0h0))
node _will_fire_hella_incoming_0_T_5 = and(_will_fire_release_0_T_5, _will_fire_hella_incoming_0_T_4)
node _will_fire_hella_incoming_0_T_6 = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h1))
node _will_fire_hella_incoming_0_T_7 = eq(_will_fire_hella_incoming_0_T_6, UInt<1>(0h0))
node _will_fire_hella_incoming_0_T_8 = and(_will_fire_release_0_T_8, _will_fire_hella_incoming_0_T_7)
node _will_fire_hella_incoming_0_T_9 = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h0))
node _will_fire_hella_incoming_0_T_10 = eq(_will_fire_hella_incoming_0_T_9, UInt<1>(0h0))
node _will_fire_hella_incoming_0_T_11 = and(_will_fire_release_0_T_11, _will_fire_hella_incoming_0_T_10)
connect will_fire_hella_incoming[0], will_fire_hella_incoming_0_will_fire
node _will_fire_hella_wakeup_0_will_fire_T = eq(_will_fire_hella_incoming_0_T_2, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_hella_wakeup_0_will_fire_T)
node _will_fire_hella_wakeup_0_will_fire_T_2 = eq(_will_fire_hella_wakeup_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_will_fire_T_3 = and(can_fire_hella_wakeup[0], _will_fire_hella_wakeup_0_will_fire_T_2)
node _will_fire_hella_wakeup_0_will_fire_T_4 = eq(_will_fire_hella_incoming_0_T_5, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_hella_wakeup_0_will_fire_T_4)
node _will_fire_hella_wakeup_0_will_fire_T_6 = eq(_will_fire_hella_wakeup_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_will_fire_T_7 = and(_will_fire_hella_wakeup_0_will_fire_T_3, _will_fire_hella_wakeup_0_will_fire_T_6)
node _will_fire_hella_wakeup_0_will_fire_T_8 = eq(_will_fire_hella_incoming_0_T_8, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_hella_wakeup_0_will_fire_T_8)
node _will_fire_hella_wakeup_0_will_fire_T_10 = eq(_will_fire_hella_wakeup_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_will_fire_T_11 = and(_will_fire_hella_wakeup_0_will_fire_T_7, _will_fire_hella_wakeup_0_will_fire_T_10)
node _will_fire_hella_wakeup_0_will_fire_T_12 = eq(_will_fire_hella_incoming_0_T_11, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_will_fire_T_13 = and(UInt<1>(0h0), _will_fire_hella_wakeup_0_will_fire_T_12)
node _will_fire_hella_wakeup_0_will_fire_T_14 = eq(_will_fire_hella_wakeup_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_hella_wakeup_0_will_fire = and(_will_fire_hella_wakeup_0_will_fire_T_11, _will_fire_hella_wakeup_0_will_fire_T_14)
node _will_fire_hella_wakeup_0_T = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_T_1 = eq(_will_fire_hella_wakeup_0_T, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_T_2 = and(_will_fire_hella_incoming_0_T_2, _will_fire_hella_wakeup_0_T_1)
node _will_fire_hella_wakeup_0_T_3 = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_T_4 = eq(_will_fire_hella_wakeup_0_T_3, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_T_5 = and(_will_fire_hella_incoming_0_T_5, _will_fire_hella_wakeup_0_T_4)
node _will_fire_hella_wakeup_0_T_6 = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h1))
node _will_fire_hella_wakeup_0_T_7 = eq(_will_fire_hella_wakeup_0_T_6, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_T_8 = and(_will_fire_hella_incoming_0_T_8, _will_fire_hella_wakeup_0_T_7)
node _will_fire_hella_wakeup_0_T_9 = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_T_10 = eq(_will_fire_hella_wakeup_0_T_9, UInt<1>(0h0))
node _will_fire_hella_wakeup_0_T_11 = and(_will_fire_hella_incoming_0_T_11, _will_fire_hella_wakeup_0_T_10)
connect will_fire_hella_wakeup[0], will_fire_hella_wakeup_0_will_fire
node _will_fire_load_retry_0_will_fire_T = eq(_will_fire_hella_wakeup_0_T_2, UInt<1>(0h0))
node _will_fire_load_retry_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T)
node _will_fire_load_retry_0_will_fire_T_2 = eq(_will_fire_load_retry_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_load_retry_0_will_fire_T_3 = and(can_fire_load_retry[0], _will_fire_load_retry_0_will_fire_T_2)
node _will_fire_load_retry_0_will_fire_T_4 = eq(_will_fire_hella_wakeup_0_T_5, UInt<1>(0h0))
node _will_fire_load_retry_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T_4)
node _will_fire_load_retry_0_will_fire_T_6 = eq(_will_fire_load_retry_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_load_retry_0_will_fire_T_7 = and(_will_fire_load_retry_0_will_fire_T_3, _will_fire_load_retry_0_will_fire_T_6)
node _will_fire_load_retry_0_will_fire_T_8 = eq(_will_fire_hella_wakeup_0_T_8, UInt<1>(0h0))
node _will_fire_load_retry_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T_8)
node _will_fire_load_retry_0_will_fire_T_10 = eq(_will_fire_load_retry_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_load_retry_0_will_fire_T_11 = and(_will_fire_load_retry_0_will_fire_T_7, _will_fire_load_retry_0_will_fire_T_10)
node _will_fire_load_retry_0_will_fire_T_12 = eq(_will_fire_hella_wakeup_0_T_11, UInt<1>(0h0))
node _will_fire_load_retry_0_will_fire_T_13 = and(UInt<1>(0h0), _will_fire_load_retry_0_will_fire_T_12)
node _will_fire_load_retry_0_will_fire_T_14 = eq(_will_fire_load_retry_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_load_retry_0_will_fire = and(_will_fire_load_retry_0_will_fire_T_11, _will_fire_load_retry_0_will_fire_T_14)
node _will_fire_load_retry_0_T = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1))
node _will_fire_load_retry_0_T_1 = eq(_will_fire_load_retry_0_T, UInt<1>(0h0))
node _will_fire_load_retry_0_T_2 = and(_will_fire_hella_wakeup_0_T_2, _will_fire_load_retry_0_T_1)
node _will_fire_load_retry_0_T_3 = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1))
node _will_fire_load_retry_0_T_4 = eq(_will_fire_load_retry_0_T_3, UInt<1>(0h0))
node _will_fire_load_retry_0_T_5 = and(_will_fire_hella_wakeup_0_T_5, _will_fire_load_retry_0_T_4)
node _will_fire_load_retry_0_T_6 = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1))
node _will_fire_load_retry_0_T_7 = eq(_will_fire_load_retry_0_T_6, UInt<1>(0h0))
node _will_fire_load_retry_0_T_8 = and(_will_fire_hella_wakeup_0_T_8, _will_fire_load_retry_0_T_7)
node _will_fire_load_retry_0_T_9 = and(will_fire_load_retry_0_will_fire, UInt<1>(0h0))
node _will_fire_load_retry_0_T_10 = eq(_will_fire_load_retry_0_T_9, UInt<1>(0h0))
node _will_fire_load_retry_0_T_11 = and(_will_fire_hella_wakeup_0_T_11, _will_fire_load_retry_0_T_10)
connect will_fire_load_retry[0], will_fire_load_retry_0_will_fire
node _will_fire_sta_retry_0_will_fire_T = eq(_will_fire_load_retry_0_T_2, UInt<1>(0h0))
node _will_fire_sta_retry_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_sta_retry_0_will_fire_T)
node _will_fire_sta_retry_0_will_fire_T_2 = eq(_will_fire_sta_retry_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_sta_retry_0_will_fire_T_3 = and(can_fire_sta_retry[0], _will_fire_sta_retry_0_will_fire_T_2)
node _will_fire_sta_retry_0_will_fire_T_4 = eq(_will_fire_load_retry_0_T_5, UInt<1>(0h0))
node _will_fire_sta_retry_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_sta_retry_0_will_fire_T_4)
node _will_fire_sta_retry_0_will_fire_T_6 = eq(_will_fire_sta_retry_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_sta_retry_0_will_fire_T_7 = and(_will_fire_sta_retry_0_will_fire_T_3, _will_fire_sta_retry_0_will_fire_T_6)
node _will_fire_sta_retry_0_will_fire_T_8 = eq(_will_fire_load_retry_0_T_8, UInt<1>(0h0))
node _will_fire_sta_retry_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_sta_retry_0_will_fire_T_8)
node _will_fire_sta_retry_0_will_fire_T_10 = eq(_will_fire_sta_retry_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_sta_retry_0_will_fire_T_11 = and(_will_fire_sta_retry_0_will_fire_T_7, _will_fire_sta_retry_0_will_fire_T_10)
node _will_fire_sta_retry_0_will_fire_T_12 = eq(_will_fire_load_retry_0_T_11, UInt<1>(0h0))
node _will_fire_sta_retry_0_will_fire_T_13 = and(UInt<1>(0h1), _will_fire_sta_retry_0_will_fire_T_12)
node _will_fire_sta_retry_0_will_fire_T_14 = eq(_will_fire_sta_retry_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_sta_retry_0_will_fire = and(_will_fire_sta_retry_0_will_fire_T_11, _will_fire_sta_retry_0_will_fire_T_14)
node _will_fire_sta_retry_0_T = and(will_fire_sta_retry_0_will_fire, UInt<1>(0h1))
node _will_fire_sta_retry_0_T_1 = eq(_will_fire_sta_retry_0_T, UInt<1>(0h0))
node _will_fire_sta_retry_0_T_2 = and(_will_fire_load_retry_0_T_2, _will_fire_sta_retry_0_T_1)
node _will_fire_sta_retry_0_T_3 = and(will_fire_sta_retry_0_will_fire, UInt<1>(0h1))
node _will_fire_sta_retry_0_T_4 = eq(_will_fire_sta_retry_0_T_3, UInt<1>(0h0))
node _will_fire_sta_retry_0_T_5 = and(_will_fire_load_retry_0_T_5, _will_fire_sta_retry_0_T_4)
node _will_fire_sta_retry_0_T_6 = and(will_fire_sta_retry_0_will_fire, UInt<1>(0h0))
node _will_fire_sta_retry_0_T_7 = eq(_will_fire_sta_retry_0_T_6, UInt<1>(0h0))
node _will_fire_sta_retry_0_T_8 = and(_will_fire_load_retry_0_T_8, _will_fire_sta_retry_0_T_7)
node _will_fire_sta_retry_0_T_9 = and(will_fire_sta_retry_0_will_fire, UInt<1>(0h1))
node _will_fire_sta_retry_0_T_10 = eq(_will_fire_sta_retry_0_T_9, UInt<1>(0h0))
node _will_fire_sta_retry_0_T_11 = and(_will_fire_load_retry_0_T_11, _will_fire_sta_retry_0_T_10)
connect will_fire_sta_retry[0], will_fire_sta_retry_0_will_fire
node _will_fire_load_wakeup_0_will_fire_T = eq(_will_fire_sta_retry_0_T_2, UInt<1>(0h0))
node _will_fire_load_wakeup_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_load_wakeup_0_will_fire_T)
node _will_fire_load_wakeup_0_will_fire_T_2 = eq(_will_fire_load_wakeup_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_load_wakeup_0_will_fire_T_3 = and(can_fire_load_wakeup[0], _will_fire_load_wakeup_0_will_fire_T_2)
node _will_fire_load_wakeup_0_will_fire_T_4 = eq(_will_fire_sta_retry_0_T_5, UInt<1>(0h0))
node _will_fire_load_wakeup_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_wakeup_0_will_fire_T_4)
node _will_fire_load_wakeup_0_will_fire_T_6 = eq(_will_fire_load_wakeup_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_load_wakeup_0_will_fire_T_7 = and(_will_fire_load_wakeup_0_will_fire_T_3, _will_fire_load_wakeup_0_will_fire_T_6)
node _will_fire_load_wakeup_0_will_fire_T_8 = eq(_will_fire_sta_retry_0_T_8, UInt<1>(0h0))
node _will_fire_load_wakeup_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_wakeup_0_will_fire_T_8)
node _will_fire_load_wakeup_0_will_fire_T_10 = eq(_will_fire_load_wakeup_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_load_wakeup_0_will_fire_T_11 = and(_will_fire_load_wakeup_0_will_fire_T_7, _will_fire_load_wakeup_0_will_fire_T_10)
node _will_fire_load_wakeup_0_will_fire_T_12 = eq(_will_fire_sta_retry_0_T_11, UInt<1>(0h0))
node _will_fire_load_wakeup_0_will_fire_T_13 = and(UInt<1>(0h0), _will_fire_load_wakeup_0_will_fire_T_12)
node _will_fire_load_wakeup_0_will_fire_T_14 = eq(_will_fire_load_wakeup_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_load_wakeup_0_will_fire = and(_will_fire_load_wakeup_0_will_fire_T_11, _will_fire_load_wakeup_0_will_fire_T_14)
node _will_fire_load_wakeup_0_T = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h0))
node _will_fire_load_wakeup_0_T_1 = eq(_will_fire_load_wakeup_0_T, UInt<1>(0h0))
node _will_fire_load_wakeup_0_T_2 = and(_will_fire_sta_retry_0_T_2, _will_fire_load_wakeup_0_T_1)
node _will_fire_load_wakeup_0_T_3 = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h1))
node _will_fire_load_wakeup_0_T_4 = eq(_will_fire_load_wakeup_0_T_3, UInt<1>(0h0))
node _will_fire_load_wakeup_0_T_5 = and(_will_fire_sta_retry_0_T_5, _will_fire_load_wakeup_0_T_4)
node _will_fire_load_wakeup_0_T_6 = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h1))
node _will_fire_load_wakeup_0_T_7 = eq(_will_fire_load_wakeup_0_T_6, UInt<1>(0h0))
node _will_fire_load_wakeup_0_T_8 = and(_will_fire_sta_retry_0_T_8, _will_fire_load_wakeup_0_T_7)
node _will_fire_load_wakeup_0_T_9 = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h0))
node _will_fire_load_wakeup_0_T_10 = eq(_will_fire_load_wakeup_0_T_9, UInt<1>(0h0))
node _will_fire_load_wakeup_0_T_11 = and(_will_fire_sta_retry_0_T_11, _will_fire_load_wakeup_0_T_10)
connect will_fire_load_wakeup[0], will_fire_load_wakeup_0_will_fire
node _will_fire_store_commit_0_will_fire_T = eq(_will_fire_load_wakeup_0_T_2, UInt<1>(0h0))
node _will_fire_store_commit_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_store_commit_0_will_fire_T)
node _will_fire_store_commit_0_will_fire_T_2 = eq(_will_fire_store_commit_0_will_fire_T_1, UInt<1>(0h0))
node _will_fire_store_commit_0_will_fire_T_3 = and(can_fire_store_commit[0], _will_fire_store_commit_0_will_fire_T_2)
node _will_fire_store_commit_0_will_fire_T_4 = eq(_will_fire_load_wakeup_0_T_5, UInt<1>(0h0))
node _will_fire_store_commit_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_store_commit_0_will_fire_T_4)
node _will_fire_store_commit_0_will_fire_T_6 = eq(_will_fire_store_commit_0_will_fire_T_5, UInt<1>(0h0))
node _will_fire_store_commit_0_will_fire_T_7 = and(_will_fire_store_commit_0_will_fire_T_3, _will_fire_store_commit_0_will_fire_T_6)
node _will_fire_store_commit_0_will_fire_T_8 = eq(_will_fire_load_wakeup_0_T_8, UInt<1>(0h0))
node _will_fire_store_commit_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_store_commit_0_will_fire_T_8)
node _will_fire_store_commit_0_will_fire_T_10 = eq(_will_fire_store_commit_0_will_fire_T_9, UInt<1>(0h0))
node _will_fire_store_commit_0_will_fire_T_11 = and(_will_fire_store_commit_0_will_fire_T_7, _will_fire_store_commit_0_will_fire_T_10)
node _will_fire_store_commit_0_will_fire_T_12 = eq(_will_fire_load_wakeup_0_T_11, UInt<1>(0h0))
node _will_fire_store_commit_0_will_fire_T_13 = and(UInt<1>(0h0), _will_fire_store_commit_0_will_fire_T_12)
node _will_fire_store_commit_0_will_fire_T_14 = eq(_will_fire_store_commit_0_will_fire_T_13, UInt<1>(0h0))
node will_fire_store_commit_0_will_fire = and(_will_fire_store_commit_0_will_fire_T_11, _will_fire_store_commit_0_will_fire_T_14)
node _will_fire_store_commit_0_T = and(will_fire_store_commit_0_will_fire, UInt<1>(0h0))
node _will_fire_store_commit_0_T_1 = eq(_will_fire_store_commit_0_T, UInt<1>(0h0))
node _will_fire_store_commit_0_T_2 = and(_will_fire_load_wakeup_0_T_2, _will_fire_store_commit_0_T_1)
node _will_fire_store_commit_0_T_3 = and(will_fire_store_commit_0_will_fire, UInt<1>(0h0))
node _will_fire_store_commit_0_T_4 = eq(_will_fire_store_commit_0_T_3, UInt<1>(0h0))
node _will_fire_store_commit_0_T_5 = and(_will_fire_load_wakeup_0_T_5, _will_fire_store_commit_0_T_4)
node _will_fire_store_commit_0_T_6 = and(will_fire_store_commit_0_will_fire, UInt<1>(0h1))
node _will_fire_store_commit_0_T_7 = eq(_will_fire_store_commit_0_T_6, UInt<1>(0h0))
node _will_fire_store_commit_0_T_8 = and(_will_fire_load_wakeup_0_T_8, _will_fire_store_commit_0_T_7)
node _will_fire_store_commit_0_T_9 = and(will_fire_store_commit_0_will_fire, UInt<1>(0h0))
node _will_fire_store_commit_0_T_10 = eq(_will_fire_store_commit_0_T_9, UInt<1>(0h0))
node _will_fire_store_commit_0_T_11 = and(_will_fire_load_wakeup_0_T_11, _will_fire_store_commit_0_T_10)
connect will_fire_store_commit[0], will_fire_store_commit_0_will_fire
node _T_128 = or(will_fire_load_incoming[0], will_fire_stad_incoming[0])
node _T_129 = or(_T_128, will_fire_sta_incoming[0])
node _T_130 = or(_T_129, will_fire_std_incoming[0])
node _T_131 = or(_T_130, will_fire_sfence[0])
node _T_132 = eq(_T_131, UInt<1>(0h0))
node _T_133 = and(exe_req[0].valid, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:566 assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_std_incoming(w) || will_fire_sfence(w))))\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
when will_fire_load_wakeup[0] :
node _T_138 = or(ldq_wakeup_idx, UInt<5>(0h0))
node _T_139 = bits(_T_138, 4, 0)
connect block_load_mask[_T_139], UInt<1>(0h1)
else :
when will_fire_load_incoming[0] :
connect block_load_mask[exe_req[0].bits.uop.ldq_idx], UInt<1>(0h1)
else :
when will_fire_load_retry[0] :
node _T_140 = or(ldq_retry_idx, UInt<5>(0h0))
node _T_141 = bits(_T_140, 4, 0)
connect block_load_mask[_T_141], UInt<1>(0h1)
node _exe_tlb_valid_0_T = eq(_will_fire_store_commit_0_T_2, UInt<1>(0h0))
connect exe_tlb_valid[0], _exe_tlb_valid_0_T
node _T_142 = eq(will_fire_sfence[0], UInt<1>(0h0))
node _T_143 = and(will_fire_sfence[0], _T_142)
node _T_144 = eq(_T_143, UInt<1>(0h0))
node _T_145 = eq(will_fire_hella_incoming[0], UInt<1>(0h0))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(will_fire_hella_wakeup[0], UInt<1>(0h0))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(will_fire_load_retry[0], UInt<1>(0h0))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(will_fire_sta_retry[0], UInt<1>(0h0))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(will_fire_store_commit[0], UInt<1>(0h0))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(will_fire_load_wakeup[0], UInt<1>(0h0))
node _T_156 = and(_T_154, _T_155)
node _T_157 = or(UInt<1>(0h1), _T_156)
node _T_158 = asUInt(reset)
node _T_159 = eq(_T_158, UInt<1>(0h0))
when _T_159 :
node _T_160 = eq(_T_157, UInt<1>(0h0))
when _T_160 :
printf(clock, UInt<1>(0h1), "Assertion failed: Some operations is proceeding down multiple pipes\n at lsu.scala:577 assert((memWidth == 1).B ||\n") : printf_17
assert(clock, _T_157, UInt<1>(0h1), "") : assert_17
node _T_161 = neq(hella_state, UInt<3>(0h0))
node _T_162 = eq(hella_req.cmd, UInt<5>(0h14))
node _T_163 = and(_T_161, _T_162)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: SFENCE through hella interface not supported\n at lsu.scala:592 assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE),\n") : printf_18
assert(clock, _T_164, UInt<1>(0h1), "") : assert_18
node _exe_tlb_uop_T = or(will_fire_load_incoming[0], will_fire_stad_incoming[0])
node _exe_tlb_uop_T_1 = or(_exe_tlb_uop_T, will_fire_sta_incoming[0])
node _exe_tlb_uop_T_2 = or(_exe_tlb_uop_T_1, will_fire_sfence[0])
wire exe_tlb_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate exe_tlb_uop_uop.debug_tsrc
invalidate exe_tlb_uop_uop.debug_fsrc
invalidate exe_tlb_uop_uop.bp_xcpt_if
invalidate exe_tlb_uop_uop.bp_debug_if
invalidate exe_tlb_uop_uop.xcpt_ma_if
invalidate exe_tlb_uop_uop.xcpt_ae_if
invalidate exe_tlb_uop_uop.xcpt_pf_if
invalidate exe_tlb_uop_uop.fp_single
invalidate exe_tlb_uop_uop.fp_val
invalidate exe_tlb_uop_uop.frs3_en
invalidate exe_tlb_uop_uop.lrs2_rtype
invalidate exe_tlb_uop_uop.lrs1_rtype
invalidate exe_tlb_uop_uop.dst_rtype
invalidate exe_tlb_uop_uop.ldst_val
invalidate exe_tlb_uop_uop.lrs3
invalidate exe_tlb_uop_uop.lrs2
invalidate exe_tlb_uop_uop.lrs1
invalidate exe_tlb_uop_uop.ldst
invalidate exe_tlb_uop_uop.ldst_is_rs1
invalidate exe_tlb_uop_uop.flush_on_commit
invalidate exe_tlb_uop_uop.is_unique
invalidate exe_tlb_uop_uop.is_sys_pc2epc
invalidate exe_tlb_uop_uop.uses_stq
invalidate exe_tlb_uop_uop.uses_ldq
invalidate exe_tlb_uop_uop.is_amo
invalidate exe_tlb_uop_uop.is_fencei
invalidate exe_tlb_uop_uop.is_fence
invalidate exe_tlb_uop_uop.mem_signed
invalidate exe_tlb_uop_uop.mem_size
invalidate exe_tlb_uop_uop.mem_cmd
invalidate exe_tlb_uop_uop.bypassable
invalidate exe_tlb_uop_uop.exc_cause
invalidate exe_tlb_uop_uop.exception
invalidate exe_tlb_uop_uop.stale_pdst
invalidate exe_tlb_uop_uop.ppred_busy
invalidate exe_tlb_uop_uop.prs3_busy
invalidate exe_tlb_uop_uop.prs2_busy
invalidate exe_tlb_uop_uop.prs1_busy
invalidate exe_tlb_uop_uop.ppred
invalidate exe_tlb_uop_uop.prs3
invalidate exe_tlb_uop_uop.prs2
invalidate exe_tlb_uop_uop.prs1
invalidate exe_tlb_uop_uop.pdst
invalidate exe_tlb_uop_uop.rxq_idx
invalidate exe_tlb_uop_uop.stq_idx
invalidate exe_tlb_uop_uop.ldq_idx
invalidate exe_tlb_uop_uop.rob_idx
invalidate exe_tlb_uop_uop.csr_addr
invalidate exe_tlb_uop_uop.imm_packed
invalidate exe_tlb_uop_uop.taken
invalidate exe_tlb_uop_uop.pc_lob
invalidate exe_tlb_uop_uop.edge_inst
invalidate exe_tlb_uop_uop.ftq_idx
invalidate exe_tlb_uop_uop.br_tag
invalidate exe_tlb_uop_uop.br_mask
invalidate exe_tlb_uop_uop.is_sfb
invalidate exe_tlb_uop_uop.is_jal
invalidate exe_tlb_uop_uop.is_jalr
invalidate exe_tlb_uop_uop.is_br
invalidate exe_tlb_uop_uop.iw_p2_poisoned
invalidate exe_tlb_uop_uop.iw_p1_poisoned
invalidate exe_tlb_uop_uop.iw_state
invalidate exe_tlb_uop_uop.ctrl.is_std
invalidate exe_tlb_uop_uop.ctrl.is_sta
invalidate exe_tlb_uop_uop.ctrl.is_load
invalidate exe_tlb_uop_uop.ctrl.csr_cmd
invalidate exe_tlb_uop_uop.ctrl.fcn_dw
invalidate exe_tlb_uop_uop.ctrl.op_fcn
invalidate exe_tlb_uop_uop.ctrl.imm_sel
invalidate exe_tlb_uop_uop.ctrl.op2_sel
invalidate exe_tlb_uop_uop.ctrl.op1_sel
invalidate exe_tlb_uop_uop.ctrl.br_type
invalidate exe_tlb_uop_uop.fu_code
invalidate exe_tlb_uop_uop.iq_type
invalidate exe_tlb_uop_uop.debug_pc
invalidate exe_tlb_uop_uop.is_rvc
invalidate exe_tlb_uop_uop.debug_inst
invalidate exe_tlb_uop_uop.inst
invalidate exe_tlb_uop_uop.uopc
connect exe_tlb_uop_uop.uopc, UInt<7>(0h0)
connect exe_tlb_uop_uop.bypassable, UInt<1>(0h0)
connect exe_tlb_uop_uop.fp_val, UInt<1>(0h0)
connect exe_tlb_uop_uop.uses_stq, UInt<1>(0h0)
connect exe_tlb_uop_uop.uses_ldq, UInt<1>(0h0)
connect exe_tlb_uop_uop.pdst, UInt<1>(0h0)
connect exe_tlb_uop_uop.dst_rtype, UInt<2>(0h2)
wire exe_tlb_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate exe_tlb_uop_cs.is_std
invalidate exe_tlb_uop_cs.is_sta
invalidate exe_tlb_uop_cs.is_load
invalidate exe_tlb_uop_cs.csr_cmd
invalidate exe_tlb_uop_cs.fcn_dw
invalidate exe_tlb_uop_cs.op_fcn
invalidate exe_tlb_uop_cs.imm_sel
invalidate exe_tlb_uop_cs.op2_sel
invalidate exe_tlb_uop_cs.op1_sel
invalidate exe_tlb_uop_cs.br_type
connect exe_tlb_uop_cs.br_type, UInt<4>(0h0)
connect exe_tlb_uop_cs.csr_cmd, UInt<3>(0h0)
connect exe_tlb_uop_cs.is_load, UInt<1>(0h0)
connect exe_tlb_uop_cs.is_sta, UInt<1>(0h0)
connect exe_tlb_uop_cs.is_std, UInt<1>(0h0)
connect exe_tlb_uop_uop.ctrl, exe_tlb_uop_cs
wire exe_tlb_uop_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate exe_tlb_uop_uop_1.debug_tsrc
invalidate exe_tlb_uop_uop_1.debug_fsrc
invalidate exe_tlb_uop_uop_1.bp_xcpt_if
invalidate exe_tlb_uop_uop_1.bp_debug_if
invalidate exe_tlb_uop_uop_1.xcpt_ma_if
invalidate exe_tlb_uop_uop_1.xcpt_ae_if
invalidate exe_tlb_uop_uop_1.xcpt_pf_if
invalidate exe_tlb_uop_uop_1.fp_single
invalidate exe_tlb_uop_uop_1.fp_val
invalidate exe_tlb_uop_uop_1.frs3_en
invalidate exe_tlb_uop_uop_1.lrs2_rtype
invalidate exe_tlb_uop_uop_1.lrs1_rtype
invalidate exe_tlb_uop_uop_1.dst_rtype
invalidate exe_tlb_uop_uop_1.ldst_val
invalidate exe_tlb_uop_uop_1.lrs3
invalidate exe_tlb_uop_uop_1.lrs2
invalidate exe_tlb_uop_uop_1.lrs1
invalidate exe_tlb_uop_uop_1.ldst
invalidate exe_tlb_uop_uop_1.ldst_is_rs1
invalidate exe_tlb_uop_uop_1.flush_on_commit
invalidate exe_tlb_uop_uop_1.is_unique
invalidate exe_tlb_uop_uop_1.is_sys_pc2epc
invalidate exe_tlb_uop_uop_1.uses_stq
invalidate exe_tlb_uop_uop_1.uses_ldq
invalidate exe_tlb_uop_uop_1.is_amo
invalidate exe_tlb_uop_uop_1.is_fencei
invalidate exe_tlb_uop_uop_1.is_fence
invalidate exe_tlb_uop_uop_1.mem_signed
invalidate exe_tlb_uop_uop_1.mem_size
invalidate exe_tlb_uop_uop_1.mem_cmd
invalidate exe_tlb_uop_uop_1.bypassable
invalidate exe_tlb_uop_uop_1.exc_cause
invalidate exe_tlb_uop_uop_1.exception
invalidate exe_tlb_uop_uop_1.stale_pdst
invalidate exe_tlb_uop_uop_1.ppred_busy
invalidate exe_tlb_uop_uop_1.prs3_busy
invalidate exe_tlb_uop_uop_1.prs2_busy
invalidate exe_tlb_uop_uop_1.prs1_busy
invalidate exe_tlb_uop_uop_1.ppred
invalidate exe_tlb_uop_uop_1.prs3
invalidate exe_tlb_uop_uop_1.prs2
invalidate exe_tlb_uop_uop_1.prs1
invalidate exe_tlb_uop_uop_1.pdst
invalidate exe_tlb_uop_uop_1.rxq_idx
invalidate exe_tlb_uop_uop_1.stq_idx
invalidate exe_tlb_uop_uop_1.ldq_idx
invalidate exe_tlb_uop_uop_1.rob_idx
invalidate exe_tlb_uop_uop_1.csr_addr
invalidate exe_tlb_uop_uop_1.imm_packed
invalidate exe_tlb_uop_uop_1.taken
invalidate exe_tlb_uop_uop_1.pc_lob
invalidate exe_tlb_uop_uop_1.edge_inst
invalidate exe_tlb_uop_uop_1.ftq_idx
invalidate exe_tlb_uop_uop_1.br_tag
invalidate exe_tlb_uop_uop_1.br_mask
invalidate exe_tlb_uop_uop_1.is_sfb
invalidate exe_tlb_uop_uop_1.is_jal
invalidate exe_tlb_uop_uop_1.is_jalr
invalidate exe_tlb_uop_uop_1.is_br
invalidate exe_tlb_uop_uop_1.iw_p2_poisoned
invalidate exe_tlb_uop_uop_1.iw_p1_poisoned
invalidate exe_tlb_uop_uop_1.iw_state
invalidate exe_tlb_uop_uop_1.ctrl.is_std
invalidate exe_tlb_uop_uop_1.ctrl.is_sta
invalidate exe_tlb_uop_uop_1.ctrl.is_load
invalidate exe_tlb_uop_uop_1.ctrl.csr_cmd
invalidate exe_tlb_uop_uop_1.ctrl.fcn_dw
invalidate exe_tlb_uop_uop_1.ctrl.op_fcn
invalidate exe_tlb_uop_uop_1.ctrl.imm_sel
invalidate exe_tlb_uop_uop_1.ctrl.op2_sel
invalidate exe_tlb_uop_uop_1.ctrl.op1_sel
invalidate exe_tlb_uop_uop_1.ctrl.br_type
invalidate exe_tlb_uop_uop_1.fu_code
invalidate exe_tlb_uop_uop_1.iq_type
invalidate exe_tlb_uop_uop_1.debug_pc
invalidate exe_tlb_uop_uop_1.is_rvc
invalidate exe_tlb_uop_uop_1.debug_inst
invalidate exe_tlb_uop_uop_1.inst
invalidate exe_tlb_uop_uop_1.uopc
connect exe_tlb_uop_uop_1.uopc, UInt<7>(0h0)
connect exe_tlb_uop_uop_1.bypassable, UInt<1>(0h0)
connect exe_tlb_uop_uop_1.fp_val, UInt<1>(0h0)
connect exe_tlb_uop_uop_1.uses_stq, UInt<1>(0h0)
connect exe_tlb_uop_uop_1.uses_ldq, UInt<1>(0h0)
connect exe_tlb_uop_uop_1.pdst, UInt<1>(0h0)
connect exe_tlb_uop_uop_1.dst_rtype, UInt<2>(0h2)
wire exe_tlb_uop_cs_1 : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate exe_tlb_uop_cs_1.is_std
invalidate exe_tlb_uop_cs_1.is_sta
invalidate exe_tlb_uop_cs_1.is_load
invalidate exe_tlb_uop_cs_1.csr_cmd
invalidate exe_tlb_uop_cs_1.fcn_dw
invalidate exe_tlb_uop_cs_1.op_fcn
invalidate exe_tlb_uop_cs_1.imm_sel
invalidate exe_tlb_uop_cs_1.op2_sel
invalidate exe_tlb_uop_cs_1.op1_sel
invalidate exe_tlb_uop_cs_1.br_type
connect exe_tlb_uop_cs_1.br_type, UInt<4>(0h0)
connect exe_tlb_uop_cs_1.csr_cmd, UInt<3>(0h0)
connect exe_tlb_uop_cs_1.is_load, UInt<1>(0h0)
connect exe_tlb_uop_cs_1.is_sta, UInt<1>(0h0)
connect exe_tlb_uop_cs_1.is_std, UInt<1>(0h0)
connect exe_tlb_uop_uop_1.ctrl, exe_tlb_uop_cs_1
node _exe_tlb_uop_T_3 = mux(will_fire_hella_incoming[0], exe_tlb_uop_uop, exe_tlb_uop_uop_1)
node _exe_tlb_uop_T_4 = mux(will_fire_sta_retry[0], stq[_stq_retry_e_T_1].bits.uop, _exe_tlb_uop_T_3)
node _exe_tlb_uop_T_5 = mux(will_fire_load_retry[0], ldq[_ldq_retry_e_T_1].bits.uop, _exe_tlb_uop_T_4)
node _exe_tlb_uop_T_6 = mux(_exe_tlb_uop_T_2, exe_req[0].bits.uop, _exe_tlb_uop_T_5)
wire exe_tlb_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
connect exe_tlb_uop[0], _exe_tlb_uop_T_6
node _exe_tlb_vaddr_T = or(will_fire_load_incoming[0], will_fire_stad_incoming[0])
node _exe_tlb_vaddr_T_1 = or(_exe_tlb_vaddr_T, will_fire_sta_incoming[0])
node _exe_tlb_vaddr_T_2 = mux(will_fire_hella_incoming[0], hella_req.addr, UInt<1>(0h0))
node _exe_tlb_vaddr_T_3 = mux(will_fire_sta_retry[0], stq[_stq_retry_e_T_1].bits.addr.bits, _exe_tlb_vaddr_T_2)
node _exe_tlb_vaddr_T_4 = mux(will_fire_load_retry[0], ldq[_ldq_retry_e_T_1].bits.addr.bits, _exe_tlb_vaddr_T_3)
node _exe_tlb_vaddr_T_5 = mux(will_fire_sfence[0], exe_req[0].bits.sfence.bits.addr, _exe_tlb_vaddr_T_4)
node _exe_tlb_vaddr_T_6 = mux(_exe_tlb_vaddr_T_1, exe_req[0].bits.addr, _exe_tlb_vaddr_T_5)
wire exe_tlb_vaddr : UInt<40>[1]
connect exe_tlb_vaddr[0], _exe_tlb_vaddr_T_6
wire _exe_sfence_WIRE : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}
connect _exe_sfence_WIRE.bits.hg, UInt<1>(0h0)
connect _exe_sfence_WIRE.bits.hv, UInt<1>(0h0)
connect _exe_sfence_WIRE.bits.asid, UInt<1>(0h0)
connect _exe_sfence_WIRE.bits.addr, UInt<39>(0h0)
connect _exe_sfence_WIRE.bits.rs2, UInt<1>(0h0)
connect _exe_sfence_WIRE.bits.rs1, UInt<1>(0h0)
connect _exe_sfence_WIRE.valid, UInt<1>(0h0)
wire exe_sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}
connect exe_sfence, _exe_sfence_WIRE
when will_fire_sfence[0] :
connect exe_sfence, exe_req[0].bits.sfence
node _exe_size_T = or(will_fire_load_incoming[0], will_fire_stad_incoming[0])
node _exe_size_T_1 = or(_exe_size_T, will_fire_sta_incoming[0])
node _exe_size_T_2 = or(_exe_size_T_1, will_fire_sfence[0])
node _exe_size_T_3 = or(_exe_size_T_2, will_fire_load_retry[0])
node _exe_size_T_4 = or(_exe_size_T_3, will_fire_sta_retry[0])
node _exe_size_T_5 = mux(will_fire_hella_incoming[0], hella_req.size, UInt<1>(0h0))
node _exe_size_T_6 = mux(_exe_size_T_4, exe_tlb_uop[0].mem_size, _exe_size_T_5)
wire exe_size : UInt<2>[1]
connect exe_size[0], _exe_size_T_6
node _exe_cmd_T = or(will_fire_load_incoming[0], will_fire_stad_incoming[0])
node _exe_cmd_T_1 = or(_exe_cmd_T, will_fire_sta_incoming[0])
node _exe_cmd_T_2 = or(_exe_cmd_T_1, will_fire_sfence[0])
node _exe_cmd_T_3 = or(_exe_cmd_T_2, will_fire_load_retry[0])
node _exe_cmd_T_4 = or(_exe_cmd_T_3, will_fire_sta_retry[0])
node _exe_cmd_T_5 = mux(will_fire_hella_incoming[0], hella_req.cmd, UInt<1>(0h0))
node _exe_cmd_T_6 = mux(_exe_cmd_T_4, exe_tlb_uop[0].mem_cmd, _exe_cmd_T_5)
wire exe_cmd : UInt<5>[1]
connect exe_cmd[0], _exe_cmd_T_6
node _exe_passthr_T = mux(will_fire_hella_incoming[0], hella_req.phys, UInt<1>(0h0))
wire exe_passthr : UInt<1>[1]
connect exe_passthr[0], _exe_passthr_T
node _exe_kill_T = mux(will_fire_hella_incoming[0], io.hellacache.s1_kill, UInt<1>(0h0))
wire exe_kill : UInt<1>[1]
connect exe_kill[0], _exe_kill_T
connect dtlb.io.req[0].valid, exe_tlb_valid[0]
connect dtlb.io.req[0].bits.vaddr, exe_tlb_vaddr[0]
connect dtlb.io.req[0].bits.size, exe_size[0]
connect dtlb.io.req[0].bits.cmd, exe_cmd[0]
connect dtlb.io.req[0].bits.passthrough, exe_passthr[0]
connect dtlb.io.req[0].bits.v, io.ptw.status.v
connect dtlb.io.req[0].bits.prv, io.ptw.status.prv
connect dtlb.io.kill, exe_kill[0]
connect dtlb.io.sfence.bits.hg, exe_sfence.bits.hg
connect dtlb.io.sfence.bits.hv, exe_sfence.bits.hv
connect dtlb.io.sfence.bits.asid, exe_sfence.bits.asid
connect dtlb.io.sfence.bits.addr, exe_sfence.bits.addr
connect dtlb.io.sfence.bits.rs2, exe_sfence.bits.rs2
connect dtlb.io.sfence.bits.rs1, exe_sfence.bits.rs1
connect dtlb.io.sfence.valid, exe_sfence.valid
node _ma_ld_T = and(will_fire_load_incoming[0], exe_req[0].bits.mxcpt.valid)
wire ma_ld : UInt<1>[1]
connect ma_ld[0], _ma_ld_T
node _ma_st_T = or(will_fire_sta_incoming[0], will_fire_stad_incoming[0])
node _ma_st_T_1 = and(_ma_st_T, exe_req[0].bits.mxcpt.valid)
wire ma_st : UInt<1>[1]
connect ma_st[0], _ma_st_T_1
node _pf_ld_T = and(dtlb.io.req[0].valid, dtlb.io.resp[0].pf.ld)
node _pf_ld_T_1 = and(_pf_ld_T, exe_tlb_uop[0].uses_ldq)
wire pf_ld : UInt<1>[1]
connect pf_ld[0], _pf_ld_T_1
node _pf_st_T = and(dtlb.io.req[0].valid, dtlb.io.resp[0].pf.st)
node _pf_st_T_1 = and(_pf_st_T, exe_tlb_uop[0].uses_stq)
wire pf_st : UInt<1>[1]
connect pf_st[0], _pf_st_T_1
node _ae_ld_T = and(dtlb.io.req[0].valid, dtlb.io.resp[0].ae.ld)
node _ae_ld_T_1 = and(_ae_ld_T, exe_tlb_uop[0].uses_ldq)
wire ae_ld : UInt<1>[1]
connect ae_ld[0], _ae_ld_T_1
node _ae_st_T = and(dtlb.io.req[0].valid, dtlb.io.resp[0].ae.st)
node _ae_st_T_1 = and(_ae_st_T, exe_tlb_uop[0].uses_stq)
wire ae_st : UInt<1>[1]
connect ae_st[0], _ae_st_T_1
node _mem_xcpt_valids_T = or(pf_ld[0], pf_st[0])
node _mem_xcpt_valids_T_1 = or(_mem_xcpt_valids_T, ae_ld[0])
node _mem_xcpt_valids_T_2 = or(_mem_xcpt_valids_T_1, ae_st[0])
node _mem_xcpt_valids_T_3 = or(_mem_xcpt_valids_T_2, ma_ld[0])
node _mem_xcpt_valids_T_4 = or(_mem_xcpt_valids_T_3, ma_st[0])
node _mem_xcpt_valids_T_5 = eq(io.core.exception, UInt<1>(0h0))
node _mem_xcpt_valids_T_6 = and(_mem_xcpt_valids_T_4, _mem_xcpt_valids_T_5)
node _mem_xcpt_valids_T_7 = and(io.core.brupdate.b1.mispredict_mask, exe_tlb_uop[0].br_mask)
node _mem_xcpt_valids_T_8 = neq(_mem_xcpt_valids_T_7, UInt<1>(0h0))
node _mem_xcpt_valids_T_9 = eq(_mem_xcpt_valids_T_8, UInt<1>(0h0))
node _mem_xcpt_valids_T_10 = and(_mem_xcpt_valids_T_6, _mem_xcpt_valids_T_9)
wire _mem_xcpt_valids_WIRE : UInt<1>[1]
connect _mem_xcpt_valids_WIRE[0], _mem_xcpt_valids_T_10
reg mem_xcpt_valids : UInt<1>[1], clock
connect mem_xcpt_valids, _mem_xcpt_valids_WIRE
wire mem_xcpt_uops_out : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect mem_xcpt_uops_out, exe_tlb_uop[0]
node _mem_xcpt_uops_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_xcpt_uops_out_br_mask_T_1 = and(exe_tlb_uop[0].br_mask, _mem_xcpt_uops_out_br_mask_T)
connect mem_xcpt_uops_out.br_mask, _mem_xcpt_uops_out_br_mask_T_1
wire _mem_xcpt_uops_WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
connect _mem_xcpt_uops_WIRE[0], mem_xcpt_uops_out
reg mem_xcpt_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], clock
connect mem_xcpt_uops, _mem_xcpt_uops_WIRE
node _mem_xcpt_causes_T = mux(ae_ld[0], UInt<3>(0h5), UInt<3>(0h7))
node _mem_xcpt_causes_T_1 = mux(pf_st[0], UInt<4>(0hf), _mem_xcpt_causes_T)
node _mem_xcpt_causes_T_2 = mux(pf_ld[0], UInt<4>(0hd), _mem_xcpt_causes_T_1)
node _mem_xcpt_causes_T_3 = mux(ma_st[0], UInt<3>(0h6), _mem_xcpt_causes_T_2)
node _mem_xcpt_causes_T_4 = mux(ma_ld[0], UInt<3>(0h4), _mem_xcpt_causes_T_3)
wire _mem_xcpt_causes_WIRE : UInt<4>[1]
connect _mem_xcpt_causes_WIRE[0], _mem_xcpt_causes_T_4
reg mem_xcpt_causes : UInt<4>[1], clock
connect mem_xcpt_causes, _mem_xcpt_causes_WIRE
reg mem_xcpt_vaddrs : UInt<40>[1], clock
connect mem_xcpt_vaddrs, exe_tlb_vaddr
node _T_168 = and(dtlb.io.req[0].valid, exe_tlb_uop[0].is_fence)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: Fence is pretending to talk to the TLB\n at lsu.scala:683 assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), \"Fence is pretending to talk to the TLB\")\n") : printf_19
assert(clock, _T_169, UInt<1>(0h1), "") : assert_19
node _T_173 = or(will_fire_load_incoming[0], will_fire_sta_incoming[0])
node _T_174 = or(_T_173, will_fire_stad_incoming[0])
node _T_175 = and(_T_174, exe_req[0].bits.mxcpt.valid)
node _T_176 = and(_T_175, dtlb.io.req[0].valid)
node _T_177 = or(exe_tlb_uop[0].ctrl.is_load, exe_tlb_uop[0].ctrl.is_sta)
node _T_178 = eq(_T_177, UInt<1>(0h0))
node _T_179 = and(_T_176, _T_178)
node _T_180 = eq(_T_179, UInt<1>(0h0))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: A uop that's not a load or store-address is throwing a memory exception.\n at lsu.scala:684 assert (!((will_fire_load_incoming(w) || will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) &&\n") : printf_20
assert(clock, _T_180, UInt<1>(0h1), "") : assert_20
connect mem_xcpt_valid, mem_xcpt_valids[0]
connect mem_xcpt_cause, mem_xcpt_causes[0]
connect mem_xcpt_uop, mem_xcpt_uops[0]
connect mem_xcpt_vaddr, mem_xcpt_vaddrs[0]
node _exe_tlb_miss_T = eq(dtlb.io.req[0].ready, UInt<1>(0h0))
node _exe_tlb_miss_T_1 = or(dtlb.io.resp[0].miss, _exe_tlb_miss_T)
node _exe_tlb_miss_T_2 = and(dtlb.io.req[0].valid, _exe_tlb_miss_T_1)
wire exe_tlb_miss : UInt<1>[1]
connect exe_tlb_miss[0], _exe_tlb_miss_T_2
node _exe_tlb_paddr_T = bits(dtlb.io.resp[0].paddr, 31, 12)
node _exe_tlb_paddr_T_1 = bits(exe_tlb_vaddr[0], 11, 0)
node _exe_tlb_paddr_T_2 = cat(_exe_tlb_paddr_T, _exe_tlb_paddr_T_1)
wire exe_tlb_paddr : UInt<32>[1]
connect exe_tlb_paddr[0], _exe_tlb_paddr_T_2
node _exe_tlb_uncacheable_T = eq(dtlb.io.resp[0].cacheable, UInt<1>(0h0))
wire exe_tlb_uncacheable : UInt<1>[1]
connect exe_tlb_uncacheable[0], _exe_tlb_uncacheable_T
node _T_184 = eq(exe_tlb_paddr[0], dtlb.io.resp[0].paddr)
node _T_185 = or(_T_184, exe_req[0].bits.sfence.valid)
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] paddrs should match.\n at lsu.scala:715 assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr || exe_req(w).bits.sfence.valid, \"[lsu] paddrs should match.\")\n") : printf_21
assert(clock, _T_185, UInt<1>(0h1), "") : assert_21
when mem_xcpt_valids[0] :
node _T_189 = or(will_fire_load_incoming[0], will_fire_stad_incoming[0])
node _T_190 = or(_T_189, will_fire_sta_incoming[0])
node _T_191 = or(_T_190, will_fire_load_retry[0])
node _T_192 = or(_T_191, will_fire_sta_retry[0])
reg REG : UInt<1>, clock
connect REG, _T_192
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(REG, UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:719 assert(RegNext(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) ||\n") : printf_22
assert(clock, REG, UInt<1>(0h1), "") : assert_22
node _T_196 = xor(mem_xcpt_uops[0].uses_ldq, mem_xcpt_uops[0].uses_stq)
node _T_197 = asUInt(reset)
node _T_198 = eq(_T_197, UInt<1>(0h0))
when _T_198 :
node _T_199 = eq(_T_196, UInt<1>(0h0))
when _T_199 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:722 assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq)\n") : printf_23
assert(clock, _T_196, UInt<1>(0h1), "") : assert_23
when mem_xcpt_uops[0].uses_ldq :
connect ldq[mem_xcpt_uops[0].ldq_idx].bits.uop.exception, UInt<1>(0h1)
else :
connect stq[mem_xcpt_uops[0].stq_idx].bits.uop.exception, UInt<1>(0h1)
connect io.dmem.brupdate, io.core.brupdate
connect io.dmem.exception, io.core.exception
connect io.dmem.rob_head_idx, io.core.rob_head_idx
connect io.dmem.rob_pnr_idx, io.core.rob_pnr_idx
wire dmem_req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1]
connect io.dmem.req.valid, dmem_req[0].valid
connect io.dmem.req.bits, dmem_req
node _dmem_req_fire_T = and(io.dmem.req.ready, io.dmem.req.valid)
node _dmem_req_fire_T_1 = and(dmem_req[0].valid, _dmem_req_fire_T)
wire dmem_req_fire : UInt<1>[1]
connect dmem_req_fire[0], _dmem_req_fire_T_1
wire _s0_executing_loads_WIRE : UInt<1>[24]
connect _s0_executing_loads_WIRE[0], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[1], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[2], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[3], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[4], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[5], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[6], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[7], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[8], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[9], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[10], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[11], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[12], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[13], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[14], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[15], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[16], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[17], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[18], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[19], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[20], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[21], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[22], UInt<1>(0h0)
connect _s0_executing_loads_WIRE[23], UInt<1>(0h0)
wire s0_executing_loads : UInt<1>[24]
connect s0_executing_loads, _s0_executing_loads_WIRE
connect dmem_req[0].valid, UInt<1>(0h0)
wire dmem_req_0_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate dmem_req_0_bits_uop_uop.debug_tsrc
invalidate dmem_req_0_bits_uop_uop.debug_fsrc
invalidate dmem_req_0_bits_uop_uop.bp_xcpt_if
invalidate dmem_req_0_bits_uop_uop.bp_debug_if
invalidate dmem_req_0_bits_uop_uop.xcpt_ma_if
invalidate dmem_req_0_bits_uop_uop.xcpt_ae_if
invalidate dmem_req_0_bits_uop_uop.xcpt_pf_if
invalidate dmem_req_0_bits_uop_uop.fp_single
invalidate dmem_req_0_bits_uop_uop.fp_val
invalidate dmem_req_0_bits_uop_uop.frs3_en
invalidate dmem_req_0_bits_uop_uop.lrs2_rtype
invalidate dmem_req_0_bits_uop_uop.lrs1_rtype
invalidate dmem_req_0_bits_uop_uop.dst_rtype
invalidate dmem_req_0_bits_uop_uop.ldst_val
invalidate dmem_req_0_bits_uop_uop.lrs3
invalidate dmem_req_0_bits_uop_uop.lrs2
invalidate dmem_req_0_bits_uop_uop.lrs1
invalidate dmem_req_0_bits_uop_uop.ldst
invalidate dmem_req_0_bits_uop_uop.ldst_is_rs1
invalidate dmem_req_0_bits_uop_uop.flush_on_commit
invalidate dmem_req_0_bits_uop_uop.is_unique
invalidate dmem_req_0_bits_uop_uop.is_sys_pc2epc
invalidate dmem_req_0_bits_uop_uop.uses_stq
invalidate dmem_req_0_bits_uop_uop.uses_ldq
invalidate dmem_req_0_bits_uop_uop.is_amo
invalidate dmem_req_0_bits_uop_uop.is_fencei
invalidate dmem_req_0_bits_uop_uop.is_fence
invalidate dmem_req_0_bits_uop_uop.mem_signed
invalidate dmem_req_0_bits_uop_uop.mem_size
invalidate dmem_req_0_bits_uop_uop.mem_cmd
invalidate dmem_req_0_bits_uop_uop.bypassable
invalidate dmem_req_0_bits_uop_uop.exc_cause
invalidate dmem_req_0_bits_uop_uop.exception
invalidate dmem_req_0_bits_uop_uop.stale_pdst
invalidate dmem_req_0_bits_uop_uop.ppred_busy
invalidate dmem_req_0_bits_uop_uop.prs3_busy
invalidate dmem_req_0_bits_uop_uop.prs2_busy
invalidate dmem_req_0_bits_uop_uop.prs1_busy
invalidate dmem_req_0_bits_uop_uop.ppred
invalidate dmem_req_0_bits_uop_uop.prs3
invalidate dmem_req_0_bits_uop_uop.prs2
invalidate dmem_req_0_bits_uop_uop.prs1
invalidate dmem_req_0_bits_uop_uop.pdst
invalidate dmem_req_0_bits_uop_uop.rxq_idx
invalidate dmem_req_0_bits_uop_uop.stq_idx
invalidate dmem_req_0_bits_uop_uop.ldq_idx
invalidate dmem_req_0_bits_uop_uop.rob_idx
invalidate dmem_req_0_bits_uop_uop.csr_addr
invalidate dmem_req_0_bits_uop_uop.imm_packed
invalidate dmem_req_0_bits_uop_uop.taken
invalidate dmem_req_0_bits_uop_uop.pc_lob
invalidate dmem_req_0_bits_uop_uop.edge_inst
invalidate dmem_req_0_bits_uop_uop.ftq_idx
invalidate dmem_req_0_bits_uop_uop.br_tag
invalidate dmem_req_0_bits_uop_uop.br_mask
invalidate dmem_req_0_bits_uop_uop.is_sfb
invalidate dmem_req_0_bits_uop_uop.is_jal
invalidate dmem_req_0_bits_uop_uop.is_jalr
invalidate dmem_req_0_bits_uop_uop.is_br
invalidate dmem_req_0_bits_uop_uop.iw_p2_poisoned
invalidate dmem_req_0_bits_uop_uop.iw_p1_poisoned
invalidate dmem_req_0_bits_uop_uop.iw_state
invalidate dmem_req_0_bits_uop_uop.ctrl.is_std
invalidate dmem_req_0_bits_uop_uop.ctrl.is_sta
invalidate dmem_req_0_bits_uop_uop.ctrl.is_load
invalidate dmem_req_0_bits_uop_uop.ctrl.csr_cmd
invalidate dmem_req_0_bits_uop_uop.ctrl.fcn_dw
invalidate dmem_req_0_bits_uop_uop.ctrl.op_fcn
invalidate dmem_req_0_bits_uop_uop.ctrl.imm_sel
invalidate dmem_req_0_bits_uop_uop.ctrl.op2_sel
invalidate dmem_req_0_bits_uop_uop.ctrl.op1_sel
invalidate dmem_req_0_bits_uop_uop.ctrl.br_type
invalidate dmem_req_0_bits_uop_uop.fu_code
invalidate dmem_req_0_bits_uop_uop.iq_type
invalidate dmem_req_0_bits_uop_uop.debug_pc
invalidate dmem_req_0_bits_uop_uop.is_rvc
invalidate dmem_req_0_bits_uop_uop.debug_inst
invalidate dmem_req_0_bits_uop_uop.inst
invalidate dmem_req_0_bits_uop_uop.uopc
connect dmem_req_0_bits_uop_uop.uopc, UInt<7>(0h0)
connect dmem_req_0_bits_uop_uop.bypassable, UInt<1>(0h0)
connect dmem_req_0_bits_uop_uop.fp_val, UInt<1>(0h0)
connect dmem_req_0_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect dmem_req_0_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect dmem_req_0_bits_uop_uop.pdst, UInt<1>(0h0)
connect dmem_req_0_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire dmem_req_0_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate dmem_req_0_bits_uop_cs.is_std
invalidate dmem_req_0_bits_uop_cs.is_sta
invalidate dmem_req_0_bits_uop_cs.is_load
invalidate dmem_req_0_bits_uop_cs.csr_cmd
invalidate dmem_req_0_bits_uop_cs.fcn_dw
invalidate dmem_req_0_bits_uop_cs.op_fcn
invalidate dmem_req_0_bits_uop_cs.imm_sel
invalidate dmem_req_0_bits_uop_cs.op2_sel
invalidate dmem_req_0_bits_uop_cs.op1_sel
invalidate dmem_req_0_bits_uop_cs.br_type
connect dmem_req_0_bits_uop_cs.br_type, UInt<4>(0h0)
connect dmem_req_0_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect dmem_req_0_bits_uop_cs.is_load, UInt<1>(0h0)
connect dmem_req_0_bits_uop_cs.is_sta, UInt<1>(0h0)
connect dmem_req_0_bits_uop_cs.is_std, UInt<1>(0h0)
connect dmem_req_0_bits_uop_uop.ctrl, dmem_req_0_bits_uop_cs
connect dmem_req[0].bits.uop, dmem_req_0_bits_uop_uop
connect dmem_req[0].bits.addr, UInt<1>(0h0)
connect dmem_req[0].bits.data, UInt<1>(0h0)
connect dmem_req[0].bits.is_hella, UInt<1>(0h0)
connect io.dmem.s1_kill[0], UInt<1>(0h0)
when will_fire_load_incoming[0] :
node _dmem_req_0_valid_T = eq(exe_tlb_miss[0], UInt<1>(0h0))
node _dmem_req_0_valid_T_1 = eq(exe_tlb_uncacheable[0], UInt<1>(0h0))
node _dmem_req_0_valid_T_2 = and(_dmem_req_0_valid_T, _dmem_req_0_valid_T_1)
connect dmem_req[0].valid, _dmem_req_0_valid_T_2
connect dmem_req[0].bits.addr, exe_tlb_paddr[0]
connect dmem_req[0].bits.uop, exe_tlb_uop[0]
connect s0_executing_loads[ldq_incoming_idx[0]], dmem_req_fire[0]
node _T_200 = eq(ldq_incoming_e[0].bits.executed, UInt<1>(0h0))
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:773 assert(!ldq_incoming_e(w).bits.executed)\n") : printf_24
assert(clock, _T_200, UInt<1>(0h1), "") : assert_24
else :
when will_fire_load_retry[0] :
node _dmem_req_0_valid_T_3 = eq(exe_tlb_miss[0], UInt<1>(0h0))
node _dmem_req_0_valid_T_4 = eq(exe_tlb_uncacheable[0], UInt<1>(0h0))
node _dmem_req_0_valid_T_5 = and(_dmem_req_0_valid_T_3, _dmem_req_0_valid_T_4)
connect dmem_req[0].valid, _dmem_req_0_valid_T_5
connect dmem_req[0].bits.addr, exe_tlb_paddr[0]
connect dmem_req[0].bits.uop, exe_tlb_uop[0]
node _T_204 = or(ldq_retry_idx, UInt<5>(0h0))
node _T_205 = bits(_T_204, 4, 0)
connect s0_executing_loads[_T_205], dmem_req_fire[0]
node _T_206 = eq(ldq[_ldq_retry_e_T_1].bits.executed, UInt<1>(0h0))
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:780 assert(!ldq_retry_e.bits.executed)\n") : printf_25
assert(clock, _T_206, UInt<1>(0h1), "") : assert_25
else :
when will_fire_store_commit[0] :
connect dmem_req[0].valid, UInt<1>(0h1)
connect dmem_req[0].bits.addr, stq[stq_execute_head].bits.addr.bits
wire dmem_req_0_bits_data_size : UInt<2>
connect dmem_req_0_bits_data_size, stq[stq_execute_head].bits.uop.mem_size
node _dmem_req_0_bits_data_T = eq(dmem_req_0_bits_data_size, UInt<1>(0h0))
node _dmem_req_0_bits_data_T_1 = bits(stq[stq_execute_head].bits.data.bits, 7, 0)
node _dmem_req_0_bits_data_T_2 = cat(_dmem_req_0_bits_data_T_1, _dmem_req_0_bits_data_T_1)
node _dmem_req_0_bits_data_T_3 = cat(_dmem_req_0_bits_data_T_2, _dmem_req_0_bits_data_T_2)
node _dmem_req_0_bits_data_T_4 = cat(_dmem_req_0_bits_data_T_3, _dmem_req_0_bits_data_T_3)
node _dmem_req_0_bits_data_T_5 = eq(dmem_req_0_bits_data_size, UInt<1>(0h1))
node _dmem_req_0_bits_data_T_6 = bits(stq[stq_execute_head].bits.data.bits, 15, 0)
node _dmem_req_0_bits_data_T_7 = cat(_dmem_req_0_bits_data_T_6, _dmem_req_0_bits_data_T_6)
node _dmem_req_0_bits_data_T_8 = cat(_dmem_req_0_bits_data_T_7, _dmem_req_0_bits_data_T_7)
node _dmem_req_0_bits_data_T_9 = eq(dmem_req_0_bits_data_size, UInt<2>(0h2))
node _dmem_req_0_bits_data_T_10 = bits(stq[stq_execute_head].bits.data.bits, 31, 0)
node _dmem_req_0_bits_data_T_11 = cat(_dmem_req_0_bits_data_T_10, _dmem_req_0_bits_data_T_10)
node _dmem_req_0_bits_data_T_12 = mux(_dmem_req_0_bits_data_T_9, _dmem_req_0_bits_data_T_11, stq[stq_execute_head].bits.data.bits)
node _dmem_req_0_bits_data_T_13 = mux(_dmem_req_0_bits_data_T_5, _dmem_req_0_bits_data_T_8, _dmem_req_0_bits_data_T_12)
node _dmem_req_0_bits_data_T_14 = mux(_dmem_req_0_bits_data_T, _dmem_req_0_bits_data_T_4, _dmem_req_0_bits_data_T_13)
connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_14
connect dmem_req[0].bits.uop, stq[stq_execute_head].bits.uop
node stq_execute_head_wrap = eq(stq_execute_head, UInt<5>(0h17))
node _stq_execute_head_T = add(stq_execute_head, UInt<1>(0h1))
node _stq_execute_head_T_1 = tail(_stq_execute_head_T, 1)
node _stq_execute_head_T_2 = mux(stq_execute_head_wrap, UInt<1>(0h0), _stq_execute_head_T_1)
node _stq_execute_head_T_3 = mux(dmem_req_fire[0], _stq_execute_head_T_2, stq_execute_head)
connect stq_execute_head, _stq_execute_head_T_3
connect stq[stq_execute_head].bits.succeeded, UInt<1>(0h0)
else :
when will_fire_load_wakeup[0] :
connect dmem_req[0].valid, UInt<1>(0h1)
connect dmem_req[0].bits.addr, ldq[_ldq_wakeup_e_T_1].bits.addr.bits
connect dmem_req[0].bits.uop, ldq[_ldq_wakeup_e_T_1].bits.uop
node _T_210 = or(ldq_wakeup_idx, UInt<5>(0h0))
node _T_211 = bits(_T_210, 4, 0)
connect s0_executing_loads[_T_211], dmem_req_fire[0]
node _T_212 = eq(ldq[_ldq_wakeup_e_T_1].bits.executed, UInt<1>(0h0))
node _T_213 = eq(ldq[_ldq_wakeup_e_T_1].bits.addr_is_virtual, UInt<1>(0h0))
node _T_214 = and(_T_212, _T_213)
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(_T_214, UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:802 assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual)\n") : printf_26
assert(clock, _T_214, UInt<1>(0h1), "") : assert_26
else :
when will_fire_hella_incoming[0] :
node _T_218 = eq(hella_state, UInt<3>(0h1))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:804 assert(hella_state === h_s1)\n") : printf_27
assert(clock, _T_218, UInt<1>(0h1), "") : assert_27
node _dmem_req_0_valid_T_6 = eq(io.hellacache.s1_kill, UInt<1>(0h0))
node _dmem_req_0_valid_T_7 = eq(exe_tlb_miss[0], UInt<1>(0h0))
node _dmem_req_0_valid_T_8 = or(_dmem_req_0_valid_T_7, hella_req.phys)
node _dmem_req_0_valid_T_9 = and(_dmem_req_0_valid_T_6, _dmem_req_0_valid_T_8)
connect dmem_req[0].valid, _dmem_req_0_valid_T_9
connect dmem_req[0].bits.addr, exe_tlb_paddr[0]
wire dmem_req_0_bits_data_size_1 : UInt<2>
connect dmem_req_0_bits_data_size_1, hella_req.size
node _dmem_req_0_bits_data_T_15 = eq(dmem_req_0_bits_data_size_1, UInt<1>(0h0))
node _dmem_req_0_bits_data_T_16 = bits(io.hellacache.s1_data.data, 7, 0)
node _dmem_req_0_bits_data_T_17 = cat(_dmem_req_0_bits_data_T_16, _dmem_req_0_bits_data_T_16)
node _dmem_req_0_bits_data_T_18 = cat(_dmem_req_0_bits_data_T_17, _dmem_req_0_bits_data_T_17)
node _dmem_req_0_bits_data_T_19 = cat(_dmem_req_0_bits_data_T_18, _dmem_req_0_bits_data_T_18)
node _dmem_req_0_bits_data_T_20 = eq(dmem_req_0_bits_data_size_1, UInt<1>(0h1))
node _dmem_req_0_bits_data_T_21 = bits(io.hellacache.s1_data.data, 15, 0)
node _dmem_req_0_bits_data_T_22 = cat(_dmem_req_0_bits_data_T_21, _dmem_req_0_bits_data_T_21)
node _dmem_req_0_bits_data_T_23 = cat(_dmem_req_0_bits_data_T_22, _dmem_req_0_bits_data_T_22)
node _dmem_req_0_bits_data_T_24 = eq(dmem_req_0_bits_data_size_1, UInt<2>(0h2))
node _dmem_req_0_bits_data_T_25 = bits(io.hellacache.s1_data.data, 31, 0)
node _dmem_req_0_bits_data_T_26 = cat(_dmem_req_0_bits_data_T_25, _dmem_req_0_bits_data_T_25)
node _dmem_req_0_bits_data_T_27 = mux(_dmem_req_0_bits_data_T_24, _dmem_req_0_bits_data_T_26, io.hellacache.s1_data.data)
node _dmem_req_0_bits_data_T_28 = mux(_dmem_req_0_bits_data_T_20, _dmem_req_0_bits_data_T_23, _dmem_req_0_bits_data_T_27)
node _dmem_req_0_bits_data_T_29 = mux(_dmem_req_0_bits_data_T_15, _dmem_req_0_bits_data_T_19, _dmem_req_0_bits_data_T_28)
connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_29
connect dmem_req[0].bits.uop.mem_cmd, hella_req.cmd
connect dmem_req[0].bits.uop.mem_size, hella_req.size
connect dmem_req[0].bits.uop.mem_signed, hella_req.signed
connect dmem_req[0].bits.is_hella, UInt<1>(0h1)
connect hella_paddr, exe_tlb_paddr[0]
else :
when will_fire_hella_wakeup[0] :
node _T_222 = eq(hella_state, UInt<3>(0h5))
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_T_222, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:821 assert(hella_state === h_replay)\n") : printf_28
assert(clock, _T_222, UInt<1>(0h1), "") : assert_28
connect dmem_req[0].valid, UInt<1>(0h1)
connect dmem_req[0].bits.addr, hella_paddr
wire dmem_req_0_bits_data_size_2 : UInt<2>
connect dmem_req_0_bits_data_size_2, hella_req.size
node _dmem_req_0_bits_data_T_30 = eq(dmem_req_0_bits_data_size_2, UInt<1>(0h0))
node _dmem_req_0_bits_data_T_31 = bits(hella_data.data, 7, 0)
node _dmem_req_0_bits_data_T_32 = cat(_dmem_req_0_bits_data_T_31, _dmem_req_0_bits_data_T_31)
node _dmem_req_0_bits_data_T_33 = cat(_dmem_req_0_bits_data_T_32, _dmem_req_0_bits_data_T_32)
node _dmem_req_0_bits_data_T_34 = cat(_dmem_req_0_bits_data_T_33, _dmem_req_0_bits_data_T_33)
node _dmem_req_0_bits_data_T_35 = eq(dmem_req_0_bits_data_size_2, UInt<1>(0h1))
node _dmem_req_0_bits_data_T_36 = bits(hella_data.data, 15, 0)
node _dmem_req_0_bits_data_T_37 = cat(_dmem_req_0_bits_data_T_36, _dmem_req_0_bits_data_T_36)
node _dmem_req_0_bits_data_T_38 = cat(_dmem_req_0_bits_data_T_37, _dmem_req_0_bits_data_T_37)
node _dmem_req_0_bits_data_T_39 = eq(dmem_req_0_bits_data_size_2, UInt<2>(0h2))
node _dmem_req_0_bits_data_T_40 = bits(hella_data.data, 31, 0)
node _dmem_req_0_bits_data_T_41 = cat(_dmem_req_0_bits_data_T_40, _dmem_req_0_bits_data_T_40)
node _dmem_req_0_bits_data_T_42 = mux(_dmem_req_0_bits_data_T_39, _dmem_req_0_bits_data_T_41, hella_data.data)
node _dmem_req_0_bits_data_T_43 = mux(_dmem_req_0_bits_data_T_35, _dmem_req_0_bits_data_T_38, _dmem_req_0_bits_data_T_42)
node _dmem_req_0_bits_data_T_44 = mux(_dmem_req_0_bits_data_T_30, _dmem_req_0_bits_data_T_34, _dmem_req_0_bits_data_T_43)
connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_44
connect dmem_req[0].bits.uop.mem_cmd, hella_req.cmd
connect dmem_req[0].bits.uop.mem_size, hella_req.size
connect dmem_req[0].bits.uop.mem_signed, hella_req.signed
connect dmem_req[0].bits.is_hella, UInt<1>(0h1)
node _T_226 = or(will_fire_load_incoming[0], will_fire_load_retry[0])
when _T_226 :
node ldq_idx = mux(will_fire_load_incoming[0], ldq_incoming_idx[0], ldq_retry_idx)
node _T_227 = or(ldq_idx, UInt<5>(0h0))
node _T_228 = bits(_T_227, 4, 0)
connect ldq[_T_228].bits.addr.valid, UInt<1>(0h1)
node _T_229 = or(ldq_idx, UInt<5>(0h0))
node _T_230 = bits(_T_229, 4, 0)
node _ldq_bits_addr_bits_T = mux(exe_tlb_miss[0], exe_tlb_vaddr[0], exe_tlb_paddr[0])
connect ldq[_T_230].bits.addr.bits, _ldq_bits_addr_bits_T
node _T_231 = or(ldq_idx, UInt<5>(0h0))
node _T_232 = bits(_T_231, 4, 0)
connect ldq[_T_232].bits.uop.pdst, exe_tlb_uop[0].pdst
node _T_233 = or(ldq_idx, UInt<5>(0h0))
node _T_234 = bits(_T_233, 4, 0)
connect ldq[_T_234].bits.addr_is_virtual, exe_tlb_miss[0]
node _T_235 = or(ldq_idx, UInt<5>(0h0))
node _T_236 = bits(_T_235, 4, 0)
node _ldq_bits_addr_is_uncacheable_T = eq(exe_tlb_miss[0], UInt<1>(0h0))
node _ldq_bits_addr_is_uncacheable_T_1 = and(exe_tlb_uncacheable[0], _ldq_bits_addr_is_uncacheable_T)
connect ldq[_T_236].bits.addr_is_uncacheable, _ldq_bits_addr_is_uncacheable_T_1
node _T_237 = and(will_fire_load_incoming[0], ldq_incoming_e[0].bits.addr.valid)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(_T_238, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Incoming load is overwriting a valid address\n at lsu.scala:845 assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid),\n") : printf_29
assert(clock, _T_238, UInt<1>(0h1), "") : assert_29
node _T_242 = or(will_fire_sta_incoming[0], will_fire_stad_incoming[0])
node _T_243 = or(_T_242, will_fire_sta_retry[0])
when _T_243 :
node _stq_idx_T = or(will_fire_sta_incoming[0], will_fire_stad_incoming[0])
node stq_idx = mux(_stq_idx_T, stq_incoming_idx[0], stq_retry_idx)
node _T_244 = or(stq_idx, UInt<5>(0h0))
node _T_245 = bits(_T_244, 4, 0)
node _stq_bits_addr_valid_T = eq(pf_st[0], UInt<1>(0h0))
connect stq[_T_245].bits.addr.valid, _stq_bits_addr_valid_T
node _T_246 = or(stq_idx, UInt<5>(0h0))
node _T_247 = bits(_T_246, 4, 0)
node _stq_bits_addr_bits_T = mux(exe_tlb_miss[0], exe_tlb_vaddr[0], exe_tlb_paddr[0])
connect stq[_T_247].bits.addr.bits, _stq_bits_addr_bits_T
node _T_248 = or(stq_idx, UInt<5>(0h0))
node _T_249 = bits(_T_248, 4, 0)
connect stq[_T_249].bits.uop.pdst, exe_tlb_uop[0].pdst
node _T_250 = or(stq_idx, UInt<5>(0h0))
node _T_251 = bits(_T_250, 4, 0)
connect stq[_T_251].bits.addr_is_virtual, exe_tlb_miss[0]
node _T_252 = and(will_fire_sta_incoming[0], stq_incoming_e[0].bits.addr.valid)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Incoming store is overwriting a valid address\n at lsu.scala:859 assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid),\n") : printf_30
assert(clock, _T_253, UInt<1>(0h1), "") : assert_30
node _io_core_fp_stdata_ready_T = eq(will_fire_std_incoming[0], UInt<1>(0h0))
node _io_core_fp_stdata_ready_T_1 = eq(will_fire_stad_incoming[0], UInt<1>(0h0))
node _io_core_fp_stdata_ready_T_2 = and(_io_core_fp_stdata_ready_T, _io_core_fp_stdata_ready_T_1)
connect io.core.fp_stdata.ready, _io_core_fp_stdata_ready_T_2
node _fp_stdata_fire_T = and(io.core.fp_stdata.ready, io.core.fp_stdata.valid)
node fp_stdata_fire = and(_fp_stdata_fire_T, UInt<1>(0h1))
node _T_257 = or(will_fire_std_incoming[0], will_fire_stad_incoming[0])
node _T_258 = or(_T_257, fp_stdata_fire)
when _T_258 :
node _sidx_T = or(will_fire_std_incoming[0], will_fire_stad_incoming[0])
node sidx = mux(_sidx_T, stq_incoming_idx[0], io.core.fp_stdata.bits.uop.stq_idx)
connect stq[sidx].bits.data.valid, UInt<1>(0h1)
node _stq_bits_data_bits_T = or(will_fire_std_incoming[0], will_fire_stad_incoming[0])
node _stq_bits_data_bits_T_1 = mux(_stq_bits_data_bits_T, exe_req[0].bits.data, io.core.fp_stdata.bits.data)
connect stq[sidx].bits.data.bits, _stq_bits_data_bits_T_1
node _T_259 = eq(stq[sidx].bits.data.valid, UInt<1>(0h0))
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Incoming store is overwriting a valid data entry\n at lsu.scala:878 assert(!(stq(sidx).bits.data.valid),\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node will_fire_stdf_incoming = and(io.core.fp_stdata.ready, io.core.fp_stdata.valid)
node _exe_req_killed_T = and(io.core.brupdate.b1.mispredict_mask, exe_req[0].bits.uop.br_mask)
node _exe_req_killed_T_1 = neq(_exe_req_killed_T, UInt<1>(0h0))
wire exe_req_killed : UInt<1>[1]
connect exe_req_killed[0], _exe_req_killed_T_1
node _stdf_killed_T = and(io.core.brupdate.b1.mispredict_mask, io.core.fp_stdata.bits.uop.br_mask)
node stdf_killed = neq(_stdf_killed_T, UInt<1>(0h0))
node _fired_load_incoming_T = eq(exe_req_killed[0], UInt<1>(0h0))
node _fired_load_incoming_T_1 = and(will_fire_load_incoming[0], _fired_load_incoming_T)
reg fired_load_incoming_REG : UInt<1>, clock
connect fired_load_incoming_REG, _fired_load_incoming_T_1
wire fired_load_incoming : UInt<1>[1]
connect fired_load_incoming[0], fired_load_incoming_REG
node _fired_stad_incoming_T = eq(exe_req_killed[0], UInt<1>(0h0))
node _fired_stad_incoming_T_1 = and(will_fire_stad_incoming[0], _fired_stad_incoming_T)
reg fired_stad_incoming_REG : UInt<1>, clock
connect fired_stad_incoming_REG, _fired_stad_incoming_T_1
wire fired_stad_incoming : UInt<1>[1]
connect fired_stad_incoming[0], fired_stad_incoming_REG
node _fired_sta_incoming_T = eq(exe_req_killed[0], UInt<1>(0h0))
node _fired_sta_incoming_T_1 = and(will_fire_sta_incoming[0], _fired_sta_incoming_T)
reg fired_sta_incoming_REG : UInt<1>, clock
connect fired_sta_incoming_REG, _fired_sta_incoming_T_1
wire fired_sta_incoming : UInt<1>[1]
connect fired_sta_incoming[0], fired_sta_incoming_REG
node _fired_std_incoming_T = eq(exe_req_killed[0], UInt<1>(0h0))
node _fired_std_incoming_T_1 = and(will_fire_std_incoming[0], _fired_std_incoming_T)
reg fired_std_incoming_REG : UInt<1>, clock
connect fired_std_incoming_REG, _fired_std_incoming_T_1
wire fired_std_incoming : UInt<1>[1]
connect fired_std_incoming[0], fired_std_incoming_REG
node _fired_stdf_incoming_T = eq(stdf_killed, UInt<1>(0h0))
node _fired_stdf_incoming_T_1 = and(will_fire_stdf_incoming, _fired_stdf_incoming_T)
reg fired_stdf_incoming : UInt<1>, clock
connect fired_stdf_incoming, _fired_stdf_incoming_T_1
reg fired_sfence : UInt<1>[1], clock
connect fired_sfence, will_fire_sfence
reg fired_release : UInt<1>[1], clock
connect fired_release, will_fire_release
node _fired_load_retry_T = and(io.core.brupdate.b1.mispredict_mask, ldq[_ldq_retry_e_T_1].bits.uop.br_mask)
node _fired_load_retry_T_1 = neq(_fired_load_retry_T, UInt<1>(0h0))
node _fired_load_retry_T_2 = eq(_fired_load_retry_T_1, UInt<1>(0h0))
node _fired_load_retry_T_3 = and(will_fire_load_retry[0], _fired_load_retry_T_2)
reg fired_load_retry_REG : UInt<1>, clock
connect fired_load_retry_REG, _fired_load_retry_T_3
wire fired_load_retry : UInt<1>[1]
connect fired_load_retry[0], fired_load_retry_REG
node _fired_sta_retry_T = and(io.core.brupdate.b1.mispredict_mask, stq[_stq_retry_e_T_1].bits.uop.br_mask)
node _fired_sta_retry_T_1 = neq(_fired_sta_retry_T, UInt<1>(0h0))
node _fired_sta_retry_T_2 = eq(_fired_sta_retry_T_1, UInt<1>(0h0))
node _fired_sta_retry_T_3 = and(will_fire_sta_retry[0], _fired_sta_retry_T_2)
reg fired_sta_retry_REG : UInt<1>, clock
connect fired_sta_retry_REG, _fired_sta_retry_T_3
wire fired_sta_retry : UInt<1>[1]
connect fired_sta_retry[0], fired_sta_retry_REG
reg fired_store_commit : UInt<1>[1], clock
connect fired_store_commit, will_fire_store_commit
node _fired_load_wakeup_T = and(io.core.brupdate.b1.mispredict_mask, ldq[_ldq_wakeup_e_T_1].bits.uop.br_mask)
node _fired_load_wakeup_T_1 = neq(_fired_load_wakeup_T, UInt<1>(0h0))
node _fired_load_wakeup_T_2 = eq(_fired_load_wakeup_T_1, UInt<1>(0h0))
node _fired_load_wakeup_T_3 = and(will_fire_load_wakeup[0], _fired_load_wakeup_T_2)
reg fired_load_wakeup_REG : UInt<1>, clock
connect fired_load_wakeup_REG, _fired_load_wakeup_T_3
wire fired_load_wakeup : UInt<1>[1]
connect fired_load_wakeup[0], fired_load_wakeup_REG
reg fired_hella_incoming : UInt<1>[1], clock
connect fired_hella_incoming, will_fire_hella_incoming
reg fired_hella_wakeup : UInt<1>[1], clock
connect fired_hella_wakeup, will_fire_hella_wakeup
wire mem_incoming_uop_out : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect mem_incoming_uop_out, exe_req[0].bits.uop
node _mem_incoming_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_incoming_uop_out_br_mask_T_1 = and(exe_req[0].bits.uop.br_mask, _mem_incoming_uop_out_br_mask_T)
connect mem_incoming_uop_out.br_mask, _mem_incoming_uop_out_br_mask_T_1
wire _mem_incoming_uop_WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
connect _mem_incoming_uop_WIRE[0], mem_incoming_uop_out
reg mem_incoming_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], clock
connect mem_incoming_uop, _mem_incoming_uop_WIRE
wire mem_ldq_incoming_e_out : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}
connect mem_ldq_incoming_e_out, ldq_incoming_e[0]
node _mem_ldq_incoming_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = and(ldq_incoming_e[0].bits.uop.br_mask, _mem_ldq_incoming_e_out_bits_uop_br_mask_T)
connect mem_ldq_incoming_e_out.bits.uop.br_mask, _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1
node _mem_ldq_incoming_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, ldq_incoming_e[0].bits.uop.br_mask)
node _mem_ldq_incoming_e_out_valid_T_1 = neq(_mem_ldq_incoming_e_out_valid_T, UInt<1>(0h0))
node _mem_ldq_incoming_e_out_valid_T_2 = eq(_mem_ldq_incoming_e_out_valid_T_1, UInt<1>(0h0))
node _mem_ldq_incoming_e_out_valid_T_3 = and(ldq_incoming_e[0].valid, _mem_ldq_incoming_e_out_valid_T_2)
connect mem_ldq_incoming_e_out.valid, _mem_ldq_incoming_e_out_valid_T_3
wire _mem_ldq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1]
connect _mem_ldq_incoming_e_WIRE[0], mem_ldq_incoming_e_out
reg mem_ldq_incoming_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1], clock
connect mem_ldq_incoming_e, _mem_ldq_incoming_e_WIRE
wire mem_stq_incoming_e_out : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}
connect mem_stq_incoming_e_out, stq_incoming_e[0]
node _mem_stq_incoming_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = and(stq_incoming_e[0].bits.uop.br_mask, _mem_stq_incoming_e_out_bits_uop_br_mask_T)
connect mem_stq_incoming_e_out.bits.uop.br_mask, _mem_stq_incoming_e_out_bits_uop_br_mask_T_1
node _mem_stq_incoming_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, stq_incoming_e[0].bits.uop.br_mask)
node _mem_stq_incoming_e_out_valid_T_1 = neq(_mem_stq_incoming_e_out_valid_T, UInt<1>(0h0))
node _mem_stq_incoming_e_out_valid_T_2 = eq(_mem_stq_incoming_e_out_valid_T_1, UInt<1>(0h0))
node _mem_stq_incoming_e_out_valid_T_3 = and(stq_incoming_e[0].valid, _mem_stq_incoming_e_out_valid_T_2)
connect mem_stq_incoming_e_out.valid, _mem_stq_incoming_e_out_valid_T_3
wire _mem_stq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}[1]
connect _mem_stq_incoming_e_WIRE[0], mem_stq_incoming_e_out
reg mem_stq_incoming_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}[1], clock
connect mem_stq_incoming_e, _mem_stq_incoming_e_WIRE
wire mem_ldq_wakeup_e_out : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}
connect mem_ldq_wakeup_e_out, ldq[_ldq_wakeup_e_T_1]
node _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = and(ldq[_ldq_wakeup_e_T_1].bits.uop.br_mask, _mem_ldq_wakeup_e_out_bits_uop_br_mask_T)
connect mem_ldq_wakeup_e_out.bits.uop.br_mask, _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1
node _mem_ldq_wakeup_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, ldq[_ldq_wakeup_e_T_1].bits.uop.br_mask)
node _mem_ldq_wakeup_e_out_valid_T_1 = neq(_mem_ldq_wakeup_e_out_valid_T, UInt<1>(0h0))
node _mem_ldq_wakeup_e_out_valid_T_2 = eq(_mem_ldq_wakeup_e_out_valid_T_1, UInt<1>(0h0))
node _mem_ldq_wakeup_e_out_valid_T_3 = and(ldq[_ldq_wakeup_e_T_1].valid, _mem_ldq_wakeup_e_out_valid_T_2)
connect mem_ldq_wakeup_e_out.valid, _mem_ldq_wakeup_e_out_valid_T_3
reg mem_ldq_wakeup_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}, clock
connect mem_ldq_wakeup_e, mem_ldq_wakeup_e_out
wire mem_ldq_retry_e_out : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}
connect mem_ldq_retry_e_out, ldq[_ldq_retry_e_T_1]
node _mem_ldq_retry_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = and(ldq[_ldq_retry_e_T_1].bits.uop.br_mask, _mem_ldq_retry_e_out_bits_uop_br_mask_T)
connect mem_ldq_retry_e_out.bits.uop.br_mask, _mem_ldq_retry_e_out_bits_uop_br_mask_T_1
node _mem_ldq_retry_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, ldq[_ldq_retry_e_T_1].bits.uop.br_mask)
node _mem_ldq_retry_e_out_valid_T_1 = neq(_mem_ldq_retry_e_out_valid_T, UInt<1>(0h0))
node _mem_ldq_retry_e_out_valid_T_2 = eq(_mem_ldq_retry_e_out_valid_T_1, UInt<1>(0h0))
node _mem_ldq_retry_e_out_valid_T_3 = and(ldq[_ldq_retry_e_T_1].valid, _mem_ldq_retry_e_out_valid_T_2)
connect mem_ldq_retry_e_out.valid, _mem_ldq_retry_e_out_valid_T_3
reg mem_ldq_retry_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}, clock
connect mem_ldq_retry_e, mem_ldq_retry_e_out
wire mem_stq_retry_e_out : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}
connect mem_stq_retry_e_out, stq[_stq_retry_e_T_1]
node _mem_stq_retry_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = and(stq[_stq_retry_e_T_1].bits.uop.br_mask, _mem_stq_retry_e_out_bits_uop_br_mask_T)
connect mem_stq_retry_e_out.bits.uop.br_mask, _mem_stq_retry_e_out_bits_uop_br_mask_T_1
node _mem_stq_retry_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, stq[_stq_retry_e_T_1].bits.uop.br_mask)
node _mem_stq_retry_e_out_valid_T_1 = neq(_mem_stq_retry_e_out_valid_T, UInt<1>(0h0))
node _mem_stq_retry_e_out_valid_T_2 = eq(_mem_stq_retry_e_out_valid_T_1, UInt<1>(0h0))
node _mem_stq_retry_e_out_valid_T_3 = and(stq[_stq_retry_e_T_1].valid, _mem_stq_retry_e_out_valid_T_2)
connect mem_stq_retry_e_out.valid, _mem_stq_retry_e_out_valid_T_3
reg mem_stq_retry_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}, clock
connect mem_stq_retry_e, mem_stq_retry_e_out
wire _mem_ldq_e_WIRE : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}
connect _mem_ldq_e_WIRE.bits.debug_wb_data, UInt<64>(0h0)
connect _mem_ldq_e_WIRE.bits.forward_stq_idx, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.forward_std_val, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.youngest_stq_idx, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.st_dep_mask, UInt<24>(0h0)
connect _mem_ldq_e_WIRE.bits.observed, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.order_fail, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.succeeded, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.executed, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.addr_is_uncacheable, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.addr_is_virtual, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.addr.bits, UInt<40>(0h0)
connect _mem_ldq_e_WIRE.bits.addr.valid, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.debug_tsrc, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.debug_fsrc, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.bp_xcpt_if, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.bp_debug_if, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.xcpt_ma_if, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.xcpt_ae_if, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.xcpt_pf_if, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.fp_single, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.fp_val, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.frs3_en, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.lrs2_rtype, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.lrs1_rtype, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.dst_rtype, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ldst_val, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.lrs3, UInt<6>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.lrs2, UInt<6>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.lrs1, UInt<6>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ldst, UInt<6>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ldst_is_rs1, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.flush_on_commit, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_unique, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_sys_pc2epc, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.uses_stq, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.uses_ldq, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_amo, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_fencei, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_fence, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.mem_signed, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.mem_size, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.mem_cmd, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.bypassable, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.exc_cause, UInt<64>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.exception, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.stale_pdst, UInt<7>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ppred_busy, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.prs3_busy, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.prs2_busy, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.prs1_busy, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ppred, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.prs3, UInt<7>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.prs2, UInt<7>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.prs1, UInt<7>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.pdst, UInt<7>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.rxq_idx, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.stq_idx, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ldq_idx, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.rob_idx, UInt<7>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.csr_addr, UInt<12>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.imm_packed, UInt<20>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.taken, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.pc_lob, UInt<6>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.edge_inst, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ftq_idx, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.br_tag, UInt<4>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.br_mask, UInt<16>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_sfb, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_jal, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_jalr, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_br, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.iw_p2_poisoned, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.iw_p1_poisoned, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.iw_state, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.is_std, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.is_sta, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.is_load, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.csr_cmd, UInt<3>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.fcn_dw, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.op_fcn, UInt<5>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.imm_sel, UInt<3>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.op2_sel, UInt<3>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.op1_sel, UInt<2>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.ctrl.br_type, UInt<4>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.fu_code, UInt<10>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.iq_type, UInt<3>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.debug_pc, UInt<40>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.is_rvc, UInt<1>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.debug_inst, UInt<32>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.inst, UInt<32>(0h0)
connect _mem_ldq_e_WIRE.bits.uop.uopc, UInt<7>(0h0)
connect _mem_ldq_e_WIRE.valid, UInt<1>(0h0)
node _mem_ldq_e_T = mux(fired_load_wakeup[0], mem_ldq_wakeup_e, _mem_ldq_e_WIRE)
node _mem_ldq_e_T_1 = mux(fired_load_retry[0], mem_ldq_retry_e, _mem_ldq_e_T)
node _mem_ldq_e_T_2 = mux(fired_load_incoming[0], mem_ldq_incoming_e[0], _mem_ldq_e_T_1)
wire mem_ldq_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, youngest_stq_idx : UInt<5>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1]
connect mem_ldq_e[0], _mem_ldq_e_T_2
node _mem_stq_e_T = or(fired_stad_incoming[0], fired_sta_incoming[0])
wire _mem_stq_e_WIRE : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}
connect _mem_stq_e_WIRE.bits.debug_wb_data, UInt<64>(0h0)
connect _mem_stq_e_WIRE.bits.succeeded, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.committed, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.data.bits, UInt<64>(0h0)
connect _mem_stq_e_WIRE.bits.data.valid, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.addr_is_virtual, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.addr.bits, UInt<40>(0h0)
connect _mem_stq_e_WIRE.bits.addr.valid, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.debug_tsrc, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.debug_fsrc, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.bp_xcpt_if, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.bp_debug_if, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.xcpt_ma_if, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.xcpt_ae_if, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.xcpt_pf_if, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.fp_single, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.fp_val, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.frs3_en, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.lrs2_rtype, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.lrs1_rtype, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.dst_rtype, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ldst_val, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.lrs3, UInt<6>(0h0)
connect _mem_stq_e_WIRE.bits.uop.lrs2, UInt<6>(0h0)
connect _mem_stq_e_WIRE.bits.uop.lrs1, UInt<6>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ldst, UInt<6>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ldst_is_rs1, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.flush_on_commit, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_unique, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_sys_pc2epc, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.uses_stq, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.uses_ldq, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_amo, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_fencei, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_fence, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.mem_signed, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.mem_size, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.mem_cmd, UInt<5>(0h0)
connect _mem_stq_e_WIRE.bits.uop.bypassable, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.exc_cause, UInt<64>(0h0)
connect _mem_stq_e_WIRE.bits.uop.exception, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.stale_pdst, UInt<7>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ppred_busy, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.prs3_busy, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.prs2_busy, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.prs1_busy, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ppred, UInt<5>(0h0)
connect _mem_stq_e_WIRE.bits.uop.prs3, UInt<7>(0h0)
connect _mem_stq_e_WIRE.bits.uop.prs2, UInt<7>(0h0)
connect _mem_stq_e_WIRE.bits.uop.prs1, UInt<7>(0h0)
connect _mem_stq_e_WIRE.bits.uop.pdst, UInt<7>(0h0)
connect _mem_stq_e_WIRE.bits.uop.rxq_idx, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.stq_idx, UInt<5>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ldq_idx, UInt<5>(0h0)
connect _mem_stq_e_WIRE.bits.uop.rob_idx, UInt<7>(0h0)
connect _mem_stq_e_WIRE.bits.uop.csr_addr, UInt<12>(0h0)
connect _mem_stq_e_WIRE.bits.uop.imm_packed, UInt<20>(0h0)
connect _mem_stq_e_WIRE.bits.uop.taken, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.pc_lob, UInt<6>(0h0)
connect _mem_stq_e_WIRE.bits.uop.edge_inst, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ftq_idx, UInt<5>(0h0)
connect _mem_stq_e_WIRE.bits.uop.br_tag, UInt<4>(0h0)
connect _mem_stq_e_WIRE.bits.uop.br_mask, UInt<16>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_sfb, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_jal, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_jalr, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_br, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.iw_p2_poisoned, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.iw_p1_poisoned, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.iw_state, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.is_std, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.is_sta, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.is_load, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.csr_cmd, UInt<3>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.fcn_dw, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.op_fcn, UInt<5>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.imm_sel, UInt<3>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.op2_sel, UInt<3>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.op1_sel, UInt<2>(0h0)
connect _mem_stq_e_WIRE.bits.uop.ctrl.br_type, UInt<4>(0h0)
connect _mem_stq_e_WIRE.bits.uop.fu_code, UInt<10>(0h0)
connect _mem_stq_e_WIRE.bits.uop.iq_type, UInt<3>(0h0)
connect _mem_stq_e_WIRE.bits.uop.debug_pc, UInt<40>(0h0)
connect _mem_stq_e_WIRE.bits.uop.is_rvc, UInt<1>(0h0)
connect _mem_stq_e_WIRE.bits.uop.debug_inst, UInt<32>(0h0)
connect _mem_stq_e_WIRE.bits.uop.inst, UInt<32>(0h0)
connect _mem_stq_e_WIRE.bits.uop.uopc, UInt<7>(0h0)
connect _mem_stq_e_WIRE.valid, UInt<1>(0h0)
node _mem_stq_e_T_1 = mux(fired_sta_retry[0], mem_stq_retry_e, _mem_stq_e_WIRE)
node _mem_stq_e_T_2 = mux(_mem_stq_e_T, mem_stq_incoming_e[0], _mem_stq_e_T_1)
wire mem_stq_e : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, debug_wb_data : UInt<64>}}[1]
connect mem_stq_e[0], _mem_stq_e_T_2
wire mem_stdf_uop_out : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect mem_stdf_uop_out, io.core.fp_stdata.bits.uop
node _mem_stdf_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _mem_stdf_uop_out_br_mask_T_1 = and(io.core.fp_stdata.bits.uop.br_mask, _mem_stdf_uop_out_br_mask_T)
connect mem_stdf_uop_out.br_mask, _mem_stdf_uop_out_br_mask_T_1
reg mem_stdf_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
connect mem_stdf_uop, mem_stdf_uop_out
reg mem_tlb_miss : UInt<1>[1], clock
connect mem_tlb_miss, exe_tlb_miss
reg mem_tlb_uncacheable : UInt<1>[1], clock
connect mem_tlb_uncacheable, exe_tlb_uncacheable
wire _mem_paddr_WIRE : UInt<40>[1]
connect _mem_paddr_WIRE[0], dmem_req[0].bits.addr
reg mem_paddr : UInt<40>[1], clock
connect mem_paddr, _mem_paddr_WIRE
wire _clr_bsy_valid_WIRE : UInt<1>[1]
connect _clr_bsy_valid_WIRE[0], UInt<1>(0h0)
regreset clr_bsy_valid : UInt<1>[1], clock, reset, _clr_bsy_valid_WIRE
reg clr_bsy_rob_idx : UInt<7>[1], clock
reg clr_bsy_brmask : UInt<16>[1], clock
connect clr_bsy_valid[0], UInt<1>(0h0)
connect clr_bsy_rob_idx[0], UInt<1>(0h0)
connect clr_bsy_brmask[0], UInt<1>(0h0)
when fired_stad_incoming[0] :
node _clr_bsy_valid_0_T = eq(mem_tlb_miss[0], UInt<1>(0h0))
node _clr_bsy_valid_0_T_1 = and(mem_stq_incoming_e[0].valid, _clr_bsy_valid_0_T)
node _clr_bsy_valid_0_T_2 = eq(mem_stq_incoming_e[0].bits.uop.is_amo, UInt<1>(0h0))
node _clr_bsy_valid_0_T_3 = and(_clr_bsy_valid_0_T_1, _clr_bsy_valid_0_T_2)
node _clr_bsy_valid_0_T_4 = and(io.core.brupdate.b1.mispredict_mask, mem_stq_incoming_e[0].bits.uop.br_mask)
node _clr_bsy_valid_0_T_5 = neq(_clr_bsy_valid_0_T_4, UInt<1>(0h0))
node _clr_bsy_valid_0_T_6 = eq(_clr_bsy_valid_0_T_5, UInt<1>(0h0))
node _clr_bsy_valid_0_T_7 = and(_clr_bsy_valid_0_T_3, _clr_bsy_valid_0_T_6)
connect clr_bsy_valid[0], _clr_bsy_valid_0_T_7
connect clr_bsy_rob_idx[0], mem_stq_incoming_e[0].bits.uop.rob_idx
node _clr_bsy_brmask_0_T = not(io.core.brupdate.b1.resolve_mask)
node _clr_bsy_brmask_0_T_1 = and(mem_stq_incoming_e[0].bits.uop.br_mask, _clr_bsy_brmask_0_T)
connect clr_bsy_brmask[0], _clr_bsy_brmask_0_T_1
else :
when fired_sta_incoming[0] :
node _clr_bsy_valid_0_T_8 = and(mem_stq_incoming_e[0].valid, mem_stq_incoming_e[0].bits.data.valid)
node _clr_bsy_valid_0_T_9 = eq(mem_tlb_miss[0], UInt<1>(0h0))
node _clr_bsy_valid_0_T_10 = and(_clr_bsy_valid_0_T_8, _clr_bsy_valid_0_T_9)
node _clr_bsy_valid_0_T_11 = eq(mem_stq_incoming_e[0].bits.uop.is_amo, UInt<1>(0h0))
node _clr_bsy_valid_0_T_12 = and(_clr_bsy_valid_0_T_10, _clr_bsy_valid_0_T_11)
node _clr_bsy_valid_0_T_13 = and(io.core.brupdate.b1.mispredict_mask, mem_stq_incoming_e[0].bits.uop.br_mask)
node _clr_bsy_valid_0_T_14 = neq(_clr_bsy_valid_0_T_13, UInt<1>(0h0))
node _clr_bsy_valid_0_T_15 = eq(_clr_bsy_valid_0_T_14, UInt<1>(0h0))
node _clr_bsy_valid_0_T_16 = and(_clr_bsy_valid_0_T_12, _clr_bsy_valid_0_T_15)
connect clr_bsy_valid[0], _clr_bsy_valid_0_T_16
connect clr_bsy_rob_idx[0], mem_stq_incoming_e[0].bits.uop.rob_idx
node _clr_bsy_brmask_0_T_2 = not(io.core.brupdate.b1.resolve_mask)
node _clr_bsy_brmask_0_T_3 = and(mem_stq_incoming_e[0].bits.uop.br_mask, _clr_bsy_brmask_0_T_2)
connect clr_bsy_brmask[0], _clr_bsy_brmask_0_T_3
else :
when fired_std_incoming[0] :
node _clr_bsy_valid_0_T_17 = and(mem_stq_incoming_e[0].valid, mem_stq_incoming_e[0].bits.addr.valid)
node _clr_bsy_valid_0_T_18 = eq(mem_stq_incoming_e[0].bits.addr_is_virtual, UInt<1>(0h0))
node _clr_bsy_valid_0_T_19 = and(_clr_bsy_valid_0_T_17, _clr_bsy_valid_0_T_18)
node _clr_bsy_valid_0_T_20 = eq(mem_stq_incoming_e[0].bits.uop.is_amo, UInt<1>(0h0))
node _clr_bsy_valid_0_T_21 = and(_clr_bsy_valid_0_T_19, _clr_bsy_valid_0_T_20)
node _clr_bsy_valid_0_T_22 = and(io.core.brupdate.b1.mispredict_mask, mem_stq_incoming_e[0].bits.uop.br_mask)
node _clr_bsy_valid_0_T_23 = neq(_clr_bsy_valid_0_T_22, UInt<1>(0h0))
node _clr_bsy_valid_0_T_24 = eq(_clr_bsy_valid_0_T_23, UInt<1>(0h0))
node _clr_bsy_valid_0_T_25 = and(_clr_bsy_valid_0_T_21, _clr_bsy_valid_0_T_24)
connect clr_bsy_valid[0], _clr_bsy_valid_0_T_25
connect clr_bsy_rob_idx[0], mem_stq_incoming_e[0].bits.uop.rob_idx
node _clr_bsy_brmask_0_T_4 = not(io.core.brupdate.b1.resolve_mask)
node _clr_bsy_brmask_0_T_5 = and(mem_stq_incoming_e[0].bits.uop.br_mask, _clr_bsy_brmask_0_T_4)
connect clr_bsy_brmask[0], _clr_bsy_brmask_0_T_5
else :
when fired_sfence[0] :
connect clr_bsy_valid[0], UInt<1>(0h1)
connect clr_bsy_rob_idx[0], mem_incoming_uop[0].rob_idx
node _clr_bsy_brmask_0_T_6 = not(io.core.brupdate.b1.resolve_mask)
node _clr_bsy_brmask_0_T_7 = and(mem_incoming_uop[0].br_mask, _clr_bsy_brmask_0_T_6)
connect clr_bsy_brmask[0], _clr_bsy_brmask_0_T_7
else :
when fired_sta_retry[0] :
node _clr_bsy_valid_0_T_26 = and(mem_stq_retry_e.valid, mem_stq_retry_e.bits.data.valid)
node _clr_bsy_valid_0_T_27 = eq(mem_tlb_miss[0], UInt<1>(0h0))
node _clr_bsy_valid_0_T_28 = and(_clr_bsy_valid_0_T_26, _clr_bsy_valid_0_T_27)
node _clr_bsy_valid_0_T_29 = eq(mem_stq_retry_e.bits.uop.is_amo, UInt<1>(0h0))
node _clr_bsy_valid_0_T_30 = and(_clr_bsy_valid_0_T_28, _clr_bsy_valid_0_T_29)
node _clr_bsy_valid_0_T_31 = and(io.core.brupdate.b1.mispredict_mask, mem_stq_retry_e.bits.uop.br_mask)
node _clr_bsy_valid_0_T_32 = neq(_clr_bsy_valid_0_T_31, UInt<1>(0h0))
node _clr_bsy_valid_0_T_33 = eq(_clr_bsy_valid_0_T_32, UInt<1>(0h0))
node _clr_bsy_valid_0_T_34 = and(_clr_bsy_valid_0_T_30, _clr_bsy_valid_0_T_33)
connect clr_bsy_valid[0], _clr_bsy_valid_0_T_34
connect clr_bsy_rob_idx[0], mem_stq_retry_e.bits.uop.rob_idx
node _clr_bsy_brmask_0_T_8 = not(io.core.brupdate.b1.resolve_mask)
node _clr_bsy_brmask_0_T_9 = and(mem_stq_retry_e.bits.uop.br_mask, _clr_bsy_brmask_0_T_8)
connect clr_bsy_brmask[0], _clr_bsy_brmask_0_T_9
node _io_core_clr_bsy_0_valid_T = and(io.core.brupdate.b1.mispredict_mask, clr_bsy_brmask[0])
node _io_core_clr_bsy_0_valid_T_1 = neq(_io_core_clr_bsy_0_valid_T, UInt<1>(0h0))
node _io_core_clr_bsy_0_valid_T_2 = eq(_io_core_clr_bsy_0_valid_T_1, UInt<1>(0h0))
node _io_core_clr_bsy_0_valid_T_3 = and(clr_bsy_valid[0], _io_core_clr_bsy_0_valid_T_2)
node _io_core_clr_bsy_0_valid_T_4 = eq(io.core.exception, UInt<1>(0h0))
node _io_core_clr_bsy_0_valid_T_5 = and(_io_core_clr_bsy_0_valid_T_3, _io_core_clr_bsy_0_valid_T_4)
reg io_core_clr_bsy_0_valid_REG : UInt<1>, clock
connect io_core_clr_bsy_0_valid_REG, io.core.exception
node _io_core_clr_bsy_0_valid_T_6 = eq(io_core_clr_bsy_0_valid_REG, UInt<1>(0h0))
node _io_core_clr_bsy_0_valid_T_7 = and(_io_core_clr_bsy_0_valid_T_5, _io_core_clr_bsy_0_valid_T_6)
reg io_core_clr_bsy_0_valid_REG_1 : UInt<1>, clock
connect io_core_clr_bsy_0_valid_REG_1, io.core.exception
reg io_core_clr_bsy_0_valid_REG_2 : UInt<1>, clock
connect io_core_clr_bsy_0_valid_REG_2, io_core_clr_bsy_0_valid_REG_1
node _io_core_clr_bsy_0_valid_T_8 = eq(io_core_clr_bsy_0_valid_REG_2, UInt<1>(0h0))
node _io_core_clr_bsy_0_valid_T_9 = and(_io_core_clr_bsy_0_valid_T_7, _io_core_clr_bsy_0_valid_T_8)
connect io.core.clr_bsy[0].valid, _io_core_clr_bsy_0_valid_T_9
connect io.core.clr_bsy[0].bits, clr_bsy_rob_idx[0]
regreset stdf_clr_bsy_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg stdf_clr_bsy_rob_idx : UInt<7>, clock
reg stdf_clr_bsy_brmask : UInt<16>, clock
connect stdf_clr_bsy_valid, UInt<1>(0h0)
connect stdf_clr_bsy_rob_idx, UInt<1>(0h0)
connect stdf_clr_bsy_brmask, UInt<1>(0h0)
when fired_stdf_incoming :
node _stdf_clr_bsy_valid_T = and(stq[mem_stdf_uop.stq_idx].valid, stq[mem_stdf_uop.stq_idx].bits.addr.valid)
node _stdf_clr_bsy_valid_T_1 = eq(stq[mem_stdf_uop.stq_idx].bits.addr_is_virtual, UInt<1>(0h0))
node _stdf_clr_bsy_valid_T_2 = and(_stdf_clr_bsy_valid_T, _stdf_clr_bsy_valid_T_1)
node _stdf_clr_bsy_valid_T_3 = eq(stq[mem_stdf_uop.stq_idx].bits.uop.is_amo, UInt<1>(0h0))
node _stdf_clr_bsy_valid_T_4 = and(_stdf_clr_bsy_valid_T_2, _stdf_clr_bsy_valid_T_3)
node _stdf_clr_bsy_valid_T_5 = and(io.core.brupdate.b1.mispredict_mask, mem_stdf_uop.br_mask)
node _stdf_clr_bsy_valid_T_6 = neq(_stdf_clr_bsy_valid_T_5, UInt<1>(0h0))
node _stdf_clr_bsy_valid_T_7 = eq(_stdf_clr_bsy_valid_T_6, UInt<1>(0h0))
node _stdf_clr_bsy_valid_T_8 = and(_stdf_clr_bsy_valid_T_4, _stdf_clr_bsy_valid_T_7)
connect stdf_clr_bsy_valid, _stdf_clr_bsy_valid_T_8
connect stdf_clr_bsy_rob_idx, mem_stdf_uop.rob_idx
node _stdf_clr_bsy_brmask_T = not(io.core.brupdate.b1.resolve_mask)
node _stdf_clr_bsy_brmask_T_1 = and(mem_stdf_uop.br_mask, _stdf_clr_bsy_brmask_T)
connect stdf_clr_bsy_brmask, _stdf_clr_bsy_brmask_T_1
node _io_core_clr_bsy_1_valid_T = and(io.core.brupdate.b1.mispredict_mask, stdf_clr_bsy_brmask)
node _io_core_clr_bsy_1_valid_T_1 = neq(_io_core_clr_bsy_1_valid_T, UInt<1>(0h0))
node _io_core_clr_bsy_1_valid_T_2 = eq(_io_core_clr_bsy_1_valid_T_1, UInt<1>(0h0))
node _io_core_clr_bsy_1_valid_T_3 = and(stdf_clr_bsy_valid, _io_core_clr_bsy_1_valid_T_2)
node _io_core_clr_bsy_1_valid_T_4 = eq(io.core.exception, UInt<1>(0h0))
node _io_core_clr_bsy_1_valid_T_5 = and(_io_core_clr_bsy_1_valid_T_3, _io_core_clr_bsy_1_valid_T_4)
reg io_core_clr_bsy_1_valid_REG : UInt<1>, clock
connect io_core_clr_bsy_1_valid_REG, io.core.exception
node _io_core_clr_bsy_1_valid_T_6 = eq(io_core_clr_bsy_1_valid_REG, UInt<1>(0h0))
node _io_core_clr_bsy_1_valid_T_7 = and(_io_core_clr_bsy_1_valid_T_5, _io_core_clr_bsy_1_valid_T_6)
reg io_core_clr_bsy_1_valid_REG_1 : UInt<1>, clock
connect io_core_clr_bsy_1_valid_REG_1, io.core.exception
reg io_core_clr_bsy_1_valid_REG_2 : UInt<1>, clock
connect io_core_clr_bsy_1_valid_REG_2, io_core_clr_bsy_1_valid_REG_1
node _io_core_clr_bsy_1_valid_T_8 = eq(io_core_clr_bsy_1_valid_REG_2, UInt<1>(0h0))
node _io_core_clr_bsy_1_valid_T_9 = and(_io_core_clr_bsy_1_valid_T_7, _io_core_clr_bsy_1_valid_T_8)
connect io.core.clr_bsy[1].valid, _io_core_clr_bsy_1_valid_T_9
connect io.core.clr_bsy[1].bits, stdf_clr_bsy_rob_idx
node _do_st_search_T = or(fired_stad_incoming[0], fired_sta_incoming[0])
node _do_st_search_T_1 = or(_do_st_search_T, fired_sta_retry[0])
node _do_st_search_T_2 = eq(mem_tlb_miss[0], UInt<1>(0h0))
node _do_st_search_T_3 = and(_do_st_search_T_1, _do_st_search_T_2)
wire do_st_search : UInt<1>[1]
connect do_st_search[0], _do_st_search_T_3
node _do_ld_search_T = or(fired_load_incoming[0], fired_load_retry[0])
node _do_ld_search_T_1 = eq(mem_tlb_miss[0], UInt<1>(0h0))
node _do_ld_search_T_2 = and(_do_ld_search_T, _do_ld_search_T_1)
node _do_ld_search_T_3 = or(_do_ld_search_T_2, fired_load_wakeup[0])
wire do_ld_search : UInt<1>[1]
connect do_ld_search[0], _do_ld_search_T_3
wire do_release_search : UInt<1>[1]
connect do_release_search[0], fired_release[0]
node _lcam_addr_T = or(fired_stad_incoming[0], fired_sta_incoming[0])
node _lcam_addr_T_1 = or(_lcam_addr_T, fired_sta_retry[0])
reg lcam_addr_REG : UInt, clock
connect lcam_addr_REG, exe_tlb_paddr[0]
reg lcam_addr_REG_1 : UInt, clock
connect lcam_addr_REG_1, io.dmem.release.bits.address
node _lcam_addr_T_2 = mux(fired_release[0], lcam_addr_REG_1, mem_paddr[0])
node _lcam_addr_T_3 = mux(_lcam_addr_T_1, lcam_addr_REG, _lcam_addr_T_2)
wire lcam_addr : UInt[1]
connect lcam_addr[0], _lcam_addr_T_3
wire lcam_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate lcam_uop_uop.debug_tsrc
invalidate lcam_uop_uop.debug_fsrc
invalidate lcam_uop_uop.bp_xcpt_if
invalidate lcam_uop_uop.bp_debug_if
invalidate lcam_uop_uop.xcpt_ma_if
invalidate lcam_uop_uop.xcpt_ae_if
invalidate lcam_uop_uop.xcpt_pf_if
invalidate lcam_uop_uop.fp_single
invalidate lcam_uop_uop.fp_val
invalidate lcam_uop_uop.frs3_en
invalidate lcam_uop_uop.lrs2_rtype
invalidate lcam_uop_uop.lrs1_rtype
invalidate lcam_uop_uop.dst_rtype
invalidate lcam_uop_uop.ldst_val
invalidate lcam_uop_uop.lrs3
invalidate lcam_uop_uop.lrs2
invalidate lcam_uop_uop.lrs1
invalidate lcam_uop_uop.ldst
invalidate lcam_uop_uop.ldst_is_rs1
invalidate lcam_uop_uop.flush_on_commit
invalidate lcam_uop_uop.is_unique
invalidate lcam_uop_uop.is_sys_pc2epc
invalidate lcam_uop_uop.uses_stq
invalidate lcam_uop_uop.uses_ldq
invalidate lcam_uop_uop.is_amo
invalidate lcam_uop_uop.is_fencei
invalidate lcam_uop_uop.is_fence
invalidate lcam_uop_uop.mem_signed
invalidate lcam_uop_uop.mem_size
invalidate lcam_uop_uop.mem_cmd
invalidate lcam_uop_uop.bypassable
invalidate lcam_uop_uop.exc_cause
invalidate lcam_uop_uop.exception
invalidate lcam_uop_uop.stale_pdst
invalidate lcam_uop_uop.ppred_busy
invalidate lcam_uop_uop.prs3_busy
invalidate lcam_uop_uop.prs2_busy
invalidate lcam_uop_uop.prs1_busy
invalidate lcam_uop_uop.ppred
invalidate lcam_uop_uop.prs3
invalidate lcam_uop_uop.prs2
invalidate lcam_uop_uop.prs1
invalidate lcam_uop_uop.pdst
invalidate lcam_uop_uop.rxq_idx
invalidate lcam_uop_uop.stq_idx
invalidate lcam_uop_uop.ldq_idx
invalidate lcam_uop_uop.rob_idx
invalidate lcam_uop_uop.csr_addr
invalidate lcam_uop_uop.imm_packed
invalidate lcam_uop_uop.taken
invalidate lcam_uop_uop.pc_lob
invalidate lcam_uop_uop.edge_inst
invalidate lcam_uop_uop.ftq_idx
invalidate lcam_uop_uop.br_tag
invalidate lcam_uop_uop.br_mask
invalidate lcam_uop_uop.is_sfb
invalidate lcam_uop_uop.is_jal
invalidate lcam_uop_uop.is_jalr
invalidate lcam_uop_uop.is_br
invalidate lcam_uop_uop.iw_p2_poisoned
invalidate lcam_uop_uop.iw_p1_poisoned
invalidate lcam_uop_uop.iw_state
invalidate lcam_uop_uop.ctrl.is_std
invalidate lcam_uop_uop.ctrl.is_sta
invalidate lcam_uop_uop.ctrl.is_load
invalidate lcam_uop_uop.ctrl.csr_cmd
invalidate lcam_uop_uop.ctrl.fcn_dw
invalidate lcam_uop_uop.ctrl.op_fcn
invalidate lcam_uop_uop.ctrl.imm_sel
invalidate lcam_uop_uop.ctrl.op2_sel
invalidate lcam_uop_uop.ctrl.op1_sel
invalidate lcam_uop_uop.ctrl.br_type
invalidate lcam_uop_uop.fu_code
invalidate lcam_uop_uop.iq_type
invalidate lcam_uop_uop.debug_pc
invalidate lcam_uop_uop.is_rvc
invalidate lcam_uop_uop.debug_inst
invalidate lcam_uop_uop.inst
invalidate lcam_uop_uop.uopc
connect lcam_uop_uop.uopc, UInt<7>(0h0)
connect lcam_uop_uop.bypassable, UInt<1>(0h0)
connect lcam_uop_uop.fp_val, UInt<1>(0h0)
connect lcam_uop_uop.uses_stq, UInt<1>(0h0)
connect lcam_uop_uop.uses_ldq, UInt<1>(0h0)
connect lcam_uop_uop.pdst, UInt<1>(0h0)
connect lcam_uop_uop.dst_rtype, UInt<2>(0h2)
wire lcam_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate lcam_uop_cs.is_std
invalidate lcam_uop_cs.is_sta
invalidate lcam_uop_cs.is_load
invalidate lcam_uop_cs.csr_cmd
invalidate lcam_uop_cs.fcn_dw
invalidate lcam_uop_cs.op_fcn
invalidate lcam_uop_cs.imm_sel
invalidate lcam_uop_cs.op2_sel
invalidate lcam_uop_cs.op1_sel
invalidate lcam_uop_cs.br_type
connect lcam_uop_cs.br_type, UInt<4>(0h0)
connect lcam_uop_cs.csr_cmd, UInt<3>(0h0)
connect lcam_uop_cs.is_load, UInt<1>(0h0)
connect lcam_uop_cs.is_sta, UInt<1>(0h0)
connect lcam_uop_cs.is_std, UInt<1>(0h0)
connect lcam_uop_uop.ctrl, lcam_uop_cs
node _lcam_uop_T = mux(do_ld_search[0], mem_ldq_e[0].bits.uop, lcam_uop_uop)
node _lcam_uop_T_1 = mux(do_st_search[0], mem_stq_e[0].bits.uop, _lcam_uop_T)
wire lcam_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
connect lcam_uop[0], _lcam_uop_T_1
wire lcam_mask_mask : UInt<8>
node _lcam_mask_mask_T = eq(lcam_uop[0].mem_size, UInt<1>(0h0))
node _lcam_mask_mask_T_1 = bits(lcam_addr[0], 2, 0)
node _lcam_mask_mask_T_2 = dshl(UInt<8>(0h1), _lcam_mask_mask_T_1)
node _lcam_mask_mask_T_3 = eq(lcam_uop[0].mem_size, UInt<1>(0h1))
node _lcam_mask_mask_T_4 = bits(lcam_addr[0], 2, 1)
node _lcam_mask_mask_T_5 = dshl(_lcam_mask_mask_T_4, UInt<1>(0h1))
node _lcam_mask_mask_T_6 = dshl(UInt<8>(0h3), _lcam_mask_mask_T_5)
node _lcam_mask_mask_T_7 = eq(lcam_uop[0].mem_size, UInt<2>(0h2))
node _lcam_mask_mask_T_8 = bits(lcam_addr[0], 2, 2)
node _lcam_mask_mask_T_9 = mux(_lcam_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf))
node _lcam_mask_mask_T_10 = eq(lcam_uop[0].mem_size, UInt<2>(0h3))
node _lcam_mask_mask_T_11 = mux(_lcam_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff))
node _lcam_mask_mask_T_12 = mux(_lcam_mask_mask_T_7, _lcam_mask_mask_T_9, _lcam_mask_mask_T_11)
node _lcam_mask_mask_T_13 = mux(_lcam_mask_mask_T_3, _lcam_mask_mask_T_6, _lcam_mask_mask_T_12)
node _lcam_mask_mask_T_14 = mux(_lcam_mask_mask_T, _lcam_mask_mask_T_2, _lcam_mask_mask_T_13)
connect lcam_mask_mask, _lcam_mask_mask_T_14
wire lcam_mask : UInt<8>[1]
connect lcam_mask[0], lcam_mask_mask
wire lcam_st_dep_mask : UInt<24>[1]
connect lcam_st_dep_mask[0], mem_ldq_e[0].bits.st_dep_mask
wire lcam_is_release : UInt<1>[1]
connect lcam_is_release[0], fired_release[0]
reg lcam_ldq_idx_REG : UInt, clock
connect lcam_ldq_idx_REG, ldq_wakeup_idx
reg lcam_ldq_idx_REG_1 : UInt, clock
connect lcam_ldq_idx_REG_1, ldq_retry_idx
node _lcam_ldq_idx_T = mux(fired_load_retry[0], lcam_ldq_idx_REG_1, UInt<1>(0h0))
node _lcam_ldq_idx_T_1 = mux(fired_load_wakeup[0], lcam_ldq_idx_REG, _lcam_ldq_idx_T)
node _lcam_ldq_idx_T_2 = mux(fired_load_incoming[0], mem_incoming_uop[0].ldq_idx, _lcam_ldq_idx_T_1)
wire lcam_ldq_idx : UInt[1]
connect lcam_ldq_idx[0], _lcam_ldq_idx_T_2
node _lcam_stq_idx_T = or(fired_stad_incoming[0], fired_sta_incoming[0])
reg lcam_stq_idx_REG : UInt, clock
connect lcam_stq_idx_REG, stq_retry_idx
node _lcam_stq_idx_T_1 = mux(fired_sta_retry[0], lcam_stq_idx_REG, UInt<1>(0h0))
node _lcam_stq_idx_T_2 = mux(_lcam_stq_idx_T, mem_incoming_uop[0].stq_idx, _lcam_stq_idx_T_1)
wire lcam_stq_idx : UInt[1]
connect lcam_stq_idx[0], _lcam_stq_idx_T_2
node _can_forward_T = or(fired_load_incoming[0], fired_load_retry[0])
node _can_forward_T_1 = eq(mem_tlb_uncacheable[0], UInt<1>(0h0))
node _can_forward_T_2 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _can_forward_T_3 = bits(_can_forward_T_2, 4, 0)
node _can_forward_T_4 = eq(ldq[_can_forward_T_3].bits.addr_is_uncacheable, UInt<1>(0h0))
node _can_forward_T_5 = mux(_can_forward_T, _can_forward_T_1, _can_forward_T_4)
wire _can_forward_WIRE : UInt<1>[1]
connect _can_forward_WIRE[0], _can_forward_T_5
wire can_forward : UInt<1>[1]
connect can_forward, _can_forward_WIRE
wire _ldst_addr_matches_WIRE : UInt<1>[24]
connect _ldst_addr_matches_WIRE[0], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[1], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[2], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[3], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[4], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[5], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[6], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[7], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[8], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[9], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[10], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[11], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[12], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[13], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[14], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[15], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[16], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[17], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[18], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[19], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[20], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[21], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[22], UInt<1>(0h0)
connect _ldst_addr_matches_WIRE[23], UInt<1>(0h0)
wire _ldst_addr_matches_WIRE_1 : UInt<1>[24][1]
connect _ldst_addr_matches_WIRE_1[0], _ldst_addr_matches_WIRE
wire ldst_addr_matches : UInt<1>[24][1]
connect ldst_addr_matches, _ldst_addr_matches_WIRE_1
wire _ldst_forward_matches_WIRE : UInt<1>[24]
connect _ldst_forward_matches_WIRE[0], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[1], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[2], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[3], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[4], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[5], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[6], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[7], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[8], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[9], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[10], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[11], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[12], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[13], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[14], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[15], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[16], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[17], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[18], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[19], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[20], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[21], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[22], UInt<1>(0h0)
connect _ldst_forward_matches_WIRE[23], UInt<1>(0h0)
wire _ldst_forward_matches_WIRE_1 : UInt<1>[24][1]
connect _ldst_forward_matches_WIRE_1[0], _ldst_forward_matches_WIRE
wire ldst_forward_matches : UInt<1>[24][1]
connect ldst_forward_matches, _ldst_forward_matches_WIRE_1
wire _failed_loads_WIRE : UInt<1>[24]
connect _failed_loads_WIRE[0], UInt<1>(0h0)
connect _failed_loads_WIRE[1], UInt<1>(0h0)
connect _failed_loads_WIRE[2], UInt<1>(0h0)
connect _failed_loads_WIRE[3], UInt<1>(0h0)
connect _failed_loads_WIRE[4], UInt<1>(0h0)
connect _failed_loads_WIRE[5], UInt<1>(0h0)
connect _failed_loads_WIRE[6], UInt<1>(0h0)
connect _failed_loads_WIRE[7], UInt<1>(0h0)
connect _failed_loads_WIRE[8], UInt<1>(0h0)
connect _failed_loads_WIRE[9], UInt<1>(0h0)
connect _failed_loads_WIRE[10], UInt<1>(0h0)
connect _failed_loads_WIRE[11], UInt<1>(0h0)
connect _failed_loads_WIRE[12], UInt<1>(0h0)
connect _failed_loads_WIRE[13], UInt<1>(0h0)
connect _failed_loads_WIRE[14], UInt<1>(0h0)
connect _failed_loads_WIRE[15], UInt<1>(0h0)
connect _failed_loads_WIRE[16], UInt<1>(0h0)
connect _failed_loads_WIRE[17], UInt<1>(0h0)
connect _failed_loads_WIRE[18], UInt<1>(0h0)
connect _failed_loads_WIRE[19], UInt<1>(0h0)
connect _failed_loads_WIRE[20], UInt<1>(0h0)
connect _failed_loads_WIRE[21], UInt<1>(0h0)
connect _failed_loads_WIRE[22], UInt<1>(0h0)
connect _failed_loads_WIRE[23], UInt<1>(0h0)
wire failed_loads : UInt<1>[24]
connect failed_loads, _failed_loads_WIRE
wire _nacking_loads_WIRE : UInt<1>[24]
connect _nacking_loads_WIRE[0], UInt<1>(0h0)
connect _nacking_loads_WIRE[1], UInt<1>(0h0)
connect _nacking_loads_WIRE[2], UInt<1>(0h0)
connect _nacking_loads_WIRE[3], UInt<1>(0h0)
connect _nacking_loads_WIRE[4], UInt<1>(0h0)
connect _nacking_loads_WIRE[5], UInt<1>(0h0)
connect _nacking_loads_WIRE[6], UInt<1>(0h0)
connect _nacking_loads_WIRE[7], UInt<1>(0h0)
connect _nacking_loads_WIRE[8], UInt<1>(0h0)
connect _nacking_loads_WIRE[9], UInt<1>(0h0)
connect _nacking_loads_WIRE[10], UInt<1>(0h0)
connect _nacking_loads_WIRE[11], UInt<1>(0h0)
connect _nacking_loads_WIRE[12], UInt<1>(0h0)
connect _nacking_loads_WIRE[13], UInt<1>(0h0)
connect _nacking_loads_WIRE[14], UInt<1>(0h0)
connect _nacking_loads_WIRE[15], UInt<1>(0h0)
connect _nacking_loads_WIRE[16], UInt<1>(0h0)
connect _nacking_loads_WIRE[17], UInt<1>(0h0)
connect _nacking_loads_WIRE[18], UInt<1>(0h0)
connect _nacking_loads_WIRE[19], UInt<1>(0h0)
connect _nacking_loads_WIRE[20], UInt<1>(0h0)
connect _nacking_loads_WIRE[21], UInt<1>(0h0)
connect _nacking_loads_WIRE[22], UInt<1>(0h0)
connect _nacking_loads_WIRE[23], UInt<1>(0h0)
wire nacking_loads : UInt<1>[24]
connect nacking_loads, _nacking_loads_WIRE
reg s1_executing_loads : UInt<1>[24], clock
connect s1_executing_loads, s0_executing_loads
wire s1_set_execute : UInt<1>[24]
connect s1_set_execute, s1_executing_loads
wire mem_forward_valid : UInt<1>[1]
wire mem_forward_stq_idx : UInt<5>[1]
reg wb_forward_valid : UInt<1>[1], clock
connect wb_forward_valid, mem_forward_valid
reg wb_forward_ldq_idx : UInt[1], clock
connect wb_forward_ldq_idx, lcam_ldq_idx
reg wb_forward_ld_addr : UInt[1], clock
connect wb_forward_ld_addr, lcam_addr
reg wb_forward_stq_idx : UInt<5>[1], clock
connect wb_forward_stq_idx, mem_forward_stq_idx
wire l_mask : UInt<8>
node _l_mask_mask_T = eq(ldq[0].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_1 = bits(ldq[0].bits.addr.bits, 2, 0)
node _l_mask_mask_T_2 = dshl(UInt<8>(0h1), _l_mask_mask_T_1)
node _l_mask_mask_T_3 = eq(ldq[0].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_4 = bits(ldq[0].bits.addr.bits, 2, 1)
node _l_mask_mask_T_5 = dshl(_l_mask_mask_T_4, UInt<1>(0h1))
node _l_mask_mask_T_6 = dshl(UInt<8>(0h3), _l_mask_mask_T_5)
node _l_mask_mask_T_7 = eq(ldq[0].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_8 = bits(ldq[0].bits.addr.bits, 2, 2)
node _l_mask_mask_T_9 = mux(_l_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_10 = eq(ldq[0].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_11 = mux(_l_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_12 = mux(_l_mask_mask_T_7, _l_mask_mask_T_9, _l_mask_mask_T_11)
node _l_mask_mask_T_13 = mux(_l_mask_mask_T_3, _l_mask_mask_T_6, _l_mask_mask_T_12)
node _l_mask_mask_T_14 = mux(_l_mask_mask_T, _l_mask_mask_T_2, _l_mask_mask_T_13)
connect l_mask, _l_mask_mask_T_14
node _l_forwarders_T = eq(wb_forward_ldq_idx[0], UInt<1>(0h0))
node _l_forwarders_T_1 = and(wb_forward_valid[0], _l_forwarders_T)
wire l_forwarders : UInt<1>[1]
connect l_forwarders[0], _l_forwarders_T_1
node l_forward_stq_idx = mux(l_forwarders[0], wb_forward_stq_idx[0], ldq[0].bits.forward_stq_idx)
node _block_addr_matches_T = shr(lcam_addr[0], 6)
node _block_addr_matches_T_1 = shr(ldq[0].bits.addr.bits, 6)
node _block_addr_matches_T_2 = eq(_block_addr_matches_T, _block_addr_matches_T_1)
wire block_addr_matches : UInt<1>[1]
connect block_addr_matches[0], _block_addr_matches_T_2
node _dword_addr_matches_T = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_1 = bits(ldq[0].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_2 = eq(_dword_addr_matches_T, _dword_addr_matches_T_1)
node _dword_addr_matches_T_3 = and(block_addr_matches[0], _dword_addr_matches_T_2)
wire dword_addr_matches : UInt<1>[1]
connect dword_addr_matches[0], _dword_addr_matches_T_3
node _mask_match_T = and(l_mask, lcam_mask[0])
node _mask_match_T_1 = eq(_mask_match_T, l_mask)
wire mask_match : UInt<1>[1]
connect mask_match[0], _mask_match_T_1
node _mask_overlap_T = and(l_mask, lcam_mask[0])
node _mask_overlap_T_1 = orr(_mask_overlap_T)
wire mask_overlap : UInt<1>[1]
connect mask_overlap[0], _mask_overlap_T_1
node _T_263 = and(do_release_search[0], ldq[0].valid)
node _T_264 = and(_T_263, ldq[0].bits.addr.valid)
node _T_265 = and(_T_264, block_addr_matches[0])
when _T_265 :
connect ldq[0].bits.observed, UInt<1>(0h1)
else :
node _T_266 = and(do_st_search[0], ldq[0].valid)
node _T_267 = and(_T_266, ldq[0].bits.addr.valid)
node _T_268 = or(ldq[0].bits.executed, ldq[0].bits.succeeded)
node _T_269 = or(_T_268, l_forwarders[0])
node _T_270 = and(_T_267, _T_269)
node _T_271 = eq(ldq[0].bits.addr_is_virtual, UInt<1>(0h0))
node _T_272 = and(_T_270, _T_271)
node _T_273 = dshr(ldq[0].bits.st_dep_mask, lcam_stq_idx[0])
node _T_274 = bits(_T_273, 0, 0)
node _T_275 = and(_T_272, _T_274)
node _T_276 = and(_T_275, dword_addr_matches[0])
node _T_277 = and(_T_276, mask_overlap[0])
when _T_277 :
node _forwarded_is_older_T = lt(l_forward_stq_idx, lcam_stq_idx[0])
node _forwarded_is_older_T_1 = lt(l_forward_stq_idx, ldq[0].bits.youngest_stq_idx)
node _forwarded_is_older_T_2 = xor(_forwarded_is_older_T, _forwarded_is_older_T_1)
node _forwarded_is_older_T_3 = lt(lcam_stq_idx[0], ldq[0].bits.youngest_stq_idx)
node forwarded_is_older = xor(_forwarded_is_older_T_2, _forwarded_is_older_T_3)
node _T_278 = eq(ldq[0].bits.forward_std_val, UInt<1>(0h0))
node _T_279 = neq(l_forward_stq_idx, lcam_stq_idx[0])
node _T_280 = and(_T_279, forwarded_is_older)
node _T_281 = or(_T_278, _T_280)
when _T_281 :
connect ldq[0].bits.order_fail, UInt<1>(0h1)
connect failed_loads[0], UInt<1>(0h1)
else :
node _T_282 = and(do_ld_search[0], ldq[0].valid)
node _T_283 = and(_T_282, ldq[0].bits.addr.valid)
node _T_284 = eq(ldq[0].bits.addr_is_virtual, UInt<1>(0h0))
node _T_285 = and(_T_283, _T_284)
node _T_286 = and(_T_285, dword_addr_matches[0])
node _T_287 = and(_T_286, mask_overlap[0])
when _T_287 :
node _searcher_is_older_T = lt(lcam_ldq_idx[0], UInt<1>(0h0))
node _searcher_is_older_T_1 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_2 = xor(_searcher_is_older_T, _searcher_is_older_T_1)
node _searcher_is_older_T_3 = lt(UInt<1>(0h0), ldq_head)
node searcher_is_older = xor(_searcher_is_older_T_2, _searcher_is_older_T_3)
when searcher_is_older :
node _T_288 = or(ldq[0].bits.executed, ldq[0].bits.succeeded)
node _T_289 = or(_T_288, l_forwarders[0])
node _T_290 = eq(s1_executing_loads[0], UInt<1>(0h0))
node _T_291 = and(_T_289, _T_290)
node _T_292 = and(_T_291, ldq[0].bits.observed)
when _T_292 :
connect ldq[0].bits.order_fail, UInt<1>(0h1)
connect failed_loads[0], UInt<1>(0h1)
else :
node _T_293 = neq(lcam_ldq_idx[0], UInt<1>(0h0))
when _T_293 :
reg older_nacked_REG : UInt<1>, clock
connect older_nacked_REG, nacking_loads[0]
node older_nacked = or(nacking_loads[0], older_nacked_REG)
node _T_294 = or(ldq[0].bits.executed, ldq[0].bits.succeeded)
node _T_295 = eq(_T_294, UInt<1>(0h0))
node _T_296 = or(_T_295, older_nacked)
when _T_296 :
node _T_297 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_298 = bits(_T_297, 4, 0)
connect s1_set_execute[_T_298], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG : UInt<1>, clock
connect io_dmem_s1_kill_0_REG, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG
connect can_forward[0], UInt<1>(0h0)
wire l_mask_1 : UInt<8>
node _l_mask_mask_T_15 = eq(ldq[1].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_16 = bits(ldq[1].bits.addr.bits, 2, 0)
node _l_mask_mask_T_17 = dshl(UInt<8>(0h1), _l_mask_mask_T_16)
node _l_mask_mask_T_18 = eq(ldq[1].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_19 = bits(ldq[1].bits.addr.bits, 2, 1)
node _l_mask_mask_T_20 = dshl(_l_mask_mask_T_19, UInt<1>(0h1))
node _l_mask_mask_T_21 = dshl(UInt<8>(0h3), _l_mask_mask_T_20)
node _l_mask_mask_T_22 = eq(ldq[1].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_23 = bits(ldq[1].bits.addr.bits, 2, 2)
node _l_mask_mask_T_24 = mux(_l_mask_mask_T_23, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_25 = eq(ldq[1].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_26 = mux(_l_mask_mask_T_25, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_27 = mux(_l_mask_mask_T_22, _l_mask_mask_T_24, _l_mask_mask_T_26)
node _l_mask_mask_T_28 = mux(_l_mask_mask_T_18, _l_mask_mask_T_21, _l_mask_mask_T_27)
node _l_mask_mask_T_29 = mux(_l_mask_mask_T_15, _l_mask_mask_T_17, _l_mask_mask_T_28)
connect l_mask_1, _l_mask_mask_T_29
node _l_forwarders_T_2 = eq(wb_forward_ldq_idx[0], UInt<1>(0h1))
node _l_forwarders_T_3 = and(wb_forward_valid[0], _l_forwarders_T_2)
wire l_forwarders_1 : UInt<1>[1]
connect l_forwarders_1[0], _l_forwarders_T_3
node l_forward_stq_idx_1 = mux(l_forwarders_1[0], wb_forward_stq_idx[0], ldq[1].bits.forward_stq_idx)
node _block_addr_matches_T_3 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_4 = shr(ldq[1].bits.addr.bits, 6)
node _block_addr_matches_T_5 = eq(_block_addr_matches_T_3, _block_addr_matches_T_4)
wire block_addr_matches_1 : UInt<1>[1]
connect block_addr_matches_1[0], _block_addr_matches_T_5
node _dword_addr_matches_T_4 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_5 = bits(ldq[1].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_6 = eq(_dword_addr_matches_T_4, _dword_addr_matches_T_5)
node _dword_addr_matches_T_7 = and(block_addr_matches_1[0], _dword_addr_matches_T_6)
wire dword_addr_matches_1 : UInt<1>[1]
connect dword_addr_matches_1[0], _dword_addr_matches_T_7
node _mask_match_T_2 = and(l_mask_1, lcam_mask[0])
node _mask_match_T_3 = eq(_mask_match_T_2, l_mask_1)
wire mask_match_1 : UInt<1>[1]
connect mask_match_1[0], _mask_match_T_3
node _mask_overlap_T_2 = and(l_mask_1, lcam_mask[0])
node _mask_overlap_T_3 = orr(_mask_overlap_T_2)
wire mask_overlap_1 : UInt<1>[1]
connect mask_overlap_1[0], _mask_overlap_T_3
node _T_299 = and(do_release_search[0], ldq[1].valid)
node _T_300 = and(_T_299, ldq[1].bits.addr.valid)
node _T_301 = and(_T_300, block_addr_matches_1[0])
when _T_301 :
connect ldq[1].bits.observed, UInt<1>(0h1)
else :
node _T_302 = and(do_st_search[0], ldq[1].valid)
node _T_303 = and(_T_302, ldq[1].bits.addr.valid)
node _T_304 = or(ldq[1].bits.executed, ldq[1].bits.succeeded)
node _T_305 = or(_T_304, l_forwarders_1[0])
node _T_306 = and(_T_303, _T_305)
node _T_307 = eq(ldq[1].bits.addr_is_virtual, UInt<1>(0h0))
node _T_308 = and(_T_306, _T_307)
node _T_309 = dshr(ldq[1].bits.st_dep_mask, lcam_stq_idx[0])
node _T_310 = bits(_T_309, 0, 0)
node _T_311 = and(_T_308, _T_310)
node _T_312 = and(_T_311, dword_addr_matches_1[0])
node _T_313 = and(_T_312, mask_overlap_1[0])
when _T_313 :
node _forwarded_is_older_T_4 = lt(l_forward_stq_idx_1, lcam_stq_idx[0])
node _forwarded_is_older_T_5 = lt(l_forward_stq_idx_1, ldq[1].bits.youngest_stq_idx)
node _forwarded_is_older_T_6 = xor(_forwarded_is_older_T_4, _forwarded_is_older_T_5)
node _forwarded_is_older_T_7 = lt(lcam_stq_idx[0], ldq[1].bits.youngest_stq_idx)
node forwarded_is_older_1 = xor(_forwarded_is_older_T_6, _forwarded_is_older_T_7)
node _T_314 = eq(ldq[1].bits.forward_std_val, UInt<1>(0h0))
node _T_315 = neq(l_forward_stq_idx_1, lcam_stq_idx[0])
node _T_316 = and(_T_315, forwarded_is_older_1)
node _T_317 = or(_T_314, _T_316)
when _T_317 :
connect ldq[1].bits.order_fail, UInt<1>(0h1)
connect failed_loads[1], UInt<1>(0h1)
else :
node _T_318 = and(do_ld_search[0], ldq[1].valid)
node _T_319 = and(_T_318, ldq[1].bits.addr.valid)
node _T_320 = eq(ldq[1].bits.addr_is_virtual, UInt<1>(0h0))
node _T_321 = and(_T_319, _T_320)
node _T_322 = and(_T_321, dword_addr_matches_1[0])
node _T_323 = and(_T_322, mask_overlap_1[0])
when _T_323 :
node _searcher_is_older_T_4 = lt(lcam_ldq_idx[0], UInt<1>(0h1))
node _searcher_is_older_T_5 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_6 = xor(_searcher_is_older_T_4, _searcher_is_older_T_5)
node _searcher_is_older_T_7 = lt(UInt<1>(0h1), ldq_head)
node searcher_is_older_1 = xor(_searcher_is_older_T_6, _searcher_is_older_T_7)
when searcher_is_older_1 :
node _T_324 = or(ldq[1].bits.executed, ldq[1].bits.succeeded)
node _T_325 = or(_T_324, l_forwarders_1[0])
node _T_326 = eq(s1_executing_loads[1], UInt<1>(0h0))
node _T_327 = and(_T_325, _T_326)
node _T_328 = and(_T_327, ldq[1].bits.observed)
when _T_328 :
connect ldq[1].bits.order_fail, UInt<1>(0h1)
connect failed_loads[1], UInt<1>(0h1)
else :
node _T_329 = neq(lcam_ldq_idx[0], UInt<1>(0h1))
when _T_329 :
reg older_nacked_REG_1 : UInt<1>, clock
connect older_nacked_REG_1, nacking_loads[1]
node older_nacked_1 = or(nacking_loads[1], older_nacked_REG_1)
node _T_330 = or(ldq[1].bits.executed, ldq[1].bits.succeeded)
node _T_331 = eq(_T_330, UInt<1>(0h0))
node _T_332 = or(_T_331, older_nacked_1)
when _T_332 :
node _T_333 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_334 = bits(_T_333, 4, 0)
connect s1_set_execute[_T_334], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_1 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_1, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_1
connect can_forward[0], UInt<1>(0h0)
wire l_mask_2 : UInt<8>
node _l_mask_mask_T_30 = eq(ldq[2].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_31 = bits(ldq[2].bits.addr.bits, 2, 0)
node _l_mask_mask_T_32 = dshl(UInt<8>(0h1), _l_mask_mask_T_31)
node _l_mask_mask_T_33 = eq(ldq[2].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_34 = bits(ldq[2].bits.addr.bits, 2, 1)
node _l_mask_mask_T_35 = dshl(_l_mask_mask_T_34, UInt<1>(0h1))
node _l_mask_mask_T_36 = dshl(UInt<8>(0h3), _l_mask_mask_T_35)
node _l_mask_mask_T_37 = eq(ldq[2].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_38 = bits(ldq[2].bits.addr.bits, 2, 2)
node _l_mask_mask_T_39 = mux(_l_mask_mask_T_38, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_40 = eq(ldq[2].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_41 = mux(_l_mask_mask_T_40, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_42 = mux(_l_mask_mask_T_37, _l_mask_mask_T_39, _l_mask_mask_T_41)
node _l_mask_mask_T_43 = mux(_l_mask_mask_T_33, _l_mask_mask_T_36, _l_mask_mask_T_42)
node _l_mask_mask_T_44 = mux(_l_mask_mask_T_30, _l_mask_mask_T_32, _l_mask_mask_T_43)
connect l_mask_2, _l_mask_mask_T_44
node _l_forwarders_T_4 = eq(wb_forward_ldq_idx[0], UInt<2>(0h2))
node _l_forwarders_T_5 = and(wb_forward_valid[0], _l_forwarders_T_4)
wire l_forwarders_2 : UInt<1>[1]
connect l_forwarders_2[0], _l_forwarders_T_5
node l_forward_stq_idx_2 = mux(l_forwarders_2[0], wb_forward_stq_idx[0], ldq[2].bits.forward_stq_idx)
node _block_addr_matches_T_6 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_7 = shr(ldq[2].bits.addr.bits, 6)
node _block_addr_matches_T_8 = eq(_block_addr_matches_T_6, _block_addr_matches_T_7)
wire block_addr_matches_2 : UInt<1>[1]
connect block_addr_matches_2[0], _block_addr_matches_T_8
node _dword_addr_matches_T_8 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_9 = bits(ldq[2].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_10 = eq(_dword_addr_matches_T_8, _dword_addr_matches_T_9)
node _dword_addr_matches_T_11 = and(block_addr_matches_2[0], _dword_addr_matches_T_10)
wire dword_addr_matches_2 : UInt<1>[1]
connect dword_addr_matches_2[0], _dword_addr_matches_T_11
node _mask_match_T_4 = and(l_mask_2, lcam_mask[0])
node _mask_match_T_5 = eq(_mask_match_T_4, l_mask_2)
wire mask_match_2 : UInt<1>[1]
connect mask_match_2[0], _mask_match_T_5
node _mask_overlap_T_4 = and(l_mask_2, lcam_mask[0])
node _mask_overlap_T_5 = orr(_mask_overlap_T_4)
wire mask_overlap_2 : UInt<1>[1]
connect mask_overlap_2[0], _mask_overlap_T_5
node _T_335 = and(do_release_search[0], ldq[2].valid)
node _T_336 = and(_T_335, ldq[2].bits.addr.valid)
node _T_337 = and(_T_336, block_addr_matches_2[0])
when _T_337 :
connect ldq[2].bits.observed, UInt<1>(0h1)
else :
node _T_338 = and(do_st_search[0], ldq[2].valid)
node _T_339 = and(_T_338, ldq[2].bits.addr.valid)
node _T_340 = or(ldq[2].bits.executed, ldq[2].bits.succeeded)
node _T_341 = or(_T_340, l_forwarders_2[0])
node _T_342 = and(_T_339, _T_341)
node _T_343 = eq(ldq[2].bits.addr_is_virtual, UInt<1>(0h0))
node _T_344 = and(_T_342, _T_343)
node _T_345 = dshr(ldq[2].bits.st_dep_mask, lcam_stq_idx[0])
node _T_346 = bits(_T_345, 0, 0)
node _T_347 = and(_T_344, _T_346)
node _T_348 = and(_T_347, dword_addr_matches_2[0])
node _T_349 = and(_T_348, mask_overlap_2[0])
when _T_349 :
node _forwarded_is_older_T_8 = lt(l_forward_stq_idx_2, lcam_stq_idx[0])
node _forwarded_is_older_T_9 = lt(l_forward_stq_idx_2, ldq[2].bits.youngest_stq_idx)
node _forwarded_is_older_T_10 = xor(_forwarded_is_older_T_8, _forwarded_is_older_T_9)
node _forwarded_is_older_T_11 = lt(lcam_stq_idx[0], ldq[2].bits.youngest_stq_idx)
node forwarded_is_older_2 = xor(_forwarded_is_older_T_10, _forwarded_is_older_T_11)
node _T_350 = eq(ldq[2].bits.forward_std_val, UInt<1>(0h0))
node _T_351 = neq(l_forward_stq_idx_2, lcam_stq_idx[0])
node _T_352 = and(_T_351, forwarded_is_older_2)
node _T_353 = or(_T_350, _T_352)
when _T_353 :
connect ldq[2].bits.order_fail, UInt<1>(0h1)
connect failed_loads[2], UInt<1>(0h1)
else :
node _T_354 = and(do_ld_search[0], ldq[2].valid)
node _T_355 = and(_T_354, ldq[2].bits.addr.valid)
node _T_356 = eq(ldq[2].bits.addr_is_virtual, UInt<1>(0h0))
node _T_357 = and(_T_355, _T_356)
node _T_358 = and(_T_357, dword_addr_matches_2[0])
node _T_359 = and(_T_358, mask_overlap_2[0])
when _T_359 :
node _searcher_is_older_T_8 = lt(lcam_ldq_idx[0], UInt<2>(0h2))
node _searcher_is_older_T_9 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_10 = xor(_searcher_is_older_T_8, _searcher_is_older_T_9)
node _searcher_is_older_T_11 = lt(UInt<2>(0h2), ldq_head)
node searcher_is_older_2 = xor(_searcher_is_older_T_10, _searcher_is_older_T_11)
when searcher_is_older_2 :
node _T_360 = or(ldq[2].bits.executed, ldq[2].bits.succeeded)
node _T_361 = or(_T_360, l_forwarders_2[0])
node _T_362 = eq(s1_executing_loads[2], UInt<1>(0h0))
node _T_363 = and(_T_361, _T_362)
node _T_364 = and(_T_363, ldq[2].bits.observed)
when _T_364 :
connect ldq[2].bits.order_fail, UInt<1>(0h1)
connect failed_loads[2], UInt<1>(0h1)
else :
node _T_365 = neq(lcam_ldq_idx[0], UInt<2>(0h2))
when _T_365 :
reg older_nacked_REG_2 : UInt<1>, clock
connect older_nacked_REG_2, nacking_loads[2]
node older_nacked_2 = or(nacking_loads[2], older_nacked_REG_2)
node _T_366 = or(ldq[2].bits.executed, ldq[2].bits.succeeded)
node _T_367 = eq(_T_366, UInt<1>(0h0))
node _T_368 = or(_T_367, older_nacked_2)
when _T_368 :
node _T_369 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_370 = bits(_T_369, 4, 0)
connect s1_set_execute[_T_370], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_2 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_2, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_2
connect can_forward[0], UInt<1>(0h0)
wire l_mask_3 : UInt<8>
node _l_mask_mask_T_45 = eq(ldq[3].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_46 = bits(ldq[3].bits.addr.bits, 2, 0)
node _l_mask_mask_T_47 = dshl(UInt<8>(0h1), _l_mask_mask_T_46)
node _l_mask_mask_T_48 = eq(ldq[3].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_49 = bits(ldq[3].bits.addr.bits, 2, 1)
node _l_mask_mask_T_50 = dshl(_l_mask_mask_T_49, UInt<1>(0h1))
node _l_mask_mask_T_51 = dshl(UInt<8>(0h3), _l_mask_mask_T_50)
node _l_mask_mask_T_52 = eq(ldq[3].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_53 = bits(ldq[3].bits.addr.bits, 2, 2)
node _l_mask_mask_T_54 = mux(_l_mask_mask_T_53, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_55 = eq(ldq[3].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_56 = mux(_l_mask_mask_T_55, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_57 = mux(_l_mask_mask_T_52, _l_mask_mask_T_54, _l_mask_mask_T_56)
node _l_mask_mask_T_58 = mux(_l_mask_mask_T_48, _l_mask_mask_T_51, _l_mask_mask_T_57)
node _l_mask_mask_T_59 = mux(_l_mask_mask_T_45, _l_mask_mask_T_47, _l_mask_mask_T_58)
connect l_mask_3, _l_mask_mask_T_59
node _l_forwarders_T_6 = eq(wb_forward_ldq_idx[0], UInt<2>(0h3))
node _l_forwarders_T_7 = and(wb_forward_valid[0], _l_forwarders_T_6)
wire l_forwarders_3 : UInt<1>[1]
connect l_forwarders_3[0], _l_forwarders_T_7
node l_forward_stq_idx_3 = mux(l_forwarders_3[0], wb_forward_stq_idx[0], ldq[3].bits.forward_stq_idx)
node _block_addr_matches_T_9 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_10 = shr(ldq[3].bits.addr.bits, 6)
node _block_addr_matches_T_11 = eq(_block_addr_matches_T_9, _block_addr_matches_T_10)
wire block_addr_matches_3 : UInt<1>[1]
connect block_addr_matches_3[0], _block_addr_matches_T_11
node _dword_addr_matches_T_12 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_13 = bits(ldq[3].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_14 = eq(_dword_addr_matches_T_12, _dword_addr_matches_T_13)
node _dword_addr_matches_T_15 = and(block_addr_matches_3[0], _dword_addr_matches_T_14)
wire dword_addr_matches_3 : UInt<1>[1]
connect dword_addr_matches_3[0], _dword_addr_matches_T_15
node _mask_match_T_6 = and(l_mask_3, lcam_mask[0])
node _mask_match_T_7 = eq(_mask_match_T_6, l_mask_3)
wire mask_match_3 : UInt<1>[1]
connect mask_match_3[0], _mask_match_T_7
node _mask_overlap_T_6 = and(l_mask_3, lcam_mask[0])
node _mask_overlap_T_7 = orr(_mask_overlap_T_6)
wire mask_overlap_3 : UInt<1>[1]
connect mask_overlap_3[0], _mask_overlap_T_7
node _T_371 = and(do_release_search[0], ldq[3].valid)
node _T_372 = and(_T_371, ldq[3].bits.addr.valid)
node _T_373 = and(_T_372, block_addr_matches_3[0])
when _T_373 :
connect ldq[3].bits.observed, UInt<1>(0h1)
else :
node _T_374 = and(do_st_search[0], ldq[3].valid)
node _T_375 = and(_T_374, ldq[3].bits.addr.valid)
node _T_376 = or(ldq[3].bits.executed, ldq[3].bits.succeeded)
node _T_377 = or(_T_376, l_forwarders_3[0])
node _T_378 = and(_T_375, _T_377)
node _T_379 = eq(ldq[3].bits.addr_is_virtual, UInt<1>(0h0))
node _T_380 = and(_T_378, _T_379)
node _T_381 = dshr(ldq[3].bits.st_dep_mask, lcam_stq_idx[0])
node _T_382 = bits(_T_381, 0, 0)
node _T_383 = and(_T_380, _T_382)
node _T_384 = and(_T_383, dword_addr_matches_3[0])
node _T_385 = and(_T_384, mask_overlap_3[0])
when _T_385 :
node _forwarded_is_older_T_12 = lt(l_forward_stq_idx_3, lcam_stq_idx[0])
node _forwarded_is_older_T_13 = lt(l_forward_stq_idx_3, ldq[3].bits.youngest_stq_idx)
node _forwarded_is_older_T_14 = xor(_forwarded_is_older_T_12, _forwarded_is_older_T_13)
node _forwarded_is_older_T_15 = lt(lcam_stq_idx[0], ldq[3].bits.youngest_stq_idx)
node forwarded_is_older_3 = xor(_forwarded_is_older_T_14, _forwarded_is_older_T_15)
node _T_386 = eq(ldq[3].bits.forward_std_val, UInt<1>(0h0))
node _T_387 = neq(l_forward_stq_idx_3, lcam_stq_idx[0])
node _T_388 = and(_T_387, forwarded_is_older_3)
node _T_389 = or(_T_386, _T_388)
when _T_389 :
connect ldq[3].bits.order_fail, UInt<1>(0h1)
connect failed_loads[3], UInt<1>(0h1)
else :
node _T_390 = and(do_ld_search[0], ldq[3].valid)
node _T_391 = and(_T_390, ldq[3].bits.addr.valid)
node _T_392 = eq(ldq[3].bits.addr_is_virtual, UInt<1>(0h0))
node _T_393 = and(_T_391, _T_392)
node _T_394 = and(_T_393, dword_addr_matches_3[0])
node _T_395 = and(_T_394, mask_overlap_3[0])
when _T_395 :
node _searcher_is_older_T_12 = lt(lcam_ldq_idx[0], UInt<2>(0h3))
node _searcher_is_older_T_13 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_14 = xor(_searcher_is_older_T_12, _searcher_is_older_T_13)
node _searcher_is_older_T_15 = lt(UInt<2>(0h3), ldq_head)
node searcher_is_older_3 = xor(_searcher_is_older_T_14, _searcher_is_older_T_15)
when searcher_is_older_3 :
node _T_396 = or(ldq[3].bits.executed, ldq[3].bits.succeeded)
node _T_397 = or(_T_396, l_forwarders_3[0])
node _T_398 = eq(s1_executing_loads[3], UInt<1>(0h0))
node _T_399 = and(_T_397, _T_398)
node _T_400 = and(_T_399, ldq[3].bits.observed)
when _T_400 :
connect ldq[3].bits.order_fail, UInt<1>(0h1)
connect failed_loads[3], UInt<1>(0h1)
else :
node _T_401 = neq(lcam_ldq_idx[0], UInt<2>(0h3))
when _T_401 :
reg older_nacked_REG_3 : UInt<1>, clock
connect older_nacked_REG_3, nacking_loads[3]
node older_nacked_3 = or(nacking_loads[3], older_nacked_REG_3)
node _T_402 = or(ldq[3].bits.executed, ldq[3].bits.succeeded)
node _T_403 = eq(_T_402, UInt<1>(0h0))
node _T_404 = or(_T_403, older_nacked_3)
when _T_404 :
node _T_405 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_406 = bits(_T_405, 4, 0)
connect s1_set_execute[_T_406], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_3 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_3, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_3
connect can_forward[0], UInt<1>(0h0)
wire l_mask_4 : UInt<8>
node _l_mask_mask_T_60 = eq(ldq[4].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_61 = bits(ldq[4].bits.addr.bits, 2, 0)
node _l_mask_mask_T_62 = dshl(UInt<8>(0h1), _l_mask_mask_T_61)
node _l_mask_mask_T_63 = eq(ldq[4].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_64 = bits(ldq[4].bits.addr.bits, 2, 1)
node _l_mask_mask_T_65 = dshl(_l_mask_mask_T_64, UInt<1>(0h1))
node _l_mask_mask_T_66 = dshl(UInt<8>(0h3), _l_mask_mask_T_65)
node _l_mask_mask_T_67 = eq(ldq[4].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_68 = bits(ldq[4].bits.addr.bits, 2, 2)
node _l_mask_mask_T_69 = mux(_l_mask_mask_T_68, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_70 = eq(ldq[4].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_71 = mux(_l_mask_mask_T_70, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_72 = mux(_l_mask_mask_T_67, _l_mask_mask_T_69, _l_mask_mask_T_71)
node _l_mask_mask_T_73 = mux(_l_mask_mask_T_63, _l_mask_mask_T_66, _l_mask_mask_T_72)
node _l_mask_mask_T_74 = mux(_l_mask_mask_T_60, _l_mask_mask_T_62, _l_mask_mask_T_73)
connect l_mask_4, _l_mask_mask_T_74
node _l_forwarders_T_8 = eq(wb_forward_ldq_idx[0], UInt<3>(0h4))
node _l_forwarders_T_9 = and(wb_forward_valid[0], _l_forwarders_T_8)
wire l_forwarders_4 : UInt<1>[1]
connect l_forwarders_4[0], _l_forwarders_T_9
node l_forward_stq_idx_4 = mux(l_forwarders_4[0], wb_forward_stq_idx[0], ldq[4].bits.forward_stq_idx)
node _block_addr_matches_T_12 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_13 = shr(ldq[4].bits.addr.bits, 6)
node _block_addr_matches_T_14 = eq(_block_addr_matches_T_12, _block_addr_matches_T_13)
wire block_addr_matches_4 : UInt<1>[1]
connect block_addr_matches_4[0], _block_addr_matches_T_14
node _dword_addr_matches_T_16 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_17 = bits(ldq[4].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_18 = eq(_dword_addr_matches_T_16, _dword_addr_matches_T_17)
node _dword_addr_matches_T_19 = and(block_addr_matches_4[0], _dword_addr_matches_T_18)
wire dword_addr_matches_4 : UInt<1>[1]
connect dword_addr_matches_4[0], _dword_addr_matches_T_19
node _mask_match_T_8 = and(l_mask_4, lcam_mask[0])
node _mask_match_T_9 = eq(_mask_match_T_8, l_mask_4)
wire mask_match_4 : UInt<1>[1]
connect mask_match_4[0], _mask_match_T_9
node _mask_overlap_T_8 = and(l_mask_4, lcam_mask[0])
node _mask_overlap_T_9 = orr(_mask_overlap_T_8)
wire mask_overlap_4 : UInt<1>[1]
connect mask_overlap_4[0], _mask_overlap_T_9
node _T_407 = and(do_release_search[0], ldq[4].valid)
node _T_408 = and(_T_407, ldq[4].bits.addr.valid)
node _T_409 = and(_T_408, block_addr_matches_4[0])
when _T_409 :
connect ldq[4].bits.observed, UInt<1>(0h1)
else :
node _T_410 = and(do_st_search[0], ldq[4].valid)
node _T_411 = and(_T_410, ldq[4].bits.addr.valid)
node _T_412 = or(ldq[4].bits.executed, ldq[4].bits.succeeded)
node _T_413 = or(_T_412, l_forwarders_4[0])
node _T_414 = and(_T_411, _T_413)
node _T_415 = eq(ldq[4].bits.addr_is_virtual, UInt<1>(0h0))
node _T_416 = and(_T_414, _T_415)
node _T_417 = dshr(ldq[4].bits.st_dep_mask, lcam_stq_idx[0])
node _T_418 = bits(_T_417, 0, 0)
node _T_419 = and(_T_416, _T_418)
node _T_420 = and(_T_419, dword_addr_matches_4[0])
node _T_421 = and(_T_420, mask_overlap_4[0])
when _T_421 :
node _forwarded_is_older_T_16 = lt(l_forward_stq_idx_4, lcam_stq_idx[0])
node _forwarded_is_older_T_17 = lt(l_forward_stq_idx_4, ldq[4].bits.youngest_stq_idx)
node _forwarded_is_older_T_18 = xor(_forwarded_is_older_T_16, _forwarded_is_older_T_17)
node _forwarded_is_older_T_19 = lt(lcam_stq_idx[0], ldq[4].bits.youngest_stq_idx)
node forwarded_is_older_4 = xor(_forwarded_is_older_T_18, _forwarded_is_older_T_19)
node _T_422 = eq(ldq[4].bits.forward_std_val, UInt<1>(0h0))
node _T_423 = neq(l_forward_stq_idx_4, lcam_stq_idx[0])
node _T_424 = and(_T_423, forwarded_is_older_4)
node _T_425 = or(_T_422, _T_424)
when _T_425 :
connect ldq[4].bits.order_fail, UInt<1>(0h1)
connect failed_loads[4], UInt<1>(0h1)
else :
node _T_426 = and(do_ld_search[0], ldq[4].valid)
node _T_427 = and(_T_426, ldq[4].bits.addr.valid)
node _T_428 = eq(ldq[4].bits.addr_is_virtual, UInt<1>(0h0))
node _T_429 = and(_T_427, _T_428)
node _T_430 = and(_T_429, dword_addr_matches_4[0])
node _T_431 = and(_T_430, mask_overlap_4[0])
when _T_431 :
node _searcher_is_older_T_16 = lt(lcam_ldq_idx[0], UInt<3>(0h4))
node _searcher_is_older_T_17 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_18 = xor(_searcher_is_older_T_16, _searcher_is_older_T_17)
node _searcher_is_older_T_19 = lt(UInt<3>(0h4), ldq_head)
node searcher_is_older_4 = xor(_searcher_is_older_T_18, _searcher_is_older_T_19)
when searcher_is_older_4 :
node _T_432 = or(ldq[4].bits.executed, ldq[4].bits.succeeded)
node _T_433 = or(_T_432, l_forwarders_4[0])
node _T_434 = eq(s1_executing_loads[4], UInt<1>(0h0))
node _T_435 = and(_T_433, _T_434)
node _T_436 = and(_T_435, ldq[4].bits.observed)
when _T_436 :
connect ldq[4].bits.order_fail, UInt<1>(0h1)
connect failed_loads[4], UInt<1>(0h1)
else :
node _T_437 = neq(lcam_ldq_idx[0], UInt<3>(0h4))
when _T_437 :
reg older_nacked_REG_4 : UInt<1>, clock
connect older_nacked_REG_4, nacking_loads[4]
node older_nacked_4 = or(nacking_loads[4], older_nacked_REG_4)
node _T_438 = or(ldq[4].bits.executed, ldq[4].bits.succeeded)
node _T_439 = eq(_T_438, UInt<1>(0h0))
node _T_440 = or(_T_439, older_nacked_4)
when _T_440 :
node _T_441 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_442 = bits(_T_441, 4, 0)
connect s1_set_execute[_T_442], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_4 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_4, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_4
connect can_forward[0], UInt<1>(0h0)
wire l_mask_5 : UInt<8>
node _l_mask_mask_T_75 = eq(ldq[5].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_76 = bits(ldq[5].bits.addr.bits, 2, 0)
node _l_mask_mask_T_77 = dshl(UInt<8>(0h1), _l_mask_mask_T_76)
node _l_mask_mask_T_78 = eq(ldq[5].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_79 = bits(ldq[5].bits.addr.bits, 2, 1)
node _l_mask_mask_T_80 = dshl(_l_mask_mask_T_79, UInt<1>(0h1))
node _l_mask_mask_T_81 = dshl(UInt<8>(0h3), _l_mask_mask_T_80)
node _l_mask_mask_T_82 = eq(ldq[5].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_83 = bits(ldq[5].bits.addr.bits, 2, 2)
node _l_mask_mask_T_84 = mux(_l_mask_mask_T_83, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_85 = eq(ldq[5].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_86 = mux(_l_mask_mask_T_85, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_87 = mux(_l_mask_mask_T_82, _l_mask_mask_T_84, _l_mask_mask_T_86)
node _l_mask_mask_T_88 = mux(_l_mask_mask_T_78, _l_mask_mask_T_81, _l_mask_mask_T_87)
node _l_mask_mask_T_89 = mux(_l_mask_mask_T_75, _l_mask_mask_T_77, _l_mask_mask_T_88)
connect l_mask_5, _l_mask_mask_T_89
node _l_forwarders_T_10 = eq(wb_forward_ldq_idx[0], UInt<3>(0h5))
node _l_forwarders_T_11 = and(wb_forward_valid[0], _l_forwarders_T_10)
wire l_forwarders_5 : UInt<1>[1]
connect l_forwarders_5[0], _l_forwarders_T_11
node l_forward_stq_idx_5 = mux(l_forwarders_5[0], wb_forward_stq_idx[0], ldq[5].bits.forward_stq_idx)
node _block_addr_matches_T_15 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_16 = shr(ldq[5].bits.addr.bits, 6)
node _block_addr_matches_T_17 = eq(_block_addr_matches_T_15, _block_addr_matches_T_16)
wire block_addr_matches_5 : UInt<1>[1]
connect block_addr_matches_5[0], _block_addr_matches_T_17
node _dword_addr_matches_T_20 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_21 = bits(ldq[5].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_22 = eq(_dword_addr_matches_T_20, _dword_addr_matches_T_21)
node _dword_addr_matches_T_23 = and(block_addr_matches_5[0], _dword_addr_matches_T_22)
wire dword_addr_matches_5 : UInt<1>[1]
connect dword_addr_matches_5[0], _dword_addr_matches_T_23
node _mask_match_T_10 = and(l_mask_5, lcam_mask[0])
node _mask_match_T_11 = eq(_mask_match_T_10, l_mask_5)
wire mask_match_5 : UInt<1>[1]
connect mask_match_5[0], _mask_match_T_11
node _mask_overlap_T_10 = and(l_mask_5, lcam_mask[0])
node _mask_overlap_T_11 = orr(_mask_overlap_T_10)
wire mask_overlap_5 : UInt<1>[1]
connect mask_overlap_5[0], _mask_overlap_T_11
node _T_443 = and(do_release_search[0], ldq[5].valid)
node _T_444 = and(_T_443, ldq[5].bits.addr.valid)
node _T_445 = and(_T_444, block_addr_matches_5[0])
when _T_445 :
connect ldq[5].bits.observed, UInt<1>(0h1)
else :
node _T_446 = and(do_st_search[0], ldq[5].valid)
node _T_447 = and(_T_446, ldq[5].bits.addr.valid)
node _T_448 = or(ldq[5].bits.executed, ldq[5].bits.succeeded)
node _T_449 = or(_T_448, l_forwarders_5[0])
node _T_450 = and(_T_447, _T_449)
node _T_451 = eq(ldq[5].bits.addr_is_virtual, UInt<1>(0h0))
node _T_452 = and(_T_450, _T_451)
node _T_453 = dshr(ldq[5].bits.st_dep_mask, lcam_stq_idx[0])
node _T_454 = bits(_T_453, 0, 0)
node _T_455 = and(_T_452, _T_454)
node _T_456 = and(_T_455, dword_addr_matches_5[0])
node _T_457 = and(_T_456, mask_overlap_5[0])
when _T_457 :
node _forwarded_is_older_T_20 = lt(l_forward_stq_idx_5, lcam_stq_idx[0])
node _forwarded_is_older_T_21 = lt(l_forward_stq_idx_5, ldq[5].bits.youngest_stq_idx)
node _forwarded_is_older_T_22 = xor(_forwarded_is_older_T_20, _forwarded_is_older_T_21)
node _forwarded_is_older_T_23 = lt(lcam_stq_idx[0], ldq[5].bits.youngest_stq_idx)
node forwarded_is_older_5 = xor(_forwarded_is_older_T_22, _forwarded_is_older_T_23)
node _T_458 = eq(ldq[5].bits.forward_std_val, UInt<1>(0h0))
node _T_459 = neq(l_forward_stq_idx_5, lcam_stq_idx[0])
node _T_460 = and(_T_459, forwarded_is_older_5)
node _T_461 = or(_T_458, _T_460)
when _T_461 :
connect ldq[5].bits.order_fail, UInt<1>(0h1)
connect failed_loads[5], UInt<1>(0h1)
else :
node _T_462 = and(do_ld_search[0], ldq[5].valid)
node _T_463 = and(_T_462, ldq[5].bits.addr.valid)
node _T_464 = eq(ldq[5].bits.addr_is_virtual, UInt<1>(0h0))
node _T_465 = and(_T_463, _T_464)
node _T_466 = and(_T_465, dword_addr_matches_5[0])
node _T_467 = and(_T_466, mask_overlap_5[0])
when _T_467 :
node _searcher_is_older_T_20 = lt(lcam_ldq_idx[0], UInt<3>(0h5))
node _searcher_is_older_T_21 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_22 = xor(_searcher_is_older_T_20, _searcher_is_older_T_21)
node _searcher_is_older_T_23 = lt(UInt<3>(0h5), ldq_head)
node searcher_is_older_5 = xor(_searcher_is_older_T_22, _searcher_is_older_T_23)
when searcher_is_older_5 :
node _T_468 = or(ldq[5].bits.executed, ldq[5].bits.succeeded)
node _T_469 = or(_T_468, l_forwarders_5[0])
node _T_470 = eq(s1_executing_loads[5], UInt<1>(0h0))
node _T_471 = and(_T_469, _T_470)
node _T_472 = and(_T_471, ldq[5].bits.observed)
when _T_472 :
connect ldq[5].bits.order_fail, UInt<1>(0h1)
connect failed_loads[5], UInt<1>(0h1)
else :
node _T_473 = neq(lcam_ldq_idx[0], UInt<3>(0h5))
when _T_473 :
reg older_nacked_REG_5 : UInt<1>, clock
connect older_nacked_REG_5, nacking_loads[5]
node older_nacked_5 = or(nacking_loads[5], older_nacked_REG_5)
node _T_474 = or(ldq[5].bits.executed, ldq[5].bits.succeeded)
node _T_475 = eq(_T_474, UInt<1>(0h0))
node _T_476 = or(_T_475, older_nacked_5)
when _T_476 :
node _T_477 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_478 = bits(_T_477, 4, 0)
connect s1_set_execute[_T_478], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_5 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_5, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_5
connect can_forward[0], UInt<1>(0h0)
wire l_mask_6 : UInt<8>
node _l_mask_mask_T_90 = eq(ldq[6].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_91 = bits(ldq[6].bits.addr.bits, 2, 0)
node _l_mask_mask_T_92 = dshl(UInt<8>(0h1), _l_mask_mask_T_91)
node _l_mask_mask_T_93 = eq(ldq[6].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_94 = bits(ldq[6].bits.addr.bits, 2, 1)
node _l_mask_mask_T_95 = dshl(_l_mask_mask_T_94, UInt<1>(0h1))
node _l_mask_mask_T_96 = dshl(UInt<8>(0h3), _l_mask_mask_T_95)
node _l_mask_mask_T_97 = eq(ldq[6].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_98 = bits(ldq[6].bits.addr.bits, 2, 2)
node _l_mask_mask_T_99 = mux(_l_mask_mask_T_98, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_100 = eq(ldq[6].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_101 = mux(_l_mask_mask_T_100, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_102 = mux(_l_mask_mask_T_97, _l_mask_mask_T_99, _l_mask_mask_T_101)
node _l_mask_mask_T_103 = mux(_l_mask_mask_T_93, _l_mask_mask_T_96, _l_mask_mask_T_102)
node _l_mask_mask_T_104 = mux(_l_mask_mask_T_90, _l_mask_mask_T_92, _l_mask_mask_T_103)
connect l_mask_6, _l_mask_mask_T_104
node _l_forwarders_T_12 = eq(wb_forward_ldq_idx[0], UInt<3>(0h6))
node _l_forwarders_T_13 = and(wb_forward_valid[0], _l_forwarders_T_12)
wire l_forwarders_6 : UInt<1>[1]
connect l_forwarders_6[0], _l_forwarders_T_13
node l_forward_stq_idx_6 = mux(l_forwarders_6[0], wb_forward_stq_idx[0], ldq[6].bits.forward_stq_idx)
node _block_addr_matches_T_18 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_19 = shr(ldq[6].bits.addr.bits, 6)
node _block_addr_matches_T_20 = eq(_block_addr_matches_T_18, _block_addr_matches_T_19)
wire block_addr_matches_6 : UInt<1>[1]
connect block_addr_matches_6[0], _block_addr_matches_T_20
node _dword_addr_matches_T_24 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_25 = bits(ldq[6].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_26 = eq(_dword_addr_matches_T_24, _dword_addr_matches_T_25)
node _dword_addr_matches_T_27 = and(block_addr_matches_6[0], _dword_addr_matches_T_26)
wire dword_addr_matches_6 : UInt<1>[1]
connect dword_addr_matches_6[0], _dword_addr_matches_T_27
node _mask_match_T_12 = and(l_mask_6, lcam_mask[0])
node _mask_match_T_13 = eq(_mask_match_T_12, l_mask_6)
wire mask_match_6 : UInt<1>[1]
connect mask_match_6[0], _mask_match_T_13
node _mask_overlap_T_12 = and(l_mask_6, lcam_mask[0])
node _mask_overlap_T_13 = orr(_mask_overlap_T_12)
wire mask_overlap_6 : UInt<1>[1]
connect mask_overlap_6[0], _mask_overlap_T_13
node _T_479 = and(do_release_search[0], ldq[6].valid)
node _T_480 = and(_T_479, ldq[6].bits.addr.valid)
node _T_481 = and(_T_480, block_addr_matches_6[0])
when _T_481 :
connect ldq[6].bits.observed, UInt<1>(0h1)
else :
node _T_482 = and(do_st_search[0], ldq[6].valid)
node _T_483 = and(_T_482, ldq[6].bits.addr.valid)
node _T_484 = or(ldq[6].bits.executed, ldq[6].bits.succeeded)
node _T_485 = or(_T_484, l_forwarders_6[0])
node _T_486 = and(_T_483, _T_485)
node _T_487 = eq(ldq[6].bits.addr_is_virtual, UInt<1>(0h0))
node _T_488 = and(_T_486, _T_487)
node _T_489 = dshr(ldq[6].bits.st_dep_mask, lcam_stq_idx[0])
node _T_490 = bits(_T_489, 0, 0)
node _T_491 = and(_T_488, _T_490)
node _T_492 = and(_T_491, dword_addr_matches_6[0])
node _T_493 = and(_T_492, mask_overlap_6[0])
when _T_493 :
node _forwarded_is_older_T_24 = lt(l_forward_stq_idx_6, lcam_stq_idx[0])
node _forwarded_is_older_T_25 = lt(l_forward_stq_idx_6, ldq[6].bits.youngest_stq_idx)
node _forwarded_is_older_T_26 = xor(_forwarded_is_older_T_24, _forwarded_is_older_T_25)
node _forwarded_is_older_T_27 = lt(lcam_stq_idx[0], ldq[6].bits.youngest_stq_idx)
node forwarded_is_older_6 = xor(_forwarded_is_older_T_26, _forwarded_is_older_T_27)
node _T_494 = eq(ldq[6].bits.forward_std_val, UInt<1>(0h0))
node _T_495 = neq(l_forward_stq_idx_6, lcam_stq_idx[0])
node _T_496 = and(_T_495, forwarded_is_older_6)
node _T_497 = or(_T_494, _T_496)
when _T_497 :
connect ldq[6].bits.order_fail, UInt<1>(0h1)
connect failed_loads[6], UInt<1>(0h1)
else :
node _T_498 = and(do_ld_search[0], ldq[6].valid)
node _T_499 = and(_T_498, ldq[6].bits.addr.valid)
node _T_500 = eq(ldq[6].bits.addr_is_virtual, UInt<1>(0h0))
node _T_501 = and(_T_499, _T_500)
node _T_502 = and(_T_501, dword_addr_matches_6[0])
node _T_503 = and(_T_502, mask_overlap_6[0])
when _T_503 :
node _searcher_is_older_T_24 = lt(lcam_ldq_idx[0], UInt<3>(0h6))
node _searcher_is_older_T_25 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_26 = xor(_searcher_is_older_T_24, _searcher_is_older_T_25)
node _searcher_is_older_T_27 = lt(UInt<3>(0h6), ldq_head)
node searcher_is_older_6 = xor(_searcher_is_older_T_26, _searcher_is_older_T_27)
when searcher_is_older_6 :
node _T_504 = or(ldq[6].bits.executed, ldq[6].bits.succeeded)
node _T_505 = or(_T_504, l_forwarders_6[0])
node _T_506 = eq(s1_executing_loads[6], UInt<1>(0h0))
node _T_507 = and(_T_505, _T_506)
node _T_508 = and(_T_507, ldq[6].bits.observed)
when _T_508 :
connect ldq[6].bits.order_fail, UInt<1>(0h1)
connect failed_loads[6], UInt<1>(0h1)
else :
node _T_509 = neq(lcam_ldq_idx[0], UInt<3>(0h6))
when _T_509 :
reg older_nacked_REG_6 : UInt<1>, clock
connect older_nacked_REG_6, nacking_loads[6]
node older_nacked_6 = or(nacking_loads[6], older_nacked_REG_6)
node _T_510 = or(ldq[6].bits.executed, ldq[6].bits.succeeded)
node _T_511 = eq(_T_510, UInt<1>(0h0))
node _T_512 = or(_T_511, older_nacked_6)
when _T_512 :
node _T_513 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_514 = bits(_T_513, 4, 0)
connect s1_set_execute[_T_514], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_6 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_6, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_6
connect can_forward[0], UInt<1>(0h0)
wire l_mask_7 : UInt<8>
node _l_mask_mask_T_105 = eq(ldq[7].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_106 = bits(ldq[7].bits.addr.bits, 2, 0)
node _l_mask_mask_T_107 = dshl(UInt<8>(0h1), _l_mask_mask_T_106)
node _l_mask_mask_T_108 = eq(ldq[7].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_109 = bits(ldq[7].bits.addr.bits, 2, 1)
node _l_mask_mask_T_110 = dshl(_l_mask_mask_T_109, UInt<1>(0h1))
node _l_mask_mask_T_111 = dshl(UInt<8>(0h3), _l_mask_mask_T_110)
node _l_mask_mask_T_112 = eq(ldq[7].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_113 = bits(ldq[7].bits.addr.bits, 2, 2)
node _l_mask_mask_T_114 = mux(_l_mask_mask_T_113, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_115 = eq(ldq[7].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_116 = mux(_l_mask_mask_T_115, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_117 = mux(_l_mask_mask_T_112, _l_mask_mask_T_114, _l_mask_mask_T_116)
node _l_mask_mask_T_118 = mux(_l_mask_mask_T_108, _l_mask_mask_T_111, _l_mask_mask_T_117)
node _l_mask_mask_T_119 = mux(_l_mask_mask_T_105, _l_mask_mask_T_107, _l_mask_mask_T_118)
connect l_mask_7, _l_mask_mask_T_119
node _l_forwarders_T_14 = eq(wb_forward_ldq_idx[0], UInt<3>(0h7))
node _l_forwarders_T_15 = and(wb_forward_valid[0], _l_forwarders_T_14)
wire l_forwarders_7 : UInt<1>[1]
connect l_forwarders_7[0], _l_forwarders_T_15
node l_forward_stq_idx_7 = mux(l_forwarders_7[0], wb_forward_stq_idx[0], ldq[7].bits.forward_stq_idx)
node _block_addr_matches_T_21 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_22 = shr(ldq[7].bits.addr.bits, 6)
node _block_addr_matches_T_23 = eq(_block_addr_matches_T_21, _block_addr_matches_T_22)
wire block_addr_matches_7 : UInt<1>[1]
connect block_addr_matches_7[0], _block_addr_matches_T_23
node _dword_addr_matches_T_28 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_29 = bits(ldq[7].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_30 = eq(_dword_addr_matches_T_28, _dword_addr_matches_T_29)
node _dword_addr_matches_T_31 = and(block_addr_matches_7[0], _dword_addr_matches_T_30)
wire dword_addr_matches_7 : UInt<1>[1]
connect dword_addr_matches_7[0], _dword_addr_matches_T_31
node _mask_match_T_14 = and(l_mask_7, lcam_mask[0])
node _mask_match_T_15 = eq(_mask_match_T_14, l_mask_7)
wire mask_match_7 : UInt<1>[1]
connect mask_match_7[0], _mask_match_T_15
node _mask_overlap_T_14 = and(l_mask_7, lcam_mask[0])
node _mask_overlap_T_15 = orr(_mask_overlap_T_14)
wire mask_overlap_7 : UInt<1>[1]
connect mask_overlap_7[0], _mask_overlap_T_15
node _T_515 = and(do_release_search[0], ldq[7].valid)
node _T_516 = and(_T_515, ldq[7].bits.addr.valid)
node _T_517 = and(_T_516, block_addr_matches_7[0])
when _T_517 :
connect ldq[7].bits.observed, UInt<1>(0h1)
else :
node _T_518 = and(do_st_search[0], ldq[7].valid)
node _T_519 = and(_T_518, ldq[7].bits.addr.valid)
node _T_520 = or(ldq[7].bits.executed, ldq[7].bits.succeeded)
node _T_521 = or(_T_520, l_forwarders_7[0])
node _T_522 = and(_T_519, _T_521)
node _T_523 = eq(ldq[7].bits.addr_is_virtual, UInt<1>(0h0))
node _T_524 = and(_T_522, _T_523)
node _T_525 = dshr(ldq[7].bits.st_dep_mask, lcam_stq_idx[0])
node _T_526 = bits(_T_525, 0, 0)
node _T_527 = and(_T_524, _T_526)
node _T_528 = and(_T_527, dword_addr_matches_7[0])
node _T_529 = and(_T_528, mask_overlap_7[0])
when _T_529 :
node _forwarded_is_older_T_28 = lt(l_forward_stq_idx_7, lcam_stq_idx[0])
node _forwarded_is_older_T_29 = lt(l_forward_stq_idx_7, ldq[7].bits.youngest_stq_idx)
node _forwarded_is_older_T_30 = xor(_forwarded_is_older_T_28, _forwarded_is_older_T_29)
node _forwarded_is_older_T_31 = lt(lcam_stq_idx[0], ldq[7].bits.youngest_stq_idx)
node forwarded_is_older_7 = xor(_forwarded_is_older_T_30, _forwarded_is_older_T_31)
node _T_530 = eq(ldq[7].bits.forward_std_val, UInt<1>(0h0))
node _T_531 = neq(l_forward_stq_idx_7, lcam_stq_idx[0])
node _T_532 = and(_T_531, forwarded_is_older_7)
node _T_533 = or(_T_530, _T_532)
when _T_533 :
connect ldq[7].bits.order_fail, UInt<1>(0h1)
connect failed_loads[7], UInt<1>(0h1)
else :
node _T_534 = and(do_ld_search[0], ldq[7].valid)
node _T_535 = and(_T_534, ldq[7].bits.addr.valid)
node _T_536 = eq(ldq[7].bits.addr_is_virtual, UInt<1>(0h0))
node _T_537 = and(_T_535, _T_536)
node _T_538 = and(_T_537, dword_addr_matches_7[0])
node _T_539 = and(_T_538, mask_overlap_7[0])
when _T_539 :
node _searcher_is_older_T_28 = lt(lcam_ldq_idx[0], UInt<3>(0h7))
node _searcher_is_older_T_29 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_30 = xor(_searcher_is_older_T_28, _searcher_is_older_T_29)
node _searcher_is_older_T_31 = lt(UInt<3>(0h7), ldq_head)
node searcher_is_older_7 = xor(_searcher_is_older_T_30, _searcher_is_older_T_31)
when searcher_is_older_7 :
node _T_540 = or(ldq[7].bits.executed, ldq[7].bits.succeeded)
node _T_541 = or(_T_540, l_forwarders_7[0])
node _T_542 = eq(s1_executing_loads[7], UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = and(_T_543, ldq[7].bits.observed)
when _T_544 :
connect ldq[7].bits.order_fail, UInt<1>(0h1)
connect failed_loads[7], UInt<1>(0h1)
else :
node _T_545 = neq(lcam_ldq_idx[0], UInt<3>(0h7))
when _T_545 :
reg older_nacked_REG_7 : UInt<1>, clock
connect older_nacked_REG_7, nacking_loads[7]
node older_nacked_7 = or(nacking_loads[7], older_nacked_REG_7)
node _T_546 = or(ldq[7].bits.executed, ldq[7].bits.succeeded)
node _T_547 = eq(_T_546, UInt<1>(0h0))
node _T_548 = or(_T_547, older_nacked_7)
when _T_548 :
node _T_549 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_550 = bits(_T_549, 4, 0)
connect s1_set_execute[_T_550], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_7 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_7, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_7
connect can_forward[0], UInt<1>(0h0)
wire l_mask_8 : UInt<8>
node _l_mask_mask_T_120 = eq(ldq[8].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_121 = bits(ldq[8].bits.addr.bits, 2, 0)
node _l_mask_mask_T_122 = dshl(UInt<8>(0h1), _l_mask_mask_T_121)
node _l_mask_mask_T_123 = eq(ldq[8].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_124 = bits(ldq[8].bits.addr.bits, 2, 1)
node _l_mask_mask_T_125 = dshl(_l_mask_mask_T_124, UInt<1>(0h1))
node _l_mask_mask_T_126 = dshl(UInt<8>(0h3), _l_mask_mask_T_125)
node _l_mask_mask_T_127 = eq(ldq[8].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_128 = bits(ldq[8].bits.addr.bits, 2, 2)
node _l_mask_mask_T_129 = mux(_l_mask_mask_T_128, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_130 = eq(ldq[8].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_131 = mux(_l_mask_mask_T_130, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_132 = mux(_l_mask_mask_T_127, _l_mask_mask_T_129, _l_mask_mask_T_131)
node _l_mask_mask_T_133 = mux(_l_mask_mask_T_123, _l_mask_mask_T_126, _l_mask_mask_T_132)
node _l_mask_mask_T_134 = mux(_l_mask_mask_T_120, _l_mask_mask_T_122, _l_mask_mask_T_133)
connect l_mask_8, _l_mask_mask_T_134
node _l_forwarders_T_16 = eq(wb_forward_ldq_idx[0], UInt<4>(0h8))
node _l_forwarders_T_17 = and(wb_forward_valid[0], _l_forwarders_T_16)
wire l_forwarders_8 : UInt<1>[1]
connect l_forwarders_8[0], _l_forwarders_T_17
node l_forward_stq_idx_8 = mux(l_forwarders_8[0], wb_forward_stq_idx[0], ldq[8].bits.forward_stq_idx)
node _block_addr_matches_T_24 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_25 = shr(ldq[8].bits.addr.bits, 6)
node _block_addr_matches_T_26 = eq(_block_addr_matches_T_24, _block_addr_matches_T_25)
wire block_addr_matches_8 : UInt<1>[1]
connect block_addr_matches_8[0], _block_addr_matches_T_26
node _dword_addr_matches_T_32 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_33 = bits(ldq[8].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_34 = eq(_dword_addr_matches_T_32, _dword_addr_matches_T_33)
node _dword_addr_matches_T_35 = and(block_addr_matches_8[0], _dword_addr_matches_T_34)
wire dword_addr_matches_8 : UInt<1>[1]
connect dword_addr_matches_8[0], _dword_addr_matches_T_35
node _mask_match_T_16 = and(l_mask_8, lcam_mask[0])
node _mask_match_T_17 = eq(_mask_match_T_16, l_mask_8)
wire mask_match_8 : UInt<1>[1]
connect mask_match_8[0], _mask_match_T_17
node _mask_overlap_T_16 = and(l_mask_8, lcam_mask[0])
node _mask_overlap_T_17 = orr(_mask_overlap_T_16)
wire mask_overlap_8 : UInt<1>[1]
connect mask_overlap_8[0], _mask_overlap_T_17
node _T_551 = and(do_release_search[0], ldq[8].valid)
node _T_552 = and(_T_551, ldq[8].bits.addr.valid)
node _T_553 = and(_T_552, block_addr_matches_8[0])
when _T_553 :
connect ldq[8].bits.observed, UInt<1>(0h1)
else :
node _T_554 = and(do_st_search[0], ldq[8].valid)
node _T_555 = and(_T_554, ldq[8].bits.addr.valid)
node _T_556 = or(ldq[8].bits.executed, ldq[8].bits.succeeded)
node _T_557 = or(_T_556, l_forwarders_8[0])
node _T_558 = and(_T_555, _T_557)
node _T_559 = eq(ldq[8].bits.addr_is_virtual, UInt<1>(0h0))
node _T_560 = and(_T_558, _T_559)
node _T_561 = dshr(ldq[8].bits.st_dep_mask, lcam_stq_idx[0])
node _T_562 = bits(_T_561, 0, 0)
node _T_563 = and(_T_560, _T_562)
node _T_564 = and(_T_563, dword_addr_matches_8[0])
node _T_565 = and(_T_564, mask_overlap_8[0])
when _T_565 :
node _forwarded_is_older_T_32 = lt(l_forward_stq_idx_8, lcam_stq_idx[0])
node _forwarded_is_older_T_33 = lt(l_forward_stq_idx_8, ldq[8].bits.youngest_stq_idx)
node _forwarded_is_older_T_34 = xor(_forwarded_is_older_T_32, _forwarded_is_older_T_33)
node _forwarded_is_older_T_35 = lt(lcam_stq_idx[0], ldq[8].bits.youngest_stq_idx)
node forwarded_is_older_8 = xor(_forwarded_is_older_T_34, _forwarded_is_older_T_35)
node _T_566 = eq(ldq[8].bits.forward_std_val, UInt<1>(0h0))
node _T_567 = neq(l_forward_stq_idx_8, lcam_stq_idx[0])
node _T_568 = and(_T_567, forwarded_is_older_8)
node _T_569 = or(_T_566, _T_568)
when _T_569 :
connect ldq[8].bits.order_fail, UInt<1>(0h1)
connect failed_loads[8], UInt<1>(0h1)
else :
node _T_570 = and(do_ld_search[0], ldq[8].valid)
node _T_571 = and(_T_570, ldq[8].bits.addr.valid)
node _T_572 = eq(ldq[8].bits.addr_is_virtual, UInt<1>(0h0))
node _T_573 = and(_T_571, _T_572)
node _T_574 = and(_T_573, dword_addr_matches_8[0])
node _T_575 = and(_T_574, mask_overlap_8[0])
when _T_575 :
node _searcher_is_older_T_32 = lt(lcam_ldq_idx[0], UInt<4>(0h8))
node _searcher_is_older_T_33 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_34 = xor(_searcher_is_older_T_32, _searcher_is_older_T_33)
node _searcher_is_older_T_35 = lt(UInt<4>(0h8), ldq_head)
node searcher_is_older_8 = xor(_searcher_is_older_T_34, _searcher_is_older_T_35)
when searcher_is_older_8 :
node _T_576 = or(ldq[8].bits.executed, ldq[8].bits.succeeded)
node _T_577 = or(_T_576, l_forwarders_8[0])
node _T_578 = eq(s1_executing_loads[8], UInt<1>(0h0))
node _T_579 = and(_T_577, _T_578)
node _T_580 = and(_T_579, ldq[8].bits.observed)
when _T_580 :
connect ldq[8].bits.order_fail, UInt<1>(0h1)
connect failed_loads[8], UInt<1>(0h1)
else :
node _T_581 = neq(lcam_ldq_idx[0], UInt<4>(0h8))
when _T_581 :
reg older_nacked_REG_8 : UInt<1>, clock
connect older_nacked_REG_8, nacking_loads[8]
node older_nacked_8 = or(nacking_loads[8], older_nacked_REG_8)
node _T_582 = or(ldq[8].bits.executed, ldq[8].bits.succeeded)
node _T_583 = eq(_T_582, UInt<1>(0h0))
node _T_584 = or(_T_583, older_nacked_8)
when _T_584 :
node _T_585 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_586 = bits(_T_585, 4, 0)
connect s1_set_execute[_T_586], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_8 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_8, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_8
connect can_forward[0], UInt<1>(0h0)
wire l_mask_9 : UInt<8>
node _l_mask_mask_T_135 = eq(ldq[9].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_136 = bits(ldq[9].bits.addr.bits, 2, 0)
node _l_mask_mask_T_137 = dshl(UInt<8>(0h1), _l_mask_mask_T_136)
node _l_mask_mask_T_138 = eq(ldq[9].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_139 = bits(ldq[9].bits.addr.bits, 2, 1)
node _l_mask_mask_T_140 = dshl(_l_mask_mask_T_139, UInt<1>(0h1))
node _l_mask_mask_T_141 = dshl(UInt<8>(0h3), _l_mask_mask_T_140)
node _l_mask_mask_T_142 = eq(ldq[9].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_143 = bits(ldq[9].bits.addr.bits, 2, 2)
node _l_mask_mask_T_144 = mux(_l_mask_mask_T_143, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_145 = eq(ldq[9].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_146 = mux(_l_mask_mask_T_145, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_147 = mux(_l_mask_mask_T_142, _l_mask_mask_T_144, _l_mask_mask_T_146)
node _l_mask_mask_T_148 = mux(_l_mask_mask_T_138, _l_mask_mask_T_141, _l_mask_mask_T_147)
node _l_mask_mask_T_149 = mux(_l_mask_mask_T_135, _l_mask_mask_T_137, _l_mask_mask_T_148)
connect l_mask_9, _l_mask_mask_T_149
node _l_forwarders_T_18 = eq(wb_forward_ldq_idx[0], UInt<4>(0h9))
node _l_forwarders_T_19 = and(wb_forward_valid[0], _l_forwarders_T_18)
wire l_forwarders_9 : UInt<1>[1]
connect l_forwarders_9[0], _l_forwarders_T_19
node l_forward_stq_idx_9 = mux(l_forwarders_9[0], wb_forward_stq_idx[0], ldq[9].bits.forward_stq_idx)
node _block_addr_matches_T_27 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_28 = shr(ldq[9].bits.addr.bits, 6)
node _block_addr_matches_T_29 = eq(_block_addr_matches_T_27, _block_addr_matches_T_28)
wire block_addr_matches_9 : UInt<1>[1]
connect block_addr_matches_9[0], _block_addr_matches_T_29
node _dword_addr_matches_T_36 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_37 = bits(ldq[9].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_38 = eq(_dword_addr_matches_T_36, _dword_addr_matches_T_37)
node _dword_addr_matches_T_39 = and(block_addr_matches_9[0], _dword_addr_matches_T_38)
wire dword_addr_matches_9 : UInt<1>[1]
connect dword_addr_matches_9[0], _dword_addr_matches_T_39
node _mask_match_T_18 = and(l_mask_9, lcam_mask[0])
node _mask_match_T_19 = eq(_mask_match_T_18, l_mask_9)
wire mask_match_9 : UInt<1>[1]
connect mask_match_9[0], _mask_match_T_19
node _mask_overlap_T_18 = and(l_mask_9, lcam_mask[0])
node _mask_overlap_T_19 = orr(_mask_overlap_T_18)
wire mask_overlap_9 : UInt<1>[1]
connect mask_overlap_9[0], _mask_overlap_T_19
node _T_587 = and(do_release_search[0], ldq[9].valid)
node _T_588 = and(_T_587, ldq[9].bits.addr.valid)
node _T_589 = and(_T_588, block_addr_matches_9[0])
when _T_589 :
connect ldq[9].bits.observed, UInt<1>(0h1)
else :
node _T_590 = and(do_st_search[0], ldq[9].valid)
node _T_591 = and(_T_590, ldq[9].bits.addr.valid)
node _T_592 = or(ldq[9].bits.executed, ldq[9].bits.succeeded)
node _T_593 = or(_T_592, l_forwarders_9[0])
node _T_594 = and(_T_591, _T_593)
node _T_595 = eq(ldq[9].bits.addr_is_virtual, UInt<1>(0h0))
node _T_596 = and(_T_594, _T_595)
node _T_597 = dshr(ldq[9].bits.st_dep_mask, lcam_stq_idx[0])
node _T_598 = bits(_T_597, 0, 0)
node _T_599 = and(_T_596, _T_598)
node _T_600 = and(_T_599, dword_addr_matches_9[0])
node _T_601 = and(_T_600, mask_overlap_9[0])
when _T_601 :
node _forwarded_is_older_T_36 = lt(l_forward_stq_idx_9, lcam_stq_idx[0])
node _forwarded_is_older_T_37 = lt(l_forward_stq_idx_9, ldq[9].bits.youngest_stq_idx)
node _forwarded_is_older_T_38 = xor(_forwarded_is_older_T_36, _forwarded_is_older_T_37)
node _forwarded_is_older_T_39 = lt(lcam_stq_idx[0], ldq[9].bits.youngest_stq_idx)
node forwarded_is_older_9 = xor(_forwarded_is_older_T_38, _forwarded_is_older_T_39)
node _T_602 = eq(ldq[9].bits.forward_std_val, UInt<1>(0h0))
node _T_603 = neq(l_forward_stq_idx_9, lcam_stq_idx[0])
node _T_604 = and(_T_603, forwarded_is_older_9)
node _T_605 = or(_T_602, _T_604)
when _T_605 :
connect ldq[9].bits.order_fail, UInt<1>(0h1)
connect failed_loads[9], UInt<1>(0h1)
else :
node _T_606 = and(do_ld_search[0], ldq[9].valid)
node _T_607 = and(_T_606, ldq[9].bits.addr.valid)
node _T_608 = eq(ldq[9].bits.addr_is_virtual, UInt<1>(0h0))
node _T_609 = and(_T_607, _T_608)
node _T_610 = and(_T_609, dword_addr_matches_9[0])
node _T_611 = and(_T_610, mask_overlap_9[0])
when _T_611 :
node _searcher_is_older_T_36 = lt(lcam_ldq_idx[0], UInt<4>(0h9))
node _searcher_is_older_T_37 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_38 = xor(_searcher_is_older_T_36, _searcher_is_older_T_37)
node _searcher_is_older_T_39 = lt(UInt<4>(0h9), ldq_head)
node searcher_is_older_9 = xor(_searcher_is_older_T_38, _searcher_is_older_T_39)
when searcher_is_older_9 :
node _T_612 = or(ldq[9].bits.executed, ldq[9].bits.succeeded)
node _T_613 = or(_T_612, l_forwarders_9[0])
node _T_614 = eq(s1_executing_loads[9], UInt<1>(0h0))
node _T_615 = and(_T_613, _T_614)
node _T_616 = and(_T_615, ldq[9].bits.observed)
when _T_616 :
connect ldq[9].bits.order_fail, UInt<1>(0h1)
connect failed_loads[9], UInt<1>(0h1)
else :
node _T_617 = neq(lcam_ldq_idx[0], UInt<4>(0h9))
when _T_617 :
reg older_nacked_REG_9 : UInt<1>, clock
connect older_nacked_REG_9, nacking_loads[9]
node older_nacked_9 = or(nacking_loads[9], older_nacked_REG_9)
node _T_618 = or(ldq[9].bits.executed, ldq[9].bits.succeeded)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = or(_T_619, older_nacked_9)
when _T_620 :
node _T_621 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_622 = bits(_T_621, 4, 0)
connect s1_set_execute[_T_622], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_9 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_9, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_9
connect can_forward[0], UInt<1>(0h0)
wire l_mask_10 : UInt<8>
node _l_mask_mask_T_150 = eq(ldq[10].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_151 = bits(ldq[10].bits.addr.bits, 2, 0)
node _l_mask_mask_T_152 = dshl(UInt<8>(0h1), _l_mask_mask_T_151)
node _l_mask_mask_T_153 = eq(ldq[10].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_154 = bits(ldq[10].bits.addr.bits, 2, 1)
node _l_mask_mask_T_155 = dshl(_l_mask_mask_T_154, UInt<1>(0h1))
node _l_mask_mask_T_156 = dshl(UInt<8>(0h3), _l_mask_mask_T_155)
node _l_mask_mask_T_157 = eq(ldq[10].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_158 = bits(ldq[10].bits.addr.bits, 2, 2)
node _l_mask_mask_T_159 = mux(_l_mask_mask_T_158, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_160 = eq(ldq[10].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_161 = mux(_l_mask_mask_T_160, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_162 = mux(_l_mask_mask_T_157, _l_mask_mask_T_159, _l_mask_mask_T_161)
node _l_mask_mask_T_163 = mux(_l_mask_mask_T_153, _l_mask_mask_T_156, _l_mask_mask_T_162)
node _l_mask_mask_T_164 = mux(_l_mask_mask_T_150, _l_mask_mask_T_152, _l_mask_mask_T_163)
connect l_mask_10, _l_mask_mask_T_164
node _l_forwarders_T_20 = eq(wb_forward_ldq_idx[0], UInt<4>(0ha))
node _l_forwarders_T_21 = and(wb_forward_valid[0], _l_forwarders_T_20)
wire l_forwarders_10 : UInt<1>[1]
connect l_forwarders_10[0], _l_forwarders_T_21
node l_forward_stq_idx_10 = mux(l_forwarders_10[0], wb_forward_stq_idx[0], ldq[10].bits.forward_stq_idx)
node _block_addr_matches_T_30 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_31 = shr(ldq[10].bits.addr.bits, 6)
node _block_addr_matches_T_32 = eq(_block_addr_matches_T_30, _block_addr_matches_T_31)
wire block_addr_matches_10 : UInt<1>[1]
connect block_addr_matches_10[0], _block_addr_matches_T_32
node _dword_addr_matches_T_40 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_41 = bits(ldq[10].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_42 = eq(_dword_addr_matches_T_40, _dword_addr_matches_T_41)
node _dword_addr_matches_T_43 = and(block_addr_matches_10[0], _dword_addr_matches_T_42)
wire dword_addr_matches_10 : UInt<1>[1]
connect dword_addr_matches_10[0], _dword_addr_matches_T_43
node _mask_match_T_20 = and(l_mask_10, lcam_mask[0])
node _mask_match_T_21 = eq(_mask_match_T_20, l_mask_10)
wire mask_match_10 : UInt<1>[1]
connect mask_match_10[0], _mask_match_T_21
node _mask_overlap_T_20 = and(l_mask_10, lcam_mask[0])
node _mask_overlap_T_21 = orr(_mask_overlap_T_20)
wire mask_overlap_10 : UInt<1>[1]
connect mask_overlap_10[0], _mask_overlap_T_21
node _T_623 = and(do_release_search[0], ldq[10].valid)
node _T_624 = and(_T_623, ldq[10].bits.addr.valid)
node _T_625 = and(_T_624, block_addr_matches_10[0])
when _T_625 :
connect ldq[10].bits.observed, UInt<1>(0h1)
else :
node _T_626 = and(do_st_search[0], ldq[10].valid)
node _T_627 = and(_T_626, ldq[10].bits.addr.valid)
node _T_628 = or(ldq[10].bits.executed, ldq[10].bits.succeeded)
node _T_629 = or(_T_628, l_forwarders_10[0])
node _T_630 = and(_T_627, _T_629)
node _T_631 = eq(ldq[10].bits.addr_is_virtual, UInt<1>(0h0))
node _T_632 = and(_T_630, _T_631)
node _T_633 = dshr(ldq[10].bits.st_dep_mask, lcam_stq_idx[0])
node _T_634 = bits(_T_633, 0, 0)
node _T_635 = and(_T_632, _T_634)
node _T_636 = and(_T_635, dword_addr_matches_10[0])
node _T_637 = and(_T_636, mask_overlap_10[0])
when _T_637 :
node _forwarded_is_older_T_40 = lt(l_forward_stq_idx_10, lcam_stq_idx[0])
node _forwarded_is_older_T_41 = lt(l_forward_stq_idx_10, ldq[10].bits.youngest_stq_idx)
node _forwarded_is_older_T_42 = xor(_forwarded_is_older_T_40, _forwarded_is_older_T_41)
node _forwarded_is_older_T_43 = lt(lcam_stq_idx[0], ldq[10].bits.youngest_stq_idx)
node forwarded_is_older_10 = xor(_forwarded_is_older_T_42, _forwarded_is_older_T_43)
node _T_638 = eq(ldq[10].bits.forward_std_val, UInt<1>(0h0))
node _T_639 = neq(l_forward_stq_idx_10, lcam_stq_idx[0])
node _T_640 = and(_T_639, forwarded_is_older_10)
node _T_641 = or(_T_638, _T_640)
when _T_641 :
connect ldq[10].bits.order_fail, UInt<1>(0h1)
connect failed_loads[10], UInt<1>(0h1)
else :
node _T_642 = and(do_ld_search[0], ldq[10].valid)
node _T_643 = and(_T_642, ldq[10].bits.addr.valid)
node _T_644 = eq(ldq[10].bits.addr_is_virtual, UInt<1>(0h0))
node _T_645 = and(_T_643, _T_644)
node _T_646 = and(_T_645, dword_addr_matches_10[0])
node _T_647 = and(_T_646, mask_overlap_10[0])
when _T_647 :
node _searcher_is_older_T_40 = lt(lcam_ldq_idx[0], UInt<4>(0ha))
node _searcher_is_older_T_41 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_42 = xor(_searcher_is_older_T_40, _searcher_is_older_T_41)
node _searcher_is_older_T_43 = lt(UInt<4>(0ha), ldq_head)
node searcher_is_older_10 = xor(_searcher_is_older_T_42, _searcher_is_older_T_43)
when searcher_is_older_10 :
node _T_648 = or(ldq[10].bits.executed, ldq[10].bits.succeeded)
node _T_649 = or(_T_648, l_forwarders_10[0])
node _T_650 = eq(s1_executing_loads[10], UInt<1>(0h0))
node _T_651 = and(_T_649, _T_650)
node _T_652 = and(_T_651, ldq[10].bits.observed)
when _T_652 :
connect ldq[10].bits.order_fail, UInt<1>(0h1)
connect failed_loads[10], UInt<1>(0h1)
else :
node _T_653 = neq(lcam_ldq_idx[0], UInt<4>(0ha))
when _T_653 :
reg older_nacked_REG_10 : UInt<1>, clock
connect older_nacked_REG_10, nacking_loads[10]
node older_nacked_10 = or(nacking_loads[10], older_nacked_REG_10)
node _T_654 = or(ldq[10].bits.executed, ldq[10].bits.succeeded)
node _T_655 = eq(_T_654, UInt<1>(0h0))
node _T_656 = or(_T_655, older_nacked_10)
when _T_656 :
node _T_657 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_658 = bits(_T_657, 4, 0)
connect s1_set_execute[_T_658], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_10 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_10, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_10
connect can_forward[0], UInt<1>(0h0)
wire l_mask_11 : UInt<8>
node _l_mask_mask_T_165 = eq(ldq[11].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_166 = bits(ldq[11].bits.addr.bits, 2, 0)
node _l_mask_mask_T_167 = dshl(UInt<8>(0h1), _l_mask_mask_T_166)
node _l_mask_mask_T_168 = eq(ldq[11].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_169 = bits(ldq[11].bits.addr.bits, 2, 1)
node _l_mask_mask_T_170 = dshl(_l_mask_mask_T_169, UInt<1>(0h1))
node _l_mask_mask_T_171 = dshl(UInt<8>(0h3), _l_mask_mask_T_170)
node _l_mask_mask_T_172 = eq(ldq[11].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_173 = bits(ldq[11].bits.addr.bits, 2, 2)
node _l_mask_mask_T_174 = mux(_l_mask_mask_T_173, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_175 = eq(ldq[11].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_176 = mux(_l_mask_mask_T_175, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_177 = mux(_l_mask_mask_T_172, _l_mask_mask_T_174, _l_mask_mask_T_176)
node _l_mask_mask_T_178 = mux(_l_mask_mask_T_168, _l_mask_mask_T_171, _l_mask_mask_T_177)
node _l_mask_mask_T_179 = mux(_l_mask_mask_T_165, _l_mask_mask_T_167, _l_mask_mask_T_178)
connect l_mask_11, _l_mask_mask_T_179
node _l_forwarders_T_22 = eq(wb_forward_ldq_idx[0], UInt<4>(0hb))
node _l_forwarders_T_23 = and(wb_forward_valid[0], _l_forwarders_T_22)
wire l_forwarders_11 : UInt<1>[1]
connect l_forwarders_11[0], _l_forwarders_T_23
node l_forward_stq_idx_11 = mux(l_forwarders_11[0], wb_forward_stq_idx[0], ldq[11].bits.forward_stq_idx)
node _block_addr_matches_T_33 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_34 = shr(ldq[11].bits.addr.bits, 6)
node _block_addr_matches_T_35 = eq(_block_addr_matches_T_33, _block_addr_matches_T_34)
wire block_addr_matches_11 : UInt<1>[1]
connect block_addr_matches_11[0], _block_addr_matches_T_35
node _dword_addr_matches_T_44 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_45 = bits(ldq[11].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_46 = eq(_dword_addr_matches_T_44, _dword_addr_matches_T_45)
node _dword_addr_matches_T_47 = and(block_addr_matches_11[0], _dword_addr_matches_T_46)
wire dword_addr_matches_11 : UInt<1>[1]
connect dword_addr_matches_11[0], _dword_addr_matches_T_47
node _mask_match_T_22 = and(l_mask_11, lcam_mask[0])
node _mask_match_T_23 = eq(_mask_match_T_22, l_mask_11)
wire mask_match_11 : UInt<1>[1]
connect mask_match_11[0], _mask_match_T_23
node _mask_overlap_T_22 = and(l_mask_11, lcam_mask[0])
node _mask_overlap_T_23 = orr(_mask_overlap_T_22)
wire mask_overlap_11 : UInt<1>[1]
connect mask_overlap_11[0], _mask_overlap_T_23
node _T_659 = and(do_release_search[0], ldq[11].valid)
node _T_660 = and(_T_659, ldq[11].bits.addr.valid)
node _T_661 = and(_T_660, block_addr_matches_11[0])
when _T_661 :
connect ldq[11].bits.observed, UInt<1>(0h1)
else :
node _T_662 = and(do_st_search[0], ldq[11].valid)
node _T_663 = and(_T_662, ldq[11].bits.addr.valid)
node _T_664 = or(ldq[11].bits.executed, ldq[11].bits.succeeded)
node _T_665 = or(_T_664, l_forwarders_11[0])
node _T_666 = and(_T_663, _T_665)
node _T_667 = eq(ldq[11].bits.addr_is_virtual, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
node _T_669 = dshr(ldq[11].bits.st_dep_mask, lcam_stq_idx[0])
node _T_670 = bits(_T_669, 0, 0)
node _T_671 = and(_T_668, _T_670)
node _T_672 = and(_T_671, dword_addr_matches_11[0])
node _T_673 = and(_T_672, mask_overlap_11[0])
when _T_673 :
node _forwarded_is_older_T_44 = lt(l_forward_stq_idx_11, lcam_stq_idx[0])
node _forwarded_is_older_T_45 = lt(l_forward_stq_idx_11, ldq[11].bits.youngest_stq_idx)
node _forwarded_is_older_T_46 = xor(_forwarded_is_older_T_44, _forwarded_is_older_T_45)
node _forwarded_is_older_T_47 = lt(lcam_stq_idx[0], ldq[11].bits.youngest_stq_idx)
node forwarded_is_older_11 = xor(_forwarded_is_older_T_46, _forwarded_is_older_T_47)
node _T_674 = eq(ldq[11].bits.forward_std_val, UInt<1>(0h0))
node _T_675 = neq(l_forward_stq_idx_11, lcam_stq_idx[0])
node _T_676 = and(_T_675, forwarded_is_older_11)
node _T_677 = or(_T_674, _T_676)
when _T_677 :
connect ldq[11].bits.order_fail, UInt<1>(0h1)
connect failed_loads[11], UInt<1>(0h1)
else :
node _T_678 = and(do_ld_search[0], ldq[11].valid)
node _T_679 = and(_T_678, ldq[11].bits.addr.valid)
node _T_680 = eq(ldq[11].bits.addr_is_virtual, UInt<1>(0h0))
node _T_681 = and(_T_679, _T_680)
node _T_682 = and(_T_681, dword_addr_matches_11[0])
node _T_683 = and(_T_682, mask_overlap_11[0])
when _T_683 :
node _searcher_is_older_T_44 = lt(lcam_ldq_idx[0], UInt<4>(0hb))
node _searcher_is_older_T_45 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_46 = xor(_searcher_is_older_T_44, _searcher_is_older_T_45)
node _searcher_is_older_T_47 = lt(UInt<4>(0hb), ldq_head)
node searcher_is_older_11 = xor(_searcher_is_older_T_46, _searcher_is_older_T_47)
when searcher_is_older_11 :
node _T_684 = or(ldq[11].bits.executed, ldq[11].bits.succeeded)
node _T_685 = or(_T_684, l_forwarders_11[0])
node _T_686 = eq(s1_executing_loads[11], UInt<1>(0h0))
node _T_687 = and(_T_685, _T_686)
node _T_688 = and(_T_687, ldq[11].bits.observed)
when _T_688 :
connect ldq[11].bits.order_fail, UInt<1>(0h1)
connect failed_loads[11], UInt<1>(0h1)
else :
node _T_689 = neq(lcam_ldq_idx[0], UInt<4>(0hb))
when _T_689 :
reg older_nacked_REG_11 : UInt<1>, clock
connect older_nacked_REG_11, nacking_loads[11]
node older_nacked_11 = or(nacking_loads[11], older_nacked_REG_11)
node _T_690 = or(ldq[11].bits.executed, ldq[11].bits.succeeded)
node _T_691 = eq(_T_690, UInt<1>(0h0))
node _T_692 = or(_T_691, older_nacked_11)
when _T_692 :
node _T_693 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_694 = bits(_T_693, 4, 0)
connect s1_set_execute[_T_694], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_11 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_11, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_11
connect can_forward[0], UInt<1>(0h0)
wire l_mask_12 : UInt<8>
node _l_mask_mask_T_180 = eq(ldq[12].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_181 = bits(ldq[12].bits.addr.bits, 2, 0)
node _l_mask_mask_T_182 = dshl(UInt<8>(0h1), _l_mask_mask_T_181)
node _l_mask_mask_T_183 = eq(ldq[12].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_184 = bits(ldq[12].bits.addr.bits, 2, 1)
node _l_mask_mask_T_185 = dshl(_l_mask_mask_T_184, UInt<1>(0h1))
node _l_mask_mask_T_186 = dshl(UInt<8>(0h3), _l_mask_mask_T_185)
node _l_mask_mask_T_187 = eq(ldq[12].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_188 = bits(ldq[12].bits.addr.bits, 2, 2)
node _l_mask_mask_T_189 = mux(_l_mask_mask_T_188, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_190 = eq(ldq[12].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_191 = mux(_l_mask_mask_T_190, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_192 = mux(_l_mask_mask_T_187, _l_mask_mask_T_189, _l_mask_mask_T_191)
node _l_mask_mask_T_193 = mux(_l_mask_mask_T_183, _l_mask_mask_T_186, _l_mask_mask_T_192)
node _l_mask_mask_T_194 = mux(_l_mask_mask_T_180, _l_mask_mask_T_182, _l_mask_mask_T_193)
connect l_mask_12, _l_mask_mask_T_194
node _l_forwarders_T_24 = eq(wb_forward_ldq_idx[0], UInt<4>(0hc))
node _l_forwarders_T_25 = and(wb_forward_valid[0], _l_forwarders_T_24)
wire l_forwarders_12 : UInt<1>[1]
connect l_forwarders_12[0], _l_forwarders_T_25
node l_forward_stq_idx_12 = mux(l_forwarders_12[0], wb_forward_stq_idx[0], ldq[12].bits.forward_stq_idx)
node _block_addr_matches_T_36 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_37 = shr(ldq[12].bits.addr.bits, 6)
node _block_addr_matches_T_38 = eq(_block_addr_matches_T_36, _block_addr_matches_T_37)
wire block_addr_matches_12 : UInt<1>[1]
connect block_addr_matches_12[0], _block_addr_matches_T_38
node _dword_addr_matches_T_48 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_49 = bits(ldq[12].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_50 = eq(_dword_addr_matches_T_48, _dword_addr_matches_T_49)
node _dword_addr_matches_T_51 = and(block_addr_matches_12[0], _dword_addr_matches_T_50)
wire dword_addr_matches_12 : UInt<1>[1]
connect dword_addr_matches_12[0], _dword_addr_matches_T_51
node _mask_match_T_24 = and(l_mask_12, lcam_mask[0])
node _mask_match_T_25 = eq(_mask_match_T_24, l_mask_12)
wire mask_match_12 : UInt<1>[1]
connect mask_match_12[0], _mask_match_T_25
node _mask_overlap_T_24 = and(l_mask_12, lcam_mask[0])
node _mask_overlap_T_25 = orr(_mask_overlap_T_24)
wire mask_overlap_12 : UInt<1>[1]
connect mask_overlap_12[0], _mask_overlap_T_25
node _T_695 = and(do_release_search[0], ldq[12].valid)
node _T_696 = and(_T_695, ldq[12].bits.addr.valid)
node _T_697 = and(_T_696, block_addr_matches_12[0])
when _T_697 :
connect ldq[12].bits.observed, UInt<1>(0h1)
else :
node _T_698 = and(do_st_search[0], ldq[12].valid)
node _T_699 = and(_T_698, ldq[12].bits.addr.valid)
node _T_700 = or(ldq[12].bits.executed, ldq[12].bits.succeeded)
node _T_701 = or(_T_700, l_forwarders_12[0])
node _T_702 = and(_T_699, _T_701)
node _T_703 = eq(ldq[12].bits.addr_is_virtual, UInt<1>(0h0))
node _T_704 = and(_T_702, _T_703)
node _T_705 = dshr(ldq[12].bits.st_dep_mask, lcam_stq_idx[0])
node _T_706 = bits(_T_705, 0, 0)
node _T_707 = and(_T_704, _T_706)
node _T_708 = and(_T_707, dword_addr_matches_12[0])
node _T_709 = and(_T_708, mask_overlap_12[0])
when _T_709 :
node _forwarded_is_older_T_48 = lt(l_forward_stq_idx_12, lcam_stq_idx[0])
node _forwarded_is_older_T_49 = lt(l_forward_stq_idx_12, ldq[12].bits.youngest_stq_idx)
node _forwarded_is_older_T_50 = xor(_forwarded_is_older_T_48, _forwarded_is_older_T_49)
node _forwarded_is_older_T_51 = lt(lcam_stq_idx[0], ldq[12].bits.youngest_stq_idx)
node forwarded_is_older_12 = xor(_forwarded_is_older_T_50, _forwarded_is_older_T_51)
node _T_710 = eq(ldq[12].bits.forward_std_val, UInt<1>(0h0))
node _T_711 = neq(l_forward_stq_idx_12, lcam_stq_idx[0])
node _T_712 = and(_T_711, forwarded_is_older_12)
node _T_713 = or(_T_710, _T_712)
when _T_713 :
connect ldq[12].bits.order_fail, UInt<1>(0h1)
connect failed_loads[12], UInt<1>(0h1)
else :
node _T_714 = and(do_ld_search[0], ldq[12].valid)
node _T_715 = and(_T_714, ldq[12].bits.addr.valid)
node _T_716 = eq(ldq[12].bits.addr_is_virtual, UInt<1>(0h0))
node _T_717 = and(_T_715, _T_716)
node _T_718 = and(_T_717, dword_addr_matches_12[0])
node _T_719 = and(_T_718, mask_overlap_12[0])
when _T_719 :
node _searcher_is_older_T_48 = lt(lcam_ldq_idx[0], UInt<4>(0hc))
node _searcher_is_older_T_49 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_50 = xor(_searcher_is_older_T_48, _searcher_is_older_T_49)
node _searcher_is_older_T_51 = lt(UInt<4>(0hc), ldq_head)
node searcher_is_older_12 = xor(_searcher_is_older_T_50, _searcher_is_older_T_51)
when searcher_is_older_12 :
node _T_720 = or(ldq[12].bits.executed, ldq[12].bits.succeeded)
node _T_721 = or(_T_720, l_forwarders_12[0])
node _T_722 = eq(s1_executing_loads[12], UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
node _T_724 = and(_T_723, ldq[12].bits.observed)
when _T_724 :
connect ldq[12].bits.order_fail, UInt<1>(0h1)
connect failed_loads[12], UInt<1>(0h1)
else :
node _T_725 = neq(lcam_ldq_idx[0], UInt<4>(0hc))
when _T_725 :
reg older_nacked_REG_12 : UInt<1>, clock
connect older_nacked_REG_12, nacking_loads[12]
node older_nacked_12 = or(nacking_loads[12], older_nacked_REG_12)
node _T_726 = or(ldq[12].bits.executed, ldq[12].bits.succeeded)
node _T_727 = eq(_T_726, UInt<1>(0h0))
node _T_728 = or(_T_727, older_nacked_12)
when _T_728 :
node _T_729 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_730 = bits(_T_729, 4, 0)
connect s1_set_execute[_T_730], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_12 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_12, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_12
connect can_forward[0], UInt<1>(0h0)
wire l_mask_13 : UInt<8>
node _l_mask_mask_T_195 = eq(ldq[13].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_196 = bits(ldq[13].bits.addr.bits, 2, 0)
node _l_mask_mask_T_197 = dshl(UInt<8>(0h1), _l_mask_mask_T_196)
node _l_mask_mask_T_198 = eq(ldq[13].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_199 = bits(ldq[13].bits.addr.bits, 2, 1)
node _l_mask_mask_T_200 = dshl(_l_mask_mask_T_199, UInt<1>(0h1))
node _l_mask_mask_T_201 = dshl(UInt<8>(0h3), _l_mask_mask_T_200)
node _l_mask_mask_T_202 = eq(ldq[13].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_203 = bits(ldq[13].bits.addr.bits, 2, 2)
node _l_mask_mask_T_204 = mux(_l_mask_mask_T_203, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_205 = eq(ldq[13].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_206 = mux(_l_mask_mask_T_205, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_207 = mux(_l_mask_mask_T_202, _l_mask_mask_T_204, _l_mask_mask_T_206)
node _l_mask_mask_T_208 = mux(_l_mask_mask_T_198, _l_mask_mask_T_201, _l_mask_mask_T_207)
node _l_mask_mask_T_209 = mux(_l_mask_mask_T_195, _l_mask_mask_T_197, _l_mask_mask_T_208)
connect l_mask_13, _l_mask_mask_T_209
node _l_forwarders_T_26 = eq(wb_forward_ldq_idx[0], UInt<4>(0hd))
node _l_forwarders_T_27 = and(wb_forward_valid[0], _l_forwarders_T_26)
wire l_forwarders_13 : UInt<1>[1]
connect l_forwarders_13[0], _l_forwarders_T_27
node l_forward_stq_idx_13 = mux(l_forwarders_13[0], wb_forward_stq_idx[0], ldq[13].bits.forward_stq_idx)
node _block_addr_matches_T_39 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_40 = shr(ldq[13].bits.addr.bits, 6)
node _block_addr_matches_T_41 = eq(_block_addr_matches_T_39, _block_addr_matches_T_40)
wire block_addr_matches_13 : UInt<1>[1]
connect block_addr_matches_13[0], _block_addr_matches_T_41
node _dword_addr_matches_T_52 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_53 = bits(ldq[13].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_54 = eq(_dword_addr_matches_T_52, _dword_addr_matches_T_53)
node _dword_addr_matches_T_55 = and(block_addr_matches_13[0], _dword_addr_matches_T_54)
wire dword_addr_matches_13 : UInt<1>[1]
connect dword_addr_matches_13[0], _dword_addr_matches_T_55
node _mask_match_T_26 = and(l_mask_13, lcam_mask[0])
node _mask_match_T_27 = eq(_mask_match_T_26, l_mask_13)
wire mask_match_13 : UInt<1>[1]
connect mask_match_13[0], _mask_match_T_27
node _mask_overlap_T_26 = and(l_mask_13, lcam_mask[0])
node _mask_overlap_T_27 = orr(_mask_overlap_T_26)
wire mask_overlap_13 : UInt<1>[1]
connect mask_overlap_13[0], _mask_overlap_T_27
node _T_731 = and(do_release_search[0], ldq[13].valid)
node _T_732 = and(_T_731, ldq[13].bits.addr.valid)
node _T_733 = and(_T_732, block_addr_matches_13[0])
when _T_733 :
connect ldq[13].bits.observed, UInt<1>(0h1)
else :
node _T_734 = and(do_st_search[0], ldq[13].valid)
node _T_735 = and(_T_734, ldq[13].bits.addr.valid)
node _T_736 = or(ldq[13].bits.executed, ldq[13].bits.succeeded)
node _T_737 = or(_T_736, l_forwarders_13[0])
node _T_738 = and(_T_735, _T_737)
node _T_739 = eq(ldq[13].bits.addr_is_virtual, UInt<1>(0h0))
node _T_740 = and(_T_738, _T_739)
node _T_741 = dshr(ldq[13].bits.st_dep_mask, lcam_stq_idx[0])
node _T_742 = bits(_T_741, 0, 0)
node _T_743 = and(_T_740, _T_742)
node _T_744 = and(_T_743, dword_addr_matches_13[0])
node _T_745 = and(_T_744, mask_overlap_13[0])
when _T_745 :
node _forwarded_is_older_T_52 = lt(l_forward_stq_idx_13, lcam_stq_idx[0])
node _forwarded_is_older_T_53 = lt(l_forward_stq_idx_13, ldq[13].bits.youngest_stq_idx)
node _forwarded_is_older_T_54 = xor(_forwarded_is_older_T_52, _forwarded_is_older_T_53)
node _forwarded_is_older_T_55 = lt(lcam_stq_idx[0], ldq[13].bits.youngest_stq_idx)
node forwarded_is_older_13 = xor(_forwarded_is_older_T_54, _forwarded_is_older_T_55)
node _T_746 = eq(ldq[13].bits.forward_std_val, UInt<1>(0h0))
node _T_747 = neq(l_forward_stq_idx_13, lcam_stq_idx[0])
node _T_748 = and(_T_747, forwarded_is_older_13)
node _T_749 = or(_T_746, _T_748)
when _T_749 :
connect ldq[13].bits.order_fail, UInt<1>(0h1)
connect failed_loads[13], UInt<1>(0h1)
else :
node _T_750 = and(do_ld_search[0], ldq[13].valid)
node _T_751 = and(_T_750, ldq[13].bits.addr.valid)
node _T_752 = eq(ldq[13].bits.addr_is_virtual, UInt<1>(0h0))
node _T_753 = and(_T_751, _T_752)
node _T_754 = and(_T_753, dword_addr_matches_13[0])
node _T_755 = and(_T_754, mask_overlap_13[0])
when _T_755 :
node _searcher_is_older_T_52 = lt(lcam_ldq_idx[0], UInt<4>(0hd))
node _searcher_is_older_T_53 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_54 = xor(_searcher_is_older_T_52, _searcher_is_older_T_53)
node _searcher_is_older_T_55 = lt(UInt<4>(0hd), ldq_head)
node searcher_is_older_13 = xor(_searcher_is_older_T_54, _searcher_is_older_T_55)
when searcher_is_older_13 :
node _T_756 = or(ldq[13].bits.executed, ldq[13].bits.succeeded)
node _T_757 = or(_T_756, l_forwarders_13[0])
node _T_758 = eq(s1_executing_loads[13], UInt<1>(0h0))
node _T_759 = and(_T_757, _T_758)
node _T_760 = and(_T_759, ldq[13].bits.observed)
when _T_760 :
connect ldq[13].bits.order_fail, UInt<1>(0h1)
connect failed_loads[13], UInt<1>(0h1)
else :
node _T_761 = neq(lcam_ldq_idx[0], UInt<4>(0hd))
when _T_761 :
reg older_nacked_REG_13 : UInt<1>, clock
connect older_nacked_REG_13, nacking_loads[13]
node older_nacked_13 = or(nacking_loads[13], older_nacked_REG_13)
node _T_762 = or(ldq[13].bits.executed, ldq[13].bits.succeeded)
node _T_763 = eq(_T_762, UInt<1>(0h0))
node _T_764 = or(_T_763, older_nacked_13)
when _T_764 :
node _T_765 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_766 = bits(_T_765, 4, 0)
connect s1_set_execute[_T_766], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_13 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_13, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_13
connect can_forward[0], UInt<1>(0h0)
wire l_mask_14 : UInt<8>
node _l_mask_mask_T_210 = eq(ldq[14].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_211 = bits(ldq[14].bits.addr.bits, 2, 0)
node _l_mask_mask_T_212 = dshl(UInt<8>(0h1), _l_mask_mask_T_211)
node _l_mask_mask_T_213 = eq(ldq[14].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_214 = bits(ldq[14].bits.addr.bits, 2, 1)
node _l_mask_mask_T_215 = dshl(_l_mask_mask_T_214, UInt<1>(0h1))
node _l_mask_mask_T_216 = dshl(UInt<8>(0h3), _l_mask_mask_T_215)
node _l_mask_mask_T_217 = eq(ldq[14].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_218 = bits(ldq[14].bits.addr.bits, 2, 2)
node _l_mask_mask_T_219 = mux(_l_mask_mask_T_218, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_220 = eq(ldq[14].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_221 = mux(_l_mask_mask_T_220, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_222 = mux(_l_mask_mask_T_217, _l_mask_mask_T_219, _l_mask_mask_T_221)
node _l_mask_mask_T_223 = mux(_l_mask_mask_T_213, _l_mask_mask_T_216, _l_mask_mask_T_222)
node _l_mask_mask_T_224 = mux(_l_mask_mask_T_210, _l_mask_mask_T_212, _l_mask_mask_T_223)
connect l_mask_14, _l_mask_mask_T_224
node _l_forwarders_T_28 = eq(wb_forward_ldq_idx[0], UInt<4>(0he))
node _l_forwarders_T_29 = and(wb_forward_valid[0], _l_forwarders_T_28)
wire l_forwarders_14 : UInt<1>[1]
connect l_forwarders_14[0], _l_forwarders_T_29
node l_forward_stq_idx_14 = mux(l_forwarders_14[0], wb_forward_stq_idx[0], ldq[14].bits.forward_stq_idx)
node _block_addr_matches_T_42 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_43 = shr(ldq[14].bits.addr.bits, 6)
node _block_addr_matches_T_44 = eq(_block_addr_matches_T_42, _block_addr_matches_T_43)
wire block_addr_matches_14 : UInt<1>[1]
connect block_addr_matches_14[0], _block_addr_matches_T_44
node _dword_addr_matches_T_56 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_57 = bits(ldq[14].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_58 = eq(_dword_addr_matches_T_56, _dword_addr_matches_T_57)
node _dword_addr_matches_T_59 = and(block_addr_matches_14[0], _dword_addr_matches_T_58)
wire dword_addr_matches_14 : UInt<1>[1]
connect dword_addr_matches_14[0], _dword_addr_matches_T_59
node _mask_match_T_28 = and(l_mask_14, lcam_mask[0])
node _mask_match_T_29 = eq(_mask_match_T_28, l_mask_14)
wire mask_match_14 : UInt<1>[1]
connect mask_match_14[0], _mask_match_T_29
node _mask_overlap_T_28 = and(l_mask_14, lcam_mask[0])
node _mask_overlap_T_29 = orr(_mask_overlap_T_28)
wire mask_overlap_14 : UInt<1>[1]
connect mask_overlap_14[0], _mask_overlap_T_29
node _T_767 = and(do_release_search[0], ldq[14].valid)
node _T_768 = and(_T_767, ldq[14].bits.addr.valid)
node _T_769 = and(_T_768, block_addr_matches_14[0])
when _T_769 :
connect ldq[14].bits.observed, UInt<1>(0h1)
else :
node _T_770 = and(do_st_search[0], ldq[14].valid)
node _T_771 = and(_T_770, ldq[14].bits.addr.valid)
node _T_772 = or(ldq[14].bits.executed, ldq[14].bits.succeeded)
node _T_773 = or(_T_772, l_forwarders_14[0])
node _T_774 = and(_T_771, _T_773)
node _T_775 = eq(ldq[14].bits.addr_is_virtual, UInt<1>(0h0))
node _T_776 = and(_T_774, _T_775)
node _T_777 = dshr(ldq[14].bits.st_dep_mask, lcam_stq_idx[0])
node _T_778 = bits(_T_777, 0, 0)
node _T_779 = and(_T_776, _T_778)
node _T_780 = and(_T_779, dword_addr_matches_14[0])
node _T_781 = and(_T_780, mask_overlap_14[0])
when _T_781 :
node _forwarded_is_older_T_56 = lt(l_forward_stq_idx_14, lcam_stq_idx[0])
node _forwarded_is_older_T_57 = lt(l_forward_stq_idx_14, ldq[14].bits.youngest_stq_idx)
node _forwarded_is_older_T_58 = xor(_forwarded_is_older_T_56, _forwarded_is_older_T_57)
node _forwarded_is_older_T_59 = lt(lcam_stq_idx[0], ldq[14].bits.youngest_stq_idx)
node forwarded_is_older_14 = xor(_forwarded_is_older_T_58, _forwarded_is_older_T_59)
node _T_782 = eq(ldq[14].bits.forward_std_val, UInt<1>(0h0))
node _T_783 = neq(l_forward_stq_idx_14, lcam_stq_idx[0])
node _T_784 = and(_T_783, forwarded_is_older_14)
node _T_785 = or(_T_782, _T_784)
when _T_785 :
connect ldq[14].bits.order_fail, UInt<1>(0h1)
connect failed_loads[14], UInt<1>(0h1)
else :
node _T_786 = and(do_ld_search[0], ldq[14].valid)
node _T_787 = and(_T_786, ldq[14].bits.addr.valid)
node _T_788 = eq(ldq[14].bits.addr_is_virtual, UInt<1>(0h0))
node _T_789 = and(_T_787, _T_788)
node _T_790 = and(_T_789, dword_addr_matches_14[0])
node _T_791 = and(_T_790, mask_overlap_14[0])
when _T_791 :
node _searcher_is_older_T_56 = lt(lcam_ldq_idx[0], UInt<4>(0he))
node _searcher_is_older_T_57 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_58 = xor(_searcher_is_older_T_56, _searcher_is_older_T_57)
node _searcher_is_older_T_59 = lt(UInt<4>(0he), ldq_head)
node searcher_is_older_14 = xor(_searcher_is_older_T_58, _searcher_is_older_T_59)
when searcher_is_older_14 :
node _T_792 = or(ldq[14].bits.executed, ldq[14].bits.succeeded)
node _T_793 = or(_T_792, l_forwarders_14[0])
node _T_794 = eq(s1_executing_loads[14], UInt<1>(0h0))
node _T_795 = and(_T_793, _T_794)
node _T_796 = and(_T_795, ldq[14].bits.observed)
when _T_796 :
connect ldq[14].bits.order_fail, UInt<1>(0h1)
connect failed_loads[14], UInt<1>(0h1)
else :
node _T_797 = neq(lcam_ldq_idx[0], UInt<4>(0he))
when _T_797 :
reg older_nacked_REG_14 : UInt<1>, clock
connect older_nacked_REG_14, nacking_loads[14]
node older_nacked_14 = or(nacking_loads[14], older_nacked_REG_14)
node _T_798 = or(ldq[14].bits.executed, ldq[14].bits.succeeded)
node _T_799 = eq(_T_798, UInt<1>(0h0))
node _T_800 = or(_T_799, older_nacked_14)
when _T_800 :
node _T_801 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_802 = bits(_T_801, 4, 0)
connect s1_set_execute[_T_802], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_14 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_14, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_14
connect can_forward[0], UInt<1>(0h0)
wire l_mask_15 : UInt<8>
node _l_mask_mask_T_225 = eq(ldq[15].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_226 = bits(ldq[15].bits.addr.bits, 2, 0)
node _l_mask_mask_T_227 = dshl(UInt<8>(0h1), _l_mask_mask_T_226)
node _l_mask_mask_T_228 = eq(ldq[15].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_229 = bits(ldq[15].bits.addr.bits, 2, 1)
node _l_mask_mask_T_230 = dshl(_l_mask_mask_T_229, UInt<1>(0h1))
node _l_mask_mask_T_231 = dshl(UInt<8>(0h3), _l_mask_mask_T_230)
node _l_mask_mask_T_232 = eq(ldq[15].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_233 = bits(ldq[15].bits.addr.bits, 2, 2)
node _l_mask_mask_T_234 = mux(_l_mask_mask_T_233, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_235 = eq(ldq[15].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_236 = mux(_l_mask_mask_T_235, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_237 = mux(_l_mask_mask_T_232, _l_mask_mask_T_234, _l_mask_mask_T_236)
node _l_mask_mask_T_238 = mux(_l_mask_mask_T_228, _l_mask_mask_T_231, _l_mask_mask_T_237)
node _l_mask_mask_T_239 = mux(_l_mask_mask_T_225, _l_mask_mask_T_227, _l_mask_mask_T_238)
connect l_mask_15, _l_mask_mask_T_239
node _l_forwarders_T_30 = eq(wb_forward_ldq_idx[0], UInt<4>(0hf))
node _l_forwarders_T_31 = and(wb_forward_valid[0], _l_forwarders_T_30)
wire l_forwarders_15 : UInt<1>[1]
connect l_forwarders_15[0], _l_forwarders_T_31
node l_forward_stq_idx_15 = mux(l_forwarders_15[0], wb_forward_stq_idx[0], ldq[15].bits.forward_stq_idx)
node _block_addr_matches_T_45 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_46 = shr(ldq[15].bits.addr.bits, 6)
node _block_addr_matches_T_47 = eq(_block_addr_matches_T_45, _block_addr_matches_T_46)
wire block_addr_matches_15 : UInt<1>[1]
connect block_addr_matches_15[0], _block_addr_matches_T_47
node _dword_addr_matches_T_60 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_61 = bits(ldq[15].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_62 = eq(_dword_addr_matches_T_60, _dword_addr_matches_T_61)
node _dword_addr_matches_T_63 = and(block_addr_matches_15[0], _dword_addr_matches_T_62)
wire dword_addr_matches_15 : UInt<1>[1]
connect dword_addr_matches_15[0], _dword_addr_matches_T_63
node _mask_match_T_30 = and(l_mask_15, lcam_mask[0])
node _mask_match_T_31 = eq(_mask_match_T_30, l_mask_15)
wire mask_match_15 : UInt<1>[1]
connect mask_match_15[0], _mask_match_T_31
node _mask_overlap_T_30 = and(l_mask_15, lcam_mask[0])
node _mask_overlap_T_31 = orr(_mask_overlap_T_30)
wire mask_overlap_15 : UInt<1>[1]
connect mask_overlap_15[0], _mask_overlap_T_31
node _T_803 = and(do_release_search[0], ldq[15].valid)
node _T_804 = and(_T_803, ldq[15].bits.addr.valid)
node _T_805 = and(_T_804, block_addr_matches_15[0])
when _T_805 :
connect ldq[15].bits.observed, UInt<1>(0h1)
else :
node _T_806 = and(do_st_search[0], ldq[15].valid)
node _T_807 = and(_T_806, ldq[15].bits.addr.valid)
node _T_808 = or(ldq[15].bits.executed, ldq[15].bits.succeeded)
node _T_809 = or(_T_808, l_forwarders_15[0])
node _T_810 = and(_T_807, _T_809)
node _T_811 = eq(ldq[15].bits.addr_is_virtual, UInt<1>(0h0))
node _T_812 = and(_T_810, _T_811)
node _T_813 = dshr(ldq[15].bits.st_dep_mask, lcam_stq_idx[0])
node _T_814 = bits(_T_813, 0, 0)
node _T_815 = and(_T_812, _T_814)
node _T_816 = and(_T_815, dword_addr_matches_15[0])
node _T_817 = and(_T_816, mask_overlap_15[0])
when _T_817 :
node _forwarded_is_older_T_60 = lt(l_forward_stq_idx_15, lcam_stq_idx[0])
node _forwarded_is_older_T_61 = lt(l_forward_stq_idx_15, ldq[15].bits.youngest_stq_idx)
node _forwarded_is_older_T_62 = xor(_forwarded_is_older_T_60, _forwarded_is_older_T_61)
node _forwarded_is_older_T_63 = lt(lcam_stq_idx[0], ldq[15].bits.youngest_stq_idx)
node forwarded_is_older_15 = xor(_forwarded_is_older_T_62, _forwarded_is_older_T_63)
node _T_818 = eq(ldq[15].bits.forward_std_val, UInt<1>(0h0))
node _T_819 = neq(l_forward_stq_idx_15, lcam_stq_idx[0])
node _T_820 = and(_T_819, forwarded_is_older_15)
node _T_821 = or(_T_818, _T_820)
when _T_821 :
connect ldq[15].bits.order_fail, UInt<1>(0h1)
connect failed_loads[15], UInt<1>(0h1)
else :
node _T_822 = and(do_ld_search[0], ldq[15].valid)
node _T_823 = and(_T_822, ldq[15].bits.addr.valid)
node _T_824 = eq(ldq[15].bits.addr_is_virtual, UInt<1>(0h0))
node _T_825 = and(_T_823, _T_824)
node _T_826 = and(_T_825, dword_addr_matches_15[0])
node _T_827 = and(_T_826, mask_overlap_15[0])
when _T_827 :
node _searcher_is_older_T_60 = lt(lcam_ldq_idx[0], UInt<4>(0hf))
node _searcher_is_older_T_61 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_62 = xor(_searcher_is_older_T_60, _searcher_is_older_T_61)
node _searcher_is_older_T_63 = lt(UInt<4>(0hf), ldq_head)
node searcher_is_older_15 = xor(_searcher_is_older_T_62, _searcher_is_older_T_63)
when searcher_is_older_15 :
node _T_828 = or(ldq[15].bits.executed, ldq[15].bits.succeeded)
node _T_829 = or(_T_828, l_forwarders_15[0])
node _T_830 = eq(s1_executing_loads[15], UInt<1>(0h0))
node _T_831 = and(_T_829, _T_830)
node _T_832 = and(_T_831, ldq[15].bits.observed)
when _T_832 :
connect ldq[15].bits.order_fail, UInt<1>(0h1)
connect failed_loads[15], UInt<1>(0h1)
else :
node _T_833 = neq(lcam_ldq_idx[0], UInt<4>(0hf))
when _T_833 :
reg older_nacked_REG_15 : UInt<1>, clock
connect older_nacked_REG_15, nacking_loads[15]
node older_nacked_15 = or(nacking_loads[15], older_nacked_REG_15)
node _T_834 = or(ldq[15].bits.executed, ldq[15].bits.succeeded)
node _T_835 = eq(_T_834, UInt<1>(0h0))
node _T_836 = or(_T_835, older_nacked_15)
when _T_836 :
node _T_837 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_838 = bits(_T_837, 4, 0)
connect s1_set_execute[_T_838], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_15 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_15, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_15
connect can_forward[0], UInt<1>(0h0)
wire l_mask_16 : UInt<8>
node _l_mask_mask_T_240 = eq(ldq[16].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_241 = bits(ldq[16].bits.addr.bits, 2, 0)
node _l_mask_mask_T_242 = dshl(UInt<8>(0h1), _l_mask_mask_T_241)
node _l_mask_mask_T_243 = eq(ldq[16].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_244 = bits(ldq[16].bits.addr.bits, 2, 1)
node _l_mask_mask_T_245 = dshl(_l_mask_mask_T_244, UInt<1>(0h1))
node _l_mask_mask_T_246 = dshl(UInt<8>(0h3), _l_mask_mask_T_245)
node _l_mask_mask_T_247 = eq(ldq[16].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_248 = bits(ldq[16].bits.addr.bits, 2, 2)
node _l_mask_mask_T_249 = mux(_l_mask_mask_T_248, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_250 = eq(ldq[16].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_251 = mux(_l_mask_mask_T_250, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_252 = mux(_l_mask_mask_T_247, _l_mask_mask_T_249, _l_mask_mask_T_251)
node _l_mask_mask_T_253 = mux(_l_mask_mask_T_243, _l_mask_mask_T_246, _l_mask_mask_T_252)
node _l_mask_mask_T_254 = mux(_l_mask_mask_T_240, _l_mask_mask_T_242, _l_mask_mask_T_253)
connect l_mask_16, _l_mask_mask_T_254
node _l_forwarders_T_32 = eq(wb_forward_ldq_idx[0], UInt<5>(0h10))
node _l_forwarders_T_33 = and(wb_forward_valid[0], _l_forwarders_T_32)
wire l_forwarders_16 : UInt<1>[1]
connect l_forwarders_16[0], _l_forwarders_T_33
node l_forward_stq_idx_16 = mux(l_forwarders_16[0], wb_forward_stq_idx[0], ldq[16].bits.forward_stq_idx)
node _block_addr_matches_T_48 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_49 = shr(ldq[16].bits.addr.bits, 6)
node _block_addr_matches_T_50 = eq(_block_addr_matches_T_48, _block_addr_matches_T_49)
wire block_addr_matches_16 : UInt<1>[1]
connect block_addr_matches_16[0], _block_addr_matches_T_50
node _dword_addr_matches_T_64 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_65 = bits(ldq[16].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_66 = eq(_dword_addr_matches_T_64, _dword_addr_matches_T_65)
node _dword_addr_matches_T_67 = and(block_addr_matches_16[0], _dword_addr_matches_T_66)
wire dword_addr_matches_16 : UInt<1>[1]
connect dword_addr_matches_16[0], _dword_addr_matches_T_67
node _mask_match_T_32 = and(l_mask_16, lcam_mask[0])
node _mask_match_T_33 = eq(_mask_match_T_32, l_mask_16)
wire mask_match_16 : UInt<1>[1]
connect mask_match_16[0], _mask_match_T_33
node _mask_overlap_T_32 = and(l_mask_16, lcam_mask[0])
node _mask_overlap_T_33 = orr(_mask_overlap_T_32)
wire mask_overlap_16 : UInt<1>[1]
connect mask_overlap_16[0], _mask_overlap_T_33
node _T_839 = and(do_release_search[0], ldq[16].valid)
node _T_840 = and(_T_839, ldq[16].bits.addr.valid)
node _T_841 = and(_T_840, block_addr_matches_16[0])
when _T_841 :
connect ldq[16].bits.observed, UInt<1>(0h1)
else :
node _T_842 = and(do_st_search[0], ldq[16].valid)
node _T_843 = and(_T_842, ldq[16].bits.addr.valid)
node _T_844 = or(ldq[16].bits.executed, ldq[16].bits.succeeded)
node _T_845 = or(_T_844, l_forwarders_16[0])
node _T_846 = and(_T_843, _T_845)
node _T_847 = eq(ldq[16].bits.addr_is_virtual, UInt<1>(0h0))
node _T_848 = and(_T_846, _T_847)
node _T_849 = dshr(ldq[16].bits.st_dep_mask, lcam_stq_idx[0])
node _T_850 = bits(_T_849, 0, 0)
node _T_851 = and(_T_848, _T_850)
node _T_852 = and(_T_851, dword_addr_matches_16[0])
node _T_853 = and(_T_852, mask_overlap_16[0])
when _T_853 :
node _forwarded_is_older_T_64 = lt(l_forward_stq_idx_16, lcam_stq_idx[0])
node _forwarded_is_older_T_65 = lt(l_forward_stq_idx_16, ldq[16].bits.youngest_stq_idx)
node _forwarded_is_older_T_66 = xor(_forwarded_is_older_T_64, _forwarded_is_older_T_65)
node _forwarded_is_older_T_67 = lt(lcam_stq_idx[0], ldq[16].bits.youngest_stq_idx)
node forwarded_is_older_16 = xor(_forwarded_is_older_T_66, _forwarded_is_older_T_67)
node _T_854 = eq(ldq[16].bits.forward_std_val, UInt<1>(0h0))
node _T_855 = neq(l_forward_stq_idx_16, lcam_stq_idx[0])
node _T_856 = and(_T_855, forwarded_is_older_16)
node _T_857 = or(_T_854, _T_856)
when _T_857 :
connect ldq[16].bits.order_fail, UInt<1>(0h1)
connect failed_loads[16], UInt<1>(0h1)
else :
node _T_858 = and(do_ld_search[0], ldq[16].valid)
node _T_859 = and(_T_858, ldq[16].bits.addr.valid)
node _T_860 = eq(ldq[16].bits.addr_is_virtual, UInt<1>(0h0))
node _T_861 = and(_T_859, _T_860)
node _T_862 = and(_T_861, dword_addr_matches_16[0])
node _T_863 = and(_T_862, mask_overlap_16[0])
when _T_863 :
node _searcher_is_older_T_64 = lt(lcam_ldq_idx[0], UInt<5>(0h10))
node _searcher_is_older_T_65 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_66 = xor(_searcher_is_older_T_64, _searcher_is_older_T_65)
node _searcher_is_older_T_67 = lt(UInt<5>(0h10), ldq_head)
node searcher_is_older_16 = xor(_searcher_is_older_T_66, _searcher_is_older_T_67)
when searcher_is_older_16 :
node _T_864 = or(ldq[16].bits.executed, ldq[16].bits.succeeded)
node _T_865 = or(_T_864, l_forwarders_16[0])
node _T_866 = eq(s1_executing_loads[16], UInt<1>(0h0))
node _T_867 = and(_T_865, _T_866)
node _T_868 = and(_T_867, ldq[16].bits.observed)
when _T_868 :
connect ldq[16].bits.order_fail, UInt<1>(0h1)
connect failed_loads[16], UInt<1>(0h1)
else :
node _T_869 = neq(lcam_ldq_idx[0], UInt<5>(0h10))
when _T_869 :
reg older_nacked_REG_16 : UInt<1>, clock
connect older_nacked_REG_16, nacking_loads[16]
node older_nacked_16 = or(nacking_loads[16], older_nacked_REG_16)
node _T_870 = or(ldq[16].bits.executed, ldq[16].bits.succeeded)
node _T_871 = eq(_T_870, UInt<1>(0h0))
node _T_872 = or(_T_871, older_nacked_16)
when _T_872 :
node _T_873 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_874 = bits(_T_873, 4, 0)
connect s1_set_execute[_T_874], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_16 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_16, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_16
connect can_forward[0], UInt<1>(0h0)
wire l_mask_17 : UInt<8>
node _l_mask_mask_T_255 = eq(ldq[17].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_256 = bits(ldq[17].bits.addr.bits, 2, 0)
node _l_mask_mask_T_257 = dshl(UInt<8>(0h1), _l_mask_mask_T_256)
node _l_mask_mask_T_258 = eq(ldq[17].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_259 = bits(ldq[17].bits.addr.bits, 2, 1)
node _l_mask_mask_T_260 = dshl(_l_mask_mask_T_259, UInt<1>(0h1))
node _l_mask_mask_T_261 = dshl(UInt<8>(0h3), _l_mask_mask_T_260)
node _l_mask_mask_T_262 = eq(ldq[17].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_263 = bits(ldq[17].bits.addr.bits, 2, 2)
node _l_mask_mask_T_264 = mux(_l_mask_mask_T_263, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_265 = eq(ldq[17].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_266 = mux(_l_mask_mask_T_265, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_267 = mux(_l_mask_mask_T_262, _l_mask_mask_T_264, _l_mask_mask_T_266)
node _l_mask_mask_T_268 = mux(_l_mask_mask_T_258, _l_mask_mask_T_261, _l_mask_mask_T_267)
node _l_mask_mask_T_269 = mux(_l_mask_mask_T_255, _l_mask_mask_T_257, _l_mask_mask_T_268)
connect l_mask_17, _l_mask_mask_T_269
node _l_forwarders_T_34 = eq(wb_forward_ldq_idx[0], UInt<5>(0h11))
node _l_forwarders_T_35 = and(wb_forward_valid[0], _l_forwarders_T_34)
wire l_forwarders_17 : UInt<1>[1]
connect l_forwarders_17[0], _l_forwarders_T_35
node l_forward_stq_idx_17 = mux(l_forwarders_17[0], wb_forward_stq_idx[0], ldq[17].bits.forward_stq_idx)
node _block_addr_matches_T_51 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_52 = shr(ldq[17].bits.addr.bits, 6)
node _block_addr_matches_T_53 = eq(_block_addr_matches_T_51, _block_addr_matches_T_52)
wire block_addr_matches_17 : UInt<1>[1]
connect block_addr_matches_17[0], _block_addr_matches_T_53
node _dword_addr_matches_T_68 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_69 = bits(ldq[17].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_70 = eq(_dword_addr_matches_T_68, _dword_addr_matches_T_69)
node _dword_addr_matches_T_71 = and(block_addr_matches_17[0], _dword_addr_matches_T_70)
wire dword_addr_matches_17 : UInt<1>[1]
connect dword_addr_matches_17[0], _dword_addr_matches_T_71
node _mask_match_T_34 = and(l_mask_17, lcam_mask[0])
node _mask_match_T_35 = eq(_mask_match_T_34, l_mask_17)
wire mask_match_17 : UInt<1>[1]
connect mask_match_17[0], _mask_match_T_35
node _mask_overlap_T_34 = and(l_mask_17, lcam_mask[0])
node _mask_overlap_T_35 = orr(_mask_overlap_T_34)
wire mask_overlap_17 : UInt<1>[1]
connect mask_overlap_17[0], _mask_overlap_T_35
node _T_875 = and(do_release_search[0], ldq[17].valid)
node _T_876 = and(_T_875, ldq[17].bits.addr.valid)
node _T_877 = and(_T_876, block_addr_matches_17[0])
when _T_877 :
connect ldq[17].bits.observed, UInt<1>(0h1)
else :
node _T_878 = and(do_st_search[0], ldq[17].valid)
node _T_879 = and(_T_878, ldq[17].bits.addr.valid)
node _T_880 = or(ldq[17].bits.executed, ldq[17].bits.succeeded)
node _T_881 = or(_T_880, l_forwarders_17[0])
node _T_882 = and(_T_879, _T_881)
node _T_883 = eq(ldq[17].bits.addr_is_virtual, UInt<1>(0h0))
node _T_884 = and(_T_882, _T_883)
node _T_885 = dshr(ldq[17].bits.st_dep_mask, lcam_stq_idx[0])
node _T_886 = bits(_T_885, 0, 0)
node _T_887 = and(_T_884, _T_886)
node _T_888 = and(_T_887, dword_addr_matches_17[0])
node _T_889 = and(_T_888, mask_overlap_17[0])
when _T_889 :
node _forwarded_is_older_T_68 = lt(l_forward_stq_idx_17, lcam_stq_idx[0])
node _forwarded_is_older_T_69 = lt(l_forward_stq_idx_17, ldq[17].bits.youngest_stq_idx)
node _forwarded_is_older_T_70 = xor(_forwarded_is_older_T_68, _forwarded_is_older_T_69)
node _forwarded_is_older_T_71 = lt(lcam_stq_idx[0], ldq[17].bits.youngest_stq_idx)
node forwarded_is_older_17 = xor(_forwarded_is_older_T_70, _forwarded_is_older_T_71)
node _T_890 = eq(ldq[17].bits.forward_std_val, UInt<1>(0h0))
node _T_891 = neq(l_forward_stq_idx_17, lcam_stq_idx[0])
node _T_892 = and(_T_891, forwarded_is_older_17)
node _T_893 = or(_T_890, _T_892)
when _T_893 :
connect ldq[17].bits.order_fail, UInt<1>(0h1)
connect failed_loads[17], UInt<1>(0h1)
else :
node _T_894 = and(do_ld_search[0], ldq[17].valid)
node _T_895 = and(_T_894, ldq[17].bits.addr.valid)
node _T_896 = eq(ldq[17].bits.addr_is_virtual, UInt<1>(0h0))
node _T_897 = and(_T_895, _T_896)
node _T_898 = and(_T_897, dword_addr_matches_17[0])
node _T_899 = and(_T_898, mask_overlap_17[0])
when _T_899 :
node _searcher_is_older_T_68 = lt(lcam_ldq_idx[0], UInt<5>(0h11))
node _searcher_is_older_T_69 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_70 = xor(_searcher_is_older_T_68, _searcher_is_older_T_69)
node _searcher_is_older_T_71 = lt(UInt<5>(0h11), ldq_head)
node searcher_is_older_17 = xor(_searcher_is_older_T_70, _searcher_is_older_T_71)
when searcher_is_older_17 :
node _T_900 = or(ldq[17].bits.executed, ldq[17].bits.succeeded)
node _T_901 = or(_T_900, l_forwarders_17[0])
node _T_902 = eq(s1_executing_loads[17], UInt<1>(0h0))
node _T_903 = and(_T_901, _T_902)
node _T_904 = and(_T_903, ldq[17].bits.observed)
when _T_904 :
connect ldq[17].bits.order_fail, UInt<1>(0h1)
connect failed_loads[17], UInt<1>(0h1)
else :
node _T_905 = neq(lcam_ldq_idx[0], UInt<5>(0h11))
when _T_905 :
reg older_nacked_REG_17 : UInt<1>, clock
connect older_nacked_REG_17, nacking_loads[17]
node older_nacked_17 = or(nacking_loads[17], older_nacked_REG_17)
node _T_906 = or(ldq[17].bits.executed, ldq[17].bits.succeeded)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = or(_T_907, older_nacked_17)
when _T_908 :
node _T_909 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_910 = bits(_T_909, 4, 0)
connect s1_set_execute[_T_910], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_17 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_17, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_17
connect can_forward[0], UInt<1>(0h0)
wire l_mask_18 : UInt<8>
node _l_mask_mask_T_270 = eq(ldq[18].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_271 = bits(ldq[18].bits.addr.bits, 2, 0)
node _l_mask_mask_T_272 = dshl(UInt<8>(0h1), _l_mask_mask_T_271)
node _l_mask_mask_T_273 = eq(ldq[18].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_274 = bits(ldq[18].bits.addr.bits, 2, 1)
node _l_mask_mask_T_275 = dshl(_l_mask_mask_T_274, UInt<1>(0h1))
node _l_mask_mask_T_276 = dshl(UInt<8>(0h3), _l_mask_mask_T_275)
node _l_mask_mask_T_277 = eq(ldq[18].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_278 = bits(ldq[18].bits.addr.bits, 2, 2)
node _l_mask_mask_T_279 = mux(_l_mask_mask_T_278, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_280 = eq(ldq[18].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_281 = mux(_l_mask_mask_T_280, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_282 = mux(_l_mask_mask_T_277, _l_mask_mask_T_279, _l_mask_mask_T_281)
node _l_mask_mask_T_283 = mux(_l_mask_mask_T_273, _l_mask_mask_T_276, _l_mask_mask_T_282)
node _l_mask_mask_T_284 = mux(_l_mask_mask_T_270, _l_mask_mask_T_272, _l_mask_mask_T_283)
connect l_mask_18, _l_mask_mask_T_284
node _l_forwarders_T_36 = eq(wb_forward_ldq_idx[0], UInt<5>(0h12))
node _l_forwarders_T_37 = and(wb_forward_valid[0], _l_forwarders_T_36)
wire l_forwarders_18 : UInt<1>[1]
connect l_forwarders_18[0], _l_forwarders_T_37
node l_forward_stq_idx_18 = mux(l_forwarders_18[0], wb_forward_stq_idx[0], ldq[18].bits.forward_stq_idx)
node _block_addr_matches_T_54 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_55 = shr(ldq[18].bits.addr.bits, 6)
node _block_addr_matches_T_56 = eq(_block_addr_matches_T_54, _block_addr_matches_T_55)
wire block_addr_matches_18 : UInt<1>[1]
connect block_addr_matches_18[0], _block_addr_matches_T_56
node _dword_addr_matches_T_72 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_73 = bits(ldq[18].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_74 = eq(_dword_addr_matches_T_72, _dword_addr_matches_T_73)
node _dword_addr_matches_T_75 = and(block_addr_matches_18[0], _dword_addr_matches_T_74)
wire dword_addr_matches_18 : UInt<1>[1]
connect dword_addr_matches_18[0], _dword_addr_matches_T_75
node _mask_match_T_36 = and(l_mask_18, lcam_mask[0])
node _mask_match_T_37 = eq(_mask_match_T_36, l_mask_18)
wire mask_match_18 : UInt<1>[1]
connect mask_match_18[0], _mask_match_T_37
node _mask_overlap_T_36 = and(l_mask_18, lcam_mask[0])
node _mask_overlap_T_37 = orr(_mask_overlap_T_36)
wire mask_overlap_18 : UInt<1>[1]
connect mask_overlap_18[0], _mask_overlap_T_37
node _T_911 = and(do_release_search[0], ldq[18].valid)
node _T_912 = and(_T_911, ldq[18].bits.addr.valid)
node _T_913 = and(_T_912, block_addr_matches_18[0])
when _T_913 :
connect ldq[18].bits.observed, UInt<1>(0h1)
else :
node _T_914 = and(do_st_search[0], ldq[18].valid)
node _T_915 = and(_T_914, ldq[18].bits.addr.valid)
node _T_916 = or(ldq[18].bits.executed, ldq[18].bits.succeeded)
node _T_917 = or(_T_916, l_forwarders_18[0])
node _T_918 = and(_T_915, _T_917)
node _T_919 = eq(ldq[18].bits.addr_is_virtual, UInt<1>(0h0))
node _T_920 = and(_T_918, _T_919)
node _T_921 = dshr(ldq[18].bits.st_dep_mask, lcam_stq_idx[0])
node _T_922 = bits(_T_921, 0, 0)
node _T_923 = and(_T_920, _T_922)
node _T_924 = and(_T_923, dword_addr_matches_18[0])
node _T_925 = and(_T_924, mask_overlap_18[0])
when _T_925 :
node _forwarded_is_older_T_72 = lt(l_forward_stq_idx_18, lcam_stq_idx[0])
node _forwarded_is_older_T_73 = lt(l_forward_stq_idx_18, ldq[18].bits.youngest_stq_idx)
node _forwarded_is_older_T_74 = xor(_forwarded_is_older_T_72, _forwarded_is_older_T_73)
node _forwarded_is_older_T_75 = lt(lcam_stq_idx[0], ldq[18].bits.youngest_stq_idx)
node forwarded_is_older_18 = xor(_forwarded_is_older_T_74, _forwarded_is_older_T_75)
node _T_926 = eq(ldq[18].bits.forward_std_val, UInt<1>(0h0))
node _T_927 = neq(l_forward_stq_idx_18, lcam_stq_idx[0])
node _T_928 = and(_T_927, forwarded_is_older_18)
node _T_929 = or(_T_926, _T_928)
when _T_929 :
connect ldq[18].bits.order_fail, UInt<1>(0h1)
connect failed_loads[18], UInt<1>(0h1)
else :
node _T_930 = and(do_ld_search[0], ldq[18].valid)
node _T_931 = and(_T_930, ldq[18].bits.addr.valid)
node _T_932 = eq(ldq[18].bits.addr_is_virtual, UInt<1>(0h0))
node _T_933 = and(_T_931, _T_932)
node _T_934 = and(_T_933, dword_addr_matches_18[0])
node _T_935 = and(_T_934, mask_overlap_18[0])
when _T_935 :
node _searcher_is_older_T_72 = lt(lcam_ldq_idx[0], UInt<5>(0h12))
node _searcher_is_older_T_73 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_74 = xor(_searcher_is_older_T_72, _searcher_is_older_T_73)
node _searcher_is_older_T_75 = lt(UInt<5>(0h12), ldq_head)
node searcher_is_older_18 = xor(_searcher_is_older_T_74, _searcher_is_older_T_75)
when searcher_is_older_18 :
node _T_936 = or(ldq[18].bits.executed, ldq[18].bits.succeeded)
node _T_937 = or(_T_936, l_forwarders_18[0])
node _T_938 = eq(s1_executing_loads[18], UInt<1>(0h0))
node _T_939 = and(_T_937, _T_938)
node _T_940 = and(_T_939, ldq[18].bits.observed)
when _T_940 :
connect ldq[18].bits.order_fail, UInt<1>(0h1)
connect failed_loads[18], UInt<1>(0h1)
else :
node _T_941 = neq(lcam_ldq_idx[0], UInt<5>(0h12))
when _T_941 :
reg older_nacked_REG_18 : UInt<1>, clock
connect older_nacked_REG_18, nacking_loads[18]
node older_nacked_18 = or(nacking_loads[18], older_nacked_REG_18)
node _T_942 = or(ldq[18].bits.executed, ldq[18].bits.succeeded)
node _T_943 = eq(_T_942, UInt<1>(0h0))
node _T_944 = or(_T_943, older_nacked_18)
when _T_944 :
node _T_945 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_946 = bits(_T_945, 4, 0)
connect s1_set_execute[_T_946], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_18 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_18, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_18
connect can_forward[0], UInt<1>(0h0)
wire l_mask_19 : UInt<8>
node _l_mask_mask_T_285 = eq(ldq[19].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_286 = bits(ldq[19].bits.addr.bits, 2, 0)
node _l_mask_mask_T_287 = dshl(UInt<8>(0h1), _l_mask_mask_T_286)
node _l_mask_mask_T_288 = eq(ldq[19].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_289 = bits(ldq[19].bits.addr.bits, 2, 1)
node _l_mask_mask_T_290 = dshl(_l_mask_mask_T_289, UInt<1>(0h1))
node _l_mask_mask_T_291 = dshl(UInt<8>(0h3), _l_mask_mask_T_290)
node _l_mask_mask_T_292 = eq(ldq[19].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_293 = bits(ldq[19].bits.addr.bits, 2, 2)
node _l_mask_mask_T_294 = mux(_l_mask_mask_T_293, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_295 = eq(ldq[19].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_296 = mux(_l_mask_mask_T_295, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_297 = mux(_l_mask_mask_T_292, _l_mask_mask_T_294, _l_mask_mask_T_296)
node _l_mask_mask_T_298 = mux(_l_mask_mask_T_288, _l_mask_mask_T_291, _l_mask_mask_T_297)
node _l_mask_mask_T_299 = mux(_l_mask_mask_T_285, _l_mask_mask_T_287, _l_mask_mask_T_298)
connect l_mask_19, _l_mask_mask_T_299
node _l_forwarders_T_38 = eq(wb_forward_ldq_idx[0], UInt<5>(0h13))
node _l_forwarders_T_39 = and(wb_forward_valid[0], _l_forwarders_T_38)
wire l_forwarders_19 : UInt<1>[1]
connect l_forwarders_19[0], _l_forwarders_T_39
node l_forward_stq_idx_19 = mux(l_forwarders_19[0], wb_forward_stq_idx[0], ldq[19].bits.forward_stq_idx)
node _block_addr_matches_T_57 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_58 = shr(ldq[19].bits.addr.bits, 6)
node _block_addr_matches_T_59 = eq(_block_addr_matches_T_57, _block_addr_matches_T_58)
wire block_addr_matches_19 : UInt<1>[1]
connect block_addr_matches_19[0], _block_addr_matches_T_59
node _dword_addr_matches_T_76 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_77 = bits(ldq[19].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_78 = eq(_dword_addr_matches_T_76, _dword_addr_matches_T_77)
node _dword_addr_matches_T_79 = and(block_addr_matches_19[0], _dword_addr_matches_T_78)
wire dword_addr_matches_19 : UInt<1>[1]
connect dword_addr_matches_19[0], _dword_addr_matches_T_79
node _mask_match_T_38 = and(l_mask_19, lcam_mask[0])
node _mask_match_T_39 = eq(_mask_match_T_38, l_mask_19)
wire mask_match_19 : UInt<1>[1]
connect mask_match_19[0], _mask_match_T_39
node _mask_overlap_T_38 = and(l_mask_19, lcam_mask[0])
node _mask_overlap_T_39 = orr(_mask_overlap_T_38)
wire mask_overlap_19 : UInt<1>[1]
connect mask_overlap_19[0], _mask_overlap_T_39
node _T_947 = and(do_release_search[0], ldq[19].valid)
node _T_948 = and(_T_947, ldq[19].bits.addr.valid)
node _T_949 = and(_T_948, block_addr_matches_19[0])
when _T_949 :
connect ldq[19].bits.observed, UInt<1>(0h1)
else :
node _T_950 = and(do_st_search[0], ldq[19].valid)
node _T_951 = and(_T_950, ldq[19].bits.addr.valid)
node _T_952 = or(ldq[19].bits.executed, ldq[19].bits.succeeded)
node _T_953 = or(_T_952, l_forwarders_19[0])
node _T_954 = and(_T_951, _T_953)
node _T_955 = eq(ldq[19].bits.addr_is_virtual, UInt<1>(0h0))
node _T_956 = and(_T_954, _T_955)
node _T_957 = dshr(ldq[19].bits.st_dep_mask, lcam_stq_idx[0])
node _T_958 = bits(_T_957, 0, 0)
node _T_959 = and(_T_956, _T_958)
node _T_960 = and(_T_959, dword_addr_matches_19[0])
node _T_961 = and(_T_960, mask_overlap_19[0])
when _T_961 :
node _forwarded_is_older_T_76 = lt(l_forward_stq_idx_19, lcam_stq_idx[0])
node _forwarded_is_older_T_77 = lt(l_forward_stq_idx_19, ldq[19].bits.youngest_stq_idx)
node _forwarded_is_older_T_78 = xor(_forwarded_is_older_T_76, _forwarded_is_older_T_77)
node _forwarded_is_older_T_79 = lt(lcam_stq_idx[0], ldq[19].bits.youngest_stq_idx)
node forwarded_is_older_19 = xor(_forwarded_is_older_T_78, _forwarded_is_older_T_79)
node _T_962 = eq(ldq[19].bits.forward_std_val, UInt<1>(0h0))
node _T_963 = neq(l_forward_stq_idx_19, lcam_stq_idx[0])
node _T_964 = and(_T_963, forwarded_is_older_19)
node _T_965 = or(_T_962, _T_964)
when _T_965 :
connect ldq[19].bits.order_fail, UInt<1>(0h1)
connect failed_loads[19], UInt<1>(0h1)
else :
node _T_966 = and(do_ld_search[0], ldq[19].valid)
node _T_967 = and(_T_966, ldq[19].bits.addr.valid)
node _T_968 = eq(ldq[19].bits.addr_is_virtual, UInt<1>(0h0))
node _T_969 = and(_T_967, _T_968)
node _T_970 = and(_T_969, dword_addr_matches_19[0])
node _T_971 = and(_T_970, mask_overlap_19[0])
when _T_971 :
node _searcher_is_older_T_76 = lt(lcam_ldq_idx[0], UInt<5>(0h13))
node _searcher_is_older_T_77 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_78 = xor(_searcher_is_older_T_76, _searcher_is_older_T_77)
node _searcher_is_older_T_79 = lt(UInt<5>(0h13), ldq_head)
node searcher_is_older_19 = xor(_searcher_is_older_T_78, _searcher_is_older_T_79)
when searcher_is_older_19 :
node _T_972 = or(ldq[19].bits.executed, ldq[19].bits.succeeded)
node _T_973 = or(_T_972, l_forwarders_19[0])
node _T_974 = eq(s1_executing_loads[19], UInt<1>(0h0))
node _T_975 = and(_T_973, _T_974)
node _T_976 = and(_T_975, ldq[19].bits.observed)
when _T_976 :
connect ldq[19].bits.order_fail, UInt<1>(0h1)
connect failed_loads[19], UInt<1>(0h1)
else :
node _T_977 = neq(lcam_ldq_idx[0], UInt<5>(0h13))
when _T_977 :
reg older_nacked_REG_19 : UInt<1>, clock
connect older_nacked_REG_19, nacking_loads[19]
node older_nacked_19 = or(nacking_loads[19], older_nacked_REG_19)
node _T_978 = or(ldq[19].bits.executed, ldq[19].bits.succeeded)
node _T_979 = eq(_T_978, UInt<1>(0h0))
node _T_980 = or(_T_979, older_nacked_19)
when _T_980 :
node _T_981 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_982 = bits(_T_981, 4, 0)
connect s1_set_execute[_T_982], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_19 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_19, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_19
connect can_forward[0], UInt<1>(0h0)
wire l_mask_20 : UInt<8>
node _l_mask_mask_T_300 = eq(ldq[20].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_301 = bits(ldq[20].bits.addr.bits, 2, 0)
node _l_mask_mask_T_302 = dshl(UInt<8>(0h1), _l_mask_mask_T_301)
node _l_mask_mask_T_303 = eq(ldq[20].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_304 = bits(ldq[20].bits.addr.bits, 2, 1)
node _l_mask_mask_T_305 = dshl(_l_mask_mask_T_304, UInt<1>(0h1))
node _l_mask_mask_T_306 = dshl(UInt<8>(0h3), _l_mask_mask_T_305)
node _l_mask_mask_T_307 = eq(ldq[20].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_308 = bits(ldq[20].bits.addr.bits, 2, 2)
node _l_mask_mask_T_309 = mux(_l_mask_mask_T_308, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_310 = eq(ldq[20].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_311 = mux(_l_mask_mask_T_310, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_312 = mux(_l_mask_mask_T_307, _l_mask_mask_T_309, _l_mask_mask_T_311)
node _l_mask_mask_T_313 = mux(_l_mask_mask_T_303, _l_mask_mask_T_306, _l_mask_mask_T_312)
node _l_mask_mask_T_314 = mux(_l_mask_mask_T_300, _l_mask_mask_T_302, _l_mask_mask_T_313)
connect l_mask_20, _l_mask_mask_T_314
node _l_forwarders_T_40 = eq(wb_forward_ldq_idx[0], UInt<5>(0h14))
node _l_forwarders_T_41 = and(wb_forward_valid[0], _l_forwarders_T_40)
wire l_forwarders_20 : UInt<1>[1]
connect l_forwarders_20[0], _l_forwarders_T_41
node l_forward_stq_idx_20 = mux(l_forwarders_20[0], wb_forward_stq_idx[0], ldq[20].bits.forward_stq_idx)
node _block_addr_matches_T_60 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_61 = shr(ldq[20].bits.addr.bits, 6)
node _block_addr_matches_T_62 = eq(_block_addr_matches_T_60, _block_addr_matches_T_61)
wire block_addr_matches_20 : UInt<1>[1]
connect block_addr_matches_20[0], _block_addr_matches_T_62
node _dword_addr_matches_T_80 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_81 = bits(ldq[20].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_82 = eq(_dword_addr_matches_T_80, _dword_addr_matches_T_81)
node _dword_addr_matches_T_83 = and(block_addr_matches_20[0], _dword_addr_matches_T_82)
wire dword_addr_matches_20 : UInt<1>[1]
connect dword_addr_matches_20[0], _dword_addr_matches_T_83
node _mask_match_T_40 = and(l_mask_20, lcam_mask[0])
node _mask_match_T_41 = eq(_mask_match_T_40, l_mask_20)
wire mask_match_20 : UInt<1>[1]
connect mask_match_20[0], _mask_match_T_41
node _mask_overlap_T_40 = and(l_mask_20, lcam_mask[0])
node _mask_overlap_T_41 = orr(_mask_overlap_T_40)
wire mask_overlap_20 : UInt<1>[1]
connect mask_overlap_20[0], _mask_overlap_T_41
node _T_983 = and(do_release_search[0], ldq[20].valid)
node _T_984 = and(_T_983, ldq[20].bits.addr.valid)
node _T_985 = and(_T_984, block_addr_matches_20[0])
when _T_985 :
connect ldq[20].bits.observed, UInt<1>(0h1)
else :
node _T_986 = and(do_st_search[0], ldq[20].valid)
node _T_987 = and(_T_986, ldq[20].bits.addr.valid)
node _T_988 = or(ldq[20].bits.executed, ldq[20].bits.succeeded)
node _T_989 = or(_T_988, l_forwarders_20[0])
node _T_990 = and(_T_987, _T_989)
node _T_991 = eq(ldq[20].bits.addr_is_virtual, UInt<1>(0h0))
node _T_992 = and(_T_990, _T_991)
node _T_993 = dshr(ldq[20].bits.st_dep_mask, lcam_stq_idx[0])
node _T_994 = bits(_T_993, 0, 0)
node _T_995 = and(_T_992, _T_994)
node _T_996 = and(_T_995, dword_addr_matches_20[0])
node _T_997 = and(_T_996, mask_overlap_20[0])
when _T_997 :
node _forwarded_is_older_T_80 = lt(l_forward_stq_idx_20, lcam_stq_idx[0])
node _forwarded_is_older_T_81 = lt(l_forward_stq_idx_20, ldq[20].bits.youngest_stq_idx)
node _forwarded_is_older_T_82 = xor(_forwarded_is_older_T_80, _forwarded_is_older_T_81)
node _forwarded_is_older_T_83 = lt(lcam_stq_idx[0], ldq[20].bits.youngest_stq_idx)
node forwarded_is_older_20 = xor(_forwarded_is_older_T_82, _forwarded_is_older_T_83)
node _T_998 = eq(ldq[20].bits.forward_std_val, UInt<1>(0h0))
node _T_999 = neq(l_forward_stq_idx_20, lcam_stq_idx[0])
node _T_1000 = and(_T_999, forwarded_is_older_20)
node _T_1001 = or(_T_998, _T_1000)
when _T_1001 :
connect ldq[20].bits.order_fail, UInt<1>(0h1)
connect failed_loads[20], UInt<1>(0h1)
else :
node _T_1002 = and(do_ld_search[0], ldq[20].valid)
node _T_1003 = and(_T_1002, ldq[20].bits.addr.valid)
node _T_1004 = eq(ldq[20].bits.addr_is_virtual, UInt<1>(0h0))
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = and(_T_1005, dword_addr_matches_20[0])
node _T_1007 = and(_T_1006, mask_overlap_20[0])
when _T_1007 :
node _searcher_is_older_T_80 = lt(lcam_ldq_idx[0], UInt<5>(0h14))
node _searcher_is_older_T_81 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_82 = xor(_searcher_is_older_T_80, _searcher_is_older_T_81)
node _searcher_is_older_T_83 = lt(UInt<5>(0h14), ldq_head)
node searcher_is_older_20 = xor(_searcher_is_older_T_82, _searcher_is_older_T_83)
when searcher_is_older_20 :
node _T_1008 = or(ldq[20].bits.executed, ldq[20].bits.succeeded)
node _T_1009 = or(_T_1008, l_forwarders_20[0])
node _T_1010 = eq(s1_executing_loads[20], UInt<1>(0h0))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = and(_T_1011, ldq[20].bits.observed)
when _T_1012 :
connect ldq[20].bits.order_fail, UInt<1>(0h1)
connect failed_loads[20], UInt<1>(0h1)
else :
node _T_1013 = neq(lcam_ldq_idx[0], UInt<5>(0h14))
when _T_1013 :
reg older_nacked_REG_20 : UInt<1>, clock
connect older_nacked_REG_20, nacking_loads[20]
node older_nacked_20 = or(nacking_loads[20], older_nacked_REG_20)
node _T_1014 = or(ldq[20].bits.executed, ldq[20].bits.succeeded)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
node _T_1016 = or(_T_1015, older_nacked_20)
when _T_1016 :
node _T_1017 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1018 = bits(_T_1017, 4, 0)
connect s1_set_execute[_T_1018], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_20 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_20, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_20
connect can_forward[0], UInt<1>(0h0)
wire l_mask_21 : UInt<8>
node _l_mask_mask_T_315 = eq(ldq[21].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_316 = bits(ldq[21].bits.addr.bits, 2, 0)
node _l_mask_mask_T_317 = dshl(UInt<8>(0h1), _l_mask_mask_T_316)
node _l_mask_mask_T_318 = eq(ldq[21].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_319 = bits(ldq[21].bits.addr.bits, 2, 1)
node _l_mask_mask_T_320 = dshl(_l_mask_mask_T_319, UInt<1>(0h1))
node _l_mask_mask_T_321 = dshl(UInt<8>(0h3), _l_mask_mask_T_320)
node _l_mask_mask_T_322 = eq(ldq[21].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_323 = bits(ldq[21].bits.addr.bits, 2, 2)
node _l_mask_mask_T_324 = mux(_l_mask_mask_T_323, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_325 = eq(ldq[21].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_326 = mux(_l_mask_mask_T_325, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_327 = mux(_l_mask_mask_T_322, _l_mask_mask_T_324, _l_mask_mask_T_326)
node _l_mask_mask_T_328 = mux(_l_mask_mask_T_318, _l_mask_mask_T_321, _l_mask_mask_T_327)
node _l_mask_mask_T_329 = mux(_l_mask_mask_T_315, _l_mask_mask_T_317, _l_mask_mask_T_328)
connect l_mask_21, _l_mask_mask_T_329
node _l_forwarders_T_42 = eq(wb_forward_ldq_idx[0], UInt<5>(0h15))
node _l_forwarders_T_43 = and(wb_forward_valid[0], _l_forwarders_T_42)
wire l_forwarders_21 : UInt<1>[1]
connect l_forwarders_21[0], _l_forwarders_T_43
node l_forward_stq_idx_21 = mux(l_forwarders_21[0], wb_forward_stq_idx[0], ldq[21].bits.forward_stq_idx)
node _block_addr_matches_T_63 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_64 = shr(ldq[21].bits.addr.bits, 6)
node _block_addr_matches_T_65 = eq(_block_addr_matches_T_63, _block_addr_matches_T_64)
wire block_addr_matches_21 : UInt<1>[1]
connect block_addr_matches_21[0], _block_addr_matches_T_65
node _dword_addr_matches_T_84 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_85 = bits(ldq[21].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_86 = eq(_dword_addr_matches_T_84, _dword_addr_matches_T_85)
node _dword_addr_matches_T_87 = and(block_addr_matches_21[0], _dword_addr_matches_T_86)
wire dword_addr_matches_21 : UInt<1>[1]
connect dword_addr_matches_21[0], _dword_addr_matches_T_87
node _mask_match_T_42 = and(l_mask_21, lcam_mask[0])
node _mask_match_T_43 = eq(_mask_match_T_42, l_mask_21)
wire mask_match_21 : UInt<1>[1]
connect mask_match_21[0], _mask_match_T_43
node _mask_overlap_T_42 = and(l_mask_21, lcam_mask[0])
node _mask_overlap_T_43 = orr(_mask_overlap_T_42)
wire mask_overlap_21 : UInt<1>[1]
connect mask_overlap_21[0], _mask_overlap_T_43
node _T_1019 = and(do_release_search[0], ldq[21].valid)
node _T_1020 = and(_T_1019, ldq[21].bits.addr.valid)
node _T_1021 = and(_T_1020, block_addr_matches_21[0])
when _T_1021 :
connect ldq[21].bits.observed, UInt<1>(0h1)
else :
node _T_1022 = and(do_st_search[0], ldq[21].valid)
node _T_1023 = and(_T_1022, ldq[21].bits.addr.valid)
node _T_1024 = or(ldq[21].bits.executed, ldq[21].bits.succeeded)
node _T_1025 = or(_T_1024, l_forwarders_21[0])
node _T_1026 = and(_T_1023, _T_1025)
node _T_1027 = eq(ldq[21].bits.addr_is_virtual, UInt<1>(0h0))
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = dshr(ldq[21].bits.st_dep_mask, lcam_stq_idx[0])
node _T_1030 = bits(_T_1029, 0, 0)
node _T_1031 = and(_T_1028, _T_1030)
node _T_1032 = and(_T_1031, dword_addr_matches_21[0])
node _T_1033 = and(_T_1032, mask_overlap_21[0])
when _T_1033 :
node _forwarded_is_older_T_84 = lt(l_forward_stq_idx_21, lcam_stq_idx[0])
node _forwarded_is_older_T_85 = lt(l_forward_stq_idx_21, ldq[21].bits.youngest_stq_idx)
node _forwarded_is_older_T_86 = xor(_forwarded_is_older_T_84, _forwarded_is_older_T_85)
node _forwarded_is_older_T_87 = lt(lcam_stq_idx[0], ldq[21].bits.youngest_stq_idx)
node forwarded_is_older_21 = xor(_forwarded_is_older_T_86, _forwarded_is_older_T_87)
node _T_1034 = eq(ldq[21].bits.forward_std_val, UInt<1>(0h0))
node _T_1035 = neq(l_forward_stq_idx_21, lcam_stq_idx[0])
node _T_1036 = and(_T_1035, forwarded_is_older_21)
node _T_1037 = or(_T_1034, _T_1036)
when _T_1037 :
connect ldq[21].bits.order_fail, UInt<1>(0h1)
connect failed_loads[21], UInt<1>(0h1)
else :
node _T_1038 = and(do_ld_search[0], ldq[21].valid)
node _T_1039 = and(_T_1038, ldq[21].bits.addr.valid)
node _T_1040 = eq(ldq[21].bits.addr_is_virtual, UInt<1>(0h0))
node _T_1041 = and(_T_1039, _T_1040)
node _T_1042 = and(_T_1041, dword_addr_matches_21[0])
node _T_1043 = and(_T_1042, mask_overlap_21[0])
when _T_1043 :
node _searcher_is_older_T_84 = lt(lcam_ldq_idx[0], UInt<5>(0h15))
node _searcher_is_older_T_85 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_86 = xor(_searcher_is_older_T_84, _searcher_is_older_T_85)
node _searcher_is_older_T_87 = lt(UInt<5>(0h15), ldq_head)
node searcher_is_older_21 = xor(_searcher_is_older_T_86, _searcher_is_older_T_87)
when searcher_is_older_21 :
node _T_1044 = or(ldq[21].bits.executed, ldq[21].bits.succeeded)
node _T_1045 = or(_T_1044, l_forwarders_21[0])
node _T_1046 = eq(s1_executing_loads[21], UInt<1>(0h0))
node _T_1047 = and(_T_1045, _T_1046)
node _T_1048 = and(_T_1047, ldq[21].bits.observed)
when _T_1048 :
connect ldq[21].bits.order_fail, UInt<1>(0h1)
connect failed_loads[21], UInt<1>(0h1)
else :
node _T_1049 = neq(lcam_ldq_idx[0], UInt<5>(0h15))
when _T_1049 :
reg older_nacked_REG_21 : UInt<1>, clock
connect older_nacked_REG_21, nacking_loads[21]
node older_nacked_21 = or(nacking_loads[21], older_nacked_REG_21)
node _T_1050 = or(ldq[21].bits.executed, ldq[21].bits.succeeded)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
node _T_1052 = or(_T_1051, older_nacked_21)
when _T_1052 :
node _T_1053 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1054 = bits(_T_1053, 4, 0)
connect s1_set_execute[_T_1054], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_21 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_21, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_21
connect can_forward[0], UInt<1>(0h0)
wire l_mask_22 : UInt<8>
node _l_mask_mask_T_330 = eq(ldq[22].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_331 = bits(ldq[22].bits.addr.bits, 2, 0)
node _l_mask_mask_T_332 = dshl(UInt<8>(0h1), _l_mask_mask_T_331)
node _l_mask_mask_T_333 = eq(ldq[22].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_334 = bits(ldq[22].bits.addr.bits, 2, 1)
node _l_mask_mask_T_335 = dshl(_l_mask_mask_T_334, UInt<1>(0h1))
node _l_mask_mask_T_336 = dshl(UInt<8>(0h3), _l_mask_mask_T_335)
node _l_mask_mask_T_337 = eq(ldq[22].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_338 = bits(ldq[22].bits.addr.bits, 2, 2)
node _l_mask_mask_T_339 = mux(_l_mask_mask_T_338, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_340 = eq(ldq[22].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_341 = mux(_l_mask_mask_T_340, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_342 = mux(_l_mask_mask_T_337, _l_mask_mask_T_339, _l_mask_mask_T_341)
node _l_mask_mask_T_343 = mux(_l_mask_mask_T_333, _l_mask_mask_T_336, _l_mask_mask_T_342)
node _l_mask_mask_T_344 = mux(_l_mask_mask_T_330, _l_mask_mask_T_332, _l_mask_mask_T_343)
connect l_mask_22, _l_mask_mask_T_344
node _l_forwarders_T_44 = eq(wb_forward_ldq_idx[0], UInt<5>(0h16))
node _l_forwarders_T_45 = and(wb_forward_valid[0], _l_forwarders_T_44)
wire l_forwarders_22 : UInt<1>[1]
connect l_forwarders_22[0], _l_forwarders_T_45
node l_forward_stq_idx_22 = mux(l_forwarders_22[0], wb_forward_stq_idx[0], ldq[22].bits.forward_stq_idx)
node _block_addr_matches_T_66 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_67 = shr(ldq[22].bits.addr.bits, 6)
node _block_addr_matches_T_68 = eq(_block_addr_matches_T_66, _block_addr_matches_T_67)
wire block_addr_matches_22 : UInt<1>[1]
connect block_addr_matches_22[0], _block_addr_matches_T_68
node _dword_addr_matches_T_88 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_89 = bits(ldq[22].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_90 = eq(_dword_addr_matches_T_88, _dword_addr_matches_T_89)
node _dword_addr_matches_T_91 = and(block_addr_matches_22[0], _dword_addr_matches_T_90)
wire dword_addr_matches_22 : UInt<1>[1]
connect dword_addr_matches_22[0], _dword_addr_matches_T_91
node _mask_match_T_44 = and(l_mask_22, lcam_mask[0])
node _mask_match_T_45 = eq(_mask_match_T_44, l_mask_22)
wire mask_match_22 : UInt<1>[1]
connect mask_match_22[0], _mask_match_T_45
node _mask_overlap_T_44 = and(l_mask_22, lcam_mask[0])
node _mask_overlap_T_45 = orr(_mask_overlap_T_44)
wire mask_overlap_22 : UInt<1>[1]
connect mask_overlap_22[0], _mask_overlap_T_45
node _T_1055 = and(do_release_search[0], ldq[22].valid)
node _T_1056 = and(_T_1055, ldq[22].bits.addr.valid)
node _T_1057 = and(_T_1056, block_addr_matches_22[0])
when _T_1057 :
connect ldq[22].bits.observed, UInt<1>(0h1)
else :
node _T_1058 = and(do_st_search[0], ldq[22].valid)
node _T_1059 = and(_T_1058, ldq[22].bits.addr.valid)
node _T_1060 = or(ldq[22].bits.executed, ldq[22].bits.succeeded)
node _T_1061 = or(_T_1060, l_forwarders_22[0])
node _T_1062 = and(_T_1059, _T_1061)
node _T_1063 = eq(ldq[22].bits.addr_is_virtual, UInt<1>(0h0))
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = dshr(ldq[22].bits.st_dep_mask, lcam_stq_idx[0])
node _T_1066 = bits(_T_1065, 0, 0)
node _T_1067 = and(_T_1064, _T_1066)
node _T_1068 = and(_T_1067, dword_addr_matches_22[0])
node _T_1069 = and(_T_1068, mask_overlap_22[0])
when _T_1069 :
node _forwarded_is_older_T_88 = lt(l_forward_stq_idx_22, lcam_stq_idx[0])
node _forwarded_is_older_T_89 = lt(l_forward_stq_idx_22, ldq[22].bits.youngest_stq_idx)
node _forwarded_is_older_T_90 = xor(_forwarded_is_older_T_88, _forwarded_is_older_T_89)
node _forwarded_is_older_T_91 = lt(lcam_stq_idx[0], ldq[22].bits.youngest_stq_idx)
node forwarded_is_older_22 = xor(_forwarded_is_older_T_90, _forwarded_is_older_T_91)
node _T_1070 = eq(ldq[22].bits.forward_std_val, UInt<1>(0h0))
node _T_1071 = neq(l_forward_stq_idx_22, lcam_stq_idx[0])
node _T_1072 = and(_T_1071, forwarded_is_older_22)
node _T_1073 = or(_T_1070, _T_1072)
when _T_1073 :
connect ldq[22].bits.order_fail, UInt<1>(0h1)
connect failed_loads[22], UInt<1>(0h1)
else :
node _T_1074 = and(do_ld_search[0], ldq[22].valid)
node _T_1075 = and(_T_1074, ldq[22].bits.addr.valid)
node _T_1076 = eq(ldq[22].bits.addr_is_virtual, UInt<1>(0h0))
node _T_1077 = and(_T_1075, _T_1076)
node _T_1078 = and(_T_1077, dword_addr_matches_22[0])
node _T_1079 = and(_T_1078, mask_overlap_22[0])
when _T_1079 :
node _searcher_is_older_T_88 = lt(lcam_ldq_idx[0], UInt<5>(0h16))
node _searcher_is_older_T_89 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_90 = xor(_searcher_is_older_T_88, _searcher_is_older_T_89)
node _searcher_is_older_T_91 = lt(UInt<5>(0h16), ldq_head)
node searcher_is_older_22 = xor(_searcher_is_older_T_90, _searcher_is_older_T_91)
when searcher_is_older_22 :
node _T_1080 = or(ldq[22].bits.executed, ldq[22].bits.succeeded)
node _T_1081 = or(_T_1080, l_forwarders_22[0])
node _T_1082 = eq(s1_executing_loads[22], UInt<1>(0h0))
node _T_1083 = and(_T_1081, _T_1082)
node _T_1084 = and(_T_1083, ldq[22].bits.observed)
when _T_1084 :
connect ldq[22].bits.order_fail, UInt<1>(0h1)
connect failed_loads[22], UInt<1>(0h1)
else :
node _T_1085 = neq(lcam_ldq_idx[0], UInt<5>(0h16))
when _T_1085 :
reg older_nacked_REG_22 : UInt<1>, clock
connect older_nacked_REG_22, nacking_loads[22]
node older_nacked_22 = or(nacking_loads[22], older_nacked_REG_22)
node _T_1086 = or(ldq[22].bits.executed, ldq[22].bits.succeeded)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
node _T_1088 = or(_T_1087, older_nacked_22)
when _T_1088 :
node _T_1089 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1090 = bits(_T_1089, 4, 0)
connect s1_set_execute[_T_1090], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_22 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_22, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_22
connect can_forward[0], UInt<1>(0h0)
wire l_mask_23 : UInt<8>
node _l_mask_mask_T_345 = eq(ldq[23].bits.uop.mem_size, UInt<1>(0h0))
node _l_mask_mask_T_346 = bits(ldq[23].bits.addr.bits, 2, 0)
node _l_mask_mask_T_347 = dshl(UInt<8>(0h1), _l_mask_mask_T_346)
node _l_mask_mask_T_348 = eq(ldq[23].bits.uop.mem_size, UInt<1>(0h1))
node _l_mask_mask_T_349 = bits(ldq[23].bits.addr.bits, 2, 1)
node _l_mask_mask_T_350 = dshl(_l_mask_mask_T_349, UInt<1>(0h1))
node _l_mask_mask_T_351 = dshl(UInt<8>(0h3), _l_mask_mask_T_350)
node _l_mask_mask_T_352 = eq(ldq[23].bits.uop.mem_size, UInt<2>(0h2))
node _l_mask_mask_T_353 = bits(ldq[23].bits.addr.bits, 2, 2)
node _l_mask_mask_T_354 = mux(_l_mask_mask_T_353, UInt<8>(0hf0), UInt<8>(0hf))
node _l_mask_mask_T_355 = eq(ldq[23].bits.uop.mem_size, UInt<2>(0h3))
node _l_mask_mask_T_356 = mux(_l_mask_mask_T_355, UInt<8>(0hff), UInt<8>(0hff))
node _l_mask_mask_T_357 = mux(_l_mask_mask_T_352, _l_mask_mask_T_354, _l_mask_mask_T_356)
node _l_mask_mask_T_358 = mux(_l_mask_mask_T_348, _l_mask_mask_T_351, _l_mask_mask_T_357)
node _l_mask_mask_T_359 = mux(_l_mask_mask_T_345, _l_mask_mask_T_347, _l_mask_mask_T_358)
connect l_mask_23, _l_mask_mask_T_359
node _l_forwarders_T_46 = eq(wb_forward_ldq_idx[0], UInt<5>(0h17))
node _l_forwarders_T_47 = and(wb_forward_valid[0], _l_forwarders_T_46)
wire l_forwarders_23 : UInt<1>[1]
connect l_forwarders_23[0], _l_forwarders_T_47
node l_forward_stq_idx_23 = mux(l_forwarders_23[0], wb_forward_stq_idx[0], ldq[23].bits.forward_stq_idx)
node _block_addr_matches_T_69 = shr(lcam_addr[0], 6)
node _block_addr_matches_T_70 = shr(ldq[23].bits.addr.bits, 6)
node _block_addr_matches_T_71 = eq(_block_addr_matches_T_69, _block_addr_matches_T_70)
wire block_addr_matches_23 : UInt<1>[1]
connect block_addr_matches_23[0], _block_addr_matches_T_71
node _dword_addr_matches_T_92 = bits(lcam_addr[0], 5, 3)
node _dword_addr_matches_T_93 = bits(ldq[23].bits.addr.bits, 5, 3)
node _dword_addr_matches_T_94 = eq(_dword_addr_matches_T_92, _dword_addr_matches_T_93)
node _dword_addr_matches_T_95 = and(block_addr_matches_23[0], _dword_addr_matches_T_94)
wire dword_addr_matches_23 : UInt<1>[1]
connect dword_addr_matches_23[0], _dword_addr_matches_T_95
node _mask_match_T_46 = and(l_mask_23, lcam_mask[0])
node _mask_match_T_47 = eq(_mask_match_T_46, l_mask_23)
wire mask_match_23 : UInt<1>[1]
connect mask_match_23[0], _mask_match_T_47
node _mask_overlap_T_46 = and(l_mask_23, lcam_mask[0])
node _mask_overlap_T_47 = orr(_mask_overlap_T_46)
wire mask_overlap_23 : UInt<1>[1]
connect mask_overlap_23[0], _mask_overlap_T_47
node _T_1091 = and(do_release_search[0], ldq[23].valid)
node _T_1092 = and(_T_1091, ldq[23].bits.addr.valid)
node _T_1093 = and(_T_1092, block_addr_matches_23[0])
when _T_1093 :
connect ldq[23].bits.observed, UInt<1>(0h1)
else :
node _T_1094 = and(do_st_search[0], ldq[23].valid)
node _T_1095 = and(_T_1094, ldq[23].bits.addr.valid)
node _T_1096 = or(ldq[23].bits.executed, ldq[23].bits.succeeded)
node _T_1097 = or(_T_1096, l_forwarders_23[0])
node _T_1098 = and(_T_1095, _T_1097)
node _T_1099 = eq(ldq[23].bits.addr_is_virtual, UInt<1>(0h0))
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = dshr(ldq[23].bits.st_dep_mask, lcam_stq_idx[0])
node _T_1102 = bits(_T_1101, 0, 0)
node _T_1103 = and(_T_1100, _T_1102)
node _T_1104 = and(_T_1103, dword_addr_matches_23[0])
node _T_1105 = and(_T_1104, mask_overlap_23[0])
when _T_1105 :
node _forwarded_is_older_T_92 = lt(l_forward_stq_idx_23, lcam_stq_idx[0])
node _forwarded_is_older_T_93 = lt(l_forward_stq_idx_23, ldq[23].bits.youngest_stq_idx)
node _forwarded_is_older_T_94 = xor(_forwarded_is_older_T_92, _forwarded_is_older_T_93)
node _forwarded_is_older_T_95 = lt(lcam_stq_idx[0], ldq[23].bits.youngest_stq_idx)
node forwarded_is_older_23 = xor(_forwarded_is_older_T_94, _forwarded_is_older_T_95)
node _T_1106 = eq(ldq[23].bits.forward_std_val, UInt<1>(0h0))
node _T_1107 = neq(l_forward_stq_idx_23, lcam_stq_idx[0])
node _T_1108 = and(_T_1107, forwarded_is_older_23)
node _T_1109 = or(_T_1106, _T_1108)
when _T_1109 :
connect ldq[23].bits.order_fail, UInt<1>(0h1)
connect failed_loads[23], UInt<1>(0h1)
else :
node _T_1110 = and(do_ld_search[0], ldq[23].valid)
node _T_1111 = and(_T_1110, ldq[23].bits.addr.valid)
node _T_1112 = eq(ldq[23].bits.addr_is_virtual, UInt<1>(0h0))
node _T_1113 = and(_T_1111, _T_1112)
node _T_1114 = and(_T_1113, dword_addr_matches_23[0])
node _T_1115 = and(_T_1114, mask_overlap_23[0])
when _T_1115 :
node _searcher_is_older_T_92 = lt(lcam_ldq_idx[0], UInt<5>(0h17))
node _searcher_is_older_T_93 = lt(lcam_ldq_idx[0], ldq_head)
node _searcher_is_older_T_94 = xor(_searcher_is_older_T_92, _searcher_is_older_T_93)
node _searcher_is_older_T_95 = lt(UInt<5>(0h17), ldq_head)
node searcher_is_older_23 = xor(_searcher_is_older_T_94, _searcher_is_older_T_95)
when searcher_is_older_23 :
node _T_1116 = or(ldq[23].bits.executed, ldq[23].bits.succeeded)
node _T_1117 = or(_T_1116, l_forwarders_23[0])
node _T_1118 = eq(s1_executing_loads[23], UInt<1>(0h0))
node _T_1119 = and(_T_1117, _T_1118)
node _T_1120 = and(_T_1119, ldq[23].bits.observed)
when _T_1120 :
connect ldq[23].bits.order_fail, UInt<1>(0h1)
connect failed_loads[23], UInt<1>(0h1)
else :
node _T_1121 = neq(lcam_ldq_idx[0], UInt<5>(0h17))
when _T_1121 :
reg older_nacked_REG_23 : UInt<1>, clock
connect older_nacked_REG_23, nacking_loads[23]
node older_nacked_23 = or(nacking_loads[23], older_nacked_REG_23)
node _T_1122 = or(ldq[23].bits.executed, ldq[23].bits.succeeded)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
node _T_1124 = or(_T_1123, older_nacked_23)
when _T_1124 :
node _T_1125 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1126 = bits(_T_1125, 4, 0)
connect s1_set_execute[_T_1126], UInt<1>(0h0)
reg io_dmem_s1_kill_0_REG_23 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_23, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_23
connect can_forward[0], UInt<1>(0h0)
node _dword_addr_matches_T_96 = eq(stq[0].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_97 = and(stq[0].bits.addr.valid, _dword_addr_matches_T_96)
node _dword_addr_matches_T_98 = bits(stq[0].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_99 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_100 = eq(_dword_addr_matches_T_98, _dword_addr_matches_T_99)
node _dword_addr_matches_T_101 = and(_dword_addr_matches_T_97, _dword_addr_matches_T_100)
wire dword_addr_matches_24 : UInt<1>[1]
connect dword_addr_matches_24[0], _dword_addr_matches_T_101
wire write_mask : UInt<8>
node _write_mask_mask_T = eq(stq[0].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_1 = bits(stq[0].bits.addr.bits, 2, 0)
node _write_mask_mask_T_2 = dshl(UInt<8>(0h1), _write_mask_mask_T_1)
node _write_mask_mask_T_3 = eq(stq[0].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_4 = bits(stq[0].bits.addr.bits, 2, 1)
node _write_mask_mask_T_5 = dshl(_write_mask_mask_T_4, UInt<1>(0h1))
node _write_mask_mask_T_6 = dshl(UInt<8>(0h3), _write_mask_mask_T_5)
node _write_mask_mask_T_7 = eq(stq[0].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_8 = bits(stq[0].bits.addr.bits, 2, 2)
node _write_mask_mask_T_9 = mux(_write_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_10 = eq(stq[0].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_11 = mux(_write_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_12 = mux(_write_mask_mask_T_7, _write_mask_mask_T_9, _write_mask_mask_T_11)
node _write_mask_mask_T_13 = mux(_write_mask_mask_T_3, _write_mask_mask_T_6, _write_mask_mask_T_12)
node _write_mask_mask_T_14 = mux(_write_mask_mask_T, _write_mask_mask_T_2, _write_mask_mask_T_13)
connect write_mask, _write_mask_mask_T_14
node _T_1127 = and(do_ld_search[0], stq[0].valid)
node _T_1128 = bits(lcam_st_dep_mask[0], 0, 0)
node _T_1129 = and(_T_1127, _T_1128)
when _T_1129 :
node _T_1130 = and(lcam_mask[0], write_mask)
node _T_1131 = eq(_T_1130, lcam_mask[0])
node _T_1132 = eq(stq[0].bits.uop.is_fence, UInt<1>(0h0))
node _T_1133 = and(_T_1131, _T_1132)
node _T_1134 = eq(stq[0].bits.uop.is_amo, UInt<1>(0h0))
node _T_1135 = and(_T_1133, _T_1134)
node _T_1136 = and(_T_1135, dword_addr_matches_24[0])
node _T_1137 = and(_T_1136, can_forward[0])
when _T_1137 :
connect ldst_addr_matches[0][0], UInt<1>(0h1)
connect ldst_forward_matches[0][0], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_24 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_24, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_24
node _T_1138 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1139 = bits(_T_1138, 4, 0)
connect s1_set_execute[_T_1139], UInt<1>(0h0)
else :
node _T_1140 = and(lcam_mask[0], write_mask)
node _T_1141 = neq(_T_1140, UInt<1>(0h0))
node _T_1142 = and(_T_1141, dword_addr_matches_24[0])
when _T_1142 :
connect ldst_addr_matches[0][0], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_25 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_25, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_25
node _T_1143 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1144 = bits(_T_1143, 4, 0)
connect s1_set_execute[_T_1144], UInt<1>(0h0)
else :
node _T_1145 = or(stq[0].bits.uop.is_fence, stq[0].bits.uop.is_amo)
when _T_1145 :
connect ldst_addr_matches[0][0], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_26 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_26, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_26
node _T_1146 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1147 = bits(_T_1146, 4, 0)
connect s1_set_execute[_T_1147], UInt<1>(0h0)
node _dword_addr_matches_T_102 = eq(stq[1].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_103 = and(stq[1].bits.addr.valid, _dword_addr_matches_T_102)
node _dword_addr_matches_T_104 = bits(stq[1].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_105 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_106 = eq(_dword_addr_matches_T_104, _dword_addr_matches_T_105)
node _dword_addr_matches_T_107 = and(_dword_addr_matches_T_103, _dword_addr_matches_T_106)
wire dword_addr_matches_25 : UInt<1>[1]
connect dword_addr_matches_25[0], _dword_addr_matches_T_107
wire write_mask_1 : UInt<8>
node _write_mask_mask_T_15 = eq(stq[1].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_16 = bits(stq[1].bits.addr.bits, 2, 0)
node _write_mask_mask_T_17 = dshl(UInt<8>(0h1), _write_mask_mask_T_16)
node _write_mask_mask_T_18 = eq(stq[1].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_19 = bits(stq[1].bits.addr.bits, 2, 1)
node _write_mask_mask_T_20 = dshl(_write_mask_mask_T_19, UInt<1>(0h1))
node _write_mask_mask_T_21 = dshl(UInt<8>(0h3), _write_mask_mask_T_20)
node _write_mask_mask_T_22 = eq(stq[1].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_23 = bits(stq[1].bits.addr.bits, 2, 2)
node _write_mask_mask_T_24 = mux(_write_mask_mask_T_23, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_25 = eq(stq[1].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_26 = mux(_write_mask_mask_T_25, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_27 = mux(_write_mask_mask_T_22, _write_mask_mask_T_24, _write_mask_mask_T_26)
node _write_mask_mask_T_28 = mux(_write_mask_mask_T_18, _write_mask_mask_T_21, _write_mask_mask_T_27)
node _write_mask_mask_T_29 = mux(_write_mask_mask_T_15, _write_mask_mask_T_17, _write_mask_mask_T_28)
connect write_mask_1, _write_mask_mask_T_29
node _T_1148 = and(do_ld_search[0], stq[1].valid)
node _T_1149 = bits(lcam_st_dep_mask[0], 1, 1)
node _T_1150 = and(_T_1148, _T_1149)
when _T_1150 :
node _T_1151 = and(lcam_mask[0], write_mask_1)
node _T_1152 = eq(_T_1151, lcam_mask[0])
node _T_1153 = eq(stq[1].bits.uop.is_fence, UInt<1>(0h0))
node _T_1154 = and(_T_1152, _T_1153)
node _T_1155 = eq(stq[1].bits.uop.is_amo, UInt<1>(0h0))
node _T_1156 = and(_T_1154, _T_1155)
node _T_1157 = and(_T_1156, dword_addr_matches_25[0])
node _T_1158 = and(_T_1157, can_forward[0])
when _T_1158 :
connect ldst_addr_matches[0][1], UInt<1>(0h1)
connect ldst_forward_matches[0][1], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_27 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_27, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_27
node _T_1159 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1160 = bits(_T_1159, 4, 0)
connect s1_set_execute[_T_1160], UInt<1>(0h0)
else :
node _T_1161 = and(lcam_mask[0], write_mask_1)
node _T_1162 = neq(_T_1161, UInt<1>(0h0))
node _T_1163 = and(_T_1162, dword_addr_matches_25[0])
when _T_1163 :
connect ldst_addr_matches[0][1], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_28 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_28, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_28
node _T_1164 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1165 = bits(_T_1164, 4, 0)
connect s1_set_execute[_T_1165], UInt<1>(0h0)
else :
node _T_1166 = or(stq[1].bits.uop.is_fence, stq[1].bits.uop.is_amo)
when _T_1166 :
connect ldst_addr_matches[0][1], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_29 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_29, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_29
node _T_1167 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1168 = bits(_T_1167, 4, 0)
connect s1_set_execute[_T_1168], UInt<1>(0h0)
node _dword_addr_matches_T_108 = eq(stq[2].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_109 = and(stq[2].bits.addr.valid, _dword_addr_matches_T_108)
node _dword_addr_matches_T_110 = bits(stq[2].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_111 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_112 = eq(_dword_addr_matches_T_110, _dword_addr_matches_T_111)
node _dword_addr_matches_T_113 = and(_dword_addr_matches_T_109, _dword_addr_matches_T_112)
wire dword_addr_matches_26 : UInt<1>[1]
connect dword_addr_matches_26[0], _dword_addr_matches_T_113
wire write_mask_2 : UInt<8>
node _write_mask_mask_T_30 = eq(stq[2].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_31 = bits(stq[2].bits.addr.bits, 2, 0)
node _write_mask_mask_T_32 = dshl(UInt<8>(0h1), _write_mask_mask_T_31)
node _write_mask_mask_T_33 = eq(stq[2].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_34 = bits(stq[2].bits.addr.bits, 2, 1)
node _write_mask_mask_T_35 = dshl(_write_mask_mask_T_34, UInt<1>(0h1))
node _write_mask_mask_T_36 = dshl(UInt<8>(0h3), _write_mask_mask_T_35)
node _write_mask_mask_T_37 = eq(stq[2].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_38 = bits(stq[2].bits.addr.bits, 2, 2)
node _write_mask_mask_T_39 = mux(_write_mask_mask_T_38, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_40 = eq(stq[2].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_41 = mux(_write_mask_mask_T_40, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_42 = mux(_write_mask_mask_T_37, _write_mask_mask_T_39, _write_mask_mask_T_41)
node _write_mask_mask_T_43 = mux(_write_mask_mask_T_33, _write_mask_mask_T_36, _write_mask_mask_T_42)
node _write_mask_mask_T_44 = mux(_write_mask_mask_T_30, _write_mask_mask_T_32, _write_mask_mask_T_43)
connect write_mask_2, _write_mask_mask_T_44
node _T_1169 = and(do_ld_search[0], stq[2].valid)
node _T_1170 = bits(lcam_st_dep_mask[0], 2, 2)
node _T_1171 = and(_T_1169, _T_1170)
when _T_1171 :
node _T_1172 = and(lcam_mask[0], write_mask_2)
node _T_1173 = eq(_T_1172, lcam_mask[0])
node _T_1174 = eq(stq[2].bits.uop.is_fence, UInt<1>(0h0))
node _T_1175 = and(_T_1173, _T_1174)
node _T_1176 = eq(stq[2].bits.uop.is_amo, UInt<1>(0h0))
node _T_1177 = and(_T_1175, _T_1176)
node _T_1178 = and(_T_1177, dword_addr_matches_26[0])
node _T_1179 = and(_T_1178, can_forward[0])
when _T_1179 :
connect ldst_addr_matches[0][2], UInt<1>(0h1)
connect ldst_forward_matches[0][2], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_30 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_30, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_30
node _T_1180 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1181 = bits(_T_1180, 4, 0)
connect s1_set_execute[_T_1181], UInt<1>(0h0)
else :
node _T_1182 = and(lcam_mask[0], write_mask_2)
node _T_1183 = neq(_T_1182, UInt<1>(0h0))
node _T_1184 = and(_T_1183, dword_addr_matches_26[0])
when _T_1184 :
connect ldst_addr_matches[0][2], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_31 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_31, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_31
node _T_1185 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1186 = bits(_T_1185, 4, 0)
connect s1_set_execute[_T_1186], UInt<1>(0h0)
else :
node _T_1187 = or(stq[2].bits.uop.is_fence, stq[2].bits.uop.is_amo)
when _T_1187 :
connect ldst_addr_matches[0][2], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_32 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_32, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_32
node _T_1188 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1189 = bits(_T_1188, 4, 0)
connect s1_set_execute[_T_1189], UInt<1>(0h0)
node _dword_addr_matches_T_114 = eq(stq[3].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_115 = and(stq[3].bits.addr.valid, _dword_addr_matches_T_114)
node _dword_addr_matches_T_116 = bits(stq[3].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_117 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_118 = eq(_dword_addr_matches_T_116, _dword_addr_matches_T_117)
node _dword_addr_matches_T_119 = and(_dword_addr_matches_T_115, _dword_addr_matches_T_118)
wire dword_addr_matches_27 : UInt<1>[1]
connect dword_addr_matches_27[0], _dword_addr_matches_T_119
wire write_mask_3 : UInt<8>
node _write_mask_mask_T_45 = eq(stq[3].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_46 = bits(stq[3].bits.addr.bits, 2, 0)
node _write_mask_mask_T_47 = dshl(UInt<8>(0h1), _write_mask_mask_T_46)
node _write_mask_mask_T_48 = eq(stq[3].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_49 = bits(stq[3].bits.addr.bits, 2, 1)
node _write_mask_mask_T_50 = dshl(_write_mask_mask_T_49, UInt<1>(0h1))
node _write_mask_mask_T_51 = dshl(UInt<8>(0h3), _write_mask_mask_T_50)
node _write_mask_mask_T_52 = eq(stq[3].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_53 = bits(stq[3].bits.addr.bits, 2, 2)
node _write_mask_mask_T_54 = mux(_write_mask_mask_T_53, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_55 = eq(stq[3].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_56 = mux(_write_mask_mask_T_55, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_57 = mux(_write_mask_mask_T_52, _write_mask_mask_T_54, _write_mask_mask_T_56)
node _write_mask_mask_T_58 = mux(_write_mask_mask_T_48, _write_mask_mask_T_51, _write_mask_mask_T_57)
node _write_mask_mask_T_59 = mux(_write_mask_mask_T_45, _write_mask_mask_T_47, _write_mask_mask_T_58)
connect write_mask_3, _write_mask_mask_T_59
node _T_1190 = and(do_ld_search[0], stq[3].valid)
node _T_1191 = bits(lcam_st_dep_mask[0], 3, 3)
node _T_1192 = and(_T_1190, _T_1191)
when _T_1192 :
node _T_1193 = and(lcam_mask[0], write_mask_3)
node _T_1194 = eq(_T_1193, lcam_mask[0])
node _T_1195 = eq(stq[3].bits.uop.is_fence, UInt<1>(0h0))
node _T_1196 = and(_T_1194, _T_1195)
node _T_1197 = eq(stq[3].bits.uop.is_amo, UInt<1>(0h0))
node _T_1198 = and(_T_1196, _T_1197)
node _T_1199 = and(_T_1198, dword_addr_matches_27[0])
node _T_1200 = and(_T_1199, can_forward[0])
when _T_1200 :
connect ldst_addr_matches[0][3], UInt<1>(0h1)
connect ldst_forward_matches[0][3], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_33 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_33, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_33
node _T_1201 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1202 = bits(_T_1201, 4, 0)
connect s1_set_execute[_T_1202], UInt<1>(0h0)
else :
node _T_1203 = and(lcam_mask[0], write_mask_3)
node _T_1204 = neq(_T_1203, UInt<1>(0h0))
node _T_1205 = and(_T_1204, dword_addr_matches_27[0])
when _T_1205 :
connect ldst_addr_matches[0][3], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_34 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_34, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_34
node _T_1206 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1207 = bits(_T_1206, 4, 0)
connect s1_set_execute[_T_1207], UInt<1>(0h0)
else :
node _T_1208 = or(stq[3].bits.uop.is_fence, stq[3].bits.uop.is_amo)
when _T_1208 :
connect ldst_addr_matches[0][3], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_35 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_35, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_35
node _T_1209 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1210 = bits(_T_1209, 4, 0)
connect s1_set_execute[_T_1210], UInt<1>(0h0)
node _dword_addr_matches_T_120 = eq(stq[4].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_121 = and(stq[4].bits.addr.valid, _dword_addr_matches_T_120)
node _dword_addr_matches_T_122 = bits(stq[4].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_123 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_124 = eq(_dword_addr_matches_T_122, _dword_addr_matches_T_123)
node _dword_addr_matches_T_125 = and(_dword_addr_matches_T_121, _dword_addr_matches_T_124)
wire dword_addr_matches_28 : UInt<1>[1]
connect dword_addr_matches_28[0], _dword_addr_matches_T_125
wire write_mask_4 : UInt<8>
node _write_mask_mask_T_60 = eq(stq[4].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_61 = bits(stq[4].bits.addr.bits, 2, 0)
node _write_mask_mask_T_62 = dshl(UInt<8>(0h1), _write_mask_mask_T_61)
node _write_mask_mask_T_63 = eq(stq[4].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_64 = bits(stq[4].bits.addr.bits, 2, 1)
node _write_mask_mask_T_65 = dshl(_write_mask_mask_T_64, UInt<1>(0h1))
node _write_mask_mask_T_66 = dshl(UInt<8>(0h3), _write_mask_mask_T_65)
node _write_mask_mask_T_67 = eq(stq[4].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_68 = bits(stq[4].bits.addr.bits, 2, 2)
node _write_mask_mask_T_69 = mux(_write_mask_mask_T_68, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_70 = eq(stq[4].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_71 = mux(_write_mask_mask_T_70, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_72 = mux(_write_mask_mask_T_67, _write_mask_mask_T_69, _write_mask_mask_T_71)
node _write_mask_mask_T_73 = mux(_write_mask_mask_T_63, _write_mask_mask_T_66, _write_mask_mask_T_72)
node _write_mask_mask_T_74 = mux(_write_mask_mask_T_60, _write_mask_mask_T_62, _write_mask_mask_T_73)
connect write_mask_4, _write_mask_mask_T_74
node _T_1211 = and(do_ld_search[0], stq[4].valid)
node _T_1212 = bits(lcam_st_dep_mask[0], 4, 4)
node _T_1213 = and(_T_1211, _T_1212)
when _T_1213 :
node _T_1214 = and(lcam_mask[0], write_mask_4)
node _T_1215 = eq(_T_1214, lcam_mask[0])
node _T_1216 = eq(stq[4].bits.uop.is_fence, UInt<1>(0h0))
node _T_1217 = and(_T_1215, _T_1216)
node _T_1218 = eq(stq[4].bits.uop.is_amo, UInt<1>(0h0))
node _T_1219 = and(_T_1217, _T_1218)
node _T_1220 = and(_T_1219, dword_addr_matches_28[0])
node _T_1221 = and(_T_1220, can_forward[0])
when _T_1221 :
connect ldst_addr_matches[0][4], UInt<1>(0h1)
connect ldst_forward_matches[0][4], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_36 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_36, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_36
node _T_1222 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1223 = bits(_T_1222, 4, 0)
connect s1_set_execute[_T_1223], UInt<1>(0h0)
else :
node _T_1224 = and(lcam_mask[0], write_mask_4)
node _T_1225 = neq(_T_1224, UInt<1>(0h0))
node _T_1226 = and(_T_1225, dword_addr_matches_28[0])
when _T_1226 :
connect ldst_addr_matches[0][4], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_37 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_37, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_37
node _T_1227 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1228 = bits(_T_1227, 4, 0)
connect s1_set_execute[_T_1228], UInt<1>(0h0)
else :
node _T_1229 = or(stq[4].bits.uop.is_fence, stq[4].bits.uop.is_amo)
when _T_1229 :
connect ldst_addr_matches[0][4], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_38 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_38, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_38
node _T_1230 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1231 = bits(_T_1230, 4, 0)
connect s1_set_execute[_T_1231], UInt<1>(0h0)
node _dword_addr_matches_T_126 = eq(stq[5].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_127 = and(stq[5].bits.addr.valid, _dword_addr_matches_T_126)
node _dword_addr_matches_T_128 = bits(stq[5].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_129 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_130 = eq(_dword_addr_matches_T_128, _dword_addr_matches_T_129)
node _dword_addr_matches_T_131 = and(_dword_addr_matches_T_127, _dword_addr_matches_T_130)
wire dword_addr_matches_29 : UInt<1>[1]
connect dword_addr_matches_29[0], _dword_addr_matches_T_131
wire write_mask_5 : UInt<8>
node _write_mask_mask_T_75 = eq(stq[5].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_76 = bits(stq[5].bits.addr.bits, 2, 0)
node _write_mask_mask_T_77 = dshl(UInt<8>(0h1), _write_mask_mask_T_76)
node _write_mask_mask_T_78 = eq(stq[5].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_79 = bits(stq[5].bits.addr.bits, 2, 1)
node _write_mask_mask_T_80 = dshl(_write_mask_mask_T_79, UInt<1>(0h1))
node _write_mask_mask_T_81 = dshl(UInt<8>(0h3), _write_mask_mask_T_80)
node _write_mask_mask_T_82 = eq(stq[5].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_83 = bits(stq[5].bits.addr.bits, 2, 2)
node _write_mask_mask_T_84 = mux(_write_mask_mask_T_83, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_85 = eq(stq[5].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_86 = mux(_write_mask_mask_T_85, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_87 = mux(_write_mask_mask_T_82, _write_mask_mask_T_84, _write_mask_mask_T_86)
node _write_mask_mask_T_88 = mux(_write_mask_mask_T_78, _write_mask_mask_T_81, _write_mask_mask_T_87)
node _write_mask_mask_T_89 = mux(_write_mask_mask_T_75, _write_mask_mask_T_77, _write_mask_mask_T_88)
connect write_mask_5, _write_mask_mask_T_89
node _T_1232 = and(do_ld_search[0], stq[5].valid)
node _T_1233 = bits(lcam_st_dep_mask[0], 5, 5)
node _T_1234 = and(_T_1232, _T_1233)
when _T_1234 :
node _T_1235 = and(lcam_mask[0], write_mask_5)
node _T_1236 = eq(_T_1235, lcam_mask[0])
node _T_1237 = eq(stq[5].bits.uop.is_fence, UInt<1>(0h0))
node _T_1238 = and(_T_1236, _T_1237)
node _T_1239 = eq(stq[5].bits.uop.is_amo, UInt<1>(0h0))
node _T_1240 = and(_T_1238, _T_1239)
node _T_1241 = and(_T_1240, dword_addr_matches_29[0])
node _T_1242 = and(_T_1241, can_forward[0])
when _T_1242 :
connect ldst_addr_matches[0][5], UInt<1>(0h1)
connect ldst_forward_matches[0][5], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_39 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_39, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_39
node _T_1243 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1244 = bits(_T_1243, 4, 0)
connect s1_set_execute[_T_1244], UInt<1>(0h0)
else :
node _T_1245 = and(lcam_mask[0], write_mask_5)
node _T_1246 = neq(_T_1245, UInt<1>(0h0))
node _T_1247 = and(_T_1246, dword_addr_matches_29[0])
when _T_1247 :
connect ldst_addr_matches[0][5], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_40 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_40, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_40
node _T_1248 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1249 = bits(_T_1248, 4, 0)
connect s1_set_execute[_T_1249], UInt<1>(0h0)
else :
node _T_1250 = or(stq[5].bits.uop.is_fence, stq[5].bits.uop.is_amo)
when _T_1250 :
connect ldst_addr_matches[0][5], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_41 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_41, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_41
node _T_1251 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1252 = bits(_T_1251, 4, 0)
connect s1_set_execute[_T_1252], UInt<1>(0h0)
node _dword_addr_matches_T_132 = eq(stq[6].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_133 = and(stq[6].bits.addr.valid, _dword_addr_matches_T_132)
node _dword_addr_matches_T_134 = bits(stq[6].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_135 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_136 = eq(_dword_addr_matches_T_134, _dword_addr_matches_T_135)
node _dword_addr_matches_T_137 = and(_dword_addr_matches_T_133, _dword_addr_matches_T_136)
wire dword_addr_matches_30 : UInt<1>[1]
connect dword_addr_matches_30[0], _dword_addr_matches_T_137
wire write_mask_6 : UInt<8>
node _write_mask_mask_T_90 = eq(stq[6].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_91 = bits(stq[6].bits.addr.bits, 2, 0)
node _write_mask_mask_T_92 = dshl(UInt<8>(0h1), _write_mask_mask_T_91)
node _write_mask_mask_T_93 = eq(stq[6].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_94 = bits(stq[6].bits.addr.bits, 2, 1)
node _write_mask_mask_T_95 = dshl(_write_mask_mask_T_94, UInt<1>(0h1))
node _write_mask_mask_T_96 = dshl(UInt<8>(0h3), _write_mask_mask_T_95)
node _write_mask_mask_T_97 = eq(stq[6].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_98 = bits(stq[6].bits.addr.bits, 2, 2)
node _write_mask_mask_T_99 = mux(_write_mask_mask_T_98, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_100 = eq(stq[6].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_101 = mux(_write_mask_mask_T_100, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_102 = mux(_write_mask_mask_T_97, _write_mask_mask_T_99, _write_mask_mask_T_101)
node _write_mask_mask_T_103 = mux(_write_mask_mask_T_93, _write_mask_mask_T_96, _write_mask_mask_T_102)
node _write_mask_mask_T_104 = mux(_write_mask_mask_T_90, _write_mask_mask_T_92, _write_mask_mask_T_103)
connect write_mask_6, _write_mask_mask_T_104
node _T_1253 = and(do_ld_search[0], stq[6].valid)
node _T_1254 = bits(lcam_st_dep_mask[0], 6, 6)
node _T_1255 = and(_T_1253, _T_1254)
when _T_1255 :
node _T_1256 = and(lcam_mask[0], write_mask_6)
node _T_1257 = eq(_T_1256, lcam_mask[0])
node _T_1258 = eq(stq[6].bits.uop.is_fence, UInt<1>(0h0))
node _T_1259 = and(_T_1257, _T_1258)
node _T_1260 = eq(stq[6].bits.uop.is_amo, UInt<1>(0h0))
node _T_1261 = and(_T_1259, _T_1260)
node _T_1262 = and(_T_1261, dword_addr_matches_30[0])
node _T_1263 = and(_T_1262, can_forward[0])
when _T_1263 :
connect ldst_addr_matches[0][6], UInt<1>(0h1)
connect ldst_forward_matches[0][6], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_42 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_42, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_42
node _T_1264 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1265 = bits(_T_1264, 4, 0)
connect s1_set_execute[_T_1265], UInt<1>(0h0)
else :
node _T_1266 = and(lcam_mask[0], write_mask_6)
node _T_1267 = neq(_T_1266, UInt<1>(0h0))
node _T_1268 = and(_T_1267, dword_addr_matches_30[0])
when _T_1268 :
connect ldst_addr_matches[0][6], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_43 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_43, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_43
node _T_1269 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1270 = bits(_T_1269, 4, 0)
connect s1_set_execute[_T_1270], UInt<1>(0h0)
else :
node _T_1271 = or(stq[6].bits.uop.is_fence, stq[6].bits.uop.is_amo)
when _T_1271 :
connect ldst_addr_matches[0][6], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_44 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_44, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_44
node _T_1272 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1273 = bits(_T_1272, 4, 0)
connect s1_set_execute[_T_1273], UInt<1>(0h0)
node _dword_addr_matches_T_138 = eq(stq[7].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_139 = and(stq[7].bits.addr.valid, _dword_addr_matches_T_138)
node _dword_addr_matches_T_140 = bits(stq[7].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_141 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_142 = eq(_dword_addr_matches_T_140, _dword_addr_matches_T_141)
node _dword_addr_matches_T_143 = and(_dword_addr_matches_T_139, _dword_addr_matches_T_142)
wire dword_addr_matches_31 : UInt<1>[1]
connect dword_addr_matches_31[0], _dword_addr_matches_T_143
wire write_mask_7 : UInt<8>
node _write_mask_mask_T_105 = eq(stq[7].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_106 = bits(stq[7].bits.addr.bits, 2, 0)
node _write_mask_mask_T_107 = dshl(UInt<8>(0h1), _write_mask_mask_T_106)
node _write_mask_mask_T_108 = eq(stq[7].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_109 = bits(stq[7].bits.addr.bits, 2, 1)
node _write_mask_mask_T_110 = dshl(_write_mask_mask_T_109, UInt<1>(0h1))
node _write_mask_mask_T_111 = dshl(UInt<8>(0h3), _write_mask_mask_T_110)
node _write_mask_mask_T_112 = eq(stq[7].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_113 = bits(stq[7].bits.addr.bits, 2, 2)
node _write_mask_mask_T_114 = mux(_write_mask_mask_T_113, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_115 = eq(stq[7].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_116 = mux(_write_mask_mask_T_115, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_117 = mux(_write_mask_mask_T_112, _write_mask_mask_T_114, _write_mask_mask_T_116)
node _write_mask_mask_T_118 = mux(_write_mask_mask_T_108, _write_mask_mask_T_111, _write_mask_mask_T_117)
node _write_mask_mask_T_119 = mux(_write_mask_mask_T_105, _write_mask_mask_T_107, _write_mask_mask_T_118)
connect write_mask_7, _write_mask_mask_T_119
node _T_1274 = and(do_ld_search[0], stq[7].valid)
node _T_1275 = bits(lcam_st_dep_mask[0], 7, 7)
node _T_1276 = and(_T_1274, _T_1275)
when _T_1276 :
node _T_1277 = and(lcam_mask[0], write_mask_7)
node _T_1278 = eq(_T_1277, lcam_mask[0])
node _T_1279 = eq(stq[7].bits.uop.is_fence, UInt<1>(0h0))
node _T_1280 = and(_T_1278, _T_1279)
node _T_1281 = eq(stq[7].bits.uop.is_amo, UInt<1>(0h0))
node _T_1282 = and(_T_1280, _T_1281)
node _T_1283 = and(_T_1282, dword_addr_matches_31[0])
node _T_1284 = and(_T_1283, can_forward[0])
when _T_1284 :
connect ldst_addr_matches[0][7], UInt<1>(0h1)
connect ldst_forward_matches[0][7], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_45 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_45, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_45
node _T_1285 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1286 = bits(_T_1285, 4, 0)
connect s1_set_execute[_T_1286], UInt<1>(0h0)
else :
node _T_1287 = and(lcam_mask[0], write_mask_7)
node _T_1288 = neq(_T_1287, UInt<1>(0h0))
node _T_1289 = and(_T_1288, dword_addr_matches_31[0])
when _T_1289 :
connect ldst_addr_matches[0][7], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_46 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_46, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_46
node _T_1290 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1291 = bits(_T_1290, 4, 0)
connect s1_set_execute[_T_1291], UInt<1>(0h0)
else :
node _T_1292 = or(stq[7].bits.uop.is_fence, stq[7].bits.uop.is_amo)
when _T_1292 :
connect ldst_addr_matches[0][7], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_47 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_47, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_47
node _T_1293 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1294 = bits(_T_1293, 4, 0)
connect s1_set_execute[_T_1294], UInt<1>(0h0)
node _dword_addr_matches_T_144 = eq(stq[8].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_145 = and(stq[8].bits.addr.valid, _dword_addr_matches_T_144)
node _dword_addr_matches_T_146 = bits(stq[8].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_147 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_148 = eq(_dword_addr_matches_T_146, _dword_addr_matches_T_147)
node _dword_addr_matches_T_149 = and(_dword_addr_matches_T_145, _dword_addr_matches_T_148)
wire dword_addr_matches_32 : UInt<1>[1]
connect dword_addr_matches_32[0], _dword_addr_matches_T_149
wire write_mask_8 : UInt<8>
node _write_mask_mask_T_120 = eq(stq[8].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_121 = bits(stq[8].bits.addr.bits, 2, 0)
node _write_mask_mask_T_122 = dshl(UInt<8>(0h1), _write_mask_mask_T_121)
node _write_mask_mask_T_123 = eq(stq[8].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_124 = bits(stq[8].bits.addr.bits, 2, 1)
node _write_mask_mask_T_125 = dshl(_write_mask_mask_T_124, UInt<1>(0h1))
node _write_mask_mask_T_126 = dshl(UInt<8>(0h3), _write_mask_mask_T_125)
node _write_mask_mask_T_127 = eq(stq[8].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_128 = bits(stq[8].bits.addr.bits, 2, 2)
node _write_mask_mask_T_129 = mux(_write_mask_mask_T_128, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_130 = eq(stq[8].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_131 = mux(_write_mask_mask_T_130, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_132 = mux(_write_mask_mask_T_127, _write_mask_mask_T_129, _write_mask_mask_T_131)
node _write_mask_mask_T_133 = mux(_write_mask_mask_T_123, _write_mask_mask_T_126, _write_mask_mask_T_132)
node _write_mask_mask_T_134 = mux(_write_mask_mask_T_120, _write_mask_mask_T_122, _write_mask_mask_T_133)
connect write_mask_8, _write_mask_mask_T_134
node _T_1295 = and(do_ld_search[0], stq[8].valid)
node _T_1296 = bits(lcam_st_dep_mask[0], 8, 8)
node _T_1297 = and(_T_1295, _T_1296)
when _T_1297 :
node _T_1298 = and(lcam_mask[0], write_mask_8)
node _T_1299 = eq(_T_1298, lcam_mask[0])
node _T_1300 = eq(stq[8].bits.uop.is_fence, UInt<1>(0h0))
node _T_1301 = and(_T_1299, _T_1300)
node _T_1302 = eq(stq[8].bits.uop.is_amo, UInt<1>(0h0))
node _T_1303 = and(_T_1301, _T_1302)
node _T_1304 = and(_T_1303, dword_addr_matches_32[0])
node _T_1305 = and(_T_1304, can_forward[0])
when _T_1305 :
connect ldst_addr_matches[0][8], UInt<1>(0h1)
connect ldst_forward_matches[0][8], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_48 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_48, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_48
node _T_1306 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1307 = bits(_T_1306, 4, 0)
connect s1_set_execute[_T_1307], UInt<1>(0h0)
else :
node _T_1308 = and(lcam_mask[0], write_mask_8)
node _T_1309 = neq(_T_1308, UInt<1>(0h0))
node _T_1310 = and(_T_1309, dword_addr_matches_32[0])
when _T_1310 :
connect ldst_addr_matches[0][8], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_49 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_49, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_49
node _T_1311 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1312 = bits(_T_1311, 4, 0)
connect s1_set_execute[_T_1312], UInt<1>(0h0)
else :
node _T_1313 = or(stq[8].bits.uop.is_fence, stq[8].bits.uop.is_amo)
when _T_1313 :
connect ldst_addr_matches[0][8], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_50 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_50, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_50
node _T_1314 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1315 = bits(_T_1314, 4, 0)
connect s1_set_execute[_T_1315], UInt<1>(0h0)
node _dword_addr_matches_T_150 = eq(stq[9].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_151 = and(stq[9].bits.addr.valid, _dword_addr_matches_T_150)
node _dword_addr_matches_T_152 = bits(stq[9].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_153 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_154 = eq(_dword_addr_matches_T_152, _dword_addr_matches_T_153)
node _dword_addr_matches_T_155 = and(_dword_addr_matches_T_151, _dword_addr_matches_T_154)
wire dword_addr_matches_33 : UInt<1>[1]
connect dword_addr_matches_33[0], _dword_addr_matches_T_155
wire write_mask_9 : UInt<8>
node _write_mask_mask_T_135 = eq(stq[9].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_136 = bits(stq[9].bits.addr.bits, 2, 0)
node _write_mask_mask_T_137 = dshl(UInt<8>(0h1), _write_mask_mask_T_136)
node _write_mask_mask_T_138 = eq(stq[9].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_139 = bits(stq[9].bits.addr.bits, 2, 1)
node _write_mask_mask_T_140 = dshl(_write_mask_mask_T_139, UInt<1>(0h1))
node _write_mask_mask_T_141 = dshl(UInt<8>(0h3), _write_mask_mask_T_140)
node _write_mask_mask_T_142 = eq(stq[9].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_143 = bits(stq[9].bits.addr.bits, 2, 2)
node _write_mask_mask_T_144 = mux(_write_mask_mask_T_143, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_145 = eq(stq[9].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_146 = mux(_write_mask_mask_T_145, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_147 = mux(_write_mask_mask_T_142, _write_mask_mask_T_144, _write_mask_mask_T_146)
node _write_mask_mask_T_148 = mux(_write_mask_mask_T_138, _write_mask_mask_T_141, _write_mask_mask_T_147)
node _write_mask_mask_T_149 = mux(_write_mask_mask_T_135, _write_mask_mask_T_137, _write_mask_mask_T_148)
connect write_mask_9, _write_mask_mask_T_149
node _T_1316 = and(do_ld_search[0], stq[9].valid)
node _T_1317 = bits(lcam_st_dep_mask[0], 9, 9)
node _T_1318 = and(_T_1316, _T_1317)
when _T_1318 :
node _T_1319 = and(lcam_mask[0], write_mask_9)
node _T_1320 = eq(_T_1319, lcam_mask[0])
node _T_1321 = eq(stq[9].bits.uop.is_fence, UInt<1>(0h0))
node _T_1322 = and(_T_1320, _T_1321)
node _T_1323 = eq(stq[9].bits.uop.is_amo, UInt<1>(0h0))
node _T_1324 = and(_T_1322, _T_1323)
node _T_1325 = and(_T_1324, dword_addr_matches_33[0])
node _T_1326 = and(_T_1325, can_forward[0])
when _T_1326 :
connect ldst_addr_matches[0][9], UInt<1>(0h1)
connect ldst_forward_matches[0][9], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_51 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_51, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_51
node _T_1327 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1328 = bits(_T_1327, 4, 0)
connect s1_set_execute[_T_1328], UInt<1>(0h0)
else :
node _T_1329 = and(lcam_mask[0], write_mask_9)
node _T_1330 = neq(_T_1329, UInt<1>(0h0))
node _T_1331 = and(_T_1330, dword_addr_matches_33[0])
when _T_1331 :
connect ldst_addr_matches[0][9], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_52 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_52, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_52
node _T_1332 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1333 = bits(_T_1332, 4, 0)
connect s1_set_execute[_T_1333], UInt<1>(0h0)
else :
node _T_1334 = or(stq[9].bits.uop.is_fence, stq[9].bits.uop.is_amo)
when _T_1334 :
connect ldst_addr_matches[0][9], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_53 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_53, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_53
node _T_1335 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1336 = bits(_T_1335, 4, 0)
connect s1_set_execute[_T_1336], UInt<1>(0h0)
node _dword_addr_matches_T_156 = eq(stq[10].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_157 = and(stq[10].bits.addr.valid, _dword_addr_matches_T_156)
node _dword_addr_matches_T_158 = bits(stq[10].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_159 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_160 = eq(_dword_addr_matches_T_158, _dword_addr_matches_T_159)
node _dword_addr_matches_T_161 = and(_dword_addr_matches_T_157, _dword_addr_matches_T_160)
wire dword_addr_matches_34 : UInt<1>[1]
connect dword_addr_matches_34[0], _dword_addr_matches_T_161
wire write_mask_10 : UInt<8>
node _write_mask_mask_T_150 = eq(stq[10].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_151 = bits(stq[10].bits.addr.bits, 2, 0)
node _write_mask_mask_T_152 = dshl(UInt<8>(0h1), _write_mask_mask_T_151)
node _write_mask_mask_T_153 = eq(stq[10].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_154 = bits(stq[10].bits.addr.bits, 2, 1)
node _write_mask_mask_T_155 = dshl(_write_mask_mask_T_154, UInt<1>(0h1))
node _write_mask_mask_T_156 = dshl(UInt<8>(0h3), _write_mask_mask_T_155)
node _write_mask_mask_T_157 = eq(stq[10].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_158 = bits(stq[10].bits.addr.bits, 2, 2)
node _write_mask_mask_T_159 = mux(_write_mask_mask_T_158, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_160 = eq(stq[10].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_161 = mux(_write_mask_mask_T_160, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_162 = mux(_write_mask_mask_T_157, _write_mask_mask_T_159, _write_mask_mask_T_161)
node _write_mask_mask_T_163 = mux(_write_mask_mask_T_153, _write_mask_mask_T_156, _write_mask_mask_T_162)
node _write_mask_mask_T_164 = mux(_write_mask_mask_T_150, _write_mask_mask_T_152, _write_mask_mask_T_163)
connect write_mask_10, _write_mask_mask_T_164
node _T_1337 = and(do_ld_search[0], stq[10].valid)
node _T_1338 = bits(lcam_st_dep_mask[0], 10, 10)
node _T_1339 = and(_T_1337, _T_1338)
when _T_1339 :
node _T_1340 = and(lcam_mask[0], write_mask_10)
node _T_1341 = eq(_T_1340, lcam_mask[0])
node _T_1342 = eq(stq[10].bits.uop.is_fence, UInt<1>(0h0))
node _T_1343 = and(_T_1341, _T_1342)
node _T_1344 = eq(stq[10].bits.uop.is_amo, UInt<1>(0h0))
node _T_1345 = and(_T_1343, _T_1344)
node _T_1346 = and(_T_1345, dword_addr_matches_34[0])
node _T_1347 = and(_T_1346, can_forward[0])
when _T_1347 :
connect ldst_addr_matches[0][10], UInt<1>(0h1)
connect ldst_forward_matches[0][10], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_54 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_54, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_54
node _T_1348 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1349 = bits(_T_1348, 4, 0)
connect s1_set_execute[_T_1349], UInt<1>(0h0)
else :
node _T_1350 = and(lcam_mask[0], write_mask_10)
node _T_1351 = neq(_T_1350, UInt<1>(0h0))
node _T_1352 = and(_T_1351, dword_addr_matches_34[0])
when _T_1352 :
connect ldst_addr_matches[0][10], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_55 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_55, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_55
node _T_1353 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1354 = bits(_T_1353, 4, 0)
connect s1_set_execute[_T_1354], UInt<1>(0h0)
else :
node _T_1355 = or(stq[10].bits.uop.is_fence, stq[10].bits.uop.is_amo)
when _T_1355 :
connect ldst_addr_matches[0][10], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_56 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_56, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_56
node _T_1356 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1357 = bits(_T_1356, 4, 0)
connect s1_set_execute[_T_1357], UInt<1>(0h0)
node _dword_addr_matches_T_162 = eq(stq[11].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_163 = and(stq[11].bits.addr.valid, _dword_addr_matches_T_162)
node _dword_addr_matches_T_164 = bits(stq[11].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_165 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_166 = eq(_dword_addr_matches_T_164, _dword_addr_matches_T_165)
node _dword_addr_matches_T_167 = and(_dword_addr_matches_T_163, _dword_addr_matches_T_166)
wire dword_addr_matches_35 : UInt<1>[1]
connect dword_addr_matches_35[0], _dword_addr_matches_T_167
wire write_mask_11 : UInt<8>
node _write_mask_mask_T_165 = eq(stq[11].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_166 = bits(stq[11].bits.addr.bits, 2, 0)
node _write_mask_mask_T_167 = dshl(UInt<8>(0h1), _write_mask_mask_T_166)
node _write_mask_mask_T_168 = eq(stq[11].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_169 = bits(stq[11].bits.addr.bits, 2, 1)
node _write_mask_mask_T_170 = dshl(_write_mask_mask_T_169, UInt<1>(0h1))
node _write_mask_mask_T_171 = dshl(UInt<8>(0h3), _write_mask_mask_T_170)
node _write_mask_mask_T_172 = eq(stq[11].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_173 = bits(stq[11].bits.addr.bits, 2, 2)
node _write_mask_mask_T_174 = mux(_write_mask_mask_T_173, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_175 = eq(stq[11].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_176 = mux(_write_mask_mask_T_175, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_177 = mux(_write_mask_mask_T_172, _write_mask_mask_T_174, _write_mask_mask_T_176)
node _write_mask_mask_T_178 = mux(_write_mask_mask_T_168, _write_mask_mask_T_171, _write_mask_mask_T_177)
node _write_mask_mask_T_179 = mux(_write_mask_mask_T_165, _write_mask_mask_T_167, _write_mask_mask_T_178)
connect write_mask_11, _write_mask_mask_T_179
node _T_1358 = and(do_ld_search[0], stq[11].valid)
node _T_1359 = bits(lcam_st_dep_mask[0], 11, 11)
node _T_1360 = and(_T_1358, _T_1359)
when _T_1360 :
node _T_1361 = and(lcam_mask[0], write_mask_11)
node _T_1362 = eq(_T_1361, lcam_mask[0])
node _T_1363 = eq(stq[11].bits.uop.is_fence, UInt<1>(0h0))
node _T_1364 = and(_T_1362, _T_1363)
node _T_1365 = eq(stq[11].bits.uop.is_amo, UInt<1>(0h0))
node _T_1366 = and(_T_1364, _T_1365)
node _T_1367 = and(_T_1366, dword_addr_matches_35[0])
node _T_1368 = and(_T_1367, can_forward[0])
when _T_1368 :
connect ldst_addr_matches[0][11], UInt<1>(0h1)
connect ldst_forward_matches[0][11], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_57 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_57, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_57
node _T_1369 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1370 = bits(_T_1369, 4, 0)
connect s1_set_execute[_T_1370], UInt<1>(0h0)
else :
node _T_1371 = and(lcam_mask[0], write_mask_11)
node _T_1372 = neq(_T_1371, UInt<1>(0h0))
node _T_1373 = and(_T_1372, dword_addr_matches_35[0])
when _T_1373 :
connect ldst_addr_matches[0][11], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_58 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_58, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_58
node _T_1374 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1375 = bits(_T_1374, 4, 0)
connect s1_set_execute[_T_1375], UInt<1>(0h0)
else :
node _T_1376 = or(stq[11].bits.uop.is_fence, stq[11].bits.uop.is_amo)
when _T_1376 :
connect ldst_addr_matches[0][11], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_59 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_59, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_59
node _T_1377 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1378 = bits(_T_1377, 4, 0)
connect s1_set_execute[_T_1378], UInt<1>(0h0)
node _dword_addr_matches_T_168 = eq(stq[12].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_169 = and(stq[12].bits.addr.valid, _dword_addr_matches_T_168)
node _dword_addr_matches_T_170 = bits(stq[12].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_171 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_172 = eq(_dword_addr_matches_T_170, _dword_addr_matches_T_171)
node _dword_addr_matches_T_173 = and(_dword_addr_matches_T_169, _dword_addr_matches_T_172)
wire dword_addr_matches_36 : UInt<1>[1]
connect dword_addr_matches_36[0], _dword_addr_matches_T_173
wire write_mask_12 : UInt<8>
node _write_mask_mask_T_180 = eq(stq[12].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_181 = bits(stq[12].bits.addr.bits, 2, 0)
node _write_mask_mask_T_182 = dshl(UInt<8>(0h1), _write_mask_mask_T_181)
node _write_mask_mask_T_183 = eq(stq[12].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_184 = bits(stq[12].bits.addr.bits, 2, 1)
node _write_mask_mask_T_185 = dshl(_write_mask_mask_T_184, UInt<1>(0h1))
node _write_mask_mask_T_186 = dshl(UInt<8>(0h3), _write_mask_mask_T_185)
node _write_mask_mask_T_187 = eq(stq[12].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_188 = bits(stq[12].bits.addr.bits, 2, 2)
node _write_mask_mask_T_189 = mux(_write_mask_mask_T_188, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_190 = eq(stq[12].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_191 = mux(_write_mask_mask_T_190, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_192 = mux(_write_mask_mask_T_187, _write_mask_mask_T_189, _write_mask_mask_T_191)
node _write_mask_mask_T_193 = mux(_write_mask_mask_T_183, _write_mask_mask_T_186, _write_mask_mask_T_192)
node _write_mask_mask_T_194 = mux(_write_mask_mask_T_180, _write_mask_mask_T_182, _write_mask_mask_T_193)
connect write_mask_12, _write_mask_mask_T_194
node _T_1379 = and(do_ld_search[0], stq[12].valid)
node _T_1380 = bits(lcam_st_dep_mask[0], 12, 12)
node _T_1381 = and(_T_1379, _T_1380)
when _T_1381 :
node _T_1382 = and(lcam_mask[0], write_mask_12)
node _T_1383 = eq(_T_1382, lcam_mask[0])
node _T_1384 = eq(stq[12].bits.uop.is_fence, UInt<1>(0h0))
node _T_1385 = and(_T_1383, _T_1384)
node _T_1386 = eq(stq[12].bits.uop.is_amo, UInt<1>(0h0))
node _T_1387 = and(_T_1385, _T_1386)
node _T_1388 = and(_T_1387, dword_addr_matches_36[0])
node _T_1389 = and(_T_1388, can_forward[0])
when _T_1389 :
connect ldst_addr_matches[0][12], UInt<1>(0h1)
connect ldst_forward_matches[0][12], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_60 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_60, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_60
node _T_1390 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1391 = bits(_T_1390, 4, 0)
connect s1_set_execute[_T_1391], UInt<1>(0h0)
else :
node _T_1392 = and(lcam_mask[0], write_mask_12)
node _T_1393 = neq(_T_1392, UInt<1>(0h0))
node _T_1394 = and(_T_1393, dword_addr_matches_36[0])
when _T_1394 :
connect ldst_addr_matches[0][12], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_61 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_61, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_61
node _T_1395 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1396 = bits(_T_1395, 4, 0)
connect s1_set_execute[_T_1396], UInt<1>(0h0)
else :
node _T_1397 = or(stq[12].bits.uop.is_fence, stq[12].bits.uop.is_amo)
when _T_1397 :
connect ldst_addr_matches[0][12], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_62 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_62, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_62
node _T_1398 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1399 = bits(_T_1398, 4, 0)
connect s1_set_execute[_T_1399], UInt<1>(0h0)
node _dword_addr_matches_T_174 = eq(stq[13].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_175 = and(stq[13].bits.addr.valid, _dword_addr_matches_T_174)
node _dword_addr_matches_T_176 = bits(stq[13].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_177 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_178 = eq(_dword_addr_matches_T_176, _dword_addr_matches_T_177)
node _dword_addr_matches_T_179 = and(_dword_addr_matches_T_175, _dword_addr_matches_T_178)
wire dword_addr_matches_37 : UInt<1>[1]
connect dword_addr_matches_37[0], _dword_addr_matches_T_179
wire write_mask_13 : UInt<8>
node _write_mask_mask_T_195 = eq(stq[13].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_196 = bits(stq[13].bits.addr.bits, 2, 0)
node _write_mask_mask_T_197 = dshl(UInt<8>(0h1), _write_mask_mask_T_196)
node _write_mask_mask_T_198 = eq(stq[13].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_199 = bits(stq[13].bits.addr.bits, 2, 1)
node _write_mask_mask_T_200 = dshl(_write_mask_mask_T_199, UInt<1>(0h1))
node _write_mask_mask_T_201 = dshl(UInt<8>(0h3), _write_mask_mask_T_200)
node _write_mask_mask_T_202 = eq(stq[13].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_203 = bits(stq[13].bits.addr.bits, 2, 2)
node _write_mask_mask_T_204 = mux(_write_mask_mask_T_203, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_205 = eq(stq[13].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_206 = mux(_write_mask_mask_T_205, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_207 = mux(_write_mask_mask_T_202, _write_mask_mask_T_204, _write_mask_mask_T_206)
node _write_mask_mask_T_208 = mux(_write_mask_mask_T_198, _write_mask_mask_T_201, _write_mask_mask_T_207)
node _write_mask_mask_T_209 = mux(_write_mask_mask_T_195, _write_mask_mask_T_197, _write_mask_mask_T_208)
connect write_mask_13, _write_mask_mask_T_209
node _T_1400 = and(do_ld_search[0], stq[13].valid)
node _T_1401 = bits(lcam_st_dep_mask[0], 13, 13)
node _T_1402 = and(_T_1400, _T_1401)
when _T_1402 :
node _T_1403 = and(lcam_mask[0], write_mask_13)
node _T_1404 = eq(_T_1403, lcam_mask[0])
node _T_1405 = eq(stq[13].bits.uop.is_fence, UInt<1>(0h0))
node _T_1406 = and(_T_1404, _T_1405)
node _T_1407 = eq(stq[13].bits.uop.is_amo, UInt<1>(0h0))
node _T_1408 = and(_T_1406, _T_1407)
node _T_1409 = and(_T_1408, dword_addr_matches_37[0])
node _T_1410 = and(_T_1409, can_forward[0])
when _T_1410 :
connect ldst_addr_matches[0][13], UInt<1>(0h1)
connect ldst_forward_matches[0][13], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_63 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_63, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_63
node _T_1411 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1412 = bits(_T_1411, 4, 0)
connect s1_set_execute[_T_1412], UInt<1>(0h0)
else :
node _T_1413 = and(lcam_mask[0], write_mask_13)
node _T_1414 = neq(_T_1413, UInt<1>(0h0))
node _T_1415 = and(_T_1414, dword_addr_matches_37[0])
when _T_1415 :
connect ldst_addr_matches[0][13], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_64 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_64, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_64
node _T_1416 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1417 = bits(_T_1416, 4, 0)
connect s1_set_execute[_T_1417], UInt<1>(0h0)
else :
node _T_1418 = or(stq[13].bits.uop.is_fence, stq[13].bits.uop.is_amo)
when _T_1418 :
connect ldst_addr_matches[0][13], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_65 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_65, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_65
node _T_1419 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1420 = bits(_T_1419, 4, 0)
connect s1_set_execute[_T_1420], UInt<1>(0h0)
node _dword_addr_matches_T_180 = eq(stq[14].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_181 = and(stq[14].bits.addr.valid, _dword_addr_matches_T_180)
node _dword_addr_matches_T_182 = bits(stq[14].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_183 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_184 = eq(_dword_addr_matches_T_182, _dword_addr_matches_T_183)
node _dword_addr_matches_T_185 = and(_dword_addr_matches_T_181, _dword_addr_matches_T_184)
wire dword_addr_matches_38 : UInt<1>[1]
connect dword_addr_matches_38[0], _dword_addr_matches_T_185
wire write_mask_14 : UInt<8>
node _write_mask_mask_T_210 = eq(stq[14].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_211 = bits(stq[14].bits.addr.bits, 2, 0)
node _write_mask_mask_T_212 = dshl(UInt<8>(0h1), _write_mask_mask_T_211)
node _write_mask_mask_T_213 = eq(stq[14].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_214 = bits(stq[14].bits.addr.bits, 2, 1)
node _write_mask_mask_T_215 = dshl(_write_mask_mask_T_214, UInt<1>(0h1))
node _write_mask_mask_T_216 = dshl(UInt<8>(0h3), _write_mask_mask_T_215)
node _write_mask_mask_T_217 = eq(stq[14].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_218 = bits(stq[14].bits.addr.bits, 2, 2)
node _write_mask_mask_T_219 = mux(_write_mask_mask_T_218, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_220 = eq(stq[14].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_221 = mux(_write_mask_mask_T_220, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_222 = mux(_write_mask_mask_T_217, _write_mask_mask_T_219, _write_mask_mask_T_221)
node _write_mask_mask_T_223 = mux(_write_mask_mask_T_213, _write_mask_mask_T_216, _write_mask_mask_T_222)
node _write_mask_mask_T_224 = mux(_write_mask_mask_T_210, _write_mask_mask_T_212, _write_mask_mask_T_223)
connect write_mask_14, _write_mask_mask_T_224
node _T_1421 = and(do_ld_search[0], stq[14].valid)
node _T_1422 = bits(lcam_st_dep_mask[0], 14, 14)
node _T_1423 = and(_T_1421, _T_1422)
when _T_1423 :
node _T_1424 = and(lcam_mask[0], write_mask_14)
node _T_1425 = eq(_T_1424, lcam_mask[0])
node _T_1426 = eq(stq[14].bits.uop.is_fence, UInt<1>(0h0))
node _T_1427 = and(_T_1425, _T_1426)
node _T_1428 = eq(stq[14].bits.uop.is_amo, UInt<1>(0h0))
node _T_1429 = and(_T_1427, _T_1428)
node _T_1430 = and(_T_1429, dword_addr_matches_38[0])
node _T_1431 = and(_T_1430, can_forward[0])
when _T_1431 :
connect ldst_addr_matches[0][14], UInt<1>(0h1)
connect ldst_forward_matches[0][14], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_66 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_66, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_66
node _T_1432 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1433 = bits(_T_1432, 4, 0)
connect s1_set_execute[_T_1433], UInt<1>(0h0)
else :
node _T_1434 = and(lcam_mask[0], write_mask_14)
node _T_1435 = neq(_T_1434, UInt<1>(0h0))
node _T_1436 = and(_T_1435, dword_addr_matches_38[0])
when _T_1436 :
connect ldst_addr_matches[0][14], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_67 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_67, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_67
node _T_1437 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1438 = bits(_T_1437, 4, 0)
connect s1_set_execute[_T_1438], UInt<1>(0h0)
else :
node _T_1439 = or(stq[14].bits.uop.is_fence, stq[14].bits.uop.is_amo)
when _T_1439 :
connect ldst_addr_matches[0][14], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_68 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_68, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_68
node _T_1440 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1441 = bits(_T_1440, 4, 0)
connect s1_set_execute[_T_1441], UInt<1>(0h0)
node _dword_addr_matches_T_186 = eq(stq[15].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_187 = and(stq[15].bits.addr.valid, _dword_addr_matches_T_186)
node _dword_addr_matches_T_188 = bits(stq[15].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_189 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_190 = eq(_dword_addr_matches_T_188, _dword_addr_matches_T_189)
node _dword_addr_matches_T_191 = and(_dword_addr_matches_T_187, _dword_addr_matches_T_190)
wire dword_addr_matches_39 : UInt<1>[1]
connect dword_addr_matches_39[0], _dword_addr_matches_T_191
wire write_mask_15 : UInt<8>
node _write_mask_mask_T_225 = eq(stq[15].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_226 = bits(stq[15].bits.addr.bits, 2, 0)
node _write_mask_mask_T_227 = dshl(UInt<8>(0h1), _write_mask_mask_T_226)
node _write_mask_mask_T_228 = eq(stq[15].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_229 = bits(stq[15].bits.addr.bits, 2, 1)
node _write_mask_mask_T_230 = dshl(_write_mask_mask_T_229, UInt<1>(0h1))
node _write_mask_mask_T_231 = dshl(UInt<8>(0h3), _write_mask_mask_T_230)
node _write_mask_mask_T_232 = eq(stq[15].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_233 = bits(stq[15].bits.addr.bits, 2, 2)
node _write_mask_mask_T_234 = mux(_write_mask_mask_T_233, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_235 = eq(stq[15].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_236 = mux(_write_mask_mask_T_235, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_237 = mux(_write_mask_mask_T_232, _write_mask_mask_T_234, _write_mask_mask_T_236)
node _write_mask_mask_T_238 = mux(_write_mask_mask_T_228, _write_mask_mask_T_231, _write_mask_mask_T_237)
node _write_mask_mask_T_239 = mux(_write_mask_mask_T_225, _write_mask_mask_T_227, _write_mask_mask_T_238)
connect write_mask_15, _write_mask_mask_T_239
node _T_1442 = and(do_ld_search[0], stq[15].valid)
node _T_1443 = bits(lcam_st_dep_mask[0], 15, 15)
node _T_1444 = and(_T_1442, _T_1443)
when _T_1444 :
node _T_1445 = and(lcam_mask[0], write_mask_15)
node _T_1446 = eq(_T_1445, lcam_mask[0])
node _T_1447 = eq(stq[15].bits.uop.is_fence, UInt<1>(0h0))
node _T_1448 = and(_T_1446, _T_1447)
node _T_1449 = eq(stq[15].bits.uop.is_amo, UInt<1>(0h0))
node _T_1450 = and(_T_1448, _T_1449)
node _T_1451 = and(_T_1450, dword_addr_matches_39[0])
node _T_1452 = and(_T_1451, can_forward[0])
when _T_1452 :
connect ldst_addr_matches[0][15], UInt<1>(0h1)
connect ldst_forward_matches[0][15], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_69 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_69, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_69
node _T_1453 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1454 = bits(_T_1453, 4, 0)
connect s1_set_execute[_T_1454], UInt<1>(0h0)
else :
node _T_1455 = and(lcam_mask[0], write_mask_15)
node _T_1456 = neq(_T_1455, UInt<1>(0h0))
node _T_1457 = and(_T_1456, dword_addr_matches_39[0])
when _T_1457 :
connect ldst_addr_matches[0][15], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_70 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_70, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_70
node _T_1458 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1459 = bits(_T_1458, 4, 0)
connect s1_set_execute[_T_1459], UInt<1>(0h0)
else :
node _T_1460 = or(stq[15].bits.uop.is_fence, stq[15].bits.uop.is_amo)
when _T_1460 :
connect ldst_addr_matches[0][15], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_71 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_71, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_71
node _T_1461 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1462 = bits(_T_1461, 4, 0)
connect s1_set_execute[_T_1462], UInt<1>(0h0)
node _dword_addr_matches_T_192 = eq(stq[16].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_193 = and(stq[16].bits.addr.valid, _dword_addr_matches_T_192)
node _dword_addr_matches_T_194 = bits(stq[16].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_195 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_196 = eq(_dword_addr_matches_T_194, _dword_addr_matches_T_195)
node _dword_addr_matches_T_197 = and(_dword_addr_matches_T_193, _dword_addr_matches_T_196)
wire dword_addr_matches_40 : UInt<1>[1]
connect dword_addr_matches_40[0], _dword_addr_matches_T_197
wire write_mask_16 : UInt<8>
node _write_mask_mask_T_240 = eq(stq[16].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_241 = bits(stq[16].bits.addr.bits, 2, 0)
node _write_mask_mask_T_242 = dshl(UInt<8>(0h1), _write_mask_mask_T_241)
node _write_mask_mask_T_243 = eq(stq[16].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_244 = bits(stq[16].bits.addr.bits, 2, 1)
node _write_mask_mask_T_245 = dshl(_write_mask_mask_T_244, UInt<1>(0h1))
node _write_mask_mask_T_246 = dshl(UInt<8>(0h3), _write_mask_mask_T_245)
node _write_mask_mask_T_247 = eq(stq[16].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_248 = bits(stq[16].bits.addr.bits, 2, 2)
node _write_mask_mask_T_249 = mux(_write_mask_mask_T_248, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_250 = eq(stq[16].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_251 = mux(_write_mask_mask_T_250, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_252 = mux(_write_mask_mask_T_247, _write_mask_mask_T_249, _write_mask_mask_T_251)
node _write_mask_mask_T_253 = mux(_write_mask_mask_T_243, _write_mask_mask_T_246, _write_mask_mask_T_252)
node _write_mask_mask_T_254 = mux(_write_mask_mask_T_240, _write_mask_mask_T_242, _write_mask_mask_T_253)
connect write_mask_16, _write_mask_mask_T_254
node _T_1463 = and(do_ld_search[0], stq[16].valid)
node _T_1464 = bits(lcam_st_dep_mask[0], 16, 16)
node _T_1465 = and(_T_1463, _T_1464)
when _T_1465 :
node _T_1466 = and(lcam_mask[0], write_mask_16)
node _T_1467 = eq(_T_1466, lcam_mask[0])
node _T_1468 = eq(stq[16].bits.uop.is_fence, UInt<1>(0h0))
node _T_1469 = and(_T_1467, _T_1468)
node _T_1470 = eq(stq[16].bits.uop.is_amo, UInt<1>(0h0))
node _T_1471 = and(_T_1469, _T_1470)
node _T_1472 = and(_T_1471, dword_addr_matches_40[0])
node _T_1473 = and(_T_1472, can_forward[0])
when _T_1473 :
connect ldst_addr_matches[0][16], UInt<1>(0h1)
connect ldst_forward_matches[0][16], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_72 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_72, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_72
node _T_1474 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1475 = bits(_T_1474, 4, 0)
connect s1_set_execute[_T_1475], UInt<1>(0h0)
else :
node _T_1476 = and(lcam_mask[0], write_mask_16)
node _T_1477 = neq(_T_1476, UInt<1>(0h0))
node _T_1478 = and(_T_1477, dword_addr_matches_40[0])
when _T_1478 :
connect ldst_addr_matches[0][16], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_73 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_73, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_73
node _T_1479 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1480 = bits(_T_1479, 4, 0)
connect s1_set_execute[_T_1480], UInt<1>(0h0)
else :
node _T_1481 = or(stq[16].bits.uop.is_fence, stq[16].bits.uop.is_amo)
when _T_1481 :
connect ldst_addr_matches[0][16], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_74 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_74, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_74
node _T_1482 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1483 = bits(_T_1482, 4, 0)
connect s1_set_execute[_T_1483], UInt<1>(0h0)
node _dword_addr_matches_T_198 = eq(stq[17].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_199 = and(stq[17].bits.addr.valid, _dword_addr_matches_T_198)
node _dword_addr_matches_T_200 = bits(stq[17].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_201 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_202 = eq(_dword_addr_matches_T_200, _dword_addr_matches_T_201)
node _dword_addr_matches_T_203 = and(_dword_addr_matches_T_199, _dword_addr_matches_T_202)
wire dword_addr_matches_41 : UInt<1>[1]
connect dword_addr_matches_41[0], _dword_addr_matches_T_203
wire write_mask_17 : UInt<8>
node _write_mask_mask_T_255 = eq(stq[17].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_256 = bits(stq[17].bits.addr.bits, 2, 0)
node _write_mask_mask_T_257 = dshl(UInt<8>(0h1), _write_mask_mask_T_256)
node _write_mask_mask_T_258 = eq(stq[17].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_259 = bits(stq[17].bits.addr.bits, 2, 1)
node _write_mask_mask_T_260 = dshl(_write_mask_mask_T_259, UInt<1>(0h1))
node _write_mask_mask_T_261 = dshl(UInt<8>(0h3), _write_mask_mask_T_260)
node _write_mask_mask_T_262 = eq(stq[17].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_263 = bits(stq[17].bits.addr.bits, 2, 2)
node _write_mask_mask_T_264 = mux(_write_mask_mask_T_263, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_265 = eq(stq[17].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_266 = mux(_write_mask_mask_T_265, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_267 = mux(_write_mask_mask_T_262, _write_mask_mask_T_264, _write_mask_mask_T_266)
node _write_mask_mask_T_268 = mux(_write_mask_mask_T_258, _write_mask_mask_T_261, _write_mask_mask_T_267)
node _write_mask_mask_T_269 = mux(_write_mask_mask_T_255, _write_mask_mask_T_257, _write_mask_mask_T_268)
connect write_mask_17, _write_mask_mask_T_269
node _T_1484 = and(do_ld_search[0], stq[17].valid)
node _T_1485 = bits(lcam_st_dep_mask[0], 17, 17)
node _T_1486 = and(_T_1484, _T_1485)
when _T_1486 :
node _T_1487 = and(lcam_mask[0], write_mask_17)
node _T_1488 = eq(_T_1487, lcam_mask[0])
node _T_1489 = eq(stq[17].bits.uop.is_fence, UInt<1>(0h0))
node _T_1490 = and(_T_1488, _T_1489)
node _T_1491 = eq(stq[17].bits.uop.is_amo, UInt<1>(0h0))
node _T_1492 = and(_T_1490, _T_1491)
node _T_1493 = and(_T_1492, dword_addr_matches_41[0])
node _T_1494 = and(_T_1493, can_forward[0])
when _T_1494 :
connect ldst_addr_matches[0][17], UInt<1>(0h1)
connect ldst_forward_matches[0][17], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_75 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_75, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_75
node _T_1495 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1496 = bits(_T_1495, 4, 0)
connect s1_set_execute[_T_1496], UInt<1>(0h0)
else :
node _T_1497 = and(lcam_mask[0], write_mask_17)
node _T_1498 = neq(_T_1497, UInt<1>(0h0))
node _T_1499 = and(_T_1498, dword_addr_matches_41[0])
when _T_1499 :
connect ldst_addr_matches[0][17], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_76 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_76, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_76
node _T_1500 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1501 = bits(_T_1500, 4, 0)
connect s1_set_execute[_T_1501], UInt<1>(0h0)
else :
node _T_1502 = or(stq[17].bits.uop.is_fence, stq[17].bits.uop.is_amo)
when _T_1502 :
connect ldst_addr_matches[0][17], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_77 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_77, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_77
node _T_1503 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1504 = bits(_T_1503, 4, 0)
connect s1_set_execute[_T_1504], UInt<1>(0h0)
node _dword_addr_matches_T_204 = eq(stq[18].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_205 = and(stq[18].bits.addr.valid, _dword_addr_matches_T_204)
node _dword_addr_matches_T_206 = bits(stq[18].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_207 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_208 = eq(_dword_addr_matches_T_206, _dword_addr_matches_T_207)
node _dword_addr_matches_T_209 = and(_dword_addr_matches_T_205, _dword_addr_matches_T_208)
wire dword_addr_matches_42 : UInt<1>[1]
connect dword_addr_matches_42[0], _dword_addr_matches_T_209
wire write_mask_18 : UInt<8>
node _write_mask_mask_T_270 = eq(stq[18].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_271 = bits(stq[18].bits.addr.bits, 2, 0)
node _write_mask_mask_T_272 = dshl(UInt<8>(0h1), _write_mask_mask_T_271)
node _write_mask_mask_T_273 = eq(stq[18].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_274 = bits(stq[18].bits.addr.bits, 2, 1)
node _write_mask_mask_T_275 = dshl(_write_mask_mask_T_274, UInt<1>(0h1))
node _write_mask_mask_T_276 = dshl(UInt<8>(0h3), _write_mask_mask_T_275)
node _write_mask_mask_T_277 = eq(stq[18].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_278 = bits(stq[18].bits.addr.bits, 2, 2)
node _write_mask_mask_T_279 = mux(_write_mask_mask_T_278, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_280 = eq(stq[18].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_281 = mux(_write_mask_mask_T_280, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_282 = mux(_write_mask_mask_T_277, _write_mask_mask_T_279, _write_mask_mask_T_281)
node _write_mask_mask_T_283 = mux(_write_mask_mask_T_273, _write_mask_mask_T_276, _write_mask_mask_T_282)
node _write_mask_mask_T_284 = mux(_write_mask_mask_T_270, _write_mask_mask_T_272, _write_mask_mask_T_283)
connect write_mask_18, _write_mask_mask_T_284
node _T_1505 = and(do_ld_search[0], stq[18].valid)
node _T_1506 = bits(lcam_st_dep_mask[0], 18, 18)
node _T_1507 = and(_T_1505, _T_1506)
when _T_1507 :
node _T_1508 = and(lcam_mask[0], write_mask_18)
node _T_1509 = eq(_T_1508, lcam_mask[0])
node _T_1510 = eq(stq[18].bits.uop.is_fence, UInt<1>(0h0))
node _T_1511 = and(_T_1509, _T_1510)
node _T_1512 = eq(stq[18].bits.uop.is_amo, UInt<1>(0h0))
node _T_1513 = and(_T_1511, _T_1512)
node _T_1514 = and(_T_1513, dword_addr_matches_42[0])
node _T_1515 = and(_T_1514, can_forward[0])
when _T_1515 :
connect ldst_addr_matches[0][18], UInt<1>(0h1)
connect ldst_forward_matches[0][18], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_78 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_78, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_78
node _T_1516 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1517 = bits(_T_1516, 4, 0)
connect s1_set_execute[_T_1517], UInt<1>(0h0)
else :
node _T_1518 = and(lcam_mask[0], write_mask_18)
node _T_1519 = neq(_T_1518, UInt<1>(0h0))
node _T_1520 = and(_T_1519, dword_addr_matches_42[0])
when _T_1520 :
connect ldst_addr_matches[0][18], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_79 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_79, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_79
node _T_1521 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1522 = bits(_T_1521, 4, 0)
connect s1_set_execute[_T_1522], UInt<1>(0h0)
else :
node _T_1523 = or(stq[18].bits.uop.is_fence, stq[18].bits.uop.is_amo)
when _T_1523 :
connect ldst_addr_matches[0][18], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_80 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_80, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_80
node _T_1524 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1525 = bits(_T_1524, 4, 0)
connect s1_set_execute[_T_1525], UInt<1>(0h0)
node _dword_addr_matches_T_210 = eq(stq[19].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_211 = and(stq[19].bits.addr.valid, _dword_addr_matches_T_210)
node _dword_addr_matches_T_212 = bits(stq[19].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_213 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_214 = eq(_dword_addr_matches_T_212, _dword_addr_matches_T_213)
node _dword_addr_matches_T_215 = and(_dword_addr_matches_T_211, _dword_addr_matches_T_214)
wire dword_addr_matches_43 : UInt<1>[1]
connect dword_addr_matches_43[0], _dword_addr_matches_T_215
wire write_mask_19 : UInt<8>
node _write_mask_mask_T_285 = eq(stq[19].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_286 = bits(stq[19].bits.addr.bits, 2, 0)
node _write_mask_mask_T_287 = dshl(UInt<8>(0h1), _write_mask_mask_T_286)
node _write_mask_mask_T_288 = eq(stq[19].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_289 = bits(stq[19].bits.addr.bits, 2, 1)
node _write_mask_mask_T_290 = dshl(_write_mask_mask_T_289, UInt<1>(0h1))
node _write_mask_mask_T_291 = dshl(UInt<8>(0h3), _write_mask_mask_T_290)
node _write_mask_mask_T_292 = eq(stq[19].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_293 = bits(stq[19].bits.addr.bits, 2, 2)
node _write_mask_mask_T_294 = mux(_write_mask_mask_T_293, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_295 = eq(stq[19].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_296 = mux(_write_mask_mask_T_295, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_297 = mux(_write_mask_mask_T_292, _write_mask_mask_T_294, _write_mask_mask_T_296)
node _write_mask_mask_T_298 = mux(_write_mask_mask_T_288, _write_mask_mask_T_291, _write_mask_mask_T_297)
node _write_mask_mask_T_299 = mux(_write_mask_mask_T_285, _write_mask_mask_T_287, _write_mask_mask_T_298)
connect write_mask_19, _write_mask_mask_T_299
node _T_1526 = and(do_ld_search[0], stq[19].valid)
node _T_1527 = bits(lcam_st_dep_mask[0], 19, 19)
node _T_1528 = and(_T_1526, _T_1527)
when _T_1528 :
node _T_1529 = and(lcam_mask[0], write_mask_19)
node _T_1530 = eq(_T_1529, lcam_mask[0])
node _T_1531 = eq(stq[19].bits.uop.is_fence, UInt<1>(0h0))
node _T_1532 = and(_T_1530, _T_1531)
node _T_1533 = eq(stq[19].bits.uop.is_amo, UInt<1>(0h0))
node _T_1534 = and(_T_1532, _T_1533)
node _T_1535 = and(_T_1534, dword_addr_matches_43[0])
node _T_1536 = and(_T_1535, can_forward[0])
when _T_1536 :
connect ldst_addr_matches[0][19], UInt<1>(0h1)
connect ldst_forward_matches[0][19], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_81 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_81, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_81
node _T_1537 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1538 = bits(_T_1537, 4, 0)
connect s1_set_execute[_T_1538], UInt<1>(0h0)
else :
node _T_1539 = and(lcam_mask[0], write_mask_19)
node _T_1540 = neq(_T_1539, UInt<1>(0h0))
node _T_1541 = and(_T_1540, dword_addr_matches_43[0])
when _T_1541 :
connect ldst_addr_matches[0][19], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_82 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_82, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_82
node _T_1542 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1543 = bits(_T_1542, 4, 0)
connect s1_set_execute[_T_1543], UInt<1>(0h0)
else :
node _T_1544 = or(stq[19].bits.uop.is_fence, stq[19].bits.uop.is_amo)
when _T_1544 :
connect ldst_addr_matches[0][19], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_83 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_83, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_83
node _T_1545 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1546 = bits(_T_1545, 4, 0)
connect s1_set_execute[_T_1546], UInt<1>(0h0)
node _dword_addr_matches_T_216 = eq(stq[20].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_217 = and(stq[20].bits.addr.valid, _dword_addr_matches_T_216)
node _dword_addr_matches_T_218 = bits(stq[20].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_219 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_220 = eq(_dword_addr_matches_T_218, _dword_addr_matches_T_219)
node _dword_addr_matches_T_221 = and(_dword_addr_matches_T_217, _dword_addr_matches_T_220)
wire dword_addr_matches_44 : UInt<1>[1]
connect dword_addr_matches_44[0], _dword_addr_matches_T_221
wire write_mask_20 : UInt<8>
node _write_mask_mask_T_300 = eq(stq[20].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_301 = bits(stq[20].bits.addr.bits, 2, 0)
node _write_mask_mask_T_302 = dshl(UInt<8>(0h1), _write_mask_mask_T_301)
node _write_mask_mask_T_303 = eq(stq[20].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_304 = bits(stq[20].bits.addr.bits, 2, 1)
node _write_mask_mask_T_305 = dshl(_write_mask_mask_T_304, UInt<1>(0h1))
node _write_mask_mask_T_306 = dshl(UInt<8>(0h3), _write_mask_mask_T_305)
node _write_mask_mask_T_307 = eq(stq[20].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_308 = bits(stq[20].bits.addr.bits, 2, 2)
node _write_mask_mask_T_309 = mux(_write_mask_mask_T_308, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_310 = eq(stq[20].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_311 = mux(_write_mask_mask_T_310, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_312 = mux(_write_mask_mask_T_307, _write_mask_mask_T_309, _write_mask_mask_T_311)
node _write_mask_mask_T_313 = mux(_write_mask_mask_T_303, _write_mask_mask_T_306, _write_mask_mask_T_312)
node _write_mask_mask_T_314 = mux(_write_mask_mask_T_300, _write_mask_mask_T_302, _write_mask_mask_T_313)
connect write_mask_20, _write_mask_mask_T_314
node _T_1547 = and(do_ld_search[0], stq[20].valid)
node _T_1548 = bits(lcam_st_dep_mask[0], 20, 20)
node _T_1549 = and(_T_1547, _T_1548)
when _T_1549 :
node _T_1550 = and(lcam_mask[0], write_mask_20)
node _T_1551 = eq(_T_1550, lcam_mask[0])
node _T_1552 = eq(stq[20].bits.uop.is_fence, UInt<1>(0h0))
node _T_1553 = and(_T_1551, _T_1552)
node _T_1554 = eq(stq[20].bits.uop.is_amo, UInt<1>(0h0))
node _T_1555 = and(_T_1553, _T_1554)
node _T_1556 = and(_T_1555, dword_addr_matches_44[0])
node _T_1557 = and(_T_1556, can_forward[0])
when _T_1557 :
connect ldst_addr_matches[0][20], UInt<1>(0h1)
connect ldst_forward_matches[0][20], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_84 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_84, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_84
node _T_1558 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1559 = bits(_T_1558, 4, 0)
connect s1_set_execute[_T_1559], UInt<1>(0h0)
else :
node _T_1560 = and(lcam_mask[0], write_mask_20)
node _T_1561 = neq(_T_1560, UInt<1>(0h0))
node _T_1562 = and(_T_1561, dword_addr_matches_44[0])
when _T_1562 :
connect ldst_addr_matches[0][20], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_85 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_85, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_85
node _T_1563 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1564 = bits(_T_1563, 4, 0)
connect s1_set_execute[_T_1564], UInt<1>(0h0)
else :
node _T_1565 = or(stq[20].bits.uop.is_fence, stq[20].bits.uop.is_amo)
when _T_1565 :
connect ldst_addr_matches[0][20], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_86 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_86, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_86
node _T_1566 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1567 = bits(_T_1566, 4, 0)
connect s1_set_execute[_T_1567], UInt<1>(0h0)
node _dword_addr_matches_T_222 = eq(stq[21].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_223 = and(stq[21].bits.addr.valid, _dword_addr_matches_T_222)
node _dword_addr_matches_T_224 = bits(stq[21].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_225 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_226 = eq(_dword_addr_matches_T_224, _dword_addr_matches_T_225)
node _dword_addr_matches_T_227 = and(_dword_addr_matches_T_223, _dword_addr_matches_T_226)
wire dword_addr_matches_45 : UInt<1>[1]
connect dword_addr_matches_45[0], _dword_addr_matches_T_227
wire write_mask_21 : UInt<8>
node _write_mask_mask_T_315 = eq(stq[21].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_316 = bits(stq[21].bits.addr.bits, 2, 0)
node _write_mask_mask_T_317 = dshl(UInt<8>(0h1), _write_mask_mask_T_316)
node _write_mask_mask_T_318 = eq(stq[21].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_319 = bits(stq[21].bits.addr.bits, 2, 1)
node _write_mask_mask_T_320 = dshl(_write_mask_mask_T_319, UInt<1>(0h1))
node _write_mask_mask_T_321 = dshl(UInt<8>(0h3), _write_mask_mask_T_320)
node _write_mask_mask_T_322 = eq(stq[21].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_323 = bits(stq[21].bits.addr.bits, 2, 2)
node _write_mask_mask_T_324 = mux(_write_mask_mask_T_323, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_325 = eq(stq[21].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_326 = mux(_write_mask_mask_T_325, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_327 = mux(_write_mask_mask_T_322, _write_mask_mask_T_324, _write_mask_mask_T_326)
node _write_mask_mask_T_328 = mux(_write_mask_mask_T_318, _write_mask_mask_T_321, _write_mask_mask_T_327)
node _write_mask_mask_T_329 = mux(_write_mask_mask_T_315, _write_mask_mask_T_317, _write_mask_mask_T_328)
connect write_mask_21, _write_mask_mask_T_329
node _T_1568 = and(do_ld_search[0], stq[21].valid)
node _T_1569 = bits(lcam_st_dep_mask[0], 21, 21)
node _T_1570 = and(_T_1568, _T_1569)
when _T_1570 :
node _T_1571 = and(lcam_mask[0], write_mask_21)
node _T_1572 = eq(_T_1571, lcam_mask[0])
node _T_1573 = eq(stq[21].bits.uop.is_fence, UInt<1>(0h0))
node _T_1574 = and(_T_1572, _T_1573)
node _T_1575 = eq(stq[21].bits.uop.is_amo, UInt<1>(0h0))
node _T_1576 = and(_T_1574, _T_1575)
node _T_1577 = and(_T_1576, dword_addr_matches_45[0])
node _T_1578 = and(_T_1577, can_forward[0])
when _T_1578 :
connect ldst_addr_matches[0][21], UInt<1>(0h1)
connect ldst_forward_matches[0][21], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_87 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_87, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_87
node _T_1579 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1580 = bits(_T_1579, 4, 0)
connect s1_set_execute[_T_1580], UInt<1>(0h0)
else :
node _T_1581 = and(lcam_mask[0], write_mask_21)
node _T_1582 = neq(_T_1581, UInt<1>(0h0))
node _T_1583 = and(_T_1582, dword_addr_matches_45[0])
when _T_1583 :
connect ldst_addr_matches[0][21], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_88 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_88, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_88
node _T_1584 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1585 = bits(_T_1584, 4, 0)
connect s1_set_execute[_T_1585], UInt<1>(0h0)
else :
node _T_1586 = or(stq[21].bits.uop.is_fence, stq[21].bits.uop.is_amo)
when _T_1586 :
connect ldst_addr_matches[0][21], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_89 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_89, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_89
node _T_1587 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1588 = bits(_T_1587, 4, 0)
connect s1_set_execute[_T_1588], UInt<1>(0h0)
node _dword_addr_matches_T_228 = eq(stq[22].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_229 = and(stq[22].bits.addr.valid, _dword_addr_matches_T_228)
node _dword_addr_matches_T_230 = bits(stq[22].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_231 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_232 = eq(_dword_addr_matches_T_230, _dword_addr_matches_T_231)
node _dword_addr_matches_T_233 = and(_dword_addr_matches_T_229, _dword_addr_matches_T_232)
wire dword_addr_matches_46 : UInt<1>[1]
connect dword_addr_matches_46[0], _dword_addr_matches_T_233
wire write_mask_22 : UInt<8>
node _write_mask_mask_T_330 = eq(stq[22].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_331 = bits(stq[22].bits.addr.bits, 2, 0)
node _write_mask_mask_T_332 = dshl(UInt<8>(0h1), _write_mask_mask_T_331)
node _write_mask_mask_T_333 = eq(stq[22].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_334 = bits(stq[22].bits.addr.bits, 2, 1)
node _write_mask_mask_T_335 = dshl(_write_mask_mask_T_334, UInt<1>(0h1))
node _write_mask_mask_T_336 = dshl(UInt<8>(0h3), _write_mask_mask_T_335)
node _write_mask_mask_T_337 = eq(stq[22].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_338 = bits(stq[22].bits.addr.bits, 2, 2)
node _write_mask_mask_T_339 = mux(_write_mask_mask_T_338, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_340 = eq(stq[22].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_341 = mux(_write_mask_mask_T_340, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_342 = mux(_write_mask_mask_T_337, _write_mask_mask_T_339, _write_mask_mask_T_341)
node _write_mask_mask_T_343 = mux(_write_mask_mask_T_333, _write_mask_mask_T_336, _write_mask_mask_T_342)
node _write_mask_mask_T_344 = mux(_write_mask_mask_T_330, _write_mask_mask_T_332, _write_mask_mask_T_343)
connect write_mask_22, _write_mask_mask_T_344
node _T_1589 = and(do_ld_search[0], stq[22].valid)
node _T_1590 = bits(lcam_st_dep_mask[0], 22, 22)
node _T_1591 = and(_T_1589, _T_1590)
when _T_1591 :
node _T_1592 = and(lcam_mask[0], write_mask_22)
node _T_1593 = eq(_T_1592, lcam_mask[0])
node _T_1594 = eq(stq[22].bits.uop.is_fence, UInt<1>(0h0))
node _T_1595 = and(_T_1593, _T_1594)
node _T_1596 = eq(stq[22].bits.uop.is_amo, UInt<1>(0h0))
node _T_1597 = and(_T_1595, _T_1596)
node _T_1598 = and(_T_1597, dword_addr_matches_46[0])
node _T_1599 = and(_T_1598, can_forward[0])
when _T_1599 :
connect ldst_addr_matches[0][22], UInt<1>(0h1)
connect ldst_forward_matches[0][22], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_90 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_90, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_90
node _T_1600 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1601 = bits(_T_1600, 4, 0)
connect s1_set_execute[_T_1601], UInt<1>(0h0)
else :
node _T_1602 = and(lcam_mask[0], write_mask_22)
node _T_1603 = neq(_T_1602, UInt<1>(0h0))
node _T_1604 = and(_T_1603, dword_addr_matches_46[0])
when _T_1604 :
connect ldst_addr_matches[0][22], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_91 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_91, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_91
node _T_1605 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1606 = bits(_T_1605, 4, 0)
connect s1_set_execute[_T_1606], UInt<1>(0h0)
else :
node _T_1607 = or(stq[22].bits.uop.is_fence, stq[22].bits.uop.is_amo)
when _T_1607 :
connect ldst_addr_matches[0][22], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_92 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_92, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_92
node _T_1608 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1609 = bits(_T_1608, 4, 0)
connect s1_set_execute[_T_1609], UInt<1>(0h0)
node _dword_addr_matches_T_234 = eq(stq[23].bits.addr_is_virtual, UInt<1>(0h0))
node _dword_addr_matches_T_235 = and(stq[23].bits.addr.valid, _dword_addr_matches_T_234)
node _dword_addr_matches_T_236 = bits(stq[23].bits.addr.bits, 31, 3)
node _dword_addr_matches_T_237 = bits(lcam_addr[0], 31, 3)
node _dword_addr_matches_T_238 = eq(_dword_addr_matches_T_236, _dword_addr_matches_T_237)
node _dword_addr_matches_T_239 = and(_dword_addr_matches_T_235, _dword_addr_matches_T_238)
wire dword_addr_matches_47 : UInt<1>[1]
connect dword_addr_matches_47[0], _dword_addr_matches_T_239
wire write_mask_23 : UInt<8>
node _write_mask_mask_T_345 = eq(stq[23].bits.uop.mem_size, UInt<1>(0h0))
node _write_mask_mask_T_346 = bits(stq[23].bits.addr.bits, 2, 0)
node _write_mask_mask_T_347 = dshl(UInt<8>(0h1), _write_mask_mask_T_346)
node _write_mask_mask_T_348 = eq(stq[23].bits.uop.mem_size, UInt<1>(0h1))
node _write_mask_mask_T_349 = bits(stq[23].bits.addr.bits, 2, 1)
node _write_mask_mask_T_350 = dshl(_write_mask_mask_T_349, UInt<1>(0h1))
node _write_mask_mask_T_351 = dshl(UInt<8>(0h3), _write_mask_mask_T_350)
node _write_mask_mask_T_352 = eq(stq[23].bits.uop.mem_size, UInt<2>(0h2))
node _write_mask_mask_T_353 = bits(stq[23].bits.addr.bits, 2, 2)
node _write_mask_mask_T_354 = mux(_write_mask_mask_T_353, UInt<8>(0hf0), UInt<8>(0hf))
node _write_mask_mask_T_355 = eq(stq[23].bits.uop.mem_size, UInt<2>(0h3))
node _write_mask_mask_T_356 = mux(_write_mask_mask_T_355, UInt<8>(0hff), UInt<8>(0hff))
node _write_mask_mask_T_357 = mux(_write_mask_mask_T_352, _write_mask_mask_T_354, _write_mask_mask_T_356)
node _write_mask_mask_T_358 = mux(_write_mask_mask_T_348, _write_mask_mask_T_351, _write_mask_mask_T_357)
node _write_mask_mask_T_359 = mux(_write_mask_mask_T_345, _write_mask_mask_T_347, _write_mask_mask_T_358)
connect write_mask_23, _write_mask_mask_T_359
node _T_1610 = and(do_ld_search[0], stq[23].valid)
node _T_1611 = bits(lcam_st_dep_mask[0], 23, 23)
node _T_1612 = and(_T_1610, _T_1611)
when _T_1612 :
node _T_1613 = and(lcam_mask[0], write_mask_23)
node _T_1614 = eq(_T_1613, lcam_mask[0])
node _T_1615 = eq(stq[23].bits.uop.is_fence, UInt<1>(0h0))
node _T_1616 = and(_T_1614, _T_1615)
node _T_1617 = eq(stq[23].bits.uop.is_amo, UInt<1>(0h0))
node _T_1618 = and(_T_1616, _T_1617)
node _T_1619 = and(_T_1618, dword_addr_matches_47[0])
node _T_1620 = and(_T_1619, can_forward[0])
when _T_1620 :
connect ldst_addr_matches[0][23], UInt<1>(0h1)
connect ldst_forward_matches[0][23], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_93 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_93, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_93
node _T_1621 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1622 = bits(_T_1621, 4, 0)
connect s1_set_execute[_T_1622], UInt<1>(0h0)
else :
node _T_1623 = and(lcam_mask[0], write_mask_23)
node _T_1624 = neq(_T_1623, UInt<1>(0h0))
node _T_1625 = and(_T_1624, dword_addr_matches_47[0])
when _T_1625 :
connect ldst_addr_matches[0][23], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_94 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_94, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_94
node _T_1626 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1627 = bits(_T_1626, 4, 0)
connect s1_set_execute[_T_1627], UInt<1>(0h0)
else :
node _T_1628 = or(stq[23].bits.uop.is_fence, stq[23].bits.uop.is_amo)
when _T_1628 :
connect ldst_addr_matches[0][23], UInt<1>(0h1)
reg io_dmem_s1_kill_0_REG_95 : UInt<1>, clock
connect io_dmem_s1_kill_0_REG_95, dmem_req_fire[0]
connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG_95
node _T_1629 = or(lcam_ldq_idx[0], UInt<5>(0h0))
node _T_1630 = bits(_T_1629, 4, 0)
connect s1_set_execute[_T_1630], UInt<1>(0h0)
when s1_set_execute[0] :
connect ldq[0].bits.executed, UInt<1>(0h1)
when s1_set_execute[1] :
connect ldq[1].bits.executed, UInt<1>(0h1)
when s1_set_execute[2] :
connect ldq[2].bits.executed, UInt<1>(0h1)
when s1_set_execute[3] :
connect ldq[3].bits.executed, UInt<1>(0h1)
when s1_set_execute[4] :
connect ldq[4].bits.executed, UInt<1>(0h1)
when s1_set_execute[5] :
connect ldq[5].bits.executed, UInt<1>(0h1)
when s1_set_execute[6] :
connect ldq[6].bits.executed, UInt<1>(0h1)
when s1_set_execute[7] :
connect ldq[7].bits.executed, UInt<1>(0h1)
when s1_set_execute[8] :
connect ldq[8].bits.executed, UInt<1>(0h1)
when s1_set_execute[9] :
connect ldq[9].bits.executed, UInt<1>(0h1)
when s1_set_execute[10] :
connect ldq[10].bits.executed, UInt<1>(0h1)
when s1_set_execute[11] :
connect ldq[11].bits.executed, UInt<1>(0h1)
when s1_set_execute[12] :
connect ldq[12].bits.executed, UInt<1>(0h1)
when s1_set_execute[13] :
connect ldq[13].bits.executed, UInt<1>(0h1)
when s1_set_execute[14] :
connect ldq[14].bits.executed, UInt<1>(0h1)
when s1_set_execute[15] :
connect ldq[15].bits.executed, UInt<1>(0h1)
when s1_set_execute[16] :
connect ldq[16].bits.executed, UInt<1>(0h1)
when s1_set_execute[17] :
connect ldq[17].bits.executed, UInt<1>(0h1)
when s1_set_execute[18] :
connect ldq[18].bits.executed, UInt<1>(0h1)
when s1_set_execute[19] :
connect ldq[19].bits.executed, UInt<1>(0h1)
when s1_set_execute[20] :
connect ldq[20].bits.executed, UInt<1>(0h1)
when s1_set_execute[21] :
connect ldq[21].bits.executed, UInt<1>(0h1)
when s1_set_execute[22] :
connect ldq[22].bits.executed, UInt<1>(0h1)
when s1_set_execute[23] :
connect ldq[23].bits.executed, UInt<1>(0h1)
inst forwarding_age_logic_0 of ForwardingAgeLogic
connect forwarding_age_logic_0.clock, clock
connect forwarding_age_logic_0.reset, reset
node forwarding_age_logic_0_io_addr_matches_lo_lo_lo_hi = cat(ldst_addr_matches[0][2], ldst_addr_matches[0][1])
node forwarding_age_logic_0_io_addr_matches_lo_lo_lo = cat(forwarding_age_logic_0_io_addr_matches_lo_lo_lo_hi, ldst_addr_matches[0][0])
node forwarding_age_logic_0_io_addr_matches_lo_lo_hi_hi = cat(ldst_addr_matches[0][5], ldst_addr_matches[0][4])
node forwarding_age_logic_0_io_addr_matches_lo_lo_hi = cat(forwarding_age_logic_0_io_addr_matches_lo_lo_hi_hi, ldst_addr_matches[0][3])
node forwarding_age_logic_0_io_addr_matches_lo_lo = cat(forwarding_age_logic_0_io_addr_matches_lo_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo_lo)
node forwarding_age_logic_0_io_addr_matches_lo_hi_lo_hi = cat(ldst_addr_matches[0][8], ldst_addr_matches[0][7])
node forwarding_age_logic_0_io_addr_matches_lo_hi_lo = cat(forwarding_age_logic_0_io_addr_matches_lo_hi_lo_hi, ldst_addr_matches[0][6])
node forwarding_age_logic_0_io_addr_matches_lo_hi_hi_hi = cat(ldst_addr_matches[0][11], ldst_addr_matches[0][10])
node forwarding_age_logic_0_io_addr_matches_lo_hi_hi = cat(forwarding_age_logic_0_io_addr_matches_lo_hi_hi_hi, ldst_addr_matches[0][9])
node forwarding_age_logic_0_io_addr_matches_lo_hi = cat(forwarding_age_logic_0_io_addr_matches_lo_hi_hi, forwarding_age_logic_0_io_addr_matches_lo_hi_lo)
node forwarding_age_logic_0_io_addr_matches_lo = cat(forwarding_age_logic_0_io_addr_matches_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo)
node forwarding_age_logic_0_io_addr_matches_hi_lo_lo_hi = cat(ldst_addr_matches[0][14], ldst_addr_matches[0][13])
node forwarding_age_logic_0_io_addr_matches_hi_lo_lo = cat(forwarding_age_logic_0_io_addr_matches_hi_lo_lo_hi, ldst_addr_matches[0][12])
node forwarding_age_logic_0_io_addr_matches_hi_lo_hi_hi = cat(ldst_addr_matches[0][17], ldst_addr_matches[0][16])
node forwarding_age_logic_0_io_addr_matches_hi_lo_hi = cat(forwarding_age_logic_0_io_addr_matches_hi_lo_hi_hi, ldst_addr_matches[0][15])
node forwarding_age_logic_0_io_addr_matches_hi_lo = cat(forwarding_age_logic_0_io_addr_matches_hi_lo_hi, forwarding_age_logic_0_io_addr_matches_hi_lo_lo)
node forwarding_age_logic_0_io_addr_matches_hi_hi_lo_hi = cat(ldst_addr_matches[0][20], ldst_addr_matches[0][19])
node forwarding_age_logic_0_io_addr_matches_hi_hi_lo = cat(forwarding_age_logic_0_io_addr_matches_hi_hi_lo_hi, ldst_addr_matches[0][18])
node forwarding_age_logic_0_io_addr_matches_hi_hi_hi_hi = cat(ldst_addr_matches[0][23], ldst_addr_matches[0][22])
node forwarding_age_logic_0_io_addr_matches_hi_hi_hi = cat(forwarding_age_logic_0_io_addr_matches_hi_hi_hi_hi, ldst_addr_matches[0][21])
node forwarding_age_logic_0_io_addr_matches_hi_hi = cat(forwarding_age_logic_0_io_addr_matches_hi_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_hi_lo)
node forwarding_age_logic_0_io_addr_matches_hi = cat(forwarding_age_logic_0_io_addr_matches_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_lo)
node _forwarding_age_logic_0_io_addr_matches_T = cat(forwarding_age_logic_0_io_addr_matches_hi, forwarding_age_logic_0_io_addr_matches_lo)
connect forwarding_age_logic_0.io.addr_matches, _forwarding_age_logic_0_io_addr_matches_T
connect forwarding_age_logic_0.io.youngest_st_idx, lcam_uop[0].stq_idx
wire forwarding_idx : UInt<5>[1]
connect forwarding_idx[0], forwarding_age_logic_0.io.forwarding_idx
node _T_1631 = and(io.core.brupdate.b1.mispredict_mask, lcam_uop[0].br_mask)
node _T_1632 = neq(_T_1631, UInt<1>(0h0))
node _T_1633 = eq(_T_1632, UInt<1>(0h0))
node _T_1634 = and(ldst_forward_matches[0][forwarding_idx[0]], _T_1633)
node _T_1635 = eq(io.core.exception, UInt<1>(0h0))
node _T_1636 = and(_T_1634, _T_1635)
reg REG_1 : UInt<1>, clock
connect REG_1, io.core.exception
node _T_1637 = eq(REG_1, UInt<1>(0h0))
node _T_1638 = and(_T_1636, _T_1637)
wire _WIRE_1 : UInt<1>[1]
connect _WIRE_1[0], _T_1638
connect mem_forward_valid, _WIRE_1
connect mem_forward_stq_idx, forwarding_idx
node _T_1639 = or(ldst_addr_matches[0][0], ldst_addr_matches[0][1])
node _T_1640 = or(_T_1639, ldst_addr_matches[0][2])
node _T_1641 = or(_T_1640, ldst_addr_matches[0][3])
node _T_1642 = or(_T_1641, ldst_addr_matches[0][4])
node _T_1643 = or(_T_1642, ldst_addr_matches[0][5])
node _T_1644 = or(_T_1643, ldst_addr_matches[0][6])
node _T_1645 = or(_T_1644, ldst_addr_matches[0][7])
node _T_1646 = or(_T_1645, ldst_addr_matches[0][8])
node _T_1647 = or(_T_1646, ldst_addr_matches[0][9])
node _T_1648 = or(_T_1647, ldst_addr_matches[0][10])
node _T_1649 = or(_T_1648, ldst_addr_matches[0][11])
node _T_1650 = or(_T_1649, ldst_addr_matches[0][12])
node _T_1651 = or(_T_1650, ldst_addr_matches[0][13])
node _T_1652 = or(_T_1651, ldst_addr_matches[0][14])
node _T_1653 = or(_T_1652, ldst_addr_matches[0][15])
node _T_1654 = or(_T_1653, ldst_addr_matches[0][16])
node _T_1655 = or(_T_1654, ldst_addr_matches[0][17])
node _T_1656 = or(_T_1655, ldst_addr_matches[0][18])
node _T_1657 = or(_T_1656, ldst_addr_matches[0][19])
node _T_1658 = or(_T_1657, ldst_addr_matches[0][20])
node _T_1659 = or(_T_1658, ldst_addr_matches[0][21])
node _T_1660 = or(_T_1659, ldst_addr_matches[0][22])
node _T_1661 = or(_T_1660, ldst_addr_matches[0][23])
node _T_1662 = eq(mem_forward_valid[0], UInt<1>(0h0))
node _T_1663 = and(_T_1661, _T_1662)
reg REG_2 : UInt<1>, clock
connect REG_2, _T_1663
when REG_2 :
connect block_load_wakeup, UInt<1>(0h1)
reg store_blocked_counter : UInt<4>, clock
node _T_1664 = eq(can_fire_store_commit[0], UInt<1>(0h0))
node _T_1665 = or(will_fire_store_commit[0], _T_1664)
when _T_1665 :
connect store_blocked_counter, UInt<1>(0h0)
else :
node _T_1666 = eq(will_fire_store_commit[0], UInt<1>(0h0))
node _T_1667 = and(can_fire_store_commit[0], _T_1666)
when _T_1667 :
node _store_blocked_counter_T = eq(store_blocked_counter, UInt<4>(0hf))
node _store_blocked_counter_T_1 = add(store_blocked_counter, UInt<1>(0h1))
node _store_blocked_counter_T_2 = tail(_store_blocked_counter_T_1, 1)
node _store_blocked_counter_T_3 = mux(_store_blocked_counter_T, UInt<4>(0hf), _store_blocked_counter_T_2)
connect store_blocked_counter, _store_blocked_counter_T_3
node _T_1668 = eq(store_blocked_counter, UInt<4>(0hf))
when _T_1668 :
connect block_load_wakeup, UInt<1>(0h1)
node _io_core_clr_unsafe_0_valid_T = or(do_st_search[0], do_ld_search[0])
node _io_core_clr_unsafe_0_valid_T_1 = eq(fired_load_wakeup[0], UInt<1>(0h0))
node _io_core_clr_unsafe_0_valid_T_2 = and(_io_core_clr_unsafe_0_valid_T, _io_core_clr_unsafe_0_valid_T_1)
reg io_core_clr_unsafe_0_valid_REG : UInt<1>, clock
connect io_core_clr_unsafe_0_valid_REG, _io_core_clr_unsafe_0_valid_T_2
node _io_core_clr_unsafe_0_valid_T_3 = and(io_core_clr_unsafe_0_valid_REG, UInt<1>(0h0))
connect io.core.clr_unsafe[0].valid, _io_core_clr_unsafe_0_valid_T_3
reg io_core_clr_unsafe_0_bits_REG : UInt, clock
connect io_core_clr_unsafe_0_bits_REG, lcam_uop[0].rob_idx
connect io.core.clr_unsafe[0].bits, io_core_clr_unsafe_0_bits_REG
node _temp_bits_T = geq(UInt<1>(0h0), ldq_head)
node _temp_bits_T_1 = and(failed_loads[0], _temp_bits_T)
node _temp_bits_T_2 = geq(UInt<1>(0h1), ldq_head)
node _temp_bits_T_3 = and(failed_loads[1], _temp_bits_T_2)
node _temp_bits_T_4 = geq(UInt<2>(0h2), ldq_head)
node _temp_bits_T_5 = and(failed_loads[2], _temp_bits_T_4)
node _temp_bits_T_6 = geq(UInt<2>(0h3), ldq_head)
node _temp_bits_T_7 = and(failed_loads[3], _temp_bits_T_6)
node _temp_bits_T_8 = geq(UInt<3>(0h4), ldq_head)
node _temp_bits_T_9 = and(failed_loads[4], _temp_bits_T_8)
node _temp_bits_T_10 = geq(UInt<3>(0h5), ldq_head)
node _temp_bits_T_11 = and(failed_loads[5], _temp_bits_T_10)
node _temp_bits_T_12 = geq(UInt<3>(0h6), ldq_head)
node _temp_bits_T_13 = and(failed_loads[6], _temp_bits_T_12)
node _temp_bits_T_14 = geq(UInt<3>(0h7), ldq_head)
node _temp_bits_T_15 = and(failed_loads[7], _temp_bits_T_14)
node _temp_bits_T_16 = geq(UInt<4>(0h8), ldq_head)
node _temp_bits_T_17 = and(failed_loads[8], _temp_bits_T_16)
node _temp_bits_T_18 = geq(UInt<4>(0h9), ldq_head)
node _temp_bits_T_19 = and(failed_loads[9], _temp_bits_T_18)
node _temp_bits_T_20 = geq(UInt<4>(0ha), ldq_head)
node _temp_bits_T_21 = and(failed_loads[10], _temp_bits_T_20)
node _temp_bits_T_22 = geq(UInt<4>(0hb), ldq_head)
node _temp_bits_T_23 = and(failed_loads[11], _temp_bits_T_22)
node _temp_bits_T_24 = geq(UInt<4>(0hc), ldq_head)
node _temp_bits_T_25 = and(failed_loads[12], _temp_bits_T_24)
node _temp_bits_T_26 = geq(UInt<4>(0hd), ldq_head)
node _temp_bits_T_27 = and(failed_loads[13], _temp_bits_T_26)
node _temp_bits_T_28 = geq(UInt<4>(0he), ldq_head)
node _temp_bits_T_29 = and(failed_loads[14], _temp_bits_T_28)
node _temp_bits_T_30 = geq(UInt<4>(0hf), ldq_head)
node _temp_bits_T_31 = and(failed_loads[15], _temp_bits_T_30)
node _temp_bits_T_32 = geq(UInt<5>(0h10), ldq_head)
node _temp_bits_T_33 = and(failed_loads[16], _temp_bits_T_32)
node _temp_bits_T_34 = geq(UInt<5>(0h11), ldq_head)
node _temp_bits_T_35 = and(failed_loads[17], _temp_bits_T_34)
node _temp_bits_T_36 = geq(UInt<5>(0h12), ldq_head)
node _temp_bits_T_37 = and(failed_loads[18], _temp_bits_T_36)
node _temp_bits_T_38 = geq(UInt<5>(0h13), ldq_head)
node _temp_bits_T_39 = and(failed_loads[19], _temp_bits_T_38)
node _temp_bits_T_40 = geq(UInt<5>(0h14), ldq_head)
node _temp_bits_T_41 = and(failed_loads[20], _temp_bits_T_40)
node _temp_bits_T_42 = geq(UInt<5>(0h15), ldq_head)
node _temp_bits_T_43 = and(failed_loads[21], _temp_bits_T_42)
node _temp_bits_T_44 = geq(UInt<5>(0h16), ldq_head)
node _temp_bits_T_45 = and(failed_loads[22], _temp_bits_T_44)
node _temp_bits_T_46 = geq(UInt<5>(0h17), ldq_head)
node _temp_bits_T_47 = and(failed_loads[23], _temp_bits_T_46)
wire _temp_bits_WIRE : UInt<1>[24]
connect _temp_bits_WIRE[0], _temp_bits_T_1
connect _temp_bits_WIRE[1], _temp_bits_T_3
connect _temp_bits_WIRE[2], _temp_bits_T_5
connect _temp_bits_WIRE[3], _temp_bits_T_7
connect _temp_bits_WIRE[4], _temp_bits_T_9
connect _temp_bits_WIRE[5], _temp_bits_T_11
connect _temp_bits_WIRE[6], _temp_bits_T_13
connect _temp_bits_WIRE[7], _temp_bits_T_15
connect _temp_bits_WIRE[8], _temp_bits_T_17
connect _temp_bits_WIRE[9], _temp_bits_T_19
connect _temp_bits_WIRE[10], _temp_bits_T_21
connect _temp_bits_WIRE[11], _temp_bits_T_23
connect _temp_bits_WIRE[12], _temp_bits_T_25
connect _temp_bits_WIRE[13], _temp_bits_T_27
connect _temp_bits_WIRE[14], _temp_bits_T_29
connect _temp_bits_WIRE[15], _temp_bits_T_31
connect _temp_bits_WIRE[16], _temp_bits_T_33
connect _temp_bits_WIRE[17], _temp_bits_T_35
connect _temp_bits_WIRE[18], _temp_bits_T_37
connect _temp_bits_WIRE[19], _temp_bits_T_39
connect _temp_bits_WIRE[20], _temp_bits_T_41
connect _temp_bits_WIRE[21], _temp_bits_T_43
connect _temp_bits_WIRE[22], _temp_bits_T_45
connect _temp_bits_WIRE[23], _temp_bits_T_47
wire _temp_bits_WIRE_1 : UInt<1>[48]
connect _temp_bits_WIRE_1[0], _temp_bits_WIRE[0]
connect _temp_bits_WIRE_1[1], _temp_bits_WIRE[1]
connect _temp_bits_WIRE_1[2], _temp_bits_WIRE[2]
connect _temp_bits_WIRE_1[3], _temp_bits_WIRE[3]
connect _temp_bits_WIRE_1[4], _temp_bits_WIRE[4]
connect _temp_bits_WIRE_1[5], _temp_bits_WIRE[5]
connect _temp_bits_WIRE_1[6], _temp_bits_WIRE[6]
connect _temp_bits_WIRE_1[7], _temp_bits_WIRE[7]
connect _temp_bits_WIRE_1[8], _temp_bits_WIRE[8]
connect _temp_bits_WIRE_1[9], _temp_bits_WIRE[9]
connect _temp_bits_WIRE_1[10], _temp_bits_WIRE[10]
connect _temp_bits_WIRE_1[11], _temp_bits_WIRE[11]
connect _temp_bits_WIRE_1[12], _temp_bits_WIRE[12]
connect _temp_bits_WIRE_1[13], _temp_bits_WIRE[13]
connect _temp_bits_WIRE_1[14], _temp_bits_WIRE[14]
connect _temp_bits_WIRE_1[15], _temp_bits_WIRE[15]
connect _temp_bits_WIRE_1[16], _temp_bits_WIRE[16]
connect _temp_bits_WIRE_1[17], _temp_bits_WIRE[17]
connect _temp_bits_WIRE_1[18], _temp_bits_WIRE[18]
connect _temp_bits_WIRE_1[19], _temp_bits_WIRE[19]
connect _temp_bits_WIRE_1[20], _temp_bits_WIRE[20]
connect _temp_bits_WIRE_1[21], _temp_bits_WIRE[21]
connect _temp_bits_WIRE_1[22], _temp_bits_WIRE[22]
connect _temp_bits_WIRE_1[23], _temp_bits_WIRE[23]
connect _temp_bits_WIRE_1[24], failed_loads[0]
connect _temp_bits_WIRE_1[25], failed_loads[1]
connect _temp_bits_WIRE_1[26], failed_loads[2]
connect _temp_bits_WIRE_1[27], failed_loads[3]
connect _temp_bits_WIRE_1[28], failed_loads[4]
connect _temp_bits_WIRE_1[29], failed_loads[5]
connect _temp_bits_WIRE_1[30], failed_loads[6]
connect _temp_bits_WIRE_1[31], failed_loads[7]
connect _temp_bits_WIRE_1[32], failed_loads[8]
connect _temp_bits_WIRE_1[33], failed_loads[9]
connect _temp_bits_WIRE_1[34], failed_loads[10]
connect _temp_bits_WIRE_1[35], failed_loads[11]
connect _temp_bits_WIRE_1[36], failed_loads[12]
connect _temp_bits_WIRE_1[37], failed_loads[13]
connect _temp_bits_WIRE_1[38], failed_loads[14]
connect _temp_bits_WIRE_1[39], failed_loads[15]
connect _temp_bits_WIRE_1[40], failed_loads[16]
connect _temp_bits_WIRE_1[41], failed_loads[17]
connect _temp_bits_WIRE_1[42], failed_loads[18]
connect _temp_bits_WIRE_1[43], failed_loads[19]
connect _temp_bits_WIRE_1[44], failed_loads[20]
connect _temp_bits_WIRE_1[45], failed_loads[21]
connect _temp_bits_WIRE_1[46], failed_loads[22]
connect _temp_bits_WIRE_1[47], failed_loads[23]
node temp_bits_lo_lo_lo_lo_hi = cat(_temp_bits_WIRE_1[2], _temp_bits_WIRE_1[1])
node temp_bits_lo_lo_lo_lo = cat(temp_bits_lo_lo_lo_lo_hi, _temp_bits_WIRE_1[0])
node temp_bits_lo_lo_lo_hi_hi = cat(_temp_bits_WIRE_1[5], _temp_bits_WIRE_1[4])
node temp_bits_lo_lo_lo_hi = cat(temp_bits_lo_lo_lo_hi_hi, _temp_bits_WIRE_1[3])
node temp_bits_lo_lo_lo = cat(temp_bits_lo_lo_lo_hi, temp_bits_lo_lo_lo_lo)
node temp_bits_lo_lo_hi_lo_hi = cat(_temp_bits_WIRE_1[8], _temp_bits_WIRE_1[7])
node temp_bits_lo_lo_hi_lo = cat(temp_bits_lo_lo_hi_lo_hi, _temp_bits_WIRE_1[6])
node temp_bits_lo_lo_hi_hi_hi = cat(_temp_bits_WIRE_1[11], _temp_bits_WIRE_1[10])
node temp_bits_lo_lo_hi_hi = cat(temp_bits_lo_lo_hi_hi_hi, _temp_bits_WIRE_1[9])
node temp_bits_lo_lo_hi = cat(temp_bits_lo_lo_hi_hi, temp_bits_lo_lo_hi_lo)
node temp_bits_lo_lo = cat(temp_bits_lo_lo_hi, temp_bits_lo_lo_lo)
node temp_bits_lo_hi_lo_lo_hi = cat(_temp_bits_WIRE_1[14], _temp_bits_WIRE_1[13])
node temp_bits_lo_hi_lo_lo = cat(temp_bits_lo_hi_lo_lo_hi, _temp_bits_WIRE_1[12])
node temp_bits_lo_hi_lo_hi_hi = cat(_temp_bits_WIRE_1[17], _temp_bits_WIRE_1[16])
node temp_bits_lo_hi_lo_hi = cat(temp_bits_lo_hi_lo_hi_hi, _temp_bits_WIRE_1[15])
node temp_bits_lo_hi_lo = cat(temp_bits_lo_hi_lo_hi, temp_bits_lo_hi_lo_lo)
node temp_bits_lo_hi_hi_lo_hi = cat(_temp_bits_WIRE_1[20], _temp_bits_WIRE_1[19])
node temp_bits_lo_hi_hi_lo = cat(temp_bits_lo_hi_hi_lo_hi, _temp_bits_WIRE_1[18])
node temp_bits_lo_hi_hi_hi_hi = cat(_temp_bits_WIRE_1[23], _temp_bits_WIRE_1[22])
node temp_bits_lo_hi_hi_hi = cat(temp_bits_lo_hi_hi_hi_hi, _temp_bits_WIRE_1[21])
node temp_bits_lo_hi_hi = cat(temp_bits_lo_hi_hi_hi, temp_bits_lo_hi_hi_lo)
node temp_bits_lo_hi = cat(temp_bits_lo_hi_hi, temp_bits_lo_hi_lo)
node temp_bits_lo = cat(temp_bits_lo_hi, temp_bits_lo_lo)
node temp_bits_hi_lo_lo_lo_hi = cat(_temp_bits_WIRE_1[26], _temp_bits_WIRE_1[25])
node temp_bits_hi_lo_lo_lo = cat(temp_bits_hi_lo_lo_lo_hi, _temp_bits_WIRE_1[24])
node temp_bits_hi_lo_lo_hi_hi = cat(_temp_bits_WIRE_1[29], _temp_bits_WIRE_1[28])
node temp_bits_hi_lo_lo_hi = cat(temp_bits_hi_lo_lo_hi_hi, _temp_bits_WIRE_1[27])
node temp_bits_hi_lo_lo = cat(temp_bits_hi_lo_lo_hi, temp_bits_hi_lo_lo_lo)
node temp_bits_hi_lo_hi_lo_hi = cat(_temp_bits_WIRE_1[32], _temp_bits_WIRE_1[31])
node temp_bits_hi_lo_hi_lo = cat(temp_bits_hi_lo_hi_lo_hi, _temp_bits_WIRE_1[30])
node temp_bits_hi_lo_hi_hi_hi = cat(_temp_bits_WIRE_1[35], _temp_bits_WIRE_1[34])
node temp_bits_hi_lo_hi_hi = cat(temp_bits_hi_lo_hi_hi_hi, _temp_bits_WIRE_1[33])
node temp_bits_hi_lo_hi = cat(temp_bits_hi_lo_hi_hi, temp_bits_hi_lo_hi_lo)
node temp_bits_hi_lo = cat(temp_bits_hi_lo_hi, temp_bits_hi_lo_lo)
node temp_bits_hi_hi_lo_lo_hi = cat(_temp_bits_WIRE_1[38], _temp_bits_WIRE_1[37])
node temp_bits_hi_hi_lo_lo = cat(temp_bits_hi_hi_lo_lo_hi, _temp_bits_WIRE_1[36])
node temp_bits_hi_hi_lo_hi_hi = cat(_temp_bits_WIRE_1[41], _temp_bits_WIRE_1[40])
node temp_bits_hi_hi_lo_hi = cat(temp_bits_hi_hi_lo_hi_hi, _temp_bits_WIRE_1[39])
node temp_bits_hi_hi_lo = cat(temp_bits_hi_hi_lo_hi, temp_bits_hi_hi_lo_lo)
node temp_bits_hi_hi_hi_lo_hi = cat(_temp_bits_WIRE_1[44], _temp_bits_WIRE_1[43])
node temp_bits_hi_hi_hi_lo = cat(temp_bits_hi_hi_hi_lo_hi, _temp_bits_WIRE_1[42])
node temp_bits_hi_hi_hi_hi_hi = cat(_temp_bits_WIRE_1[47], _temp_bits_WIRE_1[46])
node temp_bits_hi_hi_hi_hi = cat(temp_bits_hi_hi_hi_hi_hi, _temp_bits_WIRE_1[45])
node temp_bits_hi_hi_hi = cat(temp_bits_hi_hi_hi_hi, temp_bits_hi_hi_hi_lo)
node temp_bits_hi_hi = cat(temp_bits_hi_hi_hi, temp_bits_hi_hi_lo)
node temp_bits_hi = cat(temp_bits_hi_hi, temp_bits_hi_lo)
node temp_bits = cat(temp_bits_hi, temp_bits_lo)
node _l_idx_T = bits(temp_bits, 0, 0)
node _l_idx_T_1 = bits(temp_bits, 1, 1)
node _l_idx_T_2 = bits(temp_bits, 2, 2)
node _l_idx_T_3 = bits(temp_bits, 3, 3)
node _l_idx_T_4 = bits(temp_bits, 4, 4)
node _l_idx_T_5 = bits(temp_bits, 5, 5)
node _l_idx_T_6 = bits(temp_bits, 6, 6)
node _l_idx_T_7 = bits(temp_bits, 7, 7)
node _l_idx_T_8 = bits(temp_bits, 8, 8)
node _l_idx_T_9 = bits(temp_bits, 9, 9)
node _l_idx_T_10 = bits(temp_bits, 10, 10)
node _l_idx_T_11 = bits(temp_bits, 11, 11)
node _l_idx_T_12 = bits(temp_bits, 12, 12)
node _l_idx_T_13 = bits(temp_bits, 13, 13)
node _l_idx_T_14 = bits(temp_bits, 14, 14)
node _l_idx_T_15 = bits(temp_bits, 15, 15)
node _l_idx_T_16 = bits(temp_bits, 16, 16)
node _l_idx_T_17 = bits(temp_bits, 17, 17)
node _l_idx_T_18 = bits(temp_bits, 18, 18)
node _l_idx_T_19 = bits(temp_bits, 19, 19)
node _l_idx_T_20 = bits(temp_bits, 20, 20)
node _l_idx_T_21 = bits(temp_bits, 21, 21)
node _l_idx_T_22 = bits(temp_bits, 22, 22)
node _l_idx_T_23 = bits(temp_bits, 23, 23)
node _l_idx_T_24 = bits(temp_bits, 24, 24)
node _l_idx_T_25 = bits(temp_bits, 25, 25)
node _l_idx_T_26 = bits(temp_bits, 26, 26)
node _l_idx_T_27 = bits(temp_bits, 27, 27)
node _l_idx_T_28 = bits(temp_bits, 28, 28)
node _l_idx_T_29 = bits(temp_bits, 29, 29)
node _l_idx_T_30 = bits(temp_bits, 30, 30)
node _l_idx_T_31 = bits(temp_bits, 31, 31)
node _l_idx_T_32 = bits(temp_bits, 32, 32)
node _l_idx_T_33 = bits(temp_bits, 33, 33)
node _l_idx_T_34 = bits(temp_bits, 34, 34)
node _l_idx_T_35 = bits(temp_bits, 35, 35)
node _l_idx_T_36 = bits(temp_bits, 36, 36)
node _l_idx_T_37 = bits(temp_bits, 37, 37)
node _l_idx_T_38 = bits(temp_bits, 38, 38)
node _l_idx_T_39 = bits(temp_bits, 39, 39)
node _l_idx_T_40 = bits(temp_bits, 40, 40)
node _l_idx_T_41 = bits(temp_bits, 41, 41)
node _l_idx_T_42 = bits(temp_bits, 42, 42)
node _l_idx_T_43 = bits(temp_bits, 43, 43)
node _l_idx_T_44 = bits(temp_bits, 44, 44)
node _l_idx_T_45 = bits(temp_bits, 45, 45)
node _l_idx_T_46 = bits(temp_bits, 46, 46)
node _l_idx_T_47 = bits(temp_bits, 47, 47)
node _l_idx_T_48 = mux(_l_idx_T_46, UInt<6>(0h2e), UInt<6>(0h2f))
node _l_idx_T_49 = mux(_l_idx_T_45, UInt<6>(0h2d), _l_idx_T_48)
node _l_idx_T_50 = mux(_l_idx_T_44, UInt<6>(0h2c), _l_idx_T_49)
node _l_idx_T_51 = mux(_l_idx_T_43, UInt<6>(0h2b), _l_idx_T_50)
node _l_idx_T_52 = mux(_l_idx_T_42, UInt<6>(0h2a), _l_idx_T_51)
node _l_idx_T_53 = mux(_l_idx_T_41, UInt<6>(0h29), _l_idx_T_52)
node _l_idx_T_54 = mux(_l_idx_T_40, UInt<6>(0h28), _l_idx_T_53)
node _l_idx_T_55 = mux(_l_idx_T_39, UInt<6>(0h27), _l_idx_T_54)
node _l_idx_T_56 = mux(_l_idx_T_38, UInt<6>(0h26), _l_idx_T_55)
node _l_idx_T_57 = mux(_l_idx_T_37, UInt<6>(0h25), _l_idx_T_56)
node _l_idx_T_58 = mux(_l_idx_T_36, UInt<6>(0h24), _l_idx_T_57)
node _l_idx_T_59 = mux(_l_idx_T_35, UInt<6>(0h23), _l_idx_T_58)
node _l_idx_T_60 = mux(_l_idx_T_34, UInt<6>(0h22), _l_idx_T_59)
node _l_idx_T_61 = mux(_l_idx_T_33, UInt<6>(0h21), _l_idx_T_60)
node _l_idx_T_62 = mux(_l_idx_T_32, UInt<6>(0h20), _l_idx_T_61)
node _l_idx_T_63 = mux(_l_idx_T_31, UInt<5>(0h1f), _l_idx_T_62)
node _l_idx_T_64 = mux(_l_idx_T_30, UInt<5>(0h1e), _l_idx_T_63)
node _l_idx_T_65 = mux(_l_idx_T_29, UInt<5>(0h1d), _l_idx_T_64)
node _l_idx_T_66 = mux(_l_idx_T_28, UInt<5>(0h1c), _l_idx_T_65)
node _l_idx_T_67 = mux(_l_idx_T_27, UInt<5>(0h1b), _l_idx_T_66)
node _l_idx_T_68 = mux(_l_idx_T_26, UInt<5>(0h1a), _l_idx_T_67)
node _l_idx_T_69 = mux(_l_idx_T_25, UInt<5>(0h19), _l_idx_T_68)
node _l_idx_T_70 = mux(_l_idx_T_24, UInt<5>(0h18), _l_idx_T_69)
node _l_idx_T_71 = mux(_l_idx_T_23, UInt<5>(0h17), _l_idx_T_70)
node _l_idx_T_72 = mux(_l_idx_T_22, UInt<5>(0h16), _l_idx_T_71)
node _l_idx_T_73 = mux(_l_idx_T_21, UInt<5>(0h15), _l_idx_T_72)
node _l_idx_T_74 = mux(_l_idx_T_20, UInt<5>(0h14), _l_idx_T_73)
node _l_idx_T_75 = mux(_l_idx_T_19, UInt<5>(0h13), _l_idx_T_74)
node _l_idx_T_76 = mux(_l_idx_T_18, UInt<5>(0h12), _l_idx_T_75)
node _l_idx_T_77 = mux(_l_idx_T_17, UInt<5>(0h11), _l_idx_T_76)
node _l_idx_T_78 = mux(_l_idx_T_16, UInt<5>(0h10), _l_idx_T_77)
node _l_idx_T_79 = mux(_l_idx_T_15, UInt<4>(0hf), _l_idx_T_78)
node _l_idx_T_80 = mux(_l_idx_T_14, UInt<4>(0he), _l_idx_T_79)
node _l_idx_T_81 = mux(_l_idx_T_13, UInt<4>(0hd), _l_idx_T_80)
node _l_idx_T_82 = mux(_l_idx_T_12, UInt<4>(0hc), _l_idx_T_81)
node _l_idx_T_83 = mux(_l_idx_T_11, UInt<4>(0hb), _l_idx_T_82)
node _l_idx_T_84 = mux(_l_idx_T_10, UInt<4>(0ha), _l_idx_T_83)
node _l_idx_T_85 = mux(_l_idx_T_9, UInt<4>(0h9), _l_idx_T_84)
node _l_idx_T_86 = mux(_l_idx_T_8, UInt<4>(0h8), _l_idx_T_85)
node _l_idx_T_87 = mux(_l_idx_T_7, UInt<3>(0h7), _l_idx_T_86)
node _l_idx_T_88 = mux(_l_idx_T_6, UInt<3>(0h6), _l_idx_T_87)
node _l_idx_T_89 = mux(_l_idx_T_5, UInt<3>(0h5), _l_idx_T_88)
node _l_idx_T_90 = mux(_l_idx_T_4, UInt<3>(0h4), _l_idx_T_89)
node _l_idx_T_91 = mux(_l_idx_T_3, UInt<2>(0h3), _l_idx_T_90)
node _l_idx_T_92 = mux(_l_idx_T_2, UInt<2>(0h2), _l_idx_T_91)
node _l_idx_T_93 = mux(_l_idx_T_1, UInt<1>(0h1), _l_idx_T_92)
node l_idx = mux(_l_idx_T, UInt<1>(0h0), _l_idx_T_93)
regreset r_xcpt_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_xcpt : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<40>}, clock
node _ld_xcpt_valid_T = or(failed_loads[0], failed_loads[1])
node _ld_xcpt_valid_T_1 = or(_ld_xcpt_valid_T, failed_loads[2])
node _ld_xcpt_valid_T_2 = or(_ld_xcpt_valid_T_1, failed_loads[3])
node _ld_xcpt_valid_T_3 = or(_ld_xcpt_valid_T_2, failed_loads[4])
node _ld_xcpt_valid_T_4 = or(_ld_xcpt_valid_T_3, failed_loads[5])
node _ld_xcpt_valid_T_5 = or(_ld_xcpt_valid_T_4, failed_loads[6])
node _ld_xcpt_valid_T_6 = or(_ld_xcpt_valid_T_5, failed_loads[7])
node _ld_xcpt_valid_T_7 = or(_ld_xcpt_valid_T_6, failed_loads[8])
node _ld_xcpt_valid_T_8 = or(_ld_xcpt_valid_T_7, failed_loads[9])
node _ld_xcpt_valid_T_9 = or(_ld_xcpt_valid_T_8, failed_loads[10])
node _ld_xcpt_valid_T_10 = or(_ld_xcpt_valid_T_9, failed_loads[11])
node _ld_xcpt_valid_T_11 = or(_ld_xcpt_valid_T_10, failed_loads[12])
node _ld_xcpt_valid_T_12 = or(_ld_xcpt_valid_T_11, failed_loads[13])
node _ld_xcpt_valid_T_13 = or(_ld_xcpt_valid_T_12, failed_loads[14])
node _ld_xcpt_valid_T_14 = or(_ld_xcpt_valid_T_13, failed_loads[15])
node _ld_xcpt_valid_T_15 = or(_ld_xcpt_valid_T_14, failed_loads[16])
node _ld_xcpt_valid_T_16 = or(_ld_xcpt_valid_T_15, failed_loads[17])
node _ld_xcpt_valid_T_17 = or(_ld_xcpt_valid_T_16, failed_loads[18])
node _ld_xcpt_valid_T_18 = or(_ld_xcpt_valid_T_17, failed_loads[19])
node _ld_xcpt_valid_T_19 = or(_ld_xcpt_valid_T_18, failed_loads[20])
node _ld_xcpt_valid_T_20 = or(_ld_xcpt_valid_T_19, failed_loads[21])
node _ld_xcpt_valid_T_21 = or(_ld_xcpt_valid_T_20, failed_loads[22])
node ld_xcpt_valid = or(_ld_xcpt_valid_T_21, failed_loads[23])
node _ld_xcpt_uop_T = geq(l_idx, UInt<5>(0h18))
node _ld_xcpt_uop_T_1 = sub(l_idx, UInt<5>(0h18))
node _ld_xcpt_uop_T_2 = tail(_ld_xcpt_uop_T_1, 1)
node _ld_xcpt_uop_T_3 = mux(_ld_xcpt_uop_T, _ld_xcpt_uop_T_2, l_idx)
node _ld_xcpt_uop_T_4 = bits(_ld_xcpt_uop_T_3, 4, 0)
node _use_mem_xcpt_T = lt(mem_xcpt_uop.rob_idx, ldq[_ld_xcpt_uop_T_4].bits.uop.rob_idx)
node _use_mem_xcpt_T_1 = lt(mem_xcpt_uop.rob_idx, io.core.rob_head_idx)
node _use_mem_xcpt_T_2 = xor(_use_mem_xcpt_T, _use_mem_xcpt_T_1)
node _use_mem_xcpt_T_3 = lt(ldq[_ld_xcpt_uop_T_4].bits.uop.rob_idx, io.core.rob_head_idx)
node _use_mem_xcpt_T_4 = xor(_use_mem_xcpt_T_2, _use_mem_xcpt_T_3)
node _use_mem_xcpt_T_5 = and(mem_xcpt_valid, _use_mem_xcpt_T_4)
node _use_mem_xcpt_T_6 = eq(ld_xcpt_valid, UInt<1>(0h0))
node use_mem_xcpt = or(_use_mem_xcpt_T_5, _use_mem_xcpt_T_6)
node xcpt_uop = mux(use_mem_xcpt, mem_xcpt_uop, ldq[_ld_xcpt_uop_T_4].bits.uop)
node _r_xcpt_valid_T = or(ld_xcpt_valid, mem_xcpt_valid)
node _r_xcpt_valid_T_1 = eq(io.core.exception, UInt<1>(0h0))
node _r_xcpt_valid_T_2 = and(_r_xcpt_valid_T, _r_xcpt_valid_T_1)
node _r_xcpt_valid_T_3 = and(io.core.brupdate.b1.mispredict_mask, xcpt_uop.br_mask)
node _r_xcpt_valid_T_4 = neq(_r_xcpt_valid_T_3, UInt<1>(0h0))
node _r_xcpt_valid_T_5 = eq(_r_xcpt_valid_T_4, UInt<1>(0h0))
node _r_xcpt_valid_T_6 = and(_r_xcpt_valid_T_2, _r_xcpt_valid_T_5)
connect r_xcpt_valid, _r_xcpt_valid_T_6
connect r_xcpt.uop, xcpt_uop
node _r_xcpt_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _r_xcpt_uop_br_mask_T_1 = and(xcpt_uop.br_mask, _r_xcpt_uop_br_mask_T)
connect r_xcpt.uop.br_mask, _r_xcpt_uop_br_mask_T_1
node _r_xcpt_cause_T = mux(use_mem_xcpt, mem_xcpt_cause, UInt<5>(0h10))
connect r_xcpt.cause, _r_xcpt_cause_T
connect r_xcpt.badvaddr, mem_xcpt_vaddr
node _io_core_lxcpt_valid_T = eq(io.core.exception, UInt<1>(0h0))
node _io_core_lxcpt_valid_T_1 = and(r_xcpt_valid, _io_core_lxcpt_valid_T)
node _io_core_lxcpt_valid_T_2 = and(io.core.brupdate.b1.mispredict_mask, r_xcpt.uop.br_mask)
node _io_core_lxcpt_valid_T_3 = neq(_io_core_lxcpt_valid_T_2, UInt<1>(0h0))
node _io_core_lxcpt_valid_T_4 = eq(_io_core_lxcpt_valid_T_3, UInt<1>(0h0))
node _io_core_lxcpt_valid_T_5 = and(_io_core_lxcpt_valid_T_1, _io_core_lxcpt_valid_T_4)
connect io.core.lxcpt.valid, _io_core_lxcpt_valid_T_5
connect io.core.lxcpt.bits, r_xcpt
node _io_core_spec_ld_wakeup_0_valid_T = and(UInt<1>(0h1), fired_load_incoming[0])
node _io_core_spec_ld_wakeup_0_valid_T_1 = eq(mem_incoming_uop[0].fp_val, UInt<1>(0h0))
node _io_core_spec_ld_wakeup_0_valid_T_2 = and(_io_core_spec_ld_wakeup_0_valid_T, _io_core_spec_ld_wakeup_0_valid_T_1)
node _io_core_spec_ld_wakeup_0_valid_T_3 = neq(mem_incoming_uop[0].pdst, UInt<1>(0h0))
node _io_core_spec_ld_wakeup_0_valid_T_4 = and(_io_core_spec_ld_wakeup_0_valid_T_2, _io_core_spec_ld_wakeup_0_valid_T_3)
connect io.core.spec_ld_wakeup[0].valid, _io_core_spec_ld_wakeup_0_valid_T_4
connect io.core.spec_ld_wakeup[0].bits, mem_incoming_uop[0].pdst
connect io.core.exe[0].iresp.valid, UInt<1>(0h0)
invalidate io.core.exe[0].iresp.bits.fflags.bits.flags
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.fp_single
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.fp_val
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.frs3_en
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.dst_rtype
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ldst_val
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.lrs3
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.lrs2
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.lrs1
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ldst
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_unique
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.uses_stq
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.uses_ldq
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_amo
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_fencei
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_fence
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.mem_signed
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.mem_size
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.mem_cmd
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.bypassable
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.exc_cause
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.exception
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.stale_pdst
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ppred_busy
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.prs3_busy
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.prs2_busy
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.prs1_busy
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ppred
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.prs3
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.prs2
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.prs1
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.pdst
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.rxq_idx
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.stq_idx
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ldq_idx
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.rob_idx
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.csr_addr
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.imm_packed
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.taken
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.pc_lob
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.edge_inst
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ftq_idx
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.br_tag
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.br_mask
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_sfb
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_jal
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_jalr
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_br
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.iw_state
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.fu_code
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.iq_type
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.debug_pc
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.is_rvc
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.debug_inst
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.inst
invalidate io.core.exe[0].iresp.bits.fflags.bits.uop.uopc
invalidate io.core.exe[0].iresp.bits.fflags.valid
invalidate io.core.exe[0].iresp.bits.predicated
invalidate io.core.exe[0].iresp.bits.data
invalidate io.core.exe[0].iresp.bits.uop.debug_tsrc
invalidate io.core.exe[0].iresp.bits.uop.debug_fsrc
invalidate io.core.exe[0].iresp.bits.uop.bp_xcpt_if
invalidate io.core.exe[0].iresp.bits.uop.bp_debug_if
invalidate io.core.exe[0].iresp.bits.uop.xcpt_ma_if
invalidate io.core.exe[0].iresp.bits.uop.xcpt_ae_if
invalidate io.core.exe[0].iresp.bits.uop.xcpt_pf_if
invalidate io.core.exe[0].iresp.bits.uop.fp_single
invalidate io.core.exe[0].iresp.bits.uop.fp_val
invalidate io.core.exe[0].iresp.bits.uop.frs3_en
invalidate io.core.exe[0].iresp.bits.uop.lrs2_rtype
invalidate io.core.exe[0].iresp.bits.uop.lrs1_rtype
invalidate io.core.exe[0].iresp.bits.uop.dst_rtype
invalidate io.core.exe[0].iresp.bits.uop.ldst_val
invalidate io.core.exe[0].iresp.bits.uop.lrs3
invalidate io.core.exe[0].iresp.bits.uop.lrs2
invalidate io.core.exe[0].iresp.bits.uop.lrs1
invalidate io.core.exe[0].iresp.bits.uop.ldst
invalidate io.core.exe[0].iresp.bits.uop.ldst_is_rs1
invalidate io.core.exe[0].iresp.bits.uop.flush_on_commit
invalidate io.core.exe[0].iresp.bits.uop.is_unique
invalidate io.core.exe[0].iresp.bits.uop.is_sys_pc2epc
invalidate io.core.exe[0].iresp.bits.uop.uses_stq
invalidate io.core.exe[0].iresp.bits.uop.uses_ldq
invalidate io.core.exe[0].iresp.bits.uop.is_amo
invalidate io.core.exe[0].iresp.bits.uop.is_fencei
invalidate io.core.exe[0].iresp.bits.uop.is_fence
invalidate io.core.exe[0].iresp.bits.uop.mem_signed
invalidate io.core.exe[0].iresp.bits.uop.mem_size
invalidate io.core.exe[0].iresp.bits.uop.mem_cmd
invalidate io.core.exe[0].iresp.bits.uop.bypassable
invalidate io.core.exe[0].iresp.bits.uop.exc_cause
invalidate io.core.exe[0].iresp.bits.uop.exception
invalidate io.core.exe[0].iresp.bits.uop.stale_pdst
invalidate io.core.exe[0].iresp.bits.uop.ppred_busy
invalidate io.core.exe[0].iresp.bits.uop.prs3_busy
invalidate io.core.exe[0].iresp.bits.uop.prs2_busy
invalidate io.core.exe[0].iresp.bits.uop.prs1_busy
invalidate io.core.exe[0].iresp.bits.uop.ppred
invalidate io.core.exe[0].iresp.bits.uop.prs3
invalidate io.core.exe[0].iresp.bits.uop.prs2
invalidate io.core.exe[0].iresp.bits.uop.prs1
invalidate io.core.exe[0].iresp.bits.uop.pdst
invalidate io.core.exe[0].iresp.bits.uop.rxq_idx
invalidate io.core.exe[0].iresp.bits.uop.stq_idx
invalidate io.core.exe[0].iresp.bits.uop.ldq_idx
invalidate io.core.exe[0].iresp.bits.uop.rob_idx
invalidate io.core.exe[0].iresp.bits.uop.csr_addr
invalidate io.core.exe[0].iresp.bits.uop.imm_packed
invalidate io.core.exe[0].iresp.bits.uop.taken
invalidate io.core.exe[0].iresp.bits.uop.pc_lob
invalidate io.core.exe[0].iresp.bits.uop.edge_inst
invalidate io.core.exe[0].iresp.bits.uop.ftq_idx
invalidate io.core.exe[0].iresp.bits.uop.br_tag
invalidate io.core.exe[0].iresp.bits.uop.br_mask
invalidate io.core.exe[0].iresp.bits.uop.is_sfb
invalidate io.core.exe[0].iresp.bits.uop.is_jal
invalidate io.core.exe[0].iresp.bits.uop.is_jalr
invalidate io.core.exe[0].iresp.bits.uop.is_br
invalidate io.core.exe[0].iresp.bits.uop.iw_p2_poisoned
invalidate io.core.exe[0].iresp.bits.uop.iw_p1_poisoned
invalidate io.core.exe[0].iresp.bits.uop.iw_state
invalidate io.core.exe[0].iresp.bits.uop.ctrl.is_std
invalidate io.core.exe[0].iresp.bits.uop.ctrl.is_sta
invalidate io.core.exe[0].iresp.bits.uop.ctrl.is_load
invalidate io.core.exe[0].iresp.bits.uop.ctrl.csr_cmd
invalidate io.core.exe[0].iresp.bits.uop.ctrl.fcn_dw
invalidate io.core.exe[0].iresp.bits.uop.ctrl.op_fcn
invalidate io.core.exe[0].iresp.bits.uop.ctrl.imm_sel
invalidate io.core.exe[0].iresp.bits.uop.ctrl.op2_sel
invalidate io.core.exe[0].iresp.bits.uop.ctrl.op1_sel
invalidate io.core.exe[0].iresp.bits.uop.ctrl.br_type
invalidate io.core.exe[0].iresp.bits.uop.fu_code
invalidate io.core.exe[0].iresp.bits.uop.iq_type
invalidate io.core.exe[0].iresp.bits.uop.debug_pc
invalidate io.core.exe[0].iresp.bits.uop.is_rvc
invalidate io.core.exe[0].iresp.bits.uop.debug_inst
invalidate io.core.exe[0].iresp.bits.uop.inst
invalidate io.core.exe[0].iresp.bits.uop.uopc
connect io.core.exe[0].fresp.valid, UInt<1>(0h0)
invalidate io.core.exe[0].fresp.bits.fflags.bits.flags
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.fp_single
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.fp_val
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.frs3_en
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.dst_rtype
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ldst_val
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.lrs3
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.lrs2
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.lrs1
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ldst
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_unique
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.uses_stq
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.uses_ldq
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_amo
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_fencei
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_fence
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.mem_signed
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.mem_size
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.mem_cmd
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.bypassable
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.exc_cause
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.exception
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.stale_pdst
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ppred_busy
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.prs3_busy
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.prs2_busy
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.prs1_busy
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ppred
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.prs3
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.prs2
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.prs1
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.pdst
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.rxq_idx
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.stq_idx
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ldq_idx
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.rob_idx
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.csr_addr
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.imm_packed
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.taken
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.pc_lob
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.edge_inst
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ftq_idx
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.br_tag
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.br_mask
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_sfb
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_jal
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_jalr
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_br
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.iw_state
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.fu_code
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.iq_type
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.debug_pc
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.is_rvc
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.debug_inst
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.inst
invalidate io.core.exe[0].fresp.bits.fflags.bits.uop.uopc
invalidate io.core.exe[0].fresp.bits.fflags.valid
invalidate io.core.exe[0].fresp.bits.predicated
invalidate io.core.exe[0].fresp.bits.data
invalidate io.core.exe[0].fresp.bits.uop.debug_tsrc
invalidate io.core.exe[0].fresp.bits.uop.debug_fsrc
invalidate io.core.exe[0].fresp.bits.uop.bp_xcpt_if
invalidate io.core.exe[0].fresp.bits.uop.bp_debug_if
invalidate io.core.exe[0].fresp.bits.uop.xcpt_ma_if
invalidate io.core.exe[0].fresp.bits.uop.xcpt_ae_if
invalidate io.core.exe[0].fresp.bits.uop.xcpt_pf_if
invalidate io.core.exe[0].fresp.bits.uop.fp_single
invalidate io.core.exe[0].fresp.bits.uop.fp_val
invalidate io.core.exe[0].fresp.bits.uop.frs3_en
invalidate io.core.exe[0].fresp.bits.uop.lrs2_rtype
invalidate io.core.exe[0].fresp.bits.uop.lrs1_rtype
invalidate io.core.exe[0].fresp.bits.uop.dst_rtype
invalidate io.core.exe[0].fresp.bits.uop.ldst_val
invalidate io.core.exe[0].fresp.bits.uop.lrs3
invalidate io.core.exe[0].fresp.bits.uop.lrs2
invalidate io.core.exe[0].fresp.bits.uop.lrs1
invalidate io.core.exe[0].fresp.bits.uop.ldst
invalidate io.core.exe[0].fresp.bits.uop.ldst_is_rs1
invalidate io.core.exe[0].fresp.bits.uop.flush_on_commit
invalidate io.core.exe[0].fresp.bits.uop.is_unique
invalidate io.core.exe[0].fresp.bits.uop.is_sys_pc2epc
invalidate io.core.exe[0].fresp.bits.uop.uses_stq
invalidate io.core.exe[0].fresp.bits.uop.uses_ldq
invalidate io.core.exe[0].fresp.bits.uop.is_amo
invalidate io.core.exe[0].fresp.bits.uop.is_fencei
invalidate io.core.exe[0].fresp.bits.uop.is_fence
invalidate io.core.exe[0].fresp.bits.uop.mem_signed
invalidate io.core.exe[0].fresp.bits.uop.mem_size
invalidate io.core.exe[0].fresp.bits.uop.mem_cmd
invalidate io.core.exe[0].fresp.bits.uop.bypassable
invalidate io.core.exe[0].fresp.bits.uop.exc_cause
invalidate io.core.exe[0].fresp.bits.uop.exception
invalidate io.core.exe[0].fresp.bits.uop.stale_pdst
invalidate io.core.exe[0].fresp.bits.uop.ppred_busy
invalidate io.core.exe[0].fresp.bits.uop.prs3_busy
invalidate io.core.exe[0].fresp.bits.uop.prs2_busy
invalidate io.core.exe[0].fresp.bits.uop.prs1_busy
invalidate io.core.exe[0].fresp.bits.uop.ppred
invalidate io.core.exe[0].fresp.bits.uop.prs3
invalidate io.core.exe[0].fresp.bits.uop.prs2
invalidate io.core.exe[0].fresp.bits.uop.prs1
invalidate io.core.exe[0].fresp.bits.uop.pdst
invalidate io.core.exe[0].fresp.bits.uop.rxq_idx
invalidate io.core.exe[0].fresp.bits.uop.stq_idx
invalidate io.core.exe[0].fresp.bits.uop.ldq_idx
invalidate io.core.exe[0].fresp.bits.uop.rob_idx
invalidate io.core.exe[0].fresp.bits.uop.csr_addr
invalidate io.core.exe[0].fresp.bits.uop.imm_packed
invalidate io.core.exe[0].fresp.bits.uop.taken
invalidate io.core.exe[0].fresp.bits.uop.pc_lob
invalidate io.core.exe[0].fresp.bits.uop.edge_inst
invalidate io.core.exe[0].fresp.bits.uop.ftq_idx
invalidate io.core.exe[0].fresp.bits.uop.br_tag
invalidate io.core.exe[0].fresp.bits.uop.br_mask
invalidate io.core.exe[0].fresp.bits.uop.is_sfb
invalidate io.core.exe[0].fresp.bits.uop.is_jal
invalidate io.core.exe[0].fresp.bits.uop.is_jalr
invalidate io.core.exe[0].fresp.bits.uop.is_br
invalidate io.core.exe[0].fresp.bits.uop.iw_p2_poisoned
invalidate io.core.exe[0].fresp.bits.uop.iw_p1_poisoned
invalidate io.core.exe[0].fresp.bits.uop.iw_state
invalidate io.core.exe[0].fresp.bits.uop.ctrl.is_std
invalidate io.core.exe[0].fresp.bits.uop.ctrl.is_sta
invalidate io.core.exe[0].fresp.bits.uop.ctrl.is_load
invalidate io.core.exe[0].fresp.bits.uop.ctrl.csr_cmd
invalidate io.core.exe[0].fresp.bits.uop.ctrl.fcn_dw
invalidate io.core.exe[0].fresp.bits.uop.ctrl.op_fcn
invalidate io.core.exe[0].fresp.bits.uop.ctrl.imm_sel
invalidate io.core.exe[0].fresp.bits.uop.ctrl.op2_sel
invalidate io.core.exe[0].fresp.bits.uop.ctrl.op1_sel
invalidate io.core.exe[0].fresp.bits.uop.ctrl.br_type
invalidate io.core.exe[0].fresp.bits.uop.fu_code
invalidate io.core.exe[0].fresp.bits.uop.iq_type
invalidate io.core.exe[0].fresp.bits.uop.debug_pc
invalidate io.core.exe[0].fresp.bits.uop.is_rvc
invalidate io.core.exe[0].fresp.bits.uop.debug_inst
invalidate io.core.exe[0].fresp.bits.uop.inst
invalidate io.core.exe[0].fresp.bits.uop.uopc
wire _dmem_resp_fired_WIRE : UInt<1>[1]
connect _dmem_resp_fired_WIRE[0], UInt<1>(0h0)
wire dmem_resp_fired : UInt<1>[1]
connect dmem_resp_fired, _dmem_resp_fired_WIRE
when io.dmem.nack[0].valid :
when io.dmem.nack[0].bits.is_hella :
node _T_1669 = eq(hella_state, UInt<3>(0h4))
node _T_1670 = eq(hella_state, UInt<3>(0h6))
node _T_1671 = or(_T_1669, _T_1670)
node _T_1672 = asUInt(reset)
node _T_1673 = eq(_T_1672, UInt<1>(0h0))
when _T_1673 :
node _T_1674 = eq(_T_1671, UInt<1>(0h0))
when _T_1674 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1291 assert(hella_state === h_wait || hella_state === h_dead)\n") : printf_32
assert(clock, _T_1671, UInt<1>(0h1), "") : assert_32
else :
when io.dmem.nack[0].bits.uop.uses_ldq :
node _T_1675 = asUInt(reset)
node _T_1676 = eq(_T_1675, UInt<1>(0h0))
when _T_1676 :
node _T_1677 = eq(ldq[io.dmem.nack[0].bits.uop.ldq_idx].bits.executed, UInt<1>(0h0))
when _T_1677 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1295 assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed)\n") : printf_33
assert(clock, ldq[io.dmem.nack[0].bits.uop.ldq_idx].bits.executed, UInt<1>(0h1), "") : assert_33
connect ldq[io.dmem.nack[0].bits.uop.ldq_idx].bits.executed, UInt<1>(0h0)
connect nacking_loads[io.dmem.nack[0].bits.uop.ldq_idx], UInt<1>(0h1)
else :
node _T_1678 = asUInt(reset)
node _T_1679 = eq(_T_1678, UInt<1>(0h0))
when _T_1679 :
node _T_1680 = eq(io.dmem.nack[0].bits.uop.uses_stq, UInt<1>(0h0))
when _T_1680 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1301 assert(io.dmem.nack(w).bits.uop.uses_stq)\n") : printf_34
assert(clock, io.dmem.nack[0].bits.uop.uses_stq, UInt<1>(0h1), "") : assert_34
node _T_1681 = lt(io.dmem.nack[0].bits.uop.stq_idx, stq_execute_head)
node _T_1682 = lt(io.dmem.nack[0].bits.uop.stq_idx, stq_head)
node _T_1683 = xor(_T_1681, _T_1682)
node _T_1684 = lt(stq_execute_head, stq_head)
node _T_1685 = xor(_T_1683, _T_1684)
when _T_1685 :
connect stq_execute_head, io.dmem.nack[0].bits.uop.stq_idx
when io.dmem.resp[0].valid :
when io.dmem.resp[0].bits.uop.uses_ldq :
node _T_1686 = eq(io.dmem.resp[0].bits.is_hella, UInt<1>(0h0))
node _T_1687 = asUInt(reset)
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
when _T_1688 :
node _T_1689 = eq(_T_1686, UInt<1>(0h0))
when _T_1689 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1312 assert(!io.dmem.resp(w).bits.is_hella)\n") : printf_35
assert(clock, _T_1686, UInt<1>(0h1), "") : assert_35
node send_iresp = eq(ldq[io.dmem.resp[0].bits.uop.ldq_idx].bits.uop.dst_rtype, UInt<2>(0h0))
node send_fresp = eq(ldq[io.dmem.resp[0].bits.uop.ldq_idx].bits.uop.dst_rtype, UInt<2>(0h1))
connect io.core.exe[0].iresp.bits.uop, ldq[io.dmem.resp[0].bits.uop.ldq_idx].bits.uop
connect io.core.exe[0].fresp.bits.uop, ldq[io.dmem.resp[0].bits.uop.ldq_idx].bits.uop
connect io.core.exe[0].iresp.valid, send_iresp
connect io.core.exe[0].iresp.bits.data, io.dmem.resp[0].bits.data
connect io.core.exe[0].fresp.valid, send_fresp
connect io.core.exe[0].fresp.bits.data, io.dmem.resp[0].bits.data
node _T_1690 = xor(send_iresp, send_fresp)
node _T_1691 = asUInt(reset)
node _T_1692 = eq(_T_1691, UInt<1>(0h0))
when _T_1692 :
node _T_1693 = eq(_T_1690, UInt<1>(0h0))
when _T_1693 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1324 assert(send_iresp ^ send_fresp)\n") : printf_36
assert(clock, _T_1690, UInt<1>(0h1), "") : assert_36
connect dmem_resp_fired[0], UInt<1>(0h1)
node _ldq_bits_succeeded_T = or(io.core.exe[0].iresp.valid, io.core.exe[0].fresp.valid)
connect ldq[io.dmem.resp[0].bits.uop.ldq_idx].bits.succeeded, _ldq_bits_succeeded_T
connect ldq[io.dmem.resp[0].bits.uop.ldq_idx].bits.debug_wb_data, io.dmem.resp[0].bits.data
else :
when io.dmem.resp[0].bits.uop.uses_stq :
node _T_1694 = eq(io.dmem.resp[0].bits.is_hella, UInt<1>(0h0))
node _T_1695 = asUInt(reset)
node _T_1696 = eq(_T_1695, UInt<1>(0h0))
when _T_1696 :
node _T_1697 = eq(_T_1694, UInt<1>(0h0))
when _T_1697 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1332 assert(!io.dmem.resp(w).bits.is_hella)\n") : printf_37
assert(clock, _T_1694, UInt<1>(0h1), "") : assert_37
connect stq[io.dmem.resp[0].bits.uop.stq_idx].bits.succeeded, UInt<1>(0h1)
when io.dmem.resp[0].bits.uop.is_amo :
connect dmem_resp_fired[0], UInt<1>(0h1)
connect io.core.exe[0].iresp.valid, UInt<1>(0h1)
connect io.core.exe[0].iresp.bits.uop, stq[io.dmem.resp[0].bits.uop.stq_idx].bits.uop
connect io.core.exe[0].iresp.bits.data, io.dmem.resp[0].bits.data
connect stq[io.dmem.resp[0].bits.uop.stq_idx].bits.debug_wb_data, io.dmem.resp[0].bits.data
node _T_1698 = and(dmem_resp_fired[0], wb_forward_valid[0])
when _T_1698 :
skip
else :
node _T_1699 = eq(dmem_resp_fired[0], UInt<1>(0h0))
node _T_1700 = and(_T_1699, wb_forward_valid[0])
when _T_1700 :
node _forward_uop_T = or(wb_forward_ldq_idx[0], UInt<5>(0h0))
node _forward_uop_T_1 = bits(_forward_uop_T, 4, 0)
node _live_T = and(io.core.brupdate.b1.mispredict_mask, ldq[_forward_uop_T_1].bits.uop.br_mask)
node _live_T_1 = neq(_live_T, UInt<1>(0h0))
node live = eq(_live_T_1, UInt<1>(0h0))
wire size : UInt<2>
connect size, stq[wb_forward_stq_idx[0]].bits.uop.mem_size
node _T_1701 = eq(size, UInt<1>(0h0))
node _T_1702 = bits(stq[wb_forward_stq_idx[0]].bits.data.bits, 7, 0)
node _T_1703 = cat(_T_1702, _T_1702)
node _T_1704 = cat(_T_1703, _T_1703)
node _T_1705 = cat(_T_1704, _T_1704)
node _T_1706 = eq(size, UInt<1>(0h1))
node _T_1707 = bits(stq[wb_forward_stq_idx[0]].bits.data.bits, 15, 0)
node _T_1708 = cat(_T_1707, _T_1707)
node _T_1709 = cat(_T_1708, _T_1708)
node _T_1710 = eq(size, UInt<2>(0h2))
node _T_1711 = bits(stq[wb_forward_stq_idx[0]].bits.data.bits, 31, 0)
node _T_1712 = cat(_T_1711, _T_1711)
node _T_1713 = mux(_T_1710, _T_1712, stq[wb_forward_stq_idx[0]].bits.data.bits)
node _T_1714 = mux(_T_1706, _T_1709, _T_1713)
node _T_1715 = mux(_T_1701, _T_1705, _T_1714)
wire size_1 : UInt<2>
connect size_1, ldq[_forward_uop_T_1].bits.uop.mem_size
node _io_core_exe_0_iresp_valid_T = eq(ldq[_forward_uop_T_1].bits.uop.dst_rtype, UInt<2>(0h0))
node _io_core_exe_0_iresp_valid_T_1 = and(_io_core_exe_0_iresp_valid_T, stq[wb_forward_stq_idx[0]].bits.data.valid)
node _io_core_exe_0_iresp_valid_T_2 = and(_io_core_exe_0_iresp_valid_T_1, live)
connect io.core.exe[0].iresp.valid, _io_core_exe_0_iresp_valid_T_2
node _io_core_exe_0_fresp_valid_T = eq(ldq[_forward_uop_T_1].bits.uop.dst_rtype, UInt<2>(0h1))
node _io_core_exe_0_fresp_valid_T_1 = and(_io_core_exe_0_fresp_valid_T, stq[wb_forward_stq_idx[0]].bits.data.valid)
node _io_core_exe_0_fresp_valid_T_2 = and(_io_core_exe_0_fresp_valid_T_1, live)
connect io.core.exe[0].fresp.valid, _io_core_exe_0_fresp_valid_T_2
connect io.core.exe[0].iresp.bits.uop, ldq[_forward_uop_T_1].bits.uop
connect io.core.exe[0].fresp.bits.uop, ldq[_forward_uop_T_1].bits.uop
node _io_core_exe_0_iresp_bits_data_shifted_T = bits(wb_forward_ld_addr[0], 2, 2)
node _io_core_exe_0_iresp_bits_data_shifted_T_1 = bits(_T_1715, 63, 32)
node _io_core_exe_0_iresp_bits_data_shifted_T_2 = bits(_T_1715, 31, 0)
node io_core_exe_0_iresp_bits_data_shifted = mux(_io_core_exe_0_iresp_bits_data_shifted_T, _io_core_exe_0_iresp_bits_data_shifted_T_1, _io_core_exe_0_iresp_bits_data_shifted_T_2)
node io_core_exe_0_iresp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_core_exe_0_iresp_bits_data_zeroed = mux(io_core_exe_0_iresp_bits_data_doZero, UInt<1>(0h0), io_core_exe_0_iresp_bits_data_shifted)
node _io_core_exe_0_iresp_bits_data_T = eq(size_1, UInt<2>(0h2))
node _io_core_exe_0_iresp_bits_data_T_1 = or(_io_core_exe_0_iresp_bits_data_T, io_core_exe_0_iresp_bits_data_doZero)
node _io_core_exe_0_iresp_bits_data_T_2 = bits(io_core_exe_0_iresp_bits_data_zeroed, 31, 31)
node _io_core_exe_0_iresp_bits_data_T_3 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _io_core_exe_0_iresp_bits_data_T_2)
node _io_core_exe_0_iresp_bits_data_T_4 = mux(_io_core_exe_0_iresp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_core_exe_0_iresp_bits_data_T_5 = bits(_T_1715, 63, 32)
node _io_core_exe_0_iresp_bits_data_T_6 = mux(_io_core_exe_0_iresp_bits_data_T_1, _io_core_exe_0_iresp_bits_data_T_4, _io_core_exe_0_iresp_bits_data_T_5)
node _io_core_exe_0_iresp_bits_data_T_7 = cat(_io_core_exe_0_iresp_bits_data_T_6, io_core_exe_0_iresp_bits_data_zeroed)
node _io_core_exe_0_iresp_bits_data_shifted_T_3 = bits(wb_forward_ld_addr[0], 1, 1)
node _io_core_exe_0_iresp_bits_data_shifted_T_4 = bits(_io_core_exe_0_iresp_bits_data_T_7, 31, 16)
node _io_core_exe_0_iresp_bits_data_shifted_T_5 = bits(_io_core_exe_0_iresp_bits_data_T_7, 15, 0)
node io_core_exe_0_iresp_bits_data_shifted_1 = mux(_io_core_exe_0_iresp_bits_data_shifted_T_3, _io_core_exe_0_iresp_bits_data_shifted_T_4, _io_core_exe_0_iresp_bits_data_shifted_T_5)
node io_core_exe_0_iresp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_core_exe_0_iresp_bits_data_zeroed_1 = mux(io_core_exe_0_iresp_bits_data_doZero_1, UInt<1>(0h0), io_core_exe_0_iresp_bits_data_shifted_1)
node _io_core_exe_0_iresp_bits_data_T_8 = eq(size_1, UInt<1>(0h1))
node _io_core_exe_0_iresp_bits_data_T_9 = or(_io_core_exe_0_iresp_bits_data_T_8, io_core_exe_0_iresp_bits_data_doZero_1)
node _io_core_exe_0_iresp_bits_data_T_10 = bits(io_core_exe_0_iresp_bits_data_zeroed_1, 15, 15)
node _io_core_exe_0_iresp_bits_data_T_11 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _io_core_exe_0_iresp_bits_data_T_10)
node _io_core_exe_0_iresp_bits_data_T_12 = mux(_io_core_exe_0_iresp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_core_exe_0_iresp_bits_data_T_13 = bits(_io_core_exe_0_iresp_bits_data_T_7, 63, 16)
node _io_core_exe_0_iresp_bits_data_T_14 = mux(_io_core_exe_0_iresp_bits_data_T_9, _io_core_exe_0_iresp_bits_data_T_12, _io_core_exe_0_iresp_bits_data_T_13)
node _io_core_exe_0_iresp_bits_data_T_15 = cat(_io_core_exe_0_iresp_bits_data_T_14, io_core_exe_0_iresp_bits_data_zeroed_1)
node _io_core_exe_0_iresp_bits_data_shifted_T_6 = bits(wb_forward_ld_addr[0], 0, 0)
node _io_core_exe_0_iresp_bits_data_shifted_T_7 = bits(_io_core_exe_0_iresp_bits_data_T_15, 15, 8)
node _io_core_exe_0_iresp_bits_data_shifted_T_8 = bits(_io_core_exe_0_iresp_bits_data_T_15, 7, 0)
node io_core_exe_0_iresp_bits_data_shifted_2 = mux(_io_core_exe_0_iresp_bits_data_shifted_T_6, _io_core_exe_0_iresp_bits_data_shifted_T_7, _io_core_exe_0_iresp_bits_data_shifted_T_8)
node io_core_exe_0_iresp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_core_exe_0_iresp_bits_data_zeroed_2 = mux(io_core_exe_0_iresp_bits_data_doZero_2, UInt<1>(0h0), io_core_exe_0_iresp_bits_data_shifted_2)
node _io_core_exe_0_iresp_bits_data_T_16 = eq(size_1, UInt<1>(0h0))
node _io_core_exe_0_iresp_bits_data_T_17 = or(_io_core_exe_0_iresp_bits_data_T_16, io_core_exe_0_iresp_bits_data_doZero_2)
node _io_core_exe_0_iresp_bits_data_T_18 = bits(io_core_exe_0_iresp_bits_data_zeroed_2, 7, 7)
node _io_core_exe_0_iresp_bits_data_T_19 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _io_core_exe_0_iresp_bits_data_T_18)
node _io_core_exe_0_iresp_bits_data_T_20 = mux(_io_core_exe_0_iresp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_core_exe_0_iresp_bits_data_T_21 = bits(_io_core_exe_0_iresp_bits_data_T_15, 63, 8)
node _io_core_exe_0_iresp_bits_data_T_22 = mux(_io_core_exe_0_iresp_bits_data_T_17, _io_core_exe_0_iresp_bits_data_T_20, _io_core_exe_0_iresp_bits_data_T_21)
node _io_core_exe_0_iresp_bits_data_T_23 = cat(_io_core_exe_0_iresp_bits_data_T_22, io_core_exe_0_iresp_bits_data_zeroed_2)
connect io.core.exe[0].iresp.bits.data, _io_core_exe_0_iresp_bits_data_T_23
node _io_core_exe_0_fresp_bits_data_shifted_T = bits(wb_forward_ld_addr[0], 2, 2)
node _io_core_exe_0_fresp_bits_data_shifted_T_1 = bits(_T_1715, 63, 32)
node _io_core_exe_0_fresp_bits_data_shifted_T_2 = bits(_T_1715, 31, 0)
node io_core_exe_0_fresp_bits_data_shifted = mux(_io_core_exe_0_fresp_bits_data_shifted_T, _io_core_exe_0_fresp_bits_data_shifted_T_1, _io_core_exe_0_fresp_bits_data_shifted_T_2)
node io_core_exe_0_fresp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_core_exe_0_fresp_bits_data_zeroed = mux(io_core_exe_0_fresp_bits_data_doZero, UInt<1>(0h0), io_core_exe_0_fresp_bits_data_shifted)
node _io_core_exe_0_fresp_bits_data_T = eq(size_1, UInt<2>(0h2))
node _io_core_exe_0_fresp_bits_data_T_1 = or(_io_core_exe_0_fresp_bits_data_T, io_core_exe_0_fresp_bits_data_doZero)
node _io_core_exe_0_fresp_bits_data_T_2 = bits(io_core_exe_0_fresp_bits_data_zeroed, 31, 31)
node _io_core_exe_0_fresp_bits_data_T_3 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _io_core_exe_0_fresp_bits_data_T_2)
node _io_core_exe_0_fresp_bits_data_T_4 = mux(_io_core_exe_0_fresp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_core_exe_0_fresp_bits_data_T_5 = bits(_T_1715, 63, 32)
node _io_core_exe_0_fresp_bits_data_T_6 = mux(_io_core_exe_0_fresp_bits_data_T_1, _io_core_exe_0_fresp_bits_data_T_4, _io_core_exe_0_fresp_bits_data_T_5)
node _io_core_exe_0_fresp_bits_data_T_7 = cat(_io_core_exe_0_fresp_bits_data_T_6, io_core_exe_0_fresp_bits_data_zeroed)
node _io_core_exe_0_fresp_bits_data_shifted_T_3 = bits(wb_forward_ld_addr[0], 1, 1)
node _io_core_exe_0_fresp_bits_data_shifted_T_4 = bits(_io_core_exe_0_fresp_bits_data_T_7, 31, 16)
node _io_core_exe_0_fresp_bits_data_shifted_T_5 = bits(_io_core_exe_0_fresp_bits_data_T_7, 15, 0)
node io_core_exe_0_fresp_bits_data_shifted_1 = mux(_io_core_exe_0_fresp_bits_data_shifted_T_3, _io_core_exe_0_fresp_bits_data_shifted_T_4, _io_core_exe_0_fresp_bits_data_shifted_T_5)
node io_core_exe_0_fresp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_core_exe_0_fresp_bits_data_zeroed_1 = mux(io_core_exe_0_fresp_bits_data_doZero_1, UInt<1>(0h0), io_core_exe_0_fresp_bits_data_shifted_1)
node _io_core_exe_0_fresp_bits_data_T_8 = eq(size_1, UInt<1>(0h1))
node _io_core_exe_0_fresp_bits_data_T_9 = or(_io_core_exe_0_fresp_bits_data_T_8, io_core_exe_0_fresp_bits_data_doZero_1)
node _io_core_exe_0_fresp_bits_data_T_10 = bits(io_core_exe_0_fresp_bits_data_zeroed_1, 15, 15)
node _io_core_exe_0_fresp_bits_data_T_11 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _io_core_exe_0_fresp_bits_data_T_10)
node _io_core_exe_0_fresp_bits_data_T_12 = mux(_io_core_exe_0_fresp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_core_exe_0_fresp_bits_data_T_13 = bits(_io_core_exe_0_fresp_bits_data_T_7, 63, 16)
node _io_core_exe_0_fresp_bits_data_T_14 = mux(_io_core_exe_0_fresp_bits_data_T_9, _io_core_exe_0_fresp_bits_data_T_12, _io_core_exe_0_fresp_bits_data_T_13)
node _io_core_exe_0_fresp_bits_data_T_15 = cat(_io_core_exe_0_fresp_bits_data_T_14, io_core_exe_0_fresp_bits_data_zeroed_1)
node _io_core_exe_0_fresp_bits_data_shifted_T_6 = bits(wb_forward_ld_addr[0], 0, 0)
node _io_core_exe_0_fresp_bits_data_shifted_T_7 = bits(_io_core_exe_0_fresp_bits_data_T_15, 15, 8)
node _io_core_exe_0_fresp_bits_data_shifted_T_8 = bits(_io_core_exe_0_fresp_bits_data_T_15, 7, 0)
node io_core_exe_0_fresp_bits_data_shifted_2 = mux(_io_core_exe_0_fresp_bits_data_shifted_T_6, _io_core_exe_0_fresp_bits_data_shifted_T_7, _io_core_exe_0_fresp_bits_data_shifted_T_8)
node io_core_exe_0_fresp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_core_exe_0_fresp_bits_data_zeroed_2 = mux(io_core_exe_0_fresp_bits_data_doZero_2, UInt<1>(0h0), io_core_exe_0_fresp_bits_data_shifted_2)
node _io_core_exe_0_fresp_bits_data_T_16 = eq(size_1, UInt<1>(0h0))
node _io_core_exe_0_fresp_bits_data_T_17 = or(_io_core_exe_0_fresp_bits_data_T_16, io_core_exe_0_fresp_bits_data_doZero_2)
node _io_core_exe_0_fresp_bits_data_T_18 = bits(io_core_exe_0_fresp_bits_data_zeroed_2, 7, 7)
node _io_core_exe_0_fresp_bits_data_T_19 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _io_core_exe_0_fresp_bits_data_T_18)
node _io_core_exe_0_fresp_bits_data_T_20 = mux(_io_core_exe_0_fresp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_core_exe_0_fresp_bits_data_T_21 = bits(_io_core_exe_0_fresp_bits_data_T_15, 63, 8)
node _io_core_exe_0_fresp_bits_data_T_22 = mux(_io_core_exe_0_fresp_bits_data_T_17, _io_core_exe_0_fresp_bits_data_T_20, _io_core_exe_0_fresp_bits_data_T_21)
node _io_core_exe_0_fresp_bits_data_T_23 = cat(_io_core_exe_0_fresp_bits_data_T_22, io_core_exe_0_fresp_bits_data_zeroed_2)
connect io.core.exe[0].fresp.bits.data, _io_core_exe_0_fresp_bits_data_T_23
node _T_1716 = and(stq[wb_forward_stq_idx[0]].bits.data.valid, live)
when _T_1716 :
node _T_1717 = or(wb_forward_ldq_idx[0], UInt<5>(0h0))
node _T_1718 = bits(_T_1717, 4, 0)
connect ldq[_T_1718].bits.succeeded, stq[wb_forward_stq_idx[0]].bits.data.valid
node _T_1719 = or(wb_forward_ldq_idx[0], UInt<5>(0h0))
node _T_1720 = bits(_T_1719, 4, 0)
connect ldq[_T_1720].bits.forward_std_val, UInt<1>(0h1)
node _T_1721 = or(wb_forward_ldq_idx[0], UInt<5>(0h0))
node _T_1722 = bits(_T_1721, 4, 0)
connect ldq[_T_1722].bits.forward_stq_idx, wb_forward_stq_idx[0]
node _T_1723 = or(wb_forward_ldq_idx[0], UInt<5>(0h0))
node _T_1724 = bits(_T_1723, 4, 0)
node _ldq_bits_debug_wb_data_shifted_T = bits(wb_forward_ld_addr[0], 2, 2)
node _ldq_bits_debug_wb_data_shifted_T_1 = bits(_T_1715, 63, 32)
node _ldq_bits_debug_wb_data_shifted_T_2 = bits(_T_1715, 31, 0)
node ldq_bits_debug_wb_data_shifted = mux(_ldq_bits_debug_wb_data_shifted_T, _ldq_bits_debug_wb_data_shifted_T_1, _ldq_bits_debug_wb_data_shifted_T_2)
node ldq_bits_debug_wb_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node ldq_bits_debug_wb_data_zeroed = mux(ldq_bits_debug_wb_data_doZero, UInt<1>(0h0), ldq_bits_debug_wb_data_shifted)
node _ldq_bits_debug_wb_data_T = eq(size_1, UInt<2>(0h2))
node _ldq_bits_debug_wb_data_T_1 = or(_ldq_bits_debug_wb_data_T, ldq_bits_debug_wb_data_doZero)
node _ldq_bits_debug_wb_data_T_2 = bits(ldq_bits_debug_wb_data_zeroed, 31, 31)
node _ldq_bits_debug_wb_data_T_3 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _ldq_bits_debug_wb_data_T_2)
node _ldq_bits_debug_wb_data_T_4 = mux(_ldq_bits_debug_wb_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _ldq_bits_debug_wb_data_T_5 = bits(_T_1715, 63, 32)
node _ldq_bits_debug_wb_data_T_6 = mux(_ldq_bits_debug_wb_data_T_1, _ldq_bits_debug_wb_data_T_4, _ldq_bits_debug_wb_data_T_5)
node _ldq_bits_debug_wb_data_T_7 = cat(_ldq_bits_debug_wb_data_T_6, ldq_bits_debug_wb_data_zeroed)
node _ldq_bits_debug_wb_data_shifted_T_3 = bits(wb_forward_ld_addr[0], 1, 1)
node _ldq_bits_debug_wb_data_shifted_T_4 = bits(_ldq_bits_debug_wb_data_T_7, 31, 16)
node _ldq_bits_debug_wb_data_shifted_T_5 = bits(_ldq_bits_debug_wb_data_T_7, 15, 0)
node ldq_bits_debug_wb_data_shifted_1 = mux(_ldq_bits_debug_wb_data_shifted_T_3, _ldq_bits_debug_wb_data_shifted_T_4, _ldq_bits_debug_wb_data_shifted_T_5)
node ldq_bits_debug_wb_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node ldq_bits_debug_wb_data_zeroed_1 = mux(ldq_bits_debug_wb_data_doZero_1, UInt<1>(0h0), ldq_bits_debug_wb_data_shifted_1)
node _ldq_bits_debug_wb_data_T_8 = eq(size_1, UInt<1>(0h1))
node _ldq_bits_debug_wb_data_T_9 = or(_ldq_bits_debug_wb_data_T_8, ldq_bits_debug_wb_data_doZero_1)
node _ldq_bits_debug_wb_data_T_10 = bits(ldq_bits_debug_wb_data_zeroed_1, 15, 15)
node _ldq_bits_debug_wb_data_T_11 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _ldq_bits_debug_wb_data_T_10)
node _ldq_bits_debug_wb_data_T_12 = mux(_ldq_bits_debug_wb_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _ldq_bits_debug_wb_data_T_13 = bits(_ldq_bits_debug_wb_data_T_7, 63, 16)
node _ldq_bits_debug_wb_data_T_14 = mux(_ldq_bits_debug_wb_data_T_9, _ldq_bits_debug_wb_data_T_12, _ldq_bits_debug_wb_data_T_13)
node _ldq_bits_debug_wb_data_T_15 = cat(_ldq_bits_debug_wb_data_T_14, ldq_bits_debug_wb_data_zeroed_1)
node _ldq_bits_debug_wb_data_shifted_T_6 = bits(wb_forward_ld_addr[0], 0, 0)
node _ldq_bits_debug_wb_data_shifted_T_7 = bits(_ldq_bits_debug_wb_data_T_15, 15, 8)
node _ldq_bits_debug_wb_data_shifted_T_8 = bits(_ldq_bits_debug_wb_data_T_15, 7, 0)
node ldq_bits_debug_wb_data_shifted_2 = mux(_ldq_bits_debug_wb_data_shifted_T_6, _ldq_bits_debug_wb_data_shifted_T_7, _ldq_bits_debug_wb_data_shifted_T_8)
node ldq_bits_debug_wb_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node ldq_bits_debug_wb_data_zeroed_2 = mux(ldq_bits_debug_wb_data_doZero_2, UInt<1>(0h0), ldq_bits_debug_wb_data_shifted_2)
node _ldq_bits_debug_wb_data_T_16 = eq(size_1, UInt<1>(0h0))
node _ldq_bits_debug_wb_data_T_17 = or(_ldq_bits_debug_wb_data_T_16, ldq_bits_debug_wb_data_doZero_2)
node _ldq_bits_debug_wb_data_T_18 = bits(ldq_bits_debug_wb_data_zeroed_2, 7, 7)
node _ldq_bits_debug_wb_data_T_19 = and(ldq[_forward_uop_T_1].bits.uop.mem_signed, _ldq_bits_debug_wb_data_T_18)
node _ldq_bits_debug_wb_data_T_20 = mux(_ldq_bits_debug_wb_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _ldq_bits_debug_wb_data_T_21 = bits(_ldq_bits_debug_wb_data_T_15, 63, 8)
node _ldq_bits_debug_wb_data_T_22 = mux(_ldq_bits_debug_wb_data_T_17, _ldq_bits_debug_wb_data_T_20, _ldq_bits_debug_wb_data_T_21)
node _ldq_bits_debug_wb_data_T_23 = cat(_ldq_bits_debug_wb_data_T_22, ldq_bits_debug_wb_data_zeroed_2)
connect ldq[_T_1724].bits.debug_wb_data, _ldq_bits_debug_wb_data_T_23
reg io_core_ld_miss_REG : UInt<1>, clock
connect io_core_ld_miss_REG, io.core.spec_ld_wakeup[0].valid
connect io.core.ld_miss, io_core_ld_miss_REG
reg spec_ld_succeed_REG : UInt<1>, clock
connect spec_ld_succeed_REG, io.core.spec_ld_wakeup[0].valid
node _spec_ld_succeed_T = eq(spec_ld_succeed_REG, UInt<1>(0h0))
reg spec_ld_succeed_REG_1 : UInt, clock
connect spec_ld_succeed_REG_1, mem_incoming_uop[0].ldq_idx
node _spec_ld_succeed_T_1 = eq(io.core.exe[0].iresp.bits.uop.ldq_idx, spec_ld_succeed_REG_1)
node _spec_ld_succeed_T_2 = and(io.core.exe[0].iresp.valid, _spec_ld_succeed_T_1)
node _spec_ld_succeed_T_3 = or(_spec_ld_succeed_T, _spec_ld_succeed_T_2)
wire _spec_ld_succeed_WIRE : UInt<1>[1]
connect _spec_ld_succeed_WIRE[0], _spec_ld_succeed_T_3
when _spec_ld_succeed_WIRE[0] :
connect io.core.ld_miss, UInt<1>(0h0)
wire st_brkilled_mask : UInt<1>[24]
connect st_brkilled_mask[0], UInt<1>(0h0)
when stq[0].valid :
node _stq_0_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_0_bits_uop_br_mask_T_1 = and(stq[0].bits.uop.br_mask, _stq_0_bits_uop_br_mask_T)
connect stq[0].bits.uop.br_mask, _stq_0_bits_uop_br_mask_T_1
node _T_1725 = and(io.core.brupdate.b1.mispredict_mask, stq[0].bits.uop.br_mask)
node _T_1726 = neq(_T_1725, UInt<1>(0h0))
when _T_1726 :
connect stq[0].valid, UInt<1>(0h0)
connect stq[0].bits.addr.valid, UInt<1>(0h0)
connect stq[0].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[0], UInt<1>(0h1)
node _T_1727 = and(io.core.brupdate.b1.mispredict_mask, stq[0].bits.uop.br_mask)
node _T_1728 = neq(_T_1727, UInt<1>(0h0))
node _T_1729 = and(_T_1728, stq[0].valid)
node _T_1730 = and(_T_1729, stq[0].bits.committed)
node _T_1731 = eq(_T_1730, UInt<1>(0h0))
node _T_1732 = asUInt(reset)
node _T_1733 = eq(_T_1732, UInt<1>(0h0))
when _T_1733 :
node _T_1734 = eq(_T_1731, UInt<1>(0h0))
when _T_1734 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_38
assert(clock, _T_1731, UInt<1>(0h1), "") : assert_38
connect st_brkilled_mask[1], UInt<1>(0h0)
when stq[1].valid :
node _stq_1_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_1_bits_uop_br_mask_T_1 = and(stq[1].bits.uop.br_mask, _stq_1_bits_uop_br_mask_T)
connect stq[1].bits.uop.br_mask, _stq_1_bits_uop_br_mask_T_1
node _T_1735 = and(io.core.brupdate.b1.mispredict_mask, stq[1].bits.uop.br_mask)
node _T_1736 = neq(_T_1735, UInt<1>(0h0))
when _T_1736 :
connect stq[1].valid, UInt<1>(0h0)
connect stq[1].bits.addr.valid, UInt<1>(0h0)
connect stq[1].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[1], UInt<1>(0h1)
node _T_1737 = and(io.core.brupdate.b1.mispredict_mask, stq[1].bits.uop.br_mask)
node _T_1738 = neq(_T_1737, UInt<1>(0h0))
node _T_1739 = and(_T_1738, stq[1].valid)
node _T_1740 = and(_T_1739, stq[1].bits.committed)
node _T_1741 = eq(_T_1740, UInt<1>(0h0))
node _T_1742 = asUInt(reset)
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
when _T_1743 :
node _T_1744 = eq(_T_1741, UInt<1>(0h0))
when _T_1744 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_39
assert(clock, _T_1741, UInt<1>(0h1), "") : assert_39
connect st_brkilled_mask[2], UInt<1>(0h0)
when stq[2].valid :
node _stq_2_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_2_bits_uop_br_mask_T_1 = and(stq[2].bits.uop.br_mask, _stq_2_bits_uop_br_mask_T)
connect stq[2].bits.uop.br_mask, _stq_2_bits_uop_br_mask_T_1
node _T_1745 = and(io.core.brupdate.b1.mispredict_mask, stq[2].bits.uop.br_mask)
node _T_1746 = neq(_T_1745, UInt<1>(0h0))
when _T_1746 :
connect stq[2].valid, UInt<1>(0h0)
connect stq[2].bits.addr.valid, UInt<1>(0h0)
connect stq[2].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[2], UInt<1>(0h1)
node _T_1747 = and(io.core.brupdate.b1.mispredict_mask, stq[2].bits.uop.br_mask)
node _T_1748 = neq(_T_1747, UInt<1>(0h0))
node _T_1749 = and(_T_1748, stq[2].valid)
node _T_1750 = and(_T_1749, stq[2].bits.committed)
node _T_1751 = eq(_T_1750, UInt<1>(0h0))
node _T_1752 = asUInt(reset)
node _T_1753 = eq(_T_1752, UInt<1>(0h0))
when _T_1753 :
node _T_1754 = eq(_T_1751, UInt<1>(0h0))
when _T_1754 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_40
assert(clock, _T_1751, UInt<1>(0h1), "") : assert_40
connect st_brkilled_mask[3], UInt<1>(0h0)
when stq[3].valid :
node _stq_3_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_3_bits_uop_br_mask_T_1 = and(stq[3].bits.uop.br_mask, _stq_3_bits_uop_br_mask_T)
connect stq[3].bits.uop.br_mask, _stq_3_bits_uop_br_mask_T_1
node _T_1755 = and(io.core.brupdate.b1.mispredict_mask, stq[3].bits.uop.br_mask)
node _T_1756 = neq(_T_1755, UInt<1>(0h0))
when _T_1756 :
connect stq[3].valid, UInt<1>(0h0)
connect stq[3].bits.addr.valid, UInt<1>(0h0)
connect stq[3].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[3], UInt<1>(0h1)
node _T_1757 = and(io.core.brupdate.b1.mispredict_mask, stq[3].bits.uop.br_mask)
node _T_1758 = neq(_T_1757, UInt<1>(0h0))
node _T_1759 = and(_T_1758, stq[3].valid)
node _T_1760 = and(_T_1759, stq[3].bits.committed)
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
node _T_1762 = asUInt(reset)
node _T_1763 = eq(_T_1762, UInt<1>(0h0))
when _T_1763 :
node _T_1764 = eq(_T_1761, UInt<1>(0h0))
when _T_1764 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_41
assert(clock, _T_1761, UInt<1>(0h1), "") : assert_41
connect st_brkilled_mask[4], UInt<1>(0h0)
when stq[4].valid :
node _stq_4_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_4_bits_uop_br_mask_T_1 = and(stq[4].bits.uop.br_mask, _stq_4_bits_uop_br_mask_T)
connect stq[4].bits.uop.br_mask, _stq_4_bits_uop_br_mask_T_1
node _T_1765 = and(io.core.brupdate.b1.mispredict_mask, stq[4].bits.uop.br_mask)
node _T_1766 = neq(_T_1765, UInt<1>(0h0))
when _T_1766 :
connect stq[4].valid, UInt<1>(0h0)
connect stq[4].bits.addr.valid, UInt<1>(0h0)
connect stq[4].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[4], UInt<1>(0h1)
node _T_1767 = and(io.core.brupdate.b1.mispredict_mask, stq[4].bits.uop.br_mask)
node _T_1768 = neq(_T_1767, UInt<1>(0h0))
node _T_1769 = and(_T_1768, stq[4].valid)
node _T_1770 = and(_T_1769, stq[4].bits.committed)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
node _T_1772 = asUInt(reset)
node _T_1773 = eq(_T_1772, UInt<1>(0h0))
when _T_1773 :
node _T_1774 = eq(_T_1771, UInt<1>(0h0))
when _T_1774 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_42
assert(clock, _T_1771, UInt<1>(0h1), "") : assert_42
connect st_brkilled_mask[5], UInt<1>(0h0)
when stq[5].valid :
node _stq_5_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_5_bits_uop_br_mask_T_1 = and(stq[5].bits.uop.br_mask, _stq_5_bits_uop_br_mask_T)
connect stq[5].bits.uop.br_mask, _stq_5_bits_uop_br_mask_T_1
node _T_1775 = and(io.core.brupdate.b1.mispredict_mask, stq[5].bits.uop.br_mask)
node _T_1776 = neq(_T_1775, UInt<1>(0h0))
when _T_1776 :
connect stq[5].valid, UInt<1>(0h0)
connect stq[5].bits.addr.valid, UInt<1>(0h0)
connect stq[5].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[5], UInt<1>(0h1)
node _T_1777 = and(io.core.brupdate.b1.mispredict_mask, stq[5].bits.uop.br_mask)
node _T_1778 = neq(_T_1777, UInt<1>(0h0))
node _T_1779 = and(_T_1778, stq[5].valid)
node _T_1780 = and(_T_1779, stq[5].bits.committed)
node _T_1781 = eq(_T_1780, UInt<1>(0h0))
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(_T_1781, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_43
assert(clock, _T_1781, UInt<1>(0h1), "") : assert_43
connect st_brkilled_mask[6], UInt<1>(0h0)
when stq[6].valid :
node _stq_6_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_6_bits_uop_br_mask_T_1 = and(stq[6].bits.uop.br_mask, _stq_6_bits_uop_br_mask_T)
connect stq[6].bits.uop.br_mask, _stq_6_bits_uop_br_mask_T_1
node _T_1785 = and(io.core.brupdate.b1.mispredict_mask, stq[6].bits.uop.br_mask)
node _T_1786 = neq(_T_1785, UInt<1>(0h0))
when _T_1786 :
connect stq[6].valid, UInt<1>(0h0)
connect stq[6].bits.addr.valid, UInt<1>(0h0)
connect stq[6].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[6], UInt<1>(0h1)
node _T_1787 = and(io.core.brupdate.b1.mispredict_mask, stq[6].bits.uop.br_mask)
node _T_1788 = neq(_T_1787, UInt<1>(0h0))
node _T_1789 = and(_T_1788, stq[6].valid)
node _T_1790 = and(_T_1789, stq[6].bits.committed)
node _T_1791 = eq(_T_1790, UInt<1>(0h0))
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_44
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_44
connect st_brkilled_mask[7], UInt<1>(0h0)
when stq[7].valid :
node _stq_7_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_7_bits_uop_br_mask_T_1 = and(stq[7].bits.uop.br_mask, _stq_7_bits_uop_br_mask_T)
connect stq[7].bits.uop.br_mask, _stq_7_bits_uop_br_mask_T_1
node _T_1795 = and(io.core.brupdate.b1.mispredict_mask, stq[7].bits.uop.br_mask)
node _T_1796 = neq(_T_1795, UInt<1>(0h0))
when _T_1796 :
connect stq[7].valid, UInt<1>(0h0)
connect stq[7].bits.addr.valid, UInt<1>(0h0)
connect stq[7].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[7], UInt<1>(0h1)
node _T_1797 = and(io.core.brupdate.b1.mispredict_mask, stq[7].bits.uop.br_mask)
node _T_1798 = neq(_T_1797, UInt<1>(0h0))
node _T_1799 = and(_T_1798, stq[7].valid)
node _T_1800 = and(_T_1799, stq[7].bits.committed)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
node _T_1802 = asUInt(reset)
node _T_1803 = eq(_T_1802, UInt<1>(0h0))
when _T_1803 :
node _T_1804 = eq(_T_1801, UInt<1>(0h0))
when _T_1804 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_45
assert(clock, _T_1801, UInt<1>(0h1), "") : assert_45
connect st_brkilled_mask[8], UInt<1>(0h0)
when stq[8].valid :
node _stq_8_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_8_bits_uop_br_mask_T_1 = and(stq[8].bits.uop.br_mask, _stq_8_bits_uop_br_mask_T)
connect stq[8].bits.uop.br_mask, _stq_8_bits_uop_br_mask_T_1
node _T_1805 = and(io.core.brupdate.b1.mispredict_mask, stq[8].bits.uop.br_mask)
node _T_1806 = neq(_T_1805, UInt<1>(0h0))
when _T_1806 :
connect stq[8].valid, UInt<1>(0h0)
connect stq[8].bits.addr.valid, UInt<1>(0h0)
connect stq[8].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[8], UInt<1>(0h1)
node _T_1807 = and(io.core.brupdate.b1.mispredict_mask, stq[8].bits.uop.br_mask)
node _T_1808 = neq(_T_1807, UInt<1>(0h0))
node _T_1809 = and(_T_1808, stq[8].valid)
node _T_1810 = and(_T_1809, stq[8].bits.committed)
node _T_1811 = eq(_T_1810, UInt<1>(0h0))
node _T_1812 = asUInt(reset)
node _T_1813 = eq(_T_1812, UInt<1>(0h0))
when _T_1813 :
node _T_1814 = eq(_T_1811, UInt<1>(0h0))
when _T_1814 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_46
assert(clock, _T_1811, UInt<1>(0h1), "") : assert_46
connect st_brkilled_mask[9], UInt<1>(0h0)
when stq[9].valid :
node _stq_9_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_9_bits_uop_br_mask_T_1 = and(stq[9].bits.uop.br_mask, _stq_9_bits_uop_br_mask_T)
connect stq[9].bits.uop.br_mask, _stq_9_bits_uop_br_mask_T_1
node _T_1815 = and(io.core.brupdate.b1.mispredict_mask, stq[9].bits.uop.br_mask)
node _T_1816 = neq(_T_1815, UInt<1>(0h0))
when _T_1816 :
connect stq[9].valid, UInt<1>(0h0)
connect stq[9].bits.addr.valid, UInt<1>(0h0)
connect stq[9].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[9], UInt<1>(0h1)
node _T_1817 = and(io.core.brupdate.b1.mispredict_mask, stq[9].bits.uop.br_mask)
node _T_1818 = neq(_T_1817, UInt<1>(0h0))
node _T_1819 = and(_T_1818, stq[9].valid)
node _T_1820 = and(_T_1819, stq[9].bits.committed)
node _T_1821 = eq(_T_1820, UInt<1>(0h0))
node _T_1822 = asUInt(reset)
node _T_1823 = eq(_T_1822, UInt<1>(0h0))
when _T_1823 :
node _T_1824 = eq(_T_1821, UInt<1>(0h0))
when _T_1824 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_47
assert(clock, _T_1821, UInt<1>(0h1), "") : assert_47
connect st_brkilled_mask[10], UInt<1>(0h0)
when stq[10].valid :
node _stq_10_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_10_bits_uop_br_mask_T_1 = and(stq[10].bits.uop.br_mask, _stq_10_bits_uop_br_mask_T)
connect stq[10].bits.uop.br_mask, _stq_10_bits_uop_br_mask_T_1
node _T_1825 = and(io.core.brupdate.b1.mispredict_mask, stq[10].bits.uop.br_mask)
node _T_1826 = neq(_T_1825, UInt<1>(0h0))
when _T_1826 :
connect stq[10].valid, UInt<1>(0h0)
connect stq[10].bits.addr.valid, UInt<1>(0h0)
connect stq[10].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[10], UInt<1>(0h1)
node _T_1827 = and(io.core.brupdate.b1.mispredict_mask, stq[10].bits.uop.br_mask)
node _T_1828 = neq(_T_1827, UInt<1>(0h0))
node _T_1829 = and(_T_1828, stq[10].valid)
node _T_1830 = and(_T_1829, stq[10].bits.committed)
node _T_1831 = eq(_T_1830, UInt<1>(0h0))
node _T_1832 = asUInt(reset)
node _T_1833 = eq(_T_1832, UInt<1>(0h0))
when _T_1833 :
node _T_1834 = eq(_T_1831, UInt<1>(0h0))
when _T_1834 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_48
assert(clock, _T_1831, UInt<1>(0h1), "") : assert_48
connect st_brkilled_mask[11], UInt<1>(0h0)
when stq[11].valid :
node _stq_11_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_11_bits_uop_br_mask_T_1 = and(stq[11].bits.uop.br_mask, _stq_11_bits_uop_br_mask_T)
connect stq[11].bits.uop.br_mask, _stq_11_bits_uop_br_mask_T_1
node _T_1835 = and(io.core.brupdate.b1.mispredict_mask, stq[11].bits.uop.br_mask)
node _T_1836 = neq(_T_1835, UInt<1>(0h0))
when _T_1836 :
connect stq[11].valid, UInt<1>(0h0)
connect stq[11].bits.addr.valid, UInt<1>(0h0)
connect stq[11].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[11], UInt<1>(0h1)
node _T_1837 = and(io.core.brupdate.b1.mispredict_mask, stq[11].bits.uop.br_mask)
node _T_1838 = neq(_T_1837, UInt<1>(0h0))
node _T_1839 = and(_T_1838, stq[11].valid)
node _T_1840 = and(_T_1839, stq[11].bits.committed)
node _T_1841 = eq(_T_1840, UInt<1>(0h0))
node _T_1842 = asUInt(reset)
node _T_1843 = eq(_T_1842, UInt<1>(0h0))
when _T_1843 :
node _T_1844 = eq(_T_1841, UInt<1>(0h0))
when _T_1844 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_49
assert(clock, _T_1841, UInt<1>(0h1), "") : assert_49
connect st_brkilled_mask[12], UInt<1>(0h0)
when stq[12].valid :
node _stq_12_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_12_bits_uop_br_mask_T_1 = and(stq[12].bits.uop.br_mask, _stq_12_bits_uop_br_mask_T)
connect stq[12].bits.uop.br_mask, _stq_12_bits_uop_br_mask_T_1
node _T_1845 = and(io.core.brupdate.b1.mispredict_mask, stq[12].bits.uop.br_mask)
node _T_1846 = neq(_T_1845, UInt<1>(0h0))
when _T_1846 :
connect stq[12].valid, UInt<1>(0h0)
connect stq[12].bits.addr.valid, UInt<1>(0h0)
connect stq[12].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[12], UInt<1>(0h1)
node _T_1847 = and(io.core.brupdate.b1.mispredict_mask, stq[12].bits.uop.br_mask)
node _T_1848 = neq(_T_1847, UInt<1>(0h0))
node _T_1849 = and(_T_1848, stq[12].valid)
node _T_1850 = and(_T_1849, stq[12].bits.committed)
node _T_1851 = eq(_T_1850, UInt<1>(0h0))
node _T_1852 = asUInt(reset)
node _T_1853 = eq(_T_1852, UInt<1>(0h0))
when _T_1853 :
node _T_1854 = eq(_T_1851, UInt<1>(0h0))
when _T_1854 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_50
assert(clock, _T_1851, UInt<1>(0h1), "") : assert_50
connect st_brkilled_mask[13], UInt<1>(0h0)
when stq[13].valid :
node _stq_13_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_13_bits_uop_br_mask_T_1 = and(stq[13].bits.uop.br_mask, _stq_13_bits_uop_br_mask_T)
connect stq[13].bits.uop.br_mask, _stq_13_bits_uop_br_mask_T_1
node _T_1855 = and(io.core.brupdate.b1.mispredict_mask, stq[13].bits.uop.br_mask)
node _T_1856 = neq(_T_1855, UInt<1>(0h0))
when _T_1856 :
connect stq[13].valid, UInt<1>(0h0)
connect stq[13].bits.addr.valid, UInt<1>(0h0)
connect stq[13].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[13], UInt<1>(0h1)
node _T_1857 = and(io.core.brupdate.b1.mispredict_mask, stq[13].bits.uop.br_mask)
node _T_1858 = neq(_T_1857, UInt<1>(0h0))
node _T_1859 = and(_T_1858, stq[13].valid)
node _T_1860 = and(_T_1859, stq[13].bits.committed)
node _T_1861 = eq(_T_1860, UInt<1>(0h0))
node _T_1862 = asUInt(reset)
node _T_1863 = eq(_T_1862, UInt<1>(0h0))
when _T_1863 :
node _T_1864 = eq(_T_1861, UInt<1>(0h0))
when _T_1864 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_51
assert(clock, _T_1861, UInt<1>(0h1), "") : assert_51
connect st_brkilled_mask[14], UInt<1>(0h0)
when stq[14].valid :
node _stq_14_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_14_bits_uop_br_mask_T_1 = and(stq[14].bits.uop.br_mask, _stq_14_bits_uop_br_mask_T)
connect stq[14].bits.uop.br_mask, _stq_14_bits_uop_br_mask_T_1
node _T_1865 = and(io.core.brupdate.b1.mispredict_mask, stq[14].bits.uop.br_mask)
node _T_1866 = neq(_T_1865, UInt<1>(0h0))
when _T_1866 :
connect stq[14].valid, UInt<1>(0h0)
connect stq[14].bits.addr.valid, UInt<1>(0h0)
connect stq[14].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[14], UInt<1>(0h1)
node _T_1867 = and(io.core.brupdate.b1.mispredict_mask, stq[14].bits.uop.br_mask)
node _T_1868 = neq(_T_1867, UInt<1>(0h0))
node _T_1869 = and(_T_1868, stq[14].valid)
node _T_1870 = and(_T_1869, stq[14].bits.committed)
node _T_1871 = eq(_T_1870, UInt<1>(0h0))
node _T_1872 = asUInt(reset)
node _T_1873 = eq(_T_1872, UInt<1>(0h0))
when _T_1873 :
node _T_1874 = eq(_T_1871, UInt<1>(0h0))
when _T_1874 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_52
assert(clock, _T_1871, UInt<1>(0h1), "") : assert_52
connect st_brkilled_mask[15], UInt<1>(0h0)
when stq[15].valid :
node _stq_15_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_15_bits_uop_br_mask_T_1 = and(stq[15].bits.uop.br_mask, _stq_15_bits_uop_br_mask_T)
connect stq[15].bits.uop.br_mask, _stq_15_bits_uop_br_mask_T_1
node _T_1875 = and(io.core.brupdate.b1.mispredict_mask, stq[15].bits.uop.br_mask)
node _T_1876 = neq(_T_1875, UInt<1>(0h0))
when _T_1876 :
connect stq[15].valid, UInt<1>(0h0)
connect stq[15].bits.addr.valid, UInt<1>(0h0)
connect stq[15].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[15], UInt<1>(0h1)
node _T_1877 = and(io.core.brupdate.b1.mispredict_mask, stq[15].bits.uop.br_mask)
node _T_1878 = neq(_T_1877, UInt<1>(0h0))
node _T_1879 = and(_T_1878, stq[15].valid)
node _T_1880 = and(_T_1879, stq[15].bits.committed)
node _T_1881 = eq(_T_1880, UInt<1>(0h0))
node _T_1882 = asUInt(reset)
node _T_1883 = eq(_T_1882, UInt<1>(0h0))
when _T_1883 :
node _T_1884 = eq(_T_1881, UInt<1>(0h0))
when _T_1884 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_53
assert(clock, _T_1881, UInt<1>(0h1), "") : assert_53
connect st_brkilled_mask[16], UInt<1>(0h0)
when stq[16].valid :
node _stq_16_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_16_bits_uop_br_mask_T_1 = and(stq[16].bits.uop.br_mask, _stq_16_bits_uop_br_mask_T)
connect stq[16].bits.uop.br_mask, _stq_16_bits_uop_br_mask_T_1
node _T_1885 = and(io.core.brupdate.b1.mispredict_mask, stq[16].bits.uop.br_mask)
node _T_1886 = neq(_T_1885, UInt<1>(0h0))
when _T_1886 :
connect stq[16].valid, UInt<1>(0h0)
connect stq[16].bits.addr.valid, UInt<1>(0h0)
connect stq[16].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[16], UInt<1>(0h1)
node _T_1887 = and(io.core.brupdate.b1.mispredict_mask, stq[16].bits.uop.br_mask)
node _T_1888 = neq(_T_1887, UInt<1>(0h0))
node _T_1889 = and(_T_1888, stq[16].valid)
node _T_1890 = and(_T_1889, stq[16].bits.committed)
node _T_1891 = eq(_T_1890, UInt<1>(0h0))
node _T_1892 = asUInt(reset)
node _T_1893 = eq(_T_1892, UInt<1>(0h0))
when _T_1893 :
node _T_1894 = eq(_T_1891, UInt<1>(0h0))
when _T_1894 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_54
assert(clock, _T_1891, UInt<1>(0h1), "") : assert_54
connect st_brkilled_mask[17], UInt<1>(0h0)
when stq[17].valid :
node _stq_17_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_17_bits_uop_br_mask_T_1 = and(stq[17].bits.uop.br_mask, _stq_17_bits_uop_br_mask_T)
connect stq[17].bits.uop.br_mask, _stq_17_bits_uop_br_mask_T_1
node _T_1895 = and(io.core.brupdate.b1.mispredict_mask, stq[17].bits.uop.br_mask)
node _T_1896 = neq(_T_1895, UInt<1>(0h0))
when _T_1896 :
connect stq[17].valid, UInt<1>(0h0)
connect stq[17].bits.addr.valid, UInt<1>(0h0)
connect stq[17].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[17], UInt<1>(0h1)
node _T_1897 = and(io.core.brupdate.b1.mispredict_mask, stq[17].bits.uop.br_mask)
node _T_1898 = neq(_T_1897, UInt<1>(0h0))
node _T_1899 = and(_T_1898, stq[17].valid)
node _T_1900 = and(_T_1899, stq[17].bits.committed)
node _T_1901 = eq(_T_1900, UInt<1>(0h0))
node _T_1902 = asUInt(reset)
node _T_1903 = eq(_T_1902, UInt<1>(0h0))
when _T_1903 :
node _T_1904 = eq(_T_1901, UInt<1>(0h0))
when _T_1904 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_55
assert(clock, _T_1901, UInt<1>(0h1), "") : assert_55
connect st_brkilled_mask[18], UInt<1>(0h0)
when stq[18].valid :
node _stq_18_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_18_bits_uop_br_mask_T_1 = and(stq[18].bits.uop.br_mask, _stq_18_bits_uop_br_mask_T)
connect stq[18].bits.uop.br_mask, _stq_18_bits_uop_br_mask_T_1
node _T_1905 = and(io.core.brupdate.b1.mispredict_mask, stq[18].bits.uop.br_mask)
node _T_1906 = neq(_T_1905, UInt<1>(0h0))
when _T_1906 :
connect stq[18].valid, UInt<1>(0h0)
connect stq[18].bits.addr.valid, UInt<1>(0h0)
connect stq[18].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[18], UInt<1>(0h1)
node _T_1907 = and(io.core.brupdate.b1.mispredict_mask, stq[18].bits.uop.br_mask)
node _T_1908 = neq(_T_1907, UInt<1>(0h0))
node _T_1909 = and(_T_1908, stq[18].valid)
node _T_1910 = and(_T_1909, stq[18].bits.committed)
node _T_1911 = eq(_T_1910, UInt<1>(0h0))
node _T_1912 = asUInt(reset)
node _T_1913 = eq(_T_1912, UInt<1>(0h0))
when _T_1913 :
node _T_1914 = eq(_T_1911, UInt<1>(0h0))
when _T_1914 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_56
assert(clock, _T_1911, UInt<1>(0h1), "") : assert_56
connect st_brkilled_mask[19], UInt<1>(0h0)
when stq[19].valid :
node _stq_19_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_19_bits_uop_br_mask_T_1 = and(stq[19].bits.uop.br_mask, _stq_19_bits_uop_br_mask_T)
connect stq[19].bits.uop.br_mask, _stq_19_bits_uop_br_mask_T_1
node _T_1915 = and(io.core.brupdate.b1.mispredict_mask, stq[19].bits.uop.br_mask)
node _T_1916 = neq(_T_1915, UInt<1>(0h0))
when _T_1916 :
connect stq[19].valid, UInt<1>(0h0)
connect stq[19].bits.addr.valid, UInt<1>(0h0)
connect stq[19].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[19], UInt<1>(0h1)
node _T_1917 = and(io.core.brupdate.b1.mispredict_mask, stq[19].bits.uop.br_mask)
node _T_1918 = neq(_T_1917, UInt<1>(0h0))
node _T_1919 = and(_T_1918, stq[19].valid)
node _T_1920 = and(_T_1919, stq[19].bits.committed)
node _T_1921 = eq(_T_1920, UInt<1>(0h0))
node _T_1922 = asUInt(reset)
node _T_1923 = eq(_T_1922, UInt<1>(0h0))
when _T_1923 :
node _T_1924 = eq(_T_1921, UInt<1>(0h0))
when _T_1924 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_57
assert(clock, _T_1921, UInt<1>(0h1), "") : assert_57
connect st_brkilled_mask[20], UInt<1>(0h0)
when stq[20].valid :
node _stq_20_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_20_bits_uop_br_mask_T_1 = and(stq[20].bits.uop.br_mask, _stq_20_bits_uop_br_mask_T)
connect stq[20].bits.uop.br_mask, _stq_20_bits_uop_br_mask_T_1
node _T_1925 = and(io.core.brupdate.b1.mispredict_mask, stq[20].bits.uop.br_mask)
node _T_1926 = neq(_T_1925, UInt<1>(0h0))
when _T_1926 :
connect stq[20].valid, UInt<1>(0h0)
connect stq[20].bits.addr.valid, UInt<1>(0h0)
connect stq[20].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[20], UInt<1>(0h1)
node _T_1927 = and(io.core.brupdate.b1.mispredict_mask, stq[20].bits.uop.br_mask)
node _T_1928 = neq(_T_1927, UInt<1>(0h0))
node _T_1929 = and(_T_1928, stq[20].valid)
node _T_1930 = and(_T_1929, stq[20].bits.committed)
node _T_1931 = eq(_T_1930, UInt<1>(0h0))
node _T_1932 = asUInt(reset)
node _T_1933 = eq(_T_1932, UInt<1>(0h0))
when _T_1933 :
node _T_1934 = eq(_T_1931, UInt<1>(0h0))
when _T_1934 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_58
assert(clock, _T_1931, UInt<1>(0h1), "") : assert_58
connect st_brkilled_mask[21], UInt<1>(0h0)
when stq[21].valid :
node _stq_21_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_21_bits_uop_br_mask_T_1 = and(stq[21].bits.uop.br_mask, _stq_21_bits_uop_br_mask_T)
connect stq[21].bits.uop.br_mask, _stq_21_bits_uop_br_mask_T_1
node _T_1935 = and(io.core.brupdate.b1.mispredict_mask, stq[21].bits.uop.br_mask)
node _T_1936 = neq(_T_1935, UInt<1>(0h0))
when _T_1936 :
connect stq[21].valid, UInt<1>(0h0)
connect stq[21].bits.addr.valid, UInt<1>(0h0)
connect stq[21].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[21], UInt<1>(0h1)
node _T_1937 = and(io.core.brupdate.b1.mispredict_mask, stq[21].bits.uop.br_mask)
node _T_1938 = neq(_T_1937, UInt<1>(0h0))
node _T_1939 = and(_T_1938, stq[21].valid)
node _T_1940 = and(_T_1939, stq[21].bits.committed)
node _T_1941 = eq(_T_1940, UInt<1>(0h0))
node _T_1942 = asUInt(reset)
node _T_1943 = eq(_T_1942, UInt<1>(0h0))
when _T_1943 :
node _T_1944 = eq(_T_1941, UInt<1>(0h0))
when _T_1944 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_59
assert(clock, _T_1941, UInt<1>(0h1), "") : assert_59
connect st_brkilled_mask[22], UInt<1>(0h0)
when stq[22].valid :
node _stq_22_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_22_bits_uop_br_mask_T_1 = and(stq[22].bits.uop.br_mask, _stq_22_bits_uop_br_mask_T)
connect stq[22].bits.uop.br_mask, _stq_22_bits_uop_br_mask_T_1
node _T_1945 = and(io.core.brupdate.b1.mispredict_mask, stq[22].bits.uop.br_mask)
node _T_1946 = neq(_T_1945, UInt<1>(0h0))
when _T_1946 :
connect stq[22].valid, UInt<1>(0h0)
connect stq[22].bits.addr.valid, UInt<1>(0h0)
connect stq[22].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[22], UInt<1>(0h1)
node _T_1947 = and(io.core.brupdate.b1.mispredict_mask, stq[22].bits.uop.br_mask)
node _T_1948 = neq(_T_1947, UInt<1>(0h0))
node _T_1949 = and(_T_1948, stq[22].valid)
node _T_1950 = and(_T_1949, stq[22].bits.committed)
node _T_1951 = eq(_T_1950, UInt<1>(0h0))
node _T_1952 = asUInt(reset)
node _T_1953 = eq(_T_1952, UInt<1>(0h0))
when _T_1953 :
node _T_1954 = eq(_T_1951, UInt<1>(0h0))
when _T_1954 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_60
assert(clock, _T_1951, UInt<1>(0h1), "") : assert_60
connect st_brkilled_mask[23], UInt<1>(0h0)
when stq[23].valid :
node _stq_23_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _stq_23_bits_uop_br_mask_T_1 = and(stq[23].bits.uop.br_mask, _stq_23_bits_uop_br_mask_T)
connect stq[23].bits.uop.br_mask, _stq_23_bits_uop_br_mask_T_1
node _T_1955 = and(io.core.brupdate.b1.mispredict_mask, stq[23].bits.uop.br_mask)
node _T_1956 = neq(_T_1955, UInt<1>(0h0))
when _T_1956 :
connect stq[23].valid, UInt<1>(0h0)
connect stq[23].bits.addr.valid, UInt<1>(0h0)
connect stq[23].bits.data.valid, UInt<1>(0h0)
connect st_brkilled_mask[23], UInt<1>(0h1)
node _T_1957 = and(io.core.brupdate.b1.mispredict_mask, stq[23].bits.uop.br_mask)
node _T_1958 = neq(_T_1957, UInt<1>(0h0))
node _T_1959 = and(_T_1958, stq[23].valid)
node _T_1960 = and(_T_1959, stq[23].bits.committed)
node _T_1961 = eq(_T_1960, UInt<1>(0h0))
node _T_1962 = asUInt(reset)
node _T_1963 = eq(_T_1962, UInt<1>(0h0))
when _T_1963 :
node _T_1964 = eq(_T_1961, UInt<1>(0h0))
when _T_1964 :
printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1419 assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n") : printf_61
assert(clock, _T_1961, UInt<1>(0h1), "") : assert_61
when ldq[0].valid :
node _ldq_0_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_0_bits_uop_br_mask_T_1 = and(ldq[0].bits.uop.br_mask, _ldq_0_bits_uop_br_mask_T)
connect ldq[0].bits.uop.br_mask, _ldq_0_bits_uop_br_mask_T_1
node _T_1965 = and(io.core.brupdate.b1.mispredict_mask, ldq[0].bits.uop.br_mask)
node _T_1966 = neq(_T_1965, UInt<1>(0h0))
when _T_1966 :
connect ldq[0].valid, UInt<1>(0h0)
connect ldq[0].bits.addr.valid, UInt<1>(0h0)
when ldq[1].valid :
node _ldq_1_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_1_bits_uop_br_mask_T_1 = and(ldq[1].bits.uop.br_mask, _ldq_1_bits_uop_br_mask_T)
connect ldq[1].bits.uop.br_mask, _ldq_1_bits_uop_br_mask_T_1
node _T_1967 = and(io.core.brupdate.b1.mispredict_mask, ldq[1].bits.uop.br_mask)
node _T_1968 = neq(_T_1967, UInt<1>(0h0))
when _T_1968 :
connect ldq[1].valid, UInt<1>(0h0)
connect ldq[1].bits.addr.valid, UInt<1>(0h0)
when ldq[2].valid :
node _ldq_2_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_2_bits_uop_br_mask_T_1 = and(ldq[2].bits.uop.br_mask, _ldq_2_bits_uop_br_mask_T)
connect ldq[2].bits.uop.br_mask, _ldq_2_bits_uop_br_mask_T_1
node _T_1969 = and(io.core.brupdate.b1.mispredict_mask, ldq[2].bits.uop.br_mask)
node _T_1970 = neq(_T_1969, UInt<1>(0h0))
when _T_1970 :
connect ldq[2].valid, UInt<1>(0h0)
connect ldq[2].bits.addr.valid, UInt<1>(0h0)
when ldq[3].valid :
node _ldq_3_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_3_bits_uop_br_mask_T_1 = and(ldq[3].bits.uop.br_mask, _ldq_3_bits_uop_br_mask_T)
connect ldq[3].bits.uop.br_mask, _ldq_3_bits_uop_br_mask_T_1
node _T_1971 = and(io.core.brupdate.b1.mispredict_mask, ldq[3].bits.uop.br_mask)
node _T_1972 = neq(_T_1971, UInt<1>(0h0))
when _T_1972 :
connect ldq[3].valid, UInt<1>(0h0)
connect ldq[3].bits.addr.valid, UInt<1>(0h0)
when ldq[4].valid :
node _ldq_4_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_4_bits_uop_br_mask_T_1 = and(ldq[4].bits.uop.br_mask, _ldq_4_bits_uop_br_mask_T)
connect ldq[4].bits.uop.br_mask, _ldq_4_bits_uop_br_mask_T_1
node _T_1973 = and(io.core.brupdate.b1.mispredict_mask, ldq[4].bits.uop.br_mask)
node _T_1974 = neq(_T_1973, UInt<1>(0h0))
when _T_1974 :
connect ldq[4].valid, UInt<1>(0h0)
connect ldq[4].bits.addr.valid, UInt<1>(0h0)
when ldq[5].valid :
node _ldq_5_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_5_bits_uop_br_mask_T_1 = and(ldq[5].bits.uop.br_mask, _ldq_5_bits_uop_br_mask_T)
connect ldq[5].bits.uop.br_mask, _ldq_5_bits_uop_br_mask_T_1
node _T_1975 = and(io.core.brupdate.b1.mispredict_mask, ldq[5].bits.uop.br_mask)
node _T_1976 = neq(_T_1975, UInt<1>(0h0))
when _T_1976 :
connect ldq[5].valid, UInt<1>(0h0)
connect ldq[5].bits.addr.valid, UInt<1>(0h0)
when ldq[6].valid :
node _ldq_6_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_6_bits_uop_br_mask_T_1 = and(ldq[6].bits.uop.br_mask, _ldq_6_bits_uop_br_mask_T)
connect ldq[6].bits.uop.br_mask, _ldq_6_bits_uop_br_mask_T_1
node _T_1977 = and(io.core.brupdate.b1.mispredict_mask, ldq[6].bits.uop.br_mask)
node _T_1978 = neq(_T_1977, UInt<1>(0h0))
when _T_1978 :
connect ldq[6].valid, UInt<1>(0h0)
connect ldq[6].bits.addr.valid, UInt<1>(0h0)
when ldq[7].valid :
node _ldq_7_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_7_bits_uop_br_mask_T_1 = and(ldq[7].bits.uop.br_mask, _ldq_7_bits_uop_br_mask_T)
connect ldq[7].bits.uop.br_mask, _ldq_7_bits_uop_br_mask_T_1
node _T_1979 = and(io.core.brupdate.b1.mispredict_mask, ldq[7].bits.uop.br_mask)
node _T_1980 = neq(_T_1979, UInt<1>(0h0))
when _T_1980 :
connect ldq[7].valid, UInt<1>(0h0)
connect ldq[7].bits.addr.valid, UInt<1>(0h0)
when ldq[8].valid :
node _ldq_8_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_8_bits_uop_br_mask_T_1 = and(ldq[8].bits.uop.br_mask, _ldq_8_bits_uop_br_mask_T)
connect ldq[8].bits.uop.br_mask, _ldq_8_bits_uop_br_mask_T_1
node _T_1981 = and(io.core.brupdate.b1.mispredict_mask, ldq[8].bits.uop.br_mask)
node _T_1982 = neq(_T_1981, UInt<1>(0h0))
when _T_1982 :
connect ldq[8].valid, UInt<1>(0h0)
connect ldq[8].bits.addr.valid, UInt<1>(0h0)
when ldq[9].valid :
node _ldq_9_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_9_bits_uop_br_mask_T_1 = and(ldq[9].bits.uop.br_mask, _ldq_9_bits_uop_br_mask_T)
connect ldq[9].bits.uop.br_mask, _ldq_9_bits_uop_br_mask_T_1
node _T_1983 = and(io.core.brupdate.b1.mispredict_mask, ldq[9].bits.uop.br_mask)
node _T_1984 = neq(_T_1983, UInt<1>(0h0))
when _T_1984 :
connect ldq[9].valid, UInt<1>(0h0)
connect ldq[9].bits.addr.valid, UInt<1>(0h0)
when ldq[10].valid :
node _ldq_10_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_10_bits_uop_br_mask_T_1 = and(ldq[10].bits.uop.br_mask, _ldq_10_bits_uop_br_mask_T)
connect ldq[10].bits.uop.br_mask, _ldq_10_bits_uop_br_mask_T_1
node _T_1985 = and(io.core.brupdate.b1.mispredict_mask, ldq[10].bits.uop.br_mask)
node _T_1986 = neq(_T_1985, UInt<1>(0h0))
when _T_1986 :
connect ldq[10].valid, UInt<1>(0h0)
connect ldq[10].bits.addr.valid, UInt<1>(0h0)
when ldq[11].valid :
node _ldq_11_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_11_bits_uop_br_mask_T_1 = and(ldq[11].bits.uop.br_mask, _ldq_11_bits_uop_br_mask_T)
connect ldq[11].bits.uop.br_mask, _ldq_11_bits_uop_br_mask_T_1
node _T_1987 = and(io.core.brupdate.b1.mispredict_mask, ldq[11].bits.uop.br_mask)
node _T_1988 = neq(_T_1987, UInt<1>(0h0))
when _T_1988 :
connect ldq[11].valid, UInt<1>(0h0)
connect ldq[11].bits.addr.valid, UInt<1>(0h0)
when ldq[12].valid :
node _ldq_12_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_12_bits_uop_br_mask_T_1 = and(ldq[12].bits.uop.br_mask, _ldq_12_bits_uop_br_mask_T)
connect ldq[12].bits.uop.br_mask, _ldq_12_bits_uop_br_mask_T_1
node _T_1989 = and(io.core.brupdate.b1.mispredict_mask, ldq[12].bits.uop.br_mask)
node _T_1990 = neq(_T_1989, UInt<1>(0h0))
when _T_1990 :
connect ldq[12].valid, UInt<1>(0h0)
connect ldq[12].bits.addr.valid, UInt<1>(0h0)
when ldq[13].valid :
node _ldq_13_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_13_bits_uop_br_mask_T_1 = and(ldq[13].bits.uop.br_mask, _ldq_13_bits_uop_br_mask_T)
connect ldq[13].bits.uop.br_mask, _ldq_13_bits_uop_br_mask_T_1
node _T_1991 = and(io.core.brupdate.b1.mispredict_mask, ldq[13].bits.uop.br_mask)
node _T_1992 = neq(_T_1991, UInt<1>(0h0))
when _T_1992 :
connect ldq[13].valid, UInt<1>(0h0)
connect ldq[13].bits.addr.valid, UInt<1>(0h0)
when ldq[14].valid :
node _ldq_14_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_14_bits_uop_br_mask_T_1 = and(ldq[14].bits.uop.br_mask, _ldq_14_bits_uop_br_mask_T)
connect ldq[14].bits.uop.br_mask, _ldq_14_bits_uop_br_mask_T_1
node _T_1993 = and(io.core.brupdate.b1.mispredict_mask, ldq[14].bits.uop.br_mask)
node _T_1994 = neq(_T_1993, UInt<1>(0h0))
when _T_1994 :
connect ldq[14].valid, UInt<1>(0h0)
connect ldq[14].bits.addr.valid, UInt<1>(0h0)
when ldq[15].valid :
node _ldq_15_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_15_bits_uop_br_mask_T_1 = and(ldq[15].bits.uop.br_mask, _ldq_15_bits_uop_br_mask_T)
connect ldq[15].bits.uop.br_mask, _ldq_15_bits_uop_br_mask_T_1
node _T_1995 = and(io.core.brupdate.b1.mispredict_mask, ldq[15].bits.uop.br_mask)
node _T_1996 = neq(_T_1995, UInt<1>(0h0))
when _T_1996 :
connect ldq[15].valid, UInt<1>(0h0)
connect ldq[15].bits.addr.valid, UInt<1>(0h0)
when ldq[16].valid :
node _ldq_16_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_16_bits_uop_br_mask_T_1 = and(ldq[16].bits.uop.br_mask, _ldq_16_bits_uop_br_mask_T)
connect ldq[16].bits.uop.br_mask, _ldq_16_bits_uop_br_mask_T_1
node _T_1997 = and(io.core.brupdate.b1.mispredict_mask, ldq[16].bits.uop.br_mask)
node _T_1998 = neq(_T_1997, UInt<1>(0h0))
when _T_1998 :
connect ldq[16].valid, UInt<1>(0h0)
connect ldq[16].bits.addr.valid, UInt<1>(0h0)
when ldq[17].valid :
node _ldq_17_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_17_bits_uop_br_mask_T_1 = and(ldq[17].bits.uop.br_mask, _ldq_17_bits_uop_br_mask_T)
connect ldq[17].bits.uop.br_mask, _ldq_17_bits_uop_br_mask_T_1
node _T_1999 = and(io.core.brupdate.b1.mispredict_mask, ldq[17].bits.uop.br_mask)
node _T_2000 = neq(_T_1999, UInt<1>(0h0))
when _T_2000 :
connect ldq[17].valid, UInt<1>(0h0)
connect ldq[17].bits.addr.valid, UInt<1>(0h0)
when ldq[18].valid :
node _ldq_18_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_18_bits_uop_br_mask_T_1 = and(ldq[18].bits.uop.br_mask, _ldq_18_bits_uop_br_mask_T)
connect ldq[18].bits.uop.br_mask, _ldq_18_bits_uop_br_mask_T_1
node _T_2001 = and(io.core.brupdate.b1.mispredict_mask, ldq[18].bits.uop.br_mask)
node _T_2002 = neq(_T_2001, UInt<1>(0h0))
when _T_2002 :
connect ldq[18].valid, UInt<1>(0h0)
connect ldq[18].bits.addr.valid, UInt<1>(0h0)
when ldq[19].valid :
node _ldq_19_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_19_bits_uop_br_mask_T_1 = and(ldq[19].bits.uop.br_mask, _ldq_19_bits_uop_br_mask_T)
connect ldq[19].bits.uop.br_mask, _ldq_19_bits_uop_br_mask_T_1
node _T_2003 = and(io.core.brupdate.b1.mispredict_mask, ldq[19].bits.uop.br_mask)
node _T_2004 = neq(_T_2003, UInt<1>(0h0))
when _T_2004 :
connect ldq[19].valid, UInt<1>(0h0)
connect ldq[19].bits.addr.valid, UInt<1>(0h0)
when ldq[20].valid :
node _ldq_20_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_20_bits_uop_br_mask_T_1 = and(ldq[20].bits.uop.br_mask, _ldq_20_bits_uop_br_mask_T)
connect ldq[20].bits.uop.br_mask, _ldq_20_bits_uop_br_mask_T_1
node _T_2005 = and(io.core.brupdate.b1.mispredict_mask, ldq[20].bits.uop.br_mask)
node _T_2006 = neq(_T_2005, UInt<1>(0h0))
when _T_2006 :
connect ldq[20].valid, UInt<1>(0h0)
connect ldq[20].bits.addr.valid, UInt<1>(0h0)
when ldq[21].valid :
node _ldq_21_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_21_bits_uop_br_mask_T_1 = and(ldq[21].bits.uop.br_mask, _ldq_21_bits_uop_br_mask_T)
connect ldq[21].bits.uop.br_mask, _ldq_21_bits_uop_br_mask_T_1
node _T_2007 = and(io.core.brupdate.b1.mispredict_mask, ldq[21].bits.uop.br_mask)
node _T_2008 = neq(_T_2007, UInt<1>(0h0))
when _T_2008 :
connect ldq[21].valid, UInt<1>(0h0)
connect ldq[21].bits.addr.valid, UInt<1>(0h0)
when ldq[22].valid :
node _ldq_22_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_22_bits_uop_br_mask_T_1 = and(ldq[22].bits.uop.br_mask, _ldq_22_bits_uop_br_mask_T)
connect ldq[22].bits.uop.br_mask, _ldq_22_bits_uop_br_mask_T_1
node _T_2009 = and(io.core.brupdate.b1.mispredict_mask, ldq[22].bits.uop.br_mask)
node _T_2010 = neq(_T_2009, UInt<1>(0h0))
when _T_2010 :
connect ldq[22].valid, UInt<1>(0h0)
connect ldq[22].bits.addr.valid, UInt<1>(0h0)
when ldq[23].valid :
node _ldq_23_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask)
node _ldq_23_bits_uop_br_mask_T_1 = and(ldq[23].bits.uop.br_mask, _ldq_23_bits_uop_br_mask_T)
connect ldq[23].bits.uop.br_mask, _ldq_23_bits_uop_br_mask_T_1
node _T_2011 = and(io.core.brupdate.b1.mispredict_mask, ldq[23].bits.uop.br_mask)
node _T_2012 = neq(_T_2011, UInt<1>(0h0))
when _T_2012 :
connect ldq[23].valid, UInt<1>(0h0)
connect ldq[23].bits.addr.valid, UInt<1>(0h0)
node _T_2013 = eq(io.core.exception, UInt<1>(0h0))
node _T_2014 = and(io.core.brupdate.b2.mispredict, _T_2013)
when _T_2014 :
connect stq_tail, io.core.brupdate.b2.uop.stq_idx
connect ldq_tail, io.core.brupdate.b2.uop.ldq_idx
node commit_store = and(io.core.commit.valids[0], io.core.commit.uops[0].uses_stq)
node commit_load = and(io.core.commit.valids[0], io.core.commit.uops[0].uses_ldq)
node idx = mux(commit_store, stq_commit_head, ldq_head)
when commit_store :
connect stq[idx].bits.committed, UInt<1>(0h1)
else :
when commit_load :
node _T_2015 = asUInt(reset)
node _T_2016 = eq(_T_2015, UInt<1>(0h0))
when _T_2016 :
node _T_2017 = eq(ldq[idx].valid, UInt<1>(0h0))
when _T_2017 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1461 assert (ldq(idx).valid, \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_62
assert(clock, ldq[idx].valid, UInt<1>(0h1), "") : assert_62
node _T_2018 = or(ldq[idx].bits.executed, ldq[idx].bits.forward_std_val)
node _T_2019 = and(_T_2018, ldq[idx].bits.succeeded)
node _T_2020 = asUInt(reset)
node _T_2021 = eq(_T_2020, UInt<1>(0h0))
when _T_2021 :
node _T_2022 = eq(_T_2019, UInt<1>(0h0))
when _T_2022 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1462 assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded ,\n") : printf_63
assert(clock, _T_2019, UInt<1>(0h1), "") : assert_63
connect ldq[idx].valid, UInt<1>(0h0)
connect ldq[idx].bits.addr.valid, UInt<1>(0h0)
connect ldq[idx].bits.executed, UInt<1>(0h0)
connect ldq[idx].bits.succeeded, UInt<1>(0h0)
connect ldq[idx].bits.order_fail, UInt<1>(0h0)
connect ldq[idx].bits.forward_std_val, UInt<1>(0h0)
node wrap_12 = eq(stq_commit_head, UInt<5>(0h17))
node _T_2023 = add(stq_commit_head, UInt<1>(0h1))
node _T_2024 = tail(_T_2023, 1)
node _T_2025 = mux(wrap_12, UInt<1>(0h0), _T_2024)
node _T_2026 = mux(commit_store, _T_2025, stq_commit_head)
node wrap_13 = eq(ldq_head, UInt<5>(0h17))
node _T_2027 = add(ldq_head, UInt<1>(0h1))
node _T_2028 = tail(_T_2027, 1)
node _T_2029 = mux(wrap_13, UInt<1>(0h0), _T_2028)
node _T_2030 = mux(commit_load, _T_2029, ldq_head)
node commit_store_1 = and(io.core.commit.valids[1], io.core.commit.uops[1].uses_stq)
node commit_load_1 = and(io.core.commit.valids[1], io.core.commit.uops[1].uses_ldq)
node idx_1 = mux(commit_store_1, _T_2026, _T_2030)
when commit_store_1 :
connect stq[idx_1].bits.committed, UInt<1>(0h1)
else :
when commit_load_1 :
node _T_2031 = asUInt(reset)
node _T_2032 = eq(_T_2031, UInt<1>(0h0))
when _T_2032 :
node _T_2033 = eq(ldq[idx_1].valid, UInt<1>(0h0))
when _T_2033 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1461 assert (ldq(idx).valid, \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_64
assert(clock, ldq[idx_1].valid, UInt<1>(0h1), "") : assert_64
node _T_2034 = or(ldq[idx_1].bits.executed, ldq[idx_1].bits.forward_std_val)
node _T_2035 = and(_T_2034, ldq[idx_1].bits.succeeded)
node _T_2036 = asUInt(reset)
node _T_2037 = eq(_T_2036, UInt<1>(0h0))
when _T_2037 :
node _T_2038 = eq(_T_2035, UInt<1>(0h0))
when _T_2038 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1462 assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded ,\n") : printf_65
assert(clock, _T_2035, UInt<1>(0h1), "") : assert_65
connect ldq[idx_1].valid, UInt<1>(0h0)
connect ldq[idx_1].bits.addr.valid, UInt<1>(0h0)
connect ldq[idx_1].bits.executed, UInt<1>(0h0)
connect ldq[idx_1].bits.succeeded, UInt<1>(0h0)
connect ldq[idx_1].bits.order_fail, UInt<1>(0h0)
connect ldq[idx_1].bits.forward_std_val, UInt<1>(0h0)
node wrap_14 = eq(_T_2026, UInt<5>(0h17))
node _T_2039 = add(_T_2026, UInt<1>(0h1))
node _T_2040 = tail(_T_2039, 1)
node _T_2041 = mux(wrap_14, UInt<1>(0h0), _T_2040)
node _T_2042 = mux(commit_store_1, _T_2041, _T_2026)
node wrap_15 = eq(_T_2030, UInt<5>(0h17))
node _T_2043 = add(_T_2030, UInt<1>(0h1))
node _T_2044 = tail(_T_2043, 1)
node _T_2045 = mux(wrap_15, UInt<1>(0h0), _T_2044)
node _T_2046 = mux(commit_load_1, _T_2045, _T_2030)
node commit_store_2 = and(io.core.commit.valids[2], io.core.commit.uops[2].uses_stq)
node commit_load_2 = and(io.core.commit.valids[2], io.core.commit.uops[2].uses_ldq)
node idx_2 = mux(commit_store_2, _T_2042, _T_2046)
when commit_store_2 :
connect stq[idx_2].bits.committed, UInt<1>(0h1)
else :
when commit_load_2 :
node _T_2047 = asUInt(reset)
node _T_2048 = eq(_T_2047, UInt<1>(0h0))
when _T_2048 :
node _T_2049 = eq(ldq[idx_2].valid, UInt<1>(0h0))
when _T_2049 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1461 assert (ldq(idx).valid, \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_66
assert(clock, ldq[idx_2].valid, UInt<1>(0h1), "") : assert_66
node _T_2050 = or(ldq[idx_2].bits.executed, ldq[idx_2].bits.forward_std_val)
node _T_2051 = and(_T_2050, ldq[idx_2].bits.succeeded)
node _T_2052 = asUInt(reset)
node _T_2053 = eq(_T_2052, UInt<1>(0h0))
when _T_2053 :
node _T_2054 = eq(_T_2051, UInt<1>(0h0))
when _T_2054 :
printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1462 assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded ,\n") : printf_67
assert(clock, _T_2051, UInt<1>(0h1), "") : assert_67
connect ldq[idx_2].valid, UInt<1>(0h0)
connect ldq[idx_2].bits.addr.valid, UInt<1>(0h0)
connect ldq[idx_2].bits.executed, UInt<1>(0h0)
connect ldq[idx_2].bits.succeeded, UInt<1>(0h0)
connect ldq[idx_2].bits.order_fail, UInt<1>(0h0)
connect ldq[idx_2].bits.forward_std_val, UInt<1>(0h0)
node wrap_16 = eq(_T_2042, UInt<5>(0h17))
node _T_2055 = add(_T_2042, UInt<1>(0h1))
node _T_2056 = tail(_T_2055, 1)
node _T_2057 = mux(wrap_16, UInt<1>(0h0), _T_2056)
node _T_2058 = mux(commit_store_2, _T_2057, _T_2042)
node wrap_17 = eq(_T_2046, UInt<5>(0h17))
node _T_2059 = add(_T_2046, UInt<1>(0h1))
node _T_2060 = tail(_T_2059, 1)
node _T_2061 = mux(wrap_17, UInt<1>(0h0), _T_2060)
node _T_2062 = mux(commit_load_2, _T_2061, _T_2046)
connect stq_commit_head, _T_2058
connect ldq_head, _T_2062
node _T_2063 = and(stq[stq_head].valid, stq[stq_head].bits.committed)
when _T_2063 :
node _T_2064 = eq(io.dmem.ordered, UInt<1>(0h0))
node _T_2065 = and(stq[stq_head].bits.uop.is_fence, _T_2064)
when _T_2065 :
connect io.dmem.force_order, UInt<1>(0h1)
connect store_needs_order, UInt<1>(0h1)
node _clear_store_T = mux(stq[stq_head].bits.uop.is_fence, io.dmem.ordered, stq[stq_head].bits.succeeded)
connect clear_store, _clear_store_T
when clear_store :
connect stq[stq_head].valid, UInt<1>(0h0)
connect stq[stq_head].bits.addr.valid, UInt<1>(0h0)
connect stq[stq_head].bits.data.valid, UInt<1>(0h0)
connect stq[stq_head].bits.succeeded, UInt<1>(0h0)
connect stq[stq_head].bits.committed, UInt<1>(0h0)
node stq_head_wrap = eq(stq_head, UInt<5>(0h17))
node _stq_head_T = add(stq_head, UInt<1>(0h1))
node _stq_head_T_1 = tail(_stq_head_T, 1)
node _stq_head_T_2 = mux(stq_head_wrap, UInt<1>(0h0), _stq_head_T_1)
connect stq_head, _stq_head_T_2
when stq[stq_head].bits.uop.is_fence :
node stq_execute_head_wrap_1 = eq(stq_execute_head, UInt<5>(0h17))
node _stq_execute_head_T_4 = add(stq_execute_head, UInt<1>(0h1))
node _stq_execute_head_T_5 = tail(_stq_execute_head_T_4, 1)
node _stq_execute_head_T_6 = mux(stq_execute_head_wrap_1, UInt<1>(0h0), _stq_execute_head_T_5)
connect stq_execute_head, _stq_execute_head_T_6
connect io.hellacache.req.ready, UInt<1>(0h0)
connect io.hellacache.s2_nack, UInt<1>(0h0)
wire _io_hellacache_s2_xcpt_WIRE : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}
connect _io_hellacache_s2_xcpt_WIRE.ae.st, UInt<1>(0h0)
connect _io_hellacache_s2_xcpt_WIRE.ae.ld, UInt<1>(0h0)
connect _io_hellacache_s2_xcpt_WIRE.gf.st, UInt<1>(0h0)
connect _io_hellacache_s2_xcpt_WIRE.gf.ld, UInt<1>(0h0)
connect _io_hellacache_s2_xcpt_WIRE.pf.st, UInt<1>(0h0)
connect _io_hellacache_s2_xcpt_WIRE.pf.ld, UInt<1>(0h0)
connect _io_hellacache_s2_xcpt_WIRE.ma.st, UInt<1>(0h0)
connect _io_hellacache_s2_xcpt_WIRE.ma.ld, UInt<1>(0h0)
connect io.hellacache.s2_xcpt, _io_hellacache_s2_xcpt_WIRE
connect io.hellacache.resp.valid, UInt<1>(0h0)
node _io_hellacache_store_pending_T = or(stq[0].valid, stq[1].valid)
node _io_hellacache_store_pending_T_1 = or(_io_hellacache_store_pending_T, stq[2].valid)
node _io_hellacache_store_pending_T_2 = or(_io_hellacache_store_pending_T_1, stq[3].valid)
node _io_hellacache_store_pending_T_3 = or(_io_hellacache_store_pending_T_2, stq[4].valid)
node _io_hellacache_store_pending_T_4 = or(_io_hellacache_store_pending_T_3, stq[5].valid)
node _io_hellacache_store_pending_T_5 = or(_io_hellacache_store_pending_T_4, stq[6].valid)
node _io_hellacache_store_pending_T_6 = or(_io_hellacache_store_pending_T_5, stq[7].valid)
node _io_hellacache_store_pending_T_7 = or(_io_hellacache_store_pending_T_6, stq[8].valid)
node _io_hellacache_store_pending_T_8 = or(_io_hellacache_store_pending_T_7, stq[9].valid)
node _io_hellacache_store_pending_T_9 = or(_io_hellacache_store_pending_T_8, stq[10].valid)
node _io_hellacache_store_pending_T_10 = or(_io_hellacache_store_pending_T_9, stq[11].valid)
node _io_hellacache_store_pending_T_11 = or(_io_hellacache_store_pending_T_10, stq[12].valid)
node _io_hellacache_store_pending_T_12 = or(_io_hellacache_store_pending_T_11, stq[13].valid)
node _io_hellacache_store_pending_T_13 = or(_io_hellacache_store_pending_T_12, stq[14].valid)
node _io_hellacache_store_pending_T_14 = or(_io_hellacache_store_pending_T_13, stq[15].valid)
node _io_hellacache_store_pending_T_15 = or(_io_hellacache_store_pending_T_14, stq[16].valid)
node _io_hellacache_store_pending_T_16 = or(_io_hellacache_store_pending_T_15, stq[17].valid)
node _io_hellacache_store_pending_T_17 = or(_io_hellacache_store_pending_T_16, stq[18].valid)
node _io_hellacache_store_pending_T_18 = or(_io_hellacache_store_pending_T_17, stq[19].valid)
node _io_hellacache_store_pending_T_19 = or(_io_hellacache_store_pending_T_18, stq[20].valid)
node _io_hellacache_store_pending_T_20 = or(_io_hellacache_store_pending_T_19, stq[21].valid)
node _io_hellacache_store_pending_T_21 = or(_io_hellacache_store_pending_T_20, stq[22].valid)
node _io_hellacache_store_pending_T_22 = or(_io_hellacache_store_pending_T_21, stq[23].valid)
connect io.hellacache.store_pending, _io_hellacache_store_pending_T_22
node _T_2066 = eq(hella_state, UInt<3>(0h0))
when _T_2066 :
connect io.hellacache.req.ready, UInt<1>(0h1)
node _T_2067 = and(io.hellacache.req.ready, io.hellacache.req.valid)
when _T_2067 :
connect hella_req, io.hellacache.req.bits
connect hella_state, UInt<3>(0h1)
else :
node _T_2068 = eq(hella_state, UInt<3>(0h1))
when _T_2068 :
connect can_fire_hella_incoming[0], UInt<1>(0h1)
connect hella_data, io.hellacache.s1_data
connect hella_xcpt.ae.st, dtlb.io.resp[0].ae.st
connect hella_xcpt.ae.ld, dtlb.io.resp[0].ae.ld
connect hella_xcpt.gf.st, dtlb.io.resp[0].gf.st
connect hella_xcpt.gf.ld, dtlb.io.resp[0].gf.ld
connect hella_xcpt.pf.st, dtlb.io.resp[0].pf.st
connect hella_xcpt.pf.ld, dtlb.io.resp[0].pf.ld
connect hella_xcpt.ma.st, dtlb.io.resp[0].ma.st
connect hella_xcpt.ma.ld, dtlb.io.resp[0].ma.ld
when io.hellacache.s1_kill :
node _T_2069 = and(will_fire_hella_incoming[0], dmem_req_fire[0])
when _T_2069 :
connect hella_state, UInt<3>(0h6)
else :
connect hella_state, UInt<3>(0h0)
else :
node _T_2070 = and(will_fire_hella_incoming[0], dmem_req_fire[0])
when _T_2070 :
connect hella_state, UInt<3>(0h2)
else :
connect hella_state, UInt<3>(0h3)
else :
node _T_2071 = eq(hella_state, UInt<3>(0h3))
when _T_2071 :
connect io.hellacache.s2_nack, UInt<1>(0h1)
connect hella_state, UInt<3>(0h0)
else :
node _T_2072 = eq(hella_state, UInt<3>(0h2))
when _T_2072 :
connect io.hellacache.s2_xcpt, hella_xcpt
node _T_2073 = cat(hella_xcpt.ae.ld, hella_xcpt.ae.st)
node _T_2074 = cat(hella_xcpt.gf.ld, hella_xcpt.gf.st)
node _T_2075 = cat(hella_xcpt.pf.ld, hella_xcpt.pf.st)
node _T_2076 = cat(hella_xcpt.ma.ld, hella_xcpt.ma.st)
node lo = cat(_T_2074, _T_2073)
node hi = cat(_T_2076, _T_2075)
node _T_2077 = cat(hi, lo)
node _T_2078 = neq(_T_2077, UInt<1>(0h0))
node _T_2079 = or(io.hellacache.s2_kill, _T_2078)
when _T_2079 :
connect hella_state, UInt<3>(0h6)
else :
connect hella_state, UInt<3>(0h4)
else :
node _T_2080 = eq(hella_state, UInt<3>(0h4))
when _T_2080 :
node _T_2081 = and(io.dmem.resp[0].valid, io.dmem.resp[0].bits.is_hella)
when _T_2081 :
connect hella_state, UInt<3>(0h0)
connect io.hellacache.resp.valid, UInt<1>(0h1)
connect io.hellacache.resp.bits.addr, hella_req.addr
connect io.hellacache.resp.bits.tag, hella_req.tag
connect io.hellacache.resp.bits.cmd, hella_req.cmd
connect io.hellacache.resp.bits.signed, hella_req.signed
connect io.hellacache.resp.bits.size, hella_req.size
connect io.hellacache.resp.bits.data, io.dmem.resp[0].bits.data
else :
node _T_2082 = and(io.dmem.nack[0].valid, io.dmem.nack[0].bits.is_hella)
when _T_2082 :
connect hella_state, UInt<3>(0h5)
else :
node _T_2083 = eq(hella_state, UInt<3>(0h5))
when _T_2083 :
connect can_fire_hella_wakeup[0], UInt<1>(0h1)
node _T_2084 = and(will_fire_hella_wakeup[0], dmem_req_fire[0])
when _T_2084 :
connect hella_state, UInt<3>(0h4)
else :
node _T_2085 = eq(hella_state, UInt<3>(0h6))
when _T_2085 :
node _T_2086 = and(io.dmem.resp[0].valid, io.dmem.resp[0].bits.is_hella)
when _T_2086 :
connect hella_state, UInt<3>(0h0)
wire _st_exc_killed_mask_WIRE : UInt<1>[24]
connect _st_exc_killed_mask_WIRE[0], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[1], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[2], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[3], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[4], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[5], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[6], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[7], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[8], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[9], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[10], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[11], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[12], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[13], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[14], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[15], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[16], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[17], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[18], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[19], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[20], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[21], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[22], UInt<1>(0h0)
connect _st_exc_killed_mask_WIRE[23], UInt<1>(0h0)
wire st_exc_killed_mask : UInt<1>[24]
connect st_exc_killed_mask, _st_exc_killed_mask_WIRE
node _T_2087 = asUInt(reset)
node _T_2088 = or(_T_2087, io.core.exception)
when _T_2088 :
connect ldq_head, UInt<1>(0h0)
connect ldq_tail, UInt<1>(0h0)
node _T_2089 = asUInt(reset)
when _T_2089 :
connect stq_head, UInt<1>(0h0)
connect stq_tail, UInt<1>(0h0)
connect stq_commit_head, UInt<1>(0h0)
connect stq_execute_head, UInt<1>(0h0)
connect stq[0].valid, UInt<1>(0h0)
connect stq[0].bits.addr.valid, UInt<1>(0h0)
connect stq[0].bits.data.valid, UInt<1>(0h0)
wire stq_0_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_0_bits_uop_uop.debug_tsrc
invalidate stq_0_bits_uop_uop.debug_fsrc
invalidate stq_0_bits_uop_uop.bp_xcpt_if
invalidate stq_0_bits_uop_uop.bp_debug_if
invalidate stq_0_bits_uop_uop.xcpt_ma_if
invalidate stq_0_bits_uop_uop.xcpt_ae_if
invalidate stq_0_bits_uop_uop.xcpt_pf_if
invalidate stq_0_bits_uop_uop.fp_single
invalidate stq_0_bits_uop_uop.fp_val
invalidate stq_0_bits_uop_uop.frs3_en
invalidate stq_0_bits_uop_uop.lrs2_rtype
invalidate stq_0_bits_uop_uop.lrs1_rtype
invalidate stq_0_bits_uop_uop.dst_rtype
invalidate stq_0_bits_uop_uop.ldst_val
invalidate stq_0_bits_uop_uop.lrs3
invalidate stq_0_bits_uop_uop.lrs2
invalidate stq_0_bits_uop_uop.lrs1
invalidate stq_0_bits_uop_uop.ldst
invalidate stq_0_bits_uop_uop.ldst_is_rs1
invalidate stq_0_bits_uop_uop.flush_on_commit
invalidate stq_0_bits_uop_uop.is_unique
invalidate stq_0_bits_uop_uop.is_sys_pc2epc
invalidate stq_0_bits_uop_uop.uses_stq
invalidate stq_0_bits_uop_uop.uses_ldq
invalidate stq_0_bits_uop_uop.is_amo
invalidate stq_0_bits_uop_uop.is_fencei
invalidate stq_0_bits_uop_uop.is_fence
invalidate stq_0_bits_uop_uop.mem_signed
invalidate stq_0_bits_uop_uop.mem_size
invalidate stq_0_bits_uop_uop.mem_cmd
invalidate stq_0_bits_uop_uop.bypassable
invalidate stq_0_bits_uop_uop.exc_cause
invalidate stq_0_bits_uop_uop.exception
invalidate stq_0_bits_uop_uop.stale_pdst
invalidate stq_0_bits_uop_uop.ppred_busy
invalidate stq_0_bits_uop_uop.prs3_busy
invalidate stq_0_bits_uop_uop.prs2_busy
invalidate stq_0_bits_uop_uop.prs1_busy
invalidate stq_0_bits_uop_uop.ppred
invalidate stq_0_bits_uop_uop.prs3
invalidate stq_0_bits_uop_uop.prs2
invalidate stq_0_bits_uop_uop.prs1
invalidate stq_0_bits_uop_uop.pdst
invalidate stq_0_bits_uop_uop.rxq_idx
invalidate stq_0_bits_uop_uop.stq_idx
invalidate stq_0_bits_uop_uop.ldq_idx
invalidate stq_0_bits_uop_uop.rob_idx
invalidate stq_0_bits_uop_uop.csr_addr
invalidate stq_0_bits_uop_uop.imm_packed
invalidate stq_0_bits_uop_uop.taken
invalidate stq_0_bits_uop_uop.pc_lob
invalidate stq_0_bits_uop_uop.edge_inst
invalidate stq_0_bits_uop_uop.ftq_idx
invalidate stq_0_bits_uop_uop.br_tag
invalidate stq_0_bits_uop_uop.br_mask
invalidate stq_0_bits_uop_uop.is_sfb
invalidate stq_0_bits_uop_uop.is_jal
invalidate stq_0_bits_uop_uop.is_jalr
invalidate stq_0_bits_uop_uop.is_br
invalidate stq_0_bits_uop_uop.iw_p2_poisoned
invalidate stq_0_bits_uop_uop.iw_p1_poisoned
invalidate stq_0_bits_uop_uop.iw_state
invalidate stq_0_bits_uop_uop.ctrl.is_std
invalidate stq_0_bits_uop_uop.ctrl.is_sta
invalidate stq_0_bits_uop_uop.ctrl.is_load
invalidate stq_0_bits_uop_uop.ctrl.csr_cmd
invalidate stq_0_bits_uop_uop.ctrl.fcn_dw
invalidate stq_0_bits_uop_uop.ctrl.op_fcn
invalidate stq_0_bits_uop_uop.ctrl.imm_sel
invalidate stq_0_bits_uop_uop.ctrl.op2_sel
invalidate stq_0_bits_uop_uop.ctrl.op1_sel
invalidate stq_0_bits_uop_uop.ctrl.br_type
invalidate stq_0_bits_uop_uop.fu_code
invalidate stq_0_bits_uop_uop.iq_type
invalidate stq_0_bits_uop_uop.debug_pc
invalidate stq_0_bits_uop_uop.is_rvc
invalidate stq_0_bits_uop_uop.debug_inst
invalidate stq_0_bits_uop_uop.inst
invalidate stq_0_bits_uop_uop.uopc
connect stq_0_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_0_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_0_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_0_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_0_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_0_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_0_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_0_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_0_bits_uop_cs.is_std
invalidate stq_0_bits_uop_cs.is_sta
invalidate stq_0_bits_uop_cs.is_load
invalidate stq_0_bits_uop_cs.csr_cmd
invalidate stq_0_bits_uop_cs.fcn_dw
invalidate stq_0_bits_uop_cs.op_fcn
invalidate stq_0_bits_uop_cs.imm_sel
invalidate stq_0_bits_uop_cs.op2_sel
invalidate stq_0_bits_uop_cs.op1_sel
invalidate stq_0_bits_uop_cs.br_type
connect stq_0_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_0_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_0_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_0_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_0_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_0_bits_uop_uop.ctrl, stq_0_bits_uop_cs
connect stq[0].bits.uop, stq_0_bits_uop_uop
connect stq[1].valid, UInt<1>(0h0)
connect stq[1].bits.addr.valid, UInt<1>(0h0)
connect stq[1].bits.data.valid, UInt<1>(0h0)
wire stq_1_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_1_bits_uop_uop.debug_tsrc
invalidate stq_1_bits_uop_uop.debug_fsrc
invalidate stq_1_bits_uop_uop.bp_xcpt_if
invalidate stq_1_bits_uop_uop.bp_debug_if
invalidate stq_1_bits_uop_uop.xcpt_ma_if
invalidate stq_1_bits_uop_uop.xcpt_ae_if
invalidate stq_1_bits_uop_uop.xcpt_pf_if
invalidate stq_1_bits_uop_uop.fp_single
invalidate stq_1_bits_uop_uop.fp_val
invalidate stq_1_bits_uop_uop.frs3_en
invalidate stq_1_bits_uop_uop.lrs2_rtype
invalidate stq_1_bits_uop_uop.lrs1_rtype
invalidate stq_1_bits_uop_uop.dst_rtype
invalidate stq_1_bits_uop_uop.ldst_val
invalidate stq_1_bits_uop_uop.lrs3
invalidate stq_1_bits_uop_uop.lrs2
invalidate stq_1_bits_uop_uop.lrs1
invalidate stq_1_bits_uop_uop.ldst
invalidate stq_1_bits_uop_uop.ldst_is_rs1
invalidate stq_1_bits_uop_uop.flush_on_commit
invalidate stq_1_bits_uop_uop.is_unique
invalidate stq_1_bits_uop_uop.is_sys_pc2epc
invalidate stq_1_bits_uop_uop.uses_stq
invalidate stq_1_bits_uop_uop.uses_ldq
invalidate stq_1_bits_uop_uop.is_amo
invalidate stq_1_bits_uop_uop.is_fencei
invalidate stq_1_bits_uop_uop.is_fence
invalidate stq_1_bits_uop_uop.mem_signed
invalidate stq_1_bits_uop_uop.mem_size
invalidate stq_1_bits_uop_uop.mem_cmd
invalidate stq_1_bits_uop_uop.bypassable
invalidate stq_1_bits_uop_uop.exc_cause
invalidate stq_1_bits_uop_uop.exception
invalidate stq_1_bits_uop_uop.stale_pdst
invalidate stq_1_bits_uop_uop.ppred_busy
invalidate stq_1_bits_uop_uop.prs3_busy
invalidate stq_1_bits_uop_uop.prs2_busy
invalidate stq_1_bits_uop_uop.prs1_busy
invalidate stq_1_bits_uop_uop.ppred
invalidate stq_1_bits_uop_uop.prs3
invalidate stq_1_bits_uop_uop.prs2
invalidate stq_1_bits_uop_uop.prs1
invalidate stq_1_bits_uop_uop.pdst
invalidate stq_1_bits_uop_uop.rxq_idx
invalidate stq_1_bits_uop_uop.stq_idx
invalidate stq_1_bits_uop_uop.ldq_idx
invalidate stq_1_bits_uop_uop.rob_idx
invalidate stq_1_bits_uop_uop.csr_addr
invalidate stq_1_bits_uop_uop.imm_packed
invalidate stq_1_bits_uop_uop.taken
invalidate stq_1_bits_uop_uop.pc_lob
invalidate stq_1_bits_uop_uop.edge_inst
invalidate stq_1_bits_uop_uop.ftq_idx
invalidate stq_1_bits_uop_uop.br_tag
invalidate stq_1_bits_uop_uop.br_mask
invalidate stq_1_bits_uop_uop.is_sfb
invalidate stq_1_bits_uop_uop.is_jal
invalidate stq_1_bits_uop_uop.is_jalr
invalidate stq_1_bits_uop_uop.is_br
invalidate stq_1_bits_uop_uop.iw_p2_poisoned
invalidate stq_1_bits_uop_uop.iw_p1_poisoned
invalidate stq_1_bits_uop_uop.iw_state
invalidate stq_1_bits_uop_uop.ctrl.is_std
invalidate stq_1_bits_uop_uop.ctrl.is_sta
invalidate stq_1_bits_uop_uop.ctrl.is_load
invalidate stq_1_bits_uop_uop.ctrl.csr_cmd
invalidate stq_1_bits_uop_uop.ctrl.fcn_dw
invalidate stq_1_bits_uop_uop.ctrl.op_fcn
invalidate stq_1_bits_uop_uop.ctrl.imm_sel
invalidate stq_1_bits_uop_uop.ctrl.op2_sel
invalidate stq_1_bits_uop_uop.ctrl.op1_sel
invalidate stq_1_bits_uop_uop.ctrl.br_type
invalidate stq_1_bits_uop_uop.fu_code
invalidate stq_1_bits_uop_uop.iq_type
invalidate stq_1_bits_uop_uop.debug_pc
invalidate stq_1_bits_uop_uop.is_rvc
invalidate stq_1_bits_uop_uop.debug_inst
invalidate stq_1_bits_uop_uop.inst
invalidate stq_1_bits_uop_uop.uopc
connect stq_1_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_1_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_1_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_1_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_1_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_1_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_1_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_1_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_1_bits_uop_cs.is_std
invalidate stq_1_bits_uop_cs.is_sta
invalidate stq_1_bits_uop_cs.is_load
invalidate stq_1_bits_uop_cs.csr_cmd
invalidate stq_1_bits_uop_cs.fcn_dw
invalidate stq_1_bits_uop_cs.op_fcn
invalidate stq_1_bits_uop_cs.imm_sel
invalidate stq_1_bits_uop_cs.op2_sel
invalidate stq_1_bits_uop_cs.op1_sel
invalidate stq_1_bits_uop_cs.br_type
connect stq_1_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_1_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_1_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_1_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_1_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_1_bits_uop_uop.ctrl, stq_1_bits_uop_cs
connect stq[1].bits.uop, stq_1_bits_uop_uop
connect stq[2].valid, UInt<1>(0h0)
connect stq[2].bits.addr.valid, UInt<1>(0h0)
connect stq[2].bits.data.valid, UInt<1>(0h0)
wire stq_2_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_2_bits_uop_uop.debug_tsrc
invalidate stq_2_bits_uop_uop.debug_fsrc
invalidate stq_2_bits_uop_uop.bp_xcpt_if
invalidate stq_2_bits_uop_uop.bp_debug_if
invalidate stq_2_bits_uop_uop.xcpt_ma_if
invalidate stq_2_bits_uop_uop.xcpt_ae_if
invalidate stq_2_bits_uop_uop.xcpt_pf_if
invalidate stq_2_bits_uop_uop.fp_single
invalidate stq_2_bits_uop_uop.fp_val
invalidate stq_2_bits_uop_uop.frs3_en
invalidate stq_2_bits_uop_uop.lrs2_rtype
invalidate stq_2_bits_uop_uop.lrs1_rtype
invalidate stq_2_bits_uop_uop.dst_rtype
invalidate stq_2_bits_uop_uop.ldst_val
invalidate stq_2_bits_uop_uop.lrs3
invalidate stq_2_bits_uop_uop.lrs2
invalidate stq_2_bits_uop_uop.lrs1
invalidate stq_2_bits_uop_uop.ldst
invalidate stq_2_bits_uop_uop.ldst_is_rs1
invalidate stq_2_bits_uop_uop.flush_on_commit
invalidate stq_2_bits_uop_uop.is_unique
invalidate stq_2_bits_uop_uop.is_sys_pc2epc
invalidate stq_2_bits_uop_uop.uses_stq
invalidate stq_2_bits_uop_uop.uses_ldq
invalidate stq_2_bits_uop_uop.is_amo
invalidate stq_2_bits_uop_uop.is_fencei
invalidate stq_2_bits_uop_uop.is_fence
invalidate stq_2_bits_uop_uop.mem_signed
invalidate stq_2_bits_uop_uop.mem_size
invalidate stq_2_bits_uop_uop.mem_cmd
invalidate stq_2_bits_uop_uop.bypassable
invalidate stq_2_bits_uop_uop.exc_cause
invalidate stq_2_bits_uop_uop.exception
invalidate stq_2_bits_uop_uop.stale_pdst
invalidate stq_2_bits_uop_uop.ppred_busy
invalidate stq_2_bits_uop_uop.prs3_busy
invalidate stq_2_bits_uop_uop.prs2_busy
invalidate stq_2_bits_uop_uop.prs1_busy
invalidate stq_2_bits_uop_uop.ppred
invalidate stq_2_bits_uop_uop.prs3
invalidate stq_2_bits_uop_uop.prs2
invalidate stq_2_bits_uop_uop.prs1
invalidate stq_2_bits_uop_uop.pdst
invalidate stq_2_bits_uop_uop.rxq_idx
invalidate stq_2_bits_uop_uop.stq_idx
invalidate stq_2_bits_uop_uop.ldq_idx
invalidate stq_2_bits_uop_uop.rob_idx
invalidate stq_2_bits_uop_uop.csr_addr
invalidate stq_2_bits_uop_uop.imm_packed
invalidate stq_2_bits_uop_uop.taken
invalidate stq_2_bits_uop_uop.pc_lob
invalidate stq_2_bits_uop_uop.edge_inst
invalidate stq_2_bits_uop_uop.ftq_idx
invalidate stq_2_bits_uop_uop.br_tag
invalidate stq_2_bits_uop_uop.br_mask
invalidate stq_2_bits_uop_uop.is_sfb
invalidate stq_2_bits_uop_uop.is_jal
invalidate stq_2_bits_uop_uop.is_jalr
invalidate stq_2_bits_uop_uop.is_br
invalidate stq_2_bits_uop_uop.iw_p2_poisoned
invalidate stq_2_bits_uop_uop.iw_p1_poisoned
invalidate stq_2_bits_uop_uop.iw_state
invalidate stq_2_bits_uop_uop.ctrl.is_std
invalidate stq_2_bits_uop_uop.ctrl.is_sta
invalidate stq_2_bits_uop_uop.ctrl.is_load
invalidate stq_2_bits_uop_uop.ctrl.csr_cmd
invalidate stq_2_bits_uop_uop.ctrl.fcn_dw
invalidate stq_2_bits_uop_uop.ctrl.op_fcn
invalidate stq_2_bits_uop_uop.ctrl.imm_sel
invalidate stq_2_bits_uop_uop.ctrl.op2_sel
invalidate stq_2_bits_uop_uop.ctrl.op1_sel
invalidate stq_2_bits_uop_uop.ctrl.br_type
invalidate stq_2_bits_uop_uop.fu_code
invalidate stq_2_bits_uop_uop.iq_type
invalidate stq_2_bits_uop_uop.debug_pc
invalidate stq_2_bits_uop_uop.is_rvc
invalidate stq_2_bits_uop_uop.debug_inst
invalidate stq_2_bits_uop_uop.inst
invalidate stq_2_bits_uop_uop.uopc
connect stq_2_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_2_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_2_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_2_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_2_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_2_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_2_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_2_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_2_bits_uop_cs.is_std
invalidate stq_2_bits_uop_cs.is_sta
invalidate stq_2_bits_uop_cs.is_load
invalidate stq_2_bits_uop_cs.csr_cmd
invalidate stq_2_bits_uop_cs.fcn_dw
invalidate stq_2_bits_uop_cs.op_fcn
invalidate stq_2_bits_uop_cs.imm_sel
invalidate stq_2_bits_uop_cs.op2_sel
invalidate stq_2_bits_uop_cs.op1_sel
invalidate stq_2_bits_uop_cs.br_type
connect stq_2_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_2_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_2_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_2_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_2_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_2_bits_uop_uop.ctrl, stq_2_bits_uop_cs
connect stq[2].bits.uop, stq_2_bits_uop_uop
connect stq[3].valid, UInt<1>(0h0)
connect stq[3].bits.addr.valid, UInt<1>(0h0)
connect stq[3].bits.data.valid, UInt<1>(0h0)
wire stq_3_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_3_bits_uop_uop.debug_tsrc
invalidate stq_3_bits_uop_uop.debug_fsrc
invalidate stq_3_bits_uop_uop.bp_xcpt_if
invalidate stq_3_bits_uop_uop.bp_debug_if
invalidate stq_3_bits_uop_uop.xcpt_ma_if
invalidate stq_3_bits_uop_uop.xcpt_ae_if
invalidate stq_3_bits_uop_uop.xcpt_pf_if
invalidate stq_3_bits_uop_uop.fp_single
invalidate stq_3_bits_uop_uop.fp_val
invalidate stq_3_bits_uop_uop.frs3_en
invalidate stq_3_bits_uop_uop.lrs2_rtype
invalidate stq_3_bits_uop_uop.lrs1_rtype
invalidate stq_3_bits_uop_uop.dst_rtype
invalidate stq_3_bits_uop_uop.ldst_val
invalidate stq_3_bits_uop_uop.lrs3
invalidate stq_3_bits_uop_uop.lrs2
invalidate stq_3_bits_uop_uop.lrs1
invalidate stq_3_bits_uop_uop.ldst
invalidate stq_3_bits_uop_uop.ldst_is_rs1
invalidate stq_3_bits_uop_uop.flush_on_commit
invalidate stq_3_bits_uop_uop.is_unique
invalidate stq_3_bits_uop_uop.is_sys_pc2epc
invalidate stq_3_bits_uop_uop.uses_stq
invalidate stq_3_bits_uop_uop.uses_ldq
invalidate stq_3_bits_uop_uop.is_amo
invalidate stq_3_bits_uop_uop.is_fencei
invalidate stq_3_bits_uop_uop.is_fence
invalidate stq_3_bits_uop_uop.mem_signed
invalidate stq_3_bits_uop_uop.mem_size
invalidate stq_3_bits_uop_uop.mem_cmd
invalidate stq_3_bits_uop_uop.bypassable
invalidate stq_3_bits_uop_uop.exc_cause
invalidate stq_3_bits_uop_uop.exception
invalidate stq_3_bits_uop_uop.stale_pdst
invalidate stq_3_bits_uop_uop.ppred_busy
invalidate stq_3_bits_uop_uop.prs3_busy
invalidate stq_3_bits_uop_uop.prs2_busy
invalidate stq_3_bits_uop_uop.prs1_busy
invalidate stq_3_bits_uop_uop.ppred
invalidate stq_3_bits_uop_uop.prs3
invalidate stq_3_bits_uop_uop.prs2
invalidate stq_3_bits_uop_uop.prs1
invalidate stq_3_bits_uop_uop.pdst
invalidate stq_3_bits_uop_uop.rxq_idx
invalidate stq_3_bits_uop_uop.stq_idx
invalidate stq_3_bits_uop_uop.ldq_idx
invalidate stq_3_bits_uop_uop.rob_idx
invalidate stq_3_bits_uop_uop.csr_addr
invalidate stq_3_bits_uop_uop.imm_packed
invalidate stq_3_bits_uop_uop.taken
invalidate stq_3_bits_uop_uop.pc_lob
invalidate stq_3_bits_uop_uop.edge_inst
invalidate stq_3_bits_uop_uop.ftq_idx
invalidate stq_3_bits_uop_uop.br_tag
invalidate stq_3_bits_uop_uop.br_mask
invalidate stq_3_bits_uop_uop.is_sfb
invalidate stq_3_bits_uop_uop.is_jal
invalidate stq_3_bits_uop_uop.is_jalr
invalidate stq_3_bits_uop_uop.is_br
invalidate stq_3_bits_uop_uop.iw_p2_poisoned
invalidate stq_3_bits_uop_uop.iw_p1_poisoned
invalidate stq_3_bits_uop_uop.iw_state
invalidate stq_3_bits_uop_uop.ctrl.is_std
invalidate stq_3_bits_uop_uop.ctrl.is_sta
invalidate stq_3_bits_uop_uop.ctrl.is_load
invalidate stq_3_bits_uop_uop.ctrl.csr_cmd
invalidate stq_3_bits_uop_uop.ctrl.fcn_dw
invalidate stq_3_bits_uop_uop.ctrl.op_fcn
invalidate stq_3_bits_uop_uop.ctrl.imm_sel
invalidate stq_3_bits_uop_uop.ctrl.op2_sel
invalidate stq_3_bits_uop_uop.ctrl.op1_sel
invalidate stq_3_bits_uop_uop.ctrl.br_type
invalidate stq_3_bits_uop_uop.fu_code
invalidate stq_3_bits_uop_uop.iq_type
invalidate stq_3_bits_uop_uop.debug_pc
invalidate stq_3_bits_uop_uop.is_rvc
invalidate stq_3_bits_uop_uop.debug_inst
invalidate stq_3_bits_uop_uop.inst
invalidate stq_3_bits_uop_uop.uopc
connect stq_3_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_3_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_3_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_3_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_3_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_3_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_3_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_3_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_3_bits_uop_cs.is_std
invalidate stq_3_bits_uop_cs.is_sta
invalidate stq_3_bits_uop_cs.is_load
invalidate stq_3_bits_uop_cs.csr_cmd
invalidate stq_3_bits_uop_cs.fcn_dw
invalidate stq_3_bits_uop_cs.op_fcn
invalidate stq_3_bits_uop_cs.imm_sel
invalidate stq_3_bits_uop_cs.op2_sel
invalidate stq_3_bits_uop_cs.op1_sel
invalidate stq_3_bits_uop_cs.br_type
connect stq_3_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_3_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_3_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_3_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_3_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_3_bits_uop_uop.ctrl, stq_3_bits_uop_cs
connect stq[3].bits.uop, stq_3_bits_uop_uop
connect stq[4].valid, UInt<1>(0h0)
connect stq[4].bits.addr.valid, UInt<1>(0h0)
connect stq[4].bits.data.valid, UInt<1>(0h0)
wire stq_4_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_4_bits_uop_uop.debug_tsrc
invalidate stq_4_bits_uop_uop.debug_fsrc
invalidate stq_4_bits_uop_uop.bp_xcpt_if
invalidate stq_4_bits_uop_uop.bp_debug_if
invalidate stq_4_bits_uop_uop.xcpt_ma_if
invalidate stq_4_bits_uop_uop.xcpt_ae_if
invalidate stq_4_bits_uop_uop.xcpt_pf_if
invalidate stq_4_bits_uop_uop.fp_single
invalidate stq_4_bits_uop_uop.fp_val
invalidate stq_4_bits_uop_uop.frs3_en
invalidate stq_4_bits_uop_uop.lrs2_rtype
invalidate stq_4_bits_uop_uop.lrs1_rtype
invalidate stq_4_bits_uop_uop.dst_rtype
invalidate stq_4_bits_uop_uop.ldst_val
invalidate stq_4_bits_uop_uop.lrs3
invalidate stq_4_bits_uop_uop.lrs2
invalidate stq_4_bits_uop_uop.lrs1
invalidate stq_4_bits_uop_uop.ldst
invalidate stq_4_bits_uop_uop.ldst_is_rs1
invalidate stq_4_bits_uop_uop.flush_on_commit
invalidate stq_4_bits_uop_uop.is_unique
invalidate stq_4_bits_uop_uop.is_sys_pc2epc
invalidate stq_4_bits_uop_uop.uses_stq
invalidate stq_4_bits_uop_uop.uses_ldq
invalidate stq_4_bits_uop_uop.is_amo
invalidate stq_4_bits_uop_uop.is_fencei
invalidate stq_4_bits_uop_uop.is_fence
invalidate stq_4_bits_uop_uop.mem_signed
invalidate stq_4_bits_uop_uop.mem_size
invalidate stq_4_bits_uop_uop.mem_cmd
invalidate stq_4_bits_uop_uop.bypassable
invalidate stq_4_bits_uop_uop.exc_cause
invalidate stq_4_bits_uop_uop.exception
invalidate stq_4_bits_uop_uop.stale_pdst
invalidate stq_4_bits_uop_uop.ppred_busy
invalidate stq_4_bits_uop_uop.prs3_busy
invalidate stq_4_bits_uop_uop.prs2_busy
invalidate stq_4_bits_uop_uop.prs1_busy
invalidate stq_4_bits_uop_uop.ppred
invalidate stq_4_bits_uop_uop.prs3
invalidate stq_4_bits_uop_uop.prs2
invalidate stq_4_bits_uop_uop.prs1
invalidate stq_4_bits_uop_uop.pdst
invalidate stq_4_bits_uop_uop.rxq_idx
invalidate stq_4_bits_uop_uop.stq_idx
invalidate stq_4_bits_uop_uop.ldq_idx
invalidate stq_4_bits_uop_uop.rob_idx
invalidate stq_4_bits_uop_uop.csr_addr
invalidate stq_4_bits_uop_uop.imm_packed
invalidate stq_4_bits_uop_uop.taken
invalidate stq_4_bits_uop_uop.pc_lob
invalidate stq_4_bits_uop_uop.edge_inst
invalidate stq_4_bits_uop_uop.ftq_idx
invalidate stq_4_bits_uop_uop.br_tag
invalidate stq_4_bits_uop_uop.br_mask
invalidate stq_4_bits_uop_uop.is_sfb
invalidate stq_4_bits_uop_uop.is_jal
invalidate stq_4_bits_uop_uop.is_jalr
invalidate stq_4_bits_uop_uop.is_br
invalidate stq_4_bits_uop_uop.iw_p2_poisoned
invalidate stq_4_bits_uop_uop.iw_p1_poisoned
invalidate stq_4_bits_uop_uop.iw_state
invalidate stq_4_bits_uop_uop.ctrl.is_std
invalidate stq_4_bits_uop_uop.ctrl.is_sta
invalidate stq_4_bits_uop_uop.ctrl.is_load
invalidate stq_4_bits_uop_uop.ctrl.csr_cmd
invalidate stq_4_bits_uop_uop.ctrl.fcn_dw
invalidate stq_4_bits_uop_uop.ctrl.op_fcn
invalidate stq_4_bits_uop_uop.ctrl.imm_sel
invalidate stq_4_bits_uop_uop.ctrl.op2_sel
invalidate stq_4_bits_uop_uop.ctrl.op1_sel
invalidate stq_4_bits_uop_uop.ctrl.br_type
invalidate stq_4_bits_uop_uop.fu_code
invalidate stq_4_bits_uop_uop.iq_type
invalidate stq_4_bits_uop_uop.debug_pc
invalidate stq_4_bits_uop_uop.is_rvc
invalidate stq_4_bits_uop_uop.debug_inst
invalidate stq_4_bits_uop_uop.inst
invalidate stq_4_bits_uop_uop.uopc
connect stq_4_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_4_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_4_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_4_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_4_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_4_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_4_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_4_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_4_bits_uop_cs.is_std
invalidate stq_4_bits_uop_cs.is_sta
invalidate stq_4_bits_uop_cs.is_load
invalidate stq_4_bits_uop_cs.csr_cmd
invalidate stq_4_bits_uop_cs.fcn_dw
invalidate stq_4_bits_uop_cs.op_fcn
invalidate stq_4_bits_uop_cs.imm_sel
invalidate stq_4_bits_uop_cs.op2_sel
invalidate stq_4_bits_uop_cs.op1_sel
invalidate stq_4_bits_uop_cs.br_type
connect stq_4_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_4_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_4_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_4_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_4_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_4_bits_uop_uop.ctrl, stq_4_bits_uop_cs
connect stq[4].bits.uop, stq_4_bits_uop_uop
connect stq[5].valid, UInt<1>(0h0)
connect stq[5].bits.addr.valid, UInt<1>(0h0)
connect stq[5].bits.data.valid, UInt<1>(0h0)
wire stq_5_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_5_bits_uop_uop.debug_tsrc
invalidate stq_5_bits_uop_uop.debug_fsrc
invalidate stq_5_bits_uop_uop.bp_xcpt_if
invalidate stq_5_bits_uop_uop.bp_debug_if
invalidate stq_5_bits_uop_uop.xcpt_ma_if
invalidate stq_5_bits_uop_uop.xcpt_ae_if
invalidate stq_5_bits_uop_uop.xcpt_pf_if
invalidate stq_5_bits_uop_uop.fp_single
invalidate stq_5_bits_uop_uop.fp_val
invalidate stq_5_bits_uop_uop.frs3_en
invalidate stq_5_bits_uop_uop.lrs2_rtype
invalidate stq_5_bits_uop_uop.lrs1_rtype
invalidate stq_5_bits_uop_uop.dst_rtype
invalidate stq_5_bits_uop_uop.ldst_val
invalidate stq_5_bits_uop_uop.lrs3
invalidate stq_5_bits_uop_uop.lrs2
invalidate stq_5_bits_uop_uop.lrs1
invalidate stq_5_bits_uop_uop.ldst
invalidate stq_5_bits_uop_uop.ldst_is_rs1
invalidate stq_5_bits_uop_uop.flush_on_commit
invalidate stq_5_bits_uop_uop.is_unique
invalidate stq_5_bits_uop_uop.is_sys_pc2epc
invalidate stq_5_bits_uop_uop.uses_stq
invalidate stq_5_bits_uop_uop.uses_ldq
invalidate stq_5_bits_uop_uop.is_amo
invalidate stq_5_bits_uop_uop.is_fencei
invalidate stq_5_bits_uop_uop.is_fence
invalidate stq_5_bits_uop_uop.mem_signed
invalidate stq_5_bits_uop_uop.mem_size
invalidate stq_5_bits_uop_uop.mem_cmd
invalidate stq_5_bits_uop_uop.bypassable
invalidate stq_5_bits_uop_uop.exc_cause
invalidate stq_5_bits_uop_uop.exception
invalidate stq_5_bits_uop_uop.stale_pdst
invalidate stq_5_bits_uop_uop.ppred_busy
invalidate stq_5_bits_uop_uop.prs3_busy
invalidate stq_5_bits_uop_uop.prs2_busy
invalidate stq_5_bits_uop_uop.prs1_busy
invalidate stq_5_bits_uop_uop.ppred
invalidate stq_5_bits_uop_uop.prs3
invalidate stq_5_bits_uop_uop.prs2
invalidate stq_5_bits_uop_uop.prs1
invalidate stq_5_bits_uop_uop.pdst
invalidate stq_5_bits_uop_uop.rxq_idx
invalidate stq_5_bits_uop_uop.stq_idx
invalidate stq_5_bits_uop_uop.ldq_idx
invalidate stq_5_bits_uop_uop.rob_idx
invalidate stq_5_bits_uop_uop.csr_addr
invalidate stq_5_bits_uop_uop.imm_packed
invalidate stq_5_bits_uop_uop.taken
invalidate stq_5_bits_uop_uop.pc_lob
invalidate stq_5_bits_uop_uop.edge_inst
invalidate stq_5_bits_uop_uop.ftq_idx
invalidate stq_5_bits_uop_uop.br_tag
invalidate stq_5_bits_uop_uop.br_mask
invalidate stq_5_bits_uop_uop.is_sfb
invalidate stq_5_bits_uop_uop.is_jal
invalidate stq_5_bits_uop_uop.is_jalr
invalidate stq_5_bits_uop_uop.is_br
invalidate stq_5_bits_uop_uop.iw_p2_poisoned
invalidate stq_5_bits_uop_uop.iw_p1_poisoned
invalidate stq_5_bits_uop_uop.iw_state
invalidate stq_5_bits_uop_uop.ctrl.is_std
invalidate stq_5_bits_uop_uop.ctrl.is_sta
invalidate stq_5_bits_uop_uop.ctrl.is_load
invalidate stq_5_bits_uop_uop.ctrl.csr_cmd
invalidate stq_5_bits_uop_uop.ctrl.fcn_dw
invalidate stq_5_bits_uop_uop.ctrl.op_fcn
invalidate stq_5_bits_uop_uop.ctrl.imm_sel
invalidate stq_5_bits_uop_uop.ctrl.op2_sel
invalidate stq_5_bits_uop_uop.ctrl.op1_sel
invalidate stq_5_bits_uop_uop.ctrl.br_type
invalidate stq_5_bits_uop_uop.fu_code
invalidate stq_5_bits_uop_uop.iq_type
invalidate stq_5_bits_uop_uop.debug_pc
invalidate stq_5_bits_uop_uop.is_rvc
invalidate stq_5_bits_uop_uop.debug_inst
invalidate stq_5_bits_uop_uop.inst
invalidate stq_5_bits_uop_uop.uopc
connect stq_5_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_5_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_5_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_5_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_5_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_5_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_5_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_5_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_5_bits_uop_cs.is_std
invalidate stq_5_bits_uop_cs.is_sta
invalidate stq_5_bits_uop_cs.is_load
invalidate stq_5_bits_uop_cs.csr_cmd
invalidate stq_5_bits_uop_cs.fcn_dw
invalidate stq_5_bits_uop_cs.op_fcn
invalidate stq_5_bits_uop_cs.imm_sel
invalidate stq_5_bits_uop_cs.op2_sel
invalidate stq_5_bits_uop_cs.op1_sel
invalidate stq_5_bits_uop_cs.br_type
connect stq_5_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_5_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_5_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_5_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_5_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_5_bits_uop_uop.ctrl, stq_5_bits_uop_cs
connect stq[5].bits.uop, stq_5_bits_uop_uop
connect stq[6].valid, UInt<1>(0h0)
connect stq[6].bits.addr.valid, UInt<1>(0h0)
connect stq[6].bits.data.valid, UInt<1>(0h0)
wire stq_6_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_6_bits_uop_uop.debug_tsrc
invalidate stq_6_bits_uop_uop.debug_fsrc
invalidate stq_6_bits_uop_uop.bp_xcpt_if
invalidate stq_6_bits_uop_uop.bp_debug_if
invalidate stq_6_bits_uop_uop.xcpt_ma_if
invalidate stq_6_bits_uop_uop.xcpt_ae_if
invalidate stq_6_bits_uop_uop.xcpt_pf_if
invalidate stq_6_bits_uop_uop.fp_single
invalidate stq_6_bits_uop_uop.fp_val
invalidate stq_6_bits_uop_uop.frs3_en
invalidate stq_6_bits_uop_uop.lrs2_rtype
invalidate stq_6_bits_uop_uop.lrs1_rtype
invalidate stq_6_bits_uop_uop.dst_rtype
invalidate stq_6_bits_uop_uop.ldst_val
invalidate stq_6_bits_uop_uop.lrs3
invalidate stq_6_bits_uop_uop.lrs2
invalidate stq_6_bits_uop_uop.lrs1
invalidate stq_6_bits_uop_uop.ldst
invalidate stq_6_bits_uop_uop.ldst_is_rs1
invalidate stq_6_bits_uop_uop.flush_on_commit
invalidate stq_6_bits_uop_uop.is_unique
invalidate stq_6_bits_uop_uop.is_sys_pc2epc
invalidate stq_6_bits_uop_uop.uses_stq
invalidate stq_6_bits_uop_uop.uses_ldq
invalidate stq_6_bits_uop_uop.is_amo
invalidate stq_6_bits_uop_uop.is_fencei
invalidate stq_6_bits_uop_uop.is_fence
invalidate stq_6_bits_uop_uop.mem_signed
invalidate stq_6_bits_uop_uop.mem_size
invalidate stq_6_bits_uop_uop.mem_cmd
invalidate stq_6_bits_uop_uop.bypassable
invalidate stq_6_bits_uop_uop.exc_cause
invalidate stq_6_bits_uop_uop.exception
invalidate stq_6_bits_uop_uop.stale_pdst
invalidate stq_6_bits_uop_uop.ppred_busy
invalidate stq_6_bits_uop_uop.prs3_busy
invalidate stq_6_bits_uop_uop.prs2_busy
invalidate stq_6_bits_uop_uop.prs1_busy
invalidate stq_6_bits_uop_uop.ppred
invalidate stq_6_bits_uop_uop.prs3
invalidate stq_6_bits_uop_uop.prs2
invalidate stq_6_bits_uop_uop.prs1
invalidate stq_6_bits_uop_uop.pdst
invalidate stq_6_bits_uop_uop.rxq_idx
invalidate stq_6_bits_uop_uop.stq_idx
invalidate stq_6_bits_uop_uop.ldq_idx
invalidate stq_6_bits_uop_uop.rob_idx
invalidate stq_6_bits_uop_uop.csr_addr
invalidate stq_6_bits_uop_uop.imm_packed
invalidate stq_6_bits_uop_uop.taken
invalidate stq_6_bits_uop_uop.pc_lob
invalidate stq_6_bits_uop_uop.edge_inst
invalidate stq_6_bits_uop_uop.ftq_idx
invalidate stq_6_bits_uop_uop.br_tag
invalidate stq_6_bits_uop_uop.br_mask
invalidate stq_6_bits_uop_uop.is_sfb
invalidate stq_6_bits_uop_uop.is_jal
invalidate stq_6_bits_uop_uop.is_jalr
invalidate stq_6_bits_uop_uop.is_br
invalidate stq_6_bits_uop_uop.iw_p2_poisoned
invalidate stq_6_bits_uop_uop.iw_p1_poisoned
invalidate stq_6_bits_uop_uop.iw_state
invalidate stq_6_bits_uop_uop.ctrl.is_std
invalidate stq_6_bits_uop_uop.ctrl.is_sta
invalidate stq_6_bits_uop_uop.ctrl.is_load
invalidate stq_6_bits_uop_uop.ctrl.csr_cmd
invalidate stq_6_bits_uop_uop.ctrl.fcn_dw
invalidate stq_6_bits_uop_uop.ctrl.op_fcn
invalidate stq_6_bits_uop_uop.ctrl.imm_sel
invalidate stq_6_bits_uop_uop.ctrl.op2_sel
invalidate stq_6_bits_uop_uop.ctrl.op1_sel
invalidate stq_6_bits_uop_uop.ctrl.br_type
invalidate stq_6_bits_uop_uop.fu_code
invalidate stq_6_bits_uop_uop.iq_type
invalidate stq_6_bits_uop_uop.debug_pc
invalidate stq_6_bits_uop_uop.is_rvc
invalidate stq_6_bits_uop_uop.debug_inst
invalidate stq_6_bits_uop_uop.inst
invalidate stq_6_bits_uop_uop.uopc
connect stq_6_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_6_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_6_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_6_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_6_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_6_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_6_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_6_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_6_bits_uop_cs.is_std
invalidate stq_6_bits_uop_cs.is_sta
invalidate stq_6_bits_uop_cs.is_load
invalidate stq_6_bits_uop_cs.csr_cmd
invalidate stq_6_bits_uop_cs.fcn_dw
invalidate stq_6_bits_uop_cs.op_fcn
invalidate stq_6_bits_uop_cs.imm_sel
invalidate stq_6_bits_uop_cs.op2_sel
invalidate stq_6_bits_uop_cs.op1_sel
invalidate stq_6_bits_uop_cs.br_type
connect stq_6_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_6_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_6_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_6_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_6_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_6_bits_uop_uop.ctrl, stq_6_bits_uop_cs
connect stq[6].bits.uop, stq_6_bits_uop_uop
connect stq[7].valid, UInt<1>(0h0)
connect stq[7].bits.addr.valid, UInt<1>(0h0)
connect stq[7].bits.data.valid, UInt<1>(0h0)
wire stq_7_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_7_bits_uop_uop.debug_tsrc
invalidate stq_7_bits_uop_uop.debug_fsrc
invalidate stq_7_bits_uop_uop.bp_xcpt_if
invalidate stq_7_bits_uop_uop.bp_debug_if
invalidate stq_7_bits_uop_uop.xcpt_ma_if
invalidate stq_7_bits_uop_uop.xcpt_ae_if
invalidate stq_7_bits_uop_uop.xcpt_pf_if
invalidate stq_7_bits_uop_uop.fp_single
invalidate stq_7_bits_uop_uop.fp_val
invalidate stq_7_bits_uop_uop.frs3_en
invalidate stq_7_bits_uop_uop.lrs2_rtype
invalidate stq_7_bits_uop_uop.lrs1_rtype
invalidate stq_7_bits_uop_uop.dst_rtype
invalidate stq_7_bits_uop_uop.ldst_val
invalidate stq_7_bits_uop_uop.lrs3
invalidate stq_7_bits_uop_uop.lrs2
invalidate stq_7_bits_uop_uop.lrs1
invalidate stq_7_bits_uop_uop.ldst
invalidate stq_7_bits_uop_uop.ldst_is_rs1
invalidate stq_7_bits_uop_uop.flush_on_commit
invalidate stq_7_bits_uop_uop.is_unique
invalidate stq_7_bits_uop_uop.is_sys_pc2epc
invalidate stq_7_bits_uop_uop.uses_stq
invalidate stq_7_bits_uop_uop.uses_ldq
invalidate stq_7_bits_uop_uop.is_amo
invalidate stq_7_bits_uop_uop.is_fencei
invalidate stq_7_bits_uop_uop.is_fence
invalidate stq_7_bits_uop_uop.mem_signed
invalidate stq_7_bits_uop_uop.mem_size
invalidate stq_7_bits_uop_uop.mem_cmd
invalidate stq_7_bits_uop_uop.bypassable
invalidate stq_7_bits_uop_uop.exc_cause
invalidate stq_7_bits_uop_uop.exception
invalidate stq_7_bits_uop_uop.stale_pdst
invalidate stq_7_bits_uop_uop.ppred_busy
invalidate stq_7_bits_uop_uop.prs3_busy
invalidate stq_7_bits_uop_uop.prs2_busy
invalidate stq_7_bits_uop_uop.prs1_busy
invalidate stq_7_bits_uop_uop.ppred
invalidate stq_7_bits_uop_uop.prs3
invalidate stq_7_bits_uop_uop.prs2
invalidate stq_7_bits_uop_uop.prs1
invalidate stq_7_bits_uop_uop.pdst
invalidate stq_7_bits_uop_uop.rxq_idx
invalidate stq_7_bits_uop_uop.stq_idx
invalidate stq_7_bits_uop_uop.ldq_idx
invalidate stq_7_bits_uop_uop.rob_idx
invalidate stq_7_bits_uop_uop.csr_addr
invalidate stq_7_bits_uop_uop.imm_packed
invalidate stq_7_bits_uop_uop.taken
invalidate stq_7_bits_uop_uop.pc_lob
invalidate stq_7_bits_uop_uop.edge_inst
invalidate stq_7_bits_uop_uop.ftq_idx
invalidate stq_7_bits_uop_uop.br_tag
invalidate stq_7_bits_uop_uop.br_mask
invalidate stq_7_bits_uop_uop.is_sfb
invalidate stq_7_bits_uop_uop.is_jal
invalidate stq_7_bits_uop_uop.is_jalr
invalidate stq_7_bits_uop_uop.is_br
invalidate stq_7_bits_uop_uop.iw_p2_poisoned
invalidate stq_7_bits_uop_uop.iw_p1_poisoned
invalidate stq_7_bits_uop_uop.iw_state
invalidate stq_7_bits_uop_uop.ctrl.is_std
invalidate stq_7_bits_uop_uop.ctrl.is_sta
invalidate stq_7_bits_uop_uop.ctrl.is_load
invalidate stq_7_bits_uop_uop.ctrl.csr_cmd
invalidate stq_7_bits_uop_uop.ctrl.fcn_dw
invalidate stq_7_bits_uop_uop.ctrl.op_fcn
invalidate stq_7_bits_uop_uop.ctrl.imm_sel
invalidate stq_7_bits_uop_uop.ctrl.op2_sel
invalidate stq_7_bits_uop_uop.ctrl.op1_sel
invalidate stq_7_bits_uop_uop.ctrl.br_type
invalidate stq_7_bits_uop_uop.fu_code
invalidate stq_7_bits_uop_uop.iq_type
invalidate stq_7_bits_uop_uop.debug_pc
invalidate stq_7_bits_uop_uop.is_rvc
invalidate stq_7_bits_uop_uop.debug_inst
invalidate stq_7_bits_uop_uop.inst
invalidate stq_7_bits_uop_uop.uopc
connect stq_7_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_7_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_7_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_7_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_7_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_7_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_7_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_7_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_7_bits_uop_cs.is_std
invalidate stq_7_bits_uop_cs.is_sta
invalidate stq_7_bits_uop_cs.is_load
invalidate stq_7_bits_uop_cs.csr_cmd
invalidate stq_7_bits_uop_cs.fcn_dw
invalidate stq_7_bits_uop_cs.op_fcn
invalidate stq_7_bits_uop_cs.imm_sel
invalidate stq_7_bits_uop_cs.op2_sel
invalidate stq_7_bits_uop_cs.op1_sel
invalidate stq_7_bits_uop_cs.br_type
connect stq_7_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_7_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_7_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_7_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_7_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_7_bits_uop_uop.ctrl, stq_7_bits_uop_cs
connect stq[7].bits.uop, stq_7_bits_uop_uop
connect stq[8].valid, UInt<1>(0h0)
connect stq[8].bits.addr.valid, UInt<1>(0h0)
connect stq[8].bits.data.valid, UInt<1>(0h0)
wire stq_8_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_8_bits_uop_uop.debug_tsrc
invalidate stq_8_bits_uop_uop.debug_fsrc
invalidate stq_8_bits_uop_uop.bp_xcpt_if
invalidate stq_8_bits_uop_uop.bp_debug_if
invalidate stq_8_bits_uop_uop.xcpt_ma_if
invalidate stq_8_bits_uop_uop.xcpt_ae_if
invalidate stq_8_bits_uop_uop.xcpt_pf_if
invalidate stq_8_bits_uop_uop.fp_single
invalidate stq_8_bits_uop_uop.fp_val
invalidate stq_8_bits_uop_uop.frs3_en
invalidate stq_8_bits_uop_uop.lrs2_rtype
invalidate stq_8_bits_uop_uop.lrs1_rtype
invalidate stq_8_bits_uop_uop.dst_rtype
invalidate stq_8_bits_uop_uop.ldst_val
invalidate stq_8_bits_uop_uop.lrs3
invalidate stq_8_bits_uop_uop.lrs2
invalidate stq_8_bits_uop_uop.lrs1
invalidate stq_8_bits_uop_uop.ldst
invalidate stq_8_bits_uop_uop.ldst_is_rs1
invalidate stq_8_bits_uop_uop.flush_on_commit
invalidate stq_8_bits_uop_uop.is_unique
invalidate stq_8_bits_uop_uop.is_sys_pc2epc
invalidate stq_8_bits_uop_uop.uses_stq
invalidate stq_8_bits_uop_uop.uses_ldq
invalidate stq_8_bits_uop_uop.is_amo
invalidate stq_8_bits_uop_uop.is_fencei
invalidate stq_8_bits_uop_uop.is_fence
invalidate stq_8_bits_uop_uop.mem_signed
invalidate stq_8_bits_uop_uop.mem_size
invalidate stq_8_bits_uop_uop.mem_cmd
invalidate stq_8_bits_uop_uop.bypassable
invalidate stq_8_bits_uop_uop.exc_cause
invalidate stq_8_bits_uop_uop.exception
invalidate stq_8_bits_uop_uop.stale_pdst
invalidate stq_8_bits_uop_uop.ppred_busy
invalidate stq_8_bits_uop_uop.prs3_busy
invalidate stq_8_bits_uop_uop.prs2_busy
invalidate stq_8_bits_uop_uop.prs1_busy
invalidate stq_8_bits_uop_uop.ppred
invalidate stq_8_bits_uop_uop.prs3
invalidate stq_8_bits_uop_uop.prs2
invalidate stq_8_bits_uop_uop.prs1
invalidate stq_8_bits_uop_uop.pdst
invalidate stq_8_bits_uop_uop.rxq_idx
invalidate stq_8_bits_uop_uop.stq_idx
invalidate stq_8_bits_uop_uop.ldq_idx
invalidate stq_8_bits_uop_uop.rob_idx
invalidate stq_8_bits_uop_uop.csr_addr
invalidate stq_8_bits_uop_uop.imm_packed
invalidate stq_8_bits_uop_uop.taken
invalidate stq_8_bits_uop_uop.pc_lob
invalidate stq_8_bits_uop_uop.edge_inst
invalidate stq_8_bits_uop_uop.ftq_idx
invalidate stq_8_bits_uop_uop.br_tag
invalidate stq_8_bits_uop_uop.br_mask
invalidate stq_8_bits_uop_uop.is_sfb
invalidate stq_8_bits_uop_uop.is_jal
invalidate stq_8_bits_uop_uop.is_jalr
invalidate stq_8_bits_uop_uop.is_br
invalidate stq_8_bits_uop_uop.iw_p2_poisoned
invalidate stq_8_bits_uop_uop.iw_p1_poisoned
invalidate stq_8_bits_uop_uop.iw_state
invalidate stq_8_bits_uop_uop.ctrl.is_std
invalidate stq_8_bits_uop_uop.ctrl.is_sta
invalidate stq_8_bits_uop_uop.ctrl.is_load
invalidate stq_8_bits_uop_uop.ctrl.csr_cmd
invalidate stq_8_bits_uop_uop.ctrl.fcn_dw
invalidate stq_8_bits_uop_uop.ctrl.op_fcn
invalidate stq_8_bits_uop_uop.ctrl.imm_sel
invalidate stq_8_bits_uop_uop.ctrl.op2_sel
invalidate stq_8_bits_uop_uop.ctrl.op1_sel
invalidate stq_8_bits_uop_uop.ctrl.br_type
invalidate stq_8_bits_uop_uop.fu_code
invalidate stq_8_bits_uop_uop.iq_type
invalidate stq_8_bits_uop_uop.debug_pc
invalidate stq_8_bits_uop_uop.is_rvc
invalidate stq_8_bits_uop_uop.debug_inst
invalidate stq_8_bits_uop_uop.inst
invalidate stq_8_bits_uop_uop.uopc
connect stq_8_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_8_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_8_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_8_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_8_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_8_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_8_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_8_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_8_bits_uop_cs.is_std
invalidate stq_8_bits_uop_cs.is_sta
invalidate stq_8_bits_uop_cs.is_load
invalidate stq_8_bits_uop_cs.csr_cmd
invalidate stq_8_bits_uop_cs.fcn_dw
invalidate stq_8_bits_uop_cs.op_fcn
invalidate stq_8_bits_uop_cs.imm_sel
invalidate stq_8_bits_uop_cs.op2_sel
invalidate stq_8_bits_uop_cs.op1_sel
invalidate stq_8_bits_uop_cs.br_type
connect stq_8_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_8_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_8_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_8_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_8_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_8_bits_uop_uop.ctrl, stq_8_bits_uop_cs
connect stq[8].bits.uop, stq_8_bits_uop_uop
connect stq[9].valid, UInt<1>(0h0)
connect stq[9].bits.addr.valid, UInt<1>(0h0)
connect stq[9].bits.data.valid, UInt<1>(0h0)
wire stq_9_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_9_bits_uop_uop.debug_tsrc
invalidate stq_9_bits_uop_uop.debug_fsrc
invalidate stq_9_bits_uop_uop.bp_xcpt_if
invalidate stq_9_bits_uop_uop.bp_debug_if
invalidate stq_9_bits_uop_uop.xcpt_ma_if
invalidate stq_9_bits_uop_uop.xcpt_ae_if
invalidate stq_9_bits_uop_uop.xcpt_pf_if
invalidate stq_9_bits_uop_uop.fp_single
invalidate stq_9_bits_uop_uop.fp_val
invalidate stq_9_bits_uop_uop.frs3_en
invalidate stq_9_bits_uop_uop.lrs2_rtype
invalidate stq_9_bits_uop_uop.lrs1_rtype
invalidate stq_9_bits_uop_uop.dst_rtype
invalidate stq_9_bits_uop_uop.ldst_val
invalidate stq_9_bits_uop_uop.lrs3
invalidate stq_9_bits_uop_uop.lrs2
invalidate stq_9_bits_uop_uop.lrs1
invalidate stq_9_bits_uop_uop.ldst
invalidate stq_9_bits_uop_uop.ldst_is_rs1
invalidate stq_9_bits_uop_uop.flush_on_commit
invalidate stq_9_bits_uop_uop.is_unique
invalidate stq_9_bits_uop_uop.is_sys_pc2epc
invalidate stq_9_bits_uop_uop.uses_stq
invalidate stq_9_bits_uop_uop.uses_ldq
invalidate stq_9_bits_uop_uop.is_amo
invalidate stq_9_bits_uop_uop.is_fencei
invalidate stq_9_bits_uop_uop.is_fence
invalidate stq_9_bits_uop_uop.mem_signed
invalidate stq_9_bits_uop_uop.mem_size
invalidate stq_9_bits_uop_uop.mem_cmd
invalidate stq_9_bits_uop_uop.bypassable
invalidate stq_9_bits_uop_uop.exc_cause
invalidate stq_9_bits_uop_uop.exception
invalidate stq_9_bits_uop_uop.stale_pdst
invalidate stq_9_bits_uop_uop.ppred_busy
invalidate stq_9_bits_uop_uop.prs3_busy
invalidate stq_9_bits_uop_uop.prs2_busy
invalidate stq_9_bits_uop_uop.prs1_busy
invalidate stq_9_bits_uop_uop.ppred
invalidate stq_9_bits_uop_uop.prs3
invalidate stq_9_bits_uop_uop.prs2
invalidate stq_9_bits_uop_uop.prs1
invalidate stq_9_bits_uop_uop.pdst
invalidate stq_9_bits_uop_uop.rxq_idx
invalidate stq_9_bits_uop_uop.stq_idx
invalidate stq_9_bits_uop_uop.ldq_idx
invalidate stq_9_bits_uop_uop.rob_idx
invalidate stq_9_bits_uop_uop.csr_addr
invalidate stq_9_bits_uop_uop.imm_packed
invalidate stq_9_bits_uop_uop.taken
invalidate stq_9_bits_uop_uop.pc_lob
invalidate stq_9_bits_uop_uop.edge_inst
invalidate stq_9_bits_uop_uop.ftq_idx
invalidate stq_9_bits_uop_uop.br_tag
invalidate stq_9_bits_uop_uop.br_mask
invalidate stq_9_bits_uop_uop.is_sfb
invalidate stq_9_bits_uop_uop.is_jal
invalidate stq_9_bits_uop_uop.is_jalr
invalidate stq_9_bits_uop_uop.is_br
invalidate stq_9_bits_uop_uop.iw_p2_poisoned
invalidate stq_9_bits_uop_uop.iw_p1_poisoned
invalidate stq_9_bits_uop_uop.iw_state
invalidate stq_9_bits_uop_uop.ctrl.is_std
invalidate stq_9_bits_uop_uop.ctrl.is_sta
invalidate stq_9_bits_uop_uop.ctrl.is_load
invalidate stq_9_bits_uop_uop.ctrl.csr_cmd
invalidate stq_9_bits_uop_uop.ctrl.fcn_dw
invalidate stq_9_bits_uop_uop.ctrl.op_fcn
invalidate stq_9_bits_uop_uop.ctrl.imm_sel
invalidate stq_9_bits_uop_uop.ctrl.op2_sel
invalidate stq_9_bits_uop_uop.ctrl.op1_sel
invalidate stq_9_bits_uop_uop.ctrl.br_type
invalidate stq_9_bits_uop_uop.fu_code
invalidate stq_9_bits_uop_uop.iq_type
invalidate stq_9_bits_uop_uop.debug_pc
invalidate stq_9_bits_uop_uop.is_rvc
invalidate stq_9_bits_uop_uop.debug_inst
invalidate stq_9_bits_uop_uop.inst
invalidate stq_9_bits_uop_uop.uopc
connect stq_9_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_9_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_9_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_9_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_9_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_9_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_9_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_9_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_9_bits_uop_cs.is_std
invalidate stq_9_bits_uop_cs.is_sta
invalidate stq_9_bits_uop_cs.is_load
invalidate stq_9_bits_uop_cs.csr_cmd
invalidate stq_9_bits_uop_cs.fcn_dw
invalidate stq_9_bits_uop_cs.op_fcn
invalidate stq_9_bits_uop_cs.imm_sel
invalidate stq_9_bits_uop_cs.op2_sel
invalidate stq_9_bits_uop_cs.op1_sel
invalidate stq_9_bits_uop_cs.br_type
connect stq_9_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_9_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_9_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_9_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_9_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_9_bits_uop_uop.ctrl, stq_9_bits_uop_cs
connect stq[9].bits.uop, stq_9_bits_uop_uop
connect stq[10].valid, UInt<1>(0h0)
connect stq[10].bits.addr.valid, UInt<1>(0h0)
connect stq[10].bits.data.valid, UInt<1>(0h0)
wire stq_10_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_10_bits_uop_uop.debug_tsrc
invalidate stq_10_bits_uop_uop.debug_fsrc
invalidate stq_10_bits_uop_uop.bp_xcpt_if
invalidate stq_10_bits_uop_uop.bp_debug_if
invalidate stq_10_bits_uop_uop.xcpt_ma_if
invalidate stq_10_bits_uop_uop.xcpt_ae_if
invalidate stq_10_bits_uop_uop.xcpt_pf_if
invalidate stq_10_bits_uop_uop.fp_single
invalidate stq_10_bits_uop_uop.fp_val
invalidate stq_10_bits_uop_uop.frs3_en
invalidate stq_10_bits_uop_uop.lrs2_rtype
invalidate stq_10_bits_uop_uop.lrs1_rtype
invalidate stq_10_bits_uop_uop.dst_rtype
invalidate stq_10_bits_uop_uop.ldst_val
invalidate stq_10_bits_uop_uop.lrs3
invalidate stq_10_bits_uop_uop.lrs2
invalidate stq_10_bits_uop_uop.lrs1
invalidate stq_10_bits_uop_uop.ldst
invalidate stq_10_bits_uop_uop.ldst_is_rs1
invalidate stq_10_bits_uop_uop.flush_on_commit
invalidate stq_10_bits_uop_uop.is_unique
invalidate stq_10_bits_uop_uop.is_sys_pc2epc
invalidate stq_10_bits_uop_uop.uses_stq
invalidate stq_10_bits_uop_uop.uses_ldq
invalidate stq_10_bits_uop_uop.is_amo
invalidate stq_10_bits_uop_uop.is_fencei
invalidate stq_10_bits_uop_uop.is_fence
invalidate stq_10_bits_uop_uop.mem_signed
invalidate stq_10_bits_uop_uop.mem_size
invalidate stq_10_bits_uop_uop.mem_cmd
invalidate stq_10_bits_uop_uop.bypassable
invalidate stq_10_bits_uop_uop.exc_cause
invalidate stq_10_bits_uop_uop.exception
invalidate stq_10_bits_uop_uop.stale_pdst
invalidate stq_10_bits_uop_uop.ppred_busy
invalidate stq_10_bits_uop_uop.prs3_busy
invalidate stq_10_bits_uop_uop.prs2_busy
invalidate stq_10_bits_uop_uop.prs1_busy
invalidate stq_10_bits_uop_uop.ppred
invalidate stq_10_bits_uop_uop.prs3
invalidate stq_10_bits_uop_uop.prs2
invalidate stq_10_bits_uop_uop.prs1
invalidate stq_10_bits_uop_uop.pdst
invalidate stq_10_bits_uop_uop.rxq_idx
invalidate stq_10_bits_uop_uop.stq_idx
invalidate stq_10_bits_uop_uop.ldq_idx
invalidate stq_10_bits_uop_uop.rob_idx
invalidate stq_10_bits_uop_uop.csr_addr
invalidate stq_10_bits_uop_uop.imm_packed
invalidate stq_10_bits_uop_uop.taken
invalidate stq_10_bits_uop_uop.pc_lob
invalidate stq_10_bits_uop_uop.edge_inst
invalidate stq_10_bits_uop_uop.ftq_idx
invalidate stq_10_bits_uop_uop.br_tag
invalidate stq_10_bits_uop_uop.br_mask
invalidate stq_10_bits_uop_uop.is_sfb
invalidate stq_10_bits_uop_uop.is_jal
invalidate stq_10_bits_uop_uop.is_jalr
invalidate stq_10_bits_uop_uop.is_br
invalidate stq_10_bits_uop_uop.iw_p2_poisoned
invalidate stq_10_bits_uop_uop.iw_p1_poisoned
invalidate stq_10_bits_uop_uop.iw_state
invalidate stq_10_bits_uop_uop.ctrl.is_std
invalidate stq_10_bits_uop_uop.ctrl.is_sta
invalidate stq_10_bits_uop_uop.ctrl.is_load
invalidate stq_10_bits_uop_uop.ctrl.csr_cmd
invalidate stq_10_bits_uop_uop.ctrl.fcn_dw
invalidate stq_10_bits_uop_uop.ctrl.op_fcn
invalidate stq_10_bits_uop_uop.ctrl.imm_sel
invalidate stq_10_bits_uop_uop.ctrl.op2_sel
invalidate stq_10_bits_uop_uop.ctrl.op1_sel
invalidate stq_10_bits_uop_uop.ctrl.br_type
invalidate stq_10_bits_uop_uop.fu_code
invalidate stq_10_bits_uop_uop.iq_type
invalidate stq_10_bits_uop_uop.debug_pc
invalidate stq_10_bits_uop_uop.is_rvc
invalidate stq_10_bits_uop_uop.debug_inst
invalidate stq_10_bits_uop_uop.inst
invalidate stq_10_bits_uop_uop.uopc
connect stq_10_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_10_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_10_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_10_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_10_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_10_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_10_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_10_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_10_bits_uop_cs.is_std
invalidate stq_10_bits_uop_cs.is_sta
invalidate stq_10_bits_uop_cs.is_load
invalidate stq_10_bits_uop_cs.csr_cmd
invalidate stq_10_bits_uop_cs.fcn_dw
invalidate stq_10_bits_uop_cs.op_fcn
invalidate stq_10_bits_uop_cs.imm_sel
invalidate stq_10_bits_uop_cs.op2_sel
invalidate stq_10_bits_uop_cs.op1_sel
invalidate stq_10_bits_uop_cs.br_type
connect stq_10_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_10_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_10_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_10_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_10_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_10_bits_uop_uop.ctrl, stq_10_bits_uop_cs
connect stq[10].bits.uop, stq_10_bits_uop_uop
connect stq[11].valid, UInt<1>(0h0)
connect stq[11].bits.addr.valid, UInt<1>(0h0)
connect stq[11].bits.data.valid, UInt<1>(0h0)
wire stq_11_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_11_bits_uop_uop.debug_tsrc
invalidate stq_11_bits_uop_uop.debug_fsrc
invalidate stq_11_bits_uop_uop.bp_xcpt_if
invalidate stq_11_bits_uop_uop.bp_debug_if
invalidate stq_11_bits_uop_uop.xcpt_ma_if
invalidate stq_11_bits_uop_uop.xcpt_ae_if
invalidate stq_11_bits_uop_uop.xcpt_pf_if
invalidate stq_11_bits_uop_uop.fp_single
invalidate stq_11_bits_uop_uop.fp_val
invalidate stq_11_bits_uop_uop.frs3_en
invalidate stq_11_bits_uop_uop.lrs2_rtype
invalidate stq_11_bits_uop_uop.lrs1_rtype
invalidate stq_11_bits_uop_uop.dst_rtype
invalidate stq_11_bits_uop_uop.ldst_val
invalidate stq_11_bits_uop_uop.lrs3
invalidate stq_11_bits_uop_uop.lrs2
invalidate stq_11_bits_uop_uop.lrs1
invalidate stq_11_bits_uop_uop.ldst
invalidate stq_11_bits_uop_uop.ldst_is_rs1
invalidate stq_11_bits_uop_uop.flush_on_commit
invalidate stq_11_bits_uop_uop.is_unique
invalidate stq_11_bits_uop_uop.is_sys_pc2epc
invalidate stq_11_bits_uop_uop.uses_stq
invalidate stq_11_bits_uop_uop.uses_ldq
invalidate stq_11_bits_uop_uop.is_amo
invalidate stq_11_bits_uop_uop.is_fencei
invalidate stq_11_bits_uop_uop.is_fence
invalidate stq_11_bits_uop_uop.mem_signed
invalidate stq_11_bits_uop_uop.mem_size
invalidate stq_11_bits_uop_uop.mem_cmd
invalidate stq_11_bits_uop_uop.bypassable
invalidate stq_11_bits_uop_uop.exc_cause
invalidate stq_11_bits_uop_uop.exception
invalidate stq_11_bits_uop_uop.stale_pdst
invalidate stq_11_bits_uop_uop.ppred_busy
invalidate stq_11_bits_uop_uop.prs3_busy
invalidate stq_11_bits_uop_uop.prs2_busy
invalidate stq_11_bits_uop_uop.prs1_busy
invalidate stq_11_bits_uop_uop.ppred
invalidate stq_11_bits_uop_uop.prs3
invalidate stq_11_bits_uop_uop.prs2
invalidate stq_11_bits_uop_uop.prs1
invalidate stq_11_bits_uop_uop.pdst
invalidate stq_11_bits_uop_uop.rxq_idx
invalidate stq_11_bits_uop_uop.stq_idx
invalidate stq_11_bits_uop_uop.ldq_idx
invalidate stq_11_bits_uop_uop.rob_idx
invalidate stq_11_bits_uop_uop.csr_addr
invalidate stq_11_bits_uop_uop.imm_packed
invalidate stq_11_bits_uop_uop.taken
invalidate stq_11_bits_uop_uop.pc_lob
invalidate stq_11_bits_uop_uop.edge_inst
invalidate stq_11_bits_uop_uop.ftq_idx
invalidate stq_11_bits_uop_uop.br_tag
invalidate stq_11_bits_uop_uop.br_mask
invalidate stq_11_bits_uop_uop.is_sfb
invalidate stq_11_bits_uop_uop.is_jal
invalidate stq_11_bits_uop_uop.is_jalr
invalidate stq_11_bits_uop_uop.is_br
invalidate stq_11_bits_uop_uop.iw_p2_poisoned
invalidate stq_11_bits_uop_uop.iw_p1_poisoned
invalidate stq_11_bits_uop_uop.iw_state
invalidate stq_11_bits_uop_uop.ctrl.is_std
invalidate stq_11_bits_uop_uop.ctrl.is_sta
invalidate stq_11_bits_uop_uop.ctrl.is_load
invalidate stq_11_bits_uop_uop.ctrl.csr_cmd
invalidate stq_11_bits_uop_uop.ctrl.fcn_dw
invalidate stq_11_bits_uop_uop.ctrl.op_fcn
invalidate stq_11_bits_uop_uop.ctrl.imm_sel
invalidate stq_11_bits_uop_uop.ctrl.op2_sel
invalidate stq_11_bits_uop_uop.ctrl.op1_sel
invalidate stq_11_bits_uop_uop.ctrl.br_type
invalidate stq_11_bits_uop_uop.fu_code
invalidate stq_11_bits_uop_uop.iq_type
invalidate stq_11_bits_uop_uop.debug_pc
invalidate stq_11_bits_uop_uop.is_rvc
invalidate stq_11_bits_uop_uop.debug_inst
invalidate stq_11_bits_uop_uop.inst
invalidate stq_11_bits_uop_uop.uopc
connect stq_11_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_11_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_11_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_11_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_11_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_11_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_11_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_11_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_11_bits_uop_cs.is_std
invalidate stq_11_bits_uop_cs.is_sta
invalidate stq_11_bits_uop_cs.is_load
invalidate stq_11_bits_uop_cs.csr_cmd
invalidate stq_11_bits_uop_cs.fcn_dw
invalidate stq_11_bits_uop_cs.op_fcn
invalidate stq_11_bits_uop_cs.imm_sel
invalidate stq_11_bits_uop_cs.op2_sel
invalidate stq_11_bits_uop_cs.op1_sel
invalidate stq_11_bits_uop_cs.br_type
connect stq_11_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_11_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_11_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_11_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_11_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_11_bits_uop_uop.ctrl, stq_11_bits_uop_cs
connect stq[11].bits.uop, stq_11_bits_uop_uop
connect stq[12].valid, UInt<1>(0h0)
connect stq[12].bits.addr.valid, UInt<1>(0h0)
connect stq[12].bits.data.valid, UInt<1>(0h0)
wire stq_12_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_12_bits_uop_uop.debug_tsrc
invalidate stq_12_bits_uop_uop.debug_fsrc
invalidate stq_12_bits_uop_uop.bp_xcpt_if
invalidate stq_12_bits_uop_uop.bp_debug_if
invalidate stq_12_bits_uop_uop.xcpt_ma_if
invalidate stq_12_bits_uop_uop.xcpt_ae_if
invalidate stq_12_bits_uop_uop.xcpt_pf_if
invalidate stq_12_bits_uop_uop.fp_single
invalidate stq_12_bits_uop_uop.fp_val
invalidate stq_12_bits_uop_uop.frs3_en
invalidate stq_12_bits_uop_uop.lrs2_rtype
invalidate stq_12_bits_uop_uop.lrs1_rtype
invalidate stq_12_bits_uop_uop.dst_rtype
invalidate stq_12_bits_uop_uop.ldst_val
invalidate stq_12_bits_uop_uop.lrs3
invalidate stq_12_bits_uop_uop.lrs2
invalidate stq_12_bits_uop_uop.lrs1
invalidate stq_12_bits_uop_uop.ldst
invalidate stq_12_bits_uop_uop.ldst_is_rs1
invalidate stq_12_bits_uop_uop.flush_on_commit
invalidate stq_12_bits_uop_uop.is_unique
invalidate stq_12_bits_uop_uop.is_sys_pc2epc
invalidate stq_12_bits_uop_uop.uses_stq
invalidate stq_12_bits_uop_uop.uses_ldq
invalidate stq_12_bits_uop_uop.is_amo
invalidate stq_12_bits_uop_uop.is_fencei
invalidate stq_12_bits_uop_uop.is_fence
invalidate stq_12_bits_uop_uop.mem_signed
invalidate stq_12_bits_uop_uop.mem_size
invalidate stq_12_bits_uop_uop.mem_cmd
invalidate stq_12_bits_uop_uop.bypassable
invalidate stq_12_bits_uop_uop.exc_cause
invalidate stq_12_bits_uop_uop.exception
invalidate stq_12_bits_uop_uop.stale_pdst
invalidate stq_12_bits_uop_uop.ppred_busy
invalidate stq_12_bits_uop_uop.prs3_busy
invalidate stq_12_bits_uop_uop.prs2_busy
invalidate stq_12_bits_uop_uop.prs1_busy
invalidate stq_12_bits_uop_uop.ppred
invalidate stq_12_bits_uop_uop.prs3
invalidate stq_12_bits_uop_uop.prs2
invalidate stq_12_bits_uop_uop.prs1
invalidate stq_12_bits_uop_uop.pdst
invalidate stq_12_bits_uop_uop.rxq_idx
invalidate stq_12_bits_uop_uop.stq_idx
invalidate stq_12_bits_uop_uop.ldq_idx
invalidate stq_12_bits_uop_uop.rob_idx
invalidate stq_12_bits_uop_uop.csr_addr
invalidate stq_12_bits_uop_uop.imm_packed
invalidate stq_12_bits_uop_uop.taken
invalidate stq_12_bits_uop_uop.pc_lob
invalidate stq_12_bits_uop_uop.edge_inst
invalidate stq_12_bits_uop_uop.ftq_idx
invalidate stq_12_bits_uop_uop.br_tag
invalidate stq_12_bits_uop_uop.br_mask
invalidate stq_12_bits_uop_uop.is_sfb
invalidate stq_12_bits_uop_uop.is_jal
invalidate stq_12_bits_uop_uop.is_jalr
invalidate stq_12_bits_uop_uop.is_br
invalidate stq_12_bits_uop_uop.iw_p2_poisoned
invalidate stq_12_bits_uop_uop.iw_p1_poisoned
invalidate stq_12_bits_uop_uop.iw_state
invalidate stq_12_bits_uop_uop.ctrl.is_std
invalidate stq_12_bits_uop_uop.ctrl.is_sta
invalidate stq_12_bits_uop_uop.ctrl.is_load
invalidate stq_12_bits_uop_uop.ctrl.csr_cmd
invalidate stq_12_bits_uop_uop.ctrl.fcn_dw
invalidate stq_12_bits_uop_uop.ctrl.op_fcn
invalidate stq_12_bits_uop_uop.ctrl.imm_sel
invalidate stq_12_bits_uop_uop.ctrl.op2_sel
invalidate stq_12_bits_uop_uop.ctrl.op1_sel
invalidate stq_12_bits_uop_uop.ctrl.br_type
invalidate stq_12_bits_uop_uop.fu_code
invalidate stq_12_bits_uop_uop.iq_type
invalidate stq_12_bits_uop_uop.debug_pc
invalidate stq_12_bits_uop_uop.is_rvc
invalidate stq_12_bits_uop_uop.debug_inst
invalidate stq_12_bits_uop_uop.inst
invalidate stq_12_bits_uop_uop.uopc
connect stq_12_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_12_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_12_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_12_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_12_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_12_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_12_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_12_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_12_bits_uop_cs.is_std
invalidate stq_12_bits_uop_cs.is_sta
invalidate stq_12_bits_uop_cs.is_load
invalidate stq_12_bits_uop_cs.csr_cmd
invalidate stq_12_bits_uop_cs.fcn_dw
invalidate stq_12_bits_uop_cs.op_fcn
invalidate stq_12_bits_uop_cs.imm_sel
invalidate stq_12_bits_uop_cs.op2_sel
invalidate stq_12_bits_uop_cs.op1_sel
invalidate stq_12_bits_uop_cs.br_type
connect stq_12_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_12_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_12_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_12_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_12_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_12_bits_uop_uop.ctrl, stq_12_bits_uop_cs
connect stq[12].bits.uop, stq_12_bits_uop_uop
connect stq[13].valid, UInt<1>(0h0)
connect stq[13].bits.addr.valid, UInt<1>(0h0)
connect stq[13].bits.data.valid, UInt<1>(0h0)
wire stq_13_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_13_bits_uop_uop.debug_tsrc
invalidate stq_13_bits_uop_uop.debug_fsrc
invalidate stq_13_bits_uop_uop.bp_xcpt_if
invalidate stq_13_bits_uop_uop.bp_debug_if
invalidate stq_13_bits_uop_uop.xcpt_ma_if
invalidate stq_13_bits_uop_uop.xcpt_ae_if
invalidate stq_13_bits_uop_uop.xcpt_pf_if
invalidate stq_13_bits_uop_uop.fp_single
invalidate stq_13_bits_uop_uop.fp_val
invalidate stq_13_bits_uop_uop.frs3_en
invalidate stq_13_bits_uop_uop.lrs2_rtype
invalidate stq_13_bits_uop_uop.lrs1_rtype
invalidate stq_13_bits_uop_uop.dst_rtype
invalidate stq_13_bits_uop_uop.ldst_val
invalidate stq_13_bits_uop_uop.lrs3
invalidate stq_13_bits_uop_uop.lrs2
invalidate stq_13_bits_uop_uop.lrs1
invalidate stq_13_bits_uop_uop.ldst
invalidate stq_13_bits_uop_uop.ldst_is_rs1
invalidate stq_13_bits_uop_uop.flush_on_commit
invalidate stq_13_bits_uop_uop.is_unique
invalidate stq_13_bits_uop_uop.is_sys_pc2epc
invalidate stq_13_bits_uop_uop.uses_stq
invalidate stq_13_bits_uop_uop.uses_ldq
invalidate stq_13_bits_uop_uop.is_amo
invalidate stq_13_bits_uop_uop.is_fencei
invalidate stq_13_bits_uop_uop.is_fence
invalidate stq_13_bits_uop_uop.mem_signed
invalidate stq_13_bits_uop_uop.mem_size
invalidate stq_13_bits_uop_uop.mem_cmd
invalidate stq_13_bits_uop_uop.bypassable
invalidate stq_13_bits_uop_uop.exc_cause
invalidate stq_13_bits_uop_uop.exception
invalidate stq_13_bits_uop_uop.stale_pdst
invalidate stq_13_bits_uop_uop.ppred_busy
invalidate stq_13_bits_uop_uop.prs3_busy
invalidate stq_13_bits_uop_uop.prs2_busy
invalidate stq_13_bits_uop_uop.prs1_busy
invalidate stq_13_bits_uop_uop.ppred
invalidate stq_13_bits_uop_uop.prs3
invalidate stq_13_bits_uop_uop.prs2
invalidate stq_13_bits_uop_uop.prs1
invalidate stq_13_bits_uop_uop.pdst
invalidate stq_13_bits_uop_uop.rxq_idx
invalidate stq_13_bits_uop_uop.stq_idx
invalidate stq_13_bits_uop_uop.ldq_idx
invalidate stq_13_bits_uop_uop.rob_idx
invalidate stq_13_bits_uop_uop.csr_addr
invalidate stq_13_bits_uop_uop.imm_packed
invalidate stq_13_bits_uop_uop.taken
invalidate stq_13_bits_uop_uop.pc_lob
invalidate stq_13_bits_uop_uop.edge_inst
invalidate stq_13_bits_uop_uop.ftq_idx
invalidate stq_13_bits_uop_uop.br_tag
invalidate stq_13_bits_uop_uop.br_mask
invalidate stq_13_bits_uop_uop.is_sfb
invalidate stq_13_bits_uop_uop.is_jal
invalidate stq_13_bits_uop_uop.is_jalr
invalidate stq_13_bits_uop_uop.is_br
invalidate stq_13_bits_uop_uop.iw_p2_poisoned
invalidate stq_13_bits_uop_uop.iw_p1_poisoned
invalidate stq_13_bits_uop_uop.iw_state
invalidate stq_13_bits_uop_uop.ctrl.is_std
invalidate stq_13_bits_uop_uop.ctrl.is_sta
invalidate stq_13_bits_uop_uop.ctrl.is_load
invalidate stq_13_bits_uop_uop.ctrl.csr_cmd
invalidate stq_13_bits_uop_uop.ctrl.fcn_dw
invalidate stq_13_bits_uop_uop.ctrl.op_fcn
invalidate stq_13_bits_uop_uop.ctrl.imm_sel
invalidate stq_13_bits_uop_uop.ctrl.op2_sel
invalidate stq_13_bits_uop_uop.ctrl.op1_sel
invalidate stq_13_bits_uop_uop.ctrl.br_type
invalidate stq_13_bits_uop_uop.fu_code
invalidate stq_13_bits_uop_uop.iq_type
invalidate stq_13_bits_uop_uop.debug_pc
invalidate stq_13_bits_uop_uop.is_rvc
invalidate stq_13_bits_uop_uop.debug_inst
invalidate stq_13_bits_uop_uop.inst
invalidate stq_13_bits_uop_uop.uopc
connect stq_13_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_13_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_13_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_13_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_13_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_13_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_13_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_13_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_13_bits_uop_cs.is_std
invalidate stq_13_bits_uop_cs.is_sta
invalidate stq_13_bits_uop_cs.is_load
invalidate stq_13_bits_uop_cs.csr_cmd
invalidate stq_13_bits_uop_cs.fcn_dw
invalidate stq_13_bits_uop_cs.op_fcn
invalidate stq_13_bits_uop_cs.imm_sel
invalidate stq_13_bits_uop_cs.op2_sel
invalidate stq_13_bits_uop_cs.op1_sel
invalidate stq_13_bits_uop_cs.br_type
connect stq_13_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_13_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_13_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_13_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_13_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_13_bits_uop_uop.ctrl, stq_13_bits_uop_cs
connect stq[13].bits.uop, stq_13_bits_uop_uop
connect stq[14].valid, UInt<1>(0h0)
connect stq[14].bits.addr.valid, UInt<1>(0h0)
connect stq[14].bits.data.valid, UInt<1>(0h0)
wire stq_14_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_14_bits_uop_uop.debug_tsrc
invalidate stq_14_bits_uop_uop.debug_fsrc
invalidate stq_14_bits_uop_uop.bp_xcpt_if
invalidate stq_14_bits_uop_uop.bp_debug_if
invalidate stq_14_bits_uop_uop.xcpt_ma_if
invalidate stq_14_bits_uop_uop.xcpt_ae_if
invalidate stq_14_bits_uop_uop.xcpt_pf_if
invalidate stq_14_bits_uop_uop.fp_single
invalidate stq_14_bits_uop_uop.fp_val
invalidate stq_14_bits_uop_uop.frs3_en
invalidate stq_14_bits_uop_uop.lrs2_rtype
invalidate stq_14_bits_uop_uop.lrs1_rtype
invalidate stq_14_bits_uop_uop.dst_rtype
invalidate stq_14_bits_uop_uop.ldst_val
invalidate stq_14_bits_uop_uop.lrs3
invalidate stq_14_bits_uop_uop.lrs2
invalidate stq_14_bits_uop_uop.lrs1
invalidate stq_14_bits_uop_uop.ldst
invalidate stq_14_bits_uop_uop.ldst_is_rs1
invalidate stq_14_bits_uop_uop.flush_on_commit
invalidate stq_14_bits_uop_uop.is_unique
invalidate stq_14_bits_uop_uop.is_sys_pc2epc
invalidate stq_14_bits_uop_uop.uses_stq
invalidate stq_14_bits_uop_uop.uses_ldq
invalidate stq_14_bits_uop_uop.is_amo
invalidate stq_14_bits_uop_uop.is_fencei
invalidate stq_14_bits_uop_uop.is_fence
invalidate stq_14_bits_uop_uop.mem_signed
invalidate stq_14_bits_uop_uop.mem_size
invalidate stq_14_bits_uop_uop.mem_cmd
invalidate stq_14_bits_uop_uop.bypassable
invalidate stq_14_bits_uop_uop.exc_cause
invalidate stq_14_bits_uop_uop.exception
invalidate stq_14_bits_uop_uop.stale_pdst
invalidate stq_14_bits_uop_uop.ppred_busy
invalidate stq_14_bits_uop_uop.prs3_busy
invalidate stq_14_bits_uop_uop.prs2_busy
invalidate stq_14_bits_uop_uop.prs1_busy
invalidate stq_14_bits_uop_uop.ppred
invalidate stq_14_bits_uop_uop.prs3
invalidate stq_14_bits_uop_uop.prs2
invalidate stq_14_bits_uop_uop.prs1
invalidate stq_14_bits_uop_uop.pdst
invalidate stq_14_bits_uop_uop.rxq_idx
invalidate stq_14_bits_uop_uop.stq_idx
invalidate stq_14_bits_uop_uop.ldq_idx
invalidate stq_14_bits_uop_uop.rob_idx
invalidate stq_14_bits_uop_uop.csr_addr
invalidate stq_14_bits_uop_uop.imm_packed
invalidate stq_14_bits_uop_uop.taken
invalidate stq_14_bits_uop_uop.pc_lob
invalidate stq_14_bits_uop_uop.edge_inst
invalidate stq_14_bits_uop_uop.ftq_idx
invalidate stq_14_bits_uop_uop.br_tag
invalidate stq_14_bits_uop_uop.br_mask
invalidate stq_14_bits_uop_uop.is_sfb
invalidate stq_14_bits_uop_uop.is_jal
invalidate stq_14_bits_uop_uop.is_jalr
invalidate stq_14_bits_uop_uop.is_br
invalidate stq_14_bits_uop_uop.iw_p2_poisoned
invalidate stq_14_bits_uop_uop.iw_p1_poisoned
invalidate stq_14_bits_uop_uop.iw_state
invalidate stq_14_bits_uop_uop.ctrl.is_std
invalidate stq_14_bits_uop_uop.ctrl.is_sta
invalidate stq_14_bits_uop_uop.ctrl.is_load
invalidate stq_14_bits_uop_uop.ctrl.csr_cmd
invalidate stq_14_bits_uop_uop.ctrl.fcn_dw
invalidate stq_14_bits_uop_uop.ctrl.op_fcn
invalidate stq_14_bits_uop_uop.ctrl.imm_sel
invalidate stq_14_bits_uop_uop.ctrl.op2_sel
invalidate stq_14_bits_uop_uop.ctrl.op1_sel
invalidate stq_14_bits_uop_uop.ctrl.br_type
invalidate stq_14_bits_uop_uop.fu_code
invalidate stq_14_bits_uop_uop.iq_type
invalidate stq_14_bits_uop_uop.debug_pc
invalidate stq_14_bits_uop_uop.is_rvc
invalidate stq_14_bits_uop_uop.debug_inst
invalidate stq_14_bits_uop_uop.inst
invalidate stq_14_bits_uop_uop.uopc
connect stq_14_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_14_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_14_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_14_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_14_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_14_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_14_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_14_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_14_bits_uop_cs.is_std
invalidate stq_14_bits_uop_cs.is_sta
invalidate stq_14_bits_uop_cs.is_load
invalidate stq_14_bits_uop_cs.csr_cmd
invalidate stq_14_bits_uop_cs.fcn_dw
invalidate stq_14_bits_uop_cs.op_fcn
invalidate stq_14_bits_uop_cs.imm_sel
invalidate stq_14_bits_uop_cs.op2_sel
invalidate stq_14_bits_uop_cs.op1_sel
invalidate stq_14_bits_uop_cs.br_type
connect stq_14_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_14_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_14_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_14_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_14_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_14_bits_uop_uop.ctrl, stq_14_bits_uop_cs
connect stq[14].bits.uop, stq_14_bits_uop_uop
connect stq[15].valid, UInt<1>(0h0)
connect stq[15].bits.addr.valid, UInt<1>(0h0)
connect stq[15].bits.data.valid, UInt<1>(0h0)
wire stq_15_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_15_bits_uop_uop.debug_tsrc
invalidate stq_15_bits_uop_uop.debug_fsrc
invalidate stq_15_bits_uop_uop.bp_xcpt_if
invalidate stq_15_bits_uop_uop.bp_debug_if
invalidate stq_15_bits_uop_uop.xcpt_ma_if
invalidate stq_15_bits_uop_uop.xcpt_ae_if
invalidate stq_15_bits_uop_uop.xcpt_pf_if
invalidate stq_15_bits_uop_uop.fp_single
invalidate stq_15_bits_uop_uop.fp_val
invalidate stq_15_bits_uop_uop.frs3_en
invalidate stq_15_bits_uop_uop.lrs2_rtype
invalidate stq_15_bits_uop_uop.lrs1_rtype
invalidate stq_15_bits_uop_uop.dst_rtype
invalidate stq_15_bits_uop_uop.ldst_val
invalidate stq_15_bits_uop_uop.lrs3
invalidate stq_15_bits_uop_uop.lrs2
invalidate stq_15_bits_uop_uop.lrs1
invalidate stq_15_bits_uop_uop.ldst
invalidate stq_15_bits_uop_uop.ldst_is_rs1
invalidate stq_15_bits_uop_uop.flush_on_commit
invalidate stq_15_bits_uop_uop.is_unique
invalidate stq_15_bits_uop_uop.is_sys_pc2epc
invalidate stq_15_bits_uop_uop.uses_stq
invalidate stq_15_bits_uop_uop.uses_ldq
invalidate stq_15_bits_uop_uop.is_amo
invalidate stq_15_bits_uop_uop.is_fencei
invalidate stq_15_bits_uop_uop.is_fence
invalidate stq_15_bits_uop_uop.mem_signed
invalidate stq_15_bits_uop_uop.mem_size
invalidate stq_15_bits_uop_uop.mem_cmd
invalidate stq_15_bits_uop_uop.bypassable
invalidate stq_15_bits_uop_uop.exc_cause
invalidate stq_15_bits_uop_uop.exception
invalidate stq_15_bits_uop_uop.stale_pdst
invalidate stq_15_bits_uop_uop.ppred_busy
invalidate stq_15_bits_uop_uop.prs3_busy
invalidate stq_15_bits_uop_uop.prs2_busy
invalidate stq_15_bits_uop_uop.prs1_busy
invalidate stq_15_bits_uop_uop.ppred
invalidate stq_15_bits_uop_uop.prs3
invalidate stq_15_bits_uop_uop.prs2
invalidate stq_15_bits_uop_uop.prs1
invalidate stq_15_bits_uop_uop.pdst
invalidate stq_15_bits_uop_uop.rxq_idx
invalidate stq_15_bits_uop_uop.stq_idx
invalidate stq_15_bits_uop_uop.ldq_idx
invalidate stq_15_bits_uop_uop.rob_idx
invalidate stq_15_bits_uop_uop.csr_addr
invalidate stq_15_bits_uop_uop.imm_packed
invalidate stq_15_bits_uop_uop.taken
invalidate stq_15_bits_uop_uop.pc_lob
invalidate stq_15_bits_uop_uop.edge_inst
invalidate stq_15_bits_uop_uop.ftq_idx
invalidate stq_15_bits_uop_uop.br_tag
invalidate stq_15_bits_uop_uop.br_mask
invalidate stq_15_bits_uop_uop.is_sfb
invalidate stq_15_bits_uop_uop.is_jal
invalidate stq_15_bits_uop_uop.is_jalr
invalidate stq_15_bits_uop_uop.is_br
invalidate stq_15_bits_uop_uop.iw_p2_poisoned
invalidate stq_15_bits_uop_uop.iw_p1_poisoned
invalidate stq_15_bits_uop_uop.iw_state
invalidate stq_15_bits_uop_uop.ctrl.is_std
invalidate stq_15_bits_uop_uop.ctrl.is_sta
invalidate stq_15_bits_uop_uop.ctrl.is_load
invalidate stq_15_bits_uop_uop.ctrl.csr_cmd
invalidate stq_15_bits_uop_uop.ctrl.fcn_dw
invalidate stq_15_bits_uop_uop.ctrl.op_fcn
invalidate stq_15_bits_uop_uop.ctrl.imm_sel
invalidate stq_15_bits_uop_uop.ctrl.op2_sel
invalidate stq_15_bits_uop_uop.ctrl.op1_sel
invalidate stq_15_bits_uop_uop.ctrl.br_type
invalidate stq_15_bits_uop_uop.fu_code
invalidate stq_15_bits_uop_uop.iq_type
invalidate stq_15_bits_uop_uop.debug_pc
invalidate stq_15_bits_uop_uop.is_rvc
invalidate stq_15_bits_uop_uop.debug_inst
invalidate stq_15_bits_uop_uop.inst
invalidate stq_15_bits_uop_uop.uopc
connect stq_15_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_15_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_15_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_15_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_15_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_15_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_15_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_15_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_15_bits_uop_cs.is_std
invalidate stq_15_bits_uop_cs.is_sta
invalidate stq_15_bits_uop_cs.is_load
invalidate stq_15_bits_uop_cs.csr_cmd
invalidate stq_15_bits_uop_cs.fcn_dw
invalidate stq_15_bits_uop_cs.op_fcn
invalidate stq_15_bits_uop_cs.imm_sel
invalidate stq_15_bits_uop_cs.op2_sel
invalidate stq_15_bits_uop_cs.op1_sel
invalidate stq_15_bits_uop_cs.br_type
connect stq_15_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_15_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_15_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_15_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_15_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_15_bits_uop_uop.ctrl, stq_15_bits_uop_cs
connect stq[15].bits.uop, stq_15_bits_uop_uop
connect stq[16].valid, UInt<1>(0h0)
connect stq[16].bits.addr.valid, UInt<1>(0h0)
connect stq[16].bits.data.valid, UInt<1>(0h0)
wire stq_16_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_16_bits_uop_uop.debug_tsrc
invalidate stq_16_bits_uop_uop.debug_fsrc
invalidate stq_16_bits_uop_uop.bp_xcpt_if
invalidate stq_16_bits_uop_uop.bp_debug_if
invalidate stq_16_bits_uop_uop.xcpt_ma_if
invalidate stq_16_bits_uop_uop.xcpt_ae_if
invalidate stq_16_bits_uop_uop.xcpt_pf_if
invalidate stq_16_bits_uop_uop.fp_single
invalidate stq_16_bits_uop_uop.fp_val
invalidate stq_16_bits_uop_uop.frs3_en
invalidate stq_16_bits_uop_uop.lrs2_rtype
invalidate stq_16_bits_uop_uop.lrs1_rtype
invalidate stq_16_bits_uop_uop.dst_rtype
invalidate stq_16_bits_uop_uop.ldst_val
invalidate stq_16_bits_uop_uop.lrs3
invalidate stq_16_bits_uop_uop.lrs2
invalidate stq_16_bits_uop_uop.lrs1
invalidate stq_16_bits_uop_uop.ldst
invalidate stq_16_bits_uop_uop.ldst_is_rs1
invalidate stq_16_bits_uop_uop.flush_on_commit
invalidate stq_16_bits_uop_uop.is_unique
invalidate stq_16_bits_uop_uop.is_sys_pc2epc
invalidate stq_16_bits_uop_uop.uses_stq
invalidate stq_16_bits_uop_uop.uses_ldq
invalidate stq_16_bits_uop_uop.is_amo
invalidate stq_16_bits_uop_uop.is_fencei
invalidate stq_16_bits_uop_uop.is_fence
invalidate stq_16_bits_uop_uop.mem_signed
invalidate stq_16_bits_uop_uop.mem_size
invalidate stq_16_bits_uop_uop.mem_cmd
invalidate stq_16_bits_uop_uop.bypassable
invalidate stq_16_bits_uop_uop.exc_cause
invalidate stq_16_bits_uop_uop.exception
invalidate stq_16_bits_uop_uop.stale_pdst
invalidate stq_16_bits_uop_uop.ppred_busy
invalidate stq_16_bits_uop_uop.prs3_busy
invalidate stq_16_bits_uop_uop.prs2_busy
invalidate stq_16_bits_uop_uop.prs1_busy
invalidate stq_16_bits_uop_uop.ppred
invalidate stq_16_bits_uop_uop.prs3
invalidate stq_16_bits_uop_uop.prs2
invalidate stq_16_bits_uop_uop.prs1
invalidate stq_16_bits_uop_uop.pdst
invalidate stq_16_bits_uop_uop.rxq_idx
invalidate stq_16_bits_uop_uop.stq_idx
invalidate stq_16_bits_uop_uop.ldq_idx
invalidate stq_16_bits_uop_uop.rob_idx
invalidate stq_16_bits_uop_uop.csr_addr
invalidate stq_16_bits_uop_uop.imm_packed
invalidate stq_16_bits_uop_uop.taken
invalidate stq_16_bits_uop_uop.pc_lob
invalidate stq_16_bits_uop_uop.edge_inst
invalidate stq_16_bits_uop_uop.ftq_idx
invalidate stq_16_bits_uop_uop.br_tag
invalidate stq_16_bits_uop_uop.br_mask
invalidate stq_16_bits_uop_uop.is_sfb
invalidate stq_16_bits_uop_uop.is_jal
invalidate stq_16_bits_uop_uop.is_jalr
invalidate stq_16_bits_uop_uop.is_br
invalidate stq_16_bits_uop_uop.iw_p2_poisoned
invalidate stq_16_bits_uop_uop.iw_p1_poisoned
invalidate stq_16_bits_uop_uop.iw_state
invalidate stq_16_bits_uop_uop.ctrl.is_std
invalidate stq_16_bits_uop_uop.ctrl.is_sta
invalidate stq_16_bits_uop_uop.ctrl.is_load
invalidate stq_16_bits_uop_uop.ctrl.csr_cmd
invalidate stq_16_bits_uop_uop.ctrl.fcn_dw
invalidate stq_16_bits_uop_uop.ctrl.op_fcn
invalidate stq_16_bits_uop_uop.ctrl.imm_sel
invalidate stq_16_bits_uop_uop.ctrl.op2_sel
invalidate stq_16_bits_uop_uop.ctrl.op1_sel
invalidate stq_16_bits_uop_uop.ctrl.br_type
invalidate stq_16_bits_uop_uop.fu_code
invalidate stq_16_bits_uop_uop.iq_type
invalidate stq_16_bits_uop_uop.debug_pc
invalidate stq_16_bits_uop_uop.is_rvc
invalidate stq_16_bits_uop_uop.debug_inst
invalidate stq_16_bits_uop_uop.inst
invalidate stq_16_bits_uop_uop.uopc
connect stq_16_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_16_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_16_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_16_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_16_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_16_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_16_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_16_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_16_bits_uop_cs.is_std
invalidate stq_16_bits_uop_cs.is_sta
invalidate stq_16_bits_uop_cs.is_load
invalidate stq_16_bits_uop_cs.csr_cmd
invalidate stq_16_bits_uop_cs.fcn_dw
invalidate stq_16_bits_uop_cs.op_fcn
invalidate stq_16_bits_uop_cs.imm_sel
invalidate stq_16_bits_uop_cs.op2_sel
invalidate stq_16_bits_uop_cs.op1_sel
invalidate stq_16_bits_uop_cs.br_type
connect stq_16_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_16_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_16_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_16_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_16_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_16_bits_uop_uop.ctrl, stq_16_bits_uop_cs
connect stq[16].bits.uop, stq_16_bits_uop_uop
connect stq[17].valid, UInt<1>(0h0)
connect stq[17].bits.addr.valid, UInt<1>(0h0)
connect stq[17].bits.data.valid, UInt<1>(0h0)
wire stq_17_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_17_bits_uop_uop.debug_tsrc
invalidate stq_17_bits_uop_uop.debug_fsrc
invalidate stq_17_bits_uop_uop.bp_xcpt_if
invalidate stq_17_bits_uop_uop.bp_debug_if
invalidate stq_17_bits_uop_uop.xcpt_ma_if
invalidate stq_17_bits_uop_uop.xcpt_ae_if
invalidate stq_17_bits_uop_uop.xcpt_pf_if
invalidate stq_17_bits_uop_uop.fp_single
invalidate stq_17_bits_uop_uop.fp_val
invalidate stq_17_bits_uop_uop.frs3_en
invalidate stq_17_bits_uop_uop.lrs2_rtype
invalidate stq_17_bits_uop_uop.lrs1_rtype
invalidate stq_17_bits_uop_uop.dst_rtype
invalidate stq_17_bits_uop_uop.ldst_val
invalidate stq_17_bits_uop_uop.lrs3
invalidate stq_17_bits_uop_uop.lrs2
invalidate stq_17_bits_uop_uop.lrs1
invalidate stq_17_bits_uop_uop.ldst
invalidate stq_17_bits_uop_uop.ldst_is_rs1
invalidate stq_17_bits_uop_uop.flush_on_commit
invalidate stq_17_bits_uop_uop.is_unique
invalidate stq_17_bits_uop_uop.is_sys_pc2epc
invalidate stq_17_bits_uop_uop.uses_stq
invalidate stq_17_bits_uop_uop.uses_ldq
invalidate stq_17_bits_uop_uop.is_amo
invalidate stq_17_bits_uop_uop.is_fencei
invalidate stq_17_bits_uop_uop.is_fence
invalidate stq_17_bits_uop_uop.mem_signed
invalidate stq_17_bits_uop_uop.mem_size
invalidate stq_17_bits_uop_uop.mem_cmd
invalidate stq_17_bits_uop_uop.bypassable
invalidate stq_17_bits_uop_uop.exc_cause
invalidate stq_17_bits_uop_uop.exception
invalidate stq_17_bits_uop_uop.stale_pdst
invalidate stq_17_bits_uop_uop.ppred_busy
invalidate stq_17_bits_uop_uop.prs3_busy
invalidate stq_17_bits_uop_uop.prs2_busy
invalidate stq_17_bits_uop_uop.prs1_busy
invalidate stq_17_bits_uop_uop.ppred
invalidate stq_17_bits_uop_uop.prs3
invalidate stq_17_bits_uop_uop.prs2
invalidate stq_17_bits_uop_uop.prs1
invalidate stq_17_bits_uop_uop.pdst
invalidate stq_17_bits_uop_uop.rxq_idx
invalidate stq_17_bits_uop_uop.stq_idx
invalidate stq_17_bits_uop_uop.ldq_idx
invalidate stq_17_bits_uop_uop.rob_idx
invalidate stq_17_bits_uop_uop.csr_addr
invalidate stq_17_bits_uop_uop.imm_packed
invalidate stq_17_bits_uop_uop.taken
invalidate stq_17_bits_uop_uop.pc_lob
invalidate stq_17_bits_uop_uop.edge_inst
invalidate stq_17_bits_uop_uop.ftq_idx
invalidate stq_17_bits_uop_uop.br_tag
invalidate stq_17_bits_uop_uop.br_mask
invalidate stq_17_bits_uop_uop.is_sfb
invalidate stq_17_bits_uop_uop.is_jal
invalidate stq_17_bits_uop_uop.is_jalr
invalidate stq_17_bits_uop_uop.is_br
invalidate stq_17_bits_uop_uop.iw_p2_poisoned
invalidate stq_17_bits_uop_uop.iw_p1_poisoned
invalidate stq_17_bits_uop_uop.iw_state
invalidate stq_17_bits_uop_uop.ctrl.is_std
invalidate stq_17_bits_uop_uop.ctrl.is_sta
invalidate stq_17_bits_uop_uop.ctrl.is_load
invalidate stq_17_bits_uop_uop.ctrl.csr_cmd
invalidate stq_17_bits_uop_uop.ctrl.fcn_dw
invalidate stq_17_bits_uop_uop.ctrl.op_fcn
invalidate stq_17_bits_uop_uop.ctrl.imm_sel
invalidate stq_17_bits_uop_uop.ctrl.op2_sel
invalidate stq_17_bits_uop_uop.ctrl.op1_sel
invalidate stq_17_bits_uop_uop.ctrl.br_type
invalidate stq_17_bits_uop_uop.fu_code
invalidate stq_17_bits_uop_uop.iq_type
invalidate stq_17_bits_uop_uop.debug_pc
invalidate stq_17_bits_uop_uop.is_rvc
invalidate stq_17_bits_uop_uop.debug_inst
invalidate stq_17_bits_uop_uop.inst
invalidate stq_17_bits_uop_uop.uopc
connect stq_17_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_17_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_17_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_17_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_17_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_17_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_17_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_17_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_17_bits_uop_cs.is_std
invalidate stq_17_bits_uop_cs.is_sta
invalidate stq_17_bits_uop_cs.is_load
invalidate stq_17_bits_uop_cs.csr_cmd
invalidate stq_17_bits_uop_cs.fcn_dw
invalidate stq_17_bits_uop_cs.op_fcn
invalidate stq_17_bits_uop_cs.imm_sel
invalidate stq_17_bits_uop_cs.op2_sel
invalidate stq_17_bits_uop_cs.op1_sel
invalidate stq_17_bits_uop_cs.br_type
connect stq_17_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_17_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_17_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_17_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_17_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_17_bits_uop_uop.ctrl, stq_17_bits_uop_cs
connect stq[17].bits.uop, stq_17_bits_uop_uop
connect stq[18].valid, UInt<1>(0h0)
connect stq[18].bits.addr.valid, UInt<1>(0h0)
connect stq[18].bits.data.valid, UInt<1>(0h0)
wire stq_18_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_18_bits_uop_uop.debug_tsrc
invalidate stq_18_bits_uop_uop.debug_fsrc
invalidate stq_18_bits_uop_uop.bp_xcpt_if
invalidate stq_18_bits_uop_uop.bp_debug_if
invalidate stq_18_bits_uop_uop.xcpt_ma_if
invalidate stq_18_bits_uop_uop.xcpt_ae_if
invalidate stq_18_bits_uop_uop.xcpt_pf_if
invalidate stq_18_bits_uop_uop.fp_single
invalidate stq_18_bits_uop_uop.fp_val
invalidate stq_18_bits_uop_uop.frs3_en
invalidate stq_18_bits_uop_uop.lrs2_rtype
invalidate stq_18_bits_uop_uop.lrs1_rtype
invalidate stq_18_bits_uop_uop.dst_rtype
invalidate stq_18_bits_uop_uop.ldst_val
invalidate stq_18_bits_uop_uop.lrs3
invalidate stq_18_bits_uop_uop.lrs2
invalidate stq_18_bits_uop_uop.lrs1
invalidate stq_18_bits_uop_uop.ldst
invalidate stq_18_bits_uop_uop.ldst_is_rs1
invalidate stq_18_bits_uop_uop.flush_on_commit
invalidate stq_18_bits_uop_uop.is_unique
invalidate stq_18_bits_uop_uop.is_sys_pc2epc
invalidate stq_18_bits_uop_uop.uses_stq
invalidate stq_18_bits_uop_uop.uses_ldq
invalidate stq_18_bits_uop_uop.is_amo
invalidate stq_18_bits_uop_uop.is_fencei
invalidate stq_18_bits_uop_uop.is_fence
invalidate stq_18_bits_uop_uop.mem_signed
invalidate stq_18_bits_uop_uop.mem_size
invalidate stq_18_bits_uop_uop.mem_cmd
invalidate stq_18_bits_uop_uop.bypassable
invalidate stq_18_bits_uop_uop.exc_cause
invalidate stq_18_bits_uop_uop.exception
invalidate stq_18_bits_uop_uop.stale_pdst
invalidate stq_18_bits_uop_uop.ppred_busy
invalidate stq_18_bits_uop_uop.prs3_busy
invalidate stq_18_bits_uop_uop.prs2_busy
invalidate stq_18_bits_uop_uop.prs1_busy
invalidate stq_18_bits_uop_uop.ppred
invalidate stq_18_bits_uop_uop.prs3
invalidate stq_18_bits_uop_uop.prs2
invalidate stq_18_bits_uop_uop.prs1
invalidate stq_18_bits_uop_uop.pdst
invalidate stq_18_bits_uop_uop.rxq_idx
invalidate stq_18_bits_uop_uop.stq_idx
invalidate stq_18_bits_uop_uop.ldq_idx
invalidate stq_18_bits_uop_uop.rob_idx
invalidate stq_18_bits_uop_uop.csr_addr
invalidate stq_18_bits_uop_uop.imm_packed
invalidate stq_18_bits_uop_uop.taken
invalidate stq_18_bits_uop_uop.pc_lob
invalidate stq_18_bits_uop_uop.edge_inst
invalidate stq_18_bits_uop_uop.ftq_idx
invalidate stq_18_bits_uop_uop.br_tag
invalidate stq_18_bits_uop_uop.br_mask
invalidate stq_18_bits_uop_uop.is_sfb
invalidate stq_18_bits_uop_uop.is_jal
invalidate stq_18_bits_uop_uop.is_jalr
invalidate stq_18_bits_uop_uop.is_br
invalidate stq_18_bits_uop_uop.iw_p2_poisoned
invalidate stq_18_bits_uop_uop.iw_p1_poisoned
invalidate stq_18_bits_uop_uop.iw_state
invalidate stq_18_bits_uop_uop.ctrl.is_std
invalidate stq_18_bits_uop_uop.ctrl.is_sta
invalidate stq_18_bits_uop_uop.ctrl.is_load
invalidate stq_18_bits_uop_uop.ctrl.csr_cmd
invalidate stq_18_bits_uop_uop.ctrl.fcn_dw
invalidate stq_18_bits_uop_uop.ctrl.op_fcn
invalidate stq_18_bits_uop_uop.ctrl.imm_sel
invalidate stq_18_bits_uop_uop.ctrl.op2_sel
invalidate stq_18_bits_uop_uop.ctrl.op1_sel
invalidate stq_18_bits_uop_uop.ctrl.br_type
invalidate stq_18_bits_uop_uop.fu_code
invalidate stq_18_bits_uop_uop.iq_type
invalidate stq_18_bits_uop_uop.debug_pc
invalidate stq_18_bits_uop_uop.is_rvc
invalidate stq_18_bits_uop_uop.debug_inst
invalidate stq_18_bits_uop_uop.inst
invalidate stq_18_bits_uop_uop.uopc
connect stq_18_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_18_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_18_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_18_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_18_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_18_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_18_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_18_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_18_bits_uop_cs.is_std
invalidate stq_18_bits_uop_cs.is_sta
invalidate stq_18_bits_uop_cs.is_load
invalidate stq_18_bits_uop_cs.csr_cmd
invalidate stq_18_bits_uop_cs.fcn_dw
invalidate stq_18_bits_uop_cs.op_fcn
invalidate stq_18_bits_uop_cs.imm_sel
invalidate stq_18_bits_uop_cs.op2_sel
invalidate stq_18_bits_uop_cs.op1_sel
invalidate stq_18_bits_uop_cs.br_type
connect stq_18_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_18_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_18_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_18_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_18_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_18_bits_uop_uop.ctrl, stq_18_bits_uop_cs
connect stq[18].bits.uop, stq_18_bits_uop_uop
connect stq[19].valid, UInt<1>(0h0)
connect stq[19].bits.addr.valid, UInt<1>(0h0)
connect stq[19].bits.data.valid, UInt<1>(0h0)
wire stq_19_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_19_bits_uop_uop.debug_tsrc
invalidate stq_19_bits_uop_uop.debug_fsrc
invalidate stq_19_bits_uop_uop.bp_xcpt_if
invalidate stq_19_bits_uop_uop.bp_debug_if
invalidate stq_19_bits_uop_uop.xcpt_ma_if
invalidate stq_19_bits_uop_uop.xcpt_ae_if
invalidate stq_19_bits_uop_uop.xcpt_pf_if
invalidate stq_19_bits_uop_uop.fp_single
invalidate stq_19_bits_uop_uop.fp_val
invalidate stq_19_bits_uop_uop.frs3_en
invalidate stq_19_bits_uop_uop.lrs2_rtype
invalidate stq_19_bits_uop_uop.lrs1_rtype
invalidate stq_19_bits_uop_uop.dst_rtype
invalidate stq_19_bits_uop_uop.ldst_val
invalidate stq_19_bits_uop_uop.lrs3
invalidate stq_19_bits_uop_uop.lrs2
invalidate stq_19_bits_uop_uop.lrs1
invalidate stq_19_bits_uop_uop.ldst
invalidate stq_19_bits_uop_uop.ldst_is_rs1
invalidate stq_19_bits_uop_uop.flush_on_commit
invalidate stq_19_bits_uop_uop.is_unique
invalidate stq_19_bits_uop_uop.is_sys_pc2epc
invalidate stq_19_bits_uop_uop.uses_stq
invalidate stq_19_bits_uop_uop.uses_ldq
invalidate stq_19_bits_uop_uop.is_amo
invalidate stq_19_bits_uop_uop.is_fencei
invalidate stq_19_bits_uop_uop.is_fence
invalidate stq_19_bits_uop_uop.mem_signed
invalidate stq_19_bits_uop_uop.mem_size
invalidate stq_19_bits_uop_uop.mem_cmd
invalidate stq_19_bits_uop_uop.bypassable
invalidate stq_19_bits_uop_uop.exc_cause
invalidate stq_19_bits_uop_uop.exception
invalidate stq_19_bits_uop_uop.stale_pdst
invalidate stq_19_bits_uop_uop.ppred_busy
invalidate stq_19_bits_uop_uop.prs3_busy
invalidate stq_19_bits_uop_uop.prs2_busy
invalidate stq_19_bits_uop_uop.prs1_busy
invalidate stq_19_bits_uop_uop.ppred
invalidate stq_19_bits_uop_uop.prs3
invalidate stq_19_bits_uop_uop.prs2
invalidate stq_19_bits_uop_uop.prs1
invalidate stq_19_bits_uop_uop.pdst
invalidate stq_19_bits_uop_uop.rxq_idx
invalidate stq_19_bits_uop_uop.stq_idx
invalidate stq_19_bits_uop_uop.ldq_idx
invalidate stq_19_bits_uop_uop.rob_idx
invalidate stq_19_bits_uop_uop.csr_addr
invalidate stq_19_bits_uop_uop.imm_packed
invalidate stq_19_bits_uop_uop.taken
invalidate stq_19_bits_uop_uop.pc_lob
invalidate stq_19_bits_uop_uop.edge_inst
invalidate stq_19_bits_uop_uop.ftq_idx
invalidate stq_19_bits_uop_uop.br_tag
invalidate stq_19_bits_uop_uop.br_mask
invalidate stq_19_bits_uop_uop.is_sfb
invalidate stq_19_bits_uop_uop.is_jal
invalidate stq_19_bits_uop_uop.is_jalr
invalidate stq_19_bits_uop_uop.is_br
invalidate stq_19_bits_uop_uop.iw_p2_poisoned
invalidate stq_19_bits_uop_uop.iw_p1_poisoned
invalidate stq_19_bits_uop_uop.iw_state
invalidate stq_19_bits_uop_uop.ctrl.is_std
invalidate stq_19_bits_uop_uop.ctrl.is_sta
invalidate stq_19_bits_uop_uop.ctrl.is_load
invalidate stq_19_bits_uop_uop.ctrl.csr_cmd
invalidate stq_19_bits_uop_uop.ctrl.fcn_dw
invalidate stq_19_bits_uop_uop.ctrl.op_fcn
invalidate stq_19_bits_uop_uop.ctrl.imm_sel
invalidate stq_19_bits_uop_uop.ctrl.op2_sel
invalidate stq_19_bits_uop_uop.ctrl.op1_sel
invalidate stq_19_bits_uop_uop.ctrl.br_type
invalidate stq_19_bits_uop_uop.fu_code
invalidate stq_19_bits_uop_uop.iq_type
invalidate stq_19_bits_uop_uop.debug_pc
invalidate stq_19_bits_uop_uop.is_rvc
invalidate stq_19_bits_uop_uop.debug_inst
invalidate stq_19_bits_uop_uop.inst
invalidate stq_19_bits_uop_uop.uopc
connect stq_19_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_19_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_19_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_19_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_19_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_19_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_19_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_19_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_19_bits_uop_cs.is_std
invalidate stq_19_bits_uop_cs.is_sta
invalidate stq_19_bits_uop_cs.is_load
invalidate stq_19_bits_uop_cs.csr_cmd
invalidate stq_19_bits_uop_cs.fcn_dw
invalidate stq_19_bits_uop_cs.op_fcn
invalidate stq_19_bits_uop_cs.imm_sel
invalidate stq_19_bits_uop_cs.op2_sel
invalidate stq_19_bits_uop_cs.op1_sel
invalidate stq_19_bits_uop_cs.br_type
connect stq_19_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_19_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_19_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_19_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_19_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_19_bits_uop_uop.ctrl, stq_19_bits_uop_cs
connect stq[19].bits.uop, stq_19_bits_uop_uop
connect stq[20].valid, UInt<1>(0h0)
connect stq[20].bits.addr.valid, UInt<1>(0h0)
connect stq[20].bits.data.valid, UInt<1>(0h0)
wire stq_20_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_20_bits_uop_uop.debug_tsrc
invalidate stq_20_bits_uop_uop.debug_fsrc
invalidate stq_20_bits_uop_uop.bp_xcpt_if
invalidate stq_20_bits_uop_uop.bp_debug_if
invalidate stq_20_bits_uop_uop.xcpt_ma_if
invalidate stq_20_bits_uop_uop.xcpt_ae_if
invalidate stq_20_bits_uop_uop.xcpt_pf_if
invalidate stq_20_bits_uop_uop.fp_single
invalidate stq_20_bits_uop_uop.fp_val
invalidate stq_20_bits_uop_uop.frs3_en
invalidate stq_20_bits_uop_uop.lrs2_rtype
invalidate stq_20_bits_uop_uop.lrs1_rtype
invalidate stq_20_bits_uop_uop.dst_rtype
invalidate stq_20_bits_uop_uop.ldst_val
invalidate stq_20_bits_uop_uop.lrs3
invalidate stq_20_bits_uop_uop.lrs2
invalidate stq_20_bits_uop_uop.lrs1
invalidate stq_20_bits_uop_uop.ldst
invalidate stq_20_bits_uop_uop.ldst_is_rs1
invalidate stq_20_bits_uop_uop.flush_on_commit
invalidate stq_20_bits_uop_uop.is_unique
invalidate stq_20_bits_uop_uop.is_sys_pc2epc
invalidate stq_20_bits_uop_uop.uses_stq
invalidate stq_20_bits_uop_uop.uses_ldq
invalidate stq_20_bits_uop_uop.is_amo
invalidate stq_20_bits_uop_uop.is_fencei
invalidate stq_20_bits_uop_uop.is_fence
invalidate stq_20_bits_uop_uop.mem_signed
invalidate stq_20_bits_uop_uop.mem_size
invalidate stq_20_bits_uop_uop.mem_cmd
invalidate stq_20_bits_uop_uop.bypassable
invalidate stq_20_bits_uop_uop.exc_cause
invalidate stq_20_bits_uop_uop.exception
invalidate stq_20_bits_uop_uop.stale_pdst
invalidate stq_20_bits_uop_uop.ppred_busy
invalidate stq_20_bits_uop_uop.prs3_busy
invalidate stq_20_bits_uop_uop.prs2_busy
invalidate stq_20_bits_uop_uop.prs1_busy
invalidate stq_20_bits_uop_uop.ppred
invalidate stq_20_bits_uop_uop.prs3
invalidate stq_20_bits_uop_uop.prs2
invalidate stq_20_bits_uop_uop.prs1
invalidate stq_20_bits_uop_uop.pdst
invalidate stq_20_bits_uop_uop.rxq_idx
invalidate stq_20_bits_uop_uop.stq_idx
invalidate stq_20_bits_uop_uop.ldq_idx
invalidate stq_20_bits_uop_uop.rob_idx
invalidate stq_20_bits_uop_uop.csr_addr
invalidate stq_20_bits_uop_uop.imm_packed
invalidate stq_20_bits_uop_uop.taken
invalidate stq_20_bits_uop_uop.pc_lob
invalidate stq_20_bits_uop_uop.edge_inst
invalidate stq_20_bits_uop_uop.ftq_idx
invalidate stq_20_bits_uop_uop.br_tag
invalidate stq_20_bits_uop_uop.br_mask
invalidate stq_20_bits_uop_uop.is_sfb
invalidate stq_20_bits_uop_uop.is_jal
invalidate stq_20_bits_uop_uop.is_jalr
invalidate stq_20_bits_uop_uop.is_br
invalidate stq_20_bits_uop_uop.iw_p2_poisoned
invalidate stq_20_bits_uop_uop.iw_p1_poisoned
invalidate stq_20_bits_uop_uop.iw_state
invalidate stq_20_bits_uop_uop.ctrl.is_std
invalidate stq_20_bits_uop_uop.ctrl.is_sta
invalidate stq_20_bits_uop_uop.ctrl.is_load
invalidate stq_20_bits_uop_uop.ctrl.csr_cmd
invalidate stq_20_bits_uop_uop.ctrl.fcn_dw
invalidate stq_20_bits_uop_uop.ctrl.op_fcn
invalidate stq_20_bits_uop_uop.ctrl.imm_sel
invalidate stq_20_bits_uop_uop.ctrl.op2_sel
invalidate stq_20_bits_uop_uop.ctrl.op1_sel
invalidate stq_20_bits_uop_uop.ctrl.br_type
invalidate stq_20_bits_uop_uop.fu_code
invalidate stq_20_bits_uop_uop.iq_type
invalidate stq_20_bits_uop_uop.debug_pc
invalidate stq_20_bits_uop_uop.is_rvc
invalidate stq_20_bits_uop_uop.debug_inst
invalidate stq_20_bits_uop_uop.inst
invalidate stq_20_bits_uop_uop.uopc
connect stq_20_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_20_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_20_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_20_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_20_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_20_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_20_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_20_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_20_bits_uop_cs.is_std
invalidate stq_20_bits_uop_cs.is_sta
invalidate stq_20_bits_uop_cs.is_load
invalidate stq_20_bits_uop_cs.csr_cmd
invalidate stq_20_bits_uop_cs.fcn_dw
invalidate stq_20_bits_uop_cs.op_fcn
invalidate stq_20_bits_uop_cs.imm_sel
invalidate stq_20_bits_uop_cs.op2_sel
invalidate stq_20_bits_uop_cs.op1_sel
invalidate stq_20_bits_uop_cs.br_type
connect stq_20_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_20_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_20_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_20_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_20_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_20_bits_uop_uop.ctrl, stq_20_bits_uop_cs
connect stq[20].bits.uop, stq_20_bits_uop_uop
connect stq[21].valid, UInt<1>(0h0)
connect stq[21].bits.addr.valid, UInt<1>(0h0)
connect stq[21].bits.data.valid, UInt<1>(0h0)
wire stq_21_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_21_bits_uop_uop.debug_tsrc
invalidate stq_21_bits_uop_uop.debug_fsrc
invalidate stq_21_bits_uop_uop.bp_xcpt_if
invalidate stq_21_bits_uop_uop.bp_debug_if
invalidate stq_21_bits_uop_uop.xcpt_ma_if
invalidate stq_21_bits_uop_uop.xcpt_ae_if
invalidate stq_21_bits_uop_uop.xcpt_pf_if
invalidate stq_21_bits_uop_uop.fp_single
invalidate stq_21_bits_uop_uop.fp_val
invalidate stq_21_bits_uop_uop.frs3_en
invalidate stq_21_bits_uop_uop.lrs2_rtype
invalidate stq_21_bits_uop_uop.lrs1_rtype
invalidate stq_21_bits_uop_uop.dst_rtype
invalidate stq_21_bits_uop_uop.ldst_val
invalidate stq_21_bits_uop_uop.lrs3
invalidate stq_21_bits_uop_uop.lrs2
invalidate stq_21_bits_uop_uop.lrs1
invalidate stq_21_bits_uop_uop.ldst
invalidate stq_21_bits_uop_uop.ldst_is_rs1
invalidate stq_21_bits_uop_uop.flush_on_commit
invalidate stq_21_bits_uop_uop.is_unique
invalidate stq_21_bits_uop_uop.is_sys_pc2epc
invalidate stq_21_bits_uop_uop.uses_stq
invalidate stq_21_bits_uop_uop.uses_ldq
invalidate stq_21_bits_uop_uop.is_amo
invalidate stq_21_bits_uop_uop.is_fencei
invalidate stq_21_bits_uop_uop.is_fence
invalidate stq_21_bits_uop_uop.mem_signed
invalidate stq_21_bits_uop_uop.mem_size
invalidate stq_21_bits_uop_uop.mem_cmd
invalidate stq_21_bits_uop_uop.bypassable
invalidate stq_21_bits_uop_uop.exc_cause
invalidate stq_21_bits_uop_uop.exception
invalidate stq_21_bits_uop_uop.stale_pdst
invalidate stq_21_bits_uop_uop.ppred_busy
invalidate stq_21_bits_uop_uop.prs3_busy
invalidate stq_21_bits_uop_uop.prs2_busy
invalidate stq_21_bits_uop_uop.prs1_busy
invalidate stq_21_bits_uop_uop.ppred
invalidate stq_21_bits_uop_uop.prs3
invalidate stq_21_bits_uop_uop.prs2
invalidate stq_21_bits_uop_uop.prs1
invalidate stq_21_bits_uop_uop.pdst
invalidate stq_21_bits_uop_uop.rxq_idx
invalidate stq_21_bits_uop_uop.stq_idx
invalidate stq_21_bits_uop_uop.ldq_idx
invalidate stq_21_bits_uop_uop.rob_idx
invalidate stq_21_bits_uop_uop.csr_addr
invalidate stq_21_bits_uop_uop.imm_packed
invalidate stq_21_bits_uop_uop.taken
invalidate stq_21_bits_uop_uop.pc_lob
invalidate stq_21_bits_uop_uop.edge_inst
invalidate stq_21_bits_uop_uop.ftq_idx
invalidate stq_21_bits_uop_uop.br_tag
invalidate stq_21_bits_uop_uop.br_mask
invalidate stq_21_bits_uop_uop.is_sfb
invalidate stq_21_bits_uop_uop.is_jal
invalidate stq_21_bits_uop_uop.is_jalr
invalidate stq_21_bits_uop_uop.is_br
invalidate stq_21_bits_uop_uop.iw_p2_poisoned
invalidate stq_21_bits_uop_uop.iw_p1_poisoned
invalidate stq_21_bits_uop_uop.iw_state
invalidate stq_21_bits_uop_uop.ctrl.is_std
invalidate stq_21_bits_uop_uop.ctrl.is_sta
invalidate stq_21_bits_uop_uop.ctrl.is_load
invalidate stq_21_bits_uop_uop.ctrl.csr_cmd
invalidate stq_21_bits_uop_uop.ctrl.fcn_dw
invalidate stq_21_bits_uop_uop.ctrl.op_fcn
invalidate stq_21_bits_uop_uop.ctrl.imm_sel
invalidate stq_21_bits_uop_uop.ctrl.op2_sel
invalidate stq_21_bits_uop_uop.ctrl.op1_sel
invalidate stq_21_bits_uop_uop.ctrl.br_type
invalidate stq_21_bits_uop_uop.fu_code
invalidate stq_21_bits_uop_uop.iq_type
invalidate stq_21_bits_uop_uop.debug_pc
invalidate stq_21_bits_uop_uop.is_rvc
invalidate stq_21_bits_uop_uop.debug_inst
invalidate stq_21_bits_uop_uop.inst
invalidate stq_21_bits_uop_uop.uopc
connect stq_21_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_21_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_21_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_21_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_21_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_21_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_21_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_21_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_21_bits_uop_cs.is_std
invalidate stq_21_bits_uop_cs.is_sta
invalidate stq_21_bits_uop_cs.is_load
invalidate stq_21_bits_uop_cs.csr_cmd
invalidate stq_21_bits_uop_cs.fcn_dw
invalidate stq_21_bits_uop_cs.op_fcn
invalidate stq_21_bits_uop_cs.imm_sel
invalidate stq_21_bits_uop_cs.op2_sel
invalidate stq_21_bits_uop_cs.op1_sel
invalidate stq_21_bits_uop_cs.br_type
connect stq_21_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_21_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_21_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_21_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_21_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_21_bits_uop_uop.ctrl, stq_21_bits_uop_cs
connect stq[21].bits.uop, stq_21_bits_uop_uop
connect stq[22].valid, UInt<1>(0h0)
connect stq[22].bits.addr.valid, UInt<1>(0h0)
connect stq[22].bits.data.valid, UInt<1>(0h0)
wire stq_22_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_22_bits_uop_uop.debug_tsrc
invalidate stq_22_bits_uop_uop.debug_fsrc
invalidate stq_22_bits_uop_uop.bp_xcpt_if
invalidate stq_22_bits_uop_uop.bp_debug_if
invalidate stq_22_bits_uop_uop.xcpt_ma_if
invalidate stq_22_bits_uop_uop.xcpt_ae_if
invalidate stq_22_bits_uop_uop.xcpt_pf_if
invalidate stq_22_bits_uop_uop.fp_single
invalidate stq_22_bits_uop_uop.fp_val
invalidate stq_22_bits_uop_uop.frs3_en
invalidate stq_22_bits_uop_uop.lrs2_rtype
invalidate stq_22_bits_uop_uop.lrs1_rtype
invalidate stq_22_bits_uop_uop.dst_rtype
invalidate stq_22_bits_uop_uop.ldst_val
invalidate stq_22_bits_uop_uop.lrs3
invalidate stq_22_bits_uop_uop.lrs2
invalidate stq_22_bits_uop_uop.lrs1
invalidate stq_22_bits_uop_uop.ldst
invalidate stq_22_bits_uop_uop.ldst_is_rs1
invalidate stq_22_bits_uop_uop.flush_on_commit
invalidate stq_22_bits_uop_uop.is_unique
invalidate stq_22_bits_uop_uop.is_sys_pc2epc
invalidate stq_22_bits_uop_uop.uses_stq
invalidate stq_22_bits_uop_uop.uses_ldq
invalidate stq_22_bits_uop_uop.is_amo
invalidate stq_22_bits_uop_uop.is_fencei
invalidate stq_22_bits_uop_uop.is_fence
invalidate stq_22_bits_uop_uop.mem_signed
invalidate stq_22_bits_uop_uop.mem_size
invalidate stq_22_bits_uop_uop.mem_cmd
invalidate stq_22_bits_uop_uop.bypassable
invalidate stq_22_bits_uop_uop.exc_cause
invalidate stq_22_bits_uop_uop.exception
invalidate stq_22_bits_uop_uop.stale_pdst
invalidate stq_22_bits_uop_uop.ppred_busy
invalidate stq_22_bits_uop_uop.prs3_busy
invalidate stq_22_bits_uop_uop.prs2_busy
invalidate stq_22_bits_uop_uop.prs1_busy
invalidate stq_22_bits_uop_uop.ppred
invalidate stq_22_bits_uop_uop.prs3
invalidate stq_22_bits_uop_uop.prs2
invalidate stq_22_bits_uop_uop.prs1
invalidate stq_22_bits_uop_uop.pdst
invalidate stq_22_bits_uop_uop.rxq_idx
invalidate stq_22_bits_uop_uop.stq_idx
invalidate stq_22_bits_uop_uop.ldq_idx
invalidate stq_22_bits_uop_uop.rob_idx
invalidate stq_22_bits_uop_uop.csr_addr
invalidate stq_22_bits_uop_uop.imm_packed
invalidate stq_22_bits_uop_uop.taken
invalidate stq_22_bits_uop_uop.pc_lob
invalidate stq_22_bits_uop_uop.edge_inst
invalidate stq_22_bits_uop_uop.ftq_idx
invalidate stq_22_bits_uop_uop.br_tag
invalidate stq_22_bits_uop_uop.br_mask
invalidate stq_22_bits_uop_uop.is_sfb
invalidate stq_22_bits_uop_uop.is_jal
invalidate stq_22_bits_uop_uop.is_jalr
invalidate stq_22_bits_uop_uop.is_br
invalidate stq_22_bits_uop_uop.iw_p2_poisoned
invalidate stq_22_bits_uop_uop.iw_p1_poisoned
invalidate stq_22_bits_uop_uop.iw_state
invalidate stq_22_bits_uop_uop.ctrl.is_std
invalidate stq_22_bits_uop_uop.ctrl.is_sta
invalidate stq_22_bits_uop_uop.ctrl.is_load
invalidate stq_22_bits_uop_uop.ctrl.csr_cmd
invalidate stq_22_bits_uop_uop.ctrl.fcn_dw
invalidate stq_22_bits_uop_uop.ctrl.op_fcn
invalidate stq_22_bits_uop_uop.ctrl.imm_sel
invalidate stq_22_bits_uop_uop.ctrl.op2_sel
invalidate stq_22_bits_uop_uop.ctrl.op1_sel
invalidate stq_22_bits_uop_uop.ctrl.br_type
invalidate stq_22_bits_uop_uop.fu_code
invalidate stq_22_bits_uop_uop.iq_type
invalidate stq_22_bits_uop_uop.debug_pc
invalidate stq_22_bits_uop_uop.is_rvc
invalidate stq_22_bits_uop_uop.debug_inst
invalidate stq_22_bits_uop_uop.inst
invalidate stq_22_bits_uop_uop.uopc
connect stq_22_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_22_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_22_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_22_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_22_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_22_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_22_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_22_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_22_bits_uop_cs.is_std
invalidate stq_22_bits_uop_cs.is_sta
invalidate stq_22_bits_uop_cs.is_load
invalidate stq_22_bits_uop_cs.csr_cmd
invalidate stq_22_bits_uop_cs.fcn_dw
invalidate stq_22_bits_uop_cs.op_fcn
invalidate stq_22_bits_uop_cs.imm_sel
invalidate stq_22_bits_uop_cs.op2_sel
invalidate stq_22_bits_uop_cs.op1_sel
invalidate stq_22_bits_uop_cs.br_type
connect stq_22_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_22_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_22_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_22_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_22_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_22_bits_uop_uop.ctrl, stq_22_bits_uop_cs
connect stq[22].bits.uop, stq_22_bits_uop_uop
connect stq[23].valid, UInt<1>(0h0)
connect stq[23].bits.addr.valid, UInt<1>(0h0)
connect stq[23].bits.data.valid, UInt<1>(0h0)
wire stq_23_bits_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate stq_23_bits_uop_uop.debug_tsrc
invalidate stq_23_bits_uop_uop.debug_fsrc
invalidate stq_23_bits_uop_uop.bp_xcpt_if
invalidate stq_23_bits_uop_uop.bp_debug_if
invalidate stq_23_bits_uop_uop.xcpt_ma_if
invalidate stq_23_bits_uop_uop.xcpt_ae_if
invalidate stq_23_bits_uop_uop.xcpt_pf_if
invalidate stq_23_bits_uop_uop.fp_single
invalidate stq_23_bits_uop_uop.fp_val
invalidate stq_23_bits_uop_uop.frs3_en
invalidate stq_23_bits_uop_uop.lrs2_rtype
invalidate stq_23_bits_uop_uop.lrs1_rtype
invalidate stq_23_bits_uop_uop.dst_rtype
invalidate stq_23_bits_uop_uop.ldst_val
invalidate stq_23_bits_uop_uop.lrs3
invalidate stq_23_bits_uop_uop.lrs2
invalidate stq_23_bits_uop_uop.lrs1
invalidate stq_23_bits_uop_uop.ldst
invalidate stq_23_bits_uop_uop.ldst_is_rs1
invalidate stq_23_bits_uop_uop.flush_on_commit
invalidate stq_23_bits_uop_uop.is_unique
invalidate stq_23_bits_uop_uop.is_sys_pc2epc
invalidate stq_23_bits_uop_uop.uses_stq
invalidate stq_23_bits_uop_uop.uses_ldq
invalidate stq_23_bits_uop_uop.is_amo
invalidate stq_23_bits_uop_uop.is_fencei
invalidate stq_23_bits_uop_uop.is_fence
invalidate stq_23_bits_uop_uop.mem_signed
invalidate stq_23_bits_uop_uop.mem_size
invalidate stq_23_bits_uop_uop.mem_cmd
invalidate stq_23_bits_uop_uop.bypassable
invalidate stq_23_bits_uop_uop.exc_cause
invalidate stq_23_bits_uop_uop.exception
invalidate stq_23_bits_uop_uop.stale_pdst
invalidate stq_23_bits_uop_uop.ppred_busy
invalidate stq_23_bits_uop_uop.prs3_busy
invalidate stq_23_bits_uop_uop.prs2_busy
invalidate stq_23_bits_uop_uop.prs1_busy
invalidate stq_23_bits_uop_uop.ppred
invalidate stq_23_bits_uop_uop.prs3
invalidate stq_23_bits_uop_uop.prs2
invalidate stq_23_bits_uop_uop.prs1
invalidate stq_23_bits_uop_uop.pdst
invalidate stq_23_bits_uop_uop.rxq_idx
invalidate stq_23_bits_uop_uop.stq_idx
invalidate stq_23_bits_uop_uop.ldq_idx
invalidate stq_23_bits_uop_uop.rob_idx
invalidate stq_23_bits_uop_uop.csr_addr
invalidate stq_23_bits_uop_uop.imm_packed
invalidate stq_23_bits_uop_uop.taken
invalidate stq_23_bits_uop_uop.pc_lob
invalidate stq_23_bits_uop_uop.edge_inst
invalidate stq_23_bits_uop_uop.ftq_idx
invalidate stq_23_bits_uop_uop.br_tag
invalidate stq_23_bits_uop_uop.br_mask
invalidate stq_23_bits_uop_uop.is_sfb
invalidate stq_23_bits_uop_uop.is_jal
invalidate stq_23_bits_uop_uop.is_jalr
invalidate stq_23_bits_uop_uop.is_br
invalidate stq_23_bits_uop_uop.iw_p2_poisoned
invalidate stq_23_bits_uop_uop.iw_p1_poisoned
invalidate stq_23_bits_uop_uop.iw_state
invalidate stq_23_bits_uop_uop.ctrl.is_std
invalidate stq_23_bits_uop_uop.ctrl.is_sta
invalidate stq_23_bits_uop_uop.ctrl.is_load
invalidate stq_23_bits_uop_uop.ctrl.csr_cmd
invalidate stq_23_bits_uop_uop.ctrl.fcn_dw
invalidate stq_23_bits_uop_uop.ctrl.op_fcn
invalidate stq_23_bits_uop_uop.ctrl.imm_sel
invalidate stq_23_bits_uop_uop.ctrl.op2_sel
invalidate stq_23_bits_uop_uop.ctrl.op1_sel
invalidate stq_23_bits_uop_uop.ctrl.br_type
invalidate stq_23_bits_uop_uop.fu_code
invalidate stq_23_bits_uop_uop.iq_type
invalidate stq_23_bits_uop_uop.debug_pc
invalidate stq_23_bits_uop_uop.is_rvc
invalidate stq_23_bits_uop_uop.debug_inst
invalidate stq_23_bits_uop_uop.inst
invalidate stq_23_bits_uop_uop.uopc
connect stq_23_bits_uop_uop.uopc, UInt<7>(0h0)
connect stq_23_bits_uop_uop.bypassable, UInt<1>(0h0)
connect stq_23_bits_uop_uop.fp_val, UInt<1>(0h0)
connect stq_23_bits_uop_uop.uses_stq, UInt<1>(0h0)
connect stq_23_bits_uop_uop.uses_ldq, UInt<1>(0h0)
connect stq_23_bits_uop_uop.pdst, UInt<1>(0h0)
connect stq_23_bits_uop_uop.dst_rtype, UInt<2>(0h2)
wire stq_23_bits_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate stq_23_bits_uop_cs.is_std
invalidate stq_23_bits_uop_cs.is_sta
invalidate stq_23_bits_uop_cs.is_load
invalidate stq_23_bits_uop_cs.csr_cmd
invalidate stq_23_bits_uop_cs.fcn_dw
invalidate stq_23_bits_uop_cs.op_fcn
invalidate stq_23_bits_uop_cs.imm_sel
invalidate stq_23_bits_uop_cs.op2_sel
invalidate stq_23_bits_uop_cs.op1_sel
invalidate stq_23_bits_uop_cs.br_type
connect stq_23_bits_uop_cs.br_type, UInt<4>(0h0)
connect stq_23_bits_uop_cs.csr_cmd, UInt<3>(0h0)
connect stq_23_bits_uop_cs.is_load, UInt<1>(0h0)
connect stq_23_bits_uop_cs.is_sta, UInt<1>(0h0)
connect stq_23_bits_uop_cs.is_std, UInt<1>(0h0)
connect stq_23_bits_uop_uop.ctrl, stq_23_bits_uop_cs
connect stq[23].bits.uop, stq_23_bits_uop_uop
else :
connect stq_tail, stq_commit_head
node _T_2090 = eq(stq[0].bits.committed, UInt<1>(0h0))
node _T_2091 = eq(stq[0].bits.succeeded, UInt<1>(0h0))
node _T_2092 = and(_T_2090, _T_2091)
when _T_2092 :
connect stq[0].valid, UInt<1>(0h0)
connect stq[0].bits.addr.valid, UInt<1>(0h0)
connect stq[0].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[0], UInt<1>(0h1)
node _T_2093 = eq(stq[1].bits.committed, UInt<1>(0h0))
node _T_2094 = eq(stq[1].bits.succeeded, UInt<1>(0h0))
node _T_2095 = and(_T_2093, _T_2094)
when _T_2095 :
connect stq[1].valid, UInt<1>(0h0)
connect stq[1].bits.addr.valid, UInt<1>(0h0)
connect stq[1].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[1], UInt<1>(0h1)
node _T_2096 = eq(stq[2].bits.committed, UInt<1>(0h0))
node _T_2097 = eq(stq[2].bits.succeeded, UInt<1>(0h0))
node _T_2098 = and(_T_2096, _T_2097)
when _T_2098 :
connect stq[2].valid, UInt<1>(0h0)
connect stq[2].bits.addr.valid, UInt<1>(0h0)
connect stq[2].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[2], UInt<1>(0h1)
node _T_2099 = eq(stq[3].bits.committed, UInt<1>(0h0))
node _T_2100 = eq(stq[3].bits.succeeded, UInt<1>(0h0))
node _T_2101 = and(_T_2099, _T_2100)
when _T_2101 :
connect stq[3].valid, UInt<1>(0h0)
connect stq[3].bits.addr.valid, UInt<1>(0h0)
connect stq[3].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[3], UInt<1>(0h1)
node _T_2102 = eq(stq[4].bits.committed, UInt<1>(0h0))
node _T_2103 = eq(stq[4].bits.succeeded, UInt<1>(0h0))
node _T_2104 = and(_T_2102, _T_2103)
when _T_2104 :
connect stq[4].valid, UInt<1>(0h0)
connect stq[4].bits.addr.valid, UInt<1>(0h0)
connect stq[4].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[4], UInt<1>(0h1)
node _T_2105 = eq(stq[5].bits.committed, UInt<1>(0h0))
node _T_2106 = eq(stq[5].bits.succeeded, UInt<1>(0h0))
node _T_2107 = and(_T_2105, _T_2106)
when _T_2107 :
connect stq[5].valid, UInt<1>(0h0)
connect stq[5].bits.addr.valid, UInt<1>(0h0)
connect stq[5].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[5], UInt<1>(0h1)
node _T_2108 = eq(stq[6].bits.committed, UInt<1>(0h0))
node _T_2109 = eq(stq[6].bits.succeeded, UInt<1>(0h0))
node _T_2110 = and(_T_2108, _T_2109)
when _T_2110 :
connect stq[6].valid, UInt<1>(0h0)
connect stq[6].bits.addr.valid, UInt<1>(0h0)
connect stq[6].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[6], UInt<1>(0h1)
node _T_2111 = eq(stq[7].bits.committed, UInt<1>(0h0))
node _T_2112 = eq(stq[7].bits.succeeded, UInt<1>(0h0))
node _T_2113 = and(_T_2111, _T_2112)
when _T_2113 :
connect stq[7].valid, UInt<1>(0h0)
connect stq[7].bits.addr.valid, UInt<1>(0h0)
connect stq[7].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[7], UInt<1>(0h1)
node _T_2114 = eq(stq[8].bits.committed, UInt<1>(0h0))
node _T_2115 = eq(stq[8].bits.succeeded, UInt<1>(0h0))
node _T_2116 = and(_T_2114, _T_2115)
when _T_2116 :
connect stq[8].valid, UInt<1>(0h0)
connect stq[8].bits.addr.valid, UInt<1>(0h0)
connect stq[8].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[8], UInt<1>(0h1)
node _T_2117 = eq(stq[9].bits.committed, UInt<1>(0h0))
node _T_2118 = eq(stq[9].bits.succeeded, UInt<1>(0h0))
node _T_2119 = and(_T_2117, _T_2118)
when _T_2119 :
connect stq[9].valid, UInt<1>(0h0)
connect stq[9].bits.addr.valid, UInt<1>(0h0)
connect stq[9].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[9], UInt<1>(0h1)
node _T_2120 = eq(stq[10].bits.committed, UInt<1>(0h0))
node _T_2121 = eq(stq[10].bits.succeeded, UInt<1>(0h0))
node _T_2122 = and(_T_2120, _T_2121)
when _T_2122 :
connect stq[10].valid, UInt<1>(0h0)
connect stq[10].bits.addr.valid, UInt<1>(0h0)
connect stq[10].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[10], UInt<1>(0h1)
node _T_2123 = eq(stq[11].bits.committed, UInt<1>(0h0))
node _T_2124 = eq(stq[11].bits.succeeded, UInt<1>(0h0))
node _T_2125 = and(_T_2123, _T_2124)
when _T_2125 :
connect stq[11].valid, UInt<1>(0h0)
connect stq[11].bits.addr.valid, UInt<1>(0h0)
connect stq[11].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[11], UInt<1>(0h1)
node _T_2126 = eq(stq[12].bits.committed, UInt<1>(0h0))
node _T_2127 = eq(stq[12].bits.succeeded, UInt<1>(0h0))
node _T_2128 = and(_T_2126, _T_2127)
when _T_2128 :
connect stq[12].valid, UInt<1>(0h0)
connect stq[12].bits.addr.valid, UInt<1>(0h0)
connect stq[12].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[12], UInt<1>(0h1)
node _T_2129 = eq(stq[13].bits.committed, UInt<1>(0h0))
node _T_2130 = eq(stq[13].bits.succeeded, UInt<1>(0h0))
node _T_2131 = and(_T_2129, _T_2130)
when _T_2131 :
connect stq[13].valid, UInt<1>(0h0)
connect stq[13].bits.addr.valid, UInt<1>(0h0)
connect stq[13].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[13], UInt<1>(0h1)
node _T_2132 = eq(stq[14].bits.committed, UInt<1>(0h0))
node _T_2133 = eq(stq[14].bits.succeeded, UInt<1>(0h0))
node _T_2134 = and(_T_2132, _T_2133)
when _T_2134 :
connect stq[14].valid, UInt<1>(0h0)
connect stq[14].bits.addr.valid, UInt<1>(0h0)
connect stq[14].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[14], UInt<1>(0h1)
node _T_2135 = eq(stq[15].bits.committed, UInt<1>(0h0))
node _T_2136 = eq(stq[15].bits.succeeded, UInt<1>(0h0))
node _T_2137 = and(_T_2135, _T_2136)
when _T_2137 :
connect stq[15].valid, UInt<1>(0h0)
connect stq[15].bits.addr.valid, UInt<1>(0h0)
connect stq[15].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[15], UInt<1>(0h1)
node _T_2138 = eq(stq[16].bits.committed, UInt<1>(0h0))
node _T_2139 = eq(stq[16].bits.succeeded, UInt<1>(0h0))
node _T_2140 = and(_T_2138, _T_2139)
when _T_2140 :
connect stq[16].valid, UInt<1>(0h0)
connect stq[16].bits.addr.valid, UInt<1>(0h0)
connect stq[16].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[16], UInt<1>(0h1)
node _T_2141 = eq(stq[17].bits.committed, UInt<1>(0h0))
node _T_2142 = eq(stq[17].bits.succeeded, UInt<1>(0h0))
node _T_2143 = and(_T_2141, _T_2142)
when _T_2143 :
connect stq[17].valid, UInt<1>(0h0)
connect stq[17].bits.addr.valid, UInt<1>(0h0)
connect stq[17].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[17], UInt<1>(0h1)
node _T_2144 = eq(stq[18].bits.committed, UInt<1>(0h0))
node _T_2145 = eq(stq[18].bits.succeeded, UInt<1>(0h0))
node _T_2146 = and(_T_2144, _T_2145)
when _T_2146 :
connect stq[18].valid, UInt<1>(0h0)
connect stq[18].bits.addr.valid, UInt<1>(0h0)
connect stq[18].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[18], UInt<1>(0h1)
node _T_2147 = eq(stq[19].bits.committed, UInt<1>(0h0))
node _T_2148 = eq(stq[19].bits.succeeded, UInt<1>(0h0))
node _T_2149 = and(_T_2147, _T_2148)
when _T_2149 :
connect stq[19].valid, UInt<1>(0h0)
connect stq[19].bits.addr.valid, UInt<1>(0h0)
connect stq[19].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[19], UInt<1>(0h1)
node _T_2150 = eq(stq[20].bits.committed, UInt<1>(0h0))
node _T_2151 = eq(stq[20].bits.succeeded, UInt<1>(0h0))
node _T_2152 = and(_T_2150, _T_2151)
when _T_2152 :
connect stq[20].valid, UInt<1>(0h0)
connect stq[20].bits.addr.valid, UInt<1>(0h0)
connect stq[20].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[20], UInt<1>(0h1)
node _T_2153 = eq(stq[21].bits.committed, UInt<1>(0h0))
node _T_2154 = eq(stq[21].bits.succeeded, UInt<1>(0h0))
node _T_2155 = and(_T_2153, _T_2154)
when _T_2155 :
connect stq[21].valid, UInt<1>(0h0)
connect stq[21].bits.addr.valid, UInt<1>(0h0)
connect stq[21].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[21], UInt<1>(0h1)
node _T_2156 = eq(stq[22].bits.committed, UInt<1>(0h0))
node _T_2157 = eq(stq[22].bits.succeeded, UInt<1>(0h0))
node _T_2158 = and(_T_2156, _T_2157)
when _T_2158 :
connect stq[22].valid, UInt<1>(0h0)
connect stq[22].bits.addr.valid, UInt<1>(0h0)
connect stq[22].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[22], UInt<1>(0h1)
node _T_2159 = eq(stq[23].bits.committed, UInt<1>(0h0))
node _T_2160 = eq(stq[23].bits.succeeded, UInt<1>(0h0))
node _T_2161 = and(_T_2159, _T_2160)
when _T_2161 :
connect stq[23].valid, UInt<1>(0h0)
connect stq[23].bits.addr.valid, UInt<1>(0h0)
connect stq[23].bits.data.valid, UInt<1>(0h0)
connect st_exc_killed_mask[23], UInt<1>(0h1)
connect ldq[0].valid, UInt<1>(0h0)
connect ldq[0].bits.addr.valid, UInt<1>(0h0)
connect ldq[0].bits.executed, UInt<1>(0h0)
connect ldq[1].valid, UInt<1>(0h0)
connect ldq[1].bits.addr.valid, UInt<1>(0h0)
connect ldq[1].bits.executed, UInt<1>(0h0)
connect ldq[2].valid, UInt<1>(0h0)
connect ldq[2].bits.addr.valid, UInt<1>(0h0)
connect ldq[2].bits.executed, UInt<1>(0h0)
connect ldq[3].valid, UInt<1>(0h0)
connect ldq[3].bits.addr.valid, UInt<1>(0h0)
connect ldq[3].bits.executed, UInt<1>(0h0)
connect ldq[4].valid, UInt<1>(0h0)
connect ldq[4].bits.addr.valid, UInt<1>(0h0)
connect ldq[4].bits.executed, UInt<1>(0h0)
connect ldq[5].valid, UInt<1>(0h0)
connect ldq[5].bits.addr.valid, UInt<1>(0h0)
connect ldq[5].bits.executed, UInt<1>(0h0)
connect ldq[6].valid, UInt<1>(0h0)
connect ldq[6].bits.addr.valid, UInt<1>(0h0)
connect ldq[6].bits.executed, UInt<1>(0h0)
connect ldq[7].valid, UInt<1>(0h0)
connect ldq[7].bits.addr.valid, UInt<1>(0h0)
connect ldq[7].bits.executed, UInt<1>(0h0)
connect ldq[8].valid, UInt<1>(0h0)
connect ldq[8].bits.addr.valid, UInt<1>(0h0)
connect ldq[8].bits.executed, UInt<1>(0h0)
connect ldq[9].valid, UInt<1>(0h0)
connect ldq[9].bits.addr.valid, UInt<1>(0h0)
connect ldq[9].bits.executed, UInt<1>(0h0)
connect ldq[10].valid, UInt<1>(0h0)
connect ldq[10].bits.addr.valid, UInt<1>(0h0)
connect ldq[10].bits.executed, UInt<1>(0h0)
connect ldq[11].valid, UInt<1>(0h0)
connect ldq[11].bits.addr.valid, UInt<1>(0h0)
connect ldq[11].bits.executed, UInt<1>(0h0)
connect ldq[12].valid, UInt<1>(0h0)
connect ldq[12].bits.addr.valid, UInt<1>(0h0)
connect ldq[12].bits.executed, UInt<1>(0h0)
connect ldq[13].valid, UInt<1>(0h0)
connect ldq[13].bits.addr.valid, UInt<1>(0h0)
connect ldq[13].bits.executed, UInt<1>(0h0)
connect ldq[14].valid, UInt<1>(0h0)
connect ldq[14].bits.addr.valid, UInt<1>(0h0)
connect ldq[14].bits.executed, UInt<1>(0h0)
connect ldq[15].valid, UInt<1>(0h0)
connect ldq[15].bits.addr.valid, UInt<1>(0h0)
connect ldq[15].bits.executed, UInt<1>(0h0)
connect ldq[16].valid, UInt<1>(0h0)
connect ldq[16].bits.addr.valid, UInt<1>(0h0)
connect ldq[16].bits.executed, UInt<1>(0h0)
connect ldq[17].valid, UInt<1>(0h0)
connect ldq[17].bits.addr.valid, UInt<1>(0h0)
connect ldq[17].bits.executed, UInt<1>(0h0)
connect ldq[18].valid, UInt<1>(0h0)
connect ldq[18].bits.addr.valid, UInt<1>(0h0)
connect ldq[18].bits.executed, UInt<1>(0h0)
connect ldq[19].valid, UInt<1>(0h0)
connect ldq[19].bits.addr.valid, UInt<1>(0h0)
connect ldq[19].bits.executed, UInt<1>(0h0)
connect ldq[20].valid, UInt<1>(0h0)
connect ldq[20].bits.addr.valid, UInt<1>(0h0)
connect ldq[20].bits.executed, UInt<1>(0h0)
connect ldq[21].valid, UInt<1>(0h0)
connect ldq[21].bits.addr.valid, UInt<1>(0h0)
connect ldq[21].bits.executed, UInt<1>(0h0)
connect ldq[22].valid, UInt<1>(0h0)
connect ldq[22].bits.addr.valid, UInt<1>(0h0)
connect ldq[22].bits.executed, UInt<1>(0h0)
connect ldq[23].valid, UInt<1>(0h0)
connect ldq[23].bits.addr.valid, UInt<1>(0h0)
connect ldq[23].bits.executed, UInt<1>(0h0)
node live_store_mask_lo_lo_lo_hi = cat(st_brkilled_mask[2], st_brkilled_mask[1])
node live_store_mask_lo_lo_lo = cat(live_store_mask_lo_lo_lo_hi, st_brkilled_mask[0])
node live_store_mask_lo_lo_hi_hi = cat(st_brkilled_mask[5], st_brkilled_mask[4])
node live_store_mask_lo_lo_hi = cat(live_store_mask_lo_lo_hi_hi, st_brkilled_mask[3])
node live_store_mask_lo_lo = cat(live_store_mask_lo_lo_hi, live_store_mask_lo_lo_lo)
node live_store_mask_lo_hi_lo_hi = cat(st_brkilled_mask[8], st_brkilled_mask[7])
node live_store_mask_lo_hi_lo = cat(live_store_mask_lo_hi_lo_hi, st_brkilled_mask[6])
node live_store_mask_lo_hi_hi_hi = cat(st_brkilled_mask[11], st_brkilled_mask[10])
node live_store_mask_lo_hi_hi = cat(live_store_mask_lo_hi_hi_hi, st_brkilled_mask[9])
node live_store_mask_lo_hi = cat(live_store_mask_lo_hi_hi, live_store_mask_lo_hi_lo)
node live_store_mask_lo = cat(live_store_mask_lo_hi, live_store_mask_lo_lo)
node live_store_mask_hi_lo_lo_hi = cat(st_brkilled_mask[14], st_brkilled_mask[13])
node live_store_mask_hi_lo_lo = cat(live_store_mask_hi_lo_lo_hi, st_brkilled_mask[12])
node live_store_mask_hi_lo_hi_hi = cat(st_brkilled_mask[17], st_brkilled_mask[16])
node live_store_mask_hi_lo_hi = cat(live_store_mask_hi_lo_hi_hi, st_brkilled_mask[15])
node live_store_mask_hi_lo = cat(live_store_mask_hi_lo_hi, live_store_mask_hi_lo_lo)
node live_store_mask_hi_hi_lo_hi = cat(st_brkilled_mask[20], st_brkilled_mask[19])
node live_store_mask_hi_hi_lo = cat(live_store_mask_hi_hi_lo_hi, st_brkilled_mask[18])
node live_store_mask_hi_hi_hi_hi = cat(st_brkilled_mask[23], st_brkilled_mask[22])
node live_store_mask_hi_hi_hi = cat(live_store_mask_hi_hi_hi_hi, st_brkilled_mask[21])
node live_store_mask_hi_hi = cat(live_store_mask_hi_hi_hi, live_store_mask_hi_hi_lo)
node live_store_mask_hi = cat(live_store_mask_hi_hi, live_store_mask_hi_lo)
node _live_store_mask_T = cat(live_store_mask_hi, live_store_mask_lo)
node _live_store_mask_T_1 = not(_live_store_mask_T)
node _live_store_mask_T_2 = and(_T_118, _live_store_mask_T_1)
node live_store_mask_lo_lo_lo_hi_1 = cat(st_exc_killed_mask[2], st_exc_killed_mask[1])
node live_store_mask_lo_lo_lo_1 = cat(live_store_mask_lo_lo_lo_hi_1, st_exc_killed_mask[0])
node live_store_mask_lo_lo_hi_hi_1 = cat(st_exc_killed_mask[5], st_exc_killed_mask[4])
node live_store_mask_lo_lo_hi_1 = cat(live_store_mask_lo_lo_hi_hi_1, st_exc_killed_mask[3])
node live_store_mask_lo_lo_1 = cat(live_store_mask_lo_lo_hi_1, live_store_mask_lo_lo_lo_1)
node live_store_mask_lo_hi_lo_hi_1 = cat(st_exc_killed_mask[8], st_exc_killed_mask[7])
node live_store_mask_lo_hi_lo_1 = cat(live_store_mask_lo_hi_lo_hi_1, st_exc_killed_mask[6])
node live_store_mask_lo_hi_hi_hi_1 = cat(st_exc_killed_mask[11], st_exc_killed_mask[10])
node live_store_mask_lo_hi_hi_1 = cat(live_store_mask_lo_hi_hi_hi_1, st_exc_killed_mask[9])
node live_store_mask_lo_hi_1 = cat(live_store_mask_lo_hi_hi_1, live_store_mask_lo_hi_lo_1)
node live_store_mask_lo_1 = cat(live_store_mask_lo_hi_1, live_store_mask_lo_lo_1)
node live_store_mask_hi_lo_lo_hi_1 = cat(st_exc_killed_mask[14], st_exc_killed_mask[13])
node live_store_mask_hi_lo_lo_1 = cat(live_store_mask_hi_lo_lo_hi_1, st_exc_killed_mask[12])
node live_store_mask_hi_lo_hi_hi_1 = cat(st_exc_killed_mask[17], st_exc_killed_mask[16])
node live_store_mask_hi_lo_hi_1 = cat(live_store_mask_hi_lo_hi_hi_1, st_exc_killed_mask[15])
node live_store_mask_hi_lo_1 = cat(live_store_mask_hi_lo_hi_1, live_store_mask_hi_lo_lo_1)
node live_store_mask_hi_hi_lo_hi_1 = cat(st_exc_killed_mask[20], st_exc_killed_mask[19])
node live_store_mask_hi_hi_lo_1 = cat(live_store_mask_hi_hi_lo_hi_1, st_exc_killed_mask[18])
node live_store_mask_hi_hi_hi_hi_1 = cat(st_exc_killed_mask[23], st_exc_killed_mask[22])
node live_store_mask_hi_hi_hi_1 = cat(live_store_mask_hi_hi_hi_hi_1, st_exc_killed_mask[21])
node live_store_mask_hi_hi_1 = cat(live_store_mask_hi_hi_hi_1, live_store_mask_hi_hi_lo_1)
node live_store_mask_hi_1 = cat(live_store_mask_hi_hi_1, live_store_mask_hi_lo_1)
node _live_store_mask_T_3 = cat(live_store_mask_hi_1, live_store_mask_lo_1)
node _live_store_mask_T_4 = not(_live_store_mask_T_3)
node _live_store_mask_T_5 = and(_live_store_mask_T_2, _live_store_mask_T_4)
connect live_store_mask, _live_store_mask_T_5 | module LSU( // @[lsu.scala:201:7]
input clock, // @[lsu.scala:201:7]
input reset, // @[lsu.scala:201:7]
input io_ptw_req_ready, // @[lsu.scala:204:14]
output io_ptw_req_valid, // @[lsu.scala:204:14]
output io_ptw_req_bits_valid, // @[lsu.scala:204:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:204:14]
input io_ptw_resp_valid, // @[lsu.scala:204:14]
input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:204:14]
input io_ptw_resp_bits_ae_final, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pf, // @[lsu.scala:204:14]
input io_ptw_resp_bits_gf, // @[lsu.scala:204:14]
input io_ptw_resp_bits_hr, // @[lsu.scala:204:14]
input io_ptw_resp_bits_hw, // @[lsu.scala:204:14]
input io_ptw_resp_bits_hx, // @[lsu.scala:204:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:204:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:204:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_d, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_a, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_g, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_u, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_x, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_w, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_r, // @[lsu.scala:204:14]
input io_ptw_resp_bits_pte_v, // @[lsu.scala:204:14]
input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:204:14]
input io_ptw_resp_bits_homogeneous, // @[lsu.scala:204:14]
input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:204:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:204:14]
input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:204:14]
input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:204:14]
input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:204:14]
input io_ptw_status_debug, // @[lsu.scala:204:14]
input io_ptw_status_cease, // @[lsu.scala:204:14]
input io_ptw_status_wfi, // @[lsu.scala:204:14]
input [1:0] io_ptw_status_dprv, // @[lsu.scala:204:14]
input io_ptw_status_dv, // @[lsu.scala:204:14]
input [1:0] io_ptw_status_prv, // @[lsu.scala:204:14]
input io_ptw_status_v, // @[lsu.scala:204:14]
input io_ptw_status_sd, // @[lsu.scala:204:14]
input io_ptw_status_mpv, // @[lsu.scala:204:14]
input io_ptw_status_gva, // @[lsu.scala:204:14]
input io_ptw_status_tsr, // @[lsu.scala:204:14]
input io_ptw_status_tw, // @[lsu.scala:204:14]
input io_ptw_status_tvm, // @[lsu.scala:204:14]
input io_ptw_status_mxr, // @[lsu.scala:204:14]
input io_ptw_status_sum, // @[lsu.scala:204:14]
input io_ptw_status_mprv, // @[lsu.scala:204:14]
input [1:0] io_ptw_status_fs, // @[lsu.scala:204:14]
input [1:0] io_ptw_status_mpp, // @[lsu.scala:204:14]
input io_ptw_status_spp, // @[lsu.scala:204:14]
input io_ptw_status_mpie, // @[lsu.scala:204:14]
input io_ptw_status_spie, // @[lsu.scala:204:14]
input io_ptw_status_mie, // @[lsu.scala:204:14]
input io_ptw_status_sie, // @[lsu.scala:204:14]
input io_ptw_pmp_0_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_0_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_0_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_0_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:204:14]
input io_ptw_pmp_1_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_1_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_1_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_1_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:204:14]
input io_ptw_pmp_2_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_2_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_2_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_2_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:204:14]
input io_ptw_pmp_3_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_3_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_3_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_3_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:204:14]
input io_ptw_pmp_4_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_4_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_4_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_4_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:204:14]
input io_ptw_pmp_5_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_5_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_5_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_5_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:204:14]
input io_ptw_pmp_6_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_6_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_6_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_6_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:204:14]
input io_ptw_pmp_7_cfg_l, // @[lsu.scala:204:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:204:14]
input io_ptw_pmp_7_cfg_x, // @[lsu.scala:204:14]
input io_ptw_pmp_7_cfg_w, // @[lsu.scala:204:14]
input io_ptw_pmp_7_cfg_r, // @[lsu.scala:204:14]
input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:204:14]
input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:204:14]
input io_core_exe_0_req_valid, // @[lsu.scala:204:14]
input [6:0] io_core_exe_0_req_bits_uop_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_exe_0_req_bits_uop_inst, // @[lsu.scala:204:14]
input [31:0] io_core_exe_0_req_bits_uop_debug_inst, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_exe_0_req_bits_uop_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_exe_0_req_bits_uop_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_exe_0_req_bits_uop_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_iw_state, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_br, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_jalr, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_jal, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_exe_0_req_bits_uop_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_exe_0_req_bits_uop_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_exe_0_req_bits_uop_ftq_idx, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_exe_0_req_bits_uop_pc_lob, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_taken, // @[lsu.scala:204:14]
input [19:0] io_core_exe_0_req_bits_uop_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_exe_0_req_bits_uop_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_exe_0_req_bits_uop_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_exe_0_req_bits_uop_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_exe_0_req_bits_uop_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_exe_0_req_bits_uop_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_exe_0_req_bits_uop_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_exe_0_req_bits_uop_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_exe_0_req_bits_uop_prs3, // @[lsu.scala:204:14]
input [4:0] io_core_exe_0_req_bits_uop_ppred, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_prs1_busy, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_prs2_busy, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_prs3_busy, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_core_exe_0_req_bits_uop_stale_pdst, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_exception, // @[lsu.scala:204:14]
input [63:0] io_core_exe_0_req_bits_uop_exc_cause, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_exe_0_req_bits_uop_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_mem_size, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_mem_signed, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_fence, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_fencei, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_amo, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_uses_ldq, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_uses_stq, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_is_unique, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_exe_0_req_bits_uop_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_exe_0_req_bits_uop_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_exe_0_req_bits_uop_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_exe_0_req_bits_uop_lrs3, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_frs3_en, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_fp_val, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_fp_single, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_exe_0_req_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
input [63:0] io_core_exe_0_req_bits_data, // @[lsu.scala:204:14]
input [39:0] io_core_exe_0_req_bits_addr, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_mxcpt_valid, // @[lsu.scala:204:14]
input [24:0] io_core_exe_0_req_bits_mxcpt_bits, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_sfence_valid, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_sfence_bits_rs1, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_sfence_bits_rs2, // @[lsu.scala:204:14]
input [38:0] io_core_exe_0_req_bits_sfence_bits_addr, // @[lsu.scala:204:14]
input io_core_exe_0_req_bits_sfence_bits_asid, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_valid, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_iresp_bits_uop_uopc, // @[lsu.scala:204:14]
output [31:0] io_core_exe_0_iresp_bits_uop_inst, // @[lsu.scala:204:14]
output [31:0] io_core_exe_0_iresp_bits_uop_debug_inst, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_rvc, // @[lsu.scala:204:14]
output [39:0] io_core_exe_0_iresp_bits_uop_debug_pc, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_iresp_bits_uop_iq_type, // @[lsu.scala:204:14]
output [9:0] io_core_exe_0_iresp_bits_uop_fu_code, // @[lsu.scala:204:14]
output [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_iw_state, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_br, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_jalr, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_jal, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_sfb, // @[lsu.scala:204:14]
output [15:0] io_core_exe_0_iresp_bits_uop_br_mask, // @[lsu.scala:204:14]
output [3:0] io_core_exe_0_iresp_bits_uop_br_tag, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_iresp_bits_uop_ftq_idx, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_edge_inst, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_iresp_bits_uop_pc_lob, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_taken, // @[lsu.scala:204:14]
output [19:0] io_core_exe_0_iresp_bits_uop_imm_packed, // @[lsu.scala:204:14]
output [11:0] io_core_exe_0_iresp_bits_uop_csr_addr, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_iresp_bits_uop_rob_idx, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_iresp_bits_uop_ldq_idx, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_iresp_bits_uop_stq_idx, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_iresp_bits_uop_pdst, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_iresp_bits_uop_prs1, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_iresp_bits_uop_prs2, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_iresp_bits_uop_prs3, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_iresp_bits_uop_ppred, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_prs1_busy, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_prs2_busy, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_prs3_busy, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_ppred_busy, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_iresp_bits_uop_stale_pdst, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_exception, // @[lsu.scala:204:14]
output [63:0] io_core_exe_0_iresp_bits_uop_exc_cause, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_bypassable, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_mem_size, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_mem_signed, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_fence, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_fencei, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_amo, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_uses_ldq, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_uses_stq, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_is_unique, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_iresp_bits_uop_ldst, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_iresp_bits_uop_lrs1, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_iresp_bits_uop_lrs2, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_iresp_bits_uop_lrs3, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_ldst_val, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_frs3_en, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_fp_val, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_fp_single, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
output io_core_exe_0_iresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
output [63:0] io_core_exe_0_iresp_bits_data, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_valid, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_fresp_bits_uop_uopc, // @[lsu.scala:204:14]
output [31:0] io_core_exe_0_fresp_bits_uop_inst, // @[lsu.scala:204:14]
output [31:0] io_core_exe_0_fresp_bits_uop_debug_inst, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_rvc, // @[lsu.scala:204:14]
output [39:0] io_core_exe_0_fresp_bits_uop_debug_pc, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_fresp_bits_uop_iq_type, // @[lsu.scala:204:14]
output [9:0] io_core_exe_0_fresp_bits_uop_fu_code, // @[lsu.scala:204:14]
output [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_iw_state, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_br, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_jalr, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_jal, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_sfb, // @[lsu.scala:204:14]
output [15:0] io_core_exe_0_fresp_bits_uop_br_mask, // @[lsu.scala:204:14]
output [3:0] io_core_exe_0_fresp_bits_uop_br_tag, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_fresp_bits_uop_ftq_idx, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_edge_inst, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_fresp_bits_uop_pc_lob, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_taken, // @[lsu.scala:204:14]
output [19:0] io_core_exe_0_fresp_bits_uop_imm_packed, // @[lsu.scala:204:14]
output [11:0] io_core_exe_0_fresp_bits_uop_csr_addr, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_fresp_bits_uop_rob_idx, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_fresp_bits_uop_ldq_idx, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_fresp_bits_uop_stq_idx, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_fresp_bits_uop_pdst, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_fresp_bits_uop_prs1, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_fresp_bits_uop_prs2, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_fresp_bits_uop_prs3, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_fresp_bits_uop_ppred, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_prs1_busy, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_prs2_busy, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_prs3_busy, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_ppred_busy, // @[lsu.scala:204:14]
output [6:0] io_core_exe_0_fresp_bits_uop_stale_pdst, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_exception, // @[lsu.scala:204:14]
output [63:0] io_core_exe_0_fresp_bits_uop_exc_cause, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_bypassable, // @[lsu.scala:204:14]
output [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_mem_size, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_mem_signed, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_fence, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_fencei, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_amo, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_uses_ldq, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_uses_stq, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_is_unique, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_fresp_bits_uop_ldst, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_fresp_bits_uop_lrs1, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_fresp_bits_uop_lrs2, // @[lsu.scala:204:14]
output [5:0] io_core_exe_0_fresp_bits_uop_lrs3, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_ldst_val, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_frs3_en, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_fp_val, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_fp_single, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
output io_core_exe_0_fresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
output [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
output [64:0] io_core_exe_0_fresp_bits_data, // @[lsu.scala:204:14]
input io_core_dis_uops_0_valid, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_0_bits_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:204:14]
input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_0_bits_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_dis_uops_0_bits_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_dis_uops_0_bits_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_iw_state, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_br, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_jalr, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_jal, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_taken, // @[lsu.scala:204:14]
input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_dis_uops_0_bits_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_exception, // @[lsu.scala:204:14]
input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_fp_single, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:204:14]
input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:204:14]
input io_core_dis_uops_1_valid, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_1_bits_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_dis_uops_1_bits_inst, // @[lsu.scala:204:14]
input [31:0] io_core_dis_uops_1_bits_debug_inst, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_dis_uops_1_bits_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_1_bits_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_dis_uops_1_bits_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_dis_uops_1_bits_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_1_bits_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_1_bits_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_1_bits_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_1_bits_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_iw_state, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_br, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_jalr, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_jal, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_dis_uops_1_bits_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_dis_uops_1_bits_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_1_bits_ftq_idx, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_1_bits_pc_lob, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_taken, // @[lsu.scala:204:14]
input [19:0] io_core_dis_uops_1_bits_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_dis_uops_1_bits_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_1_bits_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_1_bits_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_1_bits_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_1_bits_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_1_bits_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_1_bits_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_1_bits_prs3, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_prs1_busy, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_prs2_busy, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_prs3_busy, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_1_bits_stale_pdst, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_exception, // @[lsu.scala:204:14]
input [63:0] io_core_dis_uops_1_bits_exc_cause, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_1_bits_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_mem_size, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_mem_signed, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_fence, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_fencei, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_amo, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_uses_ldq, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_uses_stq, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_is_unique, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_flush_on_commit, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_1_bits_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_1_bits_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_1_bits_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_1_bits_lrs3, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_frs3_en, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_fp_val, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_fp_single, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_bp_debug_if, // @[lsu.scala:204:14]
input io_core_dis_uops_1_bits_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_1_bits_debug_tsrc, // @[lsu.scala:204:14]
input io_core_dis_uops_2_valid, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_2_bits_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_dis_uops_2_bits_inst, // @[lsu.scala:204:14]
input [31:0] io_core_dis_uops_2_bits_debug_inst, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_dis_uops_2_bits_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_2_bits_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_dis_uops_2_bits_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_dis_uops_2_bits_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_2_bits_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_2_bits_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_2_bits_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_dis_uops_2_bits_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_iw_state, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_br, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_jalr, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_jal, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_dis_uops_2_bits_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_dis_uops_2_bits_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_2_bits_ftq_idx, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_2_bits_pc_lob, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_taken, // @[lsu.scala:204:14]
input [19:0] io_core_dis_uops_2_bits_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_dis_uops_2_bits_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_2_bits_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_2_bits_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_2_bits_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_2_bits_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_2_bits_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_2_bits_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_2_bits_prs3, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_prs1_busy, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_prs2_busy, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_prs3_busy, // @[lsu.scala:204:14]
input [6:0] io_core_dis_uops_2_bits_stale_pdst, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_exception, // @[lsu.scala:204:14]
input [63:0] io_core_dis_uops_2_bits_exc_cause, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_dis_uops_2_bits_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_mem_size, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_mem_signed, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_fence, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_fencei, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_amo, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_uses_ldq, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_uses_stq, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_is_unique, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_flush_on_commit, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_2_bits_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_2_bits_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_2_bits_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_dis_uops_2_bits_lrs3, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_frs3_en, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_fp_val, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_fp_single, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_bp_debug_if, // @[lsu.scala:204:14]
input io_core_dis_uops_2_bits_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_dis_uops_2_bits_debug_tsrc, // @[lsu.scala:204:14]
output [4:0] io_core_dis_ldq_idx_0, // @[lsu.scala:204:14]
output [4:0] io_core_dis_ldq_idx_1, // @[lsu.scala:204:14]
output [4:0] io_core_dis_ldq_idx_2, // @[lsu.scala:204:14]
output [4:0] io_core_dis_stq_idx_0, // @[lsu.scala:204:14]
output [4:0] io_core_dis_stq_idx_1, // @[lsu.scala:204:14]
output [4:0] io_core_dis_stq_idx_2, // @[lsu.scala:204:14]
output io_core_ldq_full_0, // @[lsu.scala:204:14]
output io_core_ldq_full_1, // @[lsu.scala:204:14]
output io_core_ldq_full_2, // @[lsu.scala:204:14]
output io_core_stq_full_0, // @[lsu.scala:204:14]
output io_core_stq_full_1, // @[lsu.scala:204:14]
output io_core_stq_full_2, // @[lsu.scala:204:14]
output io_core_fp_stdata_ready, // @[lsu.scala:204:14]
input io_core_fp_stdata_valid, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_uop_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_fp_stdata_bits_uop_inst, // @[lsu.scala:204:14]
input [31:0] io_core_fp_stdata_bits_uop_debug_inst, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_fp_stdata_bits_uop_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_uop_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_fp_stdata_bits_uop_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_iw_state, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_br, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_jalr, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_jal, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_fp_stdata_bits_uop_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_fp_stdata_bits_uop_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_uop_ftq_idx, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_uop_pc_lob, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_taken, // @[lsu.scala:204:14]
input [19:0] io_core_fp_stdata_bits_uop_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_fp_stdata_bits_uop_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_uop_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_uop_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_uop_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_uop_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_uop_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_uop_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_uop_prs3, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_uop_ppred, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_prs1_busy, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_prs2_busy, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_prs3_busy, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_uop_stale_pdst, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_exception, // @[lsu.scala:204:14]
input [63:0] io_core_fp_stdata_bits_uop_exc_cause, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_uop_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_mem_size, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_mem_signed, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_fence, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_fencei, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_amo, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_uses_ldq, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_uses_stq, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_is_unique, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_uop_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_uop_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_uop_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_uop_lrs3, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_frs3_en, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_fp_val, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_fp_single, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
input [63:0] io_core_fp_stdata_bits_data, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_predicated, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_valid, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst, // @[lsu.scala:204:14]
input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_br, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_jal, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_taken, // @[lsu.scala:204:14]
input [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_exception, // @[lsu.scala:204:14]
input [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_fence, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_amo, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_is_unique, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_fp_val, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_fp_single, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
input io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
input [4:0] io_core_fp_stdata_bits_fflags_bits_flags, // @[lsu.scala:204:14]
input io_core_commit_valids_0, // @[lsu.scala:204:14]
input io_core_commit_valids_1, // @[lsu.scala:204:14]
input io_core_commit_valids_2, // @[lsu.scala:204:14]
input io_core_commit_arch_valids_0, // @[lsu.scala:204:14]
input io_core_commit_arch_valids_1, // @[lsu.scala:204:14]
input io_core_commit_arch_valids_2, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_0_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:204:14]
input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_0_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_commit_uops_0_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_commit_uops_0_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_0_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_0_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_0_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_commit_uops_0_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_0_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_commit_uops_0_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_commit_uops_0_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_commit_uops_0_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_iw_state, // @[lsu.scala:204:14]
input io_core_commit_uops_0_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_commit_uops_0_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_br, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_jalr, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_jal, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:204:14]
input io_core_commit_uops_0_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:204:14]
input io_core_commit_uops_0_taken, // @[lsu.scala:204:14]
input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_commit_uops_0_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_0_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_0_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_0_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_0_prs3, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_0_ppred, // @[lsu.scala:204:14]
input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:204:14]
input io_core_commit_uops_0_exception, // @[lsu.scala:204:14]
input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:204:14]
input io_core_commit_uops_0_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:204:14]
input io_core_commit_uops_0_mem_signed, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_fence, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_fencei, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_amo, // @[lsu.scala:204:14]
input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:204:14]
input io_core_commit_uops_0_uses_stq, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_commit_uops_0_is_unique, // @[lsu.scala:204:14]
input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:204:14]
input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:204:14]
input io_core_commit_uops_0_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_commit_uops_0_frs3_en, // @[lsu.scala:204:14]
input io_core_commit_uops_0_fp_val, // @[lsu.scala:204:14]
input io_core_commit_uops_0_fp_single, // @[lsu.scala:204:14]
input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:204:14]
input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_1_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_commit_uops_1_inst, // @[lsu.scala:204:14]
input [31:0] io_core_commit_uops_1_debug_inst, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_commit_uops_1_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_1_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_commit_uops_1_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_commit_uops_1_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_1_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_1_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_1_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_commit_uops_1_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_1_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_commit_uops_1_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_commit_uops_1_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_commit_uops_1_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_iw_state, // @[lsu.scala:204:14]
input io_core_commit_uops_1_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_commit_uops_1_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_br, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_jalr, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_jal, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_commit_uops_1_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_commit_uops_1_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_1_ftq_idx, // @[lsu.scala:204:14]
input io_core_commit_uops_1_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_1_pc_lob, // @[lsu.scala:204:14]
input io_core_commit_uops_1_taken, // @[lsu.scala:204:14]
input [19:0] io_core_commit_uops_1_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_commit_uops_1_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_1_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_1_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_1_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_1_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_1_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_1_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_1_prs3, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_1_ppred, // @[lsu.scala:204:14]
input io_core_commit_uops_1_prs1_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_1_prs2_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_1_prs3_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_1_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_1_stale_pdst, // @[lsu.scala:204:14]
input io_core_commit_uops_1_exception, // @[lsu.scala:204:14]
input [63:0] io_core_commit_uops_1_exc_cause, // @[lsu.scala:204:14]
input io_core_commit_uops_1_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_1_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_mem_size, // @[lsu.scala:204:14]
input io_core_commit_uops_1_mem_signed, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_fence, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_fencei, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_amo, // @[lsu.scala:204:14]
input io_core_commit_uops_1_uses_ldq, // @[lsu.scala:204:14]
input io_core_commit_uops_1_uses_stq, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_commit_uops_1_is_unique, // @[lsu.scala:204:14]
input io_core_commit_uops_1_flush_on_commit, // @[lsu.scala:204:14]
input io_core_commit_uops_1_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_1_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_1_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_1_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_1_lrs3, // @[lsu.scala:204:14]
input io_core_commit_uops_1_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_commit_uops_1_frs3_en, // @[lsu.scala:204:14]
input io_core_commit_uops_1_fp_val, // @[lsu.scala:204:14]
input io_core_commit_uops_1_fp_single, // @[lsu.scala:204:14]
input io_core_commit_uops_1_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_commit_uops_1_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_commit_uops_1_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_commit_uops_1_bp_debug_if, // @[lsu.scala:204:14]
input io_core_commit_uops_1_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_1_debug_tsrc, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_2_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_commit_uops_2_inst, // @[lsu.scala:204:14]
input [31:0] io_core_commit_uops_2_debug_inst, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_commit_uops_2_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_2_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_commit_uops_2_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_commit_uops_2_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_2_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_2_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_2_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_commit_uops_2_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_commit_uops_2_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_commit_uops_2_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_commit_uops_2_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_commit_uops_2_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_iw_state, // @[lsu.scala:204:14]
input io_core_commit_uops_2_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_commit_uops_2_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_br, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_jalr, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_jal, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_commit_uops_2_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_commit_uops_2_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_2_ftq_idx, // @[lsu.scala:204:14]
input io_core_commit_uops_2_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_2_pc_lob, // @[lsu.scala:204:14]
input io_core_commit_uops_2_taken, // @[lsu.scala:204:14]
input [19:0] io_core_commit_uops_2_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_commit_uops_2_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_2_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_2_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_2_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_2_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_2_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_2_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_2_prs3, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_2_ppred, // @[lsu.scala:204:14]
input io_core_commit_uops_2_prs1_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_2_prs2_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_2_prs3_busy, // @[lsu.scala:204:14]
input io_core_commit_uops_2_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_core_commit_uops_2_stale_pdst, // @[lsu.scala:204:14]
input io_core_commit_uops_2_exception, // @[lsu.scala:204:14]
input [63:0] io_core_commit_uops_2_exc_cause, // @[lsu.scala:204:14]
input io_core_commit_uops_2_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_commit_uops_2_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_mem_size, // @[lsu.scala:204:14]
input io_core_commit_uops_2_mem_signed, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_fence, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_fencei, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_amo, // @[lsu.scala:204:14]
input io_core_commit_uops_2_uses_ldq, // @[lsu.scala:204:14]
input io_core_commit_uops_2_uses_stq, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_commit_uops_2_is_unique, // @[lsu.scala:204:14]
input io_core_commit_uops_2_flush_on_commit, // @[lsu.scala:204:14]
input io_core_commit_uops_2_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_2_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_2_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_2_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_commit_uops_2_lrs3, // @[lsu.scala:204:14]
input io_core_commit_uops_2_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_commit_uops_2_frs3_en, // @[lsu.scala:204:14]
input io_core_commit_uops_2_fp_val, // @[lsu.scala:204:14]
input io_core_commit_uops_2_fp_single, // @[lsu.scala:204:14]
input io_core_commit_uops_2_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_commit_uops_2_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_commit_uops_2_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_commit_uops_2_bp_debug_if, // @[lsu.scala:204:14]
input io_core_commit_uops_2_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_commit_uops_2_debug_tsrc, // @[lsu.scala:204:14]
input io_core_commit_fflags_valid, // @[lsu.scala:204:14]
input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:204:14]
input [31:0] io_core_commit_debug_insts_0, // @[lsu.scala:204:14]
input [31:0] io_core_commit_debug_insts_1, // @[lsu.scala:204:14]
input [31:0] io_core_commit_debug_insts_2, // @[lsu.scala:204:14]
input io_core_commit_rbk_valids_0, // @[lsu.scala:204:14]
input io_core_commit_rbk_valids_1, // @[lsu.scala:204:14]
input io_core_commit_rbk_valids_2, // @[lsu.scala:204:14]
input io_core_commit_rollback, // @[lsu.scala:204:14]
input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:204:14]
input [63:0] io_core_commit_debug_wdata_1, // @[lsu.scala:204:14]
input [63:0] io_core_commit_debug_wdata_2, // @[lsu.scala:204:14]
input io_core_commit_load_at_rob_head, // @[lsu.scala:204:14]
output io_core_clr_bsy_0_valid, // @[lsu.scala:204:14]
output [6:0] io_core_clr_bsy_0_bits, // @[lsu.scala:204:14]
output io_core_clr_bsy_1_valid, // @[lsu.scala:204:14]
output [6:0] io_core_clr_bsy_1_bits, // @[lsu.scala:204:14]
output [6:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:204:14]
input io_core_fence_dmem, // @[lsu.scala:204:14]
output io_core_spec_ld_wakeup_0_valid, // @[lsu.scala:204:14]
output [6:0] io_core_spec_ld_wakeup_0_bits, // @[lsu.scala:204:14]
output io_core_ld_miss, // @[lsu.scala:204:14]
input [15:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:204:14]
input [15:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14]
input [6:0] io_core_brupdate_b2_uop_uopc, // @[lsu.scala:204:14]
input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:204:14]
input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_core_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14]
input [9:0] io_core_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14]
input [3:0] io_core_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_br, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14]
input [3:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14]
input [4:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_taken, // @[lsu.scala:204:14]
input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_core_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:204:14]
input [6:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:204:14]
input [6:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:204:14]
input [6:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:204:14]
input [4:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_exception, // @[lsu.scala:204:14]
input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14]
input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:204:14]
input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14]
input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14]
input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14]
input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14]
input io_core_brupdate_b2_valid, // @[lsu.scala:204:14]
input io_core_brupdate_b2_mispredict, // @[lsu.scala:204:14]
input io_core_brupdate_b2_taken, // @[lsu.scala:204:14]
input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:204:14]
input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:204:14]
input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:204:14]
input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:204:14]
input [6:0] io_core_rob_pnr_idx, // @[lsu.scala:204:14]
input [6:0] io_core_rob_head_idx, // @[lsu.scala:204:14]
input io_core_exception, // @[lsu.scala:204:14]
output io_core_fencei_rdy, // @[lsu.scala:204:14]
output io_core_lxcpt_valid, // @[lsu.scala:204:14]
output [6:0] io_core_lxcpt_bits_uop_uopc, // @[lsu.scala:204:14]
output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:204:14]
output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:204:14]
output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:204:14]
output [2:0] io_core_lxcpt_bits_uop_iq_type, // @[lsu.scala:204:14]
output [9:0] io_core_lxcpt_bits_uop_fu_code, // @[lsu.scala:204:14]
output [3:0] io_core_lxcpt_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
output [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
output [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
output [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
output [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_iw_state, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_br, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_jalr, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_jal, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:204:14]
output [15:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:204:14]
output [3:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:204:14]
output [4:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:204:14]
output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:204:14]
output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:204:14]
output [11:0] io_core_lxcpt_bits_uop_csr_addr, // @[lsu.scala:204:14]
output [6:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:204:14]
output [4:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:204:14]
output [4:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:204:14]
output [6:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:204:14]
output [6:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:204:14]
output [6:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:204:14]
output [6:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:204:14]
output [4:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:204:14]
output [6:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:204:14]
output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_bypassable, // @[lsu.scala:204:14]
output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:204:14]
output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:204:14]
output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:204:14]
output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_ldst_val, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_fp_single, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
output [1:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:204:14]
output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:204:14]
input [63:0] io_core_tsc_reg, // @[lsu.scala:204:14]
output io_core_perf_acquire, // @[lsu.scala:204:14]
output io_core_perf_release, // @[lsu.scala:204:14]
output io_core_perf_tlbMiss, // @[lsu.scala:204:14]
input io_dmem_req_ready, // @[lsu.scala:204:14]
output io_dmem_req_valid, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_valid, // @[lsu.scala:204:14]
output [6:0] io_dmem_req_bits_0_bits_uop_uopc, // @[lsu.scala:204:14]
output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:204:14]
output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:204:14]
output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:204:14]
output [2:0] io_dmem_req_bits_0_bits_uop_iq_type, // @[lsu.scala:204:14]
output [9:0] io_dmem_req_bits_0_bits_uop_fu_code, // @[lsu.scala:204:14]
output [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
output [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_iw_state, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_br, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_jalr, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_jal, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:204:14]
output [15:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:204:14]
output [3:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:204:14]
output [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:204:14]
output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:204:14]
output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:204:14]
output [11:0] io_dmem_req_bits_0_bits_uop_csr_addr, // @[lsu.scala:204:14]
output [6:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:204:14]
output [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:204:14]
output [4:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:204:14]
output [6:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:204:14]
output [6:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:204:14]
output [6:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:204:14]
output [6:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:204:14]
output [4:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:204:14]
output [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:204:14]
output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_bypassable, // @[lsu.scala:204:14]
output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:204:14]
output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:204:14]
output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:204:14]
output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_ldst_val, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_fp_single, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
output [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:204:14]
output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:204:14]
output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:204:14]
output io_dmem_s1_kill_0, // @[lsu.scala:204:14]
input io_dmem_resp_0_valid, // @[lsu.scala:204:14]
input [6:0] io_dmem_resp_0_bits_uop_uopc, // @[lsu.scala:204:14]
input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:204:14]
input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_dmem_resp_0_bits_uop_iq_type, // @[lsu.scala:204:14]
input [9:0] io_dmem_resp_0_bits_uop_fu_code, // @[lsu.scala:204:14]
input [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_iw_state, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_br, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_jalr, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_jal, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:204:14]
input [3:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:204:14]
input [4:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:204:14]
input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_dmem_resp_0_bits_uop_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:204:14]
input [6:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:204:14]
input [6:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:204:14]
input [6:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:204:14]
input [4:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:204:14]
input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_bypassable, // @[lsu.scala:204:14]
input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:204:14]
input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:204:14]
input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:204:14]
input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_fp_single, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:204:14]
input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:204:14]
input io_dmem_nack_0_valid, // @[lsu.scala:204:14]
input [6:0] io_dmem_nack_0_bits_uop_uopc, // @[lsu.scala:204:14]
input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:204:14]
input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:204:14]
input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:204:14]
input [2:0] io_dmem_nack_0_bits_uop_iq_type, // @[lsu.scala:204:14]
input [9:0] io_dmem_nack_0_bits_uop_fu_code, // @[lsu.scala:204:14]
input [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
input [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
input [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
input [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
input [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_iw_state, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_br, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_jalr, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_jal, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:204:14]
input [15:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:204:14]
input [3:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:204:14]
input [4:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:204:14]
input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:204:14]
input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:204:14]
input [11:0] io_dmem_nack_0_bits_uop_csr_addr, // @[lsu.scala:204:14]
input [6:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:204:14]
input [4:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:204:14]
input [4:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:204:14]
input [6:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:204:14]
input [6:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:204:14]
input [6:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:204:14]
input [6:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:204:14]
input [4:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:204:14]
input [6:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:204:14]
input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_bypassable, // @[lsu.scala:204:14]
input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14]
input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:204:14]
input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:204:14]
input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:204:14]
input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_ldst_val, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_fp_single, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14]
input [1:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14]
input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:204:14]
input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:204:14]
input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:204:14]
output [15:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:204:14]
output [15:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14]
output [6:0] io_dmem_brupdate_b2_uop_uopc, // @[lsu.scala:204:14]
output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:204:14]
output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14]
output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14]
output [2:0] io_dmem_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14]
output [9:0] io_dmem_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14]
output [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14]
output [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14]
output [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14]
output [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14]
output [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_br, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14]
output [15:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14]
output [3:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14]
output [4:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14]
output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:204:14]
output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14]
output [11:0] io_dmem_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14]
output [6:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14]
output [4:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14]
output [4:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14]
output [6:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:204:14]
output [6:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:204:14]
output [6:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:204:14]
output [6:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:204:14]
output [4:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14]
output [6:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:204:14]
output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14]
output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14]
output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:204:14]
output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14]
output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14]
output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_valid, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:204:14]
output io_dmem_brupdate_b2_taken, // @[lsu.scala:204:14]
output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:204:14]
output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:204:14]
output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:204:14]
output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:204:14]
output io_dmem_exception, // @[lsu.scala:204:14]
output [6:0] io_dmem_rob_pnr_idx, // @[lsu.scala:204:14]
output [6:0] io_dmem_rob_head_idx, // @[lsu.scala:204:14]
output io_dmem_release_ready, // @[lsu.scala:204:14]
input io_dmem_release_valid, // @[lsu.scala:204:14]
input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:204:14]
input [2:0] io_dmem_release_bits_param, // @[lsu.scala:204:14]
input [3:0] io_dmem_release_bits_size, // @[lsu.scala:204:14]
input [2:0] io_dmem_release_bits_source, // @[lsu.scala:204:14]
input [31:0] io_dmem_release_bits_address, // @[lsu.scala:204:14]
input [127:0] io_dmem_release_bits_data, // @[lsu.scala:204:14]
output io_dmem_force_order, // @[lsu.scala:204:14]
input io_dmem_ordered, // @[lsu.scala:204:14]
input io_dmem_perf_acquire, // @[lsu.scala:204:14]
input io_dmem_perf_release, // @[lsu.scala:204:14]
output io_hellacache_req_ready, // @[lsu.scala:204:14]
input io_hellacache_req_valid, // @[lsu.scala:204:14]
input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:204:14]
input io_hellacache_req_bits_dv, // @[lsu.scala:204:14]
input io_hellacache_s1_kill, // @[lsu.scala:204:14]
output io_hellacache_s2_nack, // @[lsu.scala:204:14]
output io_hellacache_resp_valid, // @[lsu.scala:204:14]
output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:204:14]
output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:204:14]
output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:204:14]
output io_hellacache_store_pending // @[lsu.scala:204:14]
);
wire failed_loads_22; // @[lsu.scala:1054:34]
wire failed_loads_21; // @[lsu.scala:1054:34]
wire failed_loads_20; // @[lsu.scala:1054:34]
wire failed_loads_19; // @[lsu.scala:1054:34]
wire failed_loads_18; // @[lsu.scala:1054:34]
wire failed_loads_17; // @[lsu.scala:1054:34]
wire failed_loads_16; // @[lsu.scala:1054:34]
wire failed_loads_15; // @[lsu.scala:1054:34]
wire failed_loads_14; // @[lsu.scala:1054:34]
wire failed_loads_13; // @[lsu.scala:1054:34]
wire failed_loads_12; // @[lsu.scala:1054:34]
wire failed_loads_11; // @[lsu.scala:1054:34]
wire failed_loads_10; // @[lsu.scala:1054:34]
wire failed_loads_9; // @[lsu.scala:1054:34]
wire failed_loads_8; // @[lsu.scala:1054:34]
wire failed_loads_7; // @[lsu.scala:1054:34]
wire failed_loads_6; // @[lsu.scala:1054:34]
wire failed_loads_5; // @[lsu.scala:1054:34]
wire failed_loads_4; // @[lsu.scala:1054:34]
wire failed_loads_3; // @[lsu.scala:1054:34]
wire failed_loads_2; // @[lsu.scala:1054:34]
wire failed_loads_1; // @[lsu.scala:1054:34]
wire failed_loads_0; // @[lsu.scala:1054:34]
wire mem_stq_incoming_e_out_valid; // @[util.scala:106:23]
wire [15:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_valid; // @[util.scala:106:23]
wire [15:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23]
wire [15:0] mem_incoming_uop_out_br_mask; // @[util.scala:96:23]
wire [15:0] mem_xcpt_uops_out_br_mask; // @[util.scala:96:23]
wire [63:0] stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_committed; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49]
wire [63:0] stq_incoming_e_0_bits_data_bits; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_data_valid; // @[lsu.scala:263:49]
wire [39:0] stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49]
wire [5:0] stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49]
wire [5:0] stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49]
wire [5:0] stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49]
wire [5:0] stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49]
wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49]
wire [63:0] stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49]
wire [6:0] stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49]
wire [4:0] stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:263:49]
wire [6:0] stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49]
wire [6:0] stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49]
wire [6:0] stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49]
wire [6:0] stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49]
wire [4:0] stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49]
wire [4:0] stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49]
wire [6:0] stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49]
wire [11:0] stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49]
wire [19:0] stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49]
wire [5:0] stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49]
wire [4:0] stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49]
wire [3:0] stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49]
wire [9:0] stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49]
wire [2:0] stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49]
wire [39:0] stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49]
wire [31:0] stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49]
wire [31:0] stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49]
wire [6:0] stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49]
wire [2:0] stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49]
wire stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49]
wire [4:0] stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49]
wire [2:0] stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49]
wire [2:0] stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49]
wire [1:0] stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49]
wire [3:0] stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49]
wire [63:0] ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49]
wire [4:0] ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:263:49]
wire [4:0] ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:263:49]
wire [23:0] ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_observed; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_executed; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49]
wire [39:0] ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49]
wire [5:0] ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49]
wire [5:0] ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49]
wire [5:0] ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49]
wire [5:0] ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49]
wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49]
wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49]
wire [6:0] ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49]
wire [6:0] ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49]
wire [6:0] ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49]
wire [6:0] ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49]
wire [6:0] ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49]
wire [4:0] ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49]
wire [4:0] ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49]
wire [6:0] ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49]
wire [11:0] ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49]
wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49]
wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49]
wire [4:0] ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49]
wire [3:0] ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49]
wire [9:0] ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49]
wire [2:0] ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49]
wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49]
wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49]
wire [31:0] ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49]
wire [6:0] ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49]
wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49]
wire [4:0] ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49]
wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49]
wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49]
wire [1:0] ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49]
wire [3:0] ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49]
wire [1:0] exe_req_0_bits_uop_debug_tsrc; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_debug_fsrc; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_bp_debug_if; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_fp_single; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_fp_val; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_frs3_en; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_dst_rtype; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_ldst_val; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_uop_lrs3; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_uop_lrs2; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_uop_lrs1; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_uop_ldst; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_flush_on_commit; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_unique; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_uses_stq; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_uses_ldq; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_amo; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_fencei; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_fence; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_mem_signed; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_mem_size; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_uop_mem_cmd; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_bypassable; // @[lsu.scala:383:25]
wire [63:0] exe_req_0_bits_uop_exc_cause; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_exception; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_uop_stale_pdst; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_ppred_busy; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_prs3_busy; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_prs2_busy; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_prs1_busy; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_uop_ppred; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_uop_prs3; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_uop_prs2; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_uop_prs1; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_uop_pdst; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_rxq_idx; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_uop_stq_idx; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_uop_rob_idx; // @[lsu.scala:383:25]
wire [11:0] exe_req_0_bits_uop_csr_addr; // @[lsu.scala:383:25]
wire [19:0] exe_req_0_bits_uop_imm_packed; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_taken; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_uop_pc_lob; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_edge_inst; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_uop_ftq_idx; // @[lsu.scala:383:25]
wire [3:0] exe_req_0_bits_uop_br_tag; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_sfb; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_jal; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_jalr; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_br; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_iw_state; // @[lsu.scala:383:25]
wire [9:0] exe_req_0_bits_uop_fu_code; // @[lsu.scala:383:25]
wire [2:0] exe_req_0_bits_uop_iq_type; // @[lsu.scala:383:25]
wire [39:0] exe_req_0_bits_uop_debug_pc; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_is_rvc; // @[lsu.scala:383:25]
wire [31:0] exe_req_0_bits_uop_debug_inst; // @[lsu.scala:383:25]
wire [31:0] exe_req_0_bits_uop_inst; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_uop_uopc; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25]
wire [2:0] exe_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:383:25]
wire exe_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:383:25]
wire [2:0] exe_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:383:25]
wire [2:0] exe_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:383:25]
wire [3:0] exe_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:383:25]
wire _dtlb_io_miss_rdy; // @[lsu.scala:247:20]
wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:247:20]
wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20]
wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20]
wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20]
wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20]
wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:247:20]
wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:247:20]
wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:201:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:201:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:201:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:201:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:201:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:201:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:201:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:201:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:201:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:201:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:201:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:201:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:201:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:201:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:201:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:201:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:201:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:201:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:201:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:201:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:201:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:201:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:201:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:201:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:201:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:201:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:201:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:201:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:201:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:201:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:201:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:201:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:201:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:201:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:201:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:201:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:201:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:201:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:201:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:201:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:201:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:201:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:201:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:201:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:201:7]
wire io_core_exe_0_req_valid_0 = io_core_exe_0_req_valid; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_uop_uopc_0 = io_core_exe_0_req_bits_uop_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_req_bits_uop_inst_0 = io_core_exe_0_req_bits_uop_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_req_bits_uop_debug_inst_0 = io_core_exe_0_req_bits_uop_debug_inst; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_rvc_0 = io_core_exe_0_req_bits_uop_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_exe_0_req_bits_uop_debug_pc_0 = io_core_exe_0_req_bits_uop_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_req_bits_uop_iq_type_0 = io_core_exe_0_req_bits_uop_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_exe_0_req_bits_uop_fu_code_0 = io_core_exe_0_req_bits_uop_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type_0 = io_core_exe_0_req_bits_uop_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 = io_core_exe_0_req_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 = io_core_exe_0_req_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 = io_core_exe_0_req_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 = io_core_exe_0_req_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_ctrl_is_load_0 = io_core_exe_0_req_bits_uop_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_ctrl_is_sta_0 = io_core_exe_0_req_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_ctrl_is_std_0 = io_core_exe_0_req_bits_uop_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_iw_state_0 = io_core_exe_0_req_bits_uop_iw_state; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_br_0 = io_core_exe_0_req_bits_uop_is_br; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_jalr_0 = io_core_exe_0_req_bits_uop_is_jalr; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_jal_0 = io_core_exe_0_req_bits_uop_is_jal; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_sfb_0 = io_core_exe_0_req_bits_uop_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_exe_0_req_bits_uop_br_mask_0 = io_core_exe_0_req_bits_uop_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_req_bits_uop_br_tag_0 = io_core_exe_0_req_bits_uop_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_uop_ftq_idx_0 = io_core_exe_0_req_bits_uop_ftq_idx; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_edge_inst_0 = io_core_exe_0_req_bits_uop_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_uop_pc_lob_0 = io_core_exe_0_req_bits_uop_pc_lob; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_taken_0 = io_core_exe_0_req_bits_uop_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_exe_0_req_bits_uop_imm_packed_0 = io_core_exe_0_req_bits_uop_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_exe_0_req_bits_uop_csr_addr_0 = io_core_exe_0_req_bits_uop_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_uop_rob_idx_0 = io_core_exe_0_req_bits_uop_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_uop_ldq_idx_0 = io_core_exe_0_req_bits_uop_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_uop_stq_idx_0 = io_core_exe_0_req_bits_uop_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_rxq_idx_0 = io_core_exe_0_req_bits_uop_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_uop_pdst_0 = io_core_exe_0_req_bits_uop_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_uop_prs1_0 = io_core_exe_0_req_bits_uop_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_uop_prs2_0 = io_core_exe_0_req_bits_uop_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_uop_prs3_0 = io_core_exe_0_req_bits_uop_prs3; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_uop_ppred_0 = io_core_exe_0_req_bits_uop_ppred; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_prs1_busy_0 = io_core_exe_0_req_bits_uop_prs1_busy; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_prs2_busy_0 = io_core_exe_0_req_bits_uop_prs2_busy; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_prs3_busy_0 = io_core_exe_0_req_bits_uop_prs3_busy; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_ppred_busy_0 = io_core_exe_0_req_bits_uop_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_uop_stale_pdst_0 = io_core_exe_0_req_bits_uop_stale_pdst; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_exception_0 = io_core_exe_0_req_bits_uop_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_req_bits_uop_exc_cause_0 = io_core_exe_0_req_bits_uop_exc_cause; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_bypassable_0 = io_core_exe_0_req_bits_uop_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_uop_mem_cmd_0 = io_core_exe_0_req_bits_uop_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_mem_size_0 = io_core_exe_0_req_bits_uop_mem_size; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_mem_signed_0 = io_core_exe_0_req_bits_uop_mem_signed; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_fence_0 = io_core_exe_0_req_bits_uop_is_fence; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_fencei_0 = io_core_exe_0_req_bits_uop_is_fencei; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_amo_0 = io_core_exe_0_req_bits_uop_is_amo; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_uses_ldq_0 = io_core_exe_0_req_bits_uop_uses_ldq; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_uses_stq_0 = io_core_exe_0_req_bits_uop_uses_stq; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 = io_core_exe_0_req_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_is_unique_0 = io_core_exe_0_req_bits_uop_is_unique; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_flush_on_commit_0 = io_core_exe_0_req_bits_uop_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_ldst_is_rs1_0 = io_core_exe_0_req_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_uop_ldst_0 = io_core_exe_0_req_bits_uop_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_uop_lrs1_0 = io_core_exe_0_req_bits_uop_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_uop_lrs2_0 = io_core_exe_0_req_bits_uop_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_uop_lrs3_0 = io_core_exe_0_req_bits_uop_lrs3; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_ldst_val_0 = io_core_exe_0_req_bits_uop_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_dst_rtype_0 = io_core_exe_0_req_bits_uop_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype_0 = io_core_exe_0_req_bits_uop_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype_0 = io_core_exe_0_req_bits_uop_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_frs3_en_0 = io_core_exe_0_req_bits_uop_frs3_en; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_fp_val_0 = io_core_exe_0_req_bits_uop_fp_val; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_fp_single_0 = io_core_exe_0_req_bits_uop_fp_single; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_xcpt_pf_if_0 = io_core_exe_0_req_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_xcpt_ae_if_0 = io_core_exe_0_req_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_xcpt_ma_if_0 = io_core_exe_0_req_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_bp_debug_if_0 = io_core_exe_0_req_bits_uop_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_uop_bp_xcpt_if_0 = io_core_exe_0_req_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_debug_fsrc_0 = io_core_exe_0_req_bits_uop_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_uop_debug_tsrc_0 = io_core_exe_0_req_bits_uop_debug_tsrc; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_req_bits_data_0 = io_core_exe_0_req_bits_data; // @[lsu.scala:201:7]
wire [39:0] io_core_exe_0_req_bits_addr_0 = io_core_exe_0_req_bits_addr; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_mxcpt_valid_0 = io_core_exe_0_req_bits_mxcpt_valid; // @[lsu.scala:201:7]
wire [24:0] io_core_exe_0_req_bits_mxcpt_bits_0 = io_core_exe_0_req_bits_mxcpt_bits; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_sfence_valid_0 = io_core_exe_0_req_bits_sfence_valid; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_sfence_bits_rs1_0 = io_core_exe_0_req_bits_sfence_bits_rs1; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_sfence_bits_rs2_0 = io_core_exe_0_req_bits_sfence_bits_rs2; // @[lsu.scala:201:7]
wire [38:0] io_core_exe_0_req_bits_sfence_bits_addr_0 = io_core_exe_0_req_bits_sfence_bits_addr; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_sfence_bits_asid_0 = io_core_exe_0_req_bits_sfence_bits_asid; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_0_bits_uopc_0 = io_core_dis_uops_0_bits_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_0_bits_iq_type_0 = io_core_dis_uops_0_bits_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_dis_uops_0_bits_fu_code_0 = io_core_dis_uops_0_bits_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_dis_uops_0_bits_ctrl_br_type_0 = io_core_dis_uops_0_bits_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel_0 = io_core_dis_uops_0_bits_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel_0 = io_core_dis_uops_0_bits_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel_0 = io_core_dis_uops_0_bits_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn_0 = io_core_dis_uops_0_bits_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_ctrl_fcn_dw_0 = io_core_dis_uops_0_bits_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd_0 = io_core_dis_uops_0_bits_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_ctrl_is_load_0 = io_core_dis_uops_0_bits_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_ctrl_is_sta_0 = io_core_dis_uops_0_bits_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_ctrl_is_std_0 = io_core_dis_uops_0_bits_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_iw_state_0 = io_core_dis_uops_0_bits_iw_state; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_iw_p1_poisoned_0 = io_core_dis_uops_0_bits_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_iw_p2_poisoned_0 = io_core_dis_uops_0_bits_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_br_0 = io_core_dis_uops_0_bits_is_br; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_jalr_0 = io_core_dis_uops_0_bits_is_jalr; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_jal_0 = io_core_dis_uops_0_bits_is_jal; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_dis_uops_0_bits_csr_addr_0 = io_core_dis_uops_0_bits_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_bypassable_0 = io_core_dis_uops_0_bits_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_ldst_val_0 = io_core_dis_uops_0_bits_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_fp_single_0 = io_core_dis_uops_0_bits_fp_single; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_valid_0 = io_core_dis_uops_1_valid; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_1_bits_uopc_0 = io_core_dis_uops_1_bits_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_dis_uops_1_bits_inst_0 = io_core_dis_uops_1_bits_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_dis_uops_1_bits_debug_inst_0 = io_core_dis_uops_1_bits_debug_inst; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_rvc_0 = io_core_dis_uops_1_bits_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_dis_uops_1_bits_debug_pc_0 = io_core_dis_uops_1_bits_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_1_bits_iq_type_0 = io_core_dis_uops_1_bits_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_dis_uops_1_bits_fu_code_0 = io_core_dis_uops_1_bits_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_dis_uops_1_bits_ctrl_br_type_0 = io_core_dis_uops_1_bits_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_ctrl_op1_sel_0 = io_core_dis_uops_1_bits_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_1_bits_ctrl_op2_sel_0 = io_core_dis_uops_1_bits_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_1_bits_ctrl_imm_sel_0 = io_core_dis_uops_1_bits_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_1_bits_ctrl_op_fcn_0 = io_core_dis_uops_1_bits_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_ctrl_fcn_dw_0 = io_core_dis_uops_1_bits_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_1_bits_ctrl_csr_cmd_0 = io_core_dis_uops_1_bits_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_ctrl_is_load_0 = io_core_dis_uops_1_bits_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_ctrl_is_sta_0 = io_core_dis_uops_1_bits_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_ctrl_is_std_0 = io_core_dis_uops_1_bits_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_iw_state_0 = io_core_dis_uops_1_bits_iw_state; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_iw_p1_poisoned_0 = io_core_dis_uops_1_bits_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_iw_p2_poisoned_0 = io_core_dis_uops_1_bits_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_br_0 = io_core_dis_uops_1_bits_is_br; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_jalr_0 = io_core_dis_uops_1_bits_is_jalr; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_jal_0 = io_core_dis_uops_1_bits_is_jal; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_sfb_0 = io_core_dis_uops_1_bits_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_dis_uops_1_bits_br_mask_0 = io_core_dis_uops_1_bits_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_dis_uops_1_bits_br_tag_0 = io_core_dis_uops_1_bits_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_1_bits_ftq_idx_0 = io_core_dis_uops_1_bits_ftq_idx; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_edge_inst_0 = io_core_dis_uops_1_bits_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_1_bits_pc_lob_0 = io_core_dis_uops_1_bits_pc_lob; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_taken_0 = io_core_dis_uops_1_bits_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_dis_uops_1_bits_imm_packed_0 = io_core_dis_uops_1_bits_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_dis_uops_1_bits_csr_addr_0 = io_core_dis_uops_1_bits_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_1_bits_rob_idx_0 = io_core_dis_uops_1_bits_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_1_bits_ldq_idx_0 = io_core_dis_uops_1_bits_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_1_bits_stq_idx_0 = io_core_dis_uops_1_bits_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_rxq_idx_0 = io_core_dis_uops_1_bits_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_1_bits_pdst_0 = io_core_dis_uops_1_bits_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_1_bits_prs1_0 = io_core_dis_uops_1_bits_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_1_bits_prs2_0 = io_core_dis_uops_1_bits_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_1_bits_prs3_0 = io_core_dis_uops_1_bits_prs3; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_prs1_busy_0 = io_core_dis_uops_1_bits_prs1_busy; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_prs2_busy_0 = io_core_dis_uops_1_bits_prs2_busy; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_prs3_busy_0 = io_core_dis_uops_1_bits_prs3_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_1_bits_stale_pdst_0 = io_core_dis_uops_1_bits_stale_pdst; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_exception_0 = io_core_dis_uops_1_bits_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_dis_uops_1_bits_exc_cause_0 = io_core_dis_uops_1_bits_exc_cause; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_bypassable_0 = io_core_dis_uops_1_bits_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_1_bits_mem_cmd_0 = io_core_dis_uops_1_bits_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_mem_size_0 = io_core_dis_uops_1_bits_mem_size; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_mem_signed_0 = io_core_dis_uops_1_bits_mem_signed; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_fence_0 = io_core_dis_uops_1_bits_is_fence; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_fencei_0 = io_core_dis_uops_1_bits_is_fencei; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_amo_0 = io_core_dis_uops_1_bits_is_amo; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_uses_ldq_0 = io_core_dis_uops_1_bits_uses_ldq; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_uses_stq_0 = io_core_dis_uops_1_bits_uses_stq; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_sys_pc2epc_0 = io_core_dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_is_unique_0 = io_core_dis_uops_1_bits_is_unique; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_flush_on_commit_0 = io_core_dis_uops_1_bits_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_ldst_is_rs1_0 = io_core_dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_1_bits_ldst_0 = io_core_dis_uops_1_bits_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_1_bits_lrs1_0 = io_core_dis_uops_1_bits_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_1_bits_lrs2_0 = io_core_dis_uops_1_bits_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_1_bits_lrs3_0 = io_core_dis_uops_1_bits_lrs3; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_ldst_val_0 = io_core_dis_uops_1_bits_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_dst_rtype_0 = io_core_dis_uops_1_bits_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_lrs1_rtype_0 = io_core_dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_lrs2_rtype_0 = io_core_dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_frs3_en_0 = io_core_dis_uops_1_bits_frs3_en; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_fp_val_0 = io_core_dis_uops_1_bits_fp_val; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_fp_single_0 = io_core_dis_uops_1_bits_fp_single; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_xcpt_pf_if_0 = io_core_dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_xcpt_ae_if_0 = io_core_dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_xcpt_ma_if_0 = io_core_dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_bp_debug_if_0 = io_core_dis_uops_1_bits_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_bp_xcpt_if_0 = io_core_dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_debug_fsrc_0 = io_core_dis_uops_1_bits_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_1_bits_debug_tsrc_0 = io_core_dis_uops_1_bits_debug_tsrc; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_valid_0 = io_core_dis_uops_2_valid; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_2_bits_uopc_0 = io_core_dis_uops_2_bits_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_dis_uops_2_bits_inst_0 = io_core_dis_uops_2_bits_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_dis_uops_2_bits_debug_inst_0 = io_core_dis_uops_2_bits_debug_inst; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_rvc_0 = io_core_dis_uops_2_bits_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_dis_uops_2_bits_debug_pc_0 = io_core_dis_uops_2_bits_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_2_bits_iq_type_0 = io_core_dis_uops_2_bits_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_dis_uops_2_bits_fu_code_0 = io_core_dis_uops_2_bits_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_dis_uops_2_bits_ctrl_br_type_0 = io_core_dis_uops_2_bits_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_ctrl_op1_sel_0 = io_core_dis_uops_2_bits_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_2_bits_ctrl_op2_sel_0 = io_core_dis_uops_2_bits_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_2_bits_ctrl_imm_sel_0 = io_core_dis_uops_2_bits_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_2_bits_ctrl_op_fcn_0 = io_core_dis_uops_2_bits_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_ctrl_fcn_dw_0 = io_core_dis_uops_2_bits_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_dis_uops_2_bits_ctrl_csr_cmd_0 = io_core_dis_uops_2_bits_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_ctrl_is_load_0 = io_core_dis_uops_2_bits_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_ctrl_is_sta_0 = io_core_dis_uops_2_bits_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_ctrl_is_std_0 = io_core_dis_uops_2_bits_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_iw_state_0 = io_core_dis_uops_2_bits_iw_state; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_iw_p1_poisoned_0 = io_core_dis_uops_2_bits_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_iw_p2_poisoned_0 = io_core_dis_uops_2_bits_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_br_0 = io_core_dis_uops_2_bits_is_br; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_jalr_0 = io_core_dis_uops_2_bits_is_jalr; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_jal_0 = io_core_dis_uops_2_bits_is_jal; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_sfb_0 = io_core_dis_uops_2_bits_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_dis_uops_2_bits_br_mask_0 = io_core_dis_uops_2_bits_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_dis_uops_2_bits_br_tag_0 = io_core_dis_uops_2_bits_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_2_bits_ftq_idx_0 = io_core_dis_uops_2_bits_ftq_idx; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_edge_inst_0 = io_core_dis_uops_2_bits_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_2_bits_pc_lob_0 = io_core_dis_uops_2_bits_pc_lob; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_taken_0 = io_core_dis_uops_2_bits_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_dis_uops_2_bits_imm_packed_0 = io_core_dis_uops_2_bits_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_dis_uops_2_bits_csr_addr_0 = io_core_dis_uops_2_bits_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_2_bits_rob_idx_0 = io_core_dis_uops_2_bits_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_2_bits_ldq_idx_0 = io_core_dis_uops_2_bits_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_2_bits_stq_idx_0 = io_core_dis_uops_2_bits_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_rxq_idx_0 = io_core_dis_uops_2_bits_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_2_bits_pdst_0 = io_core_dis_uops_2_bits_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_2_bits_prs1_0 = io_core_dis_uops_2_bits_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_2_bits_prs2_0 = io_core_dis_uops_2_bits_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_2_bits_prs3_0 = io_core_dis_uops_2_bits_prs3; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_prs1_busy_0 = io_core_dis_uops_2_bits_prs1_busy; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_prs2_busy_0 = io_core_dis_uops_2_bits_prs2_busy; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_prs3_busy_0 = io_core_dis_uops_2_bits_prs3_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_dis_uops_2_bits_stale_pdst_0 = io_core_dis_uops_2_bits_stale_pdst; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_exception_0 = io_core_dis_uops_2_bits_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_dis_uops_2_bits_exc_cause_0 = io_core_dis_uops_2_bits_exc_cause; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_bypassable_0 = io_core_dis_uops_2_bits_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_2_bits_mem_cmd_0 = io_core_dis_uops_2_bits_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_mem_size_0 = io_core_dis_uops_2_bits_mem_size; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_mem_signed_0 = io_core_dis_uops_2_bits_mem_signed; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_fence_0 = io_core_dis_uops_2_bits_is_fence; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_fencei_0 = io_core_dis_uops_2_bits_is_fencei; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_amo_0 = io_core_dis_uops_2_bits_is_amo; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_uses_ldq_0 = io_core_dis_uops_2_bits_uses_ldq; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_uses_stq_0 = io_core_dis_uops_2_bits_uses_stq; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_sys_pc2epc_0 = io_core_dis_uops_2_bits_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_is_unique_0 = io_core_dis_uops_2_bits_is_unique; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_flush_on_commit_0 = io_core_dis_uops_2_bits_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_ldst_is_rs1_0 = io_core_dis_uops_2_bits_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_2_bits_ldst_0 = io_core_dis_uops_2_bits_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_2_bits_lrs1_0 = io_core_dis_uops_2_bits_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_2_bits_lrs2_0 = io_core_dis_uops_2_bits_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_dis_uops_2_bits_lrs3_0 = io_core_dis_uops_2_bits_lrs3; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_ldst_val_0 = io_core_dis_uops_2_bits_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_dst_rtype_0 = io_core_dis_uops_2_bits_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_lrs1_rtype_0 = io_core_dis_uops_2_bits_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_lrs2_rtype_0 = io_core_dis_uops_2_bits_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_frs3_en_0 = io_core_dis_uops_2_bits_frs3_en; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_fp_val_0 = io_core_dis_uops_2_bits_fp_val; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_fp_single_0 = io_core_dis_uops_2_bits_fp_single; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_xcpt_pf_if_0 = io_core_dis_uops_2_bits_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_xcpt_ae_if_0 = io_core_dis_uops_2_bits_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_xcpt_ma_if_0 = io_core_dis_uops_2_bits_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_bp_debug_if_0 = io_core_dis_uops_2_bits_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_bp_xcpt_if_0 = io_core_dis_uops_2_bits_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_debug_fsrc_0 = io_core_dis_uops_2_bits_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_dis_uops_2_bits_debug_tsrc_0 = io_core_dis_uops_2_bits_debug_tsrc; // @[lsu.scala:201:7]
wire io_core_fp_stdata_valid_0 = io_core_fp_stdata_valid; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_uop_uopc_0 = io_core_fp_stdata_bits_uop_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_fp_stdata_bits_uop_inst_0 = io_core_fp_stdata_bits_uop_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_fp_stdata_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_uop_debug_inst; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_uop_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_fp_stdata_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_uop_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_uop_iq_type_0 = io_core_fp_stdata_bits_uop_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_fp_stdata_bits_uop_fu_code_0 = io_core_fp_stdata_bits_uop_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_uop_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_uop_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_uop_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_iw_state_0 = io_core_fp_stdata_bits_uop_iw_state; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_br_0 = io_core_fp_stdata_bits_uop_is_br; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_uop_is_jalr; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_jal_0 = io_core_fp_stdata_bits_uop_is_jal; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_uop_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_fp_stdata_bits_uop_br_mask_0 = io_core_fp_stdata_bits_uop_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_fp_stdata_bits_uop_br_tag_0 = io_core_fp_stdata_bits_uop_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_uop_ftq_idx; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_uop_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_uop_pc_lob; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_taken_0 = io_core_fp_stdata_bits_uop_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_fp_stdata_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_uop_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_fp_stdata_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_uop_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_uop_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_uop_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_uop_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_uop_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_uop_pdst_0 = io_core_fp_stdata_bits_uop_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_uop_prs1_0 = io_core_fp_stdata_bits_uop_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_uop_prs2_0 = io_core_fp_stdata_bits_uop_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_uop_prs3_0 = io_core_fp_stdata_bits_uop_prs3; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_uop_ppred_0 = io_core_fp_stdata_bits_uop_ppred; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_uop_prs1_busy; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_uop_prs2_busy; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_uop_prs3_busy; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_uop_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_uop_stale_pdst; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_exception_0 = io_core_fp_stdata_bits_uop_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_fp_stdata_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_uop_exc_cause; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_bypassable_0 = io_core_fp_stdata_bits_uop_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_uop_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_mem_size_0 = io_core_fp_stdata_bits_uop_mem_size; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_uop_mem_signed; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_fence_0 = io_core_fp_stdata_bits_uop_is_fence; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_uop_is_fencei; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_amo_0 = io_core_fp_stdata_bits_uop_is_amo; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_uop_uses_ldq; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_uop_uses_stq; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_is_unique_0 = io_core_fp_stdata_bits_uop_is_unique; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_uop_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_uop_ldst_0 = io_core_fp_stdata_bits_uop_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_uop_lrs1_0 = io_core_fp_stdata_bits_uop_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_uop_lrs2_0 = io_core_fp_stdata_bits_uop_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_uop_lrs3_0 = io_core_fp_stdata_bits_uop_lrs3; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_uop_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_uop_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_uop_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_uop_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_uop_frs3_en; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_fp_val_0 = io_core_fp_stdata_bits_uop_fp_val; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_fp_single_0 = io_core_fp_stdata_bits_uop_fp_single; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_uop_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_uop_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_uop_debug_tsrc; // @[lsu.scala:201:7]
wire [63:0] io_core_fp_stdata_bits_data_0 = io_core_fp_stdata_bits_data; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_predicated_0 = io_core_fp_stdata_bits_predicated; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_valid_0 = io_core_fp_stdata_bits_fflags_valid; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc_0 = io_core_fp_stdata_bits_fflags_bits_uop_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_inst; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code_0 = io_core_fp_stdata_bits_fflags_bits_uop_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_state; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_br_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_br; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jalr; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_jal_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jal; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_fflags_bits_uop_pc_lob; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_taken_0 = io_core_fp_stdata_bits_fflags_bits_uop_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_fflags_bits_uop_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_fflags_bits_uop_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_exception_0 = io_core_fp_stdata_bits_fflags_bits_uop_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_fflags_bits_uop_exc_cause; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_bypassable_0 = io_core_fp_stdata_bits_fflags_bits_uop_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_size; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_signed; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_fence_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fence; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fencei; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_amo_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_amo; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_stq; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_is_unique_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_unique; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs3; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_fflags_bits_uop_frs3_en; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_fp_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_val; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_fp_single_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_single; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc; // @[lsu.scala:201:7]
wire [4:0] io_core_fp_stdata_bits_fflags_bits_flags_0 = io_core_fp_stdata_bits_fflags_bits_flags; // @[lsu.scala:201:7]
wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:201:7]
wire io_core_commit_valids_1_0 = io_core_commit_valids_1; // @[lsu.scala:201:7]
wire io_core_commit_valids_2_0 = io_core_commit_valids_2; // @[lsu.scala:201:7]
wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:201:7]
wire io_core_commit_arch_valids_1_0 = io_core_commit_arch_valids_1; // @[lsu.scala:201:7]
wire io_core_commit_arch_valids_2_0 = io_core_commit_arch_valids_2; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_0_uopc_0 = io_core_commit_uops_0_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_0_iq_type_0 = io_core_commit_uops_0_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_commit_uops_0_fu_code_0 = io_core_commit_uops_0_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_commit_uops_0_ctrl_br_type_0 = io_core_commit_uops_0_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_ctrl_op1_sel_0 = io_core_commit_uops_0_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_0_ctrl_op2_sel_0 = io_core_commit_uops_0_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_0_ctrl_imm_sel_0 = io_core_commit_uops_0_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_0_ctrl_op_fcn_0 = io_core_commit_uops_0_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_ctrl_fcn_dw_0 = io_core_commit_uops_0_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_0_ctrl_csr_cmd_0 = io_core_commit_uops_0_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_ctrl_is_load_0 = io_core_commit_uops_0_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_ctrl_is_sta_0 = io_core_commit_uops_0_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_ctrl_is_std_0 = io_core_commit_uops_0_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_iw_state_0 = io_core_commit_uops_0_iw_state; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_iw_p1_poisoned_0 = io_core_commit_uops_0_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_iw_p2_poisoned_0 = io_core_commit_uops_0_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_br_0 = io_core_commit_uops_0_is_br; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_jalr_0 = io_core_commit_uops_0_is_jalr; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_jal_0 = io_core_commit_uops_0_is_jal; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_commit_uops_0_csr_addr_0 = io_core_commit_uops_0_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_bypassable_0 = io_core_commit_uops_0_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_ldst_val_0 = io_core_commit_uops_0_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_fp_single_0 = io_core_commit_uops_0_fp_single; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_1_uopc_0 = io_core_commit_uops_1_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_uops_1_inst_0 = io_core_commit_uops_1_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_uops_1_debug_inst_0 = io_core_commit_uops_1_debug_inst; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_rvc_0 = io_core_commit_uops_1_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_commit_uops_1_debug_pc_0 = io_core_commit_uops_1_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_1_iq_type_0 = io_core_commit_uops_1_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_commit_uops_1_fu_code_0 = io_core_commit_uops_1_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_commit_uops_1_ctrl_br_type_0 = io_core_commit_uops_1_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_ctrl_op1_sel_0 = io_core_commit_uops_1_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_1_ctrl_op2_sel_0 = io_core_commit_uops_1_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_1_ctrl_imm_sel_0 = io_core_commit_uops_1_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_1_ctrl_op_fcn_0 = io_core_commit_uops_1_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_ctrl_fcn_dw_0 = io_core_commit_uops_1_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_1_ctrl_csr_cmd_0 = io_core_commit_uops_1_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_ctrl_is_load_0 = io_core_commit_uops_1_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_ctrl_is_sta_0 = io_core_commit_uops_1_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_ctrl_is_std_0 = io_core_commit_uops_1_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_iw_state_0 = io_core_commit_uops_1_iw_state; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_iw_p1_poisoned_0 = io_core_commit_uops_1_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_iw_p2_poisoned_0 = io_core_commit_uops_1_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_br_0 = io_core_commit_uops_1_is_br; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_jalr_0 = io_core_commit_uops_1_is_jalr; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_jal_0 = io_core_commit_uops_1_is_jal; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_sfb_0 = io_core_commit_uops_1_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_commit_uops_1_br_mask_0 = io_core_commit_uops_1_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_commit_uops_1_br_tag_0 = io_core_commit_uops_1_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_1_ftq_idx_0 = io_core_commit_uops_1_ftq_idx; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_edge_inst_0 = io_core_commit_uops_1_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_1_pc_lob_0 = io_core_commit_uops_1_pc_lob; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_taken_0 = io_core_commit_uops_1_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_commit_uops_1_imm_packed_0 = io_core_commit_uops_1_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_commit_uops_1_csr_addr_0 = io_core_commit_uops_1_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_1_rob_idx_0 = io_core_commit_uops_1_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_1_ldq_idx_0 = io_core_commit_uops_1_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_1_stq_idx_0 = io_core_commit_uops_1_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_rxq_idx_0 = io_core_commit_uops_1_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_1_pdst_0 = io_core_commit_uops_1_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_1_prs1_0 = io_core_commit_uops_1_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_1_prs2_0 = io_core_commit_uops_1_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_1_prs3_0 = io_core_commit_uops_1_prs3; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_1_ppred_0 = io_core_commit_uops_1_ppred; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_prs1_busy_0 = io_core_commit_uops_1_prs1_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_prs2_busy_0 = io_core_commit_uops_1_prs2_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_prs3_busy_0 = io_core_commit_uops_1_prs3_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_ppred_busy_0 = io_core_commit_uops_1_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_1_stale_pdst_0 = io_core_commit_uops_1_stale_pdst; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_exception_0 = io_core_commit_uops_1_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_commit_uops_1_exc_cause_0 = io_core_commit_uops_1_exc_cause; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_bypassable_0 = io_core_commit_uops_1_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_1_mem_cmd_0 = io_core_commit_uops_1_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_mem_size_0 = io_core_commit_uops_1_mem_size; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_mem_signed_0 = io_core_commit_uops_1_mem_signed; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_fence_0 = io_core_commit_uops_1_is_fence; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_fencei_0 = io_core_commit_uops_1_is_fencei; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_amo_0 = io_core_commit_uops_1_is_amo; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_uses_ldq_0 = io_core_commit_uops_1_uses_ldq; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_uses_stq_0 = io_core_commit_uops_1_uses_stq; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_sys_pc2epc_0 = io_core_commit_uops_1_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_is_unique_0 = io_core_commit_uops_1_is_unique; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_flush_on_commit_0 = io_core_commit_uops_1_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_ldst_is_rs1_0 = io_core_commit_uops_1_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_1_ldst_0 = io_core_commit_uops_1_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_1_lrs1_0 = io_core_commit_uops_1_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_1_lrs2_0 = io_core_commit_uops_1_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_1_lrs3_0 = io_core_commit_uops_1_lrs3; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_ldst_val_0 = io_core_commit_uops_1_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_dst_rtype_0 = io_core_commit_uops_1_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_lrs1_rtype_0 = io_core_commit_uops_1_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_lrs2_rtype_0 = io_core_commit_uops_1_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_frs3_en_0 = io_core_commit_uops_1_frs3_en; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_fp_val_0 = io_core_commit_uops_1_fp_val; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_fp_single_0 = io_core_commit_uops_1_fp_single; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_xcpt_pf_if_0 = io_core_commit_uops_1_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_xcpt_ae_if_0 = io_core_commit_uops_1_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_xcpt_ma_if_0 = io_core_commit_uops_1_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_bp_debug_if_0 = io_core_commit_uops_1_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_1_bp_xcpt_if_0 = io_core_commit_uops_1_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_debug_fsrc_0 = io_core_commit_uops_1_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_1_debug_tsrc_0 = io_core_commit_uops_1_debug_tsrc; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_2_uopc_0 = io_core_commit_uops_2_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_uops_2_inst_0 = io_core_commit_uops_2_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_uops_2_debug_inst_0 = io_core_commit_uops_2_debug_inst; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_rvc_0 = io_core_commit_uops_2_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_commit_uops_2_debug_pc_0 = io_core_commit_uops_2_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_2_iq_type_0 = io_core_commit_uops_2_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_commit_uops_2_fu_code_0 = io_core_commit_uops_2_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_commit_uops_2_ctrl_br_type_0 = io_core_commit_uops_2_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_ctrl_op1_sel_0 = io_core_commit_uops_2_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_2_ctrl_op2_sel_0 = io_core_commit_uops_2_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_2_ctrl_imm_sel_0 = io_core_commit_uops_2_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_2_ctrl_op_fcn_0 = io_core_commit_uops_2_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_ctrl_fcn_dw_0 = io_core_commit_uops_2_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_commit_uops_2_ctrl_csr_cmd_0 = io_core_commit_uops_2_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_ctrl_is_load_0 = io_core_commit_uops_2_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_ctrl_is_sta_0 = io_core_commit_uops_2_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_ctrl_is_std_0 = io_core_commit_uops_2_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_iw_state_0 = io_core_commit_uops_2_iw_state; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_iw_p1_poisoned_0 = io_core_commit_uops_2_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_iw_p2_poisoned_0 = io_core_commit_uops_2_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_br_0 = io_core_commit_uops_2_is_br; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_jalr_0 = io_core_commit_uops_2_is_jalr; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_jal_0 = io_core_commit_uops_2_is_jal; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_sfb_0 = io_core_commit_uops_2_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_commit_uops_2_br_mask_0 = io_core_commit_uops_2_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_commit_uops_2_br_tag_0 = io_core_commit_uops_2_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_2_ftq_idx_0 = io_core_commit_uops_2_ftq_idx; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_edge_inst_0 = io_core_commit_uops_2_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_2_pc_lob_0 = io_core_commit_uops_2_pc_lob; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_taken_0 = io_core_commit_uops_2_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_commit_uops_2_imm_packed_0 = io_core_commit_uops_2_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_commit_uops_2_csr_addr_0 = io_core_commit_uops_2_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_2_rob_idx_0 = io_core_commit_uops_2_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_2_ldq_idx_0 = io_core_commit_uops_2_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_2_stq_idx_0 = io_core_commit_uops_2_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_rxq_idx_0 = io_core_commit_uops_2_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_2_pdst_0 = io_core_commit_uops_2_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_2_prs1_0 = io_core_commit_uops_2_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_2_prs2_0 = io_core_commit_uops_2_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_2_prs3_0 = io_core_commit_uops_2_prs3; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_2_ppred_0 = io_core_commit_uops_2_ppred; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_prs1_busy_0 = io_core_commit_uops_2_prs1_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_prs2_busy_0 = io_core_commit_uops_2_prs2_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_prs3_busy_0 = io_core_commit_uops_2_prs3_busy; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_ppred_busy_0 = io_core_commit_uops_2_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_commit_uops_2_stale_pdst_0 = io_core_commit_uops_2_stale_pdst; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_exception_0 = io_core_commit_uops_2_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_commit_uops_2_exc_cause_0 = io_core_commit_uops_2_exc_cause; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_bypassable_0 = io_core_commit_uops_2_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_uops_2_mem_cmd_0 = io_core_commit_uops_2_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_mem_size_0 = io_core_commit_uops_2_mem_size; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_mem_signed_0 = io_core_commit_uops_2_mem_signed; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_fence_0 = io_core_commit_uops_2_is_fence; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_fencei_0 = io_core_commit_uops_2_is_fencei; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_amo_0 = io_core_commit_uops_2_is_amo; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_uses_ldq_0 = io_core_commit_uops_2_uses_ldq; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_uses_stq_0 = io_core_commit_uops_2_uses_stq; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_sys_pc2epc_0 = io_core_commit_uops_2_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_is_unique_0 = io_core_commit_uops_2_is_unique; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_flush_on_commit_0 = io_core_commit_uops_2_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_ldst_is_rs1_0 = io_core_commit_uops_2_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_2_ldst_0 = io_core_commit_uops_2_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_2_lrs1_0 = io_core_commit_uops_2_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_2_lrs2_0 = io_core_commit_uops_2_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_commit_uops_2_lrs3_0 = io_core_commit_uops_2_lrs3; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_ldst_val_0 = io_core_commit_uops_2_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_dst_rtype_0 = io_core_commit_uops_2_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_lrs1_rtype_0 = io_core_commit_uops_2_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_lrs2_rtype_0 = io_core_commit_uops_2_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_frs3_en_0 = io_core_commit_uops_2_frs3_en; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_fp_val_0 = io_core_commit_uops_2_fp_val; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_fp_single_0 = io_core_commit_uops_2_fp_single; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_xcpt_pf_if_0 = io_core_commit_uops_2_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_xcpt_ae_if_0 = io_core_commit_uops_2_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_xcpt_ma_if_0 = io_core_commit_uops_2_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_bp_debug_if_0 = io_core_commit_uops_2_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_commit_uops_2_bp_xcpt_if_0 = io_core_commit_uops_2_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_debug_fsrc_0 = io_core_commit_uops_2_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_commit_uops_2_debug_tsrc_0 = io_core_commit_uops_2_debug_tsrc; // @[lsu.scala:201:7]
wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:201:7]
wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_debug_insts_0_0 = io_core_commit_debug_insts_0; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_debug_insts_1_0 = io_core_commit_debug_insts_1; // @[lsu.scala:201:7]
wire [31:0] io_core_commit_debug_insts_2_0 = io_core_commit_debug_insts_2; // @[lsu.scala:201:7]
wire io_core_commit_rbk_valids_0_0 = io_core_commit_rbk_valids_0; // @[lsu.scala:201:7]
wire io_core_commit_rbk_valids_1_0 = io_core_commit_rbk_valids_1; // @[lsu.scala:201:7]
wire io_core_commit_rbk_valids_2_0 = io_core_commit_rbk_valids_2; // @[lsu.scala:201:7]
wire io_core_commit_rollback_0 = io_core_commit_rollback; // @[lsu.scala:201:7]
wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:201:7]
wire [63:0] io_core_commit_debug_wdata_1_0 = io_core_commit_debug_wdata_1; // @[lsu.scala:201:7]
wire [63:0] io_core_commit_debug_wdata_2_0 = io_core_commit_debug_wdata_2; // @[lsu.scala:201:7]
wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:201:7]
wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:201:7]
wire [15:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:201:7]
wire [15:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:201:7]
wire [6:0] io_core_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc; // @[lsu.scala:201:7]
wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:201:7]
wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_core_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_core_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_core_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:201:7]
wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_core_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:201:7]
wire [6:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:201:7]
wire [6:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:201:7]
wire [6:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:201:7]
wire [4:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:201:7]
wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_valid_0 = io_core_brupdate_b2_valid; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:201:7]
wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:201:7]
wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:201:7]
wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:201:7]
wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:201:7]
wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:201:7]
wire [6:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:201:7]
wire [6:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:201:7]
wire io_core_exception_0 = io_core_exception; // @[lsu.scala:201:7]
wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:201:7]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:201:7]
wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:201:7]
wire [6:0] io_dmem_resp_0_bits_uop_uopc_0 = io_dmem_resp_0_bits_uop_uopc; // @[lsu.scala:201:7]
wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:201:7]
wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_dmem_resp_0_bits_uop_iq_type_0 = io_dmem_resp_0_bits_uop_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_dmem_resp_0_bits_uop_fu_code_0 = io_dmem_resp_0_bits_uop_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type_0 = io_dmem_resp_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel_0 = io_dmem_resp_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn_0 = io_dmem_resp_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_resp_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_resp_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_ctrl_is_load_0 = io_dmem_resp_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_ctrl_is_sta_0 = io_dmem_resp_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_ctrl_is_std_0 = io_dmem_resp_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_iw_state_0 = io_dmem_resp_0_bits_uop_iw_state; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_iw_p1_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_iw_p2_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_br_0 = io_dmem_resp_0_bits_uop_is_br; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_jalr_0 = io_dmem_resp_0_bits_uop_is_jalr; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_jal_0 = io_dmem_resp_0_bits_uop_is_jal; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:201:7]
wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_dmem_resp_0_bits_uop_csr_addr_0 = io_dmem_resp_0_bits_uop_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:201:7]
wire [6:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:201:7]
wire [6:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:201:7]
wire [6:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:201:7]
wire [4:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:201:7]
wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_bypassable_0 = io_dmem_resp_0_bits_uop_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:201:7]
wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_ldst_val_0 = io_dmem_resp_0_bits_uop_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_fp_single_0 = io_dmem_resp_0_bits_uop_fp_single; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7]
wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:201:7]
wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:201:7]
wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:201:7]
wire [6:0] io_dmem_nack_0_bits_uop_uopc_0 = io_dmem_nack_0_bits_uop_uopc; // @[lsu.scala:201:7]
wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:201:7]
wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:201:7]
wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:201:7]
wire [2:0] io_dmem_nack_0_bits_uop_iq_type_0 = io_dmem_nack_0_bits_uop_iq_type; // @[lsu.scala:201:7]
wire [9:0] io_dmem_nack_0_bits_uop_fu_code_0 = io_dmem_nack_0_bits_uop_fu_code; // @[lsu.scala:201:7]
wire [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type_0 = io_dmem_nack_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7]
wire [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7]
wire [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel_0 = io_dmem_nack_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7]
wire [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn_0 = io_dmem_nack_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_nack_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7]
wire [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_nack_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_ctrl_is_load_0 = io_dmem_nack_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_ctrl_is_sta_0 = io_dmem_nack_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_ctrl_is_std_0 = io_dmem_nack_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_iw_state_0 = io_dmem_nack_0_bits_uop_iw_state; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_iw_p1_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_iw_p2_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_br_0 = io_dmem_nack_0_bits_uop_is_br; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_jalr_0 = io_dmem_nack_0_bits_uop_is_jalr; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_jal_0 = io_dmem_nack_0_bits_uop_is_jal; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:201:7]
wire [15:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:201:7]
wire [3:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:201:7]
wire [4:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:201:7]
wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:201:7]
wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:201:7]
wire [11:0] io_dmem_nack_0_bits_uop_csr_addr_0 = io_dmem_nack_0_bits_uop_csr_addr; // @[lsu.scala:201:7]
wire [6:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:201:7]
wire [4:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:201:7]
wire [4:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:201:7]
wire [6:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:201:7]
wire [6:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:201:7]
wire [6:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:201:7]
wire [6:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:201:7]
wire [4:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:201:7]
wire [6:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:201:7]
wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_bypassable_0 = io_dmem_nack_0_bits_uop_bypassable; // @[lsu.scala:201:7]
wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7]
wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:201:7]
wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:201:7]
wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:201:7]
wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_ldst_val_0 = io_dmem_nack_0_bits_uop_ldst_val; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_fp_single_0 = io_dmem_nack_0_bits_uop_fp_single; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7]
wire [1:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7]
wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:201:7]
wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:201:7]
wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:201:7]
wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:201:7]
wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:201:7]
wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:201:7]
wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:201:7]
wire [2:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:201:7]
wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:201:7]
wire [127:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:201:7]
wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:201:7]
wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:201:7]
wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:201:7]
wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:201:7]
wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:201:7]
wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:201:7]
wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:201:7]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:201:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:201:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:201:7]
wire [15:0] io_core_exe_0_req_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:201:7]
wire [15:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:201:7]
wire [15:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:201:7]
wire [15:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:383:33]
wire [15:0] exe_req_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:383:25]
wire [15:0] exe_tlb_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] exe_tlb_uop_uop_1_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] _exe_tlb_uop_T_3_br_mask = 16'h0; // @[lsu.scala:602:24]
wire [15:0] dmem_req_0_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32]
wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69]
wire [15:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:918:90]
wire [15:0] _mem_stq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:922:89]
wire [15:0] lcam_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_0_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_1_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_2_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_3_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_4_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_5_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_6_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_7_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_8_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_9_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_10_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_11_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_12_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_13_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_14_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_15_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_16_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_17_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_18_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_19_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_20_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_21_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_22_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] stq_23_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:201:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:201:7]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:201:7]
wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_status_ube = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_status_upie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_status_hie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_status_uie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:201:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_predicated = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_predicated = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_ppred_busy_0 = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_predicated = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7]
wire io_core_dis_uops_0_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_dis_uops_1_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_dis_uops_2_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7]
wire io_core_clr_unsafe_0_valid = 1'h0; // @[lsu.scala:201:7]
wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_resp_bits_dv = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_resp_bits_has_data = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_ordered = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:201:7]
wire io_hellacache_clock_enabled = 1'h0; // @[lsu.scala:201:7]
wire _exe_req_WIRE_0_bits_predicated = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:33]
wire _exe_req_WIRE_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:33]
wire exe_req_0_bits_predicated = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:25]
wire exe_req_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:25]
wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_8 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_9 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_10 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_11 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_12 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_13 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_14 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_15 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_16 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_17 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_18 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_19 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_20 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_21 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_22 = 1'h0; // @[lsu.scala:396:44]
wire _block_load_mask_WIRE_23 = 1'h0; // @[lsu.scala:396:44]
wire ldq_incoming_e_0_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:263:49]
wire _can_fire_sta_retry_T_4 = 1'h0; // @[lsu.scala:482:75]
wire _can_fire_sta_retry_T_6 = 1'h0; // @[lsu.scala:483:75]
wire _can_fire_sta_retry_WIRE_0 = 1'h0; // @[lsu.scala:263:49]
wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:263:49]
wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:263:49]
wire _will_fire_load_incoming_0_will_fire_T = 1'h0; // @[lsu.scala:533:51]
wire _will_fire_load_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48]
wire _will_fire_load_incoming_0_will_fire_T_4 = 1'h0; // @[lsu.scala:534:52]
wire _will_fire_load_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49]
wire _will_fire_load_incoming_0_will_fire_T_8 = 1'h0; // @[lsu.scala:535:50]
wire _will_fire_load_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47]
wire _will_fire_load_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51]
wire _will_fire_load_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_load_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46]
wire _will_fire_stad_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47]
wire _will_fire_stad_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51]
wire _will_fire_stad_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_stad_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46]
wire _will_fire_sta_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47]
wire _will_fire_sta_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46]
wire _will_fire_std_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48]
wire _will_fire_std_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49]
wire _will_fire_std_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47]
wire _will_fire_std_incoming_0_T = 1'h0; // @[lsu.scala:537:46]
wire _will_fire_std_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46]
wire _will_fire_std_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46]
wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49]
wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47]
wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:538:46]
wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:539:46]
wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48]
wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47]
wire _will_fire_release_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:537:46]
wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:539:46]
wire _will_fire_release_0_T_9 = 1'h0; // @[lsu.scala:540:46]
wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49]
wire _will_fire_hella_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46]
wire _will_fire_hella_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46]
wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48]
wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49]
wire _will_fire_hella_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:537:46]
wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:538:46]
wire _will_fire_hella_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46]
wire _will_fire_load_retry_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_load_retry_0_T_9 = 1'h0; // @[lsu.scala:540:46]
wire _will_fire_sta_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47]
wire _will_fire_sta_retry_0_T_6 = 1'h0; // @[lsu.scala:539:46]
wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48]
wire _will_fire_load_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:537:46]
wire _will_fire_load_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46]
wire _will_fire_store_commit_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48]
wire _will_fire_store_commit_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49]
wire _will_fire_store_commit_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48]
wire _will_fire_store_commit_0_T = 1'h0; // @[lsu.scala:537:46]
wire _will_fire_store_commit_0_T_3 = 1'h0; // @[lsu.scala:538:46]
wire _will_fire_store_commit_0_T_9 = 1'h0; // @[lsu.scala:540:46]
wire exe_tlb_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire exe_tlb_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire exe_tlb_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire exe_tlb_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire exe_tlb_uop_uop_1_is_rvc = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_br = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_jalr = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_jal = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_sfb = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_edge_inst = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_taken = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_exception = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_bypassable = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_mem_signed = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_fence = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_fencei = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_amo = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_uses_stq = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_is_unique = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_ldst_val = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_frs3_en = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_fp_val = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_fp_single = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_uop_1_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire exe_tlb_uop_cs_1_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire exe_tlb_uop_cs_1_is_load = 1'h0; // @[consts.scala:279:18]
wire exe_tlb_uop_cs_1_is_sta = 1'h0; // @[consts.scala:279:18]
wire exe_tlb_uop_cs_1_is_std = 1'h0; // @[consts.scala:279:18]
wire _exe_tlb_uop_T_3_is_rvc = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_ctrl_fcn_dw = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_ctrl_is_load = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_ctrl_is_sta = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_ctrl_is_std = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_iw_p1_poisoned = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_iw_p2_poisoned = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_br = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_jalr = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_jal = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_sfb = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_edge_inst = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_taken = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_prs1_busy = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_prs2_busy = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_prs3_busy = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_ppred_busy = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_exception = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_bypassable = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_mem_signed = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_fence = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_fencei = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_amo = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_uses_ldq = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_uses_stq = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_sys_pc2epc = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_is_unique = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_flush_on_commit = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_ldst_is_rs1 = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_ldst_val = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_frs3_en = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_fp_val = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_fp_single = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_xcpt_pf_if = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_xcpt_ae_if = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_xcpt_ma_if = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_bp_debug_if = 1'h0; // @[lsu.scala:602:24]
wire _exe_tlb_uop_T_3_bp_xcpt_if = 1'h0; // @[lsu.scala:602:24]
wire _exe_sfence_WIRE_valid = 1'h0; // @[lsu.scala:615:43]
wire _exe_sfence_WIRE_bits_rs1 = 1'h0; // @[lsu.scala:615:43]
wire _exe_sfence_WIRE_bits_rs2 = 1'h0; // @[lsu.scala:615:43]
wire _exe_sfence_WIRE_bits_asid = 1'h0; // @[lsu.scala:615:43]
wire _exe_sfence_WIRE_bits_hv = 1'h0; // @[lsu.scala:615:43]
wire _exe_sfence_WIRE_bits_hg = 1'h0; // @[lsu.scala:615:43]
wire exe_sfence_bits_hv = 1'h0; // @[lsu.scala:615:28]
wire exe_sfence_bits_hg = 1'h0; // @[lsu.scala:615:28]
wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:709:86]
wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_8 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_9 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_10 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_11 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_12 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_13 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_14 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_15 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_16 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_17 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_18 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_19 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_20 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_21 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_22 = 1'h0; // @[lsu.scala:755:44]
wire _s0_executing_loads_WIRE_23 = 1'h0; // @[lsu.scala:755:44]
wire dmem_req_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire dmem_req_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire dmem_req_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire dmem_req_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire dmem_req_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19]
wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19]
wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19]
wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19]
wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19]
wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19]
wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23]
wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:918:90]
wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:918:90]
wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:922:89]
wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:922:89]
wire _clr_bsy_valid_WIRE_0 = 1'h0; // @[lsu.scala:263:49]
wire lcam_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire lcam_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire lcam_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire lcam_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire lcam_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _ldst_addr_matches_WIRE_0 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_1 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_2 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_3 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_4 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_5 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_6 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_7 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_8 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_9 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_10 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_11 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_12 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_13 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_14 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_15 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_16 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_17 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_18 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_19 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_20 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_21 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_22 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_23 = 1'h0; // @[lsu.scala:1050:60]
wire _ldst_addr_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_8 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_9 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_10 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_11 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_12 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_13 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_14 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_15 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_16 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_17 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_18 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_19 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_20 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_21 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_22 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_addr_matches_WIRE_1_0_23 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_0 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_1 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_2 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_3 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_4 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_5 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_6 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_7 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_8 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_9 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_10 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_11 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_12 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_13 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_14 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_15 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_16 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_17 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_18 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_19 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_20 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_21 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_22 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_23 = 1'h0; // @[lsu.scala:1052:60]
wire _ldst_forward_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_8 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_9 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_10 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_11 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_12 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_13 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_14 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_15 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_16 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_17 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_18 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_19 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_20 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_21 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_22 = 1'h0; // @[lsu.scala:263:49]
wire _ldst_forward_matches_WIRE_1_0_23 = 1'h0; // @[lsu.scala:263:49]
wire _failed_loads_WIRE_0 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_1 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_2 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_3 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_4 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_5 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_6 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_7 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_8 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_9 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_10 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_11 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_12 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_13 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_14 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_15 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_16 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_17 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_18 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_19 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_20 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_21 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_22 = 1'h0; // @[lsu.scala:1054:42]
wire _failed_loads_WIRE_23 = 1'h0; // @[lsu.scala:1054:42]
wire _nacking_loads_WIRE_0 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_1 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_2 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_3 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_4 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_5 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_6 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_7 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_8 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_9 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_10 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_11 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_12 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_13 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_14 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_15 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_16 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_17 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_18 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_19 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_20 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_21 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_22 = 1'h0; // @[lsu.scala:1055:42]
wire _nacking_loads_WIRE_23 = 1'h0; // @[lsu.scala:1055:42]
wire _searcher_is_older_T = 1'h0; // @[util.scala:363:52]
wire _io_core_clr_unsafe_0_valid_T_3 = 1'h0; // @[lsu.scala:1221:107]
wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:263:49]
wire io_core_exe_0_iresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_core_exe_0_iresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_core_exe_0_iresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire io_core_exe_0_fresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_core_exe_0_fresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_core_exe_0_fresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire ldq_bits_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire ldq_bits_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire ldq_bits_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1528:44]
wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1528:44]
wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1528:44]
wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1528:44]
wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1528:44]
wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1528:44]
wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1528:44]
wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1528:44]
wire _st_exc_killed_mask_WIRE_0 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_1 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_2 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_3 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_4 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_5 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_6 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_7 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_8 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_9 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_10 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_11 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_12 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_13 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_14 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_15 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_16 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_17 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_18 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_19 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_20 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_21 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_22 = 1'h0; // @[lsu.scala:1598:44]
wire _st_exc_killed_mask_WIRE_23 = 1'h0; // @[lsu.scala:1598:44]
wire stq_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_1_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_1_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_1_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_1_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_1_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_2_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_2_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_2_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_2_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_2_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_3_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_3_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_3_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_3_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_3_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_4_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_4_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_4_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_4_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_4_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_5_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_5_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_5_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_5_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_5_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_6_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_6_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_6_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_6_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_6_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_7_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_7_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_7_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_7_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_7_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_8_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_8_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_8_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_8_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_8_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_9_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_9_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_9_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_9_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_9_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_10_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_10_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_10_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_10_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_10_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_11_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_11_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_11_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_11_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_11_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_12_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_12_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_12_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_12_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_12_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_13_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_13_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_13_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_13_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_13_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_14_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_14_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_14_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_14_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_14_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_15_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_15_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_15_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_15_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_15_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_16_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_16_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_16_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_16_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_16_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_17_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_17_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_17_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_17_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_17_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_18_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_18_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_18_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_18_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_18_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_19_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_19_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_19_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_19_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_19_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_20_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_20_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_20_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_20_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_20_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_21_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_21_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_21_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_21_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_21_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_22_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_22_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_22_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_22_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_22_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire stq_23_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire stq_23_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire stq_23_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire stq_23_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire stq_23_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:201:7]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:201:7]
wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:201:7]
wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:201:7]
wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:201:7]
wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69]
wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7]
wire [1:0] io_hellacache_resp_bits_dprv = 2'h0; // @[lsu.scala:201:7]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:33]
wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:33]
wire [1:0] exe_req_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:25]
wire [1:0] exe_tlb_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] exe_tlb_uop_uop_1_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_cs_1_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] _exe_tlb_uop_T_3_ctrl_op1_sel = 2'h0; // @[lsu.scala:602:24]
wire [1:0] _exe_tlb_uop_T_3_iw_state = 2'h0; // @[lsu.scala:602:24]
wire [1:0] _exe_tlb_uop_T_3_rxq_idx = 2'h0; // @[lsu.scala:602:24]
wire [1:0] _exe_tlb_uop_T_3_mem_size = 2'h0; // @[lsu.scala:602:24]
wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = 2'h0; // @[lsu.scala:602:24]
wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = 2'h0; // @[lsu.scala:602:24]
wire [1:0] _exe_tlb_uop_T_3_debug_fsrc = 2'h0; // @[lsu.scala:602:24]
wire [1:0] _exe_tlb_uop_T_3_debug_tsrc = 2'h0; // @[lsu.scala:602:24]
wire [1:0] dmem_req_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] dmem_req_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:918:90]
wire [1:0] _mem_stq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:922:89]
wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:922:89]
wire [1:0] lcam_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] lcam_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_1_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_2_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_3_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_4_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_5_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_6_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_7_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_8_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_9_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_10_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_11_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_12_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_13_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_14_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_15_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_16_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_17_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_18_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_19_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_20_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_21_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_22_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] stq_23_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:201:7]
wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:201:7]
wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:33]
wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:383:33]
wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:383:33]
wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:383:33]
wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:383:33]
wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:383:33]
wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:383:33]
wire [6:0] exe_req_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:383:25]
wire [6:0] exe_req_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:383:25]
wire [6:0] exe_tlb_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_1_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_1_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_1_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_1_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_1_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_1_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] exe_tlb_uop_uop_1_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] _exe_tlb_uop_T_3_uopc = 7'h0; // @[lsu.scala:602:24]
wire [6:0] _exe_tlb_uop_T_3_rob_idx = 7'h0; // @[lsu.scala:602:24]
wire [6:0] _exe_tlb_uop_T_3_pdst = 7'h0; // @[lsu.scala:602:24]
wire [6:0] _exe_tlb_uop_T_3_prs1 = 7'h0; // @[lsu.scala:602:24]
wire [6:0] _exe_tlb_uop_T_3_prs2 = 7'h0; // @[lsu.scala:602:24]
wire [6:0] _exe_tlb_uop_T_3_prs3 = 7'h0; // @[lsu.scala:602:24]
wire [6:0] _exe_tlb_uop_T_3_stale_pdst = 7'h0; // @[lsu.scala:602:24]
wire [6:0] dmem_req_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] dmem_req_0_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] dmem_req_0_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] dmem_req_0_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] dmem_req_0_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] dmem_req_0_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] dmem_req_0_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] _mem_ldq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:918:90]
wire [6:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:918:90]
wire [6:0] _mem_ldq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:918:90]
wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:918:90]
wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:918:90]
wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:918:90]
wire [6:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:918:90]
wire [6:0] _mem_stq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:922:89]
wire [6:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:922:89]
wire [6:0] _mem_stq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:922:89]
wire [6:0] _mem_stq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:922:89]
wire [6:0] _mem_stq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:922:89]
wire [6:0] _mem_stq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:922:89]
wire [6:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:922:89]
wire [6:0] lcam_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] lcam_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] lcam_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] lcam_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] lcam_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] lcam_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] lcam_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_0_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_0_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_0_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_0_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_0_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_0_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_1_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_1_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_1_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_1_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_1_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_1_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_1_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_2_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_2_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_2_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_2_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_2_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_2_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_2_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_3_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_3_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_3_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_3_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_3_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_3_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_3_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_4_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_4_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_4_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_4_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_4_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_4_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_4_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_5_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_5_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_5_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_5_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_5_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_5_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_5_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_6_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_6_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_6_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_6_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_6_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_6_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_6_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_7_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_7_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_7_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_7_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_7_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_7_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_7_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_8_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_8_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_8_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_8_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_8_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_8_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_8_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_9_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_9_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_9_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_9_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_9_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_9_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_9_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_10_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_10_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_10_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_10_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_10_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_10_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_10_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_11_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_11_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_11_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_11_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_11_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_11_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_11_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_12_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_12_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_12_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_12_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_12_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_12_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_12_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_13_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_13_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_13_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_13_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_13_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_13_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_13_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_14_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_14_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_14_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_14_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_14_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_14_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_14_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_15_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_15_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_15_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_15_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_15_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_15_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_15_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_16_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_16_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_16_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_16_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_16_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_16_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_16_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_17_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_17_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_17_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_17_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_17_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_17_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_17_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_18_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_18_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_18_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_18_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_18_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_18_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_18_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_19_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_19_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_19_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_19_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_19_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_19_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_19_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_20_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_20_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_20_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_20_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_20_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_20_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_20_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_21_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_21_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_21_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_21_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_21_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_21_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_21_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_22_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_22_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_22_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_22_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_22_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_22_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_22_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_23_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_23_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_23_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_23_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_23_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_23_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] stq_23_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_uop_ppred_0 = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_0_bits_ppred = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_1_bits_ppred = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_uops_2_bits_ppred = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:201:7]
wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:201:7]
wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:33]
wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:383:33]
wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:383:33]
wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:383:33]
wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:383:33]
wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:33]
wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:33]
wire [4:0] exe_req_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:25]
wire [4:0] exe_req_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:25]
wire [4:0] ldq_incoming_e_0_bits_uop_ppred = 5'h0; // @[lsu.scala:263:49]
wire [4:0] exe_tlb_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] exe_tlb_uop_uop_1_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_1_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_1_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_1_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_1_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_uop_1_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] exe_tlb_uop_cs_1_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] _exe_tlb_uop_T_3_ctrl_op_fcn = 5'h0; // @[lsu.scala:602:24]
wire [4:0] _exe_tlb_uop_T_3_ftq_idx = 5'h0; // @[lsu.scala:602:24]
wire [4:0] _exe_tlb_uop_T_3_ldq_idx = 5'h0; // @[lsu.scala:602:24]
wire [4:0] _exe_tlb_uop_T_3_stq_idx = 5'h0; // @[lsu.scala:602:24]
wire [4:0] _exe_tlb_uop_T_3_ppred = 5'h0; // @[lsu.scala:602:24]
wire [4:0] _exe_tlb_uop_T_3_mem_cmd = 5'h0; // @[lsu.scala:602:24]
wire [4:0] _exe_cmd_T_5 = 5'h0; // @[lsu.scala:638:23]
wire [4:0] dmem_req_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] dmem_req_0_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] dmem_req_0_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] dmem_req_0_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] dmem_req_0_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] dmem_req_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] dmem_req_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ppred = 5'h0; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_uop_ppred = 5'h0; // @[util.scala:106:23]
wire [4:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_ldq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_ldq_e_WIRE_bits_youngest_stq_idx = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 5'h0; // @[lsu.scala:918:90]
wire [4:0] _mem_stq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:922:89]
wire [4:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:922:89]
wire [4:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:922:89]
wire [4:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:922:89]
wire [4:0] _mem_stq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:922:89]
wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:922:89]
wire [4:0] lcam_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] lcam_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] lcam_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] lcam_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] lcam_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] lcam_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] lcam_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_0_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_0_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_0_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_0_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_1_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_1_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_1_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_1_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_1_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_1_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_1_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_2_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_2_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_2_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_2_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_2_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_2_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_2_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_3_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_3_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_3_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_3_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_3_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_3_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_3_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_4_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_4_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_4_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_4_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_4_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_4_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_4_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_5_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_5_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_5_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_5_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_5_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_5_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_5_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_6_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_6_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_6_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_6_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_6_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_6_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_6_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_7_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_7_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_7_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_7_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_7_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_7_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_7_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_8_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_8_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_8_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_8_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_8_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_8_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_8_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_9_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_9_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_9_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_9_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_9_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_9_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_9_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_10_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_10_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_10_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_10_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_10_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_10_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_10_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_11_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_11_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_11_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_11_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_11_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_11_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_11_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_12_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_12_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_12_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_12_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_12_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_12_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_12_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_13_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_13_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_13_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_13_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_13_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_13_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_13_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_14_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_14_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_14_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_14_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_14_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_14_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_14_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_15_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_15_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_15_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_15_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_15_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_15_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_15_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_16_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_16_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_16_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_16_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_16_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_16_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_16_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_17_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_17_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_17_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_17_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_17_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_17_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_17_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_18_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_18_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_18_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_18_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_18_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_18_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_18_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_19_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_19_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_19_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_19_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_19_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_19_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_19_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_20_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_20_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_20_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_20_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_20_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_20_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_20_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_21_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_21_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_21_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_21_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_21_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_21_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_21_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_22_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_22_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_22_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_22_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_22_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_22_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_22_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] stq_23_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_23_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_23_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_23_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_23_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_23_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] stq_23_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:201:7]
wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:201:7]
wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18]
wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18]
wire io_core_exe_0_iresp_ready = 1'h1; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_ready = 1'h1; // @[lsu.scala:201:7]
wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:201:7]
wire _can_fire_sta_retry_T_7 = 1'h1; // @[lsu.scala:482:34]
wire _will_fire_load_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35]
wire _will_fire_load_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35]
wire _will_fire_load_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35]
wire _will_fire_load_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_load_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34]
wire _will_fire_load_incoming_0_T_11 = 1'h1; // @[lsu.scala:540:31]
wire _will_fire_stad_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35]
wire _will_fire_stad_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_stad_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34]
wire _will_fire_sta_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35]
wire _will_fire_sta_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34]
wire _will_fire_std_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35]
wire _will_fire_std_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35]
wire _will_fire_std_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35]
wire _will_fire_std_incoming_0_T_1 = 1'h1; // @[lsu.scala:537:34]
wire _will_fire_std_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34]
wire _will_fire_std_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34]
wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35]
wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35]
wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:538:34]
wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:539:34]
wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35]
wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35]
wire _will_fire_release_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:537:34]
wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:539:34]
wire _will_fire_release_0_T_10 = 1'h1; // @[lsu.scala:540:34]
wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35]
wire _will_fire_hella_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34]
wire _will_fire_hella_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34]
wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35]
wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35]
wire _will_fire_hella_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34]
wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:538:34]
wire _will_fire_hella_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34]
wire _will_fire_load_retry_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_load_retry_0_T_10 = 1'h1; // @[lsu.scala:540:34]
wire _will_fire_sta_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35]
wire _will_fire_sta_retry_0_T_7 = 1'h1; // @[lsu.scala:539:34]
wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35]
wire _will_fire_load_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34]
wire _will_fire_load_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34]
wire _will_fire_store_commit_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35]
wire _will_fire_store_commit_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35]
wire _will_fire_store_commit_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35]
wire _will_fire_store_commit_0_T_1 = 1'h1; // @[lsu.scala:537:34]
wire _will_fire_store_commit_0_T_4 = 1'h1; // @[lsu.scala:538:34]
wire _will_fire_store_commit_0_T_10 = 1'h1; // @[lsu.scala:540:34]
wire _dmem_req_0_valid_T_8 = 1'h1; // @[lsu.scala:806:86]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_hellacache_resp_bits_data_word_bypass = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_hellacache_resp_bits_data_raw = 64'h0; // @[lsu.scala:201:7]
wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:201:7]
wire [63:0] _exe_req_WIRE_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:33]
wire [63:0] exe_req_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:25]
wire [63:0] exe_tlb_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] exe_tlb_uop_uop_1_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] _exe_tlb_uop_T_3_exc_cause = 64'h0; // @[lsu.scala:602:24]
wire [63:0] dmem_req_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32]
wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32]
wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32]
wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13]
wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13]
wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13]
wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:918:90]
wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:918:90]
wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:922:89]
wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:922:89]
wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:922:89]
wire [63:0] lcam_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_1_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_2_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_3_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_4_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_5_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_6_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_7_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_8_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_9_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_10_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_11_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_12_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_13_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_14_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_15_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_16_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_17_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_18_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_19_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_20_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_21_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_22_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] stq_23_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:201:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:201:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:201:7]
wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:33]
wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:383:33]
wire [3:0] exe_req_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:25]
wire [3:0] exe_req_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:383:25]
wire [3:0] exe_tlb_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] exe_tlb_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] exe_tlb_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] exe_tlb_uop_uop_1_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] exe_tlb_uop_uop_1_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] exe_tlb_uop_cs_1_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] _exe_tlb_uop_T_3_ctrl_br_type = 4'h0; // @[lsu.scala:602:24]
wire [3:0] _exe_tlb_uop_T_3_br_tag = 4'h0; // @[lsu.scala:602:24]
wire [3:0] dmem_req_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] dmem_req_0_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] dmem_req_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] _mem_ldq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:918:90]
wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:918:90]
wire [3:0] _mem_stq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:922:89]
wire [3:0] _mem_stq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:922:89]
wire [3:0] lcam_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] lcam_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] lcam_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_0_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_1_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_1_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_1_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_2_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_2_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_2_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_3_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_3_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_3_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_4_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_4_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_4_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_5_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_5_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_5_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_6_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_6_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_6_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_7_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_7_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_7_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_8_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_8_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_8_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_9_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_9_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_9_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_10_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_10_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_10_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_11_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_11_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_11_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_12_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_12_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_12_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_13_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_13_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_13_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_14_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_14_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_14_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_15_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_15_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_15_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_16_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_16_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_16_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_17_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_17_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_17_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_18_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_18_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_18_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_19_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_19_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_19_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_20_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_20_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_20_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_21_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_21_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_21_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_22_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_22_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_22_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] stq_23_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_23_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] stq_23_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:201:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:201:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:201:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:201:7]
wire [1:0] exe_tlb_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] exe_tlb_uop_uop_1_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] _exe_tlb_uop_T_3_dst_rtype = 2'h2; // @[lsu.scala:602:24]
wire [1:0] dmem_req_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] lcam_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_1_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_2_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_3_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_4_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_5_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_6_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_7_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_8_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_9_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_10_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_11_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_12_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_13_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_14_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_15_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_16_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_17_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_18_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_19_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_20_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_21_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_22_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] stq_23_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:201:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:201:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7]
wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:33]
wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:33]
wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:33]
wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:33]
wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:33]
wire [5:0] exe_req_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:25]
wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:25]
wire [5:0] exe_tlb_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_1_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_1_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_1_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_1_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] exe_tlb_uop_uop_1_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] _exe_tlb_uop_T_3_pc_lob = 6'h0; // @[lsu.scala:602:24]
wire [5:0] _exe_tlb_uop_T_3_ldst = 6'h0; // @[lsu.scala:602:24]
wire [5:0] _exe_tlb_uop_T_3_lrs1 = 6'h0; // @[lsu.scala:602:24]
wire [5:0] _exe_tlb_uop_T_3_lrs2 = 6'h0; // @[lsu.scala:602:24]
wire [5:0] _exe_tlb_uop_T_3_lrs3 = 6'h0; // @[lsu.scala:602:24]
wire [5:0] dmem_req_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] dmem_req_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] dmem_req_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] dmem_req_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] dmem_req_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:918:90]
wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:918:90]
wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:918:90]
wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:918:90]
wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:918:90]
wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:922:89]
wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:922:89]
wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:922:89]
wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:922:89]
wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:922:89]
wire [5:0] lcam_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] lcam_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] lcam_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] lcam_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] lcam_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_1_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_1_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_1_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_1_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_1_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_2_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_2_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_2_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_2_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_2_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_3_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_3_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_3_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_3_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_3_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_4_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_4_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_4_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_4_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_4_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_5_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_5_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_5_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_5_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_5_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_6_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_6_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_6_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_6_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_6_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_7_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_7_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_7_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_7_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_7_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_8_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_8_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_8_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_8_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_8_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_9_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_9_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_9_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_9_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_9_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_10_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_10_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_10_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_10_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_10_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_11_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_11_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_11_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_11_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_11_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_12_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_12_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_12_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_12_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_12_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_13_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_13_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_13_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_13_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_13_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_14_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_14_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_14_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_14_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_14_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_15_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_15_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_15_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_15_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_15_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_16_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_16_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_16_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_16_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_16_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_17_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_17_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_17_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_17_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_17_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_18_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_18_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_18_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_18_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_18_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_19_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_19_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_19_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_19_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_19_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_20_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_20_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_20_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_20_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_20_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_21_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_21_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_21_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_21_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_21_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_22_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_22_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_22_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_22_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_22_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_23_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_23_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_23_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_23_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] stq_23_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7]
wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:201:7]
wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:33]
wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:33]
wire [31:0] exe_req_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:25]
wire [31:0] exe_req_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:25]
wire [31:0] exe_tlb_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] exe_tlb_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] exe_tlb_uop_uop_1_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] exe_tlb_uop_uop_1_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] _exe_tlb_uop_T_3_inst = 32'h0; // @[lsu.scala:602:24]
wire [31:0] _exe_tlb_uop_T_3_debug_inst = 32'h0; // @[lsu.scala:602:24]
wire [31:0] dmem_req_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] dmem_req_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32]
wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32]
wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69]
wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:918:90]
wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:918:90]
wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:922:89]
wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:922:89]
wire [31:0] lcam_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] lcam_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_1_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_1_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_2_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_2_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_3_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_3_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_4_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_4_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_5_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_5_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_6_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_6_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_7_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_7_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_8_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_8_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_9_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_9_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_10_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_10_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_11_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_11_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_12_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_12_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_13_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_13_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_14_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_14_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_15_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_15_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_16_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_16_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_17_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_17_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_18_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_18_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_19_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_19_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_20_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_20_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_21_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_21_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_22_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_22_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_23_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] stq_23_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [39:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7]
wire [39:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7]
wire [39:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7]
wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:201:7]
wire [39:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:33]
wire [39:0] exe_req_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:25]
wire [39:0] exe_tlb_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] exe_tlb_uop_uop_1_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] _exe_tlb_uop_T_3_debug_pc = 40'h0; // @[lsu.scala:602:24]
wire [39:0] dmem_req_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:918:90]
wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:918:90]
wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:922:89]
wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:922:89]
wire [39:0] lcam_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_1_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_2_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_3_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_4_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_5_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_6_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_7_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_8_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_9_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_10_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_11_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_12_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_13_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_14_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_15_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_16_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_17_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_18_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_19_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_20_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_21_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_22_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] stq_23_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7]
wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:33]
wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:33]
wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:33]
wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:33]
wire [2:0] exe_req_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:25]
wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:25]
wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:25]
wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:25]
wire [2:0] exe_tlb_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] exe_tlb_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] exe_tlb_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] exe_tlb_uop_uop_1_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_uop_1_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_uop_1_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_uop_1_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] exe_tlb_uop_cs_1_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] exe_tlb_uop_cs_1_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] exe_tlb_uop_cs_1_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] _exe_tlb_uop_T_3_iq_type = 3'h0; // @[lsu.scala:602:24]
wire [2:0] _exe_tlb_uop_T_3_ctrl_op2_sel = 3'h0; // @[lsu.scala:602:24]
wire [2:0] _exe_tlb_uop_T_3_ctrl_imm_sel = 3'h0; // @[lsu.scala:602:24]
wire [2:0] _exe_tlb_uop_T_3_ctrl_csr_cmd = 3'h0; // @[lsu.scala:602:24]
wire [2:0] dmem_req_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] dmem_req_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] dmem_req_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] dmem_req_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] dmem_req_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] dmem_req_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] dmem_req_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] _mem_ldq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:918:90]
wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:918:90]
wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:918:90]
wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:918:90]
wire [2:0] _mem_stq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:922:89]
wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:922:89]
wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:922:89]
wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:922:89]
wire [2:0] lcam_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] lcam_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] lcam_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] lcam_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] lcam_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] lcam_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] lcam_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_1_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_1_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_1_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_1_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_1_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_1_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_1_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_2_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_2_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_2_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_2_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_2_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_2_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_2_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_3_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_3_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_3_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_3_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_3_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_3_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_3_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_4_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_4_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_4_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_4_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_4_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_4_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_4_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_5_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_5_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_5_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_5_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_5_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_5_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_5_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_6_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_6_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_6_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_6_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_6_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_6_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_6_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_7_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_7_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_7_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_7_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_7_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_7_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_7_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_8_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_8_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_8_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_8_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_8_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_8_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_8_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_9_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_9_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_9_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_9_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_9_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_9_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_9_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_10_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_10_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_10_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_10_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_10_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_10_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_10_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_11_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_11_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_11_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_11_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_11_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_11_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_11_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_12_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_12_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_12_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_12_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_12_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_12_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_12_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_13_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_13_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_13_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_13_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_13_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_13_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_13_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_14_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_14_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_14_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_14_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_14_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_14_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_14_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_15_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_15_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_15_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_15_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_15_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_15_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_15_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_16_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_16_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_16_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_16_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_16_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_16_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_16_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_17_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_17_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_17_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_17_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_17_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_17_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_17_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_18_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_18_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_18_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_18_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_18_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_18_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_18_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_19_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_19_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_19_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_19_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_19_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_19_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_19_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_20_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_20_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_20_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_20_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_20_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_20_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_20_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_21_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_21_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_21_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_21_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_21_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_21_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_21_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_22_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_22_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_22_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_22_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_22_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_22_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_22_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_23_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_23_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_23_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_23_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] stq_23_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_23_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] stq_23_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [9:0] io_core_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7]
wire [9:0] io_core_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7]
wire [9:0] io_core_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7]
wire [9:0] _exe_req_WIRE_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:33]
wire [9:0] exe_req_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:25]
wire [9:0] exe_tlb_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] exe_tlb_uop_uop_1_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] _exe_tlb_uop_T_3_fu_code = 10'h0; // @[lsu.scala:602:24]
wire [9:0] dmem_req_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] _mem_ldq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:918:90]
wire [9:0] _mem_stq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:922:89]
wire [9:0] lcam_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_1_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_2_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_3_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_4_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_5_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_6_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_7_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_8_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_9_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_10_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_11_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_12_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_13_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_14_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_15_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_16_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_17_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_18_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_19_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_20_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_21_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_22_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] stq_23_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [19:0] io_core_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7]
wire [19:0] io_core_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7]
wire [19:0] io_core_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7]
wire [19:0] _exe_req_WIRE_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:33]
wire [19:0] exe_req_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:25]
wire [19:0] exe_tlb_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] exe_tlb_uop_uop_1_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] _exe_tlb_uop_T_3_imm_packed = 20'h0; // @[lsu.scala:602:24]
wire [19:0] dmem_req_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:918:90]
wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:922:89]
wire [19:0] lcam_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_1_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_2_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_3_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_4_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_5_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_6_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_7_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_8_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_9_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_10_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_11_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_12_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_13_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_14_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_15_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_16_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_17_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_18_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_19_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_20_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_21_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_22_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] stq_23_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [11:0] io_core_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7]
wire [11:0] io_core_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7]
wire [11:0] io_core_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7]
wire [11:0] _exe_req_WIRE_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:33]
wire [11:0] exe_req_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:25]
wire [11:0] exe_tlb_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] exe_tlb_uop_uop_1_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] _exe_tlb_uop_T_3_csr_addr = 12'h0; // @[lsu.scala:602:24]
wire [11:0] dmem_req_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] _mem_ldq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:918:90]
wire [11:0] _mem_stq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:922:89]
wire [11:0] lcam_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_1_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_2_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_3_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_4_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_5_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_6_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_7_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_8_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_9_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_10_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_11_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_12_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_13_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_14_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_15_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_16_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_17_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_18_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_19_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_20_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_21_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_22_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] stq_23_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_251 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_266 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_281 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_296 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_311 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_326 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_341 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _l_mask_mask_T_356 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_251 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_266 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_281 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_296 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_311 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_326 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_341 = 8'hFF; // @[Mux.scala:126:16]
wire [7:0] _write_mask_mask_T_356 = 8'hFF; // @[Mux.scala:126:16]
wire [23:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 24'h0; // @[lsu.scala:918:90]
wire [38:0] _exe_sfence_WIRE_bits_addr = 39'h0; // @[lsu.scala:615:43]
wire _exe_req_WIRE_0_valid = io_core_exe_0_req_valid_0; // @[lsu.scala:201:7, :383:33]
wire [6:0] _exe_req_WIRE_0_bits_uop_uopc = io_core_exe_0_req_bits_uop_uopc_0; // @[lsu.scala:201:7, :383:33]
wire [31:0] _exe_req_WIRE_0_bits_uop_inst = io_core_exe_0_req_bits_uop_inst_0; // @[lsu.scala:201:7, :383:33]
wire [31:0] _exe_req_WIRE_0_bits_uop_debug_inst = io_core_exe_0_req_bits_uop_debug_inst_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_rvc = io_core_exe_0_req_bits_uop_is_rvc_0; // @[lsu.scala:201:7, :383:33]
wire [39:0] _exe_req_WIRE_0_bits_uop_debug_pc = io_core_exe_0_req_bits_uop_debug_pc_0; // @[lsu.scala:201:7, :383:33]
wire [2:0] _exe_req_WIRE_0_bits_uop_iq_type = io_core_exe_0_req_bits_uop_iq_type_0; // @[lsu.scala:201:7, :383:33]
wire [9:0] _exe_req_WIRE_0_bits_uop_fu_code = io_core_exe_0_req_bits_uop_fu_code_0; // @[lsu.scala:201:7, :383:33]
wire [3:0] _exe_req_WIRE_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7, :383:33]
wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7, :383:33]
wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7, :383:33]
wire [4:0] _exe_req_WIRE_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7, :383:33]
wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_iw_state = io_core_exe_0_req_bits_uop_iw_state_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_br = io_core_exe_0_req_bits_uop_is_br_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_jalr = io_core_exe_0_req_bits_uop_is_jalr_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_jal = io_core_exe_0_req_bits_uop_is_jal_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_sfb = io_core_exe_0_req_bits_uop_is_sfb_0; // @[lsu.scala:201:7, :383:33]
wire [15:0] _exe_req_WIRE_0_bits_uop_br_mask = io_core_exe_0_req_bits_uop_br_mask_0; // @[lsu.scala:201:7, :383:33]
wire [3:0] _exe_req_WIRE_0_bits_uop_br_tag = io_core_exe_0_req_bits_uop_br_tag_0; // @[lsu.scala:201:7, :383:33]
wire [4:0] _exe_req_WIRE_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_uop_ftq_idx_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_edge_inst = io_core_exe_0_req_bits_uop_edge_inst_0; // @[lsu.scala:201:7, :383:33]
wire [5:0] _exe_req_WIRE_0_bits_uop_pc_lob = io_core_exe_0_req_bits_uop_pc_lob_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_taken = io_core_exe_0_req_bits_uop_taken_0; // @[lsu.scala:201:7, :383:33]
wire [19:0] _exe_req_WIRE_0_bits_uop_imm_packed = io_core_exe_0_req_bits_uop_imm_packed_0; // @[lsu.scala:201:7, :383:33]
wire [11:0] _exe_req_WIRE_0_bits_uop_csr_addr = io_core_exe_0_req_bits_uop_csr_addr_0; // @[lsu.scala:201:7, :383:33]
wire [6:0] _exe_req_WIRE_0_bits_uop_rob_idx = io_core_exe_0_req_bits_uop_rob_idx_0; // @[lsu.scala:201:7, :383:33]
wire [4:0] _exe_req_WIRE_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_uop_ldq_idx_0; // @[lsu.scala:201:7, :383:33]
wire [4:0] _exe_req_WIRE_0_bits_uop_stq_idx = io_core_exe_0_req_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_uop_rxq_idx_0; // @[lsu.scala:201:7, :383:33]
wire [6:0] _exe_req_WIRE_0_bits_uop_pdst = io_core_exe_0_req_bits_uop_pdst_0; // @[lsu.scala:201:7, :383:33]
wire [6:0] _exe_req_WIRE_0_bits_uop_prs1 = io_core_exe_0_req_bits_uop_prs1_0; // @[lsu.scala:201:7, :383:33]
wire [6:0] _exe_req_WIRE_0_bits_uop_prs2 = io_core_exe_0_req_bits_uop_prs2_0; // @[lsu.scala:201:7, :383:33]
wire [6:0] _exe_req_WIRE_0_bits_uop_prs3 = io_core_exe_0_req_bits_uop_prs3_0; // @[lsu.scala:201:7, :383:33]
wire [4:0] _exe_req_WIRE_0_bits_uop_ppred = io_core_exe_0_req_bits_uop_ppred_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_uop_prs1_busy_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_uop_prs2_busy_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_uop_prs3_busy_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_uop_ppred_busy_0; // @[lsu.scala:201:7, :383:33]
wire [6:0] _exe_req_WIRE_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_uop_stale_pdst_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_exception = io_core_exe_0_req_bits_uop_exception_0; // @[lsu.scala:201:7, :383:33]
wire [63:0] _exe_req_WIRE_0_bits_uop_exc_cause = io_core_exe_0_req_bits_uop_exc_cause_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_bypassable = io_core_exe_0_req_bits_uop_bypassable_0; // @[lsu.scala:201:7, :383:33]
wire [4:0] _exe_req_WIRE_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_uop_mem_cmd_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_mem_size = io_core_exe_0_req_bits_uop_mem_size_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_mem_signed = io_core_exe_0_req_bits_uop_mem_signed_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_fence = io_core_exe_0_req_bits_uop_is_fence_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_fencei = io_core_exe_0_req_bits_uop_is_fencei_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_amo = io_core_exe_0_req_bits_uop_is_amo_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_uses_stq = io_core_exe_0_req_bits_uop_uses_stq_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_is_unique = io_core_exe_0_req_bits_uop_is_unique_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7, :383:33]
wire [5:0] _exe_req_WIRE_0_bits_uop_ldst = io_core_exe_0_req_bits_uop_ldst_0; // @[lsu.scala:201:7, :383:33]
wire [5:0] _exe_req_WIRE_0_bits_uop_lrs1 = io_core_exe_0_req_bits_uop_lrs1_0; // @[lsu.scala:201:7, :383:33]
wire [5:0] _exe_req_WIRE_0_bits_uop_lrs2 = io_core_exe_0_req_bits_uop_lrs2_0; // @[lsu.scala:201:7, :383:33]
wire [5:0] _exe_req_WIRE_0_bits_uop_lrs3 = io_core_exe_0_req_bits_uop_lrs3_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_ldst_val = io_core_exe_0_req_bits_uop_ldst_val_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_uop_dst_rtype_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_frs3_en = io_core_exe_0_req_bits_uop_frs3_en_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_fp_val = io_core_exe_0_req_bits_uop_fp_val_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_fp_single = io_core_exe_0_req_bits_uop_fp_single_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7, :383:33]
wire [1:0] _exe_req_WIRE_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7, :383:33]
wire [63:0] _exe_req_WIRE_0_bits_data = io_core_exe_0_req_bits_data_0; // @[lsu.scala:201:7, :383:33]
wire [39:0] _exe_req_WIRE_0_bits_addr = io_core_exe_0_req_bits_addr_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_mxcpt_valid = io_core_exe_0_req_bits_mxcpt_valid_0; // @[lsu.scala:201:7, :383:33]
wire [24:0] _exe_req_WIRE_0_bits_mxcpt_bits = io_core_exe_0_req_bits_mxcpt_bits_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_bits_rs1_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_bits_rs2_0; // @[lsu.scala:201:7, :383:33]
wire [38:0] _exe_req_WIRE_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_bits_addr_0; // @[lsu.scala:201:7, :383:33]
wire _exe_req_WIRE_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_bits_asid_0; // @[lsu.scala:201:7, :383:33]
wire _io_core_fp_stdata_ready_T_2; // @[lsu.scala:867:61]
wire [6:0] mem_stdf_uop_out_uopc = io_core_fp_stdata_bits_uop_uopc_0; // @[util.scala:96:23]
wire [31:0] mem_stdf_uop_out_inst = io_core_fp_stdata_bits_uop_inst_0; // @[util.scala:96:23]
wire [31:0] mem_stdf_uop_out_debug_inst = io_core_fp_stdata_bits_uop_debug_inst_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_rvc = io_core_fp_stdata_bits_uop_is_rvc_0; // @[util.scala:96:23]
wire [39:0] mem_stdf_uop_out_debug_pc = io_core_fp_stdata_bits_uop_debug_pc_0; // @[util.scala:96:23]
wire [2:0] mem_stdf_uop_out_iq_type = io_core_fp_stdata_bits_uop_iq_type_0; // @[util.scala:96:23]
wire [9:0] mem_stdf_uop_out_fu_code = io_core_fp_stdata_bits_uop_fu_code_0; // @[util.scala:96:23]
wire [3:0] mem_stdf_uop_out_ctrl_br_type = io_core_fp_stdata_bits_uop_ctrl_br_type_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_ctrl_op1_sel = io_core_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[util.scala:96:23]
wire [2:0] mem_stdf_uop_out_ctrl_op2_sel = io_core_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[util.scala:96:23]
wire [2:0] mem_stdf_uop_out_ctrl_imm_sel = io_core_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[util.scala:96:23]
wire [4:0] mem_stdf_uop_out_ctrl_op_fcn = io_core_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_ctrl_fcn_dw = io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[util.scala:96:23]
wire [2:0] mem_stdf_uop_out_ctrl_csr_cmd = io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_ctrl_is_load = io_core_fp_stdata_bits_uop_ctrl_is_load_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_ctrl_is_sta = io_core_fp_stdata_bits_uop_ctrl_is_sta_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_ctrl_is_std = io_core_fp_stdata_bits_uop_ctrl_is_std_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_iw_state = io_core_fp_stdata_bits_uop_iw_state_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_iw_p1_poisoned = io_core_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_iw_p2_poisoned = io_core_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_br = io_core_fp_stdata_bits_uop_is_br_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_jalr = io_core_fp_stdata_bits_uop_is_jalr_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_jal = io_core_fp_stdata_bits_uop_is_jal_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_sfb = io_core_fp_stdata_bits_uop_is_sfb_0; // @[util.scala:96:23]
wire [3:0] mem_stdf_uop_out_br_tag = io_core_fp_stdata_bits_uop_br_tag_0; // @[util.scala:96:23]
wire [4:0] mem_stdf_uop_out_ftq_idx = io_core_fp_stdata_bits_uop_ftq_idx_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_edge_inst = io_core_fp_stdata_bits_uop_edge_inst_0; // @[util.scala:96:23]
wire [5:0] mem_stdf_uop_out_pc_lob = io_core_fp_stdata_bits_uop_pc_lob_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_taken = io_core_fp_stdata_bits_uop_taken_0; // @[util.scala:96:23]
wire [19:0] mem_stdf_uop_out_imm_packed = io_core_fp_stdata_bits_uop_imm_packed_0; // @[util.scala:96:23]
wire [11:0] mem_stdf_uop_out_csr_addr = io_core_fp_stdata_bits_uop_csr_addr_0; // @[util.scala:96:23]
wire [6:0] mem_stdf_uop_out_rob_idx = io_core_fp_stdata_bits_uop_rob_idx_0; // @[util.scala:96:23]
wire [4:0] mem_stdf_uop_out_ldq_idx = io_core_fp_stdata_bits_uop_ldq_idx_0; // @[util.scala:96:23]
wire [4:0] mem_stdf_uop_out_stq_idx = io_core_fp_stdata_bits_uop_stq_idx_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_rxq_idx = io_core_fp_stdata_bits_uop_rxq_idx_0; // @[util.scala:96:23]
wire [6:0] mem_stdf_uop_out_pdst = io_core_fp_stdata_bits_uop_pdst_0; // @[util.scala:96:23]
wire [6:0] mem_stdf_uop_out_prs1 = io_core_fp_stdata_bits_uop_prs1_0; // @[util.scala:96:23]
wire [6:0] mem_stdf_uop_out_prs2 = io_core_fp_stdata_bits_uop_prs2_0; // @[util.scala:96:23]
wire [6:0] mem_stdf_uop_out_prs3 = io_core_fp_stdata_bits_uop_prs3_0; // @[util.scala:96:23]
wire [4:0] mem_stdf_uop_out_ppred = io_core_fp_stdata_bits_uop_ppred_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_prs1_busy = io_core_fp_stdata_bits_uop_prs1_busy_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_prs2_busy = io_core_fp_stdata_bits_uop_prs2_busy_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_prs3_busy = io_core_fp_stdata_bits_uop_prs3_busy_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_ppred_busy = io_core_fp_stdata_bits_uop_ppred_busy_0; // @[util.scala:96:23]
wire [6:0] mem_stdf_uop_out_stale_pdst = io_core_fp_stdata_bits_uop_stale_pdst_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_exception = io_core_fp_stdata_bits_uop_exception_0; // @[util.scala:96:23]
wire [63:0] mem_stdf_uop_out_exc_cause = io_core_fp_stdata_bits_uop_exc_cause_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_bypassable = io_core_fp_stdata_bits_uop_bypassable_0; // @[util.scala:96:23]
wire [4:0] mem_stdf_uop_out_mem_cmd = io_core_fp_stdata_bits_uop_mem_cmd_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_mem_size = io_core_fp_stdata_bits_uop_mem_size_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_mem_signed = io_core_fp_stdata_bits_uop_mem_signed_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_fence = io_core_fp_stdata_bits_uop_is_fence_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_fencei = io_core_fp_stdata_bits_uop_is_fencei_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_amo = io_core_fp_stdata_bits_uop_is_amo_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_uses_ldq = io_core_fp_stdata_bits_uop_uses_ldq_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_uses_stq = io_core_fp_stdata_bits_uop_uses_stq_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_sys_pc2epc = io_core_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_is_unique = io_core_fp_stdata_bits_uop_is_unique_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_flush_on_commit = io_core_fp_stdata_bits_uop_flush_on_commit_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_ldst_is_rs1 = io_core_fp_stdata_bits_uop_ldst_is_rs1_0; // @[util.scala:96:23]
wire [5:0] mem_stdf_uop_out_ldst = io_core_fp_stdata_bits_uop_ldst_0; // @[util.scala:96:23]
wire [5:0] mem_stdf_uop_out_lrs1 = io_core_fp_stdata_bits_uop_lrs1_0; // @[util.scala:96:23]
wire [5:0] mem_stdf_uop_out_lrs2 = io_core_fp_stdata_bits_uop_lrs2_0; // @[util.scala:96:23]
wire [5:0] mem_stdf_uop_out_lrs3 = io_core_fp_stdata_bits_uop_lrs3_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_ldst_val = io_core_fp_stdata_bits_uop_ldst_val_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_dst_rtype = io_core_fp_stdata_bits_uop_dst_rtype_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_lrs1_rtype = io_core_fp_stdata_bits_uop_lrs1_rtype_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_lrs2_rtype = io_core_fp_stdata_bits_uop_lrs2_rtype_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_frs3_en = io_core_fp_stdata_bits_uop_frs3_en_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_fp_val = io_core_fp_stdata_bits_uop_fp_val_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_fp_single = io_core_fp_stdata_bits_uop_fp_single_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_xcpt_pf_if = io_core_fp_stdata_bits_uop_xcpt_pf_if_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_xcpt_ae_if = io_core_fp_stdata_bits_uop_xcpt_ae_if_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_xcpt_ma_if = io_core_fp_stdata_bits_uop_xcpt_ma_if_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_bp_debug_if = io_core_fp_stdata_bits_uop_bp_debug_if_0; // @[util.scala:96:23]
wire mem_stdf_uop_out_bp_xcpt_if = io_core_fp_stdata_bits_uop_bp_xcpt_if_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_debug_fsrc = io_core_fp_stdata_bits_uop_debug_fsrc_0; // @[util.scala:96:23]
wire [1:0] mem_stdf_uop_out_debug_tsrc = io_core_fp_stdata_bits_uop_debug_tsrc_0; // @[util.scala:96:23]
wire _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:980:82]
wire _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:1005:87]
wire _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:1261:69]
wire [15:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:201:7]
wire [15:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc_0; // @[lsu.scala:201:7]
wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:201:7]
wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:201:7]
wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:201:7]
wire [9:0] io_dmem_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:201:7]
wire [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:201:7]
wire [15:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:201:7]
wire [3:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:201:7]
wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:201:7]
wire [11:0] io_dmem_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:201:7]
wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_valid_0 = io_core_brupdate_b2_valid_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:201:7]
wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:201:7]
wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:201:7]
wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:201:7]
wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:201:7]
wire _io_core_fencei_rdy_T_1; // @[lsu.scala:347:42]
wire _io_core_lxcpt_valid_T_5; // @[lsu.scala:1254:61]
wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35]
wire dmem_req_0_valid; // @[lsu.scala:750:22]
wire [6:0] dmem_req_0_bits_uop_uopc; // @[lsu.scala:750:22]
wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:750:22]
wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:750:22]
wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:750:22]
wire [2:0] dmem_req_0_bits_uop_iq_type; // @[lsu.scala:750:22]
wire [9:0] dmem_req_0_bits_uop_fu_code; // @[lsu.scala:750:22]
wire [3:0] dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:750:22]
wire [2:0] dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:750:22]
wire [2:0] dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:750:22]
wire [4:0] dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:750:22]
wire [2:0] dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_iw_state; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_br; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_jal; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:750:22]
wire [15:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:750:22]
wire [3:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:750:22]
wire [4:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:750:22]
wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_taken; // @[lsu.scala:750:22]
wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:750:22]
wire [11:0] dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:750:22]
wire [6:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:750:22]
wire [4:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:750:22]
wire [4:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:750:22]
wire [6:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:750:22]
wire [6:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:750:22]
wire [6:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:750:22]
wire [6:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:750:22]
wire [4:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:750:22]
wire [6:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_exception; // @[lsu.scala:750:22]
wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_bypassable; // @[lsu.scala:750:22]
wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:750:22]
wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:750:22]
wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:750:22]
wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:750:22]
wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_fp_single; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:750:22]
wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:750:22]
wire [1:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:750:22]
wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:750:22]
wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:750:22]
wire dmem_req_0_bits_is_hella; // @[lsu.scala:750:22]
wire [63:0] io_hellacache_resp_bits_data_0 = io_dmem_resp_0_bits_data_0; // @[lsu.scala:201:7]
wire will_fire_release_0; // @[lsu.scala:377:38]
wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:201:7, :459:66]
wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:201:7]
wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:201:7]
wire _io_hellacache_store_pending_T_22; // @[lsu.scala:1530:59]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:201:7]
wire io_ptw_req_bits_valid_0; // @[lsu.scala:201:7]
wire io_ptw_req_valid_0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_uop_uopc_0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_iresp_bits_uop_inst_0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_iresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7]
wire [39:0] io_core_exe_0_iresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_iresp_bits_uop_iq_type_0; // @[lsu.scala:201:7]
wire [9:0] io_core_exe_0_iresp_bits_uop_fu_code_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_iw_state_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_br_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_jal_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7]
wire [15:0] io_core_exe_0_iresp_bits_uop_br_mask_0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_iresp_bits_uop_br_tag_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_taken_0; // @[lsu.scala:201:7]
wire [19:0] io_core_exe_0_iresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7]
wire [11:0] io_core_exe_0_iresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_uop_pdst_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_uop_prs1_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_uop_prs2_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_uop_prs3_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_uop_ppred_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_ppred_busy_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_iresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_exception_0; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_iresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_bypassable_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_mem_size_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_fence_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_amo_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_is_unique_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_uop_ldst_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_uop_lrs1_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_uop_lrs2_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_iresp_bits_uop_lrs3_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_fp_val_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_fp_single_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_iresp_bits_data_0; // @[lsu.scala:201:7]
wire io_core_exe_0_iresp_valid_0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_uop_uopc_0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_fresp_bits_uop_inst_0; // @[lsu.scala:201:7]
wire [31:0] io_core_exe_0_fresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7]
wire [39:0] io_core_exe_0_fresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7]
wire [2:0] io_core_exe_0_fresp_bits_uop_iq_type_0; // @[lsu.scala:201:7]
wire [9:0] io_core_exe_0_fresp_bits_uop_fu_code_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_iw_state_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_br_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_jal_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7]
wire [15:0] io_core_exe_0_fresp_bits_uop_br_mask_0; // @[lsu.scala:201:7]
wire [3:0] io_core_exe_0_fresp_bits_uop_br_tag_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_taken_0; // @[lsu.scala:201:7]
wire [19:0] io_core_exe_0_fresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7]
wire [11:0] io_core_exe_0_fresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_uop_pdst_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_uop_prs1_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_uop_prs2_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_uop_prs3_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7]
wire [6:0] io_core_exe_0_fresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_exception_0; // @[lsu.scala:201:7]
wire [63:0] io_core_exe_0_fresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_bypassable_0; // @[lsu.scala:201:7]
wire [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_mem_size_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_fence_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_amo_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_is_unique_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_uop_ldst_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_uop_lrs1_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_uop_lrs2_0; // @[lsu.scala:201:7]
wire [5:0] io_core_exe_0_fresp_bits_uop_lrs3_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_fp_val_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_fp_single_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7]
wire [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7]
wire [64:0] io_core_exe_0_fresp_bits_data_0; // @[lsu.scala:201:7]
wire io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_ldq_idx_1_0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_ldq_idx_2_0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_stq_idx_1_0; // @[lsu.scala:201:7]
wire [4:0] io_core_dis_stq_idx_2_0; // @[lsu.scala:201:7]
wire io_core_ldq_full_0_0; // @[lsu.scala:201:7]
wire io_core_ldq_full_1_0; // @[lsu.scala:201:7]
wire io_core_ldq_full_2_0; // @[lsu.scala:201:7]
wire io_core_stq_full_0_0; // @[lsu.scala:201:7]
wire io_core_stq_full_1_0; // @[lsu.scala:201:7]
wire io_core_stq_full_2_0; // @[lsu.scala:201:7]
wire io_core_fp_stdata_ready_0; // @[lsu.scala:201:7]
wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:201:7]
wire [6:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:201:7]
wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:201:7]
wire [6:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:201:7]
wire [6:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:201:7]
wire io_core_spec_ld_wakeup_0_valid_0; // @[lsu.scala:201:7]
wire [6:0] io_core_spec_ld_wakeup_0_bits_0; // @[lsu.scala:201:7]
wire [3:0] io_core_lxcpt_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7]
wire [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7]
wire [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7]
wire [6:0] io_core_lxcpt_bits_uop_uopc_0; // @[lsu.scala:201:7]
wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:201:7]
wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:201:7]
wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:201:7]
wire [2:0] io_core_lxcpt_bits_uop_iq_type_0; // @[lsu.scala:201:7]
wire [9:0] io_core_lxcpt_bits_uop_fu_code_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_iw_state_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_br_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_jalr_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_jal_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:201:7]
wire [15:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:201:7]
wire [3:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:201:7]
wire [4:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:201:7]
wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:201:7]
wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:201:7]
wire [11:0] io_core_lxcpt_bits_uop_csr_addr_0; // @[lsu.scala:201:7]
wire [6:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:201:7]
wire [6:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:201:7]
wire [6:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:201:7]
wire [6:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:201:7]
wire [6:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:201:7]
wire [4:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:201:7]
wire [6:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:201:7]
wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_bypassable_0; // @[lsu.scala:201:7]
wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7]
wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:201:7]
wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:201:7]
wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:201:7]
wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_ldst_val_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_fp_single_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7]
wire [1:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7]
wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:201:7]
wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:201:7]
wire io_core_lxcpt_valid_0; // @[lsu.scala:201:7]
wire io_core_perf_tlbMiss_0; // @[lsu.scala:201:7]
wire io_core_ld_miss_0; // @[lsu.scala:201:7]
wire io_core_fencei_rdy_0; // @[lsu.scala:201:7]
wire [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_req_bits_0_bits_uop_uopc_0; // @[lsu.scala:201:7]
wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:201:7]
wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:201:7]
wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:201:7]
wire [2:0] io_dmem_req_bits_0_bits_uop_iq_type_0; // @[lsu.scala:201:7]
wire [9:0] io_dmem_req_bits_0_bits_uop_fu_code_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_iw_state_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_br_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_jalr_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_jal_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:201:7]
wire [15:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:201:7]
wire [3:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:201:7]
wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:201:7]
wire [11:0] io_dmem_req_bits_0_bits_uop_csr_addr_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:201:7]
wire [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:201:7]
wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_bypassable_0; // @[lsu.scala:201:7]
wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:201:7]
wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_ldst_val_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_fp_single_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7]
wire [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7]
wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:201:7]
wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:201:7]
wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:201:7]
wire io_dmem_req_valid_0; // @[lsu.scala:201:7]
wire io_dmem_s1_kill_0_0; // @[lsu.scala:201:7]
wire io_dmem_release_ready_0; // @[lsu.scala:201:7]
wire io_dmem_force_order_0; // @[lsu.scala:201:7]
wire io_hellacache_req_ready_0; // @[lsu.scala:201:7]
wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:201:7]
wire io_hellacache_resp_valid_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:201:7]
wire io_hellacache_s2_nack_0; // @[lsu.scala:201:7]
wire io_hellacache_store_pending_0; // @[lsu.scala:201:7]
reg ldq_0_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_0_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_0_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_0_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_0_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_0_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_0_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_0_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_0_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_0_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_0_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_0_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_0_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_0_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_0_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_0_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_0_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_0_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_0_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_0_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_0_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_0_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_0_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_0_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_0_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_0_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_0_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_0_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_0_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_0_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_0_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_0_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_0_bits_executed; // @[lsu.scala:208:16]
reg ldq_0_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_0_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_0_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_0_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_0_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_0_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_0_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_1_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_1_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_1_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_1_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_1_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_1_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_1_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_1_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_1_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_1_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_1_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_1_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_1_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_1_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_1_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_1_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_1_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_1_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_1_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_1_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_1_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_1_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_1_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_1_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_1_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_1_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_1_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_1_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_1_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_1_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_1_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_1_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_1_bits_executed; // @[lsu.scala:208:16]
reg ldq_1_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_1_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_1_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_1_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_1_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_1_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_1_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_2_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_2_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_2_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_2_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_2_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_2_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_2_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_2_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_2_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_2_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_2_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_2_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_2_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_2_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_2_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_2_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_2_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_2_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_2_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_2_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_2_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_2_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_2_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_2_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_2_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_2_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_2_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_2_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_2_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_2_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_2_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_2_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_2_bits_executed; // @[lsu.scala:208:16]
reg ldq_2_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_2_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_2_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_2_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_2_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_2_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_2_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_3_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_3_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_3_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_3_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_3_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_3_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_3_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_3_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_3_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_3_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_3_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_3_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_3_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_3_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_3_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_3_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_3_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_3_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_3_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_3_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_3_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_3_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_3_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_3_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_3_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_3_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_3_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_3_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_3_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_3_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_3_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_3_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_3_bits_executed; // @[lsu.scala:208:16]
reg ldq_3_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_3_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_3_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_3_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_3_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_3_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_3_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_4_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_4_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_4_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_4_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_4_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_4_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_4_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_4_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_4_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_4_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_4_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_4_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_4_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_4_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_4_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_4_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_4_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_4_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_4_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_4_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_4_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_4_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_4_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_4_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_4_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_4_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_4_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_4_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_4_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_4_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_4_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_4_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_4_bits_executed; // @[lsu.scala:208:16]
reg ldq_4_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_4_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_4_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_4_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_4_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_4_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_4_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_5_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_5_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_5_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_5_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_5_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_5_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_5_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_5_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_5_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_5_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_5_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_5_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_5_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_5_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_5_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_5_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_5_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_5_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_5_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_5_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_5_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_5_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_5_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_5_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_5_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_5_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_5_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_5_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_5_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_5_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_5_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_5_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_5_bits_executed; // @[lsu.scala:208:16]
reg ldq_5_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_5_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_5_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_5_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_5_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_5_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_5_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_6_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_6_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_6_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_6_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_6_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_6_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_6_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_6_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_6_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_6_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_6_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_6_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_6_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_6_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_6_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_6_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_6_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_6_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_6_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_6_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_6_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_6_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_6_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_6_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_6_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_6_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_6_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_6_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_6_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_6_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_6_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_6_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_6_bits_executed; // @[lsu.scala:208:16]
reg ldq_6_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_6_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_6_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_6_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_6_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_6_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_6_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_7_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_7_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_7_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_7_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_7_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_7_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_7_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_7_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_7_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_7_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_7_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_7_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_7_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_7_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_7_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_7_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_7_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_7_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_7_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_7_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_7_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_7_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_7_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_7_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_7_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_7_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_7_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_7_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_7_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_7_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_7_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_7_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_7_bits_executed; // @[lsu.scala:208:16]
reg ldq_7_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_7_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_7_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_7_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_7_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_7_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_7_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_8_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_8_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_8_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_8_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_8_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_8_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_8_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_8_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_8_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_8_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_8_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_8_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_8_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_8_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_8_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_8_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_8_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_8_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_8_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_8_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_8_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_8_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_8_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_8_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_8_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_8_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_8_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_8_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_8_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_8_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_8_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_8_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_8_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_8_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_8_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_8_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_8_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_8_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_8_bits_executed; // @[lsu.scala:208:16]
reg ldq_8_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_8_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_8_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_8_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_8_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_8_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_8_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_8_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_9_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_9_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_9_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_9_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_9_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_9_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_9_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_9_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_9_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_9_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_9_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_9_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_9_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_9_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_9_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_9_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_9_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_9_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_9_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_9_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_9_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_9_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_9_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_9_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_9_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_9_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_9_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_9_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_9_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_9_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_9_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_9_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_9_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_9_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_9_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_9_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_9_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_9_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_9_bits_executed; // @[lsu.scala:208:16]
reg ldq_9_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_9_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_9_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_9_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_9_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_9_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_9_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_9_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_10_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_10_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_10_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_10_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_10_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_10_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_10_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_10_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_10_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_10_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_10_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_10_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_10_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_10_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_10_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_10_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_10_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_10_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_10_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_10_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_10_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_10_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_10_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_10_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_10_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_10_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_10_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_10_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_10_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_10_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_10_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_10_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_10_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_10_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_10_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_10_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_10_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_10_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_10_bits_executed; // @[lsu.scala:208:16]
reg ldq_10_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_10_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_10_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_10_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_10_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_10_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_10_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_10_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_11_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_11_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_11_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_11_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_11_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_11_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_11_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_11_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_11_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_11_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_11_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_11_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_11_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_11_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_11_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_11_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_11_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_11_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_11_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_11_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_11_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_11_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_11_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_11_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_11_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_11_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_11_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_11_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_11_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_11_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_11_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_11_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_11_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_11_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_11_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_11_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_11_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_11_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_11_bits_executed; // @[lsu.scala:208:16]
reg ldq_11_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_11_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_11_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_11_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_11_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_11_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_11_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_11_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_12_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_12_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_12_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_12_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_12_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_12_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_12_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_12_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_12_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_12_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_12_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_12_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_12_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_12_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_12_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_12_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_12_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_12_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_12_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_12_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_12_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_12_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_12_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_12_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_12_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_12_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_12_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_12_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_12_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_12_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_12_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_12_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_12_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_12_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_12_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_12_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_12_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_12_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_12_bits_executed; // @[lsu.scala:208:16]
reg ldq_12_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_12_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_12_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_12_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_12_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_12_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_12_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_12_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_13_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_13_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_13_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_13_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_13_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_13_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_13_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_13_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_13_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_13_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_13_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_13_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_13_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_13_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_13_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_13_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_13_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_13_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_13_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_13_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_13_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_13_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_13_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_13_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_13_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_13_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_13_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_13_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_13_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_13_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_13_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_13_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_13_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_13_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_13_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_13_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_13_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_13_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_13_bits_executed; // @[lsu.scala:208:16]
reg ldq_13_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_13_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_13_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_13_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_13_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_13_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_13_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_13_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_14_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_14_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_14_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_14_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_14_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_14_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_14_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_14_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_14_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_14_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_14_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_14_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_14_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_14_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_14_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_14_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_14_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_14_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_14_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_14_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_14_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_14_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_14_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_14_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_14_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_14_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_14_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_14_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_14_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_14_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_14_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_14_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_14_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_14_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_14_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_14_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_14_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_14_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_14_bits_executed; // @[lsu.scala:208:16]
reg ldq_14_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_14_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_14_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_14_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_14_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_14_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_14_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_14_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_15_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_15_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_15_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_15_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_15_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_15_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_15_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_15_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_15_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_15_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_15_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_15_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_15_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_15_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_15_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_15_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_15_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_15_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_15_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_15_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_15_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_15_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_15_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_15_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_15_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_15_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_15_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_15_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_15_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_15_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_15_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_15_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_15_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_15_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_15_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_15_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_15_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_15_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_15_bits_executed; // @[lsu.scala:208:16]
reg ldq_15_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_15_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_15_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_15_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_15_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_15_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_15_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_15_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_16_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_16_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_16_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_16_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_16_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_16_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_16_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_16_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_16_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_16_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_16_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_16_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_16_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_16_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_16_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_16_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_16_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_16_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_16_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_16_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_16_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_16_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_16_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_16_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_16_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_16_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_16_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_16_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_16_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_16_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_16_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_16_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_16_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_16_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_16_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_16_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_16_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_16_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_16_bits_executed; // @[lsu.scala:208:16]
reg ldq_16_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_16_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_16_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_16_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_16_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_16_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_16_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_16_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_17_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_17_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_17_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_17_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_17_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_17_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_17_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_17_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_17_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_17_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_17_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_17_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_17_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_17_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_17_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_17_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_17_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_17_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_17_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_17_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_17_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_17_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_17_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_17_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_17_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_17_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_17_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_17_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_17_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_17_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_17_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_17_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_17_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_17_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_17_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_17_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_17_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_17_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_17_bits_executed; // @[lsu.scala:208:16]
reg ldq_17_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_17_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_17_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_17_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_17_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_17_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_17_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_17_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_18_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_18_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_18_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_18_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_18_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_18_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_18_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_18_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_18_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_18_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_18_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_18_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_18_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_18_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_18_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_18_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_18_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_18_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_18_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_18_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_18_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_18_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_18_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_18_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_18_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_18_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_18_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_18_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_18_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_18_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_18_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_18_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_18_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_18_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_18_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_18_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_18_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_18_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_18_bits_executed; // @[lsu.scala:208:16]
reg ldq_18_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_18_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_18_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_18_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_18_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_18_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_18_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_18_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_19_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_19_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_19_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_19_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_19_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_19_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_19_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_19_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_19_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_19_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_19_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_19_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_19_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_19_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_19_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_19_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_19_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_19_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_19_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_19_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_19_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_19_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_19_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_19_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_19_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_19_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_19_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_19_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_19_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_19_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_19_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_19_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_19_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_19_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_19_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_19_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_19_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_19_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_19_bits_executed; // @[lsu.scala:208:16]
reg ldq_19_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_19_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_19_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_19_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_19_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_19_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_19_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_19_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_20_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_20_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_20_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_20_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_20_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_20_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_20_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_20_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_20_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_20_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_20_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_20_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_20_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_20_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_20_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_20_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_20_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_20_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_20_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_20_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_20_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_20_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_20_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_20_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_20_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_20_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_20_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_20_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_20_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_20_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_20_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_20_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_20_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_20_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_20_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_20_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_20_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_20_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_20_bits_executed; // @[lsu.scala:208:16]
reg ldq_20_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_20_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_20_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_20_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_20_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_20_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_20_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_20_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_21_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_21_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_21_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_21_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_21_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_21_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_21_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_21_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_21_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_21_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_21_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_21_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_21_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_21_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_21_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_21_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_21_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_21_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_21_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_21_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_21_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_21_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_21_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_21_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_21_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_21_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_21_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_21_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_21_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_21_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_21_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_21_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_21_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_21_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_21_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_21_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_21_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_21_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_21_bits_executed; // @[lsu.scala:208:16]
reg ldq_21_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_21_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_21_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_21_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_21_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_21_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_21_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_21_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_22_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_22_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_22_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_22_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_22_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_22_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_22_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_22_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_22_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_22_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_22_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_22_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_22_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_22_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_22_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_22_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_22_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_22_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_22_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_22_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_22_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_22_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_22_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_22_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_22_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_22_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_22_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_22_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_22_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_22_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_22_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_22_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_22_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_22_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_22_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_22_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_22_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_22_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_22_bits_executed; // @[lsu.scala:208:16]
reg ldq_22_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_22_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_22_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_22_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_22_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_22_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_22_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_22_bits_debug_wb_data; // @[lsu.scala:208:16]
reg ldq_23_valid; // @[lsu.scala:208:16]
reg [6:0] ldq_23_bits_uop_uopc; // @[lsu.scala:208:16]
reg [31:0] ldq_23_bits_uop_inst; // @[lsu.scala:208:16]
reg [31:0] ldq_23_bits_uop_debug_inst; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_rvc; // @[lsu.scala:208:16]
reg [39:0] ldq_23_bits_uop_debug_pc; // @[lsu.scala:208:16]
reg [2:0] ldq_23_bits_uop_iq_type; // @[lsu.scala:208:16]
reg [9:0] ldq_23_bits_uop_fu_code; // @[lsu.scala:208:16]
reg [3:0] ldq_23_bits_uop_ctrl_br_type; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_23_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16]
reg [2:0] ldq_23_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16]
reg [4:0] ldq_23_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16]
reg [2:0] ldq_23_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_ctrl_is_load; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_ctrl_is_std; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_iw_state; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_br; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_jalr; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_jal; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_sfb; // @[lsu.scala:208:16]
reg [15:0] ldq_23_bits_uop_br_mask; // @[lsu.scala:208:16]
reg [3:0] ldq_23_bits_uop_br_tag; // @[lsu.scala:208:16]
reg [4:0] ldq_23_bits_uop_ftq_idx; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_edge_inst; // @[lsu.scala:208:16]
reg [5:0] ldq_23_bits_uop_pc_lob; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_taken; // @[lsu.scala:208:16]
reg [19:0] ldq_23_bits_uop_imm_packed; // @[lsu.scala:208:16]
reg [11:0] ldq_23_bits_uop_csr_addr; // @[lsu.scala:208:16]
reg [6:0] ldq_23_bits_uop_rob_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_23_bits_uop_ldq_idx; // @[lsu.scala:208:16]
reg [4:0] ldq_23_bits_uop_stq_idx; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_rxq_idx; // @[lsu.scala:208:16]
reg [6:0] ldq_23_bits_uop_pdst; // @[lsu.scala:208:16]
reg [6:0] ldq_23_bits_uop_prs1; // @[lsu.scala:208:16]
reg [6:0] ldq_23_bits_uop_prs2; // @[lsu.scala:208:16]
reg [6:0] ldq_23_bits_uop_prs3; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_prs1_busy; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_prs2_busy; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_prs3_busy; // @[lsu.scala:208:16]
reg [6:0] ldq_23_bits_uop_stale_pdst; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_exception; // @[lsu.scala:208:16]
reg [63:0] ldq_23_bits_uop_exc_cause; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_bypassable; // @[lsu.scala:208:16]
reg [4:0] ldq_23_bits_uop_mem_cmd; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_mem_size; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_mem_signed; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_fence; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_fencei; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_amo; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_uses_ldq; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_uses_stq; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_is_unique; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_flush_on_commit; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16]
reg [5:0] ldq_23_bits_uop_ldst; // @[lsu.scala:208:16]
reg [5:0] ldq_23_bits_uop_lrs1; // @[lsu.scala:208:16]
reg [5:0] ldq_23_bits_uop_lrs2; // @[lsu.scala:208:16]
reg [5:0] ldq_23_bits_uop_lrs3; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_ldst_val; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_dst_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_lrs1_rtype; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_lrs2_rtype; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_frs3_en; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_fp_val; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_fp_single; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_bp_debug_if; // @[lsu.scala:208:16]
reg ldq_23_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_debug_fsrc; // @[lsu.scala:208:16]
reg [1:0] ldq_23_bits_uop_debug_tsrc; // @[lsu.scala:208:16]
reg ldq_23_bits_addr_valid; // @[lsu.scala:208:16]
reg [39:0] ldq_23_bits_addr_bits; // @[lsu.scala:208:16]
reg ldq_23_bits_addr_is_virtual; // @[lsu.scala:208:16]
reg ldq_23_bits_addr_is_uncacheable; // @[lsu.scala:208:16]
reg ldq_23_bits_executed; // @[lsu.scala:208:16]
reg ldq_23_bits_succeeded; // @[lsu.scala:208:16]
reg ldq_23_bits_order_fail; // @[lsu.scala:208:16]
reg ldq_23_bits_observed; // @[lsu.scala:208:16]
reg [23:0] ldq_23_bits_st_dep_mask; // @[lsu.scala:208:16]
reg [4:0] ldq_23_bits_youngest_stq_idx; // @[lsu.scala:208:16]
reg ldq_23_bits_forward_std_val; // @[lsu.scala:208:16]
reg [4:0] ldq_23_bits_forward_stq_idx; // @[lsu.scala:208:16]
reg [63:0] ldq_23_bits_debug_wb_data; // @[lsu.scala:208:16]
reg stq_0_valid; // @[lsu.scala:209:16]
reg [6:0] stq_0_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_0_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_0_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_0_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_0_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_0_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_0_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_0_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_0_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_0_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_0_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_0_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_0_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_0_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_0_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_0_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_0_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_0_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_0_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_0_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_0_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_0_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_0_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_0_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_0_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_0_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_0_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_0_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_0_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_0_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_0_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_0_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_0_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_0_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_0_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_0_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_0_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_0_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_0_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_0_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_0_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_0_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_0_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_0_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_0_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_0_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_0_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_0_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_0_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_0_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_0_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_0_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_0_bits_data_bits; // @[lsu.scala:209:16]
reg stq_0_bits_committed; // @[lsu.scala:209:16]
reg stq_0_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_0_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_1_valid; // @[lsu.scala:209:16]
reg [6:0] stq_1_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_1_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_1_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_1_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_1_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_1_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_1_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_1_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_1_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_1_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_1_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_1_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_1_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_1_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_1_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_1_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_1_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_1_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_1_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_1_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_1_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_1_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_1_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_1_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_1_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_1_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_1_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_1_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_1_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_1_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_1_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_1_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_1_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_1_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_1_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_1_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_1_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_1_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_1_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_1_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_1_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_1_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_1_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_1_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_1_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_1_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_1_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_1_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_1_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_1_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_1_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_1_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_1_bits_data_bits; // @[lsu.scala:209:16]
reg stq_1_bits_committed; // @[lsu.scala:209:16]
reg stq_1_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_1_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_2_valid; // @[lsu.scala:209:16]
reg [6:0] stq_2_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_2_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_2_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_2_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_2_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_2_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_2_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_2_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_2_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_2_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_2_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_2_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_2_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_2_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_2_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_2_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_2_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_2_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_2_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_2_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_2_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_2_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_2_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_2_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_2_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_2_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_2_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_2_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_2_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_2_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_2_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_2_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_2_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_2_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_2_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_2_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_2_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_2_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_2_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_2_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_2_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_2_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_2_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_2_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_2_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_2_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_2_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_2_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_2_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_2_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_2_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_2_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_2_bits_data_bits; // @[lsu.scala:209:16]
reg stq_2_bits_committed; // @[lsu.scala:209:16]
reg stq_2_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_2_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_3_valid; // @[lsu.scala:209:16]
reg [6:0] stq_3_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_3_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_3_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_3_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_3_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_3_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_3_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_3_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_3_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_3_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_3_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_3_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_3_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_3_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_3_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_3_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_3_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_3_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_3_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_3_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_3_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_3_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_3_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_3_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_3_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_3_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_3_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_3_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_3_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_3_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_3_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_3_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_3_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_3_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_3_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_3_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_3_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_3_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_3_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_3_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_3_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_3_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_3_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_3_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_3_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_3_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_3_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_3_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_3_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_3_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_3_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_3_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_3_bits_data_bits; // @[lsu.scala:209:16]
reg stq_3_bits_committed; // @[lsu.scala:209:16]
reg stq_3_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_3_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_4_valid; // @[lsu.scala:209:16]
reg [6:0] stq_4_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_4_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_4_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_4_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_4_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_4_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_4_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_4_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_4_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_4_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_4_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_4_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_4_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_4_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_4_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_4_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_4_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_4_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_4_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_4_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_4_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_4_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_4_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_4_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_4_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_4_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_4_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_4_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_4_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_4_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_4_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_4_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_4_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_4_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_4_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_4_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_4_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_4_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_4_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_4_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_4_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_4_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_4_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_4_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_4_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_4_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_4_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_4_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_4_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_4_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_4_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_4_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_4_bits_data_bits; // @[lsu.scala:209:16]
reg stq_4_bits_committed; // @[lsu.scala:209:16]
reg stq_4_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_4_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_5_valid; // @[lsu.scala:209:16]
reg [6:0] stq_5_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_5_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_5_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_5_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_5_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_5_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_5_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_5_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_5_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_5_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_5_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_5_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_5_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_5_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_5_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_5_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_5_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_5_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_5_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_5_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_5_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_5_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_5_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_5_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_5_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_5_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_5_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_5_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_5_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_5_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_5_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_5_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_5_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_5_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_5_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_5_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_5_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_5_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_5_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_5_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_5_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_5_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_5_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_5_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_5_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_5_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_5_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_5_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_5_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_5_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_5_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_5_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_5_bits_data_bits; // @[lsu.scala:209:16]
reg stq_5_bits_committed; // @[lsu.scala:209:16]
reg stq_5_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_5_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_6_valid; // @[lsu.scala:209:16]
reg [6:0] stq_6_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_6_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_6_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_6_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_6_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_6_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_6_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_6_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_6_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_6_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_6_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_6_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_6_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_6_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_6_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_6_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_6_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_6_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_6_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_6_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_6_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_6_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_6_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_6_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_6_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_6_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_6_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_6_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_6_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_6_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_6_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_6_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_6_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_6_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_6_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_6_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_6_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_6_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_6_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_6_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_6_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_6_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_6_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_6_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_6_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_6_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_6_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_6_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_6_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_6_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_6_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_6_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_6_bits_data_bits; // @[lsu.scala:209:16]
reg stq_6_bits_committed; // @[lsu.scala:209:16]
reg stq_6_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_6_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_7_valid; // @[lsu.scala:209:16]
reg [6:0] stq_7_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_7_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_7_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_7_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_7_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_7_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_7_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_7_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_7_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_7_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_7_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_7_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_7_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_7_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_7_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_7_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_7_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_7_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_7_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_7_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_7_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_7_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_7_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_7_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_7_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_7_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_7_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_7_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_7_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_7_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_7_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_7_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_7_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_7_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_7_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_7_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_7_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_7_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_7_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_7_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_7_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_7_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_7_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_7_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_7_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_7_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_7_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_7_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_7_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_7_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_7_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_7_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_7_bits_data_bits; // @[lsu.scala:209:16]
reg stq_7_bits_committed; // @[lsu.scala:209:16]
reg stq_7_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_7_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_8_valid; // @[lsu.scala:209:16]
reg [6:0] stq_8_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_8_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_8_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_8_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_8_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_8_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_8_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_8_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_8_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_8_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_8_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_8_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_8_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_8_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_8_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_8_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_8_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_8_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_8_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_8_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_8_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_8_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_8_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_8_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_8_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_8_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_8_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_8_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_8_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_8_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_8_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_8_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_8_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_8_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_8_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_8_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_8_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_8_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_8_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_8_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_8_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_8_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_8_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_8_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_8_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_8_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_8_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_8_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_8_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_8_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_8_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_8_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_8_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_8_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_8_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_8_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_8_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_8_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_8_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_8_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_8_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_8_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_8_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_8_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_8_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_8_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_8_bits_data_bits; // @[lsu.scala:209:16]
reg stq_8_bits_committed; // @[lsu.scala:209:16]
reg stq_8_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_8_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_9_valid; // @[lsu.scala:209:16]
reg [6:0] stq_9_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_9_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_9_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_9_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_9_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_9_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_9_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_9_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_9_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_9_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_9_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_9_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_9_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_9_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_9_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_9_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_9_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_9_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_9_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_9_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_9_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_9_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_9_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_9_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_9_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_9_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_9_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_9_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_9_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_9_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_9_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_9_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_9_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_9_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_9_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_9_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_9_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_9_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_9_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_9_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_9_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_9_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_9_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_9_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_9_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_9_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_9_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_9_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_9_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_9_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_9_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_9_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_9_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_9_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_9_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_9_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_9_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_9_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_9_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_9_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_9_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_9_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_9_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_9_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_9_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_9_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_9_bits_data_bits; // @[lsu.scala:209:16]
reg stq_9_bits_committed; // @[lsu.scala:209:16]
reg stq_9_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_9_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_10_valid; // @[lsu.scala:209:16]
reg [6:0] stq_10_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_10_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_10_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_10_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_10_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_10_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_10_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_10_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_10_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_10_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_10_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_10_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_10_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_10_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_10_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_10_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_10_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_10_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_10_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_10_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_10_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_10_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_10_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_10_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_10_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_10_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_10_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_10_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_10_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_10_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_10_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_10_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_10_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_10_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_10_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_10_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_10_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_10_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_10_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_10_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_10_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_10_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_10_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_10_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_10_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_10_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_10_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_10_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_10_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_10_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_10_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_10_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_10_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_10_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_10_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_10_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_10_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_10_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_10_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_10_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_10_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_10_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_10_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_10_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_10_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_10_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_10_bits_data_bits; // @[lsu.scala:209:16]
reg stq_10_bits_committed; // @[lsu.scala:209:16]
reg stq_10_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_10_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_11_valid; // @[lsu.scala:209:16]
reg [6:0] stq_11_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_11_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_11_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_11_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_11_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_11_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_11_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_11_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_11_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_11_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_11_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_11_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_11_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_11_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_11_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_11_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_11_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_11_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_11_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_11_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_11_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_11_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_11_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_11_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_11_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_11_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_11_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_11_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_11_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_11_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_11_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_11_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_11_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_11_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_11_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_11_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_11_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_11_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_11_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_11_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_11_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_11_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_11_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_11_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_11_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_11_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_11_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_11_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_11_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_11_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_11_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_11_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_11_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_11_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_11_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_11_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_11_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_11_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_11_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_11_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_11_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_11_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_11_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_11_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_11_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_11_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_11_bits_data_bits; // @[lsu.scala:209:16]
reg stq_11_bits_committed; // @[lsu.scala:209:16]
reg stq_11_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_11_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_12_valid; // @[lsu.scala:209:16]
reg [6:0] stq_12_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_12_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_12_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_12_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_12_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_12_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_12_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_12_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_12_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_12_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_12_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_12_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_12_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_12_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_12_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_12_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_12_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_12_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_12_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_12_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_12_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_12_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_12_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_12_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_12_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_12_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_12_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_12_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_12_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_12_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_12_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_12_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_12_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_12_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_12_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_12_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_12_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_12_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_12_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_12_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_12_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_12_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_12_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_12_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_12_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_12_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_12_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_12_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_12_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_12_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_12_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_12_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_12_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_12_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_12_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_12_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_12_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_12_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_12_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_12_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_12_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_12_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_12_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_12_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_12_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_12_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_12_bits_data_bits; // @[lsu.scala:209:16]
reg stq_12_bits_committed; // @[lsu.scala:209:16]
reg stq_12_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_12_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_13_valid; // @[lsu.scala:209:16]
reg [6:0] stq_13_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_13_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_13_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_13_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_13_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_13_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_13_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_13_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_13_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_13_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_13_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_13_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_13_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_13_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_13_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_13_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_13_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_13_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_13_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_13_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_13_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_13_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_13_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_13_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_13_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_13_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_13_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_13_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_13_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_13_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_13_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_13_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_13_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_13_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_13_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_13_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_13_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_13_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_13_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_13_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_13_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_13_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_13_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_13_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_13_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_13_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_13_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_13_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_13_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_13_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_13_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_13_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_13_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_13_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_13_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_13_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_13_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_13_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_13_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_13_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_13_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_13_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_13_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_13_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_13_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_13_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_13_bits_data_bits; // @[lsu.scala:209:16]
reg stq_13_bits_committed; // @[lsu.scala:209:16]
reg stq_13_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_13_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_14_valid; // @[lsu.scala:209:16]
reg [6:0] stq_14_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_14_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_14_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_14_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_14_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_14_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_14_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_14_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_14_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_14_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_14_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_14_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_14_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_14_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_14_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_14_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_14_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_14_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_14_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_14_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_14_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_14_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_14_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_14_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_14_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_14_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_14_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_14_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_14_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_14_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_14_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_14_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_14_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_14_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_14_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_14_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_14_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_14_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_14_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_14_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_14_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_14_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_14_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_14_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_14_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_14_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_14_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_14_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_14_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_14_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_14_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_14_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_14_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_14_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_14_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_14_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_14_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_14_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_14_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_14_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_14_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_14_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_14_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_14_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_14_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_14_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_14_bits_data_bits; // @[lsu.scala:209:16]
reg stq_14_bits_committed; // @[lsu.scala:209:16]
reg stq_14_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_14_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_15_valid; // @[lsu.scala:209:16]
reg [6:0] stq_15_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_15_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_15_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_15_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_15_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_15_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_15_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_15_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_15_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_15_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_15_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_15_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_15_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_15_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_15_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_15_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_15_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_15_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_15_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_15_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_15_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_15_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_15_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_15_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_15_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_15_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_15_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_15_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_15_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_15_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_15_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_15_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_15_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_15_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_15_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_15_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_15_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_15_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_15_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_15_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_15_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_15_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_15_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_15_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_15_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_15_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_15_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_15_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_15_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_15_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_15_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_15_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_15_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_15_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_15_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_15_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_15_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_15_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_15_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_15_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_15_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_15_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_15_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_15_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_15_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_15_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_15_bits_data_bits; // @[lsu.scala:209:16]
reg stq_15_bits_committed; // @[lsu.scala:209:16]
reg stq_15_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_15_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_16_valid; // @[lsu.scala:209:16]
reg [6:0] stq_16_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_16_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_16_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_16_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_16_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_16_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_16_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_16_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_16_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_16_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_16_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_16_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_16_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_16_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_16_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_16_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_16_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_16_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_16_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_16_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_16_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_16_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_16_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_16_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_16_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_16_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_16_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_16_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_16_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_16_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_16_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_16_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_16_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_16_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_16_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_16_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_16_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_16_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_16_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_16_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_16_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_16_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_16_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_16_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_16_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_16_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_16_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_16_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_16_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_16_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_16_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_16_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_16_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_16_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_16_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_16_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_16_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_16_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_16_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_16_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_16_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_16_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_16_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_16_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_16_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_16_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_16_bits_data_bits; // @[lsu.scala:209:16]
reg stq_16_bits_committed; // @[lsu.scala:209:16]
reg stq_16_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_16_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_17_valid; // @[lsu.scala:209:16]
reg [6:0] stq_17_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_17_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_17_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_17_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_17_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_17_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_17_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_17_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_17_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_17_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_17_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_17_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_17_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_17_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_17_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_17_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_17_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_17_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_17_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_17_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_17_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_17_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_17_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_17_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_17_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_17_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_17_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_17_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_17_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_17_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_17_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_17_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_17_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_17_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_17_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_17_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_17_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_17_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_17_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_17_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_17_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_17_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_17_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_17_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_17_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_17_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_17_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_17_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_17_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_17_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_17_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_17_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_17_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_17_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_17_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_17_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_17_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_17_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_17_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_17_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_17_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_17_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_17_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_17_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_17_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_17_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_17_bits_data_bits; // @[lsu.scala:209:16]
reg stq_17_bits_committed; // @[lsu.scala:209:16]
reg stq_17_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_17_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_18_valid; // @[lsu.scala:209:16]
reg [6:0] stq_18_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_18_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_18_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_18_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_18_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_18_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_18_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_18_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_18_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_18_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_18_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_18_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_18_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_18_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_18_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_18_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_18_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_18_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_18_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_18_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_18_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_18_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_18_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_18_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_18_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_18_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_18_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_18_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_18_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_18_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_18_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_18_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_18_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_18_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_18_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_18_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_18_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_18_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_18_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_18_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_18_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_18_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_18_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_18_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_18_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_18_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_18_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_18_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_18_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_18_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_18_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_18_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_18_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_18_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_18_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_18_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_18_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_18_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_18_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_18_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_18_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_18_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_18_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_18_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_18_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_18_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_18_bits_data_bits; // @[lsu.scala:209:16]
reg stq_18_bits_committed; // @[lsu.scala:209:16]
reg stq_18_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_18_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_19_valid; // @[lsu.scala:209:16]
reg [6:0] stq_19_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_19_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_19_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_19_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_19_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_19_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_19_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_19_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_19_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_19_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_19_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_19_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_19_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_19_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_19_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_19_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_19_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_19_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_19_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_19_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_19_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_19_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_19_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_19_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_19_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_19_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_19_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_19_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_19_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_19_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_19_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_19_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_19_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_19_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_19_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_19_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_19_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_19_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_19_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_19_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_19_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_19_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_19_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_19_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_19_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_19_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_19_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_19_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_19_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_19_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_19_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_19_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_19_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_19_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_19_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_19_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_19_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_19_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_19_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_19_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_19_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_19_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_19_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_19_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_19_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_19_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_19_bits_data_bits; // @[lsu.scala:209:16]
reg stq_19_bits_committed; // @[lsu.scala:209:16]
reg stq_19_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_19_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_20_valid; // @[lsu.scala:209:16]
reg [6:0] stq_20_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_20_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_20_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_20_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_20_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_20_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_20_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_20_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_20_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_20_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_20_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_20_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_20_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_20_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_20_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_20_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_20_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_20_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_20_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_20_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_20_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_20_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_20_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_20_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_20_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_20_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_20_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_20_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_20_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_20_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_20_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_20_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_20_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_20_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_20_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_20_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_20_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_20_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_20_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_20_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_20_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_20_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_20_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_20_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_20_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_20_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_20_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_20_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_20_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_20_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_20_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_20_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_20_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_20_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_20_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_20_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_20_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_20_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_20_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_20_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_20_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_20_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_20_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_20_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_20_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_20_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_20_bits_data_bits; // @[lsu.scala:209:16]
reg stq_20_bits_committed; // @[lsu.scala:209:16]
reg stq_20_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_20_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_21_valid; // @[lsu.scala:209:16]
reg [6:0] stq_21_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_21_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_21_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_21_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_21_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_21_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_21_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_21_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_21_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_21_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_21_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_21_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_21_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_21_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_21_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_21_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_21_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_21_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_21_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_21_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_21_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_21_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_21_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_21_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_21_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_21_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_21_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_21_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_21_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_21_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_21_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_21_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_21_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_21_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_21_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_21_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_21_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_21_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_21_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_21_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_21_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_21_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_21_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_21_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_21_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_21_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_21_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_21_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_21_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_21_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_21_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_21_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_21_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_21_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_21_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_21_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_21_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_21_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_21_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_21_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_21_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_21_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_21_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_21_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_21_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_21_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_21_bits_data_bits; // @[lsu.scala:209:16]
reg stq_21_bits_committed; // @[lsu.scala:209:16]
reg stq_21_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_21_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_22_valid; // @[lsu.scala:209:16]
reg [6:0] stq_22_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_22_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_22_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_22_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_22_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_22_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_22_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_22_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_22_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_22_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_22_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_22_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_22_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_22_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_22_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_22_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_22_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_22_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_22_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_22_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_22_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_22_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_22_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_22_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_22_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_22_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_22_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_22_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_22_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_22_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_22_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_22_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_22_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_22_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_22_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_22_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_22_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_22_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_22_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_22_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_22_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_22_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_22_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_22_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_22_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_22_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_22_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_22_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_22_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_22_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_22_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_22_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_22_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_22_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_22_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_22_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_22_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_22_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_22_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_22_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_22_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_22_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_22_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_22_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_22_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_22_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_22_bits_data_bits; // @[lsu.scala:209:16]
reg stq_22_bits_committed; // @[lsu.scala:209:16]
reg stq_22_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_22_bits_debug_wb_data; // @[lsu.scala:209:16]
reg stq_23_valid; // @[lsu.scala:209:16]
reg [6:0] stq_23_bits_uop_uopc; // @[lsu.scala:209:16]
reg [31:0] stq_23_bits_uop_inst; // @[lsu.scala:209:16]
reg [31:0] stq_23_bits_uop_debug_inst; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_rvc; // @[lsu.scala:209:16]
reg [39:0] stq_23_bits_uop_debug_pc; // @[lsu.scala:209:16]
reg [2:0] stq_23_bits_uop_iq_type; // @[lsu.scala:209:16]
reg [9:0] stq_23_bits_uop_fu_code; // @[lsu.scala:209:16]
reg [3:0] stq_23_bits_uop_ctrl_br_type; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16]
reg [2:0] stq_23_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16]
reg [2:0] stq_23_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16]
reg [4:0] stq_23_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16]
reg stq_23_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16]
reg [2:0] stq_23_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16]
reg stq_23_bits_uop_ctrl_is_load; // @[lsu.scala:209:16]
reg stq_23_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16]
reg stq_23_bits_uop_ctrl_is_std; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_iw_state; // @[lsu.scala:209:16]
reg stq_23_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16]
reg stq_23_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_br; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_jalr; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_jal; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_sfb; // @[lsu.scala:209:16]
reg [15:0] stq_23_bits_uop_br_mask; // @[lsu.scala:209:16]
reg [3:0] stq_23_bits_uop_br_tag; // @[lsu.scala:209:16]
reg [4:0] stq_23_bits_uop_ftq_idx; // @[lsu.scala:209:16]
reg stq_23_bits_uop_edge_inst; // @[lsu.scala:209:16]
reg [5:0] stq_23_bits_uop_pc_lob; // @[lsu.scala:209:16]
reg stq_23_bits_uop_taken; // @[lsu.scala:209:16]
reg [19:0] stq_23_bits_uop_imm_packed; // @[lsu.scala:209:16]
reg [11:0] stq_23_bits_uop_csr_addr; // @[lsu.scala:209:16]
reg [6:0] stq_23_bits_uop_rob_idx; // @[lsu.scala:209:16]
reg [4:0] stq_23_bits_uop_ldq_idx; // @[lsu.scala:209:16]
reg [4:0] stq_23_bits_uop_stq_idx; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_rxq_idx; // @[lsu.scala:209:16]
reg [6:0] stq_23_bits_uop_pdst; // @[lsu.scala:209:16]
reg [6:0] stq_23_bits_uop_prs1; // @[lsu.scala:209:16]
reg [6:0] stq_23_bits_uop_prs2; // @[lsu.scala:209:16]
reg [6:0] stq_23_bits_uop_prs3; // @[lsu.scala:209:16]
reg [4:0] stq_23_bits_uop_ppred; // @[lsu.scala:209:16]
reg stq_23_bits_uop_prs1_busy; // @[lsu.scala:209:16]
reg stq_23_bits_uop_prs2_busy; // @[lsu.scala:209:16]
reg stq_23_bits_uop_prs3_busy; // @[lsu.scala:209:16]
reg stq_23_bits_uop_ppred_busy; // @[lsu.scala:209:16]
reg [6:0] stq_23_bits_uop_stale_pdst; // @[lsu.scala:209:16]
reg stq_23_bits_uop_exception; // @[lsu.scala:209:16]
reg [63:0] stq_23_bits_uop_exc_cause; // @[lsu.scala:209:16]
reg stq_23_bits_uop_bypassable; // @[lsu.scala:209:16]
reg [4:0] stq_23_bits_uop_mem_cmd; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_mem_size; // @[lsu.scala:209:16]
reg stq_23_bits_uop_mem_signed; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_fence; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_fencei; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_amo; // @[lsu.scala:209:16]
reg stq_23_bits_uop_uses_ldq; // @[lsu.scala:209:16]
reg stq_23_bits_uop_uses_stq; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16]
reg stq_23_bits_uop_is_unique; // @[lsu.scala:209:16]
reg stq_23_bits_uop_flush_on_commit; // @[lsu.scala:209:16]
reg stq_23_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16]
reg [5:0] stq_23_bits_uop_ldst; // @[lsu.scala:209:16]
reg [5:0] stq_23_bits_uop_lrs1; // @[lsu.scala:209:16]
reg [5:0] stq_23_bits_uop_lrs2; // @[lsu.scala:209:16]
reg [5:0] stq_23_bits_uop_lrs3; // @[lsu.scala:209:16]
reg stq_23_bits_uop_ldst_val; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_dst_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_lrs1_rtype; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_lrs2_rtype; // @[lsu.scala:209:16]
reg stq_23_bits_uop_frs3_en; // @[lsu.scala:209:16]
reg stq_23_bits_uop_fp_val; // @[lsu.scala:209:16]
reg stq_23_bits_uop_fp_single; // @[lsu.scala:209:16]
reg stq_23_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16]
reg stq_23_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16]
reg stq_23_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16]
reg stq_23_bits_uop_bp_debug_if; // @[lsu.scala:209:16]
reg stq_23_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_debug_fsrc; // @[lsu.scala:209:16]
reg [1:0] stq_23_bits_uop_debug_tsrc; // @[lsu.scala:209:16]
reg stq_23_bits_addr_valid; // @[lsu.scala:209:16]
reg [39:0] stq_23_bits_addr_bits; // @[lsu.scala:209:16]
reg stq_23_bits_addr_is_virtual; // @[lsu.scala:209:16]
reg stq_23_bits_data_valid; // @[lsu.scala:209:16]
reg [63:0] stq_23_bits_data_bits; // @[lsu.scala:209:16]
reg stq_23_bits_committed; // @[lsu.scala:209:16]
reg stq_23_bits_succeeded; // @[lsu.scala:209:16]
reg [63:0] stq_23_bits_debug_wb_data; // @[lsu.scala:209:16]
reg [4:0] ldq_head; // @[lsu.scala:213:29]
reg [4:0] ldq_tail; // @[lsu.scala:214:29]
assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:201:7, :214:29]
reg [4:0] stq_head; // @[lsu.scala:215:29]
reg [4:0] stq_tail; // @[lsu.scala:216:29]
assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:201:7, :216:29]
reg [4:0] stq_commit_head; // @[lsu.scala:217:29]
reg [4:0] stq_execute_head; // @[lsu.scala:218:29]
wire [31:0] _GEN = {{stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_23_valid}, {stq_22_valid}, {stq_21_valid}, {stq_20_valid}, {stq_19_valid}, {stq_18_valid}, {stq_17_valid}, {stq_16_valid}, {stq_15_valid}, {stq_14_valid}, {stq_13_valid}, {stq_12_valid}, {stq_11_valid}, {stq_10_valid}, {stq_9_valid}, {stq_8_valid}, {stq_7_valid}, {stq_6_valid}, {stq_5_valid}, {stq_4_valid}, {stq_3_valid}, {stq_2_valid}, {stq_1_valid}, {stq_0_valid}}; // @[lsu.scala:209:16, :222:42]
wire _GEN_0 = _GEN[stq_execute_head]; // @[lsu.scala:218:29, :222:42]
wire [31:0][6:0] _GEN_1 = {{stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_23_bits_uop_uopc}, {stq_22_bits_uop_uopc}, {stq_21_bits_uop_uopc}, {stq_20_bits_uop_uopc}, {stq_19_bits_uop_uopc}, {stq_18_bits_uop_uopc}, {stq_17_bits_uop_uopc}, {stq_16_bits_uop_uopc}, {stq_15_bits_uop_uopc}, {stq_14_bits_uop_uopc}, {stq_13_bits_uop_uopc}, {stq_12_bits_uop_uopc}, {stq_11_bits_uop_uopc}, {stq_10_bits_uop_uopc}, {stq_9_bits_uop_uopc}, {stq_8_bits_uop_uopc}, {stq_7_bits_uop_uopc}, {stq_6_bits_uop_uopc}, {stq_5_bits_uop_uopc}, {stq_4_bits_uop_uopc}, {stq_3_bits_uop_uopc}, {stq_2_bits_uop_uopc}, {stq_1_bits_uop_uopc}, {stq_0_bits_uop_uopc}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][31:0] _GEN_2 = {{stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_23_bits_uop_inst}, {stq_22_bits_uop_inst}, {stq_21_bits_uop_inst}, {stq_20_bits_uop_inst}, {stq_19_bits_uop_inst}, {stq_18_bits_uop_inst}, {stq_17_bits_uop_inst}, {stq_16_bits_uop_inst}, {stq_15_bits_uop_inst}, {stq_14_bits_uop_inst}, {stq_13_bits_uop_inst}, {stq_12_bits_uop_inst}, {stq_11_bits_uop_inst}, {stq_10_bits_uop_inst}, {stq_9_bits_uop_inst}, {stq_8_bits_uop_inst}, {stq_7_bits_uop_inst}, {stq_6_bits_uop_inst}, {stq_5_bits_uop_inst}, {stq_4_bits_uop_inst}, {stq_3_bits_uop_inst}, {stq_2_bits_uop_inst}, {stq_1_bits_uop_inst}, {stq_0_bits_uop_inst}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][31:0] _GEN_3 = {{stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_23_bits_uop_debug_inst}, {stq_22_bits_uop_debug_inst}, {stq_21_bits_uop_debug_inst}, {stq_20_bits_uop_debug_inst}, {stq_19_bits_uop_debug_inst}, {stq_18_bits_uop_debug_inst}, {stq_17_bits_uop_debug_inst}, {stq_16_bits_uop_debug_inst}, {stq_15_bits_uop_debug_inst}, {stq_14_bits_uop_debug_inst}, {stq_13_bits_uop_debug_inst}, {stq_12_bits_uop_debug_inst}, {stq_11_bits_uop_debug_inst}, {stq_10_bits_uop_debug_inst}, {stq_9_bits_uop_debug_inst}, {stq_8_bits_uop_debug_inst}, {stq_7_bits_uop_debug_inst}, {stq_6_bits_uop_debug_inst}, {stq_5_bits_uop_debug_inst}, {stq_4_bits_uop_debug_inst}, {stq_3_bits_uop_debug_inst}, {stq_2_bits_uop_debug_inst}, {stq_1_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_4 = {{stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_23_bits_uop_is_rvc}, {stq_22_bits_uop_is_rvc}, {stq_21_bits_uop_is_rvc}, {stq_20_bits_uop_is_rvc}, {stq_19_bits_uop_is_rvc}, {stq_18_bits_uop_is_rvc}, {stq_17_bits_uop_is_rvc}, {stq_16_bits_uop_is_rvc}, {stq_15_bits_uop_is_rvc}, {stq_14_bits_uop_is_rvc}, {stq_13_bits_uop_is_rvc}, {stq_12_bits_uop_is_rvc}, {stq_11_bits_uop_is_rvc}, {stq_10_bits_uop_is_rvc}, {stq_9_bits_uop_is_rvc}, {stq_8_bits_uop_is_rvc}, {stq_7_bits_uop_is_rvc}, {stq_6_bits_uop_is_rvc}, {stq_5_bits_uop_is_rvc}, {stq_4_bits_uop_is_rvc}, {stq_3_bits_uop_is_rvc}, {stq_2_bits_uop_is_rvc}, {stq_1_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][39:0] _GEN_5 = {{stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_23_bits_uop_debug_pc}, {stq_22_bits_uop_debug_pc}, {stq_21_bits_uop_debug_pc}, {stq_20_bits_uop_debug_pc}, {stq_19_bits_uop_debug_pc}, {stq_18_bits_uop_debug_pc}, {stq_17_bits_uop_debug_pc}, {stq_16_bits_uop_debug_pc}, {stq_15_bits_uop_debug_pc}, {stq_14_bits_uop_debug_pc}, {stq_13_bits_uop_debug_pc}, {stq_12_bits_uop_debug_pc}, {stq_11_bits_uop_debug_pc}, {stq_10_bits_uop_debug_pc}, {stq_9_bits_uop_debug_pc}, {stq_8_bits_uop_debug_pc}, {stq_7_bits_uop_debug_pc}, {stq_6_bits_uop_debug_pc}, {stq_5_bits_uop_debug_pc}, {stq_4_bits_uop_debug_pc}, {stq_3_bits_uop_debug_pc}, {stq_2_bits_uop_debug_pc}, {stq_1_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][2:0] _GEN_6 = {{stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_23_bits_uop_iq_type}, {stq_22_bits_uop_iq_type}, {stq_21_bits_uop_iq_type}, {stq_20_bits_uop_iq_type}, {stq_19_bits_uop_iq_type}, {stq_18_bits_uop_iq_type}, {stq_17_bits_uop_iq_type}, {stq_16_bits_uop_iq_type}, {stq_15_bits_uop_iq_type}, {stq_14_bits_uop_iq_type}, {stq_13_bits_uop_iq_type}, {stq_12_bits_uop_iq_type}, {stq_11_bits_uop_iq_type}, {stq_10_bits_uop_iq_type}, {stq_9_bits_uop_iq_type}, {stq_8_bits_uop_iq_type}, {stq_7_bits_uop_iq_type}, {stq_6_bits_uop_iq_type}, {stq_5_bits_uop_iq_type}, {stq_4_bits_uop_iq_type}, {stq_3_bits_uop_iq_type}, {stq_2_bits_uop_iq_type}, {stq_1_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][9:0] _GEN_7 = {{stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_23_bits_uop_fu_code}, {stq_22_bits_uop_fu_code}, {stq_21_bits_uop_fu_code}, {stq_20_bits_uop_fu_code}, {stq_19_bits_uop_fu_code}, {stq_18_bits_uop_fu_code}, {stq_17_bits_uop_fu_code}, {stq_16_bits_uop_fu_code}, {stq_15_bits_uop_fu_code}, {stq_14_bits_uop_fu_code}, {stq_13_bits_uop_fu_code}, {stq_12_bits_uop_fu_code}, {stq_11_bits_uop_fu_code}, {stq_10_bits_uop_fu_code}, {stq_9_bits_uop_fu_code}, {stq_8_bits_uop_fu_code}, {stq_7_bits_uop_fu_code}, {stq_6_bits_uop_fu_code}, {stq_5_bits_uop_fu_code}, {stq_4_bits_uop_fu_code}, {stq_3_bits_uop_fu_code}, {stq_2_bits_uop_fu_code}, {stq_1_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][3:0] _GEN_8 = {{stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_23_bits_uop_ctrl_br_type}, {stq_22_bits_uop_ctrl_br_type}, {stq_21_bits_uop_ctrl_br_type}, {stq_20_bits_uop_ctrl_br_type}, {stq_19_bits_uop_ctrl_br_type}, {stq_18_bits_uop_ctrl_br_type}, {stq_17_bits_uop_ctrl_br_type}, {stq_16_bits_uop_ctrl_br_type}, {stq_15_bits_uop_ctrl_br_type}, {stq_14_bits_uop_ctrl_br_type}, {stq_13_bits_uop_ctrl_br_type}, {stq_12_bits_uop_ctrl_br_type}, {stq_11_bits_uop_ctrl_br_type}, {stq_10_bits_uop_ctrl_br_type}, {stq_9_bits_uop_ctrl_br_type}, {stq_8_bits_uop_ctrl_br_type}, {stq_7_bits_uop_ctrl_br_type}, {stq_6_bits_uop_ctrl_br_type}, {stq_5_bits_uop_ctrl_br_type}, {stq_4_bits_uop_ctrl_br_type}, {stq_3_bits_uop_ctrl_br_type}, {stq_2_bits_uop_ctrl_br_type}, {stq_1_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_9 = {{stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_23_bits_uop_ctrl_op1_sel}, {stq_22_bits_uop_ctrl_op1_sel}, {stq_21_bits_uop_ctrl_op1_sel}, {stq_20_bits_uop_ctrl_op1_sel}, {stq_19_bits_uop_ctrl_op1_sel}, {stq_18_bits_uop_ctrl_op1_sel}, {stq_17_bits_uop_ctrl_op1_sel}, {stq_16_bits_uop_ctrl_op1_sel}, {stq_15_bits_uop_ctrl_op1_sel}, {stq_14_bits_uop_ctrl_op1_sel}, {stq_13_bits_uop_ctrl_op1_sel}, {stq_12_bits_uop_ctrl_op1_sel}, {stq_11_bits_uop_ctrl_op1_sel}, {stq_10_bits_uop_ctrl_op1_sel}, {stq_9_bits_uop_ctrl_op1_sel}, {stq_8_bits_uop_ctrl_op1_sel}, {stq_7_bits_uop_ctrl_op1_sel}, {stq_6_bits_uop_ctrl_op1_sel}, {stq_5_bits_uop_ctrl_op1_sel}, {stq_4_bits_uop_ctrl_op1_sel}, {stq_3_bits_uop_ctrl_op1_sel}, {stq_2_bits_uop_ctrl_op1_sel}, {stq_1_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][2:0] _GEN_10 = {{stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_23_bits_uop_ctrl_op2_sel}, {stq_22_bits_uop_ctrl_op2_sel}, {stq_21_bits_uop_ctrl_op2_sel}, {stq_20_bits_uop_ctrl_op2_sel}, {stq_19_bits_uop_ctrl_op2_sel}, {stq_18_bits_uop_ctrl_op2_sel}, {stq_17_bits_uop_ctrl_op2_sel}, {stq_16_bits_uop_ctrl_op2_sel}, {stq_15_bits_uop_ctrl_op2_sel}, {stq_14_bits_uop_ctrl_op2_sel}, {stq_13_bits_uop_ctrl_op2_sel}, {stq_12_bits_uop_ctrl_op2_sel}, {stq_11_bits_uop_ctrl_op2_sel}, {stq_10_bits_uop_ctrl_op2_sel}, {stq_9_bits_uop_ctrl_op2_sel}, {stq_8_bits_uop_ctrl_op2_sel}, {stq_7_bits_uop_ctrl_op2_sel}, {stq_6_bits_uop_ctrl_op2_sel}, {stq_5_bits_uop_ctrl_op2_sel}, {stq_4_bits_uop_ctrl_op2_sel}, {stq_3_bits_uop_ctrl_op2_sel}, {stq_2_bits_uop_ctrl_op2_sel}, {stq_1_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][2:0] _GEN_11 = {{stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_23_bits_uop_ctrl_imm_sel}, {stq_22_bits_uop_ctrl_imm_sel}, {stq_21_bits_uop_ctrl_imm_sel}, {stq_20_bits_uop_ctrl_imm_sel}, {stq_19_bits_uop_ctrl_imm_sel}, {stq_18_bits_uop_ctrl_imm_sel}, {stq_17_bits_uop_ctrl_imm_sel}, {stq_16_bits_uop_ctrl_imm_sel}, {stq_15_bits_uop_ctrl_imm_sel}, {stq_14_bits_uop_ctrl_imm_sel}, {stq_13_bits_uop_ctrl_imm_sel}, {stq_12_bits_uop_ctrl_imm_sel}, {stq_11_bits_uop_ctrl_imm_sel}, {stq_10_bits_uop_ctrl_imm_sel}, {stq_9_bits_uop_ctrl_imm_sel}, {stq_8_bits_uop_ctrl_imm_sel}, {stq_7_bits_uop_ctrl_imm_sel}, {stq_6_bits_uop_ctrl_imm_sel}, {stq_5_bits_uop_ctrl_imm_sel}, {stq_4_bits_uop_ctrl_imm_sel}, {stq_3_bits_uop_ctrl_imm_sel}, {stq_2_bits_uop_ctrl_imm_sel}, {stq_1_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][4:0] _GEN_12 = {{stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_23_bits_uop_ctrl_op_fcn}, {stq_22_bits_uop_ctrl_op_fcn}, {stq_21_bits_uop_ctrl_op_fcn}, {stq_20_bits_uop_ctrl_op_fcn}, {stq_19_bits_uop_ctrl_op_fcn}, {stq_18_bits_uop_ctrl_op_fcn}, {stq_17_bits_uop_ctrl_op_fcn}, {stq_16_bits_uop_ctrl_op_fcn}, {stq_15_bits_uop_ctrl_op_fcn}, {stq_14_bits_uop_ctrl_op_fcn}, {stq_13_bits_uop_ctrl_op_fcn}, {stq_12_bits_uop_ctrl_op_fcn}, {stq_11_bits_uop_ctrl_op_fcn}, {stq_10_bits_uop_ctrl_op_fcn}, {stq_9_bits_uop_ctrl_op_fcn}, {stq_8_bits_uop_ctrl_op_fcn}, {stq_7_bits_uop_ctrl_op_fcn}, {stq_6_bits_uop_ctrl_op_fcn}, {stq_5_bits_uop_ctrl_op_fcn}, {stq_4_bits_uop_ctrl_op_fcn}, {stq_3_bits_uop_ctrl_op_fcn}, {stq_2_bits_uop_ctrl_op_fcn}, {stq_1_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_13 = {{stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_23_bits_uop_ctrl_fcn_dw}, {stq_22_bits_uop_ctrl_fcn_dw}, {stq_21_bits_uop_ctrl_fcn_dw}, {stq_20_bits_uop_ctrl_fcn_dw}, {stq_19_bits_uop_ctrl_fcn_dw}, {stq_18_bits_uop_ctrl_fcn_dw}, {stq_17_bits_uop_ctrl_fcn_dw}, {stq_16_bits_uop_ctrl_fcn_dw}, {stq_15_bits_uop_ctrl_fcn_dw}, {stq_14_bits_uop_ctrl_fcn_dw}, {stq_13_bits_uop_ctrl_fcn_dw}, {stq_12_bits_uop_ctrl_fcn_dw}, {stq_11_bits_uop_ctrl_fcn_dw}, {stq_10_bits_uop_ctrl_fcn_dw}, {stq_9_bits_uop_ctrl_fcn_dw}, {stq_8_bits_uop_ctrl_fcn_dw}, {stq_7_bits_uop_ctrl_fcn_dw}, {stq_6_bits_uop_ctrl_fcn_dw}, {stq_5_bits_uop_ctrl_fcn_dw}, {stq_4_bits_uop_ctrl_fcn_dw}, {stq_3_bits_uop_ctrl_fcn_dw}, {stq_2_bits_uop_ctrl_fcn_dw}, {stq_1_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][2:0] _GEN_14 = {{stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_23_bits_uop_ctrl_csr_cmd}, {stq_22_bits_uop_ctrl_csr_cmd}, {stq_21_bits_uop_ctrl_csr_cmd}, {stq_20_bits_uop_ctrl_csr_cmd}, {stq_19_bits_uop_ctrl_csr_cmd}, {stq_18_bits_uop_ctrl_csr_cmd}, {stq_17_bits_uop_ctrl_csr_cmd}, {stq_16_bits_uop_ctrl_csr_cmd}, {stq_15_bits_uop_ctrl_csr_cmd}, {stq_14_bits_uop_ctrl_csr_cmd}, {stq_13_bits_uop_ctrl_csr_cmd}, {stq_12_bits_uop_ctrl_csr_cmd}, {stq_11_bits_uop_ctrl_csr_cmd}, {stq_10_bits_uop_ctrl_csr_cmd}, {stq_9_bits_uop_ctrl_csr_cmd}, {stq_8_bits_uop_ctrl_csr_cmd}, {stq_7_bits_uop_ctrl_csr_cmd}, {stq_6_bits_uop_ctrl_csr_cmd}, {stq_5_bits_uop_ctrl_csr_cmd}, {stq_4_bits_uop_ctrl_csr_cmd}, {stq_3_bits_uop_ctrl_csr_cmd}, {stq_2_bits_uop_ctrl_csr_cmd}, {stq_1_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_15 = {{stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_23_bits_uop_ctrl_is_load}, {stq_22_bits_uop_ctrl_is_load}, {stq_21_bits_uop_ctrl_is_load}, {stq_20_bits_uop_ctrl_is_load}, {stq_19_bits_uop_ctrl_is_load}, {stq_18_bits_uop_ctrl_is_load}, {stq_17_bits_uop_ctrl_is_load}, {stq_16_bits_uop_ctrl_is_load}, {stq_15_bits_uop_ctrl_is_load}, {stq_14_bits_uop_ctrl_is_load}, {stq_13_bits_uop_ctrl_is_load}, {stq_12_bits_uop_ctrl_is_load}, {stq_11_bits_uop_ctrl_is_load}, {stq_10_bits_uop_ctrl_is_load}, {stq_9_bits_uop_ctrl_is_load}, {stq_8_bits_uop_ctrl_is_load}, {stq_7_bits_uop_ctrl_is_load}, {stq_6_bits_uop_ctrl_is_load}, {stq_5_bits_uop_ctrl_is_load}, {stq_4_bits_uop_ctrl_is_load}, {stq_3_bits_uop_ctrl_is_load}, {stq_2_bits_uop_ctrl_is_load}, {stq_1_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_16 = {{stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_23_bits_uop_ctrl_is_sta}, {stq_22_bits_uop_ctrl_is_sta}, {stq_21_bits_uop_ctrl_is_sta}, {stq_20_bits_uop_ctrl_is_sta}, {stq_19_bits_uop_ctrl_is_sta}, {stq_18_bits_uop_ctrl_is_sta}, {stq_17_bits_uop_ctrl_is_sta}, {stq_16_bits_uop_ctrl_is_sta}, {stq_15_bits_uop_ctrl_is_sta}, {stq_14_bits_uop_ctrl_is_sta}, {stq_13_bits_uop_ctrl_is_sta}, {stq_12_bits_uop_ctrl_is_sta}, {stq_11_bits_uop_ctrl_is_sta}, {stq_10_bits_uop_ctrl_is_sta}, {stq_9_bits_uop_ctrl_is_sta}, {stq_8_bits_uop_ctrl_is_sta}, {stq_7_bits_uop_ctrl_is_sta}, {stq_6_bits_uop_ctrl_is_sta}, {stq_5_bits_uop_ctrl_is_sta}, {stq_4_bits_uop_ctrl_is_sta}, {stq_3_bits_uop_ctrl_is_sta}, {stq_2_bits_uop_ctrl_is_sta}, {stq_1_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_17 = {{stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_23_bits_uop_ctrl_is_std}, {stq_22_bits_uop_ctrl_is_std}, {stq_21_bits_uop_ctrl_is_std}, {stq_20_bits_uop_ctrl_is_std}, {stq_19_bits_uop_ctrl_is_std}, {stq_18_bits_uop_ctrl_is_std}, {stq_17_bits_uop_ctrl_is_std}, {stq_16_bits_uop_ctrl_is_std}, {stq_15_bits_uop_ctrl_is_std}, {stq_14_bits_uop_ctrl_is_std}, {stq_13_bits_uop_ctrl_is_std}, {stq_12_bits_uop_ctrl_is_std}, {stq_11_bits_uop_ctrl_is_std}, {stq_10_bits_uop_ctrl_is_std}, {stq_9_bits_uop_ctrl_is_std}, {stq_8_bits_uop_ctrl_is_std}, {stq_7_bits_uop_ctrl_is_std}, {stq_6_bits_uop_ctrl_is_std}, {stq_5_bits_uop_ctrl_is_std}, {stq_4_bits_uop_ctrl_is_std}, {stq_3_bits_uop_ctrl_is_std}, {stq_2_bits_uop_ctrl_is_std}, {stq_1_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_18 = {{stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_23_bits_uop_iw_state}, {stq_22_bits_uop_iw_state}, {stq_21_bits_uop_iw_state}, {stq_20_bits_uop_iw_state}, {stq_19_bits_uop_iw_state}, {stq_18_bits_uop_iw_state}, {stq_17_bits_uop_iw_state}, {stq_16_bits_uop_iw_state}, {stq_15_bits_uop_iw_state}, {stq_14_bits_uop_iw_state}, {stq_13_bits_uop_iw_state}, {stq_12_bits_uop_iw_state}, {stq_11_bits_uop_iw_state}, {stq_10_bits_uop_iw_state}, {stq_9_bits_uop_iw_state}, {stq_8_bits_uop_iw_state}, {stq_7_bits_uop_iw_state}, {stq_6_bits_uop_iw_state}, {stq_5_bits_uop_iw_state}, {stq_4_bits_uop_iw_state}, {stq_3_bits_uop_iw_state}, {stq_2_bits_uop_iw_state}, {stq_1_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_19 = {{stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_23_bits_uop_iw_p1_poisoned}, {stq_22_bits_uop_iw_p1_poisoned}, {stq_21_bits_uop_iw_p1_poisoned}, {stq_20_bits_uop_iw_p1_poisoned}, {stq_19_bits_uop_iw_p1_poisoned}, {stq_18_bits_uop_iw_p1_poisoned}, {stq_17_bits_uop_iw_p1_poisoned}, {stq_16_bits_uop_iw_p1_poisoned}, {stq_15_bits_uop_iw_p1_poisoned}, {stq_14_bits_uop_iw_p1_poisoned}, {stq_13_bits_uop_iw_p1_poisoned}, {stq_12_bits_uop_iw_p1_poisoned}, {stq_11_bits_uop_iw_p1_poisoned}, {stq_10_bits_uop_iw_p1_poisoned}, {stq_9_bits_uop_iw_p1_poisoned}, {stq_8_bits_uop_iw_p1_poisoned}, {stq_7_bits_uop_iw_p1_poisoned}, {stq_6_bits_uop_iw_p1_poisoned}, {stq_5_bits_uop_iw_p1_poisoned}, {stq_4_bits_uop_iw_p1_poisoned}, {stq_3_bits_uop_iw_p1_poisoned}, {stq_2_bits_uop_iw_p1_poisoned}, {stq_1_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_20 = {{stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_23_bits_uop_iw_p2_poisoned}, {stq_22_bits_uop_iw_p2_poisoned}, {stq_21_bits_uop_iw_p2_poisoned}, {stq_20_bits_uop_iw_p2_poisoned}, {stq_19_bits_uop_iw_p2_poisoned}, {stq_18_bits_uop_iw_p2_poisoned}, {stq_17_bits_uop_iw_p2_poisoned}, {stq_16_bits_uop_iw_p2_poisoned}, {stq_15_bits_uop_iw_p2_poisoned}, {stq_14_bits_uop_iw_p2_poisoned}, {stq_13_bits_uop_iw_p2_poisoned}, {stq_12_bits_uop_iw_p2_poisoned}, {stq_11_bits_uop_iw_p2_poisoned}, {stq_10_bits_uop_iw_p2_poisoned}, {stq_9_bits_uop_iw_p2_poisoned}, {stq_8_bits_uop_iw_p2_poisoned}, {stq_7_bits_uop_iw_p2_poisoned}, {stq_6_bits_uop_iw_p2_poisoned}, {stq_5_bits_uop_iw_p2_poisoned}, {stq_4_bits_uop_iw_p2_poisoned}, {stq_3_bits_uop_iw_p2_poisoned}, {stq_2_bits_uop_iw_p2_poisoned}, {stq_1_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_21 = {{stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_23_bits_uop_is_br}, {stq_22_bits_uop_is_br}, {stq_21_bits_uop_is_br}, {stq_20_bits_uop_is_br}, {stq_19_bits_uop_is_br}, {stq_18_bits_uop_is_br}, {stq_17_bits_uop_is_br}, {stq_16_bits_uop_is_br}, {stq_15_bits_uop_is_br}, {stq_14_bits_uop_is_br}, {stq_13_bits_uop_is_br}, {stq_12_bits_uop_is_br}, {stq_11_bits_uop_is_br}, {stq_10_bits_uop_is_br}, {stq_9_bits_uop_is_br}, {stq_8_bits_uop_is_br}, {stq_7_bits_uop_is_br}, {stq_6_bits_uop_is_br}, {stq_5_bits_uop_is_br}, {stq_4_bits_uop_is_br}, {stq_3_bits_uop_is_br}, {stq_2_bits_uop_is_br}, {stq_1_bits_uop_is_br}, {stq_0_bits_uop_is_br}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_22 = {{stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_23_bits_uop_is_jalr}, {stq_22_bits_uop_is_jalr}, {stq_21_bits_uop_is_jalr}, {stq_20_bits_uop_is_jalr}, {stq_19_bits_uop_is_jalr}, {stq_18_bits_uop_is_jalr}, {stq_17_bits_uop_is_jalr}, {stq_16_bits_uop_is_jalr}, {stq_15_bits_uop_is_jalr}, {stq_14_bits_uop_is_jalr}, {stq_13_bits_uop_is_jalr}, {stq_12_bits_uop_is_jalr}, {stq_11_bits_uop_is_jalr}, {stq_10_bits_uop_is_jalr}, {stq_9_bits_uop_is_jalr}, {stq_8_bits_uop_is_jalr}, {stq_7_bits_uop_is_jalr}, {stq_6_bits_uop_is_jalr}, {stq_5_bits_uop_is_jalr}, {stq_4_bits_uop_is_jalr}, {stq_3_bits_uop_is_jalr}, {stq_2_bits_uop_is_jalr}, {stq_1_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_23 = {{stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_23_bits_uop_is_jal}, {stq_22_bits_uop_is_jal}, {stq_21_bits_uop_is_jal}, {stq_20_bits_uop_is_jal}, {stq_19_bits_uop_is_jal}, {stq_18_bits_uop_is_jal}, {stq_17_bits_uop_is_jal}, {stq_16_bits_uop_is_jal}, {stq_15_bits_uop_is_jal}, {stq_14_bits_uop_is_jal}, {stq_13_bits_uop_is_jal}, {stq_12_bits_uop_is_jal}, {stq_11_bits_uop_is_jal}, {stq_10_bits_uop_is_jal}, {stq_9_bits_uop_is_jal}, {stq_8_bits_uop_is_jal}, {stq_7_bits_uop_is_jal}, {stq_6_bits_uop_is_jal}, {stq_5_bits_uop_is_jal}, {stq_4_bits_uop_is_jal}, {stq_3_bits_uop_is_jal}, {stq_2_bits_uop_is_jal}, {stq_1_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_24 = {{stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_23_bits_uop_is_sfb}, {stq_22_bits_uop_is_sfb}, {stq_21_bits_uop_is_sfb}, {stq_20_bits_uop_is_sfb}, {stq_19_bits_uop_is_sfb}, {stq_18_bits_uop_is_sfb}, {stq_17_bits_uop_is_sfb}, {stq_16_bits_uop_is_sfb}, {stq_15_bits_uop_is_sfb}, {stq_14_bits_uop_is_sfb}, {stq_13_bits_uop_is_sfb}, {stq_12_bits_uop_is_sfb}, {stq_11_bits_uop_is_sfb}, {stq_10_bits_uop_is_sfb}, {stq_9_bits_uop_is_sfb}, {stq_8_bits_uop_is_sfb}, {stq_7_bits_uop_is_sfb}, {stq_6_bits_uop_is_sfb}, {stq_5_bits_uop_is_sfb}, {stq_4_bits_uop_is_sfb}, {stq_3_bits_uop_is_sfb}, {stq_2_bits_uop_is_sfb}, {stq_1_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][15:0] _GEN_25 = {{stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_23_bits_uop_br_mask}, {stq_22_bits_uop_br_mask}, {stq_21_bits_uop_br_mask}, {stq_20_bits_uop_br_mask}, {stq_19_bits_uop_br_mask}, {stq_18_bits_uop_br_mask}, {stq_17_bits_uop_br_mask}, {stq_16_bits_uop_br_mask}, {stq_15_bits_uop_br_mask}, {stq_14_bits_uop_br_mask}, {stq_13_bits_uop_br_mask}, {stq_12_bits_uop_br_mask}, {stq_11_bits_uop_br_mask}, {stq_10_bits_uop_br_mask}, {stq_9_bits_uop_br_mask}, {stq_8_bits_uop_br_mask}, {stq_7_bits_uop_br_mask}, {stq_6_bits_uop_br_mask}, {stq_5_bits_uop_br_mask}, {stq_4_bits_uop_br_mask}, {stq_3_bits_uop_br_mask}, {stq_2_bits_uop_br_mask}, {stq_1_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][3:0] _GEN_26 = {{stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_23_bits_uop_br_tag}, {stq_22_bits_uop_br_tag}, {stq_21_bits_uop_br_tag}, {stq_20_bits_uop_br_tag}, {stq_19_bits_uop_br_tag}, {stq_18_bits_uop_br_tag}, {stq_17_bits_uop_br_tag}, {stq_16_bits_uop_br_tag}, {stq_15_bits_uop_br_tag}, {stq_14_bits_uop_br_tag}, {stq_13_bits_uop_br_tag}, {stq_12_bits_uop_br_tag}, {stq_11_bits_uop_br_tag}, {stq_10_bits_uop_br_tag}, {stq_9_bits_uop_br_tag}, {stq_8_bits_uop_br_tag}, {stq_7_bits_uop_br_tag}, {stq_6_bits_uop_br_tag}, {stq_5_bits_uop_br_tag}, {stq_4_bits_uop_br_tag}, {stq_3_bits_uop_br_tag}, {stq_2_bits_uop_br_tag}, {stq_1_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][4:0] _GEN_27 = {{stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_23_bits_uop_ftq_idx}, {stq_22_bits_uop_ftq_idx}, {stq_21_bits_uop_ftq_idx}, {stq_20_bits_uop_ftq_idx}, {stq_19_bits_uop_ftq_idx}, {stq_18_bits_uop_ftq_idx}, {stq_17_bits_uop_ftq_idx}, {stq_16_bits_uop_ftq_idx}, {stq_15_bits_uop_ftq_idx}, {stq_14_bits_uop_ftq_idx}, {stq_13_bits_uop_ftq_idx}, {stq_12_bits_uop_ftq_idx}, {stq_11_bits_uop_ftq_idx}, {stq_10_bits_uop_ftq_idx}, {stq_9_bits_uop_ftq_idx}, {stq_8_bits_uop_ftq_idx}, {stq_7_bits_uop_ftq_idx}, {stq_6_bits_uop_ftq_idx}, {stq_5_bits_uop_ftq_idx}, {stq_4_bits_uop_ftq_idx}, {stq_3_bits_uop_ftq_idx}, {stq_2_bits_uop_ftq_idx}, {stq_1_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_28 = {{stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_23_bits_uop_edge_inst}, {stq_22_bits_uop_edge_inst}, {stq_21_bits_uop_edge_inst}, {stq_20_bits_uop_edge_inst}, {stq_19_bits_uop_edge_inst}, {stq_18_bits_uop_edge_inst}, {stq_17_bits_uop_edge_inst}, {stq_16_bits_uop_edge_inst}, {stq_15_bits_uop_edge_inst}, {stq_14_bits_uop_edge_inst}, {stq_13_bits_uop_edge_inst}, {stq_12_bits_uop_edge_inst}, {stq_11_bits_uop_edge_inst}, {stq_10_bits_uop_edge_inst}, {stq_9_bits_uop_edge_inst}, {stq_8_bits_uop_edge_inst}, {stq_7_bits_uop_edge_inst}, {stq_6_bits_uop_edge_inst}, {stq_5_bits_uop_edge_inst}, {stq_4_bits_uop_edge_inst}, {stq_3_bits_uop_edge_inst}, {stq_2_bits_uop_edge_inst}, {stq_1_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][5:0] _GEN_29 = {{stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_23_bits_uop_pc_lob}, {stq_22_bits_uop_pc_lob}, {stq_21_bits_uop_pc_lob}, {stq_20_bits_uop_pc_lob}, {stq_19_bits_uop_pc_lob}, {stq_18_bits_uop_pc_lob}, {stq_17_bits_uop_pc_lob}, {stq_16_bits_uop_pc_lob}, {stq_15_bits_uop_pc_lob}, {stq_14_bits_uop_pc_lob}, {stq_13_bits_uop_pc_lob}, {stq_12_bits_uop_pc_lob}, {stq_11_bits_uop_pc_lob}, {stq_10_bits_uop_pc_lob}, {stq_9_bits_uop_pc_lob}, {stq_8_bits_uop_pc_lob}, {stq_7_bits_uop_pc_lob}, {stq_6_bits_uop_pc_lob}, {stq_5_bits_uop_pc_lob}, {stq_4_bits_uop_pc_lob}, {stq_3_bits_uop_pc_lob}, {stq_2_bits_uop_pc_lob}, {stq_1_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_30 = {{stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_23_bits_uop_taken}, {stq_22_bits_uop_taken}, {stq_21_bits_uop_taken}, {stq_20_bits_uop_taken}, {stq_19_bits_uop_taken}, {stq_18_bits_uop_taken}, {stq_17_bits_uop_taken}, {stq_16_bits_uop_taken}, {stq_15_bits_uop_taken}, {stq_14_bits_uop_taken}, {stq_13_bits_uop_taken}, {stq_12_bits_uop_taken}, {stq_11_bits_uop_taken}, {stq_10_bits_uop_taken}, {stq_9_bits_uop_taken}, {stq_8_bits_uop_taken}, {stq_7_bits_uop_taken}, {stq_6_bits_uop_taken}, {stq_5_bits_uop_taken}, {stq_4_bits_uop_taken}, {stq_3_bits_uop_taken}, {stq_2_bits_uop_taken}, {stq_1_bits_uop_taken}, {stq_0_bits_uop_taken}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][19:0] _GEN_31 = {{stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_23_bits_uop_imm_packed}, {stq_22_bits_uop_imm_packed}, {stq_21_bits_uop_imm_packed}, {stq_20_bits_uop_imm_packed}, {stq_19_bits_uop_imm_packed}, {stq_18_bits_uop_imm_packed}, {stq_17_bits_uop_imm_packed}, {stq_16_bits_uop_imm_packed}, {stq_15_bits_uop_imm_packed}, {stq_14_bits_uop_imm_packed}, {stq_13_bits_uop_imm_packed}, {stq_12_bits_uop_imm_packed}, {stq_11_bits_uop_imm_packed}, {stq_10_bits_uop_imm_packed}, {stq_9_bits_uop_imm_packed}, {stq_8_bits_uop_imm_packed}, {stq_7_bits_uop_imm_packed}, {stq_6_bits_uop_imm_packed}, {stq_5_bits_uop_imm_packed}, {stq_4_bits_uop_imm_packed}, {stq_3_bits_uop_imm_packed}, {stq_2_bits_uop_imm_packed}, {stq_1_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][11:0] _GEN_32 = {{stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_23_bits_uop_csr_addr}, {stq_22_bits_uop_csr_addr}, {stq_21_bits_uop_csr_addr}, {stq_20_bits_uop_csr_addr}, {stq_19_bits_uop_csr_addr}, {stq_18_bits_uop_csr_addr}, {stq_17_bits_uop_csr_addr}, {stq_16_bits_uop_csr_addr}, {stq_15_bits_uop_csr_addr}, {stq_14_bits_uop_csr_addr}, {stq_13_bits_uop_csr_addr}, {stq_12_bits_uop_csr_addr}, {stq_11_bits_uop_csr_addr}, {stq_10_bits_uop_csr_addr}, {stq_9_bits_uop_csr_addr}, {stq_8_bits_uop_csr_addr}, {stq_7_bits_uop_csr_addr}, {stq_6_bits_uop_csr_addr}, {stq_5_bits_uop_csr_addr}, {stq_4_bits_uop_csr_addr}, {stq_3_bits_uop_csr_addr}, {stq_2_bits_uop_csr_addr}, {stq_1_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][6:0] _GEN_33 = {{stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_23_bits_uop_rob_idx}, {stq_22_bits_uop_rob_idx}, {stq_21_bits_uop_rob_idx}, {stq_20_bits_uop_rob_idx}, {stq_19_bits_uop_rob_idx}, {stq_18_bits_uop_rob_idx}, {stq_17_bits_uop_rob_idx}, {stq_16_bits_uop_rob_idx}, {stq_15_bits_uop_rob_idx}, {stq_14_bits_uop_rob_idx}, {stq_13_bits_uop_rob_idx}, {stq_12_bits_uop_rob_idx}, {stq_11_bits_uop_rob_idx}, {stq_10_bits_uop_rob_idx}, {stq_9_bits_uop_rob_idx}, {stq_8_bits_uop_rob_idx}, {stq_7_bits_uop_rob_idx}, {stq_6_bits_uop_rob_idx}, {stq_5_bits_uop_rob_idx}, {stq_4_bits_uop_rob_idx}, {stq_3_bits_uop_rob_idx}, {stq_2_bits_uop_rob_idx}, {stq_1_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][4:0] _GEN_34 = {{stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_23_bits_uop_ldq_idx}, {stq_22_bits_uop_ldq_idx}, {stq_21_bits_uop_ldq_idx}, {stq_20_bits_uop_ldq_idx}, {stq_19_bits_uop_ldq_idx}, {stq_18_bits_uop_ldq_idx}, {stq_17_bits_uop_ldq_idx}, {stq_16_bits_uop_ldq_idx}, {stq_15_bits_uop_ldq_idx}, {stq_14_bits_uop_ldq_idx}, {stq_13_bits_uop_ldq_idx}, {stq_12_bits_uop_ldq_idx}, {stq_11_bits_uop_ldq_idx}, {stq_10_bits_uop_ldq_idx}, {stq_9_bits_uop_ldq_idx}, {stq_8_bits_uop_ldq_idx}, {stq_7_bits_uop_ldq_idx}, {stq_6_bits_uop_ldq_idx}, {stq_5_bits_uop_ldq_idx}, {stq_4_bits_uop_ldq_idx}, {stq_3_bits_uop_ldq_idx}, {stq_2_bits_uop_ldq_idx}, {stq_1_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][4:0] _GEN_35 = {{stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_23_bits_uop_stq_idx}, {stq_22_bits_uop_stq_idx}, {stq_21_bits_uop_stq_idx}, {stq_20_bits_uop_stq_idx}, {stq_19_bits_uop_stq_idx}, {stq_18_bits_uop_stq_idx}, {stq_17_bits_uop_stq_idx}, {stq_16_bits_uop_stq_idx}, {stq_15_bits_uop_stq_idx}, {stq_14_bits_uop_stq_idx}, {stq_13_bits_uop_stq_idx}, {stq_12_bits_uop_stq_idx}, {stq_11_bits_uop_stq_idx}, {stq_10_bits_uop_stq_idx}, {stq_9_bits_uop_stq_idx}, {stq_8_bits_uop_stq_idx}, {stq_7_bits_uop_stq_idx}, {stq_6_bits_uop_stq_idx}, {stq_5_bits_uop_stq_idx}, {stq_4_bits_uop_stq_idx}, {stq_3_bits_uop_stq_idx}, {stq_2_bits_uop_stq_idx}, {stq_1_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_36 = {{stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_23_bits_uop_rxq_idx}, {stq_22_bits_uop_rxq_idx}, {stq_21_bits_uop_rxq_idx}, {stq_20_bits_uop_rxq_idx}, {stq_19_bits_uop_rxq_idx}, {stq_18_bits_uop_rxq_idx}, {stq_17_bits_uop_rxq_idx}, {stq_16_bits_uop_rxq_idx}, {stq_15_bits_uop_rxq_idx}, {stq_14_bits_uop_rxq_idx}, {stq_13_bits_uop_rxq_idx}, {stq_12_bits_uop_rxq_idx}, {stq_11_bits_uop_rxq_idx}, {stq_10_bits_uop_rxq_idx}, {stq_9_bits_uop_rxq_idx}, {stq_8_bits_uop_rxq_idx}, {stq_7_bits_uop_rxq_idx}, {stq_6_bits_uop_rxq_idx}, {stq_5_bits_uop_rxq_idx}, {stq_4_bits_uop_rxq_idx}, {stq_3_bits_uop_rxq_idx}, {stq_2_bits_uop_rxq_idx}, {stq_1_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][6:0] _GEN_37 = {{stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_23_bits_uop_pdst}, {stq_22_bits_uop_pdst}, {stq_21_bits_uop_pdst}, {stq_20_bits_uop_pdst}, {stq_19_bits_uop_pdst}, {stq_18_bits_uop_pdst}, {stq_17_bits_uop_pdst}, {stq_16_bits_uop_pdst}, {stq_15_bits_uop_pdst}, {stq_14_bits_uop_pdst}, {stq_13_bits_uop_pdst}, {stq_12_bits_uop_pdst}, {stq_11_bits_uop_pdst}, {stq_10_bits_uop_pdst}, {stq_9_bits_uop_pdst}, {stq_8_bits_uop_pdst}, {stq_7_bits_uop_pdst}, {stq_6_bits_uop_pdst}, {stq_5_bits_uop_pdst}, {stq_4_bits_uop_pdst}, {stq_3_bits_uop_pdst}, {stq_2_bits_uop_pdst}, {stq_1_bits_uop_pdst}, {stq_0_bits_uop_pdst}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][6:0] _GEN_38 = {{stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_23_bits_uop_prs1}, {stq_22_bits_uop_prs1}, {stq_21_bits_uop_prs1}, {stq_20_bits_uop_prs1}, {stq_19_bits_uop_prs1}, {stq_18_bits_uop_prs1}, {stq_17_bits_uop_prs1}, {stq_16_bits_uop_prs1}, {stq_15_bits_uop_prs1}, {stq_14_bits_uop_prs1}, {stq_13_bits_uop_prs1}, {stq_12_bits_uop_prs1}, {stq_11_bits_uop_prs1}, {stq_10_bits_uop_prs1}, {stq_9_bits_uop_prs1}, {stq_8_bits_uop_prs1}, {stq_7_bits_uop_prs1}, {stq_6_bits_uop_prs1}, {stq_5_bits_uop_prs1}, {stq_4_bits_uop_prs1}, {stq_3_bits_uop_prs1}, {stq_2_bits_uop_prs1}, {stq_1_bits_uop_prs1}, {stq_0_bits_uop_prs1}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][6:0] _GEN_39 = {{stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_23_bits_uop_prs2}, {stq_22_bits_uop_prs2}, {stq_21_bits_uop_prs2}, {stq_20_bits_uop_prs2}, {stq_19_bits_uop_prs2}, {stq_18_bits_uop_prs2}, {stq_17_bits_uop_prs2}, {stq_16_bits_uop_prs2}, {stq_15_bits_uop_prs2}, {stq_14_bits_uop_prs2}, {stq_13_bits_uop_prs2}, {stq_12_bits_uop_prs2}, {stq_11_bits_uop_prs2}, {stq_10_bits_uop_prs2}, {stq_9_bits_uop_prs2}, {stq_8_bits_uop_prs2}, {stq_7_bits_uop_prs2}, {stq_6_bits_uop_prs2}, {stq_5_bits_uop_prs2}, {stq_4_bits_uop_prs2}, {stq_3_bits_uop_prs2}, {stq_2_bits_uop_prs2}, {stq_1_bits_uop_prs2}, {stq_0_bits_uop_prs2}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][6:0] _GEN_40 = {{stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_23_bits_uop_prs3}, {stq_22_bits_uop_prs3}, {stq_21_bits_uop_prs3}, {stq_20_bits_uop_prs3}, {stq_19_bits_uop_prs3}, {stq_18_bits_uop_prs3}, {stq_17_bits_uop_prs3}, {stq_16_bits_uop_prs3}, {stq_15_bits_uop_prs3}, {stq_14_bits_uop_prs3}, {stq_13_bits_uop_prs3}, {stq_12_bits_uop_prs3}, {stq_11_bits_uop_prs3}, {stq_10_bits_uop_prs3}, {stq_9_bits_uop_prs3}, {stq_8_bits_uop_prs3}, {stq_7_bits_uop_prs3}, {stq_6_bits_uop_prs3}, {stq_5_bits_uop_prs3}, {stq_4_bits_uop_prs3}, {stq_3_bits_uop_prs3}, {stq_2_bits_uop_prs3}, {stq_1_bits_uop_prs3}, {stq_0_bits_uop_prs3}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][4:0] _GEN_41 = {{stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_23_bits_uop_ppred}, {stq_22_bits_uop_ppred}, {stq_21_bits_uop_ppred}, {stq_20_bits_uop_ppred}, {stq_19_bits_uop_ppred}, {stq_18_bits_uop_ppred}, {stq_17_bits_uop_ppred}, {stq_16_bits_uop_ppred}, {stq_15_bits_uop_ppred}, {stq_14_bits_uop_ppred}, {stq_13_bits_uop_ppred}, {stq_12_bits_uop_ppred}, {stq_11_bits_uop_ppred}, {stq_10_bits_uop_ppred}, {stq_9_bits_uop_ppred}, {stq_8_bits_uop_ppred}, {stq_7_bits_uop_ppred}, {stq_6_bits_uop_ppred}, {stq_5_bits_uop_ppred}, {stq_4_bits_uop_ppred}, {stq_3_bits_uop_ppred}, {stq_2_bits_uop_ppred}, {stq_1_bits_uop_ppred}, {stq_0_bits_uop_ppred}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_42 = {{stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_23_bits_uop_prs1_busy}, {stq_22_bits_uop_prs1_busy}, {stq_21_bits_uop_prs1_busy}, {stq_20_bits_uop_prs1_busy}, {stq_19_bits_uop_prs1_busy}, {stq_18_bits_uop_prs1_busy}, {stq_17_bits_uop_prs1_busy}, {stq_16_bits_uop_prs1_busy}, {stq_15_bits_uop_prs1_busy}, {stq_14_bits_uop_prs1_busy}, {stq_13_bits_uop_prs1_busy}, {stq_12_bits_uop_prs1_busy}, {stq_11_bits_uop_prs1_busy}, {stq_10_bits_uop_prs1_busy}, {stq_9_bits_uop_prs1_busy}, {stq_8_bits_uop_prs1_busy}, {stq_7_bits_uop_prs1_busy}, {stq_6_bits_uop_prs1_busy}, {stq_5_bits_uop_prs1_busy}, {stq_4_bits_uop_prs1_busy}, {stq_3_bits_uop_prs1_busy}, {stq_2_bits_uop_prs1_busy}, {stq_1_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_43 = {{stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_23_bits_uop_prs2_busy}, {stq_22_bits_uop_prs2_busy}, {stq_21_bits_uop_prs2_busy}, {stq_20_bits_uop_prs2_busy}, {stq_19_bits_uop_prs2_busy}, {stq_18_bits_uop_prs2_busy}, {stq_17_bits_uop_prs2_busy}, {stq_16_bits_uop_prs2_busy}, {stq_15_bits_uop_prs2_busy}, {stq_14_bits_uop_prs2_busy}, {stq_13_bits_uop_prs2_busy}, {stq_12_bits_uop_prs2_busy}, {stq_11_bits_uop_prs2_busy}, {stq_10_bits_uop_prs2_busy}, {stq_9_bits_uop_prs2_busy}, {stq_8_bits_uop_prs2_busy}, {stq_7_bits_uop_prs2_busy}, {stq_6_bits_uop_prs2_busy}, {stq_5_bits_uop_prs2_busy}, {stq_4_bits_uop_prs2_busy}, {stq_3_bits_uop_prs2_busy}, {stq_2_bits_uop_prs2_busy}, {stq_1_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_44 = {{stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_23_bits_uop_prs3_busy}, {stq_22_bits_uop_prs3_busy}, {stq_21_bits_uop_prs3_busy}, {stq_20_bits_uop_prs3_busy}, {stq_19_bits_uop_prs3_busy}, {stq_18_bits_uop_prs3_busy}, {stq_17_bits_uop_prs3_busy}, {stq_16_bits_uop_prs3_busy}, {stq_15_bits_uop_prs3_busy}, {stq_14_bits_uop_prs3_busy}, {stq_13_bits_uop_prs3_busy}, {stq_12_bits_uop_prs3_busy}, {stq_11_bits_uop_prs3_busy}, {stq_10_bits_uop_prs3_busy}, {stq_9_bits_uop_prs3_busy}, {stq_8_bits_uop_prs3_busy}, {stq_7_bits_uop_prs3_busy}, {stq_6_bits_uop_prs3_busy}, {stq_5_bits_uop_prs3_busy}, {stq_4_bits_uop_prs3_busy}, {stq_3_bits_uop_prs3_busy}, {stq_2_bits_uop_prs3_busy}, {stq_1_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_45 = {{stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_23_bits_uop_ppred_busy}, {stq_22_bits_uop_ppred_busy}, {stq_21_bits_uop_ppred_busy}, {stq_20_bits_uop_ppred_busy}, {stq_19_bits_uop_ppred_busy}, {stq_18_bits_uop_ppred_busy}, {stq_17_bits_uop_ppred_busy}, {stq_16_bits_uop_ppred_busy}, {stq_15_bits_uop_ppred_busy}, {stq_14_bits_uop_ppred_busy}, {stq_13_bits_uop_ppred_busy}, {stq_12_bits_uop_ppred_busy}, {stq_11_bits_uop_ppred_busy}, {stq_10_bits_uop_ppred_busy}, {stq_9_bits_uop_ppred_busy}, {stq_8_bits_uop_ppred_busy}, {stq_7_bits_uop_ppred_busy}, {stq_6_bits_uop_ppred_busy}, {stq_5_bits_uop_ppred_busy}, {stq_4_bits_uop_ppred_busy}, {stq_3_bits_uop_ppred_busy}, {stq_2_bits_uop_ppred_busy}, {stq_1_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][6:0] _GEN_46 = {{stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_23_bits_uop_stale_pdst}, {stq_22_bits_uop_stale_pdst}, {stq_21_bits_uop_stale_pdst}, {stq_20_bits_uop_stale_pdst}, {stq_19_bits_uop_stale_pdst}, {stq_18_bits_uop_stale_pdst}, {stq_17_bits_uop_stale_pdst}, {stq_16_bits_uop_stale_pdst}, {stq_15_bits_uop_stale_pdst}, {stq_14_bits_uop_stale_pdst}, {stq_13_bits_uop_stale_pdst}, {stq_12_bits_uop_stale_pdst}, {stq_11_bits_uop_stale_pdst}, {stq_10_bits_uop_stale_pdst}, {stq_9_bits_uop_stale_pdst}, {stq_8_bits_uop_stale_pdst}, {stq_7_bits_uop_stale_pdst}, {stq_6_bits_uop_stale_pdst}, {stq_5_bits_uop_stale_pdst}, {stq_4_bits_uop_stale_pdst}, {stq_3_bits_uop_stale_pdst}, {stq_2_bits_uop_stale_pdst}, {stq_1_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_47 = {{stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_23_bits_uop_exception}, {stq_22_bits_uop_exception}, {stq_21_bits_uop_exception}, {stq_20_bits_uop_exception}, {stq_19_bits_uop_exception}, {stq_18_bits_uop_exception}, {stq_17_bits_uop_exception}, {stq_16_bits_uop_exception}, {stq_15_bits_uop_exception}, {stq_14_bits_uop_exception}, {stq_13_bits_uop_exception}, {stq_12_bits_uop_exception}, {stq_11_bits_uop_exception}, {stq_10_bits_uop_exception}, {stq_9_bits_uop_exception}, {stq_8_bits_uop_exception}, {stq_7_bits_uop_exception}, {stq_6_bits_uop_exception}, {stq_5_bits_uop_exception}, {stq_4_bits_uop_exception}, {stq_3_bits_uop_exception}, {stq_2_bits_uop_exception}, {stq_1_bits_uop_exception}, {stq_0_bits_uop_exception}}; // @[lsu.scala:209:16, :222:42]
wire _GEN_48 = _GEN_47[stq_execute_head]; // @[lsu.scala:218:29, :222:42]
wire [31:0][63:0] _GEN_49 = {{stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_23_bits_uop_exc_cause}, {stq_22_bits_uop_exc_cause}, {stq_21_bits_uop_exc_cause}, {stq_20_bits_uop_exc_cause}, {stq_19_bits_uop_exc_cause}, {stq_18_bits_uop_exc_cause}, {stq_17_bits_uop_exc_cause}, {stq_16_bits_uop_exc_cause}, {stq_15_bits_uop_exc_cause}, {stq_14_bits_uop_exc_cause}, {stq_13_bits_uop_exc_cause}, {stq_12_bits_uop_exc_cause}, {stq_11_bits_uop_exc_cause}, {stq_10_bits_uop_exc_cause}, {stq_9_bits_uop_exc_cause}, {stq_8_bits_uop_exc_cause}, {stq_7_bits_uop_exc_cause}, {stq_6_bits_uop_exc_cause}, {stq_5_bits_uop_exc_cause}, {stq_4_bits_uop_exc_cause}, {stq_3_bits_uop_exc_cause}, {stq_2_bits_uop_exc_cause}, {stq_1_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_50 = {{stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_23_bits_uop_bypassable}, {stq_22_bits_uop_bypassable}, {stq_21_bits_uop_bypassable}, {stq_20_bits_uop_bypassable}, {stq_19_bits_uop_bypassable}, {stq_18_bits_uop_bypassable}, {stq_17_bits_uop_bypassable}, {stq_16_bits_uop_bypassable}, {stq_15_bits_uop_bypassable}, {stq_14_bits_uop_bypassable}, {stq_13_bits_uop_bypassable}, {stq_12_bits_uop_bypassable}, {stq_11_bits_uop_bypassable}, {stq_10_bits_uop_bypassable}, {stq_9_bits_uop_bypassable}, {stq_8_bits_uop_bypassable}, {stq_7_bits_uop_bypassable}, {stq_6_bits_uop_bypassable}, {stq_5_bits_uop_bypassable}, {stq_4_bits_uop_bypassable}, {stq_3_bits_uop_bypassable}, {stq_2_bits_uop_bypassable}, {stq_1_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][4:0] _GEN_51 = {{stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_23_bits_uop_mem_cmd}, {stq_22_bits_uop_mem_cmd}, {stq_21_bits_uop_mem_cmd}, {stq_20_bits_uop_mem_cmd}, {stq_19_bits_uop_mem_cmd}, {stq_18_bits_uop_mem_cmd}, {stq_17_bits_uop_mem_cmd}, {stq_16_bits_uop_mem_cmd}, {stq_15_bits_uop_mem_cmd}, {stq_14_bits_uop_mem_cmd}, {stq_13_bits_uop_mem_cmd}, {stq_12_bits_uop_mem_cmd}, {stq_11_bits_uop_mem_cmd}, {stq_10_bits_uop_mem_cmd}, {stq_9_bits_uop_mem_cmd}, {stq_8_bits_uop_mem_cmd}, {stq_7_bits_uop_mem_cmd}, {stq_6_bits_uop_mem_cmd}, {stq_5_bits_uop_mem_cmd}, {stq_4_bits_uop_mem_cmd}, {stq_3_bits_uop_mem_cmd}, {stq_2_bits_uop_mem_cmd}, {stq_1_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_52 = {{stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_23_bits_uop_mem_size}, {stq_22_bits_uop_mem_size}, {stq_21_bits_uop_mem_size}, {stq_20_bits_uop_mem_size}, {stq_19_bits_uop_mem_size}, {stq_18_bits_uop_mem_size}, {stq_17_bits_uop_mem_size}, {stq_16_bits_uop_mem_size}, {stq_15_bits_uop_mem_size}, {stq_14_bits_uop_mem_size}, {stq_13_bits_uop_mem_size}, {stq_12_bits_uop_mem_size}, {stq_11_bits_uop_mem_size}, {stq_10_bits_uop_mem_size}, {stq_9_bits_uop_mem_size}, {stq_8_bits_uop_mem_size}, {stq_7_bits_uop_mem_size}, {stq_6_bits_uop_mem_size}, {stq_5_bits_uop_mem_size}, {stq_4_bits_uop_mem_size}, {stq_3_bits_uop_mem_size}, {stq_2_bits_uop_mem_size}, {stq_1_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}}; // @[lsu.scala:209:16, :222:42]
wire [1:0] dmem_req_0_bits_data_size = _GEN_52[stq_execute_head]; // @[AMOALU.scala:11:18]
wire [31:0] _GEN_53 = {{stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_23_bits_uop_mem_signed}, {stq_22_bits_uop_mem_signed}, {stq_21_bits_uop_mem_signed}, {stq_20_bits_uop_mem_signed}, {stq_19_bits_uop_mem_signed}, {stq_18_bits_uop_mem_signed}, {stq_17_bits_uop_mem_signed}, {stq_16_bits_uop_mem_signed}, {stq_15_bits_uop_mem_signed}, {stq_14_bits_uop_mem_signed}, {stq_13_bits_uop_mem_signed}, {stq_12_bits_uop_mem_signed}, {stq_11_bits_uop_mem_signed}, {stq_10_bits_uop_mem_signed}, {stq_9_bits_uop_mem_signed}, {stq_8_bits_uop_mem_signed}, {stq_7_bits_uop_mem_signed}, {stq_6_bits_uop_mem_signed}, {stq_5_bits_uop_mem_signed}, {stq_4_bits_uop_mem_signed}, {stq_3_bits_uop_mem_signed}, {stq_2_bits_uop_mem_signed}, {stq_1_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_54 = {{stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_23_bits_uop_is_fence}, {stq_22_bits_uop_is_fence}, {stq_21_bits_uop_is_fence}, {stq_20_bits_uop_is_fence}, {stq_19_bits_uop_is_fence}, {stq_18_bits_uop_is_fence}, {stq_17_bits_uop_is_fence}, {stq_16_bits_uop_is_fence}, {stq_15_bits_uop_is_fence}, {stq_14_bits_uop_is_fence}, {stq_13_bits_uop_is_fence}, {stq_12_bits_uop_is_fence}, {stq_11_bits_uop_is_fence}, {stq_10_bits_uop_is_fence}, {stq_9_bits_uop_is_fence}, {stq_8_bits_uop_is_fence}, {stq_7_bits_uop_is_fence}, {stq_6_bits_uop_is_fence}, {stq_5_bits_uop_is_fence}, {stq_4_bits_uop_is_fence}, {stq_3_bits_uop_is_fence}, {stq_2_bits_uop_is_fence}, {stq_1_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}}; // @[lsu.scala:209:16, :222:42]
wire _GEN_55 = _GEN_54[stq_execute_head]; // @[lsu.scala:218:29, :222:42]
wire [31:0] _GEN_56 = {{stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_23_bits_uop_is_fencei}, {stq_22_bits_uop_is_fencei}, {stq_21_bits_uop_is_fencei}, {stq_20_bits_uop_is_fencei}, {stq_19_bits_uop_is_fencei}, {stq_18_bits_uop_is_fencei}, {stq_17_bits_uop_is_fencei}, {stq_16_bits_uop_is_fencei}, {stq_15_bits_uop_is_fencei}, {stq_14_bits_uop_is_fencei}, {stq_13_bits_uop_is_fencei}, {stq_12_bits_uop_is_fencei}, {stq_11_bits_uop_is_fencei}, {stq_10_bits_uop_is_fencei}, {stq_9_bits_uop_is_fencei}, {stq_8_bits_uop_is_fencei}, {stq_7_bits_uop_is_fencei}, {stq_6_bits_uop_is_fencei}, {stq_5_bits_uop_is_fencei}, {stq_4_bits_uop_is_fencei}, {stq_3_bits_uop_is_fencei}, {stq_2_bits_uop_is_fencei}, {stq_1_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_57 = {{stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_23_bits_uop_is_amo}, {stq_22_bits_uop_is_amo}, {stq_21_bits_uop_is_amo}, {stq_20_bits_uop_is_amo}, {stq_19_bits_uop_is_amo}, {stq_18_bits_uop_is_amo}, {stq_17_bits_uop_is_amo}, {stq_16_bits_uop_is_amo}, {stq_15_bits_uop_is_amo}, {stq_14_bits_uop_is_amo}, {stq_13_bits_uop_is_amo}, {stq_12_bits_uop_is_amo}, {stq_11_bits_uop_is_amo}, {stq_10_bits_uop_is_amo}, {stq_9_bits_uop_is_amo}, {stq_8_bits_uop_is_amo}, {stq_7_bits_uop_is_amo}, {stq_6_bits_uop_is_amo}, {stq_5_bits_uop_is_amo}, {stq_4_bits_uop_is_amo}, {stq_3_bits_uop_is_amo}, {stq_2_bits_uop_is_amo}, {stq_1_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}}; // @[lsu.scala:209:16, :222:42]
wire _GEN_58 = _GEN_57[stq_execute_head]; // @[lsu.scala:218:29, :222:42]
wire [31:0] _GEN_59 = {{stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_23_bits_uop_uses_ldq}, {stq_22_bits_uop_uses_ldq}, {stq_21_bits_uop_uses_ldq}, {stq_20_bits_uop_uses_ldq}, {stq_19_bits_uop_uses_ldq}, {stq_18_bits_uop_uses_ldq}, {stq_17_bits_uop_uses_ldq}, {stq_16_bits_uop_uses_ldq}, {stq_15_bits_uop_uses_ldq}, {stq_14_bits_uop_uses_ldq}, {stq_13_bits_uop_uses_ldq}, {stq_12_bits_uop_uses_ldq}, {stq_11_bits_uop_uses_ldq}, {stq_10_bits_uop_uses_ldq}, {stq_9_bits_uop_uses_ldq}, {stq_8_bits_uop_uses_ldq}, {stq_7_bits_uop_uses_ldq}, {stq_6_bits_uop_uses_ldq}, {stq_5_bits_uop_uses_ldq}, {stq_4_bits_uop_uses_ldq}, {stq_3_bits_uop_uses_ldq}, {stq_2_bits_uop_uses_ldq}, {stq_1_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_60 = {{stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_23_bits_uop_uses_stq}, {stq_22_bits_uop_uses_stq}, {stq_21_bits_uop_uses_stq}, {stq_20_bits_uop_uses_stq}, {stq_19_bits_uop_uses_stq}, {stq_18_bits_uop_uses_stq}, {stq_17_bits_uop_uses_stq}, {stq_16_bits_uop_uses_stq}, {stq_15_bits_uop_uses_stq}, {stq_14_bits_uop_uses_stq}, {stq_13_bits_uop_uses_stq}, {stq_12_bits_uop_uses_stq}, {stq_11_bits_uop_uses_stq}, {stq_10_bits_uop_uses_stq}, {stq_9_bits_uop_uses_stq}, {stq_8_bits_uop_uses_stq}, {stq_7_bits_uop_uses_stq}, {stq_6_bits_uop_uses_stq}, {stq_5_bits_uop_uses_stq}, {stq_4_bits_uop_uses_stq}, {stq_3_bits_uop_uses_stq}, {stq_2_bits_uop_uses_stq}, {stq_1_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_61 = {{stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_23_bits_uop_is_sys_pc2epc}, {stq_22_bits_uop_is_sys_pc2epc}, {stq_21_bits_uop_is_sys_pc2epc}, {stq_20_bits_uop_is_sys_pc2epc}, {stq_19_bits_uop_is_sys_pc2epc}, {stq_18_bits_uop_is_sys_pc2epc}, {stq_17_bits_uop_is_sys_pc2epc}, {stq_16_bits_uop_is_sys_pc2epc}, {stq_15_bits_uop_is_sys_pc2epc}, {stq_14_bits_uop_is_sys_pc2epc}, {stq_13_bits_uop_is_sys_pc2epc}, {stq_12_bits_uop_is_sys_pc2epc}, {stq_11_bits_uop_is_sys_pc2epc}, {stq_10_bits_uop_is_sys_pc2epc}, {stq_9_bits_uop_is_sys_pc2epc}, {stq_8_bits_uop_is_sys_pc2epc}, {stq_7_bits_uop_is_sys_pc2epc}, {stq_6_bits_uop_is_sys_pc2epc}, {stq_5_bits_uop_is_sys_pc2epc}, {stq_4_bits_uop_is_sys_pc2epc}, {stq_3_bits_uop_is_sys_pc2epc}, {stq_2_bits_uop_is_sys_pc2epc}, {stq_1_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_62 = {{stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_23_bits_uop_is_unique}, {stq_22_bits_uop_is_unique}, {stq_21_bits_uop_is_unique}, {stq_20_bits_uop_is_unique}, {stq_19_bits_uop_is_unique}, {stq_18_bits_uop_is_unique}, {stq_17_bits_uop_is_unique}, {stq_16_bits_uop_is_unique}, {stq_15_bits_uop_is_unique}, {stq_14_bits_uop_is_unique}, {stq_13_bits_uop_is_unique}, {stq_12_bits_uop_is_unique}, {stq_11_bits_uop_is_unique}, {stq_10_bits_uop_is_unique}, {stq_9_bits_uop_is_unique}, {stq_8_bits_uop_is_unique}, {stq_7_bits_uop_is_unique}, {stq_6_bits_uop_is_unique}, {stq_5_bits_uop_is_unique}, {stq_4_bits_uop_is_unique}, {stq_3_bits_uop_is_unique}, {stq_2_bits_uop_is_unique}, {stq_1_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_63 = {{stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_23_bits_uop_flush_on_commit}, {stq_22_bits_uop_flush_on_commit}, {stq_21_bits_uop_flush_on_commit}, {stq_20_bits_uop_flush_on_commit}, {stq_19_bits_uop_flush_on_commit}, {stq_18_bits_uop_flush_on_commit}, {stq_17_bits_uop_flush_on_commit}, {stq_16_bits_uop_flush_on_commit}, {stq_15_bits_uop_flush_on_commit}, {stq_14_bits_uop_flush_on_commit}, {stq_13_bits_uop_flush_on_commit}, {stq_12_bits_uop_flush_on_commit}, {stq_11_bits_uop_flush_on_commit}, {stq_10_bits_uop_flush_on_commit}, {stq_9_bits_uop_flush_on_commit}, {stq_8_bits_uop_flush_on_commit}, {stq_7_bits_uop_flush_on_commit}, {stq_6_bits_uop_flush_on_commit}, {stq_5_bits_uop_flush_on_commit}, {stq_4_bits_uop_flush_on_commit}, {stq_3_bits_uop_flush_on_commit}, {stq_2_bits_uop_flush_on_commit}, {stq_1_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_64 = {{stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_23_bits_uop_ldst_is_rs1}, {stq_22_bits_uop_ldst_is_rs1}, {stq_21_bits_uop_ldst_is_rs1}, {stq_20_bits_uop_ldst_is_rs1}, {stq_19_bits_uop_ldst_is_rs1}, {stq_18_bits_uop_ldst_is_rs1}, {stq_17_bits_uop_ldst_is_rs1}, {stq_16_bits_uop_ldst_is_rs1}, {stq_15_bits_uop_ldst_is_rs1}, {stq_14_bits_uop_ldst_is_rs1}, {stq_13_bits_uop_ldst_is_rs1}, {stq_12_bits_uop_ldst_is_rs1}, {stq_11_bits_uop_ldst_is_rs1}, {stq_10_bits_uop_ldst_is_rs1}, {stq_9_bits_uop_ldst_is_rs1}, {stq_8_bits_uop_ldst_is_rs1}, {stq_7_bits_uop_ldst_is_rs1}, {stq_6_bits_uop_ldst_is_rs1}, {stq_5_bits_uop_ldst_is_rs1}, {stq_4_bits_uop_ldst_is_rs1}, {stq_3_bits_uop_ldst_is_rs1}, {stq_2_bits_uop_ldst_is_rs1}, {stq_1_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][5:0] _GEN_65 = {{stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_23_bits_uop_ldst}, {stq_22_bits_uop_ldst}, {stq_21_bits_uop_ldst}, {stq_20_bits_uop_ldst}, {stq_19_bits_uop_ldst}, {stq_18_bits_uop_ldst}, {stq_17_bits_uop_ldst}, {stq_16_bits_uop_ldst}, {stq_15_bits_uop_ldst}, {stq_14_bits_uop_ldst}, {stq_13_bits_uop_ldst}, {stq_12_bits_uop_ldst}, {stq_11_bits_uop_ldst}, {stq_10_bits_uop_ldst}, {stq_9_bits_uop_ldst}, {stq_8_bits_uop_ldst}, {stq_7_bits_uop_ldst}, {stq_6_bits_uop_ldst}, {stq_5_bits_uop_ldst}, {stq_4_bits_uop_ldst}, {stq_3_bits_uop_ldst}, {stq_2_bits_uop_ldst}, {stq_1_bits_uop_ldst}, {stq_0_bits_uop_ldst}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][5:0] _GEN_66 = {{stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_23_bits_uop_lrs1}, {stq_22_bits_uop_lrs1}, {stq_21_bits_uop_lrs1}, {stq_20_bits_uop_lrs1}, {stq_19_bits_uop_lrs1}, {stq_18_bits_uop_lrs1}, {stq_17_bits_uop_lrs1}, {stq_16_bits_uop_lrs1}, {stq_15_bits_uop_lrs1}, {stq_14_bits_uop_lrs1}, {stq_13_bits_uop_lrs1}, {stq_12_bits_uop_lrs1}, {stq_11_bits_uop_lrs1}, {stq_10_bits_uop_lrs1}, {stq_9_bits_uop_lrs1}, {stq_8_bits_uop_lrs1}, {stq_7_bits_uop_lrs1}, {stq_6_bits_uop_lrs1}, {stq_5_bits_uop_lrs1}, {stq_4_bits_uop_lrs1}, {stq_3_bits_uop_lrs1}, {stq_2_bits_uop_lrs1}, {stq_1_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][5:0] _GEN_67 = {{stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_23_bits_uop_lrs2}, {stq_22_bits_uop_lrs2}, {stq_21_bits_uop_lrs2}, {stq_20_bits_uop_lrs2}, {stq_19_bits_uop_lrs2}, {stq_18_bits_uop_lrs2}, {stq_17_bits_uop_lrs2}, {stq_16_bits_uop_lrs2}, {stq_15_bits_uop_lrs2}, {stq_14_bits_uop_lrs2}, {stq_13_bits_uop_lrs2}, {stq_12_bits_uop_lrs2}, {stq_11_bits_uop_lrs2}, {stq_10_bits_uop_lrs2}, {stq_9_bits_uop_lrs2}, {stq_8_bits_uop_lrs2}, {stq_7_bits_uop_lrs2}, {stq_6_bits_uop_lrs2}, {stq_5_bits_uop_lrs2}, {stq_4_bits_uop_lrs2}, {stq_3_bits_uop_lrs2}, {stq_2_bits_uop_lrs2}, {stq_1_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][5:0] _GEN_68 = {{stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_23_bits_uop_lrs3}, {stq_22_bits_uop_lrs3}, {stq_21_bits_uop_lrs3}, {stq_20_bits_uop_lrs3}, {stq_19_bits_uop_lrs3}, {stq_18_bits_uop_lrs3}, {stq_17_bits_uop_lrs3}, {stq_16_bits_uop_lrs3}, {stq_15_bits_uop_lrs3}, {stq_14_bits_uop_lrs3}, {stq_13_bits_uop_lrs3}, {stq_12_bits_uop_lrs3}, {stq_11_bits_uop_lrs3}, {stq_10_bits_uop_lrs3}, {stq_9_bits_uop_lrs3}, {stq_8_bits_uop_lrs3}, {stq_7_bits_uop_lrs3}, {stq_6_bits_uop_lrs3}, {stq_5_bits_uop_lrs3}, {stq_4_bits_uop_lrs3}, {stq_3_bits_uop_lrs3}, {stq_2_bits_uop_lrs3}, {stq_1_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_69 = {{stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_23_bits_uop_ldst_val}, {stq_22_bits_uop_ldst_val}, {stq_21_bits_uop_ldst_val}, {stq_20_bits_uop_ldst_val}, {stq_19_bits_uop_ldst_val}, {stq_18_bits_uop_ldst_val}, {stq_17_bits_uop_ldst_val}, {stq_16_bits_uop_ldst_val}, {stq_15_bits_uop_ldst_val}, {stq_14_bits_uop_ldst_val}, {stq_13_bits_uop_ldst_val}, {stq_12_bits_uop_ldst_val}, {stq_11_bits_uop_ldst_val}, {stq_10_bits_uop_ldst_val}, {stq_9_bits_uop_ldst_val}, {stq_8_bits_uop_ldst_val}, {stq_7_bits_uop_ldst_val}, {stq_6_bits_uop_ldst_val}, {stq_5_bits_uop_ldst_val}, {stq_4_bits_uop_ldst_val}, {stq_3_bits_uop_ldst_val}, {stq_2_bits_uop_ldst_val}, {stq_1_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_70 = {{stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_23_bits_uop_dst_rtype}, {stq_22_bits_uop_dst_rtype}, {stq_21_bits_uop_dst_rtype}, {stq_20_bits_uop_dst_rtype}, {stq_19_bits_uop_dst_rtype}, {stq_18_bits_uop_dst_rtype}, {stq_17_bits_uop_dst_rtype}, {stq_16_bits_uop_dst_rtype}, {stq_15_bits_uop_dst_rtype}, {stq_14_bits_uop_dst_rtype}, {stq_13_bits_uop_dst_rtype}, {stq_12_bits_uop_dst_rtype}, {stq_11_bits_uop_dst_rtype}, {stq_10_bits_uop_dst_rtype}, {stq_9_bits_uop_dst_rtype}, {stq_8_bits_uop_dst_rtype}, {stq_7_bits_uop_dst_rtype}, {stq_6_bits_uop_dst_rtype}, {stq_5_bits_uop_dst_rtype}, {stq_4_bits_uop_dst_rtype}, {stq_3_bits_uop_dst_rtype}, {stq_2_bits_uop_dst_rtype}, {stq_1_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_71 = {{stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_23_bits_uop_lrs1_rtype}, {stq_22_bits_uop_lrs1_rtype}, {stq_21_bits_uop_lrs1_rtype}, {stq_20_bits_uop_lrs1_rtype}, {stq_19_bits_uop_lrs1_rtype}, {stq_18_bits_uop_lrs1_rtype}, {stq_17_bits_uop_lrs1_rtype}, {stq_16_bits_uop_lrs1_rtype}, {stq_15_bits_uop_lrs1_rtype}, {stq_14_bits_uop_lrs1_rtype}, {stq_13_bits_uop_lrs1_rtype}, {stq_12_bits_uop_lrs1_rtype}, {stq_11_bits_uop_lrs1_rtype}, {stq_10_bits_uop_lrs1_rtype}, {stq_9_bits_uop_lrs1_rtype}, {stq_8_bits_uop_lrs1_rtype}, {stq_7_bits_uop_lrs1_rtype}, {stq_6_bits_uop_lrs1_rtype}, {stq_5_bits_uop_lrs1_rtype}, {stq_4_bits_uop_lrs1_rtype}, {stq_3_bits_uop_lrs1_rtype}, {stq_2_bits_uop_lrs1_rtype}, {stq_1_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_72 = {{stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_23_bits_uop_lrs2_rtype}, {stq_22_bits_uop_lrs2_rtype}, {stq_21_bits_uop_lrs2_rtype}, {stq_20_bits_uop_lrs2_rtype}, {stq_19_bits_uop_lrs2_rtype}, {stq_18_bits_uop_lrs2_rtype}, {stq_17_bits_uop_lrs2_rtype}, {stq_16_bits_uop_lrs2_rtype}, {stq_15_bits_uop_lrs2_rtype}, {stq_14_bits_uop_lrs2_rtype}, {stq_13_bits_uop_lrs2_rtype}, {stq_12_bits_uop_lrs2_rtype}, {stq_11_bits_uop_lrs2_rtype}, {stq_10_bits_uop_lrs2_rtype}, {stq_9_bits_uop_lrs2_rtype}, {stq_8_bits_uop_lrs2_rtype}, {stq_7_bits_uop_lrs2_rtype}, {stq_6_bits_uop_lrs2_rtype}, {stq_5_bits_uop_lrs2_rtype}, {stq_4_bits_uop_lrs2_rtype}, {stq_3_bits_uop_lrs2_rtype}, {stq_2_bits_uop_lrs2_rtype}, {stq_1_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_73 = {{stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_23_bits_uop_frs3_en}, {stq_22_bits_uop_frs3_en}, {stq_21_bits_uop_frs3_en}, {stq_20_bits_uop_frs3_en}, {stq_19_bits_uop_frs3_en}, {stq_18_bits_uop_frs3_en}, {stq_17_bits_uop_frs3_en}, {stq_16_bits_uop_frs3_en}, {stq_15_bits_uop_frs3_en}, {stq_14_bits_uop_frs3_en}, {stq_13_bits_uop_frs3_en}, {stq_12_bits_uop_frs3_en}, {stq_11_bits_uop_frs3_en}, {stq_10_bits_uop_frs3_en}, {stq_9_bits_uop_frs3_en}, {stq_8_bits_uop_frs3_en}, {stq_7_bits_uop_frs3_en}, {stq_6_bits_uop_frs3_en}, {stq_5_bits_uop_frs3_en}, {stq_4_bits_uop_frs3_en}, {stq_3_bits_uop_frs3_en}, {stq_2_bits_uop_frs3_en}, {stq_1_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_74 = {{stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_23_bits_uop_fp_val}, {stq_22_bits_uop_fp_val}, {stq_21_bits_uop_fp_val}, {stq_20_bits_uop_fp_val}, {stq_19_bits_uop_fp_val}, {stq_18_bits_uop_fp_val}, {stq_17_bits_uop_fp_val}, {stq_16_bits_uop_fp_val}, {stq_15_bits_uop_fp_val}, {stq_14_bits_uop_fp_val}, {stq_13_bits_uop_fp_val}, {stq_12_bits_uop_fp_val}, {stq_11_bits_uop_fp_val}, {stq_10_bits_uop_fp_val}, {stq_9_bits_uop_fp_val}, {stq_8_bits_uop_fp_val}, {stq_7_bits_uop_fp_val}, {stq_6_bits_uop_fp_val}, {stq_5_bits_uop_fp_val}, {stq_4_bits_uop_fp_val}, {stq_3_bits_uop_fp_val}, {stq_2_bits_uop_fp_val}, {stq_1_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_75 = {{stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_23_bits_uop_fp_single}, {stq_22_bits_uop_fp_single}, {stq_21_bits_uop_fp_single}, {stq_20_bits_uop_fp_single}, {stq_19_bits_uop_fp_single}, {stq_18_bits_uop_fp_single}, {stq_17_bits_uop_fp_single}, {stq_16_bits_uop_fp_single}, {stq_15_bits_uop_fp_single}, {stq_14_bits_uop_fp_single}, {stq_13_bits_uop_fp_single}, {stq_12_bits_uop_fp_single}, {stq_11_bits_uop_fp_single}, {stq_10_bits_uop_fp_single}, {stq_9_bits_uop_fp_single}, {stq_8_bits_uop_fp_single}, {stq_7_bits_uop_fp_single}, {stq_6_bits_uop_fp_single}, {stq_5_bits_uop_fp_single}, {stq_4_bits_uop_fp_single}, {stq_3_bits_uop_fp_single}, {stq_2_bits_uop_fp_single}, {stq_1_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_76 = {{stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_23_bits_uop_xcpt_pf_if}, {stq_22_bits_uop_xcpt_pf_if}, {stq_21_bits_uop_xcpt_pf_if}, {stq_20_bits_uop_xcpt_pf_if}, {stq_19_bits_uop_xcpt_pf_if}, {stq_18_bits_uop_xcpt_pf_if}, {stq_17_bits_uop_xcpt_pf_if}, {stq_16_bits_uop_xcpt_pf_if}, {stq_15_bits_uop_xcpt_pf_if}, {stq_14_bits_uop_xcpt_pf_if}, {stq_13_bits_uop_xcpt_pf_if}, {stq_12_bits_uop_xcpt_pf_if}, {stq_11_bits_uop_xcpt_pf_if}, {stq_10_bits_uop_xcpt_pf_if}, {stq_9_bits_uop_xcpt_pf_if}, {stq_8_bits_uop_xcpt_pf_if}, {stq_7_bits_uop_xcpt_pf_if}, {stq_6_bits_uop_xcpt_pf_if}, {stq_5_bits_uop_xcpt_pf_if}, {stq_4_bits_uop_xcpt_pf_if}, {stq_3_bits_uop_xcpt_pf_if}, {stq_2_bits_uop_xcpt_pf_if}, {stq_1_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_77 = {{stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_23_bits_uop_xcpt_ae_if}, {stq_22_bits_uop_xcpt_ae_if}, {stq_21_bits_uop_xcpt_ae_if}, {stq_20_bits_uop_xcpt_ae_if}, {stq_19_bits_uop_xcpt_ae_if}, {stq_18_bits_uop_xcpt_ae_if}, {stq_17_bits_uop_xcpt_ae_if}, {stq_16_bits_uop_xcpt_ae_if}, {stq_15_bits_uop_xcpt_ae_if}, {stq_14_bits_uop_xcpt_ae_if}, {stq_13_bits_uop_xcpt_ae_if}, {stq_12_bits_uop_xcpt_ae_if}, {stq_11_bits_uop_xcpt_ae_if}, {stq_10_bits_uop_xcpt_ae_if}, {stq_9_bits_uop_xcpt_ae_if}, {stq_8_bits_uop_xcpt_ae_if}, {stq_7_bits_uop_xcpt_ae_if}, {stq_6_bits_uop_xcpt_ae_if}, {stq_5_bits_uop_xcpt_ae_if}, {stq_4_bits_uop_xcpt_ae_if}, {stq_3_bits_uop_xcpt_ae_if}, {stq_2_bits_uop_xcpt_ae_if}, {stq_1_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_78 = {{stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_23_bits_uop_xcpt_ma_if}, {stq_22_bits_uop_xcpt_ma_if}, {stq_21_bits_uop_xcpt_ma_if}, {stq_20_bits_uop_xcpt_ma_if}, {stq_19_bits_uop_xcpt_ma_if}, {stq_18_bits_uop_xcpt_ma_if}, {stq_17_bits_uop_xcpt_ma_if}, {stq_16_bits_uop_xcpt_ma_if}, {stq_15_bits_uop_xcpt_ma_if}, {stq_14_bits_uop_xcpt_ma_if}, {stq_13_bits_uop_xcpt_ma_if}, {stq_12_bits_uop_xcpt_ma_if}, {stq_11_bits_uop_xcpt_ma_if}, {stq_10_bits_uop_xcpt_ma_if}, {stq_9_bits_uop_xcpt_ma_if}, {stq_8_bits_uop_xcpt_ma_if}, {stq_7_bits_uop_xcpt_ma_if}, {stq_6_bits_uop_xcpt_ma_if}, {stq_5_bits_uop_xcpt_ma_if}, {stq_4_bits_uop_xcpt_ma_if}, {stq_3_bits_uop_xcpt_ma_if}, {stq_2_bits_uop_xcpt_ma_if}, {stq_1_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_79 = {{stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_23_bits_uop_bp_debug_if}, {stq_22_bits_uop_bp_debug_if}, {stq_21_bits_uop_bp_debug_if}, {stq_20_bits_uop_bp_debug_if}, {stq_19_bits_uop_bp_debug_if}, {stq_18_bits_uop_bp_debug_if}, {stq_17_bits_uop_bp_debug_if}, {stq_16_bits_uop_bp_debug_if}, {stq_15_bits_uop_bp_debug_if}, {stq_14_bits_uop_bp_debug_if}, {stq_13_bits_uop_bp_debug_if}, {stq_12_bits_uop_bp_debug_if}, {stq_11_bits_uop_bp_debug_if}, {stq_10_bits_uop_bp_debug_if}, {stq_9_bits_uop_bp_debug_if}, {stq_8_bits_uop_bp_debug_if}, {stq_7_bits_uop_bp_debug_if}, {stq_6_bits_uop_bp_debug_if}, {stq_5_bits_uop_bp_debug_if}, {stq_4_bits_uop_bp_debug_if}, {stq_3_bits_uop_bp_debug_if}, {stq_2_bits_uop_bp_debug_if}, {stq_1_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_80 = {{stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_23_bits_uop_bp_xcpt_if}, {stq_22_bits_uop_bp_xcpt_if}, {stq_21_bits_uop_bp_xcpt_if}, {stq_20_bits_uop_bp_xcpt_if}, {stq_19_bits_uop_bp_xcpt_if}, {stq_18_bits_uop_bp_xcpt_if}, {stq_17_bits_uop_bp_xcpt_if}, {stq_16_bits_uop_bp_xcpt_if}, {stq_15_bits_uop_bp_xcpt_if}, {stq_14_bits_uop_bp_xcpt_if}, {stq_13_bits_uop_bp_xcpt_if}, {stq_12_bits_uop_bp_xcpt_if}, {stq_11_bits_uop_bp_xcpt_if}, {stq_10_bits_uop_bp_xcpt_if}, {stq_9_bits_uop_bp_xcpt_if}, {stq_8_bits_uop_bp_xcpt_if}, {stq_7_bits_uop_bp_xcpt_if}, {stq_6_bits_uop_bp_xcpt_if}, {stq_5_bits_uop_bp_xcpt_if}, {stq_4_bits_uop_bp_xcpt_if}, {stq_3_bits_uop_bp_xcpt_if}, {stq_2_bits_uop_bp_xcpt_if}, {stq_1_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_81 = {{stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_23_bits_uop_debug_fsrc}, {stq_22_bits_uop_debug_fsrc}, {stq_21_bits_uop_debug_fsrc}, {stq_20_bits_uop_debug_fsrc}, {stq_19_bits_uop_debug_fsrc}, {stq_18_bits_uop_debug_fsrc}, {stq_17_bits_uop_debug_fsrc}, {stq_16_bits_uop_debug_fsrc}, {stq_15_bits_uop_debug_fsrc}, {stq_14_bits_uop_debug_fsrc}, {stq_13_bits_uop_debug_fsrc}, {stq_12_bits_uop_debug_fsrc}, {stq_11_bits_uop_debug_fsrc}, {stq_10_bits_uop_debug_fsrc}, {stq_9_bits_uop_debug_fsrc}, {stq_8_bits_uop_debug_fsrc}, {stq_7_bits_uop_debug_fsrc}, {stq_6_bits_uop_debug_fsrc}, {stq_5_bits_uop_debug_fsrc}, {stq_4_bits_uop_debug_fsrc}, {stq_3_bits_uop_debug_fsrc}, {stq_2_bits_uop_debug_fsrc}, {stq_1_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][1:0] _GEN_82 = {{stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_23_bits_uop_debug_tsrc}, {stq_22_bits_uop_debug_tsrc}, {stq_21_bits_uop_debug_tsrc}, {stq_20_bits_uop_debug_tsrc}, {stq_19_bits_uop_debug_tsrc}, {stq_18_bits_uop_debug_tsrc}, {stq_17_bits_uop_debug_tsrc}, {stq_16_bits_uop_debug_tsrc}, {stq_15_bits_uop_debug_tsrc}, {stq_14_bits_uop_debug_tsrc}, {stq_13_bits_uop_debug_tsrc}, {stq_12_bits_uop_debug_tsrc}, {stq_11_bits_uop_debug_tsrc}, {stq_10_bits_uop_debug_tsrc}, {stq_9_bits_uop_debug_tsrc}, {stq_8_bits_uop_debug_tsrc}, {stq_7_bits_uop_debug_tsrc}, {stq_6_bits_uop_debug_tsrc}, {stq_5_bits_uop_debug_tsrc}, {stq_4_bits_uop_debug_tsrc}, {stq_3_bits_uop_debug_tsrc}, {stq_2_bits_uop_debug_tsrc}, {stq_1_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_83 = {{stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_23_bits_addr_valid}, {stq_22_bits_addr_valid}, {stq_21_bits_addr_valid}, {stq_20_bits_addr_valid}, {stq_19_bits_addr_valid}, {stq_18_bits_addr_valid}, {stq_17_bits_addr_valid}, {stq_16_bits_addr_valid}, {stq_15_bits_addr_valid}, {stq_14_bits_addr_valid}, {stq_13_bits_addr_valid}, {stq_12_bits_addr_valid}, {stq_11_bits_addr_valid}, {stq_10_bits_addr_valid}, {stq_9_bits_addr_valid}, {stq_8_bits_addr_valid}, {stq_7_bits_addr_valid}, {stq_6_bits_addr_valid}, {stq_5_bits_addr_valid}, {stq_4_bits_addr_valid}, {stq_3_bits_addr_valid}, {stq_2_bits_addr_valid}, {stq_1_bits_addr_valid}, {stq_0_bits_addr_valid}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][39:0] _GEN_84 = {{stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_23_bits_addr_bits}, {stq_22_bits_addr_bits}, {stq_21_bits_addr_bits}, {stq_20_bits_addr_bits}, {stq_19_bits_addr_bits}, {stq_18_bits_addr_bits}, {stq_17_bits_addr_bits}, {stq_16_bits_addr_bits}, {stq_15_bits_addr_bits}, {stq_14_bits_addr_bits}, {stq_13_bits_addr_bits}, {stq_12_bits_addr_bits}, {stq_11_bits_addr_bits}, {stq_10_bits_addr_bits}, {stq_9_bits_addr_bits}, {stq_8_bits_addr_bits}, {stq_7_bits_addr_bits}, {stq_6_bits_addr_bits}, {stq_5_bits_addr_bits}, {stq_4_bits_addr_bits}, {stq_3_bits_addr_bits}, {stq_2_bits_addr_bits}, {stq_1_bits_addr_bits}, {stq_0_bits_addr_bits}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_85 = {{stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_23_bits_addr_is_virtual}, {stq_22_bits_addr_is_virtual}, {stq_21_bits_addr_is_virtual}, {stq_20_bits_addr_is_virtual}, {stq_19_bits_addr_is_virtual}, {stq_18_bits_addr_is_virtual}, {stq_17_bits_addr_is_virtual}, {stq_16_bits_addr_is_virtual}, {stq_15_bits_addr_is_virtual}, {stq_14_bits_addr_is_virtual}, {stq_13_bits_addr_is_virtual}, {stq_12_bits_addr_is_virtual}, {stq_11_bits_addr_is_virtual}, {stq_10_bits_addr_is_virtual}, {stq_9_bits_addr_is_virtual}, {stq_8_bits_addr_is_virtual}, {stq_7_bits_addr_is_virtual}, {stq_6_bits_addr_is_virtual}, {stq_5_bits_addr_is_virtual}, {stq_4_bits_addr_is_virtual}, {stq_3_bits_addr_is_virtual}, {stq_2_bits_addr_is_virtual}, {stq_1_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}}; // @[lsu.scala:209:16, :222:42]
wire [31:0] _GEN_86 = {{stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_23_bits_data_valid}, {stq_22_bits_data_valid}, {stq_21_bits_data_valid}, {stq_20_bits_data_valid}, {stq_19_bits_data_valid}, {stq_18_bits_data_valid}, {stq_17_bits_data_valid}, {stq_16_bits_data_valid}, {stq_15_bits_data_valid}, {stq_14_bits_data_valid}, {stq_13_bits_data_valid}, {stq_12_bits_data_valid}, {stq_11_bits_data_valid}, {stq_10_bits_data_valid}, {stq_9_bits_data_valid}, {stq_8_bits_data_valid}, {stq_7_bits_data_valid}, {stq_6_bits_data_valid}, {stq_5_bits_data_valid}, {stq_4_bits_data_valid}, {stq_3_bits_data_valid}, {stq_2_bits_data_valid}, {stq_1_bits_data_valid}, {stq_0_bits_data_valid}}; // @[lsu.scala:209:16, :222:42]
wire [31:0][63:0] _GEN_87 = {{stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_23_bits_data_bits}, {stq_22_bits_data_bits}, {stq_21_bits_data_bits}, {stq_20_bits_data_bits}, {stq_19_bits_data_bits}, {stq_18_bits_data_bits}, {stq_17_bits_data_bits}, {stq_16_bits_data_bits}, {stq_15_bits_data_bits}, {stq_14_bits_data_bits}, {stq_13_bits_data_bits}, {stq_12_bits_data_bits}, {stq_11_bits_data_bits}, {stq_10_bits_data_bits}, {stq_9_bits_data_bits}, {stq_8_bits_data_bits}, {stq_7_bits_data_bits}, {stq_6_bits_data_bits}, {stq_5_bits_data_bits}, {stq_4_bits_data_bits}, {stq_3_bits_data_bits}, {stq_2_bits_data_bits}, {stq_1_bits_data_bits}, {stq_0_bits_data_bits}}; // @[lsu.scala:209:16, :222:42]
wire [63:0] _GEN_88 = _GEN_87[stq_execute_head]; // @[lsu.scala:218:29, :222:42]
wire [31:0] _GEN_89 = {{stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_23_bits_committed}, {stq_22_bits_committed}, {stq_21_bits_committed}, {stq_20_bits_committed}, {stq_19_bits_committed}, {stq_18_bits_committed}, {stq_17_bits_committed}, {stq_16_bits_committed}, {stq_15_bits_committed}, {stq_14_bits_committed}, {stq_13_bits_committed}, {stq_12_bits_committed}, {stq_11_bits_committed}, {stq_10_bits_committed}, {stq_9_bits_committed}, {stq_8_bits_committed}, {stq_7_bits_committed}, {stq_6_bits_committed}, {stq_5_bits_committed}, {stq_4_bits_committed}, {stq_3_bits_committed}, {stq_2_bits_committed}, {stq_1_bits_committed}, {stq_0_bits_committed}}; // @[lsu.scala:209:16, :222:42]
reg [2:0] hella_state; // @[lsu.scala:240:38]
reg [39:0] hella_req_addr; // @[lsu.scala:241:34]
assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:201:7, :241:34]
reg hella_req_dv; // @[lsu.scala:241:34]
reg [63:0] hella_data_data; // @[lsu.scala:242:34]
wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13]
reg [7:0] hella_data_mask; // @[lsu.scala:242:34]
reg [31:0] hella_paddr; // @[lsu.scala:243:34]
reg hella_xcpt_ma_ld; // @[lsu.scala:244:34]
reg hella_xcpt_ma_st; // @[lsu.scala:244:34]
reg hella_xcpt_pf_ld; // @[lsu.scala:244:34]
reg hella_xcpt_pf_st; // @[lsu.scala:244:34]
reg hella_xcpt_gf_ld; // @[lsu.scala:244:34]
reg hella_xcpt_gf_st; // @[lsu.scala:244:34]
reg hella_xcpt_ae_ld; // @[lsu.scala:244:34]
reg hella_xcpt_ae_st; // @[lsu.scala:244:34]
assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35]
assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35]
wire clear_store; // @[lsu.scala:257:33]
reg [23:0] live_store_mask; // @[lsu.scala:258:32]
wire [31:0] _GEN_90 = 32'h1 << stq_head; // @[lsu.scala:215:29, :259:71]
wire [31:0] _next_live_store_mask_T; // @[lsu.scala:259:71]
assign _next_live_store_mask_T = _GEN_90; // @[lsu.scala:259:71]
wire [31:0] _ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_0_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_1_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_2_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_3_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_4_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_5_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_6_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_7_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_8_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_8_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_9_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_9_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_10_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_10_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_11_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_11_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_12_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_12_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_13_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_13_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_14_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_14_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_15_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_15_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_16_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_16_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_17_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_17_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_18_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_18_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_19_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_19_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_20_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_20_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_21_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_21_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_22_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_22_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _ldq_23_bits_st_dep_mask_T; // @[lsu.scala:277:66]
assign _ldq_23_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66]
wire [31:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:259:{65,71}]
wire [31:0] _next_live_store_mask_T_2 = {8'h0, _next_live_store_mask_T_1[23:0] & live_store_mask}; // @[lsu.scala:258:32, :259:{63,65}]
wire [31:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : {8'h0, live_store_mask}; // @[lsu.scala:257:33, :258:32, :259:{33,63}]
wire [31:0] _ldq_0_bits_st_dep_mask_T_1 = ~_ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_0_bits_st_dep_mask_T_2 = {8'h0, _ldq_0_bits_st_dep_mask_T_1[23:0] & ldq_0_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_1_bits_st_dep_mask_T_1 = ~_ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_1_bits_st_dep_mask_T_2 = {8'h0, _ldq_1_bits_st_dep_mask_T_1[23:0] & ldq_1_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_2_bits_st_dep_mask_T_1 = ~_ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_2_bits_st_dep_mask_T_2 = {8'h0, _ldq_2_bits_st_dep_mask_T_1[23:0] & ldq_2_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_3_bits_st_dep_mask_T_1 = ~_ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_3_bits_st_dep_mask_T_2 = {8'h0, _ldq_3_bits_st_dep_mask_T_1[23:0] & ldq_3_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_4_bits_st_dep_mask_T_1 = ~_ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_4_bits_st_dep_mask_T_2 = {8'h0, _ldq_4_bits_st_dep_mask_T_1[23:0] & ldq_4_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_5_bits_st_dep_mask_T_1 = ~_ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_5_bits_st_dep_mask_T_2 = {8'h0, _ldq_5_bits_st_dep_mask_T_1[23:0] & ldq_5_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_6_bits_st_dep_mask_T_1 = ~_ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_6_bits_st_dep_mask_T_2 = {8'h0, _ldq_6_bits_st_dep_mask_T_1[23:0] & ldq_6_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_7_bits_st_dep_mask_T_1 = ~_ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_7_bits_st_dep_mask_T_2 = {8'h0, _ldq_7_bits_st_dep_mask_T_1[23:0] & ldq_7_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_8_bits_st_dep_mask_T_1 = ~_ldq_8_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_8_bits_st_dep_mask_T_2 = {8'h0, _ldq_8_bits_st_dep_mask_T_1[23:0] & ldq_8_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_9_bits_st_dep_mask_T_1 = ~_ldq_9_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_9_bits_st_dep_mask_T_2 = {8'h0, _ldq_9_bits_st_dep_mask_T_1[23:0] & ldq_9_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_10_bits_st_dep_mask_T_1 = ~_ldq_10_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_10_bits_st_dep_mask_T_2 = {8'h0, _ldq_10_bits_st_dep_mask_T_1[23:0] & ldq_10_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_11_bits_st_dep_mask_T_1 = ~_ldq_11_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_11_bits_st_dep_mask_T_2 = {8'h0, _ldq_11_bits_st_dep_mask_T_1[23:0] & ldq_11_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_12_bits_st_dep_mask_T_1 = ~_ldq_12_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_12_bits_st_dep_mask_T_2 = {8'h0, _ldq_12_bits_st_dep_mask_T_1[23:0] & ldq_12_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_13_bits_st_dep_mask_T_1 = ~_ldq_13_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_13_bits_st_dep_mask_T_2 = {8'h0, _ldq_13_bits_st_dep_mask_T_1[23:0] & ldq_13_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_14_bits_st_dep_mask_T_1 = ~_ldq_14_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_14_bits_st_dep_mask_T_2 = {8'h0, _ldq_14_bits_st_dep_mask_T_1[23:0] & ldq_14_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_15_bits_st_dep_mask_T_1 = ~_ldq_15_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_15_bits_st_dep_mask_T_2 = {8'h0, _ldq_15_bits_st_dep_mask_T_1[23:0] & ldq_15_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_16_bits_st_dep_mask_T_1 = ~_ldq_16_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_16_bits_st_dep_mask_T_2 = {8'h0, _ldq_16_bits_st_dep_mask_T_1[23:0] & ldq_16_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_17_bits_st_dep_mask_T_1 = ~_ldq_17_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_17_bits_st_dep_mask_T_2 = {8'h0, _ldq_17_bits_st_dep_mask_T_1[23:0] & ldq_17_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_18_bits_st_dep_mask_T_1 = ~_ldq_18_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_18_bits_st_dep_mask_T_2 = {8'h0, _ldq_18_bits_st_dep_mask_T_1[23:0] & ldq_18_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_19_bits_st_dep_mask_T_1 = ~_ldq_19_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_19_bits_st_dep_mask_T_2 = {8'h0, _ldq_19_bits_st_dep_mask_T_1[23:0] & ldq_19_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_20_bits_st_dep_mask_T_1 = ~_ldq_20_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_20_bits_st_dep_mask_T_2 = {8'h0, _ldq_20_bits_st_dep_mask_T_1[23:0] & ldq_20_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_21_bits_st_dep_mask_T_1 = ~_ldq_21_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_21_bits_st_dep_mask_T_2 = {8'h0, _ldq_21_bits_st_dep_mask_T_1[23:0] & ldq_21_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_22_bits_st_dep_mask_T_1 = ~_ldq_22_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_22_bits_st_dep_mask_T_2 = {8'h0, _ldq_22_bits_st_dep_mask_T_1[23:0] & ldq_22_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire [31:0] _ldq_23_bits_st_dep_mask_T_1 = ~_ldq_23_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}]
wire [31:0] _ldq_23_bits_st_dep_mask_T_2 = {8'h0, _ldq_23_bits_st_dep_mask_T_1[23:0] & ldq_23_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}]
wire _GEN_91 = stq_0_valid | stq_1_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T; // @[lsu.scala:285:79]
assign _stq_nonempty_T = _GEN_91; // @[lsu.scala:285:79]
wire _io_hellacache_store_pending_T; // @[lsu.scala:1530:59]
assign _io_hellacache_store_pending_T = _GEN_91; // @[lsu.scala:285:79, :1530:59]
wire _stq_nonempty_T_1 = _stq_nonempty_T | stq_2_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_2 = _stq_nonempty_T_1 | stq_3_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_3 = _stq_nonempty_T_2 | stq_4_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_4 = _stq_nonempty_T_3 | stq_5_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_5 = _stq_nonempty_T_4 | stq_6_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_6 = _stq_nonempty_T_5 | stq_7_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_7 = _stq_nonempty_T_6 | stq_8_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_8 = _stq_nonempty_T_7 | stq_9_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_9 = _stq_nonempty_T_8 | stq_10_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_10 = _stq_nonempty_T_9 | stq_11_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_11 = _stq_nonempty_T_10 | stq_12_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_12 = _stq_nonempty_T_11 | stq_13_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_13 = _stq_nonempty_T_12 | stq_14_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_14 = _stq_nonempty_T_13 | stq_15_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_15 = _stq_nonempty_T_14 | stq_16_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_16 = _stq_nonempty_T_15 | stq_17_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_17 = _stq_nonempty_T_16 | stq_18_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_18 = _stq_nonempty_T_17 | stq_19_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_19 = _stq_nonempty_T_18 | stq_20_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_20 = _stq_nonempty_T_19 | stq_21_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_21 = _stq_nonempty_T_20 | stq_22_valid; // @[lsu.scala:209:16, :285:79]
wire _stq_nonempty_T_22 = _stq_nonempty_T_21 | stq_23_valid; // @[lsu.scala:209:16, :285:79]
wire stq_nonempty = _stq_nonempty_T_22; // @[lsu.scala:285:{79,84}]
wire _GEN_92 = ldq_tail == 5'h17; // @[util.scala:205:25]
wire wrap; // @[util.scala:205:25]
assign wrap = _GEN_92; // @[util.scala:205:25]
wire wrap_2; // @[util.scala:205:25]
assign wrap_2 = _GEN_92; // @[util.scala:205:25]
wire [4:0] _T_32 = ldq_tail + 5'h1; // @[util.scala:206:28]
assign io_core_ldq_full_0_0 = (wrap ? 5'h0 : _T_32) == ldq_head; // @[util.scala:205:25, :206:{10,28}]
wire _GEN_93 = stq_tail == 5'h17; // @[util.scala:205:25]
wire wrap_1; // @[util.scala:205:25]
assign wrap_1 = _GEN_93; // @[util.scala:205:25]
wire wrap_3; // @[util.scala:205:25]
assign wrap_3 = _GEN_93; // @[util.scala:205:25]
wire [4:0] _T_39 = stq_tail + 5'h1; // @[util.scala:206:28]
assign io_core_stq_full_0_0 = (wrap_1 ? 5'h0 : _T_39) == stq_head; // @[util.scala:205:25, :206:{10,28}]
wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48]
wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88]
wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:300:{48,85,88}]
wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48]
wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88]
wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:301:{48,85,88}]
wire [31:0] _GEN_94 = {{ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_23_valid}, {ldq_22_valid}, {ldq_21_valid}, {ldq_20_valid}, {ldq_19_valid}, {ldq_18_valid}, {ldq_17_valid}, {ldq_16_valid}, {ldq_15_valid}, {ldq_14_valid}, {ldq_13_valid}, {ldq_12_valid}, {ldq_11_valid}, {ldq_10_valid}, {ldq_9_valid}, {ldq_8_valid}, {ldq_7_valid}, {ldq_6_valid}, {ldq_5_valid}, {ldq_4_valid}, {ldq_3_valid}, {ldq_2_valid}, {ldq_1_valid}, {ldq_0_valid}}; // @[lsu.scala:208:16, :304:44]
wire [4:0] _T_34 = wrap_2 ? 5'h0 : _T_32; // @[util.scala:205:25, :206:{10,28}]
assign io_core_dis_ldq_idx_1_0 = dis_ld_val ? _T_34 : ldq_tail; // @[util.scala:206:10]
wire [31:0] _T_36 = 32'h1 << stq_tail; // @[lsu.scala:216:29, :335:72]
wire [23:0] _T_38 = {24{dis_st_val}} & _T_36[23:0] | next_live_store_mask[23:0]; // @[lsu.scala:259:33, :301:85, :307:44, :335:{31,72}]
wire [4:0] _T_41 = wrap_3 ? 5'h0 : _T_39; // @[util.scala:205:25, :206:{10,28}]
assign io_core_dis_stq_idx_1_0 = dis_st_val ? _T_41 : stq_tail; // @[util.scala:206:10]
wire _GEN_95 = io_core_dis_ldq_idx_1_0 == 5'h17; // @[util.scala:205:25]
wire wrap_4; // @[util.scala:205:25]
assign wrap_4 = _GEN_95; // @[util.scala:205:25]
wire wrap_6; // @[util.scala:205:25]
assign wrap_6 = _GEN_95; // @[util.scala:205:25]
wire [4:0] _T_72 = io_core_dis_ldq_idx_1_0 + 5'h1; // @[util.scala:206:28]
assign io_core_ldq_full_1_0 = (wrap_4 ? 5'h0 : _T_72) == ldq_head; // @[util.scala:205:25, :206:{10,28}]
wire _GEN_96 = io_core_dis_stq_idx_1_0 == 5'h17; // @[util.scala:205:25]
wire wrap_5; // @[util.scala:205:25]
assign wrap_5 = _GEN_96; // @[util.scala:205:25]
wire wrap_7; // @[util.scala:205:25]
assign wrap_7 = _GEN_96; // @[util.scala:205:25]
wire [4:0] _T_79 = io_core_dis_stq_idx_1_0 + 5'h1; // @[util.scala:206:28]
assign io_core_stq_full_1_0 = (wrap_5 ? 5'h0 : _T_79) == stq_head; // @[util.scala:205:25, :206:{10,28}]
wire _dis_ld_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48]
wire _dis_ld_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:201:7, :300:88]
wire dis_ld_val_1 = _dis_ld_val_T_2 & _dis_ld_val_T_3; // @[lsu.scala:300:{48,85,88}]
wire _dis_st_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48]
wire _dis_st_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88]
wire dis_st_val_1 = _dis_st_val_T_2 & _dis_st_val_T_3; // @[lsu.scala:301:{48,85,88}]
wire [4:0] _T_74 = wrap_6 ? 5'h0 : _T_72; // @[util.scala:205:25, :206:{10,28}]
assign io_core_dis_ldq_idx_2_0 = dis_ld_val_1 ? _T_74 : io_core_dis_ldq_idx_1_0; // @[util.scala:206:10]
wire [31:0] _T_76 = 32'h1 << io_core_dis_stq_idx_1_0; // @[lsu.scala:201:7, :335:72]
wire [23:0] _T_78 = {24{dis_st_val_1}} & _T_76[23:0] | _T_38; // @[lsu.scala:301:85, :335:{31,72}]
wire [4:0] _T_81 = wrap_7 ? 5'h0 : _T_79; // @[util.scala:205:25, :206:{10,28}]
assign io_core_dis_stq_idx_2_0 = dis_st_val_1 ? _T_81 : io_core_dis_stq_idx_1_0; // @[util.scala:206:10]
wire _GEN_97 = io_core_dis_ldq_idx_2_0 == 5'h17; // @[util.scala:205:25]
wire wrap_8; // @[util.scala:205:25]
assign wrap_8 = _GEN_97; // @[util.scala:205:25]
wire wrap_10; // @[util.scala:205:25]
assign wrap_10 = _GEN_97; // @[util.scala:205:25]
wire [4:0] _T_112 = io_core_dis_ldq_idx_2_0 + 5'h1; // @[util.scala:206:28]
assign io_core_ldq_full_2_0 = (wrap_8 ? 5'h0 : _T_112) == ldq_head; // @[util.scala:205:25, :206:{10,28}]
wire _GEN_98 = io_core_dis_stq_idx_2_0 == 5'h17; // @[util.scala:205:25]
wire wrap_9; // @[util.scala:205:25]
assign wrap_9 = _GEN_98; // @[util.scala:205:25]
wire wrap_11; // @[util.scala:205:25]
assign wrap_11 = _GEN_98; // @[util.scala:205:25]
wire [4:0] _T_119 = io_core_dis_stq_idx_2_0 + 5'h1; // @[util.scala:206:28]
assign io_core_stq_full_2_0 = (wrap_9 ? 5'h0 : _T_119) == stq_head; // @[util.scala:205:25, :206:{10,28}]
wire _dis_ld_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48]
wire _dis_ld_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:201:7, :300:88]
wire dis_ld_val_2 = _dis_ld_val_T_4 & _dis_ld_val_T_5; // @[lsu.scala:300:{48,85,88}]
wire _dis_st_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48]
wire _dis_st_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88]
wire dis_st_val_2 = _dis_st_val_T_4 & _dis_st_val_T_5; // @[lsu.scala:301:{48,85,88}]
wire [31:0] _T_116 = 32'h1 << io_core_dis_stq_idx_2_0; // @[lsu.scala:201:7, :335:72]
wire [4:0] _T_121 = wrap_11 ? 5'h0 : _T_119; // @[util.scala:205:25, :206:{10,28}]
wire [4:0] _T_122 = dis_st_val_2 ? _T_121 : io_core_dis_stq_idx_2_0; // @[util.scala:206:10]
wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:285:84, :347:28]
assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:201:7, :347:{28,42}]
assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:201:7, :347:42]
wire mem_xcpt_valid; // @[lsu.scala:358:29]
wire [3:0] mem_xcpt_cause; // @[lsu.scala:359:29]
wire [3:0] mem_xcpt_uop_ctrl_br_type; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:360:29]
wire [2:0] mem_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:360:29]
wire [2:0] mem_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:360:29]
wire [4:0] mem_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:360:29]
wire mem_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:360:29]
wire [2:0] mem_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:360:29]
wire mem_xcpt_uop_ctrl_is_load; // @[lsu.scala:360:29]
wire mem_xcpt_uop_ctrl_is_sta; // @[lsu.scala:360:29]
wire mem_xcpt_uop_ctrl_is_std; // @[lsu.scala:360:29]
wire [6:0] mem_xcpt_uop_uopc; // @[lsu.scala:360:29]
wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:360:29]
wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_rvc; // @[lsu.scala:360:29]
wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:360:29]
wire [2:0] mem_xcpt_uop_iq_type; // @[lsu.scala:360:29]
wire [9:0] mem_xcpt_uop_fu_code; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_iw_state; // @[lsu.scala:360:29]
wire mem_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:360:29]
wire mem_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_br; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_jalr; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_jal; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_sfb; // @[lsu.scala:360:29]
wire [15:0] mem_xcpt_uop_br_mask; // @[lsu.scala:360:29]
wire [3:0] mem_xcpt_uop_br_tag; // @[lsu.scala:360:29]
wire [4:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:360:29]
wire mem_xcpt_uop_edge_inst; // @[lsu.scala:360:29]
wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:360:29]
wire mem_xcpt_uop_taken; // @[lsu.scala:360:29]
wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:360:29]
wire [11:0] mem_xcpt_uop_csr_addr; // @[lsu.scala:360:29]
wire [6:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:360:29]
wire [4:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:360:29]
wire [4:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:360:29]
wire [6:0] mem_xcpt_uop_pdst; // @[lsu.scala:360:29]
wire [6:0] mem_xcpt_uop_prs1; // @[lsu.scala:360:29]
wire [6:0] mem_xcpt_uop_prs2; // @[lsu.scala:360:29]
wire [6:0] mem_xcpt_uop_prs3; // @[lsu.scala:360:29]
wire [4:0] mem_xcpt_uop_ppred; // @[lsu.scala:360:29]
wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:360:29]
wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:360:29]
wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:360:29]
wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29]
wire [6:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:360:29]
wire mem_xcpt_uop_exception; // @[lsu.scala:360:29]
wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:360:29]
wire mem_xcpt_uop_bypassable; // @[lsu.scala:360:29]
wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:360:29]
wire mem_xcpt_uop_mem_signed; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_fence; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_fencei; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_amo; // @[lsu.scala:360:29]
wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:360:29]
wire mem_xcpt_uop_uses_stq; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:360:29]
wire mem_xcpt_uop_is_unique; // @[lsu.scala:360:29]
wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:360:29]
wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:360:29]
wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:360:29]
wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:360:29]
wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:360:29]
wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:360:29]
wire mem_xcpt_uop_ldst_val; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:360:29]
wire mem_xcpt_uop_frs3_en; // @[lsu.scala:360:29]
wire mem_xcpt_uop_fp_val; // @[lsu.scala:360:29]
wire mem_xcpt_uop_fp_single; // @[lsu.scala:360:29]
wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:360:29]
wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:360:29]
wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:360:29]
wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:360:29]
wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:360:29]
wire [1:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:360:29]
wire [39:0] mem_xcpt_vaddr; // @[lsu.scala:361:29]
wire will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_load_incoming_0; // @[lsu.scala:370:38]
wire will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_stad_incoming_0; // @[lsu.scala:371:38]
wire will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_sta_incoming_0; // @[lsu.scala:372:38]
wire will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_std_incoming_0; // @[lsu.scala:373:38]
wire will_fire_sfence_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_sfence_0; // @[lsu.scala:374:38]
wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_hella_incoming_0; // @[lsu.scala:375:38]
wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:375:38, :642:23]
wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_hella_wakeup_0; // @[lsu.scala:376:38]
wire will_fire_release_0_will_fire; // @[lsu.scala:535:61]
assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:201:7, :377:38]
wire will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_load_retry_0; // @[lsu.scala:378:38]
wire will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_sta_retry_0; // @[lsu.scala:379:38]
wire will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_store_commit_0; // @[lsu.scala:380:38]
wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61]
wire will_fire_load_wakeup_0; // @[lsu.scala:381:38]
wire [6:0] mem_incoming_uop_out_uopc = exe_req_0_bits_uop_uopc; // @[util.scala:96:23]
wire [31:0] mem_incoming_uop_out_inst = exe_req_0_bits_uop_inst; // @[util.scala:96:23]
wire [31:0] mem_incoming_uop_out_debug_inst = exe_req_0_bits_uop_debug_inst; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_rvc = exe_req_0_bits_uop_is_rvc; // @[util.scala:96:23]
wire [39:0] mem_incoming_uop_out_debug_pc = exe_req_0_bits_uop_debug_pc; // @[util.scala:96:23]
wire [2:0] mem_incoming_uop_out_iq_type = exe_req_0_bits_uop_iq_type; // @[util.scala:96:23]
wire [9:0] mem_incoming_uop_out_fu_code = exe_req_0_bits_uop_fu_code; // @[util.scala:96:23]
wire [3:0] mem_incoming_uop_out_ctrl_br_type = exe_req_0_bits_uop_ctrl_br_type; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_ctrl_op1_sel = exe_req_0_bits_uop_ctrl_op1_sel; // @[util.scala:96:23]
wire [2:0] mem_incoming_uop_out_ctrl_op2_sel = exe_req_0_bits_uop_ctrl_op2_sel; // @[util.scala:96:23]
wire [2:0] mem_incoming_uop_out_ctrl_imm_sel = exe_req_0_bits_uop_ctrl_imm_sel; // @[util.scala:96:23]
wire [4:0] mem_incoming_uop_out_ctrl_op_fcn = exe_req_0_bits_uop_ctrl_op_fcn; // @[util.scala:96:23]
wire mem_incoming_uop_out_ctrl_fcn_dw = exe_req_0_bits_uop_ctrl_fcn_dw; // @[util.scala:96:23]
wire [2:0] mem_incoming_uop_out_ctrl_csr_cmd = exe_req_0_bits_uop_ctrl_csr_cmd; // @[util.scala:96:23]
wire mem_incoming_uop_out_ctrl_is_load = exe_req_0_bits_uop_ctrl_is_load; // @[util.scala:96:23]
wire mem_incoming_uop_out_ctrl_is_sta = exe_req_0_bits_uop_ctrl_is_sta; // @[util.scala:96:23]
wire mem_incoming_uop_out_ctrl_is_std = exe_req_0_bits_uop_ctrl_is_std; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_iw_state = exe_req_0_bits_uop_iw_state; // @[util.scala:96:23]
wire mem_incoming_uop_out_iw_p1_poisoned = exe_req_0_bits_uop_iw_p1_poisoned; // @[util.scala:96:23]
wire mem_incoming_uop_out_iw_p2_poisoned = exe_req_0_bits_uop_iw_p2_poisoned; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_br = exe_req_0_bits_uop_is_br; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_jalr = exe_req_0_bits_uop_is_jalr; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_jal = exe_req_0_bits_uop_is_jal; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_sfb = exe_req_0_bits_uop_is_sfb; // @[util.scala:96:23]
wire [3:0] mem_incoming_uop_out_br_tag = exe_req_0_bits_uop_br_tag; // @[util.scala:96:23]
wire [4:0] mem_incoming_uop_out_ftq_idx = exe_req_0_bits_uop_ftq_idx; // @[util.scala:96:23]
wire mem_incoming_uop_out_edge_inst = exe_req_0_bits_uop_edge_inst; // @[util.scala:96:23]
wire [5:0] mem_incoming_uop_out_pc_lob = exe_req_0_bits_uop_pc_lob; // @[util.scala:96:23]
wire mem_incoming_uop_out_taken = exe_req_0_bits_uop_taken; // @[util.scala:96:23]
wire [19:0] mem_incoming_uop_out_imm_packed = exe_req_0_bits_uop_imm_packed; // @[util.scala:96:23]
wire [11:0] mem_incoming_uop_out_csr_addr = exe_req_0_bits_uop_csr_addr; // @[util.scala:96:23]
wire [6:0] mem_incoming_uop_out_rob_idx = exe_req_0_bits_uop_rob_idx; // @[util.scala:96:23]
wire [4:0] ldq_incoming_idx_0 = exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:263:49, :383:25]
wire [4:0] mem_incoming_uop_out_ldq_idx = exe_req_0_bits_uop_ldq_idx; // @[util.scala:96:23]
wire [4:0] stq_incoming_idx_0 = exe_req_0_bits_uop_stq_idx; // @[lsu.scala:263:49, :383:25]
wire [4:0] mem_incoming_uop_out_stq_idx = exe_req_0_bits_uop_stq_idx; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_rxq_idx = exe_req_0_bits_uop_rxq_idx; // @[util.scala:96:23]
wire [6:0] mem_incoming_uop_out_pdst = exe_req_0_bits_uop_pdst; // @[util.scala:96:23]
wire [6:0] mem_incoming_uop_out_prs1 = exe_req_0_bits_uop_prs1; // @[util.scala:96:23]
wire [6:0] mem_incoming_uop_out_prs2 = exe_req_0_bits_uop_prs2; // @[util.scala:96:23]
wire [6:0] mem_incoming_uop_out_prs3 = exe_req_0_bits_uop_prs3; // @[util.scala:96:23]
wire [4:0] mem_incoming_uop_out_ppred = exe_req_0_bits_uop_ppred; // @[util.scala:96:23]
wire mem_incoming_uop_out_prs1_busy = exe_req_0_bits_uop_prs1_busy; // @[util.scala:96:23]
wire mem_incoming_uop_out_prs2_busy = exe_req_0_bits_uop_prs2_busy; // @[util.scala:96:23]
wire mem_incoming_uop_out_prs3_busy = exe_req_0_bits_uop_prs3_busy; // @[util.scala:96:23]
wire mem_incoming_uop_out_ppred_busy = exe_req_0_bits_uop_ppred_busy; // @[util.scala:96:23]
wire [6:0] mem_incoming_uop_out_stale_pdst = exe_req_0_bits_uop_stale_pdst; // @[util.scala:96:23]
wire mem_incoming_uop_out_exception = exe_req_0_bits_uop_exception; // @[util.scala:96:23]
wire [63:0] mem_incoming_uop_out_exc_cause = exe_req_0_bits_uop_exc_cause; // @[util.scala:96:23]
wire mem_incoming_uop_out_bypassable = exe_req_0_bits_uop_bypassable; // @[util.scala:96:23]
wire [4:0] mem_incoming_uop_out_mem_cmd = exe_req_0_bits_uop_mem_cmd; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_mem_size = exe_req_0_bits_uop_mem_size; // @[util.scala:96:23]
wire mem_incoming_uop_out_mem_signed = exe_req_0_bits_uop_mem_signed; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_fence = exe_req_0_bits_uop_is_fence; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_fencei = exe_req_0_bits_uop_is_fencei; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_amo = exe_req_0_bits_uop_is_amo; // @[util.scala:96:23]
wire mem_incoming_uop_out_uses_ldq = exe_req_0_bits_uop_uses_ldq; // @[util.scala:96:23]
wire mem_incoming_uop_out_uses_stq = exe_req_0_bits_uop_uses_stq; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_sys_pc2epc = exe_req_0_bits_uop_is_sys_pc2epc; // @[util.scala:96:23]
wire mem_incoming_uop_out_is_unique = exe_req_0_bits_uop_is_unique; // @[util.scala:96:23]
wire mem_incoming_uop_out_flush_on_commit = exe_req_0_bits_uop_flush_on_commit; // @[util.scala:96:23]
wire mem_incoming_uop_out_ldst_is_rs1 = exe_req_0_bits_uop_ldst_is_rs1; // @[util.scala:96:23]
wire [5:0] mem_incoming_uop_out_ldst = exe_req_0_bits_uop_ldst; // @[util.scala:96:23]
wire [5:0] mem_incoming_uop_out_lrs1 = exe_req_0_bits_uop_lrs1; // @[util.scala:96:23]
wire [5:0] mem_incoming_uop_out_lrs2 = exe_req_0_bits_uop_lrs2; // @[util.scala:96:23]
wire [5:0] mem_incoming_uop_out_lrs3 = exe_req_0_bits_uop_lrs3; // @[util.scala:96:23]
wire mem_incoming_uop_out_ldst_val = exe_req_0_bits_uop_ldst_val; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_dst_rtype = exe_req_0_bits_uop_dst_rtype; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_lrs1_rtype = exe_req_0_bits_uop_lrs1_rtype; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_lrs2_rtype = exe_req_0_bits_uop_lrs2_rtype; // @[util.scala:96:23]
wire mem_incoming_uop_out_frs3_en = exe_req_0_bits_uop_frs3_en; // @[util.scala:96:23]
wire mem_incoming_uop_out_fp_val = exe_req_0_bits_uop_fp_val; // @[util.scala:96:23]
wire mem_incoming_uop_out_fp_single = exe_req_0_bits_uop_fp_single; // @[util.scala:96:23]
wire mem_incoming_uop_out_xcpt_pf_if = exe_req_0_bits_uop_xcpt_pf_if; // @[util.scala:96:23]
wire mem_incoming_uop_out_xcpt_ae_if = exe_req_0_bits_uop_xcpt_ae_if; // @[util.scala:96:23]
wire mem_incoming_uop_out_xcpt_ma_if = exe_req_0_bits_uop_xcpt_ma_if; // @[util.scala:96:23]
wire mem_incoming_uop_out_bp_debug_if = exe_req_0_bits_uop_bp_debug_if; // @[util.scala:96:23]
wire mem_incoming_uop_out_bp_xcpt_if = exe_req_0_bits_uop_bp_xcpt_if; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_debug_fsrc = exe_req_0_bits_uop_debug_fsrc; // @[util.scala:96:23]
wire [1:0] mem_incoming_uop_out_debug_tsrc = exe_req_0_bits_uop_debug_tsrc; // @[util.scala:96:23]
wire [15:0] exe_req_0_bits_uop_br_mask; // @[lsu.scala:383:25]
wire exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25]
wire [24:0] exe_req_0_bits_mxcpt_bits; // @[lsu.scala:383:25]
wire exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:383:25]
wire exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:383:25]
wire [38:0] exe_req_0_bits_sfence_bits_addr; // @[lsu.scala:383:25]
wire exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:383:25]
wire exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25]
wire [63:0] exe_req_0_bits_data; // @[lsu.scala:383:25]
wire [39:0] exe_req_0_bits_addr; // @[lsu.scala:383:25]
wire exe_req_0_valid; // @[lsu.scala:383:25]
assign exe_req_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_asid_0 : _exe_req_WIRE_0_bits_sfence_bits_asid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_addr_0 : _exe_req_WIRE_0_bits_sfence_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs2_0 : _exe_req_WIRE_0_bits_sfence_bits_rs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs1_0 : _exe_req_WIRE_0_bits_sfence_bits_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_valid_0 : _exe_req_WIRE_0_bits_sfence_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_mxcpt_bits = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_bits_0 : _exe_req_WIRE_0_bits_mxcpt_bits; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_mxcpt_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_valid_0 : _exe_req_WIRE_0_bits_mxcpt_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_addr_0 : _exe_req_WIRE_0_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_data = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_data_0 : _exe_req_WIRE_0_bits_data; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_tsrc_0 : _exe_req_WIRE_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_fsrc_0 : _exe_req_WIRE_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_xcpt_if_0 : _exe_req_WIRE_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_debug_if_0 : _exe_req_WIRE_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ma_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ae_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_pf_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_fp_single = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_single_0 : _exe_req_WIRE_0_bits_uop_fp_single; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_fp_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_val_0 : _exe_req_WIRE_0_bits_uop_fp_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_frs3_en = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_frs3_en_0 : _exe_req_WIRE_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_dst_rtype_0 : _exe_req_WIRE_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ldst_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_val_0 : _exe_req_WIRE_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_lrs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs3_0 : _exe_req_WIRE_0_bits_uop_lrs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_lrs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_0 : _exe_req_WIRE_0_bits_uop_lrs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_lrs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_0 : _exe_req_WIRE_0_bits_uop_lrs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ldst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_0 : _exe_req_WIRE_0_bits_uop_ldst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_is_rs1_0 : _exe_req_WIRE_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_flush_on_commit_0 : _exe_req_WIRE_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_unique = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_unique_0 : _exe_req_WIRE_0_bits_uop_is_unique; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 : _exe_req_WIRE_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_uses_stq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_stq_0 : _exe_req_WIRE_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_ldq_0 : _exe_req_WIRE_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_amo = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_amo_0 : _exe_req_WIRE_0_bits_uop_is_amo; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_fencei = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fencei_0 : _exe_req_WIRE_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_fence = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fence_0 : _exe_req_WIRE_0_bits_uop_is_fence; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_mem_signed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_signed_0 : _exe_req_WIRE_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_mem_size = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_size_0 : _exe_req_WIRE_0_bits_uop_mem_size; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_cmd_0 : _exe_req_WIRE_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_bypassable = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bypassable_0 : _exe_req_WIRE_0_bits_uop_bypassable; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_exc_cause = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exc_cause_0 : _exe_req_WIRE_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_exception = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exception_0 : _exe_req_WIRE_0_bits_uop_exception; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stale_pdst_0 : _exe_req_WIRE_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_busy_0 : _exe_req_WIRE_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_busy_0 : _exe_req_WIRE_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_busy_0 : _exe_req_WIRE_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_busy_0 : _exe_req_WIRE_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ppred = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_0 : _exe_req_WIRE_0_bits_uop_ppred; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_prs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_0 : _exe_req_WIRE_0_bits_uop_prs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_prs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_0 : _exe_req_WIRE_0_bits_uop_prs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_prs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_0 : _exe_req_WIRE_0_bits_uop_prs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pdst_0 : _exe_req_WIRE_0_bits_uop_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rxq_idx_0 : _exe_req_WIRE_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_stq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stq_idx_0 : _exe_req_WIRE_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldq_idx_0 : _exe_req_WIRE_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_rob_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rob_idx_0 : _exe_req_WIRE_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_csr_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_csr_addr_0 : _exe_req_WIRE_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_imm_packed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_imm_packed_0 : _exe_req_WIRE_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_taken = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_taken_0 : _exe_req_WIRE_0_bits_uop_taken; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_pc_lob = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pc_lob_0 : _exe_req_WIRE_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_edge_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_edge_inst_0 : _exe_req_WIRE_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ftq_idx_0 : _exe_req_WIRE_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_br_tag = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_tag_0 : _exe_req_WIRE_0_bits_uop_br_tag; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_br_mask = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_mask_0 : _exe_req_WIRE_0_bits_uop_br_mask; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_sfb = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sfb_0 : _exe_req_WIRE_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_jal = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jal_0 : _exe_req_WIRE_0_bits_uop_is_jal; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_jalr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jalr_0 : _exe_req_WIRE_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_br = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_br_0 : _exe_req_WIRE_0_bits_uop_is_br; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_iw_state = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_state_0 : _exe_req_WIRE_0_bits_uop_iw_state; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_std_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_sta_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_load_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 : _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 : _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 : _exe_req_WIRE_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_br_type_0 : _exe_req_WIRE_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_fu_code = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fu_code_0 : _exe_req_WIRE_0_bits_uop_fu_code; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_iq_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iq_type_0 : _exe_req_WIRE_0_bits_uop_iq_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_debug_pc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_pc_0 : _exe_req_WIRE_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_is_rvc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_rvc_0 : _exe_req_WIRE_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_debug_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_inst_0 : _exe_req_WIRE_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_inst_0 : _exe_req_WIRE_0_bits_uop_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_bits_uop_uopc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uopc_0 : _exe_req_WIRE_0_bits_uop_uopc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
assign exe_req_0_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_valid_0 : _exe_req_WIRE_0_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15]
wire block_load_mask_0; // @[lsu.scala:396:36]
wire block_load_mask_1; // @[lsu.scala:396:36]
wire block_load_mask_2; // @[lsu.scala:396:36]
wire block_load_mask_3; // @[lsu.scala:396:36]
wire block_load_mask_4; // @[lsu.scala:396:36]
wire block_load_mask_5; // @[lsu.scala:396:36]
wire block_load_mask_6; // @[lsu.scala:396:36]
wire block_load_mask_7; // @[lsu.scala:396:36]
wire block_load_mask_8; // @[lsu.scala:396:36]
wire block_load_mask_9; // @[lsu.scala:396:36]
wire block_load_mask_10; // @[lsu.scala:396:36]
wire block_load_mask_11; // @[lsu.scala:396:36]
wire block_load_mask_12; // @[lsu.scala:396:36]
wire block_load_mask_13; // @[lsu.scala:396:36]
wire block_load_mask_14; // @[lsu.scala:396:36]
wire block_load_mask_15; // @[lsu.scala:396:36]
wire block_load_mask_16; // @[lsu.scala:396:36]
wire block_load_mask_17; // @[lsu.scala:396:36]
wire block_load_mask_18; // @[lsu.scala:396:36]
wire block_load_mask_19; // @[lsu.scala:396:36]
wire block_load_mask_20; // @[lsu.scala:396:36]
wire block_load_mask_21; // @[lsu.scala:396:36]
wire block_load_mask_22; // @[lsu.scala:396:36]
wire block_load_mask_23; // @[lsu.scala:396:36]
reg p1_block_load_mask_0; // @[lsu.scala:397:35]
reg p1_block_load_mask_1; // @[lsu.scala:397:35]
reg p1_block_load_mask_2; // @[lsu.scala:397:35]
reg p1_block_load_mask_3; // @[lsu.scala:397:35]
reg p1_block_load_mask_4; // @[lsu.scala:397:35]
reg p1_block_load_mask_5; // @[lsu.scala:397:35]
reg p1_block_load_mask_6; // @[lsu.scala:397:35]
reg p1_block_load_mask_7; // @[lsu.scala:397:35]
reg p1_block_load_mask_8; // @[lsu.scala:397:35]
reg p1_block_load_mask_9; // @[lsu.scala:397:35]
reg p1_block_load_mask_10; // @[lsu.scala:397:35]
reg p1_block_load_mask_11; // @[lsu.scala:397:35]
reg p1_block_load_mask_12; // @[lsu.scala:397:35]
reg p1_block_load_mask_13; // @[lsu.scala:397:35]
reg p1_block_load_mask_14; // @[lsu.scala:397:35]
reg p1_block_load_mask_15; // @[lsu.scala:397:35]
reg p1_block_load_mask_16; // @[lsu.scala:397:35]
reg p1_block_load_mask_17; // @[lsu.scala:397:35]
reg p1_block_load_mask_18; // @[lsu.scala:397:35]
reg p1_block_load_mask_19; // @[lsu.scala:397:35]
reg p1_block_load_mask_20; // @[lsu.scala:397:35]
reg p1_block_load_mask_21; // @[lsu.scala:397:35]
reg p1_block_load_mask_22; // @[lsu.scala:397:35]
reg p1_block_load_mask_23; // @[lsu.scala:397:35]
reg p2_block_load_mask_0; // @[lsu.scala:398:35]
reg p2_block_load_mask_1; // @[lsu.scala:398:35]
reg p2_block_load_mask_2; // @[lsu.scala:398:35]
reg p2_block_load_mask_3; // @[lsu.scala:398:35]
reg p2_block_load_mask_4; // @[lsu.scala:398:35]
reg p2_block_load_mask_5; // @[lsu.scala:398:35]
reg p2_block_load_mask_6; // @[lsu.scala:398:35]
reg p2_block_load_mask_7; // @[lsu.scala:398:35]
reg p2_block_load_mask_8; // @[lsu.scala:398:35]
reg p2_block_load_mask_9; // @[lsu.scala:398:35]
reg p2_block_load_mask_10; // @[lsu.scala:398:35]
reg p2_block_load_mask_11; // @[lsu.scala:398:35]
reg p2_block_load_mask_12; // @[lsu.scala:398:35]
reg p2_block_load_mask_13; // @[lsu.scala:398:35]
reg p2_block_load_mask_14; // @[lsu.scala:398:35]
reg p2_block_load_mask_15; // @[lsu.scala:398:35]
reg p2_block_load_mask_16; // @[lsu.scala:398:35]
reg p2_block_load_mask_17; // @[lsu.scala:398:35]
reg p2_block_load_mask_18; // @[lsu.scala:398:35]
reg p2_block_load_mask_19; // @[lsu.scala:398:35]
reg p2_block_load_mask_20; // @[lsu.scala:398:35]
reg p2_block_load_mask_21; // @[lsu.scala:398:35]
reg p2_block_load_mask_22; // @[lsu.scala:398:35]
reg p2_block_load_mask_23; // @[lsu.scala:398:35]
wire _GEN_99 = _T_122 == 5'h17; // @[util.scala:205:25]
wire stq_almost_full_wrap; // @[util.scala:205:25]
assign stq_almost_full_wrap = _GEN_99; // @[util.scala:205:25]
wire stq_almost_full_wrap_2; // @[util.scala:205:25]
assign stq_almost_full_wrap_2 = _GEN_99; // @[util.scala:205:25]
wire [5:0] _GEN_100 = {1'h0, _T_122} + 6'h1; // @[util.scala:206:28]
wire [5:0] _stq_almost_full_T; // @[util.scala:206:28]
assign _stq_almost_full_T = _GEN_100; // @[util.scala:206:28]
wire [5:0] _stq_almost_full_T_7; // @[util.scala:206:28]
assign _stq_almost_full_T_7 = _GEN_100; // @[util.scala:206:28]
wire [4:0] _stq_almost_full_T_1 = _stq_almost_full_T[4:0]; // @[util.scala:206:28]
wire [4:0] _stq_almost_full_T_2 = stq_almost_full_wrap ? 5'h0 : _stq_almost_full_T_1; // @[util.scala:205:25, :206:{10,28}]
wire stq_almost_full_wrap_1 = _stq_almost_full_T_2 == 5'h17; // @[util.scala:205:25, :206:10]
wire [5:0] _stq_almost_full_T_3 = {1'h0, _stq_almost_full_T_2} + 6'h1; // @[util.scala:206:{10,28}]
wire [4:0] _stq_almost_full_T_4 = _stq_almost_full_T_3[4:0]; // @[util.scala:206:28]
wire [4:0] _stq_almost_full_T_5 = stq_almost_full_wrap_1 ? 5'h0 : _stq_almost_full_T_4; // @[util.scala:205:25, :206:{10,28}]
wire _stq_almost_full_T_6 = _stq_almost_full_T_5 == stq_head; // @[util.scala:206:10]
wire [4:0] _stq_almost_full_T_8 = _stq_almost_full_T_7[4:0]; // @[util.scala:206:28]
wire [4:0] _stq_almost_full_T_9 = stq_almost_full_wrap_2 ? 5'h0 : _stq_almost_full_T_8; // @[util.scala:205:25, :206:{10,28}]
wire _stq_almost_full_T_10 = _stq_almost_full_T_9 == stq_head; // @[util.scala:206:10]
wire _stq_almost_full_T_11 = _stq_almost_full_T_6 | _stq_almost_full_T_10; // @[lsu.scala:401:{92,105}, :402:68]
reg stq_almost_full; // @[lsu.scala:401:32]
wire store_needs_order; // @[lsu.scala:406:35]
wire [6:0] mem_ldq_incoming_e_out_bits_uop_uopc = ldq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23]
wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23]
wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23]
wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23]
wire [2:0] mem_ldq_incoming_e_out_bits_uop_iq_type = ldq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23]
wire [9:0] mem_ldq_incoming_e_out_bits_uop_fu_code = ldq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23]
wire [3:0] mem_ldq_incoming_e_out_bits_uop_ctrl_br_type = ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel = ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23]
wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel = ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23]
wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel = ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn = ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw = ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23]
wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd = ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_load = ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta = ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_std = ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_state = ldq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned = ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned = ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_br = ldq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_jalr = ldq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_jal = ldq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23]
wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23]
wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23]
wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23]
wire [11:0] mem_ldq_incoming_e_out_bits_uop_csr_addr = ldq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23]
wire [6:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23]
wire [6:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23]
wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23]
wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23]
wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23]
wire [6:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23]
wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_bypassable = ldq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23]
wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23]
wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23]
wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23]
wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_ldst_val = ldq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_fp_single = ldq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23]
wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23]
wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:106:23]
wire [23:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_youngest_stq_idx = ldq_incoming_e_0_bits_youngest_stq_idx; // @[util.scala:106:23]
wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:106:23]
wire [4:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:106:23]
wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23]
wire [15:0] ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49]
wire ldq_incoming_e_0_valid; // @[lsu.scala:263:49]
assign ldq_incoming_e_0_valid = _GEN_94[ldq_incoming_idx_0]; // @[lsu.scala:263:49, :304:44]
wire [31:0][6:0] _GEN_101 = {{ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_23_bits_uop_uopc}, {ldq_22_bits_uop_uopc}, {ldq_21_bits_uop_uopc}, {ldq_20_bits_uop_uopc}, {ldq_19_bits_uop_uopc}, {ldq_18_bits_uop_uopc}, {ldq_17_bits_uop_uopc}, {ldq_16_bits_uop_uopc}, {ldq_15_bits_uop_uopc}, {ldq_14_bits_uop_uopc}, {ldq_13_bits_uop_uopc}, {ldq_12_bits_uop_uopc}, {ldq_11_bits_uop_uopc}, {ldq_10_bits_uop_uopc}, {ldq_9_bits_uop_uopc}, {ldq_8_bits_uop_uopc}, {ldq_7_bits_uop_uopc}, {ldq_6_bits_uop_uopc}, {ldq_5_bits_uop_uopc}, {ldq_4_bits_uop_uopc}, {ldq_3_bits_uop_uopc}, {ldq_2_bits_uop_uopc}, {ldq_1_bits_uop_uopc}, {ldq_0_bits_uop_uopc}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_uopc = _GEN_101[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][31:0] _GEN_102 = {{ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_23_bits_uop_inst}, {ldq_22_bits_uop_inst}, {ldq_21_bits_uop_inst}, {ldq_20_bits_uop_inst}, {ldq_19_bits_uop_inst}, {ldq_18_bits_uop_inst}, {ldq_17_bits_uop_inst}, {ldq_16_bits_uop_inst}, {ldq_15_bits_uop_inst}, {ldq_14_bits_uop_inst}, {ldq_13_bits_uop_inst}, {ldq_12_bits_uop_inst}, {ldq_11_bits_uop_inst}, {ldq_10_bits_uop_inst}, {ldq_9_bits_uop_inst}, {ldq_8_bits_uop_inst}, {ldq_7_bits_uop_inst}, {ldq_6_bits_uop_inst}, {ldq_5_bits_uop_inst}, {ldq_4_bits_uop_inst}, {ldq_3_bits_uop_inst}, {ldq_2_bits_uop_inst}, {ldq_1_bits_uop_inst}, {ldq_0_bits_uop_inst}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_inst = _GEN_102[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][31:0] _GEN_103 = {{ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_23_bits_uop_debug_inst}, {ldq_22_bits_uop_debug_inst}, {ldq_21_bits_uop_debug_inst}, {ldq_20_bits_uop_debug_inst}, {ldq_19_bits_uop_debug_inst}, {ldq_18_bits_uop_debug_inst}, {ldq_17_bits_uop_debug_inst}, {ldq_16_bits_uop_debug_inst}, {ldq_15_bits_uop_debug_inst}, {ldq_14_bits_uop_debug_inst}, {ldq_13_bits_uop_debug_inst}, {ldq_12_bits_uop_debug_inst}, {ldq_11_bits_uop_debug_inst}, {ldq_10_bits_uop_debug_inst}, {ldq_9_bits_uop_debug_inst}, {ldq_8_bits_uop_debug_inst}, {ldq_7_bits_uop_debug_inst}, {ldq_6_bits_uop_debug_inst}, {ldq_5_bits_uop_debug_inst}, {ldq_4_bits_uop_debug_inst}, {ldq_3_bits_uop_debug_inst}, {ldq_2_bits_uop_debug_inst}, {ldq_1_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_debug_inst = _GEN_103[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_104 = {{ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_23_bits_uop_is_rvc}, {ldq_22_bits_uop_is_rvc}, {ldq_21_bits_uop_is_rvc}, {ldq_20_bits_uop_is_rvc}, {ldq_19_bits_uop_is_rvc}, {ldq_18_bits_uop_is_rvc}, {ldq_17_bits_uop_is_rvc}, {ldq_16_bits_uop_is_rvc}, {ldq_15_bits_uop_is_rvc}, {ldq_14_bits_uop_is_rvc}, {ldq_13_bits_uop_is_rvc}, {ldq_12_bits_uop_is_rvc}, {ldq_11_bits_uop_is_rvc}, {ldq_10_bits_uop_is_rvc}, {ldq_9_bits_uop_is_rvc}, {ldq_8_bits_uop_is_rvc}, {ldq_7_bits_uop_is_rvc}, {ldq_6_bits_uop_is_rvc}, {ldq_5_bits_uop_is_rvc}, {ldq_4_bits_uop_is_rvc}, {ldq_3_bits_uop_is_rvc}, {ldq_2_bits_uop_is_rvc}, {ldq_1_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_rvc = _GEN_104[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][39:0] _GEN_105 = {{ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_23_bits_uop_debug_pc}, {ldq_22_bits_uop_debug_pc}, {ldq_21_bits_uop_debug_pc}, {ldq_20_bits_uop_debug_pc}, {ldq_19_bits_uop_debug_pc}, {ldq_18_bits_uop_debug_pc}, {ldq_17_bits_uop_debug_pc}, {ldq_16_bits_uop_debug_pc}, {ldq_15_bits_uop_debug_pc}, {ldq_14_bits_uop_debug_pc}, {ldq_13_bits_uop_debug_pc}, {ldq_12_bits_uop_debug_pc}, {ldq_11_bits_uop_debug_pc}, {ldq_10_bits_uop_debug_pc}, {ldq_9_bits_uop_debug_pc}, {ldq_8_bits_uop_debug_pc}, {ldq_7_bits_uop_debug_pc}, {ldq_6_bits_uop_debug_pc}, {ldq_5_bits_uop_debug_pc}, {ldq_4_bits_uop_debug_pc}, {ldq_3_bits_uop_debug_pc}, {ldq_2_bits_uop_debug_pc}, {ldq_1_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_debug_pc = _GEN_105[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][2:0] _GEN_106 = {{ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_23_bits_uop_iq_type}, {ldq_22_bits_uop_iq_type}, {ldq_21_bits_uop_iq_type}, {ldq_20_bits_uop_iq_type}, {ldq_19_bits_uop_iq_type}, {ldq_18_bits_uop_iq_type}, {ldq_17_bits_uop_iq_type}, {ldq_16_bits_uop_iq_type}, {ldq_15_bits_uop_iq_type}, {ldq_14_bits_uop_iq_type}, {ldq_13_bits_uop_iq_type}, {ldq_12_bits_uop_iq_type}, {ldq_11_bits_uop_iq_type}, {ldq_10_bits_uop_iq_type}, {ldq_9_bits_uop_iq_type}, {ldq_8_bits_uop_iq_type}, {ldq_7_bits_uop_iq_type}, {ldq_6_bits_uop_iq_type}, {ldq_5_bits_uop_iq_type}, {ldq_4_bits_uop_iq_type}, {ldq_3_bits_uop_iq_type}, {ldq_2_bits_uop_iq_type}, {ldq_1_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_iq_type = _GEN_106[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][9:0] _GEN_107 = {{ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_23_bits_uop_fu_code}, {ldq_22_bits_uop_fu_code}, {ldq_21_bits_uop_fu_code}, {ldq_20_bits_uop_fu_code}, {ldq_19_bits_uop_fu_code}, {ldq_18_bits_uop_fu_code}, {ldq_17_bits_uop_fu_code}, {ldq_16_bits_uop_fu_code}, {ldq_15_bits_uop_fu_code}, {ldq_14_bits_uop_fu_code}, {ldq_13_bits_uop_fu_code}, {ldq_12_bits_uop_fu_code}, {ldq_11_bits_uop_fu_code}, {ldq_10_bits_uop_fu_code}, {ldq_9_bits_uop_fu_code}, {ldq_8_bits_uop_fu_code}, {ldq_7_bits_uop_fu_code}, {ldq_6_bits_uop_fu_code}, {ldq_5_bits_uop_fu_code}, {ldq_4_bits_uop_fu_code}, {ldq_3_bits_uop_fu_code}, {ldq_2_bits_uop_fu_code}, {ldq_1_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_fu_code = _GEN_107[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][3:0] _GEN_108 = {{ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_23_bits_uop_ctrl_br_type}, {ldq_22_bits_uop_ctrl_br_type}, {ldq_21_bits_uop_ctrl_br_type}, {ldq_20_bits_uop_ctrl_br_type}, {ldq_19_bits_uop_ctrl_br_type}, {ldq_18_bits_uop_ctrl_br_type}, {ldq_17_bits_uop_ctrl_br_type}, {ldq_16_bits_uop_ctrl_br_type}, {ldq_15_bits_uop_ctrl_br_type}, {ldq_14_bits_uop_ctrl_br_type}, {ldq_13_bits_uop_ctrl_br_type}, {ldq_12_bits_uop_ctrl_br_type}, {ldq_11_bits_uop_ctrl_br_type}, {ldq_10_bits_uop_ctrl_br_type}, {ldq_9_bits_uop_ctrl_br_type}, {ldq_8_bits_uop_ctrl_br_type}, {ldq_7_bits_uop_ctrl_br_type}, {ldq_6_bits_uop_ctrl_br_type}, {ldq_5_bits_uop_ctrl_br_type}, {ldq_4_bits_uop_ctrl_br_type}, {ldq_3_bits_uop_ctrl_br_type}, {ldq_2_bits_uop_ctrl_br_type}, {ldq_1_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_108[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_109 = {{ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_23_bits_uop_ctrl_op1_sel}, {ldq_22_bits_uop_ctrl_op1_sel}, {ldq_21_bits_uop_ctrl_op1_sel}, {ldq_20_bits_uop_ctrl_op1_sel}, {ldq_19_bits_uop_ctrl_op1_sel}, {ldq_18_bits_uop_ctrl_op1_sel}, {ldq_17_bits_uop_ctrl_op1_sel}, {ldq_16_bits_uop_ctrl_op1_sel}, {ldq_15_bits_uop_ctrl_op1_sel}, {ldq_14_bits_uop_ctrl_op1_sel}, {ldq_13_bits_uop_ctrl_op1_sel}, {ldq_12_bits_uop_ctrl_op1_sel}, {ldq_11_bits_uop_ctrl_op1_sel}, {ldq_10_bits_uop_ctrl_op1_sel}, {ldq_9_bits_uop_ctrl_op1_sel}, {ldq_8_bits_uop_ctrl_op1_sel}, {ldq_7_bits_uop_ctrl_op1_sel}, {ldq_6_bits_uop_ctrl_op1_sel}, {ldq_5_bits_uop_ctrl_op1_sel}, {ldq_4_bits_uop_ctrl_op1_sel}, {ldq_3_bits_uop_ctrl_op1_sel}, {ldq_2_bits_uop_ctrl_op1_sel}, {ldq_1_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_109[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][2:0] _GEN_110 = {{ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_23_bits_uop_ctrl_op2_sel}, {ldq_22_bits_uop_ctrl_op2_sel}, {ldq_21_bits_uop_ctrl_op2_sel}, {ldq_20_bits_uop_ctrl_op2_sel}, {ldq_19_bits_uop_ctrl_op2_sel}, {ldq_18_bits_uop_ctrl_op2_sel}, {ldq_17_bits_uop_ctrl_op2_sel}, {ldq_16_bits_uop_ctrl_op2_sel}, {ldq_15_bits_uop_ctrl_op2_sel}, {ldq_14_bits_uop_ctrl_op2_sel}, {ldq_13_bits_uop_ctrl_op2_sel}, {ldq_12_bits_uop_ctrl_op2_sel}, {ldq_11_bits_uop_ctrl_op2_sel}, {ldq_10_bits_uop_ctrl_op2_sel}, {ldq_9_bits_uop_ctrl_op2_sel}, {ldq_8_bits_uop_ctrl_op2_sel}, {ldq_7_bits_uop_ctrl_op2_sel}, {ldq_6_bits_uop_ctrl_op2_sel}, {ldq_5_bits_uop_ctrl_op2_sel}, {ldq_4_bits_uop_ctrl_op2_sel}, {ldq_3_bits_uop_ctrl_op2_sel}, {ldq_2_bits_uop_ctrl_op2_sel}, {ldq_1_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_110[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][2:0] _GEN_111 = {{ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_23_bits_uop_ctrl_imm_sel}, {ldq_22_bits_uop_ctrl_imm_sel}, {ldq_21_bits_uop_ctrl_imm_sel}, {ldq_20_bits_uop_ctrl_imm_sel}, {ldq_19_bits_uop_ctrl_imm_sel}, {ldq_18_bits_uop_ctrl_imm_sel}, {ldq_17_bits_uop_ctrl_imm_sel}, {ldq_16_bits_uop_ctrl_imm_sel}, {ldq_15_bits_uop_ctrl_imm_sel}, {ldq_14_bits_uop_ctrl_imm_sel}, {ldq_13_bits_uop_ctrl_imm_sel}, {ldq_12_bits_uop_ctrl_imm_sel}, {ldq_11_bits_uop_ctrl_imm_sel}, {ldq_10_bits_uop_ctrl_imm_sel}, {ldq_9_bits_uop_ctrl_imm_sel}, {ldq_8_bits_uop_ctrl_imm_sel}, {ldq_7_bits_uop_ctrl_imm_sel}, {ldq_6_bits_uop_ctrl_imm_sel}, {ldq_5_bits_uop_ctrl_imm_sel}, {ldq_4_bits_uop_ctrl_imm_sel}, {ldq_3_bits_uop_ctrl_imm_sel}, {ldq_2_bits_uop_ctrl_imm_sel}, {ldq_1_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_111[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][4:0] _GEN_112 = {{ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_23_bits_uop_ctrl_op_fcn}, {ldq_22_bits_uop_ctrl_op_fcn}, {ldq_21_bits_uop_ctrl_op_fcn}, {ldq_20_bits_uop_ctrl_op_fcn}, {ldq_19_bits_uop_ctrl_op_fcn}, {ldq_18_bits_uop_ctrl_op_fcn}, {ldq_17_bits_uop_ctrl_op_fcn}, {ldq_16_bits_uop_ctrl_op_fcn}, {ldq_15_bits_uop_ctrl_op_fcn}, {ldq_14_bits_uop_ctrl_op_fcn}, {ldq_13_bits_uop_ctrl_op_fcn}, {ldq_12_bits_uop_ctrl_op_fcn}, {ldq_11_bits_uop_ctrl_op_fcn}, {ldq_10_bits_uop_ctrl_op_fcn}, {ldq_9_bits_uop_ctrl_op_fcn}, {ldq_8_bits_uop_ctrl_op_fcn}, {ldq_7_bits_uop_ctrl_op_fcn}, {ldq_6_bits_uop_ctrl_op_fcn}, {ldq_5_bits_uop_ctrl_op_fcn}, {ldq_4_bits_uop_ctrl_op_fcn}, {ldq_3_bits_uop_ctrl_op_fcn}, {ldq_2_bits_uop_ctrl_op_fcn}, {ldq_1_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_112[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_113 = {{ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_23_bits_uop_ctrl_fcn_dw}, {ldq_22_bits_uop_ctrl_fcn_dw}, {ldq_21_bits_uop_ctrl_fcn_dw}, {ldq_20_bits_uop_ctrl_fcn_dw}, {ldq_19_bits_uop_ctrl_fcn_dw}, {ldq_18_bits_uop_ctrl_fcn_dw}, {ldq_17_bits_uop_ctrl_fcn_dw}, {ldq_16_bits_uop_ctrl_fcn_dw}, {ldq_15_bits_uop_ctrl_fcn_dw}, {ldq_14_bits_uop_ctrl_fcn_dw}, {ldq_13_bits_uop_ctrl_fcn_dw}, {ldq_12_bits_uop_ctrl_fcn_dw}, {ldq_11_bits_uop_ctrl_fcn_dw}, {ldq_10_bits_uop_ctrl_fcn_dw}, {ldq_9_bits_uop_ctrl_fcn_dw}, {ldq_8_bits_uop_ctrl_fcn_dw}, {ldq_7_bits_uop_ctrl_fcn_dw}, {ldq_6_bits_uop_ctrl_fcn_dw}, {ldq_5_bits_uop_ctrl_fcn_dw}, {ldq_4_bits_uop_ctrl_fcn_dw}, {ldq_3_bits_uop_ctrl_fcn_dw}, {ldq_2_bits_uop_ctrl_fcn_dw}, {ldq_1_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_113[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][2:0] _GEN_114 = {{ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_23_bits_uop_ctrl_csr_cmd}, {ldq_22_bits_uop_ctrl_csr_cmd}, {ldq_21_bits_uop_ctrl_csr_cmd}, {ldq_20_bits_uop_ctrl_csr_cmd}, {ldq_19_bits_uop_ctrl_csr_cmd}, {ldq_18_bits_uop_ctrl_csr_cmd}, {ldq_17_bits_uop_ctrl_csr_cmd}, {ldq_16_bits_uop_ctrl_csr_cmd}, {ldq_15_bits_uop_ctrl_csr_cmd}, {ldq_14_bits_uop_ctrl_csr_cmd}, {ldq_13_bits_uop_ctrl_csr_cmd}, {ldq_12_bits_uop_ctrl_csr_cmd}, {ldq_11_bits_uop_ctrl_csr_cmd}, {ldq_10_bits_uop_ctrl_csr_cmd}, {ldq_9_bits_uop_ctrl_csr_cmd}, {ldq_8_bits_uop_ctrl_csr_cmd}, {ldq_7_bits_uop_ctrl_csr_cmd}, {ldq_6_bits_uop_ctrl_csr_cmd}, {ldq_5_bits_uop_ctrl_csr_cmd}, {ldq_4_bits_uop_ctrl_csr_cmd}, {ldq_3_bits_uop_ctrl_csr_cmd}, {ldq_2_bits_uop_ctrl_csr_cmd}, {ldq_1_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_114[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_115 = {{ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_23_bits_uop_ctrl_is_load}, {ldq_22_bits_uop_ctrl_is_load}, {ldq_21_bits_uop_ctrl_is_load}, {ldq_20_bits_uop_ctrl_is_load}, {ldq_19_bits_uop_ctrl_is_load}, {ldq_18_bits_uop_ctrl_is_load}, {ldq_17_bits_uop_ctrl_is_load}, {ldq_16_bits_uop_ctrl_is_load}, {ldq_15_bits_uop_ctrl_is_load}, {ldq_14_bits_uop_ctrl_is_load}, {ldq_13_bits_uop_ctrl_is_load}, {ldq_12_bits_uop_ctrl_is_load}, {ldq_11_bits_uop_ctrl_is_load}, {ldq_10_bits_uop_ctrl_is_load}, {ldq_9_bits_uop_ctrl_is_load}, {ldq_8_bits_uop_ctrl_is_load}, {ldq_7_bits_uop_ctrl_is_load}, {ldq_6_bits_uop_ctrl_is_load}, {ldq_5_bits_uop_ctrl_is_load}, {ldq_4_bits_uop_ctrl_is_load}, {ldq_3_bits_uop_ctrl_is_load}, {ldq_2_bits_uop_ctrl_is_load}, {ldq_1_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_115[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_116 = {{ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_23_bits_uop_ctrl_is_sta}, {ldq_22_bits_uop_ctrl_is_sta}, {ldq_21_bits_uop_ctrl_is_sta}, {ldq_20_bits_uop_ctrl_is_sta}, {ldq_19_bits_uop_ctrl_is_sta}, {ldq_18_bits_uop_ctrl_is_sta}, {ldq_17_bits_uop_ctrl_is_sta}, {ldq_16_bits_uop_ctrl_is_sta}, {ldq_15_bits_uop_ctrl_is_sta}, {ldq_14_bits_uop_ctrl_is_sta}, {ldq_13_bits_uop_ctrl_is_sta}, {ldq_12_bits_uop_ctrl_is_sta}, {ldq_11_bits_uop_ctrl_is_sta}, {ldq_10_bits_uop_ctrl_is_sta}, {ldq_9_bits_uop_ctrl_is_sta}, {ldq_8_bits_uop_ctrl_is_sta}, {ldq_7_bits_uop_ctrl_is_sta}, {ldq_6_bits_uop_ctrl_is_sta}, {ldq_5_bits_uop_ctrl_is_sta}, {ldq_4_bits_uop_ctrl_is_sta}, {ldq_3_bits_uop_ctrl_is_sta}, {ldq_2_bits_uop_ctrl_is_sta}, {ldq_1_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_116[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_117 = {{ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_23_bits_uop_ctrl_is_std}, {ldq_22_bits_uop_ctrl_is_std}, {ldq_21_bits_uop_ctrl_is_std}, {ldq_20_bits_uop_ctrl_is_std}, {ldq_19_bits_uop_ctrl_is_std}, {ldq_18_bits_uop_ctrl_is_std}, {ldq_17_bits_uop_ctrl_is_std}, {ldq_16_bits_uop_ctrl_is_std}, {ldq_15_bits_uop_ctrl_is_std}, {ldq_14_bits_uop_ctrl_is_std}, {ldq_13_bits_uop_ctrl_is_std}, {ldq_12_bits_uop_ctrl_is_std}, {ldq_11_bits_uop_ctrl_is_std}, {ldq_10_bits_uop_ctrl_is_std}, {ldq_9_bits_uop_ctrl_is_std}, {ldq_8_bits_uop_ctrl_is_std}, {ldq_7_bits_uop_ctrl_is_std}, {ldq_6_bits_uop_ctrl_is_std}, {ldq_5_bits_uop_ctrl_is_std}, {ldq_4_bits_uop_ctrl_is_std}, {ldq_3_bits_uop_ctrl_is_std}, {ldq_2_bits_uop_ctrl_is_std}, {ldq_1_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_117[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_118 = {{ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_23_bits_uop_iw_state}, {ldq_22_bits_uop_iw_state}, {ldq_21_bits_uop_iw_state}, {ldq_20_bits_uop_iw_state}, {ldq_19_bits_uop_iw_state}, {ldq_18_bits_uop_iw_state}, {ldq_17_bits_uop_iw_state}, {ldq_16_bits_uop_iw_state}, {ldq_15_bits_uop_iw_state}, {ldq_14_bits_uop_iw_state}, {ldq_13_bits_uop_iw_state}, {ldq_12_bits_uop_iw_state}, {ldq_11_bits_uop_iw_state}, {ldq_10_bits_uop_iw_state}, {ldq_9_bits_uop_iw_state}, {ldq_8_bits_uop_iw_state}, {ldq_7_bits_uop_iw_state}, {ldq_6_bits_uop_iw_state}, {ldq_5_bits_uop_iw_state}, {ldq_4_bits_uop_iw_state}, {ldq_3_bits_uop_iw_state}, {ldq_2_bits_uop_iw_state}, {ldq_1_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_iw_state = _GEN_118[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_119 = {{ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_23_bits_uop_iw_p1_poisoned}, {ldq_22_bits_uop_iw_p1_poisoned}, {ldq_21_bits_uop_iw_p1_poisoned}, {ldq_20_bits_uop_iw_p1_poisoned}, {ldq_19_bits_uop_iw_p1_poisoned}, {ldq_18_bits_uop_iw_p1_poisoned}, {ldq_17_bits_uop_iw_p1_poisoned}, {ldq_16_bits_uop_iw_p1_poisoned}, {ldq_15_bits_uop_iw_p1_poisoned}, {ldq_14_bits_uop_iw_p1_poisoned}, {ldq_13_bits_uop_iw_p1_poisoned}, {ldq_12_bits_uop_iw_p1_poisoned}, {ldq_11_bits_uop_iw_p1_poisoned}, {ldq_10_bits_uop_iw_p1_poisoned}, {ldq_9_bits_uop_iw_p1_poisoned}, {ldq_8_bits_uop_iw_p1_poisoned}, {ldq_7_bits_uop_iw_p1_poisoned}, {ldq_6_bits_uop_iw_p1_poisoned}, {ldq_5_bits_uop_iw_p1_poisoned}, {ldq_4_bits_uop_iw_p1_poisoned}, {ldq_3_bits_uop_iw_p1_poisoned}, {ldq_2_bits_uop_iw_p1_poisoned}, {ldq_1_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_119[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_120 = {{ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_23_bits_uop_iw_p2_poisoned}, {ldq_22_bits_uop_iw_p2_poisoned}, {ldq_21_bits_uop_iw_p2_poisoned}, {ldq_20_bits_uop_iw_p2_poisoned}, {ldq_19_bits_uop_iw_p2_poisoned}, {ldq_18_bits_uop_iw_p2_poisoned}, {ldq_17_bits_uop_iw_p2_poisoned}, {ldq_16_bits_uop_iw_p2_poisoned}, {ldq_15_bits_uop_iw_p2_poisoned}, {ldq_14_bits_uop_iw_p2_poisoned}, {ldq_13_bits_uop_iw_p2_poisoned}, {ldq_12_bits_uop_iw_p2_poisoned}, {ldq_11_bits_uop_iw_p2_poisoned}, {ldq_10_bits_uop_iw_p2_poisoned}, {ldq_9_bits_uop_iw_p2_poisoned}, {ldq_8_bits_uop_iw_p2_poisoned}, {ldq_7_bits_uop_iw_p2_poisoned}, {ldq_6_bits_uop_iw_p2_poisoned}, {ldq_5_bits_uop_iw_p2_poisoned}, {ldq_4_bits_uop_iw_p2_poisoned}, {ldq_3_bits_uop_iw_p2_poisoned}, {ldq_2_bits_uop_iw_p2_poisoned}, {ldq_1_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_120[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_121 = {{ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_23_bits_uop_is_br}, {ldq_22_bits_uop_is_br}, {ldq_21_bits_uop_is_br}, {ldq_20_bits_uop_is_br}, {ldq_19_bits_uop_is_br}, {ldq_18_bits_uop_is_br}, {ldq_17_bits_uop_is_br}, {ldq_16_bits_uop_is_br}, {ldq_15_bits_uop_is_br}, {ldq_14_bits_uop_is_br}, {ldq_13_bits_uop_is_br}, {ldq_12_bits_uop_is_br}, {ldq_11_bits_uop_is_br}, {ldq_10_bits_uop_is_br}, {ldq_9_bits_uop_is_br}, {ldq_8_bits_uop_is_br}, {ldq_7_bits_uop_is_br}, {ldq_6_bits_uop_is_br}, {ldq_5_bits_uop_is_br}, {ldq_4_bits_uop_is_br}, {ldq_3_bits_uop_is_br}, {ldq_2_bits_uop_is_br}, {ldq_1_bits_uop_is_br}, {ldq_0_bits_uop_is_br}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_br = _GEN_121[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_122 = {{ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_23_bits_uop_is_jalr}, {ldq_22_bits_uop_is_jalr}, {ldq_21_bits_uop_is_jalr}, {ldq_20_bits_uop_is_jalr}, {ldq_19_bits_uop_is_jalr}, {ldq_18_bits_uop_is_jalr}, {ldq_17_bits_uop_is_jalr}, {ldq_16_bits_uop_is_jalr}, {ldq_15_bits_uop_is_jalr}, {ldq_14_bits_uop_is_jalr}, {ldq_13_bits_uop_is_jalr}, {ldq_12_bits_uop_is_jalr}, {ldq_11_bits_uop_is_jalr}, {ldq_10_bits_uop_is_jalr}, {ldq_9_bits_uop_is_jalr}, {ldq_8_bits_uop_is_jalr}, {ldq_7_bits_uop_is_jalr}, {ldq_6_bits_uop_is_jalr}, {ldq_5_bits_uop_is_jalr}, {ldq_4_bits_uop_is_jalr}, {ldq_3_bits_uop_is_jalr}, {ldq_2_bits_uop_is_jalr}, {ldq_1_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_jalr = _GEN_122[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_123 = {{ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_23_bits_uop_is_jal}, {ldq_22_bits_uop_is_jal}, {ldq_21_bits_uop_is_jal}, {ldq_20_bits_uop_is_jal}, {ldq_19_bits_uop_is_jal}, {ldq_18_bits_uop_is_jal}, {ldq_17_bits_uop_is_jal}, {ldq_16_bits_uop_is_jal}, {ldq_15_bits_uop_is_jal}, {ldq_14_bits_uop_is_jal}, {ldq_13_bits_uop_is_jal}, {ldq_12_bits_uop_is_jal}, {ldq_11_bits_uop_is_jal}, {ldq_10_bits_uop_is_jal}, {ldq_9_bits_uop_is_jal}, {ldq_8_bits_uop_is_jal}, {ldq_7_bits_uop_is_jal}, {ldq_6_bits_uop_is_jal}, {ldq_5_bits_uop_is_jal}, {ldq_4_bits_uop_is_jal}, {ldq_3_bits_uop_is_jal}, {ldq_2_bits_uop_is_jal}, {ldq_1_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_jal = _GEN_123[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_124 = {{ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_23_bits_uop_is_sfb}, {ldq_22_bits_uop_is_sfb}, {ldq_21_bits_uop_is_sfb}, {ldq_20_bits_uop_is_sfb}, {ldq_19_bits_uop_is_sfb}, {ldq_18_bits_uop_is_sfb}, {ldq_17_bits_uop_is_sfb}, {ldq_16_bits_uop_is_sfb}, {ldq_15_bits_uop_is_sfb}, {ldq_14_bits_uop_is_sfb}, {ldq_13_bits_uop_is_sfb}, {ldq_12_bits_uop_is_sfb}, {ldq_11_bits_uop_is_sfb}, {ldq_10_bits_uop_is_sfb}, {ldq_9_bits_uop_is_sfb}, {ldq_8_bits_uop_is_sfb}, {ldq_7_bits_uop_is_sfb}, {ldq_6_bits_uop_is_sfb}, {ldq_5_bits_uop_is_sfb}, {ldq_4_bits_uop_is_sfb}, {ldq_3_bits_uop_is_sfb}, {ldq_2_bits_uop_is_sfb}, {ldq_1_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_sfb = _GEN_124[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][15:0] _GEN_125 = {{ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_23_bits_uop_br_mask}, {ldq_22_bits_uop_br_mask}, {ldq_21_bits_uop_br_mask}, {ldq_20_bits_uop_br_mask}, {ldq_19_bits_uop_br_mask}, {ldq_18_bits_uop_br_mask}, {ldq_17_bits_uop_br_mask}, {ldq_16_bits_uop_br_mask}, {ldq_15_bits_uop_br_mask}, {ldq_14_bits_uop_br_mask}, {ldq_13_bits_uop_br_mask}, {ldq_12_bits_uop_br_mask}, {ldq_11_bits_uop_br_mask}, {ldq_10_bits_uop_br_mask}, {ldq_9_bits_uop_br_mask}, {ldq_8_bits_uop_br_mask}, {ldq_7_bits_uop_br_mask}, {ldq_6_bits_uop_br_mask}, {ldq_5_bits_uop_br_mask}, {ldq_4_bits_uop_br_mask}, {ldq_3_bits_uop_br_mask}, {ldq_2_bits_uop_br_mask}, {ldq_1_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_br_mask = _GEN_125[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][3:0] _GEN_126 = {{ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_23_bits_uop_br_tag}, {ldq_22_bits_uop_br_tag}, {ldq_21_bits_uop_br_tag}, {ldq_20_bits_uop_br_tag}, {ldq_19_bits_uop_br_tag}, {ldq_18_bits_uop_br_tag}, {ldq_17_bits_uop_br_tag}, {ldq_16_bits_uop_br_tag}, {ldq_15_bits_uop_br_tag}, {ldq_14_bits_uop_br_tag}, {ldq_13_bits_uop_br_tag}, {ldq_12_bits_uop_br_tag}, {ldq_11_bits_uop_br_tag}, {ldq_10_bits_uop_br_tag}, {ldq_9_bits_uop_br_tag}, {ldq_8_bits_uop_br_tag}, {ldq_7_bits_uop_br_tag}, {ldq_6_bits_uop_br_tag}, {ldq_5_bits_uop_br_tag}, {ldq_4_bits_uop_br_tag}, {ldq_3_bits_uop_br_tag}, {ldq_2_bits_uop_br_tag}, {ldq_1_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_br_tag = _GEN_126[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][4:0] _GEN_127 = {{ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_23_bits_uop_ftq_idx}, {ldq_22_bits_uop_ftq_idx}, {ldq_21_bits_uop_ftq_idx}, {ldq_20_bits_uop_ftq_idx}, {ldq_19_bits_uop_ftq_idx}, {ldq_18_bits_uop_ftq_idx}, {ldq_17_bits_uop_ftq_idx}, {ldq_16_bits_uop_ftq_idx}, {ldq_15_bits_uop_ftq_idx}, {ldq_14_bits_uop_ftq_idx}, {ldq_13_bits_uop_ftq_idx}, {ldq_12_bits_uop_ftq_idx}, {ldq_11_bits_uop_ftq_idx}, {ldq_10_bits_uop_ftq_idx}, {ldq_9_bits_uop_ftq_idx}, {ldq_8_bits_uop_ftq_idx}, {ldq_7_bits_uop_ftq_idx}, {ldq_6_bits_uop_ftq_idx}, {ldq_5_bits_uop_ftq_idx}, {ldq_4_bits_uop_ftq_idx}, {ldq_3_bits_uop_ftq_idx}, {ldq_2_bits_uop_ftq_idx}, {ldq_1_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ftq_idx = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_128 = {{ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_23_bits_uop_edge_inst}, {ldq_22_bits_uop_edge_inst}, {ldq_21_bits_uop_edge_inst}, {ldq_20_bits_uop_edge_inst}, {ldq_19_bits_uop_edge_inst}, {ldq_18_bits_uop_edge_inst}, {ldq_17_bits_uop_edge_inst}, {ldq_16_bits_uop_edge_inst}, {ldq_15_bits_uop_edge_inst}, {ldq_14_bits_uop_edge_inst}, {ldq_13_bits_uop_edge_inst}, {ldq_12_bits_uop_edge_inst}, {ldq_11_bits_uop_edge_inst}, {ldq_10_bits_uop_edge_inst}, {ldq_9_bits_uop_edge_inst}, {ldq_8_bits_uop_edge_inst}, {ldq_7_bits_uop_edge_inst}, {ldq_6_bits_uop_edge_inst}, {ldq_5_bits_uop_edge_inst}, {ldq_4_bits_uop_edge_inst}, {ldq_3_bits_uop_edge_inst}, {ldq_2_bits_uop_edge_inst}, {ldq_1_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_edge_inst = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][5:0] _GEN_129 = {{ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_23_bits_uop_pc_lob}, {ldq_22_bits_uop_pc_lob}, {ldq_21_bits_uop_pc_lob}, {ldq_20_bits_uop_pc_lob}, {ldq_19_bits_uop_pc_lob}, {ldq_18_bits_uop_pc_lob}, {ldq_17_bits_uop_pc_lob}, {ldq_16_bits_uop_pc_lob}, {ldq_15_bits_uop_pc_lob}, {ldq_14_bits_uop_pc_lob}, {ldq_13_bits_uop_pc_lob}, {ldq_12_bits_uop_pc_lob}, {ldq_11_bits_uop_pc_lob}, {ldq_10_bits_uop_pc_lob}, {ldq_9_bits_uop_pc_lob}, {ldq_8_bits_uop_pc_lob}, {ldq_7_bits_uop_pc_lob}, {ldq_6_bits_uop_pc_lob}, {ldq_5_bits_uop_pc_lob}, {ldq_4_bits_uop_pc_lob}, {ldq_3_bits_uop_pc_lob}, {ldq_2_bits_uop_pc_lob}, {ldq_1_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_pc_lob = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_130 = {{ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_23_bits_uop_taken}, {ldq_22_bits_uop_taken}, {ldq_21_bits_uop_taken}, {ldq_20_bits_uop_taken}, {ldq_19_bits_uop_taken}, {ldq_18_bits_uop_taken}, {ldq_17_bits_uop_taken}, {ldq_16_bits_uop_taken}, {ldq_15_bits_uop_taken}, {ldq_14_bits_uop_taken}, {ldq_13_bits_uop_taken}, {ldq_12_bits_uop_taken}, {ldq_11_bits_uop_taken}, {ldq_10_bits_uop_taken}, {ldq_9_bits_uop_taken}, {ldq_8_bits_uop_taken}, {ldq_7_bits_uop_taken}, {ldq_6_bits_uop_taken}, {ldq_5_bits_uop_taken}, {ldq_4_bits_uop_taken}, {ldq_3_bits_uop_taken}, {ldq_2_bits_uop_taken}, {ldq_1_bits_uop_taken}, {ldq_0_bits_uop_taken}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_taken = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][19:0] _GEN_131 = {{ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_23_bits_uop_imm_packed}, {ldq_22_bits_uop_imm_packed}, {ldq_21_bits_uop_imm_packed}, {ldq_20_bits_uop_imm_packed}, {ldq_19_bits_uop_imm_packed}, {ldq_18_bits_uop_imm_packed}, {ldq_17_bits_uop_imm_packed}, {ldq_16_bits_uop_imm_packed}, {ldq_15_bits_uop_imm_packed}, {ldq_14_bits_uop_imm_packed}, {ldq_13_bits_uop_imm_packed}, {ldq_12_bits_uop_imm_packed}, {ldq_11_bits_uop_imm_packed}, {ldq_10_bits_uop_imm_packed}, {ldq_9_bits_uop_imm_packed}, {ldq_8_bits_uop_imm_packed}, {ldq_7_bits_uop_imm_packed}, {ldq_6_bits_uop_imm_packed}, {ldq_5_bits_uop_imm_packed}, {ldq_4_bits_uop_imm_packed}, {ldq_3_bits_uop_imm_packed}, {ldq_2_bits_uop_imm_packed}, {ldq_1_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_imm_packed = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][11:0] _GEN_132 = {{ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_23_bits_uop_csr_addr}, {ldq_22_bits_uop_csr_addr}, {ldq_21_bits_uop_csr_addr}, {ldq_20_bits_uop_csr_addr}, {ldq_19_bits_uop_csr_addr}, {ldq_18_bits_uop_csr_addr}, {ldq_17_bits_uop_csr_addr}, {ldq_16_bits_uop_csr_addr}, {ldq_15_bits_uop_csr_addr}, {ldq_14_bits_uop_csr_addr}, {ldq_13_bits_uop_csr_addr}, {ldq_12_bits_uop_csr_addr}, {ldq_11_bits_uop_csr_addr}, {ldq_10_bits_uop_csr_addr}, {ldq_9_bits_uop_csr_addr}, {ldq_8_bits_uop_csr_addr}, {ldq_7_bits_uop_csr_addr}, {ldq_6_bits_uop_csr_addr}, {ldq_5_bits_uop_csr_addr}, {ldq_4_bits_uop_csr_addr}, {ldq_3_bits_uop_csr_addr}, {ldq_2_bits_uop_csr_addr}, {ldq_1_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_csr_addr = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][6:0] _GEN_133 = {{ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_23_bits_uop_rob_idx}, {ldq_22_bits_uop_rob_idx}, {ldq_21_bits_uop_rob_idx}, {ldq_20_bits_uop_rob_idx}, {ldq_19_bits_uop_rob_idx}, {ldq_18_bits_uop_rob_idx}, {ldq_17_bits_uop_rob_idx}, {ldq_16_bits_uop_rob_idx}, {ldq_15_bits_uop_rob_idx}, {ldq_14_bits_uop_rob_idx}, {ldq_13_bits_uop_rob_idx}, {ldq_12_bits_uop_rob_idx}, {ldq_11_bits_uop_rob_idx}, {ldq_10_bits_uop_rob_idx}, {ldq_9_bits_uop_rob_idx}, {ldq_8_bits_uop_rob_idx}, {ldq_7_bits_uop_rob_idx}, {ldq_6_bits_uop_rob_idx}, {ldq_5_bits_uop_rob_idx}, {ldq_4_bits_uop_rob_idx}, {ldq_3_bits_uop_rob_idx}, {ldq_2_bits_uop_rob_idx}, {ldq_1_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_rob_idx = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][4:0] _GEN_134 = {{ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_23_bits_uop_ldq_idx}, {ldq_22_bits_uop_ldq_idx}, {ldq_21_bits_uop_ldq_idx}, {ldq_20_bits_uop_ldq_idx}, {ldq_19_bits_uop_ldq_idx}, {ldq_18_bits_uop_ldq_idx}, {ldq_17_bits_uop_ldq_idx}, {ldq_16_bits_uop_ldq_idx}, {ldq_15_bits_uop_ldq_idx}, {ldq_14_bits_uop_ldq_idx}, {ldq_13_bits_uop_ldq_idx}, {ldq_12_bits_uop_ldq_idx}, {ldq_11_bits_uop_ldq_idx}, {ldq_10_bits_uop_ldq_idx}, {ldq_9_bits_uop_ldq_idx}, {ldq_8_bits_uop_ldq_idx}, {ldq_7_bits_uop_ldq_idx}, {ldq_6_bits_uop_ldq_idx}, {ldq_5_bits_uop_ldq_idx}, {ldq_4_bits_uop_ldq_idx}, {ldq_3_bits_uop_ldq_idx}, {ldq_2_bits_uop_ldq_idx}, {ldq_1_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ldq_idx = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][4:0] _GEN_135 = {{ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_23_bits_uop_stq_idx}, {ldq_22_bits_uop_stq_idx}, {ldq_21_bits_uop_stq_idx}, {ldq_20_bits_uop_stq_idx}, {ldq_19_bits_uop_stq_idx}, {ldq_18_bits_uop_stq_idx}, {ldq_17_bits_uop_stq_idx}, {ldq_16_bits_uop_stq_idx}, {ldq_15_bits_uop_stq_idx}, {ldq_14_bits_uop_stq_idx}, {ldq_13_bits_uop_stq_idx}, {ldq_12_bits_uop_stq_idx}, {ldq_11_bits_uop_stq_idx}, {ldq_10_bits_uop_stq_idx}, {ldq_9_bits_uop_stq_idx}, {ldq_8_bits_uop_stq_idx}, {ldq_7_bits_uop_stq_idx}, {ldq_6_bits_uop_stq_idx}, {ldq_5_bits_uop_stq_idx}, {ldq_4_bits_uop_stq_idx}, {ldq_3_bits_uop_stq_idx}, {ldq_2_bits_uop_stq_idx}, {ldq_1_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_stq_idx = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_136 = {{ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_23_bits_uop_rxq_idx}, {ldq_22_bits_uop_rxq_idx}, {ldq_21_bits_uop_rxq_idx}, {ldq_20_bits_uop_rxq_idx}, {ldq_19_bits_uop_rxq_idx}, {ldq_18_bits_uop_rxq_idx}, {ldq_17_bits_uop_rxq_idx}, {ldq_16_bits_uop_rxq_idx}, {ldq_15_bits_uop_rxq_idx}, {ldq_14_bits_uop_rxq_idx}, {ldq_13_bits_uop_rxq_idx}, {ldq_12_bits_uop_rxq_idx}, {ldq_11_bits_uop_rxq_idx}, {ldq_10_bits_uop_rxq_idx}, {ldq_9_bits_uop_rxq_idx}, {ldq_8_bits_uop_rxq_idx}, {ldq_7_bits_uop_rxq_idx}, {ldq_6_bits_uop_rxq_idx}, {ldq_5_bits_uop_rxq_idx}, {ldq_4_bits_uop_rxq_idx}, {ldq_3_bits_uop_rxq_idx}, {ldq_2_bits_uop_rxq_idx}, {ldq_1_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_rxq_idx = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][6:0] _GEN_137 = {{ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_23_bits_uop_pdst}, {ldq_22_bits_uop_pdst}, {ldq_21_bits_uop_pdst}, {ldq_20_bits_uop_pdst}, {ldq_19_bits_uop_pdst}, {ldq_18_bits_uop_pdst}, {ldq_17_bits_uop_pdst}, {ldq_16_bits_uop_pdst}, {ldq_15_bits_uop_pdst}, {ldq_14_bits_uop_pdst}, {ldq_13_bits_uop_pdst}, {ldq_12_bits_uop_pdst}, {ldq_11_bits_uop_pdst}, {ldq_10_bits_uop_pdst}, {ldq_9_bits_uop_pdst}, {ldq_8_bits_uop_pdst}, {ldq_7_bits_uop_pdst}, {ldq_6_bits_uop_pdst}, {ldq_5_bits_uop_pdst}, {ldq_4_bits_uop_pdst}, {ldq_3_bits_uop_pdst}, {ldq_2_bits_uop_pdst}, {ldq_1_bits_uop_pdst}, {ldq_0_bits_uop_pdst}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_pdst = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][6:0] _GEN_138 = {{ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_23_bits_uop_prs1}, {ldq_22_bits_uop_prs1}, {ldq_21_bits_uop_prs1}, {ldq_20_bits_uop_prs1}, {ldq_19_bits_uop_prs1}, {ldq_18_bits_uop_prs1}, {ldq_17_bits_uop_prs1}, {ldq_16_bits_uop_prs1}, {ldq_15_bits_uop_prs1}, {ldq_14_bits_uop_prs1}, {ldq_13_bits_uop_prs1}, {ldq_12_bits_uop_prs1}, {ldq_11_bits_uop_prs1}, {ldq_10_bits_uop_prs1}, {ldq_9_bits_uop_prs1}, {ldq_8_bits_uop_prs1}, {ldq_7_bits_uop_prs1}, {ldq_6_bits_uop_prs1}, {ldq_5_bits_uop_prs1}, {ldq_4_bits_uop_prs1}, {ldq_3_bits_uop_prs1}, {ldq_2_bits_uop_prs1}, {ldq_1_bits_uop_prs1}, {ldq_0_bits_uop_prs1}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_prs1 = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][6:0] _GEN_139 = {{ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_23_bits_uop_prs2}, {ldq_22_bits_uop_prs2}, {ldq_21_bits_uop_prs2}, {ldq_20_bits_uop_prs2}, {ldq_19_bits_uop_prs2}, {ldq_18_bits_uop_prs2}, {ldq_17_bits_uop_prs2}, {ldq_16_bits_uop_prs2}, {ldq_15_bits_uop_prs2}, {ldq_14_bits_uop_prs2}, {ldq_13_bits_uop_prs2}, {ldq_12_bits_uop_prs2}, {ldq_11_bits_uop_prs2}, {ldq_10_bits_uop_prs2}, {ldq_9_bits_uop_prs2}, {ldq_8_bits_uop_prs2}, {ldq_7_bits_uop_prs2}, {ldq_6_bits_uop_prs2}, {ldq_5_bits_uop_prs2}, {ldq_4_bits_uop_prs2}, {ldq_3_bits_uop_prs2}, {ldq_2_bits_uop_prs2}, {ldq_1_bits_uop_prs2}, {ldq_0_bits_uop_prs2}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_prs2 = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][6:0] _GEN_140 = {{ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_23_bits_uop_prs3}, {ldq_22_bits_uop_prs3}, {ldq_21_bits_uop_prs3}, {ldq_20_bits_uop_prs3}, {ldq_19_bits_uop_prs3}, {ldq_18_bits_uop_prs3}, {ldq_17_bits_uop_prs3}, {ldq_16_bits_uop_prs3}, {ldq_15_bits_uop_prs3}, {ldq_14_bits_uop_prs3}, {ldq_13_bits_uop_prs3}, {ldq_12_bits_uop_prs3}, {ldq_11_bits_uop_prs3}, {ldq_10_bits_uop_prs3}, {ldq_9_bits_uop_prs3}, {ldq_8_bits_uop_prs3}, {ldq_7_bits_uop_prs3}, {ldq_6_bits_uop_prs3}, {ldq_5_bits_uop_prs3}, {ldq_4_bits_uop_prs3}, {ldq_3_bits_uop_prs3}, {ldq_2_bits_uop_prs3}, {ldq_1_bits_uop_prs3}, {ldq_0_bits_uop_prs3}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_prs3 = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_141 = {{ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_23_bits_uop_prs1_busy}, {ldq_22_bits_uop_prs1_busy}, {ldq_21_bits_uop_prs1_busy}, {ldq_20_bits_uop_prs1_busy}, {ldq_19_bits_uop_prs1_busy}, {ldq_18_bits_uop_prs1_busy}, {ldq_17_bits_uop_prs1_busy}, {ldq_16_bits_uop_prs1_busy}, {ldq_15_bits_uop_prs1_busy}, {ldq_14_bits_uop_prs1_busy}, {ldq_13_bits_uop_prs1_busy}, {ldq_12_bits_uop_prs1_busy}, {ldq_11_bits_uop_prs1_busy}, {ldq_10_bits_uop_prs1_busy}, {ldq_9_bits_uop_prs1_busy}, {ldq_8_bits_uop_prs1_busy}, {ldq_7_bits_uop_prs1_busy}, {ldq_6_bits_uop_prs1_busy}, {ldq_5_bits_uop_prs1_busy}, {ldq_4_bits_uop_prs1_busy}, {ldq_3_bits_uop_prs1_busy}, {ldq_2_bits_uop_prs1_busy}, {ldq_1_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_prs1_busy = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_142 = {{ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_23_bits_uop_prs2_busy}, {ldq_22_bits_uop_prs2_busy}, {ldq_21_bits_uop_prs2_busy}, {ldq_20_bits_uop_prs2_busy}, {ldq_19_bits_uop_prs2_busy}, {ldq_18_bits_uop_prs2_busy}, {ldq_17_bits_uop_prs2_busy}, {ldq_16_bits_uop_prs2_busy}, {ldq_15_bits_uop_prs2_busy}, {ldq_14_bits_uop_prs2_busy}, {ldq_13_bits_uop_prs2_busy}, {ldq_12_bits_uop_prs2_busy}, {ldq_11_bits_uop_prs2_busy}, {ldq_10_bits_uop_prs2_busy}, {ldq_9_bits_uop_prs2_busy}, {ldq_8_bits_uop_prs2_busy}, {ldq_7_bits_uop_prs2_busy}, {ldq_6_bits_uop_prs2_busy}, {ldq_5_bits_uop_prs2_busy}, {ldq_4_bits_uop_prs2_busy}, {ldq_3_bits_uop_prs2_busy}, {ldq_2_bits_uop_prs2_busy}, {ldq_1_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_prs2_busy = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_143 = {{ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_23_bits_uop_prs3_busy}, {ldq_22_bits_uop_prs3_busy}, {ldq_21_bits_uop_prs3_busy}, {ldq_20_bits_uop_prs3_busy}, {ldq_19_bits_uop_prs3_busy}, {ldq_18_bits_uop_prs3_busy}, {ldq_17_bits_uop_prs3_busy}, {ldq_16_bits_uop_prs3_busy}, {ldq_15_bits_uop_prs3_busy}, {ldq_14_bits_uop_prs3_busy}, {ldq_13_bits_uop_prs3_busy}, {ldq_12_bits_uop_prs3_busy}, {ldq_11_bits_uop_prs3_busy}, {ldq_10_bits_uop_prs3_busy}, {ldq_9_bits_uop_prs3_busy}, {ldq_8_bits_uop_prs3_busy}, {ldq_7_bits_uop_prs3_busy}, {ldq_6_bits_uop_prs3_busy}, {ldq_5_bits_uop_prs3_busy}, {ldq_4_bits_uop_prs3_busy}, {ldq_3_bits_uop_prs3_busy}, {ldq_2_bits_uop_prs3_busy}, {ldq_1_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_prs3_busy = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][6:0] _GEN_144 = {{ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_23_bits_uop_stale_pdst}, {ldq_22_bits_uop_stale_pdst}, {ldq_21_bits_uop_stale_pdst}, {ldq_20_bits_uop_stale_pdst}, {ldq_19_bits_uop_stale_pdst}, {ldq_18_bits_uop_stale_pdst}, {ldq_17_bits_uop_stale_pdst}, {ldq_16_bits_uop_stale_pdst}, {ldq_15_bits_uop_stale_pdst}, {ldq_14_bits_uop_stale_pdst}, {ldq_13_bits_uop_stale_pdst}, {ldq_12_bits_uop_stale_pdst}, {ldq_11_bits_uop_stale_pdst}, {ldq_10_bits_uop_stale_pdst}, {ldq_9_bits_uop_stale_pdst}, {ldq_8_bits_uop_stale_pdst}, {ldq_7_bits_uop_stale_pdst}, {ldq_6_bits_uop_stale_pdst}, {ldq_5_bits_uop_stale_pdst}, {ldq_4_bits_uop_stale_pdst}, {ldq_3_bits_uop_stale_pdst}, {ldq_2_bits_uop_stale_pdst}, {ldq_1_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_stale_pdst = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_145 = {{ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_23_bits_uop_exception}, {ldq_22_bits_uop_exception}, {ldq_21_bits_uop_exception}, {ldq_20_bits_uop_exception}, {ldq_19_bits_uop_exception}, {ldq_18_bits_uop_exception}, {ldq_17_bits_uop_exception}, {ldq_16_bits_uop_exception}, {ldq_15_bits_uop_exception}, {ldq_14_bits_uop_exception}, {ldq_13_bits_uop_exception}, {ldq_12_bits_uop_exception}, {ldq_11_bits_uop_exception}, {ldq_10_bits_uop_exception}, {ldq_9_bits_uop_exception}, {ldq_8_bits_uop_exception}, {ldq_7_bits_uop_exception}, {ldq_6_bits_uop_exception}, {ldq_5_bits_uop_exception}, {ldq_4_bits_uop_exception}, {ldq_3_bits_uop_exception}, {ldq_2_bits_uop_exception}, {ldq_1_bits_uop_exception}, {ldq_0_bits_uop_exception}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_exception = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][63:0] _GEN_146 = {{ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_23_bits_uop_exc_cause}, {ldq_22_bits_uop_exc_cause}, {ldq_21_bits_uop_exc_cause}, {ldq_20_bits_uop_exc_cause}, {ldq_19_bits_uop_exc_cause}, {ldq_18_bits_uop_exc_cause}, {ldq_17_bits_uop_exc_cause}, {ldq_16_bits_uop_exc_cause}, {ldq_15_bits_uop_exc_cause}, {ldq_14_bits_uop_exc_cause}, {ldq_13_bits_uop_exc_cause}, {ldq_12_bits_uop_exc_cause}, {ldq_11_bits_uop_exc_cause}, {ldq_10_bits_uop_exc_cause}, {ldq_9_bits_uop_exc_cause}, {ldq_8_bits_uop_exc_cause}, {ldq_7_bits_uop_exc_cause}, {ldq_6_bits_uop_exc_cause}, {ldq_5_bits_uop_exc_cause}, {ldq_4_bits_uop_exc_cause}, {ldq_3_bits_uop_exc_cause}, {ldq_2_bits_uop_exc_cause}, {ldq_1_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_exc_cause = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_147 = {{ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_23_bits_uop_bypassable}, {ldq_22_bits_uop_bypassable}, {ldq_21_bits_uop_bypassable}, {ldq_20_bits_uop_bypassable}, {ldq_19_bits_uop_bypassable}, {ldq_18_bits_uop_bypassable}, {ldq_17_bits_uop_bypassable}, {ldq_16_bits_uop_bypassable}, {ldq_15_bits_uop_bypassable}, {ldq_14_bits_uop_bypassable}, {ldq_13_bits_uop_bypassable}, {ldq_12_bits_uop_bypassable}, {ldq_11_bits_uop_bypassable}, {ldq_10_bits_uop_bypassable}, {ldq_9_bits_uop_bypassable}, {ldq_8_bits_uop_bypassable}, {ldq_7_bits_uop_bypassable}, {ldq_6_bits_uop_bypassable}, {ldq_5_bits_uop_bypassable}, {ldq_4_bits_uop_bypassable}, {ldq_3_bits_uop_bypassable}, {ldq_2_bits_uop_bypassable}, {ldq_1_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_bypassable = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][4:0] _GEN_148 = {{ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_23_bits_uop_mem_cmd}, {ldq_22_bits_uop_mem_cmd}, {ldq_21_bits_uop_mem_cmd}, {ldq_20_bits_uop_mem_cmd}, {ldq_19_bits_uop_mem_cmd}, {ldq_18_bits_uop_mem_cmd}, {ldq_17_bits_uop_mem_cmd}, {ldq_16_bits_uop_mem_cmd}, {ldq_15_bits_uop_mem_cmd}, {ldq_14_bits_uop_mem_cmd}, {ldq_13_bits_uop_mem_cmd}, {ldq_12_bits_uop_mem_cmd}, {ldq_11_bits_uop_mem_cmd}, {ldq_10_bits_uop_mem_cmd}, {ldq_9_bits_uop_mem_cmd}, {ldq_8_bits_uop_mem_cmd}, {ldq_7_bits_uop_mem_cmd}, {ldq_6_bits_uop_mem_cmd}, {ldq_5_bits_uop_mem_cmd}, {ldq_4_bits_uop_mem_cmd}, {ldq_3_bits_uop_mem_cmd}, {ldq_2_bits_uop_mem_cmd}, {ldq_1_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_mem_cmd = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_149 = {{ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_23_bits_uop_mem_size}, {ldq_22_bits_uop_mem_size}, {ldq_21_bits_uop_mem_size}, {ldq_20_bits_uop_mem_size}, {ldq_19_bits_uop_mem_size}, {ldq_18_bits_uop_mem_size}, {ldq_17_bits_uop_mem_size}, {ldq_16_bits_uop_mem_size}, {ldq_15_bits_uop_mem_size}, {ldq_14_bits_uop_mem_size}, {ldq_13_bits_uop_mem_size}, {ldq_12_bits_uop_mem_size}, {ldq_11_bits_uop_mem_size}, {ldq_10_bits_uop_mem_size}, {ldq_9_bits_uop_mem_size}, {ldq_8_bits_uop_mem_size}, {ldq_7_bits_uop_mem_size}, {ldq_6_bits_uop_mem_size}, {ldq_5_bits_uop_mem_size}, {ldq_4_bits_uop_mem_size}, {ldq_3_bits_uop_mem_size}, {ldq_2_bits_uop_mem_size}, {ldq_1_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_mem_size = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_150 = {{ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_23_bits_uop_mem_signed}, {ldq_22_bits_uop_mem_signed}, {ldq_21_bits_uop_mem_signed}, {ldq_20_bits_uop_mem_signed}, {ldq_19_bits_uop_mem_signed}, {ldq_18_bits_uop_mem_signed}, {ldq_17_bits_uop_mem_signed}, {ldq_16_bits_uop_mem_signed}, {ldq_15_bits_uop_mem_signed}, {ldq_14_bits_uop_mem_signed}, {ldq_13_bits_uop_mem_signed}, {ldq_12_bits_uop_mem_signed}, {ldq_11_bits_uop_mem_signed}, {ldq_10_bits_uop_mem_signed}, {ldq_9_bits_uop_mem_signed}, {ldq_8_bits_uop_mem_signed}, {ldq_7_bits_uop_mem_signed}, {ldq_6_bits_uop_mem_signed}, {ldq_5_bits_uop_mem_signed}, {ldq_4_bits_uop_mem_signed}, {ldq_3_bits_uop_mem_signed}, {ldq_2_bits_uop_mem_signed}, {ldq_1_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_mem_signed = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_151 = {{ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_23_bits_uop_is_fence}, {ldq_22_bits_uop_is_fence}, {ldq_21_bits_uop_is_fence}, {ldq_20_bits_uop_is_fence}, {ldq_19_bits_uop_is_fence}, {ldq_18_bits_uop_is_fence}, {ldq_17_bits_uop_is_fence}, {ldq_16_bits_uop_is_fence}, {ldq_15_bits_uop_is_fence}, {ldq_14_bits_uop_is_fence}, {ldq_13_bits_uop_is_fence}, {ldq_12_bits_uop_is_fence}, {ldq_11_bits_uop_is_fence}, {ldq_10_bits_uop_is_fence}, {ldq_9_bits_uop_is_fence}, {ldq_8_bits_uop_is_fence}, {ldq_7_bits_uop_is_fence}, {ldq_6_bits_uop_is_fence}, {ldq_5_bits_uop_is_fence}, {ldq_4_bits_uop_is_fence}, {ldq_3_bits_uop_is_fence}, {ldq_2_bits_uop_is_fence}, {ldq_1_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_fence = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_152 = {{ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_23_bits_uop_is_fencei}, {ldq_22_bits_uop_is_fencei}, {ldq_21_bits_uop_is_fencei}, {ldq_20_bits_uop_is_fencei}, {ldq_19_bits_uop_is_fencei}, {ldq_18_bits_uop_is_fencei}, {ldq_17_bits_uop_is_fencei}, {ldq_16_bits_uop_is_fencei}, {ldq_15_bits_uop_is_fencei}, {ldq_14_bits_uop_is_fencei}, {ldq_13_bits_uop_is_fencei}, {ldq_12_bits_uop_is_fencei}, {ldq_11_bits_uop_is_fencei}, {ldq_10_bits_uop_is_fencei}, {ldq_9_bits_uop_is_fencei}, {ldq_8_bits_uop_is_fencei}, {ldq_7_bits_uop_is_fencei}, {ldq_6_bits_uop_is_fencei}, {ldq_5_bits_uop_is_fencei}, {ldq_4_bits_uop_is_fencei}, {ldq_3_bits_uop_is_fencei}, {ldq_2_bits_uop_is_fencei}, {ldq_1_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_fencei = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_153 = {{ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_23_bits_uop_is_amo}, {ldq_22_bits_uop_is_amo}, {ldq_21_bits_uop_is_amo}, {ldq_20_bits_uop_is_amo}, {ldq_19_bits_uop_is_amo}, {ldq_18_bits_uop_is_amo}, {ldq_17_bits_uop_is_amo}, {ldq_16_bits_uop_is_amo}, {ldq_15_bits_uop_is_amo}, {ldq_14_bits_uop_is_amo}, {ldq_13_bits_uop_is_amo}, {ldq_12_bits_uop_is_amo}, {ldq_11_bits_uop_is_amo}, {ldq_10_bits_uop_is_amo}, {ldq_9_bits_uop_is_amo}, {ldq_8_bits_uop_is_amo}, {ldq_7_bits_uop_is_amo}, {ldq_6_bits_uop_is_amo}, {ldq_5_bits_uop_is_amo}, {ldq_4_bits_uop_is_amo}, {ldq_3_bits_uop_is_amo}, {ldq_2_bits_uop_is_amo}, {ldq_1_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_amo = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_154 = {{ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_23_bits_uop_uses_ldq}, {ldq_22_bits_uop_uses_ldq}, {ldq_21_bits_uop_uses_ldq}, {ldq_20_bits_uop_uses_ldq}, {ldq_19_bits_uop_uses_ldq}, {ldq_18_bits_uop_uses_ldq}, {ldq_17_bits_uop_uses_ldq}, {ldq_16_bits_uop_uses_ldq}, {ldq_15_bits_uop_uses_ldq}, {ldq_14_bits_uop_uses_ldq}, {ldq_13_bits_uop_uses_ldq}, {ldq_12_bits_uop_uses_ldq}, {ldq_11_bits_uop_uses_ldq}, {ldq_10_bits_uop_uses_ldq}, {ldq_9_bits_uop_uses_ldq}, {ldq_8_bits_uop_uses_ldq}, {ldq_7_bits_uop_uses_ldq}, {ldq_6_bits_uop_uses_ldq}, {ldq_5_bits_uop_uses_ldq}, {ldq_4_bits_uop_uses_ldq}, {ldq_3_bits_uop_uses_ldq}, {ldq_2_bits_uop_uses_ldq}, {ldq_1_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_uses_ldq = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_155 = {{ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_23_bits_uop_uses_stq}, {ldq_22_bits_uop_uses_stq}, {ldq_21_bits_uop_uses_stq}, {ldq_20_bits_uop_uses_stq}, {ldq_19_bits_uop_uses_stq}, {ldq_18_bits_uop_uses_stq}, {ldq_17_bits_uop_uses_stq}, {ldq_16_bits_uop_uses_stq}, {ldq_15_bits_uop_uses_stq}, {ldq_14_bits_uop_uses_stq}, {ldq_13_bits_uop_uses_stq}, {ldq_12_bits_uop_uses_stq}, {ldq_11_bits_uop_uses_stq}, {ldq_10_bits_uop_uses_stq}, {ldq_9_bits_uop_uses_stq}, {ldq_8_bits_uop_uses_stq}, {ldq_7_bits_uop_uses_stq}, {ldq_6_bits_uop_uses_stq}, {ldq_5_bits_uop_uses_stq}, {ldq_4_bits_uop_uses_stq}, {ldq_3_bits_uop_uses_stq}, {ldq_2_bits_uop_uses_stq}, {ldq_1_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_uses_stq = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_156 = {{ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_23_bits_uop_is_sys_pc2epc}, {ldq_22_bits_uop_is_sys_pc2epc}, {ldq_21_bits_uop_is_sys_pc2epc}, {ldq_20_bits_uop_is_sys_pc2epc}, {ldq_19_bits_uop_is_sys_pc2epc}, {ldq_18_bits_uop_is_sys_pc2epc}, {ldq_17_bits_uop_is_sys_pc2epc}, {ldq_16_bits_uop_is_sys_pc2epc}, {ldq_15_bits_uop_is_sys_pc2epc}, {ldq_14_bits_uop_is_sys_pc2epc}, {ldq_13_bits_uop_is_sys_pc2epc}, {ldq_12_bits_uop_is_sys_pc2epc}, {ldq_11_bits_uop_is_sys_pc2epc}, {ldq_10_bits_uop_is_sys_pc2epc}, {ldq_9_bits_uop_is_sys_pc2epc}, {ldq_8_bits_uop_is_sys_pc2epc}, {ldq_7_bits_uop_is_sys_pc2epc}, {ldq_6_bits_uop_is_sys_pc2epc}, {ldq_5_bits_uop_is_sys_pc2epc}, {ldq_4_bits_uop_is_sys_pc2epc}, {ldq_3_bits_uop_is_sys_pc2epc}, {ldq_2_bits_uop_is_sys_pc2epc}, {ldq_1_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_157 = {{ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_23_bits_uop_is_unique}, {ldq_22_bits_uop_is_unique}, {ldq_21_bits_uop_is_unique}, {ldq_20_bits_uop_is_unique}, {ldq_19_bits_uop_is_unique}, {ldq_18_bits_uop_is_unique}, {ldq_17_bits_uop_is_unique}, {ldq_16_bits_uop_is_unique}, {ldq_15_bits_uop_is_unique}, {ldq_14_bits_uop_is_unique}, {ldq_13_bits_uop_is_unique}, {ldq_12_bits_uop_is_unique}, {ldq_11_bits_uop_is_unique}, {ldq_10_bits_uop_is_unique}, {ldq_9_bits_uop_is_unique}, {ldq_8_bits_uop_is_unique}, {ldq_7_bits_uop_is_unique}, {ldq_6_bits_uop_is_unique}, {ldq_5_bits_uop_is_unique}, {ldq_4_bits_uop_is_unique}, {ldq_3_bits_uop_is_unique}, {ldq_2_bits_uop_is_unique}, {ldq_1_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_is_unique = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_158 = {{ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_23_bits_uop_flush_on_commit}, {ldq_22_bits_uop_flush_on_commit}, {ldq_21_bits_uop_flush_on_commit}, {ldq_20_bits_uop_flush_on_commit}, {ldq_19_bits_uop_flush_on_commit}, {ldq_18_bits_uop_flush_on_commit}, {ldq_17_bits_uop_flush_on_commit}, {ldq_16_bits_uop_flush_on_commit}, {ldq_15_bits_uop_flush_on_commit}, {ldq_14_bits_uop_flush_on_commit}, {ldq_13_bits_uop_flush_on_commit}, {ldq_12_bits_uop_flush_on_commit}, {ldq_11_bits_uop_flush_on_commit}, {ldq_10_bits_uop_flush_on_commit}, {ldq_9_bits_uop_flush_on_commit}, {ldq_8_bits_uop_flush_on_commit}, {ldq_7_bits_uop_flush_on_commit}, {ldq_6_bits_uop_flush_on_commit}, {ldq_5_bits_uop_flush_on_commit}, {ldq_4_bits_uop_flush_on_commit}, {ldq_3_bits_uop_flush_on_commit}, {ldq_2_bits_uop_flush_on_commit}, {ldq_1_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_flush_on_commit = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_159 = {{ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_23_bits_uop_ldst_is_rs1}, {ldq_22_bits_uop_ldst_is_rs1}, {ldq_21_bits_uop_ldst_is_rs1}, {ldq_20_bits_uop_ldst_is_rs1}, {ldq_19_bits_uop_ldst_is_rs1}, {ldq_18_bits_uop_ldst_is_rs1}, {ldq_17_bits_uop_ldst_is_rs1}, {ldq_16_bits_uop_ldst_is_rs1}, {ldq_15_bits_uop_ldst_is_rs1}, {ldq_14_bits_uop_ldst_is_rs1}, {ldq_13_bits_uop_ldst_is_rs1}, {ldq_12_bits_uop_ldst_is_rs1}, {ldq_11_bits_uop_ldst_is_rs1}, {ldq_10_bits_uop_ldst_is_rs1}, {ldq_9_bits_uop_ldst_is_rs1}, {ldq_8_bits_uop_ldst_is_rs1}, {ldq_7_bits_uop_ldst_is_rs1}, {ldq_6_bits_uop_ldst_is_rs1}, {ldq_5_bits_uop_ldst_is_rs1}, {ldq_4_bits_uop_ldst_is_rs1}, {ldq_3_bits_uop_ldst_is_rs1}, {ldq_2_bits_uop_ldst_is_rs1}, {ldq_1_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][5:0] _GEN_160 = {{ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_23_bits_uop_ldst}, {ldq_22_bits_uop_ldst}, {ldq_21_bits_uop_ldst}, {ldq_20_bits_uop_ldst}, {ldq_19_bits_uop_ldst}, {ldq_18_bits_uop_ldst}, {ldq_17_bits_uop_ldst}, {ldq_16_bits_uop_ldst}, {ldq_15_bits_uop_ldst}, {ldq_14_bits_uop_ldst}, {ldq_13_bits_uop_ldst}, {ldq_12_bits_uop_ldst}, {ldq_11_bits_uop_ldst}, {ldq_10_bits_uop_ldst}, {ldq_9_bits_uop_ldst}, {ldq_8_bits_uop_ldst}, {ldq_7_bits_uop_ldst}, {ldq_6_bits_uop_ldst}, {ldq_5_bits_uop_ldst}, {ldq_4_bits_uop_ldst}, {ldq_3_bits_uop_ldst}, {ldq_2_bits_uop_ldst}, {ldq_1_bits_uop_ldst}, {ldq_0_bits_uop_ldst}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ldst = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][5:0] _GEN_161 = {{ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_23_bits_uop_lrs1}, {ldq_22_bits_uop_lrs1}, {ldq_21_bits_uop_lrs1}, {ldq_20_bits_uop_lrs1}, {ldq_19_bits_uop_lrs1}, {ldq_18_bits_uop_lrs1}, {ldq_17_bits_uop_lrs1}, {ldq_16_bits_uop_lrs1}, {ldq_15_bits_uop_lrs1}, {ldq_14_bits_uop_lrs1}, {ldq_13_bits_uop_lrs1}, {ldq_12_bits_uop_lrs1}, {ldq_11_bits_uop_lrs1}, {ldq_10_bits_uop_lrs1}, {ldq_9_bits_uop_lrs1}, {ldq_8_bits_uop_lrs1}, {ldq_7_bits_uop_lrs1}, {ldq_6_bits_uop_lrs1}, {ldq_5_bits_uop_lrs1}, {ldq_4_bits_uop_lrs1}, {ldq_3_bits_uop_lrs1}, {ldq_2_bits_uop_lrs1}, {ldq_1_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_lrs1 = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][5:0] _GEN_162 = {{ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_23_bits_uop_lrs2}, {ldq_22_bits_uop_lrs2}, {ldq_21_bits_uop_lrs2}, {ldq_20_bits_uop_lrs2}, {ldq_19_bits_uop_lrs2}, {ldq_18_bits_uop_lrs2}, {ldq_17_bits_uop_lrs2}, {ldq_16_bits_uop_lrs2}, {ldq_15_bits_uop_lrs2}, {ldq_14_bits_uop_lrs2}, {ldq_13_bits_uop_lrs2}, {ldq_12_bits_uop_lrs2}, {ldq_11_bits_uop_lrs2}, {ldq_10_bits_uop_lrs2}, {ldq_9_bits_uop_lrs2}, {ldq_8_bits_uop_lrs2}, {ldq_7_bits_uop_lrs2}, {ldq_6_bits_uop_lrs2}, {ldq_5_bits_uop_lrs2}, {ldq_4_bits_uop_lrs2}, {ldq_3_bits_uop_lrs2}, {ldq_2_bits_uop_lrs2}, {ldq_1_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_lrs2 = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][5:0] _GEN_163 = {{ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_23_bits_uop_lrs3}, {ldq_22_bits_uop_lrs3}, {ldq_21_bits_uop_lrs3}, {ldq_20_bits_uop_lrs3}, {ldq_19_bits_uop_lrs3}, {ldq_18_bits_uop_lrs3}, {ldq_17_bits_uop_lrs3}, {ldq_16_bits_uop_lrs3}, {ldq_15_bits_uop_lrs3}, {ldq_14_bits_uop_lrs3}, {ldq_13_bits_uop_lrs3}, {ldq_12_bits_uop_lrs3}, {ldq_11_bits_uop_lrs3}, {ldq_10_bits_uop_lrs3}, {ldq_9_bits_uop_lrs3}, {ldq_8_bits_uop_lrs3}, {ldq_7_bits_uop_lrs3}, {ldq_6_bits_uop_lrs3}, {ldq_5_bits_uop_lrs3}, {ldq_4_bits_uop_lrs3}, {ldq_3_bits_uop_lrs3}, {ldq_2_bits_uop_lrs3}, {ldq_1_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_lrs3 = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_164 = {{ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_23_bits_uop_ldst_val}, {ldq_22_bits_uop_ldst_val}, {ldq_21_bits_uop_ldst_val}, {ldq_20_bits_uop_ldst_val}, {ldq_19_bits_uop_ldst_val}, {ldq_18_bits_uop_ldst_val}, {ldq_17_bits_uop_ldst_val}, {ldq_16_bits_uop_ldst_val}, {ldq_15_bits_uop_ldst_val}, {ldq_14_bits_uop_ldst_val}, {ldq_13_bits_uop_ldst_val}, {ldq_12_bits_uop_ldst_val}, {ldq_11_bits_uop_ldst_val}, {ldq_10_bits_uop_ldst_val}, {ldq_9_bits_uop_ldst_val}, {ldq_8_bits_uop_ldst_val}, {ldq_7_bits_uop_ldst_val}, {ldq_6_bits_uop_ldst_val}, {ldq_5_bits_uop_ldst_val}, {ldq_4_bits_uop_ldst_val}, {ldq_3_bits_uop_ldst_val}, {ldq_2_bits_uop_ldst_val}, {ldq_1_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_ldst_val = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_165 = {{ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_23_bits_uop_dst_rtype}, {ldq_22_bits_uop_dst_rtype}, {ldq_21_bits_uop_dst_rtype}, {ldq_20_bits_uop_dst_rtype}, {ldq_19_bits_uop_dst_rtype}, {ldq_18_bits_uop_dst_rtype}, {ldq_17_bits_uop_dst_rtype}, {ldq_16_bits_uop_dst_rtype}, {ldq_15_bits_uop_dst_rtype}, {ldq_14_bits_uop_dst_rtype}, {ldq_13_bits_uop_dst_rtype}, {ldq_12_bits_uop_dst_rtype}, {ldq_11_bits_uop_dst_rtype}, {ldq_10_bits_uop_dst_rtype}, {ldq_9_bits_uop_dst_rtype}, {ldq_8_bits_uop_dst_rtype}, {ldq_7_bits_uop_dst_rtype}, {ldq_6_bits_uop_dst_rtype}, {ldq_5_bits_uop_dst_rtype}, {ldq_4_bits_uop_dst_rtype}, {ldq_3_bits_uop_dst_rtype}, {ldq_2_bits_uop_dst_rtype}, {ldq_1_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_dst_rtype = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_166 = {{ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_23_bits_uop_lrs1_rtype}, {ldq_22_bits_uop_lrs1_rtype}, {ldq_21_bits_uop_lrs1_rtype}, {ldq_20_bits_uop_lrs1_rtype}, {ldq_19_bits_uop_lrs1_rtype}, {ldq_18_bits_uop_lrs1_rtype}, {ldq_17_bits_uop_lrs1_rtype}, {ldq_16_bits_uop_lrs1_rtype}, {ldq_15_bits_uop_lrs1_rtype}, {ldq_14_bits_uop_lrs1_rtype}, {ldq_13_bits_uop_lrs1_rtype}, {ldq_12_bits_uop_lrs1_rtype}, {ldq_11_bits_uop_lrs1_rtype}, {ldq_10_bits_uop_lrs1_rtype}, {ldq_9_bits_uop_lrs1_rtype}, {ldq_8_bits_uop_lrs1_rtype}, {ldq_7_bits_uop_lrs1_rtype}, {ldq_6_bits_uop_lrs1_rtype}, {ldq_5_bits_uop_lrs1_rtype}, {ldq_4_bits_uop_lrs1_rtype}, {ldq_3_bits_uop_lrs1_rtype}, {ldq_2_bits_uop_lrs1_rtype}, {ldq_1_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_167 = {{ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_23_bits_uop_lrs2_rtype}, {ldq_22_bits_uop_lrs2_rtype}, {ldq_21_bits_uop_lrs2_rtype}, {ldq_20_bits_uop_lrs2_rtype}, {ldq_19_bits_uop_lrs2_rtype}, {ldq_18_bits_uop_lrs2_rtype}, {ldq_17_bits_uop_lrs2_rtype}, {ldq_16_bits_uop_lrs2_rtype}, {ldq_15_bits_uop_lrs2_rtype}, {ldq_14_bits_uop_lrs2_rtype}, {ldq_13_bits_uop_lrs2_rtype}, {ldq_12_bits_uop_lrs2_rtype}, {ldq_11_bits_uop_lrs2_rtype}, {ldq_10_bits_uop_lrs2_rtype}, {ldq_9_bits_uop_lrs2_rtype}, {ldq_8_bits_uop_lrs2_rtype}, {ldq_7_bits_uop_lrs2_rtype}, {ldq_6_bits_uop_lrs2_rtype}, {ldq_5_bits_uop_lrs2_rtype}, {ldq_4_bits_uop_lrs2_rtype}, {ldq_3_bits_uop_lrs2_rtype}, {ldq_2_bits_uop_lrs2_rtype}, {ldq_1_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_168 = {{ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_23_bits_uop_frs3_en}, {ldq_22_bits_uop_frs3_en}, {ldq_21_bits_uop_frs3_en}, {ldq_20_bits_uop_frs3_en}, {ldq_19_bits_uop_frs3_en}, {ldq_18_bits_uop_frs3_en}, {ldq_17_bits_uop_frs3_en}, {ldq_16_bits_uop_frs3_en}, {ldq_15_bits_uop_frs3_en}, {ldq_14_bits_uop_frs3_en}, {ldq_13_bits_uop_frs3_en}, {ldq_12_bits_uop_frs3_en}, {ldq_11_bits_uop_frs3_en}, {ldq_10_bits_uop_frs3_en}, {ldq_9_bits_uop_frs3_en}, {ldq_8_bits_uop_frs3_en}, {ldq_7_bits_uop_frs3_en}, {ldq_6_bits_uop_frs3_en}, {ldq_5_bits_uop_frs3_en}, {ldq_4_bits_uop_frs3_en}, {ldq_3_bits_uop_frs3_en}, {ldq_2_bits_uop_frs3_en}, {ldq_1_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_frs3_en = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_169 = {{ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_23_bits_uop_fp_val}, {ldq_22_bits_uop_fp_val}, {ldq_21_bits_uop_fp_val}, {ldq_20_bits_uop_fp_val}, {ldq_19_bits_uop_fp_val}, {ldq_18_bits_uop_fp_val}, {ldq_17_bits_uop_fp_val}, {ldq_16_bits_uop_fp_val}, {ldq_15_bits_uop_fp_val}, {ldq_14_bits_uop_fp_val}, {ldq_13_bits_uop_fp_val}, {ldq_12_bits_uop_fp_val}, {ldq_11_bits_uop_fp_val}, {ldq_10_bits_uop_fp_val}, {ldq_9_bits_uop_fp_val}, {ldq_8_bits_uop_fp_val}, {ldq_7_bits_uop_fp_val}, {ldq_6_bits_uop_fp_val}, {ldq_5_bits_uop_fp_val}, {ldq_4_bits_uop_fp_val}, {ldq_3_bits_uop_fp_val}, {ldq_2_bits_uop_fp_val}, {ldq_1_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_fp_val = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_170 = {{ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_23_bits_uop_fp_single}, {ldq_22_bits_uop_fp_single}, {ldq_21_bits_uop_fp_single}, {ldq_20_bits_uop_fp_single}, {ldq_19_bits_uop_fp_single}, {ldq_18_bits_uop_fp_single}, {ldq_17_bits_uop_fp_single}, {ldq_16_bits_uop_fp_single}, {ldq_15_bits_uop_fp_single}, {ldq_14_bits_uop_fp_single}, {ldq_13_bits_uop_fp_single}, {ldq_12_bits_uop_fp_single}, {ldq_11_bits_uop_fp_single}, {ldq_10_bits_uop_fp_single}, {ldq_9_bits_uop_fp_single}, {ldq_8_bits_uop_fp_single}, {ldq_7_bits_uop_fp_single}, {ldq_6_bits_uop_fp_single}, {ldq_5_bits_uop_fp_single}, {ldq_4_bits_uop_fp_single}, {ldq_3_bits_uop_fp_single}, {ldq_2_bits_uop_fp_single}, {ldq_1_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_fp_single = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_171 = {{ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_23_bits_uop_xcpt_pf_if}, {ldq_22_bits_uop_xcpt_pf_if}, {ldq_21_bits_uop_xcpt_pf_if}, {ldq_20_bits_uop_xcpt_pf_if}, {ldq_19_bits_uop_xcpt_pf_if}, {ldq_18_bits_uop_xcpt_pf_if}, {ldq_17_bits_uop_xcpt_pf_if}, {ldq_16_bits_uop_xcpt_pf_if}, {ldq_15_bits_uop_xcpt_pf_if}, {ldq_14_bits_uop_xcpt_pf_if}, {ldq_13_bits_uop_xcpt_pf_if}, {ldq_12_bits_uop_xcpt_pf_if}, {ldq_11_bits_uop_xcpt_pf_if}, {ldq_10_bits_uop_xcpt_pf_if}, {ldq_9_bits_uop_xcpt_pf_if}, {ldq_8_bits_uop_xcpt_pf_if}, {ldq_7_bits_uop_xcpt_pf_if}, {ldq_6_bits_uop_xcpt_pf_if}, {ldq_5_bits_uop_xcpt_pf_if}, {ldq_4_bits_uop_xcpt_pf_if}, {ldq_3_bits_uop_xcpt_pf_if}, {ldq_2_bits_uop_xcpt_pf_if}, {ldq_1_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_172 = {{ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_23_bits_uop_xcpt_ae_if}, {ldq_22_bits_uop_xcpt_ae_if}, {ldq_21_bits_uop_xcpt_ae_if}, {ldq_20_bits_uop_xcpt_ae_if}, {ldq_19_bits_uop_xcpt_ae_if}, {ldq_18_bits_uop_xcpt_ae_if}, {ldq_17_bits_uop_xcpt_ae_if}, {ldq_16_bits_uop_xcpt_ae_if}, {ldq_15_bits_uop_xcpt_ae_if}, {ldq_14_bits_uop_xcpt_ae_if}, {ldq_13_bits_uop_xcpt_ae_if}, {ldq_12_bits_uop_xcpt_ae_if}, {ldq_11_bits_uop_xcpt_ae_if}, {ldq_10_bits_uop_xcpt_ae_if}, {ldq_9_bits_uop_xcpt_ae_if}, {ldq_8_bits_uop_xcpt_ae_if}, {ldq_7_bits_uop_xcpt_ae_if}, {ldq_6_bits_uop_xcpt_ae_if}, {ldq_5_bits_uop_xcpt_ae_if}, {ldq_4_bits_uop_xcpt_ae_if}, {ldq_3_bits_uop_xcpt_ae_if}, {ldq_2_bits_uop_xcpt_ae_if}, {ldq_1_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_173 = {{ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_23_bits_uop_xcpt_ma_if}, {ldq_22_bits_uop_xcpt_ma_if}, {ldq_21_bits_uop_xcpt_ma_if}, {ldq_20_bits_uop_xcpt_ma_if}, {ldq_19_bits_uop_xcpt_ma_if}, {ldq_18_bits_uop_xcpt_ma_if}, {ldq_17_bits_uop_xcpt_ma_if}, {ldq_16_bits_uop_xcpt_ma_if}, {ldq_15_bits_uop_xcpt_ma_if}, {ldq_14_bits_uop_xcpt_ma_if}, {ldq_13_bits_uop_xcpt_ma_if}, {ldq_12_bits_uop_xcpt_ma_if}, {ldq_11_bits_uop_xcpt_ma_if}, {ldq_10_bits_uop_xcpt_ma_if}, {ldq_9_bits_uop_xcpt_ma_if}, {ldq_8_bits_uop_xcpt_ma_if}, {ldq_7_bits_uop_xcpt_ma_if}, {ldq_6_bits_uop_xcpt_ma_if}, {ldq_5_bits_uop_xcpt_ma_if}, {ldq_4_bits_uop_xcpt_ma_if}, {ldq_3_bits_uop_xcpt_ma_if}, {ldq_2_bits_uop_xcpt_ma_if}, {ldq_1_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_174 = {{ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_23_bits_uop_bp_debug_if}, {ldq_22_bits_uop_bp_debug_if}, {ldq_21_bits_uop_bp_debug_if}, {ldq_20_bits_uop_bp_debug_if}, {ldq_19_bits_uop_bp_debug_if}, {ldq_18_bits_uop_bp_debug_if}, {ldq_17_bits_uop_bp_debug_if}, {ldq_16_bits_uop_bp_debug_if}, {ldq_15_bits_uop_bp_debug_if}, {ldq_14_bits_uop_bp_debug_if}, {ldq_13_bits_uop_bp_debug_if}, {ldq_12_bits_uop_bp_debug_if}, {ldq_11_bits_uop_bp_debug_if}, {ldq_10_bits_uop_bp_debug_if}, {ldq_9_bits_uop_bp_debug_if}, {ldq_8_bits_uop_bp_debug_if}, {ldq_7_bits_uop_bp_debug_if}, {ldq_6_bits_uop_bp_debug_if}, {ldq_5_bits_uop_bp_debug_if}, {ldq_4_bits_uop_bp_debug_if}, {ldq_3_bits_uop_bp_debug_if}, {ldq_2_bits_uop_bp_debug_if}, {ldq_1_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_bp_debug_if = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_175 = {{ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_23_bits_uop_bp_xcpt_if}, {ldq_22_bits_uop_bp_xcpt_if}, {ldq_21_bits_uop_bp_xcpt_if}, {ldq_20_bits_uop_bp_xcpt_if}, {ldq_19_bits_uop_bp_xcpt_if}, {ldq_18_bits_uop_bp_xcpt_if}, {ldq_17_bits_uop_bp_xcpt_if}, {ldq_16_bits_uop_bp_xcpt_if}, {ldq_15_bits_uop_bp_xcpt_if}, {ldq_14_bits_uop_bp_xcpt_if}, {ldq_13_bits_uop_bp_xcpt_if}, {ldq_12_bits_uop_bp_xcpt_if}, {ldq_11_bits_uop_bp_xcpt_if}, {ldq_10_bits_uop_bp_xcpt_if}, {ldq_9_bits_uop_bp_xcpt_if}, {ldq_8_bits_uop_bp_xcpt_if}, {ldq_7_bits_uop_bp_xcpt_if}, {ldq_6_bits_uop_bp_xcpt_if}, {ldq_5_bits_uop_bp_xcpt_if}, {ldq_4_bits_uop_bp_xcpt_if}, {ldq_3_bits_uop_bp_xcpt_if}, {ldq_2_bits_uop_bp_xcpt_if}, {ldq_1_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_176 = {{ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_23_bits_uop_debug_fsrc}, {ldq_22_bits_uop_debug_fsrc}, {ldq_21_bits_uop_debug_fsrc}, {ldq_20_bits_uop_debug_fsrc}, {ldq_19_bits_uop_debug_fsrc}, {ldq_18_bits_uop_debug_fsrc}, {ldq_17_bits_uop_debug_fsrc}, {ldq_16_bits_uop_debug_fsrc}, {ldq_15_bits_uop_debug_fsrc}, {ldq_14_bits_uop_debug_fsrc}, {ldq_13_bits_uop_debug_fsrc}, {ldq_12_bits_uop_debug_fsrc}, {ldq_11_bits_uop_debug_fsrc}, {ldq_10_bits_uop_debug_fsrc}, {ldq_9_bits_uop_debug_fsrc}, {ldq_8_bits_uop_debug_fsrc}, {ldq_7_bits_uop_debug_fsrc}, {ldq_6_bits_uop_debug_fsrc}, {ldq_5_bits_uop_debug_fsrc}, {ldq_4_bits_uop_debug_fsrc}, {ldq_3_bits_uop_debug_fsrc}, {ldq_2_bits_uop_debug_fsrc}, {ldq_1_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_debug_fsrc = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][1:0] _GEN_177 = {{ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_23_bits_uop_debug_tsrc}, {ldq_22_bits_uop_debug_tsrc}, {ldq_21_bits_uop_debug_tsrc}, {ldq_20_bits_uop_debug_tsrc}, {ldq_19_bits_uop_debug_tsrc}, {ldq_18_bits_uop_debug_tsrc}, {ldq_17_bits_uop_debug_tsrc}, {ldq_16_bits_uop_debug_tsrc}, {ldq_15_bits_uop_debug_tsrc}, {ldq_14_bits_uop_debug_tsrc}, {ldq_13_bits_uop_debug_tsrc}, {ldq_12_bits_uop_debug_tsrc}, {ldq_11_bits_uop_debug_tsrc}, {ldq_10_bits_uop_debug_tsrc}, {ldq_9_bits_uop_debug_tsrc}, {ldq_8_bits_uop_debug_tsrc}, {ldq_7_bits_uop_debug_tsrc}, {ldq_6_bits_uop_debug_tsrc}, {ldq_5_bits_uop_debug_tsrc}, {ldq_4_bits_uop_debug_tsrc}, {ldq_3_bits_uop_debug_tsrc}, {ldq_2_bits_uop_debug_tsrc}, {ldq_1_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_uop_debug_tsrc = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_178 = {{ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_23_bits_addr_valid}, {ldq_22_bits_addr_valid}, {ldq_21_bits_addr_valid}, {ldq_20_bits_addr_valid}, {ldq_19_bits_addr_valid}, {ldq_18_bits_addr_valid}, {ldq_17_bits_addr_valid}, {ldq_16_bits_addr_valid}, {ldq_15_bits_addr_valid}, {ldq_14_bits_addr_valid}, {ldq_13_bits_addr_valid}, {ldq_12_bits_addr_valid}, {ldq_11_bits_addr_valid}, {ldq_10_bits_addr_valid}, {ldq_9_bits_addr_valid}, {ldq_8_bits_addr_valid}, {ldq_7_bits_addr_valid}, {ldq_6_bits_addr_valid}, {ldq_5_bits_addr_valid}, {ldq_4_bits_addr_valid}, {ldq_3_bits_addr_valid}, {ldq_2_bits_addr_valid}, {ldq_1_bits_addr_valid}, {ldq_0_bits_addr_valid}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_addr_valid = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][39:0] _GEN_179 = {{ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_23_bits_addr_bits}, {ldq_22_bits_addr_bits}, {ldq_21_bits_addr_bits}, {ldq_20_bits_addr_bits}, {ldq_19_bits_addr_bits}, {ldq_18_bits_addr_bits}, {ldq_17_bits_addr_bits}, {ldq_16_bits_addr_bits}, {ldq_15_bits_addr_bits}, {ldq_14_bits_addr_bits}, {ldq_13_bits_addr_bits}, {ldq_12_bits_addr_bits}, {ldq_11_bits_addr_bits}, {ldq_10_bits_addr_bits}, {ldq_9_bits_addr_bits}, {ldq_8_bits_addr_bits}, {ldq_7_bits_addr_bits}, {ldq_6_bits_addr_bits}, {ldq_5_bits_addr_bits}, {ldq_4_bits_addr_bits}, {ldq_3_bits_addr_bits}, {ldq_2_bits_addr_bits}, {ldq_1_bits_addr_bits}, {ldq_0_bits_addr_bits}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_addr_bits = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_180 = {{ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_23_bits_addr_is_virtual}, {ldq_22_bits_addr_is_virtual}, {ldq_21_bits_addr_is_virtual}, {ldq_20_bits_addr_is_virtual}, {ldq_19_bits_addr_is_virtual}, {ldq_18_bits_addr_is_virtual}, {ldq_17_bits_addr_is_virtual}, {ldq_16_bits_addr_is_virtual}, {ldq_15_bits_addr_is_virtual}, {ldq_14_bits_addr_is_virtual}, {ldq_13_bits_addr_is_virtual}, {ldq_12_bits_addr_is_virtual}, {ldq_11_bits_addr_is_virtual}, {ldq_10_bits_addr_is_virtual}, {ldq_9_bits_addr_is_virtual}, {ldq_8_bits_addr_is_virtual}, {ldq_7_bits_addr_is_virtual}, {ldq_6_bits_addr_is_virtual}, {ldq_5_bits_addr_is_virtual}, {ldq_4_bits_addr_is_virtual}, {ldq_3_bits_addr_is_virtual}, {ldq_2_bits_addr_is_virtual}, {ldq_1_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_addr_is_virtual = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_181 = {{ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_23_bits_addr_is_uncacheable}, {ldq_22_bits_addr_is_uncacheable}, {ldq_21_bits_addr_is_uncacheable}, {ldq_20_bits_addr_is_uncacheable}, {ldq_19_bits_addr_is_uncacheable}, {ldq_18_bits_addr_is_uncacheable}, {ldq_17_bits_addr_is_uncacheable}, {ldq_16_bits_addr_is_uncacheable}, {ldq_15_bits_addr_is_uncacheable}, {ldq_14_bits_addr_is_uncacheable}, {ldq_13_bits_addr_is_uncacheable}, {ldq_12_bits_addr_is_uncacheable}, {ldq_11_bits_addr_is_uncacheable}, {ldq_10_bits_addr_is_uncacheable}, {ldq_9_bits_addr_is_uncacheable}, {ldq_8_bits_addr_is_uncacheable}, {ldq_7_bits_addr_is_uncacheable}, {ldq_6_bits_addr_is_uncacheable}, {ldq_5_bits_addr_is_uncacheable}, {ldq_4_bits_addr_is_uncacheable}, {ldq_3_bits_addr_is_uncacheable}, {ldq_2_bits_addr_is_uncacheable}, {ldq_1_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_addr_is_uncacheable = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_182 = {{ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_23_bits_executed}, {ldq_22_bits_executed}, {ldq_21_bits_executed}, {ldq_20_bits_executed}, {ldq_19_bits_executed}, {ldq_18_bits_executed}, {ldq_17_bits_executed}, {ldq_16_bits_executed}, {ldq_15_bits_executed}, {ldq_14_bits_executed}, {ldq_13_bits_executed}, {ldq_12_bits_executed}, {ldq_11_bits_executed}, {ldq_10_bits_executed}, {ldq_9_bits_executed}, {ldq_8_bits_executed}, {ldq_7_bits_executed}, {ldq_6_bits_executed}, {ldq_5_bits_executed}, {ldq_4_bits_executed}, {ldq_3_bits_executed}, {ldq_2_bits_executed}, {ldq_1_bits_executed}, {ldq_0_bits_executed}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_executed = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_183 = {{ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_23_bits_succeeded}, {ldq_22_bits_succeeded}, {ldq_21_bits_succeeded}, {ldq_20_bits_succeeded}, {ldq_19_bits_succeeded}, {ldq_18_bits_succeeded}, {ldq_17_bits_succeeded}, {ldq_16_bits_succeeded}, {ldq_15_bits_succeeded}, {ldq_14_bits_succeeded}, {ldq_13_bits_succeeded}, {ldq_12_bits_succeeded}, {ldq_11_bits_succeeded}, {ldq_10_bits_succeeded}, {ldq_9_bits_succeeded}, {ldq_8_bits_succeeded}, {ldq_7_bits_succeeded}, {ldq_6_bits_succeeded}, {ldq_5_bits_succeeded}, {ldq_4_bits_succeeded}, {ldq_3_bits_succeeded}, {ldq_2_bits_succeeded}, {ldq_1_bits_succeeded}, {ldq_0_bits_succeeded}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_succeeded = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_184 = {{ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_23_bits_order_fail}, {ldq_22_bits_order_fail}, {ldq_21_bits_order_fail}, {ldq_20_bits_order_fail}, {ldq_19_bits_order_fail}, {ldq_18_bits_order_fail}, {ldq_17_bits_order_fail}, {ldq_16_bits_order_fail}, {ldq_15_bits_order_fail}, {ldq_14_bits_order_fail}, {ldq_13_bits_order_fail}, {ldq_12_bits_order_fail}, {ldq_11_bits_order_fail}, {ldq_10_bits_order_fail}, {ldq_9_bits_order_fail}, {ldq_8_bits_order_fail}, {ldq_7_bits_order_fail}, {ldq_6_bits_order_fail}, {ldq_5_bits_order_fail}, {ldq_4_bits_order_fail}, {ldq_3_bits_order_fail}, {ldq_2_bits_order_fail}, {ldq_1_bits_order_fail}, {ldq_0_bits_order_fail}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_order_fail = _GEN_184[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_185 = {{ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_23_bits_observed}, {ldq_22_bits_observed}, {ldq_21_bits_observed}, {ldq_20_bits_observed}, {ldq_19_bits_observed}, {ldq_18_bits_observed}, {ldq_17_bits_observed}, {ldq_16_bits_observed}, {ldq_15_bits_observed}, {ldq_14_bits_observed}, {ldq_13_bits_observed}, {ldq_12_bits_observed}, {ldq_11_bits_observed}, {ldq_10_bits_observed}, {ldq_9_bits_observed}, {ldq_8_bits_observed}, {ldq_7_bits_observed}, {ldq_6_bits_observed}, {ldq_5_bits_observed}, {ldq_4_bits_observed}, {ldq_3_bits_observed}, {ldq_2_bits_observed}, {ldq_1_bits_observed}, {ldq_0_bits_observed}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_observed = _GEN_185[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][23:0] _GEN_186 = {{ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_23_bits_st_dep_mask}, {ldq_22_bits_st_dep_mask}, {ldq_21_bits_st_dep_mask}, {ldq_20_bits_st_dep_mask}, {ldq_19_bits_st_dep_mask}, {ldq_18_bits_st_dep_mask}, {ldq_17_bits_st_dep_mask}, {ldq_16_bits_st_dep_mask}, {ldq_15_bits_st_dep_mask}, {ldq_14_bits_st_dep_mask}, {ldq_13_bits_st_dep_mask}, {ldq_12_bits_st_dep_mask}, {ldq_11_bits_st_dep_mask}, {ldq_10_bits_st_dep_mask}, {ldq_9_bits_st_dep_mask}, {ldq_8_bits_st_dep_mask}, {ldq_7_bits_st_dep_mask}, {ldq_6_bits_st_dep_mask}, {ldq_5_bits_st_dep_mask}, {ldq_4_bits_st_dep_mask}, {ldq_3_bits_st_dep_mask}, {ldq_2_bits_st_dep_mask}, {ldq_1_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_st_dep_mask = _GEN_186[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][4:0] _GEN_187 = {{ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_23_bits_youngest_stq_idx}, {ldq_22_bits_youngest_stq_idx}, {ldq_21_bits_youngest_stq_idx}, {ldq_20_bits_youngest_stq_idx}, {ldq_19_bits_youngest_stq_idx}, {ldq_18_bits_youngest_stq_idx}, {ldq_17_bits_youngest_stq_idx}, {ldq_16_bits_youngest_stq_idx}, {ldq_15_bits_youngest_stq_idx}, {ldq_14_bits_youngest_stq_idx}, {ldq_13_bits_youngest_stq_idx}, {ldq_12_bits_youngest_stq_idx}, {ldq_11_bits_youngest_stq_idx}, {ldq_10_bits_youngest_stq_idx}, {ldq_9_bits_youngest_stq_idx}, {ldq_8_bits_youngest_stq_idx}, {ldq_7_bits_youngest_stq_idx}, {ldq_6_bits_youngest_stq_idx}, {ldq_5_bits_youngest_stq_idx}, {ldq_4_bits_youngest_stq_idx}, {ldq_3_bits_youngest_stq_idx}, {ldq_2_bits_youngest_stq_idx}, {ldq_1_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_youngest_stq_idx = _GEN_187[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0] _GEN_188 = {{ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_23_bits_forward_std_val}, {ldq_22_bits_forward_std_val}, {ldq_21_bits_forward_std_val}, {ldq_20_bits_forward_std_val}, {ldq_19_bits_forward_std_val}, {ldq_18_bits_forward_std_val}, {ldq_17_bits_forward_std_val}, {ldq_16_bits_forward_std_val}, {ldq_15_bits_forward_std_val}, {ldq_14_bits_forward_std_val}, {ldq_13_bits_forward_std_val}, {ldq_12_bits_forward_std_val}, {ldq_11_bits_forward_std_val}, {ldq_10_bits_forward_std_val}, {ldq_9_bits_forward_std_val}, {ldq_8_bits_forward_std_val}, {ldq_7_bits_forward_std_val}, {ldq_6_bits_forward_std_val}, {ldq_5_bits_forward_std_val}, {ldq_4_bits_forward_std_val}, {ldq_3_bits_forward_std_val}, {ldq_2_bits_forward_std_val}, {ldq_1_bits_forward_std_val}, {ldq_0_bits_forward_std_val}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_forward_std_val = _GEN_188[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][4:0] _GEN_189 = {{ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_23_bits_forward_stq_idx}, {ldq_22_bits_forward_stq_idx}, {ldq_21_bits_forward_stq_idx}, {ldq_20_bits_forward_stq_idx}, {ldq_19_bits_forward_stq_idx}, {ldq_18_bits_forward_stq_idx}, {ldq_17_bits_forward_stq_idx}, {ldq_16_bits_forward_stq_idx}, {ldq_15_bits_forward_stq_idx}, {ldq_14_bits_forward_stq_idx}, {ldq_13_bits_forward_stq_idx}, {ldq_12_bits_forward_stq_idx}, {ldq_11_bits_forward_stq_idx}, {ldq_10_bits_forward_stq_idx}, {ldq_9_bits_forward_stq_idx}, {ldq_8_bits_forward_stq_idx}, {ldq_7_bits_forward_stq_idx}, {ldq_6_bits_forward_stq_idx}, {ldq_5_bits_forward_stq_idx}, {ldq_4_bits_forward_stq_idx}, {ldq_3_bits_forward_stq_idx}, {ldq_2_bits_forward_stq_idx}, {ldq_1_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_forward_stq_idx = _GEN_189[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][63:0] _GEN_190 = {{ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_23_bits_debug_wb_data}, {ldq_22_bits_debug_wb_data}, {ldq_21_bits_debug_wb_data}, {ldq_20_bits_debug_wb_data}, {ldq_19_bits_debug_wb_data}, {ldq_18_bits_debug_wb_data}, {ldq_17_bits_debug_wb_data}, {ldq_16_bits_debug_wb_data}, {ldq_15_bits_debug_wb_data}, {ldq_14_bits_debug_wb_data}, {ldq_13_bits_debug_wb_data}, {ldq_12_bits_debug_wb_data}, {ldq_11_bits_debug_wb_data}, {ldq_10_bits_debug_wb_data}, {ldq_9_bits_debug_wb_data}, {ldq_8_bits_debug_wb_data}, {ldq_7_bits_debug_wb_data}, {ldq_6_bits_debug_wb_data}, {ldq_5_bits_debug_wb_data}, {ldq_4_bits_debug_wb_data}, {ldq_3_bits_debug_wb_data}, {ldq_2_bits_debug_wb_data}, {ldq_1_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}}; // @[lsu.scala:208:16, :263:49]
assign ldq_incoming_e_0_bits_debug_wb_data = _GEN_190[ldq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [6:0] mem_stq_incoming_e_out_bits_uop_uopc = stq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23]
wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23]
wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23]
wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23]
wire [2:0] mem_stq_incoming_e_out_bits_uop_iq_type = stq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23]
wire [9:0] mem_stq_incoming_e_out_bits_uop_fu_code = stq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23]
wire [3:0] mem_stq_incoming_e_out_bits_uop_ctrl_br_type = stq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel = stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23]
wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel = stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23]
wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel = stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23]
wire [4:0] mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn = stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw = stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23]
wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd = stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_ctrl_is_load = stq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_ctrl_is_sta = stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_ctrl_is_std = stq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_state = stq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned = stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned = stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_br = stq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_jalr = stq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_jal = stq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23]
wire [3:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23]
wire [4:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23]
wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23]
wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23]
wire [11:0] mem_stq_incoming_e_out_bits_uop_csr_addr = stq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23]
wire [6:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23]
wire [4:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23]
wire [4:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23]
wire [6:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23]
wire [6:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23]
wire [6:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23]
wire [6:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23]
wire [4:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23]
wire [6:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23]
wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_bypassable = stq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23]
wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23]
wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23]
wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23]
wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23]
wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_ldst_val = stq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_fp_single = stq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23]
wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23]
wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:106:23]
wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:106:23]
wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:106:23]
wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23]
wire [15:0] stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49]
wire stq_incoming_e_0_valid; // @[lsu.scala:263:49]
assign stq_incoming_e_0_valid = _GEN[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_uopc = _GEN_1[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_inst = _GEN_2[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_debug_inst = _GEN_3[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_rvc = _GEN_4[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_debug_pc = _GEN_5[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_iq_type = _GEN_6[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_fu_code = _GEN_7[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_8[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_9[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_10[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_11[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_12[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_13[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_14[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_15[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_16[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_17[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_iw_state = _GEN_18[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_19[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_20[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_br = _GEN_21[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_jalr = _GEN_22[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_jal = _GEN_23[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_sfb = _GEN_24[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_br_mask = _GEN_25[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_br_tag = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ftq_idx = _GEN_27[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_edge_inst = _GEN_28[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_pc_lob = _GEN_29[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_taken = _GEN_30[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_imm_packed = _GEN_31[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_csr_addr = _GEN_32[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_rob_idx = _GEN_33[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ldq_idx = _GEN_34[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_stq_idx = _GEN_35[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_rxq_idx = _GEN_36[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_pdst = _GEN_37[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_prs1 = _GEN_38[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_prs2 = _GEN_39[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_prs3 = _GEN_40[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ppred = _GEN_41[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_prs1_busy = _GEN_42[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_prs2_busy = _GEN_43[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_prs3_busy = _GEN_44[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ppred_busy = _GEN_45[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_stale_pdst = _GEN_46[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_exception = _GEN_47[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_exc_cause = _GEN_49[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_bypassable = _GEN_50[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_mem_cmd = _GEN_51[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_mem_size = _GEN_52[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_mem_signed = _GEN_53[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_fence = _GEN_54[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_fencei = _GEN_56[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_amo = _GEN_57[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_uses_ldq = _GEN_59[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_uses_stq = _GEN_60[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_61[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_is_unique = _GEN_62[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_flush_on_commit = _GEN_63[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_64[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ldst = _GEN_65[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_lrs1 = _GEN_66[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_lrs2 = _GEN_67[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_lrs3 = _GEN_68[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_ldst_val = _GEN_69[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_dst_rtype = _GEN_70[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_71[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_72[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_frs3_en = _GEN_73[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_fp_val = _GEN_74[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_fp_single = _GEN_75[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_76[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_77[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_78[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_bp_debug_if = _GEN_79[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_80[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_debug_fsrc = _GEN_81[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_uop_debug_tsrc = _GEN_82[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_addr_valid = _GEN_83[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_addr_bits = _GEN_84[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_addr_is_virtual = _GEN_85[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_data_valid = _GEN_86[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_data_bits = _GEN_87[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
assign stq_incoming_e_0_bits_committed = _GEN_89[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49]
wire [31:0] _GEN_191 = {{stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_23_bits_succeeded}, {stq_22_bits_succeeded}, {stq_21_bits_succeeded}, {stq_20_bits_succeeded}, {stq_19_bits_succeeded}, {stq_18_bits_succeeded}, {stq_17_bits_succeeded}, {stq_16_bits_succeeded}, {stq_15_bits_succeeded}, {stq_14_bits_succeeded}, {stq_13_bits_succeeded}, {stq_12_bits_succeeded}, {stq_11_bits_succeeded}, {stq_10_bits_succeeded}, {stq_9_bits_succeeded}, {stq_8_bits_succeeded}, {stq_7_bits_succeeded}, {stq_6_bits_succeeded}, {stq_5_bits_succeeded}, {stq_4_bits_succeeded}, {stq_3_bits_succeeded}, {stq_2_bits_succeeded}, {stq_1_bits_succeeded}, {stq_0_bits_succeeded}}; // @[lsu.scala:209:16, :263:49]
assign stq_incoming_e_0_bits_succeeded = _GEN_191[stq_incoming_idx_0]; // @[lsu.scala:263:49]
wire [31:0][63:0] _GEN_192 = {{stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_23_bits_debug_wb_data}, {stq_22_bits_debug_wb_data}, {stq_21_bits_debug_wb_data}, {stq_20_bits_debug_wb_data}, {stq_19_bits_debug_wb_data}, {stq_18_bits_debug_wb_data}, {stq_17_bits_debug_wb_data}, {stq_16_bits_debug_wb_data}, {stq_15_bits_debug_wb_data}, {stq_14_bits_debug_wb_data}, {stq_13_bits_debug_wb_data}, {stq_12_bits_debug_wb_data}, {stq_11_bits_debug_wb_data}, {stq_10_bits_debug_wb_data}, {stq_9_bits_debug_wb_data}, {stq_8_bits_debug_wb_data}, {stq_7_bits_debug_wb_data}, {stq_6_bits_debug_wb_data}, {stq_5_bits_debug_wb_data}, {stq_4_bits_debug_wb_data}, {stq_3_bits_debug_wb_data}, {stq_2_bits_debug_wb_data}, {stq_1_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}}; // @[lsu.scala:209:16, :263:49]
assign stq_incoming_e_0_bits_debug_wb_data = _GEN_192[stq_incoming_idx_0]; // @[lsu.scala:263:49]
wire _GEN_193 = block_load_mask_0 | p1_block_load_mask_0; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block; // @[lsu.scala:416:36]
assign ldq_retry_idx_block = _GEN_193; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block = _GEN_193; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T = ldq_0_bits_addr_valid & ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_1 = ~ldq_retry_idx_block; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_2 = _ldq_retry_idx_T & _ldq_retry_idx_T_1; // @[lsu.scala:417:{18,39,42}]
wire _GEN_194 = block_load_mask_1 | p1_block_load_mask_1; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_1; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_1 = _GEN_194; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_1; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_1 = _GEN_194; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_3 = ldq_1_bits_addr_valid & ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_4 = ~ldq_retry_idx_block_1; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_5 = _ldq_retry_idx_T_3 & _ldq_retry_idx_T_4; // @[lsu.scala:417:{18,39,42}]
wire _GEN_195 = block_load_mask_2 | p1_block_load_mask_2; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_2; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_2 = _GEN_195; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_2; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_2 = _GEN_195; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_6 = ldq_2_bits_addr_valid & ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_7 = ~ldq_retry_idx_block_2; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_8 = _ldq_retry_idx_T_6 & _ldq_retry_idx_T_7; // @[lsu.scala:417:{18,39,42}]
wire _GEN_196 = block_load_mask_3 | p1_block_load_mask_3; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_3; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_3 = _GEN_196; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_3; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_3 = _GEN_196; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_9 = ldq_3_bits_addr_valid & ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_10 = ~ldq_retry_idx_block_3; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_11 = _ldq_retry_idx_T_9 & _ldq_retry_idx_T_10; // @[lsu.scala:417:{18,39,42}]
wire _GEN_197 = block_load_mask_4 | p1_block_load_mask_4; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_4; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_4 = _GEN_197; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_4; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_4 = _GEN_197; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_12 = ldq_4_bits_addr_valid & ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_13 = ~ldq_retry_idx_block_4; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_14 = _ldq_retry_idx_T_12 & _ldq_retry_idx_T_13; // @[lsu.scala:417:{18,39,42}]
wire _GEN_198 = block_load_mask_5 | p1_block_load_mask_5; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_5; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_5 = _GEN_198; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_5; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_5 = _GEN_198; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_15 = ldq_5_bits_addr_valid & ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_16 = ~ldq_retry_idx_block_5; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_17 = _ldq_retry_idx_T_15 & _ldq_retry_idx_T_16; // @[lsu.scala:417:{18,39,42}]
wire _GEN_199 = block_load_mask_6 | p1_block_load_mask_6; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_6; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_6 = _GEN_199; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_6; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_6 = _GEN_199; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_18 = ldq_6_bits_addr_valid & ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_19 = ~ldq_retry_idx_block_6; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_20 = _ldq_retry_idx_T_18 & _ldq_retry_idx_T_19; // @[lsu.scala:417:{18,39,42}]
wire _GEN_200 = block_load_mask_7 | p1_block_load_mask_7; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_7; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_7 = _GEN_200; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_7; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_7 = _GEN_200; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_21 = ldq_7_bits_addr_valid & ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_22 = ~ldq_retry_idx_block_7; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_23 = _ldq_retry_idx_T_21 & _ldq_retry_idx_T_22; // @[lsu.scala:417:{18,39,42}]
wire _GEN_201 = block_load_mask_8 | p1_block_load_mask_8; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_8; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_8 = _GEN_201; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_8; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_8 = _GEN_201; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_24 = ldq_8_bits_addr_valid & ldq_8_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_25 = ~ldq_retry_idx_block_8; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_26 = _ldq_retry_idx_T_24 & _ldq_retry_idx_T_25; // @[lsu.scala:417:{18,39,42}]
wire _GEN_202 = block_load_mask_9 | p1_block_load_mask_9; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_9; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_9 = _GEN_202; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_9; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_9 = _GEN_202; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_27 = ldq_9_bits_addr_valid & ldq_9_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_28 = ~ldq_retry_idx_block_9; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_29 = _ldq_retry_idx_T_27 & _ldq_retry_idx_T_28; // @[lsu.scala:417:{18,39,42}]
wire _GEN_203 = block_load_mask_10 | p1_block_load_mask_10; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_10; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_10 = _GEN_203; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_10; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_10 = _GEN_203; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_30 = ldq_10_bits_addr_valid & ldq_10_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_31 = ~ldq_retry_idx_block_10; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_32 = _ldq_retry_idx_T_30 & _ldq_retry_idx_T_31; // @[lsu.scala:417:{18,39,42}]
wire _GEN_204 = block_load_mask_11 | p1_block_load_mask_11; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_11; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_11 = _GEN_204; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_11; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_11 = _GEN_204; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_33 = ldq_11_bits_addr_valid & ldq_11_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_34 = ~ldq_retry_idx_block_11; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_35 = _ldq_retry_idx_T_33 & _ldq_retry_idx_T_34; // @[lsu.scala:417:{18,39,42}]
wire _GEN_205 = block_load_mask_12 | p1_block_load_mask_12; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_12; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_12 = _GEN_205; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_12; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_12 = _GEN_205; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_36 = ldq_12_bits_addr_valid & ldq_12_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_37 = ~ldq_retry_idx_block_12; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_38 = _ldq_retry_idx_T_36 & _ldq_retry_idx_T_37; // @[lsu.scala:417:{18,39,42}]
wire _GEN_206 = block_load_mask_13 | p1_block_load_mask_13; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_13; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_13 = _GEN_206; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_13; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_13 = _GEN_206; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_39 = ldq_13_bits_addr_valid & ldq_13_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_40 = ~ldq_retry_idx_block_13; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_41 = _ldq_retry_idx_T_39 & _ldq_retry_idx_T_40; // @[lsu.scala:417:{18,39,42}]
wire _GEN_207 = block_load_mask_14 | p1_block_load_mask_14; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_14; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_14 = _GEN_207; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_14; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_14 = _GEN_207; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_42 = ldq_14_bits_addr_valid & ldq_14_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_43 = ~ldq_retry_idx_block_14; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_44 = _ldq_retry_idx_T_42 & _ldq_retry_idx_T_43; // @[lsu.scala:417:{18,39,42}]
wire _GEN_208 = block_load_mask_15 | p1_block_load_mask_15; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_15; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_15 = _GEN_208; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_15; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_15 = _GEN_208; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_45 = ldq_15_bits_addr_valid & ldq_15_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_46 = ~ldq_retry_idx_block_15; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_47 = _ldq_retry_idx_T_45 & _ldq_retry_idx_T_46; // @[lsu.scala:417:{18,39,42}]
wire _GEN_209 = block_load_mask_16 | p1_block_load_mask_16; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_16; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_16 = _GEN_209; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_16; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_16 = _GEN_209; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_48 = ldq_16_bits_addr_valid & ldq_16_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_49 = ~ldq_retry_idx_block_16; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_50 = _ldq_retry_idx_T_48 & _ldq_retry_idx_T_49; // @[lsu.scala:417:{18,39,42}]
wire _GEN_210 = block_load_mask_17 | p1_block_load_mask_17; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_17; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_17 = _GEN_210; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_17; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_17 = _GEN_210; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_51 = ldq_17_bits_addr_valid & ldq_17_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_52 = ~ldq_retry_idx_block_17; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_53 = _ldq_retry_idx_T_51 & _ldq_retry_idx_T_52; // @[lsu.scala:417:{18,39,42}]
wire _GEN_211 = block_load_mask_18 | p1_block_load_mask_18; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_18; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_18 = _GEN_211; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_18; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_18 = _GEN_211; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_54 = ldq_18_bits_addr_valid & ldq_18_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_55 = ~ldq_retry_idx_block_18; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_56 = _ldq_retry_idx_T_54 & _ldq_retry_idx_T_55; // @[lsu.scala:417:{18,39,42}]
wire _GEN_212 = block_load_mask_19 | p1_block_load_mask_19; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_19; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_19 = _GEN_212; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_19; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_19 = _GEN_212; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_57 = ldq_19_bits_addr_valid & ldq_19_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_58 = ~ldq_retry_idx_block_19; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_59 = _ldq_retry_idx_T_57 & _ldq_retry_idx_T_58; // @[lsu.scala:417:{18,39,42}]
wire _GEN_213 = block_load_mask_20 | p1_block_load_mask_20; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_20; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_20 = _GEN_213; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_20; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_20 = _GEN_213; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_60 = ldq_20_bits_addr_valid & ldq_20_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_61 = ~ldq_retry_idx_block_20; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_62 = _ldq_retry_idx_T_60 & _ldq_retry_idx_T_61; // @[lsu.scala:417:{18,39,42}]
wire _GEN_214 = block_load_mask_21 | p1_block_load_mask_21; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_21; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_21 = _GEN_214; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_21; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_21 = _GEN_214; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_63 = ldq_21_bits_addr_valid & ldq_21_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_64 = ~ldq_retry_idx_block_21; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_65 = _ldq_retry_idx_T_63 & _ldq_retry_idx_T_64; // @[lsu.scala:417:{18,39,42}]
wire _GEN_215 = block_load_mask_22 | p1_block_load_mask_22; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_22; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_22 = _GEN_215; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_22; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_22 = _GEN_215; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_66 = ldq_22_bits_addr_valid & ldq_22_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_67 = ~ldq_retry_idx_block_22; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_68 = _ldq_retry_idx_T_66 & _ldq_retry_idx_T_67; // @[lsu.scala:417:{18,39,42}]
wire _GEN_216 = block_load_mask_23 | p1_block_load_mask_23; // @[lsu.scala:396:36, :397:35, :416:36]
wire ldq_retry_idx_block_23; // @[lsu.scala:416:36]
assign ldq_retry_idx_block_23 = _GEN_216; // @[lsu.scala:416:36]
wire ldq_wakeup_idx_block_23; // @[lsu.scala:431:36]
assign ldq_wakeup_idx_block_23 = _GEN_216; // @[lsu.scala:416:36, :431:36]
wire _ldq_retry_idx_T_69 = ldq_23_bits_addr_valid & ldq_23_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18]
wire _ldq_retry_idx_T_70 = ~ldq_retry_idx_block_23; // @[lsu.scala:416:36, :417:42]
wire _ldq_retry_idx_T_71 = _ldq_retry_idx_T_69 & _ldq_retry_idx_T_70; // @[lsu.scala:417:{18,39,42}]
wire _GEN_217 = ldq_head == 5'h0; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T = _GEN_217; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T = _GEN_217; // @[util.scala:351:72]
wire _temp_bits_T; // @[lsu.scala:1230:28]
assign _temp_bits_T = _GEN_217; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_0 = _ldq_retry_idx_T_2 & _ldq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}]
wire _GEN_218 = ldq_head < 5'h2; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_1 = _GEN_218; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_218; // @[util.scala:351:72]
wire _temp_bits_T_2; // @[lsu.scala:1230:28]
assign _temp_bits_T_2 = _GEN_218; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_1 = _ldq_retry_idx_T_5 & _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}]
wire _GEN_219 = ldq_head < 5'h3; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_2 = _GEN_219; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_219; // @[util.scala:351:72]
wire _temp_bits_T_4; // @[lsu.scala:1230:28]
assign _temp_bits_T_4 = _GEN_219; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_2 = _ldq_retry_idx_T_8 & _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}]
wire _GEN_220 = ldq_head < 5'h4; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_3; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_3 = _GEN_220; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_3 = _GEN_220; // @[util.scala:351:72]
wire _temp_bits_T_6; // @[lsu.scala:1230:28]
assign _temp_bits_T_6 = _GEN_220; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_3 = _ldq_retry_idx_T_11 & _ldq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}]
wire _GEN_221 = ldq_head < 5'h5; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_4 = _GEN_221; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_221; // @[util.scala:351:72]
wire _temp_bits_T_8; // @[lsu.scala:1230:28]
assign _temp_bits_T_8 = _GEN_221; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_4 = _ldq_retry_idx_T_14 & _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}]
wire _GEN_222 = ldq_head < 5'h6; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_5 = _GEN_222; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_222; // @[util.scala:351:72]
wire _temp_bits_T_10; // @[lsu.scala:1230:28]
assign _temp_bits_T_10 = _GEN_222; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_5 = _ldq_retry_idx_T_17 & _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}]
wire _GEN_223 = ldq_head < 5'h7; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_6 = _GEN_223; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_223; // @[util.scala:351:72]
wire _temp_bits_T_12; // @[lsu.scala:1230:28]
assign _temp_bits_T_12 = _GEN_223; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_6 = _ldq_retry_idx_T_20 & _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}]
wire _GEN_224 = ldq_head < 5'h8; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_7; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_7 = _GEN_224; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_7 = _GEN_224; // @[util.scala:351:72]
wire _temp_bits_T_14; // @[lsu.scala:1230:28]
assign _temp_bits_T_14 = _GEN_224; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_7 = _ldq_retry_idx_T_23 & _ldq_retry_idx_temp_vec_T_7; // @[util.scala:351:{65,72}]
wire _GEN_225 = ldq_head < 5'h9; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_8; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_8 = _GEN_225; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_8 = _GEN_225; // @[util.scala:351:72]
wire _temp_bits_T_16; // @[lsu.scala:1230:28]
assign _temp_bits_T_16 = _GEN_225; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_8 = _ldq_retry_idx_T_26 & _ldq_retry_idx_temp_vec_T_8; // @[util.scala:351:{65,72}]
wire _GEN_226 = ldq_head < 5'hA; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_9; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_9 = _GEN_226; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_9 = _GEN_226; // @[util.scala:351:72]
wire _temp_bits_T_18; // @[lsu.scala:1230:28]
assign _temp_bits_T_18 = _GEN_226; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_9 = _ldq_retry_idx_T_29 & _ldq_retry_idx_temp_vec_T_9; // @[util.scala:351:{65,72}]
wire _GEN_227 = ldq_head < 5'hB; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_10; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_10 = _GEN_227; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_10 = _GEN_227; // @[util.scala:351:72]
wire _temp_bits_T_20; // @[lsu.scala:1230:28]
assign _temp_bits_T_20 = _GEN_227; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_10 = _ldq_retry_idx_T_32 & _ldq_retry_idx_temp_vec_T_10; // @[util.scala:351:{65,72}]
wire _GEN_228 = ldq_head < 5'hC; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_11; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_11 = _GEN_228; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_11 = _GEN_228; // @[util.scala:351:72]
wire _temp_bits_T_22; // @[lsu.scala:1230:28]
assign _temp_bits_T_22 = _GEN_228; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_11 = _ldq_retry_idx_T_35 & _ldq_retry_idx_temp_vec_T_11; // @[util.scala:351:{65,72}]
wire _GEN_229 = ldq_head < 5'hD; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_12; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_12 = _GEN_229; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_12 = _GEN_229; // @[util.scala:351:72]
wire _temp_bits_T_24; // @[lsu.scala:1230:28]
assign _temp_bits_T_24 = _GEN_229; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_12 = _ldq_retry_idx_T_38 & _ldq_retry_idx_temp_vec_T_12; // @[util.scala:351:{65,72}]
wire _GEN_230 = ldq_head < 5'hE; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_13; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_13 = _GEN_230; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_13 = _GEN_230; // @[util.scala:351:72]
wire _temp_bits_T_26; // @[lsu.scala:1230:28]
assign _temp_bits_T_26 = _GEN_230; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_13 = _ldq_retry_idx_T_41 & _ldq_retry_idx_temp_vec_T_13; // @[util.scala:351:{65,72}]
wire _GEN_231 = ldq_head < 5'hF; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_14; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_14 = _GEN_231; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_14 = _GEN_231; // @[util.scala:351:72]
wire _temp_bits_T_28; // @[lsu.scala:1230:28]
assign _temp_bits_T_28 = _GEN_231; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_14 = _ldq_retry_idx_T_44 & _ldq_retry_idx_temp_vec_T_14; // @[util.scala:351:{65,72}]
wire _searcher_is_older_T_63 = ldq_head[4]; // @[util.scala:351:72, :363:78]
wire _ldq_retry_idx_temp_vec_T_15 = ~_searcher_is_older_T_63; // @[util.scala:351:72, :363:78]
wire ldq_retry_idx_temp_vec_15 = _ldq_retry_idx_T_47 & _ldq_retry_idx_temp_vec_T_15; // @[util.scala:351:{65,72}]
wire _GEN_232 = ldq_head < 5'h11; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_16; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_16 = _GEN_232; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_16 = _GEN_232; // @[util.scala:351:72]
wire _temp_bits_T_32; // @[lsu.scala:1230:28]
assign _temp_bits_T_32 = _GEN_232; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_16 = _ldq_retry_idx_T_50 & _ldq_retry_idx_temp_vec_T_16; // @[util.scala:351:{65,72}]
wire _GEN_233 = ldq_head < 5'h12; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_17; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_17 = _GEN_233; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_17 = _GEN_233; // @[util.scala:351:72]
wire _temp_bits_T_34; // @[lsu.scala:1230:28]
assign _temp_bits_T_34 = _GEN_233; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_17 = _ldq_retry_idx_T_53 & _ldq_retry_idx_temp_vec_T_17; // @[util.scala:351:{65,72}]
wire _GEN_234 = ldq_head < 5'h13; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_18; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_18 = _GEN_234; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_18 = _GEN_234; // @[util.scala:351:72]
wire _temp_bits_T_36; // @[lsu.scala:1230:28]
assign _temp_bits_T_36 = _GEN_234; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_18 = _ldq_retry_idx_T_56 & _ldq_retry_idx_temp_vec_T_18; // @[util.scala:351:{65,72}]
wire _GEN_235 = ldq_head < 5'h14; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_19; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_19 = _GEN_235; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_19 = _GEN_235; // @[util.scala:351:72]
wire _temp_bits_T_38; // @[lsu.scala:1230:28]
assign _temp_bits_T_38 = _GEN_235; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_19 = _ldq_retry_idx_T_59 & _ldq_retry_idx_temp_vec_T_19; // @[util.scala:351:{65,72}]
wire _GEN_236 = ldq_head < 5'h15; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_20; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_20 = _GEN_236; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_20 = _GEN_236; // @[util.scala:351:72]
wire _temp_bits_T_40; // @[lsu.scala:1230:28]
assign _temp_bits_T_40 = _GEN_236; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_20 = _ldq_retry_idx_T_62 & _ldq_retry_idx_temp_vec_T_20; // @[util.scala:351:{65,72}]
wire _GEN_237 = ldq_head < 5'h16; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_21; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_21 = _GEN_237; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_21 = _GEN_237; // @[util.scala:351:72]
wire _temp_bits_T_42; // @[lsu.scala:1230:28]
assign _temp_bits_T_42 = _GEN_237; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_21 = _ldq_retry_idx_T_65 & _ldq_retry_idx_temp_vec_T_21; // @[util.scala:351:{65,72}]
wire _GEN_238 = ldq_head < 5'h17; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_22; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_22 = _GEN_238; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_22 = _GEN_238; // @[util.scala:351:72]
wire _temp_bits_T_44; // @[lsu.scala:1230:28]
assign _temp_bits_T_44 = _GEN_238; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_22 = _ldq_retry_idx_T_68 & _ldq_retry_idx_temp_vec_T_22; // @[util.scala:351:{65,72}]
wire _GEN_239 = ldq_head[4:3] != 2'h3; // @[util.scala:351:72]
wire _ldq_retry_idx_temp_vec_T_23; // @[util.scala:351:72]
assign _ldq_retry_idx_temp_vec_T_23 = _GEN_239; // @[util.scala:351:72]
wire _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:351:72]
assign _ldq_wakeup_idx_temp_vec_T_23 = _GEN_239; // @[util.scala:351:72]
wire _temp_bits_T_46; // @[lsu.scala:1230:28]
assign _temp_bits_T_46 = _GEN_239; // @[util.scala:351:72]
wire ldq_retry_idx_temp_vec_23 = _ldq_retry_idx_T_71 & _ldq_retry_idx_temp_vec_T_23; // @[util.scala:351:{65,72}]
wire [5:0] _ldq_retry_idx_idx_T = {5'h1B, ~_ldq_retry_idx_T_68}; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_1 = _ldq_retry_idx_T_65 ? 6'h35 : _ldq_retry_idx_idx_T; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_2 = _ldq_retry_idx_T_62 ? 6'h34 : _ldq_retry_idx_idx_T_1; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_3 = _ldq_retry_idx_T_59 ? 6'h33 : _ldq_retry_idx_idx_T_2; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_4 = _ldq_retry_idx_T_56 ? 6'h32 : _ldq_retry_idx_idx_T_3; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_5 = _ldq_retry_idx_T_53 ? 6'h31 : _ldq_retry_idx_idx_T_4; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_6 = _ldq_retry_idx_T_50 ? 6'h30 : _ldq_retry_idx_idx_T_5; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_7 = _ldq_retry_idx_T_47 ? 6'h2F : _ldq_retry_idx_idx_T_6; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_8 = _ldq_retry_idx_T_44 ? 6'h2E : _ldq_retry_idx_idx_T_7; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_9 = _ldq_retry_idx_T_41 ? 6'h2D : _ldq_retry_idx_idx_T_8; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_10 = _ldq_retry_idx_T_38 ? 6'h2C : _ldq_retry_idx_idx_T_9; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_11 = _ldq_retry_idx_T_35 ? 6'h2B : _ldq_retry_idx_idx_T_10; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_12 = _ldq_retry_idx_T_32 ? 6'h2A : _ldq_retry_idx_idx_T_11; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_13 = _ldq_retry_idx_T_29 ? 6'h29 : _ldq_retry_idx_idx_T_12; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_14 = _ldq_retry_idx_T_26 ? 6'h28 : _ldq_retry_idx_idx_T_13; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_15 = _ldq_retry_idx_T_23 ? 6'h27 : _ldq_retry_idx_idx_T_14; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_16 = _ldq_retry_idx_T_20 ? 6'h26 : _ldq_retry_idx_idx_T_15; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_17 = _ldq_retry_idx_T_17 ? 6'h25 : _ldq_retry_idx_idx_T_16; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_18 = _ldq_retry_idx_T_14 ? 6'h24 : _ldq_retry_idx_idx_T_17; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_19 = _ldq_retry_idx_T_11 ? 6'h23 : _ldq_retry_idx_idx_T_18; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_20 = _ldq_retry_idx_T_8 ? 6'h22 : _ldq_retry_idx_idx_T_19; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_21 = _ldq_retry_idx_T_5 ? 6'h21 : _ldq_retry_idx_idx_T_20; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_22 = _ldq_retry_idx_T_2 ? 6'h20 : _ldq_retry_idx_idx_T_21; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_23 = _ldq_retry_idx_idx_T_22; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_24 = _ldq_retry_idx_idx_T_23; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_25 = _ldq_retry_idx_idx_T_24; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_26 = _ldq_retry_idx_idx_T_25; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_27 = _ldq_retry_idx_idx_T_26; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_28 = _ldq_retry_idx_idx_T_27; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_29 = _ldq_retry_idx_idx_T_28; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_30 = _ldq_retry_idx_idx_T_29; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_31 = ldq_retry_idx_temp_vec_23 ? 6'h17 : _ldq_retry_idx_idx_T_30; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_32 = ldq_retry_idx_temp_vec_22 ? 6'h16 : _ldq_retry_idx_idx_T_31; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_33 = ldq_retry_idx_temp_vec_21 ? 6'h15 : _ldq_retry_idx_idx_T_32; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_34 = ldq_retry_idx_temp_vec_20 ? 6'h14 : _ldq_retry_idx_idx_T_33; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_35 = ldq_retry_idx_temp_vec_19 ? 6'h13 : _ldq_retry_idx_idx_T_34; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_36 = ldq_retry_idx_temp_vec_18 ? 6'h12 : _ldq_retry_idx_idx_T_35; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_37 = ldq_retry_idx_temp_vec_17 ? 6'h11 : _ldq_retry_idx_idx_T_36; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_38 = ldq_retry_idx_temp_vec_16 ? 6'h10 : _ldq_retry_idx_idx_T_37; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_39 = ldq_retry_idx_temp_vec_15 ? 6'hF : _ldq_retry_idx_idx_T_38; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_40 = ldq_retry_idx_temp_vec_14 ? 6'hE : _ldq_retry_idx_idx_T_39; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_41 = ldq_retry_idx_temp_vec_13 ? 6'hD : _ldq_retry_idx_idx_T_40; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_42 = ldq_retry_idx_temp_vec_12 ? 6'hC : _ldq_retry_idx_idx_T_41; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_43 = ldq_retry_idx_temp_vec_11 ? 6'hB : _ldq_retry_idx_idx_T_42; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_44 = ldq_retry_idx_temp_vec_10 ? 6'hA : _ldq_retry_idx_idx_T_43; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_45 = ldq_retry_idx_temp_vec_9 ? 6'h9 : _ldq_retry_idx_idx_T_44; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_46 = ldq_retry_idx_temp_vec_8 ? 6'h8 : _ldq_retry_idx_idx_T_45; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_47 = ldq_retry_idx_temp_vec_7 ? 6'h7 : _ldq_retry_idx_idx_T_46; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_48 = ldq_retry_idx_temp_vec_6 ? 6'h6 : _ldq_retry_idx_idx_T_47; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_49 = ldq_retry_idx_temp_vec_5 ? 6'h5 : _ldq_retry_idx_idx_T_48; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_50 = ldq_retry_idx_temp_vec_4 ? 6'h4 : _ldq_retry_idx_idx_T_49; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_51 = ldq_retry_idx_temp_vec_3 ? 6'h3 : _ldq_retry_idx_idx_T_50; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_52 = ldq_retry_idx_temp_vec_2 ? 6'h2 : _ldq_retry_idx_idx_T_51; // @[Mux.scala:50:70]
wire [5:0] _ldq_retry_idx_idx_T_53 = ldq_retry_idx_temp_vec_1 ? 6'h1 : _ldq_retry_idx_idx_T_52; // @[Mux.scala:50:70]
wire [5:0] ldq_retry_idx_idx = ldq_retry_idx_temp_vec_0 ? 6'h0 : _ldq_retry_idx_idx_T_53; // @[Mux.scala:50:70]
wire [4:0] _ldq_retry_idx_T_72 = ldq_retry_idx_idx[4:0]; // @[Mux.scala:50:70]
reg [4:0] ldq_retry_idx; // @[lsu.scala:414:30]
wire [4:0] _ldq_retry_e_T = ldq_retry_idx; // @[lsu.scala:414:30]
wire [4:0] _can_fire_load_retry_T_2 = ldq_retry_idx; // @[lsu.scala:414:30]
wire [4:0] _can_fire_load_retry_T_6 = ldq_retry_idx; // @[lsu.scala:414:30]
wire [4:0] _ldq_retry_e_T_1 = _ldq_retry_e_T;
wire _stq_retry_idx_T = stq_0_bits_addr_valid & stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_1 = stq_1_bits_addr_valid & stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_2 = stq_2_bits_addr_valid & stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_3 = stq_3_bits_addr_valid & stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_4 = stq_4_bits_addr_valid & stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_5 = stq_5_bits_addr_valid & stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_6 = stq_6_bits_addr_valid & stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_7 = stq_7_bits_addr_valid & stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_8 = stq_8_bits_addr_valid & stq_8_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_9 = stq_9_bits_addr_valid & stq_9_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_10 = stq_10_bits_addr_valid & stq_10_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_11 = stq_11_bits_addr_valid & stq_11_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_12 = stq_12_bits_addr_valid & stq_12_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_13 = stq_13_bits_addr_valid & stq_13_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_14 = stq_14_bits_addr_valid & stq_14_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_15 = stq_15_bits_addr_valid & stq_15_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_16 = stq_16_bits_addr_valid & stq_16_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_17 = stq_17_bits_addr_valid & stq_17_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_18 = stq_18_bits_addr_valid & stq_18_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_19 = stq_19_bits_addr_valid & stq_19_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_20 = stq_20_bits_addr_valid & stq_20_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_21 = stq_21_bits_addr_valid & stq_21_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_22 = stq_22_bits_addr_valid & stq_22_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_T_23 = stq_23_bits_addr_valid & stq_23_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18]
wire _stq_retry_idx_temp_vec_T = stq_commit_head == 5'h0; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_0 = _stq_retry_idx_T & _stq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_1 = stq_commit_head < 5'h2; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_1 = _stq_retry_idx_T_1 & _stq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_2 = stq_commit_head < 5'h3; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_2 = _stq_retry_idx_T_2 & _stq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_3 = stq_commit_head < 5'h4; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_3 = _stq_retry_idx_T_3 & _stq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_4 = stq_commit_head < 5'h5; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_4 = _stq_retry_idx_T_4 & _stq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_5 = stq_commit_head < 5'h6; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_5 = _stq_retry_idx_T_5 & _stq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_6 = stq_commit_head < 5'h7; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_6 = _stq_retry_idx_T_6 & _stq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_7 = stq_commit_head < 5'h8; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_7 = _stq_retry_idx_T_7 & _stq_retry_idx_temp_vec_T_7; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_8 = stq_commit_head < 5'h9; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_8 = _stq_retry_idx_T_8 & _stq_retry_idx_temp_vec_T_8; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_9 = stq_commit_head < 5'hA; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_9 = _stq_retry_idx_T_9 & _stq_retry_idx_temp_vec_T_9; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_10 = stq_commit_head < 5'hB; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_10 = _stq_retry_idx_T_10 & _stq_retry_idx_temp_vec_T_10; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_11 = stq_commit_head < 5'hC; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_11 = _stq_retry_idx_T_11 & _stq_retry_idx_temp_vec_T_11; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_12 = stq_commit_head < 5'hD; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_12 = _stq_retry_idx_T_12 & _stq_retry_idx_temp_vec_T_12; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_13 = stq_commit_head < 5'hE; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_13 = _stq_retry_idx_T_13 & _stq_retry_idx_temp_vec_T_13; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_14 = stq_commit_head < 5'hF; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_14 = _stq_retry_idx_T_14 & _stq_retry_idx_temp_vec_T_14; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_15 = ~(stq_commit_head[4]); // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_15 = _stq_retry_idx_T_15 & _stq_retry_idx_temp_vec_T_15; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_16 = stq_commit_head < 5'h11; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_16 = _stq_retry_idx_T_16 & _stq_retry_idx_temp_vec_T_16; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_17 = stq_commit_head < 5'h12; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_17 = _stq_retry_idx_T_17 & _stq_retry_idx_temp_vec_T_17; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_18 = stq_commit_head < 5'h13; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_18 = _stq_retry_idx_T_18 & _stq_retry_idx_temp_vec_T_18; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_19 = stq_commit_head < 5'h14; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_19 = _stq_retry_idx_T_19 & _stq_retry_idx_temp_vec_T_19; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_20 = stq_commit_head < 5'h15; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_20 = _stq_retry_idx_T_20 & _stq_retry_idx_temp_vec_T_20; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_21 = stq_commit_head < 5'h16; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_21 = _stq_retry_idx_T_21 & _stq_retry_idx_temp_vec_T_21; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_22 = stq_commit_head < 5'h17; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_22 = _stq_retry_idx_T_22 & _stq_retry_idx_temp_vec_T_22; // @[util.scala:351:{65,72}]
wire _stq_retry_idx_temp_vec_T_23 = stq_commit_head[4:3] != 2'h3; // @[util.scala:351:72]
wire stq_retry_idx_temp_vec_23 = _stq_retry_idx_T_23 & _stq_retry_idx_temp_vec_T_23; // @[util.scala:351:{65,72}]
wire [5:0] _stq_retry_idx_idx_T = {5'h1B, ~_stq_retry_idx_T_22}; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_1 = _stq_retry_idx_T_21 ? 6'h35 : _stq_retry_idx_idx_T; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_2 = _stq_retry_idx_T_20 ? 6'h34 : _stq_retry_idx_idx_T_1; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_3 = _stq_retry_idx_T_19 ? 6'h33 : _stq_retry_idx_idx_T_2; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_4 = _stq_retry_idx_T_18 ? 6'h32 : _stq_retry_idx_idx_T_3; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_5 = _stq_retry_idx_T_17 ? 6'h31 : _stq_retry_idx_idx_T_4; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_6 = _stq_retry_idx_T_16 ? 6'h30 : _stq_retry_idx_idx_T_5; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_7 = _stq_retry_idx_T_15 ? 6'h2F : _stq_retry_idx_idx_T_6; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_8 = _stq_retry_idx_T_14 ? 6'h2E : _stq_retry_idx_idx_T_7; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_9 = _stq_retry_idx_T_13 ? 6'h2D : _stq_retry_idx_idx_T_8; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_10 = _stq_retry_idx_T_12 ? 6'h2C : _stq_retry_idx_idx_T_9; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_11 = _stq_retry_idx_T_11 ? 6'h2B : _stq_retry_idx_idx_T_10; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_12 = _stq_retry_idx_T_10 ? 6'h2A : _stq_retry_idx_idx_T_11; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_13 = _stq_retry_idx_T_9 ? 6'h29 : _stq_retry_idx_idx_T_12; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_14 = _stq_retry_idx_T_8 ? 6'h28 : _stq_retry_idx_idx_T_13; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_15 = _stq_retry_idx_T_7 ? 6'h27 : _stq_retry_idx_idx_T_14; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_16 = _stq_retry_idx_T_6 ? 6'h26 : _stq_retry_idx_idx_T_15; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_17 = _stq_retry_idx_T_5 ? 6'h25 : _stq_retry_idx_idx_T_16; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_18 = _stq_retry_idx_T_4 ? 6'h24 : _stq_retry_idx_idx_T_17; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_19 = _stq_retry_idx_T_3 ? 6'h23 : _stq_retry_idx_idx_T_18; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_20 = _stq_retry_idx_T_2 ? 6'h22 : _stq_retry_idx_idx_T_19; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_21 = _stq_retry_idx_T_1 ? 6'h21 : _stq_retry_idx_idx_T_20; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_22 = _stq_retry_idx_T ? 6'h20 : _stq_retry_idx_idx_T_21; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_23 = _stq_retry_idx_idx_T_22; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_24 = _stq_retry_idx_idx_T_23; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_25 = _stq_retry_idx_idx_T_24; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_26 = _stq_retry_idx_idx_T_25; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_27 = _stq_retry_idx_idx_T_26; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_28 = _stq_retry_idx_idx_T_27; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_29 = _stq_retry_idx_idx_T_28; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_30 = _stq_retry_idx_idx_T_29; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_31 = stq_retry_idx_temp_vec_23 ? 6'h17 : _stq_retry_idx_idx_T_30; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_32 = stq_retry_idx_temp_vec_22 ? 6'h16 : _stq_retry_idx_idx_T_31; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_33 = stq_retry_idx_temp_vec_21 ? 6'h15 : _stq_retry_idx_idx_T_32; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_34 = stq_retry_idx_temp_vec_20 ? 6'h14 : _stq_retry_idx_idx_T_33; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_35 = stq_retry_idx_temp_vec_19 ? 6'h13 : _stq_retry_idx_idx_T_34; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_36 = stq_retry_idx_temp_vec_18 ? 6'h12 : _stq_retry_idx_idx_T_35; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_37 = stq_retry_idx_temp_vec_17 ? 6'h11 : _stq_retry_idx_idx_T_36; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_38 = stq_retry_idx_temp_vec_16 ? 6'h10 : _stq_retry_idx_idx_T_37; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_39 = stq_retry_idx_temp_vec_15 ? 6'hF : _stq_retry_idx_idx_T_38; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_40 = stq_retry_idx_temp_vec_14 ? 6'hE : _stq_retry_idx_idx_T_39; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_41 = stq_retry_idx_temp_vec_13 ? 6'hD : _stq_retry_idx_idx_T_40; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_42 = stq_retry_idx_temp_vec_12 ? 6'hC : _stq_retry_idx_idx_T_41; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_43 = stq_retry_idx_temp_vec_11 ? 6'hB : _stq_retry_idx_idx_T_42; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_44 = stq_retry_idx_temp_vec_10 ? 6'hA : _stq_retry_idx_idx_T_43; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_45 = stq_retry_idx_temp_vec_9 ? 6'h9 : _stq_retry_idx_idx_T_44; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_46 = stq_retry_idx_temp_vec_8 ? 6'h8 : _stq_retry_idx_idx_T_45; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_47 = stq_retry_idx_temp_vec_7 ? 6'h7 : _stq_retry_idx_idx_T_46; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_48 = stq_retry_idx_temp_vec_6 ? 6'h6 : _stq_retry_idx_idx_T_47; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_49 = stq_retry_idx_temp_vec_5 ? 6'h5 : _stq_retry_idx_idx_T_48; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_50 = stq_retry_idx_temp_vec_4 ? 6'h4 : _stq_retry_idx_idx_T_49; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_51 = stq_retry_idx_temp_vec_3 ? 6'h3 : _stq_retry_idx_idx_T_50; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_52 = stq_retry_idx_temp_vec_2 ? 6'h2 : _stq_retry_idx_idx_T_51; // @[Mux.scala:50:70]
wire [5:0] _stq_retry_idx_idx_T_53 = stq_retry_idx_temp_vec_1 ? 6'h1 : _stq_retry_idx_idx_T_52; // @[Mux.scala:50:70]
wire [5:0] stq_retry_idx_idx = stq_retry_idx_temp_vec_0 ? 6'h0 : _stq_retry_idx_idx_T_53; // @[Mux.scala:50:70]
wire [4:0] _stq_retry_idx_T_24 = stq_retry_idx_idx[4:0]; // @[Mux.scala:50:70]
reg [4:0] stq_retry_idx; // @[lsu.scala:421:30]
wire [4:0] _stq_retry_e_T = stq_retry_idx; // @[lsu.scala:421:30]
wire [4:0] _stq_retry_e_T_1 = _stq_retry_e_T;
wire _ldq_wakeup_idx_T = ~ldq_0_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_1 = ldq_0_bits_addr_valid & _ldq_wakeup_idx_T; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_2 = ~ldq_0_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_4 = ~ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_8 = ~ldq_1_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_9 = ldq_1_bits_addr_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_10 = ~ldq_1_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_12 = ~ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_16 = ~ldq_2_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_17 = ldq_2_bits_addr_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_18 = ~ldq_2_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_20 = ~ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_24 = ~ldq_3_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_25 = ldq_3_bits_addr_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_26 = ~ldq_3_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_28 = ~ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_32 = ~ldq_4_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_33 = ldq_4_bits_addr_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_34 = ~ldq_4_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_36 = ~ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_40 = ~ldq_5_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_41 = ldq_5_bits_addr_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_42 = ~ldq_5_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_44 = ~ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_48 = ~ldq_6_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_49 = ldq_6_bits_addr_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_50 = ~ldq_6_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_52 = ~ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_56 = ~ldq_7_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_57 = ldq_7_bits_addr_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_58 = ~ldq_7_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_60 = ~ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_64 = ~ldq_8_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_65 = ldq_8_bits_addr_valid & _ldq_wakeup_idx_T_64; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_66 = ~ldq_8_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_67 = _ldq_wakeup_idx_T_65 & _ldq_wakeup_idx_T_66; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_68 = ~ldq_8_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_69 = _ldq_wakeup_idx_T_67 & _ldq_wakeup_idx_T_68; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_70 = ~ldq_wakeup_idx_block_8; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_71 = _ldq_wakeup_idx_T_69 & _ldq_wakeup_idx_T_70; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_72 = ~ldq_9_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_73 = ldq_9_bits_addr_valid & _ldq_wakeup_idx_T_72; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_74 = ~ldq_9_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_75 = _ldq_wakeup_idx_T_73 & _ldq_wakeup_idx_T_74; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_76 = ~ldq_9_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_77 = _ldq_wakeup_idx_T_75 & _ldq_wakeup_idx_T_76; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_78 = ~ldq_wakeup_idx_block_9; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_79 = _ldq_wakeup_idx_T_77 & _ldq_wakeup_idx_T_78; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_80 = ~ldq_10_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_81 = ldq_10_bits_addr_valid & _ldq_wakeup_idx_T_80; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_82 = ~ldq_10_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_83 = _ldq_wakeup_idx_T_81 & _ldq_wakeup_idx_T_82; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_84 = ~ldq_10_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_85 = _ldq_wakeup_idx_T_83 & _ldq_wakeup_idx_T_84; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_86 = ~ldq_wakeup_idx_block_10; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_87 = _ldq_wakeup_idx_T_85 & _ldq_wakeup_idx_T_86; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_88 = ~ldq_11_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_89 = ldq_11_bits_addr_valid & _ldq_wakeup_idx_T_88; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_90 = ~ldq_11_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_91 = _ldq_wakeup_idx_T_89 & _ldq_wakeup_idx_T_90; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_92 = ~ldq_11_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_93 = _ldq_wakeup_idx_T_91 & _ldq_wakeup_idx_T_92; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_94 = ~ldq_wakeup_idx_block_11; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_95 = _ldq_wakeup_idx_T_93 & _ldq_wakeup_idx_T_94; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_96 = ~ldq_12_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_97 = ldq_12_bits_addr_valid & _ldq_wakeup_idx_T_96; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_98 = ~ldq_12_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_99 = _ldq_wakeup_idx_T_97 & _ldq_wakeup_idx_T_98; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_100 = ~ldq_12_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_101 = _ldq_wakeup_idx_T_99 & _ldq_wakeup_idx_T_100; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_102 = ~ldq_wakeup_idx_block_12; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_103 = _ldq_wakeup_idx_T_101 & _ldq_wakeup_idx_T_102; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_104 = ~ldq_13_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_105 = ldq_13_bits_addr_valid & _ldq_wakeup_idx_T_104; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_106 = ~ldq_13_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_107 = _ldq_wakeup_idx_T_105 & _ldq_wakeup_idx_T_106; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_108 = ~ldq_13_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_109 = _ldq_wakeup_idx_T_107 & _ldq_wakeup_idx_T_108; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_110 = ~ldq_wakeup_idx_block_13; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_111 = _ldq_wakeup_idx_T_109 & _ldq_wakeup_idx_T_110; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_112 = ~ldq_14_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_113 = ldq_14_bits_addr_valid & _ldq_wakeup_idx_T_112; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_114 = ~ldq_14_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_115 = _ldq_wakeup_idx_T_113 & _ldq_wakeup_idx_T_114; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_116 = ~ldq_14_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_117 = _ldq_wakeup_idx_T_115 & _ldq_wakeup_idx_T_116; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_118 = ~ldq_wakeup_idx_block_14; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_119 = _ldq_wakeup_idx_T_117 & _ldq_wakeup_idx_T_118; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_120 = ~ldq_15_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_121 = ldq_15_bits_addr_valid & _ldq_wakeup_idx_T_120; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_122 = ~ldq_15_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_123 = _ldq_wakeup_idx_T_121 & _ldq_wakeup_idx_T_122; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_124 = ~ldq_15_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_125 = _ldq_wakeup_idx_T_123 & _ldq_wakeup_idx_T_124; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_126 = ~ldq_wakeup_idx_block_15; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_127 = _ldq_wakeup_idx_T_125 & _ldq_wakeup_idx_T_126; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_128 = ~ldq_16_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_129 = ldq_16_bits_addr_valid & _ldq_wakeup_idx_T_128; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_130 = ~ldq_16_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_131 = _ldq_wakeup_idx_T_129 & _ldq_wakeup_idx_T_130; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_132 = ~ldq_16_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_133 = _ldq_wakeup_idx_T_131 & _ldq_wakeup_idx_T_132; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_134 = ~ldq_wakeup_idx_block_16; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_135 = _ldq_wakeup_idx_T_133 & _ldq_wakeup_idx_T_134; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_136 = ~ldq_17_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_137 = ldq_17_bits_addr_valid & _ldq_wakeup_idx_T_136; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_138 = ~ldq_17_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_139 = _ldq_wakeup_idx_T_137 & _ldq_wakeup_idx_T_138; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_140 = ~ldq_17_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_141 = _ldq_wakeup_idx_T_139 & _ldq_wakeup_idx_T_140; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_142 = ~ldq_wakeup_idx_block_17; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_143 = _ldq_wakeup_idx_T_141 & _ldq_wakeup_idx_T_142; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_144 = ~ldq_18_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_145 = ldq_18_bits_addr_valid & _ldq_wakeup_idx_T_144; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_146 = ~ldq_18_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_147 = _ldq_wakeup_idx_T_145 & _ldq_wakeup_idx_T_146; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_148 = ~ldq_18_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_149 = _ldq_wakeup_idx_T_147 & _ldq_wakeup_idx_T_148; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_150 = ~ldq_wakeup_idx_block_18; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_151 = _ldq_wakeup_idx_T_149 & _ldq_wakeup_idx_T_150; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_152 = ~ldq_19_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_153 = ldq_19_bits_addr_valid & _ldq_wakeup_idx_T_152; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_154 = ~ldq_19_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_155 = _ldq_wakeup_idx_T_153 & _ldq_wakeup_idx_T_154; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_156 = ~ldq_19_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_157 = _ldq_wakeup_idx_T_155 & _ldq_wakeup_idx_T_156; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_158 = ~ldq_wakeup_idx_block_19; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_159 = _ldq_wakeup_idx_T_157 & _ldq_wakeup_idx_T_158; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_160 = ~ldq_20_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_161 = ldq_20_bits_addr_valid & _ldq_wakeup_idx_T_160; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_162 = ~ldq_20_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_163 = _ldq_wakeup_idx_T_161 & _ldq_wakeup_idx_T_162; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_164 = ~ldq_20_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_165 = _ldq_wakeup_idx_T_163 & _ldq_wakeup_idx_T_164; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_166 = ~ldq_wakeup_idx_block_20; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_167 = _ldq_wakeup_idx_T_165 & _ldq_wakeup_idx_T_166; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_168 = ~ldq_21_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_169 = ldq_21_bits_addr_valid & _ldq_wakeup_idx_T_168; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_170 = ~ldq_21_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_171 = _ldq_wakeup_idx_T_169 & _ldq_wakeup_idx_T_170; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_172 = ~ldq_21_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_173 = _ldq_wakeup_idx_T_171 & _ldq_wakeup_idx_T_172; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_174 = ~ldq_wakeup_idx_block_21; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_175 = _ldq_wakeup_idx_T_173 & _ldq_wakeup_idx_T_174; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_176 = ~ldq_22_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_177 = ldq_22_bits_addr_valid & _ldq_wakeup_idx_T_176; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_178 = ~ldq_22_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_179 = _ldq_wakeup_idx_T_177 & _ldq_wakeup_idx_T_178; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_180 = ~ldq_22_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_181 = _ldq_wakeup_idx_T_179 & _ldq_wakeup_idx_T_180; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_182 = ~ldq_wakeup_idx_block_22; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_183 = _ldq_wakeup_idx_T_181 & _ldq_wakeup_idx_T_182; // @[lsu.scala:432:{49,71,74}]
wire _ldq_wakeup_idx_T_184 = ~ldq_23_bits_executed; // @[lsu.scala:208:16, :432:21]
wire _ldq_wakeup_idx_T_185 = ldq_23_bits_addr_valid & _ldq_wakeup_idx_T_184; // @[lsu.scala:208:16, :432:{18,21}]
wire _ldq_wakeup_idx_T_186 = ~ldq_23_bits_succeeded; // @[lsu.scala:208:16, :432:36]
wire _ldq_wakeup_idx_T_187 = _ldq_wakeup_idx_T_185 & _ldq_wakeup_idx_T_186; // @[lsu.scala:432:{18,33,36}]
wire _ldq_wakeup_idx_T_188 = ~ldq_23_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52]
wire _ldq_wakeup_idx_T_189 = _ldq_wakeup_idx_T_187 & _ldq_wakeup_idx_T_188; // @[lsu.scala:432:{33,49,52}]
wire _ldq_wakeup_idx_T_190 = ~ldq_wakeup_idx_block_23; // @[lsu.scala:431:36, :432:74]
wire _ldq_wakeup_idx_T_191 = _ldq_wakeup_idx_T_189 & _ldq_wakeup_idx_T_190; // @[lsu.scala:432:{49,71,74}]
wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63 & _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_8 = _ldq_wakeup_idx_T_71 & _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_9 = _ldq_wakeup_idx_T_79 & _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_10 = _ldq_wakeup_idx_T_87 & _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_11 = _ldq_wakeup_idx_T_95 & _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_12 = _ldq_wakeup_idx_T_103 & _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_13 = _ldq_wakeup_idx_T_111 & _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_14 = _ldq_wakeup_idx_T_119 & _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:351:{65,72}]
wire _ldq_wakeup_idx_temp_vec_T_15 = ~_searcher_is_older_T_63; // @[util.scala:351:72, :363:78]
wire ldq_wakeup_idx_temp_vec_15 = _ldq_wakeup_idx_T_127 & _ldq_wakeup_idx_temp_vec_T_15; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_16 = _ldq_wakeup_idx_T_135 & _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_17 = _ldq_wakeup_idx_T_143 & _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_18 = _ldq_wakeup_idx_T_151 & _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_19 = _ldq_wakeup_idx_T_159 & _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_20 = _ldq_wakeup_idx_T_167 & _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_21 = _ldq_wakeup_idx_T_175 & _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_22 = _ldq_wakeup_idx_T_183 & _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:351:{65,72}]
wire ldq_wakeup_idx_temp_vec_23 = _ldq_wakeup_idx_T_191 & _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:351:{65,72}]
wire [5:0] _ldq_wakeup_idx_idx_T = {5'h1B, ~_ldq_wakeup_idx_T_183}; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_175 ? 6'h35 : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_167 ? 6'h34 : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_159 ? 6'h33 : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_151 ? 6'h32 : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_143 ? 6'h31 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_135 ? 6'h30 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_7 = _ldq_wakeup_idx_T_127 ? 6'h2F : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_8 = _ldq_wakeup_idx_T_119 ? 6'h2E : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_9 = _ldq_wakeup_idx_T_111 ? 6'h2D : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_10 = _ldq_wakeup_idx_T_103 ? 6'h2C : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_11 = _ldq_wakeup_idx_T_95 ? 6'h2B : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_12 = _ldq_wakeup_idx_T_87 ? 6'h2A : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_13 = _ldq_wakeup_idx_T_79 ? 6'h29 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_14 = _ldq_wakeup_idx_T_71 ? 6'h28 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_15 = _ldq_wakeup_idx_T_63 ? 6'h27 : _ldq_wakeup_idx_idx_T_14; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_16 = _ldq_wakeup_idx_T_55 ? 6'h26 : _ldq_wakeup_idx_idx_T_15; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_17 = _ldq_wakeup_idx_T_47 ? 6'h25 : _ldq_wakeup_idx_idx_T_16; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_18 = _ldq_wakeup_idx_T_39 ? 6'h24 : _ldq_wakeup_idx_idx_T_17; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_19 = _ldq_wakeup_idx_T_31 ? 6'h23 : _ldq_wakeup_idx_idx_T_18; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_20 = _ldq_wakeup_idx_T_23 ? 6'h22 : _ldq_wakeup_idx_idx_T_19; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_21 = _ldq_wakeup_idx_T_15 ? 6'h21 : _ldq_wakeup_idx_idx_T_20; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_22 = _ldq_wakeup_idx_T_7 ? 6'h20 : _ldq_wakeup_idx_idx_T_21; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_23 = _ldq_wakeup_idx_idx_T_22; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_24 = _ldq_wakeup_idx_idx_T_23; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_25 = _ldq_wakeup_idx_idx_T_24; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_26 = _ldq_wakeup_idx_idx_T_25; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_27 = _ldq_wakeup_idx_idx_T_26; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_28 = _ldq_wakeup_idx_idx_T_27; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_29 = _ldq_wakeup_idx_idx_T_28; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_30 = _ldq_wakeup_idx_idx_T_29; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_31 = ldq_wakeup_idx_temp_vec_23 ? 6'h17 : _ldq_wakeup_idx_idx_T_30; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_32 = ldq_wakeup_idx_temp_vec_22 ? 6'h16 : _ldq_wakeup_idx_idx_T_31; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_33 = ldq_wakeup_idx_temp_vec_21 ? 6'h15 : _ldq_wakeup_idx_idx_T_32; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_34 = ldq_wakeup_idx_temp_vec_20 ? 6'h14 : _ldq_wakeup_idx_idx_T_33; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_35 = ldq_wakeup_idx_temp_vec_19 ? 6'h13 : _ldq_wakeup_idx_idx_T_34; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_36 = ldq_wakeup_idx_temp_vec_18 ? 6'h12 : _ldq_wakeup_idx_idx_T_35; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_37 = ldq_wakeup_idx_temp_vec_17 ? 6'h11 : _ldq_wakeup_idx_idx_T_36; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_38 = ldq_wakeup_idx_temp_vec_16 ? 6'h10 : _ldq_wakeup_idx_idx_T_37; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_39 = ldq_wakeup_idx_temp_vec_15 ? 6'hF : _ldq_wakeup_idx_idx_T_38; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_40 = ldq_wakeup_idx_temp_vec_14 ? 6'hE : _ldq_wakeup_idx_idx_T_39; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_41 = ldq_wakeup_idx_temp_vec_13 ? 6'hD : _ldq_wakeup_idx_idx_T_40; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_42 = ldq_wakeup_idx_temp_vec_12 ? 6'hC : _ldq_wakeup_idx_idx_T_41; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_43 = ldq_wakeup_idx_temp_vec_11 ? 6'hB : _ldq_wakeup_idx_idx_T_42; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_44 = ldq_wakeup_idx_temp_vec_10 ? 6'hA : _ldq_wakeup_idx_idx_T_43; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_45 = ldq_wakeup_idx_temp_vec_9 ? 6'h9 : _ldq_wakeup_idx_idx_T_44; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_46 = ldq_wakeup_idx_temp_vec_8 ? 6'h8 : _ldq_wakeup_idx_idx_T_45; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_47 = ldq_wakeup_idx_temp_vec_7 ? 6'h7 : _ldq_wakeup_idx_idx_T_46; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_48 = ldq_wakeup_idx_temp_vec_6 ? 6'h6 : _ldq_wakeup_idx_idx_T_47; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_49 = ldq_wakeup_idx_temp_vec_5 ? 6'h5 : _ldq_wakeup_idx_idx_T_48; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_50 = ldq_wakeup_idx_temp_vec_4 ? 6'h4 : _ldq_wakeup_idx_idx_T_49; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_51 = ldq_wakeup_idx_temp_vec_3 ? 6'h3 : _ldq_wakeup_idx_idx_T_50; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_52 = ldq_wakeup_idx_temp_vec_2 ? 6'h2 : _ldq_wakeup_idx_idx_T_51; // @[Mux.scala:50:70]
wire [5:0] _ldq_wakeup_idx_idx_T_53 = ldq_wakeup_idx_temp_vec_1 ? 6'h1 : _ldq_wakeup_idx_idx_T_52; // @[Mux.scala:50:70]
wire [5:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 6'h0 : _ldq_wakeup_idx_idx_T_53; // @[Mux.scala:50:70]
wire [4:0] _ldq_wakeup_idx_T_192 = ldq_wakeup_idx_idx[4:0]; // @[Mux.scala:50:70]
reg [4:0] ldq_wakeup_idx; // @[lsu.scala:429:31]
wire [4:0] _ldq_wakeup_e_T = ldq_wakeup_idx; // @[lsu.scala:429:31]
wire [4:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:429:31]
wire [4:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:429:31]
wire [4:0] _ldq_wakeup_e_T_1 = _ldq_wakeup_e_T;
wire _can_fire_load_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25, :440:63]
wire can_fire_load_incoming_0 = _can_fire_load_incoming_T; // @[lsu.scala:263:49, :440:63]
wire _will_fire_load_incoming_0_will_fire_T_3 = can_fire_load_incoming_0; // @[lsu.scala:263:49, :533:32]
wire _GEN_240 = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :443:63]
wire _can_fire_stad_incoming_T; // @[lsu.scala:443:63]
assign _can_fire_stad_incoming_T = _GEN_240; // @[lsu.scala:443:63]
wire _can_fire_sta_incoming_T; // @[lsu.scala:447:63]
assign _can_fire_sta_incoming_T = _GEN_240; // @[lsu.scala:443:63, :447:63]
wire _can_fire_stad_incoming_T_1 = _can_fire_stad_incoming_T & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :443:63, :444:63]
wire can_fire_stad_incoming_0 = _can_fire_stad_incoming_T_1; // @[lsu.scala:263:49, :444:63]
wire _can_fire_sta_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :448:66]
wire _can_fire_sta_incoming_T_2 = _can_fire_sta_incoming_T & _can_fire_sta_incoming_T_1; // @[lsu.scala:447:63, :448:{63,66}]
wire can_fire_sta_incoming_0 = _can_fire_sta_incoming_T_2; // @[lsu.scala:263:49, :448:63]
wire _can_fire_std_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :451:63]
wire _can_fire_std_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :452:66]
wire _can_fire_std_incoming_T_2 = _can_fire_std_incoming_T & _can_fire_std_incoming_T_1; // @[lsu.scala:451:63, :452:{63,66}]
wire can_fire_std_incoming_0 = _can_fire_std_incoming_T_2; // @[lsu.scala:263:49, :452:63]
wire _will_fire_std_incoming_0_will_fire_T_3 = can_fire_std_incoming_0; // @[lsu.scala:263:49, :533:32]
wire _can_fire_sfence_T = exe_req_0_valid & exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25, :455:63]
wire can_fire_sfence_0 = _can_fire_sfence_T; // @[lsu.scala:263:49, :455:63]
wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:263:49, :459:66]
wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:263:49, :533:32]
wire [6:0] mem_ldq_retry_e_out_bits_uop_uopc = _GEN_101[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = _GEN_102[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = _GEN_103[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_rvc = _GEN_104[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = _GEN_105[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_retry_e_out_bits_uop_iq_type = _GEN_106[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [9:0] mem_ldq_retry_e_out_bits_uop_fu_code = _GEN_107[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [3:0] mem_ldq_retry_e_out_bits_uop_ctrl_br_type = _GEN_108[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_109[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_110[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_111[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_112[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_113[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_114[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_ctrl_is_load = _GEN_115[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_116[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_ctrl_is_std = _GEN_117[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_state = _GEN_118[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_119[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_120[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_br = _GEN_121[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_jalr = _GEN_122[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_jal = _GEN_123[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_sfb = _GEN_124[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [3:0] mem_ldq_retry_e_out_bits_uop_br_tag = _GEN_126[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = _GEN_127[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_edge_inst = _GEN_128[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = _GEN_129[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_taken = _GEN_130[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = _GEN_131[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [11:0] mem_ldq_retry_e_out_bits_uop_csr_addr = _GEN_132[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_retry_e_out_bits_uop_rob_idx = _GEN_133[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = _GEN_134[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_uop_stq_idx = _GEN_135[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = _GEN_136[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_retry_e_out_bits_uop_pdst = _GEN_137[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_retry_e_out_bits_uop_prs1 = _GEN_138[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_retry_e_out_bits_uop_prs2 = _GEN_139[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_retry_e_out_bits_uop_prs3 = _GEN_140[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_prs1_busy = _GEN_141[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_prs2_busy = _GEN_142[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_prs3_busy = _GEN_143[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = _GEN_144[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_exception = _GEN_145[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = _GEN_146[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_bypassable = _GEN_147[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = _GEN_148[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = _GEN_149[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_mem_signed = _GEN_150[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_fence = _GEN_151[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_fencei = _GEN_152[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_amo = _GEN_153[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_uses_ldq = _GEN_154[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_uses_stq = _GEN_155[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_156[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_is_unique = _GEN_157[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = _GEN_158[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_159[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = _GEN_160[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = _GEN_161[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = _GEN_162[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = _GEN_163[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_ldst_val = _GEN_164[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = _GEN_165[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = _GEN_166[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = _GEN_167[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_frs3_en = _GEN_168[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_fp_val = _GEN_169[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_fp_single = _GEN_170[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_171[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_172[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_173[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = _GEN_174[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_175[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = _GEN_176[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = _GEN_177[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_addr_valid = _GEN_178[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = _GEN_179[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_addr_is_virtual = _GEN_180[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = _GEN_181[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_executed = _GEN_182[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_succeeded = _GEN_183[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_order_fail = _GEN_184[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_observed = _GEN_185[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [23:0] mem_ldq_retry_e_out_bits_st_dep_mask = _GEN_186[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_youngest_stq_idx = _GEN_187[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_bits_forward_std_val = _GEN_188[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_retry_e_out_bits_forward_stq_idx = _GEN_189[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = _GEN_190[_ldq_retry_e_T_1]; // @[util.scala:106:23]
wire _can_fire_load_retry_T = _GEN_94[_ldq_retry_e_T_1] & mem_ldq_retry_e_out_bits_addr_valid; // @[util.scala:106:23]
wire _can_fire_load_retry_T_1 = _can_fire_load_retry_T & mem_ldq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23]
wire [4:0] _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2;
wire [31:0] _GEN_241 = {{p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_23}, {p1_block_load_mask_22}, {p1_block_load_mask_21}, {p1_block_load_mask_20}, {p1_block_load_mask_19}, {p1_block_load_mask_18}, {p1_block_load_mask_17}, {p1_block_load_mask_16}, {p1_block_load_mask_15}, {p1_block_load_mask_14}, {p1_block_load_mask_13}, {p1_block_load_mask_12}, {p1_block_load_mask_11}, {p1_block_load_mask_10}, {p1_block_load_mask_9}, {p1_block_load_mask_8}, {p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:397:35, :467:33]
wire _can_fire_load_retry_T_4 = ~_GEN_241[_can_fire_load_retry_T_3]; // @[lsu.scala:467:33]
wire _can_fire_load_retry_T_5 = _can_fire_load_retry_T_1 & _can_fire_load_retry_T_4; // @[lsu.scala:465:79, :466:79, :467:33]
wire [4:0] _can_fire_load_retry_T_7 = _can_fire_load_retry_T_6;
wire [31:0] _GEN_242 = {{p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_23}, {p2_block_load_mask_22}, {p2_block_load_mask_21}, {p2_block_load_mask_20}, {p2_block_load_mask_19}, {p2_block_load_mask_18}, {p2_block_load_mask_17}, {p2_block_load_mask_16}, {p2_block_load_mask_15}, {p2_block_load_mask_14}, {p2_block_load_mask_13}, {p2_block_load_mask_12}, {p2_block_load_mask_11}, {p2_block_load_mask_10}, {p2_block_load_mask_9}, {p2_block_load_mask_8}, {p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:398:35, :468:33]
wire _can_fire_load_retry_T_8 = ~_GEN_242[_can_fire_load_retry_T_7]; // @[lsu.scala:468:33]
wire _can_fire_load_retry_T_9 = _can_fire_load_retry_T_5 & _can_fire_load_retry_T_8; // @[lsu.scala:466:79, :467:79, :468:33]
reg can_fire_load_retry_REG; // @[lsu.scala:469:40]
wire _can_fire_load_retry_T_10 = _can_fire_load_retry_T_9 & can_fire_load_retry_REG; // @[lsu.scala:467:79, :468:79, :469:40]
wire _can_fire_load_retry_T_11 = ~store_needs_order; // @[lsu.scala:406:35, :470:33]
wire _can_fire_load_retry_T_12 = _can_fire_load_retry_T_10 & _can_fire_load_retry_T_11; // @[lsu.scala:468:79, :469:79, :470:33]
wire _can_fire_load_retry_T_13 = _can_fire_load_retry_T_12; // @[lsu.scala:469:79, :470:79]
wire _can_fire_load_retry_T_14 = ~mem_ldq_retry_e_out_bits_order_fail; // @[util.scala:106:23]
wire _can_fire_load_retry_T_15 = _can_fire_load_retry_T_13 & _can_fire_load_retry_T_14; // @[lsu.scala:470:79, :471:79, :472:33]
wire can_fire_load_retry_0 = _can_fire_load_retry_T_15; // @[lsu.scala:263:49, :471:79]
wire [6:0] mem_stq_retry_e_out_bits_uop_uopc = _GEN_1[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [31:0] mem_stq_retry_e_out_bits_uop_inst = _GEN_2[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = _GEN_3[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_rvc = _GEN_4[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = _GEN_5[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_stq_retry_e_out_bits_uop_iq_type = _GEN_6[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [9:0] mem_stq_retry_e_out_bits_uop_fu_code = _GEN_7[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [3:0] mem_stq_retry_e_out_bits_uop_ctrl_br_type = _GEN_8[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_9[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_10[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_11[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_stq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_12[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_13[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_14[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_ctrl_is_load = _GEN_15[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_16[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_ctrl_is_std = _GEN_17[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_iw_state = _GEN_18[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_19[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_20[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_br = _GEN_21[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_jalr = _GEN_22[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_jal = _GEN_23[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_sfb = _GEN_24[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [3:0] mem_stq_retry_e_out_bits_uop_br_tag = _GEN_26[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_stq_retry_e_out_bits_uop_ftq_idx = _GEN_27[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_edge_inst = _GEN_28[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = _GEN_29[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_taken = _GEN_30[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = _GEN_31[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [11:0] mem_stq_retry_e_out_bits_uop_csr_addr = _GEN_32[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_stq_retry_e_out_bits_uop_rob_idx = _GEN_33[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_stq_retry_e_out_bits_uop_ldq_idx = _GEN_34[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_stq_retry_e_out_bits_uop_stq_idx = _GEN_35[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = _GEN_36[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_stq_retry_e_out_bits_uop_pdst = _GEN_37[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_stq_retry_e_out_bits_uop_prs1 = _GEN_38[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_stq_retry_e_out_bits_uop_prs2 = _GEN_39[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_stq_retry_e_out_bits_uop_prs3 = _GEN_40[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_stq_retry_e_out_bits_uop_ppred = _GEN_41[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_prs1_busy = _GEN_42[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_prs2_busy = _GEN_43[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_prs3_busy = _GEN_44[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_ppred_busy = _GEN_45[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_stq_retry_e_out_bits_uop_stale_pdst = _GEN_46[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_exception = _GEN_47[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = _GEN_49[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_bypassable = _GEN_50[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = _GEN_51[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = _GEN_52[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_mem_signed = _GEN_53[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_fence = _GEN_54[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_fencei = _GEN_56[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_amo = _GEN_57[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_uses_ldq = _GEN_59[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_uses_stq = _GEN_60[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_61[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_is_unique = _GEN_62[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_flush_on_commit = _GEN_63[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_64[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = _GEN_65[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = _GEN_66[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = _GEN_67[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = _GEN_68[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_ldst_val = _GEN_69[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = _GEN_70[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = _GEN_71[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = _GEN_72[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_frs3_en = _GEN_73[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_fp_val = _GEN_74[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_fp_single = _GEN_75[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_76[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_77[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_78[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_bp_debug_if = _GEN_79[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_80[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = _GEN_81[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = _GEN_82[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_addr_valid = _GEN_83[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [39:0] mem_stq_retry_e_out_bits_addr_bits = _GEN_84[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_addr_is_virtual = _GEN_85[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_data_valid = _GEN_86[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [63:0] mem_stq_retry_e_out_bits_data_bits = _GEN_87[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_committed = _GEN_89[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire mem_stq_retry_e_out_bits_succeeded = _GEN_191[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = _GEN_192[_stq_retry_e_T_1]; // @[util.scala:106:23]
wire _can_fire_sta_retry_T = _GEN[_stq_retry_e_T_1] & mem_stq_retry_e_out_bits_addr_valid; // @[util.scala:106:23]
wire _can_fire_sta_retry_T_1 = _can_fire_sta_retry_T & mem_stq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23]
wire _can_fire_sta_retry_T_2 = _can_fire_sta_retry_T_1; // @[lsu.scala:478:79, :479:79]
reg can_fire_sta_retry_REG; // @[lsu.scala:481:41]
wire _can_fire_sta_retry_T_3 = _can_fire_sta_retry_T_2 & can_fire_sta_retry_REG; // @[lsu.scala:479:79, :480:79, :481:41]
wire _can_fire_sta_retry_T_8 = _can_fire_sta_retry_T_3; // @[lsu.scala:480:79, :481:79]
wire _can_fire_sta_retry_T_5 = stq_incoming_idx_0 == stq_retry_idx; // @[lsu.scala:263:49, :421:30, :484:70]
wire can_fire_sta_retry_0 = _can_fire_sta_retry_T_8; // @[lsu.scala:263:49, :481:79]
wire _can_fire_store_commit_T = ~_GEN_55; // @[lsu.scala:222:42, :489:33]
wire _can_fire_store_commit_T_1 = _GEN_0 & _can_fire_store_commit_T; // @[lsu.scala:222:42, :488:79, :489:33]
wire _can_fire_store_commit_T_2 = ~mem_xcpt_valid; // @[lsu.scala:358:29, :490:33]
wire _can_fire_store_commit_T_3 = _can_fire_store_commit_T_1 & _can_fire_store_commit_T_2; // @[lsu.scala:488:79, :489:79, :490:33]
wire _can_fire_store_commit_T_4 = ~_GEN_48; // @[lsu.scala:222:42, :491:33]
wire _can_fire_store_commit_T_5 = _can_fire_store_commit_T_3 & _can_fire_store_commit_T_4; // @[lsu.scala:489:79, :490:79, :491:33]
wire _can_fire_store_commit_T_6 = _can_fire_store_commit_T_5; // @[lsu.scala:490:79, :491:79]
wire _can_fire_store_commit_T_7 = _GEN_58 & _GEN_83[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :493:101]
wire _can_fire_store_commit_T_8 = ~_GEN_85[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :495:66]
wire _can_fire_store_commit_T_9 = _can_fire_store_commit_T_7 & _can_fire_store_commit_T_8; // @[lsu.scala:493:101, :494:101, :495:66]
wire _can_fire_store_commit_T_10 = _can_fire_store_commit_T_9 & _GEN_86[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :494:101, :495:101]
wire _can_fire_store_commit_T_11 = _GEN_89[stq_execute_head] | _can_fire_store_commit_T_10; // @[lsu.scala:218:29, :222:42, :493:62, :495:101]
wire _can_fire_store_commit_T_12 = _can_fire_store_commit_T_6 & _can_fire_store_commit_T_11; // @[lsu.scala:491:79, :492:79, :493:62]
wire can_fire_store_commit_0 = _can_fire_store_commit_T_12; // @[lsu.scala:263:49, :492:79]
wire _will_fire_store_commit_0_will_fire_T_3 = can_fire_store_commit_0; // @[lsu.scala:263:49, :533:32]
wire block_load_wakeup; // @[lsu.scala:499:35]
wire [6:0] mem_ldq_wakeup_e_out_bits_uop_uopc = _GEN_101[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = _GEN_102[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = _GEN_103[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = _GEN_104[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = _GEN_105[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iq_type = _GEN_106[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [9:0] mem_ldq_wakeup_e_out_bits_uop_fu_code = _GEN_107[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type = _GEN_108[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel = _GEN_109[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel = _GEN_110[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel = _GEN_111[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn = _GEN_112[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw = _GEN_113[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd = _GEN_114[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load = _GEN_115[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta = _GEN_116[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std = _GEN_117[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_state = _GEN_118[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned = _GEN_119[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned = _GEN_120[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_br = _GEN_121[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_jalr = _GEN_122[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_jal = _GEN_123[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = _GEN_124[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = _GEN_126[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = _GEN_127[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = _GEN_128[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = _GEN_129[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_taken = _GEN_130[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = _GEN_131[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [11:0] mem_ldq_wakeup_e_out_bits_uop_csr_addr = _GEN_132[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = _GEN_133[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = _GEN_134[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = _GEN_135[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = _GEN_136[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_wakeup_e_out_bits_uop_pdst = _GEN_137[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = _GEN_138[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = _GEN_139[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = _GEN_140[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = _GEN_141[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = _GEN_142[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = _GEN_143[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [6:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = _GEN_144[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_exception = _GEN_145[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = _GEN_146[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_bypassable = _GEN_147[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = _GEN_148[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = _GEN_149[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = _GEN_150[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_fence = _GEN_151[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = _GEN_152[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_amo = _GEN_153[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = _GEN_154[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = _GEN_155[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = _GEN_156[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_is_unique = _GEN_157[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = _GEN_158[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = _GEN_159[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = _GEN_160[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = _GEN_161[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = _GEN_162[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = _GEN_163[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_ldst_val = _GEN_164[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = _GEN_165[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = _GEN_166[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = _GEN_167[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = _GEN_168[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_fp_val = _GEN_169[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_fp_single = _GEN_170[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = _GEN_171[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = _GEN_172[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = _GEN_173[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = _GEN_174[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = _GEN_175[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = _GEN_176[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = _GEN_177[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_addr_valid = _GEN_178[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = _GEN_179[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = _GEN_180[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = _GEN_181[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_executed = _GEN_182[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_succeeded = _GEN_183[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_order_fail = _GEN_184[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_observed = _GEN_185[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [23:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = _GEN_186[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_wakeup_e_out_bits_youngest_stq_idx = _GEN_187[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_bits_forward_std_val = _GEN_188[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [4:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = _GEN_189[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = _GEN_190[_ldq_wakeup_e_T_1]; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T = _GEN_94[_ldq_wakeup_e_T_1] & mem_ldq_wakeup_e_out_bits_addr_valid; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T_1 = ~mem_ldq_wakeup_e_out_bits_succeeded; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:501:88, :502:88, :503:31]
wire _can_fire_load_wakeup_T_3 = ~mem_ldq_wakeup_e_out_bits_addr_is_virtual; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:502:88, :503:88, :504:31]
wire _can_fire_load_wakeup_T_5 = ~mem_ldq_wakeup_e_out_bits_executed; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:503:88, :504:88, :505:31]
wire _can_fire_load_wakeup_T_7 = ~mem_ldq_wakeup_e_out_bits_order_fail; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:504:88, :505:88, :506:31]
wire [4:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9;
wire _can_fire_load_wakeup_T_11 = ~_GEN_241[_can_fire_load_wakeup_T_10]; // @[lsu.scala:467:33, :507:31]
wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:505:88, :506:88, :507:31]
wire [4:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13;
wire _can_fire_load_wakeup_T_15 = ~_GEN_242[_can_fire_load_wakeup_T_14]; // @[lsu.scala:468:33, :508:31]
wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:506:88, :507:88, :508:31]
wire _can_fire_load_wakeup_T_17 = ~store_needs_order; // @[lsu.scala:406:35, :470:33, :509:31]
wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:507:88, :508:88, :509:31]
wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:499:35, :510:31]
wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:508:88, :509:88, :510:31]
wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:509:88, :510:88]
wire _can_fire_load_wakeup_T_22 = ~mem_ldq_wakeup_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:213:29, :429:31, :513:84]
wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:201:7, :512:107, :513:84]
wire _can_fire_load_wakeup_T_25 = mem_ldq_wakeup_e_out_bits_st_dep_mask == 24'h0; // @[util.scala:106:23]
wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:512:107, :513:103, :514:112]
wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 | _can_fire_load_wakeup_T_26; // @[lsu.scala:512:{32,71}, :513:103]
wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:510:88, :511:88, :512:71]
wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:263:49, :511:88]
wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:263:49, :533:32]
wire can_fire_hella_incoming_0; // @[lsu.scala:517:42]
wire can_fire_hella_wakeup_0; // @[lsu.scala:520:42]
wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:520:42, :533:32]
wire _exe_tlb_valid_0_T; // @[lsu.scala:575:25]
wire exe_tlb_valid_0; // @[lsu.scala:525:27]
wire _will_fire_load_incoming_0_will_fire_T_7 = _will_fire_load_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}]
wire _will_fire_load_incoming_0_will_fire_T_11 = _will_fire_load_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65]
assign will_fire_load_incoming_0_will_fire = _will_fire_load_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
assign will_fire_load_incoming_0 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:370:38, :535:61]
wire _will_fire_load_incoming_0_T = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46]
wire _will_fire_load_incoming_0_T_3 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46]
wire _will_fire_load_incoming_0_T_6 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46]
wire _will_fire_load_incoming_0_T_1 = ~_will_fire_load_incoming_0_T; // @[lsu.scala:537:{34,46}]
wire _will_fire_load_incoming_0_T_2 = _will_fire_load_incoming_0_T_1; // @[lsu.scala:537:{31,34}]
wire _will_fire_load_incoming_0_T_4 = ~_will_fire_load_incoming_0_T_3; // @[lsu.scala:538:{34,46}]
wire _will_fire_load_incoming_0_T_5 = _will_fire_load_incoming_0_T_4; // @[lsu.scala:538:{31,34}]
wire _will_fire_load_incoming_0_T_7 = ~_will_fire_load_incoming_0_T_6; // @[lsu.scala:539:{34,46}]
wire _will_fire_load_incoming_0_T_8 = _will_fire_load_incoming_0_T_7; // @[lsu.scala:539:{31,34}]
wire _will_fire_stad_incoming_0_T_8 = _will_fire_load_incoming_0_T_8; // @[lsu.scala:539:31]
wire _will_fire_stad_incoming_0_will_fire_T = ~_will_fire_load_incoming_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_stad_incoming_0_will_fire_T_1 = _will_fire_stad_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}]
wire _will_fire_stad_incoming_0_will_fire_T_2 = ~_will_fire_stad_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}]
wire _will_fire_stad_incoming_0_will_fire_T_3 = can_fire_stad_incoming_0 & _will_fire_stad_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}]
wire _will_fire_stad_incoming_0_will_fire_T_4 = ~_will_fire_load_incoming_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_stad_incoming_0_will_fire_T_5 = _will_fire_stad_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}]
wire _will_fire_stad_incoming_0_will_fire_T_6 = ~_will_fire_stad_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}]
wire _will_fire_stad_incoming_0_will_fire_T_7 = _will_fire_stad_incoming_0_will_fire_T_3 & _will_fire_stad_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35]
wire _will_fire_stad_incoming_0_will_fire_T_11 = _will_fire_stad_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65]
wire _will_fire_stad_incoming_0_will_fire_T_8 = ~_will_fire_load_incoming_0_T_8; // @[lsu.scala:535:50, :539:31]
assign will_fire_stad_incoming_0_will_fire = _will_fire_stad_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
assign will_fire_stad_incoming_0 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:371:38, :535:61]
wire _will_fire_stad_incoming_0_T = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46]
wire _will_fire_stad_incoming_0_T_3 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46]
wire _will_fire_stad_incoming_0_T_9 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46]
wire _will_fire_stad_incoming_0_T_1 = ~_will_fire_stad_incoming_0_T; // @[lsu.scala:537:{34,46}]
wire _will_fire_stad_incoming_0_T_2 = _will_fire_load_incoming_0_T_2 & _will_fire_stad_incoming_0_T_1; // @[lsu.scala:537:{31,34}]
wire _will_fire_stad_incoming_0_T_4 = ~_will_fire_stad_incoming_0_T_3; // @[lsu.scala:538:{34,46}]
wire _will_fire_stad_incoming_0_T_5 = _will_fire_load_incoming_0_T_5 & _will_fire_stad_incoming_0_T_4; // @[lsu.scala:538:{31,34}]
wire _will_fire_sta_incoming_0_T_8 = _will_fire_stad_incoming_0_T_8; // @[lsu.scala:539:31]
wire _will_fire_stad_incoming_0_T_10 = ~_will_fire_stad_incoming_0_T_9; // @[lsu.scala:540:{34,46}]
wire _will_fire_stad_incoming_0_T_11 = _will_fire_stad_incoming_0_T_10; // @[lsu.scala:540:{31,34}]
wire _will_fire_sta_incoming_0_will_fire_T = ~_will_fire_stad_incoming_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_sta_incoming_0_will_fire_T_1 = _will_fire_sta_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}]
wire _will_fire_sta_incoming_0_will_fire_T_2 = ~_will_fire_sta_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}]
wire _will_fire_sta_incoming_0_will_fire_T_3 = can_fire_sta_incoming_0 & _will_fire_sta_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}]
wire _will_fire_sta_incoming_0_will_fire_T_4 = ~_will_fire_stad_incoming_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_sta_incoming_0_will_fire_T_5 = _will_fire_sta_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}]
wire _will_fire_sta_incoming_0_will_fire_T_6 = ~_will_fire_sta_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}]
wire _will_fire_sta_incoming_0_will_fire_T_7 = _will_fire_sta_incoming_0_will_fire_T_3 & _will_fire_sta_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35]
wire _will_fire_sta_incoming_0_will_fire_T_11 = _will_fire_sta_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65]
wire _will_fire_sta_incoming_0_will_fire_T_8 = ~_will_fire_stad_incoming_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_sta_incoming_0_will_fire_T_12 = ~_will_fire_stad_incoming_0_T_11; // @[lsu.scala:536:51, :540:31]
wire _will_fire_sta_incoming_0_will_fire_T_13 = _will_fire_sta_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}]
wire _will_fire_sta_incoming_0_will_fire_T_14 = ~_will_fire_sta_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}]
assign will_fire_sta_incoming_0_will_fire = _will_fire_sta_incoming_0_will_fire_T_11 & _will_fire_sta_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35]
assign will_fire_sta_incoming_0 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:372:38, :535:61]
wire _will_fire_sta_incoming_0_T = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46]
wire _will_fire_sta_incoming_0_T_3 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46]
wire _will_fire_sta_incoming_0_T_9 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46]
wire _will_fire_sta_incoming_0_T_1 = ~_will_fire_sta_incoming_0_T; // @[lsu.scala:537:{34,46}]
wire _will_fire_sta_incoming_0_T_2 = _will_fire_stad_incoming_0_T_2 & _will_fire_sta_incoming_0_T_1; // @[lsu.scala:537:{31,34}]
wire _will_fire_std_incoming_0_T_2 = _will_fire_sta_incoming_0_T_2; // @[lsu.scala:537:31]
wire _will_fire_sta_incoming_0_T_4 = ~_will_fire_sta_incoming_0_T_3; // @[lsu.scala:538:{34,46}]
wire _will_fire_sta_incoming_0_T_5 = _will_fire_stad_incoming_0_T_5 & _will_fire_sta_incoming_0_T_4; // @[lsu.scala:538:{31,34}]
wire _will_fire_std_incoming_0_T_5 = _will_fire_sta_incoming_0_T_5; // @[lsu.scala:538:31]
wire _will_fire_std_incoming_0_T_8 = _will_fire_sta_incoming_0_T_8; // @[lsu.scala:539:31]
wire _will_fire_sta_incoming_0_T_10 = ~_will_fire_sta_incoming_0_T_9; // @[lsu.scala:540:{34,46}]
wire _will_fire_sta_incoming_0_T_11 = _will_fire_stad_incoming_0_T_11 & _will_fire_sta_incoming_0_T_10; // @[lsu.scala:540:{31,34}]
wire _will_fire_std_incoming_0_will_fire_T = ~_will_fire_sta_incoming_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_std_incoming_0_will_fire_T_7 = _will_fire_std_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}]
wire _will_fire_std_incoming_0_will_fire_T_4 = ~_will_fire_sta_incoming_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_std_incoming_0_will_fire_T_11 = _will_fire_std_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65]
wire _will_fire_std_incoming_0_will_fire_T_8 = ~_will_fire_sta_incoming_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_std_incoming_0_will_fire_T_12 = ~_will_fire_sta_incoming_0_T_11; // @[lsu.scala:536:51, :540:31]
wire _will_fire_std_incoming_0_will_fire_T_13 = _will_fire_std_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}]
wire _will_fire_std_incoming_0_will_fire_T_14 = ~_will_fire_std_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}]
assign will_fire_std_incoming_0_will_fire = _will_fire_std_incoming_0_will_fire_T_11 & _will_fire_std_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35]
assign will_fire_std_incoming_0 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:373:38, :535:61]
wire _will_fire_std_incoming_0_T_9 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46]
wire _will_fire_sfence_0_T_5 = _will_fire_std_incoming_0_T_5; // @[lsu.scala:538:31]
wire _will_fire_sfence_0_T_8 = _will_fire_std_incoming_0_T_8; // @[lsu.scala:539:31]
wire _will_fire_std_incoming_0_T_10 = ~_will_fire_std_incoming_0_T_9; // @[lsu.scala:540:{34,46}]
wire _will_fire_std_incoming_0_T_11 = _will_fire_sta_incoming_0_T_11 & _will_fire_std_incoming_0_T_10; // @[lsu.scala:540:{31,34}]
wire _will_fire_sfence_0_will_fire_T = ~_will_fire_std_incoming_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_sfence_0_will_fire_T_1 = _will_fire_sfence_0_will_fire_T; // @[lsu.scala:533:{48,51}]
wire _will_fire_sfence_0_will_fire_T_2 = ~_will_fire_sfence_0_will_fire_T_1; // @[lsu.scala:533:{35,48}]
wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0 & _will_fire_sfence_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}]
wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:533:{32,63}]
wire _will_fire_sfence_0_will_fire_T_4 = ~_will_fire_std_incoming_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_sfence_0_will_fire_T_11 = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65]
wire _will_fire_sfence_0_will_fire_T_8 = ~_will_fire_std_incoming_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_sfence_0_will_fire_T_12 = ~_will_fire_std_incoming_0_T_11; // @[lsu.scala:536:51, :540:31]
wire _will_fire_sfence_0_will_fire_T_13 = _will_fire_sfence_0_will_fire_T_12; // @[lsu.scala:536:{48,51}]
wire _will_fire_sfence_0_will_fire_T_14 = ~_will_fire_sfence_0_will_fire_T_13; // @[lsu.scala:536:{35,48}]
assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_11 & _will_fire_sfence_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35]
assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:374:38, :535:61]
wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :537:46]
wire _will_fire_sfence_0_T_9 = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :540:46]
wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:537:{34,46}]
wire _will_fire_sfence_0_T_2 = _will_fire_std_incoming_0_T_2 & _will_fire_sfence_0_T_1; // @[lsu.scala:537:{31,34}]
wire _will_fire_release_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:537:31]
wire _will_fire_release_0_T_8 = _will_fire_sfence_0_T_8; // @[lsu.scala:539:31]
wire _will_fire_sfence_0_T_10 = ~_will_fire_sfence_0_T_9; // @[lsu.scala:540:{34,46}]
wire _will_fire_sfence_0_T_11 = _will_fire_std_incoming_0_T_11 & _will_fire_sfence_0_T_10; // @[lsu.scala:540:{31,34}]
wire _will_fire_release_0_T_11 = _will_fire_sfence_0_T_11; // @[lsu.scala:540:31]
wire _will_fire_release_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_sfence_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:534:{49,52}]
wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:534:{35,49}]
wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35]
wire _will_fire_release_0_will_fire_T_11 = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65]
wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_sfence_0_T_8; // @[lsu.scala:535:50, :539:31]
assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
wire _will_fire_release_0_will_fire_T_12 = ~_will_fire_sfence_0_T_11; // @[lsu.scala:536:51, :540:31]
assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:377:38, :535:61]
wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:535:61, :538:46]
wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:538:{34,46}]
wire _will_fire_release_0_T_5 = _will_fire_sfence_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:538:{31,34}]
wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:538:31]
wire _will_fire_hella_incoming_0_T_11 = _will_fire_release_0_T_11; // @[lsu.scala:540:31]
wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}]
wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}]
wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:517:42, :533:{32,35}]
wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}]
wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:535:{47,50}]
wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:535:{35,47}]
wire _will_fire_hella_incoming_0_will_fire_T_11 = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35]
assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
wire _will_fire_hella_incoming_0_will_fire_T_12 = ~_will_fire_release_0_T_11; // @[lsu.scala:536:51, :540:31]
assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:375:38, :535:61]
wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46]
wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46]
wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:537:{34,46}]
wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:537:{31,34}]
wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:537:31]
wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:538:31]
wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:539:{34,46}]
wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:539:{31,34}]
wire _will_fire_hella_wakeup_0_T_11 = _will_fire_hella_incoming_0_T_11; // @[lsu.scala:540:31]
wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:533:{32,63}]
wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}]
wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}]
wire _will_fire_hella_wakeup_0_will_fire_T_11 = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35]
assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
wire _will_fire_hella_wakeup_0_will_fire_T_12 = ~_will_fire_hella_incoming_0_T_11; // @[lsu.scala:536:51, :540:31]
assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:376:38, :535:61]
wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46]
wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:539:{34,46}]
wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:539:{31,34}]
wire _will_fire_load_retry_0_T_11 = _will_fire_hella_wakeup_0_T_11; // @[lsu.scala:540:31]
wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}]
wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}]
wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}]
wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}]
wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}]
wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35]
wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:535:{47,50}]
wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:535:{35,47}]
wire _will_fire_load_retry_0_will_fire_T_11 = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35]
assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
wire _will_fire_load_retry_0_will_fire_T_12 = ~_will_fire_hella_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31]
assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:378:38, :535:61]
wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :537:46]
wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :538:46]
wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :539:46]
wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:537:{34,46}]
wire _will_fire_load_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:537:{31,34}]
wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:538:{34,46}]
wire _will_fire_load_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:538:{31,34}]
wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:539:{34,46}]
wire _will_fire_load_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:539:{31,34}]
wire _will_fire_sta_retry_0_T_8 = _will_fire_load_retry_0_T_8; // @[lsu.scala:539:31]
wire _will_fire_sta_retry_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_sta_retry_0_will_fire_T_1 = _will_fire_sta_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}]
wire _will_fire_sta_retry_0_will_fire_T_2 = ~_will_fire_sta_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}]
wire _will_fire_sta_retry_0_will_fire_T_3 = can_fire_sta_retry_0 & _will_fire_sta_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}]
wire _will_fire_sta_retry_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_sta_retry_0_will_fire_T_5 = _will_fire_sta_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}]
wire _will_fire_sta_retry_0_will_fire_T_6 = ~_will_fire_sta_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}]
wire _will_fire_sta_retry_0_will_fire_T_7 = _will_fire_sta_retry_0_will_fire_T_3 & _will_fire_sta_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35]
wire _will_fire_sta_retry_0_will_fire_T_11 = _will_fire_sta_retry_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65]
wire _will_fire_sta_retry_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_sta_retry_0_will_fire_T_12 = ~_will_fire_load_retry_0_T_11; // @[lsu.scala:536:51, :540:31]
wire _will_fire_sta_retry_0_will_fire_T_13 = _will_fire_sta_retry_0_will_fire_T_12; // @[lsu.scala:536:{48,51}]
wire _will_fire_sta_retry_0_will_fire_T_14 = ~_will_fire_sta_retry_0_will_fire_T_13; // @[lsu.scala:536:{35,48}]
assign will_fire_sta_retry_0_will_fire = _will_fire_sta_retry_0_will_fire_T_11 & _will_fire_sta_retry_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35]
assign will_fire_sta_retry_0 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:379:38, :535:61]
wire _will_fire_sta_retry_0_T = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :537:46]
wire _will_fire_sta_retry_0_T_3 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :538:46]
wire _will_fire_sta_retry_0_T_9 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :540:46]
wire _will_fire_sta_retry_0_T_1 = ~_will_fire_sta_retry_0_T; // @[lsu.scala:537:{34,46}]
wire _will_fire_sta_retry_0_T_2 = _will_fire_load_retry_0_T_2 & _will_fire_sta_retry_0_T_1; // @[lsu.scala:537:{31,34}]
wire _will_fire_load_wakeup_0_T_2 = _will_fire_sta_retry_0_T_2; // @[lsu.scala:537:31]
wire _will_fire_sta_retry_0_T_4 = ~_will_fire_sta_retry_0_T_3; // @[lsu.scala:538:{34,46}]
wire _will_fire_sta_retry_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_sta_retry_0_T_4; // @[lsu.scala:538:{31,34}]
wire _will_fire_sta_retry_0_T_10 = ~_will_fire_sta_retry_0_T_9; // @[lsu.scala:540:{34,46}]
wire _will_fire_sta_retry_0_T_11 = _will_fire_load_retry_0_T_11 & _will_fire_sta_retry_0_T_10; // @[lsu.scala:540:{31,34}]
wire _will_fire_load_wakeup_0_T_11 = _will_fire_sta_retry_0_T_11; // @[lsu.scala:540:31]
wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_sta_retry_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_sta_retry_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:534:{49,52}]
wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:534:{35,49}]
wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35]
wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_sta_retry_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}]
wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}]
wire _will_fire_load_wakeup_0_will_fire_T_11 = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35]
assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
wire _will_fire_load_wakeup_0_will_fire_T_12 = ~_will_fire_sta_retry_0_T_11; // @[lsu.scala:536:51, :540:31]
assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:381:38, :535:61]
wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :538:46]
wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46]
wire _will_fire_store_commit_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:537:31]
wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:538:{34,46}]
wire _will_fire_load_wakeup_0_T_5 = _will_fire_sta_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:538:{31,34}]
wire _will_fire_store_commit_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:538:31]
wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:539:{34,46}]
wire _will_fire_load_wakeup_0_T_8 = _will_fire_sta_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:539:{31,34}]
wire _will_fire_store_commit_0_T_11 = _will_fire_load_wakeup_0_T_11; // @[lsu.scala:540:31]
wire _will_fire_store_commit_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31]
wire _will_fire_store_commit_0_will_fire_T_7 = _will_fire_store_commit_0_will_fire_T_3; // @[lsu.scala:533:{32,63}]
wire _will_fire_store_commit_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31]
wire _will_fire_store_commit_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31]
wire _will_fire_store_commit_0_will_fire_T_9 = _will_fire_store_commit_0_will_fire_T_8; // @[lsu.scala:535:{47,50}]
wire _will_fire_store_commit_0_will_fire_T_10 = ~_will_fire_store_commit_0_will_fire_T_9; // @[lsu.scala:535:{35,47}]
wire _will_fire_store_commit_0_will_fire_T_11 = _will_fire_store_commit_0_will_fire_T_7 & _will_fire_store_commit_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35]
assign will_fire_store_commit_0_will_fire = _will_fire_store_commit_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61]
wire _will_fire_store_commit_0_will_fire_T_12 = ~_will_fire_load_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31]
assign will_fire_store_commit_0 = will_fire_store_commit_0_will_fire; // @[lsu.scala:380:38, :535:61]
wire _will_fire_store_commit_0_T_6 = will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61, :539:46]
wire _will_fire_store_commit_0_T_7 = ~_will_fire_store_commit_0_T_6; // @[lsu.scala:539:{34,46}]
wire _will_fire_store_commit_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_0_T_7; // @[lsu.scala:539:{31,34}]
wire _T_189 = will_fire_load_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:370:38, :371:38, :566:63]
wire _exe_tlb_uop_T; // @[lsu.scala:596:53]
assign _exe_tlb_uop_T = _T_189; // @[lsu.scala:566:63, :596:53]
wire _exe_tlb_vaddr_T; // @[lsu.scala:606:53]
assign _exe_tlb_vaddr_T = _T_189; // @[lsu.scala:566:63, :606:53]
wire _exe_size_T; // @[lsu.scala:623:52]
assign _exe_size_T = _T_189; // @[lsu.scala:566:63, :623:52]
wire _exe_cmd_T; // @[lsu.scala:632:52]
assign _exe_cmd_T = _T_189; // @[lsu.scala:566:63, :632:52]
wire _GEN_243 = ldq_wakeup_idx == 5'h0; // @[lsu.scala:429:31, :569:49]
wire _GEN_244 = ldq_wakeup_idx == 5'h1; // @[lsu.scala:429:31, :569:49]
wire _GEN_245 = ldq_wakeup_idx == 5'h2; // @[lsu.scala:429:31, :569:49]
wire _GEN_246 = ldq_wakeup_idx == 5'h3; // @[lsu.scala:429:31, :569:49]
wire _GEN_247 = ldq_wakeup_idx == 5'h4; // @[lsu.scala:429:31, :569:49]
wire _GEN_248 = ldq_wakeup_idx == 5'h5; // @[lsu.scala:429:31, :569:49]
wire _GEN_249 = ldq_wakeup_idx == 5'h6; // @[lsu.scala:429:31, :569:49]
wire _GEN_250 = ldq_wakeup_idx == 5'h7; // @[lsu.scala:429:31, :569:49]
wire _GEN_251 = ldq_wakeup_idx == 5'h8; // @[lsu.scala:429:31, :569:49]
wire _GEN_252 = ldq_wakeup_idx == 5'h9; // @[lsu.scala:429:31, :569:49]
wire _GEN_253 = ldq_wakeup_idx == 5'hA; // @[lsu.scala:429:31, :569:49]
wire _GEN_254 = ldq_wakeup_idx == 5'hB; // @[lsu.scala:429:31, :569:49]
wire _GEN_255 = ldq_wakeup_idx == 5'hC; // @[lsu.scala:429:31, :569:49]
wire _GEN_256 = ldq_wakeup_idx == 5'hD; // @[lsu.scala:429:31, :569:49]
wire _GEN_257 = ldq_wakeup_idx == 5'hE; // @[lsu.scala:429:31, :569:49]
wire _GEN_258 = ldq_wakeup_idx == 5'hF; // @[lsu.scala:429:31, :569:49]
wire _GEN_259 = ldq_wakeup_idx == 5'h10; // @[lsu.scala:429:31, :569:49]
wire _GEN_260 = ldq_wakeup_idx == 5'h11; // @[lsu.scala:429:31, :569:49]
wire _GEN_261 = ldq_wakeup_idx == 5'h12; // @[lsu.scala:429:31, :569:49]
wire _GEN_262 = ldq_wakeup_idx == 5'h13; // @[lsu.scala:429:31, :569:49]
wire _GEN_263 = ldq_wakeup_idx == 5'h14; // @[lsu.scala:429:31, :569:49]
wire _GEN_264 = ldq_wakeup_idx == 5'h15; // @[lsu.scala:429:31, :569:49]
wire _GEN_265 = ldq_wakeup_idx == 5'h16; // @[lsu.scala:429:31, :569:49]
wire _GEN_266 = ldq_wakeup_idx == 5'h17; // @[lsu.scala:429:31, :569:49]
wire _GEN_267 = ldq_retry_idx == 5'h0; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_243 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h0 : will_fire_load_retry_0 & _GEN_267; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_268 = ldq_retry_idx == 5'h1; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_244 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h1 : will_fire_load_retry_0 & _GEN_268; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_269 = ldq_retry_idx == 5'h2; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_245 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h2 : will_fire_load_retry_0 & _GEN_269; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_270 = ldq_retry_idx == 5'h3; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_246 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h3 : will_fire_load_retry_0 & _GEN_270; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_271 = ldq_retry_idx == 5'h4; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_247 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h4 : will_fire_load_retry_0 & _GEN_271; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_272 = ldq_retry_idx == 5'h5; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_248 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h5 : will_fire_load_retry_0 & _GEN_272; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_273 = ldq_retry_idx == 5'h6; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_249 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h6 : will_fire_load_retry_0 & _GEN_273; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_274 = ldq_retry_idx == 5'h7; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_7 = will_fire_load_wakeup_0 ? _GEN_250 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h7 : will_fire_load_retry_0 & _GEN_274; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_275 = ldq_retry_idx == 5'h8; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_8 = will_fire_load_wakeup_0 ? _GEN_251 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h8 : will_fire_load_retry_0 & _GEN_275; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_276 = ldq_retry_idx == 5'h9; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_9 = will_fire_load_wakeup_0 ? _GEN_252 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h9 : will_fire_load_retry_0 & _GEN_276; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_277 = ldq_retry_idx == 5'hA; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_10 = will_fire_load_wakeup_0 ? _GEN_253 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hA : will_fire_load_retry_0 & _GEN_277; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_278 = ldq_retry_idx == 5'hB; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_11 = will_fire_load_wakeup_0 ? _GEN_254 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hB : will_fire_load_retry_0 & _GEN_278; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_279 = ldq_retry_idx == 5'hC; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_12 = will_fire_load_wakeup_0 ? _GEN_255 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hC : will_fire_load_retry_0 & _GEN_279; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_280 = ldq_retry_idx == 5'hD; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_13 = will_fire_load_wakeup_0 ? _GEN_256 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hD : will_fire_load_retry_0 & _GEN_280; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_281 = ldq_retry_idx == 5'hE; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_14 = will_fire_load_wakeup_0 ? _GEN_257 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hE : will_fire_load_retry_0 & _GEN_281; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_282 = ldq_retry_idx == 5'hF; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_15 = will_fire_load_wakeup_0 ? _GEN_258 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hF : will_fire_load_retry_0 & _GEN_282; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_283 = ldq_retry_idx == 5'h10; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_16 = will_fire_load_wakeup_0 ? _GEN_259 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h10 : will_fire_load_retry_0 & _GEN_283; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_284 = ldq_retry_idx == 5'h11; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_17 = will_fire_load_wakeup_0 ? _GEN_260 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h11 : will_fire_load_retry_0 & _GEN_284; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_285 = ldq_retry_idx == 5'h12; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_18 = will_fire_load_wakeup_0 ? _GEN_261 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h12 : will_fire_load_retry_0 & _GEN_285; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_286 = ldq_retry_idx == 5'h13; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_19 = will_fire_load_wakeup_0 ? _GEN_262 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h13 : will_fire_load_retry_0 & _GEN_286; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_287 = ldq_retry_idx == 5'h14; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_20 = will_fire_load_wakeup_0 ? _GEN_263 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h14 : will_fire_load_retry_0 & _GEN_287; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_288 = ldq_retry_idx == 5'h15; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_21 = will_fire_load_wakeup_0 ? _GEN_264 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h15 : will_fire_load_retry_0 & _GEN_288; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_289 = ldq_retry_idx == 5'h16; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_22 = will_fire_load_wakeup_0 ? _GEN_265 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h16 : will_fire_load_retry_0 & _GEN_289; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
wire _GEN_290 = ldq_retry_idx == 5'h17; // @[lsu.scala:414:30, :573:49]
assign block_load_mask_23 = will_fire_load_wakeup_0 ? _GEN_266 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h17 : will_fire_load_retry_0 & _GEN_290; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49]
assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_0_T_2; // @[lsu.scala:537:31, :575:25]
assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:525:27, :575:25]
wire _exe_tlb_uop_T_1 = _exe_tlb_uop_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :596:53, :597:53]
wire _exe_tlb_uop_T_2 = _exe_tlb_uop_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :597:53, :598:53]
wire [6:0] _exe_tlb_uop_T_4_uopc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23]
wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23]
wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_rvc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_rvc; // @[util.scala:106:23]
wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_4_iq_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23]
wire [9:0] _exe_tlb_uop_T_4_fu_code = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23]
wire [3:0] _exe_tlb_uop_T_4_ctrl_br_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_ctrl_op1_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_4_ctrl_op2_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_4_ctrl_imm_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_4_ctrl_op_fcn = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_ctrl_fcn_dw = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_4_ctrl_csr_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_ctrl_is_load = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_ctrl_is_sta = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_ctrl_is_std = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_iw_state = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_iw_p1_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_iw_p2_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_br = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_br; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_jalr = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jalr; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_jal = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jal; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_sfb = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sfb; // @[util.scala:106:23]
wire [15:0] _exe_tlb_uop_T_4_br_mask = will_fire_sta_retry_0 ? _GEN_25[_stq_retry_e_T_1] : 16'h0; // @[lsu.scala:222:42, :379:38, :477:79, :601:24]
wire [3:0] _exe_tlb_uop_T_4_br_tag = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_br_tag : 4'h0; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ftq_idx : 5'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_edge_inst = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_edge_inst; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_taken = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_taken; // @[util.scala:106:23]
wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23]
wire [11:0] _exe_tlb_uop_T_4_csr_addr = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_4_rob_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rob_idx : 7'h0; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldq_idx : 5'h0; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_4_stq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stq_idx : 5'h0; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_4_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pdst : 7'h0; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_4_prs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs1 : 7'h0; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_4_prs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs2 : 7'h0; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_4_prs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs3 : 7'h0; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_4_ppred = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ppred : 5'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_prs1_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs1_busy; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_prs2_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs2_busy; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_prs3_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs3_busy; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_ppred_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ppred_busy; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stale_pdst : 7'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_exception = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_exception; // @[util.scala:106:23]
wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_bypassable = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bypassable; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_size : 2'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_mem_signed = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_mem_signed; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_fence = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fence; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_fencei = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fencei; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_amo = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_amo; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_uses_ldq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_ldq; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_uses_stq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_stq; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_is_unique = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_unique; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_ldst_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_val; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_frs3_en = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_frs3_en; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_fp_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_val; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_fp_single = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_single; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_5_uopc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uopc : _exe_tlb_uop_T_4_uopc; // @[util.scala:106:23]
wire [31:0] _exe_tlb_uop_T_5_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[util.scala:106:23]
wire [31:0] _exe_tlb_uop_T_5_debug_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_rvc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[util.scala:106:23]
wire [39:0] _exe_tlb_uop_T_5_debug_pc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_5_iq_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iq_type : _exe_tlb_uop_T_4_iq_type; // @[util.scala:106:23]
wire [9:0] _exe_tlb_uop_T_5_fu_code = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fu_code : _exe_tlb_uop_T_4_fu_code; // @[util.scala:106:23]
wire [3:0] _exe_tlb_uop_T_5_ctrl_br_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_br_type : _exe_tlb_uop_T_4_ctrl_br_type; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_ctrl_op1_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_4_ctrl_op1_sel; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_5_ctrl_op2_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_4_ctrl_op2_sel; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_5_ctrl_imm_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_4_ctrl_imm_sel; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_5_ctrl_op_fcn = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_4_ctrl_op_fcn; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_ctrl_fcn_dw = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_4_ctrl_fcn_dw; // @[util.scala:106:23]
wire [2:0] _exe_tlb_uop_T_5_ctrl_csr_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_4_ctrl_csr_cmd; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_ctrl_is_load = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_load : _exe_tlb_uop_T_4_ctrl_is_load; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_ctrl_is_sta = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_4_ctrl_is_sta; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_ctrl_is_std = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_std : _exe_tlb_uop_T_4_ctrl_is_std; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_iw_state = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_state : _exe_tlb_uop_T_4_iw_state; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_iw_p1_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_4_iw_p1_poisoned; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_iw_p2_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_4_iw_p2_poisoned; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_br = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_br : _exe_tlb_uop_T_4_is_br; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_jalr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jalr : _exe_tlb_uop_T_4_is_jalr; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_jal = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jal : _exe_tlb_uop_T_4_is_jal; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_sfb = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[util.scala:106:23]
wire [15:0] _exe_tlb_uop_T_5_br_mask = will_fire_load_retry_0 ? _GEN_125[_ldq_retry_e_T_1] : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:263:49, :378:38, :464:79, :600:24, :601:24]
wire [3:0] _exe_tlb_uop_T_5_br_tag = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_5_ftq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_edge_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_5_pc_lob = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_taken = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[util.scala:106:23]
wire [19:0] _exe_tlb_uop_T_5_imm_packed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[util.scala:106:23]
wire [11:0] _exe_tlb_uop_T_5_csr_addr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_csr_addr : _exe_tlb_uop_T_4_csr_addr; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_5_rob_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_5_ldq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_5_stq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_rxq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_5_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_5_prs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_5_prs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_5_prs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_5_ppred = will_fire_load_retry_0 ? 5'h0 : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:378:38, :600:24, :601:24]
wire _exe_tlb_uop_T_5_prs1_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_prs2_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_prs3_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_ppred_busy = ~will_fire_load_retry_0 & _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:378:38, :600:24, :601:24]
wire [6:0] _exe_tlb_uop_T_5_stale_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_exception = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[util.scala:106:23]
wire [63:0] _exe_tlb_uop_T_5_exc_cause = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_bypassable = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bypassable : _exe_tlb_uop_T_4_bypassable; // @[util.scala:106:23]
wire [4:0] _exe_tlb_uop_T_5_mem_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_mem_size = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_mem_signed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_fence = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_fencei = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_amo = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_uses_ldq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_uses_stq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_sys_pc2epc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_is_unique = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_flush_on_commit = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_ldst_is_rs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_5_ldst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_5_lrs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_5_lrs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[util.scala:106:23]
wire [5:0] _exe_tlb_uop_T_5_lrs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_ldst_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_val : _exe_tlb_uop_T_4_ldst_val; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_dst_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_frs3_en = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_fp_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_fp_single = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_single : _exe_tlb_uop_T_4_fp_single; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_xcpt_pf_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_xcpt_ae_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_xcpt_ma_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_bp_debug_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[util.scala:106:23]
wire _exe_tlb_uop_T_5_bp_xcpt_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_debug_fsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[util.scala:106:23]
wire [1:0] _exe_tlb_uop_T_5_debug_tsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[util.scala:106:23]
wire [6:0] _exe_tlb_uop_T_6_uopc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uopc : _exe_tlb_uop_T_5_uopc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [31:0] _exe_tlb_uop_T_6_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_inst : _exe_tlb_uop_T_5_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [31:0] _exe_tlb_uop_T_6_debug_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_inst : _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_rvc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_rvc : _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [39:0] _exe_tlb_uop_T_6_debug_pc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_pc : _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [2:0] _exe_tlb_uop_T_6_iq_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iq_type : _exe_tlb_uop_T_5_iq_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [9:0] _exe_tlb_uop_T_6_fu_code = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fu_code : _exe_tlb_uop_T_5_fu_code; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [3:0] _exe_tlb_uop_T_6_ctrl_br_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_br_type : _exe_tlb_uop_T_5_ctrl_br_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_ctrl_op1_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_5_ctrl_op1_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [2:0] _exe_tlb_uop_T_6_ctrl_op2_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_5_ctrl_op2_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [2:0] _exe_tlb_uop_T_6_ctrl_imm_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_5_ctrl_imm_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [4:0] _exe_tlb_uop_T_6_ctrl_op_fcn = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_5_ctrl_op_fcn; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_ctrl_fcn_dw = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_5_ctrl_fcn_dw; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [2:0] _exe_tlb_uop_T_6_ctrl_csr_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_5_ctrl_csr_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_ctrl_is_load = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_load : _exe_tlb_uop_T_5_ctrl_is_load; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_ctrl_is_sta = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_5_ctrl_is_sta; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_ctrl_is_std = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_std : _exe_tlb_uop_T_5_ctrl_is_std; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_iw_state = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_state : _exe_tlb_uop_T_5_iw_state; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_iw_p1_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_5_iw_p1_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_iw_p2_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_5_iw_p2_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_br = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_br : _exe_tlb_uop_T_5_is_br; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_jalr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jalr : _exe_tlb_uop_T_5_is_jalr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_jal = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jal : _exe_tlb_uop_T_5_is_jal; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_sfb = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sfb : _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [15:0] _exe_tlb_uop_T_6_br_mask = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_mask : _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [3:0] _exe_tlb_uop_T_6_br_tag = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_tag : _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [4:0] _exe_tlb_uop_T_6_ftq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ftq_idx : _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_edge_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_edge_inst : _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [5:0] _exe_tlb_uop_T_6_pc_lob = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pc_lob : _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_taken = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_taken : _exe_tlb_uop_T_5_taken; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [19:0] _exe_tlb_uop_T_6_imm_packed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_imm_packed : _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [11:0] _exe_tlb_uop_T_6_csr_addr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_csr_addr : _exe_tlb_uop_T_5_csr_addr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [6:0] _exe_tlb_uop_T_6_rob_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rob_idx : _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [4:0] _exe_tlb_uop_T_6_ldq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldq_idx : _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [4:0] _exe_tlb_uop_T_6_stq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stq_idx : _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_rxq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rxq_idx : _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [6:0] _exe_tlb_uop_T_6_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pdst : _exe_tlb_uop_T_5_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [6:0] _exe_tlb_uop_T_6_prs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1 : _exe_tlb_uop_T_5_prs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [6:0] _exe_tlb_uop_T_6_prs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2 : _exe_tlb_uop_T_5_prs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [6:0] _exe_tlb_uop_T_6_prs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3 : _exe_tlb_uop_T_5_prs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [4:0] _exe_tlb_uop_T_6_ppred = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred : _exe_tlb_uop_T_5_ppred; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_prs1_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1_busy : _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_prs2_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2_busy : _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_prs3_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3_busy : _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_ppred_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred_busy : _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [6:0] _exe_tlb_uop_T_6_stale_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stale_pdst : _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_exception = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exception : _exe_tlb_uop_T_5_exception; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [63:0] _exe_tlb_uop_T_6_exc_cause = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exc_cause : _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_bypassable = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bypassable : _exe_tlb_uop_T_5_bypassable; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [4:0] _exe_tlb_uop_T_6_mem_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_cmd : _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_mem_size = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_size : _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_mem_signed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_signed : _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_fence = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fence : _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_fencei = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fencei : _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_amo = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_amo : _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_uses_ldq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_ldq : _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_uses_stq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_stq : _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_sys_pc2epc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_is_unique = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_unique : _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_flush_on_commit = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_ldst_is_rs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [5:0] _exe_tlb_uop_T_6_ldst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst : _exe_tlb_uop_T_5_ldst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [5:0] _exe_tlb_uop_T_6_lrs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1 : _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [5:0] _exe_tlb_uop_T_6_lrs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2 : _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [5:0] _exe_tlb_uop_T_6_lrs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs3 : _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_ldst_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_val : _exe_tlb_uop_T_5_ldst_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_dst_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_dst_rtype : _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_lrs1_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_lrs2_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_frs3_en = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_frs3_en : _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_fp_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_val : _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_fp_single = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_single : _exe_tlb_uop_T_5_fp_single; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_xcpt_pf_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_xcpt_ae_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_xcpt_ma_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_bp_debug_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire _exe_tlb_uop_T_6_bp_xcpt_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_debug_fsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [1:0] _exe_tlb_uop_T_6_debug_tsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24]
wire [6:0] exe_tlb_uop_0_uopc = _exe_tlb_uop_T_6_uopc; // @[lsu.scala:263:49, :596:24]
wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_6_inst; // @[lsu.scala:263:49, :596:24]
wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_6_debug_inst; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_6_is_rvc; // @[lsu.scala:263:49, :596:24]
wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_6_debug_pc; // @[lsu.scala:263:49, :596:24]
wire [2:0] exe_tlb_uop_0_iq_type = _exe_tlb_uop_T_6_iq_type; // @[lsu.scala:263:49, :596:24]
wire [9:0] exe_tlb_uop_0_fu_code = _exe_tlb_uop_T_6_fu_code; // @[lsu.scala:263:49, :596:24]
wire [3:0] exe_tlb_uop_0_ctrl_br_type = _exe_tlb_uop_T_6_ctrl_br_type; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_ctrl_op1_sel = _exe_tlb_uop_T_6_ctrl_op1_sel; // @[lsu.scala:263:49, :596:24]
wire [2:0] exe_tlb_uop_0_ctrl_op2_sel = _exe_tlb_uop_T_6_ctrl_op2_sel; // @[lsu.scala:263:49, :596:24]
wire [2:0] exe_tlb_uop_0_ctrl_imm_sel = _exe_tlb_uop_T_6_ctrl_imm_sel; // @[lsu.scala:263:49, :596:24]
wire [4:0] exe_tlb_uop_0_ctrl_op_fcn = _exe_tlb_uop_T_6_ctrl_op_fcn; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_ctrl_fcn_dw = _exe_tlb_uop_T_6_ctrl_fcn_dw; // @[lsu.scala:263:49, :596:24]
wire [2:0] exe_tlb_uop_0_ctrl_csr_cmd = _exe_tlb_uop_T_6_ctrl_csr_cmd; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_ctrl_is_load = _exe_tlb_uop_T_6_ctrl_is_load; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_ctrl_is_sta = _exe_tlb_uop_T_6_ctrl_is_sta; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_ctrl_is_std = _exe_tlb_uop_T_6_ctrl_is_std; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_iw_state = _exe_tlb_uop_T_6_iw_state; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_iw_p1_poisoned = _exe_tlb_uop_T_6_iw_p1_poisoned; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_iw_p2_poisoned = _exe_tlb_uop_T_6_iw_p2_poisoned; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_br = _exe_tlb_uop_T_6_is_br; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_jalr = _exe_tlb_uop_T_6_is_jalr; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_jal = _exe_tlb_uop_T_6_is_jal; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_6_is_sfb; // @[lsu.scala:263:49, :596:24]
wire [15:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_6_br_mask; // @[lsu.scala:263:49, :596:24]
wire [3:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_6_br_tag; // @[lsu.scala:263:49, :596:24]
wire [4:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_6_ftq_idx; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_6_edge_inst; // @[lsu.scala:263:49, :596:24]
wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_6_pc_lob; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_6_taken; // @[lsu.scala:263:49, :596:24]
wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_6_imm_packed; // @[lsu.scala:263:49, :596:24]
wire [11:0] exe_tlb_uop_0_csr_addr = _exe_tlb_uop_T_6_csr_addr; // @[lsu.scala:263:49, :596:24]
wire [6:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_6_rob_idx; // @[lsu.scala:263:49, :596:24]
wire [4:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_6_ldq_idx; // @[lsu.scala:263:49, :596:24]
wire [4:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_6_stq_idx; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_6_rxq_idx; // @[lsu.scala:263:49, :596:24]
wire [6:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_6_pdst; // @[lsu.scala:263:49, :596:24]
wire [6:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_6_prs1; // @[lsu.scala:263:49, :596:24]
wire [6:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_6_prs2; // @[lsu.scala:263:49, :596:24]
wire [6:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_6_prs3; // @[lsu.scala:263:49, :596:24]
wire [4:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_6_ppred; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_6_prs1_busy; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_6_prs2_busy; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_6_prs3_busy; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_6_ppred_busy; // @[lsu.scala:263:49, :596:24]
wire [6:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_6_stale_pdst; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_6_exception; // @[lsu.scala:263:49, :596:24]
wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_6_exc_cause; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_bypassable = _exe_tlb_uop_T_6_bypassable; // @[lsu.scala:263:49, :596:24]
wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_6_mem_cmd; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_6_mem_size; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_6_mem_signed; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_6_is_fence; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_6_is_fencei; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_6_is_amo; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_6_uses_ldq; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_6_uses_stq; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_6_is_sys_pc2epc; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_6_is_unique; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_6_flush_on_commit; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_6_ldst_is_rs1; // @[lsu.scala:263:49, :596:24]
wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_6_ldst; // @[lsu.scala:263:49, :596:24]
wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_6_lrs1; // @[lsu.scala:263:49, :596:24]
wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_6_lrs2; // @[lsu.scala:263:49, :596:24]
wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_6_lrs3; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_ldst_val = _exe_tlb_uop_T_6_ldst_val; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_6_dst_rtype; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_6_lrs1_rtype; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_6_lrs2_rtype; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_6_frs3_en; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_6_fp_val; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_fp_single = _exe_tlb_uop_T_6_fp_single; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_6_xcpt_pf_if; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_6_xcpt_ae_if; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_6_xcpt_ma_if; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_6_bp_debug_if; // @[lsu.scala:263:49, :596:24]
wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_6_bp_xcpt_if; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_6_debug_fsrc; // @[lsu.scala:263:49, :596:24]
wire [1:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_6_debug_tsrc; // @[lsu.scala:263:49, :596:24]
wire [6:0] mem_xcpt_uops_out_uopc = exe_tlb_uop_0_uopc; // @[util.scala:96:23]
wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:96:23]
wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:96:23]
wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:96:23]
wire [2:0] mem_xcpt_uops_out_iq_type = exe_tlb_uop_0_iq_type; // @[util.scala:96:23]
wire [9:0] mem_xcpt_uops_out_fu_code = exe_tlb_uop_0_fu_code; // @[util.scala:96:23]
wire [3:0] mem_xcpt_uops_out_ctrl_br_type = exe_tlb_uop_0_ctrl_br_type; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_ctrl_op1_sel = exe_tlb_uop_0_ctrl_op1_sel; // @[util.scala:96:23]
wire [2:0] mem_xcpt_uops_out_ctrl_op2_sel = exe_tlb_uop_0_ctrl_op2_sel; // @[util.scala:96:23]
wire [2:0] mem_xcpt_uops_out_ctrl_imm_sel = exe_tlb_uop_0_ctrl_imm_sel; // @[util.scala:96:23]
wire [4:0] mem_xcpt_uops_out_ctrl_op_fcn = exe_tlb_uop_0_ctrl_op_fcn; // @[util.scala:96:23]
wire mem_xcpt_uops_out_ctrl_fcn_dw = exe_tlb_uop_0_ctrl_fcn_dw; // @[util.scala:96:23]
wire [2:0] mem_xcpt_uops_out_ctrl_csr_cmd = exe_tlb_uop_0_ctrl_csr_cmd; // @[util.scala:96:23]
wire mem_xcpt_uops_out_ctrl_is_load = exe_tlb_uop_0_ctrl_is_load; // @[util.scala:96:23]
wire mem_xcpt_uops_out_ctrl_is_sta = exe_tlb_uop_0_ctrl_is_sta; // @[util.scala:96:23]
wire mem_xcpt_uops_out_ctrl_is_std = exe_tlb_uop_0_ctrl_is_std; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_iw_state = exe_tlb_uop_0_iw_state; // @[util.scala:96:23]
wire mem_xcpt_uops_out_iw_p1_poisoned = exe_tlb_uop_0_iw_p1_poisoned; // @[util.scala:96:23]
wire mem_xcpt_uops_out_iw_p2_poisoned = exe_tlb_uop_0_iw_p2_poisoned; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_br = exe_tlb_uop_0_is_br; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_jalr = exe_tlb_uop_0_is_jalr; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_jal = exe_tlb_uop_0_is_jal; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:96:23]
wire [3:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:96:23]
wire [4:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:96:23]
wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:96:23]
wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:96:23]
wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:96:23]
wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:96:23]
wire [11:0] mem_xcpt_uops_out_csr_addr = exe_tlb_uop_0_csr_addr; // @[util.scala:96:23]
wire [6:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:96:23]
wire [4:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:96:23]
wire [4:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:96:23]
wire [6:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:96:23]
wire [6:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:96:23]
wire [6:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:96:23]
wire [6:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:96:23]
wire [4:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:96:23]
wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:96:23]
wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:96:23]
wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:96:23]
wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:96:23]
wire [6:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:96:23]
wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:96:23]
wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:96:23]
wire mem_xcpt_uops_out_bypassable = exe_tlb_uop_0_bypassable; // @[util.scala:96:23]
wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:96:23]
wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:96:23]
wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:96:23]
wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:96:23]
wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:96:23]
wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:96:23]
wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:96:23]
wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:96:23]
wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:96:23]
wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:96:23]
wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:96:23]
wire mem_xcpt_uops_out_ldst_val = exe_tlb_uop_0_ldst_val; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:96:23]
wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:96:23]
wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:96:23]
wire mem_xcpt_uops_out_fp_single = exe_tlb_uop_0_fp_single; // @[util.scala:96:23]
wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:96:23]
wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:96:23]
wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:96:23]
wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:96:23]
wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:96:23]
wire [1:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:96:23]
wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :606:53, :607:53]
wire [39:0] _exe_tlb_vaddr_T_2 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:241:34, :375:38, :612:24]
wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_2; // @[util.scala:106:23]
wire [39:0] _exe_tlb_vaddr_T_4 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_3; // @[util.scala:106:23]
wire [39:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {1'h0, exe_req_0_bits_sfence_bits_addr} : _exe_tlb_vaddr_T_4; // @[lsu.scala:374:38, :383:25, :609:24, :610:24]
wire [39:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? exe_req_0_bits_addr : _exe_tlb_vaddr_T_5; // @[lsu.scala:383:25, :606:24, :607:53, :609:24]
wire [39:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:263:49, :606:24]
wire exe_sfence_bits_rs1; // @[lsu.scala:615:28]
wire exe_sfence_bits_rs2; // @[lsu.scala:615:28]
wire [38:0] exe_sfence_bits_addr; // @[lsu.scala:615:28]
wire exe_sfence_bits_asid; // @[lsu.scala:615:28]
wire exe_sfence_valid; // @[lsu.scala:615:28]
assign exe_sfence_valid = will_fire_sfence_0 & exe_req_0_bits_sfence_valid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18]
assign exe_sfence_bits_rs1 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18]
assign exe_sfence_bits_rs2 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18]
assign exe_sfence_bits_addr = will_fire_sfence_0 ? exe_req_0_bits_sfence_bits_addr : 39'h0; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18]
assign exe_sfence_bits_asid = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18]
wire _exe_size_T_1 = _exe_size_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :623:52, :624:52]
wire _exe_size_T_2 = _exe_size_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :624:52, :625:52]
wire _exe_size_T_3 = _exe_size_T_2 | will_fire_load_retry_0; // @[lsu.scala:378:38, :625:52, :626:52]
wire _exe_size_T_4 = _exe_size_T_3 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :626:52, :627:52]
wire [1:0] _exe_size_T_5 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:375:38, :629:23]
wire [1:0] _exe_size_T_6 = _exe_size_T_4 ? exe_tlb_uop_0_mem_size : _exe_size_T_5; // @[lsu.scala:263:49, :623:23, :627:52, :629:23]
wire [1:0] exe_size_0 = _exe_size_T_6; // @[lsu.scala:263:49, :623:23]
wire _exe_cmd_T_1 = _exe_cmd_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :632:52, :633:52]
wire _exe_cmd_T_2 = _exe_cmd_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :633:52, :634:52]
wire _exe_cmd_T_3 = _exe_cmd_T_2 | will_fire_load_retry_0; // @[lsu.scala:378:38, :634:52, :635:52]
wire _exe_cmd_T_4 = _exe_cmd_T_3 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :635:52, :636:52]
wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_4 ? exe_tlb_uop_0_mem_cmd : 5'h0; // @[lsu.scala:263:49, :632:23, :636:52]
wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:263:49, :632:23]
wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:263:49, :642:23]
wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :375:38, :645:23]
wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:263:49, :645:23]
wire _ma_ld_T = will_fire_load_incoming_0 & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:370:38, :383:25, :660:56]
wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:263:49, :660:56]
wire _T_242 = will_fire_sta_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:371:38, :372:38, :661:56]
wire _ma_st_T; // @[lsu.scala:661:56]
assign _ma_st_T = _T_242; // @[lsu.scala:661:56]
wire _stq_idx_T; // @[lsu.scala:851:51]
assign _stq_idx_T = _T_242; // @[lsu.scala:661:56, :851:51]
wire _ma_st_T_1 = _ma_st_T & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25, :661:{56,87}]
wire ma_st_0 = _ma_st_T_1; // @[lsu.scala:263:49, :661:87]
wire _pf_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20, :525:27, :662:50]
wire _pf_ld_T_1 = _pf_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :662:{50,75}]
wire pf_ld_0 = _pf_ld_T_1; // @[lsu.scala:263:49, :662:75]
wire _pf_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20, :525:27, :663:50]
wire _pf_st_T_1 = _pf_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :663:{50,75}]
wire pf_st_0 = _pf_st_T_1; // @[lsu.scala:263:49, :663:75]
wire _ae_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20, :525:27, :664:50]
wire _ae_ld_T_1 = _ae_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :664:{50,75}]
wire ae_ld_0 = _ae_ld_T_1; // @[lsu.scala:263:49, :664:75]
wire _ae_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20, :525:27, :665:50]
wire _ae_st_T_1 = _ae_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :665:{50,75}]
wire ae_st_0 = _ae_st_T_1; // @[lsu.scala:263:49, :665:75]
wire _mem_xcpt_valids_T = pf_ld_0 | pf_st_0; // @[lsu.scala:263:49, :669:32]
wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T | ae_ld_0; // @[lsu.scala:263:49, :669:{32,44}]
wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 | ae_st_0; // @[lsu.scala:263:49, :669:{44,56}]
wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 | ma_ld_0; // @[lsu.scala:263:49, :669:{56,68}]
wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 | ma_st_0; // @[lsu.scala:263:49, :669:{68,80}]
wire _mem_xcpt_valids_T_5 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22]
wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_4 & _mem_xcpt_valids_T_5; // @[lsu.scala:669:{80,93}, :670:22]
wire [15:0] _mem_xcpt_valids_T_7 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:118:51]
wire _mem_xcpt_valids_T_8 = |_mem_xcpt_valids_T_7; // @[util.scala:118:{51,59}]
wire _mem_xcpt_valids_T_9 = ~_mem_xcpt_valids_T_8; // @[util.scala:118:59]
wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_6 & _mem_xcpt_valids_T_9; // @[lsu.scala:669:93, :670:41, :671:22]
wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_10; // @[lsu.scala:263:49, :670:41]
reg mem_xcpt_valids_0; // @[lsu.scala:668:32]
assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:358:29, :668:32]
wire [6:0] _mem_xcpt_uops_WIRE_0_uopc = mem_xcpt_uops_out_uopc; // @[util.scala:96:23]
wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:96:23]
wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:96:23]
wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:96:23]
wire [2:0] _mem_xcpt_uops_WIRE_0_iq_type = mem_xcpt_uops_out_iq_type; // @[util.scala:96:23]
wire [9:0] _mem_xcpt_uops_WIRE_0_fu_code = mem_xcpt_uops_out_fu_code; // @[util.scala:96:23]
wire [3:0] _mem_xcpt_uops_WIRE_0_ctrl_br_type = mem_xcpt_uops_out_ctrl_br_type; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_ctrl_op1_sel = mem_xcpt_uops_out_ctrl_op1_sel; // @[util.scala:96:23]
wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_op2_sel = mem_xcpt_uops_out_ctrl_op2_sel; // @[util.scala:96:23]
wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_imm_sel = mem_xcpt_uops_out_ctrl_imm_sel; // @[util.scala:96:23]
wire [4:0] _mem_xcpt_uops_WIRE_0_ctrl_op_fcn = mem_xcpt_uops_out_ctrl_op_fcn; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_ctrl_fcn_dw = mem_xcpt_uops_out_ctrl_fcn_dw; // @[util.scala:96:23]
wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_csr_cmd = mem_xcpt_uops_out_ctrl_csr_cmd; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_ctrl_is_load = mem_xcpt_uops_out_ctrl_is_load; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_ctrl_is_sta = mem_xcpt_uops_out_ctrl_is_sta; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_ctrl_is_std = mem_xcpt_uops_out_ctrl_is_std; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_iw_state = mem_xcpt_uops_out_iw_state; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_iw_p1_poisoned = mem_xcpt_uops_out_iw_p1_poisoned; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_iw_p2_poisoned = mem_xcpt_uops_out_iw_p2_poisoned; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_br = mem_xcpt_uops_out_is_br; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_jalr = mem_xcpt_uops_out_is_jalr; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_jal = mem_xcpt_uops_out_is_jal; // @[util.scala:96:23]
wire [15:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25]
wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:96:23]
wire [15:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:96:23]
wire [3:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:96:23]
wire [4:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:96:23]
wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:96:23]
wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:96:23]
wire [11:0] _mem_xcpt_uops_WIRE_0_csr_addr = mem_xcpt_uops_out_csr_addr; // @[util.scala:96:23]
wire [6:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:96:23]
wire [4:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:96:23]
wire [4:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:96:23]
wire [6:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:96:23]
wire [6:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:96:23]
wire [6:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:96:23]
wire [6:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:96:23]
wire [4:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:96:23]
wire [6:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:96:23]
wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_bypassable = mem_xcpt_uops_out_bypassable; // @[util.scala:96:23]
wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:96:23]
wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:96:23]
wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:96:23]
wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:96:23]
wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_ldst_val = mem_xcpt_uops_out_ldst_val; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_fp_single = mem_xcpt_uops_out_fp_single; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:96:23]
wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:96:23]
wire [1:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:96:23]
wire [15:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:85:{25,27}]
assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25, :96:23]
reg [6:0] mem_xcpt_uops_0_uopc; // @[lsu.scala:672:32]
assign mem_xcpt_uop_uopc = mem_xcpt_uops_0_uopc; // @[lsu.scala:360:29, :672:32]
reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:672:32]
assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:360:29, :672:32]
reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:672:32]
assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:360:29, :672:32]
reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:672:32]
assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:360:29, :672:32]
reg [2:0] mem_xcpt_uops_0_iq_type; // @[lsu.scala:672:32]
assign mem_xcpt_uop_iq_type = mem_xcpt_uops_0_iq_type; // @[lsu.scala:360:29, :672:32]
reg [9:0] mem_xcpt_uops_0_fu_code; // @[lsu.scala:672:32]
assign mem_xcpt_uop_fu_code = mem_xcpt_uops_0_fu_code; // @[lsu.scala:360:29, :672:32]
reg [3:0] mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_br_type = mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_op1_sel = mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:360:29, :672:32]
reg [2:0] mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_op2_sel = mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:360:29, :672:32]
reg [2:0] mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_imm_sel = mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:360:29, :672:32]
reg [4:0] mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_op_fcn = mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_fcn_dw = mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:360:29, :672:32]
reg [2:0] mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_csr_cmd = mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_is_load = mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_is_sta = mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ctrl_is_std = mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_iw_state; // @[lsu.scala:672:32]
assign mem_xcpt_uop_iw_state = mem_xcpt_uops_0_iw_state; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:672:32]
assign mem_xcpt_uop_iw_p1_poisoned = mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:672:32]
assign mem_xcpt_uop_iw_p2_poisoned = mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_br; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_br = mem_xcpt_uops_0_is_br; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_jalr; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_jalr = mem_xcpt_uops_0_is_jalr; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_jal; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_jal = mem_xcpt_uops_0_is_jal; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:360:29, :672:32]
reg [15:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:672:32]
assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:360:29, :672:32]
reg [3:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:672:32]
assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:360:29, :672:32]
reg [4:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:672:32]
assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:360:29, :672:32]
reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:672:32]
assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_taken; // @[lsu.scala:672:32]
assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:360:29, :672:32]
reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:672:32]
assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:360:29, :672:32]
reg [11:0] mem_xcpt_uops_0_csr_addr; // @[lsu.scala:672:32]
assign mem_xcpt_uop_csr_addr = mem_xcpt_uops_0_csr_addr; // @[lsu.scala:360:29, :672:32]
reg [6:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:672:32]
assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:360:29, :672:32]
reg [4:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:360:29, :672:32]
reg [4:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:672:32]
assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:672:32]
assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:360:29, :672:32]
reg [6:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:672:32]
assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:360:29, :672:32]
reg [6:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:672:32]
assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:360:29, :672:32]
reg [6:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:672:32]
assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:360:29, :672:32]
reg [6:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:672:32]
assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:360:29, :672:32]
reg [4:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:672:32]
assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:672:32]
assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:672:32]
assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:360:29, :672:32]
reg [6:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:672:32]
assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_exception; // @[lsu.scala:672:32]
assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:360:29, :672:32]
reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:672:32]
assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_bypassable; // @[lsu.scala:672:32]
assign mem_xcpt_uop_bypassable = mem_xcpt_uops_0_bypassable; // @[lsu.scala:360:29, :672:32]
reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:672:32]
assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:672:32]
assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:672:32]
assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:672:32]
assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:672:32]
assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:672:32]
assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:672:32]
assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:360:29, :672:32]
reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:360:29, :672:32]
reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:672:32]
assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:360:29, :672:32]
reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:672:32]
assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:360:29, :672:32]
reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:672:32]
assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_ldst_val; // @[lsu.scala:672:32]
assign mem_xcpt_uop_ldst_val = mem_xcpt_uops_0_ldst_val; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:672:32]
assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:672:32]
assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:672:32]
assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:672:32]
assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:672:32]
assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_fp_single; // @[lsu.scala:672:32]
assign mem_xcpt_uop_fp_single = mem_xcpt_uops_0_fp_single; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:672:32]
assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:672:32]
assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:672:32]
assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:672:32]
assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:360:29, :672:32]
reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:672:32]
assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:672:32]
assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:360:29, :672:32]
reg [1:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:672:32]
assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:360:29, :672:32]
wire [2:0] _mem_xcpt_causes_T = {1'h1, ~ae_ld_0, 1'h1}; // @[lsu.scala:263:49, :678:8]
wire [3:0] _mem_xcpt_causes_T_1 = pf_st_0 ? 4'hF : {1'h0, _mem_xcpt_causes_T}; // @[lsu.scala:263:49, :677:8, :678:8]
wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : _mem_xcpt_causes_T_1; // @[lsu.scala:263:49, :676:8, :677:8]
wire [3:0] _mem_xcpt_causes_T_3 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_2; // @[lsu.scala:263:49, :675:8, :676:8]
wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:263:49, :674:8, :675:8]
wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_4; // @[lsu.scala:263:49, :674:8]
reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:673:32]
assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:359:29, :673:32]
reg [39:0] mem_xcpt_vaddrs_0; // @[lsu.scala:680:32]
assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:361:29, :680:32]
wire _exe_tlb_miss_T_1; // @[lsu.scala:709:83]
wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:525:27, :709:{58,83}]
wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:263:49, :709:58]
wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:247:20, :710:62]
wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:263:49, :711:57]
wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:710:{40,62}, :711:57]
wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:263:49, :710:40]
wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20, :712:43]
wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:263:49, :712:43]
reg REG; // @[lsu.scala:719:21]
assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_uopc_0 = dmem_req_0_bits_uop_uopc; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_iq_type_0 = dmem_req_0_bits_uop_iq_type; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_fu_code_0 = dmem_req_0_bits_uop_fu_code; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_br_type_0 = dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0 = dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0 = dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0 = dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0 = dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0 = dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0 = dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_is_load_0 = dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0 = dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ctrl_is_std_0 = dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_iw_state_0 = dmem_req_0_bits_uop_iw_state; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0 = dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0 = dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_br_0 = dmem_req_0_bits_uop_is_br; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_jalr_0 = dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_jal_0 = dmem_req_0_bits_uop_is_jal; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_csr_addr_0 = dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_bypassable_0 = dmem_req_0_bits_uop_bypassable; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_ldst_val_0 = dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_fp_single_0 = dmem_req_0_bits_uop_fp_single; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:201:7, :750:22]
wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:263:49, :750:22]
assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:201:7, :750:22]
assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:201:7, :750:22]
wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35]
wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35]
wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:263:49, :753:55]
wire s0_executing_loads_0; // @[lsu.scala:755:36]
wire s0_executing_loads_1; // @[lsu.scala:755:36]
wire s0_executing_loads_2; // @[lsu.scala:755:36]
wire s0_executing_loads_3; // @[lsu.scala:755:36]
wire s0_executing_loads_4; // @[lsu.scala:755:36]
wire s0_executing_loads_5; // @[lsu.scala:755:36]
wire s0_executing_loads_6; // @[lsu.scala:755:36]
wire s0_executing_loads_7; // @[lsu.scala:755:36]
wire s0_executing_loads_8; // @[lsu.scala:755:36]
wire s0_executing_loads_9; // @[lsu.scala:755:36]
wire s0_executing_loads_10; // @[lsu.scala:755:36]
wire s0_executing_loads_11; // @[lsu.scala:755:36]
wire s0_executing_loads_12; // @[lsu.scala:755:36]
wire s0_executing_loads_13; // @[lsu.scala:755:36]
wire s0_executing_loads_14; // @[lsu.scala:755:36]
wire s0_executing_loads_15; // @[lsu.scala:755:36]
wire s0_executing_loads_16; // @[lsu.scala:755:36]
wire s0_executing_loads_17; // @[lsu.scala:755:36]
wire s0_executing_loads_18; // @[lsu.scala:755:36]
wire s0_executing_loads_19; // @[lsu.scala:755:36]
wire s0_executing_loads_20; // @[lsu.scala:755:36]
wire s0_executing_loads_21; // @[lsu.scala:755:36]
wire s0_executing_loads_22; // @[lsu.scala:755:36]
wire s0_executing_loads_23; // @[lsu.scala:755:36]
wire _dmem_req_0_valid_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33]
wire _dmem_req_0_valid_T_1 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53]
wire _dmem_req_0_valid_T_2 = _dmem_req_0_valid_T & _dmem_req_0_valid_T_1; // @[lsu.scala:768:{33,50,53}]
wire [39:0] _GEN_291 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:263:49, :769:30]
wire _dmem_req_0_valid_T_3 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :775:33]
wire _dmem_req_0_valid_T_4 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53, :775:53]
wire _dmem_req_0_valid_T_5 = _dmem_req_0_valid_T_3 & _dmem_req_0_valid_T_4; // @[lsu.scala:775:{33,50,53}]
wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19]
wire [7:0] _dmem_req_0_bits_data_T_1 = _GEN_88[7:0]; // @[AMOALU.scala:29:69]
wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}]
wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32]
wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32]
wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19]
wire [15:0] _dmem_req_0_bits_data_T_6 = _GEN_88[15:0]; // @[AMOALU.scala:29:69]
wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32]
wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19]
wire [31:0] _dmem_req_0_bits_data_T_10 = _GEN_88[31:0]; // @[AMOALU.scala:29:69]
wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _GEN_88; // @[AMOALU.scala:29:{13,19,32}]
wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}]
wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}]
wire _GEN_292 = stq_execute_head == 5'h17; // @[util.scala:205:25]
wire stq_execute_head_wrap; // @[util.scala:205:25]
assign stq_execute_head_wrap = _GEN_292; // @[util.scala:205:25]
wire stq_execute_head_wrap_1; // @[util.scala:205:25]
assign stq_execute_head_wrap_1 = _GEN_292; // @[util.scala:205:25]
wire [5:0] _GEN_293 = {1'h0, stq_execute_head} + 6'h1; // @[util.scala:206:28]
wire [5:0] _stq_execute_head_T; // @[util.scala:206:28]
assign _stq_execute_head_T = _GEN_293; // @[util.scala:206:28]
wire [5:0] _stq_execute_head_T_4; // @[util.scala:206:28]
assign _stq_execute_head_T_4 = _GEN_293; // @[util.scala:206:28]
wire [4:0] _stq_execute_head_T_1 = _stq_execute_head_T[4:0]; // @[util.scala:206:28]
wire [4:0] _stq_execute_head_T_2 = stq_execute_head_wrap ? 5'h0 : _stq_execute_head_T_1; // @[util.scala:205:25, :206:{10,28}]
wire [4:0] _stq_execute_head_T_3 = dmem_req_fire_0 ? _stq_execute_head_T_2 : stq_execute_head; // @[util.scala:206:10]
wire _GEN_294 = will_fire_load_incoming_0 | will_fire_load_retry_0; // @[lsu.scala:218:29, :370:38, :378:38, :767:39, :774:43, :781:45]
assign dmem_req_0_bits_uop_uopc = _GEN_294 ? exe_tlb_uop_0_uopc : will_fire_store_commit_0 ? _GEN_1[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_inst = _GEN_294 ? exe_tlb_uop_0_inst : will_fire_store_commit_0 ? _GEN_2[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_debug_inst = _GEN_294 ? exe_tlb_uop_0_debug_inst : will_fire_store_commit_0 ? _GEN_3[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_rvc = _GEN_294 ? exe_tlb_uop_0_is_rvc : will_fire_store_commit_0 ? _GEN_4[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_rvc; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_debug_pc = _GEN_294 ? exe_tlb_uop_0_debug_pc : will_fire_store_commit_0 ? _GEN_5[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_iq_type = _GEN_294 ? exe_tlb_uop_0_iq_type : will_fire_store_commit_0 ? _GEN_6[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_fu_code = _GEN_294 ? exe_tlb_uop_0_fu_code : will_fire_store_commit_0 ? _GEN_7[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_br_type = _GEN_294 ? exe_tlb_uop_0_ctrl_br_type : will_fire_store_commit_0 ? _GEN_8[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_op1_sel = _GEN_294 ? exe_tlb_uop_0_ctrl_op1_sel : will_fire_store_commit_0 ? _GEN_9[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_op2_sel = _GEN_294 ? exe_tlb_uop_0_ctrl_op2_sel : will_fire_store_commit_0 ? _GEN_10[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_imm_sel = _GEN_294 ? exe_tlb_uop_0_ctrl_imm_sel : will_fire_store_commit_0 ? _GEN_11[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_op_fcn = _GEN_294 ? exe_tlb_uop_0_ctrl_op_fcn : will_fire_store_commit_0 ? _GEN_12[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_fcn_dw = _GEN_294 ? exe_tlb_uop_0_ctrl_fcn_dw : will_fire_store_commit_0 ? _GEN_13[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_csr_cmd = _GEN_294 ? exe_tlb_uop_0_ctrl_csr_cmd : will_fire_store_commit_0 ? _GEN_14[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_is_load = _GEN_294 ? exe_tlb_uop_0_ctrl_is_load : will_fire_store_commit_0 ? _GEN_15[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_is_sta = _GEN_294 ? exe_tlb_uop_0_ctrl_is_sta : will_fire_store_commit_0 ? _GEN_16[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ctrl_is_std = _GEN_294 ? exe_tlb_uop_0_ctrl_is_std : will_fire_store_commit_0 ? _GEN_17[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_iw_state = _GEN_294 ? exe_tlb_uop_0_iw_state : will_fire_store_commit_0 ? _GEN_18[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_iw_p1_poisoned = _GEN_294 ? exe_tlb_uop_0_iw_p1_poisoned : will_fire_store_commit_0 ? _GEN_19[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_iw_p2_poisoned = _GEN_294 ? exe_tlb_uop_0_iw_p2_poisoned : will_fire_store_commit_0 ? _GEN_20[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_br = _GEN_294 ? exe_tlb_uop_0_is_br : will_fire_store_commit_0 ? _GEN_21[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_br; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_jalr = _GEN_294 ? exe_tlb_uop_0_is_jalr : will_fire_store_commit_0 ? _GEN_22[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jalr; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_jal = _GEN_294 ? exe_tlb_uop_0_is_jal : will_fire_store_commit_0 ? _GEN_23[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jal; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_sfb = _GEN_294 ? exe_tlb_uop_0_is_sfb : will_fire_store_commit_0 ? _GEN_24[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sfb; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_br_mask = _GEN_294 ? exe_tlb_uop_0_br_mask : will_fire_store_commit_0 ? _GEN_25[stq_execute_head] : will_fire_load_wakeup_0 ? _GEN_125[_ldq_wakeup_e_T_1] : 16'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :381:38, :501:88, :750:22, :760:28, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44, :798:30]
assign dmem_req_0_bits_uop_br_tag = _GEN_294 ? exe_tlb_uop_0_br_tag : will_fire_store_commit_0 ? _GEN_26[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_br_tag : 4'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ftq_idx = _GEN_294 ? exe_tlb_uop_0_ftq_idx : will_fire_store_commit_0 ? _GEN_27[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ftq_idx : 5'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_edge_inst = _GEN_294 ? exe_tlb_uop_0_edge_inst : will_fire_store_commit_0 ? _GEN_28[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_edge_inst; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_pc_lob = _GEN_294 ? exe_tlb_uop_0_pc_lob : will_fire_store_commit_0 ? _GEN_29[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_taken = _GEN_294 ? exe_tlb_uop_0_taken : will_fire_store_commit_0 ? _GEN_30[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_taken; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_imm_packed = _GEN_294 ? exe_tlb_uop_0_imm_packed : will_fire_store_commit_0 ? _GEN_31[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_csr_addr = _GEN_294 ? exe_tlb_uop_0_csr_addr : will_fire_store_commit_0 ? _GEN_32[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_rob_idx = _GEN_294 ? exe_tlb_uop_0_rob_idx : will_fire_store_commit_0 ? _GEN_33[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rob_idx : 7'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ldq_idx = _GEN_294 ? exe_tlb_uop_0_ldq_idx : will_fire_store_commit_0 ? _GEN_34[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldq_idx : 5'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_stq_idx = _GEN_294 ? exe_tlb_uop_0_stq_idx : will_fire_store_commit_0 ? _GEN_35[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stq_idx : 5'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_rxq_idx = _GEN_294 ? exe_tlb_uop_0_rxq_idx : will_fire_store_commit_0 ? _GEN_36[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_pdst = _GEN_294 ? exe_tlb_uop_0_pdst : will_fire_store_commit_0 ? _GEN_37[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pdst : 7'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_prs1 = _GEN_294 ? exe_tlb_uop_0_prs1 : will_fire_store_commit_0 ? _GEN_38[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs1 : 7'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_prs2 = _GEN_294 ? exe_tlb_uop_0_prs2 : will_fire_store_commit_0 ? _GEN_39[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs2 : 7'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_prs3 = _GEN_294 ? exe_tlb_uop_0_prs3 : will_fire_store_commit_0 ? _GEN_40[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs3 : 7'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ppred = _GEN_294 ? exe_tlb_uop_0_ppred : will_fire_store_commit_0 ? _GEN_41[stq_execute_head] : 5'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44]
assign dmem_req_0_bits_uop_prs1_busy = _GEN_294 ? exe_tlb_uop_0_prs1_busy : will_fire_store_commit_0 ? _GEN_42[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs1_busy; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_prs2_busy = _GEN_294 ? exe_tlb_uop_0_prs2_busy : will_fire_store_commit_0 ? _GEN_43[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs2_busy; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_prs3_busy = _GEN_294 ? exe_tlb_uop_0_prs3_busy : will_fire_store_commit_0 ? _GEN_44[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs3_busy; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ppred_busy = _GEN_294 ? exe_tlb_uop_0_ppred_busy : will_fire_store_commit_0 & _GEN_45[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44]
assign dmem_req_0_bits_uop_stale_pdst = _GEN_294 ? exe_tlb_uop_0_stale_pdst : will_fire_store_commit_0 ? _GEN_46[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stale_pdst : 7'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_exception = _GEN_294 ? exe_tlb_uop_0_exception : will_fire_store_commit_0 ? _GEN_48 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_exception; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_exc_cause = _GEN_294 ? exe_tlb_uop_0_exc_cause : will_fire_store_commit_0 ? _GEN_49[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_bypassable = _GEN_294 ? exe_tlb_uop_0_bypassable : will_fire_store_commit_0 ? _GEN_50[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bypassable; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_fence = _GEN_294 ? exe_tlb_uop_0_is_fence : will_fire_store_commit_0 ? _GEN_55 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fence; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_fencei = _GEN_294 ? exe_tlb_uop_0_is_fencei : will_fire_store_commit_0 ? _GEN_56[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fencei; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_amo = _GEN_294 ? exe_tlb_uop_0_is_amo : will_fire_store_commit_0 ? _GEN_58 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_amo; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_uses_ldq = _GEN_294 ? exe_tlb_uop_0_uses_ldq : will_fire_store_commit_0 ? _GEN_59[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_ldq; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_uses_stq = _GEN_294 ? exe_tlb_uop_0_uses_stq : will_fire_store_commit_0 ? _GEN_60[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_stq; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_294 ? exe_tlb_uop_0_is_sys_pc2epc : will_fire_store_commit_0 ? _GEN_61[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_is_unique = _GEN_294 ? exe_tlb_uop_0_is_unique : will_fire_store_commit_0 ? _GEN_62[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_unique; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_flush_on_commit = _GEN_294 ? exe_tlb_uop_0_flush_on_commit : will_fire_store_commit_0 ? _GEN_63[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_294 ? exe_tlb_uop_0_ldst_is_rs1 : will_fire_store_commit_0 ? _GEN_64[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ldst = _GEN_294 ? exe_tlb_uop_0_ldst : will_fire_store_commit_0 ? _GEN_65[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_lrs1 = _GEN_294 ? exe_tlb_uop_0_lrs1 : will_fire_store_commit_0 ? _GEN_66[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_lrs2 = _GEN_294 ? exe_tlb_uop_0_lrs2 : will_fire_store_commit_0 ? _GEN_67[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_lrs3 = _GEN_294 ? exe_tlb_uop_0_lrs3 : will_fire_store_commit_0 ? _GEN_68[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_ldst_val = _GEN_294 ? exe_tlb_uop_0_ldst_val : will_fire_store_commit_0 ? _GEN_69[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_val; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_dst_rtype = _GEN_294 ? exe_tlb_uop_0_dst_rtype : will_fire_store_commit_0 ? _GEN_70[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_294 ? exe_tlb_uop_0_lrs1_rtype : will_fire_store_commit_0 ? _GEN_71[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_294 ? exe_tlb_uop_0_lrs2_rtype : will_fire_store_commit_0 ? _GEN_72[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_frs3_en = _GEN_294 ? exe_tlb_uop_0_frs3_en : will_fire_store_commit_0 ? _GEN_73[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_frs3_en; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_fp_val = _GEN_294 ? exe_tlb_uop_0_fp_val : will_fire_store_commit_0 ? _GEN_74[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_val; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_fp_single = _GEN_294 ? exe_tlb_uop_0_fp_single : will_fire_store_commit_0 ? _GEN_75[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_single; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_294 ? exe_tlb_uop_0_xcpt_pf_if : will_fire_store_commit_0 ? _GEN_76[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_294 ? exe_tlb_uop_0_xcpt_ae_if : will_fire_store_commit_0 ? _GEN_77[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_294 ? exe_tlb_uop_0_xcpt_ma_if : will_fire_store_commit_0 ? _GEN_78[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_bp_debug_if = _GEN_294 ? exe_tlb_uop_0_bp_debug_if : will_fire_store_commit_0 ? _GEN_79[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_294 ? exe_tlb_uop_0_bp_xcpt_if : will_fire_store_commit_0 ? _GEN_80[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_debug_fsrc = _GEN_294 ? exe_tlb_uop_0_debug_fsrc : will_fire_store_commit_0 ? _GEN_81[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_debug_tsrc = _GEN_294 ? exe_tlb_uop_0_debug_tsrc : will_fire_store_commit_0 ? _GEN_82[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23]
assign s0_executing_loads_0 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h0 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_267 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_243 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_1 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h1 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_268 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_244 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_2 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h2 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_269 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_245 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_3 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h3 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_270 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_246 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_4 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h4 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_271 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_247 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_5 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h5 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_272 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_248 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_6 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h6 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_273 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_249 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_7 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h7 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_274 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_250 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_8 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h8 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_275 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_251 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_9 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h9 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_276 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_252 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_10 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hA & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_277 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_253 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_11 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hB & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_278 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_254 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_12 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hC & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_279 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_255 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_13 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hD & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_280 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_256 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_14 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hE & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_281 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_257 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_15 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hF & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_282 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_258 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_16 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h10 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_283 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_259 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_17 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h11 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_284 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_260 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_18 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h12 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_285 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_261 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_19 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h13 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_286 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_262 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_20 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h14 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_287 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_263 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_21 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h15 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_288 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_264 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_22 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h16 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_289 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_265 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
assign s0_executing_loads_23 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h17 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_290 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_266 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42]
wire _dmem_req_0_valid_T_6 = ~io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :806:42]
wire _dmem_req_0_valid_T_9 = _dmem_req_0_valid_T_6; // @[lsu.scala:806:{42,65}]
wire _dmem_req_0_valid_T_7 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :806:69]
wire _GEN_295 = will_fire_store_commit_0 | will_fire_load_wakeup_0; // @[lsu.scala:243:34, :380:38, :381:38, :781:45, :795:44, :803:47]
assign dmem_req_0_valid = will_fire_load_incoming_0 ? _dmem_req_0_valid_T_2 : will_fire_load_retry_0 ? _dmem_req_0_valid_T_5 : _GEN_295 | (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_9 : will_fire_hella_wakeup_0); // @[lsu.scala:243:34, :370:38, :375:38, :376:38, :378:38, :750:22, :767:39, :768:{30,50}, :774:43, :775:{30,50}, :781:45, :782:33, :795:44, :796:30, :803:47, :806:{39,65}, :820:5]
assign dmem_req_0_bits_addr = will_fire_load_incoming_0 | will_fire_load_retry_0 ? _GEN_291 : will_fire_store_commit_0 ? _GEN_84[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_291 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[util.scala:106:23]
wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69]
wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}]
wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32]
wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32]
wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69]
wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32]
wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69]
wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13]
wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13]
assign dmem_req_0_bits_data = _GEN_294 ? 64'h0 : will_fire_store_commit_0 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 | will_fire_hella_incoming_0 | ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13]
assign dmem_req_0_bits_uop_mem_cmd = _GEN_294 ? exe_tlb_uop_0_mem_cmd : will_fire_store_commit_0 ? _GEN_51[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23]
assign dmem_req_0_bits_uop_mem_size = _GEN_294 ? exe_tlb_uop_0_mem_size : will_fire_store_commit_0 ? dmem_req_0_bits_data_size : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_size : {2{will_fire_hella_incoming_0 | will_fire_hella_wakeup_0}}; // @[AMOALU.scala:11:18]
assign dmem_req_0_bits_uop_mem_signed = _GEN_294 ? exe_tlb_uop_0_mem_signed : will_fire_store_commit_0 ? _GEN_53[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_mem_signed; // @[util.scala:106:23]
assign dmem_req_0_bits_is_hella = ~(_GEN_294 | will_fire_store_commit_0 | will_fire_load_wakeup_0) & (will_fire_hella_incoming_0 | will_fire_hella_wakeup_0); // @[lsu.scala:218:29, :375:38, :376:38, :380:38, :381:38, :750:22, :763:31, :767:39, :774:43, :781:45, :795:44, :803:47, :815:39, :820:5]
wire _T_226 = will_fire_load_incoming_0 | will_fire_load_retry_0; // @[lsu.scala:370:38, :378:38, :836:38]
wire [4:0] ldq_idx = will_fire_load_incoming_0 ? ldq_incoming_idx_0 : ldq_retry_idx; // @[lsu.scala:263:49, :370:38, :414:30, :838:24]
wire [39:0] _GEN_296 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : _GEN_291; // @[lsu.scala:263:49, :769:30, :840:51]
wire [39:0] _ldq_bits_addr_bits_T; // @[lsu.scala:840:51]
assign _ldq_bits_addr_bits_T = _GEN_296; // @[lsu.scala:840:51]
wire [39:0] _stq_bits_addr_bits_T; // @[lsu.scala:855:42]
assign _stq_bits_addr_bits_T = _GEN_296; // @[lsu.scala:840:51, :855:42]
wire _ldq_bits_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :843:74]
wire _ldq_bits_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_bits_addr_is_uncacheable_T; // @[lsu.scala:263:49, :843:{71,74}]
wire _T_243 = _T_242 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :661:56, :849:67]
wire [4:0] stq_idx = _stq_idx_T ? stq_incoming_idx_0 : stq_retry_idx; // @[lsu.scala:263:49, :421:30, :851:{24,51}]
wire _stq_bits_addr_valid_T = ~pf_st_0; // @[lsu.scala:263:49, :854:39]
wire _io_core_fp_stdata_ready_T = ~will_fire_std_incoming_0; // @[lsu.scala:373:38, :867:34]
wire _io_core_fp_stdata_ready_T_1 = ~will_fire_stad_incoming_0; // @[lsu.scala:371:38, :867:64]
assign _io_core_fp_stdata_ready_T_2 = _io_core_fp_stdata_ready_T & _io_core_fp_stdata_ready_T_1; // @[lsu.scala:867:{34,61,64}]
assign io_core_fp_stdata_ready_0 = _io_core_fp_stdata_ready_T_2; // @[lsu.scala:201:7, :867:61]
wire _GEN_297 = io_core_fp_stdata_ready_0 & io_core_fp_stdata_valid_0; // @[Decoupled.scala:51:35]
wire _fp_stdata_fire_T; // @[Decoupled.scala:51:35]
assign _fp_stdata_fire_T = _GEN_297; // @[Decoupled.scala:51:35]
wire will_fire_stdf_incoming; // @[Decoupled.scala:51:35]
assign will_fire_stdf_incoming = _GEN_297; // @[Decoupled.scala:51:35]
wire fp_stdata_fire = _fp_stdata_fire_T; // @[Decoupled.scala:51:35]
wire _T_257 = will_fire_std_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:371:38, :373:38, :869:37]
wire _sidx_T; // @[lsu.scala:871:48]
assign _sidx_T = _T_257; // @[lsu.scala:869:37, :871:48]
wire _stq_bits_data_bits_T; // @[lsu.scala:875:66]
assign _stq_bits_data_bits_T = _T_257; // @[lsu.scala:869:37, :875:66]
wire _T_258 = _T_257 | fp_stdata_fire; // @[lsu.scala:868:49, :869:{37,67}]
wire [4:0] sidx = _sidx_T ? stq_incoming_idx_0 : io_core_fp_stdata_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :263:49, :871:{21,48}]
wire [63:0] _stq_bits_data_bits_T_1 = _stq_bits_data_bits_T ? exe_req_0_bits_data : io_core_fp_stdata_bits_data_0; // @[lsu.scala:201:7, :383:25, :875:{39,66}]
wire [15:0] _exe_req_killed_T = io_core_brupdate_b1_mispredict_mask_0 & exe_req_0_bits_uop_br_mask; // @[util.scala:118:51]
wire _exe_req_killed_T_1 = |_exe_req_killed_T; // @[util.scala:118:{51,59}]
wire exe_req_killed_0 = _exe_req_killed_T_1; // @[util.scala:118:59]
wire [15:0] _stdf_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_fp_stdata_bits_uop_br_mask_0; // @[util.scala:118:51]
wire stdf_killed = |_stdf_killed_T; // @[util.scala:118:{51,59}]
wire _fired_load_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82]
wire _fired_load_incoming_T_1 = will_fire_load_incoming_0 & _fired_load_incoming_T; // @[lsu.scala:370:38, :895:{79,82}]
reg fired_load_incoming_REG; // @[lsu.scala:895:51]
wire fired_load_incoming_0 = fired_load_incoming_REG; // @[lsu.scala:263:49, :895:51]
wire _io_core_spec_ld_wakeup_0_valid_T = fired_load_incoming_0; // @[lsu.scala:263:49, :1259:69]
wire _fired_stad_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :896:82]
wire _fired_stad_incoming_T_1 = will_fire_stad_incoming_0 & _fired_stad_incoming_T; // @[lsu.scala:371:38, :896:{79,82}]
reg fired_stad_incoming_REG; // @[lsu.scala:896:51]
wire fired_stad_incoming_0 = fired_stad_incoming_REG; // @[lsu.scala:263:49, :896:51]
wire _fired_sta_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :897:82]
wire _fired_sta_incoming_T_1 = will_fire_sta_incoming_0 & _fired_sta_incoming_T; // @[lsu.scala:372:38, :897:{79,82}]
reg fired_sta_incoming_REG; // @[lsu.scala:897:51]
wire fired_sta_incoming_0 = fired_sta_incoming_REG; // @[lsu.scala:263:49, :897:51]
wire _fired_std_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :898:82]
wire _fired_std_incoming_T_1 = will_fire_std_incoming_0 & _fired_std_incoming_T; // @[lsu.scala:373:38, :898:{79,82}]
reg fired_std_incoming_REG; // @[lsu.scala:898:51]
wire fired_std_incoming_0 = fired_std_incoming_REG; // @[lsu.scala:263:49, :898:51]
wire _fired_stdf_incoming_T = ~stdf_killed; // @[util.scala:118:59]
wire _fired_stdf_incoming_T_1 = will_fire_stdf_incoming & _fired_stdf_incoming_T; // @[Decoupled.scala:51:35]
reg fired_stdf_incoming; // @[lsu.scala:899:37]
reg fired_sfence_0; // @[lsu.scala:900:37]
reg fired_release_0; // @[lsu.scala:901:37]
wire do_release_search_0 = fired_release_0; // @[lsu.scala:263:49, :901:37]
wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:263:49, :901:37]
wire [15:0] _GEN_298 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_125[_ldq_retry_e_T_1]; // @[util.scala:118:51]
wire [15:0] _fired_load_retry_T; // @[util.scala:118:51]
assign _fired_load_retry_T = _GEN_298; // @[util.scala:118:51]
wire [15:0] _mem_ldq_retry_e_out_valid_T; // @[util.scala:118:51]
assign _mem_ldq_retry_e_out_valid_T = _GEN_298; // @[util.scala:118:51]
wire _fired_load_retry_T_1 = |_fired_load_retry_T; // @[util.scala:118:{51,59}]
wire _fired_load_retry_T_2 = ~_fired_load_retry_T_1; // @[util.scala:118:59]
wire _fired_load_retry_T_3 = will_fire_load_retry_0 & _fired_load_retry_T_2; // @[lsu.scala:378:38, :902:{79,82}]
reg fired_load_retry_REG; // @[lsu.scala:902:51]
wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:263:49, :902:51]
wire [15:0] _GEN_299 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_25[_stq_retry_e_T_1]; // @[util.scala:118:51]
wire [15:0] _fired_sta_retry_T; // @[util.scala:118:51]
assign _fired_sta_retry_T = _GEN_299; // @[util.scala:118:51]
wire [15:0] _mem_stq_retry_e_out_valid_T; // @[util.scala:118:51]
assign _mem_stq_retry_e_out_valid_T = _GEN_299; // @[util.scala:118:51]
wire _fired_sta_retry_T_1 = |_fired_sta_retry_T; // @[util.scala:118:{51,59}]
wire _fired_sta_retry_T_2 = ~_fired_sta_retry_T_1; // @[util.scala:118:59]
wire _fired_sta_retry_T_3 = will_fire_sta_retry_0 & _fired_sta_retry_T_2; // @[lsu.scala:379:38, :903:{79,82}]
reg fired_sta_retry_REG; // @[lsu.scala:903:51]
wire fired_sta_retry_0 = fired_sta_retry_REG; // @[lsu.scala:263:49, :903:51]
reg fired_store_commit_0; // @[lsu.scala:904:37]
wire [15:0] _GEN_300 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_125[_ldq_wakeup_e_T_1]; // @[util.scala:118:51]
wire [15:0] _fired_load_wakeup_T; // @[util.scala:118:51]
assign _fired_load_wakeup_T = _GEN_300; // @[util.scala:118:51]
wire [15:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:51]
assign _mem_ldq_wakeup_e_out_valid_T = _GEN_300; // @[util.scala:118:51]
wire _fired_load_wakeup_T_1 = |_fired_load_wakeup_T; // @[util.scala:118:{51,59}]
wire _fired_load_wakeup_T_2 = ~_fired_load_wakeup_T_1; // @[util.scala:118:59]
wire _fired_load_wakeup_T_3 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_2; // @[lsu.scala:381:38, :905:{79,82}]
reg fired_load_wakeup_REG; // @[lsu.scala:905:51]
wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:263:49, :905:51]
reg fired_hella_incoming_0; // @[lsu.scala:906:37]
reg fired_hella_wakeup_0; // @[lsu.scala:907:37]
wire [6:0] _mem_incoming_uop_WIRE_0_uopc = mem_incoming_uop_out_uopc; // @[util.scala:96:23]
wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:96:23]
wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:96:23]
wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:96:23]
wire [2:0] _mem_incoming_uop_WIRE_0_iq_type = mem_incoming_uop_out_iq_type; // @[util.scala:96:23]
wire [9:0] _mem_incoming_uop_WIRE_0_fu_code = mem_incoming_uop_out_fu_code; // @[util.scala:96:23]
wire [3:0] _mem_incoming_uop_WIRE_0_ctrl_br_type = mem_incoming_uop_out_ctrl_br_type; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_ctrl_op1_sel = mem_incoming_uop_out_ctrl_op1_sel; // @[util.scala:96:23]
wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_op2_sel = mem_incoming_uop_out_ctrl_op2_sel; // @[util.scala:96:23]
wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_imm_sel = mem_incoming_uop_out_ctrl_imm_sel; // @[util.scala:96:23]
wire [4:0] _mem_incoming_uop_WIRE_0_ctrl_op_fcn = mem_incoming_uop_out_ctrl_op_fcn; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_ctrl_fcn_dw = mem_incoming_uop_out_ctrl_fcn_dw; // @[util.scala:96:23]
wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_csr_cmd = mem_incoming_uop_out_ctrl_csr_cmd; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_ctrl_is_load = mem_incoming_uop_out_ctrl_is_load; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_ctrl_is_sta = mem_incoming_uop_out_ctrl_is_sta; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_ctrl_is_std = mem_incoming_uop_out_ctrl_is_std; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_iw_state = mem_incoming_uop_out_iw_state; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_iw_p1_poisoned = mem_incoming_uop_out_iw_p1_poisoned; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_iw_p2_poisoned = mem_incoming_uop_out_iw_p2_poisoned; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_br = mem_incoming_uop_out_is_br; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_jalr = mem_incoming_uop_out_is_jalr; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_jal = mem_incoming_uop_out_is_jal; // @[util.scala:96:23]
wire [15:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25]
wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:96:23]
wire [15:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:96:23]
wire [3:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:96:23]
wire [4:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:96:23]
wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:96:23]
wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:96:23]
wire [11:0] _mem_incoming_uop_WIRE_0_csr_addr = mem_incoming_uop_out_csr_addr; // @[util.scala:96:23]
wire [6:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:96:23]
wire [4:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:96:23]
wire [4:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:96:23]
wire [6:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:96:23]
wire [6:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:96:23]
wire [6:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:96:23]
wire [6:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:96:23]
wire [4:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:96:23]
wire [6:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:96:23]
wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_bypassable = mem_incoming_uop_out_bypassable; // @[util.scala:96:23]
wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:96:23]
wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:96:23]
wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:96:23]
wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:96:23]
wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_ldst_val = mem_incoming_uop_out_ldst_val; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_fp_single = mem_incoming_uop_out_fp_single; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:96:23]
wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:96:23]
wire [1:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:96:23]
wire [15:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
assign _mem_incoming_uop_out_br_mask_T_1 = exe_req_0_bits_uop_br_mask & _mem_incoming_uop_out_br_mask_T; // @[util.scala:85:{25,27}]
assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23]
reg [6:0] mem_incoming_uop_0_uopc; // @[lsu.scala:909:37]
reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:909:37]
reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:909:37]
reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:909:37]
reg [2:0] mem_incoming_uop_0_iq_type; // @[lsu.scala:909:37]
reg [9:0] mem_incoming_uop_0_fu_code; // @[lsu.scala:909:37]
reg [3:0] mem_incoming_uop_0_ctrl_br_type; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_ctrl_op1_sel; // @[lsu.scala:909:37]
reg [2:0] mem_incoming_uop_0_ctrl_op2_sel; // @[lsu.scala:909:37]
reg [2:0] mem_incoming_uop_0_ctrl_imm_sel; // @[lsu.scala:909:37]
reg [4:0] mem_incoming_uop_0_ctrl_op_fcn; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_ctrl_fcn_dw; // @[lsu.scala:909:37]
reg [2:0] mem_incoming_uop_0_ctrl_csr_cmd; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_ctrl_is_load; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_ctrl_is_sta; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_ctrl_is_std; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_iw_state; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_iw_p1_poisoned; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_iw_p2_poisoned; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_br; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_jalr; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_jal; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:909:37]
reg [15:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:909:37]
reg [3:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:909:37]
reg [4:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:909:37]
reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_taken; // @[lsu.scala:909:37]
reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:909:37]
reg [11:0] mem_incoming_uop_0_csr_addr; // @[lsu.scala:909:37]
reg [6:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:909:37]
reg [4:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:909:37]
reg [4:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:909:37]
reg [6:0] mem_incoming_uop_0_pdst; // @[lsu.scala:909:37]
assign io_core_spec_ld_wakeup_0_bits_0 = mem_incoming_uop_0_pdst; // @[lsu.scala:201:7, :909:37]
reg [6:0] mem_incoming_uop_0_prs1; // @[lsu.scala:909:37]
reg [6:0] mem_incoming_uop_0_prs2; // @[lsu.scala:909:37]
reg [6:0] mem_incoming_uop_0_prs3; // @[lsu.scala:909:37]
reg [4:0] mem_incoming_uop_0_ppred; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:909:37]
reg [6:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_exception; // @[lsu.scala:909:37]
reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_bypassable; // @[lsu.scala:909:37]
reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_fence; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_amo; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_is_unique; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:909:37]
reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:909:37]
reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:909:37]
reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:909:37]
reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_ldst_val; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_fp_single; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:909:37]
reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:909:37]
reg [1:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:909:37]
wire _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:108:31]
wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:106:23]
wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_uopc = mem_ldq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23]
wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23]
wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23]
wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23]
wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type = mem_ldq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23]
wire [9:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code = mem_ldq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23]
wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_ldq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23]
wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23]
wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23]
wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_ldq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_ldq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_state = mem_ldq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_br = mem_ldq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_ldq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jal = mem_ldq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23]
wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23]
wire [15:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23]
wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23]
wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23]
wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23]
wire [11:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_ldq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23]
wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23]
wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23]
wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23]
wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23]
wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23]
wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23]
wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bypassable = mem_ldq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23]
wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23]
wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23]
wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23]
wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_ldq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_single = mem_ldq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23]
wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23]
wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:106:23]
wire [23:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_youngest_stq_idx = mem_ldq_incoming_e_out_bits_youngest_stq_idx; // @[util.scala:106:23]
wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:106:23]
wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:106:23]
wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23]
wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23]
wire [15:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51]
wire _mem_ldq_incoming_e_out_valid_T_1 = |_mem_ldq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}]
wire _mem_ldq_incoming_e_out_valid_T_2 = ~_mem_ldq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59]
assign _mem_ldq_incoming_e_out_valid_T_3 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}]
assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31]
reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:910:37]
reg [6:0] mem_ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:910:37]
reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:910:37]
reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:910:37]
reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:910:37]
reg [2:0] mem_ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:910:37]
reg [9:0] mem_ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:910:37]
reg [3:0] mem_ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:910:37]
reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:910:37]
reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:910:37]
reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:910:37]
reg [15:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:910:37]
reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:910:37]
reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:910:37]
reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:910:37]
reg [11:0] mem_ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:910:37]
reg [6:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:910:37]
reg [6:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:910:37]
reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:910:37]
reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:910:37]
reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:910:37]
reg [6:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:910:37]
reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:910:37]
reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:910:37]
reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:910:37]
reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:910:37]
reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:910:37]
reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:910:37]
reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:910:37]
reg [23:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:910:37]
reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:910:37]
reg [4:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:910:37]
reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:910:37]
wire _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:108:31]
wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:106:23]
wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_uopc = mem_stq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23]
wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23]
wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23]
wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23]
wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type = mem_stq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23]
wire [9:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code = mem_stq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23]
wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_stq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23]
wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23]
wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23]
wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23]
wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_stq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_stq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_stq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_state = mem_stq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_br = mem_stq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_stq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jal = mem_stq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23]
wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23]
wire [15:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23]
wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23]
wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23]
wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23]
wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23]
wire [11:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_stq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23]
wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23]
wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23]
wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23]
wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23]
wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23]
wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23]
wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23]
wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23]
wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23]
wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_bypassable = mem_stq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23]
wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23]
wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23]
wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23]
wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23]
wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_stq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_single = mem_stq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23]
wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23]
wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:106:23]
wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:106:23]
wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:106:23]
wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23]
wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23]
wire [15:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51]
wire _mem_stq_incoming_e_out_valid_T_1 = |_mem_stq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}]
wire _mem_stq_incoming_e_out_valid_T_2 = ~_mem_stq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59]
assign _mem_stq_incoming_e_out_valid_T_3 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}]
assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31]
reg mem_stq_incoming_e_0_valid; // @[lsu.scala:911:37]
reg [6:0] mem_stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:911:37]
reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:911:37]
reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:911:37]
reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:911:37]
reg [2:0] mem_stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:911:37]
reg [9:0] mem_stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:911:37]
reg [3:0] mem_stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37]
reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37]
reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37]
reg [4:0] mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37]
reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:911:37]
reg [15:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:911:37]
reg [3:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:911:37]
reg [4:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:911:37]
reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:911:37]
reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:911:37]
reg [11:0] mem_stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:911:37]
reg [6:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:911:37]
reg [4:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:911:37]
reg [4:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:911:37]
reg [6:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:911:37]
reg [6:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:911:37]
reg [6:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:911:37]
reg [6:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:911:37]
reg [4:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:911:37]
reg [6:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:911:37]
reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:911:37]
reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37]
reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:911:37]
reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:911:37]
reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:911:37]
reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:911:37]
reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37]
reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37]
reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:911:37]
reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:911:37]
reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:911:37]
wire _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:108:31]
wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21]
wire [15:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:106:23]
wire mem_ldq_wakeup_e_out_valid; // @[util.scala:106:23]
wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = _GEN_125[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23]
wire _mem_ldq_wakeup_e_out_valid_T_1 = |_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:{51,59}]
wire _mem_ldq_wakeup_e_out_valid_T_2 = ~_mem_ldq_wakeup_e_out_valid_T_1; // @[util.scala:108:34, :118:59]
assign _mem_ldq_wakeup_e_out_valid_T_3 = _GEN_94[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:108:{31,34}]
assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:106:23, :108:31]
reg mem_ldq_wakeup_e_valid; // @[lsu.scala:912:37]
reg [6:0] mem_ldq_wakeup_e_bits_uop_uopc; // @[lsu.scala:912:37]
reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:912:37]
reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:912:37]
reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:912:37]
reg [2:0] mem_ldq_wakeup_e_bits_uop_iq_type; // @[lsu.scala:912:37]
reg [9:0] mem_ldq_wakeup_e_bits_uop_fu_code; // @[lsu.scala:912:37]
reg [3:0] mem_ldq_wakeup_e_bits_uop_ctrl_br_type; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:912:37]
reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:912:37]
reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:912:37]
reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_state; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:912:37]
reg [15:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:912:37]
reg [3:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:912:37]
reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:912:37]
reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:912:37]
reg [11:0] mem_ldq_wakeup_e_bits_uop_csr_addr; // @[lsu.scala:912:37]
reg [6:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:912:37]
reg [6:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:912:37]
reg [6:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:912:37]
reg [6:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:912:37]
reg [6:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:912:37]
reg [6:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:912:37]
reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:912:37]
reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:912:37]
reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:912:37]
reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:912:37]
reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:912:37]
reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:912:37]
reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:912:37]
reg [23:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_youngest_stq_idx; // @[lsu.scala:912:37]
reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:912:37]
reg [4:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:912:37]
reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:912:37]
wire _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:108:31]
wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21]
wire [15:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23]
wire mem_ldq_retry_e_out_valid; // @[util.scala:106:23]
wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_125[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23]
wire _mem_ldq_retry_e_out_valid_T_1 = |_mem_ldq_retry_e_out_valid_T; // @[util.scala:118:{51,59}]
wire _mem_ldq_retry_e_out_valid_T_2 = ~_mem_ldq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59]
assign _mem_ldq_retry_e_out_valid_T_3 = _GEN_94[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}]
assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31]
reg mem_ldq_retry_e_valid; // @[lsu.scala:913:37]
reg [6:0] mem_ldq_retry_e_bits_uop_uopc; // @[lsu.scala:913:37]
reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:913:37]
reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:913:37]
reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:913:37]
reg [2:0] mem_ldq_retry_e_bits_uop_iq_type; // @[lsu.scala:913:37]
reg [9:0] mem_ldq_retry_e_bits_uop_fu_code; // @[lsu.scala:913:37]
reg [3:0] mem_ldq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:913:37]
reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:913:37]
reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:913:37]
reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_iw_state; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_br; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_jalr; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_jal; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:913:37]
reg [15:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:913:37]
reg [3:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:913:37]
reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:913:37]
reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:913:37]
reg [11:0] mem_ldq_retry_e_bits_uop_csr_addr; // @[lsu.scala:913:37]
reg [6:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:913:37]
reg [6:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:913:37]
reg [6:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:913:37]
reg [6:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:913:37]
reg [6:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:913:37]
reg [6:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:913:37]
reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_bypassable; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:913:37]
reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:913:37]
reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:913:37]
reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:913:37]
reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_ldst_val; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_fp_single; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:913:37]
reg [1:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:913:37]
reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:913:37]
reg [23:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_youngest_stq_idx; // @[lsu.scala:913:37]
reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:913:37]
reg [4:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:913:37]
reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:913:37]
wire _mem_stq_retry_e_out_valid_T_3; // @[util.scala:108:31]
wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21]
wire [15:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23]
wire mem_stq_retry_e_out_valid; // @[util.scala:106:23]
wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_25[_stq_retry_e_T_1] & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23]
wire _mem_stq_retry_e_out_valid_T_1 = |_mem_stq_retry_e_out_valid_T; // @[util.scala:118:{51,59}]
wire _mem_stq_retry_e_out_valid_T_2 = ~_mem_stq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59]
assign _mem_stq_retry_e_out_valid_T_3 = _GEN[_stq_retry_e_T_1] & _mem_stq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}]
assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31]
reg mem_stq_retry_e_valid; // @[lsu.scala:914:37]
reg [6:0] mem_stq_retry_e_bits_uop_uopc; // @[lsu.scala:914:37]
reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:914:37]
reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:914:37]
reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:914:37]
reg [2:0] mem_stq_retry_e_bits_uop_iq_type; // @[lsu.scala:914:37]
reg [9:0] mem_stq_retry_e_bits_uop_fu_code; // @[lsu.scala:914:37]
reg [3:0] mem_stq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:914:37]
reg [2:0] mem_stq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:914:37]
reg [2:0] mem_stq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:914:37]
reg [4:0] mem_stq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:914:37]
reg [2:0] mem_stq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_iw_state; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:914:37]
reg [15:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:914:37]
reg [3:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:914:37]
reg [4:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:914:37]
reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:914:37]
reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:914:37]
reg [11:0] mem_stq_retry_e_bits_uop_csr_addr; // @[lsu.scala:914:37]
reg [6:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:914:37]
reg [4:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:914:37]
reg [4:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:914:37]
reg [6:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:914:37]
reg [6:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:914:37]
reg [6:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:914:37]
reg [6:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:914:37]
reg [4:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:914:37]
reg [6:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:914:37]
reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:914:37]
reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:914:37]
reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:914:37]
reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:914:37]
reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:914:37]
reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:914:37]
reg [1:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:914:37]
reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37]
reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_committed; // @[lsu.scala:914:37]
reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:914:37]
reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:914:37]
wire _mem_ldq_e_T_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:263:49, :912:37, :918:33]
wire [6:0] _mem_ldq_e_T_bits_uop_uopc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [31:0] _mem_ldq_e_T_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [31:0] _mem_ldq_e_T_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :912:37, :918:33]
wire [39:0] _mem_ldq_e_T_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [2:0] _mem_ldq_e_T_bits_uop_iq_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [9:0] _mem_ldq_e_T_bits_uop_fu_code = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [3:0] _mem_ldq_e_T_bits_uop_ctrl_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_ctrl_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_uop_ctrl_op_fcn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_ctrl_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :912:37, :918:33]
wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_ctrl_is_load = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_ctrl_is_sta = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_ctrl_is_std = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_iw_state = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_iw_p1_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_iw_p2_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_br = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_jalr = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_jal = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :912:37, :918:33]
wire [15:0] _mem_ldq_e_T_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [3:0] _mem_ldq_e_T_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :912:37, :918:33]
wire [5:0] _mem_ldq_e_T_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:263:49, :912:37, :918:33]
wire [19:0] _mem_ldq_e_T_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [11:0] _mem_ldq_e_T_bits_uop_csr_addr = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [6:0] _mem_ldq_e_T_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [6:0] _mem_ldq_e_T_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [6:0] _mem_ldq_e_T_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [6:0] _mem_ldq_e_T_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [6:0] _mem_ldq_e_T_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :912:37, :918:33]
wire [6:0] _mem_ldq_e_T_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:263:49, :912:37, :918:33]
wire [63:0] _mem_ldq_e_T_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_bypassable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :912:37, :918:33]
wire [5:0] _mem_ldq_e_T_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [5:0] _mem_ldq_e_T_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [5:0] _mem_ldq_e_T_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [5:0] _mem_ldq_e_T_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_ldst_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_fp_single = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [1:0] _mem_ldq_e_T_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:263:49, :912:37, :918:33]
wire [39:0] _mem_ldq_e_T_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:263:49, :912:37, :918:33]
wire [23:0] _mem_ldq_e_T_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 24'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_youngest_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_youngest_stq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:263:49, :912:37, :918:33]
wire [4:0] _mem_ldq_e_T_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire [63:0] _mem_ldq_e_T_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33]
wire _mem_ldq_e_T_1_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [6:0] _mem_ldq_e_T_1_bits_uop_uopc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uopc : _mem_ldq_e_T_bits_uop_uopc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_bits_uop_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_bits_uop_debug_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_bits_uop_is_rvc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_bits_uop_debug_pc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [2:0] _mem_ldq_e_T_1_bits_uop_iq_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type : _mem_ldq_e_T_bits_uop_iq_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [9:0] _mem_ldq_e_T_1_bits_uop_fu_code = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code : _mem_ldq_e_T_bits_uop_fu_code; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [3:0] _mem_ldq_e_T_1_bits_uop_ctrl_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_br_type : _mem_ldq_e_T_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_ctrl_is_load = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_load : _mem_ldq_e_T_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_ctrl_is_sta = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_sta : _mem_ldq_e_T_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_ctrl_is_std = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_std : _mem_ldq_e_T_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_state = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_state : _mem_ldq_e_T_bits_uop_iw_state; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_br = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_br : _mem_ldq_e_T_bits_uop_is_br; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_jalr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jalr : _mem_ldq_e_T_bits_uop_is_jalr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_jal = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jal : _mem_ldq_e_T_bits_uop_is_jal; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_bits_uop_is_sfb; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [15:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_bits_uop_br_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [3:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_bits_uop_br_tag; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_bits_uop_ftq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_bits_uop_edge_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_bits_uop_pc_lob; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_bits_uop_taken; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_bits_uop_imm_packed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [11:0] _mem_ldq_e_T_1_bits_uop_csr_addr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_addr : _mem_ldq_e_T_bits_uop_csr_addr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [6:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_bits_uop_rob_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_bits_uop_ldq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_bits_uop_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_bits_uop_rxq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [6:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_bits_uop_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [6:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_bits_uop_prs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [6:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_bits_uop_prs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [6:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_bits_uop_prs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_bits_uop_ppred; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_bits_uop_prs1_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_bits_uop_prs2_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_bits_uop_prs3_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_bits_uop_ppred_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [6:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_bits_uop_stale_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_bits_uop_exception; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_bits_uop_exc_cause; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_bypassable = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bypassable : _mem_ldq_e_T_bits_uop_bypassable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_bits_uop_mem_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_bits_uop_mem_size; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_bits_uop_mem_signed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_bits_uop_is_fence; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_bits_uop_is_fencei; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_bits_uop_is_amo; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_bits_uop_uses_ldq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_bits_uop_uses_stq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_bits_uop_is_unique; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_bits_uop_ldst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_bits_uop_lrs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_bits_uop_lrs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_bits_uop_lrs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_ldst_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_val : _mem_ldq_e_T_bits_uop_ldst_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_bits_uop_dst_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_bits_uop_frs3_en; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_bits_uop_fp_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_fp_single = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_single : _mem_ldq_e_T_bits_uop_fp_single; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_bits_addr_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_bits_addr_bits; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_bits_addr_is_virtual; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_bits_executed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_bits_succeeded; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_bits_order_fail; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_bits_observed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [23:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_bits_st_dep_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_youngest_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_youngest_stq_idx : _mem_ldq_e_T_bits_youngest_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_bits_forward_std_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [4:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_bits_forward_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_bits_debug_wb_data; // @[lsu.scala:263:49, :913:37, :917:33, :918:33]
wire _mem_ldq_e_T_2_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [6:0] _mem_ldq_e_T_2_bits_uop_uopc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uopc : _mem_ldq_e_T_1_bits_uop_uopc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [2:0] _mem_ldq_e_T_2_bits_uop_iq_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iq_type : _mem_ldq_e_T_1_bits_uop_iq_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [9:0] _mem_ldq_e_T_2_bits_uop_fu_code = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fu_code : _mem_ldq_e_T_1_bits_uop_fu_code; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [3:0] _mem_ldq_e_T_2_bits_uop_ctrl_br_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_br_type : _mem_ldq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_ctrl_is_load = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_load : _mem_ldq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_ctrl_is_sta = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_ldq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_ctrl_is_std = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_std : _mem_ldq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_state = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_state : _mem_ldq_e_T_1_bits_uop_iw_state; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_br = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_br : _mem_ldq_e_T_1_bits_uop_is_br; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_jalr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jalr : _mem_ldq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_jal = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jal : _mem_ldq_e_T_1_bits_uop_is_jal; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [15:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [3:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [11:0] _mem_ldq_e_T_2_bits_uop_csr_addr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_csr_addr : _mem_ldq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [6:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [6:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [6:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [6:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [6:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [6:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_bypassable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bypassable : _mem_ldq_e_T_1_bits_uop_bypassable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_ldst_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_val : _mem_ldq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_fp_single = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_single : _mem_ldq_e_T_1_bits_uop_fp_single; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_executed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_succeeded = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_order_fail = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_observed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [23:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_youngest_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_youngest_stq_idx : _mem_ldq_e_T_1_bits_youngest_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [4:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:263:49, :910:37, :916:33, :917:33]
wire mem_ldq_e_0_valid = _mem_ldq_e_T_2_valid; // @[lsu.scala:263:49, :916:33]
wire [6:0] mem_ldq_e_0_bits_uop_uopc = _mem_ldq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :916:33]
wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :916:33]
wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :916:33]
wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :916:33]
wire [2:0] mem_ldq_e_0_bits_uop_iq_type = _mem_ldq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :916:33]
wire [9:0] mem_ldq_e_0_bits_uop_fu_code = _mem_ldq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :916:33]
wire [3:0] mem_ldq_e_0_bits_uop_ctrl_br_type = _mem_ldq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_ctrl_op1_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :916:33]
wire [2:0] mem_ldq_e_0_bits_uop_ctrl_op2_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :916:33]
wire [2:0] mem_ldq_e_0_bits_uop_ctrl_imm_sel = _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_uop_ctrl_op_fcn = _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_ctrl_fcn_dw = _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :916:33]
wire [2:0] mem_ldq_e_0_bits_uop_ctrl_csr_cmd = _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_ctrl_is_load = _mem_ldq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_ctrl_is_sta = _mem_ldq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_ctrl_is_std = _mem_ldq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_iw_state = _mem_ldq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_iw_p1_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_iw_p2_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_br = _mem_ldq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_jalr = _mem_ldq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_jal = _mem_ldq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :916:33]
wire [15:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :916:33]
wire [3:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :916:33]
wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :916:33]
wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :916:33]
wire [11:0] mem_ldq_e_0_bits_uop_csr_addr = _mem_ldq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :916:33]
wire [6:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :916:33]
wire [6:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :916:33]
wire [6:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :916:33]
wire [6:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :916:33]
wire [6:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :916:33]
wire [6:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :916:33]
wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_bypassable = _mem_ldq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :916:33]
wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :916:33]
wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :916:33]
wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :916:33]
wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_ldst_val = _mem_ldq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_fp_single = _mem_ldq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :916:33]
wire [1:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :916:33]
wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:263:49, :916:33]
wire [23:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_youngest_stq_idx = _mem_ldq_e_T_2_bits_youngest_stq_idx; // @[lsu.scala:263:49, :916:33]
wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:263:49, :916:33]
wire [4:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:263:49, :916:33]
wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :916:33]
wire [23:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:263:49]
wire _GEN_301 = fired_stad_incoming_0 | fired_sta_incoming_0; // @[lsu.scala:263:49, :920:57]
wire _mem_stq_e_T; // @[lsu.scala:920:57]
assign _mem_stq_e_T = _GEN_301; // @[lsu.scala:920:57]
wire _do_st_search_T; // @[lsu.scala:1015:60]
assign _do_st_search_T = _GEN_301; // @[lsu.scala:920:57, :1015:60]
wire _lcam_addr_T; // @[lsu.scala:1026:61]
assign _lcam_addr_T = _GEN_301; // @[lsu.scala:920:57, :1026:61]
wire _lcam_stq_idx_T; // @[lsu.scala:1041:50]
assign _lcam_stq_idx_T = _GEN_301; // @[lsu.scala:920:57, :1041:50]
wire _mem_stq_e_T_1_valid = fired_sta_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:263:49, :914:37, :922:33]
wire [6:0] _mem_stq_e_T_1_bits_uop_uopc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :914:37, :922:33]
wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [2:0] _mem_stq_e_T_1_bits_uop_iq_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [9:0] _mem_stq_e_T_1_bits_uop_fu_code = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [3:0] _mem_stq_e_T_1_bits_uop_ctrl_br_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_ctrl_op1_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_op2_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_imm_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [4:0] _mem_stq_e_T_1_bits_uop_ctrl_op_fcn = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :914:37, :922:33]
wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_ctrl_is_load = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_ctrl_is_sta = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_ctrl_is_std = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_iw_state = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_iw_p1_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_iw_p2_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_br = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_jalr = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_jal = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :914:37, :922:33]
wire [15:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [3:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [4:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :914:37, :922:33]
wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_taken = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:263:49, :914:37, :922:33]
wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [11:0] _mem_stq_e_T_1_bits_uop_csr_addr = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [6:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [4:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [4:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [6:0] _mem_stq_e_T_1_bits_uop_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [6:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [6:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [6:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [4:0] _mem_stq_e_T_1_bits_uop_ppred = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :914:37, :922:33]
wire [6:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_exception = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:263:49, :914:37, :922:33]
wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_bypassable = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:263:49, :914:37, :922:33]
wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_fence = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_amo = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_is_unique = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :914:37, :922:33]
wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_ldst_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_fp_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_fp_single = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire [1:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_addr_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:263:49, :914:37, :922:33]
wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_data_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:263:49, :914:37, :922:33]
wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_committed = fired_sta_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_1_bits_succeeded = fired_sta_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:263:49, :914:37, :922:33]
wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_sta_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33]
wire _mem_stq_e_T_2_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_1_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [6:0] _mem_stq_e_T_2_bits_uop_uopc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uopc : _mem_stq_e_T_1_bits_uop_uopc; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [31:0] _mem_stq_e_T_2_bits_uop_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [31:0] _mem_stq_e_T_2_bits_uop_debug_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_rvc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [39:0] _mem_stq_e_T_2_bits_uop_debug_pc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [2:0] _mem_stq_e_T_2_bits_uop_iq_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iq_type : _mem_stq_e_T_1_bits_uop_iq_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [9:0] _mem_stq_e_T_2_bits_uop_fu_code = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fu_code : _mem_stq_e_T_1_bits_uop_fu_code; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [3:0] _mem_stq_e_T_2_bits_uop_ctrl_br_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_br_type : _mem_stq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_ctrl_op1_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_stq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_op2_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_stq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_imm_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_stq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [4:0] _mem_stq_e_T_2_bits_uop_ctrl_op_fcn = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_stq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_ctrl_is_load = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_load : _mem_stq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_ctrl_is_sta = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_stq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_ctrl_is_std = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_std : _mem_stq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_iw_state = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_state : _mem_stq_e_T_1_bits_uop_iw_state; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_iw_p1_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_stq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_iw_p2_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_stq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_br = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_br : _mem_stq_e_T_1_bits_uop_is_br; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_jalr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jalr : _mem_stq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_jal = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jal : _mem_stq_e_T_1_bits_uop_is_jal; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_sfb = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [15:0] _mem_stq_e_T_2_bits_uop_br_mask = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [3:0] _mem_stq_e_T_2_bits_uop_br_tag = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [4:0] _mem_stq_e_T_2_bits_uop_ftq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_edge_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [5:0] _mem_stq_e_T_2_bits_uop_pc_lob = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_taken = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [19:0] _mem_stq_e_T_2_bits_uop_imm_packed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [11:0] _mem_stq_e_T_2_bits_uop_csr_addr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_csr_addr : _mem_stq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [6:0] _mem_stq_e_T_2_bits_uop_rob_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [4:0] _mem_stq_e_T_2_bits_uop_ldq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [4:0] _mem_stq_e_T_2_bits_uop_stq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_rxq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [6:0] _mem_stq_e_T_2_bits_uop_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [6:0] _mem_stq_e_T_2_bits_uop_prs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [6:0] _mem_stq_e_T_2_bits_uop_prs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [6:0] _mem_stq_e_T_2_bits_uop_prs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [4:0] _mem_stq_e_T_2_bits_uop_ppred = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_prs1_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_prs2_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_prs3_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_ppred_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [6:0] _mem_stq_e_T_2_bits_uop_stale_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_exception = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [63:0] _mem_stq_e_T_2_bits_uop_exc_cause = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_bypassable = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bypassable : _mem_stq_e_T_1_bits_uop_bypassable; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [4:0] _mem_stq_e_T_2_bits_uop_mem_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_mem_size = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_mem_signed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_fence = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_fencei = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_amo = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_uses_ldq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_uses_stq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_sys_pc2epc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_is_unique = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_flush_on_commit = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_ldst_is_rs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [5:0] _mem_stq_e_T_2_bits_uop_ldst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [5:0] _mem_stq_e_T_2_bits_uop_lrs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [5:0] _mem_stq_e_T_2_bits_uop_lrs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [5:0] _mem_stq_e_T_2_bits_uop_lrs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_ldst_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_val : _mem_stq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_dst_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_lrs1_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_lrs2_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_frs3_en = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_fp_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_fp_single = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_single : _mem_stq_e_T_1_bits_uop_fp_single; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_xcpt_pf_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_xcpt_ae_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_xcpt_ma_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_bp_debug_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_uop_bp_xcpt_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_debug_fsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [1:0] _mem_stq_e_T_2_bits_uop_debug_tsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_addr_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [39:0] _mem_stq_e_T_2_bits_addr_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_addr_is_virtual = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_data_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [63:0] _mem_stq_e_T_2_bits_data_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_committed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_1_bits_committed; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire _mem_stq_e_T_2_bits_succeeded = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire [63:0] _mem_stq_e_T_2_bits_debug_wb_data = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:911:37, :920:{33,57}, :922:33]
wire mem_stq_e_0_valid = _mem_stq_e_T_2_valid; // @[lsu.scala:263:49, :920:33]
wire [6:0] mem_stq_e_0_bits_uop_uopc = _mem_stq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :920:33]
wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :920:33]
wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :920:33]
wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :920:33]
wire [2:0] mem_stq_e_0_bits_uop_iq_type = _mem_stq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :920:33]
wire [9:0] mem_stq_e_0_bits_uop_fu_code = _mem_stq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :920:33]
wire [3:0] mem_stq_e_0_bits_uop_ctrl_br_type = _mem_stq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_ctrl_op1_sel = _mem_stq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :920:33]
wire [2:0] mem_stq_e_0_bits_uop_ctrl_op2_sel = _mem_stq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :920:33]
wire [2:0] mem_stq_e_0_bits_uop_ctrl_imm_sel = _mem_stq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :920:33]
wire [4:0] mem_stq_e_0_bits_uop_ctrl_op_fcn = _mem_stq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_ctrl_fcn_dw = _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :920:33]
wire [2:0] mem_stq_e_0_bits_uop_ctrl_csr_cmd = _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_ctrl_is_load = _mem_stq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_ctrl_is_sta = _mem_stq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_ctrl_is_std = _mem_stq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_iw_state = _mem_stq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_iw_p1_poisoned = _mem_stq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_iw_p2_poisoned = _mem_stq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_br = _mem_stq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_jalr = _mem_stq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_jal = _mem_stq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :920:33]
wire [15:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :920:33]
wire [3:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :920:33]
wire [4:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :920:33]
wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :920:33]
wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :920:33]
wire [11:0] mem_stq_e_0_bits_uop_csr_addr = _mem_stq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :920:33]
wire [6:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :920:33]
wire [4:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :920:33]
wire [4:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :920:33]
wire [6:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :920:33]
wire [6:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :920:33]
wire [6:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :920:33]
wire [6:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :920:33]
wire [4:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :920:33]
wire [6:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :920:33]
wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_bypassable = _mem_stq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :920:33]
wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :920:33]
wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :920:33]
wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :920:33]
wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :920:33]
wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_ldst_val = _mem_stq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_fp_single = _mem_stq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :920:33]
wire [1:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :920:33]
wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_2_bits_data_valid; // @[lsu.scala:263:49, :920:33]
wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_2_bits_data_bits; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_committed = _mem_stq_e_T_2_bits_committed; // @[lsu.scala:263:49, :920:33]
wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :920:33]
wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :920:33]
wire [15:0] _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25]
wire [15:0] mem_stdf_uop_out_br_mask; // @[util.scala:96:23]
wire [15:0] _mem_stdf_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
assign _mem_stdf_uop_out_br_mask_T_1 = io_core_fp_stdata_bits_uop_br_mask_0 & _mem_stdf_uop_out_br_mask_T; // @[util.scala:85:{25,27}]
assign mem_stdf_uop_out_br_mask = _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23]
reg [6:0] mem_stdf_uop_uopc; // @[lsu.scala:923:37]
reg [31:0] mem_stdf_uop_inst; // @[lsu.scala:923:37]
reg [31:0] mem_stdf_uop_debug_inst; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_rvc; // @[lsu.scala:923:37]
reg [39:0] mem_stdf_uop_debug_pc; // @[lsu.scala:923:37]
reg [2:0] mem_stdf_uop_iq_type; // @[lsu.scala:923:37]
reg [9:0] mem_stdf_uop_fu_code; // @[lsu.scala:923:37]
reg [3:0] mem_stdf_uop_ctrl_br_type; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_ctrl_op1_sel; // @[lsu.scala:923:37]
reg [2:0] mem_stdf_uop_ctrl_op2_sel; // @[lsu.scala:923:37]
reg [2:0] mem_stdf_uop_ctrl_imm_sel; // @[lsu.scala:923:37]
reg [4:0] mem_stdf_uop_ctrl_op_fcn; // @[lsu.scala:923:37]
reg mem_stdf_uop_ctrl_fcn_dw; // @[lsu.scala:923:37]
reg [2:0] mem_stdf_uop_ctrl_csr_cmd; // @[lsu.scala:923:37]
reg mem_stdf_uop_ctrl_is_load; // @[lsu.scala:923:37]
reg mem_stdf_uop_ctrl_is_sta; // @[lsu.scala:923:37]
reg mem_stdf_uop_ctrl_is_std; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_iw_state; // @[lsu.scala:923:37]
reg mem_stdf_uop_iw_p1_poisoned; // @[lsu.scala:923:37]
reg mem_stdf_uop_iw_p2_poisoned; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_br; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_jalr; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_jal; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_sfb; // @[lsu.scala:923:37]
reg [15:0] mem_stdf_uop_br_mask; // @[lsu.scala:923:37]
reg [3:0] mem_stdf_uop_br_tag; // @[lsu.scala:923:37]
reg [4:0] mem_stdf_uop_ftq_idx; // @[lsu.scala:923:37]
reg mem_stdf_uop_edge_inst; // @[lsu.scala:923:37]
reg [5:0] mem_stdf_uop_pc_lob; // @[lsu.scala:923:37]
reg mem_stdf_uop_taken; // @[lsu.scala:923:37]
reg [19:0] mem_stdf_uop_imm_packed; // @[lsu.scala:923:37]
reg [11:0] mem_stdf_uop_csr_addr; // @[lsu.scala:923:37]
reg [6:0] mem_stdf_uop_rob_idx; // @[lsu.scala:923:37]
reg [4:0] mem_stdf_uop_ldq_idx; // @[lsu.scala:923:37]
reg [4:0] mem_stdf_uop_stq_idx; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_rxq_idx; // @[lsu.scala:923:37]
reg [6:0] mem_stdf_uop_pdst; // @[lsu.scala:923:37]
reg [6:0] mem_stdf_uop_prs1; // @[lsu.scala:923:37]
reg [6:0] mem_stdf_uop_prs2; // @[lsu.scala:923:37]
reg [6:0] mem_stdf_uop_prs3; // @[lsu.scala:923:37]
reg [4:0] mem_stdf_uop_ppred; // @[lsu.scala:923:37]
reg mem_stdf_uop_prs1_busy; // @[lsu.scala:923:37]
reg mem_stdf_uop_prs2_busy; // @[lsu.scala:923:37]
reg mem_stdf_uop_prs3_busy; // @[lsu.scala:923:37]
reg mem_stdf_uop_ppred_busy; // @[lsu.scala:923:37]
reg [6:0] mem_stdf_uop_stale_pdst; // @[lsu.scala:923:37]
reg mem_stdf_uop_exception; // @[lsu.scala:923:37]
reg [63:0] mem_stdf_uop_exc_cause; // @[lsu.scala:923:37]
reg mem_stdf_uop_bypassable; // @[lsu.scala:923:37]
reg [4:0] mem_stdf_uop_mem_cmd; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_mem_size; // @[lsu.scala:923:37]
reg mem_stdf_uop_mem_signed; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_fence; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_fencei; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_amo; // @[lsu.scala:923:37]
reg mem_stdf_uop_uses_ldq; // @[lsu.scala:923:37]
reg mem_stdf_uop_uses_stq; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_sys_pc2epc; // @[lsu.scala:923:37]
reg mem_stdf_uop_is_unique; // @[lsu.scala:923:37]
reg mem_stdf_uop_flush_on_commit; // @[lsu.scala:923:37]
reg mem_stdf_uop_ldst_is_rs1; // @[lsu.scala:923:37]
reg [5:0] mem_stdf_uop_ldst; // @[lsu.scala:923:37]
reg [5:0] mem_stdf_uop_lrs1; // @[lsu.scala:923:37]
reg [5:0] mem_stdf_uop_lrs2; // @[lsu.scala:923:37]
reg [5:0] mem_stdf_uop_lrs3; // @[lsu.scala:923:37]
reg mem_stdf_uop_ldst_val; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_dst_rtype; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_lrs1_rtype; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_lrs2_rtype; // @[lsu.scala:923:37]
reg mem_stdf_uop_frs3_en; // @[lsu.scala:923:37]
reg mem_stdf_uop_fp_val; // @[lsu.scala:923:37]
reg mem_stdf_uop_fp_single; // @[lsu.scala:923:37]
reg mem_stdf_uop_xcpt_pf_if; // @[lsu.scala:923:37]
reg mem_stdf_uop_xcpt_ae_if; // @[lsu.scala:923:37]
reg mem_stdf_uop_xcpt_ma_if; // @[lsu.scala:923:37]
reg mem_stdf_uop_bp_debug_if; // @[lsu.scala:923:37]
reg mem_stdf_uop_bp_xcpt_if; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_debug_fsrc; // @[lsu.scala:923:37]
reg [1:0] mem_stdf_uop_debug_tsrc; // @[lsu.scala:923:37]
reg mem_tlb_miss_0; // @[lsu.scala:926:41]
reg mem_tlb_uncacheable_0; // @[lsu.scala:927:41]
reg [39:0] mem_paddr_0; // @[lsu.scala:928:41]
reg clr_bsy_valid_0; // @[lsu.scala:931:32]
reg [6:0] clr_bsy_rob_idx_0; // @[lsu.scala:932:28]
assign io_core_clr_bsy_0_bits_0 = clr_bsy_rob_idx_0; // @[lsu.scala:201:7, :932:28]
reg [15:0] clr_bsy_brmask_0; // @[lsu.scala:933:28]
wire _clr_bsy_valid_0_T = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29]
wire _clr_bsy_valid_0_T_1 = mem_stq_incoming_e_0_valid & _clr_bsy_valid_0_T; // @[lsu.scala:911:37, :942:68, :943:29]
wire _clr_bsy_valid_0_T_2 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29]
wire _clr_bsy_valid_0_T_3 = _clr_bsy_valid_0_T_1 & _clr_bsy_valid_0_T_2; // @[lsu.scala:942:68, :943:68, :944:29]
wire [15:0] _GEN_302 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51]
wire [15:0] _clr_bsy_valid_0_T_4; // @[util.scala:118:51]
assign _clr_bsy_valid_0_T_4 = _GEN_302; // @[util.scala:118:51]
wire [15:0] _clr_bsy_valid_0_T_13; // @[util.scala:118:51]
assign _clr_bsy_valid_0_T_13 = _GEN_302; // @[util.scala:118:51]
wire [15:0] _clr_bsy_valid_0_T_22; // @[util.scala:118:51]
assign _clr_bsy_valid_0_T_22 = _GEN_302; // @[util.scala:118:51]
wire _clr_bsy_valid_0_T_5 = |_clr_bsy_valid_0_T_4; // @[util.scala:118:{51,59}]
wire _clr_bsy_valid_0_T_6 = ~_clr_bsy_valid_0_T_5; // @[util.scala:118:59]
wire _clr_bsy_valid_0_T_7 = _clr_bsy_valid_0_T_3 & _clr_bsy_valid_0_T_6; // @[lsu.scala:943:68, :944:68, :945:29]
wire [15:0] _clr_bsy_brmask_0_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _clr_bsy_brmask_0_T_1 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T; // @[util.scala:85:{25,27}]
wire _clr_bsy_valid_0_T_8 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37, :949:69]
wire _clr_bsy_valid_0_T_9 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :951:29]
wire _clr_bsy_valid_0_T_10 = _clr_bsy_valid_0_T_8 & _clr_bsy_valid_0_T_9; // @[lsu.scala:949:69, :950:69, :951:29]
wire _clr_bsy_valid_0_T_11 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :952:29]
wire _clr_bsy_valid_0_T_12 = _clr_bsy_valid_0_T_10 & _clr_bsy_valid_0_T_11; // @[lsu.scala:950:69, :951:69, :952:29]
wire _clr_bsy_valid_0_T_14 = |_clr_bsy_valid_0_T_13; // @[util.scala:118:{51,59}]
wire _clr_bsy_valid_0_T_15 = ~_clr_bsy_valid_0_T_14; // @[util.scala:118:59]
wire _clr_bsy_valid_0_T_16 = _clr_bsy_valid_0_T_12 & _clr_bsy_valid_0_T_15; // @[lsu.scala:951:69, :952:69, :953:29]
wire [15:0] _clr_bsy_brmask_0_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _clr_bsy_brmask_0_T_3 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_2; // @[util.scala:85:{25,27}]
wire _clr_bsy_valid_0_T_17 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37, :957:74]
wire _clr_bsy_valid_0_T_18 = ~mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37, :959:29]
wire _clr_bsy_valid_0_T_19 = _clr_bsy_valid_0_T_17 & _clr_bsy_valid_0_T_18; // @[lsu.scala:957:74, :958:74, :959:29]
wire _clr_bsy_valid_0_T_20 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :960:29]
wire _clr_bsy_valid_0_T_21 = _clr_bsy_valid_0_T_19 & _clr_bsy_valid_0_T_20; // @[lsu.scala:958:74, :959:74, :960:29]
wire _clr_bsy_valid_0_T_23 = |_clr_bsy_valid_0_T_22; // @[util.scala:118:{51,59}]
wire _clr_bsy_valid_0_T_24 = ~_clr_bsy_valid_0_T_23; // @[util.scala:118:59]
wire _clr_bsy_valid_0_T_25 = _clr_bsy_valid_0_T_21 & _clr_bsy_valid_0_T_24; // @[lsu.scala:959:74, :960:74, :961:29]
wire [15:0] _clr_bsy_brmask_0_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _clr_bsy_brmask_0_T_5 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_4; // @[util.scala:85:{25,27}]
wire [15:0] _clr_bsy_brmask_0_T_6 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _clr_bsy_brmask_0_T_7 = mem_incoming_uop_0_br_mask & _clr_bsy_brmask_0_T_6; // @[util.scala:85:{25,27}]
wire _clr_bsy_valid_0_T_26 = mem_stq_retry_e_valid & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37, :969:63]
wire _clr_bsy_valid_0_T_27 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :971:29]
wire _clr_bsy_valid_0_T_28 = _clr_bsy_valid_0_T_26 & _clr_bsy_valid_0_T_27; // @[lsu.scala:969:63, :970:63, :971:29]
wire _clr_bsy_valid_0_T_29 = ~mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37, :972:29]
wire _clr_bsy_valid_0_T_30 = _clr_bsy_valid_0_T_28 & _clr_bsy_valid_0_T_29; // @[lsu.scala:970:63, :971:63, :972:29]
wire [15:0] _clr_bsy_valid_0_T_31 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_bits_uop_br_mask; // @[util.scala:118:51]
wire _clr_bsy_valid_0_T_32 = |_clr_bsy_valid_0_T_31; // @[util.scala:118:{51,59}]
wire _clr_bsy_valid_0_T_33 = ~_clr_bsy_valid_0_T_32; // @[util.scala:118:59]
wire _clr_bsy_valid_0_T_34 = _clr_bsy_valid_0_T_30 & _clr_bsy_valid_0_T_33; // @[lsu.scala:971:63, :972:63, :973:29]
wire [15:0] _clr_bsy_brmask_0_T_8 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _clr_bsy_brmask_0_T_9 = mem_stq_retry_e_bits_uop_br_mask & _clr_bsy_brmask_0_T_8; // @[util.scala:85:{25,27}]
wire [15:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_bsy_brmask_0; // @[util.scala:118:51]
wire _io_core_clr_bsy_0_valid_T_1 = |_io_core_clr_bsy_0_valid_T; // @[util.scala:118:{51,59}]
wire _io_core_clr_bsy_0_valid_T_2 = ~_io_core_clr_bsy_0_valid_T_1; // @[util.scala:118:59]
wire _io_core_clr_bsy_0_valid_T_3 = clr_bsy_valid_0 & _io_core_clr_bsy_0_valid_T_2; // @[lsu.scala:931:32, :978:50, :979:32]
wire _io_core_clr_bsy_0_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :980:32]
wire _io_core_clr_bsy_0_valid_T_5 = _io_core_clr_bsy_0_valid_T_3 & _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:978:50, :979:87, :980:32]
reg io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:62]
wire _io_core_clr_bsy_0_valid_T_6 = ~io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:{54,62}]
wire _io_core_clr_bsy_0_valid_T_7 = _io_core_clr_bsy_0_valid_T_5 & _io_core_clr_bsy_0_valid_T_6; // @[lsu.scala:979:87, :980:{51,54}]
reg io_core_clr_bsy_0_valid_REG_1; // @[lsu.scala:980:101]
reg io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:93]
wire _io_core_clr_bsy_0_valid_T_8 = ~io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:{85,93}]
assign _io_core_clr_bsy_0_valid_T_9 = _io_core_clr_bsy_0_valid_T_7 & _io_core_clr_bsy_0_valid_T_8; // @[lsu.scala:980:{51,82,85}]
assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:201:7, :980:82]
reg stdf_clr_bsy_valid; // @[lsu.scala:984:37]
reg [6:0] stdf_clr_bsy_rob_idx; // @[lsu.scala:985:33]
assign io_core_clr_bsy_1_bits_0 = stdf_clr_bsy_rob_idx; // @[lsu.scala:201:7, :985:33]
reg [15:0] stdf_clr_bsy_brmask; // @[lsu.scala:986:33]
wire _stdf_clr_bsy_valid_T = _GEN[mem_stdf_uop_stq_idx] & _GEN_83[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62]
wire _stdf_clr_bsy_valid_T_1 = ~_GEN_85[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :994:29]
wire _stdf_clr_bsy_valid_T_2 = _stdf_clr_bsy_valid_T & _stdf_clr_bsy_valid_T_1; // @[lsu.scala:992:62, :993:62, :994:29]
wire _stdf_clr_bsy_valid_T_3 = ~_GEN_57[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :995:29]
wire _stdf_clr_bsy_valid_T_4 = _stdf_clr_bsy_valid_T_2 & _stdf_clr_bsy_valid_T_3; // @[lsu.scala:993:62, :994:62, :995:29]
wire [15:0] _stdf_clr_bsy_valid_T_5 = io_core_brupdate_b1_mispredict_mask_0 & mem_stdf_uop_br_mask; // @[util.scala:118:51]
wire _stdf_clr_bsy_valid_T_6 = |_stdf_clr_bsy_valid_T_5; // @[util.scala:118:{51,59}]
wire _stdf_clr_bsy_valid_T_7 = ~_stdf_clr_bsy_valid_T_6; // @[util.scala:118:59]
wire _stdf_clr_bsy_valid_T_8 = _stdf_clr_bsy_valid_T_4 & _stdf_clr_bsy_valid_T_7; // @[lsu.scala:994:62, :995:62, :996:29]
wire [15:0] _stdf_clr_bsy_brmask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _stdf_clr_bsy_brmask_T_1 = mem_stdf_uop_br_mask & _stdf_clr_bsy_brmask_T; // @[util.scala:85:{25,27}]
wire [15:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stdf_clr_bsy_brmask; // @[util.scala:118:51]
wire _io_core_clr_bsy_1_valid_T_1 = |_io_core_clr_bsy_1_valid_T; // @[util.scala:118:{51,59}]
wire _io_core_clr_bsy_1_valid_T_2 = ~_io_core_clr_bsy_1_valid_T_1; // @[util.scala:118:59]
wire _io_core_clr_bsy_1_valid_T_3 = stdf_clr_bsy_valid & _io_core_clr_bsy_1_valid_T_2; // @[lsu.scala:984:37, :1003:57, :1004:37]
wire _io_core_clr_bsy_1_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1005:37]
wire _io_core_clr_bsy_1_valid_T_5 = _io_core_clr_bsy_1_valid_T_3 & _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1003:57, :1004:94, :1005:37]
reg io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:67]
wire _io_core_clr_bsy_1_valid_T_6 = ~io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:{59,67}]
wire _io_core_clr_bsy_1_valid_T_7 = _io_core_clr_bsy_1_valid_T_5 & _io_core_clr_bsy_1_valid_T_6; // @[lsu.scala:1004:94, :1005:{56,59}]
reg io_core_clr_bsy_1_valid_REG_1; // @[lsu.scala:1005:106]
reg io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:98]
wire _io_core_clr_bsy_1_valid_T_8 = ~io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:{90,98}]
assign _io_core_clr_bsy_1_valid_T_9 = _io_core_clr_bsy_1_valid_T_7 & _io_core_clr_bsy_1_valid_T_8; // @[lsu.scala:1005:{56,87,90}]
assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:201:7, :1005:87]
wire _do_st_search_T_1 = _do_st_search_T | fired_sta_retry_0; // @[lsu.scala:263:49, :1015:{60,85}]
wire _do_st_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1015:111]
wire _do_st_search_T_3 = _do_st_search_T_1 & _do_st_search_T_2; // @[lsu.scala:1015:{85,108,111}]
wire do_st_search_0 = _do_st_search_T_3; // @[lsu.scala:263:49, :1015:108]
wire _GEN_303 = fired_load_incoming_0 | fired_load_retry_0; // @[lsu.scala:263:49, :1017:61]
wire _do_ld_search_T; // @[lsu.scala:1017:61]
assign _do_ld_search_T = _GEN_303; // @[lsu.scala:1017:61]
wire _can_forward_T; // @[lsu.scala:1046:32]
assign _can_forward_T = _GEN_303; // @[lsu.scala:1017:61, :1046:32]
wire _do_ld_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1017:88]
wire _do_ld_search_T_2 = _do_ld_search_T & _do_ld_search_T_1; // @[lsu.scala:1017:{61,85,88}]
wire _do_ld_search_T_3 = _do_ld_search_T_2 | fired_load_wakeup_0; // @[lsu.scala:263:49, :1017:{85,106}]
wire do_ld_search_0 = _do_ld_search_T_3; // @[lsu.scala:263:49, :1017:106]
wire _lcam_addr_T_1 = _lcam_addr_T | fired_sta_retry_0; // @[lsu.scala:263:49, :1026:{61,86}]
reg [31:0] lcam_addr_REG; // @[lsu.scala:1027:45]
reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1028:67]
wire [39:0] _lcam_addr_T_2 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:901:37, :928:41, :1028:{41,67}]
wire [39:0] _lcam_addr_T_3 = _lcam_addr_T_1 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_2; // @[lsu.scala:1026:{37,86}, :1027:45, :1028:41]
wire [39:0] lcam_addr_0 = _lcam_addr_T_3; // @[lsu.scala:263:49, :1026:37]
wire [6:0] _lcam_uop_T_uopc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :1031:37]
wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :1031:37]
wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49, :1031:37]
wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :1031:37]
wire [2:0] _lcam_uop_T_iq_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :1031:37]
wire [9:0] _lcam_uop_T_fu_code = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :1031:37]
wire [3:0] _lcam_uop_T_ctrl_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_ctrl_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire [2:0] _lcam_uop_T_ctrl_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :1031:37]
wire [2:0] _lcam_uop_T_ctrl_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :1031:37]
wire [4:0] _lcam_uop_T_ctrl_op_fcn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_ctrl_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :1031:37]
wire [2:0] _lcam_uop_T_ctrl_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_ctrl_is_load = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_ctrl_is_sta = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_ctrl_is_std = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_iw_state = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_iw_p1_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_iw_p2_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_br = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_br; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_jalr = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_jal = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jal; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49, :1031:37]
wire [15:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 16'h0; // @[lsu.scala:263:49, :1031:37]
wire [3:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 4'h0; // @[lsu.scala:263:49, :1031:37]
wire [4:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49, :1031:37]
wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:263:49, :1031:37]
wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :1031:37]
wire [11:0] _lcam_uop_T_csr_addr = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :1031:37]
wire [6:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 7'h0; // @[lsu.scala:263:49, :1031:37]
wire [4:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:263:49, :1031:37]
wire [4:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 5'h0; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire [6:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 7'h0; // @[lsu.scala:263:49, :1031:37]
wire [6:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 7'h0; // @[lsu.scala:263:49, :1031:37]
wire [6:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 7'h0; // @[lsu.scala:263:49, :1031:37]
wire [6:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 7'h0; // @[lsu.scala:263:49, :1031:37]
wire [4:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 5'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49, :1031:37]
wire [6:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:263:49, :1031:37]
wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_bypassable = do_ld_search_0 & mem_ldq_e_0_bits_uop_bypassable; // @[lsu.scala:263:49, :1031:37]
wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :1031:37]
wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :1031:37]
wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :1031:37]
wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :1031:37]
wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_ldst_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h2; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_fp_single = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_single; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :1031:37]
wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire [1:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :1031:37]
wire [6:0] _lcam_uop_T_1_uopc = do_st_search_0 ? mem_stq_e_0_bits_uop_uopc : _lcam_uop_T_uopc; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [2:0] _lcam_uop_T_1_iq_type = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type : _lcam_uop_T_iq_type; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [9:0] _lcam_uop_T_1_fu_code = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code : _lcam_uop_T_fu_code; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [3:0] _lcam_uop_T_1_ctrl_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_br_type : _lcam_uop_T_ctrl_br_type; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_ctrl_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op1_sel : _lcam_uop_T_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [2:0] _lcam_uop_T_1_ctrl_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op2_sel : _lcam_uop_T_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [2:0] _lcam_uop_T_1_ctrl_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_imm_sel : _lcam_uop_T_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [4:0] _lcam_uop_T_1_ctrl_op_fcn = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op_fcn : _lcam_uop_T_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_ctrl_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_fcn_dw : _lcam_uop_T_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [2:0] _lcam_uop_T_1_ctrl_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_csr_cmd : _lcam_uop_T_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_ctrl_is_load = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_load : _lcam_uop_T_ctrl_is_load; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_ctrl_is_sta = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_sta : _lcam_uop_T_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_ctrl_is_std = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_std : _lcam_uop_T_ctrl_is_std; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_iw_state = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_state : _lcam_uop_T_iw_state; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_iw_p1_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_poisoned : _lcam_uop_T_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_iw_p2_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_poisoned : _lcam_uop_T_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_br = do_st_search_0 ? mem_stq_e_0_bits_uop_is_br : _lcam_uop_T_is_br; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_jalr = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jalr : _lcam_uop_T_is_jalr; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_jal = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jal : _lcam_uop_T_is_jal; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [15:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [3:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [4:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [11:0] _lcam_uop_T_1_csr_addr = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_addr : _lcam_uop_T_csr_addr; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [6:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [4:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [4:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [6:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [6:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [6:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [6:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [4:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [6:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_bypassable = do_st_search_0 ? mem_stq_e_0_bits_uop_bypassable : _lcam_uop_T_bypassable; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_ldst_val = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_val : _lcam_uop_T_ldst_val; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_fp_single = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_single : _lcam_uop_T_fp_single; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [1:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:263:49, :1030:37, :1031:37]
wire [6:0] lcam_uop_0_uopc = _lcam_uop_T_1_uopc; // @[lsu.scala:263:49, :1030:37]
wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:263:49, :1030:37]
wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:263:49, :1030:37]
wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:263:49, :1030:37]
wire [2:0] lcam_uop_0_iq_type = _lcam_uop_T_1_iq_type; // @[lsu.scala:263:49, :1030:37]
wire [9:0] lcam_uop_0_fu_code = _lcam_uop_T_1_fu_code; // @[lsu.scala:263:49, :1030:37]
wire [3:0] lcam_uop_0_ctrl_br_type = _lcam_uop_T_1_ctrl_br_type; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_ctrl_op1_sel = _lcam_uop_T_1_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37]
wire [2:0] lcam_uop_0_ctrl_op2_sel = _lcam_uop_T_1_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37]
wire [2:0] lcam_uop_0_ctrl_imm_sel = _lcam_uop_T_1_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37]
wire [4:0] lcam_uop_0_ctrl_op_fcn = _lcam_uop_T_1_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_ctrl_fcn_dw = _lcam_uop_T_1_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37]
wire [2:0] lcam_uop_0_ctrl_csr_cmd = _lcam_uop_T_1_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_ctrl_is_load = _lcam_uop_T_1_ctrl_is_load; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_ctrl_is_sta = _lcam_uop_T_1_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_ctrl_is_std = _lcam_uop_T_1_ctrl_is_std; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_iw_state = _lcam_uop_T_1_iw_state; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_iw_p1_poisoned = _lcam_uop_T_1_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_iw_p2_poisoned = _lcam_uop_T_1_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_br = _lcam_uop_T_1_is_br; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_jalr = _lcam_uop_T_1_is_jalr; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_jal = _lcam_uop_T_1_is_jal; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:263:49, :1030:37]
wire [15:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:263:49, :1030:37]
wire [3:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:263:49, :1030:37]
wire [4:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:263:49, :1030:37]
wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:263:49, :1030:37]
wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:263:49, :1030:37]
wire [11:0] lcam_uop_0_csr_addr = _lcam_uop_T_1_csr_addr; // @[lsu.scala:263:49, :1030:37]
wire [6:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:263:49, :1030:37]
wire [4:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:263:49, :1030:37]
wire [4:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:263:49, :1030:37]
wire [6:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:263:49, :1030:37]
wire [6:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:263:49, :1030:37]
wire [6:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:263:49, :1030:37]
wire [6:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:263:49, :1030:37]
wire [4:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:263:49, :1030:37]
wire [6:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:263:49, :1030:37]
wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_bypassable = _lcam_uop_T_1_bypassable; // @[lsu.scala:263:49, :1030:37]
wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37]
wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:263:49, :1030:37]
wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:263:49, :1030:37]
wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:263:49, :1030:37]
wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_ldst_val = _lcam_uop_T_1_ldst_val; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_fp_single = _lcam_uop_T_1_fp_single; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:263:49, :1030:37]
wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:263:49, :1030:37]
wire [1:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:263:49, :1030:37]
wire [7:0] lcam_mask_mask; // @[lsu.scala:1665:22]
wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:263:49, :1665:22]
wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:263:49, :1667:26]
wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:263:49, :1667:55]
wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1667:{48,55}]
wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:263:49, :1668:26]
wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:263:49, :1668:56]
wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1668:{48,62}]
wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:263:49, :1669:26]
wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:263:49, :1669:46]
wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:263:49, :1670:26]
wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16]
wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16]
assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16]
reg [4:0] lcam_ldq_idx_REG; // @[lsu.scala:1038:58]
reg [4:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1039:58]
wire [4:0] _lcam_ldq_idx_T = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 5'h0; // @[lsu.scala:263:49, :1039:{26,58}]
wire [4:0] _lcam_ldq_idx_T_1 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T; // @[lsu.scala:263:49, :1038:{26,58}, :1039:26]
wire [4:0] _lcam_ldq_idx_T_2 = fired_load_incoming_0 ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_1; // @[lsu.scala:263:49, :909:37, :1037:26, :1038:26]
wire [4:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_2; // @[lsu.scala:263:49, :1037:26]
wire [4:0] _can_forward_T_2 = lcam_ldq_idx_0; // @[lsu.scala:263:49]
reg [4:0] lcam_stq_idx_REG; // @[lsu.scala:1043:58]
wire [4:0] _lcam_stq_idx_T_1 = fired_sta_retry_0 ? lcam_stq_idx_REG : 5'h0; // @[lsu.scala:263:49, :1043:{26,58}]
wire [4:0] _lcam_stq_idx_T_2 = _lcam_stq_idx_T ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T_1; // @[lsu.scala:909:37, :1041:{26,50}, :1043:26]
wire [4:0] lcam_stq_idx_0 = _lcam_stq_idx_T_2; // @[lsu.scala:263:49, :1041:26]
wire _can_forward_T_1 = ~mem_tlb_uncacheable_0; // @[lsu.scala:927:41, :1046:56]
wire [4:0] _can_forward_T_3 = _can_forward_T_2;
wire _can_forward_T_4 = ~_GEN_181[_can_forward_T_3]; // @[lsu.scala:263:49, :1047:7]
wire _can_forward_T_5 = _can_forward_T ? _can_forward_T_1 : _can_forward_T_4; // @[lsu.scala:1046:{8,32,56}, :1047:7]
wire _can_forward_WIRE_0 = _can_forward_T_5; // @[lsu.scala:263:49, :1046:8]
wire can_forward_0; // @[lsu.scala:1045:29]
wire ldst_addr_matches_0_0; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_1; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_2; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_3; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_4; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_5; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_6; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_7; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_8; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_9; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_10; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_11; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_12; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_13; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_14; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_15; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_16; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_17; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_18; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_19; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_20; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_21; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_22; // @[lsu.scala:1050:38]
wire ldst_addr_matches_0_23; // @[lsu.scala:1050:38]
wire ldst_forward_matches_0_0; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_1; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_2; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_3; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_4; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_5; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_6; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_7; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_8; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_9; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_10; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_11; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_12; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_13; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_14; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_15; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_16; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_17; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_18; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_19; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_20; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_21; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_22; // @[lsu.scala:1052:38]
wire ldst_forward_matches_0_23; // @[lsu.scala:1052:38]
wire _temp_bits_WIRE_1_24 = failed_loads_0; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_25 = failed_loads_1; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_26 = failed_loads_2; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_27 = failed_loads_3; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_28 = failed_loads_4; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_29 = failed_loads_5; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_30 = failed_loads_6; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_31 = failed_loads_7; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_32 = failed_loads_8; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_33 = failed_loads_9; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_34 = failed_loads_10; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_35 = failed_loads_11; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_36 = failed_loads_12; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_37 = failed_loads_13; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_38 = failed_loads_14; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_39 = failed_loads_15; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_40 = failed_loads_16; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_41 = failed_loads_17; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_42 = failed_loads_18; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_43 = failed_loads_19; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_44 = failed_loads_20; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_45 = failed_loads_21; // @[lsu.scala:1054:34, :1229:27]
wire _temp_bits_WIRE_1_46 = failed_loads_22; // @[lsu.scala:1054:34, :1229:27]
wire failed_loads_23; // @[lsu.scala:1054:34]
wire _temp_bits_WIRE_1_47 = failed_loads_23; // @[lsu.scala:1054:34, :1229:27]
wire nacking_loads_0; // @[lsu.scala:1055:34]
wire nacking_loads_1; // @[lsu.scala:1055:34]
wire nacking_loads_2; // @[lsu.scala:1055:34]
wire nacking_loads_3; // @[lsu.scala:1055:34]
wire nacking_loads_4; // @[lsu.scala:1055:34]
wire nacking_loads_5; // @[lsu.scala:1055:34]
wire nacking_loads_6; // @[lsu.scala:1055:34]
wire nacking_loads_7; // @[lsu.scala:1055:34]
wire nacking_loads_8; // @[lsu.scala:1055:34]
wire nacking_loads_9; // @[lsu.scala:1055:34]
wire nacking_loads_10; // @[lsu.scala:1055:34]
wire nacking_loads_11; // @[lsu.scala:1055:34]
wire nacking_loads_12; // @[lsu.scala:1055:34]
wire nacking_loads_13; // @[lsu.scala:1055:34]
wire nacking_loads_14; // @[lsu.scala:1055:34]
wire nacking_loads_15; // @[lsu.scala:1055:34]
wire nacking_loads_16; // @[lsu.scala:1055:34]
wire nacking_loads_17; // @[lsu.scala:1055:34]
wire nacking_loads_18; // @[lsu.scala:1055:34]
wire nacking_loads_19; // @[lsu.scala:1055:34]
wire nacking_loads_20; // @[lsu.scala:1055:34]
wire nacking_loads_21; // @[lsu.scala:1055:34]
wire nacking_loads_22; // @[lsu.scala:1055:34]
wire nacking_loads_23; // @[lsu.scala:1055:34]
reg s1_executing_loads_0; // @[lsu.scala:1057:35]
reg s1_executing_loads_1; // @[lsu.scala:1057:35]
reg s1_executing_loads_2; // @[lsu.scala:1057:35]
reg s1_executing_loads_3; // @[lsu.scala:1057:35]
reg s1_executing_loads_4; // @[lsu.scala:1057:35]
reg s1_executing_loads_5; // @[lsu.scala:1057:35]
reg s1_executing_loads_6; // @[lsu.scala:1057:35]
reg s1_executing_loads_7; // @[lsu.scala:1057:35]
reg s1_executing_loads_8; // @[lsu.scala:1057:35]
reg s1_executing_loads_9; // @[lsu.scala:1057:35]
reg s1_executing_loads_10; // @[lsu.scala:1057:35]
reg s1_executing_loads_11; // @[lsu.scala:1057:35]
reg s1_executing_loads_12; // @[lsu.scala:1057:35]
reg s1_executing_loads_13; // @[lsu.scala:1057:35]
reg s1_executing_loads_14; // @[lsu.scala:1057:35]
reg s1_executing_loads_15; // @[lsu.scala:1057:35]
reg s1_executing_loads_16; // @[lsu.scala:1057:35]
reg s1_executing_loads_17; // @[lsu.scala:1057:35]
reg s1_executing_loads_18; // @[lsu.scala:1057:35]
reg s1_executing_loads_19; // @[lsu.scala:1057:35]
reg s1_executing_loads_20; // @[lsu.scala:1057:35]
reg s1_executing_loads_21; // @[lsu.scala:1057:35]
reg s1_executing_loads_22; // @[lsu.scala:1057:35]
reg s1_executing_loads_23; // @[lsu.scala:1057:35]
wire s1_set_execute_0; // @[lsu.scala:1058:36]
wire s1_set_execute_1; // @[lsu.scala:1058:36]
wire s1_set_execute_2; // @[lsu.scala:1058:36]
wire s1_set_execute_3; // @[lsu.scala:1058:36]
wire s1_set_execute_4; // @[lsu.scala:1058:36]
wire s1_set_execute_5; // @[lsu.scala:1058:36]
wire s1_set_execute_6; // @[lsu.scala:1058:36]
wire s1_set_execute_7; // @[lsu.scala:1058:36]
wire s1_set_execute_8; // @[lsu.scala:1058:36]
wire s1_set_execute_9; // @[lsu.scala:1058:36]
wire s1_set_execute_10; // @[lsu.scala:1058:36]
wire s1_set_execute_11; // @[lsu.scala:1058:36]
wire s1_set_execute_12; // @[lsu.scala:1058:36]
wire s1_set_execute_13; // @[lsu.scala:1058:36]
wire s1_set_execute_14; // @[lsu.scala:1058:36]
wire s1_set_execute_15; // @[lsu.scala:1058:36]
wire s1_set_execute_16; // @[lsu.scala:1058:36]
wire s1_set_execute_17; // @[lsu.scala:1058:36]
wire s1_set_execute_18; // @[lsu.scala:1058:36]
wire s1_set_execute_19; // @[lsu.scala:1058:36]
wire s1_set_execute_20; // @[lsu.scala:1058:36]
wire s1_set_execute_21; // @[lsu.scala:1058:36]
wire s1_set_execute_22; // @[lsu.scala:1058:36]
wire s1_set_execute_23; // @[lsu.scala:1058:36]
wire mem_forward_valid_0; // @[lsu.scala:1060:33]
wire [4:0] forwarding_idx_0; // @[lsu.scala:263:49]
wire [4:0] mem_forward_stq_idx_0; // @[lsu.scala:1063:33]
reg wb_forward_valid_0; // @[lsu.scala:1065:36]
reg [4:0] wb_forward_ldq_idx_0; // @[lsu.scala:1066:36]
wire [4:0] _forward_uop_T = wb_forward_ldq_idx_0; // @[lsu.scala:1066:36]
reg [39:0] wb_forward_ld_addr_0; // @[lsu.scala:1067:36]
reg [4:0] wb_forward_stq_idx_0; // @[lsu.scala:1068:36]
wire [7:0] l_mask; // @[lsu.scala:1665:22]
wire _l_mask_mask_T = ldq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_1 = ldq_0_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_2 = 15'h1 << _l_mask_mask_T_1; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_3 = ldq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_4 = ldq_0_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_5 = {_l_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_6 = 15'h3 << _l_mask_mask_T_5; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_7 = ldq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_8 = ldq_0_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_9 = _l_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_10 = &ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_12 = _l_mask_mask_T_7 ? _l_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_13 = _l_mask_mask_T_3 ? _l_mask_mask_T_6 : {7'h0, _l_mask_mask_T_12}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_14 = _l_mask_mask_T ? _l_mask_mask_T_2 : _l_mask_mask_T_13; // @[Mux.scala:126:16]
assign l_mask = _l_mask_mask_T_14[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T = wb_forward_ldq_idx_0 == 5'h0; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_1 = wb_forward_valid_0 & _l_forwarders_T; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_0 = _l_forwarders_T_1; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx = l_forwarders_0 ? wb_forward_stq_idx_0 : ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_24 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_27 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_30 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_33 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_36 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_39 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_42 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_45 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_48 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_51 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_54 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_57 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_60 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_63 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_66 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_69 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57]
wire [33:0] _block_addr_matches_T_1 = ldq_0_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_32 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_36 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_40 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_44 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_48 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_52 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_56 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_60 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_64 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_68 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_72 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_76 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_80 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_84 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_88 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_92 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81]
wire [2:0] _dword_addr_matches_T_1 = ldq_0_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_304 = l_mask & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T; // @[lsu.scala:1083:46]
assign _mask_match_T = _GEN_304; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T; // @[lsu.scala:1084:46]
assign _mask_overlap_T = _GEN_304; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_1 = _mask_match_T == l_mask; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_1 = |_mask_overlap_T; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:263:49, :1084:62]
wire _T_265 = do_release_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & block_addr_matches_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_294 = ldq_0_bits_executed | ldq_0_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _GEN_305 = {19'h0, lcam_stq_idx_0}; // @[lsu.scala:263:49, :1101:38]
wire [23:0] _T_273 = ldq_0_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_277 = do_st_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & (_T_294 | l_forwarders_0) & ~ldq_0_bits_addr_is_virtual & _T_273[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T = l_forward_stq_idx < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_1 = l_forward_stq_idx < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:363:{58,72,78}]
wire _T_281 = ~ldq_0_bits_forward_std_val | l_forward_stq_idx != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:363:72]
wire _T_287 = do_ld_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & ~ldq_0_bits_addr_is_virtual & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _GEN_306 = lcam_ldq_idx_0 < ldq_head; // @[util.scala:363:64]
wire _searcher_is_older_T_1; // @[util.scala:363:64]
assign _searcher_is_older_T_1 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_5; // @[util.scala:363:64]
assign _searcher_is_older_T_5 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_9; // @[util.scala:363:64]
assign _searcher_is_older_T_9 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_13; // @[util.scala:363:64]
assign _searcher_is_older_T_13 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_17; // @[util.scala:363:64]
assign _searcher_is_older_T_17 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_21; // @[util.scala:363:64]
assign _searcher_is_older_T_21 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_25; // @[util.scala:363:64]
assign _searcher_is_older_T_25 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_29; // @[util.scala:363:64]
assign _searcher_is_older_T_29 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_33; // @[util.scala:363:64]
assign _searcher_is_older_T_33 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_37; // @[util.scala:363:64]
assign _searcher_is_older_T_37 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_41; // @[util.scala:363:64]
assign _searcher_is_older_T_41 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_45; // @[util.scala:363:64]
assign _searcher_is_older_T_45 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_49; // @[util.scala:363:64]
assign _searcher_is_older_T_49 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_53; // @[util.scala:363:64]
assign _searcher_is_older_T_53 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_57; // @[util.scala:363:64]
assign _searcher_is_older_T_57 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_61; // @[util.scala:363:64]
assign _searcher_is_older_T_61 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_65; // @[util.scala:363:64]
assign _searcher_is_older_T_65 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_69; // @[util.scala:363:64]
assign _searcher_is_older_T_69 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_73; // @[util.scala:363:64]
assign _searcher_is_older_T_73 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_77; // @[util.scala:363:64]
assign _searcher_is_older_T_77 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_81; // @[util.scala:363:64]
assign _searcher_is_older_T_81 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_85; // @[util.scala:363:64]
assign _searcher_is_older_T_85 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_89; // @[util.scala:363:64]
assign _searcher_is_older_T_89 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_93; // @[util.scala:363:64]
assign _searcher_is_older_T_93 = _GEN_306; // @[util.scala:363:64]
wire _searcher_is_older_T_2 = _searcher_is_older_T_1; // @[util.scala:363:{58,64}]
wire _searcher_is_older_T_3 = |ldq_head; // @[util.scala:363:78]
wire searcher_is_older = _searcher_is_older_T_2 ^ _searcher_is_older_T_3; // @[util.scala:363:{58,72,78}]
wire _GEN_307 = _T_287 & searcher_is_older & (_T_294 | l_forwarders_0) & ~s1_executing_loads_0 & ldq_0_bits_observed; // @[util.scala:363:72]
assign failed_loads_0 = ~_T_265 & (_T_277 ? _T_281 : _GEN_307); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG; // @[lsu.scala:1129:57]
wire older_nacked = nacking_loads_0 | older_nacked_REG; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_296 = ~_T_294 | older_nacked; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _searcher_is_older_T_4 = lcam_ldq_idx_0 == 5'h0; // @[util.scala:363:52]
wire _GEN_308 = _T_265 | _T_277; // @[lsu.scala:1058:36, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
wire _GEN_309 = lcam_ldq_idx_0 == 5'h1; // @[lsu.scala:263:49, :1131:48]
wire _GEN_310 = lcam_ldq_idx_0 == 5'h2; // @[lsu.scala:263:49, :1131:48]
wire _GEN_311 = lcam_ldq_idx_0 == 5'h3; // @[lsu.scala:263:49, :1131:48]
wire _GEN_312 = lcam_ldq_idx_0 == 5'h4; // @[lsu.scala:263:49, :1131:48]
wire _GEN_313 = lcam_ldq_idx_0 == 5'h5; // @[lsu.scala:263:49, :1131:48]
wire _GEN_314 = lcam_ldq_idx_0 == 5'h6; // @[lsu.scala:263:49, :1131:48]
wire _GEN_315 = lcam_ldq_idx_0 == 5'h7; // @[lsu.scala:263:49, :1131:48]
wire _GEN_316 = lcam_ldq_idx_0 == 5'h8; // @[lsu.scala:263:49, :1131:48]
wire _GEN_317 = lcam_ldq_idx_0 == 5'h9; // @[lsu.scala:263:49, :1131:48]
wire _GEN_318 = lcam_ldq_idx_0 == 5'hA; // @[lsu.scala:263:49, :1131:48]
wire _GEN_319 = lcam_ldq_idx_0 == 5'hB; // @[lsu.scala:263:49, :1131:48]
wire _GEN_320 = lcam_ldq_idx_0 == 5'hC; // @[lsu.scala:263:49, :1131:48]
wire _GEN_321 = lcam_ldq_idx_0 == 5'hD; // @[lsu.scala:263:49, :1131:48]
wire _GEN_322 = lcam_ldq_idx_0 == 5'hE; // @[lsu.scala:263:49, :1131:48]
wire _GEN_323 = lcam_ldq_idx_0 == 5'hF; // @[lsu.scala:263:49, :1131:48]
wire _GEN_324 = lcam_ldq_idx_0 == 5'h10; // @[lsu.scala:263:49, :1131:48]
wire _GEN_325 = lcam_ldq_idx_0 == 5'h11; // @[lsu.scala:263:49, :1131:48]
wire _GEN_326 = lcam_ldq_idx_0 == 5'h12; // @[lsu.scala:263:49, :1131:48]
wire _GEN_327 = lcam_ldq_idx_0 == 5'h13; // @[lsu.scala:263:49, :1131:48]
wire _GEN_328 = lcam_ldq_idx_0 == 5'h14; // @[lsu.scala:263:49, :1131:48]
wire _GEN_329 = lcam_ldq_idx_0 == 5'h15; // @[lsu.scala:263:49, :1131:48]
wire _GEN_330 = lcam_ldq_idx_0 == 5'h16; // @[lsu.scala:263:49, :1131:48]
wire _GEN_331 = lcam_ldq_idx_0 == 5'h17; // @[lsu.scala:263:49, :1131:48]
reg io_dmem_s1_kill_0_REG; // @[lsu.scala:1132:58]
wire _GEN_332 = (|lcam_ldq_idx_0) & _T_296; // @[lsu.scala:263:49, :765:24, :1126:{38,47}, :1130:{56,73}, :1132:48]
wire [7:0] l_mask_1; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_15 = ldq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_16 = ldq_1_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_17 = 15'h1 << _l_mask_mask_T_16; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_18 = ldq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_19 = ldq_1_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_20 = {_l_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_21 = 15'h3 << _l_mask_mask_T_20; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_22 = ldq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_23 = ldq_1_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_24 = _l_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_25 = &ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_27 = _l_mask_mask_T_22 ? _l_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_28 = _l_mask_mask_T_18 ? _l_mask_mask_T_21 : {7'h0, _l_mask_mask_T_27}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_29 = _l_mask_mask_T_15 ? _l_mask_mask_T_17 : _l_mask_mask_T_28; // @[Mux.scala:126:16]
assign l_mask_1 = _l_mask_mask_T_29[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_2 = wb_forward_ldq_idx_0 == 5'h1; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_3 = wb_forward_valid_0 & _l_forwarders_T_2; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_1_0 = _l_forwarders_T_3; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_1 = l_forwarders_1_0 ? wb_forward_stq_idx_0 : ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_4 = ldq_1_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_5 = ldq_1_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_333 = l_mask_1 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_2; // @[lsu.scala:1083:46]
assign _mask_match_T_2 = _GEN_333; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1084:46]
assign _mask_overlap_T_2 = _GEN_333; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_3 = _mask_match_T_2 == l_mask_1; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_3 = |_mask_overlap_T_2; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:263:49, :1084:62]
wire _T_301 = do_release_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & block_addr_matches_1_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_330 = ldq_1_bits_executed | ldq_1_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_309 = ldq_1_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_313 = do_st_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & (_T_330 | l_forwarders_1_0) & ~ldq_1_bits_addr_is_virtual & _T_309[0] & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_4 = l_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_5 = l_forward_stq_idx_1 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:363:{58,72,78}]
wire _T_317 = ~ldq_1_bits_forward_std_val | l_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1; // @[util.scala:363:72]
wire _T_323 = do_ld_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & ~ldq_1_bits_addr_is_virtual & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_6 = _searcher_is_older_T_4 ^ _searcher_is_older_T_5; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_7 = |(ldq_head[4:1]); // @[util.scala:363:78]
wire searcher_is_older_1 = _searcher_is_older_T_6 ^ _searcher_is_older_T_7; // @[util.scala:363:{58,72,78}]
wire _GEN_334 = _T_323 & searcher_is_older_1 & (_T_330 | l_forwarders_1_0) & ~s1_executing_loads_1 & ldq_1_bits_observed; // @[util.scala:363:72]
assign failed_loads_1 = ~_T_301 & (_T_313 ? _T_317 : _GEN_334); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_1; // @[lsu.scala:1129:57]
wire older_nacked_1 = nacking_loads_1 | older_nacked_REG_1; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_332 = ~_T_330 | older_nacked_1; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_335 = searcher_is_older_1 | _GEN_309; // @[util.scala:363:72]
wire _GEN_336 = _T_301 | _T_313; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_1; // @[lsu.scala:1132:58]
wire _GEN_337 = _GEN_336 | ~_T_323 | _GEN_335 | ~_T_332; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_2; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_30 = ldq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_31 = ldq_2_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_32 = 15'h1 << _l_mask_mask_T_31; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_33 = ldq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_34 = ldq_2_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_35 = {_l_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_36 = 15'h3 << _l_mask_mask_T_35; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_37 = ldq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_38 = ldq_2_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_39 = _l_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_40 = &ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_42 = _l_mask_mask_T_37 ? _l_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_43 = _l_mask_mask_T_33 ? _l_mask_mask_T_36 : {7'h0, _l_mask_mask_T_42}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_44 = _l_mask_mask_T_30 ? _l_mask_mask_T_32 : _l_mask_mask_T_43; // @[Mux.scala:126:16]
assign l_mask_2 = _l_mask_mask_T_44[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_4 = wb_forward_ldq_idx_0 == 5'h2; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_5 = wb_forward_valid_0 & _l_forwarders_T_4; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_2_0 = _l_forwarders_T_5; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_2 = l_forwarders_2_0 ? wb_forward_stq_idx_0 : ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_7 = ldq_2_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_9 = ldq_2_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_338 = l_mask_2 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_4; // @[lsu.scala:1083:46]
assign _mask_match_T_4 = _GEN_338; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1084:46]
assign _mask_overlap_T_4 = _GEN_338; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_5 = _mask_match_T_4 == l_mask_2; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_5 = |_mask_overlap_T_4; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:263:49, :1084:62]
wire _T_337 = do_release_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & block_addr_matches_2_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_366 = ldq_2_bits_executed | ldq_2_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_345 = ldq_2_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_349 = do_st_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & (_T_366 | l_forwarders_2_0) & ~ldq_2_bits_addr_is_virtual & _T_345[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_8 = l_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_9 = l_forward_stq_idx_2 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:363:{58,72,78}]
wire _T_353 = ~ldq_2_bits_forward_std_val | l_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:363:72]
wire _T_359 = do_ld_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & ~ldq_2_bits_addr_is_virtual & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_8 = lcam_ldq_idx_0 < 5'h2; // @[util.scala:363:52]
wire _searcher_is_older_T_10 = _searcher_is_older_T_8 ^ _searcher_is_older_T_9; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_11 = ldq_head > 5'h2; // @[util.scala:363:78]
wire searcher_is_older_2 = _searcher_is_older_T_10 ^ _searcher_is_older_T_11; // @[util.scala:363:{58,72,78}]
wire _GEN_339 = _T_359 & searcher_is_older_2 & (_T_366 | l_forwarders_2_0) & ~s1_executing_loads_2 & ldq_2_bits_observed; // @[util.scala:363:72]
assign failed_loads_2 = ~_T_337 & (_T_349 ? _T_353 : _GEN_339); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_2; // @[lsu.scala:1129:57]
wire older_nacked_2 = nacking_loads_2 | older_nacked_REG_2; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_368 = ~_T_366 | older_nacked_2; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_340 = searcher_is_older_2 | _GEN_310; // @[util.scala:363:72]
wire _GEN_341 = _T_337 | _T_349; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_2; // @[lsu.scala:1132:58]
wire _GEN_342 = _GEN_341 | ~_T_359 | _GEN_340 | ~_T_368; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_3; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_45 = ldq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_46 = ldq_3_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_47 = 15'h1 << _l_mask_mask_T_46; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_48 = ldq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_49 = ldq_3_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_50 = {_l_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_51 = 15'h3 << _l_mask_mask_T_50; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_52 = ldq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_53 = ldq_3_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_54 = _l_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_55 = &ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_57 = _l_mask_mask_T_52 ? _l_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_58 = _l_mask_mask_T_48 ? _l_mask_mask_T_51 : {7'h0, _l_mask_mask_T_57}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_59 = _l_mask_mask_T_45 ? _l_mask_mask_T_47 : _l_mask_mask_T_58; // @[Mux.scala:126:16]
assign l_mask_3 = _l_mask_mask_T_59[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_6 = wb_forward_ldq_idx_0 == 5'h3; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_7 = wb_forward_valid_0 & _l_forwarders_T_6; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_3_0 = _l_forwarders_T_7; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_3 = l_forwarders_3_0 ? wb_forward_stq_idx_0 : ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_10 = ldq_3_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_13 = ldq_3_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_343 = l_mask_3 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_6; // @[lsu.scala:1083:46]
assign _mask_match_T_6 = _GEN_343; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1084:46]
assign _mask_overlap_T_6 = _GEN_343; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_7 = _mask_match_T_6 == l_mask_3; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_7 = |_mask_overlap_T_6; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:263:49, :1084:62]
wire _T_373 = do_release_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & block_addr_matches_3_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_402 = ldq_3_bits_executed | ldq_3_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_381 = ldq_3_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_385 = do_st_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & (_T_402 | l_forwarders_3_0) & ~ldq_3_bits_addr_is_virtual & _T_381[0] & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_12 = l_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_13 = l_forward_stq_idx_3 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:363:{58,72,78}]
wire _T_389 = ~ldq_3_bits_forward_std_val | l_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3; // @[util.scala:363:72]
wire _T_395 = do_ld_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & ~ldq_3_bits_addr_is_virtual & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_12 = lcam_ldq_idx_0 < 5'h3; // @[util.scala:363:52]
wire _searcher_is_older_T_14 = _searcher_is_older_T_12 ^ _searcher_is_older_T_13; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_15 = |(ldq_head[4:2]); // @[util.scala:363:78]
wire searcher_is_older_3 = _searcher_is_older_T_14 ^ _searcher_is_older_T_15; // @[util.scala:363:{58,72,78}]
wire _GEN_344 = _T_395 & searcher_is_older_3 & (_T_402 | l_forwarders_3_0) & ~s1_executing_loads_3 & ldq_3_bits_observed; // @[util.scala:363:72]
assign failed_loads_3 = ~_T_373 & (_T_385 ? _T_389 : _GEN_344); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_3; // @[lsu.scala:1129:57]
wire older_nacked_3 = nacking_loads_3 | older_nacked_REG_3; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_404 = ~_T_402 | older_nacked_3; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_345 = searcher_is_older_3 | _GEN_311; // @[util.scala:363:72]
wire _GEN_346 = _T_373 | _T_385; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_3; // @[lsu.scala:1132:58]
wire _GEN_347 = _GEN_346 | ~_T_395 | _GEN_345 | ~_T_404; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_4; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_60 = ldq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_61 = ldq_4_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_62 = 15'h1 << _l_mask_mask_T_61; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_63 = ldq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_64 = ldq_4_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_65 = {_l_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_66 = 15'h3 << _l_mask_mask_T_65; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_67 = ldq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_68 = ldq_4_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_69 = _l_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_70 = &ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_72 = _l_mask_mask_T_67 ? _l_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_73 = _l_mask_mask_T_63 ? _l_mask_mask_T_66 : {7'h0, _l_mask_mask_T_72}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_74 = _l_mask_mask_T_60 ? _l_mask_mask_T_62 : _l_mask_mask_T_73; // @[Mux.scala:126:16]
assign l_mask_4 = _l_mask_mask_T_74[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_8 = wb_forward_ldq_idx_0 == 5'h4; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_9 = wb_forward_valid_0 & _l_forwarders_T_8; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_4_0 = _l_forwarders_T_9; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_4 = l_forwarders_4_0 ? wb_forward_stq_idx_0 : ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_13 = ldq_4_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_17 = ldq_4_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_348 = l_mask_4 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_8; // @[lsu.scala:1083:46]
assign _mask_match_T_8 = _GEN_348; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1084:46]
assign _mask_overlap_T_8 = _GEN_348; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_9 = _mask_match_T_8 == l_mask_4; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_9 = |_mask_overlap_T_8; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:263:49, :1084:62]
wire _T_409 = do_release_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & block_addr_matches_4_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_438 = ldq_4_bits_executed | ldq_4_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_417 = ldq_4_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_421 = do_st_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & (_T_438 | l_forwarders_4_0) & ~ldq_4_bits_addr_is_virtual & _T_417[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_16 = l_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_17 = l_forward_stq_idx_4 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:363:{58,72,78}]
wire _T_425 = ~ldq_4_bits_forward_std_val | l_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:363:72]
wire _T_431 = do_ld_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & ~ldq_4_bits_addr_is_virtual & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_16 = lcam_ldq_idx_0 < 5'h4; // @[util.scala:363:52]
wire _searcher_is_older_T_18 = _searcher_is_older_T_16 ^ _searcher_is_older_T_17; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_19 = ldq_head > 5'h4; // @[util.scala:363:78]
wire searcher_is_older_4 = _searcher_is_older_T_18 ^ _searcher_is_older_T_19; // @[util.scala:363:{58,72,78}]
wire _GEN_349 = _T_431 & searcher_is_older_4 & (_T_438 | l_forwarders_4_0) & ~s1_executing_loads_4 & ldq_4_bits_observed; // @[util.scala:363:72]
assign failed_loads_4 = ~_T_409 & (_T_421 ? _T_425 : _GEN_349); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_4; // @[lsu.scala:1129:57]
wire older_nacked_4 = nacking_loads_4 | older_nacked_REG_4; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_440 = ~_T_438 | older_nacked_4; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_350 = searcher_is_older_4 | _GEN_312; // @[util.scala:363:72]
wire _GEN_351 = _T_409 | _T_421; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_4; // @[lsu.scala:1132:58]
wire _GEN_352 = _GEN_351 | ~_T_431 | _GEN_350 | ~_T_440; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_5; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_75 = ldq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_76 = ldq_5_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_77 = 15'h1 << _l_mask_mask_T_76; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_78 = ldq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_79 = ldq_5_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_80 = {_l_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_81 = 15'h3 << _l_mask_mask_T_80; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_82 = ldq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_83 = ldq_5_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_84 = _l_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_85 = &ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_87 = _l_mask_mask_T_82 ? _l_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_88 = _l_mask_mask_T_78 ? _l_mask_mask_T_81 : {7'h0, _l_mask_mask_T_87}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_89 = _l_mask_mask_T_75 ? _l_mask_mask_T_77 : _l_mask_mask_T_88; // @[Mux.scala:126:16]
assign l_mask_5 = _l_mask_mask_T_89[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_10 = wb_forward_ldq_idx_0 == 5'h5; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_11 = wb_forward_valid_0 & _l_forwarders_T_10; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_5_0 = _l_forwarders_T_11; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_5 = l_forwarders_5_0 ? wb_forward_stq_idx_0 : ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_16 = ldq_5_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_21 = ldq_5_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_353 = l_mask_5 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_10; // @[lsu.scala:1083:46]
assign _mask_match_T_10 = _GEN_353; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1084:46]
assign _mask_overlap_T_10 = _GEN_353; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_11 = _mask_match_T_10 == l_mask_5; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_11 = |_mask_overlap_T_10; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:263:49, :1084:62]
wire _T_445 = do_release_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & block_addr_matches_5_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_474 = ldq_5_bits_executed | ldq_5_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_453 = ldq_5_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_457 = do_st_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & (_T_474 | l_forwarders_5_0) & ~ldq_5_bits_addr_is_virtual & _T_453[0] & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_20 = l_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_21 = l_forward_stq_idx_5 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:363:{58,72,78}]
wire _T_461 = ~ldq_5_bits_forward_std_val | l_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5; // @[util.scala:363:72]
wire _T_467 = do_ld_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & ~ldq_5_bits_addr_is_virtual & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_20 = lcam_ldq_idx_0 < 5'h5; // @[util.scala:363:52]
wire _searcher_is_older_T_22 = _searcher_is_older_T_20 ^ _searcher_is_older_T_21; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_23 = ldq_head > 5'h5; // @[util.scala:363:78]
wire searcher_is_older_5 = _searcher_is_older_T_22 ^ _searcher_is_older_T_23; // @[util.scala:363:{58,72,78}]
wire _GEN_354 = _T_467 & searcher_is_older_5 & (_T_474 | l_forwarders_5_0) & ~s1_executing_loads_5 & ldq_5_bits_observed; // @[util.scala:363:72]
assign failed_loads_5 = ~_T_445 & (_T_457 ? _T_461 : _GEN_354); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_5; // @[lsu.scala:1129:57]
wire older_nacked_5 = nacking_loads_5 | older_nacked_REG_5; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_476 = ~_T_474 | older_nacked_5; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_355 = searcher_is_older_5 | _GEN_313; // @[util.scala:363:72]
wire _GEN_356 = _T_445 | _T_457; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_5; // @[lsu.scala:1132:58]
wire _GEN_357 = _GEN_356 | ~_T_467 | _GEN_355 | ~_T_476; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_6; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_90 = ldq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_91 = ldq_6_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_92 = 15'h1 << _l_mask_mask_T_91; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_93 = ldq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_94 = ldq_6_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_95 = {_l_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_96 = 15'h3 << _l_mask_mask_T_95; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_97 = ldq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_98 = ldq_6_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_99 = _l_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_100 = &ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_102 = _l_mask_mask_T_97 ? _l_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_103 = _l_mask_mask_T_93 ? _l_mask_mask_T_96 : {7'h0, _l_mask_mask_T_102}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_104 = _l_mask_mask_T_90 ? _l_mask_mask_T_92 : _l_mask_mask_T_103; // @[Mux.scala:126:16]
assign l_mask_6 = _l_mask_mask_T_104[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_12 = wb_forward_ldq_idx_0 == 5'h6; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_13 = wb_forward_valid_0 & _l_forwarders_T_12; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_6_0 = _l_forwarders_T_13; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_6 = l_forwarders_6_0 ? wb_forward_stq_idx_0 : ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_19 = ldq_6_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_25 = ldq_6_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_358 = l_mask_6 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_12; // @[lsu.scala:1083:46]
assign _mask_match_T_12 = _GEN_358; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1084:46]
assign _mask_overlap_T_12 = _GEN_358; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_13 = _mask_match_T_12 == l_mask_6; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_13 = |_mask_overlap_T_12; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:263:49, :1084:62]
wire _T_481 = do_release_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & block_addr_matches_6_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_510 = ldq_6_bits_executed | ldq_6_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_489 = ldq_6_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_493 = do_st_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & (_T_510 | l_forwarders_6_0) & ~ldq_6_bits_addr_is_virtual & _T_489[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_24 = l_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_25 = l_forward_stq_idx_6 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:363:{58,72,78}]
wire _T_497 = ~ldq_6_bits_forward_std_val | l_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:363:72]
wire _T_503 = do_ld_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & ~ldq_6_bits_addr_is_virtual & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_24 = lcam_ldq_idx_0 < 5'h6; // @[util.scala:363:52]
wire _searcher_is_older_T_26 = _searcher_is_older_T_24 ^ _searcher_is_older_T_25; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_27 = ldq_head > 5'h6; // @[util.scala:363:78]
wire searcher_is_older_6 = _searcher_is_older_T_26 ^ _searcher_is_older_T_27; // @[util.scala:363:{58,72,78}]
wire _GEN_359 = _T_503 & searcher_is_older_6 & (_T_510 | l_forwarders_6_0) & ~s1_executing_loads_6 & ldq_6_bits_observed; // @[util.scala:363:72]
assign failed_loads_6 = ~_T_481 & (_T_493 ? _T_497 : _GEN_359); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_6; // @[lsu.scala:1129:57]
wire older_nacked_6 = nacking_loads_6 | older_nacked_REG_6; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_512 = ~_T_510 | older_nacked_6; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_360 = searcher_is_older_6 | _GEN_314; // @[util.scala:363:72]
wire _GEN_361 = _T_481 | _T_493; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_6; // @[lsu.scala:1132:58]
wire _GEN_362 = _GEN_361 | ~_T_503 | _GEN_360 | ~_T_512; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_7; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_105 = ldq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_106 = ldq_7_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_107 = 15'h1 << _l_mask_mask_T_106; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_108 = ldq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_109 = ldq_7_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_110 = {_l_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_111 = 15'h3 << _l_mask_mask_T_110; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_112 = ldq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_113 = ldq_7_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_114 = _l_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_115 = &ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_117 = _l_mask_mask_T_112 ? _l_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_118 = _l_mask_mask_T_108 ? _l_mask_mask_T_111 : {7'h0, _l_mask_mask_T_117}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_119 = _l_mask_mask_T_105 ? _l_mask_mask_T_107 : _l_mask_mask_T_118; // @[Mux.scala:126:16]
assign l_mask_7 = _l_mask_mask_T_119[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_14 = wb_forward_ldq_idx_0 == 5'h7; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_15 = wb_forward_valid_0 & _l_forwarders_T_14; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_7_0 = _l_forwarders_T_15; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_7 = l_forwarders_7_0 ? wb_forward_stq_idx_0 : ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_22 = ldq_7_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_29 = ldq_7_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_363 = l_mask_7 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_14; // @[lsu.scala:1083:46]
assign _mask_match_T_14 = _GEN_363; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1084:46]
assign _mask_overlap_T_14 = _GEN_363; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_15 = _mask_match_T_14 == l_mask_7; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_15 = |_mask_overlap_T_14; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:263:49, :1084:62]
wire _T_517 = do_release_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & block_addr_matches_7_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_546 = ldq_7_bits_executed | ldq_7_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_525 = ldq_7_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_529 = do_st_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & (_T_546 | l_forwarders_7_0) & ~ldq_7_bits_addr_is_virtual & _T_525[0] & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_28 = l_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_29 = l_forward_stq_idx_7 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:363:{58,72,78}]
wire _T_533 = ~ldq_7_bits_forward_std_val | l_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7; // @[util.scala:363:72]
wire _T_539 = do_ld_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & ~ldq_7_bits_addr_is_virtual & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_28 = lcam_ldq_idx_0 < 5'h7; // @[util.scala:363:52]
wire _searcher_is_older_T_30 = _searcher_is_older_T_28 ^ _searcher_is_older_T_29; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_31 = |(ldq_head[4:3]); // @[util.scala:351:72, :363:78]
wire searcher_is_older_7 = _searcher_is_older_T_30 ^ _searcher_is_older_T_31; // @[util.scala:363:{58,72,78}]
wire _GEN_364 = _T_539 & searcher_is_older_7 & (_T_546 | l_forwarders_7_0) & ~s1_executing_loads_7 & ldq_7_bits_observed; // @[util.scala:363:72]
assign failed_loads_7 = ~_T_517 & (_T_529 ? _T_533 : _GEN_364); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_7; // @[lsu.scala:1129:57]
wire older_nacked_7 = nacking_loads_7 | older_nacked_REG_7; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_548 = ~_T_546 | older_nacked_7; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_365 = searcher_is_older_7 | _GEN_315; // @[util.scala:363:72]
wire _GEN_366 = _T_517 | _T_529; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_7; // @[lsu.scala:1132:58]
wire _GEN_367 = _GEN_366 | ~_T_539 | _GEN_365 | ~_T_548; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_8; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_120 = ldq_8_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_121 = ldq_8_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_122 = 15'h1 << _l_mask_mask_T_121; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_123 = ldq_8_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_124 = ldq_8_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_125 = {_l_mask_mask_T_124, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_126 = 15'h3 << _l_mask_mask_T_125; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_127 = ldq_8_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_128 = ldq_8_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_129 = _l_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_130 = &ldq_8_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_132 = _l_mask_mask_T_127 ? _l_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_133 = _l_mask_mask_T_123 ? _l_mask_mask_T_126 : {7'h0, _l_mask_mask_T_132}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_134 = _l_mask_mask_T_120 ? _l_mask_mask_T_122 : _l_mask_mask_T_133; // @[Mux.scala:126:16]
assign l_mask_8 = _l_mask_mask_T_134[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_16 = wb_forward_ldq_idx_0 == 5'h8; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_17 = wb_forward_valid_0 & _l_forwarders_T_16; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_8_0 = _l_forwarders_T_17; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_8 = l_forwarders_8_0 ? wb_forward_stq_idx_0 : ldq_8_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_25 = ldq_8_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_26 = _block_addr_matches_T_24 == _block_addr_matches_T_25; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_8_0 = _block_addr_matches_T_26; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_33 = ldq_8_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_34 = _dword_addr_matches_T_32 == _dword_addr_matches_T_33; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_35 = block_addr_matches_8_0 & _dword_addr_matches_T_34; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_8_0 = _dword_addr_matches_T_35; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_368 = l_mask_8 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_16; // @[lsu.scala:1083:46]
assign _mask_match_T_16 = _GEN_368; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_16; // @[lsu.scala:1084:46]
assign _mask_overlap_T_16 = _GEN_368; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_17 = _mask_match_T_16 == l_mask_8; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_8_0 = _mask_match_T_17; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_17 = |_mask_overlap_T_16; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_8_0 = _mask_overlap_T_17; // @[lsu.scala:263:49, :1084:62]
wire _T_553 = do_release_search_0 & ldq_8_valid & ldq_8_bits_addr_valid & block_addr_matches_8_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_582 = ldq_8_bits_executed | ldq_8_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_561 = ldq_8_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_565 = do_st_search_0 & ldq_8_valid & ldq_8_bits_addr_valid & (_T_582 | l_forwarders_8_0) & ~ldq_8_bits_addr_is_virtual & _T_561[0] & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_32 = l_forward_stq_idx_8 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_33 = l_forward_stq_idx_8 < ldq_8_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_34 = _forwarded_is_older_T_32 ^ _forwarded_is_older_T_33; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_35 = lcam_stq_idx_0 < ldq_8_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_8 = _forwarded_is_older_T_34 ^ _forwarded_is_older_T_35; // @[util.scala:363:{58,72,78}]
wire _T_569 = ~ldq_8_bits_forward_std_val | l_forward_stq_idx_8 != lcam_stq_idx_0 & forwarded_is_older_8; // @[util.scala:363:72]
wire _T_575 = do_ld_search_0 & ldq_8_valid & ldq_8_bits_addr_valid & ~ldq_8_bits_addr_is_virtual & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_32 = lcam_ldq_idx_0 < 5'h8; // @[util.scala:363:52]
wire _searcher_is_older_T_34 = _searcher_is_older_T_32 ^ _searcher_is_older_T_33; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_35 = ldq_head > 5'h8; // @[util.scala:363:78]
wire searcher_is_older_8 = _searcher_is_older_T_34 ^ _searcher_is_older_T_35; // @[util.scala:363:{58,72,78}]
wire _GEN_369 = _T_575 & searcher_is_older_8 & (_T_582 | l_forwarders_8_0) & ~s1_executing_loads_8 & ldq_8_bits_observed; // @[util.scala:363:72]
assign failed_loads_8 = ~_T_553 & (_T_565 ? _T_569 : _GEN_369); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_8; // @[lsu.scala:1129:57]
wire older_nacked_8 = nacking_loads_8 | older_nacked_REG_8; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_584 = ~_T_582 | older_nacked_8; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_370 = searcher_is_older_8 | _GEN_316; // @[util.scala:363:72]
wire _GEN_371 = _T_553 | _T_565; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_8; // @[lsu.scala:1132:58]
wire _GEN_372 = _GEN_371 | ~_T_575 | _GEN_370 | ~_T_584; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_9; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_135 = ldq_9_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_136 = ldq_9_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_137 = 15'h1 << _l_mask_mask_T_136; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_138 = ldq_9_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_139 = ldq_9_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_140 = {_l_mask_mask_T_139, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_141 = 15'h3 << _l_mask_mask_T_140; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_142 = ldq_9_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_143 = ldq_9_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_144 = _l_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_145 = &ldq_9_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_147 = _l_mask_mask_T_142 ? _l_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_148 = _l_mask_mask_T_138 ? _l_mask_mask_T_141 : {7'h0, _l_mask_mask_T_147}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_149 = _l_mask_mask_T_135 ? _l_mask_mask_T_137 : _l_mask_mask_T_148; // @[Mux.scala:126:16]
assign l_mask_9 = _l_mask_mask_T_149[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_18 = wb_forward_ldq_idx_0 == 5'h9; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_19 = wb_forward_valid_0 & _l_forwarders_T_18; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_9_0 = _l_forwarders_T_19; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_9 = l_forwarders_9_0 ? wb_forward_stq_idx_0 : ldq_9_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_28 = ldq_9_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_29 = _block_addr_matches_T_27 == _block_addr_matches_T_28; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_9_0 = _block_addr_matches_T_29; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_37 = ldq_9_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_38 = _dword_addr_matches_T_36 == _dword_addr_matches_T_37; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_39 = block_addr_matches_9_0 & _dword_addr_matches_T_38; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_9_0 = _dword_addr_matches_T_39; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_373 = l_mask_9 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_18; // @[lsu.scala:1083:46]
assign _mask_match_T_18 = _GEN_373; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_18; // @[lsu.scala:1084:46]
assign _mask_overlap_T_18 = _GEN_373; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_19 = _mask_match_T_18 == l_mask_9; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_9_0 = _mask_match_T_19; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_19 = |_mask_overlap_T_18; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_9_0 = _mask_overlap_T_19; // @[lsu.scala:263:49, :1084:62]
wire _T_589 = do_release_search_0 & ldq_9_valid & ldq_9_bits_addr_valid & block_addr_matches_9_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_618 = ldq_9_bits_executed | ldq_9_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_597 = ldq_9_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_601 = do_st_search_0 & ldq_9_valid & ldq_9_bits_addr_valid & (_T_618 | l_forwarders_9_0) & ~ldq_9_bits_addr_is_virtual & _T_597[0] & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_36 = l_forward_stq_idx_9 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_37 = l_forward_stq_idx_9 < ldq_9_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_38 = _forwarded_is_older_T_36 ^ _forwarded_is_older_T_37; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_39 = lcam_stq_idx_0 < ldq_9_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_9 = _forwarded_is_older_T_38 ^ _forwarded_is_older_T_39; // @[util.scala:363:{58,72,78}]
wire _T_605 = ~ldq_9_bits_forward_std_val | l_forward_stq_idx_9 != lcam_stq_idx_0 & forwarded_is_older_9; // @[util.scala:363:72]
wire _T_611 = do_ld_search_0 & ldq_9_valid & ldq_9_bits_addr_valid & ~ldq_9_bits_addr_is_virtual & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_36 = lcam_ldq_idx_0 < 5'h9; // @[util.scala:363:52]
wire _searcher_is_older_T_38 = _searcher_is_older_T_36 ^ _searcher_is_older_T_37; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_39 = ldq_head > 5'h9; // @[util.scala:363:78]
wire searcher_is_older_9 = _searcher_is_older_T_38 ^ _searcher_is_older_T_39; // @[util.scala:363:{58,72,78}]
wire _GEN_374 = _T_611 & searcher_is_older_9 & (_T_618 | l_forwarders_9_0) & ~s1_executing_loads_9 & ldq_9_bits_observed; // @[util.scala:363:72]
assign failed_loads_9 = ~_T_589 & (_T_601 ? _T_605 : _GEN_374); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_9; // @[lsu.scala:1129:57]
wire older_nacked_9 = nacking_loads_9 | older_nacked_REG_9; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_620 = ~_T_618 | older_nacked_9; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_375 = searcher_is_older_9 | _GEN_317; // @[util.scala:363:72]
wire _GEN_376 = _T_589 | _T_601; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_9; // @[lsu.scala:1132:58]
wire _GEN_377 = _GEN_376 | ~_T_611 | _GEN_375 | ~_T_620; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_10; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_150 = ldq_10_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_151 = ldq_10_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_152 = 15'h1 << _l_mask_mask_T_151; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_153 = ldq_10_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_154 = ldq_10_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_155 = {_l_mask_mask_T_154, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_156 = 15'h3 << _l_mask_mask_T_155; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_157 = ldq_10_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_158 = ldq_10_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_159 = _l_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_160 = &ldq_10_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_162 = _l_mask_mask_T_157 ? _l_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_163 = _l_mask_mask_T_153 ? _l_mask_mask_T_156 : {7'h0, _l_mask_mask_T_162}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_164 = _l_mask_mask_T_150 ? _l_mask_mask_T_152 : _l_mask_mask_T_163; // @[Mux.scala:126:16]
assign l_mask_10 = _l_mask_mask_T_164[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_20 = wb_forward_ldq_idx_0 == 5'hA; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_21 = wb_forward_valid_0 & _l_forwarders_T_20; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_10_0 = _l_forwarders_T_21; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_10 = l_forwarders_10_0 ? wb_forward_stq_idx_0 : ldq_10_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_31 = ldq_10_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_32 = _block_addr_matches_T_30 == _block_addr_matches_T_31; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_10_0 = _block_addr_matches_T_32; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_41 = ldq_10_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_43 = block_addr_matches_10_0 & _dword_addr_matches_T_42; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_10_0 = _dword_addr_matches_T_43; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_378 = l_mask_10 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_20; // @[lsu.scala:1083:46]
assign _mask_match_T_20 = _GEN_378; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_20; // @[lsu.scala:1084:46]
assign _mask_overlap_T_20 = _GEN_378; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_21 = _mask_match_T_20 == l_mask_10; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_10_0 = _mask_match_T_21; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_21 = |_mask_overlap_T_20; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_10_0 = _mask_overlap_T_21; // @[lsu.scala:263:49, :1084:62]
wire _T_625 = do_release_search_0 & ldq_10_valid & ldq_10_bits_addr_valid & block_addr_matches_10_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_654 = ldq_10_bits_executed | ldq_10_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_633 = ldq_10_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_637 = do_st_search_0 & ldq_10_valid & ldq_10_bits_addr_valid & (_T_654 | l_forwarders_10_0) & ~ldq_10_bits_addr_is_virtual & _T_633[0] & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_40 = l_forward_stq_idx_10 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_41 = l_forward_stq_idx_10 < ldq_10_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_42 = _forwarded_is_older_T_40 ^ _forwarded_is_older_T_41; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_43 = lcam_stq_idx_0 < ldq_10_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_10 = _forwarded_is_older_T_42 ^ _forwarded_is_older_T_43; // @[util.scala:363:{58,72,78}]
wire _T_641 = ~ldq_10_bits_forward_std_val | l_forward_stq_idx_10 != lcam_stq_idx_0 & forwarded_is_older_10; // @[util.scala:363:72]
wire _T_647 = do_ld_search_0 & ldq_10_valid & ldq_10_bits_addr_valid & ~ldq_10_bits_addr_is_virtual & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_40 = lcam_ldq_idx_0 < 5'hA; // @[util.scala:363:52]
wire _searcher_is_older_T_42 = _searcher_is_older_T_40 ^ _searcher_is_older_T_41; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_43 = ldq_head > 5'hA; // @[util.scala:363:78]
wire searcher_is_older_10 = _searcher_is_older_T_42 ^ _searcher_is_older_T_43; // @[util.scala:363:{58,72,78}]
wire _GEN_379 = _T_647 & searcher_is_older_10 & (_T_654 | l_forwarders_10_0) & ~s1_executing_loads_10 & ldq_10_bits_observed; // @[util.scala:363:72]
assign failed_loads_10 = ~_T_625 & (_T_637 ? _T_641 : _GEN_379); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_10; // @[lsu.scala:1129:57]
wire older_nacked_10 = nacking_loads_10 | older_nacked_REG_10; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_656 = ~_T_654 | older_nacked_10; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_380 = searcher_is_older_10 | _GEN_318; // @[util.scala:363:72]
wire _GEN_381 = _T_625 | _T_637; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_10; // @[lsu.scala:1132:58]
wire _GEN_382 = _GEN_381 | ~_T_647 | _GEN_380 | ~_T_656; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_11; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_165 = ldq_11_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_166 = ldq_11_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_167 = 15'h1 << _l_mask_mask_T_166; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_168 = ldq_11_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_169 = ldq_11_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_170 = {_l_mask_mask_T_169, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_171 = 15'h3 << _l_mask_mask_T_170; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_172 = ldq_11_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_173 = ldq_11_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_174 = _l_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_175 = &ldq_11_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_177 = _l_mask_mask_T_172 ? _l_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_178 = _l_mask_mask_T_168 ? _l_mask_mask_T_171 : {7'h0, _l_mask_mask_T_177}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_179 = _l_mask_mask_T_165 ? _l_mask_mask_T_167 : _l_mask_mask_T_178; // @[Mux.scala:126:16]
assign l_mask_11 = _l_mask_mask_T_179[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_22 = wb_forward_ldq_idx_0 == 5'hB; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_23 = wb_forward_valid_0 & _l_forwarders_T_22; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_11_0 = _l_forwarders_T_23; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_11 = l_forwarders_11_0 ? wb_forward_stq_idx_0 : ldq_11_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_34 = ldq_11_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_35 = _block_addr_matches_T_33 == _block_addr_matches_T_34; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_11_0 = _block_addr_matches_T_35; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_45 = ldq_11_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_46 = _dword_addr_matches_T_44 == _dword_addr_matches_T_45; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_47 = block_addr_matches_11_0 & _dword_addr_matches_T_46; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_11_0 = _dword_addr_matches_T_47; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_383 = l_mask_11 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_22; // @[lsu.scala:1083:46]
assign _mask_match_T_22 = _GEN_383; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_22; // @[lsu.scala:1084:46]
assign _mask_overlap_T_22 = _GEN_383; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_23 = _mask_match_T_22 == l_mask_11; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_11_0 = _mask_match_T_23; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_23 = |_mask_overlap_T_22; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_11_0 = _mask_overlap_T_23; // @[lsu.scala:263:49, :1084:62]
wire _T_661 = do_release_search_0 & ldq_11_valid & ldq_11_bits_addr_valid & block_addr_matches_11_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_690 = ldq_11_bits_executed | ldq_11_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_669 = ldq_11_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_673 = do_st_search_0 & ldq_11_valid & ldq_11_bits_addr_valid & (_T_690 | l_forwarders_11_0) & ~ldq_11_bits_addr_is_virtual & _T_669[0] & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_44 = l_forward_stq_idx_11 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_45 = l_forward_stq_idx_11 < ldq_11_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_46 = _forwarded_is_older_T_44 ^ _forwarded_is_older_T_45; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_47 = lcam_stq_idx_0 < ldq_11_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_11 = _forwarded_is_older_T_46 ^ _forwarded_is_older_T_47; // @[util.scala:363:{58,72,78}]
wire _T_677 = ~ldq_11_bits_forward_std_val | l_forward_stq_idx_11 != lcam_stq_idx_0 & forwarded_is_older_11; // @[util.scala:363:72]
wire _T_683 = do_ld_search_0 & ldq_11_valid & ldq_11_bits_addr_valid & ~ldq_11_bits_addr_is_virtual & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_44 = lcam_ldq_idx_0 < 5'hB; // @[util.scala:363:52]
wire _searcher_is_older_T_46 = _searcher_is_older_T_44 ^ _searcher_is_older_T_45; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_47 = ldq_head > 5'hB; // @[util.scala:363:78]
wire searcher_is_older_11 = _searcher_is_older_T_46 ^ _searcher_is_older_T_47; // @[util.scala:363:{58,72,78}]
wire _GEN_384 = _T_683 & searcher_is_older_11 & (_T_690 | l_forwarders_11_0) & ~s1_executing_loads_11 & ldq_11_bits_observed; // @[util.scala:363:72]
assign failed_loads_11 = ~_T_661 & (_T_673 ? _T_677 : _GEN_384); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_11; // @[lsu.scala:1129:57]
wire older_nacked_11 = nacking_loads_11 | older_nacked_REG_11; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_692 = ~_T_690 | older_nacked_11; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_385 = searcher_is_older_11 | _GEN_319; // @[util.scala:363:72]
wire _GEN_386 = _T_661 | _T_673; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_11; // @[lsu.scala:1132:58]
wire _GEN_387 = _GEN_386 | ~_T_683 | _GEN_385 | ~_T_692; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_12; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_180 = ldq_12_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_181 = ldq_12_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_182 = 15'h1 << _l_mask_mask_T_181; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_183 = ldq_12_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_184 = ldq_12_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_185 = {_l_mask_mask_T_184, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_186 = 15'h3 << _l_mask_mask_T_185; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_187 = ldq_12_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_188 = ldq_12_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_189 = _l_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_190 = &ldq_12_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_192 = _l_mask_mask_T_187 ? _l_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_193 = _l_mask_mask_T_183 ? _l_mask_mask_T_186 : {7'h0, _l_mask_mask_T_192}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_194 = _l_mask_mask_T_180 ? _l_mask_mask_T_182 : _l_mask_mask_T_193; // @[Mux.scala:126:16]
assign l_mask_12 = _l_mask_mask_T_194[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_24 = wb_forward_ldq_idx_0 == 5'hC; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_25 = wb_forward_valid_0 & _l_forwarders_T_24; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_12_0 = _l_forwarders_T_25; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_12 = l_forwarders_12_0 ? wb_forward_stq_idx_0 : ldq_12_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_37 = ldq_12_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_38 = _block_addr_matches_T_36 == _block_addr_matches_T_37; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_12_0 = _block_addr_matches_T_38; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_49 = ldq_12_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_50 = _dword_addr_matches_T_48 == _dword_addr_matches_T_49; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_51 = block_addr_matches_12_0 & _dword_addr_matches_T_50; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_12_0 = _dword_addr_matches_T_51; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_388 = l_mask_12 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_24; // @[lsu.scala:1083:46]
assign _mask_match_T_24 = _GEN_388; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_24; // @[lsu.scala:1084:46]
assign _mask_overlap_T_24 = _GEN_388; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_25 = _mask_match_T_24 == l_mask_12; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_12_0 = _mask_match_T_25; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_25 = |_mask_overlap_T_24; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_12_0 = _mask_overlap_T_25; // @[lsu.scala:263:49, :1084:62]
wire _T_697 = do_release_search_0 & ldq_12_valid & ldq_12_bits_addr_valid & block_addr_matches_12_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_726 = ldq_12_bits_executed | ldq_12_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_705 = ldq_12_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_709 = do_st_search_0 & ldq_12_valid & ldq_12_bits_addr_valid & (_T_726 | l_forwarders_12_0) & ~ldq_12_bits_addr_is_virtual & _T_705[0] & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_48 = l_forward_stq_idx_12 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_49 = l_forward_stq_idx_12 < ldq_12_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_50 = _forwarded_is_older_T_48 ^ _forwarded_is_older_T_49; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_51 = lcam_stq_idx_0 < ldq_12_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_12 = _forwarded_is_older_T_50 ^ _forwarded_is_older_T_51; // @[util.scala:363:{58,72,78}]
wire _T_713 = ~ldq_12_bits_forward_std_val | l_forward_stq_idx_12 != lcam_stq_idx_0 & forwarded_is_older_12; // @[util.scala:363:72]
wire _T_719 = do_ld_search_0 & ldq_12_valid & ldq_12_bits_addr_valid & ~ldq_12_bits_addr_is_virtual & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_48 = lcam_ldq_idx_0 < 5'hC; // @[util.scala:363:52]
wire _searcher_is_older_T_50 = _searcher_is_older_T_48 ^ _searcher_is_older_T_49; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_51 = ldq_head > 5'hC; // @[util.scala:363:78]
wire searcher_is_older_12 = _searcher_is_older_T_50 ^ _searcher_is_older_T_51; // @[util.scala:363:{58,72,78}]
wire _GEN_389 = _T_719 & searcher_is_older_12 & (_T_726 | l_forwarders_12_0) & ~s1_executing_loads_12 & ldq_12_bits_observed; // @[util.scala:363:72]
assign failed_loads_12 = ~_T_697 & (_T_709 ? _T_713 : _GEN_389); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_12; // @[lsu.scala:1129:57]
wire older_nacked_12 = nacking_loads_12 | older_nacked_REG_12; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_728 = ~_T_726 | older_nacked_12; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_390 = searcher_is_older_12 | _GEN_320; // @[util.scala:363:72]
wire _GEN_391 = _T_697 | _T_709; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_12; // @[lsu.scala:1132:58]
wire _GEN_392 = _GEN_391 | ~_T_719 | _GEN_390 | ~_T_728; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_13; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_195 = ldq_13_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_196 = ldq_13_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_197 = 15'h1 << _l_mask_mask_T_196; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_198 = ldq_13_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_199 = ldq_13_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_200 = {_l_mask_mask_T_199, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_201 = 15'h3 << _l_mask_mask_T_200; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_202 = ldq_13_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_203 = ldq_13_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_204 = _l_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_205 = &ldq_13_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_207 = _l_mask_mask_T_202 ? _l_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_208 = _l_mask_mask_T_198 ? _l_mask_mask_T_201 : {7'h0, _l_mask_mask_T_207}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_209 = _l_mask_mask_T_195 ? _l_mask_mask_T_197 : _l_mask_mask_T_208; // @[Mux.scala:126:16]
assign l_mask_13 = _l_mask_mask_T_209[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_26 = wb_forward_ldq_idx_0 == 5'hD; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_27 = wb_forward_valid_0 & _l_forwarders_T_26; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_13_0 = _l_forwarders_T_27; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_13 = l_forwarders_13_0 ? wb_forward_stq_idx_0 : ldq_13_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_40 = ldq_13_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_41 = _block_addr_matches_T_39 == _block_addr_matches_T_40; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_13_0 = _block_addr_matches_T_41; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_53 = ldq_13_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_55 = block_addr_matches_13_0 & _dword_addr_matches_T_54; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_13_0 = _dword_addr_matches_T_55; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_393 = l_mask_13 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_26; // @[lsu.scala:1083:46]
assign _mask_match_T_26 = _GEN_393; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_26; // @[lsu.scala:1084:46]
assign _mask_overlap_T_26 = _GEN_393; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_27 = _mask_match_T_26 == l_mask_13; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_13_0 = _mask_match_T_27; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_27 = |_mask_overlap_T_26; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_13_0 = _mask_overlap_T_27; // @[lsu.scala:263:49, :1084:62]
wire _T_733 = do_release_search_0 & ldq_13_valid & ldq_13_bits_addr_valid & block_addr_matches_13_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_762 = ldq_13_bits_executed | ldq_13_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_741 = ldq_13_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_745 = do_st_search_0 & ldq_13_valid & ldq_13_bits_addr_valid & (_T_762 | l_forwarders_13_0) & ~ldq_13_bits_addr_is_virtual & _T_741[0] & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_52 = l_forward_stq_idx_13 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_53 = l_forward_stq_idx_13 < ldq_13_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_54 = _forwarded_is_older_T_52 ^ _forwarded_is_older_T_53; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_55 = lcam_stq_idx_0 < ldq_13_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_13 = _forwarded_is_older_T_54 ^ _forwarded_is_older_T_55; // @[util.scala:363:{58,72,78}]
wire _T_749 = ~ldq_13_bits_forward_std_val | l_forward_stq_idx_13 != lcam_stq_idx_0 & forwarded_is_older_13; // @[util.scala:363:72]
wire _T_755 = do_ld_search_0 & ldq_13_valid & ldq_13_bits_addr_valid & ~ldq_13_bits_addr_is_virtual & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_52 = lcam_ldq_idx_0 < 5'hD; // @[util.scala:363:52]
wire _searcher_is_older_T_54 = _searcher_is_older_T_52 ^ _searcher_is_older_T_53; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_55 = ldq_head > 5'hD; // @[util.scala:363:78]
wire searcher_is_older_13 = _searcher_is_older_T_54 ^ _searcher_is_older_T_55; // @[util.scala:363:{58,72,78}]
wire _GEN_394 = _T_755 & searcher_is_older_13 & (_T_762 | l_forwarders_13_0) & ~s1_executing_loads_13 & ldq_13_bits_observed; // @[util.scala:363:72]
assign failed_loads_13 = ~_T_733 & (_T_745 ? _T_749 : _GEN_394); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_13; // @[lsu.scala:1129:57]
wire older_nacked_13 = nacking_loads_13 | older_nacked_REG_13; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_764 = ~_T_762 | older_nacked_13; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_395 = searcher_is_older_13 | _GEN_321; // @[util.scala:363:72]
wire _GEN_396 = _T_733 | _T_745; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_13; // @[lsu.scala:1132:58]
wire _GEN_397 = _GEN_396 | ~_T_755 | _GEN_395 | ~_T_764; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_14; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_210 = ldq_14_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_211 = ldq_14_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_212 = 15'h1 << _l_mask_mask_T_211; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_213 = ldq_14_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_214 = ldq_14_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_215 = {_l_mask_mask_T_214, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_216 = 15'h3 << _l_mask_mask_T_215; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_217 = ldq_14_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_218 = ldq_14_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_219 = _l_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_220 = &ldq_14_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_222 = _l_mask_mask_T_217 ? _l_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_223 = _l_mask_mask_T_213 ? _l_mask_mask_T_216 : {7'h0, _l_mask_mask_T_222}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_224 = _l_mask_mask_T_210 ? _l_mask_mask_T_212 : _l_mask_mask_T_223; // @[Mux.scala:126:16]
assign l_mask_14 = _l_mask_mask_T_224[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_28 = wb_forward_ldq_idx_0 == 5'hE; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_29 = wb_forward_valid_0 & _l_forwarders_T_28; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_14_0 = _l_forwarders_T_29; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_14 = l_forwarders_14_0 ? wb_forward_stq_idx_0 : ldq_14_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_43 = ldq_14_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_44 = _block_addr_matches_T_42 == _block_addr_matches_T_43; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_14_0 = _block_addr_matches_T_44; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_57 = ldq_14_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_58 = _dword_addr_matches_T_56 == _dword_addr_matches_T_57; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_59 = block_addr_matches_14_0 & _dword_addr_matches_T_58; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_14_0 = _dword_addr_matches_T_59; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_398 = l_mask_14 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_28; // @[lsu.scala:1083:46]
assign _mask_match_T_28 = _GEN_398; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_28; // @[lsu.scala:1084:46]
assign _mask_overlap_T_28 = _GEN_398; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_29 = _mask_match_T_28 == l_mask_14; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_14_0 = _mask_match_T_29; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_29 = |_mask_overlap_T_28; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_14_0 = _mask_overlap_T_29; // @[lsu.scala:263:49, :1084:62]
wire _T_769 = do_release_search_0 & ldq_14_valid & ldq_14_bits_addr_valid & block_addr_matches_14_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_798 = ldq_14_bits_executed | ldq_14_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_777 = ldq_14_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_781 = do_st_search_0 & ldq_14_valid & ldq_14_bits_addr_valid & (_T_798 | l_forwarders_14_0) & ~ldq_14_bits_addr_is_virtual & _T_777[0] & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_56 = l_forward_stq_idx_14 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_57 = l_forward_stq_idx_14 < ldq_14_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_58 = _forwarded_is_older_T_56 ^ _forwarded_is_older_T_57; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_59 = lcam_stq_idx_0 < ldq_14_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_14 = _forwarded_is_older_T_58 ^ _forwarded_is_older_T_59; // @[util.scala:363:{58,72,78}]
wire _T_785 = ~ldq_14_bits_forward_std_val | l_forward_stq_idx_14 != lcam_stq_idx_0 & forwarded_is_older_14; // @[util.scala:363:72]
wire _T_791 = do_ld_search_0 & ldq_14_valid & ldq_14_bits_addr_valid & ~ldq_14_bits_addr_is_virtual & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_56 = lcam_ldq_idx_0 < 5'hE; // @[util.scala:363:52]
wire _searcher_is_older_T_58 = _searcher_is_older_T_56 ^ _searcher_is_older_T_57; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_59 = ldq_head > 5'hE; // @[util.scala:363:78]
wire searcher_is_older_14 = _searcher_is_older_T_58 ^ _searcher_is_older_T_59; // @[util.scala:363:{58,72,78}]
wire _GEN_399 = _T_791 & searcher_is_older_14 & (_T_798 | l_forwarders_14_0) & ~s1_executing_loads_14 & ldq_14_bits_observed; // @[util.scala:363:72]
assign failed_loads_14 = ~_T_769 & (_T_781 ? _T_785 : _GEN_399); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_14; // @[lsu.scala:1129:57]
wire older_nacked_14 = nacking_loads_14 | older_nacked_REG_14; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_800 = ~_T_798 | older_nacked_14; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_400 = searcher_is_older_14 | _GEN_322; // @[util.scala:363:72]
wire _GEN_401 = _T_769 | _T_781; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_14; // @[lsu.scala:1132:58]
wire _GEN_402 = _GEN_401 | ~_T_791 | _GEN_400 | ~_T_800; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_15; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_225 = ldq_15_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_226 = ldq_15_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_227 = 15'h1 << _l_mask_mask_T_226; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_228 = ldq_15_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_229 = ldq_15_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_230 = {_l_mask_mask_T_229, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_231 = 15'h3 << _l_mask_mask_T_230; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_232 = ldq_15_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_233 = ldq_15_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_234 = _l_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_235 = &ldq_15_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_237 = _l_mask_mask_T_232 ? _l_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_238 = _l_mask_mask_T_228 ? _l_mask_mask_T_231 : {7'h0, _l_mask_mask_T_237}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_239 = _l_mask_mask_T_225 ? _l_mask_mask_T_227 : _l_mask_mask_T_238; // @[Mux.scala:126:16]
assign l_mask_15 = _l_mask_mask_T_239[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_30 = wb_forward_ldq_idx_0 == 5'hF; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_31 = wb_forward_valid_0 & _l_forwarders_T_30; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_15_0 = _l_forwarders_T_31; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_15 = l_forwarders_15_0 ? wb_forward_stq_idx_0 : ldq_15_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_46 = ldq_15_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_47 = _block_addr_matches_T_45 == _block_addr_matches_T_46; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_15_0 = _block_addr_matches_T_47; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_61 = ldq_15_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_62 = _dword_addr_matches_T_60 == _dword_addr_matches_T_61; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_63 = block_addr_matches_15_0 & _dword_addr_matches_T_62; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_15_0 = _dword_addr_matches_T_63; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_403 = l_mask_15 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_30; // @[lsu.scala:1083:46]
assign _mask_match_T_30 = _GEN_403; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_30; // @[lsu.scala:1084:46]
assign _mask_overlap_T_30 = _GEN_403; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_31 = _mask_match_T_30 == l_mask_15; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_15_0 = _mask_match_T_31; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_31 = |_mask_overlap_T_30; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_15_0 = _mask_overlap_T_31; // @[lsu.scala:263:49, :1084:62]
wire _T_805 = do_release_search_0 & ldq_15_valid & ldq_15_bits_addr_valid & block_addr_matches_15_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_834 = ldq_15_bits_executed | ldq_15_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_813 = ldq_15_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_817 = do_st_search_0 & ldq_15_valid & ldq_15_bits_addr_valid & (_T_834 | l_forwarders_15_0) & ~ldq_15_bits_addr_is_virtual & _T_813[0] & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_60 = l_forward_stq_idx_15 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_61 = l_forward_stq_idx_15 < ldq_15_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_62 = _forwarded_is_older_T_60 ^ _forwarded_is_older_T_61; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_63 = lcam_stq_idx_0 < ldq_15_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_15 = _forwarded_is_older_T_62 ^ _forwarded_is_older_T_63; // @[util.scala:363:{58,72,78}]
wire _T_821 = ~ldq_15_bits_forward_std_val | l_forward_stq_idx_15 != lcam_stq_idx_0 & forwarded_is_older_15; // @[util.scala:363:72]
wire _T_827 = do_ld_search_0 & ldq_15_valid & ldq_15_bits_addr_valid & ~ldq_15_bits_addr_is_virtual & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_60 = lcam_ldq_idx_0 < 5'hF; // @[util.scala:363:52]
wire _searcher_is_older_T_62 = _searcher_is_older_T_60 ^ _searcher_is_older_T_61; // @[util.scala:363:{52,58,64}]
wire searcher_is_older_15 = _searcher_is_older_T_62 ^ _searcher_is_older_T_63; // @[util.scala:363:{58,72,78}]
wire _GEN_404 = _T_827 & searcher_is_older_15 & (_T_834 | l_forwarders_15_0) & ~s1_executing_loads_15 & ldq_15_bits_observed; // @[util.scala:363:72]
assign failed_loads_15 = ~_T_805 & (_T_817 ? _T_821 : _GEN_404); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_15; // @[lsu.scala:1129:57]
wire older_nacked_15 = nacking_loads_15 | older_nacked_REG_15; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_836 = ~_T_834 | older_nacked_15; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_405 = searcher_is_older_15 | _GEN_323; // @[util.scala:363:72]
wire _GEN_406 = _T_805 | _T_817; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_15; // @[lsu.scala:1132:58]
wire _GEN_407 = _GEN_406 | ~_T_827 | _GEN_405 | ~_T_836; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_16; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_240 = ldq_16_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_241 = ldq_16_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_242 = 15'h1 << _l_mask_mask_T_241; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_243 = ldq_16_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_244 = ldq_16_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_245 = {_l_mask_mask_T_244, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_246 = 15'h3 << _l_mask_mask_T_245; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_247 = ldq_16_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_248 = ldq_16_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_249 = _l_mask_mask_T_248 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_250 = &ldq_16_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_252 = _l_mask_mask_T_247 ? _l_mask_mask_T_249 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_253 = _l_mask_mask_T_243 ? _l_mask_mask_T_246 : {7'h0, _l_mask_mask_T_252}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_254 = _l_mask_mask_T_240 ? _l_mask_mask_T_242 : _l_mask_mask_T_253; // @[Mux.scala:126:16]
assign l_mask_16 = _l_mask_mask_T_254[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_32 = wb_forward_ldq_idx_0 == 5'h10; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_33 = wb_forward_valid_0 & _l_forwarders_T_32; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_16_0 = _l_forwarders_T_33; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_16 = l_forwarders_16_0 ? wb_forward_stq_idx_0 : ldq_16_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_49 = ldq_16_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_50 = _block_addr_matches_T_48 == _block_addr_matches_T_49; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_16_0 = _block_addr_matches_T_50; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_65 = ldq_16_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_66 = _dword_addr_matches_T_64 == _dword_addr_matches_T_65; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_67 = block_addr_matches_16_0 & _dword_addr_matches_T_66; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_16_0 = _dword_addr_matches_T_67; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_408 = l_mask_16 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_32; // @[lsu.scala:1083:46]
assign _mask_match_T_32 = _GEN_408; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_32; // @[lsu.scala:1084:46]
assign _mask_overlap_T_32 = _GEN_408; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_33 = _mask_match_T_32 == l_mask_16; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_16_0 = _mask_match_T_33; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_33 = |_mask_overlap_T_32; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_16_0 = _mask_overlap_T_33; // @[lsu.scala:263:49, :1084:62]
wire _T_841 = do_release_search_0 & ldq_16_valid & ldq_16_bits_addr_valid & block_addr_matches_16_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_870 = ldq_16_bits_executed | ldq_16_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_849 = ldq_16_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_853 = do_st_search_0 & ldq_16_valid & ldq_16_bits_addr_valid & (_T_870 | l_forwarders_16_0) & ~ldq_16_bits_addr_is_virtual & _T_849[0] & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_64 = l_forward_stq_idx_16 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_65 = l_forward_stq_idx_16 < ldq_16_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_66 = _forwarded_is_older_T_64 ^ _forwarded_is_older_T_65; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_67 = lcam_stq_idx_0 < ldq_16_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_16 = _forwarded_is_older_T_66 ^ _forwarded_is_older_T_67; // @[util.scala:363:{58,72,78}]
wire _T_857 = ~ldq_16_bits_forward_std_val | l_forward_stq_idx_16 != lcam_stq_idx_0 & forwarded_is_older_16; // @[util.scala:363:72]
wire _T_863 = do_ld_search_0 & ldq_16_valid & ldq_16_bits_addr_valid & ~ldq_16_bits_addr_is_virtual & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_64 = ~(lcam_ldq_idx_0[4]); // @[util.scala:363:52]
wire _searcher_is_older_T_66 = _searcher_is_older_T_64 ^ _searcher_is_older_T_65; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_67 = ldq_head > 5'h10; // @[util.scala:363:78]
wire searcher_is_older_16 = _searcher_is_older_T_66 ^ _searcher_is_older_T_67; // @[util.scala:363:{58,72,78}]
wire _GEN_409 = _T_863 & searcher_is_older_16 & (_T_870 | l_forwarders_16_0) & ~s1_executing_loads_16 & ldq_16_bits_observed; // @[util.scala:363:72]
assign failed_loads_16 = ~_T_841 & (_T_853 ? _T_857 : _GEN_409); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_16; // @[lsu.scala:1129:57]
wire older_nacked_16 = nacking_loads_16 | older_nacked_REG_16; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_872 = ~_T_870 | older_nacked_16; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_410 = searcher_is_older_16 | _GEN_324; // @[util.scala:363:72]
wire _GEN_411 = _T_841 | _T_853; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_16; // @[lsu.scala:1132:58]
wire _GEN_412 = _GEN_411 | ~_T_863 | _GEN_410 | ~_T_872; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_17; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_255 = ldq_17_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_256 = ldq_17_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_257 = 15'h1 << _l_mask_mask_T_256; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_258 = ldq_17_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_259 = ldq_17_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_260 = {_l_mask_mask_T_259, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_261 = 15'h3 << _l_mask_mask_T_260; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_262 = ldq_17_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_263 = ldq_17_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_264 = _l_mask_mask_T_263 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_265 = &ldq_17_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_267 = _l_mask_mask_T_262 ? _l_mask_mask_T_264 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_268 = _l_mask_mask_T_258 ? _l_mask_mask_T_261 : {7'h0, _l_mask_mask_T_267}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_269 = _l_mask_mask_T_255 ? _l_mask_mask_T_257 : _l_mask_mask_T_268; // @[Mux.scala:126:16]
assign l_mask_17 = _l_mask_mask_T_269[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_34 = wb_forward_ldq_idx_0 == 5'h11; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_35 = wb_forward_valid_0 & _l_forwarders_T_34; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_17_0 = _l_forwarders_T_35; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_17 = l_forwarders_17_0 ? wb_forward_stq_idx_0 : ldq_17_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_52 = ldq_17_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_53 = _block_addr_matches_T_51 == _block_addr_matches_T_52; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_17_0 = _block_addr_matches_T_53; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_69 = ldq_17_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_70 = _dword_addr_matches_T_68 == _dword_addr_matches_T_69; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_71 = block_addr_matches_17_0 & _dword_addr_matches_T_70; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_17_0 = _dword_addr_matches_T_71; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_413 = l_mask_17 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_34; // @[lsu.scala:1083:46]
assign _mask_match_T_34 = _GEN_413; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_34; // @[lsu.scala:1084:46]
assign _mask_overlap_T_34 = _GEN_413; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_35 = _mask_match_T_34 == l_mask_17; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_17_0 = _mask_match_T_35; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_35 = |_mask_overlap_T_34; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_17_0 = _mask_overlap_T_35; // @[lsu.scala:263:49, :1084:62]
wire _T_877 = do_release_search_0 & ldq_17_valid & ldq_17_bits_addr_valid & block_addr_matches_17_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_906 = ldq_17_bits_executed | ldq_17_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_885 = ldq_17_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_889 = do_st_search_0 & ldq_17_valid & ldq_17_bits_addr_valid & (_T_906 | l_forwarders_17_0) & ~ldq_17_bits_addr_is_virtual & _T_885[0] & dword_addr_matches_17_0 & mask_overlap_17_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_68 = l_forward_stq_idx_17 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_69 = l_forward_stq_idx_17 < ldq_17_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_70 = _forwarded_is_older_T_68 ^ _forwarded_is_older_T_69; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_71 = lcam_stq_idx_0 < ldq_17_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_17 = _forwarded_is_older_T_70 ^ _forwarded_is_older_T_71; // @[util.scala:363:{58,72,78}]
wire _T_893 = ~ldq_17_bits_forward_std_val | l_forward_stq_idx_17 != lcam_stq_idx_0 & forwarded_is_older_17; // @[util.scala:363:72]
wire _T_899 = do_ld_search_0 & ldq_17_valid & ldq_17_bits_addr_valid & ~ldq_17_bits_addr_is_virtual & dword_addr_matches_17_0 & mask_overlap_17_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_68 = lcam_ldq_idx_0 < 5'h11; // @[util.scala:363:52]
wire _searcher_is_older_T_70 = _searcher_is_older_T_68 ^ _searcher_is_older_T_69; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_71 = ldq_head > 5'h11; // @[util.scala:363:78]
wire searcher_is_older_17 = _searcher_is_older_T_70 ^ _searcher_is_older_T_71; // @[util.scala:363:{58,72,78}]
wire _GEN_414 = _T_899 & searcher_is_older_17 & (_T_906 | l_forwarders_17_0) & ~s1_executing_loads_17 & ldq_17_bits_observed; // @[util.scala:363:72]
assign failed_loads_17 = ~_T_877 & (_T_889 ? _T_893 : _GEN_414); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_17; // @[lsu.scala:1129:57]
wire older_nacked_17 = nacking_loads_17 | older_nacked_REG_17; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_908 = ~_T_906 | older_nacked_17; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_415 = searcher_is_older_17 | _GEN_325; // @[util.scala:363:72]
wire _GEN_416 = _T_877 | _T_889; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_17; // @[lsu.scala:1132:58]
wire _GEN_417 = _GEN_416 | ~_T_899 | _GEN_415 | ~_T_908; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_18; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_270 = ldq_18_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_271 = ldq_18_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_272 = 15'h1 << _l_mask_mask_T_271; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_273 = ldq_18_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_274 = ldq_18_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_275 = {_l_mask_mask_T_274, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_276 = 15'h3 << _l_mask_mask_T_275; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_277 = ldq_18_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_278 = ldq_18_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_279 = _l_mask_mask_T_278 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_280 = &ldq_18_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_282 = _l_mask_mask_T_277 ? _l_mask_mask_T_279 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_283 = _l_mask_mask_T_273 ? _l_mask_mask_T_276 : {7'h0, _l_mask_mask_T_282}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_284 = _l_mask_mask_T_270 ? _l_mask_mask_T_272 : _l_mask_mask_T_283; // @[Mux.scala:126:16]
assign l_mask_18 = _l_mask_mask_T_284[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_36 = wb_forward_ldq_idx_0 == 5'h12; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_37 = wb_forward_valid_0 & _l_forwarders_T_36; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_18_0 = _l_forwarders_T_37; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_18 = l_forwarders_18_0 ? wb_forward_stq_idx_0 : ldq_18_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_55 = ldq_18_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_56 = _block_addr_matches_T_54 == _block_addr_matches_T_55; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_18_0 = _block_addr_matches_T_56; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_73 = ldq_18_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_74 = _dword_addr_matches_T_72 == _dword_addr_matches_T_73; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_75 = block_addr_matches_18_0 & _dword_addr_matches_T_74; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_18_0 = _dword_addr_matches_T_75; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_418 = l_mask_18 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_36; // @[lsu.scala:1083:46]
assign _mask_match_T_36 = _GEN_418; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_36; // @[lsu.scala:1084:46]
assign _mask_overlap_T_36 = _GEN_418; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_37 = _mask_match_T_36 == l_mask_18; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_18_0 = _mask_match_T_37; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_37 = |_mask_overlap_T_36; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_18_0 = _mask_overlap_T_37; // @[lsu.scala:263:49, :1084:62]
wire _T_913 = do_release_search_0 & ldq_18_valid & ldq_18_bits_addr_valid & block_addr_matches_18_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_942 = ldq_18_bits_executed | ldq_18_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_921 = ldq_18_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_925 = do_st_search_0 & ldq_18_valid & ldq_18_bits_addr_valid & (_T_942 | l_forwarders_18_0) & ~ldq_18_bits_addr_is_virtual & _T_921[0] & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_72 = l_forward_stq_idx_18 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_73 = l_forward_stq_idx_18 < ldq_18_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_74 = _forwarded_is_older_T_72 ^ _forwarded_is_older_T_73; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_75 = lcam_stq_idx_0 < ldq_18_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_18 = _forwarded_is_older_T_74 ^ _forwarded_is_older_T_75; // @[util.scala:363:{58,72,78}]
wire _T_929 = ~ldq_18_bits_forward_std_val | l_forward_stq_idx_18 != lcam_stq_idx_0 & forwarded_is_older_18; // @[util.scala:363:72]
wire _T_935 = do_ld_search_0 & ldq_18_valid & ldq_18_bits_addr_valid & ~ldq_18_bits_addr_is_virtual & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_72 = lcam_ldq_idx_0 < 5'h12; // @[util.scala:363:52]
wire _searcher_is_older_T_74 = _searcher_is_older_T_72 ^ _searcher_is_older_T_73; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_75 = ldq_head > 5'h12; // @[util.scala:363:78]
wire searcher_is_older_18 = _searcher_is_older_T_74 ^ _searcher_is_older_T_75; // @[util.scala:363:{58,72,78}]
wire _GEN_419 = _T_935 & searcher_is_older_18 & (_T_942 | l_forwarders_18_0) & ~s1_executing_loads_18 & ldq_18_bits_observed; // @[util.scala:363:72]
assign failed_loads_18 = ~_T_913 & (_T_925 ? _T_929 : _GEN_419); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_18; // @[lsu.scala:1129:57]
wire older_nacked_18 = nacking_loads_18 | older_nacked_REG_18; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_944 = ~_T_942 | older_nacked_18; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_420 = searcher_is_older_18 | _GEN_326; // @[util.scala:363:72]
wire _GEN_421 = _T_913 | _T_925; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_18; // @[lsu.scala:1132:58]
wire _GEN_422 = _GEN_421 | ~_T_935 | _GEN_420 | ~_T_944; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_19; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_285 = ldq_19_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_286 = ldq_19_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_287 = 15'h1 << _l_mask_mask_T_286; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_288 = ldq_19_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_289 = ldq_19_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_290 = {_l_mask_mask_T_289, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_291 = 15'h3 << _l_mask_mask_T_290; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_292 = ldq_19_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_293 = ldq_19_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_294 = _l_mask_mask_T_293 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_295 = &ldq_19_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_297 = _l_mask_mask_T_292 ? _l_mask_mask_T_294 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_298 = _l_mask_mask_T_288 ? _l_mask_mask_T_291 : {7'h0, _l_mask_mask_T_297}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_299 = _l_mask_mask_T_285 ? _l_mask_mask_T_287 : _l_mask_mask_T_298; // @[Mux.scala:126:16]
assign l_mask_19 = _l_mask_mask_T_299[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_38 = wb_forward_ldq_idx_0 == 5'h13; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_39 = wb_forward_valid_0 & _l_forwarders_T_38; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_19_0 = _l_forwarders_T_39; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_19 = l_forwarders_19_0 ? wb_forward_stq_idx_0 : ldq_19_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_58 = ldq_19_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_59 = _block_addr_matches_T_57 == _block_addr_matches_T_58; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_19_0 = _block_addr_matches_T_59; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_77 = ldq_19_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_78 = _dword_addr_matches_T_76 == _dword_addr_matches_T_77; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_79 = block_addr_matches_19_0 & _dword_addr_matches_T_78; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_19_0 = _dword_addr_matches_T_79; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_423 = l_mask_19 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_38; // @[lsu.scala:1083:46]
assign _mask_match_T_38 = _GEN_423; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_38; // @[lsu.scala:1084:46]
assign _mask_overlap_T_38 = _GEN_423; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_39 = _mask_match_T_38 == l_mask_19; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_19_0 = _mask_match_T_39; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_39 = |_mask_overlap_T_38; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_19_0 = _mask_overlap_T_39; // @[lsu.scala:263:49, :1084:62]
wire _T_949 = do_release_search_0 & ldq_19_valid & ldq_19_bits_addr_valid & block_addr_matches_19_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_978 = ldq_19_bits_executed | ldq_19_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_957 = ldq_19_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_961 = do_st_search_0 & ldq_19_valid & ldq_19_bits_addr_valid & (_T_978 | l_forwarders_19_0) & ~ldq_19_bits_addr_is_virtual & _T_957[0] & dword_addr_matches_19_0 & mask_overlap_19_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_76 = l_forward_stq_idx_19 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_77 = l_forward_stq_idx_19 < ldq_19_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_78 = _forwarded_is_older_T_76 ^ _forwarded_is_older_T_77; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_79 = lcam_stq_idx_0 < ldq_19_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_19 = _forwarded_is_older_T_78 ^ _forwarded_is_older_T_79; // @[util.scala:363:{58,72,78}]
wire _T_965 = ~ldq_19_bits_forward_std_val | l_forward_stq_idx_19 != lcam_stq_idx_0 & forwarded_is_older_19; // @[util.scala:363:72]
wire _T_971 = do_ld_search_0 & ldq_19_valid & ldq_19_bits_addr_valid & ~ldq_19_bits_addr_is_virtual & dword_addr_matches_19_0 & mask_overlap_19_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_76 = lcam_ldq_idx_0 < 5'h13; // @[util.scala:363:52]
wire _searcher_is_older_T_78 = _searcher_is_older_T_76 ^ _searcher_is_older_T_77; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_79 = ldq_head > 5'h13; // @[util.scala:363:78]
wire searcher_is_older_19 = _searcher_is_older_T_78 ^ _searcher_is_older_T_79; // @[util.scala:363:{58,72,78}]
wire _GEN_424 = _T_971 & searcher_is_older_19 & (_T_978 | l_forwarders_19_0) & ~s1_executing_loads_19 & ldq_19_bits_observed; // @[util.scala:363:72]
assign failed_loads_19 = ~_T_949 & (_T_961 ? _T_965 : _GEN_424); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_19; // @[lsu.scala:1129:57]
wire older_nacked_19 = nacking_loads_19 | older_nacked_REG_19; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_980 = ~_T_978 | older_nacked_19; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_425 = searcher_is_older_19 | _GEN_327; // @[util.scala:363:72]
wire _GEN_426 = _T_949 | _T_961; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_19; // @[lsu.scala:1132:58]
wire _GEN_427 = _GEN_426 | ~_T_971 | _GEN_425 | ~_T_980; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_20; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_300 = ldq_20_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_301 = ldq_20_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_302 = 15'h1 << _l_mask_mask_T_301; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_303 = ldq_20_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_304 = ldq_20_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_305 = {_l_mask_mask_T_304, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_306 = 15'h3 << _l_mask_mask_T_305; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_307 = ldq_20_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_308 = ldq_20_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_309 = _l_mask_mask_T_308 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_310 = &ldq_20_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_312 = _l_mask_mask_T_307 ? _l_mask_mask_T_309 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_313 = _l_mask_mask_T_303 ? _l_mask_mask_T_306 : {7'h0, _l_mask_mask_T_312}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_314 = _l_mask_mask_T_300 ? _l_mask_mask_T_302 : _l_mask_mask_T_313; // @[Mux.scala:126:16]
assign l_mask_20 = _l_mask_mask_T_314[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_40 = wb_forward_ldq_idx_0 == 5'h14; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_41 = wb_forward_valid_0 & _l_forwarders_T_40; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_20_0 = _l_forwarders_T_41; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_20 = l_forwarders_20_0 ? wb_forward_stq_idx_0 : ldq_20_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_61 = ldq_20_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_62 = _block_addr_matches_T_60 == _block_addr_matches_T_61; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_20_0 = _block_addr_matches_T_62; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_81 = ldq_20_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_82 = _dword_addr_matches_T_80 == _dword_addr_matches_T_81; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_83 = block_addr_matches_20_0 & _dword_addr_matches_T_82; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_20_0 = _dword_addr_matches_T_83; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_428 = l_mask_20 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_40; // @[lsu.scala:1083:46]
assign _mask_match_T_40 = _GEN_428; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_40; // @[lsu.scala:1084:46]
assign _mask_overlap_T_40 = _GEN_428; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_41 = _mask_match_T_40 == l_mask_20; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_20_0 = _mask_match_T_41; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_41 = |_mask_overlap_T_40; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_20_0 = _mask_overlap_T_41; // @[lsu.scala:263:49, :1084:62]
wire _T_985 = do_release_search_0 & ldq_20_valid & ldq_20_bits_addr_valid & block_addr_matches_20_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_1014 = ldq_20_bits_executed | ldq_20_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_993 = ldq_20_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_997 = do_st_search_0 & ldq_20_valid & ldq_20_bits_addr_valid & (_T_1014 | l_forwarders_20_0) & ~ldq_20_bits_addr_is_virtual & _T_993[0] & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_80 = l_forward_stq_idx_20 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_81 = l_forward_stq_idx_20 < ldq_20_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_82 = _forwarded_is_older_T_80 ^ _forwarded_is_older_T_81; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_83 = lcam_stq_idx_0 < ldq_20_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_20 = _forwarded_is_older_T_82 ^ _forwarded_is_older_T_83; // @[util.scala:363:{58,72,78}]
wire _T_1001 = ~ldq_20_bits_forward_std_val | l_forward_stq_idx_20 != lcam_stq_idx_0 & forwarded_is_older_20; // @[util.scala:363:72]
wire _T_1007 = do_ld_search_0 & ldq_20_valid & ldq_20_bits_addr_valid & ~ldq_20_bits_addr_is_virtual & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_80 = lcam_ldq_idx_0 < 5'h14; // @[util.scala:363:52]
wire _searcher_is_older_T_82 = _searcher_is_older_T_80 ^ _searcher_is_older_T_81; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_83 = ldq_head > 5'h14; // @[util.scala:363:78]
wire searcher_is_older_20 = _searcher_is_older_T_82 ^ _searcher_is_older_T_83; // @[util.scala:363:{58,72,78}]
wire _GEN_429 = _T_1007 & searcher_is_older_20 & (_T_1014 | l_forwarders_20_0) & ~s1_executing_loads_20 & ldq_20_bits_observed; // @[util.scala:363:72]
assign failed_loads_20 = ~_T_985 & (_T_997 ? _T_1001 : _GEN_429); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_20; // @[lsu.scala:1129:57]
wire older_nacked_20 = nacking_loads_20 | older_nacked_REG_20; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_1016 = ~_T_1014 | older_nacked_20; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_430 = searcher_is_older_20 | _GEN_328; // @[util.scala:363:72]
wire _GEN_431 = _T_985 | _T_997; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_20; // @[lsu.scala:1132:58]
wire _GEN_432 = _GEN_431 | ~_T_1007 | _GEN_430 | ~_T_1016; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_21; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_315 = ldq_21_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_316 = ldq_21_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_317 = 15'h1 << _l_mask_mask_T_316; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_318 = ldq_21_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_319 = ldq_21_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_320 = {_l_mask_mask_T_319, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_321 = 15'h3 << _l_mask_mask_T_320; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_322 = ldq_21_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_323 = ldq_21_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_324 = _l_mask_mask_T_323 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_325 = &ldq_21_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_327 = _l_mask_mask_T_322 ? _l_mask_mask_T_324 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_328 = _l_mask_mask_T_318 ? _l_mask_mask_T_321 : {7'h0, _l_mask_mask_T_327}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_329 = _l_mask_mask_T_315 ? _l_mask_mask_T_317 : _l_mask_mask_T_328; // @[Mux.scala:126:16]
assign l_mask_21 = _l_mask_mask_T_329[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_42 = wb_forward_ldq_idx_0 == 5'h15; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_43 = wb_forward_valid_0 & _l_forwarders_T_42; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_21_0 = _l_forwarders_T_43; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_21 = l_forwarders_21_0 ? wb_forward_stq_idx_0 : ldq_21_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_64 = ldq_21_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_65 = _block_addr_matches_T_63 == _block_addr_matches_T_64; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_21_0 = _block_addr_matches_T_65; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_85 = ldq_21_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_86 = _dword_addr_matches_T_84 == _dword_addr_matches_T_85; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_87 = block_addr_matches_21_0 & _dword_addr_matches_T_86; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_21_0 = _dword_addr_matches_T_87; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_433 = l_mask_21 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_42; // @[lsu.scala:1083:46]
assign _mask_match_T_42 = _GEN_433; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_42; // @[lsu.scala:1084:46]
assign _mask_overlap_T_42 = _GEN_433; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_43 = _mask_match_T_42 == l_mask_21; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_21_0 = _mask_match_T_43; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_43 = |_mask_overlap_T_42; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_21_0 = _mask_overlap_T_43; // @[lsu.scala:263:49, :1084:62]
wire _T_1021 = do_release_search_0 & ldq_21_valid & ldq_21_bits_addr_valid & block_addr_matches_21_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_1050 = ldq_21_bits_executed | ldq_21_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_1029 = ldq_21_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_1033 = do_st_search_0 & ldq_21_valid & ldq_21_bits_addr_valid & (_T_1050 | l_forwarders_21_0) & ~ldq_21_bits_addr_is_virtual & _T_1029[0] & dword_addr_matches_21_0 & mask_overlap_21_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_84 = l_forward_stq_idx_21 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_85 = l_forward_stq_idx_21 < ldq_21_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_86 = _forwarded_is_older_T_84 ^ _forwarded_is_older_T_85; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_87 = lcam_stq_idx_0 < ldq_21_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_21 = _forwarded_is_older_T_86 ^ _forwarded_is_older_T_87; // @[util.scala:363:{58,72,78}]
wire _T_1037 = ~ldq_21_bits_forward_std_val | l_forward_stq_idx_21 != lcam_stq_idx_0 & forwarded_is_older_21; // @[util.scala:363:72]
wire _T_1043 = do_ld_search_0 & ldq_21_valid & ldq_21_bits_addr_valid & ~ldq_21_bits_addr_is_virtual & dword_addr_matches_21_0 & mask_overlap_21_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_84 = lcam_ldq_idx_0 < 5'h15; // @[util.scala:363:52]
wire _searcher_is_older_T_86 = _searcher_is_older_T_84 ^ _searcher_is_older_T_85; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_87 = ldq_head > 5'h15; // @[util.scala:363:78]
wire searcher_is_older_21 = _searcher_is_older_T_86 ^ _searcher_is_older_T_87; // @[util.scala:363:{58,72,78}]
wire _GEN_434 = _T_1043 & searcher_is_older_21 & (_T_1050 | l_forwarders_21_0) & ~s1_executing_loads_21 & ldq_21_bits_observed; // @[util.scala:363:72]
assign failed_loads_21 = ~_T_1021 & (_T_1033 ? _T_1037 : _GEN_434); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_21; // @[lsu.scala:1129:57]
wire older_nacked_21 = nacking_loads_21 | older_nacked_REG_21; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_1052 = ~_T_1050 | older_nacked_21; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_435 = searcher_is_older_21 | _GEN_329; // @[util.scala:363:72]
wire _GEN_436 = _T_1021 | _T_1033; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_21; // @[lsu.scala:1132:58]
wire _GEN_437 = _GEN_436 | ~_T_1043 | _GEN_435 | ~_T_1052; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_22; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_330 = ldq_22_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_331 = ldq_22_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_332 = 15'h1 << _l_mask_mask_T_331; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_333 = ldq_22_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_334 = ldq_22_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_335 = {_l_mask_mask_T_334, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_336 = 15'h3 << _l_mask_mask_T_335; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_337 = ldq_22_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_338 = ldq_22_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_339 = _l_mask_mask_T_338 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_340 = &ldq_22_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_342 = _l_mask_mask_T_337 ? _l_mask_mask_T_339 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_343 = _l_mask_mask_T_333 ? _l_mask_mask_T_336 : {7'h0, _l_mask_mask_T_342}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_344 = _l_mask_mask_T_330 ? _l_mask_mask_T_332 : _l_mask_mask_T_343; // @[Mux.scala:126:16]
assign l_mask_22 = _l_mask_mask_T_344[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_44 = wb_forward_ldq_idx_0 == 5'h16; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_45 = wb_forward_valid_0 & _l_forwarders_T_44; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_22_0 = _l_forwarders_T_45; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_22 = l_forwarders_22_0 ? wb_forward_stq_idx_0 : ldq_22_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_67 = ldq_22_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_68 = _block_addr_matches_T_66 == _block_addr_matches_T_67; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_22_0 = _block_addr_matches_T_68; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_89 = ldq_22_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_90 = _dword_addr_matches_T_88 == _dword_addr_matches_T_89; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_91 = block_addr_matches_22_0 & _dword_addr_matches_T_90; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_22_0 = _dword_addr_matches_T_91; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_438 = l_mask_22 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_44; // @[lsu.scala:1083:46]
assign _mask_match_T_44 = _GEN_438; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_44; // @[lsu.scala:1084:46]
assign _mask_overlap_T_44 = _GEN_438; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_45 = _mask_match_T_44 == l_mask_22; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_22_0 = _mask_match_T_45; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_45 = |_mask_overlap_T_44; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_22_0 = _mask_overlap_T_45; // @[lsu.scala:263:49, :1084:62]
wire _T_1057 = do_release_search_0 & ldq_22_valid & ldq_22_bits_addr_valid & block_addr_matches_22_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_1086 = ldq_22_bits_executed | ldq_22_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_1065 = ldq_22_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_1069 = do_st_search_0 & ldq_22_valid & ldq_22_bits_addr_valid & (_T_1086 | l_forwarders_22_0) & ~ldq_22_bits_addr_is_virtual & _T_1065[0] & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_88 = l_forward_stq_idx_22 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_89 = l_forward_stq_idx_22 < ldq_22_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_90 = _forwarded_is_older_T_88 ^ _forwarded_is_older_T_89; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_91 = lcam_stq_idx_0 < ldq_22_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_22 = _forwarded_is_older_T_90 ^ _forwarded_is_older_T_91; // @[util.scala:363:{58,72,78}]
wire _T_1073 = ~ldq_22_bits_forward_std_val | l_forward_stq_idx_22 != lcam_stq_idx_0 & forwarded_is_older_22; // @[util.scala:363:72]
wire _T_1079 = do_ld_search_0 & ldq_22_valid & ldq_22_bits_addr_valid & ~ldq_22_bits_addr_is_virtual & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_88 = lcam_ldq_idx_0 < 5'h16; // @[util.scala:363:52]
wire _searcher_is_older_T_90 = _searcher_is_older_T_88 ^ _searcher_is_older_T_89; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_91 = ldq_head > 5'h16; // @[util.scala:363:78]
wire searcher_is_older_22 = _searcher_is_older_T_90 ^ _searcher_is_older_T_91; // @[util.scala:363:{58,72,78}]
wire _GEN_439 = _T_1079 & searcher_is_older_22 & (_T_1086 | l_forwarders_22_0) & ~s1_executing_loads_22 & ldq_22_bits_observed; // @[util.scala:363:72]
assign failed_loads_22 = ~_T_1057 & (_T_1069 ? _T_1073 : _GEN_439); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_22; // @[lsu.scala:1129:57]
wire older_nacked_22 = nacking_loads_22 | older_nacked_REG_22; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_1088 = ~_T_1086 | older_nacked_22; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_440 = searcher_is_older_22 | _GEN_330; // @[util.scala:363:72]
wire _GEN_441 = _T_1057 | _T_1069; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
reg io_dmem_s1_kill_0_REG_22; // @[lsu.scala:1132:58]
wire _GEN_442 = _GEN_441 | ~_T_1079 | _GEN_440 | ~_T_1088; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire [7:0] l_mask_23; // @[lsu.scala:1665:22]
wire _l_mask_mask_T_345 = ldq_23_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26]
wire [2:0] _l_mask_mask_T_346 = ldq_23_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55]
wire [14:0] _l_mask_mask_T_347 = 15'h1 << _l_mask_mask_T_346; // @[lsu.scala:1667:{48,55}]
wire _l_mask_mask_T_348 = ldq_23_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26]
wire [1:0] _l_mask_mask_T_349 = ldq_23_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56]
wire [2:0] _l_mask_mask_T_350 = {_l_mask_mask_T_349, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _l_mask_mask_T_351 = 15'h3 << _l_mask_mask_T_350; // @[lsu.scala:1668:{48,62}]
wire _l_mask_mask_T_352 = ldq_23_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26]
wire _l_mask_mask_T_353 = ldq_23_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46]
wire [7:0] _l_mask_mask_T_354 = _l_mask_mask_T_353 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _l_mask_mask_T_355 = &ldq_23_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26]
wire [7:0] _l_mask_mask_T_357 = _l_mask_mask_T_352 ? _l_mask_mask_T_354 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_358 = _l_mask_mask_T_348 ? _l_mask_mask_T_351 : {7'h0, _l_mask_mask_T_357}; // @[Mux.scala:126:16]
wire [14:0] _l_mask_mask_T_359 = _l_mask_mask_T_345 ? _l_mask_mask_T_347 : _l_mask_mask_T_358; // @[Mux.scala:126:16]
assign l_mask_23 = _l_mask_mask_T_359[7:0]; // @[Mux.scala:126:16]
wire _l_forwarders_T_46 = wb_forward_ldq_idx_0 == 5'h17; // @[lsu.scala:1066:36, :1076:88]
wire _l_forwarders_T_47 = wb_forward_valid_0 & _l_forwarders_T_46; // @[lsu.scala:1065:36, :1076:{63,88}]
wire l_forwarders_23_0 = _l_forwarders_T_47; // @[lsu.scala:263:49, :1076:63]
wire [4:0] l_forward_stq_idx_23 = l_forwarders_23_0 ? wb_forward_stq_idx_0 : ldq_23_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32]
wire [33:0] _block_addr_matches_T_70 = ldq_23_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84]
wire _block_addr_matches_T_71 = _block_addr_matches_T_69 == _block_addr_matches_T_70; // @[lsu.scala:1081:{57,73,84}]
wire block_addr_matches_23_0 = _block_addr_matches_T_71; // @[lsu.scala:263:49, :1081:73]
wire [2:0] _dword_addr_matches_T_93 = ldq_23_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110]
wire _dword_addr_matches_T_94 = _dword_addr_matches_T_92 == _dword_addr_matches_T_93; // @[lsu.scala:1082:{81,100,110}]
wire _dword_addr_matches_T_95 = block_addr_matches_23_0 & _dword_addr_matches_T_94; // @[lsu.scala:263:49, :1082:{66,100}]
wire dword_addr_matches_23_0 = _dword_addr_matches_T_95; // @[lsu.scala:263:49, :1082:66]
wire [7:0] _GEN_443 = l_mask_23 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22]
wire [7:0] _mask_match_T_46; // @[lsu.scala:1083:46]
assign _mask_match_T_46 = _GEN_443; // @[lsu.scala:1083:46]
wire [7:0] _mask_overlap_T_46; // @[lsu.scala:1084:46]
assign _mask_overlap_T_46 = _GEN_443; // @[lsu.scala:1083:46, :1084:46]
wire _mask_match_T_47 = _mask_match_T_46 == l_mask_23; // @[lsu.scala:1083:{46,62}, :1665:22]
wire mask_match_23_0 = _mask_match_T_47; // @[lsu.scala:263:49, :1083:62]
wire _mask_overlap_T_47 = |_mask_overlap_T_46; // @[lsu.scala:1084:{46,62}]
wire mask_overlap_23_0 = _mask_overlap_T_47; // @[lsu.scala:263:49, :1084:62]
wire _T_1093 = do_release_search_0 & ldq_23_valid & ldq_23_bits_addr_valid & block_addr_matches_23_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34]
wire _T_1122 = ldq_23_bits_executed | ldq_23_bits_succeeded; // @[lsu.scala:208:16, :1099:37]
wire [23:0] _T_1101 = ldq_23_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38]
wire _T_1105 = do_st_search_0 & ldq_23_valid & ldq_23_bits_addr_valid & (_T_1122 | l_forwarders_23_0) & ~ldq_23_bits_addr_is_virtual & _T_1101[0] & dword_addr_matches_23_0 & mask_overlap_23_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131]
wire _forwarded_is_older_T_92 = l_forward_stq_idx_23 < lcam_stq_idx_0; // @[util.scala:363:52]
wire _forwarded_is_older_T_93 = l_forward_stq_idx_23 < ldq_23_bits_youngest_stq_idx; // @[util.scala:363:64]
wire _forwarded_is_older_T_94 = _forwarded_is_older_T_92 ^ _forwarded_is_older_T_93; // @[util.scala:363:{52,58,64}]
wire _forwarded_is_older_T_95 = lcam_stq_idx_0 < ldq_23_bits_youngest_stq_idx; // @[util.scala:363:78]
wire forwarded_is_older_23 = _forwarded_is_older_T_94 ^ _forwarded_is_older_T_95; // @[util.scala:363:{58,72,78}]
wire _T_1109 = ~ldq_23_bits_forward_std_val | l_forward_stq_idx_23 != lcam_stq_idx_0 & forwarded_is_older_23; // @[util.scala:363:72]
wire _T_1115 = do_ld_search_0 & ldq_23_valid & ldq_23_bits_addr_valid & ~ldq_23_bits_addr_is_virtual & dword_addr_matches_23_0 & mask_overlap_23_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47]
wire _searcher_is_older_T_92 = lcam_ldq_idx_0 < 5'h17; // @[util.scala:363:52]
wire _searcher_is_older_T_94 = _searcher_is_older_T_92 ^ _searcher_is_older_T_93; // @[util.scala:363:{52,58,64}]
wire _searcher_is_older_T_95 = ldq_head > 5'h17; // @[util.scala:363:78]
wire searcher_is_older_23 = _searcher_is_older_T_94 ^ _searcher_is_older_T_95; // @[util.scala:363:{58,72,78}]
wire _GEN_444 = _T_1115 & searcher_is_older_23 & (_T_1122 | l_forwarders_23_0) & ~s1_executing_loads_23 & ldq_23_bits_observed; // @[util.scala:363:72]
assign failed_loads_23 = ~_T_1093 & (_T_1105 ? _T_1109 : _GEN_444); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36]
reg older_nacked_REG_23; // @[lsu.scala:1129:57]
wire older_nacked_23 = nacking_loads_23 | older_nacked_REG_23; // @[lsu.scala:1055:34, :1129:{47,57}]
wire _T_1124 = ~_T_1122 | older_nacked_23; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}]
wire _GEN_445 = searcher_is_older_23 | _GEN_331; // @[util.scala:363:72]
wire _GEN_446 = _T_1093 | _T_1105; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37]
wire _GEN_447 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _searcher_is_older_T_4)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _searcher_is_older_T_4)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _searcher_is_older_T_4)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _searcher_is_older_T_4)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _searcher_is_older_T_4)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _searcher_is_older_T_4)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _searcher_is_older_T_4)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _searcher_is_older_T_4)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _searcher_is_older_T_4)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _searcher_is_older_T_4)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _searcher_is_older_T_4)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _searcher_is_older_T_4)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _searcher_is_older_T_4)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _searcher_is_older_T_4)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _searcher_is_older_T_4)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _searcher_is_older_T_4)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _searcher_is_older_T_4)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _searcher_is_older_T_4)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _searcher_is_older_T_4)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _searcher_is_older_T_4)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _searcher_is_older_T_4)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _searcher_is_older_T_4)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _searcher_is_older_T_4)) & s1_executing_loads_0; // @[util.scala:363:52]
wire _GEN_448 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_309)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_309)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_309)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_309)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_309)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_309)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_309)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_309)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_309)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_309)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_309)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_309)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_309)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_309)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_309)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_309)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_309)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_309)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_309)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_309)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_309)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_309)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_309)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_309)) & s1_executing_loads_1; // @[util.scala:363:72]
wire _GEN_449 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_310)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_310)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_310)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_310)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_310)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_310)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_310)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_310)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_310)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_310)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_310)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_310)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_310)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_310)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_310)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_310)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_310)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_310)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_310)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_310)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_310)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_310)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_310)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_310)) & s1_executing_loads_2; // @[util.scala:363:72]
wire _GEN_450 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_311)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_311)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_311)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_311)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_311)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_311)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_311)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_311)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_311)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_311)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_311)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_311)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_311)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_311)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_311)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_311)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_311)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_311)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_311)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_311)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_311)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_311)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_311)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_311)) & s1_executing_loads_3; // @[util.scala:363:72]
wire _GEN_451 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_312)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_312)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_312)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_312)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_312)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_312)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_312)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_312)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_312)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_312)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_312)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_312)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_312)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_312)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_312)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_312)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_312)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_312)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_312)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_312)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_312)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_312)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_312)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_312)) & s1_executing_loads_4; // @[util.scala:363:72]
wire _GEN_452 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_313)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_313)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_313)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_313)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_313)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_313)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_313)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_313)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_313)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_313)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_313)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_313)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_313)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_313)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_313)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_313)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_313)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_313)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_313)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_313)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_313)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_313)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_313)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_313)) & s1_executing_loads_5; // @[util.scala:363:72]
wire _GEN_453 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_314)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_314)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_314)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_314)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_314)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_314)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_314)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_314)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_314)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_314)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_314)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_314)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_314)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_314)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_314)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_314)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_314)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_314)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_314)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_314)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_314)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_314)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_314)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_314)) & s1_executing_loads_6; // @[util.scala:363:72]
wire _GEN_454 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_315)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_315)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_315)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_315)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_315)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_315)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_315)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_315)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_315)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_315)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_315)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_315)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_315)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_315)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_315)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_315)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_315)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_315)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_315)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_315)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_315)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_315)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_315)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_315)) & s1_executing_loads_7; // @[util.scala:363:72]
wire _GEN_455 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_316)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_316)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_316)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_316)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_316)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_316)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_316)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_316)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_316)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_316)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_316)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_316)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_316)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_316)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_316)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_316)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_316)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_316)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_316)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_316)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_316)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_316)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_316)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_316)) & s1_executing_loads_8; // @[util.scala:363:72]
wire _GEN_456 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_317)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_317)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_317)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_317)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_317)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_317)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_317)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_317)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_317)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_317)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_317)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_317)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_317)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_317)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_317)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_317)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_317)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_317)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_317)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_317)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_317)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_317)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_317)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_317)) & s1_executing_loads_9; // @[util.scala:363:72]
wire _GEN_457 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_318)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_318)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_318)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_318)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_318)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_318)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_318)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_318)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_318)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_318)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_318)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_318)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_318)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_318)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_318)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_318)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_318)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_318)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_318)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_318)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_318)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_318)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_318)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_318)) & s1_executing_loads_10; // @[util.scala:363:72]
wire _GEN_458 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_319)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_319)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_319)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_319)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_319)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_319)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_319)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_319)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_319)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_319)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_319)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_319)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_319)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_319)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_319)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_319)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_319)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_319)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_319)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_319)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_319)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_319)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_319)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_319)) & s1_executing_loads_11; // @[util.scala:363:72]
wire _GEN_459 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_320)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_320)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_320)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_320)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_320)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_320)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_320)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_320)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_320)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_320)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_320)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_320)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_320)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_320)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_320)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_320)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_320)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_320)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_320)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_320)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_320)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_320)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_320)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_320)) & s1_executing_loads_12; // @[util.scala:363:72]
wire _GEN_460 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_321)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_321)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_321)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_321)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_321)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_321)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_321)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_321)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_321)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_321)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_321)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_321)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_321)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_321)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_321)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_321)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_321)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_321)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_321)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_321)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_321)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_321)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_321)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_321)) & s1_executing_loads_13; // @[util.scala:363:72]
wire _GEN_461 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_322)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_322)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_322)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_322)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_322)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_322)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_322)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_322)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_322)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_322)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_322)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_322)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_322)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_322)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_322)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_322)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_322)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_322)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_322)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_322)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_322)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_322)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_322)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_322)) & s1_executing_loads_14; // @[util.scala:363:72]
wire _GEN_462 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_323)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_323)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_323)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_323)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_323)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_323)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_323)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_323)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_323)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_323)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_323)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_323)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_323)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_323)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_323)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_323)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_323)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_323)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_323)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_323)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_323)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_323)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_323)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_323)) & s1_executing_loads_15; // @[util.scala:363:72]
wire _GEN_463 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_324)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_324)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_324)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_324)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_324)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_324)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_324)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_324)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_324)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_324)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_324)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_324)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_324)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_324)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_324)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_324)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_324)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_324)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_324)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_324)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_324)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_324)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_324)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_324)) & s1_executing_loads_16; // @[util.scala:363:72]
wire _GEN_464 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_325)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_325)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_325)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_325)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_325)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_325)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_325)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_325)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_325)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_325)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_325)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_325)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_325)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_325)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_325)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_325)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_325)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_325)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_325)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_325)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_325)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_325)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_325)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_325)) & s1_executing_loads_17; // @[util.scala:363:72]
wire _GEN_465 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_326)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_326)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_326)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_326)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_326)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_326)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_326)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_326)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_326)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_326)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_326)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_326)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_326)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_326)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_326)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_326)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_326)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_326)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_326)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_326)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_326)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_326)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_326)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_326)) & s1_executing_loads_18; // @[util.scala:363:72]
wire _GEN_466 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_327)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_327)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_327)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_327)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_327)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_327)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_327)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_327)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_327)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_327)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_327)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_327)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_327)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_327)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_327)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_327)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_327)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_327)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_327)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_327)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_327)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_327)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_327)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_327)) & s1_executing_loads_19; // @[util.scala:363:72]
wire _GEN_467 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_328)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_328)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_328)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_328)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_328)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_328)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_328)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_328)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_328)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_328)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_328)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_328)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_328)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_328)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_328)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_328)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_328)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_328)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_328)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_328)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_328)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_328)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_328)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_328)) & s1_executing_loads_20; // @[util.scala:363:72]
wire _GEN_468 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_329)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_329)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_329)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_329)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_329)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_329)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_329)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_329)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_329)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_329)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_329)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_329)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_329)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_329)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_329)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_329)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_329)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_329)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_329)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_329)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_329)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_329)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_329)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_329)) & s1_executing_loads_21; // @[util.scala:363:72]
wire _GEN_469 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_330)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_330)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_330)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_330)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_330)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_330)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_330)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_330)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_330)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_330)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_330)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_330)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_330)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_330)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_330)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_330)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_330)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_330)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_330)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_330)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_330)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_330)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_330)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_330)) & s1_executing_loads_22; // @[util.scala:363:72]
wire _GEN_470 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_331)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_331)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_331)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_331)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_331)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_331)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_331)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_331)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_331)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_331)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_331)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_331)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_331)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_331)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_331)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_331)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_331)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_331)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_331)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_331)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_331)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_331)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_331)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_331)) & s1_executing_loads_23; // @[util.scala:363:72]
reg io_dmem_s1_kill_0_REG_23; // @[lsu.scala:1132:58]
wire _GEN_471 = _GEN_446 | ~_T_1115 | _GEN_445 | ~_T_1124; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}]
wire _GEN_472 = _GEN_471 ? (_GEN_442 ? (_GEN_437 ? (_GEN_432 ? (_GEN_427 ? (_GEN_422 ? (_GEN_417 ? (_GEN_412 ? (_GEN_407 ? (_GEN_402 ? (_GEN_397 ? (_GEN_392 ? (_GEN_387 ? (_GEN_382 ? (_GEN_377 ? (_GEN_372 ? (_GEN_367 ? (_GEN_362 ? (_GEN_357 ? (_GEN_352 ? (_GEN_347 ? (_GEN_342 ? (_GEN_337 ? ~_GEN_308 & _T_287 & ~searcher_is_older & _GEN_332 & io_dmem_s1_kill_0_REG : io_dmem_s1_kill_0_REG_1) : io_dmem_s1_kill_0_REG_2) : io_dmem_s1_kill_0_REG_3) : io_dmem_s1_kill_0_REG_4) : io_dmem_s1_kill_0_REG_5) : io_dmem_s1_kill_0_REG_6) : io_dmem_s1_kill_0_REG_7) : io_dmem_s1_kill_0_REG_8) : io_dmem_s1_kill_0_REG_9) : io_dmem_s1_kill_0_REG_10) : io_dmem_s1_kill_0_REG_11) : io_dmem_s1_kill_0_REG_12) : io_dmem_s1_kill_0_REG_13) : io_dmem_s1_kill_0_REG_14) : io_dmem_s1_kill_0_REG_15) : io_dmem_s1_kill_0_REG_16) : io_dmem_s1_kill_0_REG_17) : io_dmem_s1_kill_0_REG_18) : io_dmem_s1_kill_0_REG_19) : io_dmem_s1_kill_0_REG_20) : io_dmem_s1_kill_0_REG_21) : io_dmem_s1_kill_0_REG_22) : io_dmem_s1_kill_0_REG_23; // @[util.scala:363:72]
assign can_forward_0 = _GEN_471 & _GEN_442 & _GEN_437 & _GEN_432 & _GEN_427 & _GEN_422 & _GEN_417 & _GEN_412 & _GEN_407 & _GEN_402 & _GEN_397 & _GEN_392 & _GEN_387 & _GEN_382 & _GEN_377 & _GEN_372 & _GEN_367 & _GEN_362 & _GEN_357 & _GEN_352 & _GEN_347 & _GEN_342 & _GEN_337 & (_GEN_308 | ~_T_287 | searcher_is_older | ~_GEN_332) & _can_forward_WIRE_0; // @[util.scala:363:72]
wire _dword_addr_matches_T_96 = ~stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_97 = stq_0_bits_addr_valid & _dword_addr_matches_T_96; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_98 = stq_0_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire [28:0] _dword_addr_matches_T_99 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_105 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_111 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_117 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_123 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_129 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_135 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_141 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_147 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_153 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_159 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_165 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_171 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_177 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_183 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_189 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_195 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_201 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_207 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_213 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_219 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_225 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_231 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire [28:0] _dword_addr_matches_T_237 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74]
wire _dword_addr_matches_T_100 = _dword_addr_matches_T_98 == _dword_addr_matches_T_99; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_101 = _dword_addr_matches_T_97 & _dword_addr_matches_T_100; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_24_0 = _dword_addr_matches_T_101; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask; // @[lsu.scala:1665:22]
wire _write_mask_mask_T = stq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_1 = stq_0_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_3 = stq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_4 = stq_0_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_7 = stq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_8 = stq_0_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_10 = &stq_0_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16]
assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16]
wire _T_1129 = do_ld_search_0 & stq_0_valid & lcam_st_dep_mask_0[0]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1140 = lcam_mask_0 & write_mask; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1137 = _T_1140 == lcam_mask_0 & ~stq_0_bits_uop_is_fence & ~stq_0_bits_uop_is_amo & dword_addr_matches_24_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_0 = _T_1129 & _T_1137; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_24; // @[lsu.scala:1154:56]
wire _T_1142 = (|_T_1140) & dword_addr_matches_24_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_25; // @[lsu.scala:1160:56]
wire _T_1145 = stq_0_bits_uop_is_fence | stq_0_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_0 = _T_1129 & (_T_1137 | _T_1142 | _T_1145); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_26; // @[lsu.scala:1166:56]
wire _GEN_473 = _T_1129 ? (_T_1137 ? io_dmem_s1_kill_0_REG_24 : _T_1142 ? io_dmem_s1_kill_0_REG_25 : _T_1145 ? io_dmem_s1_kill_0_REG_26 : _GEN_472) : _GEN_472; // @[lsu.scala:1092:36, :1103:37, :1117:37, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_474 = _T_1137 | _T_1142; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_475 = _T_1129 ? (_GEN_474 ? ~_searcher_is_older_T_4 & _GEN_447 : ~(_T_1145 & _searcher_is_older_T_4) & _GEN_447) : _GEN_447; // @[util.scala:363:52]
wire _GEN_476 = _T_1129 ? (_GEN_474 ? ~_GEN_309 & _GEN_448 : ~(_T_1145 & _GEN_309) & _GEN_448) : _GEN_448; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_477 = _T_1129 ? (_GEN_474 ? ~_GEN_310 & _GEN_449 : ~(_T_1145 & _GEN_310) & _GEN_449) : _GEN_449; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_478 = _T_1129 ? (_GEN_474 ? ~_GEN_311 & _GEN_450 : ~(_T_1145 & _GEN_311) & _GEN_450) : _GEN_450; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_479 = _T_1129 ? (_GEN_474 ? ~_GEN_312 & _GEN_451 : ~(_T_1145 & _GEN_312) & _GEN_451) : _GEN_451; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_480 = _T_1129 ? (_GEN_474 ? ~_GEN_313 & _GEN_452 : ~(_T_1145 & _GEN_313) & _GEN_452) : _GEN_452; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_481 = _T_1129 ? (_GEN_474 ? ~_GEN_314 & _GEN_453 : ~(_T_1145 & _GEN_314) & _GEN_453) : _GEN_453; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_482 = _T_1129 ? (_GEN_474 ? ~_GEN_315 & _GEN_454 : ~(_T_1145 & _GEN_315) & _GEN_454) : _GEN_454; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_483 = _T_1129 ? (_GEN_474 ? ~_GEN_316 & _GEN_455 : ~(_T_1145 & _GEN_316) & _GEN_455) : _GEN_455; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_484 = _T_1129 ? (_GEN_474 ? ~_GEN_317 & _GEN_456 : ~(_T_1145 & _GEN_317) & _GEN_456) : _GEN_456; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_485 = _T_1129 ? (_GEN_474 ? ~_GEN_318 & _GEN_457 : ~(_T_1145 & _GEN_318) & _GEN_457) : _GEN_457; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_486 = _T_1129 ? (_GEN_474 ? ~_GEN_319 & _GEN_458 : ~(_T_1145 & _GEN_319) & _GEN_458) : _GEN_458; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_487 = _T_1129 ? (_GEN_474 ? ~_GEN_320 & _GEN_459 : ~(_T_1145 & _GEN_320) & _GEN_459) : _GEN_459; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_488 = _T_1129 ? (_GEN_474 ? ~_GEN_321 & _GEN_460 : ~(_T_1145 & _GEN_321) & _GEN_460) : _GEN_460; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_489 = _T_1129 ? (_GEN_474 ? ~_GEN_322 & _GEN_461 : ~(_T_1145 & _GEN_322) & _GEN_461) : _GEN_461; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_490 = _T_1129 ? (_GEN_474 ? ~_GEN_323 & _GEN_462 : ~(_T_1145 & _GEN_323) & _GEN_462) : _GEN_462; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_491 = _T_1129 ? (_GEN_474 ? ~_GEN_324 & _GEN_463 : ~(_T_1145 & _GEN_324) & _GEN_463) : _GEN_463; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_492 = _T_1129 ? (_GEN_474 ? ~_GEN_325 & _GEN_464 : ~(_T_1145 & _GEN_325) & _GEN_464) : _GEN_464; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_493 = _T_1129 ? (_GEN_474 ? ~_GEN_326 & _GEN_465 : ~(_T_1145 & _GEN_326) & _GEN_465) : _GEN_465; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_494 = _T_1129 ? (_GEN_474 ? ~_GEN_327 & _GEN_466 : ~(_T_1145 & _GEN_327) & _GEN_466) : _GEN_466; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_495 = _T_1129 ? (_GEN_474 ? ~_GEN_328 & _GEN_467 : ~(_T_1145 & _GEN_328) & _GEN_467) : _GEN_467; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_496 = _T_1129 ? (_GEN_474 ? ~_GEN_329 & _GEN_468 : ~(_T_1145 & _GEN_329) & _GEN_468) : _GEN_468; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_497 = _T_1129 ? (_GEN_474 ? ~_GEN_330 & _GEN_469 : ~(_T_1145 & _GEN_330) & _GEN_469) : _GEN_469; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_498 = _T_1129 ? (_GEN_474 ? ~_GEN_331 & _GEN_470 : ~(_T_1145 & _GEN_331) & _GEN_470) : _GEN_470; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_102 = ~stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_103 = stq_1_bits_addr_valid & _dword_addr_matches_T_102; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_104 = stq_1_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_106 = _dword_addr_matches_T_104 == _dword_addr_matches_T_105; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_107 = _dword_addr_matches_T_103 & _dword_addr_matches_T_106; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_25_0 = _dword_addr_matches_T_107; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_1; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_15 = stq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_16 = stq_1_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_18 = stq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_19 = stq_1_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_22 = stq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_23 = stq_1_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_25 = &stq_1_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16]
assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16]
wire _T_1150 = do_ld_search_0 & stq_1_valid & lcam_st_dep_mask_0[1]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1161 = lcam_mask_0 & write_mask_1; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1158 = _T_1161 == lcam_mask_0 & ~stq_1_bits_uop_is_fence & ~stq_1_bits_uop_is_amo & dword_addr_matches_25_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_1 = _T_1150 & _T_1158; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_27; // @[lsu.scala:1154:56]
wire _T_1163 = (|_T_1161) & dword_addr_matches_25_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_28; // @[lsu.scala:1160:56]
wire _T_1166 = stq_1_bits_uop_is_fence | stq_1_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_1 = _T_1150 & (_T_1158 | _T_1163 | _T_1166); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_29; // @[lsu.scala:1166:56]
wire _GEN_499 = _T_1150 ? (_T_1158 ? io_dmem_s1_kill_0_REG_27 : _T_1163 ? io_dmem_s1_kill_0_REG_28 : _T_1166 ? io_dmem_s1_kill_0_REG_29 : _GEN_473) : _GEN_473; // @[lsu.scala:1092:36, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_500 = _T_1158 | _T_1163; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_501 = _T_1150 ? (_GEN_500 ? ~_searcher_is_older_T_4 & _GEN_475 : ~(_T_1166 & _searcher_is_older_T_4) & _GEN_475) : _GEN_475; // @[util.scala:363:52]
wire _GEN_502 = _T_1150 ? (_GEN_500 ? ~_GEN_309 & _GEN_476 : ~(_T_1166 & _GEN_309) & _GEN_476) : _GEN_476; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_503 = _T_1150 ? (_GEN_500 ? ~_GEN_310 & _GEN_477 : ~(_T_1166 & _GEN_310) & _GEN_477) : _GEN_477; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_504 = _T_1150 ? (_GEN_500 ? ~_GEN_311 & _GEN_478 : ~(_T_1166 & _GEN_311) & _GEN_478) : _GEN_478; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_505 = _T_1150 ? (_GEN_500 ? ~_GEN_312 & _GEN_479 : ~(_T_1166 & _GEN_312) & _GEN_479) : _GEN_479; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_506 = _T_1150 ? (_GEN_500 ? ~_GEN_313 & _GEN_480 : ~(_T_1166 & _GEN_313) & _GEN_480) : _GEN_480; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_507 = _T_1150 ? (_GEN_500 ? ~_GEN_314 & _GEN_481 : ~(_T_1166 & _GEN_314) & _GEN_481) : _GEN_481; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_508 = _T_1150 ? (_GEN_500 ? ~_GEN_315 & _GEN_482 : ~(_T_1166 & _GEN_315) & _GEN_482) : _GEN_482; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_509 = _T_1150 ? (_GEN_500 ? ~_GEN_316 & _GEN_483 : ~(_T_1166 & _GEN_316) & _GEN_483) : _GEN_483; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_510 = _T_1150 ? (_GEN_500 ? ~_GEN_317 & _GEN_484 : ~(_T_1166 & _GEN_317) & _GEN_484) : _GEN_484; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_511 = _T_1150 ? (_GEN_500 ? ~_GEN_318 & _GEN_485 : ~(_T_1166 & _GEN_318) & _GEN_485) : _GEN_485; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_512 = _T_1150 ? (_GEN_500 ? ~_GEN_319 & _GEN_486 : ~(_T_1166 & _GEN_319) & _GEN_486) : _GEN_486; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_513 = _T_1150 ? (_GEN_500 ? ~_GEN_320 & _GEN_487 : ~(_T_1166 & _GEN_320) & _GEN_487) : _GEN_487; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_514 = _T_1150 ? (_GEN_500 ? ~_GEN_321 & _GEN_488 : ~(_T_1166 & _GEN_321) & _GEN_488) : _GEN_488; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_515 = _T_1150 ? (_GEN_500 ? ~_GEN_322 & _GEN_489 : ~(_T_1166 & _GEN_322) & _GEN_489) : _GEN_489; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_516 = _T_1150 ? (_GEN_500 ? ~_GEN_323 & _GEN_490 : ~(_T_1166 & _GEN_323) & _GEN_490) : _GEN_490; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_517 = _T_1150 ? (_GEN_500 ? ~_GEN_324 & _GEN_491 : ~(_T_1166 & _GEN_324) & _GEN_491) : _GEN_491; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_518 = _T_1150 ? (_GEN_500 ? ~_GEN_325 & _GEN_492 : ~(_T_1166 & _GEN_325) & _GEN_492) : _GEN_492; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_519 = _T_1150 ? (_GEN_500 ? ~_GEN_326 & _GEN_493 : ~(_T_1166 & _GEN_326) & _GEN_493) : _GEN_493; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_520 = _T_1150 ? (_GEN_500 ? ~_GEN_327 & _GEN_494 : ~(_T_1166 & _GEN_327) & _GEN_494) : _GEN_494; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_521 = _T_1150 ? (_GEN_500 ? ~_GEN_328 & _GEN_495 : ~(_T_1166 & _GEN_328) & _GEN_495) : _GEN_495; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_522 = _T_1150 ? (_GEN_500 ? ~_GEN_329 & _GEN_496 : ~(_T_1166 & _GEN_329) & _GEN_496) : _GEN_496; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_523 = _T_1150 ? (_GEN_500 ? ~_GEN_330 & _GEN_497 : ~(_T_1166 & _GEN_330) & _GEN_497) : _GEN_497; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_524 = _T_1150 ? (_GEN_500 ? ~_GEN_331 & _GEN_498 : ~(_T_1166 & _GEN_331) & _GEN_498) : _GEN_498; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_108 = ~stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_109 = stq_2_bits_addr_valid & _dword_addr_matches_T_108; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_110 = stq_2_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_112 = _dword_addr_matches_T_110 == _dword_addr_matches_T_111; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_113 = _dword_addr_matches_T_109 & _dword_addr_matches_T_112; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_26_0 = _dword_addr_matches_T_113; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_2; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_30 = stq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_31 = stq_2_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_33 = stq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_34 = stq_2_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_37 = stq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_38 = stq_2_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_40 = &stq_2_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16]
assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16]
wire _T_1171 = do_ld_search_0 & stq_2_valid & lcam_st_dep_mask_0[2]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1182 = lcam_mask_0 & write_mask_2; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1179 = _T_1182 == lcam_mask_0 & ~stq_2_bits_uop_is_fence & ~stq_2_bits_uop_is_amo & dword_addr_matches_26_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_2 = _T_1171 & _T_1179; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_30; // @[lsu.scala:1154:56]
wire _T_1184 = (|_T_1182) & dword_addr_matches_26_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_31; // @[lsu.scala:1160:56]
wire _T_1187 = stq_2_bits_uop_is_fence | stq_2_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_2 = _T_1171 & (_T_1179 | _T_1184 | _T_1187); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_32; // @[lsu.scala:1166:56]
wire _GEN_525 = _T_1171 ? (_T_1179 ? io_dmem_s1_kill_0_REG_30 : _T_1184 ? io_dmem_s1_kill_0_REG_31 : _T_1187 ? io_dmem_s1_kill_0_REG_32 : _GEN_499) : _GEN_499; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_526 = _T_1179 | _T_1184; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_527 = _T_1171 ? (_GEN_526 ? ~_searcher_is_older_T_4 & _GEN_501 : ~(_T_1187 & _searcher_is_older_T_4) & _GEN_501) : _GEN_501; // @[util.scala:363:52]
wire _GEN_528 = _T_1171 ? (_GEN_526 ? ~_GEN_309 & _GEN_502 : ~(_T_1187 & _GEN_309) & _GEN_502) : _GEN_502; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_529 = _T_1171 ? (_GEN_526 ? ~_GEN_310 & _GEN_503 : ~(_T_1187 & _GEN_310) & _GEN_503) : _GEN_503; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_530 = _T_1171 ? (_GEN_526 ? ~_GEN_311 & _GEN_504 : ~(_T_1187 & _GEN_311) & _GEN_504) : _GEN_504; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_531 = _T_1171 ? (_GEN_526 ? ~_GEN_312 & _GEN_505 : ~(_T_1187 & _GEN_312) & _GEN_505) : _GEN_505; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_532 = _T_1171 ? (_GEN_526 ? ~_GEN_313 & _GEN_506 : ~(_T_1187 & _GEN_313) & _GEN_506) : _GEN_506; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_533 = _T_1171 ? (_GEN_526 ? ~_GEN_314 & _GEN_507 : ~(_T_1187 & _GEN_314) & _GEN_507) : _GEN_507; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_534 = _T_1171 ? (_GEN_526 ? ~_GEN_315 & _GEN_508 : ~(_T_1187 & _GEN_315) & _GEN_508) : _GEN_508; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_535 = _T_1171 ? (_GEN_526 ? ~_GEN_316 & _GEN_509 : ~(_T_1187 & _GEN_316) & _GEN_509) : _GEN_509; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_536 = _T_1171 ? (_GEN_526 ? ~_GEN_317 & _GEN_510 : ~(_T_1187 & _GEN_317) & _GEN_510) : _GEN_510; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_537 = _T_1171 ? (_GEN_526 ? ~_GEN_318 & _GEN_511 : ~(_T_1187 & _GEN_318) & _GEN_511) : _GEN_511; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_538 = _T_1171 ? (_GEN_526 ? ~_GEN_319 & _GEN_512 : ~(_T_1187 & _GEN_319) & _GEN_512) : _GEN_512; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_539 = _T_1171 ? (_GEN_526 ? ~_GEN_320 & _GEN_513 : ~(_T_1187 & _GEN_320) & _GEN_513) : _GEN_513; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_540 = _T_1171 ? (_GEN_526 ? ~_GEN_321 & _GEN_514 : ~(_T_1187 & _GEN_321) & _GEN_514) : _GEN_514; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_541 = _T_1171 ? (_GEN_526 ? ~_GEN_322 & _GEN_515 : ~(_T_1187 & _GEN_322) & _GEN_515) : _GEN_515; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_542 = _T_1171 ? (_GEN_526 ? ~_GEN_323 & _GEN_516 : ~(_T_1187 & _GEN_323) & _GEN_516) : _GEN_516; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_543 = _T_1171 ? (_GEN_526 ? ~_GEN_324 & _GEN_517 : ~(_T_1187 & _GEN_324) & _GEN_517) : _GEN_517; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_544 = _T_1171 ? (_GEN_526 ? ~_GEN_325 & _GEN_518 : ~(_T_1187 & _GEN_325) & _GEN_518) : _GEN_518; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_545 = _T_1171 ? (_GEN_526 ? ~_GEN_326 & _GEN_519 : ~(_T_1187 & _GEN_326) & _GEN_519) : _GEN_519; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_546 = _T_1171 ? (_GEN_526 ? ~_GEN_327 & _GEN_520 : ~(_T_1187 & _GEN_327) & _GEN_520) : _GEN_520; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_547 = _T_1171 ? (_GEN_526 ? ~_GEN_328 & _GEN_521 : ~(_T_1187 & _GEN_328) & _GEN_521) : _GEN_521; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_548 = _T_1171 ? (_GEN_526 ? ~_GEN_329 & _GEN_522 : ~(_T_1187 & _GEN_329) & _GEN_522) : _GEN_522; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_549 = _T_1171 ? (_GEN_526 ? ~_GEN_330 & _GEN_523 : ~(_T_1187 & _GEN_330) & _GEN_523) : _GEN_523; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_550 = _T_1171 ? (_GEN_526 ? ~_GEN_331 & _GEN_524 : ~(_T_1187 & _GEN_331) & _GEN_524) : _GEN_524; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_114 = ~stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_115 = stq_3_bits_addr_valid & _dword_addr_matches_T_114; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_116 = stq_3_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_118 = _dword_addr_matches_T_116 == _dword_addr_matches_T_117; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_119 = _dword_addr_matches_T_115 & _dword_addr_matches_T_118; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_27_0 = _dword_addr_matches_T_119; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_3; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_45 = stq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_46 = stq_3_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_48 = stq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_49 = stq_3_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_52 = stq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_53 = stq_3_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_55 = &stq_3_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16]
assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16]
wire _T_1192 = do_ld_search_0 & stq_3_valid & lcam_st_dep_mask_0[3]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1203 = lcam_mask_0 & write_mask_3; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1200 = _T_1203 == lcam_mask_0 & ~stq_3_bits_uop_is_fence & ~stq_3_bits_uop_is_amo & dword_addr_matches_27_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_3 = _T_1192 & _T_1200; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_33; // @[lsu.scala:1154:56]
wire _T_1205 = (|_T_1203) & dword_addr_matches_27_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_34; // @[lsu.scala:1160:56]
wire _T_1208 = stq_3_bits_uop_is_fence | stq_3_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_3 = _T_1192 & (_T_1200 | _T_1205 | _T_1208); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_35; // @[lsu.scala:1166:56]
wire _GEN_551 = _T_1192 ? (_T_1200 ? io_dmem_s1_kill_0_REG_33 : _T_1205 ? io_dmem_s1_kill_0_REG_34 : _T_1208 ? io_dmem_s1_kill_0_REG_35 : _GEN_525) : _GEN_525; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_552 = _T_1200 | _T_1205; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_553 = _T_1192 ? (_GEN_552 ? ~_searcher_is_older_T_4 & _GEN_527 : ~(_T_1208 & _searcher_is_older_T_4) & _GEN_527) : _GEN_527; // @[util.scala:363:52]
wire _GEN_554 = _T_1192 ? (_GEN_552 ? ~_GEN_309 & _GEN_528 : ~(_T_1208 & _GEN_309) & _GEN_528) : _GEN_528; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_555 = _T_1192 ? (_GEN_552 ? ~_GEN_310 & _GEN_529 : ~(_T_1208 & _GEN_310) & _GEN_529) : _GEN_529; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_556 = _T_1192 ? (_GEN_552 ? ~_GEN_311 & _GEN_530 : ~(_T_1208 & _GEN_311) & _GEN_530) : _GEN_530; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_557 = _T_1192 ? (_GEN_552 ? ~_GEN_312 & _GEN_531 : ~(_T_1208 & _GEN_312) & _GEN_531) : _GEN_531; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_558 = _T_1192 ? (_GEN_552 ? ~_GEN_313 & _GEN_532 : ~(_T_1208 & _GEN_313) & _GEN_532) : _GEN_532; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_559 = _T_1192 ? (_GEN_552 ? ~_GEN_314 & _GEN_533 : ~(_T_1208 & _GEN_314) & _GEN_533) : _GEN_533; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_560 = _T_1192 ? (_GEN_552 ? ~_GEN_315 & _GEN_534 : ~(_T_1208 & _GEN_315) & _GEN_534) : _GEN_534; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_561 = _T_1192 ? (_GEN_552 ? ~_GEN_316 & _GEN_535 : ~(_T_1208 & _GEN_316) & _GEN_535) : _GEN_535; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_562 = _T_1192 ? (_GEN_552 ? ~_GEN_317 & _GEN_536 : ~(_T_1208 & _GEN_317) & _GEN_536) : _GEN_536; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_563 = _T_1192 ? (_GEN_552 ? ~_GEN_318 & _GEN_537 : ~(_T_1208 & _GEN_318) & _GEN_537) : _GEN_537; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_564 = _T_1192 ? (_GEN_552 ? ~_GEN_319 & _GEN_538 : ~(_T_1208 & _GEN_319) & _GEN_538) : _GEN_538; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_565 = _T_1192 ? (_GEN_552 ? ~_GEN_320 & _GEN_539 : ~(_T_1208 & _GEN_320) & _GEN_539) : _GEN_539; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_566 = _T_1192 ? (_GEN_552 ? ~_GEN_321 & _GEN_540 : ~(_T_1208 & _GEN_321) & _GEN_540) : _GEN_540; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_567 = _T_1192 ? (_GEN_552 ? ~_GEN_322 & _GEN_541 : ~(_T_1208 & _GEN_322) & _GEN_541) : _GEN_541; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_568 = _T_1192 ? (_GEN_552 ? ~_GEN_323 & _GEN_542 : ~(_T_1208 & _GEN_323) & _GEN_542) : _GEN_542; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_569 = _T_1192 ? (_GEN_552 ? ~_GEN_324 & _GEN_543 : ~(_T_1208 & _GEN_324) & _GEN_543) : _GEN_543; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_570 = _T_1192 ? (_GEN_552 ? ~_GEN_325 & _GEN_544 : ~(_T_1208 & _GEN_325) & _GEN_544) : _GEN_544; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_571 = _T_1192 ? (_GEN_552 ? ~_GEN_326 & _GEN_545 : ~(_T_1208 & _GEN_326) & _GEN_545) : _GEN_545; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_572 = _T_1192 ? (_GEN_552 ? ~_GEN_327 & _GEN_546 : ~(_T_1208 & _GEN_327) & _GEN_546) : _GEN_546; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_573 = _T_1192 ? (_GEN_552 ? ~_GEN_328 & _GEN_547 : ~(_T_1208 & _GEN_328) & _GEN_547) : _GEN_547; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_574 = _T_1192 ? (_GEN_552 ? ~_GEN_329 & _GEN_548 : ~(_T_1208 & _GEN_329) & _GEN_548) : _GEN_548; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_575 = _T_1192 ? (_GEN_552 ? ~_GEN_330 & _GEN_549 : ~(_T_1208 & _GEN_330) & _GEN_549) : _GEN_549; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_576 = _T_1192 ? (_GEN_552 ? ~_GEN_331 & _GEN_550 : ~(_T_1208 & _GEN_331) & _GEN_550) : _GEN_550; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_120 = ~stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_121 = stq_4_bits_addr_valid & _dword_addr_matches_T_120; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_122 = stq_4_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_124 = _dword_addr_matches_T_122 == _dword_addr_matches_T_123; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_125 = _dword_addr_matches_T_121 & _dword_addr_matches_T_124; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_28_0 = _dword_addr_matches_T_125; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_4; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_60 = stq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_61 = stq_4_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_63 = stq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_64 = stq_4_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_67 = stq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_68 = stq_4_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_70 = &stq_4_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16]
assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16]
wire _T_1213 = do_ld_search_0 & stq_4_valid & lcam_st_dep_mask_0[4]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1224 = lcam_mask_0 & write_mask_4; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1221 = _T_1224 == lcam_mask_0 & ~stq_4_bits_uop_is_fence & ~stq_4_bits_uop_is_amo & dword_addr_matches_28_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_4 = _T_1213 & _T_1221; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_36; // @[lsu.scala:1154:56]
wire _T_1226 = (|_T_1224) & dword_addr_matches_28_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_37; // @[lsu.scala:1160:56]
wire _T_1229 = stq_4_bits_uop_is_fence | stq_4_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_4 = _T_1213 & (_T_1221 | _T_1226 | _T_1229); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_38; // @[lsu.scala:1166:56]
wire _GEN_577 = _T_1213 ? (_T_1221 ? io_dmem_s1_kill_0_REG_36 : _T_1226 ? io_dmem_s1_kill_0_REG_37 : _T_1229 ? io_dmem_s1_kill_0_REG_38 : _GEN_551) : _GEN_551; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_578 = _T_1221 | _T_1226; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_579 = _T_1213 ? (_GEN_578 ? ~_searcher_is_older_T_4 & _GEN_553 : ~(_T_1229 & _searcher_is_older_T_4) & _GEN_553) : _GEN_553; // @[util.scala:363:52]
wire _GEN_580 = _T_1213 ? (_GEN_578 ? ~_GEN_309 & _GEN_554 : ~(_T_1229 & _GEN_309) & _GEN_554) : _GEN_554; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_581 = _T_1213 ? (_GEN_578 ? ~_GEN_310 & _GEN_555 : ~(_T_1229 & _GEN_310) & _GEN_555) : _GEN_555; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_582 = _T_1213 ? (_GEN_578 ? ~_GEN_311 & _GEN_556 : ~(_T_1229 & _GEN_311) & _GEN_556) : _GEN_556; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_583 = _T_1213 ? (_GEN_578 ? ~_GEN_312 & _GEN_557 : ~(_T_1229 & _GEN_312) & _GEN_557) : _GEN_557; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_584 = _T_1213 ? (_GEN_578 ? ~_GEN_313 & _GEN_558 : ~(_T_1229 & _GEN_313) & _GEN_558) : _GEN_558; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_585 = _T_1213 ? (_GEN_578 ? ~_GEN_314 & _GEN_559 : ~(_T_1229 & _GEN_314) & _GEN_559) : _GEN_559; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_586 = _T_1213 ? (_GEN_578 ? ~_GEN_315 & _GEN_560 : ~(_T_1229 & _GEN_315) & _GEN_560) : _GEN_560; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_587 = _T_1213 ? (_GEN_578 ? ~_GEN_316 & _GEN_561 : ~(_T_1229 & _GEN_316) & _GEN_561) : _GEN_561; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_588 = _T_1213 ? (_GEN_578 ? ~_GEN_317 & _GEN_562 : ~(_T_1229 & _GEN_317) & _GEN_562) : _GEN_562; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_589 = _T_1213 ? (_GEN_578 ? ~_GEN_318 & _GEN_563 : ~(_T_1229 & _GEN_318) & _GEN_563) : _GEN_563; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_590 = _T_1213 ? (_GEN_578 ? ~_GEN_319 & _GEN_564 : ~(_T_1229 & _GEN_319) & _GEN_564) : _GEN_564; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_591 = _T_1213 ? (_GEN_578 ? ~_GEN_320 & _GEN_565 : ~(_T_1229 & _GEN_320) & _GEN_565) : _GEN_565; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_592 = _T_1213 ? (_GEN_578 ? ~_GEN_321 & _GEN_566 : ~(_T_1229 & _GEN_321) & _GEN_566) : _GEN_566; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_593 = _T_1213 ? (_GEN_578 ? ~_GEN_322 & _GEN_567 : ~(_T_1229 & _GEN_322) & _GEN_567) : _GEN_567; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_594 = _T_1213 ? (_GEN_578 ? ~_GEN_323 & _GEN_568 : ~(_T_1229 & _GEN_323) & _GEN_568) : _GEN_568; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_595 = _T_1213 ? (_GEN_578 ? ~_GEN_324 & _GEN_569 : ~(_T_1229 & _GEN_324) & _GEN_569) : _GEN_569; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_596 = _T_1213 ? (_GEN_578 ? ~_GEN_325 & _GEN_570 : ~(_T_1229 & _GEN_325) & _GEN_570) : _GEN_570; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_597 = _T_1213 ? (_GEN_578 ? ~_GEN_326 & _GEN_571 : ~(_T_1229 & _GEN_326) & _GEN_571) : _GEN_571; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_598 = _T_1213 ? (_GEN_578 ? ~_GEN_327 & _GEN_572 : ~(_T_1229 & _GEN_327) & _GEN_572) : _GEN_572; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_599 = _T_1213 ? (_GEN_578 ? ~_GEN_328 & _GEN_573 : ~(_T_1229 & _GEN_328) & _GEN_573) : _GEN_573; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_600 = _T_1213 ? (_GEN_578 ? ~_GEN_329 & _GEN_574 : ~(_T_1229 & _GEN_329) & _GEN_574) : _GEN_574; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_601 = _T_1213 ? (_GEN_578 ? ~_GEN_330 & _GEN_575 : ~(_T_1229 & _GEN_330) & _GEN_575) : _GEN_575; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_602 = _T_1213 ? (_GEN_578 ? ~_GEN_331 & _GEN_576 : ~(_T_1229 & _GEN_331) & _GEN_576) : _GEN_576; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_126 = ~stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_127 = stq_5_bits_addr_valid & _dword_addr_matches_T_126; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_128 = stq_5_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_130 = _dword_addr_matches_T_128 == _dword_addr_matches_T_129; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_131 = _dword_addr_matches_T_127 & _dword_addr_matches_T_130; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_29_0 = _dword_addr_matches_T_131; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_5; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_75 = stq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_76 = stq_5_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_78 = stq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_79 = stq_5_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_82 = stq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_83 = stq_5_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_85 = &stq_5_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16]
assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16]
wire _T_1234 = do_ld_search_0 & stq_5_valid & lcam_st_dep_mask_0[5]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1245 = lcam_mask_0 & write_mask_5; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1242 = _T_1245 == lcam_mask_0 & ~stq_5_bits_uop_is_fence & ~stq_5_bits_uop_is_amo & dword_addr_matches_29_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_5 = _T_1234 & _T_1242; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_39; // @[lsu.scala:1154:56]
wire _T_1247 = (|_T_1245) & dword_addr_matches_29_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_40; // @[lsu.scala:1160:56]
wire _T_1250 = stq_5_bits_uop_is_fence | stq_5_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_5 = _T_1234 & (_T_1242 | _T_1247 | _T_1250); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_41; // @[lsu.scala:1166:56]
wire _GEN_603 = _T_1234 ? (_T_1242 ? io_dmem_s1_kill_0_REG_39 : _T_1247 ? io_dmem_s1_kill_0_REG_40 : _T_1250 ? io_dmem_s1_kill_0_REG_41 : _GEN_577) : _GEN_577; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_604 = _T_1242 | _T_1247; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_605 = _T_1234 ? (_GEN_604 ? ~_searcher_is_older_T_4 & _GEN_579 : ~(_T_1250 & _searcher_is_older_T_4) & _GEN_579) : _GEN_579; // @[util.scala:363:52]
wire _GEN_606 = _T_1234 ? (_GEN_604 ? ~_GEN_309 & _GEN_580 : ~(_T_1250 & _GEN_309) & _GEN_580) : _GEN_580; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_607 = _T_1234 ? (_GEN_604 ? ~_GEN_310 & _GEN_581 : ~(_T_1250 & _GEN_310) & _GEN_581) : _GEN_581; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_608 = _T_1234 ? (_GEN_604 ? ~_GEN_311 & _GEN_582 : ~(_T_1250 & _GEN_311) & _GEN_582) : _GEN_582; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_609 = _T_1234 ? (_GEN_604 ? ~_GEN_312 & _GEN_583 : ~(_T_1250 & _GEN_312) & _GEN_583) : _GEN_583; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_610 = _T_1234 ? (_GEN_604 ? ~_GEN_313 & _GEN_584 : ~(_T_1250 & _GEN_313) & _GEN_584) : _GEN_584; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_611 = _T_1234 ? (_GEN_604 ? ~_GEN_314 & _GEN_585 : ~(_T_1250 & _GEN_314) & _GEN_585) : _GEN_585; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_612 = _T_1234 ? (_GEN_604 ? ~_GEN_315 & _GEN_586 : ~(_T_1250 & _GEN_315) & _GEN_586) : _GEN_586; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_613 = _T_1234 ? (_GEN_604 ? ~_GEN_316 & _GEN_587 : ~(_T_1250 & _GEN_316) & _GEN_587) : _GEN_587; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_614 = _T_1234 ? (_GEN_604 ? ~_GEN_317 & _GEN_588 : ~(_T_1250 & _GEN_317) & _GEN_588) : _GEN_588; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_615 = _T_1234 ? (_GEN_604 ? ~_GEN_318 & _GEN_589 : ~(_T_1250 & _GEN_318) & _GEN_589) : _GEN_589; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_616 = _T_1234 ? (_GEN_604 ? ~_GEN_319 & _GEN_590 : ~(_T_1250 & _GEN_319) & _GEN_590) : _GEN_590; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_617 = _T_1234 ? (_GEN_604 ? ~_GEN_320 & _GEN_591 : ~(_T_1250 & _GEN_320) & _GEN_591) : _GEN_591; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_618 = _T_1234 ? (_GEN_604 ? ~_GEN_321 & _GEN_592 : ~(_T_1250 & _GEN_321) & _GEN_592) : _GEN_592; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_619 = _T_1234 ? (_GEN_604 ? ~_GEN_322 & _GEN_593 : ~(_T_1250 & _GEN_322) & _GEN_593) : _GEN_593; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_620 = _T_1234 ? (_GEN_604 ? ~_GEN_323 & _GEN_594 : ~(_T_1250 & _GEN_323) & _GEN_594) : _GEN_594; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_621 = _T_1234 ? (_GEN_604 ? ~_GEN_324 & _GEN_595 : ~(_T_1250 & _GEN_324) & _GEN_595) : _GEN_595; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_622 = _T_1234 ? (_GEN_604 ? ~_GEN_325 & _GEN_596 : ~(_T_1250 & _GEN_325) & _GEN_596) : _GEN_596; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_623 = _T_1234 ? (_GEN_604 ? ~_GEN_326 & _GEN_597 : ~(_T_1250 & _GEN_326) & _GEN_597) : _GEN_597; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_624 = _T_1234 ? (_GEN_604 ? ~_GEN_327 & _GEN_598 : ~(_T_1250 & _GEN_327) & _GEN_598) : _GEN_598; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_625 = _T_1234 ? (_GEN_604 ? ~_GEN_328 & _GEN_599 : ~(_T_1250 & _GEN_328) & _GEN_599) : _GEN_599; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_626 = _T_1234 ? (_GEN_604 ? ~_GEN_329 & _GEN_600 : ~(_T_1250 & _GEN_329) & _GEN_600) : _GEN_600; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_627 = _T_1234 ? (_GEN_604 ? ~_GEN_330 & _GEN_601 : ~(_T_1250 & _GEN_330) & _GEN_601) : _GEN_601; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_628 = _T_1234 ? (_GEN_604 ? ~_GEN_331 & _GEN_602 : ~(_T_1250 & _GEN_331) & _GEN_602) : _GEN_602; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_132 = ~stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_133 = stq_6_bits_addr_valid & _dword_addr_matches_T_132; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_134 = stq_6_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_136 = _dword_addr_matches_T_134 == _dword_addr_matches_T_135; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_137 = _dword_addr_matches_T_133 & _dword_addr_matches_T_136; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_30_0 = _dword_addr_matches_T_137; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_6; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_90 = stq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_91 = stq_6_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_93 = stq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_94 = stq_6_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_97 = stq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_98 = stq_6_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_100 = &stq_6_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16]
assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16]
wire _T_1255 = do_ld_search_0 & stq_6_valid & lcam_st_dep_mask_0[6]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1266 = lcam_mask_0 & write_mask_6; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1263 = _T_1266 == lcam_mask_0 & ~stq_6_bits_uop_is_fence & ~stq_6_bits_uop_is_amo & dword_addr_matches_30_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_6 = _T_1255 & _T_1263; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_42; // @[lsu.scala:1154:56]
wire _T_1268 = (|_T_1266) & dword_addr_matches_30_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_43; // @[lsu.scala:1160:56]
wire _T_1271 = stq_6_bits_uop_is_fence | stq_6_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_6 = _T_1255 & (_T_1263 | _T_1268 | _T_1271); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_44; // @[lsu.scala:1166:56]
wire _GEN_629 = _T_1255 ? (_T_1263 ? io_dmem_s1_kill_0_REG_42 : _T_1268 ? io_dmem_s1_kill_0_REG_43 : _T_1271 ? io_dmem_s1_kill_0_REG_44 : _GEN_603) : _GEN_603; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_630 = _T_1263 | _T_1268; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_631 = _T_1255 ? (_GEN_630 ? ~_searcher_is_older_T_4 & _GEN_605 : ~(_T_1271 & _searcher_is_older_T_4) & _GEN_605) : _GEN_605; // @[util.scala:363:52]
wire _GEN_632 = _T_1255 ? (_GEN_630 ? ~_GEN_309 & _GEN_606 : ~(_T_1271 & _GEN_309) & _GEN_606) : _GEN_606; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_633 = _T_1255 ? (_GEN_630 ? ~_GEN_310 & _GEN_607 : ~(_T_1271 & _GEN_310) & _GEN_607) : _GEN_607; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_634 = _T_1255 ? (_GEN_630 ? ~_GEN_311 & _GEN_608 : ~(_T_1271 & _GEN_311) & _GEN_608) : _GEN_608; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_635 = _T_1255 ? (_GEN_630 ? ~_GEN_312 & _GEN_609 : ~(_T_1271 & _GEN_312) & _GEN_609) : _GEN_609; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_636 = _T_1255 ? (_GEN_630 ? ~_GEN_313 & _GEN_610 : ~(_T_1271 & _GEN_313) & _GEN_610) : _GEN_610; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_637 = _T_1255 ? (_GEN_630 ? ~_GEN_314 & _GEN_611 : ~(_T_1271 & _GEN_314) & _GEN_611) : _GEN_611; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_638 = _T_1255 ? (_GEN_630 ? ~_GEN_315 & _GEN_612 : ~(_T_1271 & _GEN_315) & _GEN_612) : _GEN_612; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_639 = _T_1255 ? (_GEN_630 ? ~_GEN_316 & _GEN_613 : ~(_T_1271 & _GEN_316) & _GEN_613) : _GEN_613; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_640 = _T_1255 ? (_GEN_630 ? ~_GEN_317 & _GEN_614 : ~(_T_1271 & _GEN_317) & _GEN_614) : _GEN_614; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_641 = _T_1255 ? (_GEN_630 ? ~_GEN_318 & _GEN_615 : ~(_T_1271 & _GEN_318) & _GEN_615) : _GEN_615; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_642 = _T_1255 ? (_GEN_630 ? ~_GEN_319 & _GEN_616 : ~(_T_1271 & _GEN_319) & _GEN_616) : _GEN_616; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_643 = _T_1255 ? (_GEN_630 ? ~_GEN_320 & _GEN_617 : ~(_T_1271 & _GEN_320) & _GEN_617) : _GEN_617; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_644 = _T_1255 ? (_GEN_630 ? ~_GEN_321 & _GEN_618 : ~(_T_1271 & _GEN_321) & _GEN_618) : _GEN_618; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_645 = _T_1255 ? (_GEN_630 ? ~_GEN_322 & _GEN_619 : ~(_T_1271 & _GEN_322) & _GEN_619) : _GEN_619; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_646 = _T_1255 ? (_GEN_630 ? ~_GEN_323 & _GEN_620 : ~(_T_1271 & _GEN_323) & _GEN_620) : _GEN_620; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_647 = _T_1255 ? (_GEN_630 ? ~_GEN_324 & _GEN_621 : ~(_T_1271 & _GEN_324) & _GEN_621) : _GEN_621; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_648 = _T_1255 ? (_GEN_630 ? ~_GEN_325 & _GEN_622 : ~(_T_1271 & _GEN_325) & _GEN_622) : _GEN_622; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_649 = _T_1255 ? (_GEN_630 ? ~_GEN_326 & _GEN_623 : ~(_T_1271 & _GEN_326) & _GEN_623) : _GEN_623; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_650 = _T_1255 ? (_GEN_630 ? ~_GEN_327 & _GEN_624 : ~(_T_1271 & _GEN_327) & _GEN_624) : _GEN_624; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_651 = _T_1255 ? (_GEN_630 ? ~_GEN_328 & _GEN_625 : ~(_T_1271 & _GEN_328) & _GEN_625) : _GEN_625; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_652 = _T_1255 ? (_GEN_630 ? ~_GEN_329 & _GEN_626 : ~(_T_1271 & _GEN_329) & _GEN_626) : _GEN_626; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_653 = _T_1255 ? (_GEN_630 ? ~_GEN_330 & _GEN_627 : ~(_T_1271 & _GEN_330) & _GEN_627) : _GEN_627; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_654 = _T_1255 ? (_GEN_630 ? ~_GEN_331 & _GEN_628 : ~(_T_1271 & _GEN_331) & _GEN_628) : _GEN_628; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_138 = ~stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_139 = stq_7_bits_addr_valid & _dword_addr_matches_T_138; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_140 = stq_7_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_142 = _dword_addr_matches_T_140 == _dword_addr_matches_T_141; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_143 = _dword_addr_matches_T_139 & _dword_addr_matches_T_142; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_31_0 = _dword_addr_matches_T_143; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_7; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_105 = stq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_106 = stq_7_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_108 = stq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_109 = stq_7_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_112 = stq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_113 = stq_7_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_115 = &stq_7_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16]
assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16]
wire _T_1276 = do_ld_search_0 & stq_7_valid & lcam_st_dep_mask_0[7]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1287 = lcam_mask_0 & write_mask_7; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1284 = _T_1287 == lcam_mask_0 & ~stq_7_bits_uop_is_fence & ~stq_7_bits_uop_is_amo & dword_addr_matches_31_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_7 = _T_1276 & _T_1284; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_45; // @[lsu.scala:1154:56]
wire _T_1289 = (|_T_1287) & dword_addr_matches_31_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_46; // @[lsu.scala:1160:56]
wire _T_1292 = stq_7_bits_uop_is_fence | stq_7_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_7 = _T_1276 & (_T_1284 | _T_1289 | _T_1292); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_47; // @[lsu.scala:1166:56]
wire _GEN_655 = _T_1276 ? (_T_1284 ? io_dmem_s1_kill_0_REG_45 : _T_1289 ? io_dmem_s1_kill_0_REG_46 : _T_1292 ? io_dmem_s1_kill_0_REG_47 : _GEN_629) : _GEN_629; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_656 = _T_1284 | _T_1289; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_657 = _T_1276 ? (_GEN_656 ? ~_searcher_is_older_T_4 & _GEN_631 : ~(_T_1292 & _searcher_is_older_T_4) & _GEN_631) : _GEN_631; // @[util.scala:363:52]
wire _GEN_658 = _T_1276 ? (_GEN_656 ? ~_GEN_309 & _GEN_632 : ~(_T_1292 & _GEN_309) & _GEN_632) : _GEN_632; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_659 = _T_1276 ? (_GEN_656 ? ~_GEN_310 & _GEN_633 : ~(_T_1292 & _GEN_310) & _GEN_633) : _GEN_633; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_660 = _T_1276 ? (_GEN_656 ? ~_GEN_311 & _GEN_634 : ~(_T_1292 & _GEN_311) & _GEN_634) : _GEN_634; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_661 = _T_1276 ? (_GEN_656 ? ~_GEN_312 & _GEN_635 : ~(_T_1292 & _GEN_312) & _GEN_635) : _GEN_635; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_662 = _T_1276 ? (_GEN_656 ? ~_GEN_313 & _GEN_636 : ~(_T_1292 & _GEN_313) & _GEN_636) : _GEN_636; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_663 = _T_1276 ? (_GEN_656 ? ~_GEN_314 & _GEN_637 : ~(_T_1292 & _GEN_314) & _GEN_637) : _GEN_637; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_664 = _T_1276 ? (_GEN_656 ? ~_GEN_315 & _GEN_638 : ~(_T_1292 & _GEN_315) & _GEN_638) : _GEN_638; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_665 = _T_1276 ? (_GEN_656 ? ~_GEN_316 & _GEN_639 : ~(_T_1292 & _GEN_316) & _GEN_639) : _GEN_639; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_666 = _T_1276 ? (_GEN_656 ? ~_GEN_317 & _GEN_640 : ~(_T_1292 & _GEN_317) & _GEN_640) : _GEN_640; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_667 = _T_1276 ? (_GEN_656 ? ~_GEN_318 & _GEN_641 : ~(_T_1292 & _GEN_318) & _GEN_641) : _GEN_641; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_668 = _T_1276 ? (_GEN_656 ? ~_GEN_319 & _GEN_642 : ~(_T_1292 & _GEN_319) & _GEN_642) : _GEN_642; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_669 = _T_1276 ? (_GEN_656 ? ~_GEN_320 & _GEN_643 : ~(_T_1292 & _GEN_320) & _GEN_643) : _GEN_643; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_670 = _T_1276 ? (_GEN_656 ? ~_GEN_321 & _GEN_644 : ~(_T_1292 & _GEN_321) & _GEN_644) : _GEN_644; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_671 = _T_1276 ? (_GEN_656 ? ~_GEN_322 & _GEN_645 : ~(_T_1292 & _GEN_322) & _GEN_645) : _GEN_645; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_672 = _T_1276 ? (_GEN_656 ? ~_GEN_323 & _GEN_646 : ~(_T_1292 & _GEN_323) & _GEN_646) : _GEN_646; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_673 = _T_1276 ? (_GEN_656 ? ~_GEN_324 & _GEN_647 : ~(_T_1292 & _GEN_324) & _GEN_647) : _GEN_647; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_674 = _T_1276 ? (_GEN_656 ? ~_GEN_325 & _GEN_648 : ~(_T_1292 & _GEN_325) & _GEN_648) : _GEN_648; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_675 = _T_1276 ? (_GEN_656 ? ~_GEN_326 & _GEN_649 : ~(_T_1292 & _GEN_326) & _GEN_649) : _GEN_649; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_676 = _T_1276 ? (_GEN_656 ? ~_GEN_327 & _GEN_650 : ~(_T_1292 & _GEN_327) & _GEN_650) : _GEN_650; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_677 = _T_1276 ? (_GEN_656 ? ~_GEN_328 & _GEN_651 : ~(_T_1292 & _GEN_328) & _GEN_651) : _GEN_651; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_678 = _T_1276 ? (_GEN_656 ? ~_GEN_329 & _GEN_652 : ~(_T_1292 & _GEN_329) & _GEN_652) : _GEN_652; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_679 = _T_1276 ? (_GEN_656 ? ~_GEN_330 & _GEN_653 : ~(_T_1292 & _GEN_330) & _GEN_653) : _GEN_653; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_680 = _T_1276 ? (_GEN_656 ? ~_GEN_331 & _GEN_654 : ~(_T_1292 & _GEN_331) & _GEN_654) : _GEN_654; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_144 = ~stq_8_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_145 = stq_8_bits_addr_valid & _dword_addr_matches_T_144; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_146 = stq_8_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_148 = _dword_addr_matches_T_146 == _dword_addr_matches_T_147; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_149 = _dword_addr_matches_T_145 & _dword_addr_matches_T_148; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_32_0 = _dword_addr_matches_T_149; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_8; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_120 = stq_8_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_121 = stq_8_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_122 = 15'h1 << _write_mask_mask_T_121; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_123 = stq_8_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_124 = stq_8_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_125 = {_write_mask_mask_T_124, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_126 = 15'h3 << _write_mask_mask_T_125; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_127 = stq_8_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_128 = stq_8_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_129 = _write_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_130 = &stq_8_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_132 = _write_mask_mask_T_127 ? _write_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_133 = _write_mask_mask_T_123 ? _write_mask_mask_T_126 : {7'h0, _write_mask_mask_T_132}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_134 = _write_mask_mask_T_120 ? _write_mask_mask_T_122 : _write_mask_mask_T_133; // @[Mux.scala:126:16]
assign write_mask_8 = _write_mask_mask_T_134[7:0]; // @[Mux.scala:126:16]
wire _T_1297 = do_ld_search_0 & stq_8_valid & lcam_st_dep_mask_0[8]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1308 = lcam_mask_0 & write_mask_8; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1305 = _T_1308 == lcam_mask_0 & ~stq_8_bits_uop_is_fence & ~stq_8_bits_uop_is_amo & dword_addr_matches_32_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_8 = _T_1297 & _T_1305; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_48; // @[lsu.scala:1154:56]
wire _T_1310 = (|_T_1308) & dword_addr_matches_32_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_49; // @[lsu.scala:1160:56]
wire _T_1313 = stq_8_bits_uop_is_fence | stq_8_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_8 = _T_1297 & (_T_1305 | _T_1310 | _T_1313); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_50; // @[lsu.scala:1166:56]
wire _GEN_681 = _T_1297 ? (_T_1305 ? io_dmem_s1_kill_0_REG_48 : _T_1310 ? io_dmem_s1_kill_0_REG_49 : _T_1313 ? io_dmem_s1_kill_0_REG_50 : _GEN_655) : _GEN_655; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_682 = _T_1305 | _T_1310; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_683 = _T_1297 ? (_GEN_682 ? ~_searcher_is_older_T_4 & _GEN_657 : ~(_T_1313 & _searcher_is_older_T_4) & _GEN_657) : _GEN_657; // @[util.scala:363:52]
wire _GEN_684 = _T_1297 ? (_GEN_682 ? ~_GEN_309 & _GEN_658 : ~(_T_1313 & _GEN_309) & _GEN_658) : _GEN_658; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_685 = _T_1297 ? (_GEN_682 ? ~_GEN_310 & _GEN_659 : ~(_T_1313 & _GEN_310) & _GEN_659) : _GEN_659; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_686 = _T_1297 ? (_GEN_682 ? ~_GEN_311 & _GEN_660 : ~(_T_1313 & _GEN_311) & _GEN_660) : _GEN_660; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_687 = _T_1297 ? (_GEN_682 ? ~_GEN_312 & _GEN_661 : ~(_T_1313 & _GEN_312) & _GEN_661) : _GEN_661; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_688 = _T_1297 ? (_GEN_682 ? ~_GEN_313 & _GEN_662 : ~(_T_1313 & _GEN_313) & _GEN_662) : _GEN_662; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_689 = _T_1297 ? (_GEN_682 ? ~_GEN_314 & _GEN_663 : ~(_T_1313 & _GEN_314) & _GEN_663) : _GEN_663; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_690 = _T_1297 ? (_GEN_682 ? ~_GEN_315 & _GEN_664 : ~(_T_1313 & _GEN_315) & _GEN_664) : _GEN_664; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_691 = _T_1297 ? (_GEN_682 ? ~_GEN_316 & _GEN_665 : ~(_T_1313 & _GEN_316) & _GEN_665) : _GEN_665; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_692 = _T_1297 ? (_GEN_682 ? ~_GEN_317 & _GEN_666 : ~(_T_1313 & _GEN_317) & _GEN_666) : _GEN_666; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_693 = _T_1297 ? (_GEN_682 ? ~_GEN_318 & _GEN_667 : ~(_T_1313 & _GEN_318) & _GEN_667) : _GEN_667; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_694 = _T_1297 ? (_GEN_682 ? ~_GEN_319 & _GEN_668 : ~(_T_1313 & _GEN_319) & _GEN_668) : _GEN_668; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_695 = _T_1297 ? (_GEN_682 ? ~_GEN_320 & _GEN_669 : ~(_T_1313 & _GEN_320) & _GEN_669) : _GEN_669; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_696 = _T_1297 ? (_GEN_682 ? ~_GEN_321 & _GEN_670 : ~(_T_1313 & _GEN_321) & _GEN_670) : _GEN_670; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_697 = _T_1297 ? (_GEN_682 ? ~_GEN_322 & _GEN_671 : ~(_T_1313 & _GEN_322) & _GEN_671) : _GEN_671; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_698 = _T_1297 ? (_GEN_682 ? ~_GEN_323 & _GEN_672 : ~(_T_1313 & _GEN_323) & _GEN_672) : _GEN_672; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_699 = _T_1297 ? (_GEN_682 ? ~_GEN_324 & _GEN_673 : ~(_T_1313 & _GEN_324) & _GEN_673) : _GEN_673; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_700 = _T_1297 ? (_GEN_682 ? ~_GEN_325 & _GEN_674 : ~(_T_1313 & _GEN_325) & _GEN_674) : _GEN_674; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_701 = _T_1297 ? (_GEN_682 ? ~_GEN_326 & _GEN_675 : ~(_T_1313 & _GEN_326) & _GEN_675) : _GEN_675; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_702 = _T_1297 ? (_GEN_682 ? ~_GEN_327 & _GEN_676 : ~(_T_1313 & _GEN_327) & _GEN_676) : _GEN_676; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_703 = _T_1297 ? (_GEN_682 ? ~_GEN_328 & _GEN_677 : ~(_T_1313 & _GEN_328) & _GEN_677) : _GEN_677; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_704 = _T_1297 ? (_GEN_682 ? ~_GEN_329 & _GEN_678 : ~(_T_1313 & _GEN_329) & _GEN_678) : _GEN_678; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_705 = _T_1297 ? (_GEN_682 ? ~_GEN_330 & _GEN_679 : ~(_T_1313 & _GEN_330) & _GEN_679) : _GEN_679; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_706 = _T_1297 ? (_GEN_682 ? ~_GEN_331 & _GEN_680 : ~(_T_1313 & _GEN_331) & _GEN_680) : _GEN_680; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_150 = ~stq_9_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_151 = stq_9_bits_addr_valid & _dword_addr_matches_T_150; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_152 = stq_9_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_154 = _dword_addr_matches_T_152 == _dword_addr_matches_T_153; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_155 = _dword_addr_matches_T_151 & _dword_addr_matches_T_154; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_33_0 = _dword_addr_matches_T_155; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_9; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_135 = stq_9_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_136 = stq_9_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_137 = 15'h1 << _write_mask_mask_T_136; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_138 = stq_9_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_139 = stq_9_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_140 = {_write_mask_mask_T_139, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_141 = 15'h3 << _write_mask_mask_T_140; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_142 = stq_9_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_143 = stq_9_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_144 = _write_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_145 = &stq_9_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_147 = _write_mask_mask_T_142 ? _write_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_148 = _write_mask_mask_T_138 ? _write_mask_mask_T_141 : {7'h0, _write_mask_mask_T_147}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_149 = _write_mask_mask_T_135 ? _write_mask_mask_T_137 : _write_mask_mask_T_148; // @[Mux.scala:126:16]
assign write_mask_9 = _write_mask_mask_T_149[7:0]; // @[Mux.scala:126:16]
wire _T_1318 = do_ld_search_0 & stq_9_valid & lcam_st_dep_mask_0[9]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1329 = lcam_mask_0 & write_mask_9; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1326 = _T_1329 == lcam_mask_0 & ~stq_9_bits_uop_is_fence & ~stq_9_bits_uop_is_amo & dword_addr_matches_33_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_9 = _T_1318 & _T_1326; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_51; // @[lsu.scala:1154:56]
wire _T_1331 = (|_T_1329) & dword_addr_matches_33_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_52; // @[lsu.scala:1160:56]
wire _T_1334 = stq_9_bits_uop_is_fence | stq_9_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_9 = _T_1318 & (_T_1326 | _T_1331 | _T_1334); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_53; // @[lsu.scala:1166:56]
wire _GEN_707 = _T_1318 ? (_T_1326 ? io_dmem_s1_kill_0_REG_51 : _T_1331 ? io_dmem_s1_kill_0_REG_52 : _T_1334 ? io_dmem_s1_kill_0_REG_53 : _GEN_681) : _GEN_681; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_708 = _T_1326 | _T_1331; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_709 = _T_1318 ? (_GEN_708 ? ~_searcher_is_older_T_4 & _GEN_683 : ~(_T_1334 & _searcher_is_older_T_4) & _GEN_683) : _GEN_683; // @[util.scala:363:52]
wire _GEN_710 = _T_1318 ? (_GEN_708 ? ~_GEN_309 & _GEN_684 : ~(_T_1334 & _GEN_309) & _GEN_684) : _GEN_684; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_711 = _T_1318 ? (_GEN_708 ? ~_GEN_310 & _GEN_685 : ~(_T_1334 & _GEN_310) & _GEN_685) : _GEN_685; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_712 = _T_1318 ? (_GEN_708 ? ~_GEN_311 & _GEN_686 : ~(_T_1334 & _GEN_311) & _GEN_686) : _GEN_686; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_713 = _T_1318 ? (_GEN_708 ? ~_GEN_312 & _GEN_687 : ~(_T_1334 & _GEN_312) & _GEN_687) : _GEN_687; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_714 = _T_1318 ? (_GEN_708 ? ~_GEN_313 & _GEN_688 : ~(_T_1334 & _GEN_313) & _GEN_688) : _GEN_688; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_715 = _T_1318 ? (_GEN_708 ? ~_GEN_314 & _GEN_689 : ~(_T_1334 & _GEN_314) & _GEN_689) : _GEN_689; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_716 = _T_1318 ? (_GEN_708 ? ~_GEN_315 & _GEN_690 : ~(_T_1334 & _GEN_315) & _GEN_690) : _GEN_690; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_717 = _T_1318 ? (_GEN_708 ? ~_GEN_316 & _GEN_691 : ~(_T_1334 & _GEN_316) & _GEN_691) : _GEN_691; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_718 = _T_1318 ? (_GEN_708 ? ~_GEN_317 & _GEN_692 : ~(_T_1334 & _GEN_317) & _GEN_692) : _GEN_692; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_719 = _T_1318 ? (_GEN_708 ? ~_GEN_318 & _GEN_693 : ~(_T_1334 & _GEN_318) & _GEN_693) : _GEN_693; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_720 = _T_1318 ? (_GEN_708 ? ~_GEN_319 & _GEN_694 : ~(_T_1334 & _GEN_319) & _GEN_694) : _GEN_694; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_721 = _T_1318 ? (_GEN_708 ? ~_GEN_320 & _GEN_695 : ~(_T_1334 & _GEN_320) & _GEN_695) : _GEN_695; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_722 = _T_1318 ? (_GEN_708 ? ~_GEN_321 & _GEN_696 : ~(_T_1334 & _GEN_321) & _GEN_696) : _GEN_696; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_723 = _T_1318 ? (_GEN_708 ? ~_GEN_322 & _GEN_697 : ~(_T_1334 & _GEN_322) & _GEN_697) : _GEN_697; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_724 = _T_1318 ? (_GEN_708 ? ~_GEN_323 & _GEN_698 : ~(_T_1334 & _GEN_323) & _GEN_698) : _GEN_698; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_725 = _T_1318 ? (_GEN_708 ? ~_GEN_324 & _GEN_699 : ~(_T_1334 & _GEN_324) & _GEN_699) : _GEN_699; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_726 = _T_1318 ? (_GEN_708 ? ~_GEN_325 & _GEN_700 : ~(_T_1334 & _GEN_325) & _GEN_700) : _GEN_700; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_727 = _T_1318 ? (_GEN_708 ? ~_GEN_326 & _GEN_701 : ~(_T_1334 & _GEN_326) & _GEN_701) : _GEN_701; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_728 = _T_1318 ? (_GEN_708 ? ~_GEN_327 & _GEN_702 : ~(_T_1334 & _GEN_327) & _GEN_702) : _GEN_702; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_729 = _T_1318 ? (_GEN_708 ? ~_GEN_328 & _GEN_703 : ~(_T_1334 & _GEN_328) & _GEN_703) : _GEN_703; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_730 = _T_1318 ? (_GEN_708 ? ~_GEN_329 & _GEN_704 : ~(_T_1334 & _GEN_329) & _GEN_704) : _GEN_704; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_731 = _T_1318 ? (_GEN_708 ? ~_GEN_330 & _GEN_705 : ~(_T_1334 & _GEN_330) & _GEN_705) : _GEN_705; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_732 = _T_1318 ? (_GEN_708 ? ~_GEN_331 & _GEN_706 : ~(_T_1334 & _GEN_331) & _GEN_706) : _GEN_706; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_156 = ~stq_10_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_157 = stq_10_bits_addr_valid & _dword_addr_matches_T_156; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_158 = stq_10_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_160 = _dword_addr_matches_T_158 == _dword_addr_matches_T_159; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_161 = _dword_addr_matches_T_157 & _dword_addr_matches_T_160; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_34_0 = _dword_addr_matches_T_161; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_10; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_150 = stq_10_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_151 = stq_10_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_152 = 15'h1 << _write_mask_mask_T_151; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_153 = stq_10_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_154 = stq_10_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_155 = {_write_mask_mask_T_154, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_156 = 15'h3 << _write_mask_mask_T_155; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_157 = stq_10_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_158 = stq_10_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_159 = _write_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_160 = &stq_10_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_162 = _write_mask_mask_T_157 ? _write_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_163 = _write_mask_mask_T_153 ? _write_mask_mask_T_156 : {7'h0, _write_mask_mask_T_162}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_164 = _write_mask_mask_T_150 ? _write_mask_mask_T_152 : _write_mask_mask_T_163; // @[Mux.scala:126:16]
assign write_mask_10 = _write_mask_mask_T_164[7:0]; // @[Mux.scala:126:16]
wire _T_1339 = do_ld_search_0 & stq_10_valid & lcam_st_dep_mask_0[10]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1350 = lcam_mask_0 & write_mask_10; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1347 = _T_1350 == lcam_mask_0 & ~stq_10_bits_uop_is_fence & ~stq_10_bits_uop_is_amo & dword_addr_matches_34_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_10 = _T_1339 & _T_1347; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_54; // @[lsu.scala:1154:56]
wire _T_1352 = (|_T_1350) & dword_addr_matches_34_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_55; // @[lsu.scala:1160:56]
wire _T_1355 = stq_10_bits_uop_is_fence | stq_10_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_10 = _T_1339 & (_T_1347 | _T_1352 | _T_1355); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_56; // @[lsu.scala:1166:56]
wire _GEN_733 = _T_1339 ? (_T_1347 ? io_dmem_s1_kill_0_REG_54 : _T_1352 ? io_dmem_s1_kill_0_REG_55 : _T_1355 ? io_dmem_s1_kill_0_REG_56 : _GEN_707) : _GEN_707; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_734 = _T_1347 | _T_1352; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_735 = _T_1339 ? (_GEN_734 ? ~_searcher_is_older_T_4 & _GEN_709 : ~(_T_1355 & _searcher_is_older_T_4) & _GEN_709) : _GEN_709; // @[util.scala:363:52]
wire _GEN_736 = _T_1339 ? (_GEN_734 ? ~_GEN_309 & _GEN_710 : ~(_T_1355 & _GEN_309) & _GEN_710) : _GEN_710; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_737 = _T_1339 ? (_GEN_734 ? ~_GEN_310 & _GEN_711 : ~(_T_1355 & _GEN_310) & _GEN_711) : _GEN_711; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_738 = _T_1339 ? (_GEN_734 ? ~_GEN_311 & _GEN_712 : ~(_T_1355 & _GEN_311) & _GEN_712) : _GEN_712; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_739 = _T_1339 ? (_GEN_734 ? ~_GEN_312 & _GEN_713 : ~(_T_1355 & _GEN_312) & _GEN_713) : _GEN_713; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_740 = _T_1339 ? (_GEN_734 ? ~_GEN_313 & _GEN_714 : ~(_T_1355 & _GEN_313) & _GEN_714) : _GEN_714; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_741 = _T_1339 ? (_GEN_734 ? ~_GEN_314 & _GEN_715 : ~(_T_1355 & _GEN_314) & _GEN_715) : _GEN_715; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_742 = _T_1339 ? (_GEN_734 ? ~_GEN_315 & _GEN_716 : ~(_T_1355 & _GEN_315) & _GEN_716) : _GEN_716; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_743 = _T_1339 ? (_GEN_734 ? ~_GEN_316 & _GEN_717 : ~(_T_1355 & _GEN_316) & _GEN_717) : _GEN_717; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_744 = _T_1339 ? (_GEN_734 ? ~_GEN_317 & _GEN_718 : ~(_T_1355 & _GEN_317) & _GEN_718) : _GEN_718; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_745 = _T_1339 ? (_GEN_734 ? ~_GEN_318 & _GEN_719 : ~(_T_1355 & _GEN_318) & _GEN_719) : _GEN_719; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_746 = _T_1339 ? (_GEN_734 ? ~_GEN_319 & _GEN_720 : ~(_T_1355 & _GEN_319) & _GEN_720) : _GEN_720; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_747 = _T_1339 ? (_GEN_734 ? ~_GEN_320 & _GEN_721 : ~(_T_1355 & _GEN_320) & _GEN_721) : _GEN_721; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_748 = _T_1339 ? (_GEN_734 ? ~_GEN_321 & _GEN_722 : ~(_T_1355 & _GEN_321) & _GEN_722) : _GEN_722; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_749 = _T_1339 ? (_GEN_734 ? ~_GEN_322 & _GEN_723 : ~(_T_1355 & _GEN_322) & _GEN_723) : _GEN_723; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_750 = _T_1339 ? (_GEN_734 ? ~_GEN_323 & _GEN_724 : ~(_T_1355 & _GEN_323) & _GEN_724) : _GEN_724; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_751 = _T_1339 ? (_GEN_734 ? ~_GEN_324 & _GEN_725 : ~(_T_1355 & _GEN_324) & _GEN_725) : _GEN_725; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_752 = _T_1339 ? (_GEN_734 ? ~_GEN_325 & _GEN_726 : ~(_T_1355 & _GEN_325) & _GEN_726) : _GEN_726; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_753 = _T_1339 ? (_GEN_734 ? ~_GEN_326 & _GEN_727 : ~(_T_1355 & _GEN_326) & _GEN_727) : _GEN_727; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_754 = _T_1339 ? (_GEN_734 ? ~_GEN_327 & _GEN_728 : ~(_T_1355 & _GEN_327) & _GEN_728) : _GEN_728; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_755 = _T_1339 ? (_GEN_734 ? ~_GEN_328 & _GEN_729 : ~(_T_1355 & _GEN_328) & _GEN_729) : _GEN_729; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_756 = _T_1339 ? (_GEN_734 ? ~_GEN_329 & _GEN_730 : ~(_T_1355 & _GEN_329) & _GEN_730) : _GEN_730; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_757 = _T_1339 ? (_GEN_734 ? ~_GEN_330 & _GEN_731 : ~(_T_1355 & _GEN_330) & _GEN_731) : _GEN_731; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_758 = _T_1339 ? (_GEN_734 ? ~_GEN_331 & _GEN_732 : ~(_T_1355 & _GEN_331) & _GEN_732) : _GEN_732; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_162 = ~stq_11_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_163 = stq_11_bits_addr_valid & _dword_addr_matches_T_162; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_164 = stq_11_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_166 = _dword_addr_matches_T_164 == _dword_addr_matches_T_165; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_167 = _dword_addr_matches_T_163 & _dword_addr_matches_T_166; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_35_0 = _dword_addr_matches_T_167; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_11; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_165 = stq_11_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_166 = stq_11_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_167 = 15'h1 << _write_mask_mask_T_166; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_168 = stq_11_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_169 = stq_11_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_170 = {_write_mask_mask_T_169, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_171 = 15'h3 << _write_mask_mask_T_170; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_172 = stq_11_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_173 = stq_11_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_174 = _write_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_175 = &stq_11_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_177 = _write_mask_mask_T_172 ? _write_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_178 = _write_mask_mask_T_168 ? _write_mask_mask_T_171 : {7'h0, _write_mask_mask_T_177}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_179 = _write_mask_mask_T_165 ? _write_mask_mask_T_167 : _write_mask_mask_T_178; // @[Mux.scala:126:16]
assign write_mask_11 = _write_mask_mask_T_179[7:0]; // @[Mux.scala:126:16]
wire _T_1360 = do_ld_search_0 & stq_11_valid & lcam_st_dep_mask_0[11]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1371 = lcam_mask_0 & write_mask_11; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1368 = _T_1371 == lcam_mask_0 & ~stq_11_bits_uop_is_fence & ~stq_11_bits_uop_is_amo & dword_addr_matches_35_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_11 = _T_1360 & _T_1368; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_57; // @[lsu.scala:1154:56]
wire _T_1373 = (|_T_1371) & dword_addr_matches_35_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_58; // @[lsu.scala:1160:56]
wire _T_1376 = stq_11_bits_uop_is_fence | stq_11_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_11 = _T_1360 & (_T_1368 | _T_1373 | _T_1376); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_59; // @[lsu.scala:1166:56]
wire _GEN_759 = _T_1360 ? (_T_1368 ? io_dmem_s1_kill_0_REG_57 : _T_1373 ? io_dmem_s1_kill_0_REG_58 : _T_1376 ? io_dmem_s1_kill_0_REG_59 : _GEN_733) : _GEN_733; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_760 = _T_1368 | _T_1373; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_761 = _T_1360 ? (_GEN_760 ? ~_searcher_is_older_T_4 & _GEN_735 : ~(_T_1376 & _searcher_is_older_T_4) & _GEN_735) : _GEN_735; // @[util.scala:363:52]
wire _GEN_762 = _T_1360 ? (_GEN_760 ? ~_GEN_309 & _GEN_736 : ~(_T_1376 & _GEN_309) & _GEN_736) : _GEN_736; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_763 = _T_1360 ? (_GEN_760 ? ~_GEN_310 & _GEN_737 : ~(_T_1376 & _GEN_310) & _GEN_737) : _GEN_737; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_764 = _T_1360 ? (_GEN_760 ? ~_GEN_311 & _GEN_738 : ~(_T_1376 & _GEN_311) & _GEN_738) : _GEN_738; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_765 = _T_1360 ? (_GEN_760 ? ~_GEN_312 & _GEN_739 : ~(_T_1376 & _GEN_312) & _GEN_739) : _GEN_739; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_766 = _T_1360 ? (_GEN_760 ? ~_GEN_313 & _GEN_740 : ~(_T_1376 & _GEN_313) & _GEN_740) : _GEN_740; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_767 = _T_1360 ? (_GEN_760 ? ~_GEN_314 & _GEN_741 : ~(_T_1376 & _GEN_314) & _GEN_741) : _GEN_741; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_768 = _T_1360 ? (_GEN_760 ? ~_GEN_315 & _GEN_742 : ~(_T_1376 & _GEN_315) & _GEN_742) : _GEN_742; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_769 = _T_1360 ? (_GEN_760 ? ~_GEN_316 & _GEN_743 : ~(_T_1376 & _GEN_316) & _GEN_743) : _GEN_743; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_770 = _T_1360 ? (_GEN_760 ? ~_GEN_317 & _GEN_744 : ~(_T_1376 & _GEN_317) & _GEN_744) : _GEN_744; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_771 = _T_1360 ? (_GEN_760 ? ~_GEN_318 & _GEN_745 : ~(_T_1376 & _GEN_318) & _GEN_745) : _GEN_745; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_772 = _T_1360 ? (_GEN_760 ? ~_GEN_319 & _GEN_746 : ~(_T_1376 & _GEN_319) & _GEN_746) : _GEN_746; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_773 = _T_1360 ? (_GEN_760 ? ~_GEN_320 & _GEN_747 : ~(_T_1376 & _GEN_320) & _GEN_747) : _GEN_747; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_774 = _T_1360 ? (_GEN_760 ? ~_GEN_321 & _GEN_748 : ~(_T_1376 & _GEN_321) & _GEN_748) : _GEN_748; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_775 = _T_1360 ? (_GEN_760 ? ~_GEN_322 & _GEN_749 : ~(_T_1376 & _GEN_322) & _GEN_749) : _GEN_749; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_776 = _T_1360 ? (_GEN_760 ? ~_GEN_323 & _GEN_750 : ~(_T_1376 & _GEN_323) & _GEN_750) : _GEN_750; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_777 = _T_1360 ? (_GEN_760 ? ~_GEN_324 & _GEN_751 : ~(_T_1376 & _GEN_324) & _GEN_751) : _GEN_751; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_778 = _T_1360 ? (_GEN_760 ? ~_GEN_325 & _GEN_752 : ~(_T_1376 & _GEN_325) & _GEN_752) : _GEN_752; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_779 = _T_1360 ? (_GEN_760 ? ~_GEN_326 & _GEN_753 : ~(_T_1376 & _GEN_326) & _GEN_753) : _GEN_753; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_780 = _T_1360 ? (_GEN_760 ? ~_GEN_327 & _GEN_754 : ~(_T_1376 & _GEN_327) & _GEN_754) : _GEN_754; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_781 = _T_1360 ? (_GEN_760 ? ~_GEN_328 & _GEN_755 : ~(_T_1376 & _GEN_328) & _GEN_755) : _GEN_755; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_782 = _T_1360 ? (_GEN_760 ? ~_GEN_329 & _GEN_756 : ~(_T_1376 & _GEN_329) & _GEN_756) : _GEN_756; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_783 = _T_1360 ? (_GEN_760 ? ~_GEN_330 & _GEN_757 : ~(_T_1376 & _GEN_330) & _GEN_757) : _GEN_757; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_784 = _T_1360 ? (_GEN_760 ? ~_GEN_331 & _GEN_758 : ~(_T_1376 & _GEN_331) & _GEN_758) : _GEN_758; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_168 = ~stq_12_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_169 = stq_12_bits_addr_valid & _dword_addr_matches_T_168; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_170 = stq_12_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_172 = _dword_addr_matches_T_170 == _dword_addr_matches_T_171; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_173 = _dword_addr_matches_T_169 & _dword_addr_matches_T_172; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_36_0 = _dword_addr_matches_T_173; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_12; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_180 = stq_12_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_181 = stq_12_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_182 = 15'h1 << _write_mask_mask_T_181; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_183 = stq_12_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_184 = stq_12_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_185 = {_write_mask_mask_T_184, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_186 = 15'h3 << _write_mask_mask_T_185; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_187 = stq_12_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_188 = stq_12_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_189 = _write_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_190 = &stq_12_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_192 = _write_mask_mask_T_187 ? _write_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_193 = _write_mask_mask_T_183 ? _write_mask_mask_T_186 : {7'h0, _write_mask_mask_T_192}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_194 = _write_mask_mask_T_180 ? _write_mask_mask_T_182 : _write_mask_mask_T_193; // @[Mux.scala:126:16]
assign write_mask_12 = _write_mask_mask_T_194[7:0]; // @[Mux.scala:126:16]
wire _T_1381 = do_ld_search_0 & stq_12_valid & lcam_st_dep_mask_0[12]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1392 = lcam_mask_0 & write_mask_12; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1389 = _T_1392 == lcam_mask_0 & ~stq_12_bits_uop_is_fence & ~stq_12_bits_uop_is_amo & dword_addr_matches_36_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_12 = _T_1381 & _T_1389; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_60; // @[lsu.scala:1154:56]
wire _T_1394 = (|_T_1392) & dword_addr_matches_36_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_61; // @[lsu.scala:1160:56]
wire _T_1397 = stq_12_bits_uop_is_fence | stq_12_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_12 = _T_1381 & (_T_1389 | _T_1394 | _T_1397); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_62; // @[lsu.scala:1166:56]
wire _GEN_785 = _T_1381 ? (_T_1389 ? io_dmem_s1_kill_0_REG_60 : _T_1394 ? io_dmem_s1_kill_0_REG_61 : _T_1397 ? io_dmem_s1_kill_0_REG_62 : _GEN_759) : _GEN_759; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_786 = _T_1389 | _T_1394; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_787 = _T_1381 ? (_GEN_786 ? ~_searcher_is_older_T_4 & _GEN_761 : ~(_T_1397 & _searcher_is_older_T_4) & _GEN_761) : _GEN_761; // @[util.scala:363:52]
wire _GEN_788 = _T_1381 ? (_GEN_786 ? ~_GEN_309 & _GEN_762 : ~(_T_1397 & _GEN_309) & _GEN_762) : _GEN_762; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_789 = _T_1381 ? (_GEN_786 ? ~_GEN_310 & _GEN_763 : ~(_T_1397 & _GEN_310) & _GEN_763) : _GEN_763; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_790 = _T_1381 ? (_GEN_786 ? ~_GEN_311 & _GEN_764 : ~(_T_1397 & _GEN_311) & _GEN_764) : _GEN_764; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_791 = _T_1381 ? (_GEN_786 ? ~_GEN_312 & _GEN_765 : ~(_T_1397 & _GEN_312) & _GEN_765) : _GEN_765; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_792 = _T_1381 ? (_GEN_786 ? ~_GEN_313 & _GEN_766 : ~(_T_1397 & _GEN_313) & _GEN_766) : _GEN_766; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_793 = _T_1381 ? (_GEN_786 ? ~_GEN_314 & _GEN_767 : ~(_T_1397 & _GEN_314) & _GEN_767) : _GEN_767; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_794 = _T_1381 ? (_GEN_786 ? ~_GEN_315 & _GEN_768 : ~(_T_1397 & _GEN_315) & _GEN_768) : _GEN_768; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_795 = _T_1381 ? (_GEN_786 ? ~_GEN_316 & _GEN_769 : ~(_T_1397 & _GEN_316) & _GEN_769) : _GEN_769; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_796 = _T_1381 ? (_GEN_786 ? ~_GEN_317 & _GEN_770 : ~(_T_1397 & _GEN_317) & _GEN_770) : _GEN_770; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_797 = _T_1381 ? (_GEN_786 ? ~_GEN_318 & _GEN_771 : ~(_T_1397 & _GEN_318) & _GEN_771) : _GEN_771; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_798 = _T_1381 ? (_GEN_786 ? ~_GEN_319 & _GEN_772 : ~(_T_1397 & _GEN_319) & _GEN_772) : _GEN_772; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_799 = _T_1381 ? (_GEN_786 ? ~_GEN_320 & _GEN_773 : ~(_T_1397 & _GEN_320) & _GEN_773) : _GEN_773; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_800 = _T_1381 ? (_GEN_786 ? ~_GEN_321 & _GEN_774 : ~(_T_1397 & _GEN_321) & _GEN_774) : _GEN_774; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_801 = _T_1381 ? (_GEN_786 ? ~_GEN_322 & _GEN_775 : ~(_T_1397 & _GEN_322) & _GEN_775) : _GEN_775; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_802 = _T_1381 ? (_GEN_786 ? ~_GEN_323 & _GEN_776 : ~(_T_1397 & _GEN_323) & _GEN_776) : _GEN_776; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_803 = _T_1381 ? (_GEN_786 ? ~_GEN_324 & _GEN_777 : ~(_T_1397 & _GEN_324) & _GEN_777) : _GEN_777; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_804 = _T_1381 ? (_GEN_786 ? ~_GEN_325 & _GEN_778 : ~(_T_1397 & _GEN_325) & _GEN_778) : _GEN_778; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_805 = _T_1381 ? (_GEN_786 ? ~_GEN_326 & _GEN_779 : ~(_T_1397 & _GEN_326) & _GEN_779) : _GEN_779; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_806 = _T_1381 ? (_GEN_786 ? ~_GEN_327 & _GEN_780 : ~(_T_1397 & _GEN_327) & _GEN_780) : _GEN_780; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_807 = _T_1381 ? (_GEN_786 ? ~_GEN_328 & _GEN_781 : ~(_T_1397 & _GEN_328) & _GEN_781) : _GEN_781; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_808 = _T_1381 ? (_GEN_786 ? ~_GEN_329 & _GEN_782 : ~(_T_1397 & _GEN_329) & _GEN_782) : _GEN_782; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_809 = _T_1381 ? (_GEN_786 ? ~_GEN_330 & _GEN_783 : ~(_T_1397 & _GEN_330) & _GEN_783) : _GEN_783; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_810 = _T_1381 ? (_GEN_786 ? ~_GEN_331 & _GEN_784 : ~(_T_1397 & _GEN_331) & _GEN_784) : _GEN_784; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_174 = ~stq_13_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_175 = stq_13_bits_addr_valid & _dword_addr_matches_T_174; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_176 = stq_13_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_178 = _dword_addr_matches_T_176 == _dword_addr_matches_T_177; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_179 = _dword_addr_matches_T_175 & _dword_addr_matches_T_178; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_37_0 = _dword_addr_matches_T_179; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_13; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_195 = stq_13_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_196 = stq_13_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_197 = 15'h1 << _write_mask_mask_T_196; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_198 = stq_13_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_199 = stq_13_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_200 = {_write_mask_mask_T_199, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_201 = 15'h3 << _write_mask_mask_T_200; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_202 = stq_13_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_203 = stq_13_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_204 = _write_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_205 = &stq_13_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_207 = _write_mask_mask_T_202 ? _write_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_208 = _write_mask_mask_T_198 ? _write_mask_mask_T_201 : {7'h0, _write_mask_mask_T_207}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_209 = _write_mask_mask_T_195 ? _write_mask_mask_T_197 : _write_mask_mask_T_208; // @[Mux.scala:126:16]
assign write_mask_13 = _write_mask_mask_T_209[7:0]; // @[Mux.scala:126:16]
wire _T_1402 = do_ld_search_0 & stq_13_valid & lcam_st_dep_mask_0[13]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1413 = lcam_mask_0 & write_mask_13; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1410 = _T_1413 == lcam_mask_0 & ~stq_13_bits_uop_is_fence & ~stq_13_bits_uop_is_amo & dword_addr_matches_37_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_13 = _T_1402 & _T_1410; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_63; // @[lsu.scala:1154:56]
wire _T_1415 = (|_T_1413) & dword_addr_matches_37_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_64; // @[lsu.scala:1160:56]
wire _T_1418 = stq_13_bits_uop_is_fence | stq_13_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_13 = _T_1402 & (_T_1410 | _T_1415 | _T_1418); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_65; // @[lsu.scala:1166:56]
wire _GEN_811 = _T_1402 ? (_T_1410 ? io_dmem_s1_kill_0_REG_63 : _T_1415 ? io_dmem_s1_kill_0_REG_64 : _T_1418 ? io_dmem_s1_kill_0_REG_65 : _GEN_785) : _GEN_785; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_812 = _T_1410 | _T_1415; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_813 = _T_1402 ? (_GEN_812 ? ~_searcher_is_older_T_4 & _GEN_787 : ~(_T_1418 & _searcher_is_older_T_4) & _GEN_787) : _GEN_787; // @[util.scala:363:52]
wire _GEN_814 = _T_1402 ? (_GEN_812 ? ~_GEN_309 & _GEN_788 : ~(_T_1418 & _GEN_309) & _GEN_788) : _GEN_788; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_815 = _T_1402 ? (_GEN_812 ? ~_GEN_310 & _GEN_789 : ~(_T_1418 & _GEN_310) & _GEN_789) : _GEN_789; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_816 = _T_1402 ? (_GEN_812 ? ~_GEN_311 & _GEN_790 : ~(_T_1418 & _GEN_311) & _GEN_790) : _GEN_790; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_817 = _T_1402 ? (_GEN_812 ? ~_GEN_312 & _GEN_791 : ~(_T_1418 & _GEN_312) & _GEN_791) : _GEN_791; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_818 = _T_1402 ? (_GEN_812 ? ~_GEN_313 & _GEN_792 : ~(_T_1418 & _GEN_313) & _GEN_792) : _GEN_792; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_819 = _T_1402 ? (_GEN_812 ? ~_GEN_314 & _GEN_793 : ~(_T_1418 & _GEN_314) & _GEN_793) : _GEN_793; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_820 = _T_1402 ? (_GEN_812 ? ~_GEN_315 & _GEN_794 : ~(_T_1418 & _GEN_315) & _GEN_794) : _GEN_794; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_821 = _T_1402 ? (_GEN_812 ? ~_GEN_316 & _GEN_795 : ~(_T_1418 & _GEN_316) & _GEN_795) : _GEN_795; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_822 = _T_1402 ? (_GEN_812 ? ~_GEN_317 & _GEN_796 : ~(_T_1418 & _GEN_317) & _GEN_796) : _GEN_796; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_823 = _T_1402 ? (_GEN_812 ? ~_GEN_318 & _GEN_797 : ~(_T_1418 & _GEN_318) & _GEN_797) : _GEN_797; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_824 = _T_1402 ? (_GEN_812 ? ~_GEN_319 & _GEN_798 : ~(_T_1418 & _GEN_319) & _GEN_798) : _GEN_798; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_825 = _T_1402 ? (_GEN_812 ? ~_GEN_320 & _GEN_799 : ~(_T_1418 & _GEN_320) & _GEN_799) : _GEN_799; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_826 = _T_1402 ? (_GEN_812 ? ~_GEN_321 & _GEN_800 : ~(_T_1418 & _GEN_321) & _GEN_800) : _GEN_800; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_827 = _T_1402 ? (_GEN_812 ? ~_GEN_322 & _GEN_801 : ~(_T_1418 & _GEN_322) & _GEN_801) : _GEN_801; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_828 = _T_1402 ? (_GEN_812 ? ~_GEN_323 & _GEN_802 : ~(_T_1418 & _GEN_323) & _GEN_802) : _GEN_802; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_829 = _T_1402 ? (_GEN_812 ? ~_GEN_324 & _GEN_803 : ~(_T_1418 & _GEN_324) & _GEN_803) : _GEN_803; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_830 = _T_1402 ? (_GEN_812 ? ~_GEN_325 & _GEN_804 : ~(_T_1418 & _GEN_325) & _GEN_804) : _GEN_804; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_831 = _T_1402 ? (_GEN_812 ? ~_GEN_326 & _GEN_805 : ~(_T_1418 & _GEN_326) & _GEN_805) : _GEN_805; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_832 = _T_1402 ? (_GEN_812 ? ~_GEN_327 & _GEN_806 : ~(_T_1418 & _GEN_327) & _GEN_806) : _GEN_806; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_833 = _T_1402 ? (_GEN_812 ? ~_GEN_328 & _GEN_807 : ~(_T_1418 & _GEN_328) & _GEN_807) : _GEN_807; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_834 = _T_1402 ? (_GEN_812 ? ~_GEN_329 & _GEN_808 : ~(_T_1418 & _GEN_329) & _GEN_808) : _GEN_808; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_835 = _T_1402 ? (_GEN_812 ? ~_GEN_330 & _GEN_809 : ~(_T_1418 & _GEN_330) & _GEN_809) : _GEN_809; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_836 = _T_1402 ? (_GEN_812 ? ~_GEN_331 & _GEN_810 : ~(_T_1418 & _GEN_331) & _GEN_810) : _GEN_810; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_180 = ~stq_14_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_181 = stq_14_bits_addr_valid & _dword_addr_matches_T_180; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_182 = stq_14_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_184 = _dword_addr_matches_T_182 == _dword_addr_matches_T_183; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_185 = _dword_addr_matches_T_181 & _dword_addr_matches_T_184; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_38_0 = _dword_addr_matches_T_185; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_14; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_210 = stq_14_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_211 = stq_14_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_212 = 15'h1 << _write_mask_mask_T_211; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_213 = stq_14_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_214 = stq_14_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_215 = {_write_mask_mask_T_214, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_216 = 15'h3 << _write_mask_mask_T_215; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_217 = stq_14_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_218 = stq_14_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_219 = _write_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_220 = &stq_14_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_222 = _write_mask_mask_T_217 ? _write_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_223 = _write_mask_mask_T_213 ? _write_mask_mask_T_216 : {7'h0, _write_mask_mask_T_222}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_224 = _write_mask_mask_T_210 ? _write_mask_mask_T_212 : _write_mask_mask_T_223; // @[Mux.scala:126:16]
assign write_mask_14 = _write_mask_mask_T_224[7:0]; // @[Mux.scala:126:16]
wire _T_1423 = do_ld_search_0 & stq_14_valid & lcam_st_dep_mask_0[14]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1434 = lcam_mask_0 & write_mask_14; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1431 = _T_1434 == lcam_mask_0 & ~stq_14_bits_uop_is_fence & ~stq_14_bits_uop_is_amo & dword_addr_matches_38_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_14 = _T_1423 & _T_1431; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_66; // @[lsu.scala:1154:56]
wire _T_1436 = (|_T_1434) & dword_addr_matches_38_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_67; // @[lsu.scala:1160:56]
wire _T_1439 = stq_14_bits_uop_is_fence | stq_14_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_14 = _T_1423 & (_T_1431 | _T_1436 | _T_1439); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_68; // @[lsu.scala:1166:56]
wire _GEN_837 = _T_1423 ? (_T_1431 ? io_dmem_s1_kill_0_REG_66 : _T_1436 ? io_dmem_s1_kill_0_REG_67 : _T_1439 ? io_dmem_s1_kill_0_REG_68 : _GEN_811) : _GEN_811; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_838 = _T_1431 | _T_1436; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_839 = _T_1423 ? (_GEN_838 ? ~_searcher_is_older_T_4 & _GEN_813 : ~(_T_1439 & _searcher_is_older_T_4) & _GEN_813) : _GEN_813; // @[util.scala:363:52]
wire _GEN_840 = _T_1423 ? (_GEN_838 ? ~_GEN_309 & _GEN_814 : ~(_T_1439 & _GEN_309) & _GEN_814) : _GEN_814; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_841 = _T_1423 ? (_GEN_838 ? ~_GEN_310 & _GEN_815 : ~(_T_1439 & _GEN_310) & _GEN_815) : _GEN_815; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_842 = _T_1423 ? (_GEN_838 ? ~_GEN_311 & _GEN_816 : ~(_T_1439 & _GEN_311) & _GEN_816) : _GEN_816; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_843 = _T_1423 ? (_GEN_838 ? ~_GEN_312 & _GEN_817 : ~(_T_1439 & _GEN_312) & _GEN_817) : _GEN_817; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_844 = _T_1423 ? (_GEN_838 ? ~_GEN_313 & _GEN_818 : ~(_T_1439 & _GEN_313) & _GEN_818) : _GEN_818; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_845 = _T_1423 ? (_GEN_838 ? ~_GEN_314 & _GEN_819 : ~(_T_1439 & _GEN_314) & _GEN_819) : _GEN_819; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_846 = _T_1423 ? (_GEN_838 ? ~_GEN_315 & _GEN_820 : ~(_T_1439 & _GEN_315) & _GEN_820) : _GEN_820; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_847 = _T_1423 ? (_GEN_838 ? ~_GEN_316 & _GEN_821 : ~(_T_1439 & _GEN_316) & _GEN_821) : _GEN_821; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_848 = _T_1423 ? (_GEN_838 ? ~_GEN_317 & _GEN_822 : ~(_T_1439 & _GEN_317) & _GEN_822) : _GEN_822; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_849 = _T_1423 ? (_GEN_838 ? ~_GEN_318 & _GEN_823 : ~(_T_1439 & _GEN_318) & _GEN_823) : _GEN_823; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_850 = _T_1423 ? (_GEN_838 ? ~_GEN_319 & _GEN_824 : ~(_T_1439 & _GEN_319) & _GEN_824) : _GEN_824; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_851 = _T_1423 ? (_GEN_838 ? ~_GEN_320 & _GEN_825 : ~(_T_1439 & _GEN_320) & _GEN_825) : _GEN_825; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_852 = _T_1423 ? (_GEN_838 ? ~_GEN_321 & _GEN_826 : ~(_T_1439 & _GEN_321) & _GEN_826) : _GEN_826; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_853 = _T_1423 ? (_GEN_838 ? ~_GEN_322 & _GEN_827 : ~(_T_1439 & _GEN_322) & _GEN_827) : _GEN_827; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_854 = _T_1423 ? (_GEN_838 ? ~_GEN_323 & _GEN_828 : ~(_T_1439 & _GEN_323) & _GEN_828) : _GEN_828; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_855 = _T_1423 ? (_GEN_838 ? ~_GEN_324 & _GEN_829 : ~(_T_1439 & _GEN_324) & _GEN_829) : _GEN_829; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_856 = _T_1423 ? (_GEN_838 ? ~_GEN_325 & _GEN_830 : ~(_T_1439 & _GEN_325) & _GEN_830) : _GEN_830; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_857 = _T_1423 ? (_GEN_838 ? ~_GEN_326 & _GEN_831 : ~(_T_1439 & _GEN_326) & _GEN_831) : _GEN_831; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_858 = _T_1423 ? (_GEN_838 ? ~_GEN_327 & _GEN_832 : ~(_T_1439 & _GEN_327) & _GEN_832) : _GEN_832; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_859 = _T_1423 ? (_GEN_838 ? ~_GEN_328 & _GEN_833 : ~(_T_1439 & _GEN_328) & _GEN_833) : _GEN_833; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_860 = _T_1423 ? (_GEN_838 ? ~_GEN_329 & _GEN_834 : ~(_T_1439 & _GEN_329) & _GEN_834) : _GEN_834; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_861 = _T_1423 ? (_GEN_838 ? ~_GEN_330 & _GEN_835 : ~(_T_1439 & _GEN_330) & _GEN_835) : _GEN_835; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_862 = _T_1423 ? (_GEN_838 ? ~_GEN_331 & _GEN_836 : ~(_T_1439 & _GEN_331) & _GEN_836) : _GEN_836; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_186 = ~stq_15_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_187 = stq_15_bits_addr_valid & _dword_addr_matches_T_186; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_188 = stq_15_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_190 = _dword_addr_matches_T_188 == _dword_addr_matches_T_189; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_191 = _dword_addr_matches_T_187 & _dword_addr_matches_T_190; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_39_0 = _dword_addr_matches_T_191; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_15; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_225 = stq_15_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_226 = stq_15_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_227 = 15'h1 << _write_mask_mask_T_226; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_228 = stq_15_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_229 = stq_15_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_230 = {_write_mask_mask_T_229, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_231 = 15'h3 << _write_mask_mask_T_230; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_232 = stq_15_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_233 = stq_15_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_234 = _write_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_235 = &stq_15_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_237 = _write_mask_mask_T_232 ? _write_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_238 = _write_mask_mask_T_228 ? _write_mask_mask_T_231 : {7'h0, _write_mask_mask_T_237}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_239 = _write_mask_mask_T_225 ? _write_mask_mask_T_227 : _write_mask_mask_T_238; // @[Mux.scala:126:16]
assign write_mask_15 = _write_mask_mask_T_239[7:0]; // @[Mux.scala:126:16]
wire _T_1444 = do_ld_search_0 & stq_15_valid & lcam_st_dep_mask_0[15]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1455 = lcam_mask_0 & write_mask_15; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1452 = _T_1455 == lcam_mask_0 & ~stq_15_bits_uop_is_fence & ~stq_15_bits_uop_is_amo & dword_addr_matches_39_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_15 = _T_1444 & _T_1452; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_69; // @[lsu.scala:1154:56]
wire _T_1457 = (|_T_1455) & dword_addr_matches_39_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_70; // @[lsu.scala:1160:56]
wire _T_1460 = stq_15_bits_uop_is_fence | stq_15_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_15 = _T_1444 & (_T_1452 | _T_1457 | _T_1460); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_71; // @[lsu.scala:1166:56]
wire _GEN_863 = _T_1444 ? (_T_1452 ? io_dmem_s1_kill_0_REG_69 : _T_1457 ? io_dmem_s1_kill_0_REG_70 : _T_1460 ? io_dmem_s1_kill_0_REG_71 : _GEN_837) : _GEN_837; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_864 = _T_1452 | _T_1457; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_865 = _T_1444 ? (_GEN_864 ? ~_searcher_is_older_T_4 & _GEN_839 : ~(_T_1460 & _searcher_is_older_T_4) & _GEN_839) : _GEN_839; // @[util.scala:363:52]
wire _GEN_866 = _T_1444 ? (_GEN_864 ? ~_GEN_309 & _GEN_840 : ~(_T_1460 & _GEN_309) & _GEN_840) : _GEN_840; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_867 = _T_1444 ? (_GEN_864 ? ~_GEN_310 & _GEN_841 : ~(_T_1460 & _GEN_310) & _GEN_841) : _GEN_841; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_868 = _T_1444 ? (_GEN_864 ? ~_GEN_311 & _GEN_842 : ~(_T_1460 & _GEN_311) & _GEN_842) : _GEN_842; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_869 = _T_1444 ? (_GEN_864 ? ~_GEN_312 & _GEN_843 : ~(_T_1460 & _GEN_312) & _GEN_843) : _GEN_843; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_870 = _T_1444 ? (_GEN_864 ? ~_GEN_313 & _GEN_844 : ~(_T_1460 & _GEN_313) & _GEN_844) : _GEN_844; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_871 = _T_1444 ? (_GEN_864 ? ~_GEN_314 & _GEN_845 : ~(_T_1460 & _GEN_314) & _GEN_845) : _GEN_845; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_872 = _T_1444 ? (_GEN_864 ? ~_GEN_315 & _GEN_846 : ~(_T_1460 & _GEN_315) & _GEN_846) : _GEN_846; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_873 = _T_1444 ? (_GEN_864 ? ~_GEN_316 & _GEN_847 : ~(_T_1460 & _GEN_316) & _GEN_847) : _GEN_847; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_874 = _T_1444 ? (_GEN_864 ? ~_GEN_317 & _GEN_848 : ~(_T_1460 & _GEN_317) & _GEN_848) : _GEN_848; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_875 = _T_1444 ? (_GEN_864 ? ~_GEN_318 & _GEN_849 : ~(_T_1460 & _GEN_318) & _GEN_849) : _GEN_849; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_876 = _T_1444 ? (_GEN_864 ? ~_GEN_319 & _GEN_850 : ~(_T_1460 & _GEN_319) & _GEN_850) : _GEN_850; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_877 = _T_1444 ? (_GEN_864 ? ~_GEN_320 & _GEN_851 : ~(_T_1460 & _GEN_320) & _GEN_851) : _GEN_851; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_878 = _T_1444 ? (_GEN_864 ? ~_GEN_321 & _GEN_852 : ~(_T_1460 & _GEN_321) & _GEN_852) : _GEN_852; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_879 = _T_1444 ? (_GEN_864 ? ~_GEN_322 & _GEN_853 : ~(_T_1460 & _GEN_322) & _GEN_853) : _GEN_853; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_880 = _T_1444 ? (_GEN_864 ? ~_GEN_323 & _GEN_854 : ~(_T_1460 & _GEN_323) & _GEN_854) : _GEN_854; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_881 = _T_1444 ? (_GEN_864 ? ~_GEN_324 & _GEN_855 : ~(_T_1460 & _GEN_324) & _GEN_855) : _GEN_855; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_882 = _T_1444 ? (_GEN_864 ? ~_GEN_325 & _GEN_856 : ~(_T_1460 & _GEN_325) & _GEN_856) : _GEN_856; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_883 = _T_1444 ? (_GEN_864 ? ~_GEN_326 & _GEN_857 : ~(_T_1460 & _GEN_326) & _GEN_857) : _GEN_857; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_884 = _T_1444 ? (_GEN_864 ? ~_GEN_327 & _GEN_858 : ~(_T_1460 & _GEN_327) & _GEN_858) : _GEN_858; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_885 = _T_1444 ? (_GEN_864 ? ~_GEN_328 & _GEN_859 : ~(_T_1460 & _GEN_328) & _GEN_859) : _GEN_859; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_886 = _T_1444 ? (_GEN_864 ? ~_GEN_329 & _GEN_860 : ~(_T_1460 & _GEN_329) & _GEN_860) : _GEN_860; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_887 = _T_1444 ? (_GEN_864 ? ~_GEN_330 & _GEN_861 : ~(_T_1460 & _GEN_330) & _GEN_861) : _GEN_861; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_888 = _T_1444 ? (_GEN_864 ? ~_GEN_331 & _GEN_862 : ~(_T_1460 & _GEN_331) & _GEN_862) : _GEN_862; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_192 = ~stq_16_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_193 = stq_16_bits_addr_valid & _dword_addr_matches_T_192; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_194 = stq_16_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_196 = _dword_addr_matches_T_194 == _dword_addr_matches_T_195; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_197 = _dword_addr_matches_T_193 & _dword_addr_matches_T_196; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_40_0 = _dword_addr_matches_T_197; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_16; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_240 = stq_16_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_241 = stq_16_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_242 = 15'h1 << _write_mask_mask_T_241; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_243 = stq_16_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_244 = stq_16_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_245 = {_write_mask_mask_T_244, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_246 = 15'h3 << _write_mask_mask_T_245; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_247 = stq_16_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_248 = stq_16_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_249 = _write_mask_mask_T_248 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_250 = &stq_16_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_252 = _write_mask_mask_T_247 ? _write_mask_mask_T_249 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_253 = _write_mask_mask_T_243 ? _write_mask_mask_T_246 : {7'h0, _write_mask_mask_T_252}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_254 = _write_mask_mask_T_240 ? _write_mask_mask_T_242 : _write_mask_mask_T_253; // @[Mux.scala:126:16]
assign write_mask_16 = _write_mask_mask_T_254[7:0]; // @[Mux.scala:126:16]
wire _T_1465 = do_ld_search_0 & stq_16_valid & lcam_st_dep_mask_0[16]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1476 = lcam_mask_0 & write_mask_16; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1473 = _T_1476 == lcam_mask_0 & ~stq_16_bits_uop_is_fence & ~stq_16_bits_uop_is_amo & dword_addr_matches_40_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_16 = _T_1465 & _T_1473; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_72; // @[lsu.scala:1154:56]
wire _T_1478 = (|_T_1476) & dword_addr_matches_40_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_73; // @[lsu.scala:1160:56]
wire _T_1481 = stq_16_bits_uop_is_fence | stq_16_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_16 = _T_1465 & (_T_1473 | _T_1478 | _T_1481); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_74; // @[lsu.scala:1166:56]
wire _GEN_889 = _T_1465 ? (_T_1473 ? io_dmem_s1_kill_0_REG_72 : _T_1478 ? io_dmem_s1_kill_0_REG_73 : _T_1481 ? io_dmem_s1_kill_0_REG_74 : _GEN_863) : _GEN_863; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_890 = _T_1473 | _T_1478; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_891 = _T_1465 ? (_GEN_890 ? ~_searcher_is_older_T_4 & _GEN_865 : ~(_T_1481 & _searcher_is_older_T_4) & _GEN_865) : _GEN_865; // @[util.scala:363:52]
wire _GEN_892 = _T_1465 ? (_GEN_890 ? ~_GEN_309 & _GEN_866 : ~(_T_1481 & _GEN_309) & _GEN_866) : _GEN_866; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_893 = _T_1465 ? (_GEN_890 ? ~_GEN_310 & _GEN_867 : ~(_T_1481 & _GEN_310) & _GEN_867) : _GEN_867; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_894 = _T_1465 ? (_GEN_890 ? ~_GEN_311 & _GEN_868 : ~(_T_1481 & _GEN_311) & _GEN_868) : _GEN_868; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_895 = _T_1465 ? (_GEN_890 ? ~_GEN_312 & _GEN_869 : ~(_T_1481 & _GEN_312) & _GEN_869) : _GEN_869; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_896 = _T_1465 ? (_GEN_890 ? ~_GEN_313 & _GEN_870 : ~(_T_1481 & _GEN_313) & _GEN_870) : _GEN_870; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_897 = _T_1465 ? (_GEN_890 ? ~_GEN_314 & _GEN_871 : ~(_T_1481 & _GEN_314) & _GEN_871) : _GEN_871; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_898 = _T_1465 ? (_GEN_890 ? ~_GEN_315 & _GEN_872 : ~(_T_1481 & _GEN_315) & _GEN_872) : _GEN_872; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_899 = _T_1465 ? (_GEN_890 ? ~_GEN_316 & _GEN_873 : ~(_T_1481 & _GEN_316) & _GEN_873) : _GEN_873; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_900 = _T_1465 ? (_GEN_890 ? ~_GEN_317 & _GEN_874 : ~(_T_1481 & _GEN_317) & _GEN_874) : _GEN_874; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_901 = _T_1465 ? (_GEN_890 ? ~_GEN_318 & _GEN_875 : ~(_T_1481 & _GEN_318) & _GEN_875) : _GEN_875; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_902 = _T_1465 ? (_GEN_890 ? ~_GEN_319 & _GEN_876 : ~(_T_1481 & _GEN_319) & _GEN_876) : _GEN_876; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_903 = _T_1465 ? (_GEN_890 ? ~_GEN_320 & _GEN_877 : ~(_T_1481 & _GEN_320) & _GEN_877) : _GEN_877; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_904 = _T_1465 ? (_GEN_890 ? ~_GEN_321 & _GEN_878 : ~(_T_1481 & _GEN_321) & _GEN_878) : _GEN_878; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_905 = _T_1465 ? (_GEN_890 ? ~_GEN_322 & _GEN_879 : ~(_T_1481 & _GEN_322) & _GEN_879) : _GEN_879; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_906 = _T_1465 ? (_GEN_890 ? ~_GEN_323 & _GEN_880 : ~(_T_1481 & _GEN_323) & _GEN_880) : _GEN_880; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_907 = _T_1465 ? (_GEN_890 ? ~_GEN_324 & _GEN_881 : ~(_T_1481 & _GEN_324) & _GEN_881) : _GEN_881; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_908 = _T_1465 ? (_GEN_890 ? ~_GEN_325 & _GEN_882 : ~(_T_1481 & _GEN_325) & _GEN_882) : _GEN_882; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_909 = _T_1465 ? (_GEN_890 ? ~_GEN_326 & _GEN_883 : ~(_T_1481 & _GEN_326) & _GEN_883) : _GEN_883; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_910 = _T_1465 ? (_GEN_890 ? ~_GEN_327 & _GEN_884 : ~(_T_1481 & _GEN_327) & _GEN_884) : _GEN_884; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_911 = _T_1465 ? (_GEN_890 ? ~_GEN_328 & _GEN_885 : ~(_T_1481 & _GEN_328) & _GEN_885) : _GEN_885; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_912 = _T_1465 ? (_GEN_890 ? ~_GEN_329 & _GEN_886 : ~(_T_1481 & _GEN_329) & _GEN_886) : _GEN_886; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_913 = _T_1465 ? (_GEN_890 ? ~_GEN_330 & _GEN_887 : ~(_T_1481 & _GEN_330) & _GEN_887) : _GEN_887; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_914 = _T_1465 ? (_GEN_890 ? ~_GEN_331 & _GEN_888 : ~(_T_1481 & _GEN_331) & _GEN_888) : _GEN_888; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_198 = ~stq_17_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_199 = stq_17_bits_addr_valid & _dword_addr_matches_T_198; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_200 = stq_17_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_202 = _dword_addr_matches_T_200 == _dword_addr_matches_T_201; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_203 = _dword_addr_matches_T_199 & _dword_addr_matches_T_202; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_41_0 = _dword_addr_matches_T_203; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_17; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_255 = stq_17_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_256 = stq_17_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_257 = 15'h1 << _write_mask_mask_T_256; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_258 = stq_17_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_259 = stq_17_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_260 = {_write_mask_mask_T_259, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_261 = 15'h3 << _write_mask_mask_T_260; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_262 = stq_17_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_263 = stq_17_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_264 = _write_mask_mask_T_263 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_265 = &stq_17_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_267 = _write_mask_mask_T_262 ? _write_mask_mask_T_264 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_268 = _write_mask_mask_T_258 ? _write_mask_mask_T_261 : {7'h0, _write_mask_mask_T_267}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_269 = _write_mask_mask_T_255 ? _write_mask_mask_T_257 : _write_mask_mask_T_268; // @[Mux.scala:126:16]
assign write_mask_17 = _write_mask_mask_T_269[7:0]; // @[Mux.scala:126:16]
wire _T_1486 = do_ld_search_0 & stq_17_valid & lcam_st_dep_mask_0[17]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1497 = lcam_mask_0 & write_mask_17; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1494 = _T_1497 == lcam_mask_0 & ~stq_17_bits_uop_is_fence & ~stq_17_bits_uop_is_amo & dword_addr_matches_41_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_17 = _T_1486 & _T_1494; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_75; // @[lsu.scala:1154:56]
wire _T_1499 = (|_T_1497) & dword_addr_matches_41_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_76; // @[lsu.scala:1160:56]
wire _T_1502 = stq_17_bits_uop_is_fence | stq_17_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_17 = _T_1486 & (_T_1494 | _T_1499 | _T_1502); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_77; // @[lsu.scala:1166:56]
wire _GEN_915 = _T_1486 ? (_T_1494 ? io_dmem_s1_kill_0_REG_75 : _T_1499 ? io_dmem_s1_kill_0_REG_76 : _T_1502 ? io_dmem_s1_kill_0_REG_77 : _GEN_889) : _GEN_889; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_916 = _T_1494 | _T_1499; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_917 = _T_1486 ? (_GEN_916 ? ~_searcher_is_older_T_4 & _GEN_891 : ~(_T_1502 & _searcher_is_older_T_4) & _GEN_891) : _GEN_891; // @[util.scala:363:52]
wire _GEN_918 = _T_1486 ? (_GEN_916 ? ~_GEN_309 & _GEN_892 : ~(_T_1502 & _GEN_309) & _GEN_892) : _GEN_892; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_919 = _T_1486 ? (_GEN_916 ? ~_GEN_310 & _GEN_893 : ~(_T_1502 & _GEN_310) & _GEN_893) : _GEN_893; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_920 = _T_1486 ? (_GEN_916 ? ~_GEN_311 & _GEN_894 : ~(_T_1502 & _GEN_311) & _GEN_894) : _GEN_894; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_921 = _T_1486 ? (_GEN_916 ? ~_GEN_312 & _GEN_895 : ~(_T_1502 & _GEN_312) & _GEN_895) : _GEN_895; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_922 = _T_1486 ? (_GEN_916 ? ~_GEN_313 & _GEN_896 : ~(_T_1502 & _GEN_313) & _GEN_896) : _GEN_896; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_923 = _T_1486 ? (_GEN_916 ? ~_GEN_314 & _GEN_897 : ~(_T_1502 & _GEN_314) & _GEN_897) : _GEN_897; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_924 = _T_1486 ? (_GEN_916 ? ~_GEN_315 & _GEN_898 : ~(_T_1502 & _GEN_315) & _GEN_898) : _GEN_898; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_925 = _T_1486 ? (_GEN_916 ? ~_GEN_316 & _GEN_899 : ~(_T_1502 & _GEN_316) & _GEN_899) : _GEN_899; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_926 = _T_1486 ? (_GEN_916 ? ~_GEN_317 & _GEN_900 : ~(_T_1502 & _GEN_317) & _GEN_900) : _GEN_900; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_927 = _T_1486 ? (_GEN_916 ? ~_GEN_318 & _GEN_901 : ~(_T_1502 & _GEN_318) & _GEN_901) : _GEN_901; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_928 = _T_1486 ? (_GEN_916 ? ~_GEN_319 & _GEN_902 : ~(_T_1502 & _GEN_319) & _GEN_902) : _GEN_902; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_929 = _T_1486 ? (_GEN_916 ? ~_GEN_320 & _GEN_903 : ~(_T_1502 & _GEN_320) & _GEN_903) : _GEN_903; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_930 = _T_1486 ? (_GEN_916 ? ~_GEN_321 & _GEN_904 : ~(_T_1502 & _GEN_321) & _GEN_904) : _GEN_904; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_931 = _T_1486 ? (_GEN_916 ? ~_GEN_322 & _GEN_905 : ~(_T_1502 & _GEN_322) & _GEN_905) : _GEN_905; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_932 = _T_1486 ? (_GEN_916 ? ~_GEN_323 & _GEN_906 : ~(_T_1502 & _GEN_323) & _GEN_906) : _GEN_906; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_933 = _T_1486 ? (_GEN_916 ? ~_GEN_324 & _GEN_907 : ~(_T_1502 & _GEN_324) & _GEN_907) : _GEN_907; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_934 = _T_1486 ? (_GEN_916 ? ~_GEN_325 & _GEN_908 : ~(_T_1502 & _GEN_325) & _GEN_908) : _GEN_908; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_935 = _T_1486 ? (_GEN_916 ? ~_GEN_326 & _GEN_909 : ~(_T_1502 & _GEN_326) & _GEN_909) : _GEN_909; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_936 = _T_1486 ? (_GEN_916 ? ~_GEN_327 & _GEN_910 : ~(_T_1502 & _GEN_327) & _GEN_910) : _GEN_910; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_937 = _T_1486 ? (_GEN_916 ? ~_GEN_328 & _GEN_911 : ~(_T_1502 & _GEN_328) & _GEN_911) : _GEN_911; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_938 = _T_1486 ? (_GEN_916 ? ~_GEN_329 & _GEN_912 : ~(_T_1502 & _GEN_329) & _GEN_912) : _GEN_912; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_939 = _T_1486 ? (_GEN_916 ? ~_GEN_330 & _GEN_913 : ~(_T_1502 & _GEN_330) & _GEN_913) : _GEN_913; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_940 = _T_1486 ? (_GEN_916 ? ~_GEN_331 & _GEN_914 : ~(_T_1502 & _GEN_331) & _GEN_914) : _GEN_914; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_204 = ~stq_18_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_205 = stq_18_bits_addr_valid & _dword_addr_matches_T_204; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_206 = stq_18_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_208 = _dword_addr_matches_T_206 == _dword_addr_matches_T_207; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_209 = _dword_addr_matches_T_205 & _dword_addr_matches_T_208; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_42_0 = _dword_addr_matches_T_209; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_18; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_270 = stq_18_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_271 = stq_18_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_272 = 15'h1 << _write_mask_mask_T_271; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_273 = stq_18_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_274 = stq_18_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_275 = {_write_mask_mask_T_274, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_276 = 15'h3 << _write_mask_mask_T_275; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_277 = stq_18_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_278 = stq_18_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_279 = _write_mask_mask_T_278 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_280 = &stq_18_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_282 = _write_mask_mask_T_277 ? _write_mask_mask_T_279 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_283 = _write_mask_mask_T_273 ? _write_mask_mask_T_276 : {7'h0, _write_mask_mask_T_282}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_284 = _write_mask_mask_T_270 ? _write_mask_mask_T_272 : _write_mask_mask_T_283; // @[Mux.scala:126:16]
assign write_mask_18 = _write_mask_mask_T_284[7:0]; // @[Mux.scala:126:16]
wire _T_1507 = do_ld_search_0 & stq_18_valid & lcam_st_dep_mask_0[18]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1518 = lcam_mask_0 & write_mask_18; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1515 = _T_1518 == lcam_mask_0 & ~stq_18_bits_uop_is_fence & ~stq_18_bits_uop_is_amo & dword_addr_matches_42_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_18 = _T_1507 & _T_1515; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_78; // @[lsu.scala:1154:56]
wire _T_1520 = (|_T_1518) & dword_addr_matches_42_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_79; // @[lsu.scala:1160:56]
wire _T_1523 = stq_18_bits_uop_is_fence | stq_18_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_18 = _T_1507 & (_T_1515 | _T_1520 | _T_1523); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_80; // @[lsu.scala:1166:56]
wire _GEN_941 = _T_1507 ? (_T_1515 ? io_dmem_s1_kill_0_REG_78 : _T_1520 ? io_dmem_s1_kill_0_REG_79 : _T_1523 ? io_dmem_s1_kill_0_REG_80 : _GEN_915) : _GEN_915; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_942 = _T_1515 | _T_1520; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_943 = _T_1507 ? (_GEN_942 ? ~_searcher_is_older_T_4 & _GEN_917 : ~(_T_1523 & _searcher_is_older_T_4) & _GEN_917) : _GEN_917; // @[util.scala:363:52]
wire _GEN_944 = _T_1507 ? (_GEN_942 ? ~_GEN_309 & _GEN_918 : ~(_T_1523 & _GEN_309) & _GEN_918) : _GEN_918; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_945 = _T_1507 ? (_GEN_942 ? ~_GEN_310 & _GEN_919 : ~(_T_1523 & _GEN_310) & _GEN_919) : _GEN_919; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_946 = _T_1507 ? (_GEN_942 ? ~_GEN_311 & _GEN_920 : ~(_T_1523 & _GEN_311) & _GEN_920) : _GEN_920; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_947 = _T_1507 ? (_GEN_942 ? ~_GEN_312 & _GEN_921 : ~(_T_1523 & _GEN_312) & _GEN_921) : _GEN_921; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_948 = _T_1507 ? (_GEN_942 ? ~_GEN_313 & _GEN_922 : ~(_T_1523 & _GEN_313) & _GEN_922) : _GEN_922; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_949 = _T_1507 ? (_GEN_942 ? ~_GEN_314 & _GEN_923 : ~(_T_1523 & _GEN_314) & _GEN_923) : _GEN_923; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_950 = _T_1507 ? (_GEN_942 ? ~_GEN_315 & _GEN_924 : ~(_T_1523 & _GEN_315) & _GEN_924) : _GEN_924; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_951 = _T_1507 ? (_GEN_942 ? ~_GEN_316 & _GEN_925 : ~(_T_1523 & _GEN_316) & _GEN_925) : _GEN_925; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_952 = _T_1507 ? (_GEN_942 ? ~_GEN_317 & _GEN_926 : ~(_T_1523 & _GEN_317) & _GEN_926) : _GEN_926; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_953 = _T_1507 ? (_GEN_942 ? ~_GEN_318 & _GEN_927 : ~(_T_1523 & _GEN_318) & _GEN_927) : _GEN_927; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_954 = _T_1507 ? (_GEN_942 ? ~_GEN_319 & _GEN_928 : ~(_T_1523 & _GEN_319) & _GEN_928) : _GEN_928; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_955 = _T_1507 ? (_GEN_942 ? ~_GEN_320 & _GEN_929 : ~(_T_1523 & _GEN_320) & _GEN_929) : _GEN_929; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_956 = _T_1507 ? (_GEN_942 ? ~_GEN_321 & _GEN_930 : ~(_T_1523 & _GEN_321) & _GEN_930) : _GEN_930; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_957 = _T_1507 ? (_GEN_942 ? ~_GEN_322 & _GEN_931 : ~(_T_1523 & _GEN_322) & _GEN_931) : _GEN_931; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_958 = _T_1507 ? (_GEN_942 ? ~_GEN_323 & _GEN_932 : ~(_T_1523 & _GEN_323) & _GEN_932) : _GEN_932; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_959 = _T_1507 ? (_GEN_942 ? ~_GEN_324 & _GEN_933 : ~(_T_1523 & _GEN_324) & _GEN_933) : _GEN_933; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_960 = _T_1507 ? (_GEN_942 ? ~_GEN_325 & _GEN_934 : ~(_T_1523 & _GEN_325) & _GEN_934) : _GEN_934; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_961 = _T_1507 ? (_GEN_942 ? ~_GEN_326 & _GEN_935 : ~(_T_1523 & _GEN_326) & _GEN_935) : _GEN_935; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_962 = _T_1507 ? (_GEN_942 ? ~_GEN_327 & _GEN_936 : ~(_T_1523 & _GEN_327) & _GEN_936) : _GEN_936; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_963 = _T_1507 ? (_GEN_942 ? ~_GEN_328 & _GEN_937 : ~(_T_1523 & _GEN_328) & _GEN_937) : _GEN_937; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_964 = _T_1507 ? (_GEN_942 ? ~_GEN_329 & _GEN_938 : ~(_T_1523 & _GEN_329) & _GEN_938) : _GEN_938; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_965 = _T_1507 ? (_GEN_942 ? ~_GEN_330 & _GEN_939 : ~(_T_1523 & _GEN_330) & _GEN_939) : _GEN_939; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_966 = _T_1507 ? (_GEN_942 ? ~_GEN_331 & _GEN_940 : ~(_T_1523 & _GEN_331) & _GEN_940) : _GEN_940; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_210 = ~stq_19_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_211 = stq_19_bits_addr_valid & _dword_addr_matches_T_210; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_212 = stq_19_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_214 = _dword_addr_matches_T_212 == _dword_addr_matches_T_213; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_215 = _dword_addr_matches_T_211 & _dword_addr_matches_T_214; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_43_0 = _dword_addr_matches_T_215; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_19; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_285 = stq_19_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_286 = stq_19_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_287 = 15'h1 << _write_mask_mask_T_286; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_288 = stq_19_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_289 = stq_19_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_290 = {_write_mask_mask_T_289, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_291 = 15'h3 << _write_mask_mask_T_290; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_292 = stq_19_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_293 = stq_19_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_294 = _write_mask_mask_T_293 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_295 = &stq_19_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_297 = _write_mask_mask_T_292 ? _write_mask_mask_T_294 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_298 = _write_mask_mask_T_288 ? _write_mask_mask_T_291 : {7'h0, _write_mask_mask_T_297}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_299 = _write_mask_mask_T_285 ? _write_mask_mask_T_287 : _write_mask_mask_T_298; // @[Mux.scala:126:16]
assign write_mask_19 = _write_mask_mask_T_299[7:0]; // @[Mux.scala:126:16]
wire _T_1528 = do_ld_search_0 & stq_19_valid & lcam_st_dep_mask_0[19]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1539 = lcam_mask_0 & write_mask_19; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1536 = _T_1539 == lcam_mask_0 & ~stq_19_bits_uop_is_fence & ~stq_19_bits_uop_is_amo & dword_addr_matches_43_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_19 = _T_1528 & _T_1536; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_81; // @[lsu.scala:1154:56]
wire _T_1541 = (|_T_1539) & dword_addr_matches_43_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_82; // @[lsu.scala:1160:56]
wire _T_1544 = stq_19_bits_uop_is_fence | stq_19_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_19 = _T_1528 & (_T_1536 | _T_1541 | _T_1544); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_83; // @[lsu.scala:1166:56]
wire _GEN_967 = _T_1528 ? (_T_1536 ? io_dmem_s1_kill_0_REG_81 : _T_1541 ? io_dmem_s1_kill_0_REG_82 : _T_1544 ? io_dmem_s1_kill_0_REG_83 : _GEN_941) : _GEN_941; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_968 = _T_1536 | _T_1541; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_969 = _T_1528 ? (_GEN_968 ? ~_searcher_is_older_T_4 & _GEN_943 : ~(_T_1544 & _searcher_is_older_T_4) & _GEN_943) : _GEN_943; // @[util.scala:363:52]
wire _GEN_970 = _T_1528 ? (_GEN_968 ? ~_GEN_309 & _GEN_944 : ~(_T_1544 & _GEN_309) & _GEN_944) : _GEN_944; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_971 = _T_1528 ? (_GEN_968 ? ~_GEN_310 & _GEN_945 : ~(_T_1544 & _GEN_310) & _GEN_945) : _GEN_945; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_972 = _T_1528 ? (_GEN_968 ? ~_GEN_311 & _GEN_946 : ~(_T_1544 & _GEN_311) & _GEN_946) : _GEN_946; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_973 = _T_1528 ? (_GEN_968 ? ~_GEN_312 & _GEN_947 : ~(_T_1544 & _GEN_312) & _GEN_947) : _GEN_947; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_974 = _T_1528 ? (_GEN_968 ? ~_GEN_313 & _GEN_948 : ~(_T_1544 & _GEN_313) & _GEN_948) : _GEN_948; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_975 = _T_1528 ? (_GEN_968 ? ~_GEN_314 & _GEN_949 : ~(_T_1544 & _GEN_314) & _GEN_949) : _GEN_949; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_976 = _T_1528 ? (_GEN_968 ? ~_GEN_315 & _GEN_950 : ~(_T_1544 & _GEN_315) & _GEN_950) : _GEN_950; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_977 = _T_1528 ? (_GEN_968 ? ~_GEN_316 & _GEN_951 : ~(_T_1544 & _GEN_316) & _GEN_951) : _GEN_951; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_978 = _T_1528 ? (_GEN_968 ? ~_GEN_317 & _GEN_952 : ~(_T_1544 & _GEN_317) & _GEN_952) : _GEN_952; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_979 = _T_1528 ? (_GEN_968 ? ~_GEN_318 & _GEN_953 : ~(_T_1544 & _GEN_318) & _GEN_953) : _GEN_953; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_980 = _T_1528 ? (_GEN_968 ? ~_GEN_319 & _GEN_954 : ~(_T_1544 & _GEN_319) & _GEN_954) : _GEN_954; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_981 = _T_1528 ? (_GEN_968 ? ~_GEN_320 & _GEN_955 : ~(_T_1544 & _GEN_320) & _GEN_955) : _GEN_955; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_982 = _T_1528 ? (_GEN_968 ? ~_GEN_321 & _GEN_956 : ~(_T_1544 & _GEN_321) & _GEN_956) : _GEN_956; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_983 = _T_1528 ? (_GEN_968 ? ~_GEN_322 & _GEN_957 : ~(_T_1544 & _GEN_322) & _GEN_957) : _GEN_957; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_984 = _T_1528 ? (_GEN_968 ? ~_GEN_323 & _GEN_958 : ~(_T_1544 & _GEN_323) & _GEN_958) : _GEN_958; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_985 = _T_1528 ? (_GEN_968 ? ~_GEN_324 & _GEN_959 : ~(_T_1544 & _GEN_324) & _GEN_959) : _GEN_959; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_986 = _T_1528 ? (_GEN_968 ? ~_GEN_325 & _GEN_960 : ~(_T_1544 & _GEN_325) & _GEN_960) : _GEN_960; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_987 = _T_1528 ? (_GEN_968 ? ~_GEN_326 & _GEN_961 : ~(_T_1544 & _GEN_326) & _GEN_961) : _GEN_961; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_988 = _T_1528 ? (_GEN_968 ? ~_GEN_327 & _GEN_962 : ~(_T_1544 & _GEN_327) & _GEN_962) : _GEN_962; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_989 = _T_1528 ? (_GEN_968 ? ~_GEN_328 & _GEN_963 : ~(_T_1544 & _GEN_328) & _GEN_963) : _GEN_963; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_990 = _T_1528 ? (_GEN_968 ? ~_GEN_329 & _GEN_964 : ~(_T_1544 & _GEN_329) & _GEN_964) : _GEN_964; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_991 = _T_1528 ? (_GEN_968 ? ~_GEN_330 & _GEN_965 : ~(_T_1544 & _GEN_330) & _GEN_965) : _GEN_965; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_992 = _T_1528 ? (_GEN_968 ? ~_GEN_331 & _GEN_966 : ~(_T_1544 & _GEN_331) & _GEN_966) : _GEN_966; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_216 = ~stq_20_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_217 = stq_20_bits_addr_valid & _dword_addr_matches_T_216; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_218 = stq_20_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_220 = _dword_addr_matches_T_218 == _dword_addr_matches_T_219; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_221 = _dword_addr_matches_T_217 & _dword_addr_matches_T_220; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_44_0 = _dword_addr_matches_T_221; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_20; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_300 = stq_20_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_301 = stq_20_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_302 = 15'h1 << _write_mask_mask_T_301; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_303 = stq_20_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_304 = stq_20_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_305 = {_write_mask_mask_T_304, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_306 = 15'h3 << _write_mask_mask_T_305; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_307 = stq_20_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_308 = stq_20_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_309 = _write_mask_mask_T_308 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_310 = &stq_20_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_312 = _write_mask_mask_T_307 ? _write_mask_mask_T_309 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_313 = _write_mask_mask_T_303 ? _write_mask_mask_T_306 : {7'h0, _write_mask_mask_T_312}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_314 = _write_mask_mask_T_300 ? _write_mask_mask_T_302 : _write_mask_mask_T_313; // @[Mux.scala:126:16]
assign write_mask_20 = _write_mask_mask_T_314[7:0]; // @[Mux.scala:126:16]
wire _T_1549 = do_ld_search_0 & stq_20_valid & lcam_st_dep_mask_0[20]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1560 = lcam_mask_0 & write_mask_20; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1557 = _T_1560 == lcam_mask_0 & ~stq_20_bits_uop_is_fence & ~stq_20_bits_uop_is_amo & dword_addr_matches_44_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_20 = _T_1549 & _T_1557; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_84; // @[lsu.scala:1154:56]
wire _T_1562 = (|_T_1560) & dword_addr_matches_44_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_85; // @[lsu.scala:1160:56]
wire _T_1565 = stq_20_bits_uop_is_fence | stq_20_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_20 = _T_1549 & (_T_1557 | _T_1562 | _T_1565); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_86; // @[lsu.scala:1166:56]
wire _GEN_993 = _T_1549 ? (_T_1557 ? io_dmem_s1_kill_0_REG_84 : _T_1562 ? io_dmem_s1_kill_0_REG_85 : _T_1565 ? io_dmem_s1_kill_0_REG_86 : _GEN_967) : _GEN_967; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_994 = _T_1557 | _T_1562; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_995 = _T_1549 ? (_GEN_994 ? ~_searcher_is_older_T_4 & _GEN_969 : ~(_T_1565 & _searcher_is_older_T_4) & _GEN_969) : _GEN_969; // @[util.scala:363:52]
wire _GEN_996 = _T_1549 ? (_GEN_994 ? ~_GEN_309 & _GEN_970 : ~(_T_1565 & _GEN_309) & _GEN_970) : _GEN_970; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_997 = _T_1549 ? (_GEN_994 ? ~_GEN_310 & _GEN_971 : ~(_T_1565 & _GEN_310) & _GEN_971) : _GEN_971; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_998 = _T_1549 ? (_GEN_994 ? ~_GEN_311 & _GEN_972 : ~(_T_1565 & _GEN_311) & _GEN_972) : _GEN_972; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_999 = _T_1549 ? (_GEN_994 ? ~_GEN_312 & _GEN_973 : ~(_T_1565 & _GEN_312) & _GEN_973) : _GEN_973; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1000 = _T_1549 ? (_GEN_994 ? ~_GEN_313 & _GEN_974 : ~(_T_1565 & _GEN_313) & _GEN_974) : _GEN_974; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1001 = _T_1549 ? (_GEN_994 ? ~_GEN_314 & _GEN_975 : ~(_T_1565 & _GEN_314) & _GEN_975) : _GEN_975; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1002 = _T_1549 ? (_GEN_994 ? ~_GEN_315 & _GEN_976 : ~(_T_1565 & _GEN_315) & _GEN_976) : _GEN_976; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1003 = _T_1549 ? (_GEN_994 ? ~_GEN_316 & _GEN_977 : ~(_T_1565 & _GEN_316) & _GEN_977) : _GEN_977; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1004 = _T_1549 ? (_GEN_994 ? ~_GEN_317 & _GEN_978 : ~(_T_1565 & _GEN_317) & _GEN_978) : _GEN_978; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1005 = _T_1549 ? (_GEN_994 ? ~_GEN_318 & _GEN_979 : ~(_T_1565 & _GEN_318) & _GEN_979) : _GEN_979; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1006 = _T_1549 ? (_GEN_994 ? ~_GEN_319 & _GEN_980 : ~(_T_1565 & _GEN_319) & _GEN_980) : _GEN_980; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1007 = _T_1549 ? (_GEN_994 ? ~_GEN_320 & _GEN_981 : ~(_T_1565 & _GEN_320) & _GEN_981) : _GEN_981; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1008 = _T_1549 ? (_GEN_994 ? ~_GEN_321 & _GEN_982 : ~(_T_1565 & _GEN_321) & _GEN_982) : _GEN_982; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1009 = _T_1549 ? (_GEN_994 ? ~_GEN_322 & _GEN_983 : ~(_T_1565 & _GEN_322) & _GEN_983) : _GEN_983; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1010 = _T_1549 ? (_GEN_994 ? ~_GEN_323 & _GEN_984 : ~(_T_1565 & _GEN_323) & _GEN_984) : _GEN_984; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1011 = _T_1549 ? (_GEN_994 ? ~_GEN_324 & _GEN_985 : ~(_T_1565 & _GEN_324) & _GEN_985) : _GEN_985; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1012 = _T_1549 ? (_GEN_994 ? ~_GEN_325 & _GEN_986 : ~(_T_1565 & _GEN_325) & _GEN_986) : _GEN_986; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1013 = _T_1549 ? (_GEN_994 ? ~_GEN_326 & _GEN_987 : ~(_T_1565 & _GEN_326) & _GEN_987) : _GEN_987; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1014 = _T_1549 ? (_GEN_994 ? ~_GEN_327 & _GEN_988 : ~(_T_1565 & _GEN_327) & _GEN_988) : _GEN_988; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1015 = _T_1549 ? (_GEN_994 ? ~_GEN_328 & _GEN_989 : ~(_T_1565 & _GEN_328) & _GEN_989) : _GEN_989; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1016 = _T_1549 ? (_GEN_994 ? ~_GEN_329 & _GEN_990 : ~(_T_1565 & _GEN_329) & _GEN_990) : _GEN_990; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1017 = _T_1549 ? (_GEN_994 ? ~_GEN_330 & _GEN_991 : ~(_T_1565 & _GEN_330) & _GEN_991) : _GEN_991; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1018 = _T_1549 ? (_GEN_994 ? ~_GEN_331 & _GEN_992 : ~(_T_1565 & _GEN_331) & _GEN_992) : _GEN_992; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_222 = ~stq_21_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_223 = stq_21_bits_addr_valid & _dword_addr_matches_T_222; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_224 = stq_21_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_226 = _dword_addr_matches_T_224 == _dword_addr_matches_T_225; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_227 = _dword_addr_matches_T_223 & _dword_addr_matches_T_226; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_45_0 = _dword_addr_matches_T_227; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_21; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_315 = stq_21_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_316 = stq_21_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_317 = 15'h1 << _write_mask_mask_T_316; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_318 = stq_21_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_319 = stq_21_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_320 = {_write_mask_mask_T_319, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_321 = 15'h3 << _write_mask_mask_T_320; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_322 = stq_21_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_323 = stq_21_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_324 = _write_mask_mask_T_323 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_325 = &stq_21_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_327 = _write_mask_mask_T_322 ? _write_mask_mask_T_324 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_328 = _write_mask_mask_T_318 ? _write_mask_mask_T_321 : {7'h0, _write_mask_mask_T_327}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_329 = _write_mask_mask_T_315 ? _write_mask_mask_T_317 : _write_mask_mask_T_328; // @[Mux.scala:126:16]
assign write_mask_21 = _write_mask_mask_T_329[7:0]; // @[Mux.scala:126:16]
wire _T_1570 = do_ld_search_0 & stq_21_valid & lcam_st_dep_mask_0[21]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1581 = lcam_mask_0 & write_mask_21; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1578 = _T_1581 == lcam_mask_0 & ~stq_21_bits_uop_is_fence & ~stq_21_bits_uop_is_amo & dword_addr_matches_45_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_21 = _T_1570 & _T_1578; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_87; // @[lsu.scala:1154:56]
wire _T_1583 = (|_T_1581) & dword_addr_matches_45_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_88; // @[lsu.scala:1160:56]
wire _T_1586 = stq_21_bits_uop_is_fence | stq_21_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_21 = _T_1570 & (_T_1578 | _T_1583 | _T_1586); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_89; // @[lsu.scala:1166:56]
wire _GEN_1019 = _T_1570 ? (_T_1578 ? io_dmem_s1_kill_0_REG_87 : _T_1583 ? io_dmem_s1_kill_0_REG_88 : _T_1586 ? io_dmem_s1_kill_0_REG_89 : _GEN_993) : _GEN_993; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_1020 = _T_1578 | _T_1583; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_1021 = _T_1570 ? (_GEN_1020 ? ~_searcher_is_older_T_4 & _GEN_995 : ~(_T_1586 & _searcher_is_older_T_4) & _GEN_995) : _GEN_995; // @[util.scala:363:52]
wire _GEN_1022 = _T_1570 ? (_GEN_1020 ? ~_GEN_309 & _GEN_996 : ~(_T_1586 & _GEN_309) & _GEN_996) : _GEN_996; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1023 = _T_1570 ? (_GEN_1020 ? ~_GEN_310 & _GEN_997 : ~(_T_1586 & _GEN_310) & _GEN_997) : _GEN_997; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1024 = _T_1570 ? (_GEN_1020 ? ~_GEN_311 & _GEN_998 : ~(_T_1586 & _GEN_311) & _GEN_998) : _GEN_998; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1025 = _T_1570 ? (_GEN_1020 ? ~_GEN_312 & _GEN_999 : ~(_T_1586 & _GEN_312) & _GEN_999) : _GEN_999; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1026 = _T_1570 ? (_GEN_1020 ? ~_GEN_313 & _GEN_1000 : ~(_T_1586 & _GEN_313) & _GEN_1000) : _GEN_1000; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1027 = _T_1570 ? (_GEN_1020 ? ~_GEN_314 & _GEN_1001 : ~(_T_1586 & _GEN_314) & _GEN_1001) : _GEN_1001; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1028 = _T_1570 ? (_GEN_1020 ? ~_GEN_315 & _GEN_1002 : ~(_T_1586 & _GEN_315) & _GEN_1002) : _GEN_1002; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1029 = _T_1570 ? (_GEN_1020 ? ~_GEN_316 & _GEN_1003 : ~(_T_1586 & _GEN_316) & _GEN_1003) : _GEN_1003; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1030 = _T_1570 ? (_GEN_1020 ? ~_GEN_317 & _GEN_1004 : ~(_T_1586 & _GEN_317) & _GEN_1004) : _GEN_1004; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1031 = _T_1570 ? (_GEN_1020 ? ~_GEN_318 & _GEN_1005 : ~(_T_1586 & _GEN_318) & _GEN_1005) : _GEN_1005; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1032 = _T_1570 ? (_GEN_1020 ? ~_GEN_319 & _GEN_1006 : ~(_T_1586 & _GEN_319) & _GEN_1006) : _GEN_1006; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1033 = _T_1570 ? (_GEN_1020 ? ~_GEN_320 & _GEN_1007 : ~(_T_1586 & _GEN_320) & _GEN_1007) : _GEN_1007; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1034 = _T_1570 ? (_GEN_1020 ? ~_GEN_321 & _GEN_1008 : ~(_T_1586 & _GEN_321) & _GEN_1008) : _GEN_1008; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1035 = _T_1570 ? (_GEN_1020 ? ~_GEN_322 & _GEN_1009 : ~(_T_1586 & _GEN_322) & _GEN_1009) : _GEN_1009; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1036 = _T_1570 ? (_GEN_1020 ? ~_GEN_323 & _GEN_1010 : ~(_T_1586 & _GEN_323) & _GEN_1010) : _GEN_1010; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1037 = _T_1570 ? (_GEN_1020 ? ~_GEN_324 & _GEN_1011 : ~(_T_1586 & _GEN_324) & _GEN_1011) : _GEN_1011; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1038 = _T_1570 ? (_GEN_1020 ? ~_GEN_325 & _GEN_1012 : ~(_T_1586 & _GEN_325) & _GEN_1012) : _GEN_1012; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1039 = _T_1570 ? (_GEN_1020 ? ~_GEN_326 & _GEN_1013 : ~(_T_1586 & _GEN_326) & _GEN_1013) : _GEN_1013; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1040 = _T_1570 ? (_GEN_1020 ? ~_GEN_327 & _GEN_1014 : ~(_T_1586 & _GEN_327) & _GEN_1014) : _GEN_1014; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1041 = _T_1570 ? (_GEN_1020 ? ~_GEN_328 & _GEN_1015 : ~(_T_1586 & _GEN_328) & _GEN_1015) : _GEN_1015; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1042 = _T_1570 ? (_GEN_1020 ? ~_GEN_329 & _GEN_1016 : ~(_T_1586 & _GEN_329) & _GEN_1016) : _GEN_1016; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1043 = _T_1570 ? (_GEN_1020 ? ~_GEN_330 & _GEN_1017 : ~(_T_1586 & _GEN_330) & _GEN_1017) : _GEN_1017; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1044 = _T_1570 ? (_GEN_1020 ? ~_GEN_331 & _GEN_1018 : ~(_T_1586 & _GEN_331) & _GEN_1018) : _GEN_1018; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_228 = ~stq_22_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_229 = stq_22_bits_addr_valid & _dword_addr_matches_T_228; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_230 = stq_22_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_232 = _dword_addr_matches_T_230 == _dword_addr_matches_T_231; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_233 = _dword_addr_matches_T_229 & _dword_addr_matches_T_232; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_46_0 = _dword_addr_matches_T_233; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_22; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_330 = stq_22_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_331 = stq_22_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_332 = 15'h1 << _write_mask_mask_T_331; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_333 = stq_22_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_334 = stq_22_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_335 = {_write_mask_mask_T_334, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_336 = 15'h3 << _write_mask_mask_T_335; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_337 = stq_22_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_338 = stq_22_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_339 = _write_mask_mask_T_338 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_340 = &stq_22_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_342 = _write_mask_mask_T_337 ? _write_mask_mask_T_339 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_343 = _write_mask_mask_T_333 ? _write_mask_mask_T_336 : {7'h0, _write_mask_mask_T_342}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_344 = _write_mask_mask_T_330 ? _write_mask_mask_T_332 : _write_mask_mask_T_343; // @[Mux.scala:126:16]
assign write_mask_22 = _write_mask_mask_T_344[7:0]; // @[Mux.scala:126:16]
wire _T_1591 = do_ld_search_0 & stq_22_valid & lcam_st_dep_mask_0[22]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1602 = lcam_mask_0 & write_mask_22; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1599 = _T_1602 == lcam_mask_0 & ~stq_22_bits_uop_is_fence & ~stq_22_bits_uop_is_amo & dword_addr_matches_46_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_22 = _T_1591 & _T_1599; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_90; // @[lsu.scala:1154:56]
wire _T_1604 = (|_T_1602) & dword_addr_matches_46_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_91; // @[lsu.scala:1160:56]
wire _T_1607 = stq_22_bits_uop_is_fence | stq_22_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_22 = _T_1591 & (_T_1599 | _T_1604 | _T_1607); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_92; // @[lsu.scala:1166:56]
wire _GEN_1045 = _T_1591 ? (_T_1599 ? io_dmem_s1_kill_0_REG_90 : _T_1604 ? io_dmem_s1_kill_0_REG_91 : _T_1607 ? io_dmem_s1_kill_0_REG_92 : _GEN_1019) : _GEN_1019; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_1046 = _T_1599 | _T_1604; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
wire _GEN_1047 = _T_1591 ? (_GEN_1046 ? ~_searcher_is_older_T_4 & _GEN_1021 : ~(_T_1607 & _searcher_is_older_T_4) & _GEN_1021) : _GEN_1021; // @[util.scala:363:52]
wire _GEN_1048 = _T_1591 ? (_GEN_1046 ? ~_GEN_309 & _GEN_1022 : ~(_T_1607 & _GEN_309) & _GEN_1022) : _GEN_1022; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1049 = _T_1591 ? (_GEN_1046 ? ~_GEN_310 & _GEN_1023 : ~(_T_1607 & _GEN_310) & _GEN_1023) : _GEN_1023; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1050 = _T_1591 ? (_GEN_1046 ? ~_GEN_311 & _GEN_1024 : ~(_T_1607 & _GEN_311) & _GEN_1024) : _GEN_1024; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1051 = _T_1591 ? (_GEN_1046 ? ~_GEN_312 & _GEN_1025 : ~(_T_1607 & _GEN_312) & _GEN_1025) : _GEN_1025; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1052 = _T_1591 ? (_GEN_1046 ? ~_GEN_313 & _GEN_1026 : ~(_T_1607 & _GEN_313) & _GEN_1026) : _GEN_1026; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1053 = _T_1591 ? (_GEN_1046 ? ~_GEN_314 & _GEN_1027 : ~(_T_1607 & _GEN_314) & _GEN_1027) : _GEN_1027; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1054 = _T_1591 ? (_GEN_1046 ? ~_GEN_315 & _GEN_1028 : ~(_T_1607 & _GEN_315) & _GEN_1028) : _GEN_1028; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1055 = _T_1591 ? (_GEN_1046 ? ~_GEN_316 & _GEN_1029 : ~(_T_1607 & _GEN_316) & _GEN_1029) : _GEN_1029; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1056 = _T_1591 ? (_GEN_1046 ? ~_GEN_317 & _GEN_1030 : ~(_T_1607 & _GEN_317) & _GEN_1030) : _GEN_1030; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1057 = _T_1591 ? (_GEN_1046 ? ~_GEN_318 & _GEN_1031 : ~(_T_1607 & _GEN_318) & _GEN_1031) : _GEN_1031; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1058 = _T_1591 ? (_GEN_1046 ? ~_GEN_319 & _GEN_1032 : ~(_T_1607 & _GEN_319) & _GEN_1032) : _GEN_1032; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1059 = _T_1591 ? (_GEN_1046 ? ~_GEN_320 & _GEN_1033 : ~(_T_1607 & _GEN_320) & _GEN_1033) : _GEN_1033; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1060 = _T_1591 ? (_GEN_1046 ? ~_GEN_321 & _GEN_1034 : ~(_T_1607 & _GEN_321) & _GEN_1034) : _GEN_1034; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1061 = _T_1591 ? (_GEN_1046 ? ~_GEN_322 & _GEN_1035 : ~(_T_1607 & _GEN_322) & _GEN_1035) : _GEN_1035; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1062 = _T_1591 ? (_GEN_1046 ? ~_GEN_323 & _GEN_1036 : ~(_T_1607 & _GEN_323) & _GEN_1036) : _GEN_1036; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1063 = _T_1591 ? (_GEN_1046 ? ~_GEN_324 & _GEN_1037 : ~(_T_1607 & _GEN_324) & _GEN_1037) : _GEN_1037; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1064 = _T_1591 ? (_GEN_1046 ? ~_GEN_325 & _GEN_1038 : ~(_T_1607 & _GEN_325) & _GEN_1038) : _GEN_1038; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1065 = _T_1591 ? (_GEN_1046 ? ~_GEN_326 & _GEN_1039 : ~(_T_1607 & _GEN_326) & _GEN_1039) : _GEN_1039; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1066 = _T_1591 ? (_GEN_1046 ? ~_GEN_327 & _GEN_1040 : ~(_T_1607 & _GEN_327) & _GEN_1040) : _GEN_1040; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1067 = _T_1591 ? (_GEN_1046 ? ~_GEN_328 & _GEN_1041 : ~(_T_1607 & _GEN_328) & _GEN_1041) : _GEN_1041; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1068 = _T_1591 ? (_GEN_1046 ? ~_GEN_329 & _GEN_1042 : ~(_T_1607 & _GEN_329) & _GEN_1042) : _GEN_1042; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1069 = _T_1591 ? (_GEN_1046 ? ~_GEN_330 & _GEN_1043 : ~(_T_1607 & _GEN_330) & _GEN_1043) : _GEN_1043; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _GEN_1070 = _T_1591 ? (_GEN_1046 ? ~_GEN_331 & _GEN_1044 : ~(_T_1607 & _GEN_331) & _GEN_1044) : _GEN_1044; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire _dword_addr_matches_T_234 = ~stq_23_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31]
wire _dword_addr_matches_T_235 = stq_23_bits_addr_valid & _dword_addr_matches_T_234; // @[lsu.scala:209:16, :1144:60, :1145:31]
wire [28:0] _dword_addr_matches_T_236 = stq_23_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38]
wire _dword_addr_matches_T_238 = _dword_addr_matches_T_236 == _dword_addr_matches_T_237; // @[lsu.scala:1146:{38,58,74}]
wire _dword_addr_matches_T_239 = _dword_addr_matches_T_235 & _dword_addr_matches_T_238; // @[lsu.scala:1144:60, :1145:60, :1146:58]
wire dword_addr_matches_47_0 = _dword_addr_matches_T_239; // @[lsu.scala:263:49, :1145:60]
wire [7:0] write_mask_23; // @[lsu.scala:1665:22]
wire _write_mask_mask_T_345 = stq_23_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26]
wire [2:0] _write_mask_mask_T_346 = stq_23_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55]
wire [14:0] _write_mask_mask_T_347 = 15'h1 << _write_mask_mask_T_346; // @[lsu.scala:1667:{48,55}]
wire _write_mask_mask_T_348 = stq_23_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26]
wire [1:0] _write_mask_mask_T_349 = stq_23_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56]
wire [2:0] _write_mask_mask_T_350 = {_write_mask_mask_T_349, 1'h0}; // @[lsu.scala:1668:{56,62}]
wire [14:0] _write_mask_mask_T_351 = 15'h3 << _write_mask_mask_T_350; // @[lsu.scala:1668:{48,62}]
wire _write_mask_mask_T_352 = stq_23_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26]
wire _write_mask_mask_T_353 = stq_23_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46]
wire [7:0] _write_mask_mask_T_354 = _write_mask_mask_T_353 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}]
wire _write_mask_mask_T_355 = &stq_23_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26]
wire [7:0] _write_mask_mask_T_357 = _write_mask_mask_T_352 ? _write_mask_mask_T_354 : 8'hFF; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_358 = _write_mask_mask_T_348 ? _write_mask_mask_T_351 : {7'h0, _write_mask_mask_T_357}; // @[Mux.scala:126:16]
wire [14:0] _write_mask_mask_T_359 = _write_mask_mask_T_345 ? _write_mask_mask_T_347 : _write_mask_mask_T_358; // @[Mux.scala:126:16]
assign write_mask_23 = _write_mask_mask_T_359[7:0]; // @[Mux.scala:126:16]
wire _T_1612 = do_ld_search_0 & stq_23_valid & lcam_st_dep_mask_0[23]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}]
wire [7:0] _T_1623 = lcam_mask_0 & write_mask_23; // @[lsu.scala:263:49, :1150:30, :1665:22]
wire _T_1620 = _T_1623 == lcam_mask_0 & ~stq_23_bits_uop_is_fence & ~stq_23_bits_uop_is_amo & dword_addr_matches_47_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}]
assign ldst_forward_matches_0_23 = _T_1612 & _T_1620; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46]
reg io_dmem_s1_kill_0_REG_93; // @[lsu.scala:1154:56]
wire _T_1625 = (|_T_1623) & dword_addr_matches_47_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}]
reg io_dmem_s1_kill_0_REG_94; // @[lsu.scala:1160:56]
wire _T_1628 = stq_23_bits_uop_is_fence | stq_23_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37]
assign ldst_addr_matches_0_23 = _T_1612 & (_T_1620 | _T_1625 | _T_1628); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46]
reg io_dmem_s1_kill_0_REG_95; // @[lsu.scala:1166:56]
assign io_dmem_s1_kill_0_0 = _T_1612 ? (_T_1620 ? io_dmem_s1_kill_0_REG_93 : _T_1625 ? io_dmem_s1_kill_0_REG_94 : _T_1628 ? io_dmem_s1_kill_0_REG_95 : _GEN_1045) : _GEN_1045; // @[lsu.scala:201:7, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}]
wire _GEN_1071 = _T_1620 | _T_1625; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9]
assign s1_set_execute_0 = _T_1612 ? (_GEN_1071 ? ~_searcher_is_older_T_4 & _GEN_1047 : ~(_T_1628 & _searcher_is_older_T_4) & _GEN_1047) : _GEN_1047; // @[util.scala:363:52]
assign s1_set_execute_1 = _T_1612 ? (_GEN_1071 ? ~_GEN_309 & _GEN_1048 : ~(_T_1628 & _GEN_309) & _GEN_1048) : _GEN_1048; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_2 = _T_1612 ? (_GEN_1071 ? ~_GEN_310 & _GEN_1049 : ~(_T_1628 & _GEN_310) & _GEN_1049) : _GEN_1049; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_3 = _T_1612 ? (_GEN_1071 ? ~_GEN_311 & _GEN_1050 : ~(_T_1628 & _GEN_311) & _GEN_1050) : _GEN_1050; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_4 = _T_1612 ? (_GEN_1071 ? ~_GEN_312 & _GEN_1051 : ~(_T_1628 & _GEN_312) & _GEN_1051) : _GEN_1051; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_5 = _T_1612 ? (_GEN_1071 ? ~_GEN_313 & _GEN_1052 : ~(_T_1628 & _GEN_313) & _GEN_1052) : _GEN_1052; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_6 = _T_1612 ? (_GEN_1071 ? ~_GEN_314 & _GEN_1053 : ~(_T_1628 & _GEN_314) & _GEN_1053) : _GEN_1053; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_7 = _T_1612 ? (_GEN_1071 ? ~_GEN_315 & _GEN_1054 : ~(_T_1628 & _GEN_315) & _GEN_1054) : _GEN_1054; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_8 = _T_1612 ? (_GEN_1071 ? ~_GEN_316 & _GEN_1055 : ~(_T_1628 & _GEN_316) & _GEN_1055) : _GEN_1055; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_9 = _T_1612 ? (_GEN_1071 ? ~_GEN_317 & _GEN_1056 : ~(_T_1628 & _GEN_317) & _GEN_1056) : _GEN_1056; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_10 = _T_1612 ? (_GEN_1071 ? ~_GEN_318 & _GEN_1057 : ~(_T_1628 & _GEN_318) & _GEN_1057) : _GEN_1057; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_11 = _T_1612 ? (_GEN_1071 ? ~_GEN_319 & _GEN_1058 : ~(_T_1628 & _GEN_319) & _GEN_1058) : _GEN_1058; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_12 = _T_1612 ? (_GEN_1071 ? ~_GEN_320 & _GEN_1059 : ~(_T_1628 & _GEN_320) & _GEN_1059) : _GEN_1059; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_13 = _T_1612 ? (_GEN_1071 ? ~_GEN_321 & _GEN_1060 : ~(_T_1628 & _GEN_321) & _GEN_1060) : _GEN_1060; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_14 = _T_1612 ? (_GEN_1071 ? ~_GEN_322 & _GEN_1061 : ~(_T_1628 & _GEN_322) & _GEN_1061) : _GEN_1061; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_15 = _T_1612 ? (_GEN_1071 ? ~_GEN_323 & _GEN_1062 : ~(_T_1628 & _GEN_323) & _GEN_1062) : _GEN_1062; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_16 = _T_1612 ? (_GEN_1071 ? ~_GEN_324 & _GEN_1063 : ~(_T_1628 & _GEN_324) & _GEN_1063) : _GEN_1063; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_17 = _T_1612 ? (_GEN_1071 ? ~_GEN_325 & _GEN_1064 : ~(_T_1628 & _GEN_325) & _GEN_1064) : _GEN_1064; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_18 = _T_1612 ? (_GEN_1071 ? ~_GEN_326 & _GEN_1065 : ~(_T_1628 & _GEN_326) & _GEN_1065) : _GEN_1065; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_19 = _T_1612 ? (_GEN_1071 ? ~_GEN_327 & _GEN_1066 : ~(_T_1628 & _GEN_327) & _GEN_1066) : _GEN_1066; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_20 = _T_1612 ? (_GEN_1071 ? ~_GEN_328 & _GEN_1067 : ~(_T_1628 & _GEN_328) & _GEN_1067) : _GEN_1067; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_21 = _T_1612 ? (_GEN_1071 ? ~_GEN_329 & _GEN_1068 : ~(_T_1628 & _GEN_329) & _GEN_1068) : _GEN_1068; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_22 = _T_1612 ? (_GEN_1071 ? ~_GEN_330 & _GEN_1069 : ~(_T_1628 & _GEN_330) & _GEN_1069) : _GEN_1069; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
assign s1_set_execute_23 = _T_1612 ? (_GEN_1071 ? ~_GEN_331 & _GEN_1070 : ~(_T_1628 & _GEN_331) & _GEN_1070) : _GEN_1070; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46]
wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_lo_lo_hi = {ldst_addr_matches_0_2, ldst_addr_matches_0_1}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_lo_lo = {forwarding_age_logic_0_io_addr_matches_lo_lo_lo_hi, ldst_addr_matches_0_0}; // @[lsu.scala:1050:38, :1181:72]
wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_lo_hi_hi = {ldst_addr_matches_0_5, ldst_addr_matches_0_4}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_lo_hi = {forwarding_age_logic_0_io_addr_matches_lo_lo_hi_hi, ldst_addr_matches_0_3}; // @[lsu.scala:1050:38, :1181:72]
wire [5:0] forwarding_age_logic_0_io_addr_matches_lo_lo = {forwarding_age_logic_0_io_addr_matches_lo_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo_lo}; // @[lsu.scala:1181:72]
wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_hi_lo_hi = {ldst_addr_matches_0_8, ldst_addr_matches_0_7}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_hi_lo = {forwarding_age_logic_0_io_addr_matches_lo_hi_lo_hi, ldst_addr_matches_0_6}; // @[lsu.scala:1050:38, :1181:72]
wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_hi_hi_hi = {ldst_addr_matches_0_11, ldst_addr_matches_0_10}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_hi_hi = {forwarding_age_logic_0_io_addr_matches_lo_hi_hi_hi, ldst_addr_matches_0_9}; // @[lsu.scala:1050:38, :1181:72]
wire [5:0] forwarding_age_logic_0_io_addr_matches_lo_hi = {forwarding_age_logic_0_io_addr_matches_lo_hi_hi, forwarding_age_logic_0_io_addr_matches_lo_hi_lo}; // @[lsu.scala:1181:72]
wire [11:0] forwarding_age_logic_0_io_addr_matches_lo = {forwarding_age_logic_0_io_addr_matches_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo}; // @[lsu.scala:1181:72]
wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_lo_lo_hi = {ldst_addr_matches_0_14, ldst_addr_matches_0_13}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_lo_lo = {forwarding_age_logic_0_io_addr_matches_hi_lo_lo_hi, ldst_addr_matches_0_12}; // @[lsu.scala:1050:38, :1181:72]
wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_lo_hi_hi = {ldst_addr_matches_0_17, ldst_addr_matches_0_16}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_lo_hi = {forwarding_age_logic_0_io_addr_matches_hi_lo_hi_hi, ldst_addr_matches_0_15}; // @[lsu.scala:1050:38, :1181:72]
wire [5:0] forwarding_age_logic_0_io_addr_matches_hi_lo = {forwarding_age_logic_0_io_addr_matches_hi_lo_hi, forwarding_age_logic_0_io_addr_matches_hi_lo_lo}; // @[lsu.scala:1181:72]
wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_hi_lo_hi = {ldst_addr_matches_0_20, ldst_addr_matches_0_19}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_hi_lo = {forwarding_age_logic_0_io_addr_matches_hi_hi_lo_hi, ldst_addr_matches_0_18}; // @[lsu.scala:1050:38, :1181:72]
wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_hi_hi_hi = {ldst_addr_matches_0_23, ldst_addr_matches_0_22}; // @[lsu.scala:1050:38, :1181:72]
wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_hi_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi_hi_hi, ldst_addr_matches_0_21}; // @[lsu.scala:1050:38, :1181:72]
wire [5:0] forwarding_age_logic_0_io_addr_matches_hi_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_hi_lo}; // @[lsu.scala:1181:72]
wire [11:0] forwarding_age_logic_0_io_addr_matches_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_lo}; // @[lsu.scala:1181:72]
wire [23:0] _forwarding_age_logic_0_io_addr_matches_T = {forwarding_age_logic_0_io_addr_matches_hi, forwarding_age_logic_0_io_addr_matches_lo}; // @[lsu.scala:1181:72]
assign mem_forward_stq_idx_0 = forwarding_idx_0; // @[lsu.scala:263:49, :1063:33]
wire [31:0] _GEN_1072 = {{ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_23}, {ldst_forward_matches_0_22}, {ldst_forward_matches_0_21}, {ldst_forward_matches_0_20}, {ldst_forward_matches_0_19}, {ldst_forward_matches_0_18}, {ldst_forward_matches_0_17}, {ldst_forward_matches_0_16}, {ldst_forward_matches_0_15}, {ldst_forward_matches_0_14}, {ldst_forward_matches_0_13}, {ldst_forward_matches_0_12}, {ldst_forward_matches_0_11}, {ldst_forward_matches_0_10}, {ldst_forward_matches_0_9}, {ldst_forward_matches_0_8}, {ldst_forward_matches_0_7}, {ldst_forward_matches_0_6}, {ldst_forward_matches_0_5}, {ldst_forward_matches_0_4}, {ldst_forward_matches_0_3}, {ldst_forward_matches_0_2}, {ldst_forward_matches_0_1}, {ldst_forward_matches_0_0}}; // @[lsu.scala:1052:38, :1188:86]
reg REG_1; // @[lsu.scala:1190:64]
assign mem_forward_valid_0 = _GEN_1072[forwarding_idx_0] & (io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask) == 16'h0 & ~io_core_exception_0 & ~REG_1; // @[util.scala:118:{51,59}]
reg REG_2; // @[lsu.scala:1200:18]
reg [3:0] store_blocked_counter; // @[lsu.scala:1205:36]
wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1205:36, :1209:58]
wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1205:36, :1209:96]
wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1209:96]
wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1209:{35,58,96}]
assign block_load_wakeup = (&store_blocked_counter) | REG_2; // @[lsu.scala:499:35, :1200:{18,80}, :1205:36, :1211:{33,43}, :1212:25]
wire _io_core_clr_unsafe_0_valid_T = do_st_search_0 | do_ld_search_0; // @[lsu.scala:263:49, :1221:61]
wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_wakeup_0; // @[lsu.scala:263:49, :1221:84]
wire _io_core_clr_unsafe_0_valid_T_2 = _io_core_clr_unsafe_0_valid_T & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:1221:{61,81,84}]
reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1221:43]
reg [6:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1222:43]
assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:201:7, :1222:43]
wire _temp_bits_T_1 = failed_loads_0 & _temp_bits_T; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_0 = _temp_bits_T_1; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_3 = failed_loads_1 & _temp_bits_T_2; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_1 = _temp_bits_T_3; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_5 = failed_loads_2 & _temp_bits_T_4; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_2 = _temp_bits_T_5; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_7 = failed_loads_3 & _temp_bits_T_6; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_3 = _temp_bits_T_7; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_9 = failed_loads_4 & _temp_bits_T_8; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_4 = _temp_bits_T_9; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_11 = failed_loads_5 & _temp_bits_T_10; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_5 = _temp_bits_T_11; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_13 = failed_loads_6 & _temp_bits_T_12; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_6 = _temp_bits_T_13; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_15 = failed_loads_7 & _temp_bits_T_14; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_7 = _temp_bits_T_15; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_17 = failed_loads_8 & _temp_bits_T_16; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_8 = _temp_bits_T_17; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_19 = failed_loads_9 & _temp_bits_T_18; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_9 = _temp_bits_T_19; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_21 = failed_loads_10 & _temp_bits_T_20; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_10 = _temp_bits_T_21; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_23 = failed_loads_11 & _temp_bits_T_22; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_11 = _temp_bits_T_23; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_25 = failed_loads_12 & _temp_bits_T_24; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_12 = _temp_bits_T_25; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_27 = failed_loads_13 & _temp_bits_T_26; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_13 = _temp_bits_T_27; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_29 = failed_loads_14 & _temp_bits_T_28; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_14 = _temp_bits_T_29; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_30 = ~_searcher_is_older_T_63; // @[util.scala:351:72, :363:78]
wire _temp_bits_T_31 = failed_loads_15 & _temp_bits_T_30; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_15 = _temp_bits_T_31; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_33 = failed_loads_16 & _temp_bits_T_32; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_16 = _temp_bits_T_33; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_35 = failed_loads_17 & _temp_bits_T_34; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_17 = _temp_bits_T_35; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_37 = failed_loads_18 & _temp_bits_T_36; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_18 = _temp_bits_T_37; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_39 = failed_loads_19 & _temp_bits_T_38; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_19 = _temp_bits_T_39; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_41 = failed_loads_20 & _temp_bits_T_40; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_20 = _temp_bits_T_41; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_43 = failed_loads_21 & _temp_bits_T_42; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_21 = _temp_bits_T_43; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_45 = failed_loads_22 & _temp_bits_T_44; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_22 = _temp_bits_T_45; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_T_47 = failed_loads_23 & _temp_bits_T_46; // @[lsu.scala:1054:34, :1230:{21,28}]
wire _temp_bits_WIRE_23 = _temp_bits_T_47; // @[lsu.scala:1229:59, :1230:21]
wire _temp_bits_WIRE_1_0 = _temp_bits_WIRE_0; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_1 = _temp_bits_WIRE_1; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_2 = _temp_bits_WIRE_2; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_3 = _temp_bits_WIRE_3; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_4 = _temp_bits_WIRE_4; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_5 = _temp_bits_WIRE_5; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_6 = _temp_bits_WIRE_6; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_7 = _temp_bits_WIRE_7; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_8 = _temp_bits_WIRE_8; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_9 = _temp_bits_WIRE_9; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_10 = _temp_bits_WIRE_10; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_11 = _temp_bits_WIRE_11; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_12 = _temp_bits_WIRE_12; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_13 = _temp_bits_WIRE_13; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_14 = _temp_bits_WIRE_14; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_15 = _temp_bits_WIRE_15; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_16 = _temp_bits_WIRE_16; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_17 = _temp_bits_WIRE_17; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_18 = _temp_bits_WIRE_18; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_19 = _temp_bits_WIRE_19; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_20 = _temp_bits_WIRE_20; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_21 = _temp_bits_WIRE_21; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_22 = _temp_bits_WIRE_22; // @[lsu.scala:1229:{27,59}]
wire _temp_bits_WIRE_1_23 = _temp_bits_WIRE_23; // @[lsu.scala:1229:{27,59}]
wire [1:0] temp_bits_lo_lo_lo_lo_hi = {_temp_bits_WIRE_1_2, _temp_bits_WIRE_1_1}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_lo_lo_lo = {temp_bits_lo_lo_lo_lo_hi, _temp_bits_WIRE_1_0}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_lo_lo_lo_hi_hi = {_temp_bits_WIRE_1_5, _temp_bits_WIRE_1_4}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_lo_lo_hi = {temp_bits_lo_lo_lo_hi_hi, _temp_bits_WIRE_1_3}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_lo_lo_lo = {temp_bits_lo_lo_lo_hi, temp_bits_lo_lo_lo_lo}; // @[lsu.scala:1230:59]
wire [1:0] temp_bits_lo_lo_hi_lo_hi = {_temp_bits_WIRE_1_8, _temp_bits_WIRE_1_7}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_lo_hi_lo = {temp_bits_lo_lo_hi_lo_hi, _temp_bits_WIRE_1_6}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_lo_lo_hi_hi_hi = {_temp_bits_WIRE_1_11, _temp_bits_WIRE_1_10}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_lo_hi_hi = {temp_bits_lo_lo_hi_hi_hi, _temp_bits_WIRE_1_9}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_lo_lo_hi = {temp_bits_lo_lo_hi_hi, temp_bits_lo_lo_hi_lo}; // @[lsu.scala:1230:59]
wire [11:0] temp_bits_lo_lo = {temp_bits_lo_lo_hi, temp_bits_lo_lo_lo}; // @[lsu.scala:1230:59]
wire [1:0] temp_bits_lo_hi_lo_lo_hi = {_temp_bits_WIRE_1_14, _temp_bits_WIRE_1_13}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_hi_lo_lo = {temp_bits_lo_hi_lo_lo_hi, _temp_bits_WIRE_1_12}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_lo_hi_lo_hi_hi = {_temp_bits_WIRE_1_17, _temp_bits_WIRE_1_16}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_hi_lo_hi = {temp_bits_lo_hi_lo_hi_hi, _temp_bits_WIRE_1_15}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_lo_hi_lo = {temp_bits_lo_hi_lo_hi, temp_bits_lo_hi_lo_lo}; // @[lsu.scala:1230:59]
wire [1:0] temp_bits_lo_hi_hi_lo_hi = {_temp_bits_WIRE_1_20, _temp_bits_WIRE_1_19}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_hi_hi_lo = {temp_bits_lo_hi_hi_lo_hi, _temp_bits_WIRE_1_18}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_lo_hi_hi_hi_hi = {_temp_bits_WIRE_1_23, _temp_bits_WIRE_1_22}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_lo_hi_hi_hi = {temp_bits_lo_hi_hi_hi_hi, _temp_bits_WIRE_1_21}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_lo_hi_hi = {temp_bits_lo_hi_hi_hi, temp_bits_lo_hi_hi_lo}; // @[lsu.scala:1230:59]
wire [11:0] temp_bits_lo_hi = {temp_bits_lo_hi_hi, temp_bits_lo_hi_lo}; // @[lsu.scala:1230:59]
wire [23:0] temp_bits_lo = {temp_bits_lo_hi, temp_bits_lo_lo}; // @[lsu.scala:1230:59]
wire [1:0] temp_bits_hi_lo_lo_lo_hi = {_temp_bits_WIRE_1_26, _temp_bits_WIRE_1_25}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_lo_lo_lo = {temp_bits_hi_lo_lo_lo_hi, _temp_bits_WIRE_1_24}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_hi_lo_lo_hi_hi = {_temp_bits_WIRE_1_29, _temp_bits_WIRE_1_28}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_lo_lo_hi = {temp_bits_hi_lo_lo_hi_hi, _temp_bits_WIRE_1_27}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_hi_lo_lo = {temp_bits_hi_lo_lo_hi, temp_bits_hi_lo_lo_lo}; // @[lsu.scala:1230:59]
wire [1:0] temp_bits_hi_lo_hi_lo_hi = {_temp_bits_WIRE_1_32, _temp_bits_WIRE_1_31}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_lo_hi_lo = {temp_bits_hi_lo_hi_lo_hi, _temp_bits_WIRE_1_30}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_hi_lo_hi_hi_hi = {_temp_bits_WIRE_1_35, _temp_bits_WIRE_1_34}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_lo_hi_hi = {temp_bits_hi_lo_hi_hi_hi, _temp_bits_WIRE_1_33}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_hi_lo_hi = {temp_bits_hi_lo_hi_hi, temp_bits_hi_lo_hi_lo}; // @[lsu.scala:1230:59]
wire [11:0] temp_bits_hi_lo = {temp_bits_hi_lo_hi, temp_bits_hi_lo_lo}; // @[lsu.scala:1230:59]
wire [1:0] temp_bits_hi_hi_lo_lo_hi = {_temp_bits_WIRE_1_38, _temp_bits_WIRE_1_37}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_hi_lo_lo = {temp_bits_hi_hi_lo_lo_hi, _temp_bits_WIRE_1_36}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_hi_hi_lo_hi_hi = {_temp_bits_WIRE_1_41, _temp_bits_WIRE_1_40}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_hi_lo_hi = {temp_bits_hi_hi_lo_hi_hi, _temp_bits_WIRE_1_39}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_hi_hi_lo = {temp_bits_hi_hi_lo_hi, temp_bits_hi_hi_lo_lo}; // @[lsu.scala:1230:59]
wire [1:0] temp_bits_hi_hi_hi_lo_hi = {_temp_bits_WIRE_1_44, _temp_bits_WIRE_1_43}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_hi_hi_lo = {temp_bits_hi_hi_hi_lo_hi, _temp_bits_WIRE_1_42}; // @[lsu.scala:1229:27, :1230:59]
wire [1:0] temp_bits_hi_hi_hi_hi_hi = {_temp_bits_WIRE_1_47, _temp_bits_WIRE_1_46}; // @[lsu.scala:1229:27, :1230:59]
wire [2:0] temp_bits_hi_hi_hi_hi = {temp_bits_hi_hi_hi_hi_hi, _temp_bits_WIRE_1_45}; // @[lsu.scala:1229:27, :1230:59]
wire [5:0] temp_bits_hi_hi_hi = {temp_bits_hi_hi_hi_hi, temp_bits_hi_hi_hi_lo}; // @[lsu.scala:1230:59]
wire [11:0] temp_bits_hi_hi = {temp_bits_hi_hi_hi, temp_bits_hi_hi_lo}; // @[lsu.scala:1230:59]
wire [23:0] temp_bits_hi = {temp_bits_hi_hi, temp_bits_hi_lo}; // @[lsu.scala:1230:59]
wire [47:0] temp_bits = {temp_bits_hi, temp_bits_lo}; // @[lsu.scala:1230:59]
wire _l_idx_T = temp_bits[0]; // @[OneHot.scala:48:45]
wire _l_idx_T_1 = temp_bits[1]; // @[OneHot.scala:48:45]
wire _l_idx_T_2 = temp_bits[2]; // @[OneHot.scala:48:45]
wire _l_idx_T_3 = temp_bits[3]; // @[OneHot.scala:48:45]
wire _l_idx_T_4 = temp_bits[4]; // @[OneHot.scala:48:45]
wire _l_idx_T_5 = temp_bits[5]; // @[OneHot.scala:48:45]
wire _l_idx_T_6 = temp_bits[6]; // @[OneHot.scala:48:45]
wire _l_idx_T_7 = temp_bits[7]; // @[OneHot.scala:48:45]
wire _l_idx_T_8 = temp_bits[8]; // @[OneHot.scala:48:45]
wire _l_idx_T_9 = temp_bits[9]; // @[OneHot.scala:48:45]
wire _l_idx_T_10 = temp_bits[10]; // @[OneHot.scala:48:45]
wire _l_idx_T_11 = temp_bits[11]; // @[OneHot.scala:48:45]
wire _l_idx_T_12 = temp_bits[12]; // @[OneHot.scala:48:45]
wire _l_idx_T_13 = temp_bits[13]; // @[OneHot.scala:48:45]
wire _l_idx_T_14 = temp_bits[14]; // @[OneHot.scala:48:45]
wire _l_idx_T_15 = temp_bits[15]; // @[OneHot.scala:48:45]
wire _l_idx_T_16 = temp_bits[16]; // @[OneHot.scala:48:45]
wire _l_idx_T_17 = temp_bits[17]; // @[OneHot.scala:48:45]
wire _l_idx_T_18 = temp_bits[18]; // @[OneHot.scala:48:45]
wire _l_idx_T_19 = temp_bits[19]; // @[OneHot.scala:48:45]
wire _l_idx_T_20 = temp_bits[20]; // @[OneHot.scala:48:45]
wire _l_idx_T_21 = temp_bits[21]; // @[OneHot.scala:48:45]
wire _l_idx_T_22 = temp_bits[22]; // @[OneHot.scala:48:45]
wire _l_idx_T_23 = temp_bits[23]; // @[OneHot.scala:48:45]
wire _l_idx_T_24 = temp_bits[24]; // @[OneHot.scala:48:45]
wire _l_idx_T_25 = temp_bits[25]; // @[OneHot.scala:48:45]
wire _l_idx_T_26 = temp_bits[26]; // @[OneHot.scala:48:45]
wire _l_idx_T_27 = temp_bits[27]; // @[OneHot.scala:48:45]
wire _l_idx_T_28 = temp_bits[28]; // @[OneHot.scala:48:45]
wire _l_idx_T_29 = temp_bits[29]; // @[OneHot.scala:48:45]
wire _l_idx_T_30 = temp_bits[30]; // @[OneHot.scala:48:45]
wire _l_idx_T_31 = temp_bits[31]; // @[OneHot.scala:48:45]
wire _l_idx_T_32 = temp_bits[32]; // @[OneHot.scala:48:45]
wire _l_idx_T_33 = temp_bits[33]; // @[OneHot.scala:48:45]
wire _l_idx_T_34 = temp_bits[34]; // @[OneHot.scala:48:45]
wire _l_idx_T_35 = temp_bits[35]; // @[OneHot.scala:48:45]
wire _l_idx_T_36 = temp_bits[36]; // @[OneHot.scala:48:45]
wire _l_idx_T_37 = temp_bits[37]; // @[OneHot.scala:48:45]
wire _l_idx_T_38 = temp_bits[38]; // @[OneHot.scala:48:45]
wire _l_idx_T_39 = temp_bits[39]; // @[OneHot.scala:48:45]
wire _l_idx_T_40 = temp_bits[40]; // @[OneHot.scala:48:45]
wire _l_idx_T_41 = temp_bits[41]; // @[OneHot.scala:48:45]
wire _l_idx_T_42 = temp_bits[42]; // @[OneHot.scala:48:45]
wire _l_idx_T_43 = temp_bits[43]; // @[OneHot.scala:48:45]
wire _l_idx_T_44 = temp_bits[44]; // @[OneHot.scala:48:45]
wire _l_idx_T_45 = temp_bits[45]; // @[OneHot.scala:48:45]
wire _l_idx_T_46 = temp_bits[46]; // @[OneHot.scala:48:45]
wire _l_idx_T_47 = temp_bits[47]; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_48 = {5'h17, ~_l_idx_T_46}; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_49 = _l_idx_T_45 ? 6'h2D : _l_idx_T_48; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_50 = _l_idx_T_44 ? 6'h2C : _l_idx_T_49; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_51 = _l_idx_T_43 ? 6'h2B : _l_idx_T_50; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_52 = _l_idx_T_42 ? 6'h2A : _l_idx_T_51; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_53 = _l_idx_T_41 ? 6'h29 : _l_idx_T_52; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_54 = _l_idx_T_40 ? 6'h28 : _l_idx_T_53; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_55 = _l_idx_T_39 ? 6'h27 : _l_idx_T_54; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_56 = _l_idx_T_38 ? 6'h26 : _l_idx_T_55; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_57 = _l_idx_T_37 ? 6'h25 : _l_idx_T_56; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_58 = _l_idx_T_36 ? 6'h24 : _l_idx_T_57; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_59 = _l_idx_T_35 ? 6'h23 : _l_idx_T_58; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_60 = _l_idx_T_34 ? 6'h22 : _l_idx_T_59; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_61 = _l_idx_T_33 ? 6'h21 : _l_idx_T_60; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_62 = _l_idx_T_32 ? 6'h20 : _l_idx_T_61; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_63 = _l_idx_T_31 ? 6'h1F : _l_idx_T_62; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_64 = _l_idx_T_30 ? 6'h1E : _l_idx_T_63; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_65 = _l_idx_T_29 ? 6'h1D : _l_idx_T_64; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_66 = _l_idx_T_28 ? 6'h1C : _l_idx_T_65; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_67 = _l_idx_T_27 ? 6'h1B : _l_idx_T_66; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_68 = _l_idx_T_26 ? 6'h1A : _l_idx_T_67; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_69 = _l_idx_T_25 ? 6'h19 : _l_idx_T_68; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_70 = _l_idx_T_24 ? 6'h18 : _l_idx_T_69; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_71 = _l_idx_T_23 ? 6'h17 : _l_idx_T_70; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_72 = _l_idx_T_22 ? 6'h16 : _l_idx_T_71; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_73 = _l_idx_T_21 ? 6'h15 : _l_idx_T_72; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_74 = _l_idx_T_20 ? 6'h14 : _l_idx_T_73; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_75 = _l_idx_T_19 ? 6'h13 : _l_idx_T_74; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_76 = _l_idx_T_18 ? 6'h12 : _l_idx_T_75; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_77 = _l_idx_T_17 ? 6'h11 : _l_idx_T_76; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_78 = _l_idx_T_16 ? 6'h10 : _l_idx_T_77; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_79 = _l_idx_T_15 ? 6'hF : _l_idx_T_78; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_80 = _l_idx_T_14 ? 6'hE : _l_idx_T_79; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_81 = _l_idx_T_13 ? 6'hD : _l_idx_T_80; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_82 = _l_idx_T_12 ? 6'hC : _l_idx_T_81; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_83 = _l_idx_T_11 ? 6'hB : _l_idx_T_82; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_84 = _l_idx_T_10 ? 6'hA : _l_idx_T_83; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_85 = _l_idx_T_9 ? 6'h9 : _l_idx_T_84; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_86 = _l_idx_T_8 ? 6'h8 : _l_idx_T_85; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_87 = _l_idx_T_7 ? 6'h7 : _l_idx_T_86; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_88 = _l_idx_T_6 ? 6'h6 : _l_idx_T_87; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_89 = _l_idx_T_5 ? 6'h5 : _l_idx_T_88; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_90 = _l_idx_T_4 ? 6'h4 : _l_idx_T_89; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_91 = _l_idx_T_3 ? 6'h3 : _l_idx_T_90; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_92 = _l_idx_T_2 ? 6'h2 : _l_idx_T_91; // @[OneHot.scala:48:45]
wire [5:0] _l_idx_T_93 = _l_idx_T_1 ? 6'h1 : _l_idx_T_92; // @[OneHot.scala:48:45]
wire [5:0] l_idx = _l_idx_T ? 6'h0 : _l_idx_T_93; // @[OneHot.scala:48:45]
reg r_xcpt_valid; // @[lsu.scala:1236:29]
reg [6:0] r_xcpt_uop_uopc; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_uopc_0 = r_xcpt_uop_uopc; // @[lsu.scala:201:7, :1237:25]
reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:201:7, :1237:25]
reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_rvc; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:201:7, :1237:25]
reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:201:7, :1237:25]
reg [2:0] r_xcpt_uop_iq_type; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_iq_type_0 = r_xcpt_uop_iq_type; // @[lsu.scala:201:7, :1237:25]
reg [9:0] r_xcpt_uop_fu_code; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_fu_code_0 = r_xcpt_uop_fu_code; // @[lsu.scala:201:7, :1237:25]
reg [3:0] r_xcpt_uop_ctrl_br_type; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_br_type_0 = r_xcpt_uop_ctrl_br_type; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_op1_sel_0 = r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :1237:25]
reg [2:0] r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_op2_sel_0 = r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :1237:25]
reg [2:0] r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_imm_sel_0 = r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :1237:25]
reg [4:0] r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_op_fcn_0 = r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_fcn_dw_0 = r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :1237:25]
reg [2:0] r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_csr_cmd_0 = r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_ctrl_is_load; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_is_load_0 = r_xcpt_uop_ctrl_is_load; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_is_sta_0 = r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_ctrl_is_std; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ctrl_is_std_0 = r_xcpt_uop_ctrl_is_std; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_iw_state; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_iw_state_0 = r_xcpt_uop_iw_state; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_iw_p1_poisoned_0 = r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_iw_p2_poisoned_0 = r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_br; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_br_0 = r_xcpt_uop_is_br; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_jalr; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_jalr_0 = r_xcpt_uop_is_jalr; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_jal; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_jal_0 = r_xcpt_uop_is_jal; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_sfb; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:201:7, :1237:25]
reg [15:0] r_xcpt_uop_br_mask; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:201:7, :1237:25]
reg [3:0] r_xcpt_uop_br_tag; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:201:7, :1237:25]
reg [4:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_edge_inst; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:201:7, :1237:25]
reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_taken; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:201:7, :1237:25]
reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:201:7, :1237:25]
reg [11:0] r_xcpt_uop_csr_addr; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_csr_addr_0 = r_xcpt_uop_csr_addr; // @[lsu.scala:201:7, :1237:25]
reg [6:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:201:7, :1237:25]
reg [4:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:201:7, :1237:25]
reg [4:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:201:7, :1237:25]
reg [6:0] r_xcpt_uop_pdst; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:201:7, :1237:25]
reg [6:0] r_xcpt_uop_prs1; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:201:7, :1237:25]
reg [6:0] r_xcpt_uop_prs2; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:201:7, :1237:25]
reg [6:0] r_xcpt_uop_prs3; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:201:7, :1237:25]
reg [4:0] r_xcpt_uop_ppred; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:201:7, :1237:25]
reg [6:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_exception; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:201:7, :1237:25]
reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_bypassable; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_bypassable_0 = r_xcpt_uop_bypassable; // @[lsu.scala:201:7, :1237:25]
reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_mem_signed; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_fence; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_fencei; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_amo; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_uses_stq; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_is_unique; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:201:7, :1237:25]
reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:201:7, :1237:25]
reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:201:7, :1237:25]
reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:201:7, :1237:25]
reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_ldst_val; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_ldst_val_0 = r_xcpt_uop_ldst_val; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_frs3_en; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_fp_val; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_fp_single; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_fp_single_0 = r_xcpt_uop_fp_single; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:201:7, :1237:25]
reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:201:7, :1237:25]
reg [1:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:201:7, :1237:25]
reg [4:0] r_xcpt_cause; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:201:7, :1237:25]
reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1237:25]
assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:201:7, :1237:25]
wire _ld_xcpt_valid_T = failed_loads_0 | failed_loads_1; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_1 = _ld_xcpt_valid_T | failed_loads_2; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T_1 | failed_loads_3; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_3 = _ld_xcpt_valid_T_2 | failed_loads_4; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_4 = _ld_xcpt_valid_T_3 | failed_loads_5; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_5 = _ld_xcpt_valid_T_4 | failed_loads_6; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_6 = _ld_xcpt_valid_T_5 | failed_loads_7; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_7 = _ld_xcpt_valid_T_6 | failed_loads_8; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_8 = _ld_xcpt_valid_T_7 | failed_loads_9; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_9 = _ld_xcpt_valid_T_8 | failed_loads_10; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_10 = _ld_xcpt_valid_T_9 | failed_loads_11; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_11 = _ld_xcpt_valid_T_10 | failed_loads_12; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_12 = _ld_xcpt_valid_T_11 | failed_loads_13; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_13 = _ld_xcpt_valid_T_12 | failed_loads_14; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_14 = _ld_xcpt_valid_T_13 | failed_loads_15; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_15 = _ld_xcpt_valid_T_14 | failed_loads_16; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_16 = _ld_xcpt_valid_T_15 | failed_loads_17; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_17 = _ld_xcpt_valid_T_16 | failed_loads_18; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_18 = _ld_xcpt_valid_T_17 | failed_loads_19; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_19 = _ld_xcpt_valid_T_18 | failed_loads_20; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_20 = _ld_xcpt_valid_T_19 | failed_loads_21; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_valid_T_21 = _ld_xcpt_valid_T_20 | failed_loads_22; // @[lsu.scala:1054:34, :1239:44]
wire ld_xcpt_valid = _ld_xcpt_valid_T_21 | failed_loads_23; // @[lsu.scala:1054:34, :1239:44]
wire _ld_xcpt_uop_T = l_idx > 6'h17; // @[Mux.scala:50:70]
wire [6:0] _ld_xcpt_uop_T_1 = {1'h0, l_idx} - 7'h18; // @[Mux.scala:50:70]
wire [5:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[5:0]; // @[lsu.scala:1240:63]
wire [5:0] _ld_xcpt_uop_T_3 = _ld_xcpt_uop_T ? _ld_xcpt_uop_T_2 : l_idx; // @[Mux.scala:50:70]
wire [4:0] _ld_xcpt_uop_T_4 = _ld_xcpt_uop_T_3[4:0]; // @[lsu.scala:1240:30]
wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < _GEN_133[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:363:64]
wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:363:{52,58,64}]
wire _use_mem_xcpt_T_3 = _GEN_133[_ld_xcpt_uop_T_4] < io_core_rob_head_idx_0; // @[util.scala:363:{52,78}]
wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:363:{58,72,78}]
wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:363:72]
wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1239:44, :1242:118]
wire use_mem_xcpt = _use_mem_xcpt_T_5 | _use_mem_xcpt_T_6; // @[lsu.scala:1242:{38,115,118}]
wire [6:0] xcpt_uop_uopc = use_mem_xcpt ? mem_xcpt_uop_uopc : _GEN_101[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : _GEN_102[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : _GEN_103[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : _GEN_104[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : _GEN_105[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [2:0] xcpt_uop_iq_type = use_mem_xcpt ? mem_xcpt_uop_iq_type : _GEN_106[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [9:0] xcpt_uop_fu_code = use_mem_xcpt ? mem_xcpt_uop_fu_code : _GEN_107[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [3:0] xcpt_uop_ctrl_br_type = use_mem_xcpt ? mem_xcpt_uop_ctrl_br_type : _GEN_108[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_ctrl_op1_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op1_sel : _GEN_109[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [2:0] xcpt_uop_ctrl_op2_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op2_sel : _GEN_110[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [2:0] xcpt_uop_ctrl_imm_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_imm_sel : _GEN_111[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [4:0] xcpt_uop_ctrl_op_fcn = use_mem_xcpt ? mem_xcpt_uop_ctrl_op_fcn : _GEN_112[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_ctrl_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_ctrl_fcn_dw : _GEN_113[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [2:0] xcpt_uop_ctrl_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_ctrl_csr_cmd : _GEN_114[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_ctrl_is_load = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_load : _GEN_115[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_ctrl_is_sta = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_sta : _GEN_116[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_ctrl_is_std = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_std : _GEN_117[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_iw_state = use_mem_xcpt ? mem_xcpt_uop_iw_state : _GEN_118[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_iw_p1_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p1_poisoned : _GEN_119[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_iw_p2_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p2_poisoned : _GEN_120[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_br = use_mem_xcpt ? mem_xcpt_uop_is_br : _GEN_121[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_jalr = use_mem_xcpt ? mem_xcpt_uop_is_jalr : _GEN_122[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_jal = use_mem_xcpt ? mem_xcpt_uop_is_jal : _GEN_123[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : _GEN_124[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [15:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : _GEN_125[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [3:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : _GEN_126[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [4:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : _GEN_127[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : _GEN_128[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : _GEN_129[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : _GEN_130[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : _GEN_131[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [11:0] xcpt_uop_csr_addr = use_mem_xcpt ? mem_xcpt_uop_csr_addr : _GEN_132[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [6:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : _GEN_133[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [4:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : _GEN_134[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [4:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : _GEN_135[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : _GEN_136[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [6:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : _GEN_137[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [6:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : _GEN_138[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [6:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : _GEN_139[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [6:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : _GEN_140[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [4:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : 5'h0; // @[lsu.scala:360:29, :1242:115, :1244:21]
wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : _GEN_141[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : _GEN_142[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : _GEN_143[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_ppred_busy = use_mem_xcpt & mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29, :1242:115, :1244:21]
wire [6:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : _GEN_144[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : _GEN_145[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : _GEN_146[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_bypassable = use_mem_xcpt ? mem_xcpt_uop_bypassable : _GEN_147[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : _GEN_148[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : _GEN_149[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : _GEN_150[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : _GEN_151[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : _GEN_152[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : _GEN_153[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : _GEN_154[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : _GEN_155[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : _GEN_156[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : _GEN_157[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : _GEN_158[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : _GEN_159[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : _GEN_160[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : _GEN_161[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : _GEN_162[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : _GEN_163[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_ldst_val = use_mem_xcpt ? mem_xcpt_uop_ldst_val : _GEN_164[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : _GEN_165[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : _GEN_166[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : _GEN_167[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : _GEN_168[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : _GEN_169[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_fp_single = use_mem_xcpt ? mem_xcpt_uop_fp_single : _GEN_170[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : _GEN_171[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : _GEN_172[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : _GEN_173[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : _GEN_174[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : _GEN_175[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : _GEN_176[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire [1:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : _GEN_177[_ld_xcpt_uop_T_4]; // @[util.scala:363:52]
wire _r_xcpt_valid_T = ld_xcpt_valid | mem_xcpt_valid; // @[lsu.scala:358:29, :1239:44, :1246:34]
wire _r_xcpt_valid_T_1 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1247:20]
wire _r_xcpt_valid_T_2 = _r_xcpt_valid_T & _r_xcpt_valid_T_1; // @[lsu.scala:1246:{34,53}, :1247:20]
wire [15:0] _r_xcpt_valid_T_3 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:118:51]
wire _r_xcpt_valid_T_4 = |_r_xcpt_valid_T_3; // @[util.scala:118:{51,59}]
wire _r_xcpt_valid_T_5 = ~_r_xcpt_valid_T_4; // @[util.scala:118:59]
wire _r_xcpt_valid_T_6 = _r_xcpt_valid_T_2 & _r_xcpt_valid_T_5; // @[lsu.scala:1246:53, :1247:39, :1248:20]
wire [15:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:359:29, :1242:115, :1251:28]
wire _io_core_lxcpt_valid_T = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1254:42]
wire _io_core_lxcpt_valid_T_1 = r_xcpt_valid & _io_core_lxcpt_valid_T; // @[lsu.scala:1236:29, :1254:{39,42}]
wire [15:0] _io_core_lxcpt_valid_T_2 = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:118:51]
wire _io_core_lxcpt_valid_T_3 = |_io_core_lxcpt_valid_T_2; // @[util.scala:118:{51,59}]
wire _io_core_lxcpt_valid_T_4 = ~_io_core_lxcpt_valid_T_3; // @[util.scala:118:59]
assign _io_core_lxcpt_valid_T_5 = _io_core_lxcpt_valid_T_1 & _io_core_lxcpt_valid_T_4; // @[lsu.scala:1254:{39,61,64}]
assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_5; // @[lsu.scala:201:7, :1254:61]
wire _io_core_spec_ld_wakeup_0_valid_T_1 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37, :1261:40]
wire _io_core_spec_ld_wakeup_0_valid_T_2 = _io_core_spec_ld_wakeup_0_valid_T & _io_core_spec_ld_wakeup_0_valid_T_1; // @[lsu.scala:1259:69, :1260:69, :1261:40]
wire _io_core_spec_ld_wakeup_0_valid_T_3 = |mem_incoming_uop_0_pdst; // @[lsu.scala:909:37, :1262:65]
assign _io_core_spec_ld_wakeup_0_valid_T_4 = _io_core_spec_ld_wakeup_0_valid_T_2 & _io_core_spec_ld_wakeup_0_valid_T_3; // @[lsu.scala:1260:69, :1261:69, :1262:65]
assign io_core_spec_ld_wakeup_0_valid_0 = _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:201:7, :1261:69]
wire dmem_resp_fired_0; // @[lsu.scala:1282:33]
wire _GEN_1073 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:201:7, :1290:7]
wire _GEN_1074 = _GEN_1073 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:201:7, :1290:7, :1294:7, :1295:15]
wire _GEN_1075 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h0; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1076 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h1; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1077 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h2; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1078 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h3; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1079 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h4; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1080 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h5; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1081 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h6; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1082 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h7; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1083 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h8; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1084 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h9; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1085 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hA; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1086 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hB; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1087 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hC; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1088 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hD; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1089 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hE; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1090 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hF; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1091 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h10; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1092 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h11; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1093 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h12; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1094 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h13; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1095 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h14; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1096 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h15; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1097 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h16; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
wire _GEN_1098 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h17; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62]
assign nacking_loads_0 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1075; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_1 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1076; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_2 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1077; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_3 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1078; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_4 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1079; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_5 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1080; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_6 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1081; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_7 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1082; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_8 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1083; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_9 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1084; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_10 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1085; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_11 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1086; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_12 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1087; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_13 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1088; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_14 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1089; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_15 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1090; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_16 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1091; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_17 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1092; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_18 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1093; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_19 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1094; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_20 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1095; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_21 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1096; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_22 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1097; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
assign nacking_loads_23 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1098; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62]
wire _GEN_1099 = io_dmem_resp_0_valid_0 & io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :1311:7]
wire send_iresp = _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h0; // @[lsu.scala:201:7, :263:49, :1314:58]
wire send_fresp = _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h1; // @[lsu.scala:201:7, :263:49, :1314:58, :1315:58]
wire _ldq_bits_succeeded_T = io_core_exe_0_iresp_valid_0 | io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7, :1327:72]
assign dmem_resp_fired_0 = io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 | io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0); // @[lsu.scala:201:7, :1282:33, :1309:5, :1311:7, :1325:28, :1331:7, :1334:48, :1335:30]
wire _T_1698 = dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1346:30]
wire _T_1700 = ~dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1350:{18,38}]
wire [4:0] _forward_uop_T_1 = _forward_uop_T;
wire [1:0] size_1 = _GEN_149[_forward_uop_T_1]; // @[AMOALU.scala:11:18]
wire [15:0] _live_T = io_core_brupdate_b1_mispredict_mask_0 & _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51]
wire _live_T_1 = |_live_T; // @[util.scala:118:{51,59}]
wire live = ~_live_T_1; // @[util.scala:118:59]
wire [1:0] size; // @[AMOALU.scala:11:18]
assign size = _GEN_52[wb_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8]
wire _GEN_1100 = _GEN_86[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8]
wire [63:0] _GEN_1101 = _GEN_87[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8]
wire [3:0][63:0] _GEN_1102 = {{_GEN_1101}, {{2{_GEN_1101[31:0]}}}, {{2{{2{_GEN_1101[15:0]}}}}}, {{2{{2{{2{_GEN_1101[7:0]}}}}}}}}; // @[AMOALU.scala:12:8, :29:{13,19,32,69}]
wire _io_core_exe_0_iresp_valid_T = _GEN_165[_forward_uop_T_1] == 2'h0; // @[util.scala:118:51]
wire _io_core_exe_0_iresp_valid_T_1 = _io_core_exe_0_iresp_valid_T & _GEN_1100; // @[AMOALU.scala:12:8]
wire _io_core_exe_0_iresp_valid_T_2 = _io_core_exe_0_iresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1365:{72,86}]
wire _GEN_1103 = _T_1698 | ~_T_1700; // @[lsu.scala:1309:5, :1346:30, :1347:5, :1350:38, :1351:5]
assign io_core_exe_0_iresp_valid_0 = _GEN_1103 ? io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 ? send_iresp : io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0) : _io_core_exe_0_iresp_valid_T_2; // @[lsu.scala:201:7, :1276:32, :1309:5, :1311:7, :1314:58, :1319:40, :1331:7, :1334:48, :1347:5, :1351:5, :1365:86]
wire _io_core_exe_0_fresp_valid_T = _GEN_165[_forward_uop_T_1] == 2'h1; // @[util.scala:118:51]
wire _io_core_exe_0_fresp_valid_T_1 = _io_core_exe_0_fresp_valid_T & _GEN_1100; // @[AMOALU.scala:12:8]
wire _io_core_exe_0_fresp_valid_T_2 = _io_core_exe_0_fresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1366:{72,86}]
assign io_core_exe_0_fresp_valid_0 = _GEN_1103 ? _GEN_1099 & send_fresp : _io_core_exe_0_fresp_valid_T_2; // @[lsu.scala:201:7, :1278:32, :1309:5, :1311:7, :1315:58, :1321:40, :1347:5, :1351:5, :1366:86]
assign io_core_exe_0_iresp_bits_uop_uopc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_1[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_inst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_2[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_debug_inst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_3[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_rvc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_4[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_debug_pc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_5[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_iq_type_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_6[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_fu_code_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_7[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_br_type_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_8[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_9[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_10[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_11[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_12[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_13[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_14[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_is_load_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_15[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_16[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ctrl_is_std_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_17[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_iw_state_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_18[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_19[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_20[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_br_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_21[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_jalr_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_22[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_jal_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_23[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_sfb_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_24[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_br_mask_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_25[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_br_tag_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_26[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ftq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_27[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_edge_inst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_28[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_pc_lob_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_29[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_taken_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_30[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_imm_packed_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_31[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_csr_addr_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_32[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_rob_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_33[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ldq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_34[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_stq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_35[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_rxq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_36[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_pdst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_37[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_prs1_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_38[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_prs2_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_39[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_prs3_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_40[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ppred_0 = ~_GEN_1103 | io_dmem_resp_0_bits_uop_uses_ldq_0 ? 5'h0 : _GEN_41[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :1309:5, :1333:62, :1347:5, :1351:5]
assign io_core_exe_0_iresp_bits_uop_prs1_busy_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_42[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_prs2_busy_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_43[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_142[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_prs3_busy_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_44[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ppred_busy_0 = _GEN_1103 & ~io_dmem_resp_0_bits_uop_uses_ldq_0 & _GEN_45[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :767:39, :1309:5, :1311:7, :1317:40, :1331:7, :1333:62, :1347:5, :1351:5]
assign io_core_exe_0_iresp_bits_uop_stale_pdst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_46[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_exception_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_47[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_exc_cause_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_49[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_bypassable_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_50[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_mem_cmd_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_51[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_mem_size_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_52[io_dmem_resp_0_bits_uop_stq_idx_0]) : size_1; // @[AMOALU.scala:11:18]
assign io_core_exe_0_iresp_bits_uop_mem_signed_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_53[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_fence_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_54[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_fencei_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_56[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_amo_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_57[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_uses_ldq_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_59[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_uses_stq_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_60[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_61[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_is_unique_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_62[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_flush_on_commit_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_63[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_64[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ldst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_65[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_lrs1_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_66[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_lrs2_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_67[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_lrs3_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_68[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_ldst_val_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_69[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_dst_rtype_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_70[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_lrs1_rtype_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_71[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_lrs2_rtype_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_72[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_frs3_en_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_73[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_fp_val_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_74[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_fp_single_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_75[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_171[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_76[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_171[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_172[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_77[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_172[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_173[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_78[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_173[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_bp_debug_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_174[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_79[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_174[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_175[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_80[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_175[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_debug_fsrc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_176[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_81[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_176[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_iresp_bits_uop_debug_tsrc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_177[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_82[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_177[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_uopc_0 = _GEN_1103 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_inst_0 = _GEN_1103 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_debug_inst_0 = _GEN_1103 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_rvc_0 = _GEN_1103 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_debug_pc_0 = _GEN_1103 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_iq_type_0 = _GEN_1103 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_fu_code_0 = _GEN_1103 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_br_type_0 = _GEN_1103 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = _GEN_1103 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = _GEN_1103 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = _GEN_1103 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = _GEN_1103 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = _GEN_1103 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = _GEN_1103 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_is_load_0 = _GEN_1103 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0 = _GEN_1103 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ctrl_is_std_0 = _GEN_1103 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_iw_state_0 = _GEN_1103 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = _GEN_1103 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = _GEN_1103 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_br_0 = _GEN_1103 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_jalr_0 = _GEN_1103 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_jal_0 = _GEN_1103 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_sfb_0 = _GEN_1103 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_br_mask_0 = _GEN_1103 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_br_tag_0 = _GEN_1103 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ftq_idx_0 = _GEN_1103 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_edge_inst_0 = _GEN_1103 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_pc_lob_0 = _GEN_1103 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_taken_0 = _GEN_1103 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_imm_packed_0 = _GEN_1103 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_csr_addr_0 = _GEN_1103 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_rob_idx_0 = _GEN_1103 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ldq_idx_0 = _GEN_1103 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_stq_idx_0 = _GEN_1103 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_rxq_idx_0 = _GEN_1103 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_pdst_0 = _GEN_1103 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_prs1_0 = _GEN_1103 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_prs2_0 = _GEN_1103 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_prs3_0 = _GEN_1103 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_prs1_busy_0 = _GEN_1103 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_prs2_busy_0 = _GEN_1103 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_142[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_prs3_busy_0 = _GEN_1103 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_stale_pdst_0 = _GEN_1103 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_exception_0 = _GEN_1103 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_exc_cause_0 = _GEN_1103 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_bypassable_0 = _GEN_1103 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_mem_cmd_0 = _GEN_1103 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_mem_size_0 = _GEN_1103 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : size_1; // @[AMOALU.scala:11:18]
assign io_core_exe_0_fresp_bits_uop_mem_signed_0 = _GEN_1103 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_fence_0 = _GEN_1103 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_fencei_0 = _GEN_1103 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_amo_0 = _GEN_1103 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_uses_ldq_0 = _GEN_1103 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_uses_stq_0 = _GEN_1103 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = _GEN_1103 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_is_unique_0 = _GEN_1103 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_flush_on_commit_0 = _GEN_1103 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0 = _GEN_1103 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ldst_0 = _GEN_1103 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_lrs1_0 = _GEN_1103 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_lrs2_0 = _GEN_1103 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_lrs3_0 = _GEN_1103 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_ldst_val_0 = _GEN_1103 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_dst_rtype_0 = _GEN_1103 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_lrs1_rtype_0 = _GEN_1103 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_lrs2_rtype_0 = _GEN_1103 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_frs3_en_0 = _GEN_1103 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_fp_val_0 = _GEN_1103 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_fp_single_0 = _GEN_1103 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0 = _GEN_1103 ? _GEN_171[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_171[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0 = _GEN_1103 ? _GEN_172[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_172[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0 = _GEN_1103 ? _GEN_173[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_173[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_bp_debug_if_0 = _GEN_1103 ? _GEN_174[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_174[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0 = _GEN_1103 ? _GEN_175[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_175[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_debug_fsrc_0 = _GEN_1103 ? _GEN_176[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_176[_forward_uop_T_1]; // @[util.scala:118:51]
assign io_core_exe_0_fresp_bits_uop_debug_tsrc_0 = _GEN_1103 ? _GEN_177[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_177[_forward_uop_T_1]; // @[util.scala:118:51]
wire _io_core_exe_0_iresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29]
wire _io_core_exe_0_fresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29]
wire _ldq_bits_debug_wb_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_1 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37]
wire [31:0] _io_core_exe_0_iresp_bits_data_T_5 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94]
wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_1 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37]
wire [31:0] _io_core_exe_0_fresp_bits_data_T_5 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94]
wire [31:0] _ldq_bits_debug_wb_data_shifted_T_1 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37]
wire [31:0] _ldq_bits_debug_wb_data_T_5 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94]
wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_2 = _GEN_1102[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55]
wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_2 = _GEN_1102[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55]
wire [31:0] _ldq_bits_debug_wb_data_shifted_T_2 = _GEN_1102[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55]
wire [31:0] io_core_exe_0_iresp_bits_data_shifted = _io_core_exe_0_iresp_bits_data_shifted_T ? _io_core_exe_0_iresp_bits_data_shifted_T_1 : _io_core_exe_0_iresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_core_exe_0_iresp_bits_data_zeroed = io_core_exe_0_iresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _GEN_1104 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:26]
assign _io_core_exe_0_iresp_bits_data_T = _GEN_1104; // @[AMOALU.scala:45:26]
wire _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:26]
assign _io_core_exe_0_fresp_bits_data_T = _GEN_1104; // @[AMOALU.scala:45:26]
wire _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:26]
assign _ldq_bits_debug_wb_data_T = _GEN_1104; // @[AMOALU.scala:45:26]
wire _io_core_exe_0_iresp_bits_data_T_1 = _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_core_exe_0_iresp_bits_data_T_2 = io_core_exe_0_iresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_core_exe_0_iresp_bits_data_T_3 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_core_exe_0_iresp_bits_data_T_4 = {32{_io_core_exe_0_iresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_core_exe_0_iresp_bits_data_T_6 = _io_core_exe_0_iresp_bits_data_T_1 ? _io_core_exe_0_iresp_bits_data_T_4 : _io_core_exe_0_iresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_core_exe_0_iresp_bits_data_T_7 = {_io_core_exe_0_iresp_bits_data_T_6, io_core_exe_0_iresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_core_exe_0_iresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29]
wire _io_core_exe_0_fresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29]
wire _ldq_bits_debug_wb_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_4 = _io_core_exe_0_iresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_5 = _io_core_exe_0_iresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_core_exe_0_iresp_bits_data_shifted_1 = _io_core_exe_0_iresp_bits_data_shifted_T_3 ? _io_core_exe_0_iresp_bits_data_shifted_T_4 : _io_core_exe_0_iresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_core_exe_0_iresp_bits_data_zeroed_1 = io_core_exe_0_iresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _GEN_1105 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:26]
assign _io_core_exe_0_iresp_bits_data_T_8 = _GEN_1105; // @[AMOALU.scala:45:26]
wire _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:26]
assign _io_core_exe_0_fresp_bits_data_T_8 = _GEN_1105; // @[AMOALU.scala:45:26]
wire _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:26]
assign _ldq_bits_debug_wb_data_T_8 = _GEN_1105; // @[AMOALU.scala:45:26]
wire _io_core_exe_0_iresp_bits_data_T_9 = _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_core_exe_0_iresp_bits_data_T_10 = io_core_exe_0_iresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_core_exe_0_iresp_bits_data_T_11 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_core_exe_0_iresp_bits_data_T_12 = {48{_io_core_exe_0_iresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_core_exe_0_iresp_bits_data_T_13 = _io_core_exe_0_iresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_core_exe_0_iresp_bits_data_T_14 = _io_core_exe_0_iresp_bits_data_T_9 ? _io_core_exe_0_iresp_bits_data_T_12 : _io_core_exe_0_iresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_core_exe_0_iresp_bits_data_T_15 = {_io_core_exe_0_iresp_bits_data_T_14, io_core_exe_0_iresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_core_exe_0_iresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29]
wire _io_core_exe_0_fresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29]
wire _ldq_bits_debug_wb_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_7 = _io_core_exe_0_iresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_8 = _io_core_exe_0_iresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_core_exe_0_iresp_bits_data_shifted_2 = _io_core_exe_0_iresp_bits_data_shifted_T_6 ? _io_core_exe_0_iresp_bits_data_shifted_T_7 : _io_core_exe_0_iresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_core_exe_0_iresp_bits_data_zeroed_2 = io_core_exe_0_iresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _GEN_1106 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:26]
assign _io_core_exe_0_iresp_bits_data_T_16 = _GEN_1106; // @[AMOALU.scala:45:26]
wire _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:26]
assign _io_core_exe_0_fresp_bits_data_T_16 = _GEN_1106; // @[AMOALU.scala:45:26]
wire _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:26]
assign _ldq_bits_debug_wb_data_T_16 = _GEN_1106; // @[AMOALU.scala:45:26]
wire _io_core_exe_0_iresp_bits_data_T_17 = _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_core_exe_0_iresp_bits_data_T_18 = io_core_exe_0_iresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_core_exe_0_iresp_bits_data_T_19 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_core_exe_0_iresp_bits_data_T_20 = {56{_io_core_exe_0_iresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_core_exe_0_iresp_bits_data_T_21 = _io_core_exe_0_iresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_core_exe_0_iresp_bits_data_T_22 = _io_core_exe_0_iresp_bits_data_T_17 ? _io_core_exe_0_iresp_bits_data_T_20 : _io_core_exe_0_iresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_core_exe_0_iresp_bits_data_T_23 = {_io_core_exe_0_iresp_bits_data_T_22, io_core_exe_0_iresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_core_exe_0_iresp_bits_data_0 = _GEN_1103 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_iresp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire [31:0] io_core_exe_0_fresp_bits_data_shifted = _io_core_exe_0_fresp_bits_data_shifted_T ? _io_core_exe_0_fresp_bits_data_shifted_T_1 : _io_core_exe_0_fresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_core_exe_0_fresp_bits_data_zeroed = io_core_exe_0_fresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_core_exe_0_fresp_bits_data_T_1 = _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_core_exe_0_fresp_bits_data_T_2 = io_core_exe_0_fresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_core_exe_0_fresp_bits_data_T_3 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_core_exe_0_fresp_bits_data_T_4 = {32{_io_core_exe_0_fresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_core_exe_0_fresp_bits_data_T_6 = _io_core_exe_0_fresp_bits_data_T_1 ? _io_core_exe_0_fresp_bits_data_T_4 : _io_core_exe_0_fresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_core_exe_0_fresp_bits_data_T_7 = {_io_core_exe_0_fresp_bits_data_T_6, io_core_exe_0_fresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_4 = _io_core_exe_0_fresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_5 = _io_core_exe_0_fresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_core_exe_0_fresp_bits_data_shifted_1 = _io_core_exe_0_fresp_bits_data_shifted_T_3 ? _io_core_exe_0_fresp_bits_data_shifted_T_4 : _io_core_exe_0_fresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_core_exe_0_fresp_bits_data_zeroed_1 = io_core_exe_0_fresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_core_exe_0_fresp_bits_data_T_9 = _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_core_exe_0_fresp_bits_data_T_10 = io_core_exe_0_fresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_core_exe_0_fresp_bits_data_T_11 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_core_exe_0_fresp_bits_data_T_12 = {48{_io_core_exe_0_fresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_core_exe_0_fresp_bits_data_T_13 = _io_core_exe_0_fresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_core_exe_0_fresp_bits_data_T_14 = _io_core_exe_0_fresp_bits_data_T_9 ? _io_core_exe_0_fresp_bits_data_T_12 : _io_core_exe_0_fresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_core_exe_0_fresp_bits_data_T_15 = {_io_core_exe_0_fresp_bits_data_T_14, io_core_exe_0_fresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_7 = _io_core_exe_0_fresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_8 = _io_core_exe_0_fresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_core_exe_0_fresp_bits_data_shifted_2 = _io_core_exe_0_fresp_bits_data_shifted_T_6 ? _io_core_exe_0_fresp_bits_data_shifted_T_7 : _io_core_exe_0_fresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_core_exe_0_fresp_bits_data_zeroed_2 = io_core_exe_0_fresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_core_exe_0_fresp_bits_data_T_17 = _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_core_exe_0_fresp_bits_data_T_18 = io_core_exe_0_fresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_core_exe_0_fresp_bits_data_T_19 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_core_exe_0_fresp_bits_data_T_20 = {56{_io_core_exe_0_fresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_core_exe_0_fresp_bits_data_T_21 = _io_core_exe_0_fresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_core_exe_0_fresp_bits_data_T_22 = _io_core_exe_0_fresp_bits_data_T_17 ? _io_core_exe_0_fresp_bits_data_T_20 : _io_core_exe_0_fresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_core_exe_0_fresp_bits_data_T_23 = {_io_core_exe_0_fresp_bits_data_T_22, io_core_exe_0_fresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_core_exe_0_fresp_bits_data_0 = {1'h0, _GEN_1103 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_fresp_bits_data_T_23}; // @[AMOALU.scala:45:16]
wire [31:0] ldq_bits_debug_wb_data_shifted = _ldq_bits_debug_wb_data_shifted_T ? _ldq_bits_debug_wb_data_shifted_T_1 : _ldq_bits_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] ldq_bits_debug_wb_data_zeroed = ldq_bits_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _ldq_bits_debug_wb_data_T_1 = _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}]
wire _ldq_bits_debug_wb_data_T_2 = ldq_bits_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _ldq_bits_debug_wb_data_T_3 = _GEN_150[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _ldq_bits_debug_wb_data_T_4 = {32{_ldq_bits_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _ldq_bits_debug_wb_data_T_6 = _ldq_bits_debug_wb_data_T_1 ? _ldq_bits_debug_wb_data_T_4 : _ldq_bits_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _ldq_bits_debug_wb_data_T_7 = {_ldq_bits_debug_wb_data_T_6, ldq_bits_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire [15:0] _ldq_bits_debug_wb_data_shifted_T_4 = _ldq_bits_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _ldq_bits_debug_wb_data_shifted_T_5 = _ldq_bits_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] ldq_bits_debug_wb_data_shifted_1 = _ldq_bits_debug_wb_data_shifted_T_3 ? _ldq_bits_debug_wb_data_shifted_T_4 : _ldq_bits_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] ldq_bits_debug_wb_data_zeroed_1 = ldq_bits_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _ldq_bits_debug_wb_data_T_9 = _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _ldq_bits_debug_wb_data_T_10 = ldq_bits_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _ldq_bits_debug_wb_data_T_11 = _GEN_150[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _ldq_bits_debug_wb_data_T_12 = {48{_ldq_bits_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _ldq_bits_debug_wb_data_T_13 = _ldq_bits_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _ldq_bits_debug_wb_data_T_14 = _ldq_bits_debug_wb_data_T_9 ? _ldq_bits_debug_wb_data_T_12 : _ldq_bits_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _ldq_bits_debug_wb_data_T_15 = {_ldq_bits_debug_wb_data_T_14, ldq_bits_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire [7:0] _ldq_bits_debug_wb_data_shifted_T_7 = _ldq_bits_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _ldq_bits_debug_wb_data_shifted_T_8 = _ldq_bits_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] ldq_bits_debug_wb_data_shifted_2 = _ldq_bits_debug_wb_data_shifted_T_6 ? _ldq_bits_debug_wb_data_shifted_T_7 : _ldq_bits_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] ldq_bits_debug_wb_data_zeroed_2 = ldq_bits_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _ldq_bits_debug_wb_data_T_17 = _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _ldq_bits_debug_wb_data_T_18 = ldq_bits_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _ldq_bits_debug_wb_data_T_19 = _GEN_150[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _ldq_bits_debug_wb_data_T_20 = {56{_ldq_bits_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _ldq_bits_debug_wb_data_T_21 = _ldq_bits_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _ldq_bits_debug_wb_data_T_22 = _ldq_bits_debug_wb_data_T_17 ? _ldq_bits_debug_wb_data_T_20 : _ldq_bits_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _ldq_bits_debug_wb_data_T_23 = {_ldq_bits_debug_wb_data_T_22, ldq_bits_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
reg io_core_ld_miss_REG; // @[lsu.scala:1383:37]
reg spec_ld_succeed_REG; // @[lsu.scala:1385:13]
wire _spec_ld_succeed_T = ~spec_ld_succeed_REG; // @[lsu.scala:1385:{5,13}]
reg [4:0] spec_ld_succeed_REG_1; // @[lsu.scala:1387:56]
wire _spec_ld_succeed_T_1 = io_core_exe_0_iresp_bits_uop_ldq_idx_0 == spec_ld_succeed_REG_1; // @[lsu.scala:201:7, :1387:{45,56}]
wire _spec_ld_succeed_T_2 = io_core_exe_0_iresp_valid_0 & _spec_ld_succeed_T_1; // @[lsu.scala:201:7, :1386:33, :1387:45]
wire _spec_ld_succeed_T_3 = _spec_ld_succeed_T | _spec_ld_succeed_T_2; // @[lsu.scala:1385:{5,47}, :1386:33]
wire _spec_ld_succeed_WIRE_0 = _spec_ld_succeed_T_3; // @[lsu.scala:263:49, :1385:47]
assign io_core_ld_miss_0 = ~_spec_ld_succeed_WIRE_0 & io_core_ld_miss_REG; // @[lsu.scala:201:7, :263:49, :1383:{27,37}, :1390:26, :1391:21]
wire st_brkilled_mask_0; // @[lsu.scala:1401:30]
wire st_brkilled_mask_1; // @[lsu.scala:1401:30]
wire st_brkilled_mask_2; // @[lsu.scala:1401:30]
wire st_brkilled_mask_3; // @[lsu.scala:1401:30]
wire st_brkilled_mask_4; // @[lsu.scala:1401:30]
wire st_brkilled_mask_5; // @[lsu.scala:1401:30]
wire st_brkilled_mask_6; // @[lsu.scala:1401:30]
wire st_brkilled_mask_7; // @[lsu.scala:1401:30]
wire st_brkilled_mask_8; // @[lsu.scala:1401:30]
wire st_brkilled_mask_9; // @[lsu.scala:1401:30]
wire st_brkilled_mask_10; // @[lsu.scala:1401:30]
wire st_brkilled_mask_11; // @[lsu.scala:1401:30]
wire st_brkilled_mask_12; // @[lsu.scala:1401:30]
wire st_brkilled_mask_13; // @[lsu.scala:1401:30]
wire st_brkilled_mask_14; // @[lsu.scala:1401:30]
wire st_brkilled_mask_15; // @[lsu.scala:1401:30]
wire st_brkilled_mask_16; // @[lsu.scala:1401:30]
wire st_brkilled_mask_17; // @[lsu.scala:1401:30]
wire st_brkilled_mask_18; // @[lsu.scala:1401:30]
wire st_brkilled_mask_19; // @[lsu.scala:1401:30]
wire st_brkilled_mask_20; // @[lsu.scala:1401:30]
wire st_brkilled_mask_21; // @[lsu.scala:1401:30]
wire st_brkilled_mask_22; // @[lsu.scala:1401:30]
wire st_brkilled_mask_23; // @[lsu.scala:1401:30]
wire [15:0] _stq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_0_bits_uop_br_mask_T_1 = stq_0_bits_uop_br_mask & _stq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1725 = io_core_brupdate_b1_mispredict_mask_0 & stq_0_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_0 = stq_0_valid & (|_T_1725); // @[util.scala:118:{51,59}]
wire [15:0] _stq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_1_bits_uop_br_mask_T_1 = stq_1_bits_uop_br_mask & _stq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1735 = io_core_brupdate_b1_mispredict_mask_0 & stq_1_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_1 = stq_1_valid & (|_T_1735); // @[util.scala:118:{51,59}]
wire [15:0] _stq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_2_bits_uop_br_mask_T_1 = stq_2_bits_uop_br_mask & _stq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1745 = io_core_brupdate_b1_mispredict_mask_0 & stq_2_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_2 = stq_2_valid & (|_T_1745); // @[util.scala:118:{51,59}]
wire [15:0] _stq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_3_bits_uop_br_mask_T_1 = stq_3_bits_uop_br_mask & _stq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1755 = io_core_brupdate_b1_mispredict_mask_0 & stq_3_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_3 = stq_3_valid & (|_T_1755); // @[util.scala:118:{51,59}]
wire [15:0] _stq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_4_bits_uop_br_mask_T_1 = stq_4_bits_uop_br_mask & _stq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1765 = io_core_brupdate_b1_mispredict_mask_0 & stq_4_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_4 = stq_4_valid & (|_T_1765); // @[util.scala:118:{51,59}]
wire [15:0] _stq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_5_bits_uop_br_mask_T_1 = stq_5_bits_uop_br_mask & _stq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1775 = io_core_brupdate_b1_mispredict_mask_0 & stq_5_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_5 = stq_5_valid & (|_T_1775); // @[util.scala:118:{51,59}]
wire [15:0] _stq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_6_bits_uop_br_mask_T_1 = stq_6_bits_uop_br_mask & _stq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1785 = io_core_brupdate_b1_mispredict_mask_0 & stq_6_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_6 = stq_6_valid & (|_T_1785); // @[util.scala:118:{51,59}]
wire [15:0] _stq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_7_bits_uop_br_mask_T_1 = stq_7_bits_uop_br_mask & _stq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1795 = io_core_brupdate_b1_mispredict_mask_0 & stq_7_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_7 = stq_7_valid & (|_T_1795); // @[util.scala:118:{51,59}]
wire [15:0] _stq_8_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_8_bits_uop_br_mask_T_1 = stq_8_bits_uop_br_mask & _stq_8_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1805 = io_core_brupdate_b1_mispredict_mask_0 & stq_8_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_8 = stq_8_valid & (|_T_1805); // @[util.scala:118:{51,59}]
wire [15:0] _stq_9_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_9_bits_uop_br_mask_T_1 = stq_9_bits_uop_br_mask & _stq_9_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1815 = io_core_brupdate_b1_mispredict_mask_0 & stq_9_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_9 = stq_9_valid & (|_T_1815); // @[util.scala:118:{51,59}]
wire [15:0] _stq_10_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_10_bits_uop_br_mask_T_1 = stq_10_bits_uop_br_mask & _stq_10_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1825 = io_core_brupdate_b1_mispredict_mask_0 & stq_10_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_10 = stq_10_valid & (|_T_1825); // @[util.scala:118:{51,59}]
wire [15:0] _stq_11_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_11_bits_uop_br_mask_T_1 = stq_11_bits_uop_br_mask & _stq_11_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1835 = io_core_brupdate_b1_mispredict_mask_0 & stq_11_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_11 = stq_11_valid & (|_T_1835); // @[util.scala:118:{51,59}]
wire [15:0] _stq_12_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_12_bits_uop_br_mask_T_1 = stq_12_bits_uop_br_mask & _stq_12_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1845 = io_core_brupdate_b1_mispredict_mask_0 & stq_12_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_12 = stq_12_valid & (|_T_1845); // @[util.scala:118:{51,59}]
wire [15:0] _stq_13_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_13_bits_uop_br_mask_T_1 = stq_13_bits_uop_br_mask & _stq_13_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1855 = io_core_brupdate_b1_mispredict_mask_0 & stq_13_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_13 = stq_13_valid & (|_T_1855); // @[util.scala:118:{51,59}]
wire [15:0] _stq_14_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_14_bits_uop_br_mask_T_1 = stq_14_bits_uop_br_mask & _stq_14_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1865 = io_core_brupdate_b1_mispredict_mask_0 & stq_14_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_14 = stq_14_valid & (|_T_1865); // @[util.scala:118:{51,59}]
wire [15:0] _stq_15_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_15_bits_uop_br_mask_T_1 = stq_15_bits_uop_br_mask & _stq_15_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1875 = io_core_brupdate_b1_mispredict_mask_0 & stq_15_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_15 = stq_15_valid & (|_T_1875); // @[util.scala:118:{51,59}]
wire [15:0] _stq_16_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_16_bits_uop_br_mask_T_1 = stq_16_bits_uop_br_mask & _stq_16_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1885 = io_core_brupdate_b1_mispredict_mask_0 & stq_16_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_16 = stq_16_valid & (|_T_1885); // @[util.scala:118:{51,59}]
wire [15:0] _stq_17_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_17_bits_uop_br_mask_T_1 = stq_17_bits_uop_br_mask & _stq_17_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1895 = io_core_brupdate_b1_mispredict_mask_0 & stq_17_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_17 = stq_17_valid & (|_T_1895); // @[util.scala:118:{51,59}]
wire [15:0] _stq_18_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_18_bits_uop_br_mask_T_1 = stq_18_bits_uop_br_mask & _stq_18_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1905 = io_core_brupdate_b1_mispredict_mask_0 & stq_18_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_18 = stq_18_valid & (|_T_1905); // @[util.scala:118:{51,59}]
wire [15:0] _stq_19_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_19_bits_uop_br_mask_T_1 = stq_19_bits_uop_br_mask & _stq_19_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1915 = io_core_brupdate_b1_mispredict_mask_0 & stq_19_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_19 = stq_19_valid & (|_T_1915); // @[util.scala:118:{51,59}]
wire [15:0] _stq_20_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_20_bits_uop_br_mask_T_1 = stq_20_bits_uop_br_mask & _stq_20_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1925 = io_core_brupdate_b1_mispredict_mask_0 & stq_20_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_20 = stq_20_valid & (|_T_1925); // @[util.scala:118:{51,59}]
wire [15:0] _stq_21_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_21_bits_uop_br_mask_T_1 = stq_21_bits_uop_br_mask & _stq_21_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1935 = io_core_brupdate_b1_mispredict_mask_0 & stq_21_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_21 = stq_21_valid & (|_T_1935); // @[util.scala:118:{51,59}]
wire [15:0] _stq_22_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_22_bits_uop_br_mask_T_1 = stq_22_bits_uop_br_mask & _stq_22_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1945 = io_core_brupdate_b1_mispredict_mask_0 & stq_22_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_22 = stq_22_valid & (|_T_1945); // @[util.scala:118:{51,59}]
wire [15:0] _stq_23_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _stq_23_bits_uop_br_mask_T_1 = stq_23_bits_uop_br_mask & _stq_23_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _T_1955 = io_core_brupdate_b1_mispredict_mask_0 & stq_23_bits_uop_br_mask; // @[util.scala:118:51]
assign st_brkilled_mask_23 = stq_23_valid & (|_T_1955); // @[util.scala:118:{51,59}]
wire [15:0] _ldq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_0_bits_uop_br_mask_T_1 = ldq_0_bits_uop_br_mask & _ldq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_1_bits_uop_br_mask_T_1 = ldq_1_bits_uop_br_mask & _ldq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_2_bits_uop_br_mask_T_1 = ldq_2_bits_uop_br_mask & _ldq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_3_bits_uop_br_mask_T_1 = ldq_3_bits_uop_br_mask & _ldq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_4_bits_uop_br_mask_T_1 = ldq_4_bits_uop_br_mask & _ldq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_5_bits_uop_br_mask_T_1 = ldq_5_bits_uop_br_mask & _ldq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_6_bits_uop_br_mask_T_1 = ldq_6_bits_uop_br_mask & _ldq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_7_bits_uop_br_mask_T_1 = ldq_7_bits_uop_br_mask & _ldq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_8_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_8_bits_uop_br_mask_T_1 = ldq_8_bits_uop_br_mask & _ldq_8_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_9_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_9_bits_uop_br_mask_T_1 = ldq_9_bits_uop_br_mask & _ldq_9_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_10_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_10_bits_uop_br_mask_T_1 = ldq_10_bits_uop_br_mask & _ldq_10_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_11_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_11_bits_uop_br_mask_T_1 = ldq_11_bits_uop_br_mask & _ldq_11_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_12_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_12_bits_uop_br_mask_T_1 = ldq_12_bits_uop_br_mask & _ldq_12_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_13_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_13_bits_uop_br_mask_T_1 = ldq_13_bits_uop_br_mask & _ldq_13_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_14_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_14_bits_uop_br_mask_T_1 = ldq_14_bits_uop_br_mask & _ldq_14_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_15_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_15_bits_uop_br_mask_T_1 = ldq_15_bits_uop_br_mask & _ldq_15_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_16_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_16_bits_uop_br_mask_T_1 = ldq_16_bits_uop_br_mask & _ldq_16_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_17_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_17_bits_uop_br_mask_T_1 = ldq_17_bits_uop_br_mask & _ldq_17_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_18_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_18_bits_uop_br_mask_T_1 = ldq_18_bits_uop_br_mask & _ldq_18_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_19_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_19_bits_uop_br_mask_T_1 = ldq_19_bits_uop_br_mask & _ldq_19_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_20_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_20_bits_uop_br_mask_T_1 = ldq_20_bits_uop_br_mask & _ldq_20_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_21_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_21_bits_uop_br_mask_T_1 = ldq_21_bits_uop_br_mask & _ldq_21_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_22_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_22_bits_uop_br_mask_T_1 = ldq_22_bits_uop_br_mask & _ldq_22_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _ldq_23_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _ldq_23_bits_uop_br_mask_T_1 = ldq_23_bits_uop_br_mask & _ldq_23_bits_uop_br_mask_T; // @[util.scala:89:{21,23}]
wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:201:7, :1454:49]
wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:201:7, :1455:49]
wire [4:0] idx = commit_store ? stq_commit_head : ldq_head; // @[lsu.scala:213:29, :217:29, :1454:49, :1456:18]
wire _GEN_1107 = ~commit_store & commit_load; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31]
wire _GEN_1108 = _GEN_1107 & ~reset; // @[lsu.scala:1460:31, :1461:14]
wire wrap_12 = stq_commit_head == 5'h17; // @[util.scala:205:25]
wire [4:0] _T_2025 = wrap_12 ? 5'h0 : stq_commit_head + 5'h1; // @[util.scala:205:25, :206:{10,28}]
wire [4:0] _T_2026 = commit_store ? _T_2025 : stq_commit_head; // @[util.scala:206:10]
wire wrap_13 = ldq_head == 5'h17; // @[util.scala:205:25]
wire [4:0] _T_2029 = wrap_13 ? 5'h0 : ldq_head + 5'h1; // @[util.scala:205:25, :206:{10,28}]
wire [4:0] _T_2030 = commit_load ? _T_2029 : ldq_head; // @[util.scala:206:10]
wire commit_store_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_stq_0; // @[lsu.scala:201:7, :1454:49]
wire commit_load_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_ldq_0; // @[lsu.scala:201:7, :1455:49]
wire [4:0] idx_1 = commit_store_1 ? _T_2026 : _T_2030; // @[lsu.scala:1454:49, :1456:18, :1485:31, :1489:31]
wire _GEN_1109 = ~commit_store_1 & commit_load_1; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31]
wire _GEN_1110 = _GEN_1109 & ~reset; // @[lsu.scala:1460:31, :1461:14]
wire wrap_14 = _T_2026 == 5'h17; // @[util.scala:205:25]
wire [4:0] _T_2041 = wrap_14 ? 5'h0 : _T_2026 + 5'h1; // @[util.scala:205:25, :206:{10,28}]
wire [4:0] _T_2042 = commit_store_1 ? _T_2041 : _T_2026; // @[util.scala:206:10]
wire wrap_15 = _T_2030 == 5'h17; // @[util.scala:205:25]
wire [4:0] _T_2045 = wrap_15 ? 5'h0 : _T_2030 + 5'h1; // @[util.scala:205:25, :206:{10,28}]
wire [4:0] _T_2046 = commit_load_1 ? _T_2045 : _T_2030; // @[util.scala:206:10]
wire commit_store_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_stq_0; // @[lsu.scala:201:7, :1454:49]
wire commit_load_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_ldq_0; // @[lsu.scala:201:7, :1455:49]
wire [4:0] idx_2 = commit_store_2 ? _T_2042 : _T_2046; // @[lsu.scala:1454:49, :1456:18, :1485:31, :1489:31]
wire _GEN_1111 = ~commit_store_2 & commit_load_2; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31]
wire _GEN_1112 = _GEN_1111 & ~reset; // @[lsu.scala:1460:31, :1461:14] |
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler_3 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<16>[8], flip divs : UInt<11>[8], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}}
inst sourceA of SourceA_3
connect sourceA.clock, clock
connect sourceA.reset, reset
inst sourceB of SourceB_3
connect sourceB.clock, clock
connect sourceB.reset, reset
inst sourceC of SourceC_3
connect sourceC.clock, clock
connect sourceC.reset, reset
inst sourceD of SourceD_3
connect sourceD.clock, clock
connect sourceD.reset, reset
inst sourceE of SourceE_3
connect sourceE.clock, clock
connect sourceE.reset, reset
inst sourceX of SourceX_3
connect sourceX.clock, clock
connect sourceX.reset, reset
connect io.out.a.bits, sourceA.io.a.bits
connect io.out.a.valid, sourceA.io.a.valid
connect sourceA.io.a.ready, io.out.a.ready
connect io.out.c.bits, sourceC.io.c.bits
connect io.out.c.valid, sourceC.io.c.valid
connect sourceC.io.c.ready, io.out.c.ready
connect io.out.e.bits, sourceE.io.e.bits
connect io.out.e.valid, sourceE.io.e.valid
connect sourceE.io.e.ready, io.out.e.ready
connect io.in.b.bits, sourceB.io.b.bits
connect io.in.b.valid, sourceB.io.b.valid
connect sourceB.io.b.ready, io.in.b.ready
connect io.in.d.bits, sourceD.io.d.bits
connect io.in.d.valid, sourceD.io.d.valid
connect sourceD.io.d.ready, io.in.d.ready
connect io.resp.bits, sourceX.io.x.bits
connect io.resp.valid, sourceX.io.x.valid
connect sourceX.io.x.ready, io.resp.ready
inst sinkA of SinkA_3
connect sinkA.clock, clock
connect sinkA.reset, reset
inst sinkC of SinkC_3
connect sinkC.clock, clock
connect sinkC.reset, reset
inst sinkD of SinkD_3
connect sinkD.clock, clock
connect sinkD.reset, reset
inst sinkE of SinkE_3
connect sinkE.clock, clock
connect sinkE.reset, reset
inst sinkX of SinkX_3
connect sinkX.clock, clock
connect sinkX.reset, reset
connect sinkA.io.a, io.in.a
connect sinkC.io.c, io.in.c
connect sinkE.io.e, io.in.e
connect sinkD.io.d, io.out.d
connect sinkX.io.x, io.req
connect io.out.b.ready, UInt<1>(0h1)
inst directory of Directory_3
connect directory.clock, clock
connect directory.reset, reset
inst bankedStore of BankedStore_3
connect bankedStore.clock, clock
connect bankedStore.reset, reset
inst requests of ListBuffer_QueuedRequest_q36_e28_3
connect requests.clock, clock
connect requests.reset, reset
inst mshrs_0 of MSHR_36
connect mshrs_0.clock, clock
connect mshrs_0.reset, reset
inst mshrs_1 of MSHR_37
connect mshrs_1.clock, clock
connect mshrs_1.reset, reset
inst mshrs_2 of MSHR_38
connect mshrs_2.clock, clock
connect mshrs_2.reset, reset
inst mshrs_3 of MSHR_39
connect mshrs_3.clock, clock
connect mshrs_3.reset, reset
inst mshrs_4 of MSHR_40
connect mshrs_4.clock, clock
connect mshrs_4.reset, reset
inst mshrs_5 of MSHR_41
connect mshrs_5.clock, clock
connect mshrs_5.reset, reset
inst mshrs_6 of MSHR_42
connect mshrs_6.clock, clock
connect mshrs_6.reset, reset
inst mshrs_7 of MSHR_43
connect mshrs_7.clock, clock
connect mshrs_7.reset, reset
inst mshrs_8 of MSHR_44
connect mshrs_8.clock, clock
connect mshrs_8.reset, reset
inst mshrs_9 of MSHR_45
connect mshrs_9.clock, clock
connect mshrs_9.reset, reset
inst mshrs_10 of MSHR_46
connect mshrs_10.clock, clock
connect mshrs_10.reset, reset
inst mshrs_11 of MSHR_47
connect mshrs_11.clock, clock
connect mshrs_11.reset, reset
wire nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}
node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set)
node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T)
connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1
node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0))
node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T)
connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1
node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0))
node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T)
connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1
connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_0.io.nestedwb.tag, nestedwb.tag
connect mshrs_0.io.nestedwb.set, nestedwb.set
node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set)
node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T)
connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1
node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1))
node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T)
connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1
node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1))
node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T)
connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1
connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_1.io.nestedwb.tag, nestedwb.tag
connect mshrs_1.io.nestedwb.set, nestedwb.set
node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set)
node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T)
connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1
node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2))
node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T)
connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1
node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2))
node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T)
connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1
connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_2.io.nestedwb.tag, nestedwb.tag
connect mshrs_2.io.nestedwb.set, nestedwb.set
node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set)
node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T)
connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1
node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3))
node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T)
connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1
node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3))
node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T)
connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1
connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_3.io.nestedwb.tag, nestedwb.tag
connect mshrs_3.io.nestedwb.set, nestedwb.set
node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set)
node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T)
connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1
node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4))
node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T)
connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1
node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4))
node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T)
connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1
connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_4.io.nestedwb.tag, nestedwb.tag
connect mshrs_4.io.nestedwb.set, nestedwb.set
node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set)
node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T)
connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1
node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5))
node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T)
connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1
node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5))
node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T)
connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1
connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_5.io.nestedwb.tag, nestedwb.tag
connect mshrs_5.io.nestedwb.set, nestedwb.set
node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set)
node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T)
connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1
node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6))
node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T)
connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1
node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6))
node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T)
connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1
connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_6.io.nestedwb.tag, nestedwb.tag
connect mshrs_6.io.nestedwb.set, nestedwb.set
node _mshrs_7_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_7.io.status.bits.set)
node _mshrs_7_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_7_io_sinkc_valid_T)
connect mshrs_7.io.sinkc.valid, _mshrs_7_io_sinkc_valid_T_1
node _mshrs_7_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h7))
node _mshrs_7_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_7_io_sinkd_valid_T)
connect mshrs_7.io.sinkd.valid, _mshrs_7_io_sinkd_valid_T_1
node _mshrs_7_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h7))
node _mshrs_7_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_7_io_sinke_valid_T)
connect mshrs_7.io.sinke.valid, _mshrs_7_io_sinke_valid_T_1
connect mshrs_7.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_7.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_7.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_7.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_7.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_7.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_7.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_7.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_7.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_7.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_7.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_7.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_7.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_7.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_7.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_7.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_7.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_7.io.nestedwb.tag, nestedwb.tag
connect mshrs_7.io.nestedwb.set, nestedwb.set
node _mshrs_8_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_8.io.status.bits.set)
node _mshrs_8_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_8_io_sinkc_valid_T)
connect mshrs_8.io.sinkc.valid, _mshrs_8_io_sinkc_valid_T_1
node _mshrs_8_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h8))
node _mshrs_8_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_8_io_sinkd_valid_T)
connect mshrs_8.io.sinkd.valid, _mshrs_8_io_sinkd_valid_T_1
node _mshrs_8_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h8))
node _mshrs_8_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_8_io_sinke_valid_T)
connect mshrs_8.io.sinke.valid, _mshrs_8_io_sinke_valid_T_1
connect mshrs_8.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_8.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_8.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_8.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_8.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_8.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_8.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_8.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_8.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_8.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_8.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_8.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_8.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_8.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_8.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_8.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_8.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_8.io.nestedwb.tag, nestedwb.tag
connect mshrs_8.io.nestedwb.set, nestedwb.set
node _mshrs_9_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_9.io.status.bits.set)
node _mshrs_9_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_9_io_sinkc_valid_T)
connect mshrs_9.io.sinkc.valid, _mshrs_9_io_sinkc_valid_T_1
node _mshrs_9_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h9))
node _mshrs_9_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_9_io_sinkd_valid_T)
connect mshrs_9.io.sinkd.valid, _mshrs_9_io_sinkd_valid_T_1
node _mshrs_9_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h9))
node _mshrs_9_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_9_io_sinke_valid_T)
connect mshrs_9.io.sinke.valid, _mshrs_9_io_sinke_valid_T_1
connect mshrs_9.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_9.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_9.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_9.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_9.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_9.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_9.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_9.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_9.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_9.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_9.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_9.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_9.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_9.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_9.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_9.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_9.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_9.io.nestedwb.tag, nestedwb.tag
connect mshrs_9.io.nestedwb.set, nestedwb.set
node _mshrs_10_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_10.io.status.bits.set)
node _mshrs_10_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_10_io_sinkc_valid_T)
connect mshrs_10.io.sinkc.valid, _mshrs_10_io_sinkc_valid_T_1
node _mshrs_10_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0ha))
node _mshrs_10_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_10_io_sinkd_valid_T)
connect mshrs_10.io.sinkd.valid, _mshrs_10_io_sinkd_valid_T_1
node _mshrs_10_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0ha))
node _mshrs_10_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_10_io_sinke_valid_T)
connect mshrs_10.io.sinke.valid, _mshrs_10_io_sinke_valid_T_1
connect mshrs_10.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_10.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_10.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_10.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_10.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_10.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_10.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_10.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_10.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_10.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_10.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_10.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_10.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_10.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_10.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_10.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_10.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_10.io.nestedwb.tag, nestedwb.tag
connect mshrs_10.io.nestedwb.set, nestedwb.set
node _mshrs_11_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_11.io.status.bits.set)
node _mshrs_11_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_11_io_sinkc_valid_T)
connect mshrs_11.io.sinkc.valid, _mshrs_11_io_sinkc_valid_T_1
node _mshrs_11_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0hb))
node _mshrs_11_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_11_io_sinkd_valid_T)
connect mshrs_11.io.sinkd.valid, _mshrs_11_io_sinkd_valid_T_1
node _mshrs_11_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0hb))
node _mshrs_11_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_11_io_sinke_valid_T)
connect mshrs_11.io.sinke.valid, _mshrs_11_io_sinke_valid_T_1
connect mshrs_11.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_11.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_11.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_11.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_11.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_11.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_11.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_11.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_11.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_11.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_11.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_11.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_11.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_11.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_11.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_11.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_11.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_11.io.nestedwb.tag, nestedwb.tag
connect mshrs_11.io.nestedwb.set, nestedwb.set
node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_1 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T)
node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_3 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_2)
node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3)
node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_5 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_4)
node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_7 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_6)
node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7)
node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_9 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_8)
node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_11 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_10)
node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11)
node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_13 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_12)
node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_15 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_14)
node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15)
node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_17 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_16)
node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_19 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_18)
node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19)
node _mshr_stall_abc_T_20 = eq(mshrs_5.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_21 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_20)
node _mshr_stall_abc_T_22 = eq(mshrs_5.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_23 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_22)
node mshr_stall_abc_5 = or(_mshr_stall_abc_T_21, _mshr_stall_abc_T_23)
node _mshr_stall_abc_T_24 = eq(mshrs_6.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_25 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_24)
node _mshr_stall_abc_T_26 = eq(mshrs_6.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_27 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_26)
node mshr_stall_abc_6 = or(_mshr_stall_abc_T_25, _mshr_stall_abc_T_27)
node _mshr_stall_abc_T_28 = eq(mshrs_7.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_29 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_28)
node _mshr_stall_abc_T_30 = eq(mshrs_7.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_31 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_30)
node mshr_stall_abc_7 = or(_mshr_stall_abc_T_29, _mshr_stall_abc_T_31)
node _mshr_stall_abc_T_32 = eq(mshrs_8.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_33 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_32)
node _mshr_stall_abc_T_34 = eq(mshrs_8.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_35 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_34)
node mshr_stall_abc_8 = or(_mshr_stall_abc_T_33, _mshr_stall_abc_T_35)
node _mshr_stall_abc_T_36 = eq(mshrs_9.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_37 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_36)
node _mshr_stall_abc_T_38 = eq(mshrs_9.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_39 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_38)
node mshr_stall_abc_9 = or(_mshr_stall_abc_T_37, _mshr_stall_abc_T_39)
node _mshr_stall_bc_T = eq(mshrs_10.io.status.bits.set, mshrs_11.io.status.bits.set)
node mshr_stall_bc = and(mshrs_11.io.status.valid, _mshr_stall_bc_T)
node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid)
node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid)
node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid)
node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid)
node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid)
node stall_abc_5 = and(mshr_stall_abc_5, mshrs_5.io.status.valid)
node stall_abc_6 = and(mshr_stall_abc_6, mshrs_6.io.status.valid)
node stall_abc_7 = and(mshr_stall_abc_7, mshrs_7.io.status.valid)
node stall_abc_8 = and(mshr_stall_abc_8, mshrs_8.io.status.valid)
node stall_abc_9 = and(mshr_stall_abc_9, mshrs_9.io.status.valid)
node _T = or(stall_abc_0, stall_abc_1)
node _T_1 = or(_T, stall_abc_2)
node _T_2 = or(_T_1, stall_abc_3)
node _T_3 = or(_T_2, stall_abc_4)
node _T_4 = or(_T_3, stall_abc_5)
node _T_5 = or(_T_4, stall_abc_6)
node _T_6 = or(_T_5, stall_abc_7)
node _T_7 = or(_T_6, stall_abc_8)
node _T_8 = or(_T_7, stall_abc_9)
node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0))
node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T)
node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2)
node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3)
node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5)
node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6)
node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8)
node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9)
node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11)
node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12)
node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14)
node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15)
node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17)
node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18)
node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20)
node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21)
node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0))
node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23)
node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25)
node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26)
node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28)
node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29)
node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31)
node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32)
node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34)
node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35)
node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37)
node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38)
node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40)
node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41)
node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43)
node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44)
node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0))
node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46)
node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48)
node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49)
node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51)
node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52)
node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54)
node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55)
node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57)
node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58)
node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60)
node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61)
node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63)
node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64)
node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66)
node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67)
node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0))
node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69)
node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71)
node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72)
node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74)
node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75)
node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77)
node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78)
node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80)
node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81)
node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83)
node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84)
node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86)
node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87)
node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89)
node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90)
node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0))
node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92)
node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94)
node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95)
node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97)
node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98)
node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100)
node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101)
node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103)
node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104)
node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106)
node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107)
node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109)
node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110)
node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112)
node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113)
node _mshr_request_T_115 = eq(mshr_stall_abc_5, UInt<1>(0h0))
node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115)
node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117)
node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118)
node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120)
node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121)
node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123)
node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124)
node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126)
node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127)
node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129)
node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130)
node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132)
node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133)
node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135)
node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136)
node _mshr_request_T_138 = eq(mshr_stall_abc_6, UInt<1>(0h0))
node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138)
node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140)
node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141)
node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143)
node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144)
node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146)
node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147)
node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149)
node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150)
node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152)
node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153)
node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155)
node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156)
node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158)
node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159)
node _mshr_request_T_161 = eq(mshr_stall_abc_7, UInt<1>(0h0))
node _mshr_request_T_162 = and(mshrs_7.io.schedule.valid, _mshr_request_T_161)
node _mshr_request_T_163 = eq(mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_164 = or(sourceA.io.req.ready, _mshr_request_T_163)
node _mshr_request_T_165 = and(_mshr_request_T_162, _mshr_request_T_164)
node _mshr_request_T_166 = eq(mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_167 = or(sourceB.io.req.ready, _mshr_request_T_166)
node _mshr_request_T_168 = and(_mshr_request_T_165, _mshr_request_T_167)
node _mshr_request_T_169 = eq(mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_170 = or(sourceC.io.req.ready, _mshr_request_T_169)
node _mshr_request_T_171 = and(_mshr_request_T_168, _mshr_request_T_170)
node _mshr_request_T_172 = eq(mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_173 = or(sourceD.io.req.ready, _mshr_request_T_172)
node _mshr_request_T_174 = and(_mshr_request_T_171, _mshr_request_T_173)
node _mshr_request_T_175 = eq(mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_176 = or(sourceE.io.req.ready, _mshr_request_T_175)
node _mshr_request_T_177 = and(_mshr_request_T_174, _mshr_request_T_176)
node _mshr_request_T_178 = eq(mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_179 = or(sourceX.io.req.ready, _mshr_request_T_178)
node _mshr_request_T_180 = and(_mshr_request_T_177, _mshr_request_T_179)
node _mshr_request_T_181 = eq(mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_182 = or(directory.io.write.ready, _mshr_request_T_181)
node _mshr_request_T_183 = and(_mshr_request_T_180, _mshr_request_T_182)
node _mshr_request_T_184 = eq(mshr_stall_abc_8, UInt<1>(0h0))
node _mshr_request_T_185 = and(mshrs_8.io.schedule.valid, _mshr_request_T_184)
node _mshr_request_T_186 = eq(mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_187 = or(sourceA.io.req.ready, _mshr_request_T_186)
node _mshr_request_T_188 = and(_mshr_request_T_185, _mshr_request_T_187)
node _mshr_request_T_189 = eq(mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_190 = or(sourceB.io.req.ready, _mshr_request_T_189)
node _mshr_request_T_191 = and(_mshr_request_T_188, _mshr_request_T_190)
node _mshr_request_T_192 = eq(mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_193 = or(sourceC.io.req.ready, _mshr_request_T_192)
node _mshr_request_T_194 = and(_mshr_request_T_191, _mshr_request_T_193)
node _mshr_request_T_195 = eq(mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_196 = or(sourceD.io.req.ready, _mshr_request_T_195)
node _mshr_request_T_197 = and(_mshr_request_T_194, _mshr_request_T_196)
node _mshr_request_T_198 = eq(mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_199 = or(sourceE.io.req.ready, _mshr_request_T_198)
node _mshr_request_T_200 = and(_mshr_request_T_197, _mshr_request_T_199)
node _mshr_request_T_201 = eq(mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_202 = or(sourceX.io.req.ready, _mshr_request_T_201)
node _mshr_request_T_203 = and(_mshr_request_T_200, _mshr_request_T_202)
node _mshr_request_T_204 = eq(mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_205 = or(directory.io.write.ready, _mshr_request_T_204)
node _mshr_request_T_206 = and(_mshr_request_T_203, _mshr_request_T_205)
node _mshr_request_T_207 = eq(mshr_stall_abc_9, UInt<1>(0h0))
node _mshr_request_T_208 = and(mshrs_9.io.schedule.valid, _mshr_request_T_207)
node _mshr_request_T_209 = eq(mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_210 = or(sourceA.io.req.ready, _mshr_request_T_209)
node _mshr_request_T_211 = and(_mshr_request_T_208, _mshr_request_T_210)
node _mshr_request_T_212 = eq(mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_213 = or(sourceB.io.req.ready, _mshr_request_T_212)
node _mshr_request_T_214 = and(_mshr_request_T_211, _mshr_request_T_213)
node _mshr_request_T_215 = eq(mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_216 = or(sourceC.io.req.ready, _mshr_request_T_215)
node _mshr_request_T_217 = and(_mshr_request_T_214, _mshr_request_T_216)
node _mshr_request_T_218 = eq(mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_219 = or(sourceD.io.req.ready, _mshr_request_T_218)
node _mshr_request_T_220 = and(_mshr_request_T_217, _mshr_request_T_219)
node _mshr_request_T_221 = eq(mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_222 = or(sourceE.io.req.ready, _mshr_request_T_221)
node _mshr_request_T_223 = and(_mshr_request_T_220, _mshr_request_T_222)
node _mshr_request_T_224 = eq(mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_225 = or(sourceX.io.req.ready, _mshr_request_T_224)
node _mshr_request_T_226 = and(_mshr_request_T_223, _mshr_request_T_225)
node _mshr_request_T_227 = eq(mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_228 = or(directory.io.write.ready, _mshr_request_T_227)
node _mshr_request_T_229 = and(_mshr_request_T_226, _mshr_request_T_228)
node _mshr_request_T_230 = eq(mshr_stall_bc, UInt<1>(0h0))
node _mshr_request_T_231 = and(mshrs_10.io.schedule.valid, _mshr_request_T_230)
node _mshr_request_T_232 = eq(mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_233 = or(sourceA.io.req.ready, _mshr_request_T_232)
node _mshr_request_T_234 = and(_mshr_request_T_231, _mshr_request_T_233)
node _mshr_request_T_235 = eq(mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_236 = or(sourceB.io.req.ready, _mshr_request_T_235)
node _mshr_request_T_237 = and(_mshr_request_T_234, _mshr_request_T_236)
node _mshr_request_T_238 = eq(mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_239 = or(sourceC.io.req.ready, _mshr_request_T_238)
node _mshr_request_T_240 = and(_mshr_request_T_237, _mshr_request_T_239)
node _mshr_request_T_241 = eq(mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_242 = or(sourceD.io.req.ready, _mshr_request_T_241)
node _mshr_request_T_243 = and(_mshr_request_T_240, _mshr_request_T_242)
node _mshr_request_T_244 = eq(mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_245 = or(sourceE.io.req.ready, _mshr_request_T_244)
node _mshr_request_T_246 = and(_mshr_request_T_243, _mshr_request_T_245)
node _mshr_request_T_247 = eq(mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_248 = or(sourceX.io.req.ready, _mshr_request_T_247)
node _mshr_request_T_249 = and(_mshr_request_T_246, _mshr_request_T_248)
node _mshr_request_T_250 = eq(mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_251 = or(directory.io.write.ready, _mshr_request_T_250)
node _mshr_request_T_252 = and(_mshr_request_T_249, _mshr_request_T_251)
node _mshr_request_T_253 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _mshr_request_T_254 = and(mshrs_11.io.schedule.valid, _mshr_request_T_253)
node _mshr_request_T_255 = eq(mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_256 = or(sourceA.io.req.ready, _mshr_request_T_255)
node _mshr_request_T_257 = and(_mshr_request_T_254, _mshr_request_T_256)
node _mshr_request_T_258 = eq(mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_259 = or(sourceB.io.req.ready, _mshr_request_T_258)
node _mshr_request_T_260 = and(_mshr_request_T_257, _mshr_request_T_259)
node _mshr_request_T_261 = eq(mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_262 = or(sourceC.io.req.ready, _mshr_request_T_261)
node _mshr_request_T_263 = and(_mshr_request_T_260, _mshr_request_T_262)
node _mshr_request_T_264 = eq(mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_265 = or(sourceD.io.req.ready, _mshr_request_T_264)
node _mshr_request_T_266 = and(_mshr_request_T_263, _mshr_request_T_265)
node _mshr_request_T_267 = eq(mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_268 = or(sourceE.io.req.ready, _mshr_request_T_267)
node _mshr_request_T_269 = and(_mshr_request_T_266, _mshr_request_T_268)
node _mshr_request_T_270 = eq(mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_271 = or(sourceX.io.req.ready, _mshr_request_T_270)
node _mshr_request_T_272 = and(_mshr_request_T_269, _mshr_request_T_271)
node _mshr_request_T_273 = eq(mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_274 = or(directory.io.write.ready, _mshr_request_T_273)
node _mshr_request_T_275 = and(_mshr_request_T_272, _mshr_request_T_274)
node mshr_request_lo_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45)
node mshr_request_lo_lo = cat(mshr_request_lo_lo_hi, _mshr_request_T_22)
node mshr_request_lo_hi_hi = cat(_mshr_request_T_137, _mshr_request_T_114)
node mshr_request_lo_hi = cat(mshr_request_lo_hi_hi, _mshr_request_T_91)
node mshr_request_lo = cat(mshr_request_lo_hi, mshr_request_lo_lo)
node mshr_request_hi_lo_hi = cat(_mshr_request_T_206, _mshr_request_T_183)
node mshr_request_hi_lo = cat(mshr_request_hi_lo_hi, _mshr_request_T_160)
node mshr_request_hi_hi_hi = cat(_mshr_request_T_275, _mshr_request_T_252)
node mshr_request_hi_hi = cat(mshr_request_hi_hi_hi, _mshr_request_T_229)
node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo)
node mshr_request = cat(mshr_request_hi, mshr_request_lo)
regreset robin_filter : UInt<12>, clock, reset, UInt<12>(0h0)
node _robin_request_T = and(mshr_request, robin_filter)
node robin_request = cat(mshr_request, _robin_request_T)
node _mshr_selectOH2_T = shl(robin_request, 1)
node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 23, 0)
node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1)
node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2)
node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 23, 0)
node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4)
node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4)
node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 23, 0)
node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7)
node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8)
node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 23, 0)
node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10)
node _mshr_selectOH2_T_12 = shl(_mshr_selectOH2_T_11, 16)
node _mshr_selectOH2_T_13 = bits(_mshr_selectOH2_T_12, 23, 0)
node _mshr_selectOH2_T_14 = or(_mshr_selectOH2_T_11, _mshr_selectOH2_T_13)
node _mshr_selectOH2_T_15 = bits(_mshr_selectOH2_T_14, 23, 0)
node _mshr_selectOH2_T_16 = shl(_mshr_selectOH2_T_15, 1)
node _mshr_selectOH2_T_17 = not(_mshr_selectOH2_T_16)
node mshr_selectOH2 = and(_mshr_selectOH2_T_17, robin_request)
node _mshr_selectOH_T = bits(mshr_selectOH2, 23, 12)
node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 11, 0)
node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1)
node mshr_select_hi = bits(mshr_selectOH, 11, 8)
node mshr_select_lo = bits(mshr_selectOH, 7, 0)
node _mshr_select_T = orr(mshr_select_hi)
node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo)
node mshr_select_hi_1 = bits(_mshr_select_T_1, 7, 4)
node mshr_select_lo_1 = bits(_mshr_select_T_1, 3, 0)
node _mshr_select_T_2 = orr(mshr_select_hi_1)
node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1)
node mshr_select_hi_2 = bits(_mshr_select_T_3, 3, 2)
node mshr_select_lo_2 = bits(_mshr_select_T_3, 1, 0)
node _mshr_select_T_4 = orr(mshr_select_hi_2)
node _mshr_select_T_5 = or(mshr_select_hi_2, mshr_select_lo_2)
node _mshr_select_T_6 = bits(_mshr_select_T_5, 1, 1)
node _mshr_select_T_7 = cat(_mshr_select_T_4, _mshr_select_T_6)
node _mshr_select_T_8 = cat(_mshr_select_T_2, _mshr_select_T_7)
node mshr_select = cat(_mshr_select_T, _mshr_select_T_8)
node _schedule_T = bits(mshr_selectOH, 0, 0)
node _schedule_T_1 = bits(mshr_selectOH, 1, 1)
node _schedule_T_2 = bits(mshr_selectOH, 2, 2)
node _schedule_T_3 = bits(mshr_selectOH, 3, 3)
node _schedule_T_4 = bits(mshr_selectOH, 4, 4)
node _schedule_T_5 = bits(mshr_selectOH, 5, 5)
node _schedule_T_6 = bits(mshr_selectOH, 6, 6)
node _schedule_T_7 = bits(mshr_selectOH, 7, 7)
node _schedule_T_8 = bits(mshr_selectOH, 8, 8)
node _schedule_T_9 = bits(mshr_selectOH, 9, 9)
node _schedule_T_10 = bits(mshr_selectOH, 10, 10)
node _schedule_T_11 = bits(mshr_selectOH, 11, 11)
wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}
node _schedule_T_12 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_13 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_14 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_15 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_16 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_17 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_18 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_19 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_20 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_21 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_22 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_23 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_24 = or(_schedule_T_12, _schedule_T_13)
node _schedule_T_25 = or(_schedule_T_24, _schedule_T_14)
node _schedule_T_26 = or(_schedule_T_25, _schedule_T_15)
node _schedule_T_27 = or(_schedule_T_26, _schedule_T_16)
node _schedule_T_28 = or(_schedule_T_27, _schedule_T_17)
node _schedule_T_29 = or(_schedule_T_28, _schedule_T_18)
node _schedule_T_30 = or(_schedule_T_29, _schedule_T_19)
node _schedule_T_31 = or(_schedule_T_30, _schedule_T_20)
node _schedule_T_32 = or(_schedule_T_31, _schedule_T_21)
node _schedule_T_33 = or(_schedule_T_32, _schedule_T_22)
node _schedule_T_34 = or(_schedule_T_33, _schedule_T_23)
wire _schedule_WIRE : UInt<1>
connect _schedule_WIRE, _schedule_T_34
connect schedule.reload, _schedule_WIRE
wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}
wire _schedule_WIRE_2 : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}
wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
node _schedule_T_35 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_36 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_37 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_38 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_39 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_40 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_41 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_42 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_43 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_44 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_45 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_46 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_47 = or(_schedule_T_35, _schedule_T_36)
node _schedule_T_48 = or(_schedule_T_47, _schedule_T_37)
node _schedule_T_49 = or(_schedule_T_48, _schedule_T_38)
node _schedule_T_50 = or(_schedule_T_49, _schedule_T_39)
node _schedule_T_51 = or(_schedule_T_50, _schedule_T_40)
node _schedule_T_52 = or(_schedule_T_51, _schedule_T_41)
node _schedule_T_53 = or(_schedule_T_52, _schedule_T_42)
node _schedule_T_54 = or(_schedule_T_53, _schedule_T_43)
node _schedule_T_55 = or(_schedule_T_54, _schedule_T_44)
node _schedule_T_56 = or(_schedule_T_55, _schedule_T_45)
node _schedule_T_57 = or(_schedule_T_56, _schedule_T_46)
wire _schedule_WIRE_4 : UInt<9>
connect _schedule_WIRE_4, _schedule_T_57
connect _schedule_WIRE_3.tag, _schedule_WIRE_4
node _schedule_T_58 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_59 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_60 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_61 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_62 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_63 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_64 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_65 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_66 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_67 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_68 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_69 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_70 = or(_schedule_T_58, _schedule_T_59)
node _schedule_T_71 = or(_schedule_T_70, _schedule_T_60)
node _schedule_T_72 = or(_schedule_T_71, _schedule_T_61)
node _schedule_T_73 = or(_schedule_T_72, _schedule_T_62)
node _schedule_T_74 = or(_schedule_T_73, _schedule_T_63)
node _schedule_T_75 = or(_schedule_T_74, _schedule_T_64)
node _schedule_T_76 = or(_schedule_T_75, _schedule_T_65)
node _schedule_T_77 = or(_schedule_T_76, _schedule_T_66)
node _schedule_T_78 = or(_schedule_T_77, _schedule_T_67)
node _schedule_T_79 = or(_schedule_T_78, _schedule_T_68)
node _schedule_T_80 = or(_schedule_T_79, _schedule_T_69)
wire _schedule_WIRE_5 : UInt<1>
connect _schedule_WIRE_5, _schedule_T_80
connect _schedule_WIRE_3.clients, _schedule_WIRE_5
node _schedule_T_81 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_82 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_83 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_84 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_85 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_86 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_87 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_88 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_89 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_90 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_91 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_92 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_93 = or(_schedule_T_81, _schedule_T_82)
node _schedule_T_94 = or(_schedule_T_93, _schedule_T_83)
node _schedule_T_95 = or(_schedule_T_94, _schedule_T_84)
node _schedule_T_96 = or(_schedule_T_95, _schedule_T_85)
node _schedule_T_97 = or(_schedule_T_96, _schedule_T_86)
node _schedule_T_98 = or(_schedule_T_97, _schedule_T_87)
node _schedule_T_99 = or(_schedule_T_98, _schedule_T_88)
node _schedule_T_100 = or(_schedule_T_99, _schedule_T_89)
node _schedule_T_101 = or(_schedule_T_100, _schedule_T_90)
node _schedule_T_102 = or(_schedule_T_101, _schedule_T_91)
node _schedule_T_103 = or(_schedule_T_102, _schedule_T_92)
wire _schedule_WIRE_6 : UInt<2>
connect _schedule_WIRE_6, _schedule_T_103
connect _schedule_WIRE_3.state, _schedule_WIRE_6
node _schedule_T_104 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_105 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_106 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_107 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_108 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_109 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_110 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_111 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_112 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_113 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_114 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_115 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_116 = or(_schedule_T_104, _schedule_T_105)
node _schedule_T_117 = or(_schedule_T_116, _schedule_T_106)
node _schedule_T_118 = or(_schedule_T_117, _schedule_T_107)
node _schedule_T_119 = or(_schedule_T_118, _schedule_T_108)
node _schedule_T_120 = or(_schedule_T_119, _schedule_T_109)
node _schedule_T_121 = or(_schedule_T_120, _schedule_T_110)
node _schedule_T_122 = or(_schedule_T_121, _schedule_T_111)
node _schedule_T_123 = or(_schedule_T_122, _schedule_T_112)
node _schedule_T_124 = or(_schedule_T_123, _schedule_T_113)
node _schedule_T_125 = or(_schedule_T_124, _schedule_T_114)
node _schedule_T_126 = or(_schedule_T_125, _schedule_T_115)
wire _schedule_WIRE_7 : UInt<1>
connect _schedule_WIRE_7, _schedule_T_126
connect _schedule_WIRE_3.dirty, _schedule_WIRE_7
connect _schedule_WIRE_2.data, _schedule_WIRE_3
node _schedule_T_127 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_128 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_129 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_130 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_131 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_132 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_133 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_134 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_135 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_136 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_137 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_138 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_139 = or(_schedule_T_127, _schedule_T_128)
node _schedule_T_140 = or(_schedule_T_139, _schedule_T_129)
node _schedule_T_141 = or(_schedule_T_140, _schedule_T_130)
node _schedule_T_142 = or(_schedule_T_141, _schedule_T_131)
node _schedule_T_143 = or(_schedule_T_142, _schedule_T_132)
node _schedule_T_144 = or(_schedule_T_143, _schedule_T_133)
node _schedule_T_145 = or(_schedule_T_144, _schedule_T_134)
node _schedule_T_146 = or(_schedule_T_145, _schedule_T_135)
node _schedule_T_147 = or(_schedule_T_146, _schedule_T_136)
node _schedule_T_148 = or(_schedule_T_147, _schedule_T_137)
node _schedule_T_149 = or(_schedule_T_148, _schedule_T_138)
wire _schedule_WIRE_8 : UInt<4>
connect _schedule_WIRE_8, _schedule_T_149
connect _schedule_WIRE_2.way, _schedule_WIRE_8
node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_157 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_158 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_159 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_160 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_161 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_162 = or(_schedule_T_150, _schedule_T_151)
node _schedule_T_163 = or(_schedule_T_162, _schedule_T_152)
node _schedule_T_164 = or(_schedule_T_163, _schedule_T_153)
node _schedule_T_165 = or(_schedule_T_164, _schedule_T_154)
node _schedule_T_166 = or(_schedule_T_165, _schedule_T_155)
node _schedule_T_167 = or(_schedule_T_166, _schedule_T_156)
node _schedule_T_168 = or(_schedule_T_167, _schedule_T_157)
node _schedule_T_169 = or(_schedule_T_168, _schedule_T_158)
node _schedule_T_170 = or(_schedule_T_169, _schedule_T_159)
node _schedule_T_171 = or(_schedule_T_170, _schedule_T_160)
node _schedule_T_172 = or(_schedule_T_171, _schedule_T_161)
wire _schedule_WIRE_9 : UInt<11>
connect _schedule_WIRE_9, _schedule_T_172
connect _schedule_WIRE_2.set, _schedule_WIRE_9
connect _schedule_WIRE_1.bits, _schedule_WIRE_2
node _schedule_T_173 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_174 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_175 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_176 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_177 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_178 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_179 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_180 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_181 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_182 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_183 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_184 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_185 = or(_schedule_T_173, _schedule_T_174)
node _schedule_T_186 = or(_schedule_T_185, _schedule_T_175)
node _schedule_T_187 = or(_schedule_T_186, _schedule_T_176)
node _schedule_T_188 = or(_schedule_T_187, _schedule_T_177)
node _schedule_T_189 = or(_schedule_T_188, _schedule_T_178)
node _schedule_T_190 = or(_schedule_T_189, _schedule_T_179)
node _schedule_T_191 = or(_schedule_T_190, _schedule_T_180)
node _schedule_T_192 = or(_schedule_T_191, _schedule_T_181)
node _schedule_T_193 = or(_schedule_T_192, _schedule_T_182)
node _schedule_T_194 = or(_schedule_T_193, _schedule_T_183)
node _schedule_T_195 = or(_schedule_T_194, _schedule_T_184)
wire _schedule_WIRE_10 : UInt<1>
connect _schedule_WIRE_10, _schedule_T_195
connect _schedule_WIRE_1.valid, _schedule_WIRE_10
connect schedule.dir, _schedule_WIRE_1
wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}}
wire _schedule_WIRE_12 : { fail : UInt<1>}
node _schedule_T_196 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_197 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_198 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_199 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_200 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_201 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_202 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_203 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_204 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_205 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_206 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_207 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_208 = or(_schedule_T_196, _schedule_T_197)
node _schedule_T_209 = or(_schedule_T_208, _schedule_T_198)
node _schedule_T_210 = or(_schedule_T_209, _schedule_T_199)
node _schedule_T_211 = or(_schedule_T_210, _schedule_T_200)
node _schedule_T_212 = or(_schedule_T_211, _schedule_T_201)
node _schedule_T_213 = or(_schedule_T_212, _schedule_T_202)
node _schedule_T_214 = or(_schedule_T_213, _schedule_T_203)
node _schedule_T_215 = or(_schedule_T_214, _schedule_T_204)
node _schedule_T_216 = or(_schedule_T_215, _schedule_T_205)
node _schedule_T_217 = or(_schedule_T_216, _schedule_T_206)
node _schedule_T_218 = or(_schedule_T_217, _schedule_T_207)
wire _schedule_WIRE_13 : UInt<1>
connect _schedule_WIRE_13, _schedule_T_218
connect _schedule_WIRE_12.fail, _schedule_WIRE_13
connect _schedule_WIRE_11.bits, _schedule_WIRE_12
node _schedule_T_219 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_220 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_221 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_222 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_223 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_224 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_225 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_226 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_227 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_228 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_229 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_230 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_231 = or(_schedule_T_219, _schedule_T_220)
node _schedule_T_232 = or(_schedule_T_231, _schedule_T_221)
node _schedule_T_233 = or(_schedule_T_232, _schedule_T_222)
node _schedule_T_234 = or(_schedule_T_233, _schedule_T_223)
node _schedule_T_235 = or(_schedule_T_234, _schedule_T_224)
node _schedule_T_236 = or(_schedule_T_235, _schedule_T_225)
node _schedule_T_237 = or(_schedule_T_236, _schedule_T_226)
node _schedule_T_238 = or(_schedule_T_237, _schedule_T_227)
node _schedule_T_239 = or(_schedule_T_238, _schedule_T_228)
node _schedule_T_240 = or(_schedule_T_239, _schedule_T_229)
node _schedule_T_241 = or(_schedule_T_240, _schedule_T_230)
wire _schedule_WIRE_14 : UInt<1>
connect _schedule_WIRE_14, _schedule_T_241
connect _schedule_WIRE_11.valid, _schedule_WIRE_14
connect schedule.x, _schedule_WIRE_11
wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}}
wire _schedule_WIRE_16 : { sink : UInt<3>}
node _schedule_T_242 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_243 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_244 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_245 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_246 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_247 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_248 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_249 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_250 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_251 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_252 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_253 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_254 = or(_schedule_T_242, _schedule_T_243)
node _schedule_T_255 = or(_schedule_T_254, _schedule_T_244)
node _schedule_T_256 = or(_schedule_T_255, _schedule_T_245)
node _schedule_T_257 = or(_schedule_T_256, _schedule_T_246)
node _schedule_T_258 = or(_schedule_T_257, _schedule_T_247)
node _schedule_T_259 = or(_schedule_T_258, _schedule_T_248)
node _schedule_T_260 = or(_schedule_T_259, _schedule_T_249)
node _schedule_T_261 = or(_schedule_T_260, _schedule_T_250)
node _schedule_T_262 = or(_schedule_T_261, _schedule_T_251)
node _schedule_T_263 = or(_schedule_T_262, _schedule_T_252)
node _schedule_T_264 = or(_schedule_T_263, _schedule_T_253)
wire _schedule_WIRE_17 : UInt<3>
connect _schedule_WIRE_17, _schedule_T_264
connect _schedule_WIRE_16.sink, _schedule_WIRE_17
connect _schedule_WIRE_15.bits, _schedule_WIRE_16
node _schedule_T_265 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_266 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_267 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_268 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_269 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_270 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_271 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_272 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_273 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_274 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_275 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_276 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_277 = or(_schedule_T_265, _schedule_T_266)
node _schedule_T_278 = or(_schedule_T_277, _schedule_T_267)
node _schedule_T_279 = or(_schedule_T_278, _schedule_T_268)
node _schedule_T_280 = or(_schedule_T_279, _schedule_T_269)
node _schedule_T_281 = or(_schedule_T_280, _schedule_T_270)
node _schedule_T_282 = or(_schedule_T_281, _schedule_T_271)
node _schedule_T_283 = or(_schedule_T_282, _schedule_T_272)
node _schedule_T_284 = or(_schedule_T_283, _schedule_T_273)
node _schedule_T_285 = or(_schedule_T_284, _schedule_T_274)
node _schedule_T_286 = or(_schedule_T_285, _schedule_T_275)
node _schedule_T_287 = or(_schedule_T_286, _schedule_T_276)
wire _schedule_WIRE_18 : UInt<1>
connect _schedule_WIRE_18, _schedule_T_287
connect _schedule_WIRE_15.valid, _schedule_WIRE_18
connect schedule.e, _schedule_WIRE_15
wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}
wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}
node _schedule_T_288 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_289 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_290 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_291 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_292 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_293 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_294 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_295 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_296 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_297 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_298 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_299 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_300 = or(_schedule_T_288, _schedule_T_289)
node _schedule_T_301 = or(_schedule_T_300, _schedule_T_290)
node _schedule_T_302 = or(_schedule_T_301, _schedule_T_291)
node _schedule_T_303 = or(_schedule_T_302, _schedule_T_292)
node _schedule_T_304 = or(_schedule_T_303, _schedule_T_293)
node _schedule_T_305 = or(_schedule_T_304, _schedule_T_294)
node _schedule_T_306 = or(_schedule_T_305, _schedule_T_295)
node _schedule_T_307 = or(_schedule_T_306, _schedule_T_296)
node _schedule_T_308 = or(_schedule_T_307, _schedule_T_297)
node _schedule_T_309 = or(_schedule_T_308, _schedule_T_298)
node _schedule_T_310 = or(_schedule_T_309, _schedule_T_299)
wire _schedule_WIRE_21 : UInt<1>
connect _schedule_WIRE_21, _schedule_T_310
connect _schedule_WIRE_20.bad, _schedule_WIRE_21
node _schedule_T_311 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_312 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_313 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_314 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_315 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_316 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_317 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_318 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_319 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_320 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_321 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_322 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_323 = or(_schedule_T_311, _schedule_T_312)
node _schedule_T_324 = or(_schedule_T_323, _schedule_T_313)
node _schedule_T_325 = or(_schedule_T_324, _schedule_T_314)
node _schedule_T_326 = or(_schedule_T_325, _schedule_T_315)
node _schedule_T_327 = or(_schedule_T_326, _schedule_T_316)
node _schedule_T_328 = or(_schedule_T_327, _schedule_T_317)
node _schedule_T_329 = or(_schedule_T_328, _schedule_T_318)
node _schedule_T_330 = or(_schedule_T_329, _schedule_T_319)
node _schedule_T_331 = or(_schedule_T_330, _schedule_T_320)
node _schedule_T_332 = or(_schedule_T_331, _schedule_T_321)
node _schedule_T_333 = or(_schedule_T_332, _schedule_T_322)
wire _schedule_WIRE_22 : UInt<4>
connect _schedule_WIRE_22, _schedule_T_333
connect _schedule_WIRE_20.way, _schedule_WIRE_22
node _schedule_T_334 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_335 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_336 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_337 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_338 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_339 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_340 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_341 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_342 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_343 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_344 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_345 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_346 = or(_schedule_T_334, _schedule_T_335)
node _schedule_T_347 = or(_schedule_T_346, _schedule_T_336)
node _schedule_T_348 = or(_schedule_T_347, _schedule_T_337)
node _schedule_T_349 = or(_schedule_T_348, _schedule_T_338)
node _schedule_T_350 = or(_schedule_T_349, _schedule_T_339)
node _schedule_T_351 = or(_schedule_T_350, _schedule_T_340)
node _schedule_T_352 = or(_schedule_T_351, _schedule_T_341)
node _schedule_T_353 = or(_schedule_T_352, _schedule_T_342)
node _schedule_T_354 = or(_schedule_T_353, _schedule_T_343)
node _schedule_T_355 = or(_schedule_T_354, _schedule_T_344)
node _schedule_T_356 = or(_schedule_T_355, _schedule_T_345)
wire _schedule_WIRE_23 : UInt<4>
connect _schedule_WIRE_23, _schedule_T_356
connect _schedule_WIRE_20.sink, _schedule_WIRE_23
node _schedule_T_357 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_358 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_359 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_360 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_361 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_362 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_363 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_364 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_365 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_366 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_367 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_368 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_369 = or(_schedule_T_357, _schedule_T_358)
node _schedule_T_370 = or(_schedule_T_369, _schedule_T_359)
node _schedule_T_371 = or(_schedule_T_370, _schedule_T_360)
node _schedule_T_372 = or(_schedule_T_371, _schedule_T_361)
node _schedule_T_373 = or(_schedule_T_372, _schedule_T_362)
node _schedule_T_374 = or(_schedule_T_373, _schedule_T_363)
node _schedule_T_375 = or(_schedule_T_374, _schedule_T_364)
node _schedule_T_376 = or(_schedule_T_375, _schedule_T_365)
node _schedule_T_377 = or(_schedule_T_376, _schedule_T_366)
node _schedule_T_378 = or(_schedule_T_377, _schedule_T_367)
node _schedule_T_379 = or(_schedule_T_378, _schedule_T_368)
wire _schedule_WIRE_24 : UInt<11>
connect _schedule_WIRE_24, _schedule_T_379
connect _schedule_WIRE_20.set, _schedule_WIRE_24
node _schedule_T_380 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_381 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_382 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_383 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_384 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_385 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_386 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_387 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_388 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_389 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_390 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_391 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_392 = or(_schedule_T_380, _schedule_T_381)
node _schedule_T_393 = or(_schedule_T_392, _schedule_T_382)
node _schedule_T_394 = or(_schedule_T_393, _schedule_T_383)
node _schedule_T_395 = or(_schedule_T_394, _schedule_T_384)
node _schedule_T_396 = or(_schedule_T_395, _schedule_T_385)
node _schedule_T_397 = or(_schedule_T_396, _schedule_T_386)
node _schedule_T_398 = or(_schedule_T_397, _schedule_T_387)
node _schedule_T_399 = or(_schedule_T_398, _schedule_T_388)
node _schedule_T_400 = or(_schedule_T_399, _schedule_T_389)
node _schedule_T_401 = or(_schedule_T_400, _schedule_T_390)
node _schedule_T_402 = or(_schedule_T_401, _schedule_T_391)
wire _schedule_WIRE_25 : UInt<6>
connect _schedule_WIRE_25, _schedule_T_402
connect _schedule_WIRE_20.put, _schedule_WIRE_25
node _schedule_T_403 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_404 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_405 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_406 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_407 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_408 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_409 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_410 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_411 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_412 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_413 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_414 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_415 = or(_schedule_T_403, _schedule_T_404)
node _schedule_T_416 = or(_schedule_T_415, _schedule_T_405)
node _schedule_T_417 = or(_schedule_T_416, _schedule_T_406)
node _schedule_T_418 = or(_schedule_T_417, _schedule_T_407)
node _schedule_T_419 = or(_schedule_T_418, _schedule_T_408)
node _schedule_T_420 = or(_schedule_T_419, _schedule_T_409)
node _schedule_T_421 = or(_schedule_T_420, _schedule_T_410)
node _schedule_T_422 = or(_schedule_T_421, _schedule_T_411)
node _schedule_T_423 = or(_schedule_T_422, _schedule_T_412)
node _schedule_T_424 = or(_schedule_T_423, _schedule_T_413)
node _schedule_T_425 = or(_schedule_T_424, _schedule_T_414)
wire _schedule_WIRE_26 : UInt<6>
connect _schedule_WIRE_26, _schedule_T_425
connect _schedule_WIRE_20.offset, _schedule_WIRE_26
node _schedule_T_426 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_427 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_428 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_429 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_430 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_431 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_432 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_433 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_434 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_435 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_436 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_437 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_438 = or(_schedule_T_426, _schedule_T_427)
node _schedule_T_439 = or(_schedule_T_438, _schedule_T_428)
node _schedule_T_440 = or(_schedule_T_439, _schedule_T_429)
node _schedule_T_441 = or(_schedule_T_440, _schedule_T_430)
node _schedule_T_442 = or(_schedule_T_441, _schedule_T_431)
node _schedule_T_443 = or(_schedule_T_442, _schedule_T_432)
node _schedule_T_444 = or(_schedule_T_443, _schedule_T_433)
node _schedule_T_445 = or(_schedule_T_444, _schedule_T_434)
node _schedule_T_446 = or(_schedule_T_445, _schedule_T_435)
node _schedule_T_447 = or(_schedule_T_446, _schedule_T_436)
node _schedule_T_448 = or(_schedule_T_447, _schedule_T_437)
wire _schedule_WIRE_27 : UInt<9>
connect _schedule_WIRE_27, _schedule_T_448
connect _schedule_WIRE_20.tag, _schedule_WIRE_27
node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_456 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_457 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_458 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_459 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_460 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_461 = or(_schedule_T_449, _schedule_T_450)
node _schedule_T_462 = or(_schedule_T_461, _schedule_T_451)
node _schedule_T_463 = or(_schedule_T_462, _schedule_T_452)
node _schedule_T_464 = or(_schedule_T_463, _schedule_T_453)
node _schedule_T_465 = or(_schedule_T_464, _schedule_T_454)
node _schedule_T_466 = or(_schedule_T_465, _schedule_T_455)
node _schedule_T_467 = or(_schedule_T_466, _schedule_T_456)
node _schedule_T_468 = or(_schedule_T_467, _schedule_T_457)
node _schedule_T_469 = or(_schedule_T_468, _schedule_T_458)
node _schedule_T_470 = or(_schedule_T_469, _schedule_T_459)
node _schedule_T_471 = or(_schedule_T_470, _schedule_T_460)
wire _schedule_WIRE_28 : UInt<6>
connect _schedule_WIRE_28, _schedule_T_471
connect _schedule_WIRE_20.source, _schedule_WIRE_28
node _schedule_T_472 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_473 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_474 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_475 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_476 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_477 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_478 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_479 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_480 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_481 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_482 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_483 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_484 = or(_schedule_T_472, _schedule_T_473)
node _schedule_T_485 = or(_schedule_T_484, _schedule_T_474)
node _schedule_T_486 = or(_schedule_T_485, _schedule_T_475)
node _schedule_T_487 = or(_schedule_T_486, _schedule_T_476)
node _schedule_T_488 = or(_schedule_T_487, _schedule_T_477)
node _schedule_T_489 = or(_schedule_T_488, _schedule_T_478)
node _schedule_T_490 = or(_schedule_T_489, _schedule_T_479)
node _schedule_T_491 = or(_schedule_T_490, _schedule_T_480)
node _schedule_T_492 = or(_schedule_T_491, _schedule_T_481)
node _schedule_T_493 = or(_schedule_T_492, _schedule_T_482)
node _schedule_T_494 = or(_schedule_T_493, _schedule_T_483)
wire _schedule_WIRE_29 : UInt<3>
connect _schedule_WIRE_29, _schedule_T_494
connect _schedule_WIRE_20.size, _schedule_WIRE_29
node _schedule_T_495 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_496 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_497 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_498 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_499 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_500 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_501 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_502 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_503 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_504 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_505 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_506 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_507 = or(_schedule_T_495, _schedule_T_496)
node _schedule_T_508 = or(_schedule_T_507, _schedule_T_497)
node _schedule_T_509 = or(_schedule_T_508, _schedule_T_498)
node _schedule_T_510 = or(_schedule_T_509, _schedule_T_499)
node _schedule_T_511 = or(_schedule_T_510, _schedule_T_500)
node _schedule_T_512 = or(_schedule_T_511, _schedule_T_501)
node _schedule_T_513 = or(_schedule_T_512, _schedule_T_502)
node _schedule_T_514 = or(_schedule_T_513, _schedule_T_503)
node _schedule_T_515 = or(_schedule_T_514, _schedule_T_504)
node _schedule_T_516 = or(_schedule_T_515, _schedule_T_505)
node _schedule_T_517 = or(_schedule_T_516, _schedule_T_506)
wire _schedule_WIRE_30 : UInt<3>
connect _schedule_WIRE_30, _schedule_T_517
connect _schedule_WIRE_20.param, _schedule_WIRE_30
node _schedule_T_518 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_519 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_520 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_521 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_522 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_523 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_524 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_525 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_526 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_527 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_528 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_529 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_530 = or(_schedule_T_518, _schedule_T_519)
node _schedule_T_531 = or(_schedule_T_530, _schedule_T_520)
node _schedule_T_532 = or(_schedule_T_531, _schedule_T_521)
node _schedule_T_533 = or(_schedule_T_532, _schedule_T_522)
node _schedule_T_534 = or(_schedule_T_533, _schedule_T_523)
node _schedule_T_535 = or(_schedule_T_534, _schedule_T_524)
node _schedule_T_536 = or(_schedule_T_535, _schedule_T_525)
node _schedule_T_537 = or(_schedule_T_536, _schedule_T_526)
node _schedule_T_538 = or(_schedule_T_537, _schedule_T_527)
node _schedule_T_539 = or(_schedule_T_538, _schedule_T_528)
node _schedule_T_540 = or(_schedule_T_539, _schedule_T_529)
wire _schedule_WIRE_31 : UInt<3>
connect _schedule_WIRE_31, _schedule_T_540
connect _schedule_WIRE_20.opcode, _schedule_WIRE_31
node _schedule_T_541 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_542 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_543 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_544 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_545 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_546 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_547 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_548 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_549 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_550 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_551 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_552 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_553 = or(_schedule_T_541, _schedule_T_542)
node _schedule_T_554 = or(_schedule_T_553, _schedule_T_543)
node _schedule_T_555 = or(_schedule_T_554, _schedule_T_544)
node _schedule_T_556 = or(_schedule_T_555, _schedule_T_545)
node _schedule_T_557 = or(_schedule_T_556, _schedule_T_546)
node _schedule_T_558 = or(_schedule_T_557, _schedule_T_547)
node _schedule_T_559 = or(_schedule_T_558, _schedule_T_548)
node _schedule_T_560 = or(_schedule_T_559, _schedule_T_549)
node _schedule_T_561 = or(_schedule_T_560, _schedule_T_550)
node _schedule_T_562 = or(_schedule_T_561, _schedule_T_551)
node _schedule_T_563 = or(_schedule_T_562, _schedule_T_552)
wire _schedule_WIRE_32 : UInt<1>
connect _schedule_WIRE_32, _schedule_T_563
connect _schedule_WIRE_20.control, _schedule_WIRE_32
wire _schedule_WIRE_33 : UInt<1>[3]
node _schedule_T_564 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_565 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_566 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_567 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_568 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_569 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_570 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_571 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_572 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_573 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_574 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_575 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_576 = or(_schedule_T_564, _schedule_T_565)
node _schedule_T_577 = or(_schedule_T_576, _schedule_T_566)
node _schedule_T_578 = or(_schedule_T_577, _schedule_T_567)
node _schedule_T_579 = or(_schedule_T_578, _schedule_T_568)
node _schedule_T_580 = or(_schedule_T_579, _schedule_T_569)
node _schedule_T_581 = or(_schedule_T_580, _schedule_T_570)
node _schedule_T_582 = or(_schedule_T_581, _schedule_T_571)
node _schedule_T_583 = or(_schedule_T_582, _schedule_T_572)
node _schedule_T_584 = or(_schedule_T_583, _schedule_T_573)
node _schedule_T_585 = or(_schedule_T_584, _schedule_T_574)
node _schedule_T_586 = or(_schedule_T_585, _schedule_T_575)
wire _schedule_WIRE_34 : UInt<1>
connect _schedule_WIRE_34, _schedule_T_586
connect _schedule_WIRE_33[0], _schedule_WIRE_34
node _schedule_T_587 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_588 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_589 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_590 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_591 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_592 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_593 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_594 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_595 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_596 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_597 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_598 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_599 = or(_schedule_T_587, _schedule_T_588)
node _schedule_T_600 = or(_schedule_T_599, _schedule_T_589)
node _schedule_T_601 = or(_schedule_T_600, _schedule_T_590)
node _schedule_T_602 = or(_schedule_T_601, _schedule_T_591)
node _schedule_T_603 = or(_schedule_T_602, _schedule_T_592)
node _schedule_T_604 = or(_schedule_T_603, _schedule_T_593)
node _schedule_T_605 = or(_schedule_T_604, _schedule_T_594)
node _schedule_T_606 = or(_schedule_T_605, _schedule_T_595)
node _schedule_T_607 = or(_schedule_T_606, _schedule_T_596)
node _schedule_T_608 = or(_schedule_T_607, _schedule_T_597)
node _schedule_T_609 = or(_schedule_T_608, _schedule_T_598)
wire _schedule_WIRE_35 : UInt<1>
connect _schedule_WIRE_35, _schedule_T_609
connect _schedule_WIRE_33[1], _schedule_WIRE_35
node _schedule_T_610 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_611 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_612 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_613 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_614 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_615 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_616 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_617 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_618 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_619 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_620 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_621 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_622 = or(_schedule_T_610, _schedule_T_611)
node _schedule_T_623 = or(_schedule_T_622, _schedule_T_612)
node _schedule_T_624 = or(_schedule_T_623, _schedule_T_613)
node _schedule_T_625 = or(_schedule_T_624, _schedule_T_614)
node _schedule_T_626 = or(_schedule_T_625, _schedule_T_615)
node _schedule_T_627 = or(_schedule_T_626, _schedule_T_616)
node _schedule_T_628 = or(_schedule_T_627, _schedule_T_617)
node _schedule_T_629 = or(_schedule_T_628, _schedule_T_618)
node _schedule_T_630 = or(_schedule_T_629, _schedule_T_619)
node _schedule_T_631 = or(_schedule_T_630, _schedule_T_620)
node _schedule_T_632 = or(_schedule_T_631, _schedule_T_621)
wire _schedule_WIRE_36 : UInt<1>
connect _schedule_WIRE_36, _schedule_T_632
connect _schedule_WIRE_33[2], _schedule_WIRE_36
connect _schedule_WIRE_20.prio, _schedule_WIRE_33
connect _schedule_WIRE_19.bits, _schedule_WIRE_20
node _schedule_T_633 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_634 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_635 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_636 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_637 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_638 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_639 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_640 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_641 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_642 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_643 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_644 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_645 = or(_schedule_T_633, _schedule_T_634)
node _schedule_T_646 = or(_schedule_T_645, _schedule_T_635)
node _schedule_T_647 = or(_schedule_T_646, _schedule_T_636)
node _schedule_T_648 = or(_schedule_T_647, _schedule_T_637)
node _schedule_T_649 = or(_schedule_T_648, _schedule_T_638)
node _schedule_T_650 = or(_schedule_T_649, _schedule_T_639)
node _schedule_T_651 = or(_schedule_T_650, _schedule_T_640)
node _schedule_T_652 = or(_schedule_T_651, _schedule_T_641)
node _schedule_T_653 = or(_schedule_T_652, _schedule_T_642)
node _schedule_T_654 = or(_schedule_T_653, _schedule_T_643)
node _schedule_T_655 = or(_schedule_T_654, _schedule_T_644)
wire _schedule_WIRE_37 : UInt<1>
connect _schedule_WIRE_37, _schedule_T_655
connect _schedule_WIRE_19.valid, _schedule_WIRE_37
connect schedule.d, _schedule_WIRE_19
wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}
wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}
node _schedule_T_656 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_657 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_658 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_659 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_660 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_661 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_662 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_663 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_664 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_665 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_666 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_667 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_668 = or(_schedule_T_656, _schedule_T_657)
node _schedule_T_669 = or(_schedule_T_668, _schedule_T_658)
node _schedule_T_670 = or(_schedule_T_669, _schedule_T_659)
node _schedule_T_671 = or(_schedule_T_670, _schedule_T_660)
node _schedule_T_672 = or(_schedule_T_671, _schedule_T_661)
node _schedule_T_673 = or(_schedule_T_672, _schedule_T_662)
node _schedule_T_674 = or(_schedule_T_673, _schedule_T_663)
node _schedule_T_675 = or(_schedule_T_674, _schedule_T_664)
node _schedule_T_676 = or(_schedule_T_675, _schedule_T_665)
node _schedule_T_677 = or(_schedule_T_676, _schedule_T_666)
node _schedule_T_678 = or(_schedule_T_677, _schedule_T_667)
wire _schedule_WIRE_40 : UInt<1>
connect _schedule_WIRE_40, _schedule_T_678
connect _schedule_WIRE_39.dirty, _schedule_WIRE_40
node _schedule_T_679 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_680 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_681 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_682 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_683 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_684 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_685 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_686 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_687 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_688 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_689 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_690 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_691 = or(_schedule_T_679, _schedule_T_680)
node _schedule_T_692 = or(_schedule_T_691, _schedule_T_681)
node _schedule_T_693 = or(_schedule_T_692, _schedule_T_682)
node _schedule_T_694 = or(_schedule_T_693, _schedule_T_683)
node _schedule_T_695 = or(_schedule_T_694, _schedule_T_684)
node _schedule_T_696 = or(_schedule_T_695, _schedule_T_685)
node _schedule_T_697 = or(_schedule_T_696, _schedule_T_686)
node _schedule_T_698 = or(_schedule_T_697, _schedule_T_687)
node _schedule_T_699 = or(_schedule_T_698, _schedule_T_688)
node _schedule_T_700 = or(_schedule_T_699, _schedule_T_689)
node _schedule_T_701 = or(_schedule_T_700, _schedule_T_690)
wire _schedule_WIRE_41 : UInt<4>
connect _schedule_WIRE_41, _schedule_T_701
connect _schedule_WIRE_39.way, _schedule_WIRE_41
node _schedule_T_702 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_703 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_704 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_705 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_706 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_707 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_708 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_709 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_710 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_711 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_712 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_713 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_714 = or(_schedule_T_702, _schedule_T_703)
node _schedule_T_715 = or(_schedule_T_714, _schedule_T_704)
node _schedule_T_716 = or(_schedule_T_715, _schedule_T_705)
node _schedule_T_717 = or(_schedule_T_716, _schedule_T_706)
node _schedule_T_718 = or(_schedule_T_717, _schedule_T_707)
node _schedule_T_719 = or(_schedule_T_718, _schedule_T_708)
node _schedule_T_720 = or(_schedule_T_719, _schedule_T_709)
node _schedule_T_721 = or(_schedule_T_720, _schedule_T_710)
node _schedule_T_722 = or(_schedule_T_721, _schedule_T_711)
node _schedule_T_723 = or(_schedule_T_722, _schedule_T_712)
node _schedule_T_724 = or(_schedule_T_723, _schedule_T_713)
wire _schedule_WIRE_42 : UInt<11>
connect _schedule_WIRE_42, _schedule_T_724
connect _schedule_WIRE_39.set, _schedule_WIRE_42
node _schedule_T_725 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_726 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_727 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_728 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_729 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_730 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_731 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_732 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_733 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_734 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_735 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_736 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_737 = or(_schedule_T_725, _schedule_T_726)
node _schedule_T_738 = or(_schedule_T_737, _schedule_T_727)
node _schedule_T_739 = or(_schedule_T_738, _schedule_T_728)
node _schedule_T_740 = or(_schedule_T_739, _schedule_T_729)
node _schedule_T_741 = or(_schedule_T_740, _schedule_T_730)
node _schedule_T_742 = or(_schedule_T_741, _schedule_T_731)
node _schedule_T_743 = or(_schedule_T_742, _schedule_T_732)
node _schedule_T_744 = or(_schedule_T_743, _schedule_T_733)
node _schedule_T_745 = or(_schedule_T_744, _schedule_T_734)
node _schedule_T_746 = or(_schedule_T_745, _schedule_T_735)
node _schedule_T_747 = or(_schedule_T_746, _schedule_T_736)
wire _schedule_WIRE_43 : UInt<9>
connect _schedule_WIRE_43, _schedule_T_747
connect _schedule_WIRE_39.tag, _schedule_WIRE_43
node _schedule_T_748 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_749 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_750 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_751 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_752 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_753 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_754 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_755 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_756 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_757 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_758 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_759 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_760 = or(_schedule_T_748, _schedule_T_749)
node _schedule_T_761 = or(_schedule_T_760, _schedule_T_750)
node _schedule_T_762 = or(_schedule_T_761, _schedule_T_751)
node _schedule_T_763 = or(_schedule_T_762, _schedule_T_752)
node _schedule_T_764 = or(_schedule_T_763, _schedule_T_753)
node _schedule_T_765 = or(_schedule_T_764, _schedule_T_754)
node _schedule_T_766 = or(_schedule_T_765, _schedule_T_755)
node _schedule_T_767 = or(_schedule_T_766, _schedule_T_756)
node _schedule_T_768 = or(_schedule_T_767, _schedule_T_757)
node _schedule_T_769 = or(_schedule_T_768, _schedule_T_758)
node _schedule_T_770 = or(_schedule_T_769, _schedule_T_759)
wire _schedule_WIRE_44 : UInt<4>
connect _schedule_WIRE_44, _schedule_T_770
connect _schedule_WIRE_39.source, _schedule_WIRE_44
node _schedule_T_771 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_772 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_773 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_774 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_775 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_776 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_777 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_778 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_779 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_780 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_781 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_782 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_783 = or(_schedule_T_771, _schedule_T_772)
node _schedule_T_784 = or(_schedule_T_783, _schedule_T_773)
node _schedule_T_785 = or(_schedule_T_784, _schedule_T_774)
node _schedule_T_786 = or(_schedule_T_785, _schedule_T_775)
node _schedule_T_787 = or(_schedule_T_786, _schedule_T_776)
node _schedule_T_788 = or(_schedule_T_787, _schedule_T_777)
node _schedule_T_789 = or(_schedule_T_788, _schedule_T_778)
node _schedule_T_790 = or(_schedule_T_789, _schedule_T_779)
node _schedule_T_791 = or(_schedule_T_790, _schedule_T_780)
node _schedule_T_792 = or(_schedule_T_791, _schedule_T_781)
node _schedule_T_793 = or(_schedule_T_792, _schedule_T_782)
wire _schedule_WIRE_45 : UInt<3>
connect _schedule_WIRE_45, _schedule_T_793
connect _schedule_WIRE_39.param, _schedule_WIRE_45
node _schedule_T_794 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_795 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_796 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_797 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_798 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_799 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_800 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_801 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_802 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_803 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_804 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_805 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_806 = or(_schedule_T_794, _schedule_T_795)
node _schedule_T_807 = or(_schedule_T_806, _schedule_T_796)
node _schedule_T_808 = or(_schedule_T_807, _schedule_T_797)
node _schedule_T_809 = or(_schedule_T_808, _schedule_T_798)
node _schedule_T_810 = or(_schedule_T_809, _schedule_T_799)
node _schedule_T_811 = or(_schedule_T_810, _schedule_T_800)
node _schedule_T_812 = or(_schedule_T_811, _schedule_T_801)
node _schedule_T_813 = or(_schedule_T_812, _schedule_T_802)
node _schedule_T_814 = or(_schedule_T_813, _schedule_T_803)
node _schedule_T_815 = or(_schedule_T_814, _schedule_T_804)
node _schedule_T_816 = or(_schedule_T_815, _schedule_T_805)
wire _schedule_WIRE_46 : UInt<3>
connect _schedule_WIRE_46, _schedule_T_816
connect _schedule_WIRE_39.opcode, _schedule_WIRE_46
connect _schedule_WIRE_38.bits, _schedule_WIRE_39
node _schedule_T_817 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_818 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_819 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_820 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_821 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_822 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_823 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_824 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_825 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_826 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_827 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_828 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_829 = or(_schedule_T_817, _schedule_T_818)
node _schedule_T_830 = or(_schedule_T_829, _schedule_T_819)
node _schedule_T_831 = or(_schedule_T_830, _schedule_T_820)
node _schedule_T_832 = or(_schedule_T_831, _schedule_T_821)
node _schedule_T_833 = or(_schedule_T_832, _schedule_T_822)
node _schedule_T_834 = or(_schedule_T_833, _schedule_T_823)
node _schedule_T_835 = or(_schedule_T_834, _schedule_T_824)
node _schedule_T_836 = or(_schedule_T_835, _schedule_T_825)
node _schedule_T_837 = or(_schedule_T_836, _schedule_T_826)
node _schedule_T_838 = or(_schedule_T_837, _schedule_T_827)
node _schedule_T_839 = or(_schedule_T_838, _schedule_T_828)
wire _schedule_WIRE_47 : UInt<1>
connect _schedule_WIRE_47, _schedule_T_839
connect _schedule_WIRE_38.valid, _schedule_WIRE_47
connect schedule.c, _schedule_WIRE_38
wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}
wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}
node _schedule_T_840 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_841 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_842 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_843 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_844 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_845 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_846 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_847 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_848 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_849 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_850 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_851 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_852 = or(_schedule_T_840, _schedule_T_841)
node _schedule_T_853 = or(_schedule_T_852, _schedule_T_842)
node _schedule_T_854 = or(_schedule_T_853, _schedule_T_843)
node _schedule_T_855 = or(_schedule_T_854, _schedule_T_844)
node _schedule_T_856 = or(_schedule_T_855, _schedule_T_845)
node _schedule_T_857 = or(_schedule_T_856, _schedule_T_846)
node _schedule_T_858 = or(_schedule_T_857, _schedule_T_847)
node _schedule_T_859 = or(_schedule_T_858, _schedule_T_848)
node _schedule_T_860 = or(_schedule_T_859, _schedule_T_849)
node _schedule_T_861 = or(_schedule_T_860, _schedule_T_850)
node _schedule_T_862 = or(_schedule_T_861, _schedule_T_851)
wire _schedule_WIRE_50 : UInt<1>
connect _schedule_WIRE_50, _schedule_T_862
connect _schedule_WIRE_49.clients, _schedule_WIRE_50
node _schedule_T_863 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_864 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_865 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_866 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_867 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_868 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_869 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_870 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_871 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_872 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_873 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_874 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_875 = or(_schedule_T_863, _schedule_T_864)
node _schedule_T_876 = or(_schedule_T_875, _schedule_T_865)
node _schedule_T_877 = or(_schedule_T_876, _schedule_T_866)
node _schedule_T_878 = or(_schedule_T_877, _schedule_T_867)
node _schedule_T_879 = or(_schedule_T_878, _schedule_T_868)
node _schedule_T_880 = or(_schedule_T_879, _schedule_T_869)
node _schedule_T_881 = or(_schedule_T_880, _schedule_T_870)
node _schedule_T_882 = or(_schedule_T_881, _schedule_T_871)
node _schedule_T_883 = or(_schedule_T_882, _schedule_T_872)
node _schedule_T_884 = or(_schedule_T_883, _schedule_T_873)
node _schedule_T_885 = or(_schedule_T_884, _schedule_T_874)
wire _schedule_WIRE_51 : UInt<11>
connect _schedule_WIRE_51, _schedule_T_885
connect _schedule_WIRE_49.set, _schedule_WIRE_51
node _schedule_T_886 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_887 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_888 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_889 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_890 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_891 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_892 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_893 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_894 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_895 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_896 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_897 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_898 = or(_schedule_T_886, _schedule_T_887)
node _schedule_T_899 = or(_schedule_T_898, _schedule_T_888)
node _schedule_T_900 = or(_schedule_T_899, _schedule_T_889)
node _schedule_T_901 = or(_schedule_T_900, _schedule_T_890)
node _schedule_T_902 = or(_schedule_T_901, _schedule_T_891)
node _schedule_T_903 = or(_schedule_T_902, _schedule_T_892)
node _schedule_T_904 = or(_schedule_T_903, _schedule_T_893)
node _schedule_T_905 = or(_schedule_T_904, _schedule_T_894)
node _schedule_T_906 = or(_schedule_T_905, _schedule_T_895)
node _schedule_T_907 = or(_schedule_T_906, _schedule_T_896)
node _schedule_T_908 = or(_schedule_T_907, _schedule_T_897)
wire _schedule_WIRE_52 : UInt<9>
connect _schedule_WIRE_52, _schedule_T_908
connect _schedule_WIRE_49.tag, _schedule_WIRE_52
node _schedule_T_909 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_910 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_911 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_912 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_913 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_914 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_915 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_916 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_917 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_918 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_919 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_920 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_921 = or(_schedule_T_909, _schedule_T_910)
node _schedule_T_922 = or(_schedule_T_921, _schedule_T_911)
node _schedule_T_923 = or(_schedule_T_922, _schedule_T_912)
node _schedule_T_924 = or(_schedule_T_923, _schedule_T_913)
node _schedule_T_925 = or(_schedule_T_924, _schedule_T_914)
node _schedule_T_926 = or(_schedule_T_925, _schedule_T_915)
node _schedule_T_927 = or(_schedule_T_926, _schedule_T_916)
node _schedule_T_928 = or(_schedule_T_927, _schedule_T_917)
node _schedule_T_929 = or(_schedule_T_928, _schedule_T_918)
node _schedule_T_930 = or(_schedule_T_929, _schedule_T_919)
node _schedule_T_931 = or(_schedule_T_930, _schedule_T_920)
wire _schedule_WIRE_53 : UInt<3>
connect _schedule_WIRE_53, _schedule_T_931
connect _schedule_WIRE_49.param, _schedule_WIRE_53
connect _schedule_WIRE_48.bits, _schedule_WIRE_49
node _schedule_T_932 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_933 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_934 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_935 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_936 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_937 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_938 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_939 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_940 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_941 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_942 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_943 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_944 = or(_schedule_T_932, _schedule_T_933)
node _schedule_T_945 = or(_schedule_T_944, _schedule_T_934)
node _schedule_T_946 = or(_schedule_T_945, _schedule_T_935)
node _schedule_T_947 = or(_schedule_T_946, _schedule_T_936)
node _schedule_T_948 = or(_schedule_T_947, _schedule_T_937)
node _schedule_T_949 = or(_schedule_T_948, _schedule_T_938)
node _schedule_T_950 = or(_schedule_T_949, _schedule_T_939)
node _schedule_T_951 = or(_schedule_T_950, _schedule_T_940)
node _schedule_T_952 = or(_schedule_T_951, _schedule_T_941)
node _schedule_T_953 = or(_schedule_T_952, _schedule_T_942)
node _schedule_T_954 = or(_schedule_T_953, _schedule_T_943)
wire _schedule_WIRE_54 : UInt<1>
connect _schedule_WIRE_54, _schedule_T_954
connect _schedule_WIRE_48.valid, _schedule_WIRE_54
connect schedule.b, _schedule_WIRE_48
wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}
wire _schedule_WIRE_56 : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}
node _schedule_T_955 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_956 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_957 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_958 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_959 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_960 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_961 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_962 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_963 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_964 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_965 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_966 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_967 = or(_schedule_T_955, _schedule_T_956)
node _schedule_T_968 = or(_schedule_T_967, _schedule_T_957)
node _schedule_T_969 = or(_schedule_T_968, _schedule_T_958)
node _schedule_T_970 = or(_schedule_T_969, _schedule_T_959)
node _schedule_T_971 = or(_schedule_T_970, _schedule_T_960)
node _schedule_T_972 = or(_schedule_T_971, _schedule_T_961)
node _schedule_T_973 = or(_schedule_T_972, _schedule_T_962)
node _schedule_T_974 = or(_schedule_T_973, _schedule_T_963)
node _schedule_T_975 = or(_schedule_T_974, _schedule_T_964)
node _schedule_T_976 = or(_schedule_T_975, _schedule_T_965)
node _schedule_T_977 = or(_schedule_T_976, _schedule_T_966)
wire _schedule_WIRE_57 : UInt<1>
connect _schedule_WIRE_57, _schedule_T_977
connect _schedule_WIRE_56.block, _schedule_WIRE_57
node _schedule_T_978 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_979 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_980 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_981 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_982 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_983 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_984 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_985 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_986 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_987 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_988 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_989 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_990 = or(_schedule_T_978, _schedule_T_979)
node _schedule_T_991 = or(_schedule_T_990, _schedule_T_980)
node _schedule_T_992 = or(_schedule_T_991, _schedule_T_981)
node _schedule_T_993 = or(_schedule_T_992, _schedule_T_982)
node _schedule_T_994 = or(_schedule_T_993, _schedule_T_983)
node _schedule_T_995 = or(_schedule_T_994, _schedule_T_984)
node _schedule_T_996 = or(_schedule_T_995, _schedule_T_985)
node _schedule_T_997 = or(_schedule_T_996, _schedule_T_986)
node _schedule_T_998 = or(_schedule_T_997, _schedule_T_987)
node _schedule_T_999 = or(_schedule_T_998, _schedule_T_988)
node _schedule_T_1000 = or(_schedule_T_999, _schedule_T_989)
wire _schedule_WIRE_58 : UInt<4>
connect _schedule_WIRE_58, _schedule_T_1000
connect _schedule_WIRE_56.source, _schedule_WIRE_58
node _schedule_T_1001 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1002 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1003 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1004 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1005 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1006 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1007 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1008 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1009 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1010 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1011 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1012 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1013 = or(_schedule_T_1001, _schedule_T_1002)
node _schedule_T_1014 = or(_schedule_T_1013, _schedule_T_1003)
node _schedule_T_1015 = or(_schedule_T_1014, _schedule_T_1004)
node _schedule_T_1016 = or(_schedule_T_1015, _schedule_T_1005)
node _schedule_T_1017 = or(_schedule_T_1016, _schedule_T_1006)
node _schedule_T_1018 = or(_schedule_T_1017, _schedule_T_1007)
node _schedule_T_1019 = or(_schedule_T_1018, _schedule_T_1008)
node _schedule_T_1020 = or(_schedule_T_1019, _schedule_T_1009)
node _schedule_T_1021 = or(_schedule_T_1020, _schedule_T_1010)
node _schedule_T_1022 = or(_schedule_T_1021, _schedule_T_1011)
node _schedule_T_1023 = or(_schedule_T_1022, _schedule_T_1012)
wire _schedule_WIRE_59 : UInt<3>
connect _schedule_WIRE_59, _schedule_T_1023
connect _schedule_WIRE_56.param, _schedule_WIRE_59
node _schedule_T_1024 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1025 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1026 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1027 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1028 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1029 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1030 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1031 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1032 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1033 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1034 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1035 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1036 = or(_schedule_T_1024, _schedule_T_1025)
node _schedule_T_1037 = or(_schedule_T_1036, _schedule_T_1026)
node _schedule_T_1038 = or(_schedule_T_1037, _schedule_T_1027)
node _schedule_T_1039 = or(_schedule_T_1038, _schedule_T_1028)
node _schedule_T_1040 = or(_schedule_T_1039, _schedule_T_1029)
node _schedule_T_1041 = or(_schedule_T_1040, _schedule_T_1030)
node _schedule_T_1042 = or(_schedule_T_1041, _schedule_T_1031)
node _schedule_T_1043 = or(_schedule_T_1042, _schedule_T_1032)
node _schedule_T_1044 = or(_schedule_T_1043, _schedule_T_1033)
node _schedule_T_1045 = or(_schedule_T_1044, _schedule_T_1034)
node _schedule_T_1046 = or(_schedule_T_1045, _schedule_T_1035)
wire _schedule_WIRE_60 : UInt<11>
connect _schedule_WIRE_60, _schedule_T_1046
connect _schedule_WIRE_56.set, _schedule_WIRE_60
node _schedule_T_1047 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1048 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1049 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1050 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1051 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1052 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1053 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1054 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1055 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1056 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1057 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1058 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1059 = or(_schedule_T_1047, _schedule_T_1048)
node _schedule_T_1060 = or(_schedule_T_1059, _schedule_T_1049)
node _schedule_T_1061 = or(_schedule_T_1060, _schedule_T_1050)
node _schedule_T_1062 = or(_schedule_T_1061, _schedule_T_1051)
node _schedule_T_1063 = or(_schedule_T_1062, _schedule_T_1052)
node _schedule_T_1064 = or(_schedule_T_1063, _schedule_T_1053)
node _schedule_T_1065 = or(_schedule_T_1064, _schedule_T_1054)
node _schedule_T_1066 = or(_schedule_T_1065, _schedule_T_1055)
node _schedule_T_1067 = or(_schedule_T_1066, _schedule_T_1056)
node _schedule_T_1068 = or(_schedule_T_1067, _schedule_T_1057)
node _schedule_T_1069 = or(_schedule_T_1068, _schedule_T_1058)
wire _schedule_WIRE_61 : UInt<9>
connect _schedule_WIRE_61, _schedule_T_1069
connect _schedule_WIRE_56.tag, _schedule_WIRE_61
connect _schedule_WIRE_55.bits, _schedule_WIRE_56
node _schedule_T_1070 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1071 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1072 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1073 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1074 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1075 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1076 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1077 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1078 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1079 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1080 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1081 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1082 = or(_schedule_T_1070, _schedule_T_1071)
node _schedule_T_1083 = or(_schedule_T_1082, _schedule_T_1072)
node _schedule_T_1084 = or(_schedule_T_1083, _schedule_T_1073)
node _schedule_T_1085 = or(_schedule_T_1084, _schedule_T_1074)
node _schedule_T_1086 = or(_schedule_T_1085, _schedule_T_1075)
node _schedule_T_1087 = or(_schedule_T_1086, _schedule_T_1076)
node _schedule_T_1088 = or(_schedule_T_1087, _schedule_T_1077)
node _schedule_T_1089 = or(_schedule_T_1088, _schedule_T_1078)
node _schedule_T_1090 = or(_schedule_T_1089, _schedule_T_1079)
node _schedule_T_1091 = or(_schedule_T_1090, _schedule_T_1080)
node _schedule_T_1092 = or(_schedule_T_1091, _schedule_T_1081)
wire _schedule_WIRE_62 : UInt<1>
connect _schedule_WIRE_62, _schedule_T_1092
connect _schedule_WIRE_55.valid, _schedule_WIRE_62
connect schedule.a, _schedule_WIRE_55
node _scheduleTag_T = bits(mshr_selectOH, 0, 0)
node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleTag_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleTag_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleTag_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleTag_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleTag_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleTag_T_12 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_13 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_14 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_15 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_16 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_17 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_18 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_19 = mux(_scheduleTag_T_7, mshrs_7.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_20 = mux(_scheduleTag_T_8, mshrs_8.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_21 = mux(_scheduleTag_T_9, mshrs_9.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_22 = mux(_scheduleTag_T_10, mshrs_10.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_23 = mux(_scheduleTag_T_11, mshrs_11.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_24 = or(_scheduleTag_T_12, _scheduleTag_T_13)
node _scheduleTag_T_25 = or(_scheduleTag_T_24, _scheduleTag_T_14)
node _scheduleTag_T_26 = or(_scheduleTag_T_25, _scheduleTag_T_15)
node _scheduleTag_T_27 = or(_scheduleTag_T_26, _scheduleTag_T_16)
node _scheduleTag_T_28 = or(_scheduleTag_T_27, _scheduleTag_T_17)
node _scheduleTag_T_29 = or(_scheduleTag_T_28, _scheduleTag_T_18)
node _scheduleTag_T_30 = or(_scheduleTag_T_29, _scheduleTag_T_19)
node _scheduleTag_T_31 = or(_scheduleTag_T_30, _scheduleTag_T_20)
node _scheduleTag_T_32 = or(_scheduleTag_T_31, _scheduleTag_T_21)
node _scheduleTag_T_33 = or(_scheduleTag_T_32, _scheduleTag_T_22)
node _scheduleTag_T_34 = or(_scheduleTag_T_33, _scheduleTag_T_23)
wire scheduleTag : UInt<9>
connect scheduleTag, _scheduleTag_T_34
node _scheduleSet_T = bits(mshr_selectOH, 0, 0)
node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleSet_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleSet_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleSet_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleSet_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleSet_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleSet_T_12 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_13 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_14 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_15 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_16 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_17 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_18 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_19 = mux(_scheduleSet_T_7, mshrs_7.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_20 = mux(_scheduleSet_T_8, mshrs_8.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_21 = mux(_scheduleSet_T_9, mshrs_9.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_22 = mux(_scheduleSet_T_10, mshrs_10.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_23 = mux(_scheduleSet_T_11, mshrs_11.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_24 = or(_scheduleSet_T_12, _scheduleSet_T_13)
node _scheduleSet_T_25 = or(_scheduleSet_T_24, _scheduleSet_T_14)
node _scheduleSet_T_26 = or(_scheduleSet_T_25, _scheduleSet_T_15)
node _scheduleSet_T_27 = or(_scheduleSet_T_26, _scheduleSet_T_16)
node _scheduleSet_T_28 = or(_scheduleSet_T_27, _scheduleSet_T_17)
node _scheduleSet_T_29 = or(_scheduleSet_T_28, _scheduleSet_T_18)
node _scheduleSet_T_30 = or(_scheduleSet_T_29, _scheduleSet_T_19)
node _scheduleSet_T_31 = or(_scheduleSet_T_30, _scheduleSet_T_20)
node _scheduleSet_T_32 = or(_scheduleSet_T_31, _scheduleSet_T_21)
node _scheduleSet_T_33 = or(_scheduleSet_T_32, _scheduleSet_T_22)
node _scheduleSet_T_34 = or(_scheduleSet_T_33, _scheduleSet_T_23)
wire scheduleSet : UInt<11>
connect scheduleSet, _scheduleSet_T_34
node _T_9 = orr(mshr_request)
when _T_9 :
node _robin_filter_T = shr(mshr_selectOH, 1)
node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T)
node _robin_filter_T_2 = shr(_robin_filter_T_1, 2)
node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2)
node _robin_filter_T_4 = shr(_robin_filter_T_3, 4)
node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4)
node _robin_filter_T_6 = shr(_robin_filter_T_5, 8)
node _robin_filter_T_7 = or(_robin_filter_T_5, _robin_filter_T_6)
node _robin_filter_T_8 = bits(_robin_filter_T_7, 11, 0)
node _robin_filter_T_9 = not(_robin_filter_T_8)
connect robin_filter, _robin_filter_T_9
connect schedule.a.bits.source, mshr_select
node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1)
node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0))
connect schedule.c.bits.source, _schedule_c_bits_source_T_1
connect schedule.d.bits.sink, mshr_select
connect sourceA.io.req.valid, schedule.a.valid
connect sourceB.io.req.valid, schedule.b.valid
connect sourceC.io.req.valid, schedule.c.valid
connect sourceD.io.req.valid, schedule.d.valid
connect sourceE.io.req.valid, schedule.e.valid
connect sourceX.io.req.valid, schedule.x.valid
connect sourceA.io.req.bits.block, schedule.a.bits.block
connect sourceA.io.req.bits.source, schedule.a.bits.source
connect sourceA.io.req.bits.param, schedule.a.bits.param
connect sourceA.io.req.bits.set, schedule.a.bits.set
connect sourceA.io.req.bits.tag, schedule.a.bits.tag
connect sourceB.io.req.bits.clients, schedule.b.bits.clients
connect sourceB.io.req.bits.set, schedule.b.bits.set
connect sourceB.io.req.bits.tag, schedule.b.bits.tag
connect sourceB.io.req.bits.param, schedule.b.bits.param
connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty
connect sourceC.io.req.bits.way, schedule.c.bits.way
connect sourceC.io.req.bits.set, schedule.c.bits.set
connect sourceC.io.req.bits.tag, schedule.c.bits.tag
connect sourceC.io.req.bits.source, schedule.c.bits.source
connect sourceC.io.req.bits.param, schedule.c.bits.param
connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode
connect sourceD.io.req.bits.bad, schedule.d.bits.bad
connect sourceD.io.req.bits.way, schedule.d.bits.way
connect sourceD.io.req.bits.sink, schedule.d.bits.sink
connect sourceD.io.req.bits.set, schedule.d.bits.set
connect sourceD.io.req.bits.put, schedule.d.bits.put
connect sourceD.io.req.bits.offset, schedule.d.bits.offset
connect sourceD.io.req.bits.tag, schedule.d.bits.tag
connect sourceD.io.req.bits.source, schedule.d.bits.source
connect sourceD.io.req.bits.size, schedule.d.bits.size
connect sourceD.io.req.bits.param, schedule.d.bits.param
connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode
connect sourceD.io.req.bits.control, schedule.d.bits.control
connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0]
connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1]
connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2]
connect sourceE.io.req.bits.sink, schedule.e.bits.sink
connect sourceX.io.req.bits.fail, schedule.x.bits.fail
connect directory.io.write.valid, schedule.dir.valid
connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag
connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients
connect directory.io.write.bits.data.state, schedule.dir.bits.data.state
connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty
connect directory.io.write.bits.way, schedule.dir.bits.way
connect directory.io.write.bits.set, schedule.dir.bits.set
node select_c = bits(mshr_selectOH, 11, 11)
node select_bc = bits(mshr_selectOH, 10, 10)
node _nestedwb_set_T = mux(select_c, mshrs_11.io.status.bits.set, mshrs_10.io.status.bits.set)
connect nestedwb.set, _nestedwb_set_T
node _nestedwb_tag_T = mux(select_c, mshrs_11.io.status.bits.tag, mshrs_10.io.status.bits.tag)
connect nestedwb.tag, _nestedwb_tag_T
node _nestedwb_b_toN_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toN_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0))
node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1)
connect nestedwb.b_toN, _nestedwb_b_toN_T_2
node _nestedwb_b_toB_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toB_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1))
node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1)
connect nestedwb.b_toB, _nestedwb_b_toB_T_2
node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T
node _nestedwb_c_set_dirty_T = and(select_c, mshrs_11.io.schedule.bits.dir.valid)
node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_11.io.schedule.bits.dir.bits.data.dirty)
connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1
wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}}
node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid)
node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid)
node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1)
connect request.valid, _request_valid_T_2
node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits)
node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T)
connect request.bits, _request_bits_T_1
node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready)
connect sinkC.io.req.ready, _sinkC_io_req_ready_T
node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1)
connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2
node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1)
node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3)
connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4
node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set)
node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T)
node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set)
node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2)
node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set)
node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4)
node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set)
node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6)
node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set)
node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8)
node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set)
node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10)
node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set)
node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12)
node _setMatches_T_14 = eq(mshrs_7.io.status.bits.set, request.bits.set)
node _setMatches_T_15 = and(mshrs_7.io.status.valid, _setMatches_T_14)
node _setMatches_T_16 = eq(mshrs_8.io.status.bits.set, request.bits.set)
node _setMatches_T_17 = and(mshrs_8.io.status.valid, _setMatches_T_16)
node _setMatches_T_18 = eq(mshrs_9.io.status.bits.set, request.bits.set)
node _setMatches_T_19 = and(mshrs_9.io.status.valid, _setMatches_T_18)
node _setMatches_T_20 = eq(mshrs_10.io.status.bits.set, request.bits.set)
node _setMatches_T_21 = and(mshrs_10.io.status.valid, _setMatches_T_20)
node _setMatches_T_22 = eq(mshrs_11.io.status.bits.set, request.bits.set)
node _setMatches_T_23 = and(mshrs_11.io.status.valid, _setMatches_T_22)
node setMatches_lo_lo_hi = cat(_setMatches_T_5, _setMatches_T_3)
node setMatches_lo_lo = cat(setMatches_lo_lo_hi, _setMatches_T_1)
node setMatches_lo_hi_hi = cat(_setMatches_T_11, _setMatches_T_9)
node setMatches_lo_hi = cat(setMatches_lo_hi_hi, _setMatches_T_7)
node setMatches_lo = cat(setMatches_lo_hi, setMatches_lo_lo)
node setMatches_hi_lo_hi = cat(_setMatches_T_17, _setMatches_T_15)
node setMatches_hi_lo = cat(setMatches_hi_lo_hi, _setMatches_T_13)
node setMatches_hi_hi_hi = cat(_setMatches_T_23, _setMatches_T_21)
node setMatches_hi_hi = cat(setMatches_hi_hi_hi, _setMatches_T_19)
node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo)
node setMatches = cat(setMatches_hi, setMatches_lo)
node _alloc_T = orr(setMatches)
node alloc = eq(_alloc_T, UInt<1>(0h0))
node _blockB_T = bits(setMatches, 0, 0)
node _blockB_T_1 = bits(setMatches, 1, 1)
node _blockB_T_2 = bits(setMatches, 2, 2)
node _blockB_T_3 = bits(setMatches, 3, 3)
node _blockB_T_4 = bits(setMatches, 4, 4)
node _blockB_T_5 = bits(setMatches, 5, 5)
node _blockB_T_6 = bits(setMatches, 6, 6)
node _blockB_T_7 = bits(setMatches, 7, 7)
node _blockB_T_8 = bits(setMatches, 8, 8)
node _blockB_T_9 = bits(setMatches, 9, 9)
node _blockB_T_10 = bits(setMatches, 10, 10)
node _blockB_T_11 = bits(setMatches, 11, 11)
node _blockB_T_12 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_13 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_14 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_15 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_16 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_17 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_18 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_19 = mux(_blockB_T_7, mshrs_7.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_20 = mux(_blockB_T_8, mshrs_8.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_21 = mux(_blockB_T_9, mshrs_9.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_22 = mux(_blockB_T_10, mshrs_10.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_23 = mux(_blockB_T_11, mshrs_11.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_24 = or(_blockB_T_12, _blockB_T_13)
node _blockB_T_25 = or(_blockB_T_24, _blockB_T_14)
node _blockB_T_26 = or(_blockB_T_25, _blockB_T_15)
node _blockB_T_27 = or(_blockB_T_26, _blockB_T_16)
node _blockB_T_28 = or(_blockB_T_27, _blockB_T_17)
node _blockB_T_29 = or(_blockB_T_28, _blockB_T_18)
node _blockB_T_30 = or(_blockB_T_29, _blockB_T_19)
node _blockB_T_31 = or(_blockB_T_30, _blockB_T_20)
node _blockB_T_32 = or(_blockB_T_31, _blockB_T_21)
node _blockB_T_33 = or(_blockB_T_32, _blockB_T_22)
node _blockB_T_34 = or(_blockB_T_33, _blockB_T_23)
wire _blockB_WIRE : UInt<1>
connect _blockB_WIRE, _blockB_T_34
node blockB = and(_blockB_WIRE, request.bits.prio[1])
node _blockC_T = bits(setMatches, 0, 0)
node _blockC_T_1 = bits(setMatches, 1, 1)
node _blockC_T_2 = bits(setMatches, 2, 2)
node _blockC_T_3 = bits(setMatches, 3, 3)
node _blockC_T_4 = bits(setMatches, 4, 4)
node _blockC_T_5 = bits(setMatches, 5, 5)
node _blockC_T_6 = bits(setMatches, 6, 6)
node _blockC_T_7 = bits(setMatches, 7, 7)
node _blockC_T_8 = bits(setMatches, 8, 8)
node _blockC_T_9 = bits(setMatches, 9, 9)
node _blockC_T_10 = bits(setMatches, 10, 10)
node _blockC_T_11 = bits(setMatches, 11, 11)
node _blockC_T_12 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_13 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_14 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_15 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_16 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_17 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_18 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_19 = mux(_blockC_T_7, mshrs_7.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_20 = mux(_blockC_T_8, mshrs_8.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_21 = mux(_blockC_T_9, mshrs_9.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_22 = mux(_blockC_T_10, mshrs_10.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_23 = mux(_blockC_T_11, mshrs_11.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_24 = or(_blockC_T_12, _blockC_T_13)
node _blockC_T_25 = or(_blockC_T_24, _blockC_T_14)
node _blockC_T_26 = or(_blockC_T_25, _blockC_T_15)
node _blockC_T_27 = or(_blockC_T_26, _blockC_T_16)
node _blockC_T_28 = or(_blockC_T_27, _blockC_T_17)
node _blockC_T_29 = or(_blockC_T_28, _blockC_T_18)
node _blockC_T_30 = or(_blockC_T_29, _blockC_T_19)
node _blockC_T_31 = or(_blockC_T_30, _blockC_T_20)
node _blockC_T_32 = or(_blockC_T_31, _blockC_T_21)
node _blockC_T_33 = or(_blockC_T_32, _blockC_T_22)
node _blockC_T_34 = or(_blockC_T_33, _blockC_T_23)
wire _blockC_WIRE : UInt<1>
connect _blockC_WIRE, _blockC_T_34
node blockC = and(_blockC_WIRE, request.bits.prio[2])
node _nestB_T = bits(setMatches, 0, 0)
node _nestB_T_1 = bits(setMatches, 1, 1)
node _nestB_T_2 = bits(setMatches, 2, 2)
node _nestB_T_3 = bits(setMatches, 3, 3)
node _nestB_T_4 = bits(setMatches, 4, 4)
node _nestB_T_5 = bits(setMatches, 5, 5)
node _nestB_T_6 = bits(setMatches, 6, 6)
node _nestB_T_7 = bits(setMatches, 7, 7)
node _nestB_T_8 = bits(setMatches, 8, 8)
node _nestB_T_9 = bits(setMatches, 9, 9)
node _nestB_T_10 = bits(setMatches, 10, 10)
node _nestB_T_11 = bits(setMatches, 11, 11)
node _nestB_T_12 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_13 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_14 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_15 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_16 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_17 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_18 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_19 = mux(_nestB_T_7, mshrs_7.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_20 = mux(_nestB_T_8, mshrs_8.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_21 = mux(_nestB_T_9, mshrs_9.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_22 = mux(_nestB_T_10, mshrs_10.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_23 = mux(_nestB_T_11, mshrs_11.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_24 = or(_nestB_T_12, _nestB_T_13)
node _nestB_T_25 = or(_nestB_T_24, _nestB_T_14)
node _nestB_T_26 = or(_nestB_T_25, _nestB_T_15)
node _nestB_T_27 = or(_nestB_T_26, _nestB_T_16)
node _nestB_T_28 = or(_nestB_T_27, _nestB_T_17)
node _nestB_T_29 = or(_nestB_T_28, _nestB_T_18)
node _nestB_T_30 = or(_nestB_T_29, _nestB_T_19)
node _nestB_T_31 = or(_nestB_T_30, _nestB_T_20)
node _nestB_T_32 = or(_nestB_T_31, _nestB_T_21)
node _nestB_T_33 = or(_nestB_T_32, _nestB_T_22)
node _nestB_T_34 = or(_nestB_T_33, _nestB_T_23)
wire _nestB_WIRE : UInt<1>
connect _nestB_WIRE, _nestB_T_34
node nestB = and(_nestB_WIRE, request.bits.prio[1])
node _nestC_T = bits(setMatches, 0, 0)
node _nestC_T_1 = bits(setMatches, 1, 1)
node _nestC_T_2 = bits(setMatches, 2, 2)
node _nestC_T_3 = bits(setMatches, 3, 3)
node _nestC_T_4 = bits(setMatches, 4, 4)
node _nestC_T_5 = bits(setMatches, 5, 5)
node _nestC_T_6 = bits(setMatches, 6, 6)
node _nestC_T_7 = bits(setMatches, 7, 7)
node _nestC_T_8 = bits(setMatches, 8, 8)
node _nestC_T_9 = bits(setMatches, 9, 9)
node _nestC_T_10 = bits(setMatches, 10, 10)
node _nestC_T_11 = bits(setMatches, 11, 11)
node _nestC_T_12 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_13 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_14 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_15 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_16 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_17 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_18 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_19 = mux(_nestC_T_7, mshrs_7.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_20 = mux(_nestC_T_8, mshrs_8.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_21 = mux(_nestC_T_9, mshrs_9.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_22 = mux(_nestC_T_10, mshrs_10.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_23 = mux(_nestC_T_11, mshrs_11.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_24 = or(_nestC_T_12, _nestC_T_13)
node _nestC_T_25 = or(_nestC_T_24, _nestC_T_14)
node _nestC_T_26 = or(_nestC_T_25, _nestC_T_15)
node _nestC_T_27 = or(_nestC_T_26, _nestC_T_16)
node _nestC_T_28 = or(_nestC_T_27, _nestC_T_17)
node _nestC_T_29 = or(_nestC_T_28, _nestC_T_18)
node _nestC_T_30 = or(_nestC_T_29, _nestC_T_19)
node _nestC_T_31 = or(_nestC_T_30, _nestC_T_20)
node _nestC_T_32 = or(_nestC_T_31, _nestC_T_21)
node _nestC_T_33 = or(_nestC_T_32, _nestC_T_22)
node _nestC_T_34 = or(_nestC_T_33, _nestC_T_23)
wire _nestC_WIRE : UInt<1>
connect _nestC_WIRE, _nestC_T_34
node nestC = and(_nestC_WIRE, request.bits.prio[2])
node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0))
node _prioFilter_T_1 = not(UInt<10>(0h0))
node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T)
node prioFilter = cat(prioFilter_hi, _prioFilter_T_1)
node lowerMatches = and(setMatches, prioFilter)
node _queue_T = orr(lowerMatches)
node _queue_T_1 = eq(nestB, UInt<1>(0h0))
node _queue_T_2 = and(_queue_T, _queue_T_1)
node _queue_T_3 = eq(nestC, UInt<1>(0h0))
node _queue_T_4 = and(_queue_T_2, _queue_T_3)
node _queue_T_5 = eq(blockB, UInt<1>(0h0))
node _queue_T_6 = and(_queue_T_4, _queue_T_5)
node _queue_T_7 = eq(blockC, UInt<1>(0h0))
node queue = and(_queue_T_6, _queue_T_7)
node _T_10 = and(request.valid, blockC)
node _T_11 = and(request.valid, nestC)
node _T_12 = and(request.valid, queue)
node _lowerMatches1_T = bits(lowerMatches, 11, 11)
node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 11)
node _lowerMatches1_T_2 = bits(lowerMatches, 10, 10)
node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 10)
node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches)
node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4)
node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH)
node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH)
node selected_requests = and(_selected_requests_T, requests.io.valid)
node _a_pop_T = bits(selected_requests, 11, 0)
node a_pop = orr(_a_pop_T)
node _b_pop_T = bits(selected_requests, 23, 12)
node b_pop = orr(_b_pop_T)
node _c_pop_T = bits(selected_requests, 35, 24)
node c_pop = orr(_c_pop_T)
node _bypassMatches_T = and(mshr_selectOH, lowerMatches1)
node _bypassMatches_T_1 = orr(_bypassMatches_T)
node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2])
node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0))
node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1])
node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0))
node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0))
node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6)
node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7)
node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8)
node _may_pop_T = or(a_pop, b_pop)
node may_pop = or(_may_pop_T, c_pop)
node _bypass_T = and(request.valid, queue)
node bypass = and(_bypass_T, bypassMatches)
node _will_reload_T = or(may_pop, bypass)
node will_reload = and(schedule.reload, _will_reload_T)
node _will_pop_T = and(schedule.reload, may_pop)
node _will_pop_T_1 = eq(bypass, UInt<1>(0h0))
node will_pop = and(_will_pop_T, _will_pop_T_1)
node _T_13 = orr(mshr_selectOH)
node _T_14 = and(_T_13, bypass)
node _T_15 = orr(mshr_selectOH)
node _T_16 = and(_T_15, will_reload)
node _T_17 = orr(mshr_selectOH)
node _T_18 = and(_T_17, will_pop)
node sel = bits(mshr_selectOH, 0, 0)
connect mshrs_0.io.schedule.ready, sel
node a_pop_1 = bits(requests.io.valid, 0, 0)
node b_pop_1 = bits(requests.io.valid, 12, 12)
node c_pop_1 = bits(requests.io.valid, 24, 24)
node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0)
node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2])
node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0))
node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1])
node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0))
node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0))
node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14)
node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15)
node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16)
node _may_pop_T_1 = or(a_pop_1, b_pop_1)
node may_pop_1 = or(_may_pop_T_1, c_pop_1)
node _bypass_T_1 = and(request.valid, queue)
node bypass_1 = and(_bypass_T_1, bypassMatches_1)
node _will_reload_T_1 = or(may_pop_1, bypass_1)
node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1)
wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE.put, request.bits.put
connect _view__WIRE.offset, request.bits.offset
connect _view__WIRE.tag, request.bits.tag
connect _view__WIRE.source, request.bits.source
connect _view__WIRE.size, request.bits.size
connect _view__WIRE.param, request.bits.param
connect _view__WIRE.opcode, request.bits.opcode
connect _view__WIRE.control, request.bits.control
connect _view__WIRE.prio, request.bits.prio
node _view__T = mux(bypass_1, _view__WIRE, requests.io.data)
connect mshrs_0.io.allocate.bits.put, _view__T.put
connect mshrs_0.io.allocate.bits.offset, _view__T.offset
connect mshrs_0.io.allocate.bits.tag, _view__T.tag
connect mshrs_0.io.allocate.bits.source, _view__T.source
connect mshrs_0.io.allocate.bits.size, _view__T.size
connect mshrs_0.io.allocate.bits.param, _view__T.param
connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode
connect mshrs_0.io.allocate.bits.control, _view__T.control
connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2]
connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set
node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag)
connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T
node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1)
connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T
node sel_1 = bits(mshr_selectOH, 1, 1)
connect mshrs_1.io.schedule.ready, sel_1
node a_pop_2 = bits(requests.io.valid, 1, 1)
node b_pop_2 = bits(requests.io.valid, 13, 13)
node c_pop_2 = bits(requests.io.valid, 25, 25)
node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1)
node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2])
node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0))
node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1])
node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0))
node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0))
node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22)
node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23)
node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24)
node _may_pop_T_2 = or(a_pop_2, b_pop_2)
node may_pop_2 = or(_may_pop_T_2, c_pop_2)
node _bypass_T_2 = and(request.valid, queue)
node bypass_2 = and(_bypass_T_2, bypassMatches_2)
node _will_reload_T_2 = or(may_pop_2, bypass_2)
node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2)
wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_1.put, request.bits.put
connect _view__WIRE_1.offset, request.bits.offset
connect _view__WIRE_1.tag, request.bits.tag
connect _view__WIRE_1.source, request.bits.source
connect _view__WIRE_1.size, request.bits.size
connect _view__WIRE_1.param, request.bits.param
connect _view__WIRE_1.opcode, request.bits.opcode
connect _view__WIRE_1.control, request.bits.control
connect _view__WIRE_1.prio, request.bits.prio
node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data)
connect mshrs_1.io.allocate.bits.put, _view__T_1.put
connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset
connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag
connect mshrs_1.io.allocate.bits.source, _view__T_1.source
connect mshrs_1.io.allocate.bits.size, _view__T_1.size
connect mshrs_1.io.allocate.bits.param, _view__T_1.param
connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode
connect mshrs_1.io.allocate.bits.control, _view__T_1.control
connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2]
connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set
node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag)
connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T
node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2)
connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T
node sel_2 = bits(mshr_selectOH, 2, 2)
connect mshrs_2.io.schedule.ready, sel_2
node a_pop_3 = bits(requests.io.valid, 2, 2)
node b_pop_3 = bits(requests.io.valid, 14, 14)
node c_pop_3 = bits(requests.io.valid, 26, 26)
node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2)
node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2])
node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0))
node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1])
node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0))
node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0))
node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30)
node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31)
node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32)
node _may_pop_T_3 = or(a_pop_3, b_pop_3)
node may_pop_3 = or(_may_pop_T_3, c_pop_3)
node _bypass_T_3 = and(request.valid, queue)
node bypass_3 = and(_bypass_T_3, bypassMatches_3)
node _will_reload_T_3 = or(may_pop_3, bypass_3)
node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3)
wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_2.put, request.bits.put
connect _view__WIRE_2.offset, request.bits.offset
connect _view__WIRE_2.tag, request.bits.tag
connect _view__WIRE_2.source, request.bits.source
connect _view__WIRE_2.size, request.bits.size
connect _view__WIRE_2.param, request.bits.param
connect _view__WIRE_2.opcode, request.bits.opcode
connect _view__WIRE_2.control, request.bits.control
connect _view__WIRE_2.prio, request.bits.prio
node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data)
connect mshrs_2.io.allocate.bits.put, _view__T_2.put
connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset
connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag
connect mshrs_2.io.allocate.bits.source, _view__T_2.source
connect mshrs_2.io.allocate.bits.size, _view__T_2.size
connect mshrs_2.io.allocate.bits.param, _view__T_2.param
connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode
connect mshrs_2.io.allocate.bits.control, _view__T_2.control
connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2]
connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set
node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag)
connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T
node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3)
connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T
node sel_3 = bits(mshr_selectOH, 3, 3)
connect mshrs_3.io.schedule.ready, sel_3
node a_pop_4 = bits(requests.io.valid, 3, 3)
node b_pop_4 = bits(requests.io.valid, 15, 15)
node c_pop_4 = bits(requests.io.valid, 27, 27)
node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3)
node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2])
node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0))
node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1])
node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0))
node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0))
node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38)
node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39)
node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40)
node _may_pop_T_4 = or(a_pop_4, b_pop_4)
node may_pop_4 = or(_may_pop_T_4, c_pop_4)
node _bypass_T_4 = and(request.valid, queue)
node bypass_4 = and(_bypass_T_4, bypassMatches_4)
node _will_reload_T_4 = or(may_pop_4, bypass_4)
node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4)
wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_3.put, request.bits.put
connect _view__WIRE_3.offset, request.bits.offset
connect _view__WIRE_3.tag, request.bits.tag
connect _view__WIRE_3.source, request.bits.source
connect _view__WIRE_3.size, request.bits.size
connect _view__WIRE_3.param, request.bits.param
connect _view__WIRE_3.opcode, request.bits.opcode
connect _view__WIRE_3.control, request.bits.control
connect _view__WIRE_3.prio, request.bits.prio
node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data)
connect mshrs_3.io.allocate.bits.put, _view__T_3.put
connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset
connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag
connect mshrs_3.io.allocate.bits.source, _view__T_3.source
connect mshrs_3.io.allocate.bits.size, _view__T_3.size
connect mshrs_3.io.allocate.bits.param, _view__T_3.param
connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode
connect mshrs_3.io.allocate.bits.control, _view__T_3.control
connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2]
connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set
node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag)
connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T
node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4)
connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T
node sel_4 = bits(mshr_selectOH, 4, 4)
connect mshrs_4.io.schedule.ready, sel_4
node a_pop_5 = bits(requests.io.valid, 4, 4)
node b_pop_5 = bits(requests.io.valid, 16, 16)
node c_pop_5 = bits(requests.io.valid, 28, 28)
node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4)
node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2])
node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0))
node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1])
node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0))
node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0))
node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46)
node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47)
node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48)
node _may_pop_T_5 = or(a_pop_5, b_pop_5)
node may_pop_5 = or(_may_pop_T_5, c_pop_5)
node _bypass_T_5 = and(request.valid, queue)
node bypass_5 = and(_bypass_T_5, bypassMatches_5)
node _will_reload_T_5 = or(may_pop_5, bypass_5)
node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5)
wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_4.put, request.bits.put
connect _view__WIRE_4.offset, request.bits.offset
connect _view__WIRE_4.tag, request.bits.tag
connect _view__WIRE_4.source, request.bits.source
connect _view__WIRE_4.size, request.bits.size
connect _view__WIRE_4.param, request.bits.param
connect _view__WIRE_4.opcode, request.bits.opcode
connect _view__WIRE_4.control, request.bits.control
connect _view__WIRE_4.prio, request.bits.prio
node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data)
connect mshrs_4.io.allocate.bits.put, _view__T_4.put
connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset
connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag
connect mshrs_4.io.allocate.bits.source, _view__T_4.source
connect mshrs_4.io.allocate.bits.size, _view__T_4.size
connect mshrs_4.io.allocate.bits.param, _view__T_4.param
connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode
connect mshrs_4.io.allocate.bits.control, _view__T_4.control
connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2]
connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set
node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag)
connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T
node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5)
connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T
node sel_5 = bits(mshr_selectOH, 5, 5)
connect mshrs_5.io.schedule.ready, sel_5
node a_pop_6 = bits(requests.io.valid, 5, 5)
node b_pop_6 = bits(requests.io.valid, 17, 17)
node c_pop_6 = bits(requests.io.valid, 29, 29)
node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5)
node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2])
node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0))
node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1])
node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0))
node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0))
node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54)
node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55)
node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56)
node _may_pop_T_6 = or(a_pop_6, b_pop_6)
node may_pop_6 = or(_may_pop_T_6, c_pop_6)
node _bypass_T_6 = and(request.valid, queue)
node bypass_6 = and(_bypass_T_6, bypassMatches_6)
node _will_reload_T_6 = or(may_pop_6, bypass_6)
node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6)
wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_5.put, request.bits.put
connect _view__WIRE_5.offset, request.bits.offset
connect _view__WIRE_5.tag, request.bits.tag
connect _view__WIRE_5.source, request.bits.source
connect _view__WIRE_5.size, request.bits.size
connect _view__WIRE_5.param, request.bits.param
connect _view__WIRE_5.opcode, request.bits.opcode
connect _view__WIRE_5.control, request.bits.control
connect _view__WIRE_5.prio, request.bits.prio
node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data)
connect mshrs_5.io.allocate.bits.put, _view__T_5.put
connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset
connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag
connect mshrs_5.io.allocate.bits.source, _view__T_5.source
connect mshrs_5.io.allocate.bits.size, _view__T_5.size
connect mshrs_5.io.allocate.bits.param, _view__T_5.param
connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode
connect mshrs_5.io.allocate.bits.control, _view__T_5.control
connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2]
connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set
node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag)
connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T
node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6)
connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T
node sel_6 = bits(mshr_selectOH, 6, 6)
connect mshrs_6.io.schedule.ready, sel_6
node a_pop_7 = bits(requests.io.valid, 6, 6)
node b_pop_7 = bits(requests.io.valid, 18, 18)
node c_pop_7 = bits(requests.io.valid, 30, 30)
node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6)
node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2])
node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0))
node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1])
node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0))
node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0))
node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62)
node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63)
node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64)
node _may_pop_T_7 = or(a_pop_7, b_pop_7)
node may_pop_7 = or(_may_pop_T_7, c_pop_7)
node _bypass_T_7 = and(request.valid, queue)
node bypass_7 = and(_bypass_T_7, bypassMatches_7)
node _will_reload_T_7 = or(may_pop_7, bypass_7)
node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7)
wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_6.put, request.bits.put
connect _view__WIRE_6.offset, request.bits.offset
connect _view__WIRE_6.tag, request.bits.tag
connect _view__WIRE_6.source, request.bits.source
connect _view__WIRE_6.size, request.bits.size
connect _view__WIRE_6.param, request.bits.param
connect _view__WIRE_6.opcode, request.bits.opcode
connect _view__WIRE_6.control, request.bits.control
connect _view__WIRE_6.prio, request.bits.prio
node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data)
connect mshrs_6.io.allocate.bits.put, _view__T_6.put
connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset
connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag
connect mshrs_6.io.allocate.bits.source, _view__T_6.source
connect mshrs_6.io.allocate.bits.size, _view__T_6.size
connect mshrs_6.io.allocate.bits.param, _view__T_6.param
connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode
connect mshrs_6.io.allocate.bits.control, _view__T_6.control
connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2]
connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set
node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag)
connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T
node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7)
connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T
node sel_7 = bits(mshr_selectOH, 7, 7)
connect mshrs_7.io.schedule.ready, sel_7
node a_pop_8 = bits(requests.io.valid, 7, 7)
node b_pop_8 = bits(requests.io.valid, 19, 19)
node c_pop_8 = bits(requests.io.valid, 31, 31)
node _bypassMatches_T_65 = bits(lowerMatches1, 7, 7)
node _bypassMatches_T_66 = or(c_pop_8, request.bits.prio[2])
node _bypassMatches_T_67 = eq(c_pop_8, UInt<1>(0h0))
node _bypassMatches_T_68 = or(b_pop_8, request.bits.prio[1])
node _bypassMatches_T_69 = eq(b_pop_8, UInt<1>(0h0))
node _bypassMatches_T_70 = eq(a_pop_8, UInt<1>(0h0))
node _bypassMatches_T_71 = mux(_bypassMatches_T_68, _bypassMatches_T_69, _bypassMatches_T_70)
node _bypassMatches_T_72 = mux(_bypassMatches_T_66, _bypassMatches_T_67, _bypassMatches_T_71)
node bypassMatches_8 = and(_bypassMatches_T_65, _bypassMatches_T_72)
node _may_pop_T_8 = or(a_pop_8, b_pop_8)
node may_pop_8 = or(_may_pop_T_8, c_pop_8)
node _bypass_T_8 = and(request.valid, queue)
node bypass_8 = and(_bypass_T_8, bypassMatches_8)
node _will_reload_T_8 = or(may_pop_8, bypass_8)
node will_reload_8 = and(mshrs_7.io.schedule.bits.reload, _will_reload_T_8)
wire _view__WIRE_7 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_7.put, request.bits.put
connect _view__WIRE_7.offset, request.bits.offset
connect _view__WIRE_7.tag, request.bits.tag
connect _view__WIRE_7.source, request.bits.source
connect _view__WIRE_7.size, request.bits.size
connect _view__WIRE_7.param, request.bits.param
connect _view__WIRE_7.opcode, request.bits.opcode
connect _view__WIRE_7.control, request.bits.control
connect _view__WIRE_7.prio, request.bits.prio
node _view__T_7 = mux(bypass_8, _view__WIRE_7, requests.io.data)
connect mshrs_7.io.allocate.bits.put, _view__T_7.put
connect mshrs_7.io.allocate.bits.offset, _view__T_7.offset
connect mshrs_7.io.allocate.bits.tag, _view__T_7.tag
connect mshrs_7.io.allocate.bits.source, _view__T_7.source
connect mshrs_7.io.allocate.bits.size, _view__T_7.size
connect mshrs_7.io.allocate.bits.param, _view__T_7.param
connect mshrs_7.io.allocate.bits.opcode, _view__T_7.opcode
connect mshrs_7.io.allocate.bits.control, _view__T_7.control
connect mshrs_7.io.allocate.bits.prio[0], _view__T_7.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], _view__T_7.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], _view__T_7.prio[2]
connect mshrs_7.io.allocate.bits.set, mshrs_7.io.status.bits.set
node _mshrs_7_io_allocate_bits_repeat_T = eq(mshrs_7.io.allocate.bits.tag, mshrs_7.io.status.bits.tag)
connect mshrs_7.io.allocate.bits.repeat, _mshrs_7_io_allocate_bits_repeat_T
node _mshrs_7_io_allocate_valid_T = and(sel_7, will_reload_8)
connect mshrs_7.io.allocate.valid, _mshrs_7_io_allocate_valid_T
node sel_8 = bits(mshr_selectOH, 8, 8)
connect mshrs_8.io.schedule.ready, sel_8
node a_pop_9 = bits(requests.io.valid, 8, 8)
node b_pop_9 = bits(requests.io.valid, 20, 20)
node c_pop_9 = bits(requests.io.valid, 32, 32)
node _bypassMatches_T_73 = bits(lowerMatches1, 8, 8)
node _bypassMatches_T_74 = or(c_pop_9, request.bits.prio[2])
node _bypassMatches_T_75 = eq(c_pop_9, UInt<1>(0h0))
node _bypassMatches_T_76 = or(b_pop_9, request.bits.prio[1])
node _bypassMatches_T_77 = eq(b_pop_9, UInt<1>(0h0))
node _bypassMatches_T_78 = eq(a_pop_9, UInt<1>(0h0))
node _bypassMatches_T_79 = mux(_bypassMatches_T_76, _bypassMatches_T_77, _bypassMatches_T_78)
node _bypassMatches_T_80 = mux(_bypassMatches_T_74, _bypassMatches_T_75, _bypassMatches_T_79)
node bypassMatches_9 = and(_bypassMatches_T_73, _bypassMatches_T_80)
node _may_pop_T_9 = or(a_pop_9, b_pop_9)
node may_pop_9 = or(_may_pop_T_9, c_pop_9)
node _bypass_T_9 = and(request.valid, queue)
node bypass_9 = and(_bypass_T_9, bypassMatches_9)
node _will_reload_T_9 = or(may_pop_9, bypass_9)
node will_reload_9 = and(mshrs_8.io.schedule.bits.reload, _will_reload_T_9)
wire _view__WIRE_8 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_8.put, request.bits.put
connect _view__WIRE_8.offset, request.bits.offset
connect _view__WIRE_8.tag, request.bits.tag
connect _view__WIRE_8.source, request.bits.source
connect _view__WIRE_8.size, request.bits.size
connect _view__WIRE_8.param, request.bits.param
connect _view__WIRE_8.opcode, request.bits.opcode
connect _view__WIRE_8.control, request.bits.control
connect _view__WIRE_8.prio, request.bits.prio
node _view__T_8 = mux(bypass_9, _view__WIRE_8, requests.io.data)
connect mshrs_8.io.allocate.bits.put, _view__T_8.put
connect mshrs_8.io.allocate.bits.offset, _view__T_8.offset
connect mshrs_8.io.allocate.bits.tag, _view__T_8.tag
connect mshrs_8.io.allocate.bits.source, _view__T_8.source
connect mshrs_8.io.allocate.bits.size, _view__T_8.size
connect mshrs_8.io.allocate.bits.param, _view__T_8.param
connect mshrs_8.io.allocate.bits.opcode, _view__T_8.opcode
connect mshrs_8.io.allocate.bits.control, _view__T_8.control
connect mshrs_8.io.allocate.bits.prio[0], _view__T_8.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], _view__T_8.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], _view__T_8.prio[2]
connect mshrs_8.io.allocate.bits.set, mshrs_8.io.status.bits.set
node _mshrs_8_io_allocate_bits_repeat_T = eq(mshrs_8.io.allocate.bits.tag, mshrs_8.io.status.bits.tag)
connect mshrs_8.io.allocate.bits.repeat, _mshrs_8_io_allocate_bits_repeat_T
node _mshrs_8_io_allocate_valid_T = and(sel_8, will_reload_9)
connect mshrs_8.io.allocate.valid, _mshrs_8_io_allocate_valid_T
node sel_9 = bits(mshr_selectOH, 9, 9)
connect mshrs_9.io.schedule.ready, sel_9
node a_pop_10 = bits(requests.io.valid, 9, 9)
node b_pop_10 = bits(requests.io.valid, 21, 21)
node c_pop_10 = bits(requests.io.valid, 33, 33)
node _bypassMatches_T_81 = bits(lowerMatches1, 9, 9)
node _bypassMatches_T_82 = or(c_pop_10, request.bits.prio[2])
node _bypassMatches_T_83 = eq(c_pop_10, UInt<1>(0h0))
node _bypassMatches_T_84 = or(b_pop_10, request.bits.prio[1])
node _bypassMatches_T_85 = eq(b_pop_10, UInt<1>(0h0))
node _bypassMatches_T_86 = eq(a_pop_10, UInt<1>(0h0))
node _bypassMatches_T_87 = mux(_bypassMatches_T_84, _bypassMatches_T_85, _bypassMatches_T_86)
node _bypassMatches_T_88 = mux(_bypassMatches_T_82, _bypassMatches_T_83, _bypassMatches_T_87)
node bypassMatches_10 = and(_bypassMatches_T_81, _bypassMatches_T_88)
node _may_pop_T_10 = or(a_pop_10, b_pop_10)
node may_pop_10 = or(_may_pop_T_10, c_pop_10)
node _bypass_T_10 = and(request.valid, queue)
node bypass_10 = and(_bypass_T_10, bypassMatches_10)
node _will_reload_T_10 = or(may_pop_10, bypass_10)
node will_reload_10 = and(mshrs_9.io.schedule.bits.reload, _will_reload_T_10)
wire _view__WIRE_9 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_9.put, request.bits.put
connect _view__WIRE_9.offset, request.bits.offset
connect _view__WIRE_9.tag, request.bits.tag
connect _view__WIRE_9.source, request.bits.source
connect _view__WIRE_9.size, request.bits.size
connect _view__WIRE_9.param, request.bits.param
connect _view__WIRE_9.opcode, request.bits.opcode
connect _view__WIRE_9.control, request.bits.control
connect _view__WIRE_9.prio, request.bits.prio
node _view__T_9 = mux(bypass_10, _view__WIRE_9, requests.io.data)
connect mshrs_9.io.allocate.bits.put, _view__T_9.put
connect mshrs_9.io.allocate.bits.offset, _view__T_9.offset
connect mshrs_9.io.allocate.bits.tag, _view__T_9.tag
connect mshrs_9.io.allocate.bits.source, _view__T_9.source
connect mshrs_9.io.allocate.bits.size, _view__T_9.size
connect mshrs_9.io.allocate.bits.param, _view__T_9.param
connect mshrs_9.io.allocate.bits.opcode, _view__T_9.opcode
connect mshrs_9.io.allocate.bits.control, _view__T_9.control
connect mshrs_9.io.allocate.bits.prio[0], _view__T_9.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], _view__T_9.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], _view__T_9.prio[2]
connect mshrs_9.io.allocate.bits.set, mshrs_9.io.status.bits.set
node _mshrs_9_io_allocate_bits_repeat_T = eq(mshrs_9.io.allocate.bits.tag, mshrs_9.io.status.bits.tag)
connect mshrs_9.io.allocate.bits.repeat, _mshrs_9_io_allocate_bits_repeat_T
node _mshrs_9_io_allocate_valid_T = and(sel_9, will_reload_10)
connect mshrs_9.io.allocate.valid, _mshrs_9_io_allocate_valid_T
node sel_10 = bits(mshr_selectOH, 10, 10)
connect mshrs_10.io.schedule.ready, sel_10
node a_pop_11 = bits(requests.io.valid, 10, 10)
node b_pop_11 = bits(requests.io.valid, 22, 22)
node c_pop_11 = bits(requests.io.valid, 34, 34)
node _bypassMatches_T_89 = bits(lowerMatches1, 10, 10)
node _bypassMatches_T_90 = or(c_pop_11, request.bits.prio[2])
node _bypassMatches_T_91 = eq(c_pop_11, UInt<1>(0h0))
node _bypassMatches_T_92 = or(b_pop_11, request.bits.prio[1])
node _bypassMatches_T_93 = eq(b_pop_11, UInt<1>(0h0))
node _bypassMatches_T_94 = eq(a_pop_11, UInt<1>(0h0))
node _bypassMatches_T_95 = mux(_bypassMatches_T_92, _bypassMatches_T_93, _bypassMatches_T_94)
node _bypassMatches_T_96 = mux(_bypassMatches_T_90, _bypassMatches_T_91, _bypassMatches_T_95)
node bypassMatches_11 = and(_bypassMatches_T_89, _bypassMatches_T_96)
node _may_pop_T_11 = or(a_pop_11, b_pop_11)
node may_pop_11 = or(_may_pop_T_11, c_pop_11)
node _bypass_T_11 = and(request.valid, queue)
node bypass_11 = and(_bypass_T_11, bypassMatches_11)
node _will_reload_T_11 = or(may_pop_11, bypass_11)
node will_reload_11 = and(mshrs_10.io.schedule.bits.reload, _will_reload_T_11)
wire _view__WIRE_10 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_10.put, request.bits.put
connect _view__WIRE_10.offset, request.bits.offset
connect _view__WIRE_10.tag, request.bits.tag
connect _view__WIRE_10.source, request.bits.source
connect _view__WIRE_10.size, request.bits.size
connect _view__WIRE_10.param, request.bits.param
connect _view__WIRE_10.opcode, request.bits.opcode
connect _view__WIRE_10.control, request.bits.control
connect _view__WIRE_10.prio, request.bits.prio
node _view__T_10 = mux(bypass_11, _view__WIRE_10, requests.io.data)
connect mshrs_10.io.allocate.bits.put, _view__T_10.put
connect mshrs_10.io.allocate.bits.offset, _view__T_10.offset
connect mshrs_10.io.allocate.bits.tag, _view__T_10.tag
connect mshrs_10.io.allocate.bits.source, _view__T_10.source
connect mshrs_10.io.allocate.bits.size, _view__T_10.size
connect mshrs_10.io.allocate.bits.param, _view__T_10.param
connect mshrs_10.io.allocate.bits.opcode, _view__T_10.opcode
connect mshrs_10.io.allocate.bits.control, _view__T_10.control
connect mshrs_10.io.allocate.bits.prio[0], _view__T_10.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], _view__T_10.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], _view__T_10.prio[2]
connect mshrs_10.io.allocate.bits.set, mshrs_10.io.status.bits.set
node _mshrs_10_io_allocate_bits_repeat_T = eq(mshrs_10.io.allocate.bits.tag, mshrs_10.io.status.bits.tag)
connect mshrs_10.io.allocate.bits.repeat, _mshrs_10_io_allocate_bits_repeat_T
node _mshrs_10_io_allocate_valid_T = and(sel_10, will_reload_11)
connect mshrs_10.io.allocate.valid, _mshrs_10_io_allocate_valid_T
node sel_11 = bits(mshr_selectOH, 11, 11)
connect mshrs_11.io.schedule.ready, sel_11
node a_pop_12 = bits(requests.io.valid, 11, 11)
node b_pop_12 = bits(requests.io.valid, 23, 23)
node c_pop_12 = bits(requests.io.valid, 35, 35)
node _bypassMatches_T_97 = bits(lowerMatches1, 11, 11)
node _bypassMatches_T_98 = or(c_pop_12, request.bits.prio[2])
node _bypassMatches_T_99 = eq(c_pop_12, UInt<1>(0h0))
node _bypassMatches_T_100 = or(b_pop_12, request.bits.prio[1])
node _bypassMatches_T_101 = eq(b_pop_12, UInt<1>(0h0))
node _bypassMatches_T_102 = eq(a_pop_12, UInt<1>(0h0))
node _bypassMatches_T_103 = mux(_bypassMatches_T_100, _bypassMatches_T_101, _bypassMatches_T_102)
node _bypassMatches_T_104 = mux(_bypassMatches_T_98, _bypassMatches_T_99, _bypassMatches_T_103)
node bypassMatches_12 = and(_bypassMatches_T_97, _bypassMatches_T_104)
node _may_pop_T_12 = or(a_pop_12, b_pop_12)
node may_pop_12 = or(_may_pop_T_12, c_pop_12)
node _bypass_T_12 = and(request.valid, queue)
node bypass_12 = and(_bypass_T_12, bypassMatches_12)
node _will_reload_T_12 = or(may_pop_12, bypass_12)
node will_reload_12 = and(mshrs_11.io.schedule.bits.reload, _will_reload_T_12)
wire _view__WIRE_11 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_11.put, request.bits.put
connect _view__WIRE_11.offset, request.bits.offset
connect _view__WIRE_11.tag, request.bits.tag
connect _view__WIRE_11.source, request.bits.source
connect _view__WIRE_11.size, request.bits.size
connect _view__WIRE_11.param, request.bits.param
connect _view__WIRE_11.opcode, request.bits.opcode
connect _view__WIRE_11.control, request.bits.control
connect _view__WIRE_11.prio, request.bits.prio
node _view__T_11 = mux(bypass_12, _view__WIRE_11, requests.io.data)
connect mshrs_11.io.allocate.bits.put, _view__T_11.put
connect mshrs_11.io.allocate.bits.offset, _view__T_11.offset
connect mshrs_11.io.allocate.bits.tag, _view__T_11.tag
connect mshrs_11.io.allocate.bits.source, _view__T_11.source
connect mshrs_11.io.allocate.bits.size, _view__T_11.size
connect mshrs_11.io.allocate.bits.param, _view__T_11.param
connect mshrs_11.io.allocate.bits.opcode, _view__T_11.opcode
connect mshrs_11.io.allocate.bits.control, _view__T_11.control
connect mshrs_11.io.allocate.bits.prio[0], _view__T_11.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], _view__T_11.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], _view__T_11.prio[2]
connect mshrs_11.io.allocate.bits.set, mshrs_11.io.status.bits.set
node _mshrs_11_io_allocate_bits_repeat_T = eq(mshrs_11.io.allocate.bits.tag, mshrs_11.io.status.bits.tag)
connect mshrs_11.io.allocate.bits.repeat, _mshrs_11_io_allocate_bits_repeat_T
node _mshrs_11_io_allocate_valid_T = and(sel_11, will_reload_12)
connect mshrs_11.io.allocate.valid, _mshrs_11_io_allocate_valid_T
node _prio_requests_T = not(requests.io.valid)
node _prio_requests_T_1 = shr(requests.io.valid, 12)
node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1)
node _prio_requests_T_3 = shr(requests.io.valid, 24)
node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3)
node prio_requests = not(_prio_requests_T_4)
node pop_index_hi = cat(mshr_selectOH, mshr_selectOH)
node _pop_index_T = cat(pop_index_hi, mshr_selectOH)
node _pop_index_T_1 = and(_pop_index_T, prio_requests)
node pop_index_hi_1 = bits(_pop_index_T_1, 35, 32)
node pop_index_lo = bits(_pop_index_T_1, 31, 0)
node _pop_index_T_2 = orr(pop_index_hi_1)
node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo)
node pop_index_hi_2 = bits(_pop_index_T_3, 31, 16)
node pop_index_lo_1 = bits(_pop_index_T_3, 15, 0)
node _pop_index_T_4 = orr(pop_index_hi_2)
node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1)
node pop_index_hi_3 = bits(_pop_index_T_5, 15, 8)
node pop_index_lo_2 = bits(_pop_index_T_5, 7, 0)
node _pop_index_T_6 = orr(pop_index_hi_3)
node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2)
node pop_index_hi_4 = bits(_pop_index_T_7, 7, 4)
node pop_index_lo_3 = bits(_pop_index_T_7, 3, 0)
node _pop_index_T_8 = orr(pop_index_hi_4)
node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3)
node pop_index_hi_5 = bits(_pop_index_T_9, 3, 2)
node pop_index_lo_4 = bits(_pop_index_T_9, 1, 0)
node _pop_index_T_10 = orr(pop_index_hi_5)
node _pop_index_T_11 = or(pop_index_hi_5, pop_index_lo_4)
node _pop_index_T_12 = bits(_pop_index_T_11, 1, 1)
node _pop_index_T_13 = cat(_pop_index_T_10, _pop_index_T_12)
node _pop_index_T_14 = cat(_pop_index_T_8, _pop_index_T_13)
node _pop_index_T_15 = cat(_pop_index_T_6, _pop_index_T_14)
node _pop_index_T_16 = cat(_pop_index_T_4, _pop_index_T_15)
node pop_index = cat(_pop_index_T_2, _pop_index_T_16)
connect requests.io.pop.valid, will_pop
connect requests.io.pop.bits, pop_index
node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag)
node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop)
node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch)
node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch)
node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag)
node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T)
node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1)
node mshr_validOH_lo_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid)
node mshr_validOH_lo_lo = cat(mshr_validOH_lo_lo_hi, mshrs_0.io.status.valid)
node mshr_validOH_lo_hi_hi = cat(mshrs_5.io.status.valid, mshrs_4.io.status.valid)
node mshr_validOH_lo_hi = cat(mshr_validOH_lo_hi_hi, mshrs_3.io.status.valid)
node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshr_validOH_lo_lo)
node mshr_validOH_hi_lo_hi = cat(mshrs_8.io.status.valid, mshrs_7.io.status.valid)
node mshr_validOH_hi_lo = cat(mshr_validOH_hi_lo_hi, mshrs_6.io.status.valid)
node mshr_validOH_hi_hi_hi = cat(mshrs_11.io.status.valid, mshrs_10.io.status.valid)
node mshr_validOH_hi_hi = cat(mshr_validOH_hi_hi_hi, mshrs_9.io.status.valid)
node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo)
node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo)
node _mshr_free_T = not(mshr_validOH)
node _mshr_free_T_1 = and(_mshr_free_T, prioFilter)
node mshr_free = orr(_mshr_free_T_1)
node bypassQueue = and(schedule.reload, bypassMatches)
node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T)
node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free)
node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3)
node _request_alloc_cases_T_5 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5)
node _request_alloc_cases_T_7 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7)
node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8)
node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10)
node _request_alloc_cases_T_12 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12)
node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13)
node _request_ready_T = or(bypassQueue, requests.io.push.ready)
node _request_ready_T_1 = and(queue, _request_ready_T)
node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1)
connect request.ready, _request_ready_T_2
node alloc_uses_directory = and(request.valid, request_alloc_cases)
node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory)
connect directory.io.read.valid, _directory_io_read_valid_T
node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set)
connect directory.io.read.bits.set, _directory_io_read_bits_set_T
node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag)
connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T
node _requests_io_push_valid_T = and(request.valid, queue)
node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0))
node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1)
connect requests.io.push.valid, _requests_io_push_valid_T_2
connect requests.io.push.bits.data.put, request.bits.put
connect requests.io.push.bits.data.offset, request.bits.offset
connect requests.io.push.bits.data.tag, request.bits.tag
connect requests.io.push.bits.data.source, request.bits.source
connect requests.io.push.bits.data.size, request.bits.size
connect requests.io.push.bits.data.param, request.bits.param
connect requests.io.push.bits.data.opcode, request.bits.opcode
connect requests.io.push.bits.data.control, request.bits.control
connect requests.io.push.bits.data.prio[0], request.bits.prio[0]
connect requests.io.push.bits.data.prio[1], request.bits.prio[1]
connect requests.io.push.bits.data.prio[2], request.bits.prio[2]
node _requests_io_push_bits_index_T = shl(lowerMatches1, 0)
node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 11, 8)
node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 7, 0)
node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi)
node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo)
node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 7, 4)
node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 3, 0)
node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1)
node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1)
node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_4, 3, 2)
node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_4, 1, 0)
node _requests_io_push_bits_index_T_5 = orr(requests_io_push_bits_index_hi_2)
node _requests_io_push_bits_index_T_6 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2)
node _requests_io_push_bits_index_T_7 = bits(_requests_io_push_bits_index_T_6, 1, 1)
node _requests_io_push_bits_index_T_8 = cat(_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7)
node _requests_io_push_bits_index_T_9 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8)
node _requests_io_push_bits_index_T_10 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9)
node _requests_io_push_bits_index_T_11 = shl(lowerMatches1, 12)
node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_11, 23, 16)
node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_11, 15, 0)
node _requests_io_push_bits_index_T_12 = orr(requests_io_push_bits_index_hi_3)
node _requests_io_push_bits_index_T_13 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3)
node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_13, 15, 8)
node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_13, 7, 0)
node _requests_io_push_bits_index_T_14 = orr(requests_io_push_bits_index_hi_4)
node _requests_io_push_bits_index_T_15 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4)
node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_15, 7, 4)
node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_15, 3, 0)
node _requests_io_push_bits_index_T_16 = orr(requests_io_push_bits_index_hi_5)
node _requests_io_push_bits_index_T_17 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5)
node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_17, 3, 2)
node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_17, 1, 0)
node _requests_io_push_bits_index_T_18 = orr(requests_io_push_bits_index_hi_6)
node _requests_io_push_bits_index_T_19 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6)
node _requests_io_push_bits_index_T_20 = bits(_requests_io_push_bits_index_T_19, 1, 1)
node _requests_io_push_bits_index_T_21 = cat(_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20)
node _requests_io_push_bits_index_T_22 = cat(_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21)
node _requests_io_push_bits_index_T_23 = cat(_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22)
node _requests_io_push_bits_index_T_24 = cat(_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23)
node _requests_io_push_bits_index_T_25 = shl(lowerMatches1, 24)
node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_25, 35, 32)
node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_25, 31, 0)
node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_7)
node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7)
node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_27, 31, 16)
node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_27, 15, 0)
node _requests_io_push_bits_index_T_28 = orr(requests_io_push_bits_index_hi_8)
node _requests_io_push_bits_index_T_29 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8)
node requests_io_push_bits_index_hi_9 = bits(_requests_io_push_bits_index_T_29, 15, 8)
node requests_io_push_bits_index_lo_9 = bits(_requests_io_push_bits_index_T_29, 7, 0)
node _requests_io_push_bits_index_T_30 = orr(requests_io_push_bits_index_hi_9)
node _requests_io_push_bits_index_T_31 = or(requests_io_push_bits_index_hi_9, requests_io_push_bits_index_lo_9)
node requests_io_push_bits_index_hi_10 = bits(_requests_io_push_bits_index_T_31, 7, 4)
node requests_io_push_bits_index_lo_10 = bits(_requests_io_push_bits_index_T_31, 3, 0)
node _requests_io_push_bits_index_T_32 = orr(requests_io_push_bits_index_hi_10)
node _requests_io_push_bits_index_T_33 = or(requests_io_push_bits_index_hi_10, requests_io_push_bits_index_lo_10)
node requests_io_push_bits_index_hi_11 = bits(_requests_io_push_bits_index_T_33, 3, 2)
node requests_io_push_bits_index_lo_11 = bits(_requests_io_push_bits_index_T_33, 1, 0)
node _requests_io_push_bits_index_T_34 = orr(requests_io_push_bits_index_hi_11)
node _requests_io_push_bits_index_T_35 = or(requests_io_push_bits_index_hi_11, requests_io_push_bits_index_lo_11)
node _requests_io_push_bits_index_T_36 = bits(_requests_io_push_bits_index_T_35, 1, 1)
node _requests_io_push_bits_index_T_37 = cat(_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36)
node _requests_io_push_bits_index_T_38 = cat(_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37)
node _requests_io_push_bits_index_T_39 = cat(_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38)
node _requests_io_push_bits_index_T_40 = cat(_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39)
node _requests_io_push_bits_index_T_41 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40)
node _requests_io_push_bits_index_T_42 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_10, UInt<1>(0h0))
node _requests_io_push_bits_index_T_43 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_24, UInt<1>(0h0))
node _requests_io_push_bits_index_T_44 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_41, UInt<1>(0h0))
node _requests_io_push_bits_index_T_45 = or(_requests_io_push_bits_index_T_42, _requests_io_push_bits_index_T_43)
node _requests_io_push_bits_index_T_46 = or(_requests_io_push_bits_index_T_45, _requests_io_push_bits_index_T_44)
wire _requests_io_push_bits_index_WIRE : UInt<6>
connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_46
connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE
node _mshr_insertOH_T = not(mshr_validOH)
node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1)
node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 11, 0)
node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2)
node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2)
node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 11, 0)
node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5)
node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4)
node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 11, 0)
node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8)
node _mshr_insertOH_T_10 = shl(_mshr_insertOH_T_9, 8)
node _mshr_insertOH_T_11 = bits(_mshr_insertOH_T_10, 11, 0)
node _mshr_insertOH_T_12 = or(_mshr_insertOH_T_9, _mshr_insertOH_T_11)
node _mshr_insertOH_T_13 = bits(_mshr_insertOH_T_12, 11, 0)
node _mshr_insertOH_T_14 = shl(_mshr_insertOH_T_13, 1)
node _mshr_insertOH_T_15 = not(_mshr_insertOH_T_14)
node _mshr_insertOH_T_16 = not(mshr_validOH)
node _mshr_insertOH_T_17 = and(_mshr_insertOH_T_15, _mshr_insertOH_T_16)
node mshr_insertOH = and(_mshr_insertOH_T_17, prioFilter)
node _T_19 = bits(mshr_insertOH, 0, 0)
node _T_20 = bits(mshr_insertOH, 1, 1)
node _T_21 = bits(mshr_insertOH, 2, 2)
node _T_22 = bits(mshr_insertOH, 3, 3)
node _T_23 = bits(mshr_insertOH, 4, 4)
node _T_24 = bits(mshr_insertOH, 5, 5)
node _T_25 = bits(mshr_insertOH, 6, 6)
node _T_26 = bits(mshr_insertOH, 7, 7)
node _T_27 = bits(mshr_insertOH, 8, 8)
node _T_28 = bits(mshr_insertOH, 9, 9)
node _T_29 = bits(mshr_insertOH, 10, 10)
node _T_30 = bits(mshr_insertOH, 11, 11)
node _T_31 = bits(mshr_insertOH, 12, 12)
node _T_32 = and(request.valid, alloc)
node _T_33 = and(_T_32, _T_19)
node _T_34 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_35 = and(_T_33, _T_34)
when _T_35 :
connect mshrs_0.io.allocate.valid, UInt<1>(0h1)
connect mshrs_0.io.allocate.bits.set, request.bits.set
connect mshrs_0.io.allocate.bits.put, request.bits.put
connect mshrs_0.io.allocate.bits.offset, request.bits.offset
connect mshrs_0.io.allocate.bits.tag, request.bits.tag
connect mshrs_0.io.allocate.bits.source, request.bits.source
connect mshrs_0.io.allocate.bits.size, request.bits.size
connect mshrs_0.io.allocate.bits.param, request.bits.param
connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_0.io.allocate.bits.control, request.bits.control
connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_36 = and(request.valid, alloc)
node _T_37 = and(_T_36, _T_20)
node _T_38 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect mshrs_1.io.allocate.valid, UInt<1>(0h1)
connect mshrs_1.io.allocate.bits.set, request.bits.set
connect mshrs_1.io.allocate.bits.put, request.bits.put
connect mshrs_1.io.allocate.bits.offset, request.bits.offset
connect mshrs_1.io.allocate.bits.tag, request.bits.tag
connect mshrs_1.io.allocate.bits.source, request.bits.source
connect mshrs_1.io.allocate.bits.size, request.bits.size
connect mshrs_1.io.allocate.bits.param, request.bits.param
connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_1.io.allocate.bits.control, request.bits.control
connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_40 = and(request.valid, alloc)
node _T_41 = and(_T_40, _T_21)
node _T_42 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
when _T_43 :
connect mshrs_2.io.allocate.valid, UInt<1>(0h1)
connect mshrs_2.io.allocate.bits.set, request.bits.set
connect mshrs_2.io.allocate.bits.put, request.bits.put
connect mshrs_2.io.allocate.bits.offset, request.bits.offset
connect mshrs_2.io.allocate.bits.tag, request.bits.tag
connect mshrs_2.io.allocate.bits.source, request.bits.source
connect mshrs_2.io.allocate.bits.size, request.bits.size
connect mshrs_2.io.allocate.bits.param, request.bits.param
connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_2.io.allocate.bits.control, request.bits.control
connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_44 = and(request.valid, alloc)
node _T_45 = and(_T_44, _T_22)
node _T_46 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
when _T_47 :
connect mshrs_3.io.allocate.valid, UInt<1>(0h1)
connect mshrs_3.io.allocate.bits.set, request.bits.set
connect mshrs_3.io.allocate.bits.put, request.bits.put
connect mshrs_3.io.allocate.bits.offset, request.bits.offset
connect mshrs_3.io.allocate.bits.tag, request.bits.tag
connect mshrs_3.io.allocate.bits.source, request.bits.source
connect mshrs_3.io.allocate.bits.size, request.bits.size
connect mshrs_3.io.allocate.bits.param, request.bits.param
connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_3.io.allocate.bits.control, request.bits.control
connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_48 = and(request.valid, alloc)
node _T_49 = and(_T_48, _T_23)
node _T_50 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect mshrs_4.io.allocate.valid, UInt<1>(0h1)
connect mshrs_4.io.allocate.bits.set, request.bits.set
connect mshrs_4.io.allocate.bits.put, request.bits.put
connect mshrs_4.io.allocate.bits.offset, request.bits.offset
connect mshrs_4.io.allocate.bits.tag, request.bits.tag
connect mshrs_4.io.allocate.bits.source, request.bits.source
connect mshrs_4.io.allocate.bits.size, request.bits.size
connect mshrs_4.io.allocate.bits.param, request.bits.param
connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_4.io.allocate.bits.control, request.bits.control
connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_52 = and(request.valid, alloc)
node _T_53 = and(_T_52, _T_24)
node _T_54 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect mshrs_5.io.allocate.valid, UInt<1>(0h1)
connect mshrs_5.io.allocate.bits.set, request.bits.set
connect mshrs_5.io.allocate.bits.put, request.bits.put
connect mshrs_5.io.allocate.bits.offset, request.bits.offset
connect mshrs_5.io.allocate.bits.tag, request.bits.tag
connect mshrs_5.io.allocate.bits.source, request.bits.source
connect mshrs_5.io.allocate.bits.size, request.bits.size
connect mshrs_5.io.allocate.bits.param, request.bits.param
connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_5.io.allocate.bits.control, request.bits.control
connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_56 = and(request.valid, alloc)
node _T_57 = and(_T_56, _T_25)
node _T_58 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
when _T_59 :
connect mshrs_6.io.allocate.valid, UInt<1>(0h1)
connect mshrs_6.io.allocate.bits.set, request.bits.set
connect mshrs_6.io.allocate.bits.put, request.bits.put
connect mshrs_6.io.allocate.bits.offset, request.bits.offset
connect mshrs_6.io.allocate.bits.tag, request.bits.tag
connect mshrs_6.io.allocate.bits.source, request.bits.source
connect mshrs_6.io.allocate.bits.size, request.bits.size
connect mshrs_6.io.allocate.bits.param, request.bits.param
connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_6.io.allocate.bits.control, request.bits.control
connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_60 = and(request.valid, alloc)
node _T_61 = and(_T_60, _T_26)
node _T_62 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect mshrs_7.io.allocate.valid, UInt<1>(0h1)
connect mshrs_7.io.allocate.bits.set, request.bits.set
connect mshrs_7.io.allocate.bits.put, request.bits.put
connect mshrs_7.io.allocate.bits.offset, request.bits.offset
connect mshrs_7.io.allocate.bits.tag, request.bits.tag
connect mshrs_7.io.allocate.bits.source, request.bits.source
connect mshrs_7.io.allocate.bits.size, request.bits.size
connect mshrs_7.io.allocate.bits.param, request.bits.param
connect mshrs_7.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_7.io.allocate.bits.control, request.bits.control
connect mshrs_7.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_7.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_64 = and(request.valid, alloc)
node _T_65 = and(_T_64, _T_27)
node _T_66 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_67 = and(_T_65, _T_66)
when _T_67 :
connect mshrs_8.io.allocate.valid, UInt<1>(0h1)
connect mshrs_8.io.allocate.bits.set, request.bits.set
connect mshrs_8.io.allocate.bits.put, request.bits.put
connect mshrs_8.io.allocate.bits.offset, request.bits.offset
connect mshrs_8.io.allocate.bits.tag, request.bits.tag
connect mshrs_8.io.allocate.bits.source, request.bits.source
connect mshrs_8.io.allocate.bits.size, request.bits.size
connect mshrs_8.io.allocate.bits.param, request.bits.param
connect mshrs_8.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_8.io.allocate.bits.control, request.bits.control
connect mshrs_8.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_8.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_68 = and(request.valid, alloc)
node _T_69 = and(_T_68, _T_28)
node _T_70 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_71 = and(_T_69, _T_70)
when _T_71 :
connect mshrs_9.io.allocate.valid, UInt<1>(0h1)
connect mshrs_9.io.allocate.bits.set, request.bits.set
connect mshrs_9.io.allocate.bits.put, request.bits.put
connect mshrs_9.io.allocate.bits.offset, request.bits.offset
connect mshrs_9.io.allocate.bits.tag, request.bits.tag
connect mshrs_9.io.allocate.bits.source, request.bits.source
connect mshrs_9.io.allocate.bits.size, request.bits.size
connect mshrs_9.io.allocate.bits.param, request.bits.param
connect mshrs_9.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_9.io.allocate.bits.control, request.bits.control
connect mshrs_9.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_9.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_72 = and(request.valid, alloc)
node _T_73 = and(_T_72, _T_29)
node _T_74 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_75 = and(_T_73, _T_74)
when _T_75 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_76 = and(request.valid, alloc)
node _T_77 = and(_T_76, _T_30)
node _T_78 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_79 = and(_T_77, _T_78)
when _T_79 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_80 = and(request.valid, nestB)
node _T_81 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_84 = and(_T_82, _T_83)
node _T_85 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_86 = and(_T_84, _T_85)
when _T_86 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_87 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf
assert(clock, _T_87, UInt<1>(0h1), "") : assert
connect mshrs_10.io.allocate.bits.prio[0], UInt<1>(0h0)
node _T_91 = and(request.valid, nestC)
node _T_92 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
when _T_95 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_96 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1
assert(clock, _T_96, UInt<1>(0h1), "") : assert_1
node _T_100 = eq(request.bits.prio[1], UInt<1>(0h0))
node _T_101 = asUInt(reset)
node _T_102 = eq(_T_101, UInt<1>(0h0))
when _T_102 :
node _T_103 = eq(_T_100, UInt<1>(0h0))
when _T_103 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2
assert(clock, _T_100, UInt<1>(0h1), "") : assert_2
connect mshrs_11.io.allocate.bits.prio[0], UInt<1>(0h0)
connect mshrs_11.io.allocate.bits.prio[1], UInt<1>(0h0)
node _dirTarget_T = mux(nestB, UInt<11>(0h400), UInt<12>(0h800))
node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T)
node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0))
node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T)
reg directoryFanout : UInt, clock
connect directoryFanout, _directoryFanout_T_1
node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0)
connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T
connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1)
connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T
connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2)
connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T
connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3)
connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T
connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4)
connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T
connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5)
connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T
connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6)
connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T
connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_7_io_directory_valid_T = bits(directoryFanout, 7, 7)
connect mshrs_7.io.directory.valid, _mshrs_7_io_directory_valid_T
connect mshrs_7.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_7.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_7.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_7.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_7.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_7.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_8_io_directory_valid_T = bits(directoryFanout, 8, 8)
connect mshrs_8.io.directory.valid, _mshrs_8_io_directory_valid_T
connect mshrs_8.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_8.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_8.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_8.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_8.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_8.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_9_io_directory_valid_T = bits(directoryFanout, 9, 9)
connect mshrs_9.io.directory.valid, _mshrs_9_io_directory_valid_T
connect mshrs_9.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_9.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_9.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_9.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_9.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_9.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_10_io_directory_valid_T = bits(directoryFanout, 10, 10)
connect mshrs_10.io.directory.valid, _mshrs_10_io_directory_valid_T
connect mshrs_10.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_10.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_10.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_10.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_10.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_10.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_11_io_directory_valid_T = bits(directoryFanout, 11, 11)
connect mshrs_11.io.directory.valid, _mshrs_11_io_directory_valid_T
connect mshrs_11.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_11.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_11.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_11.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_11.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_11.io.directory.bits.dirty, directory.io.result.bits.dirty
node _sinkC_io_way_T = eq(mshrs_10.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_1 = and(mshrs_10.io.status.valid, _sinkC_io_way_T)
node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2)
node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4)
node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6)
node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8)
node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10)
node _sinkC_io_way_T_12 = eq(mshrs_5.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_13 = and(mshrs_5.io.status.valid, _sinkC_io_way_T_12)
node _sinkC_io_way_T_14 = eq(mshrs_6.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_15 = and(mshrs_6.io.status.valid, _sinkC_io_way_T_14)
node _sinkC_io_way_T_16 = eq(mshrs_7.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_17 = and(mshrs_7.io.status.valid, _sinkC_io_way_T_16)
node _sinkC_io_way_T_18 = eq(mshrs_8.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_19 = and(mshrs_8.io.status.valid, _sinkC_io_way_T_18)
node _sinkC_io_way_T_20 = eq(mshrs_9.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_21 = and(mshrs_9.io.status.valid, _sinkC_io_way_T_20)
node _sinkC_io_way_T_22 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_23 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_24 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_25 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_26 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_27 = mux(_sinkC_io_way_T_13, mshrs_5.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_28 = mux(_sinkC_io_way_T_15, mshrs_6.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_29 = mux(_sinkC_io_way_T_17, mshrs_7.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_30 = mux(_sinkC_io_way_T_19, mshrs_8.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_31 = mux(_sinkC_io_way_T_21, mshrs_9.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_32 = or(_sinkC_io_way_T_22, _sinkC_io_way_T_23)
node _sinkC_io_way_T_33 = or(_sinkC_io_way_T_32, _sinkC_io_way_T_24)
node _sinkC_io_way_T_34 = or(_sinkC_io_way_T_33, _sinkC_io_way_T_25)
node _sinkC_io_way_T_35 = or(_sinkC_io_way_T_34, _sinkC_io_way_T_26)
node _sinkC_io_way_T_36 = or(_sinkC_io_way_T_35, _sinkC_io_way_T_27)
node _sinkC_io_way_T_37 = or(_sinkC_io_way_T_36, _sinkC_io_way_T_28)
node _sinkC_io_way_T_38 = or(_sinkC_io_way_T_37, _sinkC_io_way_T_29)
node _sinkC_io_way_T_39 = or(_sinkC_io_way_T_38, _sinkC_io_way_T_30)
node _sinkC_io_way_T_40 = or(_sinkC_io_way_T_39, _sinkC_io_way_T_31)
wire _sinkC_io_way_WIRE : UInt<4>
connect _sinkC_io_way_WIRE, _sinkC_io_way_T_40
node _sinkC_io_way_T_41 = mux(_sinkC_io_way_T_1, mshrs_10.io.status.bits.way, _sinkC_io_way_WIRE)
connect sinkC.io.way, _sinkC_io_way_T_41
wire _sinkD_io_way_WIRE : UInt<4>[12]
connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way
connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way
connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way
connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way
connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way
connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way
connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way
connect _sinkD_io_way_WIRE[7], mshrs_7.io.status.bits.way
connect _sinkD_io_way_WIRE[8], mshrs_8.io.status.bits.way
connect _sinkD_io_way_WIRE[9], mshrs_9.io.status.bits.way
connect _sinkD_io_way_WIRE[10], mshrs_10.io.status.bits.way
connect _sinkD_io_way_WIRE[11], mshrs_11.io.status.bits.way
connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source]
wire _sinkD_io_set_WIRE : UInt<11>[12]
connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set
connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set
connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set
connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set
connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set
connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set
connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set
connect _sinkD_io_set_WIRE[7], mshrs_7.io.status.bits.set
connect _sinkD_io_set_WIRE[8], mshrs_8.io.status.bits.set
connect _sinkD_io_set_WIRE[9], mshrs_9.io.status.bits.set
connect _sinkD_io_set_WIRE[10], mshrs_10.io.status.bits.set
connect _sinkD_io_set_WIRE[11], mshrs_11.io.status.bits.set
connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source]
connect sinkA.io.pb_pop, sourceD.io.pb_pop
connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt
connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask
connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data
connect sinkC.io.rel_pop, sourceD.io.rel_pop
connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt
connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data
connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr
connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data
connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr
connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data
connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr
connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr
connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr
connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data
connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data
connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data
connect sourceD.io.evict_req.way, sourceC.io.evict_req.way
connect sourceD.io.evict_req.set, sourceC.io.evict_req.set
connect sourceD.io.grant_req.way, sinkD.io.grant_req.way
connect sourceD.io.grant_req.set, sinkD.io.grant_req.set
connect sourceC.io.evict_safe, sourceD.io.evict_safe
connect sinkD.io.grant_safe, sourceD.io.grant_safe | module InclusiveCacheBankScheduler_3( // @[Scheduler.scala:27:7]
input clock, // @[Scheduler.scala:27:7]
input reset, // @[Scheduler.scala:27:7]
output io_in_a_ready, // @[Scheduler.scala:29:14]
input io_in_a_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14]
input [15:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14]
input [127:0] io_in_a_bits_data, // @[Scheduler.scala:29:14]
input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_b_ready, // @[Scheduler.scala:29:14]
output io_in_b_valid, // @[Scheduler.scala:29:14]
output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14]
output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14]
output io_in_c_ready, // @[Scheduler.scala:29:14]
input io_in_c_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14]
input [127:0] io_in_c_bits_data, // @[Scheduler.scala:29:14]
input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_d_ready, // @[Scheduler.scala:29:14]
output io_in_d_valid, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14]
output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14]
output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14]
output [3:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14]
output io_in_d_bits_denied, // @[Scheduler.scala:29:14]
output [127:0] io_in_d_bits_data, // @[Scheduler.scala:29:14]
output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_e_valid, // @[Scheduler.scala:29:14]
input [3:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14]
input io_out_a_ready, // @[Scheduler.scala:29:14]
output io_out_a_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_a_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14]
output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14]
output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14]
output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_out_c_ready, // @[Scheduler.scala:29:14]
output io_out_c_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_c_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14]
output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14]
output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_d_ready, // @[Scheduler.scala:29:14]
input io_out_d_valid, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14]
input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14]
input [3:0] io_out_d_bits_source, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14]
input io_out_d_bits_denied, // @[Scheduler.scala:29:14]
input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14]
input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_e_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14]
output io_req_ready, // @[Scheduler.scala:29:14]
input io_req_valid, // @[Scheduler.scala:29:14]
input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14]
output io_resp_valid // @[Scheduler.scala:29:14]
);
wire [8:0] mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73]
wire [8:0] mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74]
wire [8:0] mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [5:0] request_bits_put; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21]
wire [8:0] request_bits_tag; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_source; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_size; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_param; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21]
wire request_bits_control; // @[Scheduler.scala:163:21]
wire request_bits_prio_2; // @[Scheduler.scala:163:21]
wire request_bits_prio_0; // @[Scheduler.scala:163:21]
wire _mshrs_11_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _requests_io_push_ready; // @[Scheduler.scala:70:24]
wire [35:0] _requests_io_valid; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24]
wire _requests_io_data_control; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24]
wire [8:0] _requests_io_data_tag; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24]
wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27]
wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27]
wire [127:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27]
wire _directory_io_write_ready; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25]
wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25]
wire [8:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25]
wire [3:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25]
wire _directory_io_ready; // @[Scheduler.scala:68:25]
wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21]
wire [8:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21]
wire [10:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21]
wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21]
wire [3:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21]
wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_source; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21]
wire [10:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21]
wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21]
wire [10:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21]
wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21]
wire [3:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21]
wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21]
wire [8:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21]
wire [10:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21]
wire [127:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21]
wire [15:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21]
wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23]
wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23]
wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23]
wire [3:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23]
wire [10:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23]
wire [3:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23]
wire [10:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23]
wire [127:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23]
wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23]
wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23]
wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23]
wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23]
wire [3:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23]
wire [10:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23]
wire [10:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23]
wire [3:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23]
wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23]
wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23]
wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7]
wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7]
wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7]
wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7]
wire [3:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7]
wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7]
wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7]
wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7]
wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_196 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_197 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_198 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_199 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_200 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_201 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_202 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_203 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_204 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_205 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_206 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_207 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_208 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_209 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_210 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_211 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_212 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_213 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_214 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_215 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_216 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_217 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_218 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_574 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_575 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_598 = 1'h0; // @[Mux.scala:30:73]
wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21]
wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22]
wire blockB = 1'h0; // @[Scheduler.scala:175:70]
wire nestB = 1'h0; // @[Scheduler.scala:179:70]
wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_7_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_8_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_9_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_10_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_11_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13]
wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56]
wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7]
wire [5:0] io_in_b_bits_source = 6'h28; // @[Scheduler.scala:27:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Scheduler.scala:27:7]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Scheduler.scala:27:7]
wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7]
wire _mshr_request_T_253 = 1'h1; // @[Scheduler.scala:107:28]
wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22]
wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35]
wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55]
wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7]
wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_b_bits_source = 4'h0; // @[Scheduler.scala:27:7]
wire [3:0] _schedule_WIRE_19_bits_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_334 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_335 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_336 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_337 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_338 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_339 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_340 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_341 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_342 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_343 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_344 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_345 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_346 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_347 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_348 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_349 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_350 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_351 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_352 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_353 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_354 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_355 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_356 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_23 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_748 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_749 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_750 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_751 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_752 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_753 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_754 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_755 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_756 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_757 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_758 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_759 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_760 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_761 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_762 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_763 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_764 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_765 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_766 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_767 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_768 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_769 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_770 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_44 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_55_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_56_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_978 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_979 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_980 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_981 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_982 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_983 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_984 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_985 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_986 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_987 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_988 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_989 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_990 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_991 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_992 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_993 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_994 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_995 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_996 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_997 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_998 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_999 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_1000 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_58 = 4'h0; // @[Mux.scala:30:73]
wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_0 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_1 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_2 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_3 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_4 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_5 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_6 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_7 = 16'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7]
wire [11:0] _lowerMatches1_T_1 = 12'h800; // @[Scheduler.scala:200:43]
wire [11:0] _dirTarget_T = 12'h800; // @[Scheduler.scala:306:48]
wire [4:0] _requests_io_push_bits_index_T_43 = 5'h0; // @[Mux.scala:30:73]
wire [9:0] _prioFilter_T_1 = 10'h3FF; // @[Scheduler.scala:182:69]
wire [10:0] _lowerMatches1_T_3 = 11'h400; // @[Scheduler.scala:201:43]
wire io_in_a_ready_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7]
wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7]
wire io_in_b_valid_0; // @[Scheduler.scala:27:7]
wire io_in_c_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7]
wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7]
wire [3:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7]
wire [127:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_in_d_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_a_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_c_valid_0; // @[Scheduler.scala:27:7]
wire io_out_d_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_out_e_valid_0; // @[Scheduler.scala:27:7]
wire io_req_ready_0; // @[Scheduler.scala:27:7]
wire io_resp_valid_0; // @[Scheduler.scala:27:7]
wire [10:0] _nestedwb_set_T; // @[Scheduler.scala:155:24]
wire [8:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24]
wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75]
wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75]
wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37]
wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75]
wire [10:0] nestedwb_set; // @[Scheduler.scala:75:22]
wire [8:0] nestedwb_tag; // @[Scheduler.scala:75:22]
wire nestedwb_b_toN; // @[Scheduler.scala:75:22]
wire nestedwb_b_toB; // @[Scheduler.scala:75:22]
wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22]
wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22]
wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h0; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h0; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h1; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h1; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h2; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h2; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h3; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h3; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h4; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h4; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h5; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h5; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h6; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h6; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_7_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_7_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_7_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_7_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_7_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h7; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_7_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_7_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_7_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h7; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_7_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_7_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_8_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_8_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_8_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_8_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_8_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h8; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_8_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_8_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_8_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h8; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_8_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_8_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_9_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_9_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_9_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_9_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_9_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h9; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_9_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_9_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_9_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h9; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_9_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_9_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_10_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_10_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_10_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_10_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hA; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_10_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_10_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_10_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hA; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_10_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_10_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_11_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_11_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_11_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_11_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hB; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_11_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_11_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_11_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hB; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_11_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_11_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_1 = _mshrs_10_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_3 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_5 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_7 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_9 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_11 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_13 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_15 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_17 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_19 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_20 = _mshrs_5_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_21 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_20; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_22 = _mshrs_5_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_23 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_22; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_5 = _mshr_stall_abc_T_21 | _mshr_stall_abc_T_23; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_24 = _mshrs_6_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_25 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_24; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_26 = _mshrs_6_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_27 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_26; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_6 = _mshr_stall_abc_T_25 | _mshr_stall_abc_T_27; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_28 = _mshrs_7_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_29 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_28; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_30 = _mshrs_7_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_31 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_30; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_7 = _mshr_stall_abc_T_29 | _mshr_stall_abc_T_31; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_32 = _mshrs_8_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_33 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_32; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_34 = _mshrs_8_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_35 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_34; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_8 = _mshr_stall_abc_T_33 | _mshr_stall_abc_T_35; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_36 = _mshrs_9_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_37 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_36; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_38 = _mshrs_9_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_39 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_38; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_9 = _mshr_stall_abc_T_37 | _mshr_stall_abc_T_39; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_bc_T = _mshrs_10_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58]
wire mshr_stall_bc = _mshrs_11_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}]
wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_5 = mshr_stall_abc_5 & _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_6 = mshr_stall_abc_6 & _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_7 = mshr_stall_abc_7 & _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_8 = mshr_stall_abc_8 & _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_9 = mshr_stall_abc_9 & _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_115 = ~mshr_stall_abc_5; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_138 = ~mshr_stall_abc_6; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_139 = _mshrs_6_io_schedule_valid & _mshr_request_T_138; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_161 = ~mshr_stall_abc_7; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_162 = _mshrs_7_io_schedule_valid & _mshr_request_T_161; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_163 = ~_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_164 = _sourceA_io_req_ready | _mshr_request_T_163; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_165 = _mshr_request_T_162 & _mshr_request_T_164; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_166 = ~_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_167 = _sourceB_io_req_ready | _mshr_request_T_166; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_169 = ~_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_170 = _sourceC_io_req_ready | _mshr_request_T_169; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_172 = ~_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_173 = _sourceD_io_req_ready | _mshr_request_T_172; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_175 = ~_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_176 = _sourceE_io_req_ready | _mshr_request_T_175; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_178 = ~_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_179 = _sourceX_io_req_ready | _mshr_request_T_178; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_180 = _mshr_request_T_177 & _mshr_request_T_179; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_181 = ~_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_182 = _directory_io_write_ready | _mshr_request_T_181; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_183 = _mshr_request_T_180 & _mshr_request_T_182; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_184 = ~mshr_stall_abc_8; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_185 = _mshrs_8_io_schedule_valid & _mshr_request_T_184; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_186 = ~_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_187 = _sourceA_io_req_ready | _mshr_request_T_186; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_188 = _mshr_request_T_185 & _mshr_request_T_187; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_189 = ~_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_190 = _sourceB_io_req_ready | _mshr_request_T_189; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_192 = ~_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_193 = _sourceC_io_req_ready | _mshr_request_T_192; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_195 = ~_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_196 = _sourceD_io_req_ready | _mshr_request_T_195; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_198 = ~_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_199 = _sourceE_io_req_ready | _mshr_request_T_198; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_201 = ~_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_202 = _sourceX_io_req_ready | _mshr_request_T_201; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_203 = _mshr_request_T_200 & _mshr_request_T_202; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_204 = ~_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_205 = _directory_io_write_ready | _mshr_request_T_204; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_206 = _mshr_request_T_203 & _mshr_request_T_205; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_207 = ~mshr_stall_abc_9; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_208 = _mshrs_9_io_schedule_valid & _mshr_request_T_207; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_209 = ~_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_210 = _sourceA_io_req_ready | _mshr_request_T_209; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_211 = _mshr_request_T_208 & _mshr_request_T_210; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_212 = ~_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_213 = _sourceB_io_req_ready | _mshr_request_T_212; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_215 = ~_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_216 = _sourceC_io_req_ready | _mshr_request_T_215; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_218 = ~_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_219 = _sourceD_io_req_ready | _mshr_request_T_218; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_221 = ~_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_222 = _sourceE_io_req_ready | _mshr_request_T_221; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_224 = ~_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_225 = _sourceX_io_req_ready | _mshr_request_T_224; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_226 = _mshr_request_T_223 & _mshr_request_T_225; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_227 = ~_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_228 = _directory_io_write_ready | _mshr_request_T_227; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_229 = _mshr_request_T_226 & _mshr_request_T_228; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_230 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28]
wire _mshr_request_T_231 = _mshrs_10_io_schedule_valid & _mshr_request_T_230; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_232 = ~_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_233 = _sourceA_io_req_ready | _mshr_request_T_232; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_234 = _mshr_request_T_231 & _mshr_request_T_233; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_235 = ~_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_236 = _sourceB_io_req_ready | _mshr_request_T_235; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_238 = ~_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_239 = _sourceC_io_req_ready | _mshr_request_T_238; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_241 = ~_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_242 = _sourceD_io_req_ready | _mshr_request_T_241; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_244 = ~_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_245 = _sourceE_io_req_ready | _mshr_request_T_244; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_247 = ~_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_248 = _sourceX_io_req_ready | _mshr_request_T_247; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_249 = _mshr_request_T_246 & _mshr_request_T_248; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_250 = ~_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_251 = _directory_io_write_ready | _mshr_request_T_250; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_252 = _mshr_request_T_249 & _mshr_request_T_251; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_255 = ~_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_256 = _sourceA_io_req_ready | _mshr_request_T_255; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_254; // @[Scheduler.scala:107:25]
wire _mshr_request_T_257 = _mshr_request_T_254 & _mshr_request_T_256; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_258 = ~_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_259 = _sourceB_io_req_ready | _mshr_request_T_258; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_261 = ~_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_262 = _sourceC_io_req_ready | _mshr_request_T_261; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_264 = ~_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_265 = _sourceD_io_req_ready | _mshr_request_T_264; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_267 = ~_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_268 = _sourceE_io_req_ready | _mshr_request_T_267; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_270 = ~_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_271 = _sourceX_io_req_ready | _mshr_request_T_270; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_272 = _mshr_request_T_269 & _mshr_request_T_271; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_273 = ~_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_274 = _directory_io_write_ready | _mshr_request_T_273; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_275 = _mshr_request_T_272 & _mshr_request_T_274; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire [1:0] mshr_request_lo_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_lo = {mshr_request_lo_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_lo_hi_hi = {_mshr_request_T_137, _mshr_request_T_114}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_hi = {mshr_request_lo_hi_hi, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_lo = {mshr_request_lo_hi, mshr_request_lo_lo}; // @[Scheduler.scala:106:25]
wire [1:0] mshr_request_hi_lo_hi = {_mshr_request_T_206, _mshr_request_T_183}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_lo = {mshr_request_hi_lo_hi, _mshr_request_T_160}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_hi_hi_hi = {_mshr_request_T_275, _mshr_request_T_252}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_hi = {mshr_request_hi_hi_hi, _mshr_request_T_229}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25]
wire [11:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25]
reg [11:0] robin_filter; // @[Scheduler.scala:118:29]
wire [11:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54]
wire [23:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}]
wire [24:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48]
wire [23:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}]
wire [25:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}]
wire [27:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}]
wire [31:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}]
wire [39:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_13 = _mshr_selectOH2_T_12[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 | _mshr_selectOH2_T_13; // @[package.scala:253:{43,53}]
wire [23:0] _mshr_selectOH2_T_15 = _mshr_selectOH2_T_14; // @[package.scala:253:43, :254:17]
wire [24:0] _mshr_selectOH2_T_16 = {_mshr_selectOH2_T_15, 1'h0}; // @[package.scala:254:17]
wire [24:0] _mshr_selectOH2_T_17 = ~_mshr_selectOH2_T_16; // @[Scheduler.scala:120:{24,48}]
wire [24:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_17[23:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}]
wire [11:0] _mshr_selectOH_T = mshr_selectOH2[23:12]; // @[Scheduler.scala:120:54, :121:37]
wire [11:0] _mshr_selectOH_T_1 = mshr_selectOH2[11:0]; // @[Scheduler.scala:120:54, :121:86]
wire [11:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}]
wire [3:0] mshr_select_hi = mshr_selectOH[11:8]; // @[OneHot.scala:30:18]
wire [7:0] mshr_select_lo = mshr_selectOH[7:0]; // @[OneHot.scala:31:18]
wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _mshr_select_T_1 = {4'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] mshr_select_hi_1 = _mshr_select_T_1[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] mshr_select_lo_1 = _mshr_select_T_1[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] mshr_select_hi_2 = _mshr_select_T_3[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] mshr_select_lo_2 = _mshr_select_T_3[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_4 = |mshr_select_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _mshr_select_T_5 = mshr_select_hi_2 | mshr_select_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _mshr_select_T_6 = _mshr_select_T_5[1]; // @[OneHot.scala:32:28]
wire [1:0] _mshr_select_T_7 = {_mshr_select_T_4, _mshr_select_T_6}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _mshr_select_T_8 = {_mshr_select_T_2, _mshr_select_T_7}; // @[OneHot.scala:32:{10,14}]
wire [3:0] mshr_select = {_mshr_select_T, _mshr_select_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10]
wire [3:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10]
wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _schedule_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleTag_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleSet_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire sel_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _schedule_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleTag_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleSet_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire sel_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _schedule_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleTag_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleSet_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire sel_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _schedule_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleTag_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleSet_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire select_bc = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire sel_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _schedule_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleTag_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleSet_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire select_c = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire sel_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [3:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32]
wire [8:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE; // @[Mux.scala:30:73]
wire [8:0] schedule_a_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_a_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73]
wire schedule_a_bits_block; // @[Mux.scala:30:73]
wire schedule_a_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73]
wire [8:0] schedule_b_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_b_bits_set; // @[Mux.scala:30:73]
wire schedule_b_bits_clients; // @[Mux.scala:30:73]
wire schedule_b_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_source; // @[Mux.scala:30:73]
wire [8:0] schedule_c_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_c_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_way; // @[Mux.scala:30:73]
wire schedule_c_bits_dirty; // @[Mux.scala:30:73]
wire schedule_c_valid; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_0; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_1; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_2; // @[Mux.scala:30:73]
wire schedule_d_bits_control; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73]
wire [8:0] schedule_d_bits_tag; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73]
wire [10:0] schedule_d_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_d_bits_way; // @[Mux.scala:30:73]
wire schedule_d_bits_bad; // @[Mux.scala:30:73]
wire schedule_d_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73]
wire schedule_e_valid; // @[Mux.scala:30:73]
wire schedule_x_valid; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_dir_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_dir_bits_way; // @[Mux.scala:30:73]
wire schedule_dir_valid; // @[Mux.scala:30:73]
wire schedule_reload; // @[Mux.scala:30:73]
wire _schedule_T_12 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_13 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_14 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_15 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_16 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_17 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_18 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_19 = _schedule_T_7 & _mshrs_7_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_20 = _schedule_T_8 & _mshrs_8_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_21 = _schedule_T_9 & _mshrs_9_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_22 = _schedule_T_10 & _mshrs_10_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_23 = _schedule_T_11 & _mshrs_11_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_24 = _schedule_T_12 | _schedule_T_13; // @[Mux.scala:30:73]
wire _schedule_T_25 = _schedule_T_24 | _schedule_T_14; // @[Mux.scala:30:73]
wire _schedule_T_26 = _schedule_T_25 | _schedule_T_15; // @[Mux.scala:30:73]
wire _schedule_T_27 = _schedule_T_26 | _schedule_T_16; // @[Mux.scala:30:73]
wire _schedule_T_28 = _schedule_T_27 | _schedule_T_17; // @[Mux.scala:30:73]
wire _schedule_T_29 = _schedule_T_28 | _schedule_T_18; // @[Mux.scala:30:73]
wire _schedule_T_30 = _schedule_T_29 | _schedule_T_19; // @[Mux.scala:30:73]
wire _schedule_T_31 = _schedule_T_30 | _schedule_T_20; // @[Mux.scala:30:73]
wire _schedule_T_32 = _schedule_T_31 | _schedule_T_21; // @[Mux.scala:30:73]
wire _schedule_T_33 = _schedule_T_32 | _schedule_T_22; // @[Mux.scala:30:73]
wire _schedule_T_34 = _schedule_T_33 | _schedule_T_23; // @[Mux.scala:30:73]
assign _schedule_WIRE = _schedule_T_34; // @[Mux.scala:30:73]
assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73]
wire _schedule_WIRE_10; // @[Mux.scala:30:73]
assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73]
assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73]
assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_9; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_8; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE_7; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_5; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_4; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_35 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_36 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_37 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_38 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_39 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_40 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_41 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_42 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_43 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_44 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_45 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_46 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_47 = _schedule_T_35 | _schedule_T_36; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_48 = _schedule_T_47 | _schedule_T_37; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_49 = _schedule_T_48 | _schedule_T_38; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_50 = _schedule_T_49 | _schedule_T_39; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_51 = _schedule_T_50 | _schedule_T_40; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_52 = _schedule_T_51 | _schedule_T_41; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_53 = _schedule_T_52 | _schedule_T_42; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_43; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_44; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_45; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_4 = _schedule_T_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73]
wire _schedule_T_58 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_59 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_60 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_61 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_62 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_63 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_64 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_65 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_66 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_67 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_68 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_69 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_70 = _schedule_T_58 | _schedule_T_59; // @[Mux.scala:30:73]
wire _schedule_T_71 = _schedule_T_70 | _schedule_T_60; // @[Mux.scala:30:73]
wire _schedule_T_72 = _schedule_T_71 | _schedule_T_61; // @[Mux.scala:30:73]
wire _schedule_T_73 = _schedule_T_72 | _schedule_T_62; // @[Mux.scala:30:73]
wire _schedule_T_74 = _schedule_T_73 | _schedule_T_63; // @[Mux.scala:30:73]
wire _schedule_T_75 = _schedule_T_74 | _schedule_T_64; // @[Mux.scala:30:73]
wire _schedule_T_76 = _schedule_T_75 | _schedule_T_65; // @[Mux.scala:30:73]
wire _schedule_T_77 = _schedule_T_76 | _schedule_T_66; // @[Mux.scala:30:73]
wire _schedule_T_78 = _schedule_T_77 | _schedule_T_67; // @[Mux.scala:30:73]
wire _schedule_T_79 = _schedule_T_78 | _schedule_T_68; // @[Mux.scala:30:73]
wire _schedule_T_80 = _schedule_T_79 | _schedule_T_69; // @[Mux.scala:30:73]
assign _schedule_WIRE_5 = _schedule_T_80; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_81 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_82 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_83 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_84 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_85 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_86 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_87 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_88 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_89 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_90 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_91 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_92 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_93 = _schedule_T_81 | _schedule_T_82; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_83; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_84; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_85; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_86; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_98 = _schedule_T_97 | _schedule_T_87; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_99 = _schedule_T_98 | _schedule_T_88; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_100 = _schedule_T_99 | _schedule_T_89; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_101 = _schedule_T_100 | _schedule_T_90; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_102 = _schedule_T_101 | _schedule_T_91; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_103 = _schedule_T_102 | _schedule_T_92; // @[Mux.scala:30:73]
assign _schedule_WIRE_6 = _schedule_T_103; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73]
wire _schedule_T_104 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_105 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_106 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_107 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_108 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_109 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_110 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_111 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_112 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_113 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_114 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_115 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_116 = _schedule_T_104 | _schedule_T_105; // @[Mux.scala:30:73]
wire _schedule_T_117 = _schedule_T_116 | _schedule_T_106; // @[Mux.scala:30:73]
wire _schedule_T_118 = _schedule_T_117 | _schedule_T_107; // @[Mux.scala:30:73]
wire _schedule_T_119 = _schedule_T_118 | _schedule_T_108; // @[Mux.scala:30:73]
wire _schedule_T_120 = _schedule_T_119 | _schedule_T_109; // @[Mux.scala:30:73]
wire _schedule_T_121 = _schedule_T_120 | _schedule_T_110; // @[Mux.scala:30:73]
wire _schedule_T_122 = _schedule_T_121 | _schedule_T_111; // @[Mux.scala:30:73]
wire _schedule_T_123 = _schedule_T_122 | _schedule_T_112; // @[Mux.scala:30:73]
wire _schedule_T_124 = _schedule_T_123 | _schedule_T_113; // @[Mux.scala:30:73]
wire _schedule_T_125 = _schedule_T_124 | _schedule_T_114; // @[Mux.scala:30:73]
wire _schedule_T_126 = _schedule_T_125 | _schedule_T_115; // @[Mux.scala:30:73]
assign _schedule_WIRE_7 = _schedule_T_126; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_127 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_128 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_129 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_130 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_131 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_132 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_133 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_134 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_135 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_136 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_137 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_138 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_139 = _schedule_T_127 | _schedule_T_128; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_140 = _schedule_T_139 | _schedule_T_129; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_141 = _schedule_T_140 | _schedule_T_130; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_142 = _schedule_T_141 | _schedule_T_131; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_143 = _schedule_T_142 | _schedule_T_132; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_144 = _schedule_T_143 | _schedule_T_133; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_134; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_135; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_136; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_137; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_138; // @[Mux.scala:30:73]
assign _schedule_WIRE_8 = _schedule_T_149; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_150 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_151 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_152 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_153 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_154 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_155 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_156 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_157 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_158 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_159 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_160 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_161 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_162 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_163 = _schedule_T_162 | _schedule_T_152; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_164 = _schedule_T_163 | _schedule_T_153; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_165 = _schedule_T_164 | _schedule_T_154; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_166 = _schedule_T_165 | _schedule_T_155; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_167 = _schedule_T_166 | _schedule_T_156; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_168 = _schedule_T_167 | _schedule_T_157; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_169 = _schedule_T_168 | _schedule_T_158; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_170 = _schedule_T_169 | _schedule_T_159; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_171 = _schedule_T_170 | _schedule_T_160; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_172 = _schedule_T_171 | _schedule_T_161; // @[Mux.scala:30:73]
assign _schedule_WIRE_9 = _schedule_T_172; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73]
wire _schedule_T_173 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_174 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_175 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_176 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_177 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_178 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_179 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_180 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_181 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_182 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_183 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_184 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_185 = _schedule_T_173 | _schedule_T_174; // @[Mux.scala:30:73]
wire _schedule_T_186 = _schedule_T_185 | _schedule_T_175; // @[Mux.scala:30:73]
wire _schedule_T_187 = _schedule_T_186 | _schedule_T_176; // @[Mux.scala:30:73]
wire _schedule_T_188 = _schedule_T_187 | _schedule_T_177; // @[Mux.scala:30:73]
wire _schedule_T_189 = _schedule_T_188 | _schedule_T_178; // @[Mux.scala:30:73]
wire _schedule_T_190 = _schedule_T_189 | _schedule_T_179; // @[Mux.scala:30:73]
wire _schedule_T_191 = _schedule_T_190 | _schedule_T_180; // @[Mux.scala:30:73]
wire _schedule_T_192 = _schedule_T_191 | _schedule_T_181; // @[Mux.scala:30:73]
wire _schedule_T_193 = _schedule_T_192 | _schedule_T_182; // @[Mux.scala:30:73]
wire _schedule_T_194 = _schedule_T_193 | _schedule_T_183; // @[Mux.scala:30:73]
wire _schedule_T_195 = _schedule_T_194 | _schedule_T_184; // @[Mux.scala:30:73]
assign _schedule_WIRE_10 = _schedule_T_195; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73]
wire _schedule_WIRE_14; // @[Mux.scala:30:73]
assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_T_219 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_220 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_221 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_222 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_223 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_224 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_225 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_226 = _schedule_T_7 & _mshrs_7_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_227 = _schedule_T_8 & _mshrs_8_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_228 = _schedule_T_9 & _mshrs_9_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_229 = _schedule_T_10 & _mshrs_10_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_230 = _schedule_T_11 & _mshrs_11_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_231 = _schedule_T_219 | _schedule_T_220; // @[Mux.scala:30:73]
wire _schedule_T_232 = _schedule_T_231 | _schedule_T_221; // @[Mux.scala:30:73]
wire _schedule_T_233 = _schedule_T_232 | _schedule_T_222; // @[Mux.scala:30:73]
wire _schedule_T_234 = _schedule_T_233 | _schedule_T_223; // @[Mux.scala:30:73]
wire _schedule_T_235 = _schedule_T_234 | _schedule_T_224; // @[Mux.scala:30:73]
wire _schedule_T_236 = _schedule_T_235 | _schedule_T_225; // @[Mux.scala:30:73]
wire _schedule_T_237 = _schedule_T_236 | _schedule_T_226; // @[Mux.scala:30:73]
wire _schedule_T_238 = _schedule_T_237 | _schedule_T_227; // @[Mux.scala:30:73]
wire _schedule_T_239 = _schedule_T_238 | _schedule_T_228; // @[Mux.scala:30:73]
wire _schedule_T_240 = _schedule_T_239 | _schedule_T_229; // @[Mux.scala:30:73]
wire _schedule_T_241 = _schedule_T_240 | _schedule_T_230; // @[Mux.scala:30:73]
assign _schedule_WIRE_14 = _schedule_T_241; // @[Mux.scala:30:73]
assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73]
wire _schedule_WIRE_18; // @[Mux.scala:30:73]
assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_242 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_243 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_244 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_245 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_246 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_247 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_248 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_249 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_250 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_251 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_252 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_253 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_254 = _schedule_T_242 | _schedule_T_243; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_255 = _schedule_T_254 | _schedule_T_244; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_256 = _schedule_T_255 | _schedule_T_245; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_257 = _schedule_T_256 | _schedule_T_246; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_258 = _schedule_T_257 | _schedule_T_247; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_259 = _schedule_T_258 | _schedule_T_248; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_260 = _schedule_T_259 | _schedule_T_249; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_261 = _schedule_T_260 | _schedule_T_250; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_251; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_252; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_253; // @[Mux.scala:30:73]
assign _schedule_WIRE_17 = _schedule_T_264; // @[Mux.scala:30:73]
assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73]
wire _schedule_T_265 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_266 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_267 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_268 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_269 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_270 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_271 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_272 = _schedule_T_7 & _mshrs_7_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_273 = _schedule_T_8 & _mshrs_8_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_274 = _schedule_T_9 & _mshrs_9_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_275 = _schedule_T_10 & _mshrs_10_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_276 = _schedule_T_11 & _mshrs_11_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_277 = _schedule_T_265 | _schedule_T_266; // @[Mux.scala:30:73]
wire _schedule_T_278 = _schedule_T_277 | _schedule_T_267; // @[Mux.scala:30:73]
wire _schedule_T_279 = _schedule_T_278 | _schedule_T_268; // @[Mux.scala:30:73]
wire _schedule_T_280 = _schedule_T_279 | _schedule_T_269; // @[Mux.scala:30:73]
wire _schedule_T_281 = _schedule_T_280 | _schedule_T_270; // @[Mux.scala:30:73]
wire _schedule_T_282 = _schedule_T_281 | _schedule_T_271; // @[Mux.scala:30:73]
wire _schedule_T_283 = _schedule_T_282 | _schedule_T_272; // @[Mux.scala:30:73]
wire _schedule_T_284 = _schedule_T_283 | _schedule_T_273; // @[Mux.scala:30:73]
wire _schedule_T_285 = _schedule_T_284 | _schedule_T_274; // @[Mux.scala:30:73]
wire _schedule_T_286 = _schedule_T_285 | _schedule_T_275; // @[Mux.scala:30:73]
wire _schedule_T_287 = _schedule_T_286 | _schedule_T_276; // @[Mux.scala:30:73]
assign _schedule_WIRE_18 = _schedule_T_287; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73]
wire _schedule_WIRE_37; // @[Mux.scala:30:73]
assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_control; // @[Mux.scala:30:73]
assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73]
assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73]
assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73]
assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73]
assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73]
assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73]
assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_0; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_1; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_2; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_32; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_27; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_24; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_22; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_21; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
wire _schedule_T_288 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_289 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_290 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_291 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_292 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_293 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_294 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_295 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_296 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_297 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_298 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_299 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_300 = _schedule_T_288 | _schedule_T_289; // @[Mux.scala:30:73]
wire _schedule_T_301 = _schedule_T_300 | _schedule_T_290; // @[Mux.scala:30:73]
wire _schedule_T_302 = _schedule_T_301 | _schedule_T_291; // @[Mux.scala:30:73]
wire _schedule_T_303 = _schedule_T_302 | _schedule_T_292; // @[Mux.scala:30:73]
wire _schedule_T_304 = _schedule_T_303 | _schedule_T_293; // @[Mux.scala:30:73]
wire _schedule_T_305 = _schedule_T_304 | _schedule_T_294; // @[Mux.scala:30:73]
wire _schedule_T_306 = _schedule_T_305 | _schedule_T_295; // @[Mux.scala:30:73]
wire _schedule_T_307 = _schedule_T_306 | _schedule_T_296; // @[Mux.scala:30:73]
wire _schedule_T_308 = _schedule_T_307 | _schedule_T_297; // @[Mux.scala:30:73]
wire _schedule_T_309 = _schedule_T_308 | _schedule_T_298; // @[Mux.scala:30:73]
wire _schedule_T_310 = _schedule_T_309 | _schedule_T_299; // @[Mux.scala:30:73]
assign _schedule_WIRE_21 = _schedule_T_310; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_311 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_312 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_313 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_314 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_315 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_316 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_317 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_318 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_319 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_320 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_321 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_322 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_323 = _schedule_T_311 | _schedule_T_312; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_324 = _schedule_T_323 | _schedule_T_313; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_325 = _schedule_T_324 | _schedule_T_314; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_326 = _schedule_T_325 | _schedule_T_315; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_327 = _schedule_T_326 | _schedule_T_316; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_328 = _schedule_T_327 | _schedule_T_317; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_329 = _schedule_T_328 | _schedule_T_318; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_330 = _schedule_T_329 | _schedule_T_319; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_331 = _schedule_T_330 | _schedule_T_320; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_332 = _schedule_T_331 | _schedule_T_321; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_333 = _schedule_T_332 | _schedule_T_322; // @[Mux.scala:30:73]
assign _schedule_WIRE_22 = _schedule_T_333; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_357 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_358 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_359 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_360 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_361 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_362 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_363 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_364 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_365 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_366 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_367 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_368 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_369 = _schedule_T_357 | _schedule_T_358; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_370 = _schedule_T_369 | _schedule_T_359; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_371 = _schedule_T_370 | _schedule_T_360; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_372 = _schedule_T_371 | _schedule_T_361; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_373 = _schedule_T_372 | _schedule_T_362; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_374 = _schedule_T_373 | _schedule_T_363; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_375 = _schedule_T_374 | _schedule_T_364; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_376 = _schedule_T_375 | _schedule_T_365; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_377 = _schedule_T_376 | _schedule_T_366; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_378 = _schedule_T_377 | _schedule_T_367; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_379 = _schedule_T_378 | _schedule_T_368; // @[Mux.scala:30:73]
assign _schedule_WIRE_24 = _schedule_T_379; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_380 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_381 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_382 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_383 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_384 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_385 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_386 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_387 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_388 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_389 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_390 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_391 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_392 = _schedule_T_380 | _schedule_T_381; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_382; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_383; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_384; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_385; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_397 = _schedule_T_396 | _schedule_T_386; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_398 = _schedule_T_397 | _schedule_T_387; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_399 = _schedule_T_398 | _schedule_T_388; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_400 = _schedule_T_399 | _schedule_T_389; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_401 = _schedule_T_400 | _schedule_T_390; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_402 = _schedule_T_401 | _schedule_T_391; // @[Mux.scala:30:73]
assign _schedule_WIRE_25 = _schedule_T_402; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_403 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_404 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_405 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_406 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_407 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_408 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_409 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_410 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_411 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_412 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_413 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_414 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_415 = _schedule_T_403 | _schedule_T_404; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_416 = _schedule_T_415 | _schedule_T_405; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_417 = _schedule_T_416 | _schedule_T_406; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_407; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_408; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_409; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_410; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_411; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_423 = _schedule_T_422 | _schedule_T_412; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_424 = _schedule_T_423 | _schedule_T_413; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_425 = _schedule_T_424 | _schedule_T_414; // @[Mux.scala:30:73]
assign _schedule_WIRE_26 = _schedule_T_425; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_426 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_427 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_428 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_429 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_430 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_431 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_432 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_433 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_434 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_435 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_436 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_437 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_438 = _schedule_T_426 | _schedule_T_427; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_439 = _schedule_T_438 | _schedule_T_428; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_440 = _schedule_T_439 | _schedule_T_429; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_441 = _schedule_T_440 | _schedule_T_430; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_442 = _schedule_T_441 | _schedule_T_431; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_443 = _schedule_T_442 | _schedule_T_432; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_433; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_434; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_435; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_436; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_437; // @[Mux.scala:30:73]
assign _schedule_WIRE_27 = _schedule_T_448; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_456 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_457 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_458 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_459 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_460 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_461 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_462 = _schedule_T_461 | _schedule_T_451; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_463 = _schedule_T_462 | _schedule_T_452; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_464 = _schedule_T_463 | _schedule_T_453; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_465 = _schedule_T_464 | _schedule_T_454; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_466 = _schedule_T_465 | _schedule_T_455; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_467 = _schedule_T_466 | _schedule_T_456; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_468 = _schedule_T_467 | _schedule_T_457; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_469 = _schedule_T_468 | _schedule_T_458; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_470 = _schedule_T_469 | _schedule_T_459; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_471 = _schedule_T_470 | _schedule_T_460; // @[Mux.scala:30:73]
assign _schedule_WIRE_28 = _schedule_T_471; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_472 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_473 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_474 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_475 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_476 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_477 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_478 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_479 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_480 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_481 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_482 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_483 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_484 = _schedule_T_472 | _schedule_T_473; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_474; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_475; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_476; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_488 = _schedule_T_487 | _schedule_T_477; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_489 = _schedule_T_488 | _schedule_T_478; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_490 = _schedule_T_489 | _schedule_T_479; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_491 = _schedule_T_490 | _schedule_T_480; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_492 = _schedule_T_491 | _schedule_T_481; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_493 = _schedule_T_492 | _schedule_T_482; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_494 = _schedule_T_493 | _schedule_T_483; // @[Mux.scala:30:73]
assign _schedule_WIRE_29 = _schedule_T_494; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_495 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_496 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_497 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_498 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_499 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_500 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_501 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_502 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_503 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_504 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_505 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_506 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_507 = _schedule_T_495 | _schedule_T_496; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_508 = _schedule_T_507 | _schedule_T_497; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_498; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_499; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_500; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_501; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_502; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_514 = _schedule_T_513 | _schedule_T_503; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_515 = _schedule_T_514 | _schedule_T_504; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_516 = _schedule_T_515 | _schedule_T_505; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_517 = _schedule_T_516 | _schedule_T_506; // @[Mux.scala:30:73]
assign _schedule_WIRE_30 = _schedule_T_517; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_518 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_519 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_520 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_521 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_522 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_523 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_524 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_525 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_526 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_527 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_528 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_529 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_530 = _schedule_T_518 | _schedule_T_519; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_531 = _schedule_T_530 | _schedule_T_520; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_532 = _schedule_T_531 | _schedule_T_521; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_533 = _schedule_T_532 | _schedule_T_522; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_534 = _schedule_T_533 | _schedule_T_523; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_535 = _schedule_T_534 | _schedule_T_524; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_536 = _schedule_T_535 | _schedule_T_525; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_537 = _schedule_T_536 | _schedule_T_526; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_538 = _schedule_T_537 | _schedule_T_527; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_539 = _schedule_T_538 | _schedule_T_528; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_540 = _schedule_T_539 | _schedule_T_529; // @[Mux.scala:30:73]
assign _schedule_WIRE_31 = _schedule_T_540; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73]
wire _schedule_T_541 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_542 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_543 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_544 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_545 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_546 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_547 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_548 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_549 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_550 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_551 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_552 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_553 = _schedule_T_541 | _schedule_T_542; // @[Mux.scala:30:73]
wire _schedule_T_554 = _schedule_T_553 | _schedule_T_543; // @[Mux.scala:30:73]
wire _schedule_T_555 = _schedule_T_554 | _schedule_T_544; // @[Mux.scala:30:73]
wire _schedule_T_556 = _schedule_T_555 | _schedule_T_545; // @[Mux.scala:30:73]
wire _schedule_T_557 = _schedule_T_556 | _schedule_T_546; // @[Mux.scala:30:73]
wire _schedule_T_558 = _schedule_T_557 | _schedule_T_547; // @[Mux.scala:30:73]
wire _schedule_T_559 = _schedule_T_558 | _schedule_T_548; // @[Mux.scala:30:73]
wire _schedule_T_560 = _schedule_T_559 | _schedule_T_549; // @[Mux.scala:30:73]
wire _schedule_T_561 = _schedule_T_560 | _schedule_T_550; // @[Mux.scala:30:73]
wire _schedule_T_562 = _schedule_T_561 | _schedule_T_551; // @[Mux.scala:30:73]
wire _schedule_T_563 = _schedule_T_562 | _schedule_T_552; // @[Mux.scala:30:73]
assign _schedule_WIRE_32 = _schedule_T_563; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73]
wire _schedule_WIRE_34; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_35; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_36; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73]
wire _schedule_T_564 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_565 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_566 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_567 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_568 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_569 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_570 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_571 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_572 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_573 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_576 = _schedule_T_564 | _schedule_T_565; // @[Mux.scala:30:73]
wire _schedule_T_577 = _schedule_T_576 | _schedule_T_566; // @[Mux.scala:30:73]
wire _schedule_T_578 = _schedule_T_577 | _schedule_T_567; // @[Mux.scala:30:73]
wire _schedule_T_579 = _schedule_T_578 | _schedule_T_568; // @[Mux.scala:30:73]
wire _schedule_T_580 = _schedule_T_579 | _schedule_T_569; // @[Mux.scala:30:73]
wire _schedule_T_581 = _schedule_T_580 | _schedule_T_570; // @[Mux.scala:30:73]
wire _schedule_T_582 = _schedule_T_581 | _schedule_T_571; // @[Mux.scala:30:73]
wire _schedule_T_583 = _schedule_T_582 | _schedule_T_572; // @[Mux.scala:30:73]
wire _schedule_T_584 = _schedule_T_583 | _schedule_T_573; // @[Mux.scala:30:73]
wire _schedule_T_585 = _schedule_T_584; // @[Mux.scala:30:73]
wire _schedule_T_586 = _schedule_T_585; // @[Mux.scala:30:73]
assign _schedule_WIRE_34 = _schedule_T_586; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73]
wire _schedule_T_587 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_588 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_589 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_590 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_591 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_592 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_593 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_594 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_595 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_596 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_597 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_599 = _schedule_T_587 | _schedule_T_588; // @[Mux.scala:30:73]
wire _schedule_T_600 = _schedule_T_599 | _schedule_T_589; // @[Mux.scala:30:73]
wire _schedule_T_601 = _schedule_T_600 | _schedule_T_590; // @[Mux.scala:30:73]
wire _schedule_T_602 = _schedule_T_601 | _schedule_T_591; // @[Mux.scala:30:73]
wire _schedule_T_603 = _schedule_T_602 | _schedule_T_592; // @[Mux.scala:30:73]
wire _schedule_T_604 = _schedule_T_603 | _schedule_T_593; // @[Mux.scala:30:73]
wire _schedule_T_605 = _schedule_T_604 | _schedule_T_594; // @[Mux.scala:30:73]
wire _schedule_T_606 = _schedule_T_605 | _schedule_T_595; // @[Mux.scala:30:73]
wire _schedule_T_607 = _schedule_T_606 | _schedule_T_596; // @[Mux.scala:30:73]
wire _schedule_T_608 = _schedule_T_607 | _schedule_T_597; // @[Mux.scala:30:73]
wire _schedule_T_609 = _schedule_T_608; // @[Mux.scala:30:73]
assign _schedule_WIRE_35 = _schedule_T_609; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73]
wire _schedule_T_610 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_611 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_612 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_613 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_614 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_615 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_616 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_617 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_618 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_619 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_620 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_621 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_622 = _schedule_T_610 | _schedule_T_611; // @[Mux.scala:30:73]
wire _schedule_T_623 = _schedule_T_622 | _schedule_T_612; // @[Mux.scala:30:73]
wire _schedule_T_624 = _schedule_T_623 | _schedule_T_613; // @[Mux.scala:30:73]
wire _schedule_T_625 = _schedule_T_624 | _schedule_T_614; // @[Mux.scala:30:73]
wire _schedule_T_626 = _schedule_T_625 | _schedule_T_615; // @[Mux.scala:30:73]
wire _schedule_T_627 = _schedule_T_626 | _schedule_T_616; // @[Mux.scala:30:73]
wire _schedule_T_628 = _schedule_T_627 | _schedule_T_617; // @[Mux.scala:30:73]
wire _schedule_T_629 = _schedule_T_628 | _schedule_T_618; // @[Mux.scala:30:73]
wire _schedule_T_630 = _schedule_T_629 | _schedule_T_619; // @[Mux.scala:30:73]
wire _schedule_T_631 = _schedule_T_630 | _schedule_T_620; // @[Mux.scala:30:73]
wire _schedule_T_632 = _schedule_T_631 | _schedule_T_621; // @[Mux.scala:30:73]
assign _schedule_WIRE_36 = _schedule_T_632; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73]
wire _schedule_T_633 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_634 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_635 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_636 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_637 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_638 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_639 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_640 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_641 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_642 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_643 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_644 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_645 = _schedule_T_633 | _schedule_T_634; // @[Mux.scala:30:73]
wire _schedule_T_646 = _schedule_T_645 | _schedule_T_635; // @[Mux.scala:30:73]
wire _schedule_T_647 = _schedule_T_646 | _schedule_T_636; // @[Mux.scala:30:73]
wire _schedule_T_648 = _schedule_T_647 | _schedule_T_637; // @[Mux.scala:30:73]
wire _schedule_T_649 = _schedule_T_648 | _schedule_T_638; // @[Mux.scala:30:73]
wire _schedule_T_650 = _schedule_T_649 | _schedule_T_639; // @[Mux.scala:30:73]
wire _schedule_T_651 = _schedule_T_650 | _schedule_T_640; // @[Mux.scala:30:73]
wire _schedule_T_652 = _schedule_T_651 | _schedule_T_641; // @[Mux.scala:30:73]
wire _schedule_T_653 = _schedule_T_652 | _schedule_T_642; // @[Mux.scala:30:73]
wire _schedule_T_654 = _schedule_T_653 | _schedule_T_643; // @[Mux.scala:30:73]
wire _schedule_T_655 = _schedule_T_654 | _schedule_T_644; // @[Mux.scala:30:73]
assign _schedule_WIRE_37 = _schedule_T_655; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73]
wire _schedule_WIRE_47; // @[Mux.scala:30:73]
assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73]
assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73]
assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73]
assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_43; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_42; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_41; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_40; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
wire _schedule_T_656 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_657 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_658 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_659 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_660 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_661 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_662 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_663 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_664 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_665 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_666 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_667 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_668 = _schedule_T_656 | _schedule_T_657; // @[Mux.scala:30:73]
wire _schedule_T_669 = _schedule_T_668 | _schedule_T_658; // @[Mux.scala:30:73]
wire _schedule_T_670 = _schedule_T_669 | _schedule_T_659; // @[Mux.scala:30:73]
wire _schedule_T_671 = _schedule_T_670 | _schedule_T_660; // @[Mux.scala:30:73]
wire _schedule_T_672 = _schedule_T_671 | _schedule_T_661; // @[Mux.scala:30:73]
wire _schedule_T_673 = _schedule_T_672 | _schedule_T_662; // @[Mux.scala:30:73]
wire _schedule_T_674 = _schedule_T_673 | _schedule_T_663; // @[Mux.scala:30:73]
wire _schedule_T_675 = _schedule_T_674 | _schedule_T_664; // @[Mux.scala:30:73]
wire _schedule_T_676 = _schedule_T_675 | _schedule_T_665; // @[Mux.scala:30:73]
wire _schedule_T_677 = _schedule_T_676 | _schedule_T_666; // @[Mux.scala:30:73]
wire _schedule_T_678 = _schedule_T_677 | _schedule_T_667; // @[Mux.scala:30:73]
assign _schedule_WIRE_40 = _schedule_T_678; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_679 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_680 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_681 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_682 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_683 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_684 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_685 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_686 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_687 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_688 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_689 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_690 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_691 = _schedule_T_679 | _schedule_T_680; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_692 = _schedule_T_691 | _schedule_T_681; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_693 = _schedule_T_692 | _schedule_T_682; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_694 = _schedule_T_693 | _schedule_T_683; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_695 = _schedule_T_694 | _schedule_T_684; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_696 = _schedule_T_695 | _schedule_T_685; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_697 = _schedule_T_696 | _schedule_T_686; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_698 = _schedule_T_697 | _schedule_T_687; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_699 = _schedule_T_698 | _schedule_T_688; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_700 = _schedule_T_699 | _schedule_T_689; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_701 = _schedule_T_700 | _schedule_T_690; // @[Mux.scala:30:73]
assign _schedule_WIRE_41 = _schedule_T_701; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_702 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_703 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_704 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_705 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_706 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_707 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_708 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_709 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_710 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_711 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_712 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_713 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_714 = _schedule_T_702 | _schedule_T_703; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_715 = _schedule_T_714 | _schedule_T_704; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_716 = _schedule_T_715 | _schedule_T_705; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_717 = _schedule_T_716 | _schedule_T_706; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_718 = _schedule_T_717 | _schedule_T_707; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_719 = _schedule_T_718 | _schedule_T_708; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_720 = _schedule_T_719 | _schedule_T_709; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_721 = _schedule_T_720 | _schedule_T_710; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_722 = _schedule_T_721 | _schedule_T_711; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_723 = _schedule_T_722 | _schedule_T_712; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_724 = _schedule_T_723 | _schedule_T_713; // @[Mux.scala:30:73]
assign _schedule_WIRE_42 = _schedule_T_724; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_725 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_726 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_727 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_728 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_729 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_730 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_731 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_732 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_733 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_734 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_735 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_736 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_737 = _schedule_T_725 | _schedule_T_726; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_738 = _schedule_T_737 | _schedule_T_727; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_739 = _schedule_T_738 | _schedule_T_728; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_740 = _schedule_T_739 | _schedule_T_729; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_741 = _schedule_T_740 | _schedule_T_730; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_742 = _schedule_T_741 | _schedule_T_731; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_743 = _schedule_T_742 | _schedule_T_732; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_744 = _schedule_T_743 | _schedule_T_733; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_745 = _schedule_T_744 | _schedule_T_734; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_746 = _schedule_T_745 | _schedule_T_735; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_747 = _schedule_T_746 | _schedule_T_736; // @[Mux.scala:30:73]
assign _schedule_WIRE_43 = _schedule_T_747; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_771 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_772 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_773 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_774 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_775 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_776 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_777 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_778 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_779 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_780 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_781 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_782 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_783 = _schedule_T_771 | _schedule_T_772; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_784 = _schedule_T_783 | _schedule_T_773; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_785 = _schedule_T_784 | _schedule_T_774; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_786 = _schedule_T_785 | _schedule_T_775; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_787 = _schedule_T_786 | _schedule_T_776; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_788 = _schedule_T_787 | _schedule_T_777; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_789 = _schedule_T_788 | _schedule_T_778; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_790 = _schedule_T_789 | _schedule_T_779; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_791 = _schedule_T_790 | _schedule_T_780; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_792 = _schedule_T_791 | _schedule_T_781; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_793 = _schedule_T_792 | _schedule_T_782; // @[Mux.scala:30:73]
assign _schedule_WIRE_45 = _schedule_T_793; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_794 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_795 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_796 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_797 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_798 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_799 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_800 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_801 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_802 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_803 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_804 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_805 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_806 = _schedule_T_794 | _schedule_T_795; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_807 = _schedule_T_806 | _schedule_T_796; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_808 = _schedule_T_807 | _schedule_T_797; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_809 = _schedule_T_808 | _schedule_T_798; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_810 = _schedule_T_809 | _schedule_T_799; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_811 = _schedule_T_810 | _schedule_T_800; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_812 = _schedule_T_811 | _schedule_T_801; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_813 = _schedule_T_812 | _schedule_T_802; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_814 = _schedule_T_813 | _schedule_T_803; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_815 = _schedule_T_814 | _schedule_T_804; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_816 = _schedule_T_815 | _schedule_T_805; // @[Mux.scala:30:73]
assign _schedule_WIRE_46 = _schedule_T_816; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73]
wire _schedule_T_817 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_818 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_819 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_820 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_821 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_822 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_823 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_824 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_825 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_826 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_827 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_828 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_829 = _schedule_T_817 | _schedule_T_818; // @[Mux.scala:30:73]
wire _schedule_T_830 = _schedule_T_829 | _schedule_T_819; // @[Mux.scala:30:73]
wire _schedule_T_831 = _schedule_T_830 | _schedule_T_820; // @[Mux.scala:30:73]
wire _schedule_T_832 = _schedule_T_831 | _schedule_T_821; // @[Mux.scala:30:73]
wire _schedule_T_833 = _schedule_T_832 | _schedule_T_822; // @[Mux.scala:30:73]
wire _schedule_T_834 = _schedule_T_833 | _schedule_T_823; // @[Mux.scala:30:73]
wire _schedule_T_835 = _schedule_T_834 | _schedule_T_824; // @[Mux.scala:30:73]
wire _schedule_T_836 = _schedule_T_835 | _schedule_T_825; // @[Mux.scala:30:73]
wire _schedule_T_837 = _schedule_T_836 | _schedule_T_826; // @[Mux.scala:30:73]
wire _schedule_T_838 = _schedule_T_837 | _schedule_T_827; // @[Mux.scala:30:73]
wire _schedule_T_839 = _schedule_T_838 | _schedule_T_828; // @[Mux.scala:30:73]
assign _schedule_WIRE_47 = _schedule_T_839; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73]
wire _schedule_WIRE_54; // @[Mux.scala:30:73]
assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73]
assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73]
assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_52; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_51; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_50; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
wire _schedule_T_840 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_841 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_842 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_843 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_844 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_845 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_846 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_847 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_848 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_849 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_850 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_851 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_852 = _schedule_T_840 | _schedule_T_841; // @[Mux.scala:30:73]
wire _schedule_T_853 = _schedule_T_852 | _schedule_T_842; // @[Mux.scala:30:73]
wire _schedule_T_854 = _schedule_T_853 | _schedule_T_843; // @[Mux.scala:30:73]
wire _schedule_T_855 = _schedule_T_854 | _schedule_T_844; // @[Mux.scala:30:73]
wire _schedule_T_856 = _schedule_T_855 | _schedule_T_845; // @[Mux.scala:30:73]
wire _schedule_T_857 = _schedule_T_856 | _schedule_T_846; // @[Mux.scala:30:73]
wire _schedule_T_858 = _schedule_T_857 | _schedule_T_847; // @[Mux.scala:30:73]
wire _schedule_T_859 = _schedule_T_858 | _schedule_T_848; // @[Mux.scala:30:73]
wire _schedule_T_860 = _schedule_T_859 | _schedule_T_849; // @[Mux.scala:30:73]
wire _schedule_T_861 = _schedule_T_860 | _schedule_T_850; // @[Mux.scala:30:73]
wire _schedule_T_862 = _schedule_T_861 | _schedule_T_851; // @[Mux.scala:30:73]
assign _schedule_WIRE_50 = _schedule_T_862; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_863 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_864 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_865 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_866 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_867 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_868 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_869 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_870 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_871 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_872 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_873 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_874 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_875 = _schedule_T_863 | _schedule_T_864; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_876 = _schedule_T_875 | _schedule_T_865; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_877 = _schedule_T_876 | _schedule_T_866; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_878 = _schedule_T_877 | _schedule_T_867; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_879 = _schedule_T_878 | _schedule_T_868; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_880 = _schedule_T_879 | _schedule_T_869; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_881 = _schedule_T_880 | _schedule_T_870; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_882 = _schedule_T_881 | _schedule_T_871; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_883 = _schedule_T_882 | _schedule_T_872; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_884 = _schedule_T_883 | _schedule_T_873; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_885 = _schedule_T_884 | _schedule_T_874; // @[Mux.scala:30:73]
assign _schedule_WIRE_51 = _schedule_T_885; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_886 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_887 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_888 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_889 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_890 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_891 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_892 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_893 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_894 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_895 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_896 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_897 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_898 = _schedule_T_886 | _schedule_T_887; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_899 = _schedule_T_898 | _schedule_T_888; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_900 = _schedule_T_899 | _schedule_T_889; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_901 = _schedule_T_900 | _schedule_T_890; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_902 = _schedule_T_901 | _schedule_T_891; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_903 = _schedule_T_902 | _schedule_T_892; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_904 = _schedule_T_903 | _schedule_T_893; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_905 = _schedule_T_904 | _schedule_T_894; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_906 = _schedule_T_905 | _schedule_T_895; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_907 = _schedule_T_906 | _schedule_T_896; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_908 = _schedule_T_907 | _schedule_T_897; // @[Mux.scala:30:73]
assign _schedule_WIRE_52 = _schedule_T_908; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_909 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_910 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_911 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_912 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_913 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_914 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_915 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_916 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_917 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_918 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_919 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_920 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_921 = _schedule_T_909 | _schedule_T_910; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_922 = _schedule_T_921 | _schedule_T_911; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_923 = _schedule_T_922 | _schedule_T_912; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_924 = _schedule_T_923 | _schedule_T_913; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_925 = _schedule_T_924 | _schedule_T_914; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_926 = _schedule_T_925 | _schedule_T_915; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_927 = _schedule_T_926 | _schedule_T_916; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_928 = _schedule_T_927 | _schedule_T_917; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_929 = _schedule_T_928 | _schedule_T_918; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_930 = _schedule_T_929 | _schedule_T_919; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_931 = _schedule_T_930 | _schedule_T_920; // @[Mux.scala:30:73]
assign _schedule_WIRE_53 = _schedule_T_931; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73]
wire _schedule_T_932 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_933 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_934 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_935 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_936 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_937 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_938 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_939 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_940 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_941 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_942 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_943 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_944 = _schedule_T_932 | _schedule_T_933; // @[Mux.scala:30:73]
wire _schedule_T_945 = _schedule_T_944 | _schedule_T_934; // @[Mux.scala:30:73]
wire _schedule_T_946 = _schedule_T_945 | _schedule_T_935; // @[Mux.scala:30:73]
wire _schedule_T_947 = _schedule_T_946 | _schedule_T_936; // @[Mux.scala:30:73]
wire _schedule_T_948 = _schedule_T_947 | _schedule_T_937; // @[Mux.scala:30:73]
wire _schedule_T_949 = _schedule_T_948 | _schedule_T_938; // @[Mux.scala:30:73]
wire _schedule_T_950 = _schedule_T_949 | _schedule_T_939; // @[Mux.scala:30:73]
wire _schedule_T_951 = _schedule_T_950 | _schedule_T_940; // @[Mux.scala:30:73]
wire _schedule_T_952 = _schedule_T_951 | _schedule_T_941; // @[Mux.scala:30:73]
wire _schedule_T_953 = _schedule_T_952 | _schedule_T_942; // @[Mux.scala:30:73]
wire _schedule_T_954 = _schedule_T_953 | _schedule_T_943; // @[Mux.scala:30:73]
assign _schedule_WIRE_54 = _schedule_T_954; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73]
wire _schedule_WIRE_62; // @[Mux.scala:30:73]
assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73]
assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73]
assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_56_block; // @[Mux.scala:30:73]
assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_61; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_60; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73]
wire _schedule_T_955 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_956 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_957 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_958 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_959 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_960 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_961 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_962 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_963 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_964 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_965 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_966 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_967 = _schedule_T_955 | _schedule_T_956; // @[Mux.scala:30:73]
wire _schedule_T_968 = _schedule_T_967 | _schedule_T_957; // @[Mux.scala:30:73]
wire _schedule_T_969 = _schedule_T_968 | _schedule_T_958; // @[Mux.scala:30:73]
wire _schedule_T_970 = _schedule_T_969 | _schedule_T_959; // @[Mux.scala:30:73]
wire _schedule_T_971 = _schedule_T_970 | _schedule_T_960; // @[Mux.scala:30:73]
wire _schedule_T_972 = _schedule_T_971 | _schedule_T_961; // @[Mux.scala:30:73]
wire _schedule_T_973 = _schedule_T_972 | _schedule_T_962; // @[Mux.scala:30:73]
wire _schedule_T_974 = _schedule_T_973 | _schedule_T_963; // @[Mux.scala:30:73]
wire _schedule_T_975 = _schedule_T_974 | _schedule_T_964; // @[Mux.scala:30:73]
wire _schedule_T_976 = _schedule_T_975 | _schedule_T_965; // @[Mux.scala:30:73]
wire _schedule_T_977 = _schedule_T_976 | _schedule_T_966; // @[Mux.scala:30:73]
assign _schedule_WIRE_57 = _schedule_T_977; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1001 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1002 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1003 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1004 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1005 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1006 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1007 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1008 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1009 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1010 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1011 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1012 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1013 = _schedule_T_1001 | _schedule_T_1002; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1014 = _schedule_T_1013 | _schedule_T_1003; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1015 = _schedule_T_1014 | _schedule_T_1004; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1016 = _schedule_T_1015 | _schedule_T_1005; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1017 = _schedule_T_1016 | _schedule_T_1006; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1018 = _schedule_T_1017 | _schedule_T_1007; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1019 = _schedule_T_1018 | _schedule_T_1008; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1020 = _schedule_T_1019 | _schedule_T_1009; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1021 = _schedule_T_1020 | _schedule_T_1010; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1022 = _schedule_T_1021 | _schedule_T_1011; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1023 = _schedule_T_1022 | _schedule_T_1012; // @[Mux.scala:30:73]
assign _schedule_WIRE_59 = _schedule_T_1023; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1024 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1025 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1026 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1027 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1028 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1029 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1030 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1031 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1032 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1033 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1034 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1035 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1036 = _schedule_T_1024 | _schedule_T_1025; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1037 = _schedule_T_1036 | _schedule_T_1026; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1038 = _schedule_T_1037 | _schedule_T_1027; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1039 = _schedule_T_1038 | _schedule_T_1028; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1040 = _schedule_T_1039 | _schedule_T_1029; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1041 = _schedule_T_1040 | _schedule_T_1030; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1042 = _schedule_T_1041 | _schedule_T_1031; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1043 = _schedule_T_1042 | _schedule_T_1032; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1044 = _schedule_T_1043 | _schedule_T_1033; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1045 = _schedule_T_1044 | _schedule_T_1034; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1046 = _schedule_T_1045 | _schedule_T_1035; // @[Mux.scala:30:73]
assign _schedule_WIRE_60 = _schedule_T_1046; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1047 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1048 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1049 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1050 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1051 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1052 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1053 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1054 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1055 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1056 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1057 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1058 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1059 = _schedule_T_1047 | _schedule_T_1048; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1060 = _schedule_T_1059 | _schedule_T_1049; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1061 = _schedule_T_1060 | _schedule_T_1050; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1062 = _schedule_T_1061 | _schedule_T_1051; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1063 = _schedule_T_1062 | _schedule_T_1052; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1064 = _schedule_T_1063 | _schedule_T_1053; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1065 = _schedule_T_1064 | _schedule_T_1054; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1066 = _schedule_T_1065 | _schedule_T_1055; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1067 = _schedule_T_1066 | _schedule_T_1056; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1068 = _schedule_T_1067 | _schedule_T_1057; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1069 = _schedule_T_1068 | _schedule_T_1058; // @[Mux.scala:30:73]
assign _schedule_WIRE_61 = _schedule_T_1069; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73]
wire _schedule_T_1070 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1071 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1072 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1073 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1074 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1075 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1076 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1077 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1078 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1079 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1080 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1081 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1082 = _schedule_T_1070 | _schedule_T_1071; // @[Mux.scala:30:73]
wire _schedule_T_1083 = _schedule_T_1082 | _schedule_T_1072; // @[Mux.scala:30:73]
wire _schedule_T_1084 = _schedule_T_1083 | _schedule_T_1073; // @[Mux.scala:30:73]
wire _schedule_T_1085 = _schedule_T_1084 | _schedule_T_1074; // @[Mux.scala:30:73]
wire _schedule_T_1086 = _schedule_T_1085 | _schedule_T_1075; // @[Mux.scala:30:73]
wire _schedule_T_1087 = _schedule_T_1086 | _schedule_T_1076; // @[Mux.scala:30:73]
wire _schedule_T_1088 = _schedule_T_1087 | _schedule_T_1077; // @[Mux.scala:30:73]
wire _schedule_T_1089 = _schedule_T_1088 | _schedule_T_1078; // @[Mux.scala:30:73]
wire _schedule_T_1090 = _schedule_T_1089 | _schedule_T_1079; // @[Mux.scala:30:73]
wire _schedule_T_1091 = _schedule_T_1090 | _schedule_T_1080; // @[Mux.scala:30:73]
wire _schedule_T_1092 = _schedule_T_1091 | _schedule_T_1081; // @[Mux.scala:30:73]
assign _schedule_WIRE_62 = _schedule_T_1092; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_12 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_13 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_14 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_15 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_16 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_17 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_18 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_19 = _scheduleTag_T_7 ? _mshrs_7_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_20 = _scheduleTag_T_8 ? _mshrs_8_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_21 = _scheduleTag_T_9 ? _mshrs_9_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_22 = _scheduleTag_T_10 ? _mshrs_10_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_23 = _scheduleTag_T_11 ? _mshrs_11_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_24 = _scheduleTag_T_12 | _scheduleTag_T_13; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_25 = _scheduleTag_T_24 | _scheduleTag_T_14; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_26 = _scheduleTag_T_25 | _scheduleTag_T_15; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_27 = _scheduleTag_T_26 | _scheduleTag_T_16; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_28 = _scheduleTag_T_27 | _scheduleTag_T_17; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_29 = _scheduleTag_T_28 | _scheduleTag_T_18; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_30 = _scheduleTag_T_29 | _scheduleTag_T_19; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_31 = _scheduleTag_T_30 | _scheduleTag_T_20; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_32 = _scheduleTag_T_31 | _scheduleTag_T_21; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_33 = _scheduleTag_T_32 | _scheduleTag_T_22; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_34 = _scheduleTag_T_33 | _scheduleTag_T_23; // @[Mux.scala:30:73]
wire [8:0] scheduleTag = _scheduleTag_T_34; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_12 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_13 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_14 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_15 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_16 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_17 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_18 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_19 = _scheduleSet_T_7 ? _mshrs_7_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_20 = _scheduleSet_T_8 ? _mshrs_8_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_21 = _scheduleSet_T_9 ? _mshrs_9_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_22 = _scheduleSet_T_10 ? _mshrs_10_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_23 = _scheduleSet_T_11 ? _mshrs_11_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_24 = _scheduleSet_T_12 | _scheduleSet_T_13; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_25 = _scheduleSet_T_24 | _scheduleSet_T_14; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_26 = _scheduleSet_T_25 | _scheduleSet_T_15; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_27 = _scheduleSet_T_26 | _scheduleSet_T_16; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_28 = _scheduleSet_T_27 | _scheduleSet_T_17; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_29 = _scheduleSet_T_28 | _scheduleSet_T_18; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_30 = _scheduleSet_T_29 | _scheduleSet_T_19; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_31 = _scheduleSet_T_30 | _scheduleSet_T_20; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_32 = _scheduleSet_T_31 | _scheduleSet_T_21; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_33 = _scheduleSet_T_32 | _scheduleSet_T_22; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_34 = _scheduleSet_T_33 | _scheduleSet_T_23; // @[Mux.scala:30:73]
wire [10:0] scheduleSet = _scheduleSet_T_34; // @[Mux.scala:30:73]
wire [10:0] _robin_filter_T = mshr_selectOH[11:1]; // @[package.scala:262:48]
wire [11:0] _robin_filter_T_1 = {mshr_selectOH[11], mshr_selectOH[10:0] | _robin_filter_T}; // @[Mux.scala:32:36]
wire [9:0] _robin_filter_T_2 = _robin_filter_T_1[11:2]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_3 = {_robin_filter_T_1[11:10], _robin_filter_T_1[9:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}]
wire [7:0] _robin_filter_T_4 = _robin_filter_T_3[11:4]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_5 = {_robin_filter_T_3[11:8], _robin_filter_T_3[7:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}]
wire [3:0] _robin_filter_T_6 = _robin_filter_T_5[11:8]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_7 = {_robin_filter_T_5[11:4], _robin_filter_T_5[3:0] | _robin_filter_T_6}; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_8 = _robin_filter_T_7; // @[package.scala:262:43, :263:17]
wire [11:0] _robin_filter_T_9 = ~_robin_filter_T_8; // @[package.scala:263:17]
wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73]
assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 4'h0; // @[OneHot.scala:32:10]
assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73]
assign _nestedwb_set_T = select_c ? _mshrs_11_io_status_bits_set : _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24]
assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24]
assign _nestedwb_tag_T = select_c ? _mshrs_11_io_status_bits_tag : _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24]
assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24]
wire _GEN = select_bc & _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37]
wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37]
assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37]
wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37]
assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37]
assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37]
wire _nestedwb_b_toN_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123]
assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}]
assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75]
wire _nestedwb_b_toB_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123]
assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}]
assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75]
assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37]
wire _nestedwb_c_set_dirty_T = select_c & _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37]
assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}]
assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75]
wire _request_ready_T_2; // @[Scheduler.scala:261:40]
wire _request_valid_T_2; // @[Scheduler.scala:164:39]
wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22]
wire _request_bits_T_1_control; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22]
wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22]
wire [8:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_7_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_8_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_9_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_10_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_11_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [10:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [10:0] request_bits_set; // @[Scheduler.scala:163:21]
wire request_ready; // @[Scheduler.scala:163:21]
wire request_valid; // @[Scheduler.scala:163:21]
wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62]
wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}]
assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}]
assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39]
wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [8:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [10:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire _request_bits_T_control; // @[Scheduler.scala:166:22]
assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22]
assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22]
wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44]
wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44]
assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44]
wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44]
assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44]
wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44]
assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44]
wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64]
wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}]
wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64]
wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}]
wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87]
wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}]
wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_14 = _mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_15 = _mshrs_7_io_status_valid & _setMatches_T_14; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_16 = _mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_17 = _mshrs_8_io_status_valid & _setMatches_T_16; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_18 = _mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_19 = _mshrs_9_io_status_valid & _setMatches_T_18; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_20 = _mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_21 = _mshrs_10_io_status_valid & _setMatches_T_20; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_22 = _mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_23 = _mshrs_11_io_status_valid & _setMatches_T_22; // @[Scheduler.scala:71:46, :172:{59,83}]
wire [1:0] setMatches_lo_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_lo = {setMatches_lo_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_lo_hi_hi = {_setMatches_T_11, _setMatches_T_9}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_hi = {setMatches_lo_hi_hi, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_lo = {setMatches_lo_hi, setMatches_lo_lo}; // @[Scheduler.scala:172:23]
wire [1:0] setMatches_hi_lo_hi = {_setMatches_T_17, _setMatches_T_15}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_lo = {setMatches_hi_lo_hi, _setMatches_T_13}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_hi_hi_hi = {_setMatches_T_23, _setMatches_T_21}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_hi = {setMatches_hi_hi_hi, _setMatches_T_19}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23]
wire [11:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23]
wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27]
wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}]
wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockB_T_12 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_13 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_14 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_15 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_16 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_17 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_18 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_19 = _blockB_T_7 & _mshrs_7_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_20 = _blockB_T_8 & _mshrs_8_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_21 = _blockB_T_9 & _mshrs_9_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_22 = _blockB_T_10 & _mshrs_10_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_23 = _blockB_T_11 & _mshrs_11_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_24 = _blockB_T_12 | _blockB_T_13; // @[Mux.scala:30:73]
wire _blockB_T_25 = _blockB_T_24 | _blockB_T_14; // @[Mux.scala:30:73]
wire _blockB_T_26 = _blockB_T_25 | _blockB_T_15; // @[Mux.scala:30:73]
wire _blockB_T_27 = _blockB_T_26 | _blockB_T_16; // @[Mux.scala:30:73]
wire _blockB_T_28 = _blockB_T_27 | _blockB_T_17; // @[Mux.scala:30:73]
wire _blockB_T_29 = _blockB_T_28 | _blockB_T_18; // @[Mux.scala:30:73]
wire _blockB_T_30 = _blockB_T_29 | _blockB_T_19; // @[Mux.scala:30:73]
wire _blockB_T_31 = _blockB_T_30 | _blockB_T_20; // @[Mux.scala:30:73]
wire _blockB_T_32 = _blockB_T_31 | _blockB_T_21; // @[Mux.scala:30:73]
wire _blockB_T_33 = _blockB_T_32 | _blockB_T_22; // @[Mux.scala:30:73]
wire _blockB_T_34 = _blockB_T_33 | _blockB_T_23; // @[Mux.scala:30:73]
wire _blockB_WIRE = _blockB_T_34; // @[Mux.scala:30:73]
wire _blockC_T_12 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_13 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_14 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_15 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_16 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_17 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_18 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_19 = _blockC_T_7 & _mshrs_7_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_20 = _blockC_T_8 & _mshrs_8_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_21 = _blockC_T_9 & _mshrs_9_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_22 = _blockC_T_10 & _mshrs_10_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_23 = _blockC_T_11 & _mshrs_11_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_24 = _blockC_T_12 | _blockC_T_13; // @[Mux.scala:30:73]
wire _blockC_T_25 = _blockC_T_24 | _blockC_T_14; // @[Mux.scala:30:73]
wire _blockC_T_26 = _blockC_T_25 | _blockC_T_15; // @[Mux.scala:30:73]
wire _blockC_T_27 = _blockC_T_26 | _blockC_T_16; // @[Mux.scala:30:73]
wire _blockC_T_28 = _blockC_T_27 | _blockC_T_17; // @[Mux.scala:30:73]
wire _blockC_T_29 = _blockC_T_28 | _blockC_T_18; // @[Mux.scala:30:73]
wire _blockC_T_30 = _blockC_T_29 | _blockC_T_19; // @[Mux.scala:30:73]
wire _blockC_T_31 = _blockC_T_30 | _blockC_T_20; // @[Mux.scala:30:73]
wire _blockC_T_32 = _blockC_T_31 | _blockC_T_21; // @[Mux.scala:30:73]
wire _blockC_T_33 = _blockC_T_32 | _blockC_T_22; // @[Mux.scala:30:73]
wire _blockC_T_34 = _blockC_T_33 | _blockC_T_23; // @[Mux.scala:30:73]
wire _blockC_WIRE = _blockC_T_34; // @[Mux.scala:30:73]
wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _nestB_T_12 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_13 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_14 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_15 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_16 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_17 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_18 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_19 = _nestB_T_7 & _mshrs_7_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_20 = _nestB_T_8 & _mshrs_8_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_21 = _nestB_T_9 & _mshrs_9_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_22 = _nestB_T_10 & _mshrs_10_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_23 = _nestB_T_11 & _mshrs_11_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_24 = _nestB_T_12 | _nestB_T_13; // @[Mux.scala:30:73]
wire _nestB_T_25 = _nestB_T_24 | _nestB_T_14; // @[Mux.scala:30:73]
wire _nestB_T_26 = _nestB_T_25 | _nestB_T_15; // @[Mux.scala:30:73]
wire _nestB_T_27 = _nestB_T_26 | _nestB_T_16; // @[Mux.scala:30:73]
wire _nestB_T_28 = _nestB_T_27 | _nestB_T_17; // @[Mux.scala:30:73]
wire _nestB_T_29 = _nestB_T_28 | _nestB_T_18; // @[Mux.scala:30:73]
wire _nestB_T_30 = _nestB_T_29 | _nestB_T_19; // @[Mux.scala:30:73]
wire _nestB_T_31 = _nestB_T_30 | _nestB_T_20; // @[Mux.scala:30:73]
wire _nestB_T_32 = _nestB_T_31 | _nestB_T_21; // @[Mux.scala:30:73]
wire _nestB_T_33 = _nestB_T_32 | _nestB_T_22; // @[Mux.scala:30:73]
wire _nestB_T_34 = _nestB_T_33 | _nestB_T_23; // @[Mux.scala:30:73]
wire _nestB_WIRE = _nestB_T_34; // @[Mux.scala:30:73]
wire _nestC_T_12 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_13 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_14 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_15 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_16 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_17 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_18 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_19 = _nestC_T_7 & _mshrs_7_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_20 = _nestC_T_8 & _mshrs_8_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_21 = _nestC_T_9 & _mshrs_9_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_22 = _nestC_T_10 & _mshrs_10_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_23 = _nestC_T_11 & _mshrs_11_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_24 = _nestC_T_12 | _nestC_T_13; // @[Mux.scala:30:73]
wire _nestC_T_25 = _nestC_T_24 | _nestC_T_14; // @[Mux.scala:30:73]
wire _nestC_T_26 = _nestC_T_25 | _nestC_T_15; // @[Mux.scala:30:73]
wire _nestC_T_27 = _nestC_T_26 | _nestC_T_16; // @[Mux.scala:30:73]
wire _nestC_T_28 = _nestC_T_27 | _nestC_T_17; // @[Mux.scala:30:73]
wire _nestC_T_29 = _nestC_T_28 | _nestC_T_18; // @[Mux.scala:30:73]
wire _nestC_T_30 = _nestC_T_29 | _nestC_T_19; // @[Mux.scala:30:73]
wire _nestC_T_31 = _nestC_T_30 | _nestC_T_20; // @[Mux.scala:30:73]
wire _nestC_T_32 = _nestC_T_31 | _nestC_T_21; // @[Mux.scala:30:73]
wire _nestC_T_33 = _nestC_T_32 | _nestC_T_22; // @[Mux.scala:30:73]
wire _nestC_T_34 = _nestC_T_33 | _nestC_T_23; // @[Mux.scala:30:73]
wire _nestC_WIRE = _nestC_T_34; // @[Mux.scala:30:73]
wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46]
wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}]
wire [11:0] prioFilter = {prioFilter_hi, 10'h3FF}; // @[Scheduler.scala:182:23]
wire [11:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33]
wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28]
wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}]
wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45]
wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}]
wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}]
wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66]
wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}]
wire _T_12 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31]
wire _bypass_T; // @[Scheduler.scala:213:30]
assign _bypass_T = _T_12; // @[Scheduler.scala:195:31, :213:30]
wire _bypass_T_1; // @[Scheduler.scala:231:32]
assign _bypass_T_1 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_2; // @[Scheduler.scala:231:32]
assign _bypass_T_2 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_3; // @[Scheduler.scala:231:32]
assign _bypass_T_3 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_4; // @[Scheduler.scala:231:32]
assign _bypass_T_4 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_5; // @[Scheduler.scala:231:32]
assign _bypass_T_5 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_6; // @[Scheduler.scala:231:32]
assign _bypass_T_6 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_7; // @[Scheduler.scala:231:32]
assign _bypass_T_7 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_8; // @[Scheduler.scala:231:32]
assign _bypass_T_8 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_9; // @[Scheduler.scala:231:32]
assign _bypass_T_9 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_10; // @[Scheduler.scala:231:32]
assign _bypass_T_10 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_11; // @[Scheduler.scala:231:32]
assign _bypass_T_11 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_12; // @[Scheduler.scala:231:32]
assign _bypass_T_12 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43]
assign _requests_io_push_valid_T = _T_12; // @[Scheduler.scala:195:31, :270:43]
wire _lowerMatches1_T = lowerMatches[11]; // @[Scheduler.scala:183:33, :200:21]
wire _lowerMatches1_T_2 = lowerMatches[10]; // @[Scheduler.scala:183:33, :201:21]
wire [11:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 12'h400 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}]
wire [11:0] lowerMatches1 = _lowerMatches1_T ? 12'h800 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8]
wire [11:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30]
wire [23:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30]
wire [23:0] selected_requests_hi; // @[Scheduler.scala:206:30]
assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30]
wire [23:0] pop_index_hi; // @[Scheduler.scala:241:31]
assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31]
wire [35:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30]
wire [35:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}]
wire [11:0] _a_pop_T = selected_requests[11:0]; // @[Scheduler.scala:206:76, :207:32]
wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}]
wire [11:0] _b_pop_T = selected_requests[23:12]; // @[Scheduler.scala:206:76, :208:32]
wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}]
wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76]
wire [11:0] _c_pop_T = selected_requests[35:24]; // @[Scheduler.scala:206:76, :209:32]
wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}]
wire [11:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38]
wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}]
wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33]
wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58]
wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101]
wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109]
wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}]
wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}]
wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26]
wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23]
wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}]
wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}]
wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49]
wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73]
wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73]
wire _will_pop_T; // @[Scheduler.scala:215:34]
assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34]
wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64]
assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64]
wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48]
wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}]
wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_1 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_1 = _requests_io_valid[24]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_2 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_2 = _requests_io_valid[25]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_3 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_3 = _requests_io_valid[26]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_4 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_4 = _requests_io_valid[27]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_5 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_5 = _requests_io_valid[28]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_6 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_6 = _requests_io_valid[29]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_7 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_7 = _requests_io_valid[30]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_8 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_8 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_68 = b_pop_8; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_8 = _requests_io_valid[31]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_65 = lowerMatches1[7]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_66 = c_pop_8 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_67 = ~c_pop_8; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_69 = ~b_pop_8; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_70 = ~a_pop_8; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_71 = _bypassMatches_T_68 ? _bypassMatches_T_69 : _bypassMatches_T_70; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_72 = _bypassMatches_T_66 ? _bypassMatches_T_67 : _bypassMatches_T_71; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_8 = _bypassMatches_T_65 & _bypassMatches_T_72; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_8 = a_pop_8 | b_pop_8; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_8 = _may_pop_T_8 | c_pop_8; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_8 = _bypass_T_8 & bypassMatches_8; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_8 = may_pop_8 | bypass_8; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_8 = _mshrs_7_io_schedule_bits_reload & _will_reload_T_8; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_7_prio_0 = bypass_8 ? _view__WIRE_7_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_prio_1 = ~bypass_8 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_7_prio_2 = bypass_8 ? _view__WIRE_7_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_control = bypass_8 ? _view__WIRE_7_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_opcode = bypass_8 ? _view__WIRE_7_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_param = bypass_8 ? _view__WIRE_7_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_size = bypass_8 ? _view__WIRE_7_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_source = bypass_8 ? _view__WIRE_7_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_7_tag = bypass_8 ? _view__WIRE_7_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_offset = bypass_8 ? _view__WIRE_7_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_put = bypass_8 ? _view__WIRE_7_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_7_io_allocate_bits_repeat_T = mshrs_7_io_allocate_bits_tag == _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_7_io_allocate_valid_T = sel_7 & will_reload_8; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_9 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_9 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_76 = b_pop_9; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_9 = _requests_io_valid[32]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_73 = lowerMatches1[8]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_74 = c_pop_9 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_75 = ~c_pop_9; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_77 = ~b_pop_9; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_78 = ~a_pop_9; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_79 = _bypassMatches_T_76 ? _bypassMatches_T_77 : _bypassMatches_T_78; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_80 = _bypassMatches_T_74 ? _bypassMatches_T_75 : _bypassMatches_T_79; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_9 = _bypassMatches_T_73 & _bypassMatches_T_80; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_9 = a_pop_9 | b_pop_9; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_9 = _may_pop_T_9 | c_pop_9; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_9 = _bypass_T_9 & bypassMatches_9; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_9 = may_pop_9 | bypass_9; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_9 = _mshrs_8_io_schedule_bits_reload & _will_reload_T_9; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_8_prio_0 = bypass_9 ? _view__WIRE_8_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_prio_1 = ~bypass_9 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_8_prio_2 = bypass_9 ? _view__WIRE_8_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_control = bypass_9 ? _view__WIRE_8_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_opcode = bypass_9 ? _view__WIRE_8_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_param = bypass_9 ? _view__WIRE_8_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_size = bypass_9 ? _view__WIRE_8_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_source = bypass_9 ? _view__WIRE_8_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_8_tag = bypass_9 ? _view__WIRE_8_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_offset = bypass_9 ? _view__WIRE_8_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_put = bypass_9 ? _view__WIRE_8_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_8_io_allocate_bits_repeat_T = mshrs_8_io_allocate_bits_tag == _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_8_io_allocate_valid_T = sel_8 & will_reload_9; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_10 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_10 = _requests_io_valid[21]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_84 = b_pop_10; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_10 = _requests_io_valid[33]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_81 = lowerMatches1[9]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_82 = c_pop_10 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_83 = ~c_pop_10; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_85 = ~b_pop_10; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_86 = ~a_pop_10; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_87 = _bypassMatches_T_84 ? _bypassMatches_T_85 : _bypassMatches_T_86; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_88 = _bypassMatches_T_82 ? _bypassMatches_T_83 : _bypassMatches_T_87; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_10 = _bypassMatches_T_81 & _bypassMatches_T_88; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_10 = a_pop_10 | b_pop_10; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_10 = _may_pop_T_10 | c_pop_10; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_10 = _bypass_T_10 & bypassMatches_10; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_10 = may_pop_10 | bypass_10; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_10 = _mshrs_9_io_schedule_bits_reload & _will_reload_T_10; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_9_prio_0 = bypass_10 ? _view__WIRE_9_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_prio_1 = ~bypass_10 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_9_prio_2 = bypass_10 ? _view__WIRE_9_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_control = bypass_10 ? _view__WIRE_9_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_opcode = bypass_10 ? _view__WIRE_9_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_param = bypass_10 ? _view__WIRE_9_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_size = bypass_10 ? _view__WIRE_9_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_source = bypass_10 ? _view__WIRE_9_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_9_tag = bypass_10 ? _view__WIRE_9_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_offset = bypass_10 ? _view__WIRE_9_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_put = bypass_10 ? _view__WIRE_9_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_9_io_allocate_bits_repeat_T = mshrs_9_io_allocate_bits_tag == _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_9_io_allocate_valid_T = sel_9 & will_reload_10; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_11 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_11 = _requests_io_valid[22]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_92 = b_pop_11; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_11 = _requests_io_valid[34]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_89 = lowerMatches1[10]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_90 = c_pop_11 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_91 = ~c_pop_11; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_93 = ~b_pop_11; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_94 = ~a_pop_11; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_95 = _bypassMatches_T_92 ? _bypassMatches_T_93 : _bypassMatches_T_94; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_96 = _bypassMatches_T_90 ? _bypassMatches_T_91 : _bypassMatches_T_95; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_11 = _bypassMatches_T_89 & _bypassMatches_T_96; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_11 = a_pop_11 | b_pop_11; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_11 = _may_pop_T_11 | c_pop_11; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_11 = _bypass_T_11 & bypassMatches_11; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_11 = may_pop_11 | bypass_11; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_11 = _mshrs_10_io_schedule_bits_reload & _will_reload_T_11; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_10_prio_0 = bypass_11 ? _view__WIRE_10_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_prio_1 = ~bypass_11 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_10_prio_2 = bypass_11 ? _view__WIRE_10_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_control = bypass_11 ? _view__WIRE_10_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_opcode = bypass_11 ? _view__WIRE_10_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_param = bypass_11 ? _view__WIRE_10_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_size = bypass_11 ? _view__WIRE_10_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_source = bypass_11 ? _view__WIRE_10_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_10_tag = bypass_11 ? _view__WIRE_10_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_offset = bypass_11 ? _view__WIRE_10_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_put = bypass_11 ? _view__WIRE_10_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_10_io_allocate_bits_repeat_T = mshrs_10_io_allocate_bits_tag == _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74]
wire _mshrs_10_io_allocate_valid_T = sel_10 & will_reload_11; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_12 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_12 = _requests_io_valid[23]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_100 = b_pop_12; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_12 = _requests_io_valid[35]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_97 = lowerMatches1[11]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_98 = c_pop_12 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_99 = ~c_pop_12; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_101 = ~b_pop_12; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_102 = ~a_pop_12; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_103 = _bypassMatches_T_100 ? _bypassMatches_T_101 : _bypassMatches_T_102; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_104 = _bypassMatches_T_98 ? _bypassMatches_T_99 : _bypassMatches_T_103; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_12 = _bypassMatches_T_97 & _bypassMatches_T_104; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_12 = a_pop_12 | b_pop_12; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_12 = _may_pop_T_12 | c_pop_12; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_12 = _bypass_T_12 & bypassMatches_12; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_12 = may_pop_12 | bypass_12; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_12 = _mshrs_11_io_schedule_bits_reload & _will_reload_T_12; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_11_prio_0 = bypass_12 ? _view__WIRE_11_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_prio_1 = ~bypass_12 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_11_prio_2 = bypass_12 ? _view__WIRE_11_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_control = bypass_12 ? _view__WIRE_11_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_opcode = bypass_12 ? _view__WIRE_11_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_param = bypass_12 ? _view__WIRE_11_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_size = bypass_12 ? _view__WIRE_11_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_source = bypass_12 ? _view__WIRE_11_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_11_tag = bypass_12 ? _view__WIRE_11_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_offset = bypass_12 ? _view__WIRE_11_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_put = bypass_12 ? _view__WIRE_11_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_11_io_allocate_bits_repeat_T = mshrs_11_io_allocate_bits_tag == _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73]
wire _mshrs_11_io_allocate_valid_T = sel_11 & will_reload_12; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire [35:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25]
wire [23:0] _prio_requests_T_1 = _requests_io_valid[35:12]; // @[Scheduler.scala:70:24, :240:65]
wire [35:0] _prio_requests_T_2 = {_prio_requests_T[35:24], _prio_requests_T[23:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}]
wire [11:0] _prio_requests_T_3 = _requests_io_valid[35:24]; // @[Scheduler.scala:70:24, :240:103]
wire [35:0] _prio_requests_T_4 = {_prio_requests_T_2[35:12], _prio_requests_T_2[11:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}]
wire [35:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}]
wire [35:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31]
wire [35:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}]
wire [3:0] pop_index_hi_1 = _pop_index_T_1[35:32]; // @[OneHot.scala:30:18]
wire [31:0] pop_index_lo = _pop_index_T_1[31:0]; // @[OneHot.scala:31:18]
wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _pop_index_T_3 = {28'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] pop_index_hi_2 = _pop_index_T_3[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] pop_index_lo_1 = _pop_index_T_3[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] pop_index_hi_3 = _pop_index_T_5[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] pop_index_lo_2 = _pop_index_T_5[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] pop_index_hi_4 = _pop_index_T_7[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] pop_index_lo_3 = _pop_index_T_7[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] pop_index_hi_5 = _pop_index_T_9[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] pop_index_lo_4 = _pop_index_T_9[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_10 = |pop_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _pop_index_T_11 = pop_index_hi_5 | pop_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _pop_index_T_12 = _pop_index_T_11[1]; // @[OneHot.scala:32:28]
wire [1:0] _pop_index_T_13 = {_pop_index_T_10, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _pop_index_T_14 = {_pop_index_T_8, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _pop_index_T_15 = {_pop_index_T_6, _pop_index_T_14}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _pop_index_T_16 = {_pop_index_T_4, _pop_index_T_15}; // @[OneHot.scala:32:{10,14}]
wire [5:0] pop_index = {_pop_index_T_2, _pop_index_T_16}; // @[OneHot.scala:32:{10,14}]
wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73]
wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}]
wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45]
wire [8:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63]
wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73]
wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}]
wire [1:0] mshr_validOH_lo_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_lo = {mshr_validOH_lo_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_lo_hi_hi = {_mshrs_5_io_status_valid, _mshrs_4_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_hi = {mshr_validOH_lo_hi_hi, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_lo = {mshr_validOH_lo_hi, mshr_validOH_lo_lo}; // @[Scheduler.scala:252:25]
wire [1:0] mshr_validOH_hi_lo_hi = {_mshrs_8_io_status_valid, _mshrs_7_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_lo = {mshr_validOH_hi_lo_hi, _mshrs_6_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_hi_hi_hi = {_mshrs_11_io_status_valid, _mshrs_10_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_hi = {mshr_validOH_hi_hi_hi, _mshrs_9_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25]
wire [11:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25]
wire [11:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20]
wire [11:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}]
wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}]
wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73]
wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16]
wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}]
wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}]
wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}]
wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16]
wire _request_alloc_cases_T_5 = ~_mshrs_10_io_status_valid; // @[Scheduler.scala:71:46, :259:59]
wire _request_alloc_cases_T_7 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87]
wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16]
wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}]
wire _request_alloc_cases_T_12 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59]
wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}]
wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56]
wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66]
wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}]
assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}]
assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40]
wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44]
wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50]
wire [10:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73]
wire [8:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36]
wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55]
wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}]
wire [3:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[11:8]; // @[OneHot.scala:30:18]
wire [7:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[7:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_2 = {4'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_5 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_7 = _requests_io_push_bits_index_T_6[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_8 = {_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_9 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_10 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9}; // @[OneHot.scala:32:{10,14}]
wire [23:0] _requests_io_push_bits_index_T_11 = {lowerMatches1, 12'h0}; // @[Scheduler.scala:200:8, :275:30]
wire [7:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_11[23:16]; // @[OneHot.scala:30:18]
wire [15:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_11[15:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_12 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_13 = {8'h0, requests_io_push_bits_index_hi_3} | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_13[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_13[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_14 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_15 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_15[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_15[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_16 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_17 = requests_io_push_bits_index_hi_5 | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_17[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_17[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_18 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_19 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_20 = _requests_io_push_bits_index_T_19[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_21 = {_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_22 = {_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_23 = {_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_24 = {_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23}; // @[OneHot.scala:32:{10,14}]
wire [35:0] _requests_io_push_bits_index_T_25 = {lowerMatches1, 24'h0}; // @[Scheduler.scala:200:8, :276:30]
wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_25[35:32]; // @[OneHot.scala:30:18]
wire [31:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_25[31:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _requests_io_push_bits_index_T_27 = {28'h0, requests_io_push_bits_index_hi_7} | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_27[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_27[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_28 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_29 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_29[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_29[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_30 = |requests_io_push_bits_index_hi_9; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_31 = requests_io_push_bits_index_hi_9 | requests_io_push_bits_index_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_31[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_31[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_32 = |requests_io_push_bits_index_hi_10; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_33 = requests_io_push_bits_index_hi_10 | requests_io_push_bits_index_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_34 = |requests_io_push_bits_index_hi_11; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_11 | requests_io_push_bits_index_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_36 = _requests_io_push_bits_index_T_35[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_37 = {_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_38 = {_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_39 = {_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_40 = {_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39}; // @[OneHot.scala:32:{10,14}]
wire [5:0] _requests_io_push_bits_index_T_41 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_42 = request_bits_prio_0 ? _requests_io_push_bits_index_T_10 : 4'h0; // @[OneHot.scala:32:10]
wire [5:0] _requests_io_push_bits_index_T_44 = request_bits_prio_2 ? _requests_io_push_bits_index_T_41 : 6'h0; // @[OneHot.scala:32:10]
wire [4:0] _requests_io_push_bits_index_T_45 = {1'h0, _requests_io_push_bits_index_T_42}; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_T_46 = {1'h0, _requests_io_push_bits_index_T_45} | _requests_io_push_bits_index_T_44; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_46; // @[Mux.scala:30:73]
wire [11:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32]
wire [12:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48]
wire [11:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}]
wire [13:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}]
wire [15:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}]
wire [19:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_11 = _mshr_insertOH_T_10[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 | _mshr_insertOH_T_11; // @[package.scala:253:{43,53}]
wire [11:0] _mshr_insertOH_T_13 = _mshr_insertOH_T_12; // @[package.scala:253:43, :254:17]
wire [12:0] _mshr_insertOH_T_14 = {_mshr_insertOH_T_13, 1'h0}; // @[package.scala:254:17]
wire [12:0] _mshr_insertOH_T_15 = ~_mshr_insertOH_T_14; // @[Scheduler.scala:278:{23,47}]
wire [11:0] _mshr_insertOH_T_16 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55]
wire [12:0] _mshr_insertOH_T_17 = {1'h0, _mshr_insertOH_T_15[11:0] & _mshr_insertOH_T_16}; // @[Scheduler.scala:278:{23,53,55}]
wire [12:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_17[11:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}]
wire _T_76 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25]
wire _T_35 = _T_76 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_0_io_allocate_bits_tag = _T_35 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_39 = _T_76 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_1_io_allocate_bits_tag = _T_39 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_43 = _T_76 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_2_io_allocate_bits_tag = _T_43 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_47 = _T_76 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_3_io_allocate_bits_tag = _T_47 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_51 = _T_76 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_4_io_allocate_bits_tag = _T_51 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_55 = _T_76 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_5_io_allocate_bits_tag = _T_55 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_59 = _T_76 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_6_io_allocate_bits_tag = _T_59 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_63 = _T_76 & mshr_insertOH[7] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_7_io_allocate_bits_tag = _T_63 ? request_bits_tag : _view__T_7_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_67 = _T_76 & mshr_insertOH[8] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_8_io_allocate_bits_tag = _T_67 ? request_bits_tag : _view__T_8_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_71 = _T_76 & mshr_insertOH[9] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_9_io_allocate_bits_tag = _T_71 ? request_bits_tag : _view__T_9_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_75 = _T_76 & mshr_insertOH[10] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_10_io_allocate_bits_tag = _T_75 ? request_bits_tag : _view__T_10_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74]
wire _T_95 = request_valid & nestC & ~_mshrs_11_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}]
wire _GEN_3 = _T_95 | _T_76 & mshr_insertOH[11] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30]
assign mshrs_11_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_11_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_8 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_264
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_8( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_264 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLROM :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_111
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect nodeIn, auto.in
wire rom : UInt<64>[2048]
connect rom[0], UInt<64>(0h405051300000517)
connect rom[1], UInt<64>(0h301022f330551073)
connect rom[2], UInt<64>(0h12f2934122d293)
connect rom[3], UInt<64>(0h3030107300028863)
connect rom[4], UInt<64>(0h3445307322200513)
connect rom[5], UInt<64>(0h3045107300800513)
connect rom[6], UInt<64>(0h1050007330052073)
connect rom[7], UInt<64>(0hffdff06f)
connect rom[8], UInt<64>(0hf1402573020005b7)
connect rom[9], UInt<64>(0h380006f00050463)
connect rom[10], UInt<64>(0h10069300458613)
connect rom[11], UInt<64>(0h46061300d62023)
connect rom[12], UInt<64>(0hfe069ae3ffc62683)
connect rom[13], UInt<64>(0h2c0006f)
connect rom[14], UInt<64>(0h0)
connect rom[15], UInt<64>(0h0)
connect rom[16], UInt<64>(0h5a283f81ff06f)
connect rom[17], UInt<64>(0h251513fe029ee3)
connect rom[18], UInt<64>(0h5a02300b505b3)
connect rom[19], UInt<64>(0h5350300001537)
connect rom[20], UInt<64>(0hf140257334151073)
connect rom[21], UInt<64>(0h185859300000597)
connect rom[22], UInt<64>(0h3006307308000613)
connect rom[23], UInt<64>(0h1330200073)
connect rom[24], UInt<64>(0h30280000edfe0dd0)
connect rom[25], UInt<64>(0hd025000038000000)
connect rom[26], UInt<64>(0h1100000028000000)
connect rom[27], UInt<64>(0h10000000)
connect rom[28], UInt<64>(0h9825000060020000)
connect rom[29], UInt<64>(0h0)
connect rom[30], UInt<64>(0h0)
connect rom[31], UInt<64>(0h1000000)
connect rom[32], UInt<64>(0h400000003000000)
connect rom[33], UInt<64>(0h100000000000000)
connect rom[34], UInt<64>(0h400000003000000)
connect rom[35], UInt<64>(0h10000000f000000)
connect rom[36], UInt<64>(0h1500000003000000)
connect rom[37], UInt<64>(0h2d6263751b000000)
connect rom[38], UInt<64>(0h706968632c726162)
connect rom[39], UInt<64>(0h7665642d64726179)
connect rom[40], UInt<64>(0h300000000000000)
connect rom[41], UInt<64>(0h2600000011000000)
connect rom[42], UInt<64>(0h2c7261622d626375)
connect rom[43], UInt<64>(0h6472617970696863)
connect rom[44], UInt<64>(0h100000000000000)
connect rom[45], UInt<64>(0h73657361696c61)
connect rom[46], UInt<64>(0h1500000003000000)
connect rom[47], UInt<64>(0h636f732f2c000000)
connect rom[48], UInt<64>(0h406c61697265732f)
connect rom[49], UInt<64>(0h3030303032303031)
connect rom[50], UInt<64>(0h200000000000000)
connect rom[51], UInt<64>(0h736f686301000000)
connect rom[52], UInt<64>(0h300000000006e65)
connect rom[53], UInt<64>(0h3400000015000000)
connect rom[54], UInt<64>(0h7265732f636f732f)
connect rom[55], UInt<64>(0h32303031406c6169)
connect rom[56], UInt<64>(0h30303030)
connect rom[57], UInt<64>(0h100000002000000)
connect rom[58], UInt<64>(0h73757063)
connect rom[59], UInt<64>(0h400000003000000)
connect rom[60], UInt<64>(0h100000000000000)
connect rom[61], UInt<64>(0h400000003000000)
connect rom[62], UInt<64>(0hf000000)
connect rom[63], UInt<64>(0h400000003000000)
connect rom[64], UInt<64>(0h20a1070040000000)
connect rom[65], UInt<64>(0h4075706301000000)
connect rom[66], UInt<64>(0h300000000000030)
connect rom[67], UInt<64>(0h5300000004000000)
connect rom[68], UInt<64>(0h300000000000000)
connect rom[69], UInt<64>(0h1b00000015000000)
connect rom[70], UInt<64>(0h722c657669666973)
connect rom[71], UInt<64>(0h72003074656b636f)
connect rom[72], UInt<64>(0h76637369)
connect rom[73], UInt<64>(0h400000003000000)
connect rom[74], UInt<64>(0h4000000063000000)
connect rom[75], UInt<64>(0h400000003000000)
connect rom[76], UInt<64>(0h4000000076000000)
connect rom[77], UInt<64>(0h400000003000000)
connect rom[78], UInt<64>(0h80000083000000)
connect rom[79], UInt<64>(0h400000003000000)
connect rom[80], UInt<64>(0h100000090000000)
connect rom[81], UInt<64>(0h400000003000000)
connect rom[82], UInt<64>(0h200000009b000000)
connect rom[83], UInt<64>(0h400000003000000)
connect rom[84], UInt<64>(0h757063a6000000)
connect rom[85], UInt<64>(0h400000003000000)
connect rom[86], UInt<64>(0h1000000b2000000)
connect rom[87], UInt<64>(0h400000003000000)
connect rom[88], UInt<64>(0h40000000d1000000)
connect rom[89], UInt<64>(0h400000003000000)
connect rom[90], UInt<64>(0h40000000e4000000)
connect rom[91], UInt<64>(0h400000003000000)
connect rom[92], UInt<64>(0h800000f1000000)
connect rom[93], UInt<64>(0h400000003000000)
connect rom[94], UInt<64>(0h1000000fe000000)
connect rom[95], UInt<64>(0h400000003000000)
connect rom[96], UInt<64>(0h2000000009010000)
connect rom[97], UInt<64>(0hb00000003000000)
connect rom[98], UInt<64>(0h6373697214010000)
connect rom[99], UInt<64>(0h393376732c76)
connect rom[100], UInt<64>(0h400000003000000)
connect rom[101], UInt<64>(0h10000001d010000)
connect rom[102], UInt<64>(0h400000003000000)
connect rom[103], UInt<64>(0h2e010000)
connect rom[104], UInt<64>(0h3800000003000000)
connect rom[105], UInt<64>(0h3436767232010000)
connect rom[106], UInt<64>(0h7a62636466616d69)
connect rom[107], UInt<64>(0h66697a5f72736369)
connect rom[108], UInt<64>(0h697a5f6965636e65)
connect rom[109], UInt<64>(0h5f68667a5f6d7068)
connect rom[110], UInt<64>(0h5f62627a5f61627a)
connect rom[111], UInt<64>(0h636f72785f73627a)
connect rom[112], UInt<64>(0h30000000074656b)
connect rom[113], UInt<64>(0h3c01000004000000)
connect rom[114], UInt<64>(0h300000004000000)
connect rom[115], UInt<64>(0h5101000004000000)
connect rom[116], UInt<64>(0h300000008000000)
connect rom[117], UInt<64>(0h6201000005000000)
connect rom[118], UInt<64>(0h79616b6f)
connect rom[119], UInt<64>(0h400000003000000)
connect rom[120], UInt<64>(0h20a1070040000000)
connect rom[121], UInt<64>(0h3000000)
connect rom[122], UInt<64>(0h100000069010000)
connect rom[123], UInt<64>(0h7075727265746e69)
connect rom[124], UInt<64>(0h6f72746e6f632d74)
connect rom[125], UInt<64>(0h72656c6c)
connect rom[126], UInt<64>(0h400000003000000)
connect rom[127], UInt<64>(0h100000073010000)
connect rom[128], UInt<64>(0hf00000003000000)
connect rom[129], UInt<64>(0h637369721b000000)
connect rom[130], UInt<64>(0h6e692d7570632c76)
connect rom[131], UInt<64>(0h300000000006374)
connect rom[132], UInt<64>(0h8401000000000000)
connect rom[133], UInt<64>(0h400000003000000)
connect rom[134], UInt<64>(0h400000099010000)
connect rom[135], UInt<64>(0h200000002000000)
connect rom[136], UInt<64>(0h4075706301000000)
connect rom[137], UInt<64>(0h300000000000031)
connect rom[138], UInt<64>(0h5300000004000000)
connect rom[139], UInt<64>(0h300000000000000)
connect rom[140], UInt<64>(0h1b00000015000000)
connect rom[141], UInt<64>(0h722c657669666973)
connect rom[142], UInt<64>(0h72003074656b636f)
connect rom[143], UInt<64>(0h76637369)
connect rom[144], UInt<64>(0h400000003000000)
connect rom[145], UInt<64>(0h4000000063000000)
connect rom[146], UInt<64>(0h400000003000000)
connect rom[147], UInt<64>(0h4000000076000000)
connect rom[148], UInt<64>(0h400000003000000)
connect rom[149], UInt<64>(0h80000083000000)
connect rom[150], UInt<64>(0h400000003000000)
connect rom[151], UInt<64>(0h100000090000000)
connect rom[152], UInt<64>(0h400000003000000)
connect rom[153], UInt<64>(0h200000009b000000)
connect rom[154], UInt<64>(0h400000003000000)
connect rom[155], UInt<64>(0h757063a6000000)
connect rom[156], UInt<64>(0h400000003000000)
connect rom[157], UInt<64>(0h1000000b2000000)
connect rom[158], UInt<64>(0h400000003000000)
connect rom[159], UInt<64>(0h40000000d1000000)
connect rom[160], UInt<64>(0h400000003000000)
connect rom[161], UInt<64>(0h40000000e4000000)
connect rom[162], UInt<64>(0h400000003000000)
connect rom[163], UInt<64>(0h800000f1000000)
connect rom[164], UInt<64>(0h400000003000000)
connect rom[165], UInt<64>(0h1000000fe000000)
connect rom[166], UInt<64>(0h400000003000000)
connect rom[167], UInt<64>(0h2000000009010000)
connect rom[168], UInt<64>(0hb00000003000000)
connect rom[169], UInt<64>(0h6373697214010000)
connect rom[170], UInt<64>(0h393376732c76)
connect rom[171], UInt<64>(0h400000003000000)
connect rom[172], UInt<64>(0h10000001d010000)
connect rom[173], UInt<64>(0h400000003000000)
connect rom[174], UInt<64>(0h10000002e010000)
connect rom[175], UInt<64>(0h3800000003000000)
connect rom[176], UInt<64>(0h3436767232010000)
connect rom[177], UInt<64>(0h7a62636466616d69)
connect rom[178], UInt<64>(0h66697a5f72736369)
connect rom[179], UInt<64>(0h697a5f6965636e65)
connect rom[180], UInt<64>(0h5f68667a5f6d7068)
connect rom[181], UInt<64>(0h5f62627a5f61627a)
connect rom[182], UInt<64>(0h636f72785f73627a)
connect rom[183], UInt<64>(0h30000000074656b)
connect rom[184], UInt<64>(0h3c01000004000000)
connect rom[185], UInt<64>(0h300000004000000)
connect rom[186], UInt<64>(0h5101000004000000)
connect rom[187], UInt<64>(0h300000008000000)
connect rom[188], UInt<64>(0h6201000005000000)
connect rom[189], UInt<64>(0h79616b6f)
connect rom[190], UInt<64>(0h400000003000000)
connect rom[191], UInt<64>(0h20a1070040000000)
connect rom[192], UInt<64>(0h3000000)
connect rom[193], UInt<64>(0h100000069010000)
connect rom[194], UInt<64>(0h7075727265746e69)
connect rom[195], UInt<64>(0h6f72746e6f632d74)
connect rom[196], UInt<64>(0h72656c6c)
connect rom[197], UInt<64>(0h400000003000000)
connect rom[198], UInt<64>(0h100000073010000)
connect rom[199], UInt<64>(0hf00000003000000)
connect rom[200], UInt<64>(0h637369721b000000)
connect rom[201], UInt<64>(0h6e692d7570632c76)
connect rom[202], UInt<64>(0h300000000006374)
connect rom[203], UInt<64>(0h8401000000000000)
connect rom[204], UInt<64>(0h400000003000000)
connect rom[205], UInt<64>(0h500000099010000)
connect rom[206], UInt<64>(0h200000002000000)
connect rom[207], UInt<64>(0h4075706301000000)
connect rom[208], UInt<64>(0h300000000000032)
connect rom[209], UInt<64>(0h5300000004000000)
connect rom[210], UInt<64>(0h300000000000000)
connect rom[211], UInt<64>(0h1b00000015000000)
connect rom[212], UInt<64>(0h722c657669666973)
connect rom[213], UInt<64>(0h72003074656b636f)
connect rom[214], UInt<64>(0h76637369)
connect rom[215], UInt<64>(0h400000003000000)
connect rom[216], UInt<64>(0h4000000063000000)
connect rom[217], UInt<64>(0h400000003000000)
connect rom[218], UInt<64>(0h4000000076000000)
connect rom[219], UInt<64>(0h400000003000000)
connect rom[220], UInt<64>(0h80000083000000)
connect rom[221], UInt<64>(0h400000003000000)
connect rom[222], UInt<64>(0h100000090000000)
connect rom[223], UInt<64>(0h400000003000000)
connect rom[224], UInt<64>(0h200000009b000000)
connect rom[225], UInt<64>(0h400000003000000)
connect rom[226], UInt<64>(0h757063a6000000)
connect rom[227], UInt<64>(0h400000003000000)
connect rom[228], UInt<64>(0h1000000b2000000)
connect rom[229], UInt<64>(0h400000003000000)
connect rom[230], UInt<64>(0h40000000d1000000)
connect rom[231], UInt<64>(0h400000003000000)
connect rom[232], UInt<64>(0h40000000e4000000)
connect rom[233], UInt<64>(0h400000003000000)
connect rom[234], UInt<64>(0h800000f1000000)
connect rom[235], UInt<64>(0h400000003000000)
connect rom[236], UInt<64>(0h1000000fe000000)
connect rom[237], UInt<64>(0h400000003000000)
connect rom[238], UInt<64>(0h2000000009010000)
connect rom[239], UInt<64>(0hb00000003000000)
connect rom[240], UInt<64>(0h6373697214010000)
connect rom[241], UInt<64>(0h393376732c76)
connect rom[242], UInt<64>(0h400000003000000)
connect rom[243], UInt<64>(0h10000001d010000)
connect rom[244], UInt<64>(0h400000003000000)
connect rom[245], UInt<64>(0h20000002e010000)
connect rom[246], UInt<64>(0h3800000003000000)
connect rom[247], UInt<64>(0h3436767232010000)
connect rom[248], UInt<64>(0h7a62636466616d69)
connect rom[249], UInt<64>(0h66697a5f72736369)
connect rom[250], UInt<64>(0h697a5f6965636e65)
connect rom[251], UInt<64>(0h5f68667a5f6d7068)
connect rom[252], UInt<64>(0h5f62627a5f61627a)
connect rom[253], UInt<64>(0h636f72785f73627a)
connect rom[254], UInt<64>(0h30000000074656b)
connect rom[255], UInt<64>(0h3c01000004000000)
connect rom[256], UInt<64>(0h300000004000000)
connect rom[257], UInt<64>(0h5101000004000000)
connect rom[258], UInt<64>(0h300000008000000)
connect rom[259], UInt<64>(0h6201000005000000)
connect rom[260], UInt<64>(0h79616b6f)
connect rom[261], UInt<64>(0h400000003000000)
connect rom[262], UInt<64>(0h20a1070040000000)
connect rom[263], UInt<64>(0h3000000)
connect rom[264], UInt<64>(0h100000069010000)
connect rom[265], UInt<64>(0h7075727265746e69)
connect rom[266], UInt<64>(0h6f72746e6f632d74)
connect rom[267], UInt<64>(0h72656c6c)
connect rom[268], UInt<64>(0h400000003000000)
connect rom[269], UInt<64>(0h100000073010000)
connect rom[270], UInt<64>(0hf00000003000000)
connect rom[271], UInt<64>(0h637369721b000000)
connect rom[272], UInt<64>(0h6e692d7570632c76)
connect rom[273], UInt<64>(0h300000000006374)
connect rom[274], UInt<64>(0h8401000000000000)
connect rom[275], UInt<64>(0h400000003000000)
connect rom[276], UInt<64>(0h600000099010000)
connect rom[277], UInt<64>(0h200000002000000)
connect rom[278], UInt<64>(0h4075706301000000)
connect rom[279], UInt<64>(0h300000000000033)
connect rom[280], UInt<64>(0h5300000004000000)
connect rom[281], UInt<64>(0h300000000000000)
connect rom[282], UInt<64>(0h1b00000015000000)
connect rom[283], UInt<64>(0h722c657669666973)
connect rom[284], UInt<64>(0h72003074656b636f)
connect rom[285], UInt<64>(0h76637369)
connect rom[286], UInt<64>(0h400000003000000)
connect rom[287], UInt<64>(0h4000000063000000)
connect rom[288], UInt<64>(0h400000003000000)
connect rom[289], UInt<64>(0h4000000076000000)
connect rom[290], UInt<64>(0h400000003000000)
connect rom[291], UInt<64>(0h80000083000000)
connect rom[292], UInt<64>(0h400000003000000)
connect rom[293], UInt<64>(0h100000090000000)
connect rom[294], UInt<64>(0h400000003000000)
connect rom[295], UInt<64>(0h200000009b000000)
connect rom[296], UInt<64>(0h400000003000000)
connect rom[297], UInt<64>(0h757063a6000000)
connect rom[298], UInt<64>(0h400000003000000)
connect rom[299], UInt<64>(0h1000000b2000000)
connect rom[300], UInt<64>(0h400000003000000)
connect rom[301], UInt<64>(0h40000000d1000000)
connect rom[302], UInt<64>(0h400000003000000)
connect rom[303], UInt<64>(0h40000000e4000000)
connect rom[304], UInt<64>(0h400000003000000)
connect rom[305], UInt<64>(0h800000f1000000)
connect rom[306], UInt<64>(0h400000003000000)
connect rom[307], UInt<64>(0h1000000fe000000)
connect rom[308], UInt<64>(0h400000003000000)
connect rom[309], UInt<64>(0h2000000009010000)
connect rom[310], UInt<64>(0hb00000003000000)
connect rom[311], UInt<64>(0h6373697214010000)
connect rom[312], UInt<64>(0h393376732c76)
connect rom[313], UInt<64>(0h400000003000000)
connect rom[314], UInt<64>(0h10000001d010000)
connect rom[315], UInt<64>(0h400000003000000)
connect rom[316], UInt<64>(0h30000002e010000)
connect rom[317], UInt<64>(0h3800000003000000)
connect rom[318], UInt<64>(0h3436767232010000)
connect rom[319], UInt<64>(0h7a62636466616d69)
connect rom[320], UInt<64>(0h66697a5f72736369)
connect rom[321], UInt<64>(0h697a5f6965636e65)
connect rom[322], UInt<64>(0h5f68667a5f6d7068)
connect rom[323], UInt<64>(0h5f62627a5f61627a)
connect rom[324], UInt<64>(0h636f72785f73627a)
connect rom[325], UInt<64>(0h30000000074656b)
connect rom[326], UInt<64>(0h3c01000004000000)
connect rom[327], UInt<64>(0h300000004000000)
connect rom[328], UInt<64>(0h5101000004000000)
connect rom[329], UInt<64>(0h300000008000000)
connect rom[330], UInt<64>(0h6201000005000000)
connect rom[331], UInt<64>(0h79616b6f)
connect rom[332], UInt<64>(0h400000003000000)
connect rom[333], UInt<64>(0h20a1070040000000)
connect rom[334], UInt<64>(0h3000000)
connect rom[335], UInt<64>(0h100000069010000)
connect rom[336], UInt<64>(0h7075727265746e69)
connect rom[337], UInt<64>(0h6f72746e6f632d74)
connect rom[338], UInt<64>(0h72656c6c)
connect rom[339], UInt<64>(0h400000003000000)
connect rom[340], UInt<64>(0h100000073010000)
connect rom[341], UInt<64>(0hf00000003000000)
connect rom[342], UInt<64>(0h637369721b000000)
connect rom[343], UInt<64>(0h6e692d7570632c76)
connect rom[344], UInt<64>(0h300000000006374)
connect rom[345], UInt<64>(0h8401000000000000)
connect rom[346], UInt<64>(0h400000003000000)
connect rom[347], UInt<64>(0h700000099010000)
connect rom[348], UInt<64>(0h200000002000000)
connect rom[349], UInt<64>(0h4075706301000000)
connect rom[350], UInt<64>(0h300000000000034)
connect rom[351], UInt<64>(0h5300000004000000)
connect rom[352], UInt<64>(0h300000000000000)
connect rom[353], UInt<64>(0h1b00000015000000)
connect rom[354], UInt<64>(0h722c657669666973)
connect rom[355], UInt<64>(0h72003074656b636f)
connect rom[356], UInt<64>(0h76637369)
connect rom[357], UInt<64>(0h400000003000000)
connect rom[358], UInt<64>(0h4000000063000000)
connect rom[359], UInt<64>(0h400000003000000)
connect rom[360], UInt<64>(0h4000000076000000)
connect rom[361], UInt<64>(0h400000003000000)
connect rom[362], UInt<64>(0h80000083000000)
connect rom[363], UInt<64>(0h400000003000000)
connect rom[364], UInt<64>(0h100000090000000)
connect rom[365], UInt<64>(0h400000003000000)
connect rom[366], UInt<64>(0h200000009b000000)
connect rom[367], UInt<64>(0h400000003000000)
connect rom[368], UInt<64>(0h757063a6000000)
connect rom[369], UInt<64>(0h400000003000000)
connect rom[370], UInt<64>(0h1000000b2000000)
connect rom[371], UInt<64>(0h400000003000000)
connect rom[372], UInt<64>(0h40000000d1000000)
connect rom[373], UInt<64>(0h400000003000000)
connect rom[374], UInt<64>(0h40000000e4000000)
connect rom[375], UInt<64>(0h400000003000000)
connect rom[376], UInt<64>(0h800000f1000000)
connect rom[377], UInt<64>(0h400000003000000)
connect rom[378], UInt<64>(0h1000000fe000000)
connect rom[379], UInt<64>(0h400000003000000)
connect rom[380], UInt<64>(0h2000000009010000)
connect rom[381], UInt<64>(0hb00000003000000)
connect rom[382], UInt<64>(0h6373697214010000)
connect rom[383], UInt<64>(0h393376732c76)
connect rom[384], UInt<64>(0h400000003000000)
connect rom[385], UInt<64>(0h10000001d010000)
connect rom[386], UInt<64>(0h400000003000000)
connect rom[387], UInt<64>(0h40000002e010000)
connect rom[388], UInt<64>(0h3800000003000000)
connect rom[389], UInt<64>(0h3436767232010000)
connect rom[390], UInt<64>(0h7a62636466616d69)
connect rom[391], UInt<64>(0h66697a5f72736369)
connect rom[392], UInt<64>(0h697a5f6965636e65)
connect rom[393], UInt<64>(0h5f68667a5f6d7068)
connect rom[394], UInt<64>(0h5f62627a5f61627a)
connect rom[395], UInt<64>(0h636f72785f73627a)
connect rom[396], UInt<64>(0h30000000074656b)
connect rom[397], UInt<64>(0h3c01000004000000)
connect rom[398], UInt<64>(0h300000004000000)
connect rom[399], UInt<64>(0h5101000004000000)
connect rom[400], UInt<64>(0h300000008000000)
connect rom[401], UInt<64>(0h6201000005000000)
connect rom[402], UInt<64>(0h79616b6f)
connect rom[403], UInt<64>(0h400000003000000)
connect rom[404], UInt<64>(0h20a1070040000000)
connect rom[405], UInt<64>(0h3000000)
connect rom[406], UInt<64>(0h100000069010000)
connect rom[407], UInt<64>(0h7075727265746e69)
connect rom[408], UInt<64>(0h6f72746e6f632d74)
connect rom[409], UInt<64>(0h72656c6c)
connect rom[410], UInt<64>(0h400000003000000)
connect rom[411], UInt<64>(0h100000073010000)
connect rom[412], UInt<64>(0hf00000003000000)
connect rom[413], UInt<64>(0h637369721b000000)
connect rom[414], UInt<64>(0h6e692d7570632c76)
connect rom[415], UInt<64>(0h300000000006374)
connect rom[416], UInt<64>(0h8401000000000000)
connect rom[417], UInt<64>(0h400000003000000)
connect rom[418], UInt<64>(0h800000099010000)
connect rom[419], UInt<64>(0h200000002000000)
connect rom[420], UInt<64>(0h4075706301000000)
connect rom[421], UInt<64>(0h300000000000035)
connect rom[422], UInt<64>(0h5300000004000000)
connect rom[423], UInt<64>(0h300000000000000)
connect rom[424], UInt<64>(0h1b00000015000000)
connect rom[425], UInt<64>(0h722c657669666973)
connect rom[426], UInt<64>(0h72003074656b636f)
connect rom[427], UInt<64>(0h76637369)
connect rom[428], UInt<64>(0h400000003000000)
connect rom[429], UInt<64>(0h4000000063000000)
connect rom[430], UInt<64>(0h400000003000000)
connect rom[431], UInt<64>(0h4000000076000000)
connect rom[432], UInt<64>(0h400000003000000)
connect rom[433], UInt<64>(0h80000083000000)
connect rom[434], UInt<64>(0h400000003000000)
connect rom[435], UInt<64>(0h100000090000000)
connect rom[436], UInt<64>(0h400000003000000)
connect rom[437], UInt<64>(0h200000009b000000)
connect rom[438], UInt<64>(0h400000003000000)
connect rom[439], UInt<64>(0h757063a6000000)
connect rom[440], UInt<64>(0h400000003000000)
connect rom[441], UInt<64>(0h1000000b2000000)
connect rom[442], UInt<64>(0h400000003000000)
connect rom[443], UInt<64>(0h40000000d1000000)
connect rom[444], UInt<64>(0h400000003000000)
connect rom[445], UInt<64>(0h40000000e4000000)
connect rom[446], UInt<64>(0h400000003000000)
connect rom[447], UInt<64>(0h800000f1000000)
connect rom[448], UInt<64>(0h400000003000000)
connect rom[449], UInt<64>(0h1000000fe000000)
connect rom[450], UInt<64>(0h400000003000000)
connect rom[451], UInt<64>(0h2000000009010000)
connect rom[452], UInt<64>(0hb00000003000000)
connect rom[453], UInt<64>(0h6373697214010000)
connect rom[454], UInt<64>(0h393376732c76)
connect rom[455], UInt<64>(0h400000003000000)
connect rom[456], UInt<64>(0h10000001d010000)
connect rom[457], UInt<64>(0h400000003000000)
connect rom[458], UInt<64>(0h50000002e010000)
connect rom[459], UInt<64>(0h3800000003000000)
connect rom[460], UInt<64>(0h3436767232010000)
connect rom[461], UInt<64>(0h7a62636466616d69)
connect rom[462], UInt<64>(0h66697a5f72736369)
connect rom[463], UInt<64>(0h697a5f6965636e65)
connect rom[464], UInt<64>(0h5f68667a5f6d7068)
connect rom[465], UInt<64>(0h5f62627a5f61627a)
connect rom[466], UInt<64>(0h636f72785f73627a)
connect rom[467], UInt<64>(0h30000000074656b)
connect rom[468], UInt<64>(0h3c01000004000000)
connect rom[469], UInt<64>(0h300000004000000)
connect rom[470], UInt<64>(0h5101000004000000)
connect rom[471], UInt<64>(0h300000008000000)
connect rom[472], UInt<64>(0h6201000005000000)
connect rom[473], UInt<64>(0h79616b6f)
connect rom[474], UInt<64>(0h400000003000000)
connect rom[475], UInt<64>(0h20a1070040000000)
connect rom[476], UInt<64>(0h3000000)
connect rom[477], UInt<64>(0h100000069010000)
connect rom[478], UInt<64>(0h7075727265746e69)
connect rom[479], UInt<64>(0h6f72746e6f632d74)
connect rom[480], UInt<64>(0h72656c6c)
connect rom[481], UInt<64>(0h400000003000000)
connect rom[482], UInt<64>(0h100000073010000)
connect rom[483], UInt<64>(0hf00000003000000)
connect rom[484], UInt<64>(0h637369721b000000)
connect rom[485], UInt<64>(0h6e692d7570632c76)
connect rom[486], UInt<64>(0h300000000006374)
connect rom[487], UInt<64>(0h8401000000000000)
connect rom[488], UInt<64>(0h400000003000000)
connect rom[489], UInt<64>(0h900000099010000)
connect rom[490], UInt<64>(0h200000002000000)
connect rom[491], UInt<64>(0h4075706301000000)
connect rom[492], UInt<64>(0h300000000000036)
connect rom[493], UInt<64>(0h5300000004000000)
connect rom[494], UInt<64>(0h300000000000000)
connect rom[495], UInt<64>(0h1b00000015000000)
connect rom[496], UInt<64>(0h722c657669666973)
connect rom[497], UInt<64>(0h72003074656b636f)
connect rom[498], UInt<64>(0h76637369)
connect rom[499], UInt<64>(0h400000003000000)
connect rom[500], UInt<64>(0h4000000063000000)
connect rom[501], UInt<64>(0h400000003000000)
connect rom[502], UInt<64>(0h4000000076000000)
connect rom[503], UInt<64>(0h400000003000000)
connect rom[504], UInt<64>(0h80000083000000)
connect rom[505], UInt<64>(0h400000003000000)
connect rom[506], UInt<64>(0h100000090000000)
connect rom[507], UInt<64>(0h400000003000000)
connect rom[508], UInt<64>(0h200000009b000000)
connect rom[509], UInt<64>(0h400000003000000)
connect rom[510], UInt<64>(0h757063a6000000)
connect rom[511], UInt<64>(0h400000003000000)
connect rom[512], UInt<64>(0h1000000b2000000)
connect rom[513], UInt<64>(0h400000003000000)
connect rom[514], UInt<64>(0h40000000d1000000)
connect rom[515], UInt<64>(0h400000003000000)
connect rom[516], UInt<64>(0h40000000e4000000)
connect rom[517], UInt<64>(0h400000003000000)
connect rom[518], UInt<64>(0h800000f1000000)
connect rom[519], UInt<64>(0h400000003000000)
connect rom[520], UInt<64>(0h1000000fe000000)
connect rom[521], UInt<64>(0h400000003000000)
connect rom[522], UInt<64>(0h2000000009010000)
connect rom[523], UInt<64>(0hb00000003000000)
connect rom[524], UInt<64>(0h6373697214010000)
connect rom[525], UInt<64>(0h393376732c76)
connect rom[526], UInt<64>(0h400000003000000)
connect rom[527], UInt<64>(0h10000001d010000)
connect rom[528], UInt<64>(0h400000003000000)
connect rom[529], UInt<64>(0h60000002e010000)
connect rom[530], UInt<64>(0h3800000003000000)
connect rom[531], UInt<64>(0h3436767232010000)
connect rom[532], UInt<64>(0h7a62636466616d69)
connect rom[533], UInt<64>(0h66697a5f72736369)
connect rom[534], UInt<64>(0h697a5f6965636e65)
connect rom[535], UInt<64>(0h5f68667a5f6d7068)
connect rom[536], UInt<64>(0h5f62627a5f61627a)
connect rom[537], UInt<64>(0h636f72785f73627a)
connect rom[538], UInt<64>(0h30000000074656b)
connect rom[539], UInt<64>(0h3c01000004000000)
connect rom[540], UInt<64>(0h300000004000000)
connect rom[541], UInt<64>(0h5101000004000000)
connect rom[542], UInt<64>(0h300000008000000)
connect rom[543], UInt<64>(0h6201000005000000)
connect rom[544], UInt<64>(0h79616b6f)
connect rom[545], UInt<64>(0h400000003000000)
connect rom[546], UInt<64>(0h20a1070040000000)
connect rom[547], UInt<64>(0h3000000)
connect rom[548], UInt<64>(0h100000069010000)
connect rom[549], UInt<64>(0h7075727265746e69)
connect rom[550], UInt<64>(0h6f72746e6f632d74)
connect rom[551], UInt<64>(0h72656c6c)
connect rom[552], UInt<64>(0h400000003000000)
connect rom[553], UInt<64>(0h100000073010000)
connect rom[554], UInt<64>(0hf00000003000000)
connect rom[555], UInt<64>(0h637369721b000000)
connect rom[556], UInt<64>(0h6e692d7570632c76)
connect rom[557], UInt<64>(0h300000000006374)
connect rom[558], UInt<64>(0h8401000000000000)
connect rom[559], UInt<64>(0h400000003000000)
connect rom[560], UInt<64>(0ha00000099010000)
connect rom[561], UInt<64>(0h200000002000000)
connect rom[562], UInt<64>(0h4075706301000000)
connect rom[563], UInt<64>(0h300000000000037)
connect rom[564], UInt<64>(0h5300000004000000)
connect rom[565], UInt<64>(0h300000000000000)
connect rom[566], UInt<64>(0h1b00000015000000)
connect rom[567], UInt<64>(0h722c657669666973)
connect rom[568], UInt<64>(0h72003074656b636f)
connect rom[569], UInt<64>(0h76637369)
connect rom[570], UInt<64>(0h400000003000000)
connect rom[571], UInt<64>(0h4000000063000000)
connect rom[572], UInt<64>(0h400000003000000)
connect rom[573], UInt<64>(0h4000000076000000)
connect rom[574], UInt<64>(0h400000003000000)
connect rom[575], UInt<64>(0h80000083000000)
connect rom[576], UInt<64>(0h400000003000000)
connect rom[577], UInt<64>(0h100000090000000)
connect rom[578], UInt<64>(0h400000003000000)
connect rom[579], UInt<64>(0h200000009b000000)
connect rom[580], UInt<64>(0h400000003000000)
connect rom[581], UInt<64>(0h757063a6000000)
connect rom[582], UInt<64>(0h400000003000000)
connect rom[583], UInt<64>(0h1000000b2000000)
connect rom[584], UInt<64>(0h400000003000000)
connect rom[585], UInt<64>(0h40000000d1000000)
connect rom[586], UInt<64>(0h400000003000000)
connect rom[587], UInt<64>(0h40000000e4000000)
connect rom[588], UInt<64>(0h400000003000000)
connect rom[589], UInt<64>(0h800000f1000000)
connect rom[590], UInt<64>(0h400000003000000)
connect rom[591], UInt<64>(0h1000000fe000000)
connect rom[592], UInt<64>(0h400000003000000)
connect rom[593], UInt<64>(0h2000000009010000)
connect rom[594], UInt<64>(0hb00000003000000)
connect rom[595], UInt<64>(0h6373697214010000)
connect rom[596], UInt<64>(0h393376732c76)
connect rom[597], UInt<64>(0h400000003000000)
connect rom[598], UInt<64>(0h10000001d010000)
connect rom[599], UInt<64>(0h400000003000000)
connect rom[600], UInt<64>(0h70000002e010000)
connect rom[601], UInt<64>(0h3800000003000000)
connect rom[602], UInt<64>(0h3436767232010000)
connect rom[603], UInt<64>(0h7a62636466616d69)
connect rom[604], UInt<64>(0h66697a5f72736369)
connect rom[605], UInt<64>(0h697a5f6965636e65)
connect rom[606], UInt<64>(0h5f68667a5f6d7068)
connect rom[607], UInt<64>(0h5f62627a5f61627a)
connect rom[608], UInt<64>(0h636f72785f73627a)
connect rom[609], UInt<64>(0h30000000074656b)
connect rom[610], UInt<64>(0h3c01000004000000)
connect rom[611], UInt<64>(0h300000004000000)
connect rom[612], UInt<64>(0h5101000004000000)
connect rom[613], UInt<64>(0h300000008000000)
connect rom[614], UInt<64>(0h6201000005000000)
connect rom[615], UInt<64>(0h79616b6f)
connect rom[616], UInt<64>(0h400000003000000)
connect rom[617], UInt<64>(0h20a1070040000000)
connect rom[618], UInt<64>(0h3000000)
connect rom[619], UInt<64>(0h100000069010000)
connect rom[620], UInt<64>(0h7075727265746e69)
connect rom[621], UInt<64>(0h6f72746e6f632d74)
connect rom[622], UInt<64>(0h72656c6c)
connect rom[623], UInt<64>(0h400000003000000)
connect rom[624], UInt<64>(0h100000073010000)
connect rom[625], UInt<64>(0hf00000003000000)
connect rom[626], UInt<64>(0h637369721b000000)
connect rom[627], UInt<64>(0h6e692d7570632c76)
connect rom[628], UInt<64>(0h300000000006374)
connect rom[629], UInt<64>(0h8401000000000000)
connect rom[630], UInt<64>(0h400000003000000)
connect rom[631], UInt<64>(0hb00000099010000)
connect rom[632], UInt<64>(0h200000002000000)
connect rom[633], UInt<64>(0h4075706301000000)
connect rom[634], UInt<64>(0h300000000000038)
connect rom[635], UInt<64>(0h5300000004000000)
connect rom[636], UInt<64>(0h300000000000000)
connect rom[637], UInt<64>(0h1b00000015000000)
connect rom[638], UInt<64>(0h722c657669666973)
connect rom[639], UInt<64>(0h72003074656b636f)
connect rom[640], UInt<64>(0h76637369)
connect rom[641], UInt<64>(0h400000003000000)
connect rom[642], UInt<64>(0h4000000063000000)
connect rom[643], UInt<64>(0h400000003000000)
connect rom[644], UInt<64>(0h4000000076000000)
connect rom[645], UInt<64>(0h400000003000000)
connect rom[646], UInt<64>(0h80000083000000)
connect rom[647], UInt<64>(0h400000003000000)
connect rom[648], UInt<64>(0h100000090000000)
connect rom[649], UInt<64>(0h400000003000000)
connect rom[650], UInt<64>(0h200000009b000000)
connect rom[651], UInt<64>(0h400000003000000)
connect rom[652], UInt<64>(0h757063a6000000)
connect rom[653], UInt<64>(0h400000003000000)
connect rom[654], UInt<64>(0h1000000b2000000)
connect rom[655], UInt<64>(0h400000003000000)
connect rom[656], UInt<64>(0h40000000d1000000)
connect rom[657], UInt<64>(0h400000003000000)
connect rom[658], UInt<64>(0h40000000e4000000)
connect rom[659], UInt<64>(0h400000003000000)
connect rom[660], UInt<64>(0h800000f1000000)
connect rom[661], UInt<64>(0h400000003000000)
connect rom[662], UInt<64>(0h1000000fe000000)
connect rom[663], UInt<64>(0h400000003000000)
connect rom[664], UInt<64>(0h2000000009010000)
connect rom[665], UInt<64>(0hb00000003000000)
connect rom[666], UInt<64>(0h6373697214010000)
connect rom[667], UInt<64>(0h393376732c76)
connect rom[668], UInt<64>(0h400000003000000)
connect rom[669], UInt<64>(0h10000001d010000)
connect rom[670], UInt<64>(0h400000003000000)
connect rom[671], UInt<64>(0h80000002e010000)
connect rom[672], UInt<64>(0h3800000003000000)
connect rom[673], UInt<64>(0h3436767232010000)
connect rom[674], UInt<64>(0h7a62636466616d69)
connect rom[675], UInt<64>(0h66697a5f72736369)
connect rom[676], UInt<64>(0h697a5f6965636e65)
connect rom[677], UInt<64>(0h5f68667a5f6d7068)
connect rom[678], UInt<64>(0h5f62627a5f61627a)
connect rom[679], UInt<64>(0h636f72785f73627a)
connect rom[680], UInt<64>(0h30000000074656b)
connect rom[681], UInt<64>(0h3c01000004000000)
connect rom[682], UInt<64>(0h300000004000000)
connect rom[683], UInt<64>(0h5101000004000000)
connect rom[684], UInt<64>(0h300000008000000)
connect rom[685], UInt<64>(0h6201000005000000)
connect rom[686], UInt<64>(0h79616b6f)
connect rom[687], UInt<64>(0h400000003000000)
connect rom[688], UInt<64>(0h20a1070040000000)
connect rom[689], UInt<64>(0h3000000)
connect rom[690], UInt<64>(0h100000069010000)
connect rom[691], UInt<64>(0h7075727265746e69)
connect rom[692], UInt<64>(0h6f72746e6f632d74)
connect rom[693], UInt<64>(0h72656c6c)
connect rom[694], UInt<64>(0h400000003000000)
connect rom[695], UInt<64>(0h100000073010000)
connect rom[696], UInt<64>(0hf00000003000000)
connect rom[697], UInt<64>(0h637369721b000000)
connect rom[698], UInt<64>(0h6e692d7570632c76)
connect rom[699], UInt<64>(0h300000000006374)
connect rom[700], UInt<64>(0h8401000000000000)
connect rom[701], UInt<64>(0h400000003000000)
connect rom[702], UInt<64>(0hc00000099010000)
connect rom[703], UInt<64>(0h200000002000000)
connect rom[704], UInt<64>(0h4075706301000000)
connect rom[705], UInt<64>(0h300000000000039)
connect rom[706], UInt<64>(0h5300000004000000)
connect rom[707], UInt<64>(0h300000000000000)
connect rom[708], UInt<64>(0h1b00000015000000)
connect rom[709], UInt<64>(0h722c657669666973)
connect rom[710], UInt<64>(0h72003074656b636f)
connect rom[711], UInt<64>(0h76637369)
connect rom[712], UInt<64>(0h400000003000000)
connect rom[713], UInt<64>(0h4000000063000000)
connect rom[714], UInt<64>(0h400000003000000)
connect rom[715], UInt<64>(0h4000000076000000)
connect rom[716], UInt<64>(0h400000003000000)
connect rom[717], UInt<64>(0h80000083000000)
connect rom[718], UInt<64>(0h400000003000000)
connect rom[719], UInt<64>(0h100000090000000)
connect rom[720], UInt<64>(0h400000003000000)
connect rom[721], UInt<64>(0h200000009b000000)
connect rom[722], UInt<64>(0h400000003000000)
connect rom[723], UInt<64>(0h757063a6000000)
connect rom[724], UInt<64>(0h400000003000000)
connect rom[725], UInt<64>(0h1000000b2000000)
connect rom[726], UInt<64>(0h400000003000000)
connect rom[727], UInt<64>(0h40000000d1000000)
connect rom[728], UInt<64>(0h400000003000000)
connect rom[729], UInt<64>(0h40000000e4000000)
connect rom[730], UInt<64>(0h400000003000000)
connect rom[731], UInt<64>(0h800000f1000000)
connect rom[732], UInt<64>(0h400000003000000)
connect rom[733], UInt<64>(0h1000000fe000000)
connect rom[734], UInt<64>(0h400000003000000)
connect rom[735], UInt<64>(0h2000000009010000)
connect rom[736], UInt<64>(0hb00000003000000)
connect rom[737], UInt<64>(0h6373697214010000)
connect rom[738], UInt<64>(0h393376732c76)
connect rom[739], UInt<64>(0h400000003000000)
connect rom[740], UInt<64>(0h10000001d010000)
connect rom[741], UInt<64>(0h400000003000000)
connect rom[742], UInt<64>(0h90000002e010000)
connect rom[743], UInt<64>(0h3800000003000000)
connect rom[744], UInt<64>(0h3436767232010000)
connect rom[745], UInt<64>(0h7a62636466616d69)
connect rom[746], UInt<64>(0h66697a5f72736369)
connect rom[747], UInt<64>(0h697a5f6965636e65)
connect rom[748], UInt<64>(0h5f68667a5f6d7068)
connect rom[749], UInt<64>(0h5f62627a5f61627a)
connect rom[750], UInt<64>(0h636f72785f73627a)
connect rom[751], UInt<64>(0h30000000074656b)
connect rom[752], UInt<64>(0h3c01000004000000)
connect rom[753], UInt<64>(0h300000004000000)
connect rom[754], UInt<64>(0h5101000004000000)
connect rom[755], UInt<64>(0h300000008000000)
connect rom[756], UInt<64>(0h6201000005000000)
connect rom[757], UInt<64>(0h79616b6f)
connect rom[758], UInt<64>(0h400000003000000)
connect rom[759], UInt<64>(0h20a1070040000000)
connect rom[760], UInt<64>(0h3000000)
connect rom[761], UInt<64>(0h100000069010000)
connect rom[762], UInt<64>(0h7075727265746e69)
connect rom[763], UInt<64>(0h6f72746e6f632d74)
connect rom[764], UInt<64>(0h72656c6c)
connect rom[765], UInt<64>(0h400000003000000)
connect rom[766], UInt<64>(0h100000073010000)
connect rom[767], UInt<64>(0hf00000003000000)
connect rom[768], UInt<64>(0h637369721b000000)
connect rom[769], UInt<64>(0h6e692d7570632c76)
connect rom[770], UInt<64>(0h300000000006374)
connect rom[771], UInt<64>(0h8401000000000000)
connect rom[772], UInt<64>(0h400000003000000)
connect rom[773], UInt<64>(0hd00000099010000)
connect rom[774], UInt<64>(0h200000002000000)
connect rom[775], UInt<64>(0h4075706301000000)
connect rom[776], UInt<64>(0h300000000000061)
connect rom[777], UInt<64>(0h5300000004000000)
connect rom[778], UInt<64>(0h300000000000000)
connect rom[779], UInt<64>(0h1b00000015000000)
connect rom[780], UInt<64>(0h722c657669666973)
connect rom[781], UInt<64>(0h72003074656b636f)
connect rom[782], UInt<64>(0h76637369)
connect rom[783], UInt<64>(0h400000003000000)
connect rom[784], UInt<64>(0h4000000063000000)
connect rom[785], UInt<64>(0h400000003000000)
connect rom[786], UInt<64>(0h4000000076000000)
connect rom[787], UInt<64>(0h400000003000000)
connect rom[788], UInt<64>(0h80000083000000)
connect rom[789], UInt<64>(0h400000003000000)
connect rom[790], UInt<64>(0h100000090000000)
connect rom[791], UInt<64>(0h400000003000000)
connect rom[792], UInt<64>(0h200000009b000000)
connect rom[793], UInt<64>(0h400000003000000)
connect rom[794], UInt<64>(0h757063a6000000)
connect rom[795], UInt<64>(0h400000003000000)
connect rom[796], UInt<64>(0h1000000b2000000)
connect rom[797], UInt<64>(0h400000003000000)
connect rom[798], UInt<64>(0h40000000d1000000)
connect rom[799], UInt<64>(0h400000003000000)
connect rom[800], UInt<64>(0h40000000e4000000)
connect rom[801], UInt<64>(0h400000003000000)
connect rom[802], UInt<64>(0h800000f1000000)
connect rom[803], UInt<64>(0h400000003000000)
connect rom[804], UInt<64>(0h1000000fe000000)
connect rom[805], UInt<64>(0h400000003000000)
connect rom[806], UInt<64>(0h2000000009010000)
connect rom[807], UInt<64>(0hb00000003000000)
connect rom[808], UInt<64>(0h6373697214010000)
connect rom[809], UInt<64>(0h393376732c76)
connect rom[810], UInt<64>(0h400000003000000)
connect rom[811], UInt<64>(0h10000001d010000)
connect rom[812], UInt<64>(0h400000003000000)
connect rom[813], UInt<64>(0ha0000002e010000)
connect rom[814], UInt<64>(0h3800000003000000)
connect rom[815], UInt<64>(0h3436767232010000)
connect rom[816], UInt<64>(0h7a62636466616d69)
connect rom[817], UInt<64>(0h66697a5f72736369)
connect rom[818], UInt<64>(0h697a5f6965636e65)
connect rom[819], UInt<64>(0h5f68667a5f6d7068)
connect rom[820], UInt<64>(0h5f62627a5f61627a)
connect rom[821], UInt<64>(0h636f72785f73627a)
connect rom[822], UInt<64>(0h30000000074656b)
connect rom[823], UInt<64>(0h3c01000004000000)
connect rom[824], UInt<64>(0h300000004000000)
connect rom[825], UInt<64>(0h5101000004000000)
connect rom[826], UInt<64>(0h300000008000000)
connect rom[827], UInt<64>(0h6201000005000000)
connect rom[828], UInt<64>(0h79616b6f)
connect rom[829], UInt<64>(0h400000003000000)
connect rom[830], UInt<64>(0h20a1070040000000)
connect rom[831], UInt<64>(0h3000000)
connect rom[832], UInt<64>(0h100000069010000)
connect rom[833], UInt<64>(0h7075727265746e69)
connect rom[834], UInt<64>(0h6f72746e6f632d74)
connect rom[835], UInt<64>(0h72656c6c)
connect rom[836], UInt<64>(0h400000003000000)
connect rom[837], UInt<64>(0h100000073010000)
connect rom[838], UInt<64>(0hf00000003000000)
connect rom[839], UInt<64>(0h637369721b000000)
connect rom[840], UInt<64>(0h6e692d7570632c76)
connect rom[841], UInt<64>(0h300000000006374)
connect rom[842], UInt<64>(0h8401000000000000)
connect rom[843], UInt<64>(0h400000003000000)
connect rom[844], UInt<64>(0he00000099010000)
connect rom[845], UInt<64>(0h200000002000000)
connect rom[846], UInt<64>(0h4075706301000000)
connect rom[847], UInt<64>(0h300000000000062)
connect rom[848], UInt<64>(0h5300000004000000)
connect rom[849], UInt<64>(0h300000000000000)
connect rom[850], UInt<64>(0h1b00000015000000)
connect rom[851], UInt<64>(0h722c657669666973)
connect rom[852], UInt<64>(0h72003074656b636f)
connect rom[853], UInt<64>(0h76637369)
connect rom[854], UInt<64>(0h400000003000000)
connect rom[855], UInt<64>(0h4000000063000000)
connect rom[856], UInt<64>(0h400000003000000)
connect rom[857], UInt<64>(0h4000000076000000)
connect rom[858], UInt<64>(0h400000003000000)
connect rom[859], UInt<64>(0h80000083000000)
connect rom[860], UInt<64>(0h400000003000000)
connect rom[861], UInt<64>(0h100000090000000)
connect rom[862], UInt<64>(0h400000003000000)
connect rom[863], UInt<64>(0h200000009b000000)
connect rom[864], UInt<64>(0h400000003000000)
connect rom[865], UInt<64>(0h757063a6000000)
connect rom[866], UInt<64>(0h400000003000000)
connect rom[867], UInt<64>(0h1000000b2000000)
connect rom[868], UInt<64>(0h400000003000000)
connect rom[869], UInt<64>(0h40000000d1000000)
connect rom[870], UInt<64>(0h400000003000000)
connect rom[871], UInt<64>(0h40000000e4000000)
connect rom[872], UInt<64>(0h400000003000000)
connect rom[873], UInt<64>(0h800000f1000000)
connect rom[874], UInt<64>(0h400000003000000)
connect rom[875], UInt<64>(0h1000000fe000000)
connect rom[876], UInt<64>(0h400000003000000)
connect rom[877], UInt<64>(0h2000000009010000)
connect rom[878], UInt<64>(0hb00000003000000)
connect rom[879], UInt<64>(0h6373697214010000)
connect rom[880], UInt<64>(0h393376732c76)
connect rom[881], UInt<64>(0h400000003000000)
connect rom[882], UInt<64>(0h10000001d010000)
connect rom[883], UInt<64>(0h400000003000000)
connect rom[884], UInt<64>(0hb0000002e010000)
connect rom[885], UInt<64>(0h3800000003000000)
connect rom[886], UInt<64>(0h3436767232010000)
connect rom[887], UInt<64>(0h7a62636466616d69)
connect rom[888], UInt<64>(0h66697a5f72736369)
connect rom[889], UInt<64>(0h697a5f6965636e65)
connect rom[890], UInt<64>(0h5f68667a5f6d7068)
connect rom[891], UInt<64>(0h5f62627a5f61627a)
connect rom[892], UInt<64>(0h636f72785f73627a)
connect rom[893], UInt<64>(0h30000000074656b)
connect rom[894], UInt<64>(0h3c01000004000000)
connect rom[895], UInt<64>(0h300000004000000)
connect rom[896], UInt<64>(0h5101000004000000)
connect rom[897], UInt<64>(0h300000008000000)
connect rom[898], UInt<64>(0h6201000005000000)
connect rom[899], UInt<64>(0h79616b6f)
connect rom[900], UInt<64>(0h400000003000000)
connect rom[901], UInt<64>(0h20a1070040000000)
connect rom[902], UInt<64>(0h3000000)
connect rom[903], UInt<64>(0h100000069010000)
connect rom[904], UInt<64>(0h7075727265746e69)
connect rom[905], UInt<64>(0h6f72746e6f632d74)
connect rom[906], UInt<64>(0h72656c6c)
connect rom[907], UInt<64>(0h400000003000000)
connect rom[908], UInt<64>(0h100000073010000)
connect rom[909], UInt<64>(0hf00000003000000)
connect rom[910], UInt<64>(0h637369721b000000)
connect rom[911], UInt<64>(0h6e692d7570632c76)
connect rom[912], UInt<64>(0h300000000006374)
connect rom[913], UInt<64>(0h8401000000000000)
connect rom[914], UInt<64>(0h400000003000000)
connect rom[915], UInt<64>(0hf00000099010000)
connect rom[916], UInt<64>(0h200000002000000)
connect rom[917], UInt<64>(0h100000002000000)
connect rom[918], UInt<64>(0h66697468)
connect rom[919], UInt<64>(0ha00000003000000)
connect rom[920], UInt<64>(0h2c6263751b000000)
connect rom[921], UInt<64>(0h3066697468)
connect rom[922], UInt<64>(0h100000002000000)
connect rom[923], UInt<64>(0h384079726f6d656d)
connect rom[924], UInt<64>(0h303030303030)
connect rom[925], UInt<64>(0h700000003000000)
connect rom[926], UInt<64>(0h6f6d656da6000000)
connect rom[927], UInt<64>(0h300000000007972)
connect rom[928], UInt<64>(0h2e01000008000000)
connect rom[929], UInt<64>(0h10000000008)
connect rom[930], UInt<64>(0h900000003000000)
connect rom[931], UInt<64>(0h6173696462010000)
connect rom[932], UInt<64>(0h64656c62)
connect rom[933], UInt<64>(0h400000003000000)
connect rom[934], UInt<64>(0h300000099010000)
connect rom[935], UInt<64>(0h100000002000000)
connect rom[936], UInt<64>(0h384079726f6d656d)
connect rom[937], UInt<64>(0h30303030303030)
connect rom[938], UInt<64>(0h700000003000000)
connect rom[939], UInt<64>(0h6f6d656da6000000)
connect rom[940], UInt<64>(0h300000000007972)
connect rom[941], UInt<64>(0h2e01000008000000)
connect rom[942], UInt<64>(0h1000000080)
connect rom[943], UInt<64>(0h400000003000000)
connect rom[944], UInt<64>(0h200000099010000)
connect rom[945], UInt<64>(0h100000002000000)
connect rom[946], UInt<64>(0h300000000636f73)
connect rom[947], UInt<64>(0h4000000)
connect rom[948], UInt<64>(0h300000001000000)
connect rom[949], UInt<64>(0hf00000004000000)
connect rom[950], UInt<64>(0h300000001000000)
connect rom[951], UInt<64>(0h1b00000020000000)
connect rom[952], UInt<64>(0h2c7261622d626375)
connect rom[953], UInt<64>(0h6472617970696863)
connect rom[954], UInt<64>(0h6d697300636f732d)
connect rom[955], UInt<64>(0h7375622d656c70)
connect rom[956], UInt<64>(0h3000000)
connect rom[957], UInt<64>(0h1000000a1010000)
connect rom[958], UInt<64>(0h6464612d746f6f62)
connect rom[959], UInt<64>(0h6765722d73736572)
connect rom[960], UInt<64>(0h3030303140)
connect rom[961], UInt<64>(0h800000003000000)
connect rom[962], UInt<64>(0h1000002e010000)
connect rom[963], UInt<64>(0h300000000100000)
connect rom[964], UInt<64>(0ha801000008000000)
connect rom[965], UInt<64>(0h6c6f72746e6f63)
connect rom[966], UInt<64>(0h100000002000000)
connect rom[967], UInt<64>(0h6f632d6568636163)
connect rom[968], UInt<64>(0h72656c6c6f72746e)
connect rom[969], UInt<64>(0h3030303031303240)
connect rom[970], UInt<64>(0h300000000000000)
connect rom[971], UInt<64>(0h6500000004000000)
connect rom[972], UInt<64>(0h300000040000000)
connect rom[973], UInt<64>(0hb201000004000000)
connect rom[974], UInt<64>(0h300000002000000)
connect rom[975], UInt<64>(0h7800000004000000)
connect rom[976], UInt<64>(0h300000000100000)
connect rom[977], UInt<64>(0h8500000004000000)
connect rom[978], UInt<64>(0h300000000002000)
connect rom[979], UInt<64>(0hbe01000000000000)
connect rom[980], UInt<64>(0h1d00000003000000)
connect rom[981], UInt<64>(0h696669731b000000)
connect rom[982], UInt<64>(0h756c636e692c6576)
connect rom[983], UInt<64>(0h6863616365766973)
connect rom[984], UInt<64>(0h6568636163003065)
connect rom[985], UInt<64>(0h300000000000000)
connect rom[986], UInt<64>(0h1d01000008000000)
connect rom[987], UInt<64>(0h300000002000000)
connect rom[988], UInt<64>(0h800000003000000)
connect rom[989], UInt<64>(0h1022e010000)
connect rom[990], UInt<64>(0h300000000100000)
connect rom[991], UInt<64>(0ha801000008000000)
connect rom[992], UInt<64>(0h6c6f72746e6f63)
connect rom[993], UInt<64>(0h400000003000000)
connect rom[994], UInt<64>(0hc000000cc010000)
connect rom[995], UInt<64>(0h400000003000000)
connect rom[996], UInt<64>(0h100000099010000)
connect rom[997], UInt<64>(0h100000002000000)
connect rom[998], UInt<64>(0h6f6c635f73756263)
connect rom[999], UInt<64>(0h300000000006b63)
connect rom[1000], UInt<64>(0hde01000004000000)
connect rom[1001], UInt<64>(0h300000000000000)
connect rom[1002], UInt<64>(0h5300000004000000)
connect rom[1003], UInt<64>(0h30000000065cd1d)
connect rom[1004], UInt<64>(0heb0100000b000000)
connect rom[1005], UInt<64>(0h6f6c635f73756263)
connect rom[1006], UInt<64>(0h300000000006b63)
connect rom[1007], UInt<64>(0h1b0000000c000000)
connect rom[1008], UInt<64>(0h6c632d6465786966)
connect rom[1009], UInt<64>(0h2000000006b636f)
connect rom[1010], UInt<64>(0h6e696c6301000000)
connect rom[1011], UInt<64>(0h3030303030324074)
connect rom[1012], UInt<64>(0h300000000000030)
connect rom[1013], UInt<64>(0h1b0000000d000000)
connect rom[1014], UInt<64>(0h6c632c7663736972)
connect rom[1015], UInt<64>(0h30746e69)
connect rom[1016], UInt<64>(0hc000000003000000)
connect rom[1017], UInt<64>(0h4000000fe010000)
connect rom[1018], UInt<64>(0h400000003000000)
connect rom[1019], UInt<64>(0h500000007000000)
connect rom[1020], UInt<64>(0h500000003000000)
connect rom[1021], UInt<64>(0h600000007000000)
connect rom[1022], UInt<64>(0h600000003000000)
connect rom[1023], UInt<64>(0h700000007000000)
connect rom[1024], UInt<64>(0h700000003000000)
connect rom[1025], UInt<64>(0h800000007000000)
connect rom[1026], UInt<64>(0h800000003000000)
connect rom[1027], UInt<64>(0h900000007000000)
connect rom[1028], UInt<64>(0h900000003000000)
connect rom[1029], UInt<64>(0ha00000007000000)
connect rom[1030], UInt<64>(0ha00000003000000)
connect rom[1031], UInt<64>(0hb00000007000000)
connect rom[1032], UInt<64>(0hb00000003000000)
connect rom[1033], UInt<64>(0hc00000007000000)
connect rom[1034], UInt<64>(0hc00000003000000)
connect rom[1035], UInt<64>(0hd00000007000000)
connect rom[1036], UInt<64>(0hd00000003000000)
connect rom[1037], UInt<64>(0he00000007000000)
connect rom[1038], UInt<64>(0he00000003000000)
connect rom[1039], UInt<64>(0hf00000007000000)
connect rom[1040], UInt<64>(0hf00000003000000)
connect rom[1041], UInt<64>(0h300000007000000)
connect rom[1042], UInt<64>(0h2e01000008000000)
connect rom[1043], UInt<64>(0h10000000002)
connect rom[1044], UInt<64>(0h800000003000000)
connect rom[1045], UInt<64>(0h746e6f63a8010000)
connect rom[1046], UInt<64>(0h2000000006c6f72)
connect rom[1047], UInt<64>(0h636f6c6301000000)
connect rom[1048], UInt<64>(0h4072657461672d6b)
connect rom[1049], UInt<64>(0h303030303031)
connect rom[1050], UInt<64>(0h800000003000000)
connect rom[1051], UInt<64>(0h10002e010000)
connect rom[1052], UInt<64>(0h300000000100000)
connect rom[1053], UInt<64>(0ha801000008000000)
connect rom[1054], UInt<64>(0h6c6f72746e6f63)
connect rom[1055], UInt<64>(0h100000002000000)
connect rom[1056], UInt<64>(0h6f632d6775626564)
connect rom[1057], UInt<64>(0h72656c6c6f72746e)
connect rom[1058], UInt<64>(0h300000000003040)
connect rom[1059], UInt<64>(0h1b00000021000000)
connect rom[1060], UInt<64>(0h642c657669666973)
connect rom[1061], UInt<64>(0h3331302d67756265)
connect rom[1062], UInt<64>(0h642c766373697200)
connect rom[1063], UInt<64>(0h3331302d67756265)
connect rom[1064], UInt<64>(0h300000000000000)
connect rom[1065], UInt<64>(0h1202000005000000)
connect rom[1066], UInt<64>(0h6761746a)
connect rom[1067], UInt<64>(0h6000000003000000)
connect rom[1068], UInt<64>(0h4000000fe010000)
connect rom[1069], UInt<64>(0h5000000ffff0000)
connect rom[1070], UInt<64>(0h6000000ffff0000)
connect rom[1071], UInt<64>(0h7000000ffff0000)
connect rom[1072], UInt<64>(0h8000000ffff0000)
connect rom[1073], UInt<64>(0h9000000ffff0000)
connect rom[1074], UInt<64>(0ha000000ffff0000)
connect rom[1075], UInt<64>(0hb000000ffff0000)
connect rom[1076], UInt<64>(0hc000000ffff0000)
connect rom[1077], UInt<64>(0hd000000ffff0000)
connect rom[1078], UInt<64>(0he000000ffff0000)
connect rom[1079], UInt<64>(0hf000000ffff0000)
connect rom[1080], UInt<64>(0h3000000ffff0000)
connect rom[1081], UInt<64>(0h2e01000008000000)
connect rom[1082], UInt<64>(0h10000000000000)
connect rom[1083], UInt<64>(0h800000003000000)
connect rom[1084], UInt<64>(0h746e6f63a8010000)
connect rom[1085], UInt<64>(0h2000000006c6f72)
connect rom[1086], UInt<64>(0h6f72726501000000)
connect rom[1087], UInt<64>(0h6563697665642d72)
connect rom[1088], UInt<64>(0h3030303340)
connect rom[1089], UInt<64>(0he00000003000000)
connect rom[1090], UInt<64>(0h696669731b000000)
connect rom[1091], UInt<64>(0h726f7272652c6576)
connect rom[1092], UInt<64>(0h300000000000030)
connect rom[1093], UInt<64>(0h2e01000008000000)
connect rom[1094], UInt<64>(0h10000000300000)
connect rom[1095], UInt<64>(0h100000002000000)
connect rom[1096], UInt<64>(0h6f6c635f73756266)
connect rom[1097], UInt<64>(0h300000000006b63)
connect rom[1098], UInt<64>(0hde01000004000000)
connect rom[1099], UInt<64>(0h300000000000000)
connect rom[1100], UInt<64>(0h5300000004000000)
connect rom[1101], UInt<64>(0h30000000065cd1d)
connect rom[1102], UInt<64>(0heb0100000b000000)
connect rom[1103], UInt<64>(0h6f6c635f73756266)
connect rom[1104], UInt<64>(0h300000000006b63)
connect rom[1105], UInt<64>(0h1b0000000c000000)
connect rom[1106], UInt<64>(0h6c632d6465786966)
connect rom[1107], UInt<64>(0h2000000006b636f)
connect rom[1108], UInt<64>(0h65746e6901000000)
connect rom[1109], UInt<64>(0h6f632d7470757272)
connect rom[1110], UInt<64>(0h72656c6c6f72746e)
connect rom[1111], UInt<64>(0h3030303030306340)
connect rom[1112], UInt<64>(0h300000000000000)
connect rom[1113], UInt<64>(0h7301000004000000)
connect rom[1114], UInt<64>(0h300000001000000)
connect rom[1115], UInt<64>(0h1b0000000c000000)
connect rom[1116], UInt<64>(0h6c702c7663736972)
connect rom[1117], UInt<64>(0h300000000306369)
connect rom[1118], UInt<64>(0h8401000000000000)
connect rom[1119], UInt<64>(0hc000000003000000)
connect rom[1120], UInt<64>(0h4000000fe010000)
connect rom[1121], UInt<64>(0h40000000b000000)
connect rom[1122], UInt<64>(0h500000009000000)
connect rom[1123], UInt<64>(0h50000000b000000)
connect rom[1124], UInt<64>(0h600000009000000)
connect rom[1125], UInt<64>(0h60000000b000000)
connect rom[1126], UInt<64>(0h700000009000000)
connect rom[1127], UInt<64>(0h70000000b000000)
connect rom[1128], UInt<64>(0h800000009000000)
connect rom[1129], UInt<64>(0h80000000b000000)
connect rom[1130], UInt<64>(0h900000009000000)
connect rom[1131], UInt<64>(0h90000000b000000)
connect rom[1132], UInt<64>(0ha00000009000000)
connect rom[1133], UInt<64>(0ha0000000b000000)
connect rom[1134], UInt<64>(0hb00000009000000)
connect rom[1135], UInt<64>(0hb0000000b000000)
connect rom[1136], UInt<64>(0hc00000009000000)
connect rom[1137], UInt<64>(0hc0000000b000000)
connect rom[1138], UInt<64>(0hd00000009000000)
connect rom[1139], UInt<64>(0hd0000000b000000)
connect rom[1140], UInt<64>(0he00000009000000)
connect rom[1141], UInt<64>(0he0000000b000000)
connect rom[1142], UInt<64>(0hf00000009000000)
connect rom[1143], UInt<64>(0hf0000000b000000)
connect rom[1144], UInt<64>(0h300000009000000)
connect rom[1145], UInt<64>(0h2e01000008000000)
connect rom[1146], UInt<64>(0h40000000c)
connect rom[1147], UInt<64>(0h800000003000000)
connect rom[1148], UInt<64>(0h746e6f63a8010000)
connect rom[1149], UInt<64>(0h3000000006c6f72)
connect rom[1150], UInt<64>(0h1f02000004000000)
connect rom[1151], UInt<64>(0h300000001000000)
connect rom[1152], UInt<64>(0h3202000004000000)
connect rom[1153], UInt<64>(0h300000001000000)
connect rom[1154], UInt<64>(0h9901000004000000)
connect rom[1155], UInt<64>(0h200000011000000)
connect rom[1156], UInt<64>(0h7375626d01000000)
connect rom[1157], UInt<64>(0h6b636f6c635f)
connect rom[1158], UInt<64>(0h400000003000000)
connect rom[1159], UInt<64>(0hde010000)
connect rom[1160], UInt<64>(0h400000003000000)
connect rom[1161], UInt<64>(0h65cd1d53000000)
connect rom[1162], UInt<64>(0hb00000003000000)
connect rom[1163], UInt<64>(0h7375626deb010000)
connect rom[1164], UInt<64>(0h6b636f6c635f)
connect rom[1165], UInt<64>(0hc00000003000000)
connect rom[1166], UInt<64>(0h657869661b000000)
connect rom[1167], UInt<64>(0h6b636f6c632d64)
connect rom[1168], UInt<64>(0h100000002000000)
connect rom[1169], UInt<64>(0h6f6c635f73756270)
connect rom[1170], UInt<64>(0h300000000006b63)
connect rom[1171], UInt<64>(0hde01000004000000)
connect rom[1172], UInt<64>(0h300000000000000)
connect rom[1173], UInt<64>(0h5300000004000000)
connect rom[1174], UInt<64>(0h30000000065cd1d)
connect rom[1175], UInt<64>(0heb0100000b000000)
connect rom[1176], UInt<64>(0h6f6c635f73756270)
connect rom[1177], UInt<64>(0h300000000006b63)
connect rom[1178], UInt<64>(0h1b0000000c000000)
connect rom[1179], UInt<64>(0h6c632d6465786966)
connect rom[1180], UInt<64>(0h3000000006b636f)
connect rom[1181], UInt<64>(0h9901000004000000)
connect rom[1182], UInt<64>(0h200000010000000)
connect rom[1183], UInt<64>(0h406d6f7201000000)
connect rom[1184], UInt<64>(0h3030303031)
connect rom[1185], UInt<64>(0hc00000003000000)
connect rom[1186], UInt<64>(0h696669731b000000)
connect rom[1187], UInt<64>(0h306d6f722c6576)
connect rom[1188], UInt<64>(0h800000003000000)
connect rom[1189], UInt<64>(0h1002e010000)
connect rom[1190], UInt<64>(0h300000000000100)
connect rom[1191], UInt<64>(0ha801000004000000)
connect rom[1192], UInt<64>(0h2000000006d656d)
connect rom[1193], UInt<64>(0h7375627301000000)
connect rom[1194], UInt<64>(0h6b636f6c635f)
connect rom[1195], UInt<64>(0h400000003000000)
connect rom[1196], UInt<64>(0hde010000)
connect rom[1197], UInt<64>(0h400000003000000)
connect rom[1198], UInt<64>(0h65cd1d53000000)
connect rom[1199], UInt<64>(0hb00000003000000)
connect rom[1200], UInt<64>(0h73756273eb010000)
connect rom[1201], UInt<64>(0h6b636f6c635f)
connect rom[1202], UInt<64>(0hc00000003000000)
connect rom[1203], UInt<64>(0h657869661b000000)
connect rom[1204], UInt<64>(0h6b636f6c632d64)
connect rom[1205], UInt<64>(0h100000002000000)
connect rom[1206], UInt<64>(0h31406c6169726573)
connect rom[1207], UInt<64>(0h30303030323030)
connect rom[1208], UInt<64>(0h400000003000000)
connect rom[1209], UInt<64>(0h100000003d020000)
connect rom[1210], UInt<64>(0hd00000003000000)
connect rom[1211], UInt<64>(0h696669731b000000)
connect rom[1212], UInt<64>(0h30747261752c6576)
connect rom[1213], UInt<64>(0h300000000000000)
connect rom[1214], UInt<64>(0h4402000004000000)
connect rom[1215], UInt<64>(0h300000011000000)
connect rom[1216], UInt<64>(0h5502000004000000)
connect rom[1217], UInt<64>(0h300000001000000)
connect rom[1218], UInt<64>(0h2e01000008000000)
connect rom[1219], UInt<64>(0h10000000000210)
connect rom[1220], UInt<64>(0h800000003000000)
connect rom[1221], UInt<64>(0h746e6f63a8010000)
connect rom[1222], UInt<64>(0h2000000006c6f72)
connect rom[1223], UInt<64>(0h656c697401000000)
connect rom[1224], UInt<64>(0h732d74657365722d)
connect rom[1225], UInt<64>(0h3131407265747465)
connect rom[1226], UInt<64>(0h30303030)
connect rom[1227], UInt<64>(0h800000003000000)
connect rom[1228], UInt<64>(0h11002e010000)
connect rom[1229], UInt<64>(0h300000000100000)
connect rom[1230], UInt<64>(0ha801000008000000)
connect rom[1231], UInt<64>(0h6c6f72746e6f63)
connect rom[1232], UInt<64>(0h200000002000000)
connect rom[1233], UInt<64>(0h900000002000000)
connect rom[1234], UInt<64>(0h7373657264646123)
connect rom[1235], UInt<64>(0h2300736c6c65632d)
connect rom[1236], UInt<64>(0h6c65632d657a6973)
connect rom[1237], UInt<64>(0h61706d6f6300736c)
connect rom[1238], UInt<64>(0h6f6d00656c626974)
connect rom[1239], UInt<64>(0h69726573006c6564)
connect rom[1240], UInt<64>(0h6f64747300306c61)
connect rom[1241], UInt<64>(0h687461702d7475)
connect rom[1242], UInt<64>(0h65736162656d6974)
connect rom[1243], UInt<64>(0h6e6575716572662d)
connect rom[1244], UInt<64>(0h6b636f6c63007963)
connect rom[1245], UInt<64>(0h6e6575716572662d)
connect rom[1246], UInt<64>(0h6361632d64007963)
connect rom[1247], UInt<64>(0h6b636f6c622d6568)
connect rom[1248], UInt<64>(0h2d6400657a69732d)
connect rom[1249], UInt<64>(0h65732d6568636163)
connect rom[1250], UInt<64>(0h6361632d64007374)
connect rom[1251], UInt<64>(0h657a69732d6568)
connect rom[1252], UInt<64>(0h65732d626c742d64)
connect rom[1253], UInt<64>(0h626c742d64007374)
connect rom[1254], UInt<64>(0h656400657a69732d)
connect rom[1255], UInt<64>(0h7079745f65636976)
connect rom[1256], UInt<64>(0h6177647261680065)
connect rom[1257], UInt<64>(0h2d636578652d6572)
connect rom[1258], UInt<64>(0h696f706b61657262)
connect rom[1259], UInt<64>(0h746e756f632d746e)
connect rom[1260], UInt<64>(0h65686361632d6900)
connect rom[1261], UInt<64>(0h732d6b636f6c622d)
connect rom[1262], UInt<64>(0h61632d6900657a69)
connect rom[1263], UInt<64>(0h737465732d656863)
connect rom[1264], UInt<64>(0h65686361632d6900)
connect rom[1265], UInt<64>(0h2d6900657a69732d)
connect rom[1266], UInt<64>(0h737465732d626c74)
connect rom[1267], UInt<64>(0h732d626c742d6900)
connect rom[1268], UInt<64>(0h2d756d6d00657a69)
connect rom[1269], UInt<64>(0h78656e0065707974)
connect rom[1270], UInt<64>(0h2d6c6576656c2d74)
connect rom[1271], UInt<64>(0h6572006568636163)
connect rom[1272], UInt<64>(0h2c76637369720067)
connect rom[1273], UInt<64>(0h6373697200617369)
connect rom[1274], UInt<64>(0h617267706d702c76)
connect rom[1275], UInt<64>(0h79746972616c756e)
connect rom[1276], UInt<64>(0h702c766373697200)
connect rom[1277], UInt<64>(0h6e6f69676572706d)
connect rom[1278], UInt<64>(0h7375746174730073)
connect rom[1279], UInt<64>(0h6c70732d626c7400)
connect rom[1280], UInt<64>(0h65746e6923007469)
connect rom[1281], UInt<64>(0h65632d7470757272)
connect rom[1282], UInt<64>(0h65746e6900736c6c)
connect rom[1283], UInt<64>(0h6f632d7470757272)
connect rom[1284], UInt<64>(0h72656c6c6f72746e)
connect rom[1285], UInt<64>(0h656c646e61687000)
connect rom[1286], UInt<64>(0h7365676e617200)
connect rom[1287], UInt<64>(0h656d616e2d676572)
connect rom[1288], UInt<64>(0h2d65686361630073)
connect rom[1289], UInt<64>(0h6163006c6576656c)
connect rom[1290], UInt<64>(0h66696e752d656863)
connect rom[1291], UInt<64>(0h6966697300646569)
connect rom[1292], UInt<64>(0h2d7268736d2c6576)
connect rom[1293], UInt<64>(0h632300746e756f63)
connect rom[1294], UInt<64>(0h6c65632d6b636f6c)
connect rom[1295], UInt<64>(0h6b636f6c6300736c)
connect rom[1296], UInt<64>(0h2d74757074756f2d)
connect rom[1297], UInt<64>(0h6e690073656d616e)
connect rom[1298], UInt<64>(0h7374707572726574)
connect rom[1299], UInt<64>(0h65646e657478652d)
connect rom[1300], UInt<64>(0h2d67756265640064)
connect rom[1301], UInt<64>(0h7200686361747461)
connect rom[1302], UInt<64>(0h78616d2c76637369)
connect rom[1303], UInt<64>(0h7469726f6972702d)
connect rom[1304], UInt<64>(0h2c76637369720079)
connect rom[1305], UInt<64>(0h6f6c63007665646e)
connect rom[1306], UInt<64>(0h65746e6900736b63)
connect rom[1307], UInt<64>(0h61702d7470757272)
connect rom[1308], UInt<64>(0h746e6900746e6572)
connect rom[1309], UInt<64>(0h73747075727265)
connect rom[1310], UInt<64>(0h0)
connect rom[1311], UInt<64>(0h0)
connect rom[1312], UInt<64>(0h0)
connect rom[1313], UInt<64>(0h0)
connect rom[1314], UInt<64>(0h0)
connect rom[1315], UInt<64>(0h0)
connect rom[1316], UInt<64>(0h0)
connect rom[1317], UInt<64>(0h0)
connect rom[1318], UInt<64>(0h0)
connect rom[1319], UInt<64>(0h0)
connect rom[1320], UInt<64>(0h0)
connect rom[1321], UInt<64>(0h0)
connect rom[1322], UInt<64>(0h0)
connect rom[1323], UInt<64>(0h0)
connect rom[1324], UInt<64>(0h0)
connect rom[1325], UInt<64>(0h0)
connect rom[1326], UInt<64>(0h0)
connect rom[1327], UInt<64>(0h0)
connect rom[1328], UInt<64>(0h0)
connect rom[1329], UInt<64>(0h0)
connect rom[1330], UInt<64>(0h0)
connect rom[1331], UInt<64>(0h0)
connect rom[1332], UInt<64>(0h0)
connect rom[1333], UInt<64>(0h0)
connect rom[1334], UInt<64>(0h0)
connect rom[1335], UInt<64>(0h0)
connect rom[1336], UInt<64>(0h0)
connect rom[1337], UInt<64>(0h0)
connect rom[1338], UInt<64>(0h0)
connect rom[1339], UInt<64>(0h0)
connect rom[1340], UInt<64>(0h0)
connect rom[1341], UInt<64>(0h0)
connect rom[1342], UInt<64>(0h0)
connect rom[1343], UInt<64>(0h0)
connect rom[1344], UInt<64>(0h0)
connect rom[1345], UInt<64>(0h0)
connect rom[1346], UInt<64>(0h0)
connect rom[1347], UInt<64>(0h0)
connect rom[1348], UInt<64>(0h0)
connect rom[1349], UInt<64>(0h0)
connect rom[1350], UInt<64>(0h0)
connect rom[1351], UInt<64>(0h0)
connect rom[1352], UInt<64>(0h0)
connect rom[1353], UInt<64>(0h0)
connect rom[1354], UInt<64>(0h0)
connect rom[1355], UInt<64>(0h0)
connect rom[1356], UInt<64>(0h0)
connect rom[1357], UInt<64>(0h0)
connect rom[1358], UInt<64>(0h0)
connect rom[1359], UInt<64>(0h0)
connect rom[1360], UInt<64>(0h0)
connect rom[1361], UInt<64>(0h0)
connect rom[1362], UInt<64>(0h0)
connect rom[1363], UInt<64>(0h0)
connect rom[1364], UInt<64>(0h0)
connect rom[1365], UInt<64>(0h0)
connect rom[1366], UInt<64>(0h0)
connect rom[1367], UInt<64>(0h0)
connect rom[1368], UInt<64>(0h0)
connect rom[1369], UInt<64>(0h0)
connect rom[1370], UInt<64>(0h0)
connect rom[1371], UInt<64>(0h0)
connect rom[1372], UInt<64>(0h0)
connect rom[1373], UInt<64>(0h0)
connect rom[1374], UInt<64>(0h0)
connect rom[1375], UInt<64>(0h0)
connect rom[1376], UInt<64>(0h0)
connect rom[1377], UInt<64>(0h0)
connect rom[1378], UInt<64>(0h0)
connect rom[1379], UInt<64>(0h0)
connect rom[1380], UInt<64>(0h0)
connect rom[1381], UInt<64>(0h0)
connect rom[1382], UInt<64>(0h0)
connect rom[1383], UInt<64>(0h0)
connect rom[1384], UInt<64>(0h0)
connect rom[1385], UInt<64>(0h0)
connect rom[1386], UInt<64>(0h0)
connect rom[1387], UInt<64>(0h0)
connect rom[1388], UInt<64>(0h0)
connect rom[1389], UInt<64>(0h0)
connect rom[1390], UInt<64>(0h0)
connect rom[1391], UInt<64>(0h0)
connect rom[1392], UInt<64>(0h0)
connect rom[1393], UInt<64>(0h0)
connect rom[1394], UInt<64>(0h0)
connect rom[1395], UInt<64>(0h0)
connect rom[1396], UInt<64>(0h0)
connect rom[1397], UInt<64>(0h0)
connect rom[1398], UInt<64>(0h0)
connect rom[1399], UInt<64>(0h0)
connect rom[1400], UInt<64>(0h0)
connect rom[1401], UInt<64>(0h0)
connect rom[1402], UInt<64>(0h0)
connect rom[1403], UInt<64>(0h0)
connect rom[1404], UInt<64>(0h0)
connect rom[1405], UInt<64>(0h0)
connect rom[1406], UInt<64>(0h0)
connect rom[1407], UInt<64>(0h0)
connect rom[1408], UInt<64>(0h0)
connect rom[1409], UInt<64>(0h0)
connect rom[1410], UInt<64>(0h0)
connect rom[1411], UInt<64>(0h0)
connect rom[1412], UInt<64>(0h0)
connect rom[1413], UInt<64>(0h0)
connect rom[1414], UInt<64>(0h0)
connect rom[1415], UInt<64>(0h0)
connect rom[1416], UInt<64>(0h0)
connect rom[1417], UInt<64>(0h0)
connect rom[1418], UInt<64>(0h0)
connect rom[1419], UInt<64>(0h0)
connect rom[1420], UInt<64>(0h0)
connect rom[1421], UInt<64>(0h0)
connect rom[1422], UInt<64>(0h0)
connect rom[1423], UInt<64>(0h0)
connect rom[1424], UInt<64>(0h0)
connect rom[1425], UInt<64>(0h0)
connect rom[1426], UInt<64>(0h0)
connect rom[1427], UInt<64>(0h0)
connect rom[1428], UInt<64>(0h0)
connect rom[1429], UInt<64>(0h0)
connect rom[1430], UInt<64>(0h0)
connect rom[1431], UInt<64>(0h0)
connect rom[1432], UInt<64>(0h0)
connect rom[1433], UInt<64>(0h0)
connect rom[1434], UInt<64>(0h0)
connect rom[1435], UInt<64>(0h0)
connect rom[1436], UInt<64>(0h0)
connect rom[1437], UInt<64>(0h0)
connect rom[1438], UInt<64>(0h0)
connect rom[1439], UInt<64>(0h0)
connect rom[1440], UInt<64>(0h0)
connect rom[1441], UInt<64>(0h0)
connect rom[1442], UInt<64>(0h0)
connect rom[1443], UInt<64>(0h0)
connect rom[1444], UInt<64>(0h0)
connect rom[1445], UInt<64>(0h0)
connect rom[1446], UInt<64>(0h0)
connect rom[1447], UInt<64>(0h0)
connect rom[1448], UInt<64>(0h0)
connect rom[1449], UInt<64>(0h0)
connect rom[1450], UInt<64>(0h0)
connect rom[1451], UInt<64>(0h0)
connect rom[1452], UInt<64>(0h0)
connect rom[1453], UInt<64>(0h0)
connect rom[1454], UInt<64>(0h0)
connect rom[1455], UInt<64>(0h0)
connect rom[1456], UInt<64>(0h0)
connect rom[1457], UInt<64>(0h0)
connect rom[1458], UInt<64>(0h0)
connect rom[1459], UInt<64>(0h0)
connect rom[1460], UInt<64>(0h0)
connect rom[1461], UInt<64>(0h0)
connect rom[1462], UInt<64>(0h0)
connect rom[1463], UInt<64>(0h0)
connect rom[1464], UInt<64>(0h0)
connect rom[1465], UInt<64>(0h0)
connect rom[1466], UInt<64>(0h0)
connect rom[1467], UInt<64>(0h0)
connect rom[1468], UInt<64>(0h0)
connect rom[1469], UInt<64>(0h0)
connect rom[1470], UInt<64>(0h0)
connect rom[1471], UInt<64>(0h0)
connect rom[1472], UInt<64>(0h0)
connect rom[1473], UInt<64>(0h0)
connect rom[1474], UInt<64>(0h0)
connect rom[1475], UInt<64>(0h0)
connect rom[1476], UInt<64>(0h0)
connect rom[1477], UInt<64>(0h0)
connect rom[1478], UInt<64>(0h0)
connect rom[1479], UInt<64>(0h0)
connect rom[1480], UInt<64>(0h0)
connect rom[1481], UInt<64>(0h0)
connect rom[1482], UInt<64>(0h0)
connect rom[1483], UInt<64>(0h0)
connect rom[1484], UInt<64>(0h0)
connect rom[1485], UInt<64>(0h0)
connect rom[1486], UInt<64>(0h0)
connect rom[1487], UInt<64>(0h0)
connect rom[1488], UInt<64>(0h0)
connect rom[1489], UInt<64>(0h0)
connect rom[1490], UInt<64>(0h0)
connect rom[1491], UInt<64>(0h0)
connect rom[1492], UInt<64>(0h0)
connect rom[1493], UInt<64>(0h0)
connect rom[1494], UInt<64>(0h0)
connect rom[1495], UInt<64>(0h0)
connect rom[1496], UInt<64>(0h0)
connect rom[1497], UInt<64>(0h0)
connect rom[1498], UInt<64>(0h0)
connect rom[1499], UInt<64>(0h0)
connect rom[1500], UInt<64>(0h0)
connect rom[1501], UInt<64>(0h0)
connect rom[1502], UInt<64>(0h0)
connect rom[1503], UInt<64>(0h0)
connect rom[1504], UInt<64>(0h0)
connect rom[1505], UInt<64>(0h0)
connect rom[1506], UInt<64>(0h0)
connect rom[1507], UInt<64>(0h0)
connect rom[1508], UInt<64>(0h0)
connect rom[1509], UInt<64>(0h0)
connect rom[1510], UInt<64>(0h0)
connect rom[1511], UInt<64>(0h0)
connect rom[1512], UInt<64>(0h0)
connect rom[1513], UInt<64>(0h0)
connect rom[1514], UInt<64>(0h0)
connect rom[1515], UInt<64>(0h0)
connect rom[1516], UInt<64>(0h0)
connect rom[1517], UInt<64>(0h0)
connect rom[1518], UInt<64>(0h0)
connect rom[1519], UInt<64>(0h0)
connect rom[1520], UInt<64>(0h0)
connect rom[1521], UInt<64>(0h0)
connect rom[1522], UInt<64>(0h0)
connect rom[1523], UInt<64>(0h0)
connect rom[1524], UInt<64>(0h0)
connect rom[1525], UInt<64>(0h0)
connect rom[1526], UInt<64>(0h0)
connect rom[1527], UInt<64>(0h0)
connect rom[1528], UInt<64>(0h0)
connect rom[1529], UInt<64>(0h0)
connect rom[1530], UInt<64>(0h0)
connect rom[1531], UInt<64>(0h0)
connect rom[1532], UInt<64>(0h0)
connect rom[1533], UInt<64>(0h0)
connect rom[1534], UInt<64>(0h0)
connect rom[1535], UInt<64>(0h0)
connect rom[1536], UInt<64>(0h0)
connect rom[1537], UInt<64>(0h0)
connect rom[1538], UInt<64>(0h0)
connect rom[1539], UInt<64>(0h0)
connect rom[1540], UInt<64>(0h0)
connect rom[1541], UInt<64>(0h0)
connect rom[1542], UInt<64>(0h0)
connect rom[1543], UInt<64>(0h0)
connect rom[1544], UInt<64>(0h0)
connect rom[1545], UInt<64>(0h0)
connect rom[1546], UInt<64>(0h0)
connect rom[1547], UInt<64>(0h0)
connect rom[1548], UInt<64>(0h0)
connect rom[1549], UInt<64>(0h0)
connect rom[1550], UInt<64>(0h0)
connect rom[1551], UInt<64>(0h0)
connect rom[1552], UInt<64>(0h0)
connect rom[1553], UInt<64>(0h0)
connect rom[1554], UInt<64>(0h0)
connect rom[1555], UInt<64>(0h0)
connect rom[1556], UInt<64>(0h0)
connect rom[1557], UInt<64>(0h0)
connect rom[1558], UInt<64>(0h0)
connect rom[1559], UInt<64>(0h0)
connect rom[1560], UInt<64>(0h0)
connect rom[1561], UInt<64>(0h0)
connect rom[1562], UInt<64>(0h0)
connect rom[1563], UInt<64>(0h0)
connect rom[1564], UInt<64>(0h0)
connect rom[1565], UInt<64>(0h0)
connect rom[1566], UInt<64>(0h0)
connect rom[1567], UInt<64>(0h0)
connect rom[1568], UInt<64>(0h0)
connect rom[1569], UInt<64>(0h0)
connect rom[1570], UInt<64>(0h0)
connect rom[1571], UInt<64>(0h0)
connect rom[1572], UInt<64>(0h0)
connect rom[1573], UInt<64>(0h0)
connect rom[1574], UInt<64>(0h0)
connect rom[1575], UInt<64>(0h0)
connect rom[1576], UInt<64>(0h0)
connect rom[1577], UInt<64>(0h0)
connect rom[1578], UInt<64>(0h0)
connect rom[1579], UInt<64>(0h0)
connect rom[1580], UInt<64>(0h0)
connect rom[1581], UInt<64>(0h0)
connect rom[1582], UInt<64>(0h0)
connect rom[1583], UInt<64>(0h0)
connect rom[1584], UInt<64>(0h0)
connect rom[1585], UInt<64>(0h0)
connect rom[1586], UInt<64>(0h0)
connect rom[1587], UInt<64>(0h0)
connect rom[1588], UInt<64>(0h0)
connect rom[1589], UInt<64>(0h0)
connect rom[1590], UInt<64>(0h0)
connect rom[1591], UInt<64>(0h0)
connect rom[1592], UInt<64>(0h0)
connect rom[1593], UInt<64>(0h0)
connect rom[1594], UInt<64>(0h0)
connect rom[1595], UInt<64>(0h0)
connect rom[1596], UInt<64>(0h0)
connect rom[1597], UInt<64>(0h0)
connect rom[1598], UInt<64>(0h0)
connect rom[1599], UInt<64>(0h0)
connect rom[1600], UInt<64>(0h0)
connect rom[1601], UInt<64>(0h0)
connect rom[1602], UInt<64>(0h0)
connect rom[1603], UInt<64>(0h0)
connect rom[1604], UInt<64>(0h0)
connect rom[1605], UInt<64>(0h0)
connect rom[1606], UInt<64>(0h0)
connect rom[1607], UInt<64>(0h0)
connect rom[1608], UInt<64>(0h0)
connect rom[1609], UInt<64>(0h0)
connect rom[1610], UInt<64>(0h0)
connect rom[1611], UInt<64>(0h0)
connect rom[1612], UInt<64>(0h0)
connect rom[1613], UInt<64>(0h0)
connect rom[1614], UInt<64>(0h0)
connect rom[1615], UInt<64>(0h0)
connect rom[1616], UInt<64>(0h0)
connect rom[1617], UInt<64>(0h0)
connect rom[1618], UInt<64>(0h0)
connect rom[1619], UInt<64>(0h0)
connect rom[1620], UInt<64>(0h0)
connect rom[1621], UInt<64>(0h0)
connect rom[1622], UInt<64>(0h0)
connect rom[1623], UInt<64>(0h0)
connect rom[1624], UInt<64>(0h0)
connect rom[1625], UInt<64>(0h0)
connect rom[1626], UInt<64>(0h0)
connect rom[1627], UInt<64>(0h0)
connect rom[1628], UInt<64>(0h0)
connect rom[1629], UInt<64>(0h0)
connect rom[1630], UInt<64>(0h0)
connect rom[1631], UInt<64>(0h0)
connect rom[1632], UInt<64>(0h0)
connect rom[1633], UInt<64>(0h0)
connect rom[1634], UInt<64>(0h0)
connect rom[1635], UInt<64>(0h0)
connect rom[1636], UInt<64>(0h0)
connect rom[1637], UInt<64>(0h0)
connect rom[1638], UInt<64>(0h0)
connect rom[1639], UInt<64>(0h0)
connect rom[1640], UInt<64>(0h0)
connect rom[1641], UInt<64>(0h0)
connect rom[1642], UInt<64>(0h0)
connect rom[1643], UInt<64>(0h0)
connect rom[1644], UInt<64>(0h0)
connect rom[1645], UInt<64>(0h0)
connect rom[1646], UInt<64>(0h0)
connect rom[1647], UInt<64>(0h0)
connect rom[1648], UInt<64>(0h0)
connect rom[1649], UInt<64>(0h0)
connect rom[1650], UInt<64>(0h0)
connect rom[1651], UInt<64>(0h0)
connect rom[1652], UInt<64>(0h0)
connect rom[1653], UInt<64>(0h0)
connect rom[1654], UInt<64>(0h0)
connect rom[1655], UInt<64>(0h0)
connect rom[1656], UInt<64>(0h0)
connect rom[1657], UInt<64>(0h0)
connect rom[1658], UInt<64>(0h0)
connect rom[1659], UInt<64>(0h0)
connect rom[1660], UInt<64>(0h0)
connect rom[1661], UInt<64>(0h0)
connect rom[1662], UInt<64>(0h0)
connect rom[1663], UInt<64>(0h0)
connect rom[1664], UInt<64>(0h0)
connect rom[1665], UInt<64>(0h0)
connect rom[1666], UInt<64>(0h0)
connect rom[1667], UInt<64>(0h0)
connect rom[1668], UInt<64>(0h0)
connect rom[1669], UInt<64>(0h0)
connect rom[1670], UInt<64>(0h0)
connect rom[1671], UInt<64>(0h0)
connect rom[1672], UInt<64>(0h0)
connect rom[1673], UInt<64>(0h0)
connect rom[1674], UInt<64>(0h0)
connect rom[1675], UInt<64>(0h0)
connect rom[1676], UInt<64>(0h0)
connect rom[1677], UInt<64>(0h0)
connect rom[1678], UInt<64>(0h0)
connect rom[1679], UInt<64>(0h0)
connect rom[1680], UInt<64>(0h0)
connect rom[1681], UInt<64>(0h0)
connect rom[1682], UInt<64>(0h0)
connect rom[1683], UInt<64>(0h0)
connect rom[1684], UInt<64>(0h0)
connect rom[1685], UInt<64>(0h0)
connect rom[1686], UInt<64>(0h0)
connect rom[1687], UInt<64>(0h0)
connect rom[1688], UInt<64>(0h0)
connect rom[1689], UInt<64>(0h0)
connect rom[1690], UInt<64>(0h0)
connect rom[1691], UInt<64>(0h0)
connect rom[1692], UInt<64>(0h0)
connect rom[1693], UInt<64>(0h0)
connect rom[1694], UInt<64>(0h0)
connect rom[1695], UInt<64>(0h0)
connect rom[1696], UInt<64>(0h0)
connect rom[1697], UInt<64>(0h0)
connect rom[1698], UInt<64>(0h0)
connect rom[1699], UInt<64>(0h0)
connect rom[1700], UInt<64>(0h0)
connect rom[1701], UInt<64>(0h0)
connect rom[1702], UInt<64>(0h0)
connect rom[1703], UInt<64>(0h0)
connect rom[1704], UInt<64>(0h0)
connect rom[1705], UInt<64>(0h0)
connect rom[1706], UInt<64>(0h0)
connect rom[1707], UInt<64>(0h0)
connect rom[1708], UInt<64>(0h0)
connect rom[1709], UInt<64>(0h0)
connect rom[1710], UInt<64>(0h0)
connect rom[1711], UInt<64>(0h0)
connect rom[1712], UInt<64>(0h0)
connect rom[1713], UInt<64>(0h0)
connect rom[1714], UInt<64>(0h0)
connect rom[1715], UInt<64>(0h0)
connect rom[1716], UInt<64>(0h0)
connect rom[1717], UInt<64>(0h0)
connect rom[1718], UInt<64>(0h0)
connect rom[1719], UInt<64>(0h0)
connect rom[1720], UInt<64>(0h0)
connect rom[1721], UInt<64>(0h0)
connect rom[1722], UInt<64>(0h0)
connect rom[1723], UInt<64>(0h0)
connect rom[1724], UInt<64>(0h0)
connect rom[1725], UInt<64>(0h0)
connect rom[1726], UInt<64>(0h0)
connect rom[1727], UInt<64>(0h0)
connect rom[1728], UInt<64>(0h0)
connect rom[1729], UInt<64>(0h0)
connect rom[1730], UInt<64>(0h0)
connect rom[1731], UInt<64>(0h0)
connect rom[1732], UInt<64>(0h0)
connect rom[1733], UInt<64>(0h0)
connect rom[1734], UInt<64>(0h0)
connect rom[1735], UInt<64>(0h0)
connect rom[1736], UInt<64>(0h0)
connect rom[1737], UInt<64>(0h0)
connect rom[1738], UInt<64>(0h0)
connect rom[1739], UInt<64>(0h0)
connect rom[1740], UInt<64>(0h0)
connect rom[1741], UInt<64>(0h0)
connect rom[1742], UInt<64>(0h0)
connect rom[1743], UInt<64>(0h0)
connect rom[1744], UInt<64>(0h0)
connect rom[1745], UInt<64>(0h0)
connect rom[1746], UInt<64>(0h0)
connect rom[1747], UInt<64>(0h0)
connect rom[1748], UInt<64>(0h0)
connect rom[1749], UInt<64>(0h0)
connect rom[1750], UInt<64>(0h0)
connect rom[1751], UInt<64>(0h0)
connect rom[1752], UInt<64>(0h0)
connect rom[1753], UInt<64>(0h0)
connect rom[1754], UInt<64>(0h0)
connect rom[1755], UInt<64>(0h0)
connect rom[1756], UInt<64>(0h0)
connect rom[1757], UInt<64>(0h0)
connect rom[1758], UInt<64>(0h0)
connect rom[1759], UInt<64>(0h0)
connect rom[1760], UInt<64>(0h0)
connect rom[1761], UInt<64>(0h0)
connect rom[1762], UInt<64>(0h0)
connect rom[1763], UInt<64>(0h0)
connect rom[1764], UInt<64>(0h0)
connect rom[1765], UInt<64>(0h0)
connect rom[1766], UInt<64>(0h0)
connect rom[1767], UInt<64>(0h0)
connect rom[1768], UInt<64>(0h0)
connect rom[1769], UInt<64>(0h0)
connect rom[1770], UInt<64>(0h0)
connect rom[1771], UInt<64>(0h0)
connect rom[1772], UInt<64>(0h0)
connect rom[1773], UInt<64>(0h0)
connect rom[1774], UInt<64>(0h0)
connect rom[1775], UInt<64>(0h0)
connect rom[1776], UInt<64>(0h0)
connect rom[1777], UInt<64>(0h0)
connect rom[1778], UInt<64>(0h0)
connect rom[1779], UInt<64>(0h0)
connect rom[1780], UInt<64>(0h0)
connect rom[1781], UInt<64>(0h0)
connect rom[1782], UInt<64>(0h0)
connect rom[1783], UInt<64>(0h0)
connect rom[1784], UInt<64>(0h0)
connect rom[1785], UInt<64>(0h0)
connect rom[1786], UInt<64>(0h0)
connect rom[1787], UInt<64>(0h0)
connect rom[1788], UInt<64>(0h0)
connect rom[1789], UInt<64>(0h0)
connect rom[1790], UInt<64>(0h0)
connect rom[1791], UInt<64>(0h0)
connect rom[1792], UInt<64>(0h0)
connect rom[1793], UInt<64>(0h0)
connect rom[1794], UInt<64>(0h0)
connect rom[1795], UInt<64>(0h0)
connect rom[1796], UInt<64>(0h0)
connect rom[1797], UInt<64>(0h0)
connect rom[1798], UInt<64>(0h0)
connect rom[1799], UInt<64>(0h0)
connect rom[1800], UInt<64>(0h0)
connect rom[1801], UInt<64>(0h0)
connect rom[1802], UInt<64>(0h0)
connect rom[1803], UInt<64>(0h0)
connect rom[1804], UInt<64>(0h0)
connect rom[1805], UInt<64>(0h0)
connect rom[1806], UInt<64>(0h0)
connect rom[1807], UInt<64>(0h0)
connect rom[1808], UInt<64>(0h0)
connect rom[1809], UInt<64>(0h0)
connect rom[1810], UInt<64>(0h0)
connect rom[1811], UInt<64>(0h0)
connect rom[1812], UInt<64>(0h0)
connect rom[1813], UInt<64>(0h0)
connect rom[1814], UInt<64>(0h0)
connect rom[1815], UInt<64>(0h0)
connect rom[1816], UInt<64>(0h0)
connect rom[1817], UInt<64>(0h0)
connect rom[1818], UInt<64>(0h0)
connect rom[1819], UInt<64>(0h0)
connect rom[1820], UInt<64>(0h0)
connect rom[1821], UInt<64>(0h0)
connect rom[1822], UInt<64>(0h0)
connect rom[1823], UInt<64>(0h0)
connect rom[1824], UInt<64>(0h0)
connect rom[1825], UInt<64>(0h0)
connect rom[1826], UInt<64>(0h0)
connect rom[1827], UInt<64>(0h0)
connect rom[1828], UInt<64>(0h0)
connect rom[1829], UInt<64>(0h0)
connect rom[1830], UInt<64>(0h0)
connect rom[1831], UInt<64>(0h0)
connect rom[1832], UInt<64>(0h0)
connect rom[1833], UInt<64>(0h0)
connect rom[1834], UInt<64>(0h0)
connect rom[1835], UInt<64>(0h0)
connect rom[1836], UInt<64>(0h0)
connect rom[1837], UInt<64>(0h0)
connect rom[1838], UInt<64>(0h0)
connect rom[1839], UInt<64>(0h0)
connect rom[1840], UInt<64>(0h0)
connect rom[1841], UInt<64>(0h0)
connect rom[1842], UInt<64>(0h0)
connect rom[1843], UInt<64>(0h0)
connect rom[1844], UInt<64>(0h0)
connect rom[1845], UInt<64>(0h0)
connect rom[1846], UInt<64>(0h0)
connect rom[1847], UInt<64>(0h0)
connect rom[1848], UInt<64>(0h0)
connect rom[1849], UInt<64>(0h0)
connect rom[1850], UInt<64>(0h0)
connect rom[1851], UInt<64>(0h0)
connect rom[1852], UInt<64>(0h0)
connect rom[1853], UInt<64>(0h0)
connect rom[1854], UInt<64>(0h0)
connect rom[1855], UInt<64>(0h0)
connect rom[1856], UInt<64>(0h0)
connect rom[1857], UInt<64>(0h0)
connect rom[1858], UInt<64>(0h0)
connect rom[1859], UInt<64>(0h0)
connect rom[1860], UInt<64>(0h0)
connect rom[1861], UInt<64>(0h0)
connect rom[1862], UInt<64>(0h0)
connect rom[1863], UInt<64>(0h0)
connect rom[1864], UInt<64>(0h0)
connect rom[1865], UInt<64>(0h0)
connect rom[1866], UInt<64>(0h0)
connect rom[1867], UInt<64>(0h0)
connect rom[1868], UInt<64>(0h0)
connect rom[1869], UInt<64>(0h0)
connect rom[1870], UInt<64>(0h0)
connect rom[1871], UInt<64>(0h0)
connect rom[1872], UInt<64>(0h0)
connect rom[1873], UInt<64>(0h0)
connect rom[1874], UInt<64>(0h0)
connect rom[1875], UInt<64>(0h0)
connect rom[1876], UInt<64>(0h0)
connect rom[1877], UInt<64>(0h0)
connect rom[1878], UInt<64>(0h0)
connect rom[1879], UInt<64>(0h0)
connect rom[1880], UInt<64>(0h0)
connect rom[1881], UInt<64>(0h0)
connect rom[1882], UInt<64>(0h0)
connect rom[1883], UInt<64>(0h0)
connect rom[1884], UInt<64>(0h0)
connect rom[1885], UInt<64>(0h0)
connect rom[1886], UInt<64>(0h0)
connect rom[1887], UInt<64>(0h0)
connect rom[1888], UInt<64>(0h0)
connect rom[1889], UInt<64>(0h0)
connect rom[1890], UInt<64>(0h0)
connect rom[1891], UInt<64>(0h0)
connect rom[1892], UInt<64>(0h0)
connect rom[1893], UInt<64>(0h0)
connect rom[1894], UInt<64>(0h0)
connect rom[1895], UInt<64>(0h0)
connect rom[1896], UInt<64>(0h0)
connect rom[1897], UInt<64>(0h0)
connect rom[1898], UInt<64>(0h0)
connect rom[1899], UInt<64>(0h0)
connect rom[1900], UInt<64>(0h0)
connect rom[1901], UInt<64>(0h0)
connect rom[1902], UInt<64>(0h0)
connect rom[1903], UInt<64>(0h0)
connect rom[1904], UInt<64>(0h0)
connect rom[1905], UInt<64>(0h0)
connect rom[1906], UInt<64>(0h0)
connect rom[1907], UInt<64>(0h0)
connect rom[1908], UInt<64>(0h0)
connect rom[1909], UInt<64>(0h0)
connect rom[1910], UInt<64>(0h0)
connect rom[1911], UInt<64>(0h0)
connect rom[1912], UInt<64>(0h0)
connect rom[1913], UInt<64>(0h0)
connect rom[1914], UInt<64>(0h0)
connect rom[1915], UInt<64>(0h0)
connect rom[1916], UInt<64>(0h0)
connect rom[1917], UInt<64>(0h0)
connect rom[1918], UInt<64>(0h0)
connect rom[1919], UInt<64>(0h0)
connect rom[1920], UInt<64>(0h0)
connect rom[1921], UInt<64>(0h0)
connect rom[1922], UInt<64>(0h0)
connect rom[1923], UInt<64>(0h0)
connect rom[1924], UInt<64>(0h0)
connect rom[1925], UInt<64>(0h0)
connect rom[1926], UInt<64>(0h0)
connect rom[1927], UInt<64>(0h0)
connect rom[1928], UInt<64>(0h0)
connect rom[1929], UInt<64>(0h0)
connect rom[1930], UInt<64>(0h0)
connect rom[1931], UInt<64>(0h0)
connect rom[1932], UInt<64>(0h0)
connect rom[1933], UInt<64>(0h0)
connect rom[1934], UInt<64>(0h0)
connect rom[1935], UInt<64>(0h0)
connect rom[1936], UInt<64>(0h0)
connect rom[1937], UInt<64>(0h0)
connect rom[1938], UInt<64>(0h0)
connect rom[1939], UInt<64>(0h0)
connect rom[1940], UInt<64>(0h0)
connect rom[1941], UInt<64>(0h0)
connect rom[1942], UInt<64>(0h0)
connect rom[1943], UInt<64>(0h0)
connect rom[1944], UInt<64>(0h0)
connect rom[1945], UInt<64>(0h0)
connect rom[1946], UInt<64>(0h0)
connect rom[1947], UInt<64>(0h0)
connect rom[1948], UInt<64>(0h0)
connect rom[1949], UInt<64>(0h0)
connect rom[1950], UInt<64>(0h0)
connect rom[1951], UInt<64>(0h0)
connect rom[1952], UInt<64>(0h0)
connect rom[1953], UInt<64>(0h0)
connect rom[1954], UInt<64>(0h0)
connect rom[1955], UInt<64>(0h0)
connect rom[1956], UInt<64>(0h0)
connect rom[1957], UInt<64>(0h0)
connect rom[1958], UInt<64>(0h0)
connect rom[1959], UInt<64>(0h0)
connect rom[1960], UInt<64>(0h0)
connect rom[1961], UInt<64>(0h0)
connect rom[1962], UInt<64>(0h0)
connect rom[1963], UInt<64>(0h0)
connect rom[1964], UInt<64>(0h0)
connect rom[1965], UInt<64>(0h0)
connect rom[1966], UInt<64>(0h0)
connect rom[1967], UInt<64>(0h0)
connect rom[1968], UInt<64>(0h0)
connect rom[1969], UInt<64>(0h0)
connect rom[1970], UInt<64>(0h0)
connect rom[1971], UInt<64>(0h0)
connect rom[1972], UInt<64>(0h0)
connect rom[1973], UInt<64>(0h0)
connect rom[1974], UInt<64>(0h0)
connect rom[1975], UInt<64>(0h0)
connect rom[1976], UInt<64>(0h0)
connect rom[1977], UInt<64>(0h0)
connect rom[1978], UInt<64>(0h0)
connect rom[1979], UInt<64>(0h0)
connect rom[1980], UInt<64>(0h0)
connect rom[1981], UInt<64>(0h0)
connect rom[1982], UInt<64>(0h0)
connect rom[1983], UInt<64>(0h0)
connect rom[1984], UInt<64>(0h0)
connect rom[1985], UInt<64>(0h0)
connect rom[1986], UInt<64>(0h0)
connect rom[1987], UInt<64>(0h0)
connect rom[1988], UInt<64>(0h0)
connect rom[1989], UInt<64>(0h0)
connect rom[1990], UInt<64>(0h0)
connect rom[1991], UInt<64>(0h0)
connect rom[1992], UInt<64>(0h0)
connect rom[1993], UInt<64>(0h0)
connect rom[1994], UInt<64>(0h0)
connect rom[1995], UInt<64>(0h0)
connect rom[1996], UInt<64>(0h0)
connect rom[1997], UInt<64>(0h0)
connect rom[1998], UInt<64>(0h0)
connect rom[1999], UInt<64>(0h0)
connect rom[2000], UInt<64>(0h0)
connect rom[2001], UInt<64>(0h0)
connect rom[2002], UInt<64>(0h0)
connect rom[2003], UInt<64>(0h0)
connect rom[2004], UInt<64>(0h0)
connect rom[2005], UInt<64>(0h0)
connect rom[2006], UInt<64>(0h0)
connect rom[2007], UInt<64>(0h0)
connect rom[2008], UInt<64>(0h0)
connect rom[2009], UInt<64>(0h0)
connect rom[2010], UInt<64>(0h0)
connect rom[2011], UInt<64>(0h0)
connect rom[2012], UInt<64>(0h0)
connect rom[2013], UInt<64>(0h0)
connect rom[2014], UInt<64>(0h0)
connect rom[2015], UInt<64>(0h0)
connect rom[2016], UInt<64>(0h0)
connect rom[2017], UInt<64>(0h0)
connect rom[2018], UInt<64>(0h0)
connect rom[2019], UInt<64>(0h0)
connect rom[2020], UInt<64>(0h0)
connect rom[2021], UInt<64>(0h0)
connect rom[2022], UInt<64>(0h0)
connect rom[2023], UInt<64>(0h0)
connect rom[2024], UInt<64>(0h0)
connect rom[2025], UInt<64>(0h0)
connect rom[2026], UInt<64>(0h0)
connect rom[2027], UInt<64>(0h0)
connect rom[2028], UInt<64>(0h0)
connect rom[2029], UInt<64>(0h0)
connect rom[2030], UInt<64>(0h0)
connect rom[2031], UInt<64>(0h0)
connect rom[2032], UInt<64>(0h0)
connect rom[2033], UInt<64>(0h0)
connect rom[2034], UInt<64>(0h0)
connect rom[2035], UInt<64>(0h0)
connect rom[2036], UInt<64>(0h0)
connect rom[2037], UInt<64>(0h0)
connect rom[2038], UInt<64>(0h0)
connect rom[2039], UInt<64>(0h0)
connect rom[2040], UInt<64>(0h0)
connect rom[2041], UInt<64>(0h0)
connect rom[2042], UInt<64>(0h0)
connect rom[2043], UInt<64>(0h0)
connect rom[2044], UInt<64>(0h0)
connect rom[2045], UInt<64>(0h0)
connect rom[2046], UInt<64>(0h0)
connect rom[2047], UInt<64>(0h0)
connect nodeIn.d.valid, nodeIn.a.valid
connect nodeIn.a.ready, nodeIn.d.ready
node index = bits(nodeIn.a.bits.address, 13, 3)
node high = bits(nodeIn.a.bits.address, 15, 14)
node _nodeIn_d_bits_T = orr(high)
node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index])
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h1)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, nodeIn.a.bits.size
connect nodeIn_d_bits_d.source, nodeIn.a.bits.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire [2047:0][63:0] _GEN =
'{64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h73747075727265,
64'h746E6900746E6572,
64'h61702D7470757272,
64'h65746E6900736B63,
64'h6F6C63007665646E,
64'h2C76637369720079,
64'h7469726F6972702D,
64'h78616D2C76637369,
64'h7200686361747461,
64'h2D67756265640064,
64'h65646E657478652D,
64'h7374707572726574,
64'h6E690073656D616E,
64'h2D74757074756F2D,
64'h6B636F6C6300736C,
64'h6C65632D6B636F6C,
64'h632300746E756F63,
64'h2D7268736D2C6576,
64'h6966697300646569,
64'h66696E752D656863,
64'h6163006C6576656C,
64'h2D65686361630073,
64'h656D616E2D676572,
64'h7365676E617200,
64'h656C646E61687000,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6900736C6C,
64'h65632D7470757272,
64'h65746E6923007469,
64'h6C70732D626C7400,
64'h7375746174730073,
64'h6E6F69676572706D,
64'h702C766373697200,
64'h79746972616C756E,
64'h617267706D702C76,
64'h6373697200617369,
64'h2C76637369720067,
64'h6572006568636163,
64'h2D6C6576656C2D74,
64'h78656E0065707974,
64'h2D756D6D00657A69,
64'h732D626C742D6900,
64'h737465732D626C74,
64'h2D6900657A69732D,
64'h65686361632D6900,
64'h737465732D656863,
64'h61632D6900657A69,
64'h732D6B636F6C622D,
64'h65686361632D6900,
64'h746E756F632D746E,
64'h696F706B61657262,
64'h2D636578652D6572,
64'h6177647261680065,
64'h7079745F65636976,
64'h656400657A69732D,
64'h626C742D64007374,
64'h65732D626C742D64,
64'h657A69732D6568,
64'h6361632D64007374,
64'h65732D6568636163,
64'h2D6400657A69732D,
64'h6B636F6C622D6568,
64'h6361632D64007963,
64'h6E6575716572662D,
64'h6B636F6C63007963,
64'h6E6575716572662D,
64'h65736162656D6974,
64'h687461702D7475,
64'h6F64747300306C61,
64'h69726573006C6564,
64'h6F6D00656C626974,
64'h61706D6F6300736C,
64'h6C65632D657A6973,
64'h2300736C6C65632D,
64'h7373657264646123,
64'h900000002000000,
64'h200000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h11002E010000,
64'h800000003000000,
64'h30303030,
64'h3131407265747465,
64'h732D74657365722D,
64'h656C697401000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000210,
64'h2E01000008000000,
64'h300000001000000,
64'h5502000004000000,
64'h300000011000000,
64'h4402000004000000,
64'h300000000000000,
64'h30747261752C6576,
64'h696669731B000000,
64'hD00000003000000,
64'h100000003D020000,
64'h400000003000000,
64'h30303030323030,
64'h31406C6169726573,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h73756273EB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375627301000000,
64'h2000000006D656D,
64'hA801000004000000,
64'h300000000000100,
64'h1002E010000,
64'h800000003000000,
64'h306D6F722C6576,
64'h696669731B000000,
64'hC00000003000000,
64'h3030303031,
64'h406D6F7201000000,
64'h200000010000000,
64'h9901000004000000,
64'h3000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h7375626DEB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626D01000000,
64'h200000011000000,
64'h9901000004000000,
64'h300000001000000,
64'h3202000004000000,
64'h300000001000000,
64'h1F02000004000000,
64'h3000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h40000000C,
64'h2E01000008000000,
64'h300000009000000,
64'hF0000000B000000,
64'hF00000009000000,
64'hE0000000B000000,
64'hE00000009000000,
64'hD0000000B000000,
64'hD00000009000000,
64'hC0000000B000000,
64'hC00000009000000,
64'hB0000000B000000,
64'hB00000009000000,
64'hA0000000B000000,
64'hA00000009000000,
64'h90000000B000000,
64'h900000009000000,
64'h80000000B000000,
64'h800000009000000,
64'h70000000B000000,
64'h700000009000000,
64'h60000000B000000,
64'h600000009000000,
64'h50000000B000000,
64'h500000009000000,
64'h40000000B000000,
64'h4000000FE010000,
64'hC000000003000000,
64'h8401000000000000,
64'h300000000306369,
64'h6C702C7663736972,
64'h1B0000000C000000,
64'h300000001000000,
64'h7301000004000000,
64'h300000000000000,
64'h3030303030306340,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6901000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'h100000002000000,
64'h10000000300000,
64'h2E01000008000000,
64'h300000000000030,
64'h726F7272652C6576,
64'h696669731B000000,
64'hE00000003000000,
64'h3030303340,
64'h6563697665642D72,
64'h6F72726501000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000000,
64'h2E01000008000000,
64'h3000000FFFF0000,
64'hF000000FFFF0000,
64'hE000000FFFF0000,
64'hD000000FFFF0000,
64'hC000000FFFF0000,
64'hB000000FFFF0000,
64'hA000000FFFF0000,
64'h9000000FFFF0000,
64'h8000000FFFF0000,
64'h7000000FFFF0000,
64'h6000000FFFF0000,
64'h5000000FFFF0000,
64'h4000000FE010000,
64'h6000000003000000,
64'h6761746A,
64'h1202000005000000,
64'h300000000000000,
64'h3331302D67756265,
64'h642C766373697200,
64'h3331302D67756265,
64'h642C657669666973,
64'h1B00000021000000,
64'h300000000003040,
64'h72656C6C6F72746E,
64'h6F632D6775626564,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h10002E010000,
64'h800000003000000,
64'h303030303031,
64'h4072657461672D6B,
64'h636F6C6301000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000002,
64'h2E01000008000000,
64'h300000007000000,
64'hF00000003000000,
64'hF00000007000000,
64'hE00000003000000,
64'hE00000007000000,
64'hD00000003000000,
64'hD00000007000000,
64'hC00000003000000,
64'hC00000007000000,
64'hB00000003000000,
64'hB00000007000000,
64'hA00000003000000,
64'hA00000007000000,
64'h900000003000000,
64'h900000007000000,
64'h800000003000000,
64'h800000007000000,
64'h700000003000000,
64'h700000007000000,
64'h600000003000000,
64'h600000007000000,
64'h500000003000000,
64'h500000007000000,
64'h400000003000000,
64'h4000000FE010000,
64'hC000000003000000,
64'h30746E69,
64'h6C632C7663736972,
64'h1B0000000D000000,
64'h300000000000030,
64'h3030303030324074,
64'h6E696C6301000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'h100000002000000,
64'h100000099010000,
64'h400000003000000,
64'hC000000CC010000,
64'h400000003000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1022E010000,
64'h800000003000000,
64'h300000002000000,
64'h1D01000008000000,
64'h300000000000000,
64'h6568636163003065,
64'h6863616365766973,
64'h756C636E692C6576,
64'h696669731B000000,
64'h1D00000003000000,
64'hBE01000000000000,
64'h300000000002000,
64'h8500000004000000,
64'h300000000100000,
64'h7800000004000000,
64'h300000002000000,
64'hB201000004000000,
64'h300000040000000,
64'h6500000004000000,
64'h300000000000000,
64'h3030303031303240,
64'h72656C6C6F72746E,
64'h6F632D6568636163,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1000002E010000,
64'h800000003000000,
64'h3030303140,
64'h6765722D73736572,
64'h6464612D746F6F62,
64'h1000000A1010000,
64'h3000000,
64'h7375622D656C70,
64'h6D697300636F732D,
64'h6472617970696863,
64'h2C7261622D626375,
64'h1B00000020000000,
64'h300000001000000,
64'hF00000004000000,
64'h300000001000000,
64'h4000000,
64'h300000000636F73,
64'h100000002000000,
64'h200000099010000,
64'h400000003000000,
64'h1000000080,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h30303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h300000099010000,
64'h400000003000000,
64'h64656C62,
64'h6173696462010000,
64'h900000003000000,
64'h10000000008,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h3066697468,
64'h2C6263751B000000,
64'hA00000003000000,
64'h66697468,
64'h100000002000000,
64'h200000002000000,
64'hF00000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'hB0000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000062,
64'h4075706301000000,
64'h200000002000000,
64'hE00000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'hA0000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000061,
64'h4075706301000000,
64'h200000002000000,
64'hD00000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h90000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000039,
64'h4075706301000000,
64'h200000002000000,
64'hC00000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h80000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000038,
64'h4075706301000000,
64'h200000002000000,
64'hB00000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h70000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000037,
64'h4075706301000000,
64'h200000002000000,
64'hA00000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h60000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000036,
64'h4075706301000000,
64'h200000002000000,
64'h900000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h50000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000035,
64'h4075706301000000,
64'h200000002000000,
64'h800000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h40000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000034,
64'h4075706301000000,
64'h200000002000000,
64'h700000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h30000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000033,
64'h4075706301000000,
64'h200000002000000,
64'h600000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h20000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000032,
64'h4075706301000000,
64'h200000002000000,
64'h500000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h10000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000031,
64'h4075706301000000,
64'h200000002000000,
64'h400000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h2E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'h9825000060020000,
64'h10000000,
64'h1100000028000000,
64'hD025000038000000,
64'h30280000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5350300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
TLMonitor_111 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_in_d_ready),
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (auto_in_a_valid),
.io_in_d_bits_size (auto_in_a_bits_size),
.io_in_d_bits_source (auto_in_a_bits_source)
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_d_ready; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_a_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_a_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_a_bits_source; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = (|(auto_in_a_bits_address[15:14])) ? 64'h0 : _GEN[auto_in_a_bits_address[13:3]]; // @[BootROM.scala:41:9, :55:34, :56:64, :57:{47,53}]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 2)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_17 = shr(io.in.a.bits.source, 2)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_30 = shr(io.in.a.bits.source, 2)
node _T_31 = eq(_T_30, UInt<2>(0h2))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<2>(0h3))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_66 = shr(io.in.a.bits.source, 2)
node _T_67 = eq(_T_66, UInt<1>(0h0))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_78 = shr(io.in.a.bits.source, 2)
node _T_79 = eq(_T_78, UInt<2>(0h2))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_84 = shr(io.in.a.bits.source, 2)
node _T_85 = eq(_T_84, UInt<2>(0h3))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = or(_T_100, _T_105)
node _T_137 = or(_T_136, _T_110)
node _T_138 = or(_T_137, _T_115)
node _T_139 = or(_T_138, _T_120)
node _T_140 = or(_T_139, _T_125)
node _T_141 = or(_T_140, _T_130)
node _T_142 = or(_T_141, _T_135)
node _T_143 = and(_T_95, _T_142)
node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = or(_T_150, _T_155)
node _T_157 = and(_T_145, _T_156)
node _T_158 = or(UInt<1>(0h0), _T_143)
node _T_159 = or(_T_158, _T_157)
node _T_160 = and(_T_94, _T_159)
node _T_161 = asUInt(reset)
node _T_162 = eq(_T_161, UInt<1>(0h0))
when _T_162 :
node _T_163 = eq(_T_160, UInt<1>(0h0))
when _T_163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_160, UInt<1>(0h1), "") : assert_2
node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_166 = and(_T_164, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_184 = cvt(_T_183)
node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000)))
node _T_186 = asSInt(_T_185)
node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0)))
node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_189 = cvt(_T_188)
node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000)))
node _T_191 = asSInt(_T_190)
node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0)))
node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = or(_T_172, _T_177)
node _T_219 = or(_T_218, _T_182)
node _T_220 = or(_T_219, _T_187)
node _T_221 = or(_T_220, _T_192)
node _T_222 = or(_T_221, _T_197)
node _T_223 = or(_T_222, _T_202)
node _T_224 = or(_T_223, _T_207)
node _T_225 = or(_T_224, _T_212)
node _T_226 = or(_T_225, _T_217)
node _T_227 = and(_T_167, _T_226)
node _T_228 = or(UInt<1>(0h0), _T_227)
node _T_229 = and(UInt<1>(0h0), _T_228)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_229, UInt<1>(0h1), "") : assert_3
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(source_ok, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_236, UInt<1>(0h1), "") : assert_5
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(is_aligned, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_243, UInt<1>(0h1), "") : assert_7
node _T_247 = not(io.in.a.bits.mask)
node _T_248 = eq(_T_247, UInt<1>(0h0))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_248, UInt<1>(0h1), "") : assert_8
node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_253 = asUInt(reset)
node _T_254 = eq(_T_253, UInt<1>(0h0))
when _T_254 :
node _T_255 = eq(_T_252, UInt<1>(0h0))
when _T_255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_252, UInt<1>(0h1), "") : assert_9
node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_256 :
node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_259 = and(_T_257, _T_258)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_260 = shr(io.in.a.bits.source, 2)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_263 = and(_T_261, _T_262)
node _T_264 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_265 = and(_T_263, _T_264)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h1))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<2>(0h2))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h3))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _T_284 = or(_T_265, _T_271)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_283)
node _T_287 = and(_T_259, _T_286)
node _T_288 = or(UInt<1>(0h0), _T_287)
node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_321 = cvt(_T_320)
node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000)))
node _T_323 = asSInt(_T_322)
node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = or(_T_294, _T_299)
node _T_331 = or(_T_330, _T_304)
node _T_332 = or(_T_331, _T_309)
node _T_333 = or(_T_332, _T_314)
node _T_334 = or(_T_333, _T_319)
node _T_335 = or(_T_334, _T_324)
node _T_336 = or(_T_335, _T_329)
node _T_337 = and(_T_289, _T_336)
node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_339 = or(UInt<1>(0h0), _T_338)
node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = or(_T_344, _T_349)
node _T_351 = and(_T_339, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_337)
node _T_353 = or(_T_352, _T_351)
node _T_354 = and(_T_288, _T_353)
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_354, UInt<1>(0h1), "") : assert_10
node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_368 = cvt(_T_367)
node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000)))
node _T_370 = asSInt(_T_369)
node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0)))
node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_388 = cvt(_T_387)
node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000)))
node _T_390 = asSInt(_T_389)
node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0)))
node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_393 = cvt(_T_392)
node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000)))
node _T_395 = asSInt(_T_394)
node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0)))
node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_398 = cvt(_T_397)
node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000)))
node _T_400 = asSInt(_T_399)
node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0)))
node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_403 = cvt(_T_402)
node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000)))
node _T_405 = asSInt(_T_404)
node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0)))
node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_408 = cvt(_T_407)
node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000)))
node _T_410 = asSInt(_T_409)
node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0)))
node _T_412 = or(_T_366, _T_371)
node _T_413 = or(_T_412, _T_376)
node _T_414 = or(_T_413, _T_381)
node _T_415 = or(_T_414, _T_386)
node _T_416 = or(_T_415, _T_391)
node _T_417 = or(_T_416, _T_396)
node _T_418 = or(_T_417, _T_401)
node _T_419 = or(_T_418, _T_406)
node _T_420 = or(_T_419, _T_411)
node _T_421 = and(_T_361, _T_420)
node _T_422 = or(UInt<1>(0h0), _T_421)
node _T_423 = and(UInt<1>(0h0), _T_422)
node _T_424 = asUInt(reset)
node _T_425 = eq(_T_424, UInt<1>(0h0))
when _T_425 :
node _T_426 = eq(_T_423, UInt<1>(0h0))
when _T_426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_423, UInt<1>(0h1), "") : assert_11
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(source_ok, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_430, UInt<1>(0h1), "") : assert_13
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(is_aligned, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_437, UInt<1>(0h1), "") : assert_15
node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_441, UInt<1>(0h1), "") : assert_16
node _T_445 = not(io.in.a.bits.mask)
node _T_446 = eq(_T_445, UInt<1>(0h0))
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_446, UInt<1>(0h1), "") : assert_17
node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_450, UInt<1>(0h1), "") : assert_18
node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_454 :
node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_457 = and(_T_455, _T_456)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_458 = shr(io.in.a.bits.source, 2)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_461 = and(_T_459, _T_460)
node _T_462 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_463 = and(_T_461, _T_462)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_464 = shr(io.in.a.bits.source, 2)
node _T_465 = eq(_T_464, UInt<1>(0h1))
node _T_466 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_467 = and(_T_465, _T_466)
node _T_468 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_469 = and(_T_467, _T_468)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_470 = shr(io.in.a.bits.source, 2)
node _T_471 = eq(_T_470, UInt<2>(0h2))
node _T_472 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_473 = and(_T_471, _T_472)
node _T_474 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_475 = and(_T_473, _T_474)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_476 = shr(io.in.a.bits.source, 2)
node _T_477 = eq(_T_476, UInt<2>(0h3))
node _T_478 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_479 = and(_T_477, _T_478)
node _T_480 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_481 = and(_T_479, _T_480)
node _T_482 = or(_T_463, _T_469)
node _T_483 = or(_T_482, _T_475)
node _T_484 = or(_T_483, _T_481)
node _T_485 = and(_T_457, _T_484)
node _T_486 = or(UInt<1>(0h0), _T_485)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_486, UInt<1>(0h1), "") : assert_19
node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_492 = and(_T_490, _T_491)
node _T_493 = or(UInt<1>(0h0), _T_492)
node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_495 = cvt(_T_494)
node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000)))
node _T_497 = asSInt(_T_496)
node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0)))
node _T_499 = and(_T_493, _T_498)
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_502 = and(_T_500, _T_501)
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = or(_T_508, _T_513)
node _T_550 = or(_T_549, _T_518)
node _T_551 = or(_T_550, _T_523)
node _T_552 = or(_T_551, _T_528)
node _T_553 = or(_T_552, _T_533)
node _T_554 = or(_T_553, _T_538)
node _T_555 = or(_T_554, _T_543)
node _T_556 = or(_T_555, _T_548)
node _T_557 = and(_T_503, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_499)
node _T_559 = or(_T_558, _T_557)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_559, UInt<1>(0h1), "") : assert_20
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(source_ok, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(is_aligned, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_569, UInt<1>(0h1), "") : assert_23
node _T_573 = eq(io.in.a.bits.mask, mask)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_573, UInt<1>(0h1), "") : assert_24
node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_577, UInt<1>(0h1), "") : assert_25
node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_581 :
node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_584 = and(_T_582, _T_583)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_585 = shr(io.in.a.bits.source, 2)
node _T_586 = eq(_T_585, UInt<1>(0h0))
node _T_587 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_588 = and(_T_586, _T_587)
node _T_589 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_590 = and(_T_588, _T_589)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<1>(0h1))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<2>(0h2))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<2>(0h3))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _T_609 = or(_T_590, _T_596)
node _T_610 = or(_T_609, _T_602)
node _T_611 = or(_T_610, _T_608)
node _T_612 = and(_T_584, _T_611)
node _T_613 = or(UInt<1>(0h0), _T_612)
node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_616 = and(_T_614, _T_615)
node _T_617 = or(UInt<1>(0h0), _T_616)
node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = and(_T_617, _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_634 = cvt(_T_633)
node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000)))
node _T_636 = asSInt(_T_635)
node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0)))
node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_639 = cvt(_T_638)
node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000)))
node _T_641 = asSInt(_T_640)
node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0)))
node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_644 = cvt(_T_643)
node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000)))
node _T_646 = asSInt(_T_645)
node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0)))
node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_649 = cvt(_T_648)
node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000)))
node _T_651 = asSInt(_T_650)
node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0)))
node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = or(_T_632, _T_637)
node _T_669 = or(_T_668, _T_642)
node _T_670 = or(_T_669, _T_647)
node _T_671 = or(_T_670, _T_652)
node _T_672 = or(_T_671, _T_657)
node _T_673 = or(_T_672, _T_662)
node _T_674 = or(_T_673, _T_667)
node _T_675 = and(_T_627, _T_674)
node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_678 = cvt(_T_677)
node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000)))
node _T_680 = asSInt(_T_679)
node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0)))
node _T_682 = and(_T_676, _T_681)
node _T_683 = or(UInt<1>(0h0), _T_623)
node _T_684 = or(_T_683, _T_675)
node _T_685 = or(_T_684, _T_682)
node _T_686 = and(_T_613, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_686, UInt<1>(0h1), "") : assert_26
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(source_ok, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_693 = asUInt(reset)
node _T_694 = eq(_T_693, UInt<1>(0h0))
when _T_694 :
node _T_695 = eq(is_aligned, UInt<1>(0h0))
when _T_695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_696, UInt<1>(0h1), "") : assert_29
node _T_700 = eq(io.in.a.bits.mask, mask)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_700, UInt<1>(0h1), "") : assert_30
node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_704 :
node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_707 = and(_T_705, _T_706)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_708 = shr(io.in.a.bits.source, 2)
node _T_709 = eq(_T_708, UInt<1>(0h0))
node _T_710 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_711 = and(_T_709, _T_710)
node _T_712 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_713 = and(_T_711, _T_712)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_714 = shr(io.in.a.bits.source, 2)
node _T_715 = eq(_T_714, UInt<1>(0h1))
node _T_716 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_717 = and(_T_715, _T_716)
node _T_718 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_719 = and(_T_717, _T_718)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_720 = shr(io.in.a.bits.source, 2)
node _T_721 = eq(_T_720, UInt<2>(0h2))
node _T_722 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_723 = and(_T_721, _T_722)
node _T_724 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_725 = and(_T_723, _T_724)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_726 = shr(io.in.a.bits.source, 2)
node _T_727 = eq(_T_726, UInt<2>(0h3))
node _T_728 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_729 = and(_T_727, _T_728)
node _T_730 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_731 = and(_T_729, _T_730)
node _T_732 = or(_T_713, _T_719)
node _T_733 = or(_T_732, _T_725)
node _T_734 = or(_T_733, _T_731)
node _T_735 = and(_T_707, _T_734)
node _T_736 = or(UInt<1>(0h0), _T_735)
node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_739 = and(_T_737, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = and(_T_740, _T_745)
node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_757 = cvt(_T_756)
node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000)))
node _T_759 = asSInt(_T_758)
node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0)))
node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_762 = cvt(_T_761)
node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000)))
node _T_764 = asSInt(_T_763)
node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0)))
node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_772 = cvt(_T_771)
node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000)))
node _T_774 = asSInt(_T_773)
node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0)))
node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_777 = cvt(_T_776)
node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000)))
node _T_779 = asSInt(_T_778)
node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0)))
node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_782 = cvt(_T_781)
node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000)))
node _T_784 = asSInt(_T_783)
node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0)))
node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_787 = cvt(_T_786)
node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000)))
node _T_789 = asSInt(_T_788)
node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0)))
node _T_791 = or(_T_755, _T_760)
node _T_792 = or(_T_791, _T_765)
node _T_793 = or(_T_792, _T_770)
node _T_794 = or(_T_793, _T_775)
node _T_795 = or(_T_794, _T_780)
node _T_796 = or(_T_795, _T_785)
node _T_797 = or(_T_796, _T_790)
node _T_798 = and(_T_750, _T_797)
node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = and(_T_799, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_746)
node _T_807 = or(_T_806, _T_798)
node _T_808 = or(_T_807, _T_805)
node _T_809 = and(_T_736, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_809, UInt<1>(0h1), "") : assert_31
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(source_ok, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(is_aligned, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_819, UInt<1>(0h1), "") : assert_34
node _T_823 = not(mask)
node _T_824 = and(io.in.a.bits.mask, _T_823)
node _T_825 = eq(_T_824, UInt<1>(0h0))
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(_T_825, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_825, UInt<1>(0h1), "") : assert_35
node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_829 :
node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_832 = and(_T_830, _T_831)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<1>(0h1))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<2>(0h2))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<2>(0h3))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _T_857 = or(_T_838, _T_844)
node _T_858 = or(_T_857, _T_850)
node _T_859 = or(_T_858, _T_856)
node _T_860 = and(_T_832, _T_859)
node _T_861 = or(UInt<1>(0h0), _T_860)
node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _T_865 = or(UInt<1>(0h0), _T_864)
node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_867 = cvt(_T_866)
node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000)))
node _T_869 = asSInt(_T_868)
node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0)))
node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_872 = cvt(_T_871)
node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000)))
node _T_874 = asSInt(_T_873)
node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0)))
node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_877 = cvt(_T_876)
node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000)))
node _T_879 = asSInt(_T_878)
node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0)))
node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_882 = cvt(_T_881)
node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000)))
node _T_884 = asSInt(_T_883)
node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0)))
node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<27>(0h4000000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = or(_T_870, _T_875)
node _T_902 = or(_T_901, _T_880)
node _T_903 = or(_T_902, _T_885)
node _T_904 = or(_T_903, _T_890)
node _T_905 = or(_T_904, _T_895)
node _T_906 = or(_T_905, _T_900)
node _T_907 = and(_T_865, _T_906)
node _T_908 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_909 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<17>(0h10000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = and(_T_908, _T_913)
node _T_915 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_916 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_917 = and(_T_915, _T_916)
node _T_918 = or(UInt<1>(0h0), _T_917)
node _T_919 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<17>(0h10000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<29>(0h10000000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = or(_T_923, _T_928)
node _T_930 = and(_T_918, _T_929)
node _T_931 = or(UInt<1>(0h0), _T_907)
node _T_932 = or(_T_931, _T_914)
node _T_933 = or(_T_932, _T_930)
node _T_934 = and(_T_861, _T_933)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_934, UInt<1>(0h1), "") : assert_36
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(source_ok, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(is_aligned, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_944 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_944, UInt<1>(0h1), "") : assert_39
node _T_948 = eq(io.in.a.bits.mask, mask)
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_948, UInt<1>(0h1), "") : assert_40
node _T_952 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_952 :
node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_954 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_955 = and(_T_953, _T_954)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_956 = shr(io.in.a.bits.source, 2)
node _T_957 = eq(_T_956, UInt<1>(0h0))
node _T_958 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_959 = and(_T_957, _T_958)
node _T_960 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_961 = and(_T_959, _T_960)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_962 = shr(io.in.a.bits.source, 2)
node _T_963 = eq(_T_962, UInt<1>(0h1))
node _T_964 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_965 = and(_T_963, _T_964)
node _T_966 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_967 = and(_T_965, _T_966)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_968 = shr(io.in.a.bits.source, 2)
node _T_969 = eq(_T_968, UInt<2>(0h2))
node _T_970 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_971 = and(_T_969, _T_970)
node _T_972 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_973 = and(_T_971, _T_972)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_974 = shr(io.in.a.bits.source, 2)
node _T_975 = eq(_T_974, UInt<2>(0h3))
node _T_976 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_977 = and(_T_975, _T_976)
node _T_978 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_979 = and(_T_977, _T_978)
node _T_980 = or(_T_961, _T_967)
node _T_981 = or(_T_980, _T_973)
node _T_982 = or(_T_981, _T_979)
node _T_983 = and(_T_955, _T_982)
node _T_984 = or(UInt<1>(0h0), _T_983)
node _T_985 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_986 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_987 = and(_T_985, _T_986)
node _T_988 = or(UInt<1>(0h0), _T_987)
node _T_989 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<14>(0h2000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<13>(0h1000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1000 = cvt(_T_999)
node _T_1001 = and(_T_1000, asSInt(UInt<18>(0h2f000)))
node _T_1002 = asSInt(_T_1001)
node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0)))
node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1015 = cvt(_T_1014)
node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000)))
node _T_1017 = asSInt(_T_1016)
node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0)))
node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1020 = cvt(_T_1019)
node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000)))
node _T_1022 = asSInt(_T_1021)
node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0)))
node _T_1024 = or(_T_993, _T_998)
node _T_1025 = or(_T_1024, _T_1003)
node _T_1026 = or(_T_1025, _T_1008)
node _T_1027 = or(_T_1026, _T_1013)
node _T_1028 = or(_T_1027, _T_1018)
node _T_1029 = or(_T_1028, _T_1023)
node _T_1030 = and(_T_988, _T_1029)
node _T_1031 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1032 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1033 = cvt(_T_1032)
node _T_1034 = and(_T_1033, asSInt(UInt<17>(0h10000)))
node _T_1035 = asSInt(_T_1034)
node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0)))
node _T_1037 = and(_T_1031, _T_1036)
node _T_1038 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1039 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = or(UInt<1>(0h0), _T_1040)
node _T_1042 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1043 = cvt(_T_1042)
node _T_1044 = and(_T_1043, asSInt(UInt<17>(0h10000)))
node _T_1045 = asSInt(_T_1044)
node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0)))
node _T_1047 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1048 = cvt(_T_1047)
node _T_1049 = and(_T_1048, asSInt(UInt<29>(0h10000000)))
node _T_1050 = asSInt(_T_1049)
node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0)))
node _T_1052 = or(_T_1046, _T_1051)
node _T_1053 = and(_T_1041, _T_1052)
node _T_1054 = or(UInt<1>(0h0), _T_1030)
node _T_1055 = or(_T_1054, _T_1037)
node _T_1056 = or(_T_1055, _T_1053)
node _T_1057 = and(_T_984, _T_1056)
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_41
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(source_ok, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(is_aligned, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_44
node _T_1071 = eq(io.in.a.bits.mask, mask)
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_45
node _T_1075 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1075 :
node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1078 = and(_T_1076, _T_1077)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1079 = shr(io.in.a.bits.source, 2)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
node _T_1081 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1084 = and(_T_1082, _T_1083)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1085 = shr(io.in.a.bits.source, 2)
node _T_1086 = eq(_T_1085, UInt<1>(0h1))
node _T_1087 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1088 = and(_T_1086, _T_1087)
node _T_1089 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1090 = and(_T_1088, _T_1089)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1091 = shr(io.in.a.bits.source, 2)
node _T_1092 = eq(_T_1091, UInt<2>(0h2))
node _T_1093 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1094 = and(_T_1092, _T_1093)
node _T_1095 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1096 = and(_T_1094, _T_1095)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1097 = shr(io.in.a.bits.source, 2)
node _T_1098 = eq(_T_1097, UInt<2>(0h3))
node _T_1099 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1102 = and(_T_1100, _T_1101)
node _T_1103 = or(_T_1084, _T_1090)
node _T_1104 = or(_T_1103, _T_1096)
node _T_1105 = or(_T_1104, _T_1102)
node _T_1106 = and(_T_1078, _T_1105)
node _T_1107 = or(UInt<1>(0h0), _T_1106)
node _T_1108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1110 = and(_T_1108, _T_1109)
node _T_1111 = or(UInt<1>(0h0), _T_1110)
node _T_1112 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1113 = cvt(_T_1112)
node _T_1114 = and(_T_1113, asSInt(UInt<13>(0h1000)))
node _T_1115 = asSInt(_T_1114)
node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0)))
node _T_1117 = and(_T_1111, _T_1116)
node _T_1118 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1119 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<14>(0h2000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1130 = cvt(_T_1129)
node _T_1131 = and(_T_1130, asSInt(UInt<18>(0h2f000)))
node _T_1132 = asSInt(_T_1131)
node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0)))
node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1135 = cvt(_T_1134)
node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000)))
node _T_1137 = asSInt(_T_1136)
node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0)))
node _T_1139 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1140 = cvt(_T_1139)
node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000)))
node _T_1142 = asSInt(_T_1141)
node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1145 = cvt(_T_1144)
node _T_1146 = and(_T_1145, asSInt(UInt<27>(0h4000000)))
node _T_1147 = asSInt(_T_1146)
node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1150 = cvt(_T_1149)
node _T_1151 = and(_T_1150, asSInt(UInt<13>(0h1000)))
node _T_1152 = asSInt(_T_1151)
node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0)))
node _T_1154 = or(_T_1123, _T_1128)
node _T_1155 = or(_T_1154, _T_1133)
node _T_1156 = or(_T_1155, _T_1138)
node _T_1157 = or(_T_1156, _T_1143)
node _T_1158 = or(_T_1157, _T_1148)
node _T_1159 = or(_T_1158, _T_1153)
node _T_1160 = and(_T_1118, _T_1159)
node _T_1161 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1162 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1163 = and(_T_1161, _T_1162)
node _T_1164 = or(UInt<1>(0h0), _T_1163)
node _T_1165 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1166 = cvt(_T_1165)
node _T_1167 = and(_T_1166, asSInt(UInt<17>(0h10000)))
node _T_1168 = asSInt(_T_1167)
node _T_1169 = eq(_T_1168, asSInt(UInt<1>(0h0)))
node _T_1170 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1171 = cvt(_T_1170)
node _T_1172 = and(_T_1171, asSInt(UInt<29>(0h10000000)))
node _T_1173 = asSInt(_T_1172)
node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0)))
node _T_1175 = or(_T_1169, _T_1174)
node _T_1176 = and(_T_1164, _T_1175)
node _T_1177 = or(UInt<1>(0h0), _T_1117)
node _T_1178 = or(_T_1177, _T_1160)
node _T_1179 = or(_T_1178, _T_1176)
node _T_1180 = and(_T_1107, _T_1179)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_46
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(source_ok, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(is_aligned, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1190 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_49
node _T_1194 = eq(io.in.a.bits.mask, mask)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_50
node _T_1198 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1202 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 2)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 2)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_1206 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1206 :
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(source_ok_1, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1210 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1211 = asUInt(reset)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = eq(_T_1210, UInt<1>(0h0))
when _T_1213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1210, UInt<1>(0h1), "") : assert_54
node _T_1214 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_55
node _T_1218 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_56
node _T_1222 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1223 = asUInt(reset)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
when _T_1224 :
node _T_1225 = eq(_T_1222, UInt<1>(0h0))
when _T_1225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1222, UInt<1>(0h1), "") : assert_57
node _T_1226 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1226 :
node _T_1227 = asUInt(reset)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
when _T_1228 :
node _T_1229 = eq(source_ok_1, UInt<1>(0h0))
when _T_1229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(sink_ok, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1233 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_60
node _T_1237 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_61
node _T_1241 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_62
node _T_1245 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_63
node _T_1249 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1250 = or(UInt<1>(0h1), _T_1249)
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(_T_1250, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1250, UInt<1>(0h1), "") : assert_64
node _T_1254 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1254 :
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(source_ok_1, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(sink_ok, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1261 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_67
node _T_1265 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_68
node _T_1269 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_69
node _T_1273 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1274 = or(_T_1273, io.in.d.bits.corrupt)
node _T_1275 = asUInt(reset)
node _T_1276 = eq(_T_1275, UInt<1>(0h0))
when _T_1276 :
node _T_1277 = eq(_T_1274, UInt<1>(0h0))
when _T_1277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1274, UInt<1>(0h1), "") : assert_70
node _T_1278 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1279 = or(UInt<1>(0h1), _T_1278)
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_71
node _T_1283 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(source_ok_1, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1287 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_73
node _T_1291 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_74
node _T_1295 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1296 = or(UInt<1>(0h1), _T_1295)
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_75
node _T_1300 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1300 :
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(source_ok_1, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1304 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(_T_1304, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1304, UInt<1>(0h1), "") : assert_77
node _T_1308 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1309 = or(_T_1308, io.in.d.bits.corrupt)
node _T_1310 = asUInt(reset)
node _T_1311 = eq(_T_1310, UInt<1>(0h0))
when _T_1311 :
node _T_1312 = eq(_T_1309, UInt<1>(0h0))
when _T_1312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1309, UInt<1>(0h1), "") : assert_78
node _T_1313 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1314 = or(UInt<1>(0h1), _T_1313)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_79
node _T_1318 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1318 :
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(source_ok_1, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1322 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_81
node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_82
node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1331 = or(UInt<1>(0h1), _T_1330)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1335 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1339 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1343 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1347 = eq(a_first, UInt<1>(0h0))
node _T_1348 = and(io.in.a.valid, _T_1347)
when _T_1348 :
node _T_1349 = eq(io.in.a.bits.opcode, opcode)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_87
node _T_1353 = eq(io.in.a.bits.param, param)
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_88
node _T_1357 = eq(io.in.a.bits.size, size)
node _T_1358 = asUInt(reset)
node _T_1359 = eq(_T_1358, UInt<1>(0h0))
when _T_1359 :
node _T_1360 = eq(_T_1357, UInt<1>(0h0))
when _T_1360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1357, UInt<1>(0h1), "") : assert_89
node _T_1361 = eq(io.in.a.bits.source, source)
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(_T_1361, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1361, UInt<1>(0h1), "") : assert_90
node _T_1365 = eq(io.in.a.bits.address, address)
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_91
node _T_1369 = and(io.in.a.ready, io.in.a.valid)
node _T_1370 = and(_T_1369, a_first)
when _T_1370 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1371 = eq(d_first, UInt<1>(0h0))
node _T_1372 = and(io.in.d.valid, _T_1371)
when _T_1372 :
node _T_1373 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(_T_1373, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1373, UInt<1>(0h1), "") : assert_92
node _T_1377 = eq(io.in.d.bits.param, param_1)
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_93
node _T_1381 = eq(io.in.d.bits.size, size_1)
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(_T_1381, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1381, UInt<1>(0h1), "") : assert_94
node _T_1385 = eq(io.in.d.bits.source, source_1)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_95
node _T_1389 = eq(io.in.d.bits.sink, sink)
node _T_1390 = asUInt(reset)
node _T_1391 = eq(_T_1390, UInt<1>(0h0))
when _T_1391 :
node _T_1392 = eq(_T_1389, UInt<1>(0h0))
when _T_1392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1389, UInt<1>(0h1), "") : assert_96
node _T_1393 = eq(io.in.d.bits.denied, denied)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_97
node _T_1397 = and(io.in.d.ready, io.in.d.valid)
node _T_1398 = and(_T_1397, d_first)
when _T_1398 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1399 = and(io.in.a.valid, a_first_1)
node _T_1400 = and(_T_1399, UInt<1>(0h1))
when _T_1400 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1401 = and(io.in.a.ready, io.in.a.valid)
node _T_1402 = and(_T_1401, a_first_1)
node _T_1403 = and(_T_1402, UInt<1>(0h1))
when _T_1403 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1404 = dshr(inflight, io.in.a.bits.source)
node _T_1405 = bits(_T_1404, 0, 0)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1410 = and(io.in.d.valid, d_first_1)
node _T_1411 = and(_T_1410, UInt<1>(0h1))
node _T_1412 = eq(d_release_ack, UInt<1>(0h0))
node _T_1413 = and(_T_1411, _T_1412)
when _T_1413 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1414 = and(io.in.d.ready, io.in.d.valid)
node _T_1415 = and(_T_1414, d_first_1)
node _T_1416 = and(_T_1415, UInt<1>(0h1))
node _T_1417 = eq(d_release_ack, UInt<1>(0h0))
node _T_1418 = and(_T_1416, _T_1417)
when _T_1418 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1419 = and(io.in.d.valid, d_first_1)
node _T_1420 = and(_T_1419, UInt<1>(0h1))
node _T_1421 = eq(d_release_ack, UInt<1>(0h0))
node _T_1422 = and(_T_1420, _T_1421)
when _T_1422 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1423 = dshr(inflight, io.in.d.bits.source)
node _T_1424 = bits(_T_1423, 0, 0)
node _T_1425 = or(_T_1424, same_cycle_resp)
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1429 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1431 = or(_T_1429, _T_1430)
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_100
node _T_1435 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_101
else :
node _T_1439 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1440 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1441 = or(_T_1439, _T_1440)
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_102
node _T_1445 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1446 = asUInt(reset)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = eq(_T_1445, UInt<1>(0h0))
when _T_1448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1445, UInt<1>(0h1), "") : assert_103
node _T_1449 = and(io.in.d.valid, d_first_1)
node _T_1450 = and(_T_1449, a_first_1)
node _T_1451 = and(_T_1450, io.in.a.valid)
node _T_1452 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1453 = and(_T_1451, _T_1452)
node _T_1454 = eq(d_release_ack, UInt<1>(0h0))
node _T_1455 = and(_T_1453, _T_1454)
when _T_1455 :
node _T_1456 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1457 = or(_T_1456, io.in.a.ready)
node _T_1458 = asUInt(reset)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
when _T_1459 :
node _T_1460 = eq(_T_1457, UInt<1>(0h0))
when _T_1460 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1457, UInt<1>(0h1), "") : assert_104
node _T_1461 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1462 = orr(a_set_wo_ready)
node _T_1463 = eq(_T_1462, UInt<1>(0h0))
node _T_1464 = or(_T_1461, _T_1463)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_36
node _T_1468 = orr(inflight)
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
node _T_1470 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1471 = or(_T_1469, _T_1470)
node _T_1472 = lt(watchdog, plusarg_reader.out)
node _T_1473 = or(_T_1471, _T_1472)
node _T_1474 = asUInt(reset)
node _T_1475 = eq(_T_1474, UInt<1>(0h0))
when _T_1475 :
node _T_1476 = eq(_T_1473, UInt<1>(0h0))
when _T_1476 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1473, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1477 = and(io.in.a.ready, io.in.a.valid)
node _T_1478 = and(io.in.d.ready, io.in.d.valid)
node _T_1479 = or(_T_1477, _T_1478)
when _T_1479 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1480 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1481 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1482 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1483 = and(_T_1481, _T_1482)
node _T_1484 = and(_T_1480, _T_1483)
when _T_1484 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1485 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1486 = and(_T_1485, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1487 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1488 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1489 = and(_T_1487, _T_1488)
node _T_1490 = and(_T_1486, _T_1489)
when _T_1490 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1491 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1492 = bits(_T_1491, 0, 0)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
node _T_1494 = asUInt(reset)
node _T_1495 = eq(_T_1494, UInt<1>(0h0))
when _T_1495 :
node _T_1496 = eq(_T_1493, UInt<1>(0h0))
when _T_1496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1493, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1497 = and(io.in.d.valid, d_first_2)
node _T_1498 = and(_T_1497, UInt<1>(0h1))
node _T_1499 = and(_T_1498, d_release_ack_1)
when _T_1499 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1500 = and(io.in.d.ready, io.in.d.valid)
node _T_1501 = and(_T_1500, d_first_2)
node _T_1502 = and(_T_1501, UInt<1>(0h1))
node _T_1503 = and(_T_1502, d_release_ack_1)
when _T_1503 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1504 = and(io.in.d.valid, d_first_2)
node _T_1505 = and(_T_1504, UInt<1>(0h1))
node _T_1506 = and(_T_1505, d_release_ack_1)
when _T_1506 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1507 = dshr(inflight_1, io.in.d.bits.source)
node _T_1508 = bits(_T_1507, 0, 0)
node _T_1509 = or(_T_1508, same_cycle_resp_1)
node _T_1510 = asUInt(reset)
node _T_1511 = eq(_T_1510, UInt<1>(0h0))
when _T_1511 :
node _T_1512 = eq(_T_1509, UInt<1>(0h0))
when _T_1512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1509, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1513 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1514 = asUInt(reset)
node _T_1515 = eq(_T_1514, UInt<1>(0h0))
when _T_1515 :
node _T_1516 = eq(_T_1513, UInt<1>(0h0))
when _T_1516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1513, UInt<1>(0h1), "") : assert_109
else :
node _T_1517 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1518 = asUInt(reset)
node _T_1519 = eq(_T_1518, UInt<1>(0h0))
when _T_1519 :
node _T_1520 = eq(_T_1517, UInt<1>(0h0))
when _T_1520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1517, UInt<1>(0h1), "") : assert_110
node _T_1521 = and(io.in.d.valid, d_first_2)
node _T_1522 = and(_T_1521, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1523 = and(_T_1522, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1524 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1525 = and(_T_1523, _T_1524)
node _T_1526 = and(_T_1525, d_release_ack_1)
node _T_1527 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1528 = and(_T_1526, _T_1527)
when _T_1528 :
node _T_1529 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1530 = or(_T_1529, _WIRE_23.ready)
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_111
node _T_1534 = orr(c_set_wo_ready)
when _T_1534 :
node _T_1535 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_37
node _T_1539 = orr(inflight_1)
node _T_1540 = eq(_T_1539, UInt<1>(0h0))
node _T_1541 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1542 = or(_T_1540, _T_1541)
node _T_1543 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1544 = or(_T_1542, _T_1543)
node _T_1545 = asUInt(reset)
node _T_1546 = eq(_T_1545, UInt<1>(0h0))
when _T_1546 :
node _T_1547 = eq(_T_1544, UInt<1>(0h0))
when _T_1547 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1544, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1548 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1549 = and(io.in.d.ready, io.in.d.valid)
node _T_1550 = or(_T_1548, _T_1549)
when _T_1550 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_18( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1477 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1477; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1477; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1550 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1550; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1550; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1550; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1403 = _T_1477 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1403 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1403 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1403 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1403 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1403 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1449 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1449 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1418 = _T_1550 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1418 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1418 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1418 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1521 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1521 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1503 = _T_1550 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1503 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1503 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1503 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module SBToTL :
input clock : Clock
input reset : Reset
output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}}
output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>}
input rf_reset : Reset
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
regreset sbState : UInt, clock, reset, UInt<1>(0h0)
inst d_q of Queue2_TLBundleD_a32d8s1k3z4u
connect d_q.clock, clock
connect d_q.reset, reset
connect d_q.io.enq.valid, nodeOut.d.valid
connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect d_q.io.enq.bits.data, nodeOut.d.bits.data
connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect d_q.io.enq.bits.source, nodeOut.d.bits.source
connect d_q.io.enq.bits.size, nodeOut.d.bits.size
connect d_q.io.enq.bits.param, nodeOut.d.bits.param
connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, d_q.io.enq.ready
node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3))
node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4))
node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1)
connect d_q.io.deq.ready, _q_io_deq_ready_T_2
wire muxedData : UInt<8>
connect muxedData, UInt<8>(0h0)
regreset counter : UInt<4>, clock, reset, UInt<4>(0h0)
wire vecData : UInt<8>[8]
node _vecData_0_T = bits(io.dataIn, 7, 0)
connect vecData[0], _vecData_0_T
node _vecData_1_T = bits(io.dataIn, 15, 8)
connect vecData[1], _vecData_1_T
node _vecData_2_T = bits(io.dataIn, 23, 16)
connect vecData[2], _vecData_2_T
node _vecData_3_T = bits(io.dataIn, 31, 24)
connect vecData[3], _vecData_3_T
node _vecData_4_T = bits(io.dataIn, 39, 32)
connect vecData[4], _vecData_4_T
node _vecData_5_T = bits(io.dataIn, 47, 40)
connect vecData[5], _vecData_5_T
node _vecData_6_T = bits(io.dataIn, 55, 48)
connect vecData[6], _vecData_6_T
node _vecData_7_T = bits(io.dataIn, 63, 56)
connect vecData[7], _vecData_7_T
node _muxedData_T = bits(counter, 2, 0)
connect muxedData, vecData[_muxedData_T]
node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn)
node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3))
node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1)
node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2)
node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0))
node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4)
node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000)))
node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6)
node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000))
node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9)
node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<13>(0h1000)))
node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11)
node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<17>(0h10000))
node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14)
node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<17>(0h10000)))
node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16)
node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000))
node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19)
node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<18>(0h2f000)))
node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21)
node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<22>(0h200000))
node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24)
node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<12>(0h800)))
node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26)
node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<22>(0h300000))
node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29)
node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<16>(0h8000)))
node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31)
node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<26>(0h2000000))
node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34)
node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<17>(0h10000)))
node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36)
node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<26>(0h2010000))
node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39)
node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<13>(0h1000)))
node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41)
node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<28>(0h8000000))
node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44)
node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<17>(0h10000)))
node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46)
node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<28>(0hc000000))
node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49)
node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<27>(0h4000000)))
node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51)
node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_54 = xor(io.addrIn, UInt<29>(0h10020000))
node _rdLegal_addr_T_55 = cvt(_rdLegal_addr_T_54)
node _rdLegal_addr_T_56 = and(_rdLegal_addr_T_55, asSInt(UInt<13>(0h1000)))
node _rdLegal_addr_T_57 = asSInt(_rdLegal_addr_T_56)
node _rdLegal_addr_T_58 = eq(_rdLegal_addr_T_57, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_59 = xor(io.addrIn, UInt<32>(0h80000000))
node _rdLegal_addr_T_60 = cvt(_rdLegal_addr_T_59)
node _rdLegal_addr_T_61 = and(_rdLegal_addr_T_60, asSInt(UInt<29>(0h10000000)))
node _rdLegal_addr_T_62 = asSInt(_rdLegal_addr_T_61)
node _rdLegal_addr_T_63 = eq(_rdLegal_addr_T_62, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_64 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13)
node _rdLegal_addr_T_65 = or(_rdLegal_addr_T_64, _rdLegal_addr_T_18)
node _rdLegal_addr_T_66 = or(_rdLegal_addr_T_65, _rdLegal_addr_T_23)
node _rdLegal_addr_T_67 = or(_rdLegal_addr_T_66, _rdLegal_addr_T_28)
node _rdLegal_addr_T_68 = or(_rdLegal_addr_T_67, _rdLegal_addr_T_33)
node _rdLegal_addr_T_69 = or(_rdLegal_addr_T_68, _rdLegal_addr_T_38)
node _rdLegal_addr_T_70 = or(_rdLegal_addr_T_69, _rdLegal_addr_T_43)
node _rdLegal_addr_T_71 = or(_rdLegal_addr_T_70, _rdLegal_addr_T_48)
node _rdLegal_addr_T_72 = or(_rdLegal_addr_T_71, _rdLegal_addr_T_53)
node _rdLegal_addr_T_73 = or(_rdLegal_addr_T_72, _rdLegal_addr_T_58)
node _rdLegal_addr_T_74 = or(_rdLegal_addr_T_73, _rdLegal_addr_T_63)
node _rdLegal_addr_T_75 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_74)
node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_75)
node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn)
node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3))
node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1)
node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2)
node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0))
node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4)
node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000)))
node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6)
node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000))
node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9)
node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<13>(0h1000)))
node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11)
node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<21>(0h100000))
node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14)
node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<18>(0h2f000)))
node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16)
node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<22>(0h200000))
node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19)
node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<12>(0h800)))
node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21)
node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<22>(0h300000))
node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24)
node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<16>(0h8000)))
node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26)
node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2000000))
node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29)
node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<17>(0h10000)))
node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31)
node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<26>(0h2010000))
node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34)
node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<13>(0h1000)))
node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36)
node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0h8000000))
node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39)
node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<17>(0h10000)))
node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41)
node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<28>(0hc000000))
node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44)
node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<27>(0h4000000)))
node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46)
node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_49 = xor(io.addrIn, UInt<29>(0h10020000))
node _wrLegal_addr_T_50 = cvt(_wrLegal_addr_T_49)
node _wrLegal_addr_T_51 = and(_wrLegal_addr_T_50, asSInt(UInt<13>(0h1000)))
node _wrLegal_addr_T_52 = asSInt(_wrLegal_addr_T_51)
node _wrLegal_addr_T_53 = eq(_wrLegal_addr_T_52, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_54 = xor(io.addrIn, UInt<32>(0h80000000))
node _wrLegal_addr_T_55 = cvt(_wrLegal_addr_T_54)
node _wrLegal_addr_T_56 = and(_wrLegal_addr_T_55, asSInt(UInt<29>(0h10000000)))
node _wrLegal_addr_T_57 = asSInt(_wrLegal_addr_T_56)
node _wrLegal_addr_T_58 = eq(_wrLegal_addr_T_57, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_59 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13)
node _wrLegal_addr_T_60 = or(_wrLegal_addr_T_59, _wrLegal_addr_T_18)
node _wrLegal_addr_T_61 = or(_wrLegal_addr_T_60, _wrLegal_addr_T_23)
node _wrLegal_addr_T_62 = or(_wrLegal_addr_T_61, _wrLegal_addr_T_28)
node _wrLegal_addr_T_63 = or(_wrLegal_addr_T_62, _wrLegal_addr_T_33)
node _wrLegal_addr_T_64 = or(_wrLegal_addr_T_63, _wrLegal_addr_T_38)
node _wrLegal_addr_T_65 = or(_wrLegal_addr_T_64, _wrLegal_addr_T_43)
node _wrLegal_addr_T_66 = or(_wrLegal_addr_T_65, _wrLegal_addr_T_48)
node _wrLegal_addr_T_67 = or(_wrLegal_addr_T_66, _wrLegal_addr_T_53)
node _wrLegal_addr_T_68 = or(_wrLegal_addr_T_67, _wrLegal_addr_T_58)
node _wrLegal_addr_T_69 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_68)
node _wrLegal_addr_T_70 = or(UInt<1>(0h0), UInt<1>(0h0))
node _wrLegal_addr_T_71 = xor(io.addrIn, UInt<17>(0h10000))
node _wrLegal_addr_T_72 = cvt(_wrLegal_addr_T_71)
node _wrLegal_addr_T_73 = and(_wrLegal_addr_T_72, asSInt(UInt<17>(0h10000)))
node _wrLegal_addr_T_74 = asSInt(_wrLegal_addr_T_73)
node _wrLegal_addr_T_75 = eq(_wrLegal_addr_T_74, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_76 = and(_wrLegal_addr_T_70, _wrLegal_addr_T_75)
node _wrLegal_addr_T_77 = or(UInt<1>(0h0), _wrLegal_addr_T_69)
node wrLegal_addr = or(_wrLegal_addr_T_77, _wrLegal_addr_T_76)
node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn)
node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc))
node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1)
node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2)
node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000))
node _gbits_legal_T_5 = cvt(_gbits_legal_T_4)
node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h9a113000)))
node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6)
node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8)
node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn)
node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6))
node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11)
node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12)
node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0))
node _gbits_legal_T_15 = cvt(_gbits_legal_T_14)
node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h9a112000)))
node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16)
node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_19 = xor(io.addrIn, UInt<17>(0h10000))
node _gbits_legal_T_20 = cvt(_gbits_legal_T_19)
node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h9a110000)))
node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21)
node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000))
node _gbits_legal_T_25 = cvt(_gbits_legal_T_24)
node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h9a103000)))
node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26)
node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_29 = xor(io.addrIn, UInt<21>(0h100000))
node _gbits_legal_T_30 = cvt(_gbits_legal_T_29)
node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h9a110000)))
node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31)
node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2000000))
node _gbits_legal_T_35 = cvt(_gbits_legal_T_34)
node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h9a110000)))
node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36)
node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_39 = xor(io.addrIn, UInt<26>(0h2010000))
node _gbits_legal_T_40 = cvt(_gbits_legal_T_39)
node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h9a113000)))
node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41)
node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000))
node _gbits_legal_T_45 = cvt(_gbits_legal_T_44)
node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0h98000000)))
node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46)
node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_49 = xor(io.addrIn, UInt<28>(0h8000000))
node _gbits_legal_T_50 = cvt(_gbits_legal_T_49)
node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0h9a110000)))
node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51)
node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_54 = xor(io.addrIn, UInt<29>(0h10000000))
node _gbits_legal_T_55 = cvt(_gbits_legal_T_54)
node _gbits_legal_T_56 = and(_gbits_legal_T_55, asSInt(UInt<33>(0h9a113000)))
node _gbits_legal_T_57 = asSInt(_gbits_legal_T_56)
node _gbits_legal_T_58 = eq(_gbits_legal_T_57, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_59 = xor(io.addrIn, UInt<32>(0h80000000))
node _gbits_legal_T_60 = cvt(_gbits_legal_T_59)
node _gbits_legal_T_61 = and(_gbits_legal_T_60, asSInt(UInt<33>(0h90000000)))
node _gbits_legal_T_62 = asSInt(_gbits_legal_T_61)
node _gbits_legal_T_63 = eq(_gbits_legal_T_62, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_64 = or(_gbits_legal_T_18, _gbits_legal_T_23)
node _gbits_legal_T_65 = or(_gbits_legal_T_64, _gbits_legal_T_28)
node _gbits_legal_T_66 = or(_gbits_legal_T_65, _gbits_legal_T_33)
node _gbits_legal_T_67 = or(_gbits_legal_T_66, _gbits_legal_T_38)
node _gbits_legal_T_68 = or(_gbits_legal_T_67, _gbits_legal_T_43)
node _gbits_legal_T_69 = or(_gbits_legal_T_68, _gbits_legal_T_48)
node _gbits_legal_T_70 = or(_gbits_legal_T_69, _gbits_legal_T_53)
node _gbits_legal_T_71 = or(_gbits_legal_T_70, _gbits_legal_T_58)
node _gbits_legal_T_72 = or(_gbits_legal_T_71, _gbits_legal_T_63)
node _gbits_legal_T_73 = and(_gbits_legal_T_13, _gbits_legal_T_72)
node _gbits_legal_T_74 = or(UInt<1>(0h0), _gbits_legal_T_9)
node gbits_legal = or(_gbits_legal_T_74, _gbits_legal_T_73)
wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}
connect gbits.opcode, UInt<3>(0h4)
connect gbits.param, UInt<1>(0h0)
connect gbits.size, io.sizeIn
connect gbits.source, UInt<1>(0h0)
connect gbits.address, io.addrIn
node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0))
node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1))
connect gbits.mask, UInt<1>(0h1)
invalidate gbits.data
connect gbits.corrupt, UInt<1>(0h0)
node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn)
node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc))
node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1)
node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2)
node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000))
node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4)
node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h9a313000)))
node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6)
node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8)
node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn)
node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6))
node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11)
node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12)
node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0))
node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14)
node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h9a312000)))
node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16)
node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_19 = xor(io.addrIn, UInt<21>(0h100000))
node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19)
node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h9a303000)))
node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21)
node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_24 = xor(io.addrIn, UInt<22>(0h200000))
node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24)
node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h9a313000)))
node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26)
node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_29 = xor(io.addrIn, UInt<22>(0h300000))
node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29)
node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h9a310000)))
node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31)
node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2000000))
node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34)
node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h9a310000)))
node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36)
node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_39 = xor(io.addrIn, UInt<26>(0h2010000))
node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39)
node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0h9a313000)))
node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41)
node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_44 = xor(io.addrIn, UInt<28>(0h8000000))
node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44)
node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0h98000000)))
node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46)
node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_49 = xor(io.addrIn, UInt<28>(0h8000000))
node _pfbits_legal_T_50 = cvt(_pfbits_legal_T_49)
node _pfbits_legal_T_51 = and(_pfbits_legal_T_50, asSInt(UInt<33>(0h9a310000)))
node _pfbits_legal_T_52 = asSInt(_pfbits_legal_T_51)
node _pfbits_legal_T_53 = eq(_pfbits_legal_T_52, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_54 = xor(io.addrIn, UInt<29>(0h10000000))
node _pfbits_legal_T_55 = cvt(_pfbits_legal_T_54)
node _pfbits_legal_T_56 = and(_pfbits_legal_T_55, asSInt(UInt<33>(0h9a313000)))
node _pfbits_legal_T_57 = asSInt(_pfbits_legal_T_56)
node _pfbits_legal_T_58 = eq(_pfbits_legal_T_57, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_59 = xor(io.addrIn, UInt<32>(0h80000000))
node _pfbits_legal_T_60 = cvt(_pfbits_legal_T_59)
node _pfbits_legal_T_61 = and(_pfbits_legal_T_60, asSInt(UInt<33>(0h90000000)))
node _pfbits_legal_T_62 = asSInt(_pfbits_legal_T_61)
node _pfbits_legal_T_63 = eq(_pfbits_legal_T_62, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_64 = or(_pfbits_legal_T_18, _pfbits_legal_T_23)
node _pfbits_legal_T_65 = or(_pfbits_legal_T_64, _pfbits_legal_T_28)
node _pfbits_legal_T_66 = or(_pfbits_legal_T_65, _pfbits_legal_T_33)
node _pfbits_legal_T_67 = or(_pfbits_legal_T_66, _pfbits_legal_T_38)
node _pfbits_legal_T_68 = or(_pfbits_legal_T_67, _pfbits_legal_T_43)
node _pfbits_legal_T_69 = or(_pfbits_legal_T_68, _pfbits_legal_T_48)
node _pfbits_legal_T_70 = or(_pfbits_legal_T_69, _pfbits_legal_T_53)
node _pfbits_legal_T_71 = or(_pfbits_legal_T_70, _pfbits_legal_T_58)
node _pfbits_legal_T_72 = or(_pfbits_legal_T_71, _pfbits_legal_T_63)
node _pfbits_legal_T_73 = and(_pfbits_legal_T_13, _pfbits_legal_T_72)
node _pfbits_legal_T_74 = or(UInt<1>(0h0), UInt<1>(0h0))
node _pfbits_legal_T_75 = xor(io.addrIn, UInt<17>(0h10000))
node _pfbits_legal_T_76 = cvt(_pfbits_legal_T_75)
node _pfbits_legal_T_77 = and(_pfbits_legal_T_76, asSInt(UInt<33>(0h9a310000)))
node _pfbits_legal_T_78 = asSInt(_pfbits_legal_T_77)
node _pfbits_legal_T_79 = eq(_pfbits_legal_T_78, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_80 = and(_pfbits_legal_T_74, _pfbits_legal_T_79)
node _pfbits_legal_T_81 = or(UInt<1>(0h0), _pfbits_legal_T_9)
node _pfbits_legal_T_82 = or(_pfbits_legal_T_81, _pfbits_legal_T_73)
node pfbits_legal = or(_pfbits_legal_T_82, _pfbits_legal_T_80)
wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}
connect pfbits.opcode, UInt<1>(0h0)
connect pfbits.param, UInt<1>(0h0)
connect pfbits.size, io.sizeIn
connect pfbits.source, UInt<1>(0h0)
connect pfbits.address, io.addrIn
node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0))
node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1))
connect pfbits.mask, UInt<1>(0h1)
connect pfbits.data, muxedData
connect pfbits.corrupt, UInt<1>(0h0)
connect io.rdLegal, rdLegal_addr
connect io.wrLegal, wrLegal_addr
connect io.sbStateOut, sbState
node _T = eq(sbState, UInt<1>(0h1))
when _T :
connect nodeOut.a.bits, gbits
else :
connect nodeOut.a.bits, pfbits
node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt)
connect io.respError, respError
node _wrTxValid_T = eq(sbState, UInt<2>(0h2))
node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid)
node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready)
node _rdTxValid_T = eq(sbState, UInt<2>(0h3))
node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid)
node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready)
node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn)
node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1))
node _txLast_T_2 = tail(_txLast_T_1, 1)
node txLast = eq(counter, _txLast_T_2)
node _counter_T = or(wrTxValid, rdTxValid)
node _counter_T_1 = and(_counter_T, txLast)
node _counter_T_2 = or(wrTxValid, rdTxValid)
node _counter_T_3 = add(counter, UInt<1>(0h1))
node _counter_T_4 = tail(_counter_T_3, 1)
node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter)
node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5)
connect counter, _counter_T_6
node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0))
node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T)
connect io.rdLoad[0], _io_rdLoad_0_T_1
node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1))
node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T)
connect io.rdLoad[1], _io_rdLoad_1_T_1
node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2))
node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T)
connect io.rdLoad[2], _io_rdLoad_2_T_1
node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3))
node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T)
connect io.rdLoad[3], _io_rdLoad_3_T_1
node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4))
node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T)
connect io.rdLoad[4], _io_rdLoad_4_T_1
node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5))
node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T)
connect io.rdLoad[5], _io_rdLoad_5_T_1
node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6))
node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T)
connect io.rdLoad[6], _io_rdLoad_6_T_1
node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7))
node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T)
connect io.rdLoad[7], _io_rdLoad_7_T_1
node _T_1 = eq(sbState, UInt<1>(0h0))
when _T_1 :
node _sbState_T = and(io.rdEn, io.rdLegal)
node _sbState_T_1 = and(io.wrEn, io.wrLegal)
node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState)
node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2)
connect sbState, _sbState_T_3
else :
node _T_2 = eq(sbState, UInt<1>(0h1))
when _T_2 :
node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready)
node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState)
connect sbState, _sbState_T_5
else :
node _T_3 = eq(sbState, UInt<2>(0h2))
when _T_3 :
node _sbState_T_6 = and(wrTxValid, txLast)
node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState)
connect sbState, _sbState_T_7
else :
node _T_4 = eq(sbState, UInt<2>(0h3))
when _T_4 :
node _sbState_T_8 = and(rdTxValid, txLast)
node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState)
connect sbState, _sbState_T_9
else :
node _T_5 = eq(sbState, UInt<3>(0h4))
when _T_5 :
node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready)
node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState)
connect sbState, _sbState_T_11
node _io_rdDone_T = and(rdTxValid, txLast)
connect io.rdDone, _io_rdDone_T
node _io_wrDone_T = eq(sbState, UInt<3>(0h4))
node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid)
node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready)
connect io.wrDone, _io_wrDone_T_2
connect io.dataOut, d_q.io.deq.bits.data
node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1))
node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2))
node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1)
connect nodeOut.a.valid, _nodeOut_a_valid_T_2
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<8>(0h0)
connect _WIRE.bits.mask, UInt<1>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.ready, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.valid, UInt<1>(0h0)
node _T_6 = eq(sbState, UInt<1>(0h0))
node _T_7 = eq(sbState, UInt<1>(0h1))
node _T_8 = or(_T_6, _T_7)
node _T_9 = eq(sbState, UInt<2>(0h2))
node _T_10 = or(_T_8, _T_9)
node _T_11 = eq(sbState, UInt<2>(0h3))
node _T_12 = or(_T_10, _T_11)
node _T_13 = eq(sbState, UInt<3>(0h4))
node _T_14 = or(_T_12, _T_13)
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n") : printf
assert(clock, _T_14, UInt<1>(0h1), "") : assert
node _T_18 = eq(sbState, UInt<1>(0h0))
node _T_19 = eq(sbState, UInt<1>(0h1))
node _T_20 = eq(sbState, UInt<2>(0h2))
node _T_21 = eq(sbState, UInt<2>(0h3))
node _T_22 = eq(sbState, UInt<3>(0h4))
node _T_23 = eq(io.rdLegal, UInt<1>(0h0))
node _T_24 = and(io.rdEn, _T_23)
node _T_25 = eq(io.wrLegal, UInt<1>(0h0))
node _T_26 = and(io.wrEn, _T_25)
extmodule plusarg_reader_97 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_98 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module SBToTL( // @[SBA.scala:273:9]
input clock, // @[SBA.scala:273:9]
input reset, // @[SBA.scala:273:9]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_rdEn, // @[SBA.scala:274:16]
input io_wrEn, // @[SBA.scala:274:16]
input [127:0] io_addrIn, // @[SBA.scala:274:16]
input [127:0] io_dataIn, // @[SBA.scala:274:16]
input [2:0] io_sizeIn, // @[SBA.scala:274:16]
output io_rdLegal, // @[SBA.scala:274:16]
output io_wrLegal, // @[SBA.scala:274:16]
output io_rdDone, // @[SBA.scala:274:16]
output io_wrDone, // @[SBA.scala:274:16]
output io_respError, // @[SBA.scala:274:16]
output [7:0] io_dataOut, // @[SBA.scala:274:16]
output io_rdLoad_0, // @[SBA.scala:274:16]
output io_rdLoad_1, // @[SBA.scala:274:16]
output io_rdLoad_2, // @[SBA.scala:274:16]
output io_rdLoad_3, // @[SBA.scala:274:16]
output io_rdLoad_4, // @[SBA.scala:274:16]
output io_rdLoad_5, // @[SBA.scala:274:16]
output io_rdLoad_6, // @[SBA.scala:274:16]
output io_rdLoad_7, // @[SBA.scala:274:16]
output [2:0] io_sbStateOut, // @[SBA.scala:274:16]
input rf_reset // @[SBA.scala:289:28]
);
wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[SBA.scala:273:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[SBA.scala:273:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[SBA.scala:273:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[SBA.scala:273:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[SBA.scala:273:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[SBA.scala:273:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[SBA.scala:273:9]
wire [7:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[SBA.scala:273:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[SBA.scala:273:9]
wire io_rdEn_0 = io_rdEn; // @[SBA.scala:273:9]
wire io_wrEn_0 = io_wrEn; // @[SBA.scala:273:9]
wire [127:0] io_addrIn_0 = io_addrIn; // @[SBA.scala:273:9]
wire [127:0] io_dataIn_0 = io_dataIn; // @[SBA.scala:273:9]
wire [2:0] io_sizeIn_0 = io_sizeIn; // @[SBA.scala:273:9]
wire auto_out_a_bits_source = 1'h0; // @[SBA.scala:273:9]
wire auto_out_a_bits_corrupt = 1'h0; // @[SBA.scala:273:9]
wire auto_out_d_bits_source = 1'h0; // @[SBA.scala:273:9]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire _wrLegal_addr_T_70 = 1'h0; // @[Parameters.scala:684:29]
wire _wrLegal_addr_T_76 = 1'h0; // @[Parameters.scala:684:54]
wire gbits_source = 1'h0; // @[Edges.scala:460:17]
wire gbits_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _pfbits_legal_T_74 = 1'h0; // @[Parameters.scala:684:29]
wire _pfbits_legal_T_80 = 1'h0; // @[Parameters.scala:684:54]
wire pfbits_source = 1'h0; // @[Edges.scala:480:17]
wire pfbits_corrupt = 1'h0; // @[Edges.scala:480:17]
wire [2:0] auto_out_a_bits_param = 3'h0; // @[SBA.scala:273:9]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] gbits_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] pfbits_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] pfbits_param = 3'h0; // @[Edges.scala:480:17]
wire auto_out_a_bits_mask = 1'h1; // @[SBA.scala:273:9]
wire nodeOut_a_bits_mask = 1'h1; // @[MixedNode.scala:542:17]
wire _rdLegal_addr_T = 1'h1; // @[Parameters.scala:92:28]
wire _rdLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _wrLegal_addr_T = 1'h1; // @[Parameters.scala:92:28]
wire _wrLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _gbits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _gbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _gbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _gbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _gbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire gbits_mask = 1'h1; // @[Edges.scala:460:17]
wire gbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81]
wire _pfbits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _pfbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _pfbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _pfbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _pfbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire pfbits_mask = 1'h1; // @[Edges.scala:480:17]
wire pfbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81]
wire [7:0] gbits_data = 8'h0; // @[Edges.scala:460:17]
wire [2:0] gbits_opcode = 3'h4; // @[Edges.scala:460:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[SBA.scala:273:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[SBA.scala:273:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[SBA.scala:273:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[SBA.scala:273:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[SBA.scala:273:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[SBA.scala:273:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[SBA.scala:273:9]
wire [7:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[SBA.scala:273:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[SBA.scala:273:9]
wire [127:0] _rdLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31]
wire rdLegal_addr; // @[Parameters.scala:686:26]
wire [2:0] _gbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34]
wire [2:0] _pfbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34]
wire wrLegal_addr; // @[Parameters.scala:686:26]
wire _io_rdDone_T; // @[SBA.scala:362:29]
wire _io_wrDone_T_2; // @[SBA.scala:363:71]
wire respError; // @[SBA.scala:335:35]
wire _io_rdLoad_0_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_1_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_2_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_3_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_4_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_5_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_6_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_7_T_1; // @[SBA.scala:345:33]
wire [2:0] auto_out_a_bits_opcode_0; // @[SBA.scala:273:9]
wire [3:0] auto_out_a_bits_size_0; // @[SBA.scala:273:9]
wire [31:0] auto_out_a_bits_address_0; // @[SBA.scala:273:9]
wire [7:0] auto_out_a_bits_data_0; // @[SBA.scala:273:9]
wire auto_out_a_valid_0; // @[SBA.scala:273:9]
wire auto_out_d_ready_0; // @[SBA.scala:273:9]
wire io_rdLoad_0_0; // @[SBA.scala:273:9]
wire io_rdLoad_1_0; // @[SBA.scala:273:9]
wire io_rdLoad_2_0; // @[SBA.scala:273:9]
wire io_rdLoad_3_0; // @[SBA.scala:273:9]
wire io_rdLoad_4_0; // @[SBA.scala:273:9]
wire io_rdLoad_5_0; // @[SBA.scala:273:9]
wire io_rdLoad_6_0; // @[SBA.scala:273:9]
wire io_rdLoad_7_0; // @[SBA.scala:273:9]
wire io_rdLegal_0; // @[SBA.scala:273:9]
wire io_wrLegal_0; // @[SBA.scala:273:9]
wire io_rdDone_0; // @[SBA.scala:273:9]
wire io_wrDone_0; // @[SBA.scala:273:9]
wire io_respError_0; // @[SBA.scala:273:9]
wire [7:0] io_dataOut_0; // @[SBA.scala:273:9]
wire [2:0] io_sbStateOut_0; // @[SBA.scala:273:9]
wire _nodeOut_a_valid_T_2; // @[SBA.scala:366:52]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[SBA.scala:273:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[SBA.scala:273:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[SBA.scala:273:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[SBA.scala:273:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[SBA.scala:273:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[SBA.scala:273:9]
reg [2:0] sbState; // @[SBA.scala:295:26]
assign io_sbStateOut_0 = sbState; // @[SBA.scala:273:9, :295:26]
wire _T_21 = sbState == 3'h3; // @[SBA.scala:295:26, :299:25]
wire _q_io_deq_ready_T; // @[SBA.scala:299:25]
assign _q_io_deq_ready_T = _T_21; // @[SBA.scala:299:25]
wire _rdTxValid_T; // @[SBA.scala:339:29]
assign _rdTxValid_T = _T_21; // @[SBA.scala:299:25, :339:29]
wire _T_22 = sbState == 3'h4; // @[SBA.scala:295:26, :299:62]
wire _q_io_deq_ready_T_1; // @[SBA.scala:299:62]
assign _q_io_deq_ready_T_1 = _T_22; // @[SBA.scala:299:62]
wire _io_wrDone_T; // @[SBA.scala:363:28]
assign _io_wrDone_T = _T_22; // @[SBA.scala:299:62, :363:28]
wire _q_io_deq_ready_T_2 = _q_io_deq_ready_T | _q_io_deq_ready_T_1; // @[SBA.scala:299:{25,50,62}]
wire [7:0] muxedData; // @[SBA.scala:301:29]
wire [7:0] pfbits_data = muxedData; // @[Edges.scala:480:17]
reg [3:0] counter; // @[SBA.scala:307:26]
wire [7:0] _vecData_0_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_1_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_2_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_3_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_4_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_5_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_6_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_7_T; // @[SBA.scala:309:63]
wire [7:0] vecData_0; // @[SBA.scala:308:25]
wire [7:0] vecData_1; // @[SBA.scala:308:25]
wire [7:0] vecData_2; // @[SBA.scala:308:25]
wire [7:0] vecData_3; // @[SBA.scala:308:25]
wire [7:0] vecData_4; // @[SBA.scala:308:25]
wire [7:0] vecData_5; // @[SBA.scala:308:25]
wire [7:0] vecData_6; // @[SBA.scala:308:25]
wire [7:0] vecData_7; // @[SBA.scala:308:25]
assign _vecData_0_T = io_dataIn_0[7:0]; // @[SBA.scala:273:9, :309:63]
assign vecData_0 = _vecData_0_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_1_T = io_dataIn_0[15:8]; // @[SBA.scala:273:9, :309:63]
assign vecData_1 = _vecData_1_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_2_T = io_dataIn_0[23:16]; // @[SBA.scala:273:9, :309:63]
assign vecData_2 = _vecData_2_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_3_T = io_dataIn_0[31:24]; // @[SBA.scala:273:9, :309:63]
assign vecData_3 = _vecData_3_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_4_T = io_dataIn_0[39:32]; // @[SBA.scala:273:9, :309:63]
assign vecData_4 = _vecData_4_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_5_T = io_dataIn_0[47:40]; // @[SBA.scala:273:9, :309:63]
assign vecData_5 = _vecData_5_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_6_T = io_dataIn_0[55:48]; // @[SBA.scala:273:9, :309:63]
assign vecData_6 = _vecData_6_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_7_T = io_dataIn_0[63:56]; // @[SBA.scala:273:9, :309:63]
assign vecData_7 = _vecData_7_T; // @[SBA.scala:308:25, :309:63]
wire [2:0] _muxedData_T = counter[2:0]; // @[SBA.scala:307:26, :310:33]
wire [7:0][7:0] _GEN = {{vecData_7}, {vecData_6}, {vecData_5}, {vecData_4}, {vecData_3}, {vecData_2}, {vecData_1}, {vecData_0}}; // @[SBA.scala:308:25, :310:15]
assign muxedData = _GEN[_muxedData_T]; // @[SBA.scala:301:29, :310:{15,33}]
wire _rdLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38]
wire _rdLegal_addr_T_2 = _rdLegal_addr_T_1; // @[Parameters.scala:92:{33,38}]
wire [128:0] _rdLegal_addr_T_5 = {1'h0, _rdLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_6 = _rdLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_7 = _rdLegal_addr_T_6; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_8 = _rdLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_0 = {io_addrIn_0[127:14], io_addrIn_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_9; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_9; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_4; // @[Parameters.scala:137:31]
assign _gbits_legal_T_4 = _GEN_0; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_4; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_4 = _GEN_0; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_10 = {1'h0, _rdLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_11 = _rdLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_12 = _rdLegal_addr_T_11; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_13 = _rdLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_1 = {io_addrIn_0[127:17], io_addrIn_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_14; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_14 = _GEN_1; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_71; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_71 = _GEN_1; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_19; // @[Parameters.scala:137:31]
assign _gbits_legal_T_19 = _GEN_1; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_75; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_75 = _GEN_1; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_15 = {1'h0, _rdLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_16 = _rdLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_17 = _rdLegal_addr_T_16; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_18 = _rdLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_2 = {io_addrIn_0[127:21], io_addrIn_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_19; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_19 = _GEN_2; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_14; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_14 = _GEN_2; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_24; // @[Parameters.scala:137:31]
assign _gbits_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_29; // @[Parameters.scala:137:31]
assign _gbits_legal_T_29 = _GEN_2; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_19; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_20 = {1'h0, _rdLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_21 = _rdLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_22 = _rdLegal_addr_T_21; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_23 = _rdLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_3 = {io_addrIn_0[127:22], io_addrIn_0[21:0] ^ 22'h200000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_24; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_24 = _GEN_3; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_19; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_19 = _GEN_3; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_24; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_25 = {1'h0, _rdLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_26 = _rdLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF800; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_27 = _rdLegal_addr_T_26; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_28 = _rdLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_4 = {io_addrIn_0[127:22], io_addrIn_0[21:0] ^ 22'h300000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_29; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_29 = _GEN_4; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_24; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_24 = _GEN_4; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_29; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_29 = _GEN_4; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_30 = {1'h0, _rdLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_31 = _rdLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_32 = _rdLegal_addr_T_31; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_33 = _rdLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_5 = {io_addrIn_0[127:26], io_addrIn_0[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_34; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_34 = _GEN_5; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_29; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_29 = _GEN_5; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_34; // @[Parameters.scala:137:31]
assign _gbits_legal_T_34 = _GEN_5; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_34; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_34 = _GEN_5; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_35 = {1'h0, _rdLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_36 = _rdLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_37 = _rdLegal_addr_T_36; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_38 = _rdLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_6 = {io_addrIn_0[127:26], io_addrIn_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_39; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_39 = _GEN_6; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_34; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_34 = _GEN_6; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_39; // @[Parameters.scala:137:31]
assign _gbits_legal_T_39 = _GEN_6; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_39; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_39 = _GEN_6; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_40 = {1'h0, _rdLegal_addr_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_41 = _rdLegal_addr_T_40 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_42 = _rdLegal_addr_T_41; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_43 = _rdLegal_addr_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_7 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_44; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_44 = _GEN_7; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_39; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_39 = _GEN_7; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_44; // @[Parameters.scala:137:31]
assign _gbits_legal_T_44 = _GEN_7; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_49; // @[Parameters.scala:137:31]
assign _gbits_legal_T_49 = _GEN_7; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_44; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_44 = _GEN_7; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_49; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_49 = _GEN_7; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_45 = {1'h0, _rdLegal_addr_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_46 = _rdLegal_addr_T_45 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_47 = _rdLegal_addr_T_46; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_48 = _rdLegal_addr_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_8 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_49; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_49 = _GEN_8; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_44; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_44 = _GEN_8; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_50 = {1'h0, _rdLegal_addr_T_49}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_51 = _rdLegal_addr_T_50 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_52 = _rdLegal_addr_T_51; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_53 = _rdLegal_addr_T_52 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_9 = {io_addrIn_0[127:29], io_addrIn_0[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_54; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_54 = _GEN_9; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_49; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_49 = _GEN_9; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_55 = {1'h0, _rdLegal_addr_T_54}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_56 = _rdLegal_addr_T_55 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_57 = _rdLegal_addr_T_56; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_58 = _rdLegal_addr_T_57 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] gbits_address = io_addrIn_0[31:0]; // @[Edges.scala:460:17]
wire [31:0] pfbits_address = io_addrIn_0[31:0]; // @[Edges.scala:480:17]
wire [127:0] _GEN_10 = {io_addrIn_0[127:32], io_addrIn_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_59; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_59 = _GEN_10; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_54; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_54 = _GEN_10; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_59; // @[Parameters.scala:137:31]
assign _gbits_legal_T_59 = _GEN_10; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_59; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_59 = _GEN_10; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_60 = {1'h0, _rdLegal_addr_T_59}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_61 = _rdLegal_addr_T_60 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_62 = _rdLegal_addr_T_61; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_63 = _rdLegal_addr_T_62 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _rdLegal_addr_T_64 = _rdLegal_addr_T_8 | _rdLegal_addr_T_13; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_65 = _rdLegal_addr_T_64 | _rdLegal_addr_T_18; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_66 = _rdLegal_addr_T_65 | _rdLegal_addr_T_23; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_67 = _rdLegal_addr_T_66 | _rdLegal_addr_T_28; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_68 = _rdLegal_addr_T_67 | _rdLegal_addr_T_33; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_69 = _rdLegal_addr_T_68 | _rdLegal_addr_T_38; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_70 = _rdLegal_addr_T_69 | _rdLegal_addr_T_43; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_71 = _rdLegal_addr_T_70 | _rdLegal_addr_T_48; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_72 = _rdLegal_addr_T_71 | _rdLegal_addr_T_53; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_73 = _rdLegal_addr_T_72 | _rdLegal_addr_T_58; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_74 = _rdLegal_addr_T_73 | _rdLegal_addr_T_63; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_75 = _rdLegal_addr_T_74; // @[Parameters.scala:684:54, :685:42]
assign rdLegal_addr = _rdLegal_addr_T_75; // @[Parameters.scala:684:54, :686:26]
assign io_rdLegal_0 = rdLegal_addr; // @[Parameters.scala:686:26]
wire _wrLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38]
wire _wrLegal_addr_T_2 = _wrLegal_addr_T_1; // @[Parameters.scala:92:{33,38}]
wire [128:0] _wrLegal_addr_T_5 = {1'h0, _wrLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_6 = _wrLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_7 = _wrLegal_addr_T_6; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_8 = _wrLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_10 = {1'h0, _wrLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_11 = _wrLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_12 = _wrLegal_addr_T_11; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_13 = _wrLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_15 = {1'h0, _wrLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_16 = _wrLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_17 = _wrLegal_addr_T_16; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_18 = _wrLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_20 = {1'h0, _wrLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_21 = _wrLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF800; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_22 = _wrLegal_addr_T_21; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_23 = _wrLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_25 = {1'h0, _wrLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_26 = _wrLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_27 = _wrLegal_addr_T_26; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_28 = _wrLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_30 = {1'h0, _wrLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_31 = _wrLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_32 = _wrLegal_addr_T_31; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_33 = _wrLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_35 = {1'h0, _wrLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_36 = _wrLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_37 = _wrLegal_addr_T_36; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_38 = _wrLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_40 = {1'h0, _wrLegal_addr_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_41 = _wrLegal_addr_T_40 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_42 = _wrLegal_addr_T_41; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_43 = _wrLegal_addr_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_45 = {1'h0, _wrLegal_addr_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_46 = _wrLegal_addr_T_45 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_47 = _wrLegal_addr_T_46; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_48 = _wrLegal_addr_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_50 = {1'h0, _wrLegal_addr_T_49}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_51 = _wrLegal_addr_T_50 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_52 = _wrLegal_addr_T_51; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_53 = _wrLegal_addr_T_52 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_55 = {1'h0, _wrLegal_addr_T_54}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_56 = _wrLegal_addr_T_55 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_57 = _wrLegal_addr_T_56; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_58 = _wrLegal_addr_T_57 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _wrLegal_addr_T_59 = _wrLegal_addr_T_8 | _wrLegal_addr_T_13; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_60 = _wrLegal_addr_T_59 | _wrLegal_addr_T_18; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_61 = _wrLegal_addr_T_60 | _wrLegal_addr_T_23; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_62 = _wrLegal_addr_T_61 | _wrLegal_addr_T_28; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_63 = _wrLegal_addr_T_62 | _wrLegal_addr_T_33; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_64 = _wrLegal_addr_T_63 | _wrLegal_addr_T_38; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_65 = _wrLegal_addr_T_64 | _wrLegal_addr_T_43; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_66 = _wrLegal_addr_T_65 | _wrLegal_addr_T_48; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_67 = _wrLegal_addr_T_66 | _wrLegal_addr_T_53; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_68 = _wrLegal_addr_T_67 | _wrLegal_addr_T_58; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_69 = _wrLegal_addr_T_68; // @[Parameters.scala:684:54, :685:42]
wire _wrLegal_addr_T_77 = _wrLegal_addr_T_69; // @[Parameters.scala:684:54, :686:26]
wire [128:0] _wrLegal_addr_T_72 = {1'h0, _wrLegal_addr_T_71}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_73 = _wrLegal_addr_T_72 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_74 = _wrLegal_addr_T_73; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_75 = _wrLegal_addr_T_74 == 129'h0; // @[Parameters.scala:137:{46,59}]
assign wrLegal_addr = _wrLegal_addr_T_77; // @[Parameters.scala:686:26]
assign io_wrLegal_0 = wrLegal_addr; // @[Parameters.scala:686:26]
wire [128:0] _gbits_legal_T_5 = {1'h0, _gbits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_6 = _gbits_legal_T_5 & 129'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_7 = _gbits_legal_T_6; // @[Parameters.scala:137:46]
wire _gbits_legal_T_8 = _gbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _gbits_legal_T_9 = _gbits_legal_T_8; // @[Parameters.scala:684:54]
wire _gbits_legal_T_74 = _gbits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _GEN_11 = io_sizeIn_0 != 3'h7; // @[Parameters.scala:92:38]
wire _gbits_legal_T_11; // @[Parameters.scala:92:38]
assign _gbits_legal_T_11 = _GEN_11; // @[Parameters.scala:92:38]
wire _pfbits_legal_T_11; // @[Parameters.scala:92:38]
assign _pfbits_legal_T_11 = _GEN_11; // @[Parameters.scala:92:38]
wire _gbits_legal_T_12 = _gbits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _gbits_legal_T_13 = _gbits_legal_T_12; // @[Parameters.scala:684:29]
wire [128:0] _gbits_legal_T_15 = {1'h0, _gbits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_16 = _gbits_legal_T_15 & 129'h9A112000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_17 = _gbits_legal_T_16; // @[Parameters.scala:137:46]
wire _gbits_legal_T_18 = _gbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_20 = {1'h0, _gbits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_21 = _gbits_legal_T_20 & 129'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_22 = _gbits_legal_T_21; // @[Parameters.scala:137:46]
wire _gbits_legal_T_23 = _gbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_25 = {1'h0, _gbits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_26 = _gbits_legal_T_25 & 129'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_27 = _gbits_legal_T_26; // @[Parameters.scala:137:46]
wire _gbits_legal_T_28 = _gbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_30 = {1'h0, _gbits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_31 = _gbits_legal_T_30 & 129'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_32 = _gbits_legal_T_31; // @[Parameters.scala:137:46]
wire _gbits_legal_T_33 = _gbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_35 = {1'h0, _gbits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_36 = _gbits_legal_T_35 & 129'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_37 = _gbits_legal_T_36; // @[Parameters.scala:137:46]
wire _gbits_legal_T_38 = _gbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_40 = {1'h0, _gbits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_41 = _gbits_legal_T_40 & 129'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_42 = _gbits_legal_T_41; // @[Parameters.scala:137:46]
wire _gbits_legal_T_43 = _gbits_legal_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_45 = {1'h0, _gbits_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_46 = _gbits_legal_T_45 & 129'h98000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_47 = _gbits_legal_T_46; // @[Parameters.scala:137:46]
wire _gbits_legal_T_48 = _gbits_legal_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_50 = {1'h0, _gbits_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_51 = _gbits_legal_T_50 & 129'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_52 = _gbits_legal_T_51; // @[Parameters.scala:137:46]
wire _gbits_legal_T_53 = _gbits_legal_T_52 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_12 = {io_addrIn_0[127:29], io_addrIn_0[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_54; // @[Parameters.scala:137:31]
assign _gbits_legal_T_54 = _GEN_12; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_54; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_54 = _GEN_12; // @[Parameters.scala:137:31]
wire [128:0] _gbits_legal_T_55 = {1'h0, _gbits_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_56 = _gbits_legal_T_55 & 129'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_57 = _gbits_legal_T_56; // @[Parameters.scala:137:46]
wire _gbits_legal_T_58 = _gbits_legal_T_57 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_60 = {1'h0, _gbits_legal_T_59}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_61 = _gbits_legal_T_60 & 129'h90000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_62 = _gbits_legal_T_61; // @[Parameters.scala:137:46]
wire _gbits_legal_T_63 = _gbits_legal_T_62 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _gbits_legal_T_64 = _gbits_legal_T_18 | _gbits_legal_T_23; // @[Parameters.scala:685:42]
wire _gbits_legal_T_65 = _gbits_legal_T_64 | _gbits_legal_T_28; // @[Parameters.scala:685:42]
wire _gbits_legal_T_66 = _gbits_legal_T_65 | _gbits_legal_T_33; // @[Parameters.scala:685:42]
wire _gbits_legal_T_67 = _gbits_legal_T_66 | _gbits_legal_T_38; // @[Parameters.scala:685:42]
wire _gbits_legal_T_68 = _gbits_legal_T_67 | _gbits_legal_T_43; // @[Parameters.scala:685:42]
wire _gbits_legal_T_69 = _gbits_legal_T_68 | _gbits_legal_T_48; // @[Parameters.scala:685:42]
wire _gbits_legal_T_70 = _gbits_legal_T_69 | _gbits_legal_T_53; // @[Parameters.scala:685:42]
wire _gbits_legal_T_71 = _gbits_legal_T_70 | _gbits_legal_T_58; // @[Parameters.scala:685:42]
wire _gbits_legal_T_72 = _gbits_legal_T_71 | _gbits_legal_T_63; // @[Parameters.scala:685:42]
wire _gbits_legal_T_73 = _gbits_legal_T_13 & _gbits_legal_T_72; // @[Parameters.scala:684:{29,54}, :685:42]
wire gbits_legal = _gbits_legal_T_74 | _gbits_legal_T_73; // @[Parameters.scala:684:54, :686:26]
wire [3:0] gbits_size; // @[Edges.scala:460:17]
wire [3:0] _GEN_13 = {1'h0, io_sizeIn_0}; // @[Edges.scala:463:15]
assign gbits_size = _GEN_13; // @[Edges.scala:460:17, :463:15]
wire [3:0] pfbits_size; // @[Edges.scala:480:17]
assign pfbits_size = _GEN_13; // @[Edges.scala:463:15, :480:17]
wire [128:0] _pfbits_legal_T_5 = {1'h0, _pfbits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_6 = _pfbits_legal_T_5 & 129'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_7 = _pfbits_legal_T_6; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_8 = _pfbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _pfbits_legal_T_9 = _pfbits_legal_T_8; // @[Parameters.scala:684:54]
wire _pfbits_legal_T_81 = _pfbits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _pfbits_legal_T_12 = _pfbits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _pfbits_legal_T_13 = _pfbits_legal_T_12; // @[Parameters.scala:684:29]
wire [128:0] _pfbits_legal_T_15 = {1'h0, _pfbits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_16 = _pfbits_legal_T_15 & 129'h9A312000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_17 = _pfbits_legal_T_16; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_18 = _pfbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_20 = {1'h0, _pfbits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_21 = _pfbits_legal_T_20 & 129'h9A303000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_22 = _pfbits_legal_T_21; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_23 = _pfbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_25 = {1'h0, _pfbits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_26 = _pfbits_legal_T_25 & 129'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_27 = _pfbits_legal_T_26; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_28 = _pfbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_30 = {1'h0, _pfbits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_31 = _pfbits_legal_T_30 & 129'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_32 = _pfbits_legal_T_31; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_33 = _pfbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_35 = {1'h0, _pfbits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_36 = _pfbits_legal_T_35 & 129'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_37 = _pfbits_legal_T_36; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_38 = _pfbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_40 = {1'h0, _pfbits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_41 = _pfbits_legal_T_40 & 129'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_42 = _pfbits_legal_T_41; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_43 = _pfbits_legal_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_45 = {1'h0, _pfbits_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_46 = _pfbits_legal_T_45 & 129'h98000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_47 = _pfbits_legal_T_46; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_48 = _pfbits_legal_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_50 = {1'h0, _pfbits_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_51 = _pfbits_legal_T_50 & 129'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_52 = _pfbits_legal_T_51; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_53 = _pfbits_legal_T_52 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_55 = {1'h0, _pfbits_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_56 = _pfbits_legal_T_55 & 129'h9A313000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_57 = _pfbits_legal_T_56; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_58 = _pfbits_legal_T_57 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_60 = {1'h0, _pfbits_legal_T_59}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_61 = _pfbits_legal_T_60 & 129'h90000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_62 = _pfbits_legal_T_61; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_63 = _pfbits_legal_T_62 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _pfbits_legal_T_64 = _pfbits_legal_T_18 | _pfbits_legal_T_23; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_65 = _pfbits_legal_T_64 | _pfbits_legal_T_28; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_66 = _pfbits_legal_T_65 | _pfbits_legal_T_33; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_67 = _pfbits_legal_T_66 | _pfbits_legal_T_38; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_68 = _pfbits_legal_T_67 | _pfbits_legal_T_43; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_69 = _pfbits_legal_T_68 | _pfbits_legal_T_48; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_70 = _pfbits_legal_T_69 | _pfbits_legal_T_53; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_71 = _pfbits_legal_T_70 | _pfbits_legal_T_58; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_72 = _pfbits_legal_T_71 | _pfbits_legal_T_63; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_73 = _pfbits_legal_T_13 & _pfbits_legal_T_72; // @[Parameters.scala:684:{29,54}, :685:42]
wire [128:0] _pfbits_legal_T_76 = {1'h0, _pfbits_legal_T_75}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_77 = _pfbits_legal_T_76 & 129'h9A310000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_78 = _pfbits_legal_T_77; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_79 = _pfbits_legal_T_78 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _pfbits_legal_T_82 = _pfbits_legal_T_81 | _pfbits_legal_T_73; // @[Parameters.scala:684:54, :686:26]
wire pfbits_legal = _pfbits_legal_T_82; // @[Parameters.scala:686:26]
wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18, :366:28]
assign nodeOut_a_bits_opcode = {_nodeOut_a_valid_T, 2'h0}; // @[SBA.scala:322:{42,54}, :323:54, :366:28]
assign nodeOut_a_bits_size = _nodeOut_a_valid_T ? gbits_size : pfbits_size; // @[Edges.scala:460:17, :480:17]
assign nodeOut_a_bits_address = _nodeOut_a_valid_T ? gbits_address : pfbits_address; // @[Edges.scala:460:17, :480:17]
assign nodeOut_a_bits_data = _nodeOut_a_valid_T ? 8'h0 : pfbits_data; // @[Edges.scala:480:17]
assign respError = _d_q_io_deq_bits_denied | _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign io_respError_0 = respError; // @[SBA.scala:273:9, :335:35]
wire _T_20 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29]
wire _wrTxValid_T; // @[SBA.scala:338:29]
assign _wrTxValid_T = _T_20; // @[SBA.scala:338:29]
wire _nodeOut_a_valid_T_1; // @[SBA.scala:366:64]
assign _nodeOut_a_valid_T_1 = _T_20; // @[SBA.scala:338:29, :366:64]
wire _wrTxValid_T_1 = _wrTxValid_T & nodeOut_a_valid; // @[SBA.scala:338:{29,53}]
wire wrTxValid = _wrTxValid_T_1 & nodeOut_a_ready; // @[SBA.scala:338:{53,69}]
wire _rdTxValid_T_1 = _rdTxValid_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire rdTxValid = _rdTxValid_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :339:{53,70}]
wire [7:0] _txLast_T = 8'h1 << io_sizeIn_0; // @[SBA.scala:273:9, :340:39]
wire [8:0] _txLast_T_1 = {1'h0, _txLast_T} - 9'h1; // @[SBA.scala:340:{39,53}]
wire [7:0] _txLast_T_2 = _txLast_T_1[7:0]; // @[SBA.scala:340:53]
wire txLast = {4'h0, counter} == _txLast_T_2; // @[SBA.scala:307:26, :340:{29,53}]
wire _GEN_14 = wrTxValid | rdTxValid; // @[SBA.scala:338:69, :339:70, :341:31]
wire _counter_T; // @[SBA.scala:341:31]
assign _counter_T = _GEN_14; // @[SBA.scala:341:31]
wire _counter_T_2; // @[SBA.scala:342:31]
assign _counter_T_2 = _GEN_14; // @[SBA.scala:341:31, :342:31]
wire _counter_T_1 = _counter_T & txLast; // @[SBA.scala:340:29, :341:{31,45}]
wire [4:0] _counter_T_3 = {1'h0, counter} + 5'h1; // @[SBA.scala:307:26, :342:63]
wire [3:0] _counter_T_4 = _counter_T_3[3:0]; // @[SBA.scala:342:63]
wire [3:0] _counter_T_5 = _counter_T_2 ? _counter_T_4 : counter; // @[SBA.scala:307:26, :342:{19,31,63}]
wire [3:0] _counter_T_6 = _counter_T_1 ? 4'h0 : _counter_T_5; // @[SBA.scala:341:{19,45}, :342:19]
wire _io_rdLoad_0_T = counter == 4'h0; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_0_T_1 = rdTxValid & _io_rdLoad_0_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_0_0 = _io_rdLoad_0_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_1_T = counter == 4'h1; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_1_T_1 = rdTxValid & _io_rdLoad_1_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_1_0 = _io_rdLoad_1_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_2_T = counter == 4'h2; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_2_T_1 = rdTxValid & _io_rdLoad_2_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_2_0 = _io_rdLoad_2_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_3_T = counter == 4'h3; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_3_T_1 = rdTxValid & _io_rdLoad_3_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_3_0 = _io_rdLoad_3_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_4_T = counter == 4'h4; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_4_T_1 = rdTxValid & _io_rdLoad_4_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_4_0 = _io_rdLoad_4_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_5_T = counter == 4'h5; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_5_T_1 = rdTxValid & _io_rdLoad_5_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_5_0 = _io_rdLoad_5_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_6_T = counter == 4'h6; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_6_T_1 = rdTxValid & _io_rdLoad_6_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_6_0 = _io_rdLoad_6_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_7_T = counter == 4'h7; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_7_T_1 = rdTxValid & _io_rdLoad_7_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_7_0 = _io_rdLoad_7_T_1; // @[SBA.scala:273:9, :345:33]
wire _sbState_T = io_rdEn_0 & io_rdLegal_0; // @[SBA.scala:273:9, :350:30]
wire _sbState_T_1 = io_wrEn_0 & io_wrLegal_0; // @[SBA.scala:273:9, :351:30]
wire [2:0] _sbState_T_2 = _sbState_T_1 ? 3'h2 : sbState; // @[SBA.scala:295:26, :351:{21,30}]
wire [2:0] _sbState_T_3 = _sbState_T ? 3'h1 : _sbState_T_2; // @[SBA.scala:350:{21,30}, :351:21]
wire _sbState_T_4 = nodeOut_a_valid & nodeOut_a_ready; // @[SBA.scala:353:35]
wire [2:0] _sbState_T_5 = _sbState_T_4 ? 3'h3 : sbState; // @[SBA.scala:295:26, :353:{21,35}]
wire _sbState_T_6 = wrTxValid & txLast; // @[SBA.scala:338:69, :340:29, :355:32]
wire [2:0] _sbState_T_7 = _sbState_T_6 ? 3'h4 : sbState; // @[SBA.scala:295:26, :355:{21,32}]
wire _GEN_15 = rdTxValid & txLast; // @[SBA.scala:339:70, :340:29, :357:32]
wire _sbState_T_8; // @[SBA.scala:357:32]
assign _sbState_T_8 = _GEN_15; // @[SBA.scala:357:32]
assign _io_rdDone_T = _GEN_15; // @[SBA.scala:357:32, :362:29]
wire [2:0] _sbState_T_9 = _sbState_T_8 ? 3'h0 : sbState; // @[SBA.scala:295:26, :357:{21,32}]
wire _sbState_T_10 = _d_q_io_deq_valid & _q_io_deq_ready_T_2; // @[Decoupled.scala:362:21]
wire [2:0] _sbState_T_11 = _sbState_T_10 ? 3'h0 : sbState; // @[SBA.scala:295:26, :359:{21,36}]
assign io_rdDone_0 = _io_rdDone_T; // @[SBA.scala:273:9, :362:29]
wire _io_wrDone_T_1 = _io_wrDone_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign _io_wrDone_T_2 = _io_wrDone_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :363:{54,71}]
assign io_wrDone_0 = _io_wrDone_T_2; // @[SBA.scala:273:9, :363:71]
assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[SBA.scala:366:{28,52,64}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[SBA.scala:366:52] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s7k4z3c :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_38
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue1_TLBundleA_a32d128s7k4z3c
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue1_TLBundleD_a32d128s7k4z3c
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
connect nodeIn.b, nodeOut.b
connect nodeOut.c, nodeIn.c
connect nodeOut.e, nodeIn.e | module TLBuffer_a32d128s7k4z3c( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire [127:0] auto_in_b_bits_data = 128'h0; // @[Nodes.scala:27:25]
wire [127:0] auto_out_b_bits_data = 128'h0; // @[Nodes.scala:27:25]
wire [127:0] nodeIn_b_bits_data = 128'h0; // @[Nodes.scala:27:25]
wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Nodes.scala:27:25]
wire [15:0] auto_in_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25]
wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25]
wire [15:0] nodeIn_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25]
wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25]
wire [6:0] auto_in_b_bits_source = 7'h40; // @[Nodes.scala:27:25]
wire [6:0] auto_out_b_bits_source = 7'h40; // @[Nodes.scala:27:25]
wire [6:0] nodeIn_b_bits_source = 7'h40; // @[Nodes.scala:27:25]
wire [6:0] nodeOut_b_bits_source = 7'h40; // @[Nodes.scala:27:25]
wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] auto_out_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] nodeOut_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_c_bits_source = nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_38 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue1_TLBundleA_a32d128s7k4z3c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue1_TLBundleD_a32d128s7k4z3c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_10 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<7>(0h7f))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 3)
node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 6, 0)
node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 13, 7)
node idx_history_hist_chunks_2 = bits(io.f1_req_ghist, 20, 14)
node idx_history_hist_chunks_3 = bits(io.f1_req_ghist, 27, 21)
node idx_history_hist_chunks_4 = bits(io.f1_req_ghist, 31, 28)
node _idx_history_T = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1)
node _idx_history_T_1 = xor(_idx_history_T, idx_history_hist_chunks_2)
node _idx_history_T_2 = xor(_idx_history_T_1, idx_history_hist_chunks_3)
node idx_history = xor(_idx_history_T_2, idx_history_hist_chunks_4)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 6, 0)
node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 8, 0)
node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 17, 9)
node tag_history_hist_chunks_2 = bits(io.f1_req_ghist, 26, 18)
node tag_history_hist_chunks_3 = bits(io.f1_req_ghist, 31, 27)
node _tag_history_T = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1)
node _tag_history_T_1 = xor(_tag_history_T, tag_history_hist_chunks_2)
node tag_history = xor(_tag_history_T_1, tag_history_hist_chunks_3)
node _tag_T = shr(_T_1, 7)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 8, 0)
smem hi_us : UInt<1>[4] [128]
smem lo_us : UInt<1>[4] [128]
smem table : UInt<13>[4] [128]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire _s2_req_rtage_WIRE : UInt<7>
invalidate _s2_req_rtage_WIRE
when io.f1_req_valid :
connect _s2_req_rtage_WIRE, s1_hashed_idx
read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock
wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_2 : UInt<13>
connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0]
node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0)
connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T
node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 11, 3)
connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1
node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 12, 12)
connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2
wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_4 : UInt<13>
connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1]
node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0)
connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3
node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 11, 3)
connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4
node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 12, 12)
connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5
wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_6 : UInt<13>
connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2]
node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0)
connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6
node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 11, 3)
connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7
node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 12, 12)
connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8
wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_8 : UInt<13>
connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3]
node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0)
connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9
node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 11, 3)
connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10
node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 12, 12)
connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4]
connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr
connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag
connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid
connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr
connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag
connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid
connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr
connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag
connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid
connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr
connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag
connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid
wire _s2_req_rhius_WIRE : UInt<7>
invalidate _s2_req_rhius_WIRE
when io.f1_req_valid :
connect _s2_req_rhius_WIRE, s1_hashed_idx
read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock
wire _s2_req_rlous_WIRE : UInt<7>
invalidate _s2_req_rlous_WIRE
when io.f1_req_valid :
connect _s2_req_rlous_WIRE, s1_hashed_idx
read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
reg io_f3_resp_0_valid_REG : UInt<1>, clock
connect io_f3_resp_0_valid_REG, s2_req_rhits[0]
connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG
node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0])
reg io_f3_resp_0_bits_u_REG : UInt, clock
connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T
connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG
reg io_f3_resp_0_bits_ctr_REG : UInt, clock
connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr
connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG
reg io_f3_resp_1_valid_REG : UInt<1>, clock
connect io_f3_resp_1_valid_REG, s2_req_rhits[1]
connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG
node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1])
reg io_f3_resp_1_bits_u_REG : UInt, clock
connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T
connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG
reg io_f3_resp_1_bits_ctr_REG : UInt, clock
connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr
connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG
reg io_f3_resp_2_valid_REG : UInt<1>, clock
connect io_f3_resp_2_valid_REG, s2_req_rhits[2]
connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG
node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2])
reg io_f3_resp_2_bits_u_REG : UInt, clock
connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T
connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG
reg io_f3_resp_2_bits_ctr_REG : UInt, clock
connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr
connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG
reg io_f3_resp_3_valid_REG : UInt<1>, clock
connect io_f3_resp_3_valid_REG, s2_req_rhits[3]
connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG
node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3])
reg io_f3_resp_3_bits_u_REG : UInt, clock
connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T
connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG
reg io_f3_resp_3_bits_ctr_REG : UInt, clock
connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr
connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG
regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _doing_clear_u_hi_T = bits(clear_u_ctr, 18, 18)
node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1))
node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1)
node _doing_clear_u_lo_T = bits(clear_u_ctr, 18, 18)
node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0))
node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1)
node clear_u_idx = shr(clear_u_ctr, 11)
node _T_2 = shr(io.update_pc, 3)
node idx_history_hist_chunks_0_1 = bits(io.update_hist, 6, 0)
node idx_history_hist_chunks_1_1 = bits(io.update_hist, 13, 7)
node idx_history_hist_chunks_2_1 = bits(io.update_hist, 20, 14)
node idx_history_hist_chunks_3_1 = bits(io.update_hist, 27, 21)
node idx_history_hist_chunks_4_1 = bits(io.update_hist, 31, 28)
node _idx_history_T_3 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1)
node _idx_history_T_4 = xor(_idx_history_T_3, idx_history_hist_chunks_2_1)
node _idx_history_T_5 = xor(_idx_history_T_4, idx_history_hist_chunks_3_1)
node idx_history_1 = xor(_idx_history_T_5, idx_history_hist_chunks_4_1)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 6, 0)
node tag_history_hist_chunks_0_1 = bits(io.update_hist, 8, 0)
node tag_history_hist_chunks_1_1 = bits(io.update_hist, 17, 9)
node tag_history_hist_chunks_2_1 = bits(io.update_hist, 26, 18)
node tag_history_hist_chunks_3_1 = bits(io.update_hist, 31, 27)
node _tag_history_T_2 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1)
node _tag_history_T_3 = xor(_tag_history_T_2, tag_history_hist_chunks_2_1)
node tag_history_1 = xor(_tag_history_T_3, tag_history_hist_chunks_3_1)
node _tag_T_2 = shr(_T_2, 7)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 8, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4]
node _T_3 = mux(doing_reset, reset_idx, update_idx)
wire _WIRE : UInt<13>[4]
connect _WIRE[0], UInt<13>(0h0)
connect _WIRE[1], UInt<13>(0h0)
connect _WIRE[2], UInt<13>(0h0)
connect _WIRE[3], UInt<13>(0h0)
node hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _T_4 = cat(hi, update_wdata[0].ctr)
node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _T_5 = cat(hi_1, update_wdata[1].ctr)
node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _T_6 = cat(hi_2, update_wdata[2].ctr)
node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _T_7 = cat(hi_3, update_wdata[3].ctr)
wire _WIRE_1 : UInt<13>[4]
connect _WIRE_1[0], _T_4
connect _WIRE_1[1], _T_5
connect _WIRE_1[2], _T_6
connect _WIRE_1[3], _T_7
node _T_8 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_9 = not(UInt<4>(0h0))
node lo = cat(io.update_mask[1], io.update_mask[0])
node hi_4 = cat(io.update_mask[3], io.update_mask[2])
node _T_10 = cat(hi_4, lo)
node _T_11 = mux(doing_reset, _T_9, _T_10)
node _T_12 = bits(_T_11, 0, 0)
node _T_13 = bits(_T_11, 1, 1)
node _T_14 = bits(_T_11, 2, 2)
node _T_15 = bits(_T_11, 3, 3)
write mport MPORT = table[_T_3], clock
when _T_12 :
connect MPORT[0], _T_8[0]
when _T_13 :
connect MPORT[1], _T_8[1]
when _T_14 :
connect MPORT[2], _T_8[2]
when _T_15 :
connect MPORT[3], _T_8[3]
wire update_hi_wdata : UInt<1>[4]
node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx)
node _T_17 = mux(doing_reset, reset_idx, _T_16)
node _T_18 = or(doing_reset, doing_clear_u_hi)
wire _WIRE_2 : UInt<1>[4]
connect _WIRE_2[0], UInt<1>(0h0)
connect _WIRE_2[1], UInt<1>(0h0)
connect _WIRE_2[2], UInt<1>(0h0)
connect _WIRE_2[3], UInt<1>(0h0)
node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata)
node _T_20 = or(doing_reset, doing_clear_u_hi)
node _T_21 = not(UInt<4>(0h0))
node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_22 = cat(hi_5, lo_1)
node _T_23 = mux(_T_20, _T_21, _T_22)
node _T_24 = bits(_T_23, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node _T_26 = bits(_T_23, 2, 2)
node _T_27 = bits(_T_23, 3, 3)
node _T_28 = bits(_T_17, 6, 0)
write mport MPORT_1 = hi_us[_T_28], clock
when _T_24 :
connect MPORT_1[0], _T_19[0]
when _T_25 :
connect MPORT_1[1], _T_19[1]
when _T_26 :
connect MPORT_1[2], _T_19[2]
when _T_27 :
connect MPORT_1[3], _T_19[3]
wire update_lo_wdata : UInt<1>[4]
node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx)
node _T_30 = mux(doing_reset, reset_idx, _T_29)
node _T_31 = or(doing_reset, doing_clear_u_lo)
wire _WIRE_3 : UInt<1>[4]
connect _WIRE_3[0], UInt<1>(0h0)
connect _WIRE_3[1], UInt<1>(0h0)
connect _WIRE_3[2], UInt<1>(0h0)
connect _WIRE_3[3], UInt<1>(0h0)
node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata)
node _T_33 = or(doing_reset, doing_clear_u_lo)
node _T_34 = not(UInt<4>(0h0))
node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_35 = cat(hi_6, lo_2)
node _T_36 = mux(_T_33, _T_34, _T_35)
node _T_37 = bits(_T_36, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node _T_39 = bits(_T_36, 2, 2)
node _T_40 = bits(_T_36, 3, 3)
node _T_41 = bits(_T_30, 6, 0)
write mport MPORT_2 = lo_us[_T_41], clock
when _T_37 :
connect MPORT_2[0], _T_32[0]
when _T_38 :
connect MPORT_2[1], _T_32[1]
when _T_39 :
connect MPORT_2[2], _T_32[2]
when _T_40 :
connect MPORT_2[3], _T_32[3]
reg wrbypass_tags : UInt<9>[2], clock
reg wrbypass_idxs : UInt<7>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1)
connect update_hi_wdata[0], _update_hi_wdata_0_T
node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0)
connect update_lo_wdata[0], _update_lo_wdata_0_T
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1)
connect update_hi_wdata[1], _update_hi_wdata_1_T
node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0)
connect update_lo_wdata[1], _update_lo_wdata_1_T
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1)
connect update_hi_wdata[2], _update_hi_wdata_2_T
node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0)
connect update_lo_wdata[2], _update_lo_wdata_2_T
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1)
connect update_hi_wdata[3], _update_hi_wdata_3_T
node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0)
connect update_lo_wdata[3], _update_lo_wdata_3_T
node _T_42 = or(io.update_mask[0], io.update_mask[1])
node _T_43 = or(_T_42, io.update_mask[2])
node _T_44 = or(_T_43, io.update_mask[3])
when _T_44 :
node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_45 :
wire _WIRE_4 : UInt<3>[4]
connect _WIRE_4[0], update_wdata[0].ctr
connect _WIRE_4[1], update_wdata[1].ctr
connect _WIRE_4[2], update_wdata[2].ctr
connect _WIRE_4[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_4
else :
wire _WIRE_5 : UInt<3>[4]
connect _WIRE_5[0], update_wdata[0].ctr
connect _WIRE_5[1], update_wdata[1].ctr
connect _WIRE_5[2], update_wdata[2].ctr
connect _WIRE_5[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_5
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_10( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f3_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14]
output io_f3_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14]
output io_f3_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14]
output io_f3_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8]
wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8]
wire [12:0] table_MPORT_data_3; // @[tage.scala:123:8]
wire [12:0] table_MPORT_data_2; // @[tage.scala:123:8]
wire [12:0] table_MPORT_data_1; // @[tage.scala:123:8]
wire [12:0] table_MPORT_data_0; // @[tage.scala:123:8]
wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87]
wire [51:0] _table_R0_data; // @[tage.scala:91:27]
wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27]
wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26]
wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [6:0] reset_idx; // @[tage.scala:73:26]
wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26]
wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26]
wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11]
wire [3:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[31:28]; // @[tage.scala:24:7, :53:11]
wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25]
wire [6:0] idx_history = {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ idx_history_hist_chunks_4}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:162:35]
wire [36:0] _idx_T = {_tag_T, io_f1_req_pc_0[9:3] ^ idx_history}; // @[frontend.scala:162:35]
wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}]
wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40]
wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32]
wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32]
wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11]
wire [4:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[31:27]; // @[tage.scala:24:7, :53:11]
wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25]
wire [8:0] tag_history = {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ tag_history_hist_chunks_3}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T_1 = {_tag_T[29:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}]
wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}]
wire [12:0] _s2_req_rtage_WIRE_2 = _table_R0_data[12:0]; // @[tage.scala:91:27, :97:87]
wire [12:0] _s2_req_rtage_WIRE_4 = _table_R0_data[25:13]; // @[tage.scala:91:27, :97:87]
wire [12:0] _s2_req_rtage_WIRE_6 = _table_R0_data[38:26]; // @[tage.scala:91:27, :97:87]
wire [12:0] _s2_req_rtage_WIRE_8 = _table_R0_data[51:39]; // @[tage.scala:91:27, :97:87]
reg [8:0] s2_tag; // @[tage.scala:95:29]
wire _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_1; // @[tage.scala:97:87]
wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87]
assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87]
assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_4; // @[tage.scala:97:87]
wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87]
assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87]
assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_7; // @[tage.scala:97:87]
wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87]
assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87]
assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_10; // @[tage.scala:97:87]
wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87]
assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87]
assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg [18:0] clear_u_ctr; // @[tage.scala:109:28]
wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85]
wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54]
wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54]
wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}]
wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}]
wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}]
wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}]
wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33]
wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11]
wire [3:0] idx_history_hist_chunks_4_1 = io_update_hist_0[31:28]; // @[tage.scala:24:7, :53:11]
wire [6:0] _idx_history_T_3 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25]
wire [6:0] idx_history_1 = {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ idx_history_hist_chunks_4_1}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:162:35]
wire [36:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[9:3] ^ idx_history_1}; // @[frontend.scala:162:35]
wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}]
wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11]
wire [4:0] tag_history_hist_chunks_3_1 = io_update_hist_0[31:27]; // @[tage.scala:24:7, :53:11]
wire [8:0] _tag_history_T_2 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25]
wire [8:0] tag_history_1 = {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ tag_history_hist_chunks_3_1}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T_3 = {_tag_T_2[29:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}]
wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}]
wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26]
wire [9:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102]
wire [9:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102]
wire [9:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102]
wire [9:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102]
assign table_MPORT_data_0 = doing_reset ? 13'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_1 = doing_reset ? 13'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_2 = doing_reset ? 13'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_3 = doing_reset ? 13'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90]
wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90]
wire _update_hi_wdata_0_T; // @[tage.scala:166:44]
wire _update_hi_wdata_1_T; // @[tage.scala:166:44]
wire _update_hi_wdata_2_T; // @[tage.scala:166:44]
wire _update_hi_wdata_3_T; // @[tage.scala:166:44]
wire update_hi_wdata_0; // @[tage.scala:127:29]
wire update_hi_wdata_1; // @[tage.scala:127:29]
wire update_hi_wdata_2; // @[tage.scala:127:29]
wire update_hi_wdata_3; // @[tage.scala:127:29]
wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21]
assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}]
wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] lo_1; // @[tage.scala:131:80]
assign lo_1 = _GEN; // @[tage.scala:131:80]
wire [1:0] lo_2; // @[tage.scala:138:80]
assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80]
wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] hi_5; // @[tage.scala:131:80]
assign hi_5 = _GEN_0; // @[tage.scala:131:80]
wire [1:0] hi_6; // @[tage.scala:138:80]
assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80]
wire _update_lo_wdata_0_T; // @[tage.scala:167:44]
wire _update_lo_wdata_1_T; // @[tage.scala:167:44]
wire _update_lo_wdata_2_T; // @[tage.scala:167:44]
wire _update_lo_wdata_3_T; // @[tage.scala:167:44]
wire update_lo_wdata_0; // @[tage.scala:134:29]
wire update_lo_wdata_1; // @[tage.scala:134:29]
wire update_lo_wdata_2; // @[tage.scala:134:29]
wire update_lo_wdata_3; // @[tage.scala:134:29]
wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21]
assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}]
reg [8:0] wrbypass_tags_0; // @[tage.scala:141:29]
reg [8:0] wrbypass_tags_1; // @[tage.scala:141:29]
reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29]
reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:143:29]
reg wrbypass_enq_idx; // @[tage.scala:144:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 7'h0; // @[tage.scala:73:26]
clear_u_ctr <= 19'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39]
end
else // @[tage.scala:144:33, :170:38, :171:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29]
io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38]
io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38]
io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38]
io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38]
io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38]
if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29]
if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29]
if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
end
else begin // @[tage.scala:143:29, :170:38, :171:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
always @(posedge)
hi_us_9 hi_us ( // @[tage.scala:89:27]
.R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}]
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8]
.W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}]
); // @[tage.scala:89:27]
lo_us_9 lo_us ( // @[tage.scala:90:27]
.R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}]
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8]
.W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}]
); // @[tage.scala:90:27]
table_9 table_0 ( // @[tage.scala:91:27]
.R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8]
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8]
.W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}]
); // @[tage.scala:91:27]
assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_349 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_349( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_14 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = or(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_16 = or(_T_15, UInt<1>(0h0))
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_21 = or(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_21, UInt<1>(0h1), "") : assert_4
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_28 = and(_T_26, _T_27)
node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_32 = and(_T_30, _T_31)
node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_42 = and(_T_40, _T_41)
node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_46 = and(_T_44, _T_45)
node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_49 = and(_T_47, _T_48)
node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_60 = and(_T_58, _T_59)
node _T_61 = or(_T_32, _T_39)
node _T_62 = or(_T_61, _T_46)
node _T_63 = or(_T_62, _T_53)
node _T_64 = or(_T_63, _T_60)
node _T_65 = or(_T_25, _T_64)
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_65, UInt<1>(0h1), "") : assert_5
node _T_69 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_71 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_78 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_79 = and(_T_77, _T_78)
node _T_80 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_83 = and(_T_81, _T_82)
node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_85 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_86 = and(_T_84, _T_85)
node _T_87 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_90 = and(_T_88, _T_89)
node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_92 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_97 = and(_T_95, _T_96)
node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_99 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_100 = and(_T_98, _T_99)
node _T_101 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_102 = and(_T_100, _T_101)
node _T_103 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_104 = and(_T_102, _T_103)
node _T_105 = or(_T_76, _T_83)
node _T_106 = or(_T_105, _T_90)
node _T_107 = or(_T_106, _T_97)
node _T_108 = or(_T_107, _T_104)
node _T_109 = or(_T_69, _T_108)
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_109, UInt<1>(0h1), "") : assert_6
node _T_113 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_115 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_116 = and(_T_114, _T_115)
node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_118 = and(_T_116, _T_117)
node _T_119 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_122 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_123 = and(_T_121, _T_122)
node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_129 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_136 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_139 = and(_T_137, _T_138)
node _T_140 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_143 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_148 = and(_T_146, _T_147)
node _T_149 = or(_T_120, _T_127)
node _T_150 = or(_T_149, _T_134)
node _T_151 = or(_T_150, _T_141)
node _T_152 = or(_T_151, _T_148)
node _T_153 = or(_T_113, _T_152)
node _T_154 = asUInt(reset)
node _T_155 = eq(_T_154, UInt<1>(0h0))
when _T_155 :
node _T_156 = eq(_T_153, UInt<1>(0h0))
when _T_156 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_153, UInt<1>(0h1), "") : assert_7
node _T_157 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_159 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_160 = and(_T_158, _T_159)
node _T_161 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_166 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_167 = and(_T_165, _T_166)
node _T_168 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_173 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_174 = and(_T_172, _T_173)
node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_178 = and(_T_176, _T_177)
node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_180 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_185 = and(_T_183, _T_184)
node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_187 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_192 = and(_T_190, _T_191)
node _T_193 = or(_T_164, _T_171)
node _T_194 = or(_T_193, _T_178)
node _T_195 = or(_T_194, _T_185)
node _T_196 = or(_T_195, _T_192)
node _T_197 = or(_T_157, _T_196)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_197, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_14( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s5k1z3u_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_62
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a28d64s5k1z3u_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a28d64s5k1z3u_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a28d64s5k1z3u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_62 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a28d64s5k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a28d64s5k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_78 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<10>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 9, 0)
node _source_ok_T = shr(io.in.a.bits.source, 10)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<10>(0h39f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits = bits(_uncommonBits_T, 9, 0)
node _T_4 = shr(io.in.a.bits.source, 10)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<10>(0h39f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 9, 0)
node _T_24 = shr(io.in.a.bits.source, 10)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<10>(0h39f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 9, 0)
node _T_86 = shr(io.in.a.bits.source, 10)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<10>(0h39f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 9, 0)
node _T_152 = shr(io.in.a.bits.source, 10)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<10>(0h39f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 9, 0)
node _T_199 = shr(io.in.a.bits.source, 10)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<10>(0h39f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 9, 0)
node _T_240 = shr(io.in.a.bits.source, 10)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<10>(0h39f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 9, 0)
node _T_283 = shr(io.in.a.bits.source, 10)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<10>(0h39f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 9, 0)
node _T_321 = shr(io.in.a.bits.source, 10)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<10>(0h39f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<10>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 9, 0)
node _T_359 = shr(io.in.a.bits.source, 10)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<10>(0h39f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<10>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 9, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 10)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<10>(0h39f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<10>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<10>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<10>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<10>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<928>, clock, reset, UInt<928>(0h0)
regreset inflight_opcodes : UInt<3712>, clock, reset, UInt<3712>(0h0)
regreset inflight_sizes : UInt<3712>, clock, reset, UInt<3712>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<928>
connect a_set, UInt<928>(0h0)
wire a_set_wo_ready : UInt<928>
connect a_set_wo_ready, UInt<928>(0h0)
wire a_opcodes_set : UInt<3712>
connect a_opcodes_set, UInt<3712>(0h0)
wire a_sizes_set : UInt<3712>
connect a_sizes_set, UInt<3712>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<928>
connect d_clr, UInt<928>(0h0)
wire d_clr_wo_ready : UInt<928>
connect d_clr_wo_ready, UInt<928>(0h0)
wire d_opcodes_clr : UInt<3712>
connect d_opcodes_clr, UInt<3712>(0h0)
wire d_sizes_clr : UInt<3712>
connect d_sizes_clr, UInt<3712>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_169
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<928>, clock, reset, UInt<928>(0h0)
regreset inflight_opcodes_1 : UInt<3712>, clock, reset, UInt<3712>(0h0)
regreset inflight_sizes_1 : UInt<3712>, clock, reset, UInt<3712>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<10>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<928>
connect c_set, UInt<928>(0h0)
wire c_set_wo_ready : UInt<928>
connect c_set_wo_ready, UInt<928>(0h0)
wire c_opcodes_set : UInt<3712>
connect c_opcodes_set, UInt<3712>(0h0)
wire c_sizes_set : UInt<3712>
connect c_sizes_set, UInt<3712>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<10>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<10>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<10>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<10>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<10>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<928>
connect d_clr_1, UInt<928>(0h0)
wire d_clr_wo_ready_1 : UInt<928>
connect d_clr_wo_ready_1, UInt<928>(0h0)
wire d_opcodes_clr_1 : UInt<3712>
connect d_opcodes_clr_1, UInt<3712>(0h0)
wire d_sizes_clr_1 : UInt<3712>
connect d_sizes_clr_1, UInt<3712>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<10>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<10>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<10>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<10>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_170
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<10>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<10>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_78( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [9:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [9:0] source_1; // @[Monitor.scala:541:22]
reg [927:0] inflight; // @[Monitor.scala:614:27]
reg [3711:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3711:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [1023:0] _GEN = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [1023:0] _GEN_2 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [927:0] inflight_1; // @[Monitor.scala:726:35]
reg [3711:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module SinkC_4 :
input clock : Clock
input reset : Reset
output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}}, resp : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, set : UInt<11>, flip way : UInt<4>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_dat : { data : UInt<128>}, flip rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, rel_beat : { data : UInt<128>, corrupt : UInt<1>}}
inst c_q of Queue2_TLBundleC_a32d128s6k4z3c_4
connect c_q.clock, clock
connect c_q.reset, reset
connect c_q.io.enq.valid, io.c.valid
connect c_q.io.enq.bits.corrupt, io.c.bits.corrupt
connect c_q.io.enq.bits.data, io.c.bits.data
connect c_q.io.enq.bits.address, io.c.bits.address
connect c_q.io.enq.bits.source, io.c.bits.source
connect c_q.io.enq.bits.size, io.c.bits.size
connect c_q.io.enq.bits.param, io.c.bits.param
connect c_q.io.enq.bits.opcode, io.c.bits.opcode
connect io.c.ready, c_q.io.enq.ready
node _offset_T = bits(c_q.io.deq.bits.address, 0, 0)
node _offset_T_1 = bits(c_q.io.deq.bits.address, 1, 1)
node _offset_T_2 = bits(c_q.io.deq.bits.address, 2, 2)
node _offset_T_3 = bits(c_q.io.deq.bits.address, 3, 3)
node _offset_T_4 = bits(c_q.io.deq.bits.address, 4, 4)
node _offset_T_5 = bits(c_q.io.deq.bits.address, 5, 5)
node _offset_T_6 = bits(c_q.io.deq.bits.address, 9, 9)
node _offset_T_7 = bits(c_q.io.deq.bits.address, 10, 10)
node _offset_T_8 = bits(c_q.io.deq.bits.address, 11, 11)
node _offset_T_9 = bits(c_q.io.deq.bits.address, 12, 12)
node _offset_T_10 = bits(c_q.io.deq.bits.address, 13, 13)
node _offset_T_11 = bits(c_q.io.deq.bits.address, 14, 14)
node _offset_T_12 = bits(c_q.io.deq.bits.address, 15, 15)
node _offset_T_13 = bits(c_q.io.deq.bits.address, 16, 16)
node _offset_T_14 = bits(c_q.io.deq.bits.address, 17, 17)
node _offset_T_15 = bits(c_q.io.deq.bits.address, 18, 18)
node _offset_T_16 = bits(c_q.io.deq.bits.address, 19, 19)
node _offset_T_17 = bits(c_q.io.deq.bits.address, 20, 20)
node _offset_T_18 = bits(c_q.io.deq.bits.address, 21, 21)
node _offset_T_19 = bits(c_q.io.deq.bits.address, 22, 22)
node _offset_T_20 = bits(c_q.io.deq.bits.address, 23, 23)
node _offset_T_21 = bits(c_q.io.deq.bits.address, 24, 24)
node _offset_T_22 = bits(c_q.io.deq.bits.address, 25, 25)
node _offset_T_23 = bits(c_q.io.deq.bits.address, 26, 26)
node _offset_T_24 = bits(c_q.io.deq.bits.address, 27, 27)
node _offset_T_25 = bits(c_q.io.deq.bits.address, 31, 31)
node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1)
node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T)
node offset_lo_lo_hi_hi = cat(_offset_T_5, _offset_T_4)
node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, _offset_T_3)
node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo)
node offset_lo_hi_lo_hi = cat(_offset_T_8, _offset_T_7)
node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_6)
node offset_lo_hi_hi_lo = cat(_offset_T_10, _offset_T_9)
node offset_lo_hi_hi_hi = cat(_offset_T_12, _offset_T_11)
node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo)
node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo)
node offset_lo = cat(offset_lo_hi, offset_lo_lo)
node offset_hi_lo_lo_hi = cat(_offset_T_15, _offset_T_14)
node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_13)
node offset_hi_lo_hi_hi = cat(_offset_T_18, _offset_T_17)
node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, _offset_T_16)
node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo)
node offset_hi_hi_lo_hi = cat(_offset_T_21, _offset_T_20)
node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, _offset_T_19)
node offset_hi_hi_hi_lo = cat(_offset_T_23, _offset_T_22)
node offset_hi_hi_hi_hi = cat(_offset_T_25, _offset_T_24)
node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo)
node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo)
node offset_hi = cat(offset_hi_hi, offset_hi_lo)
node offset = cat(offset_hi, offset_lo)
node set = shr(offset, 6)
node tag = shr(set, 11)
node tag_1 = bits(tag, 8, 0)
node set_1 = bits(set, 10, 0)
node offset_1 = bits(offset, 5, 0)
node _T = and(c_q.io.deq.ready, c_q.io.deq.valid)
node _r_beats1_decode_T = dshl(UInt<6>(0h3f), c_q.io.deq.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 4)
node r_beats1_opdata = bits(c_q.io.deq.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node last = or(_r_last_T, _r_last_T_1)
node r_3 = and(last, _T)
node _r_count_T = not(r_counter1)
node beat = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node hasData = bits(c_q.io.deq.bits.opcode, 0, 0)
node _raw_resp_T = eq(c_q.io.deq.bits.opcode, UInt<3>(0h4))
node _raw_resp_T_1 = eq(c_q.io.deq.bits.opcode, UInt<3>(0h5))
node raw_resp = or(_raw_resp_T, _raw_resp_T_1)
reg resp_r : UInt<1>, clock
when c_q.io.deq.valid :
connect resp_r, raw_resp
node resp = mux(c_q.io.deq.valid, raw_resp, resp_r)
node _T_1 = and(c_q.io.deq.valid, c_q.io.deq.bits.corrupt)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unavailable\n at SinkC.scala:90 assert (!(c.valid && c.bits.corrupt), \"Data poisoning unavailable\")\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
reg io_set_r : UInt<11>, clock
when c_q.io.deq.valid :
connect io_set_r, set_1
node _io_set_T = mux(c_q.io.deq.valid, set_1, io_set_r)
connect io.set, _io_set_T
wire bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}
inst io_bs_adr_q of Queue1_BankedStoreInnerAddress_4
connect io_bs_adr_q.clock, clock
connect io_bs_adr_q.reset, reset
connect io_bs_adr_q.io.enq.valid, bs_adr.valid
connect io_bs_adr_q.io.enq.bits.mask, bs_adr.bits.mask
connect io_bs_adr_q.io.enq.bits.beat, bs_adr.bits.beat
connect io_bs_adr_q.io.enq.bits.set, bs_adr.bits.set
connect io_bs_adr_q.io.enq.bits.way, bs_adr.bits.way
connect io_bs_adr_q.io.enq.bits.noop, bs_adr.bits.noop
connect bs_adr.ready, io_bs_adr_q.io.enq.ready
connect io.bs_adr.bits, io_bs_adr_q.io.deq.bits
connect io.bs_adr.valid, io_bs_adr_q.io.deq.valid
connect io_bs_adr_q.io.deq.ready, io.bs_adr.ready
node _io_bs_dat_data_T = and(bs_adr.ready, bs_adr.valid)
reg io_bs_dat_data_r : UInt<128>, clock
when _io_bs_dat_data_T :
connect io_bs_dat_data_r, c_q.io.deq.bits.data
connect io.bs_dat.data, io_bs_dat_data_r
node _bs_adr_valid_T = eq(first, UInt<1>(0h0))
node _bs_adr_valid_T_1 = and(c_q.io.deq.valid, hasData)
node _bs_adr_valid_T_2 = or(_bs_adr_valid_T, _bs_adr_valid_T_1)
node _bs_adr_valid_T_3 = and(resp, _bs_adr_valid_T_2)
connect bs_adr.valid, _bs_adr_valid_T_3
node _bs_adr_bits_noop_T = eq(c_q.io.deq.valid, UInt<1>(0h0))
connect bs_adr.bits.noop, _bs_adr_bits_noop_T
connect bs_adr.bits.way, io.way
connect bs_adr.bits.set, io.set
node _bs_adr_bits_beat_T = add(beat, bs_adr.ready)
node _bs_adr_bits_beat_T_1 = tail(_bs_adr_bits_beat_T, 1)
reg bs_adr_bits_beat_r : UInt<2>, clock
when c_q.io.deq.valid :
connect bs_adr_bits_beat_r, _bs_adr_bits_beat_T_1
node _bs_adr_bits_beat_T_2 = mux(c_q.io.deq.valid, beat, bs_adr_bits_beat_r)
connect bs_adr.bits.beat, _bs_adr_bits_beat_T_2
node _bs_adr_bits_mask_T = not(UInt<2>(0h0))
connect bs_adr.bits.mask, _bs_adr_bits_mask_T
node _T_6 = eq(bs_adr.ready, UInt<1>(0h0))
node _T_7 = and(bs_adr.valid, _T_6)
node _io_resp_valid_T = and(resp, c_q.io.deq.valid)
node _io_resp_valid_T_1 = or(first, last)
node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1)
node _io_resp_valid_T_3 = eq(hasData, UInt<1>(0h0))
node _io_resp_valid_T_4 = or(_io_resp_valid_T_3, bs_adr.ready)
node _io_resp_valid_T_5 = and(_io_resp_valid_T_2, _io_resp_valid_T_4)
connect io.resp.valid, _io_resp_valid_T_5
connect io.resp.bits.last, last
connect io.resp.bits.set, set_1
connect io.resp.bits.tag, tag_1
connect io.resp.bits.source, c_q.io.deq.bits.source
connect io.resp.bits.param, c_q.io.deq.bits.param
connect io.resp.bits.data, hasData
inst putbuffer of ListBuffer_PutBufferCEntry_q2_e8_4
connect putbuffer.clock, clock
connect putbuffer.reset, reset
regreset lists : UInt<2>, clock, reset, UInt<2>(0h0)
wire lists_set : UInt<2>
connect lists_set, UInt<2>(0h0)
wire lists_clr : UInt<2>
connect lists_clr, UInt<2>(0h0)
node _lists_T = or(lists, lists_set)
node _lists_T_1 = not(lists_clr)
node _lists_T_2 = and(_lists_T, _lists_T_1)
connect lists, _lists_T_2
node _free_T = andr(lists)
node free = eq(_free_T, UInt<1>(0h0))
node _freeOH_T = not(lists)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 1, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = bits(_freeOH_T_3, 1, 0)
node _freeOH_T_5 = shl(_freeOH_T_4, 1)
node _freeOH_T_6 = not(_freeOH_T_5)
node _freeOH_T_7 = not(lists)
node freeOH = and(_freeOH_T_6, _freeOH_T_7)
node freeIdx_hi = bits(freeOH, 2, 2)
node freeIdx_lo = bits(freeOH, 1, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node _freeIdx_T_2 = bits(_freeIdx_T_1, 1, 1)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_2)
node _req_block_T = eq(io.req.ready, UInt<1>(0h0))
node req_block = and(first, _req_block_T)
node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0))
node buf_block = and(hasData, _buf_block_T)
node _set_block_T = and(hasData, first)
node _set_block_T_1 = eq(free, UInt<1>(0h0))
node set_block = and(_set_block_T, _set_block_T_1)
node _T_8 = eq(raw_resp, UInt<1>(0h0))
node _T_9 = and(c_q.io.deq.valid, _T_8)
node _T_10 = and(_T_9, req_block)
node _T_11 = eq(raw_resp, UInt<1>(0h0))
node _T_12 = and(c_q.io.deq.valid, _T_11)
node _T_13 = and(_T_12, buf_block)
node _T_14 = eq(raw_resp, UInt<1>(0h0))
node _T_15 = and(c_q.io.deq.valid, _T_14)
node _T_16 = and(_T_15, set_block)
node _q_io_deq_ready_T = eq(hasData, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, bs_adr.ready)
node _q_io_deq_ready_T_2 = eq(req_block, UInt<1>(0h0))
node _q_io_deq_ready_T_3 = eq(buf_block, UInt<1>(0h0))
node _q_io_deq_ready_T_4 = and(_q_io_deq_ready_T_2, _q_io_deq_ready_T_3)
node _q_io_deq_ready_T_5 = eq(set_block, UInt<1>(0h0))
node _q_io_deq_ready_T_6 = and(_q_io_deq_ready_T_4, _q_io_deq_ready_T_5)
node _q_io_deq_ready_T_7 = mux(raw_resp, _q_io_deq_ready_T_1, _q_io_deq_ready_T_6)
connect c_q.io.deq.ready, _q_io_deq_ready_T_7
node _io_req_valid_T = eq(resp, UInt<1>(0h0))
node _io_req_valid_T_1 = and(_io_req_valid_T, c_q.io.deq.valid)
node _io_req_valid_T_2 = and(_io_req_valid_T_1, first)
node _io_req_valid_T_3 = eq(buf_block, UInt<1>(0h0))
node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3)
node _io_req_valid_T_5 = eq(set_block, UInt<1>(0h0))
node _io_req_valid_T_6 = and(_io_req_valid_T_4, _io_req_valid_T_5)
connect io.req.valid, _io_req_valid_T_6
node _putbuffer_io_push_valid_T = eq(resp, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_1 = and(_putbuffer_io_push_valid_T, c_q.io.deq.valid)
node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T_1, hasData)
node _putbuffer_io_push_valid_T_3 = eq(req_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3)
node _putbuffer_io_push_valid_T_5 = eq(set_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_6 = and(_putbuffer_io_push_valid_T_4, _putbuffer_io_push_valid_T_5)
connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_6
node _T_17 = eq(resp, UInt<1>(0h0))
node _T_18 = and(_T_17, c_q.io.deq.valid)
node _T_19 = and(_T_18, first)
node _T_20 = and(_T_19, hasData)
node _T_21 = eq(req_block, UInt<1>(0h0))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(buf_block, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
when _T_24 :
connect lists_set, freeOH
reg put_r : UInt<2>, clock
when first :
connect put_r, freeIdx
node put = mux(first, freeIdx, put_r)
wire _WIRE : UInt<1>[3]
connect _WIRE[0], UInt<1>(0h0)
connect _WIRE[1], UInt<1>(0h0)
connect _WIRE[2], UInt<1>(0h1)
connect io.req.bits.prio, _WIRE
connect io.req.bits.control, UInt<1>(0h0)
connect io.req.bits.opcode, c_q.io.deq.bits.opcode
connect io.req.bits.param, c_q.io.deq.bits.param
connect io.req.bits.size, c_q.io.deq.bits.size
connect io.req.bits.source, c_q.io.deq.bits.source
connect io.req.bits.offset, offset_1
connect io.req.bits.set, set_1
connect io.req.bits.tag, tag_1
connect io.req.bits.put, put
connect putbuffer.io.push.bits.index, put
connect putbuffer.io.push.bits.data.data, c_q.io.deq.bits.data
connect putbuffer.io.push.bits.data.corrupt, c_q.io.deq.bits.corrupt
connect putbuffer.io.pop.bits, io.rel_pop.bits.index
node _putbuffer_io_pop_valid_T = and(io.rel_pop.ready, io.rel_pop.valid)
connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T
node _io_rel_pop_ready_T = bits(io.rel_pop.bits.index, 0, 0)
node _io_rel_pop_ready_T_1 = dshr(putbuffer.io.valid, _io_rel_pop_ready_T)
node _io_rel_pop_ready_T_2 = bits(_io_rel_pop_ready_T_1, 0, 0)
connect io.rel_pop.ready, _io_rel_pop_ready_T_2
connect io.rel_beat, putbuffer.io.data
node _T_25 = and(io.rel_pop.ready, io.rel_pop.valid)
node _T_26 = and(_T_25, io.rel_pop.bits.last)
when _T_26 :
node lists_clr_shiftAmount = bits(io.rel_pop.bits.index, 0, 0)
node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount)
node _lists_clr_T_1 = bits(_lists_clr_T, 1, 0)
connect lists_clr, _lists_clr_T_1 | module SinkC_4( // @[SinkC.scala:41:7]
input clock, // @[SinkC.scala:41:7]
input reset, // @[SinkC.scala:41:7]
input io_req_ready, // @[SinkC.scala:43:14]
output io_req_valid, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_param, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_size, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_source, // @[SinkC.scala:43:14]
output [8:0] io_req_bits_tag, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_put, // @[SinkC.scala:43:14]
output [10:0] io_req_bits_set, // @[SinkC.scala:43:14]
output io_resp_valid, // @[SinkC.scala:43:14]
output io_resp_bits_last, // @[SinkC.scala:43:14]
output [10:0] io_resp_bits_set, // @[SinkC.scala:43:14]
output [8:0] io_resp_bits_tag, // @[SinkC.scala:43:14]
output [5:0] io_resp_bits_source, // @[SinkC.scala:43:14]
output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14]
output io_resp_bits_data, // @[SinkC.scala:43:14]
output io_c_ready, // @[SinkC.scala:43:14]
input io_c_valid, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_param, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_size, // @[SinkC.scala:43:14]
input [5:0] io_c_bits_source, // @[SinkC.scala:43:14]
input [31:0] io_c_bits_address, // @[SinkC.scala:43:14]
input [127:0] io_c_bits_data, // @[SinkC.scala:43:14]
input io_c_bits_corrupt, // @[SinkC.scala:43:14]
output [10:0] io_set, // @[SinkC.scala:43:14]
input [3:0] io_way, // @[SinkC.scala:43:14]
input io_bs_adr_ready, // @[SinkC.scala:43:14]
output io_bs_adr_valid, // @[SinkC.scala:43:14]
output io_bs_adr_bits_noop, // @[SinkC.scala:43:14]
output [3:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14]
output [10:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14]
output [1:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14]
output [1:0] io_bs_adr_bits_mask, // @[SinkC.scala:43:14]
output [127:0] io_bs_dat_data, // @[SinkC.scala:43:14]
output io_rel_pop_ready, // @[SinkC.scala:43:14]
input io_rel_pop_valid, // @[SinkC.scala:43:14]
input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14]
input io_rel_pop_bits_last, // @[SinkC.scala:43:14]
output [127:0] io_rel_beat_data, // @[SinkC.scala:43:14]
output io_rel_beat_corrupt // @[SinkC.scala:43:14]
);
wire [10:0] io_set_0; // @[SinkC.scala:41:7]
wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27]
wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27]
wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [5:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
wire [127:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire io_req_ready_0 = io_req_ready; // @[SinkC.scala:41:7]
wire io_c_valid_0 = io_c_valid; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_opcode_0 = io_c_bits_opcode; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_param_0 = io_c_bits_param; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_size_0 = io_c_bits_size; // @[SinkC.scala:41:7]
wire [5:0] io_c_bits_source_0 = io_c_bits_source; // @[SinkC.scala:41:7]
wire [31:0] io_c_bits_address_0 = io_c_bits_address; // @[SinkC.scala:41:7]
wire [127:0] io_c_bits_data_0 = io_c_bits_data; // @[SinkC.scala:41:7]
wire io_c_bits_corrupt_0 = io_c_bits_corrupt; // @[SinkC.scala:41:7]
wire [3:0] io_way_0 = io_way; // @[SinkC.scala:41:7]
wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkC.scala:41:7]
wire io_rel_pop_valid_0 = io_rel_pop_valid; // @[SinkC.scala:41:7]
wire [5:0] io_rel_pop_bits_index_0 = io_rel_pop_bits_index; // @[SinkC.scala:41:7]
wire io_rel_pop_bits_last_0 = io_rel_pop_bits_last; // @[SinkC.scala:41:7]
wire io_req_bits_prio_0 = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_prio_1 = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_control = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_prio_2 = 1'h1; // @[SinkC.scala:41:7]
wire [1:0] bs_adr_bits_mask = 2'h3; // @[SinkC.scala:96:22]
wire [1:0] _bs_adr_bits_mask_T = 2'h3; // @[SinkC.scala:104:25]
wire _io_req_valid_T_6; // @[SinkC.scala:136:61]
wire [8:0] tag_1; // @[Parameters.scala:217:9]
wire [5:0] offset_1; // @[Parameters.scala:217:50]
wire [10:0] set_1; // @[Parameters.scala:217:28]
wire _io_resp_valid_T_5; // @[SinkC.scala:107:57]
wire last; // @[Edges.scala:232:33]
wire hasData; // @[Edges.scala:102:36]
wire [10:0] _io_set_T; // @[SinkC.scala:92:18]
wire [10:0] bs_adr_bits_set = io_set_0; // @[SinkC.scala:41:7, :96:22]
wire [3:0] bs_adr_bits_way = io_way_0; // @[SinkC.scala:41:7, :96:22]
wire _io_rel_pop_ready_T_2; // @[SinkC.scala:160:43]
wire [2:0] io_req_bits_opcode_0; // @[SinkC.scala:41:7]
wire [2:0] io_req_bits_param_0; // @[SinkC.scala:41:7]
wire [2:0] io_req_bits_size_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_source_0; // @[SinkC.scala:41:7]
wire [8:0] io_req_bits_tag_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_offset_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_put_0; // @[SinkC.scala:41:7]
wire [10:0] io_req_bits_set_0; // @[SinkC.scala:41:7]
wire io_req_valid_0; // @[SinkC.scala:41:7]
wire io_resp_bits_last_0; // @[SinkC.scala:41:7]
wire [10:0] io_resp_bits_set_0; // @[SinkC.scala:41:7]
wire [8:0] io_resp_bits_tag_0; // @[SinkC.scala:41:7]
wire [5:0] io_resp_bits_source_0; // @[SinkC.scala:41:7]
wire [2:0] io_resp_bits_param_0; // @[SinkC.scala:41:7]
wire io_resp_bits_data_0; // @[SinkC.scala:41:7]
wire io_resp_valid_0; // @[SinkC.scala:41:7]
wire io_c_ready_0; // @[SinkC.scala:41:7]
wire io_bs_adr_bits_noop_0; // @[SinkC.scala:41:7]
wire [3:0] io_bs_adr_bits_way_0; // @[SinkC.scala:41:7]
wire [10:0] io_bs_adr_bits_set_0; // @[SinkC.scala:41:7]
wire [1:0] io_bs_adr_bits_beat_0; // @[SinkC.scala:41:7]
wire [1:0] io_bs_adr_bits_mask_0; // @[SinkC.scala:41:7]
wire io_bs_adr_valid_0; // @[SinkC.scala:41:7]
wire [127:0] io_bs_dat_data_0; // @[SinkC.scala:41:7]
wire io_rel_pop_ready_0; // @[SinkC.scala:41:7]
wire [127:0] io_rel_beat_data_0; // @[SinkC.scala:41:7]
wire io_rel_beat_corrupt_0; // @[SinkC.scala:41:7]
wire _offset_T = _c_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21]
wire _offset_T_1 = _c_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21]
wire _offset_T_2 = _c_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21]
wire _offset_T_3 = _c_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21]
wire _offset_T_4 = _c_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21]
wire _offset_T_5 = _c_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21]
wire _offset_T_6 = _c_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21]
wire _offset_T_7 = _c_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21]
wire _offset_T_8 = _c_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21]
wire _offset_T_9 = _c_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21]
wire _offset_T_10 = _c_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21]
wire _offset_T_11 = _c_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21]
wire _offset_T_12 = _c_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21]
wire _offset_T_13 = _c_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21]
wire _offset_T_14 = _c_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21]
wire _offset_T_15 = _c_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21]
wire _offset_T_16 = _c_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21]
wire _offset_T_17 = _c_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21]
wire _offset_T_18 = _c_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21]
wire _offset_T_19 = _c_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21]
wire _offset_T_20 = _c_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21]
wire _offset_T_21 = _c_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21]
wire _offset_T_22 = _c_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21]
wire _offset_T_23 = _c_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21]
wire _offset_T_24 = _c_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21]
wire _offset_T_25 = _c_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21]
wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_lo_hi_hi = {_offset_T_5, _offset_T_4}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, _offset_T_3}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_lo_hi_lo_hi = {_offset_T_8, _offset_T_7}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_6}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_lo = {_offset_T_10, _offset_T_9}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_hi = {_offset_T_12, _offset_T_11}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_lo_lo_hi = {_offset_T_15, _offset_T_14}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_13}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_lo_hi_hi = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, _offset_T_16}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_hi_lo_hi = {_offset_T_21, _offset_T_20}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_19}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_lo = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_hi = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21]
wire [25:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21]
wire [19:0] set = offset[25:6]; // @[Parameters.scala:214:21, :215:22]
wire [8:0] tag = set[19:11]; // @[Parameters.scala:215:22, :216:19]
assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9]
assign io_req_bits_tag_0 = tag_1; // @[SinkC.scala:41:7]
assign io_resp_bits_tag_0 = tag_1; // @[SinkC.scala:41:7]
assign set_1 = set[10:0]; // @[Parameters.scala:215:22, :217:28]
assign io_req_bits_set_0 = set_1; // @[SinkC.scala:41:7]
assign io_resp_bits_set_0 = set_1; // @[SinkC.scala:41:7]
assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50]
assign io_req_bits_offset_0 = offset_1; // @[SinkC.scala:41:7]
wire _q_io_deq_ready_T_7; // @[SinkC.scala:134:19]
wire _T = _q_io_deq_ready_T_7 & _c_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21]
wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] r_beats1_decode = _r_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire r_beats1_opdata = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
assign hasData = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
wire [1:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] r_counter; // @[Edges.scala:229:27]
wire [2:0] _r_counter1_T = {1'h0, r_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] r_counter1 = _r_counter1_T[1:0]; // @[Edges.scala:230:28]
wire first = r_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33]
wire r_3 = last & _T; // @[Decoupled.scala:51:35]
wire [1:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
assign io_resp_bits_data_0 = hasData; // @[Edges.scala:102:36]
wire _raw_resp_T = _c_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21]
wire _raw_resp_T_1 = _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21]
wire raw_resp = _raw_resp_T | _raw_resp_T_1; // @[SinkC.scala:78:{34,58,75}]
reg resp_r; // @[SinkC.scala:79:48]
wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_149 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_405
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_149( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_405 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a17d64s8k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a17d64s8k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [16:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [16:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [16:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [16:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [16:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [7:0] saved_source; // @[Repeater.scala:21:18]
reg [16:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
output io : { flip bypass : UInt<1>, pending : UInt<1>}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_90
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect nodeIn, auto.in
regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1)
connect in_reset, UInt<1>(0h0)
reg bypass_reg : UInt<1>, clock
node bypass = mux(in_reset, io.bypass, bypass_reg)
regreset flight : UInt<2>, clock, reset, UInt<2>(0h0)
node _T = and(nodeIn.a.ready, nodeIn.a.valid)
node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 2)
node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0))
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node a_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node a_last = or(_r_last_T, _r_last_T_1)
node r_3 = and(a_last, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(a_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid)
node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size)
node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0)
node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4)
node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2)
node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2)
node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0))
node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0))
regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1))
node r_counter1_1 = tail(_r_counter1_T_1, 1)
node b_first = eq(r_counter_1, UInt<1>(0h0))
node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1))
node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0))
node b_last = or(_r_last_T_2, _r_last_T_3)
node r_3_1 = and(b_last, _T_1)
node _r_count_T_1 = not(r_counter1_1)
node r_4_1 = and(r_beats1_1, _r_count_T_1)
when _T_1 :
node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1)
connect r_counter_1, _r_counter_T_1
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid)
node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size)
node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0)
node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7)
node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2)
node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0)
node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0))
regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1))
node r_counter1_2 = tail(_r_counter1_T_2, 1)
node c_first = eq(r_counter_2, UInt<1>(0h0))
node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1))
node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0))
node c_last = or(_r_last_T_4, _r_last_T_5)
node r_3_2 = and(c_last, _T_2)
node _r_count_T_2 = not(r_counter1_2)
node r_4_2 = and(r_beats1_2, _r_count_T_2)
when _T_2 :
node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2)
connect r_counter_2, _r_counter_T_2
node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid)
node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size)
node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0)
node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10)
node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2)
node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0)
node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0))
regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1))
node r_counter1_3 = tail(_r_counter1_T_3, 1)
node d_first = eq(r_counter_3, UInt<1>(0h0))
node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1))
node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0))
node d_last = or(_r_last_T_6, _r_last_T_7)
node r_3_3 = and(d_last, _T_3)
node _r_count_T_3 = not(r_counter1_3)
node r_4_3 = and(r_beats1_3, _r_count_T_3)
when _T_3 :
node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3)
connect r_counter_3, _r_counter_T_3
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid)
regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1))
node r_counter1_4 = tail(_r_counter1_T_4, 1)
node e_first = eq(r_counter_4, UInt<1>(0h0))
node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1))
node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0))
node e_last = or(_r_last_T_8, _r_last_T_9)
node r_3_4 = and(e_last, _T_4)
node _r_count_T_4 = not(r_counter1_4)
node r_4_4 = and(UInt<1>(0h0), _r_count_T_4)
when _T_4 :
node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4)
connect r_counter_4, _r_counter_T_4
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.mask, UInt<4>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.mask, UInt<4>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<2>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2)
node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1)
node c_request = and(_T_5, _T_6)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_8 = eq(_T_7, UInt<1>(0h0))
node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node c_response = or(_T_8, _T_10)
node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2)
node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node d_request = and(_T_11, _T_13)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_14.bits.sink, UInt<1>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_inc_T_1 = and(_a_inc_T, a_first)
node a_inc = and(_a_inc_T_1, UInt<1>(0h1))
wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_inc_WIRE.bits.data, UInt<32>(0h0)
connect _b_inc_WIRE.bits.mask, UInt<4>(0h0)
connect _b_inc_WIRE.bits.address, UInt<9>(0h0)
connect _b_inc_WIRE.bits.source, UInt<1>(0h0)
connect _b_inc_WIRE.bits.size, UInt<2>(0h0)
connect _b_inc_WIRE.bits.param, UInt<2>(0h0)
connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_inc_WIRE.valid, UInt<1>(0h0)
connect _b_inc_WIRE.ready, UInt<1>(0h0)
wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits
connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid
connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready
node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid)
node _b_inc_T_1 = and(_b_inc_T, b_first)
node b_inc = and(_b_inc_T_1, UInt<1>(0h1))
wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_inc_WIRE.bits.data, UInt<32>(0h0)
connect _c_inc_WIRE.bits.address, UInt<9>(0h0)
connect _c_inc_WIRE.bits.source, UInt<1>(0h0)
connect _c_inc_WIRE.bits.size, UInt<2>(0h0)
connect _c_inc_WIRE.bits.param, UInt<3>(0h0)
connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_inc_WIRE.valid, UInt<1>(0h0)
connect _c_inc_WIRE.ready, UInt<1>(0h0)
wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits
connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid
connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready
node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid)
node _c_inc_T_1 = and(_c_inc_T, c_first)
node c_inc = and(_c_inc_T_1, c_request)
node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_inc_T_1 = and(_d_inc_T, d_first)
node d_inc = and(_d_inc_T_1, d_request)
wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE.bits.sink, UInt<1>(0h0)
connect _e_inc_WIRE.valid, UInt<1>(0h0)
connect _e_inc_WIRE.ready, UInt<1>(0h0)
wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits
connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid
connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready
node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid)
node _e_inc_T_1 = and(_e_inc_T, e_first)
node e_inc = and(_e_inc_T_1, UInt<1>(0h0))
node inc = cat(a_inc, d_inc)
node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_dec_T_1 = and(_a_dec_T, a_last)
node a_dec = and(_a_dec_T_1, UInt<1>(0h0))
wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_dec_WIRE.bits.data, UInt<32>(0h0)
connect _b_dec_WIRE.bits.mask, UInt<4>(0h0)
connect _b_dec_WIRE.bits.address, UInt<9>(0h0)
connect _b_dec_WIRE.bits.source, UInt<1>(0h0)
connect _b_dec_WIRE.bits.size, UInt<2>(0h0)
connect _b_dec_WIRE.bits.param, UInt<2>(0h0)
connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_dec_WIRE.valid, UInt<1>(0h0)
connect _b_dec_WIRE.ready, UInt<1>(0h0)
wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits
connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid
connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready
node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid)
node _b_dec_T_1 = and(_b_dec_T, b_last)
node b_dec = and(_b_dec_T_1, UInt<1>(0h0))
wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_dec_WIRE.bits.data, UInt<32>(0h0)
connect _c_dec_WIRE.bits.address, UInt<9>(0h0)
connect _c_dec_WIRE.bits.source, UInt<1>(0h0)
connect _c_dec_WIRE.bits.size, UInt<2>(0h0)
connect _c_dec_WIRE.bits.param, UInt<3>(0h0)
connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_dec_WIRE.valid, UInt<1>(0h0)
connect _c_dec_WIRE.ready, UInt<1>(0h0)
wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits
connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid
connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready
node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid)
node _c_dec_T_1 = and(_c_dec_T, c_last)
node c_dec = and(_c_dec_T_1, c_response)
node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_dec_T_1 = and(_d_dec_T, d_last)
node d_dec = and(_d_dec_T_1, UInt<1>(0h1))
wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE.bits.sink, UInt<1>(0h0)
connect _e_dec_WIRE.valid, UInt<1>(0h0)
connect _e_dec_WIRE.ready, UInt<1>(0h0)
wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits
connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid
connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready
node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid)
node _e_dec_T_1 = and(_e_dec_T, e_last)
node e_dec = and(_e_dec_T_1, UInt<1>(0h1))
node dec = cat(a_dec, d_dec)
node _next_flight_T = bits(inc, 0, 0)
node _next_flight_T_1 = bits(inc, 1, 1)
node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1)
node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0)
node _next_flight_T_4 = add(flight, _next_flight_T_3)
node _next_flight_T_5 = tail(_next_flight_T_4, 1)
node _next_flight_T_6 = bits(dec, 0, 0)
node _next_flight_T_7 = bits(dec, 1, 1)
node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7)
node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0)
node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9)
node next_flight = tail(_next_flight_T_10, 1)
connect flight, next_flight
node _io_pending_T = gt(flight, UInt<1>(0h0))
connect io.pending, _io_pending_T
node _T_14 = eq(next_flight, UInt<1>(0h0))
node _T_15 = or(in_reset, _T_14)
when _T_15 :
connect bypass_reg, io.bypass
node _stall_T = neq(bypass, io.bypass)
node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid)
node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0)
node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1)
node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2)
node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0))
node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0))
regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1))
node stall_counter1 = tail(_stall_counter1_T, 1)
node stall_first = eq(stall_counter, UInt<1>(0h0))
node _stall_last_T = eq(stall_counter, UInt<1>(0h1))
node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0))
node stall_last = or(_stall_last_T, _stall_last_T_1)
node stall_done = and(stall_last, _stall_T_1)
node _stall_count_T = not(stall_counter1)
node stall_count = and(stall_beats1, _stall_count_T)
when _stall_T_1 :
node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1)
connect stall_counter, _stall_counter_T
node stall = and(_stall_T, stall_first)
node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid)
node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass)
connect nodeOut.a.valid, _nodeOut_a_valid_T_2
node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid)
node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0))
node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5)
connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6
node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0))
node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready)
node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1)
connect nodeIn.a.ready, _nodeIn_a_ready_T_2
connect nodeOut.a.bits, nodeIn.a.bits
connect x1_nodeOut.a.bits, nodeIn.a.bits
node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass)
connect nodeOut.d.ready, _nodeOut_d_ready_T
node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0))
node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1)
connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2
node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid)
connect nodeIn.d.valid, _nodeIn_d_valid_T
wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out, nodeIn.d.bits
connect nodeIn_d_bits_out, nodeOut.d.bits
wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out_1, nodeIn.d.bits
connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits
node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt
connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data
connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied
connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink
connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source
connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size
connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.mask, UInt<4>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<2>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.valid, UInt<1>(0h0)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.ready, UInt<1>(0h1)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.mask, UInt<4>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
connect _WIRE_25.ready, UInt<1>(0h1)
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<32>(0h0)
connect _WIRE_26.bits.address, UInt<128>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<2>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
connect _WIRE_27.valid, UInt<1>(0h0)
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_28.bits.sink, UInt<1>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<32>(0h0)
connect _WIRE_30.bits.mask, UInt<4>(0h0)
connect _WIRE_30.bits.address, UInt<9>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<2>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<32>(0h0)
connect _WIRE_32.bits.address, UInt<9>(0h0)
connect _WIRE_32.bits.source, UInt<1>(0h0)
connect _WIRE_32.bits.size, UInt<2>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
connect _WIRE_33.valid, UInt<1>(0h0)
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_34.bits.sink, UInt<1>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
connect _WIRE_35.valid, UInt<1>(0h0)
extmodule plusarg_reader_183 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_184 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBusBypassBar( // @[BusBypass.scala:66:9]
input clock, // @[BusBypass.scala:66:9]
input reset, // @[BusBypass.scala:66:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_bypass // @[BusBypass.scala:67:16]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9]
wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9]
wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71]
wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71]
wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46]
wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9]
wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53]
wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_last = 1'h1; // @[Edges.scala:232:33]
wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire b_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire c_last = 1'h1; // @[Edges.scala:232:33]
wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43]
wire d_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28]
wire e_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43]
wire e_last = 1'h1; // @[Edges.scala:232:33]
wire c_response = 1'h1; // @[Edges.scala:82:41]
wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire stall_last = 1'h1; // @[Edges.scala:232:33]
wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire r_beats1 = 1'h0; // @[Edges.scala:221:14]
wire r_4 = 1'h0; // @[Edges.scala:234:25]
wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire r_3_1 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27]
wire r_4_1 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25]
wire r_3_2 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27]
wire r_4_2 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14]
wire r_4_3 = 1'h0; // @[Edges.scala:234:25]
wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25]
wire r_3_4 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27]
wire r_4_4 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21]
wire c_request = 1'h0; // @[Edges.scala:68:40]
wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26]
wire b_inc = 1'h0; // @[Edges.scala:311:37]
wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26]
wire c_inc = 1'h0; // @[Edges.scala:312:37]
wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26]
wire e_inc = 1'h0; // @[Edges.scala:314:37]
wire a_dec = 1'h0; // @[Edges.scala:317:36]
wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26]
wire b_dec = 1'h0; // @[Edges.scala:318:36]
wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26]
wire c_dec = 1'h0; // @[Edges.scala:319:36]
wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26]
wire e_dec = 1'h0; // @[Edges.scala:321:36]
wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire stall_beats1 = 1'h0; // @[Edges.scala:221:14]
wire stall_count = 1'h0; // @[Edges.scala:234:25]
wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire _io_pending_T; // @[BusBypass.scala:84:27]
wire auto_in_a_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire auto_in_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
wire io_pending; // @[BusBypass.scala:66:9]
wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
reg in_reset; // @[BusBypass.scala:79:27]
reg bypass_reg; // @[BusBypass.scala:80:25]
wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21]
reg [1:0] flight; // @[Edges.scala:295:25]
wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35]
wire r_3; // @[Edges.scala:233:22]
assign r_3 = _T; // @[Decoupled.scala:51:35]
wire _a_inc_T; // @[Decoupled.scala:51:35]
assign _a_inc_T = _T; // @[Decoupled.scala:51:35]
wire _a_dec_T; // @[Decoupled.scala:51:35]
assign _a_dec_T = _T; // @[Decoupled.scala:51:35]
wire _stall_T_1; // @[Decoupled.scala:51:35]
assign _stall_T_1 = _T; // @[Decoupled.scala:51:35]
wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg r_counter; // @[Edges.scala:229:27]
wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25]
wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire r_3_3; // @[Edges.scala:233:22]
assign r_3_3 = _T_3; // @[Decoupled.scala:51:35]
wire _d_inc_T; // @[Decoupled.scala:51:35]
assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35]
wire _d_dec_T; // @[Decoupled.scala:51:35]
assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35]
wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg r_counter_3; // @[Edges.scala:229:27]
wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28]
wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25]
wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}]
wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35]
wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}]
wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35]
wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}]
wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18]
wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35]
wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35]
wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}]
wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18]
wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40]
wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40]
wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40]
wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40]
wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}]
wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30]
wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56]
wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56]
wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56]
wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56]
wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}]
wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46]
assign _io_pending_T = |flight; // @[Edges.scala:295:25]
assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27]
wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25]
wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35]
wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg stall_counter; // @[Edges.scala:229:27]
wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28]
wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25]
wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27]
wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire stall = _stall_T & stall_first; // @[Edges.scala:231:25]
wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21]
wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}]
assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21]
wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}]
wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45]
assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}]
assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21]
wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34]
assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}]
assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18]
assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32]
assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35]
assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}]
assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24]
assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
always @(posedge clock) begin // @[BusBypass.scala:66:9]
if (reset) begin // @[BusBypass.scala:66:9]
in_reset <= 1'h1; // @[BusBypass.scala:79:27]
flight <= 2'h0; // @[Edges.scala:295:25]
r_counter <= 1'h0; // @[Edges.scala:229:27]
r_counter_3 <= 1'h0; // @[Edges.scala:229:27]
stall_counter <= 1'h0; // @[Edges.scala:229:27]
end
else begin // @[BusBypass.scala:66:9]
in_reset <= 1'h0; // @[BusBypass.scala:79:27]
flight <= next_flight; // @[Edges.scala:295:25, :324:46]
if (_T) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
if (_T_3) // @[Decoupled.scala:51:35]
r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21]
if (_stall_T_1) // @[Decoupled.scala:51:35]
stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21]
end
if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46]
bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25]
always @(posedge)
TLMonitor_90 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_TLBundleD_a32d64s2k3z4c :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, async : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
wire sink_ready : UInt<1>
connect sink_ready, UInt<1>(0h1)
reg mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], clock
node _widx_T = asAsyncReset(reset)
node _widx_T_1 = and(io.enq.ready, io.enq.valid)
node _widx_T_2 = eq(sink_ready, UInt<1>(0h0))
wire widx_incremented : UInt<4>
regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0)
connect widx_widx_bin, widx_incremented
node _widx_incremented_T = add(widx_widx_bin, _widx_T_1)
node _widx_incremented_T_1 = tail(_widx_incremented_T, 1)
node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1)
connect widx_incremented, _widx_incremented_T_2
node _widx_T_3 = shr(widx_incremented, 1)
node widx = xor(widx_incremented, _widx_T_3)
inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_3
connect ridx_ridx_gray.clock, clock
connect ridx_ridx_gray.reset, reset
connect ridx_ridx_gray.io.d, io.async.ridx
wire ridx : UInt<4>
connect ridx, ridx_ridx_gray.io.q
node _ready_T = xor(ridx, UInt<4>(0hc))
node _ready_T_1 = neq(widx, _ready_T)
node ready = and(sink_ready, _ready_T_1)
node _index_T = bits(io.async.widx, 2, 0)
node _index_T_1 = bits(io.async.widx, 3, 3)
node _index_T_2 = shl(_index_T_1, 2)
node index = xor(_index_T, _index_T_2)
node _T = and(io.enq.ready, io.enq.valid)
when _T :
connect mem[index], io.enq.bits
node _ready_reg_T = asAsyncReset(reset)
regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0)
connect ready_reg, ready
node _io_enq_ready_T = and(ready_reg, sink_ready)
connect io.enq.ready, _io_enq_ready_T
node _widx_reg_T = asAsyncReset(reset)
regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0)
connect widx_gray, widx
connect io.async.widx, widx_gray
connect io.async.mem, mem
inst source_valid_0 of AsyncValidSync_12
inst source_valid_1 of AsyncValidSync_13
inst sink_extend of AsyncValidSync_14
inst sink_valid of AsyncValidSync_15
node _source_valid_0_reset_T = asUInt(reset)
node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1)
node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2)
connect source_valid_0.reset, _source_valid_0_reset_T_3
node _source_valid_1_reset_T = asUInt(reset)
node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1)
node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2)
connect source_valid_1.reset, _source_valid_1_reset_T_3
node _sink_extend_reset_T = asUInt(reset)
node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1)
node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2)
connect sink_extend.reset, _sink_extend_reset_T_3
node _sink_valid_reset_T = asAsyncReset(reset)
connect sink_valid.reset, _sink_valid_reset_T
connect source_valid_0.clock, clock
connect source_valid_1.clock, clock
connect sink_extend.clock, clock
connect sink_valid.clock, clock
connect source_valid_0.io.in, UInt<1>(0h1)
connect source_valid_1.io.in, source_valid_0.io.out
connect io.async.safe.widx_valid, source_valid_1.io.out
connect sink_extend.io.in, io.async.safe.ridx_valid
connect sink_valid.io.in, sink_extend.io.out
connect sink_ready, sink_valid.io.out
node _io_async_safe_source_reset_n_T = asUInt(reset)
node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0))
connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 | module AsyncQueueSource_TLBundleD_a32d64s2k3z4c( // @[AsyncQueue.scala:70:7]
input clock, // @[AsyncQueue.scala:70:7]
input reset, // @[AsyncQueue.scala:70:7]
output io_enq_ready, // @[AsyncQueue.scala:73:14]
input io_enq_valid, // @[AsyncQueue.scala:73:14]
input [2:0] io_enq_bits_opcode, // @[AsyncQueue.scala:73:14]
input [1:0] io_enq_bits_param, // @[AsyncQueue.scala:73:14]
input [3:0] io_enq_bits_size, // @[AsyncQueue.scala:73:14]
input [1:0] io_enq_bits_source, // @[AsyncQueue.scala:73:14]
input [2:0] io_enq_bits_sink, // @[AsyncQueue.scala:73:14]
input io_enq_bits_denied, // @[AsyncQueue.scala:73:14]
input [63:0] io_enq_bits_data, // @[AsyncQueue.scala:73:14]
input io_enq_bits_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_0_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_0_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_0_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_0_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_1_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_1_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_1_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_1_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_1_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_1_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_2_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_2_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_2_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_2_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_2_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_2_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_3_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_3_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_3_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_3_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_3_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_3_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_4_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_4_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_4_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_4_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_4_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_4_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_5_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_5_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_5_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_5_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_5_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_5_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_6_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_6_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_6_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_6_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_6_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_6_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_7_param, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_7_size, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_7_source, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_7_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_7_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_7_corrupt, // @[AsyncQueue.scala:73:14]
input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14]
input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14]
input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14]
);
wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30]
wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[AsyncQueue.scala:70:7]
wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[AsyncQueue.scala:70:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[AsyncQueue.scala:70:7]
wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[AsyncQueue.scala:70:7]
wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[AsyncQueue.scala:70:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7]
wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7]
wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7]
wire _widx_T = reset; // @[AsyncQueue.scala:83:30]
wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35]
wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34]
wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36]
wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36]
wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36]
wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35]
wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34]
wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29]
wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27]
wire io_enq_ready_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_0_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_0_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_0_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_0_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_0_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_0_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_1_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_1_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_1_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_1_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_1_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_1_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_1_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_1_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_2_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_2_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_2_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_2_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_2_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_2_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_2_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_2_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_3_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_3_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_3_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_3_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_3_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_3_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_3_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_3_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_4_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_4_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_4_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_4_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_4_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_4_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_4_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_4_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_5_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_5_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_5_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_5_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_5_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_5_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_5_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_5_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_6_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_6_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_6_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_6_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_6_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_6_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_6_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_6_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_7_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_7_param_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_7_size_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_7_source_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_7_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_7_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_7_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_7_corrupt_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7]
wire sink_ready; // @[AsyncQueue.scala:81:28]
reg [2:0] mem_0_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_opcode_0 = mem_0_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_0_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_param_0 = mem_0_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_0_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_size_0 = mem_0_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_0_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_source_0 = mem_0_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_0_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_sink_0 = mem_0_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_denied_0 = mem_0_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_0_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_data_0 = mem_0_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_corrupt_0 = mem_0_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_1_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_opcode_0 = mem_1_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_1_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_param_0 = mem_1_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_1_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_size_0 = mem_1_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_1_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_source_0 = mem_1_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_1_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_sink_0 = mem_1_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_1_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_denied_0 = mem_1_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_1_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_data_0 = mem_1_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_1_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_corrupt_0 = mem_1_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_2_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_opcode_0 = mem_2_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_2_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_param_0 = mem_2_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_2_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_size_0 = mem_2_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_2_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_source_0 = mem_2_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_2_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_sink_0 = mem_2_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_2_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_denied_0 = mem_2_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_2_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_data_0 = mem_2_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_2_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_corrupt_0 = mem_2_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_3_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_opcode_0 = mem_3_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_3_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_param_0 = mem_3_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_3_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_size_0 = mem_3_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_3_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_source_0 = mem_3_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_3_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_sink_0 = mem_3_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_3_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_denied_0 = mem_3_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_3_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_data_0 = mem_3_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_3_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_corrupt_0 = mem_3_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_4_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_opcode_0 = mem_4_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_4_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_param_0 = mem_4_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_4_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_size_0 = mem_4_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_4_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_source_0 = mem_4_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_4_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_sink_0 = mem_4_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_4_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_denied_0 = mem_4_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_4_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_data_0 = mem_4_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_4_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_corrupt_0 = mem_4_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_5_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_opcode_0 = mem_5_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_5_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_param_0 = mem_5_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_5_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_size_0 = mem_5_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_5_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_source_0 = mem_5_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_5_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_sink_0 = mem_5_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_5_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_denied_0 = mem_5_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_5_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_data_0 = mem_5_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_5_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_corrupt_0 = mem_5_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_6_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_opcode_0 = mem_6_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_6_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_param_0 = mem_6_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_6_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_size_0 = mem_6_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_6_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_source_0 = mem_6_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_6_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_sink_0 = mem_6_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_6_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_denied_0 = mem_6_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_6_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_data_0 = mem_6_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_6_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_corrupt_0 = mem_6_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_7_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_opcode_0 = mem_7_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_7_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_param_0 = mem_7_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_7_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_size_0 = mem_7_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_7_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_source_0 = mem_7_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_7_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_sink_0 = mem_7_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_7_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_denied_0 = mem_7_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_7_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_data_0 = mem_7_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_7_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_corrupt_0 = mem_7_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77]
wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]
assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] ridx; // @[ShiftReg.scala:48:24]
wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24]
wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}]
wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}]
wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52]
wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}]
reg ready_reg; // @[AsyncQueue.scala:90:56]
assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29]
assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29]
reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55]
assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55]
wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46]
wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}]
wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}]
wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46]
wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}]
wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}]
wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46]
wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}]
wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}]
assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}]
assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27]
always @(posedge clock) begin // @[AsyncQueue.scala:70:7]
if (_widx_T_1 & index == 3'h0) begin // @[Decoupled.scala:51:35]
mem_0_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h1) begin // @[Decoupled.scala:51:35]
mem_1_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h2) begin // @[Decoupled.scala:51:35]
mem_2_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h3) begin // @[Decoupled.scala:51:35]
mem_3_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h4) begin // @[Decoupled.scala:51:35]
mem_4_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h5) begin // @[Decoupled.scala:51:35]
mem_5_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h6) begin // @[Decoupled.scala:51:35]
mem_6_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & (&index)) begin // @[Decoupled.scala:51:35]
mem_7_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
always @(posedge)
always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30]
if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30]
widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:70:7]
widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35]
if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35]
ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56]
else // @[AsyncQueue.scala:70:7]
ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56]
always @(posedge, posedge)
always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34]
if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34]
widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55]
else // @[AsyncQueue.scala:70:7]
widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_65 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_65( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_23 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_23( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_5 :
input clock : Clock
input reset : Reset
output auto : { }
skip | module TLBuffer_5( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset // @[Buffer.scala:40:9]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_12 :
output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 0, 0)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1))
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_12
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i1_e8_s24_12(); // @[INToRecFN.scala:43:7]
wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31]
wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44]
wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22]
wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33]
wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_in = 1'h1; // @[Mux.scala:50:70]
wire io_detectTininess = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70]
wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29]
wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23]
wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36]
RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_12 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_10 :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}}
inst q of Queue1_TLBundleC_a32d128s7k6z4c_10
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 4)
node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4)
node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6)
node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8)
node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11)
node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40))
node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0))
node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24)
node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26)
node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0)
connect has_body, has_body_opdata
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h28))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLCToNoC_10( // @[TilelinkAdapters.scala:151:7]
input clock, // @[TilelinkAdapters.scala:151:7]
input reset, // @[TilelinkAdapters.scala:151:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [7:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}]
reg [7:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}]
wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7]
if (reset) begin // @[TilelinkAdapters.scala:151:7]
head_counter <= 8'h0; // @[Edges.scala:229:27]
tail_counter <= 8'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7]
end
else begin // @[TilelinkAdapters.scala:151:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BoomNonBlockingDCache_1 :
input clock : Clock
input reset : Reset
output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
output io : { flip lsu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}}[1]}, s1_kill : UInt<1>[1], flip resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1], flip nack : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}}[1], brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, exception : UInt<1>, rob_pnr_idx : UInt<6>, rob_head_idx : UInt<6>, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, force_order : UInt<1>, flip ordered : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>}}}
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
inst wb of BoomWritebackUnit_1
connect wb.clock, clock
connect wb.reset, reset
inst prober of BoomProbeUnit_1
connect prober.clock, clock
connect prober.reset, reset
inst mshrs of BoomMSHRFile_1
connect mshrs.clock, clock
connect mshrs.reset, reset
connect mshrs.io.clear_all, io.lsu.force_order
connect mshrs.io.brupdate.b2.target_offset, io.lsu.brupdate.b2.target_offset
connect mshrs.io.brupdate.b2.jalr_target, io.lsu.brupdate.b2.jalr_target
connect mshrs.io.brupdate.b2.pc_sel, io.lsu.brupdate.b2.pc_sel
connect mshrs.io.brupdate.b2.cfi_type, io.lsu.brupdate.b2.cfi_type
connect mshrs.io.brupdate.b2.taken, io.lsu.brupdate.b2.taken
connect mshrs.io.brupdate.b2.mispredict, io.lsu.brupdate.b2.mispredict
connect mshrs.io.brupdate.b2.valid, io.lsu.brupdate.b2.valid
connect mshrs.io.brupdate.b2.uop.debug_tsrc, io.lsu.brupdate.b2.uop.debug_tsrc
connect mshrs.io.brupdate.b2.uop.debug_fsrc, io.lsu.brupdate.b2.uop.debug_fsrc
connect mshrs.io.brupdate.b2.uop.bp_xcpt_if, io.lsu.brupdate.b2.uop.bp_xcpt_if
connect mshrs.io.brupdate.b2.uop.bp_debug_if, io.lsu.brupdate.b2.uop.bp_debug_if
connect mshrs.io.brupdate.b2.uop.xcpt_ma_if, io.lsu.brupdate.b2.uop.xcpt_ma_if
connect mshrs.io.brupdate.b2.uop.xcpt_ae_if, io.lsu.brupdate.b2.uop.xcpt_ae_if
connect mshrs.io.brupdate.b2.uop.xcpt_pf_if, io.lsu.brupdate.b2.uop.xcpt_pf_if
connect mshrs.io.brupdate.b2.uop.fp_single, io.lsu.brupdate.b2.uop.fp_single
connect mshrs.io.brupdate.b2.uop.fp_val, io.lsu.brupdate.b2.uop.fp_val
connect mshrs.io.brupdate.b2.uop.frs3_en, io.lsu.brupdate.b2.uop.frs3_en
connect mshrs.io.brupdate.b2.uop.lrs2_rtype, io.lsu.brupdate.b2.uop.lrs2_rtype
connect mshrs.io.brupdate.b2.uop.lrs1_rtype, io.lsu.brupdate.b2.uop.lrs1_rtype
connect mshrs.io.brupdate.b2.uop.dst_rtype, io.lsu.brupdate.b2.uop.dst_rtype
connect mshrs.io.brupdate.b2.uop.ldst_val, io.lsu.brupdate.b2.uop.ldst_val
connect mshrs.io.brupdate.b2.uop.lrs3, io.lsu.brupdate.b2.uop.lrs3
connect mshrs.io.brupdate.b2.uop.lrs2, io.lsu.brupdate.b2.uop.lrs2
connect mshrs.io.brupdate.b2.uop.lrs1, io.lsu.brupdate.b2.uop.lrs1
connect mshrs.io.brupdate.b2.uop.ldst, io.lsu.brupdate.b2.uop.ldst
connect mshrs.io.brupdate.b2.uop.ldst_is_rs1, io.lsu.brupdate.b2.uop.ldst_is_rs1
connect mshrs.io.brupdate.b2.uop.flush_on_commit, io.lsu.brupdate.b2.uop.flush_on_commit
connect mshrs.io.brupdate.b2.uop.is_unique, io.lsu.brupdate.b2.uop.is_unique
connect mshrs.io.brupdate.b2.uop.is_sys_pc2epc, io.lsu.brupdate.b2.uop.is_sys_pc2epc
connect mshrs.io.brupdate.b2.uop.uses_stq, io.lsu.brupdate.b2.uop.uses_stq
connect mshrs.io.brupdate.b2.uop.uses_ldq, io.lsu.brupdate.b2.uop.uses_ldq
connect mshrs.io.brupdate.b2.uop.is_amo, io.lsu.brupdate.b2.uop.is_amo
connect mshrs.io.brupdate.b2.uop.is_fencei, io.lsu.brupdate.b2.uop.is_fencei
connect mshrs.io.brupdate.b2.uop.is_fence, io.lsu.brupdate.b2.uop.is_fence
connect mshrs.io.brupdate.b2.uop.mem_signed, io.lsu.brupdate.b2.uop.mem_signed
connect mshrs.io.brupdate.b2.uop.mem_size, io.lsu.brupdate.b2.uop.mem_size
connect mshrs.io.brupdate.b2.uop.mem_cmd, io.lsu.brupdate.b2.uop.mem_cmd
connect mshrs.io.brupdate.b2.uop.bypassable, io.lsu.brupdate.b2.uop.bypassable
connect mshrs.io.brupdate.b2.uop.exc_cause, io.lsu.brupdate.b2.uop.exc_cause
connect mshrs.io.brupdate.b2.uop.exception, io.lsu.brupdate.b2.uop.exception
connect mshrs.io.brupdate.b2.uop.stale_pdst, io.lsu.brupdate.b2.uop.stale_pdst
connect mshrs.io.brupdate.b2.uop.ppred_busy, io.lsu.brupdate.b2.uop.ppred_busy
connect mshrs.io.brupdate.b2.uop.prs3_busy, io.lsu.brupdate.b2.uop.prs3_busy
connect mshrs.io.brupdate.b2.uop.prs2_busy, io.lsu.brupdate.b2.uop.prs2_busy
connect mshrs.io.brupdate.b2.uop.prs1_busy, io.lsu.brupdate.b2.uop.prs1_busy
connect mshrs.io.brupdate.b2.uop.ppred, io.lsu.brupdate.b2.uop.ppred
connect mshrs.io.brupdate.b2.uop.prs3, io.lsu.brupdate.b2.uop.prs3
connect mshrs.io.brupdate.b2.uop.prs2, io.lsu.brupdate.b2.uop.prs2
connect mshrs.io.brupdate.b2.uop.prs1, io.lsu.brupdate.b2.uop.prs1
connect mshrs.io.brupdate.b2.uop.pdst, io.lsu.brupdate.b2.uop.pdst
connect mshrs.io.brupdate.b2.uop.rxq_idx, io.lsu.brupdate.b2.uop.rxq_idx
connect mshrs.io.brupdate.b2.uop.stq_idx, io.lsu.brupdate.b2.uop.stq_idx
connect mshrs.io.brupdate.b2.uop.ldq_idx, io.lsu.brupdate.b2.uop.ldq_idx
connect mshrs.io.brupdate.b2.uop.rob_idx, io.lsu.brupdate.b2.uop.rob_idx
connect mshrs.io.brupdate.b2.uop.csr_addr, io.lsu.brupdate.b2.uop.csr_addr
connect mshrs.io.brupdate.b2.uop.imm_packed, io.lsu.brupdate.b2.uop.imm_packed
connect mshrs.io.brupdate.b2.uop.taken, io.lsu.brupdate.b2.uop.taken
connect mshrs.io.brupdate.b2.uop.pc_lob, io.lsu.brupdate.b2.uop.pc_lob
connect mshrs.io.brupdate.b2.uop.edge_inst, io.lsu.brupdate.b2.uop.edge_inst
connect mshrs.io.brupdate.b2.uop.ftq_idx, io.lsu.brupdate.b2.uop.ftq_idx
connect mshrs.io.brupdate.b2.uop.br_tag, io.lsu.brupdate.b2.uop.br_tag
connect mshrs.io.brupdate.b2.uop.br_mask, io.lsu.brupdate.b2.uop.br_mask
connect mshrs.io.brupdate.b2.uop.is_sfb, io.lsu.brupdate.b2.uop.is_sfb
connect mshrs.io.brupdate.b2.uop.is_jal, io.lsu.brupdate.b2.uop.is_jal
connect mshrs.io.brupdate.b2.uop.is_jalr, io.lsu.brupdate.b2.uop.is_jalr
connect mshrs.io.brupdate.b2.uop.is_br, io.lsu.brupdate.b2.uop.is_br
connect mshrs.io.brupdate.b2.uop.iw_p2_poisoned, io.lsu.brupdate.b2.uop.iw_p2_poisoned
connect mshrs.io.brupdate.b2.uop.iw_p1_poisoned, io.lsu.brupdate.b2.uop.iw_p1_poisoned
connect mshrs.io.brupdate.b2.uop.iw_state, io.lsu.brupdate.b2.uop.iw_state
connect mshrs.io.brupdate.b2.uop.ctrl.is_std, io.lsu.brupdate.b2.uop.ctrl.is_std
connect mshrs.io.brupdate.b2.uop.ctrl.is_sta, io.lsu.brupdate.b2.uop.ctrl.is_sta
connect mshrs.io.brupdate.b2.uop.ctrl.is_load, io.lsu.brupdate.b2.uop.ctrl.is_load
connect mshrs.io.brupdate.b2.uop.ctrl.csr_cmd, io.lsu.brupdate.b2.uop.ctrl.csr_cmd
connect mshrs.io.brupdate.b2.uop.ctrl.fcn_dw, io.lsu.brupdate.b2.uop.ctrl.fcn_dw
connect mshrs.io.brupdate.b2.uop.ctrl.op_fcn, io.lsu.brupdate.b2.uop.ctrl.op_fcn
connect mshrs.io.brupdate.b2.uop.ctrl.imm_sel, io.lsu.brupdate.b2.uop.ctrl.imm_sel
connect mshrs.io.brupdate.b2.uop.ctrl.op2_sel, io.lsu.brupdate.b2.uop.ctrl.op2_sel
connect mshrs.io.brupdate.b2.uop.ctrl.op1_sel, io.lsu.brupdate.b2.uop.ctrl.op1_sel
connect mshrs.io.brupdate.b2.uop.ctrl.br_type, io.lsu.brupdate.b2.uop.ctrl.br_type
connect mshrs.io.brupdate.b2.uop.fu_code, io.lsu.brupdate.b2.uop.fu_code
connect mshrs.io.brupdate.b2.uop.iq_type, io.lsu.brupdate.b2.uop.iq_type
connect mshrs.io.brupdate.b2.uop.debug_pc, io.lsu.brupdate.b2.uop.debug_pc
connect mshrs.io.brupdate.b2.uop.is_rvc, io.lsu.brupdate.b2.uop.is_rvc
connect mshrs.io.brupdate.b2.uop.debug_inst, io.lsu.brupdate.b2.uop.debug_inst
connect mshrs.io.brupdate.b2.uop.inst, io.lsu.brupdate.b2.uop.inst
connect mshrs.io.brupdate.b2.uop.uopc, io.lsu.brupdate.b2.uop.uopc
connect mshrs.io.brupdate.b1.mispredict_mask, io.lsu.brupdate.b1.mispredict_mask
connect mshrs.io.brupdate.b1.resolve_mask, io.lsu.brupdate.b1.resolve_mask
connect mshrs.io.exception, io.lsu.exception
connect mshrs.io.rob_pnr_idx, io.lsu.rob_pnr_idx
connect mshrs.io.rob_head_idx, io.lsu.rob_head_idx
inst meta_0 of L1MetadataArray_1
connect meta_0.clock, clock
connect meta_0.reset, reset
inst metaWriteArb of Arbiter2_L1MetaWriteReq_1
connect metaWriteArb.clock, clock
connect metaWriteArb.reset, reset
inst metaReadArb of Arbiter6_BoomL1MetaReadReq_1
connect metaReadArb.clock, clock
connect metaReadArb.reset, reset
invalidate metaReadArb.io.in[0].bits.req[0].tag
invalidate metaReadArb.io.in[0].bits.req[0].way_en
invalidate metaReadArb.io.in[0].bits.req[0].idx
invalidate metaReadArb.io.in[0].valid
invalidate metaReadArb.io.in[0].ready
invalidate metaReadArb.io.in[1].bits.req[0].tag
invalidate metaReadArb.io.in[1].bits.req[0].way_en
invalidate metaReadArb.io.in[1].bits.req[0].idx
invalidate metaReadArb.io.in[1].valid
invalidate metaReadArb.io.in[1].ready
invalidate metaReadArb.io.in[2].bits.req[0].tag
invalidate metaReadArb.io.in[2].bits.req[0].way_en
invalidate metaReadArb.io.in[2].bits.req[0].idx
invalidate metaReadArb.io.in[2].valid
invalidate metaReadArb.io.in[2].ready
invalidate metaReadArb.io.in[3].bits.req[0].tag
invalidate metaReadArb.io.in[3].bits.req[0].way_en
invalidate metaReadArb.io.in[3].bits.req[0].idx
invalidate metaReadArb.io.in[3].valid
invalidate metaReadArb.io.in[3].ready
invalidate metaReadArb.io.in[4].bits.req[0].tag
invalidate metaReadArb.io.in[4].bits.req[0].way_en
invalidate metaReadArb.io.in[4].bits.req[0].idx
invalidate metaReadArb.io.in[4].valid
invalidate metaReadArb.io.in[4].ready
invalidate metaReadArb.io.in[5].bits.req[0].tag
invalidate metaReadArb.io.in[5].bits.req[0].way_en
invalidate metaReadArb.io.in[5].bits.req[0].idx
invalidate metaReadArb.io.in[5].valid
invalidate metaReadArb.io.in[5].ready
node _meta_0_io_write_valid_T = and(metaWriteArb.io.out.ready, metaWriteArb.io.out.valid)
connect meta_0.io.write.valid, _meta_0_io_write_valid_T
connect meta_0.io.write.bits.data.tag, metaWriteArb.io.out.bits.data.tag
connect meta_0.io.write.bits.data.coh.state, metaWriteArb.io.out.bits.data.coh.state
connect meta_0.io.write.bits.tag, metaWriteArb.io.out.bits.tag
connect meta_0.io.write.bits.way_en, metaWriteArb.io.out.bits.way_en
connect meta_0.io.write.bits.idx, metaWriteArb.io.out.bits.idx
connect meta_0.io.read.valid, metaReadArb.io.out.valid
connect meta_0.io.read.bits.tag, metaReadArb.io.out.bits.req[0].tag
connect meta_0.io.read.bits.way_en, metaReadArb.io.out.bits.req[0].way_en
connect meta_0.io.read.bits.idx, metaReadArb.io.out.bits.req[0].idx
connect metaReadArb.io.out.ready, meta_0.io.read.ready
connect metaWriteArb.io.out.ready, meta_0.io.write.ready
inst data of BoomDuplicatedDataArray_1
connect data.clock, clock
connect data.reset, reset
inst dataWriteArb of Arbiter2_L1DataWriteReq_1
connect dataWriteArb.clock, clock
connect dataWriteArb.reset, reset
inst dataReadArb of Arbiter3_BoomL1DataReadReq_1
connect dataReadArb.clock, clock
connect dataReadArb.reset, reset
invalidate dataReadArb.io.in[0].bits.valid[0]
invalidate dataReadArb.io.in[0].bits.req[0].addr
invalidate dataReadArb.io.in[0].bits.req[0].way_en
invalidate dataReadArb.io.in[0].valid
invalidate dataReadArb.io.in[0].ready
invalidate dataReadArb.io.in[1].bits.valid[0]
invalidate dataReadArb.io.in[1].bits.req[0].addr
invalidate dataReadArb.io.in[1].bits.req[0].way_en
invalidate dataReadArb.io.in[1].valid
invalidate dataReadArb.io.in[1].ready
invalidate dataReadArb.io.in[2].bits.valid[0]
invalidate dataReadArb.io.in[2].bits.req[0].addr
invalidate dataReadArb.io.in[2].bits.req[0].way_en
invalidate dataReadArb.io.in[2].valid
invalidate dataReadArb.io.in[2].ready
node _data_io_read_0_valid_T = and(dataReadArb.io.out.bits.valid[0], dataReadArb.io.out.valid)
connect data.io.read[0].valid, _data_io_read_0_valid_T
connect data.io.read[0].bits.addr, dataReadArb.io.out.bits.req[0].addr
connect data.io.read[0].bits.way_en, dataReadArb.io.out.bits.req[0].way_en
connect dataReadArb.io.out.ready, UInt<1>(0h1)
node _data_io_write_valid_T = and(dataWriteArb.io.out.ready, dataWriteArb.io.out.valid)
connect data.io.write.valid, _data_io_write_valid_T
connect data.io.write.bits.data, dataWriteArb.io.out.bits.data
connect data.io.write.bits.wmask, dataWriteArb.io.out.bits.wmask
connect data.io.write.bits.addr, dataWriteArb.io.out.bits.addr
connect data.io.write.bits.way_en, dataWriteArb.io.out.bits.way_en
connect dataWriteArb.io.out.ready, UInt<1>(0h1)
node _io_lsu_req_ready_T = and(metaReadArb.io.in[4].ready, dataReadArb.io.in[2].ready)
connect io.lsu.req.ready, _io_lsu_req_ready_T
connect metaReadArb.io.in[4].valid, io.lsu.req.valid
connect dataReadArb.io.in[2].valid, io.lsu.req.valid
node _metaReadArb_io_in_4_bits_req_0_idx_T = shr(io.lsu.req.bits[0].bits.addr, 6)
connect metaReadArb.io.in[4].bits.req[0].idx, _metaReadArb_io_in_4_bits_req_0_idx_T
invalidate metaReadArb.io.in[4].bits.req[0].way_en
invalidate metaReadArb.io.in[4].bits.req[0].tag
connect dataReadArb.io.in[2].bits.valid[0], io.lsu.req.bits[0].valid
connect dataReadArb.io.in[2].bits.req[0].addr, io.lsu.req.bits[0].bits.addr
node _dataReadArb_io_in_2_bits_req_0_way_en_T = not(UInt<2>(0h0))
connect dataReadArb.io.in[2].bits.req[0].way_en, _dataReadArb_io_in_2_bits_req_0_way_en_T
wire replay_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate replay_req[0].is_hella
invalidate replay_req[0].data
invalidate replay_req[0].addr
invalidate replay_req[0].uop.debug_tsrc
invalidate replay_req[0].uop.debug_fsrc
invalidate replay_req[0].uop.bp_xcpt_if
invalidate replay_req[0].uop.bp_debug_if
invalidate replay_req[0].uop.xcpt_ma_if
invalidate replay_req[0].uop.xcpt_ae_if
invalidate replay_req[0].uop.xcpt_pf_if
invalidate replay_req[0].uop.fp_single
invalidate replay_req[0].uop.fp_val
invalidate replay_req[0].uop.frs3_en
invalidate replay_req[0].uop.lrs2_rtype
invalidate replay_req[0].uop.lrs1_rtype
invalidate replay_req[0].uop.dst_rtype
invalidate replay_req[0].uop.ldst_val
invalidate replay_req[0].uop.lrs3
invalidate replay_req[0].uop.lrs2
invalidate replay_req[0].uop.lrs1
invalidate replay_req[0].uop.ldst
invalidate replay_req[0].uop.ldst_is_rs1
invalidate replay_req[0].uop.flush_on_commit
invalidate replay_req[0].uop.is_unique
invalidate replay_req[0].uop.is_sys_pc2epc
invalidate replay_req[0].uop.uses_stq
invalidate replay_req[0].uop.uses_ldq
invalidate replay_req[0].uop.is_amo
invalidate replay_req[0].uop.is_fencei
invalidate replay_req[0].uop.is_fence
invalidate replay_req[0].uop.mem_signed
invalidate replay_req[0].uop.mem_size
invalidate replay_req[0].uop.mem_cmd
invalidate replay_req[0].uop.bypassable
invalidate replay_req[0].uop.exc_cause
invalidate replay_req[0].uop.exception
invalidate replay_req[0].uop.stale_pdst
invalidate replay_req[0].uop.ppred_busy
invalidate replay_req[0].uop.prs3_busy
invalidate replay_req[0].uop.prs2_busy
invalidate replay_req[0].uop.prs1_busy
invalidate replay_req[0].uop.ppred
invalidate replay_req[0].uop.prs3
invalidate replay_req[0].uop.prs2
invalidate replay_req[0].uop.prs1
invalidate replay_req[0].uop.pdst
invalidate replay_req[0].uop.rxq_idx
invalidate replay_req[0].uop.stq_idx
invalidate replay_req[0].uop.ldq_idx
invalidate replay_req[0].uop.rob_idx
invalidate replay_req[0].uop.csr_addr
invalidate replay_req[0].uop.imm_packed
invalidate replay_req[0].uop.taken
invalidate replay_req[0].uop.pc_lob
invalidate replay_req[0].uop.edge_inst
invalidate replay_req[0].uop.ftq_idx
invalidate replay_req[0].uop.br_tag
invalidate replay_req[0].uop.br_mask
invalidate replay_req[0].uop.is_sfb
invalidate replay_req[0].uop.is_jal
invalidate replay_req[0].uop.is_jalr
invalidate replay_req[0].uop.is_br
invalidate replay_req[0].uop.iw_p2_poisoned
invalidate replay_req[0].uop.iw_p1_poisoned
invalidate replay_req[0].uop.iw_state
invalidate replay_req[0].uop.ctrl.is_std
invalidate replay_req[0].uop.ctrl.is_sta
invalidate replay_req[0].uop.ctrl.is_load
invalidate replay_req[0].uop.ctrl.csr_cmd
invalidate replay_req[0].uop.ctrl.fcn_dw
invalidate replay_req[0].uop.ctrl.op_fcn
invalidate replay_req[0].uop.ctrl.imm_sel
invalidate replay_req[0].uop.ctrl.op2_sel
invalidate replay_req[0].uop.ctrl.op1_sel
invalidate replay_req[0].uop.ctrl.br_type
invalidate replay_req[0].uop.fu_code
invalidate replay_req[0].uop.iq_type
invalidate replay_req[0].uop.debug_pc
invalidate replay_req[0].uop.is_rvc
invalidate replay_req[0].uop.debug_inst
invalidate replay_req[0].uop.inst
invalidate replay_req[0].uop.uopc
connect replay_req[0].uop, mshrs.io.replay.bits.uop
connect replay_req[0].addr, mshrs.io.replay.bits.addr
connect replay_req[0].data, mshrs.io.replay.bits.data
connect replay_req[0].is_hella, mshrs.io.replay.bits.is_hella
node _mshrs_io_replay_ready_T = and(metaReadArb.io.in[0].ready, dataReadArb.io.in[0].ready)
connect mshrs.io.replay.ready, _mshrs_io_replay_ready_T
connect metaReadArb.io.in[0].valid, mshrs.io.replay.valid
node _metaReadArb_io_in_0_bits_req_0_idx_T = shr(mshrs.io.replay.bits.addr, 6)
connect metaReadArb.io.in[0].bits.req[0].idx, _metaReadArb_io_in_0_bits_req_0_idx_T
invalidate metaReadArb.io.in[0].bits.req[0].way_en
invalidate metaReadArb.io.in[0].bits.req[0].tag
connect dataReadArb.io.in[0].valid, mshrs.io.replay.valid
connect dataReadArb.io.in[0].bits.req[0].addr, mshrs.io.replay.bits.addr
connect dataReadArb.io.in[0].bits.req[0].way_en, mshrs.io.replay.bits.way_en
wire _WIRE : UInt<1>[1]
connect _WIRE[0], UInt<1>(0h1)
connect dataReadArb.io.in[0].bits.valid[0], _WIRE[0]
wire mshr_read_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate mshr_read_req[0].is_hella
invalidate mshr_read_req[0].data
invalidate mshr_read_req[0].addr
invalidate mshr_read_req[0].uop.debug_tsrc
invalidate mshr_read_req[0].uop.debug_fsrc
invalidate mshr_read_req[0].uop.bp_xcpt_if
invalidate mshr_read_req[0].uop.bp_debug_if
invalidate mshr_read_req[0].uop.xcpt_ma_if
invalidate mshr_read_req[0].uop.xcpt_ae_if
invalidate mshr_read_req[0].uop.xcpt_pf_if
invalidate mshr_read_req[0].uop.fp_single
invalidate mshr_read_req[0].uop.fp_val
invalidate mshr_read_req[0].uop.frs3_en
invalidate mshr_read_req[0].uop.lrs2_rtype
invalidate mshr_read_req[0].uop.lrs1_rtype
invalidate mshr_read_req[0].uop.dst_rtype
invalidate mshr_read_req[0].uop.ldst_val
invalidate mshr_read_req[0].uop.lrs3
invalidate mshr_read_req[0].uop.lrs2
invalidate mshr_read_req[0].uop.lrs1
invalidate mshr_read_req[0].uop.ldst
invalidate mshr_read_req[0].uop.ldst_is_rs1
invalidate mshr_read_req[0].uop.flush_on_commit
invalidate mshr_read_req[0].uop.is_unique
invalidate mshr_read_req[0].uop.is_sys_pc2epc
invalidate mshr_read_req[0].uop.uses_stq
invalidate mshr_read_req[0].uop.uses_ldq
invalidate mshr_read_req[0].uop.is_amo
invalidate mshr_read_req[0].uop.is_fencei
invalidate mshr_read_req[0].uop.is_fence
invalidate mshr_read_req[0].uop.mem_signed
invalidate mshr_read_req[0].uop.mem_size
invalidate mshr_read_req[0].uop.mem_cmd
invalidate mshr_read_req[0].uop.bypassable
invalidate mshr_read_req[0].uop.exc_cause
invalidate mshr_read_req[0].uop.exception
invalidate mshr_read_req[0].uop.stale_pdst
invalidate mshr_read_req[0].uop.ppred_busy
invalidate mshr_read_req[0].uop.prs3_busy
invalidate mshr_read_req[0].uop.prs2_busy
invalidate mshr_read_req[0].uop.prs1_busy
invalidate mshr_read_req[0].uop.ppred
invalidate mshr_read_req[0].uop.prs3
invalidate mshr_read_req[0].uop.prs2
invalidate mshr_read_req[0].uop.prs1
invalidate mshr_read_req[0].uop.pdst
invalidate mshr_read_req[0].uop.rxq_idx
invalidate mshr_read_req[0].uop.stq_idx
invalidate mshr_read_req[0].uop.ldq_idx
invalidate mshr_read_req[0].uop.rob_idx
invalidate mshr_read_req[0].uop.csr_addr
invalidate mshr_read_req[0].uop.imm_packed
invalidate mshr_read_req[0].uop.taken
invalidate mshr_read_req[0].uop.pc_lob
invalidate mshr_read_req[0].uop.edge_inst
invalidate mshr_read_req[0].uop.ftq_idx
invalidate mshr_read_req[0].uop.br_tag
invalidate mshr_read_req[0].uop.br_mask
invalidate mshr_read_req[0].uop.is_sfb
invalidate mshr_read_req[0].uop.is_jal
invalidate mshr_read_req[0].uop.is_jalr
invalidate mshr_read_req[0].uop.is_br
invalidate mshr_read_req[0].uop.iw_p2_poisoned
invalidate mshr_read_req[0].uop.iw_p1_poisoned
invalidate mshr_read_req[0].uop.iw_state
invalidate mshr_read_req[0].uop.ctrl.is_std
invalidate mshr_read_req[0].uop.ctrl.is_sta
invalidate mshr_read_req[0].uop.ctrl.is_load
invalidate mshr_read_req[0].uop.ctrl.csr_cmd
invalidate mshr_read_req[0].uop.ctrl.fcn_dw
invalidate mshr_read_req[0].uop.ctrl.op_fcn
invalidate mshr_read_req[0].uop.ctrl.imm_sel
invalidate mshr_read_req[0].uop.ctrl.op2_sel
invalidate mshr_read_req[0].uop.ctrl.op1_sel
invalidate mshr_read_req[0].uop.ctrl.br_type
invalidate mshr_read_req[0].uop.fu_code
invalidate mshr_read_req[0].uop.iq_type
invalidate mshr_read_req[0].uop.debug_pc
invalidate mshr_read_req[0].uop.is_rvc
invalidate mshr_read_req[0].uop.debug_inst
invalidate mshr_read_req[0].uop.inst
invalidate mshr_read_req[0].uop.uopc
wire mshr_read_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate mshr_read_req_0_uop_uop.debug_tsrc
invalidate mshr_read_req_0_uop_uop.debug_fsrc
invalidate mshr_read_req_0_uop_uop.bp_xcpt_if
invalidate mshr_read_req_0_uop_uop.bp_debug_if
invalidate mshr_read_req_0_uop_uop.xcpt_ma_if
invalidate mshr_read_req_0_uop_uop.xcpt_ae_if
invalidate mshr_read_req_0_uop_uop.xcpt_pf_if
invalidate mshr_read_req_0_uop_uop.fp_single
invalidate mshr_read_req_0_uop_uop.fp_val
invalidate mshr_read_req_0_uop_uop.frs3_en
invalidate mshr_read_req_0_uop_uop.lrs2_rtype
invalidate mshr_read_req_0_uop_uop.lrs1_rtype
invalidate mshr_read_req_0_uop_uop.dst_rtype
invalidate mshr_read_req_0_uop_uop.ldst_val
invalidate mshr_read_req_0_uop_uop.lrs3
invalidate mshr_read_req_0_uop_uop.lrs2
invalidate mshr_read_req_0_uop_uop.lrs1
invalidate mshr_read_req_0_uop_uop.ldst
invalidate mshr_read_req_0_uop_uop.ldst_is_rs1
invalidate mshr_read_req_0_uop_uop.flush_on_commit
invalidate mshr_read_req_0_uop_uop.is_unique
invalidate mshr_read_req_0_uop_uop.is_sys_pc2epc
invalidate mshr_read_req_0_uop_uop.uses_stq
invalidate mshr_read_req_0_uop_uop.uses_ldq
invalidate mshr_read_req_0_uop_uop.is_amo
invalidate mshr_read_req_0_uop_uop.is_fencei
invalidate mshr_read_req_0_uop_uop.is_fence
invalidate mshr_read_req_0_uop_uop.mem_signed
invalidate mshr_read_req_0_uop_uop.mem_size
invalidate mshr_read_req_0_uop_uop.mem_cmd
invalidate mshr_read_req_0_uop_uop.bypassable
invalidate mshr_read_req_0_uop_uop.exc_cause
invalidate mshr_read_req_0_uop_uop.exception
invalidate mshr_read_req_0_uop_uop.stale_pdst
invalidate mshr_read_req_0_uop_uop.ppred_busy
invalidate mshr_read_req_0_uop_uop.prs3_busy
invalidate mshr_read_req_0_uop_uop.prs2_busy
invalidate mshr_read_req_0_uop_uop.prs1_busy
invalidate mshr_read_req_0_uop_uop.ppred
invalidate mshr_read_req_0_uop_uop.prs3
invalidate mshr_read_req_0_uop_uop.prs2
invalidate mshr_read_req_0_uop_uop.prs1
invalidate mshr_read_req_0_uop_uop.pdst
invalidate mshr_read_req_0_uop_uop.rxq_idx
invalidate mshr_read_req_0_uop_uop.stq_idx
invalidate mshr_read_req_0_uop_uop.ldq_idx
invalidate mshr_read_req_0_uop_uop.rob_idx
invalidate mshr_read_req_0_uop_uop.csr_addr
invalidate mshr_read_req_0_uop_uop.imm_packed
invalidate mshr_read_req_0_uop_uop.taken
invalidate mshr_read_req_0_uop_uop.pc_lob
invalidate mshr_read_req_0_uop_uop.edge_inst
invalidate mshr_read_req_0_uop_uop.ftq_idx
invalidate mshr_read_req_0_uop_uop.br_tag
invalidate mshr_read_req_0_uop_uop.br_mask
invalidate mshr_read_req_0_uop_uop.is_sfb
invalidate mshr_read_req_0_uop_uop.is_jal
invalidate mshr_read_req_0_uop_uop.is_jalr
invalidate mshr_read_req_0_uop_uop.is_br
invalidate mshr_read_req_0_uop_uop.iw_p2_poisoned
invalidate mshr_read_req_0_uop_uop.iw_p1_poisoned
invalidate mshr_read_req_0_uop_uop.iw_state
invalidate mshr_read_req_0_uop_uop.ctrl.is_std
invalidate mshr_read_req_0_uop_uop.ctrl.is_sta
invalidate mshr_read_req_0_uop_uop.ctrl.is_load
invalidate mshr_read_req_0_uop_uop.ctrl.csr_cmd
invalidate mshr_read_req_0_uop_uop.ctrl.fcn_dw
invalidate mshr_read_req_0_uop_uop.ctrl.op_fcn
invalidate mshr_read_req_0_uop_uop.ctrl.imm_sel
invalidate mshr_read_req_0_uop_uop.ctrl.op2_sel
invalidate mshr_read_req_0_uop_uop.ctrl.op1_sel
invalidate mshr_read_req_0_uop_uop.ctrl.br_type
invalidate mshr_read_req_0_uop_uop.fu_code
invalidate mshr_read_req_0_uop_uop.iq_type
invalidate mshr_read_req_0_uop_uop.debug_pc
invalidate mshr_read_req_0_uop_uop.is_rvc
invalidate mshr_read_req_0_uop_uop.debug_inst
invalidate mshr_read_req_0_uop_uop.inst
invalidate mshr_read_req_0_uop_uop.uopc
connect mshr_read_req_0_uop_uop.uopc, UInt<7>(0h0)
connect mshr_read_req_0_uop_uop.bypassable, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.fp_val, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.uses_stq, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.uses_ldq, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.pdst, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.dst_rtype, UInt<2>(0h2)
wire mshr_read_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate mshr_read_req_0_uop_cs.is_std
invalidate mshr_read_req_0_uop_cs.is_sta
invalidate mshr_read_req_0_uop_cs.is_load
invalidate mshr_read_req_0_uop_cs.csr_cmd
invalidate mshr_read_req_0_uop_cs.fcn_dw
invalidate mshr_read_req_0_uop_cs.op_fcn
invalidate mshr_read_req_0_uop_cs.imm_sel
invalidate mshr_read_req_0_uop_cs.op2_sel
invalidate mshr_read_req_0_uop_cs.op1_sel
invalidate mshr_read_req_0_uop_cs.br_type
connect mshr_read_req_0_uop_cs.br_type, UInt<4>(0h0)
connect mshr_read_req_0_uop_cs.csr_cmd, UInt<3>(0h0)
connect mshr_read_req_0_uop_cs.is_load, UInt<1>(0h0)
connect mshr_read_req_0_uop_cs.is_sta, UInt<1>(0h0)
connect mshr_read_req_0_uop_cs.is_std, UInt<1>(0h0)
connect mshr_read_req_0_uop_uop.ctrl, mshr_read_req_0_uop_cs
connect mshr_read_req[0].uop, mshr_read_req_0_uop_uop
node _mshr_read_req_0_addr_T = cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx)
node _mshr_read_req_0_addr_T_1 = shl(_mshr_read_req_0_addr_T, 6)
connect mshr_read_req[0].addr, _mshr_read_req_0_addr_T_1
invalidate mshr_read_req[0].data
connect mshr_read_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[3].valid, mshrs.io.meta_read.valid
connect metaReadArb.io.in[3].bits.req[0].tag, mshrs.io.meta_read.bits.tag
connect metaReadArb.io.in[3].bits.req[0].way_en, mshrs.io.meta_read.bits.way_en
connect metaReadArb.io.in[3].bits.req[0].idx, mshrs.io.meta_read.bits.idx
connect mshrs.io.meta_read.ready, metaReadArb.io.in[3].ready
node _wb_fire_T = and(wb.io.meta_read.ready, wb.io.meta_read.valid)
node _wb_fire_T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid)
node wb_fire = and(_wb_fire_T, _wb_fire_T_1)
wire wb_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate wb_req[0].is_hella
invalidate wb_req[0].data
invalidate wb_req[0].addr
invalidate wb_req[0].uop.debug_tsrc
invalidate wb_req[0].uop.debug_fsrc
invalidate wb_req[0].uop.bp_xcpt_if
invalidate wb_req[0].uop.bp_debug_if
invalidate wb_req[0].uop.xcpt_ma_if
invalidate wb_req[0].uop.xcpt_ae_if
invalidate wb_req[0].uop.xcpt_pf_if
invalidate wb_req[0].uop.fp_single
invalidate wb_req[0].uop.fp_val
invalidate wb_req[0].uop.frs3_en
invalidate wb_req[0].uop.lrs2_rtype
invalidate wb_req[0].uop.lrs1_rtype
invalidate wb_req[0].uop.dst_rtype
invalidate wb_req[0].uop.ldst_val
invalidate wb_req[0].uop.lrs3
invalidate wb_req[0].uop.lrs2
invalidate wb_req[0].uop.lrs1
invalidate wb_req[0].uop.ldst
invalidate wb_req[0].uop.ldst_is_rs1
invalidate wb_req[0].uop.flush_on_commit
invalidate wb_req[0].uop.is_unique
invalidate wb_req[0].uop.is_sys_pc2epc
invalidate wb_req[0].uop.uses_stq
invalidate wb_req[0].uop.uses_ldq
invalidate wb_req[0].uop.is_amo
invalidate wb_req[0].uop.is_fencei
invalidate wb_req[0].uop.is_fence
invalidate wb_req[0].uop.mem_signed
invalidate wb_req[0].uop.mem_size
invalidate wb_req[0].uop.mem_cmd
invalidate wb_req[0].uop.bypassable
invalidate wb_req[0].uop.exc_cause
invalidate wb_req[0].uop.exception
invalidate wb_req[0].uop.stale_pdst
invalidate wb_req[0].uop.ppred_busy
invalidate wb_req[0].uop.prs3_busy
invalidate wb_req[0].uop.prs2_busy
invalidate wb_req[0].uop.prs1_busy
invalidate wb_req[0].uop.ppred
invalidate wb_req[0].uop.prs3
invalidate wb_req[0].uop.prs2
invalidate wb_req[0].uop.prs1
invalidate wb_req[0].uop.pdst
invalidate wb_req[0].uop.rxq_idx
invalidate wb_req[0].uop.stq_idx
invalidate wb_req[0].uop.ldq_idx
invalidate wb_req[0].uop.rob_idx
invalidate wb_req[0].uop.csr_addr
invalidate wb_req[0].uop.imm_packed
invalidate wb_req[0].uop.taken
invalidate wb_req[0].uop.pc_lob
invalidate wb_req[0].uop.edge_inst
invalidate wb_req[0].uop.ftq_idx
invalidate wb_req[0].uop.br_tag
invalidate wb_req[0].uop.br_mask
invalidate wb_req[0].uop.is_sfb
invalidate wb_req[0].uop.is_jal
invalidate wb_req[0].uop.is_jalr
invalidate wb_req[0].uop.is_br
invalidate wb_req[0].uop.iw_p2_poisoned
invalidate wb_req[0].uop.iw_p1_poisoned
invalidate wb_req[0].uop.iw_state
invalidate wb_req[0].uop.ctrl.is_std
invalidate wb_req[0].uop.ctrl.is_sta
invalidate wb_req[0].uop.ctrl.is_load
invalidate wb_req[0].uop.ctrl.csr_cmd
invalidate wb_req[0].uop.ctrl.fcn_dw
invalidate wb_req[0].uop.ctrl.op_fcn
invalidate wb_req[0].uop.ctrl.imm_sel
invalidate wb_req[0].uop.ctrl.op2_sel
invalidate wb_req[0].uop.ctrl.op1_sel
invalidate wb_req[0].uop.ctrl.br_type
invalidate wb_req[0].uop.fu_code
invalidate wb_req[0].uop.iq_type
invalidate wb_req[0].uop.debug_pc
invalidate wb_req[0].uop.is_rvc
invalidate wb_req[0].uop.debug_inst
invalidate wb_req[0].uop.inst
invalidate wb_req[0].uop.uopc
wire wb_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate wb_req_0_uop_uop.debug_tsrc
invalidate wb_req_0_uop_uop.debug_fsrc
invalidate wb_req_0_uop_uop.bp_xcpt_if
invalidate wb_req_0_uop_uop.bp_debug_if
invalidate wb_req_0_uop_uop.xcpt_ma_if
invalidate wb_req_0_uop_uop.xcpt_ae_if
invalidate wb_req_0_uop_uop.xcpt_pf_if
invalidate wb_req_0_uop_uop.fp_single
invalidate wb_req_0_uop_uop.fp_val
invalidate wb_req_0_uop_uop.frs3_en
invalidate wb_req_0_uop_uop.lrs2_rtype
invalidate wb_req_0_uop_uop.lrs1_rtype
invalidate wb_req_0_uop_uop.dst_rtype
invalidate wb_req_0_uop_uop.ldst_val
invalidate wb_req_0_uop_uop.lrs3
invalidate wb_req_0_uop_uop.lrs2
invalidate wb_req_0_uop_uop.lrs1
invalidate wb_req_0_uop_uop.ldst
invalidate wb_req_0_uop_uop.ldst_is_rs1
invalidate wb_req_0_uop_uop.flush_on_commit
invalidate wb_req_0_uop_uop.is_unique
invalidate wb_req_0_uop_uop.is_sys_pc2epc
invalidate wb_req_0_uop_uop.uses_stq
invalidate wb_req_0_uop_uop.uses_ldq
invalidate wb_req_0_uop_uop.is_amo
invalidate wb_req_0_uop_uop.is_fencei
invalidate wb_req_0_uop_uop.is_fence
invalidate wb_req_0_uop_uop.mem_signed
invalidate wb_req_0_uop_uop.mem_size
invalidate wb_req_0_uop_uop.mem_cmd
invalidate wb_req_0_uop_uop.bypassable
invalidate wb_req_0_uop_uop.exc_cause
invalidate wb_req_0_uop_uop.exception
invalidate wb_req_0_uop_uop.stale_pdst
invalidate wb_req_0_uop_uop.ppred_busy
invalidate wb_req_0_uop_uop.prs3_busy
invalidate wb_req_0_uop_uop.prs2_busy
invalidate wb_req_0_uop_uop.prs1_busy
invalidate wb_req_0_uop_uop.ppred
invalidate wb_req_0_uop_uop.prs3
invalidate wb_req_0_uop_uop.prs2
invalidate wb_req_0_uop_uop.prs1
invalidate wb_req_0_uop_uop.pdst
invalidate wb_req_0_uop_uop.rxq_idx
invalidate wb_req_0_uop_uop.stq_idx
invalidate wb_req_0_uop_uop.ldq_idx
invalidate wb_req_0_uop_uop.rob_idx
invalidate wb_req_0_uop_uop.csr_addr
invalidate wb_req_0_uop_uop.imm_packed
invalidate wb_req_0_uop_uop.taken
invalidate wb_req_0_uop_uop.pc_lob
invalidate wb_req_0_uop_uop.edge_inst
invalidate wb_req_0_uop_uop.ftq_idx
invalidate wb_req_0_uop_uop.br_tag
invalidate wb_req_0_uop_uop.br_mask
invalidate wb_req_0_uop_uop.is_sfb
invalidate wb_req_0_uop_uop.is_jal
invalidate wb_req_0_uop_uop.is_jalr
invalidate wb_req_0_uop_uop.is_br
invalidate wb_req_0_uop_uop.iw_p2_poisoned
invalidate wb_req_0_uop_uop.iw_p1_poisoned
invalidate wb_req_0_uop_uop.iw_state
invalidate wb_req_0_uop_uop.ctrl.is_std
invalidate wb_req_0_uop_uop.ctrl.is_sta
invalidate wb_req_0_uop_uop.ctrl.is_load
invalidate wb_req_0_uop_uop.ctrl.csr_cmd
invalidate wb_req_0_uop_uop.ctrl.fcn_dw
invalidate wb_req_0_uop_uop.ctrl.op_fcn
invalidate wb_req_0_uop_uop.ctrl.imm_sel
invalidate wb_req_0_uop_uop.ctrl.op2_sel
invalidate wb_req_0_uop_uop.ctrl.op1_sel
invalidate wb_req_0_uop_uop.ctrl.br_type
invalidate wb_req_0_uop_uop.fu_code
invalidate wb_req_0_uop_uop.iq_type
invalidate wb_req_0_uop_uop.debug_pc
invalidate wb_req_0_uop_uop.is_rvc
invalidate wb_req_0_uop_uop.debug_inst
invalidate wb_req_0_uop_uop.inst
invalidate wb_req_0_uop_uop.uopc
connect wb_req_0_uop_uop.uopc, UInt<7>(0h0)
connect wb_req_0_uop_uop.bypassable, UInt<1>(0h0)
connect wb_req_0_uop_uop.fp_val, UInt<1>(0h0)
connect wb_req_0_uop_uop.uses_stq, UInt<1>(0h0)
connect wb_req_0_uop_uop.uses_ldq, UInt<1>(0h0)
connect wb_req_0_uop_uop.pdst, UInt<1>(0h0)
connect wb_req_0_uop_uop.dst_rtype, UInt<2>(0h2)
wire wb_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate wb_req_0_uop_cs.is_std
invalidate wb_req_0_uop_cs.is_sta
invalidate wb_req_0_uop_cs.is_load
invalidate wb_req_0_uop_cs.csr_cmd
invalidate wb_req_0_uop_cs.fcn_dw
invalidate wb_req_0_uop_cs.op_fcn
invalidate wb_req_0_uop_cs.imm_sel
invalidate wb_req_0_uop_cs.op2_sel
invalidate wb_req_0_uop_cs.op1_sel
invalidate wb_req_0_uop_cs.br_type
connect wb_req_0_uop_cs.br_type, UInt<4>(0h0)
connect wb_req_0_uop_cs.csr_cmd, UInt<3>(0h0)
connect wb_req_0_uop_cs.is_load, UInt<1>(0h0)
connect wb_req_0_uop_cs.is_sta, UInt<1>(0h0)
connect wb_req_0_uop_cs.is_std, UInt<1>(0h0)
connect wb_req_0_uop_uop.ctrl, wb_req_0_uop_cs
connect wb_req[0].uop, wb_req_0_uop_uop
node _wb_req_0_addr_T = cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)
connect wb_req[0].addr, _wb_req_0_addr_T
invalidate wb_req[0].data
connect wb_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[2].valid, wb.io.meta_read.valid
connect metaReadArb.io.in[2].bits.req[0].tag, wb.io.meta_read.bits.tag
connect metaReadArb.io.in[2].bits.req[0].way_en, wb.io.meta_read.bits.way_en
connect metaReadArb.io.in[2].bits.req[0].idx, wb.io.meta_read.bits.idx
node _wb_io_meta_read_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready)
connect wb.io.meta_read.ready, _wb_io_meta_read_ready_T
connect dataReadArb.io.in[1].valid, wb.io.data_req.valid
connect dataReadArb.io.in[1].bits.req[0].addr, wb.io.data_req.bits.addr
connect dataReadArb.io.in[1].bits.req[0].way_en, wb.io.data_req.bits.way_en
wire _WIRE_1 : UInt<1>[1]
connect _WIRE_1[0], UInt<1>(0h1)
connect dataReadArb.io.in[1].bits.valid[0], _WIRE_1[0]
node _wb_io_data_req_ready_T = and(metaReadArb.io.in[2].ready, dataReadArb.io.in[1].ready)
connect wb.io.data_req.ready, _wb_io_data_req_ready_T
node _T = and(wb.io.meta_read.ready, wb.io.meta_read.valid)
node _T_1 = and(wb.io.data_req.ready, wb.io.data_req.valid)
node _T_2 = xor(_T, _T_1)
node _T_3 = eq(_T_2, UInt<1>(0h0))
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:548 assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node prober_fire = and(prober.io.meta_read.ready, prober.io.meta_read.valid)
wire prober_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate prober_req[0].is_hella
invalidate prober_req[0].data
invalidate prober_req[0].addr
invalidate prober_req[0].uop.debug_tsrc
invalidate prober_req[0].uop.debug_fsrc
invalidate prober_req[0].uop.bp_xcpt_if
invalidate prober_req[0].uop.bp_debug_if
invalidate prober_req[0].uop.xcpt_ma_if
invalidate prober_req[0].uop.xcpt_ae_if
invalidate prober_req[0].uop.xcpt_pf_if
invalidate prober_req[0].uop.fp_single
invalidate prober_req[0].uop.fp_val
invalidate prober_req[0].uop.frs3_en
invalidate prober_req[0].uop.lrs2_rtype
invalidate prober_req[0].uop.lrs1_rtype
invalidate prober_req[0].uop.dst_rtype
invalidate prober_req[0].uop.ldst_val
invalidate prober_req[0].uop.lrs3
invalidate prober_req[0].uop.lrs2
invalidate prober_req[0].uop.lrs1
invalidate prober_req[0].uop.ldst
invalidate prober_req[0].uop.ldst_is_rs1
invalidate prober_req[0].uop.flush_on_commit
invalidate prober_req[0].uop.is_unique
invalidate prober_req[0].uop.is_sys_pc2epc
invalidate prober_req[0].uop.uses_stq
invalidate prober_req[0].uop.uses_ldq
invalidate prober_req[0].uop.is_amo
invalidate prober_req[0].uop.is_fencei
invalidate prober_req[0].uop.is_fence
invalidate prober_req[0].uop.mem_signed
invalidate prober_req[0].uop.mem_size
invalidate prober_req[0].uop.mem_cmd
invalidate prober_req[0].uop.bypassable
invalidate prober_req[0].uop.exc_cause
invalidate prober_req[0].uop.exception
invalidate prober_req[0].uop.stale_pdst
invalidate prober_req[0].uop.ppred_busy
invalidate prober_req[0].uop.prs3_busy
invalidate prober_req[0].uop.prs2_busy
invalidate prober_req[0].uop.prs1_busy
invalidate prober_req[0].uop.ppred
invalidate prober_req[0].uop.prs3
invalidate prober_req[0].uop.prs2
invalidate prober_req[0].uop.prs1
invalidate prober_req[0].uop.pdst
invalidate prober_req[0].uop.rxq_idx
invalidate prober_req[0].uop.stq_idx
invalidate prober_req[0].uop.ldq_idx
invalidate prober_req[0].uop.rob_idx
invalidate prober_req[0].uop.csr_addr
invalidate prober_req[0].uop.imm_packed
invalidate prober_req[0].uop.taken
invalidate prober_req[0].uop.pc_lob
invalidate prober_req[0].uop.edge_inst
invalidate prober_req[0].uop.ftq_idx
invalidate prober_req[0].uop.br_tag
invalidate prober_req[0].uop.br_mask
invalidate prober_req[0].uop.is_sfb
invalidate prober_req[0].uop.is_jal
invalidate prober_req[0].uop.is_jalr
invalidate prober_req[0].uop.is_br
invalidate prober_req[0].uop.iw_p2_poisoned
invalidate prober_req[0].uop.iw_p1_poisoned
invalidate prober_req[0].uop.iw_state
invalidate prober_req[0].uop.ctrl.is_std
invalidate prober_req[0].uop.ctrl.is_sta
invalidate prober_req[0].uop.ctrl.is_load
invalidate prober_req[0].uop.ctrl.csr_cmd
invalidate prober_req[0].uop.ctrl.fcn_dw
invalidate prober_req[0].uop.ctrl.op_fcn
invalidate prober_req[0].uop.ctrl.imm_sel
invalidate prober_req[0].uop.ctrl.op2_sel
invalidate prober_req[0].uop.ctrl.op1_sel
invalidate prober_req[0].uop.ctrl.br_type
invalidate prober_req[0].uop.fu_code
invalidate prober_req[0].uop.iq_type
invalidate prober_req[0].uop.debug_pc
invalidate prober_req[0].uop.is_rvc
invalidate prober_req[0].uop.debug_inst
invalidate prober_req[0].uop.inst
invalidate prober_req[0].uop.uopc
wire prober_req_0_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate prober_req_0_uop_uop.debug_tsrc
invalidate prober_req_0_uop_uop.debug_fsrc
invalidate prober_req_0_uop_uop.bp_xcpt_if
invalidate prober_req_0_uop_uop.bp_debug_if
invalidate prober_req_0_uop_uop.xcpt_ma_if
invalidate prober_req_0_uop_uop.xcpt_ae_if
invalidate prober_req_0_uop_uop.xcpt_pf_if
invalidate prober_req_0_uop_uop.fp_single
invalidate prober_req_0_uop_uop.fp_val
invalidate prober_req_0_uop_uop.frs3_en
invalidate prober_req_0_uop_uop.lrs2_rtype
invalidate prober_req_0_uop_uop.lrs1_rtype
invalidate prober_req_0_uop_uop.dst_rtype
invalidate prober_req_0_uop_uop.ldst_val
invalidate prober_req_0_uop_uop.lrs3
invalidate prober_req_0_uop_uop.lrs2
invalidate prober_req_0_uop_uop.lrs1
invalidate prober_req_0_uop_uop.ldst
invalidate prober_req_0_uop_uop.ldst_is_rs1
invalidate prober_req_0_uop_uop.flush_on_commit
invalidate prober_req_0_uop_uop.is_unique
invalidate prober_req_0_uop_uop.is_sys_pc2epc
invalidate prober_req_0_uop_uop.uses_stq
invalidate prober_req_0_uop_uop.uses_ldq
invalidate prober_req_0_uop_uop.is_amo
invalidate prober_req_0_uop_uop.is_fencei
invalidate prober_req_0_uop_uop.is_fence
invalidate prober_req_0_uop_uop.mem_signed
invalidate prober_req_0_uop_uop.mem_size
invalidate prober_req_0_uop_uop.mem_cmd
invalidate prober_req_0_uop_uop.bypassable
invalidate prober_req_0_uop_uop.exc_cause
invalidate prober_req_0_uop_uop.exception
invalidate prober_req_0_uop_uop.stale_pdst
invalidate prober_req_0_uop_uop.ppred_busy
invalidate prober_req_0_uop_uop.prs3_busy
invalidate prober_req_0_uop_uop.prs2_busy
invalidate prober_req_0_uop_uop.prs1_busy
invalidate prober_req_0_uop_uop.ppred
invalidate prober_req_0_uop_uop.prs3
invalidate prober_req_0_uop_uop.prs2
invalidate prober_req_0_uop_uop.prs1
invalidate prober_req_0_uop_uop.pdst
invalidate prober_req_0_uop_uop.rxq_idx
invalidate prober_req_0_uop_uop.stq_idx
invalidate prober_req_0_uop_uop.ldq_idx
invalidate prober_req_0_uop_uop.rob_idx
invalidate prober_req_0_uop_uop.csr_addr
invalidate prober_req_0_uop_uop.imm_packed
invalidate prober_req_0_uop_uop.taken
invalidate prober_req_0_uop_uop.pc_lob
invalidate prober_req_0_uop_uop.edge_inst
invalidate prober_req_0_uop_uop.ftq_idx
invalidate prober_req_0_uop_uop.br_tag
invalidate prober_req_0_uop_uop.br_mask
invalidate prober_req_0_uop_uop.is_sfb
invalidate prober_req_0_uop_uop.is_jal
invalidate prober_req_0_uop_uop.is_jalr
invalidate prober_req_0_uop_uop.is_br
invalidate prober_req_0_uop_uop.iw_p2_poisoned
invalidate prober_req_0_uop_uop.iw_p1_poisoned
invalidate prober_req_0_uop_uop.iw_state
invalidate prober_req_0_uop_uop.ctrl.is_std
invalidate prober_req_0_uop_uop.ctrl.is_sta
invalidate prober_req_0_uop_uop.ctrl.is_load
invalidate prober_req_0_uop_uop.ctrl.csr_cmd
invalidate prober_req_0_uop_uop.ctrl.fcn_dw
invalidate prober_req_0_uop_uop.ctrl.op_fcn
invalidate prober_req_0_uop_uop.ctrl.imm_sel
invalidate prober_req_0_uop_uop.ctrl.op2_sel
invalidate prober_req_0_uop_uop.ctrl.op1_sel
invalidate prober_req_0_uop_uop.ctrl.br_type
invalidate prober_req_0_uop_uop.fu_code
invalidate prober_req_0_uop_uop.iq_type
invalidate prober_req_0_uop_uop.debug_pc
invalidate prober_req_0_uop_uop.is_rvc
invalidate prober_req_0_uop_uop.debug_inst
invalidate prober_req_0_uop_uop.inst
invalidate prober_req_0_uop_uop.uopc
connect prober_req_0_uop_uop.uopc, UInt<7>(0h0)
connect prober_req_0_uop_uop.bypassable, UInt<1>(0h0)
connect prober_req_0_uop_uop.fp_val, UInt<1>(0h0)
connect prober_req_0_uop_uop.uses_stq, UInt<1>(0h0)
connect prober_req_0_uop_uop.uses_ldq, UInt<1>(0h0)
connect prober_req_0_uop_uop.pdst, UInt<1>(0h0)
connect prober_req_0_uop_uop.dst_rtype, UInt<2>(0h2)
wire prober_req_0_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate prober_req_0_uop_cs.is_std
invalidate prober_req_0_uop_cs.is_sta
invalidate prober_req_0_uop_cs.is_load
invalidate prober_req_0_uop_cs.csr_cmd
invalidate prober_req_0_uop_cs.fcn_dw
invalidate prober_req_0_uop_cs.op_fcn
invalidate prober_req_0_uop_cs.imm_sel
invalidate prober_req_0_uop_cs.op2_sel
invalidate prober_req_0_uop_cs.op1_sel
invalidate prober_req_0_uop_cs.br_type
connect prober_req_0_uop_cs.br_type, UInt<4>(0h0)
connect prober_req_0_uop_cs.csr_cmd, UInt<3>(0h0)
connect prober_req_0_uop_cs.is_load, UInt<1>(0h0)
connect prober_req_0_uop_cs.is_sta, UInt<1>(0h0)
connect prober_req_0_uop_cs.is_std, UInt<1>(0h0)
connect prober_req_0_uop_uop.ctrl, prober_req_0_uop_cs
connect prober_req[0].uop, prober_req_0_uop_uop
node _prober_req_0_addr_T = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx)
node _prober_req_0_addr_T_1 = shl(_prober_req_0_addr_T, 6)
connect prober_req[0].addr, _prober_req_0_addr_T_1
invalidate prober_req[0].data
connect prober_req[0].is_hella, UInt<1>(0h0)
connect metaReadArb.io.in[1].valid, prober.io.meta_read.valid
connect metaReadArb.io.in[1].bits.req[0].tag, prober.io.meta_read.bits.tag
connect metaReadArb.io.in[1].bits.req[0].way_en, prober.io.meta_read.bits.way_en
connect metaReadArb.io.in[1].bits.req[0].idx, prober.io.meta_read.bits.idx
connect prober.io.meta_read.ready, metaReadArb.io.in[1].ready
node prefetch_fire = and(mshrs.io.prefetch.ready, mshrs.io.prefetch.valid)
wire prefetch_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1]
invalidate prefetch_req[0].is_hella
invalidate prefetch_req[0].data
invalidate prefetch_req[0].addr
invalidate prefetch_req[0].uop.debug_tsrc
invalidate prefetch_req[0].uop.debug_fsrc
invalidate prefetch_req[0].uop.bp_xcpt_if
invalidate prefetch_req[0].uop.bp_debug_if
invalidate prefetch_req[0].uop.xcpt_ma_if
invalidate prefetch_req[0].uop.xcpt_ae_if
invalidate prefetch_req[0].uop.xcpt_pf_if
invalidate prefetch_req[0].uop.fp_single
invalidate prefetch_req[0].uop.fp_val
invalidate prefetch_req[0].uop.frs3_en
invalidate prefetch_req[0].uop.lrs2_rtype
invalidate prefetch_req[0].uop.lrs1_rtype
invalidate prefetch_req[0].uop.dst_rtype
invalidate prefetch_req[0].uop.ldst_val
invalidate prefetch_req[0].uop.lrs3
invalidate prefetch_req[0].uop.lrs2
invalidate prefetch_req[0].uop.lrs1
invalidate prefetch_req[0].uop.ldst
invalidate prefetch_req[0].uop.ldst_is_rs1
invalidate prefetch_req[0].uop.flush_on_commit
invalidate prefetch_req[0].uop.is_unique
invalidate prefetch_req[0].uop.is_sys_pc2epc
invalidate prefetch_req[0].uop.uses_stq
invalidate prefetch_req[0].uop.uses_ldq
invalidate prefetch_req[0].uop.is_amo
invalidate prefetch_req[0].uop.is_fencei
invalidate prefetch_req[0].uop.is_fence
invalidate prefetch_req[0].uop.mem_signed
invalidate prefetch_req[0].uop.mem_size
invalidate prefetch_req[0].uop.mem_cmd
invalidate prefetch_req[0].uop.bypassable
invalidate prefetch_req[0].uop.exc_cause
invalidate prefetch_req[0].uop.exception
invalidate prefetch_req[0].uop.stale_pdst
invalidate prefetch_req[0].uop.ppred_busy
invalidate prefetch_req[0].uop.prs3_busy
invalidate prefetch_req[0].uop.prs2_busy
invalidate prefetch_req[0].uop.prs1_busy
invalidate prefetch_req[0].uop.ppred
invalidate prefetch_req[0].uop.prs3
invalidate prefetch_req[0].uop.prs2
invalidate prefetch_req[0].uop.prs1
invalidate prefetch_req[0].uop.pdst
invalidate prefetch_req[0].uop.rxq_idx
invalidate prefetch_req[0].uop.stq_idx
invalidate prefetch_req[0].uop.ldq_idx
invalidate prefetch_req[0].uop.rob_idx
invalidate prefetch_req[0].uop.csr_addr
invalidate prefetch_req[0].uop.imm_packed
invalidate prefetch_req[0].uop.taken
invalidate prefetch_req[0].uop.pc_lob
invalidate prefetch_req[0].uop.edge_inst
invalidate prefetch_req[0].uop.ftq_idx
invalidate prefetch_req[0].uop.br_tag
invalidate prefetch_req[0].uop.br_mask
invalidate prefetch_req[0].uop.is_sfb
invalidate prefetch_req[0].uop.is_jal
invalidate prefetch_req[0].uop.is_jalr
invalidate prefetch_req[0].uop.is_br
invalidate prefetch_req[0].uop.iw_p2_poisoned
invalidate prefetch_req[0].uop.iw_p1_poisoned
invalidate prefetch_req[0].uop.iw_state
invalidate prefetch_req[0].uop.ctrl.is_std
invalidate prefetch_req[0].uop.ctrl.is_sta
invalidate prefetch_req[0].uop.ctrl.is_load
invalidate prefetch_req[0].uop.ctrl.csr_cmd
invalidate prefetch_req[0].uop.ctrl.fcn_dw
invalidate prefetch_req[0].uop.ctrl.op_fcn
invalidate prefetch_req[0].uop.ctrl.imm_sel
invalidate prefetch_req[0].uop.ctrl.op2_sel
invalidate prefetch_req[0].uop.ctrl.op1_sel
invalidate prefetch_req[0].uop.ctrl.br_type
invalidate prefetch_req[0].uop.fu_code
invalidate prefetch_req[0].uop.iq_type
invalidate prefetch_req[0].uop.debug_pc
invalidate prefetch_req[0].uop.is_rvc
invalidate prefetch_req[0].uop.debug_inst
invalidate prefetch_req[0].uop.inst
invalidate prefetch_req[0].uop.uopc
connect prefetch_req[0], mshrs.io.prefetch.bits
connect metaReadArb.io.in[5].valid, mshrs.io.prefetch.valid
node _metaReadArb_io_in_5_bits_req_0_idx_T = shr(mshrs.io.prefetch.bits.addr, 6)
connect metaReadArb.io.in[5].bits.req[0].idx, _metaReadArb_io_in_5_bits_req_0_idx_T
invalidate metaReadArb.io.in[5].bits.req[0].way_en
invalidate metaReadArb.io.in[5].bits.req[0].tag
connect mshrs.io.prefetch.ready, metaReadArb.io.in[5].ready
node _s0_valid_T = and(io.lsu.req.ready, io.lsu.req.valid)
wire _s0_valid_WIRE : UInt<1>[1]
connect _s0_valid_WIRE[0], io.lsu.req.bits[0].valid
node _s0_valid_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid)
node _s0_valid_T_2 = or(_s0_valid_T_1, wb_fire)
node _s0_valid_T_3 = or(_s0_valid_T_2, prober_fire)
node _s0_valid_T_4 = or(_s0_valid_T_3, prefetch_fire)
node _s0_valid_T_5 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_valid_T_6 = or(_s0_valid_T_4, _s0_valid_T_5)
wire _s0_valid_WIRE_1 : UInt<1>[1]
connect _s0_valid_WIRE_1[0], UInt<1>(0h1)
wire _s0_valid_WIRE_2 : UInt<1>[1]
connect _s0_valid_WIRE_2[0], UInt<1>(0h0)
node _s0_valid_T_7 = mux(_s0_valid_T_6, _s0_valid_WIRE_1, _s0_valid_WIRE_2)
node s0_valid = mux(_s0_valid_T, _s0_valid_WIRE, _s0_valid_T_7)
node _s0_req_T = and(io.lsu.req.ready, io.lsu.req.valid)
wire _s0_req_WIRE : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1]
connect _s0_req_WIRE[0], io.lsu.req.bits[0].bits
node _s0_req_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_req_T_2 = mux(_s0_req_T_1, mshr_read_req, replay_req)
node _s0_req_T_3 = mux(prefetch_fire, prefetch_req, _s0_req_T_2)
node _s0_req_T_4 = mux(prober_fire, prober_req, _s0_req_T_3)
node _s0_req_T_5 = mux(wb_fire, wb_req, _s0_req_T_4)
node s0_req = mux(_s0_req_T, _s0_req_WIRE, _s0_req_T_5)
node _s0_type_T = and(io.lsu.req.ready, io.lsu.req.valid)
node _s0_type_T_1 = and(mshrs.io.meta_read.ready, mshrs.io.meta_read.valid)
node _s0_type_T_2 = mux(_s0_type_T_1, UInt<3>(0h3), UInt<3>(0h0))
node _s0_type_T_3 = mux(prefetch_fire, UInt<3>(0h5), _s0_type_T_2)
node _s0_type_T_4 = mux(prober_fire, UInt<3>(0h1), _s0_type_T_3)
node _s0_type_T_5 = mux(wb_fire, UInt<3>(0h2), _s0_type_T_4)
node s0_type = mux(_s0_type_T, UInt<3>(0h4), _s0_type_T_5)
node _s0_send_resp_or_nack_T = and(io.lsu.req.ready, io.lsu.req.valid)
node _s0_send_resp_or_nack_T_1 = and(mshrs.io.replay.ready, mshrs.io.replay.valid)
node _s0_send_resp_or_nack_T_2 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<1>(0h0))
node _s0_send_resp_or_nack_T_3 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<5>(0h10))
node _s0_send_resp_or_nack_T_4 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h6))
node _s0_send_resp_or_nack_T_5 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h7))
node _s0_send_resp_or_nack_T_6 = or(_s0_send_resp_or_nack_T_2, _s0_send_resp_or_nack_T_3)
node _s0_send_resp_or_nack_T_7 = or(_s0_send_resp_or_nack_T_6, _s0_send_resp_or_nack_T_4)
node _s0_send_resp_or_nack_T_8 = or(_s0_send_resp_or_nack_T_7, _s0_send_resp_or_nack_T_5)
node _s0_send_resp_or_nack_T_9 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<3>(0h4))
node _s0_send_resp_or_nack_T_10 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h9))
node _s0_send_resp_or_nack_T_11 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0ha))
node _s0_send_resp_or_nack_T_12 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hb))
node _s0_send_resp_or_nack_T_13 = or(_s0_send_resp_or_nack_T_9, _s0_send_resp_or_nack_T_10)
node _s0_send_resp_or_nack_T_14 = or(_s0_send_resp_or_nack_T_13, _s0_send_resp_or_nack_T_11)
node _s0_send_resp_or_nack_T_15 = or(_s0_send_resp_or_nack_T_14, _s0_send_resp_or_nack_T_12)
node _s0_send_resp_or_nack_T_16 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0h8))
node _s0_send_resp_or_nack_T_17 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hc))
node _s0_send_resp_or_nack_T_18 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hd))
node _s0_send_resp_or_nack_T_19 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0he))
node _s0_send_resp_or_nack_T_20 = eq(mshrs.io.replay.bits.uop.mem_cmd, UInt<4>(0hf))
node _s0_send_resp_or_nack_T_21 = or(_s0_send_resp_or_nack_T_16, _s0_send_resp_or_nack_T_17)
node _s0_send_resp_or_nack_T_22 = or(_s0_send_resp_or_nack_T_21, _s0_send_resp_or_nack_T_18)
node _s0_send_resp_or_nack_T_23 = or(_s0_send_resp_or_nack_T_22, _s0_send_resp_or_nack_T_19)
node _s0_send_resp_or_nack_T_24 = or(_s0_send_resp_or_nack_T_23, _s0_send_resp_or_nack_T_20)
node _s0_send_resp_or_nack_T_25 = or(_s0_send_resp_or_nack_T_15, _s0_send_resp_or_nack_T_24)
node _s0_send_resp_or_nack_T_26 = or(_s0_send_resp_or_nack_T_8, _s0_send_resp_or_nack_T_25)
node _s0_send_resp_or_nack_T_27 = and(_s0_send_resp_or_nack_T_1, _s0_send_resp_or_nack_T_26)
node _s0_send_resp_or_nack_T_28 = mux(_s0_send_resp_or_nack_T_27, UInt<1>(0h1), UInt<1>(0h0))
node _s0_send_resp_or_nack_T_29 = bits(_s0_send_resp_or_nack_T_28, 0, 0)
wire _s0_send_resp_or_nack_WIRE : UInt<1>[1]
connect _s0_send_resp_or_nack_WIRE[0], _s0_send_resp_or_nack_T_29
node s0_send_resp_or_nack = mux(_s0_send_resp_or_nack_T, s0_valid, _s0_send_resp_or_nack_WIRE)
reg s1_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1], clock
connect s1_req, s0_req
node _s1_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _s1_req_0_uop_br_mask_T_1 = and(s0_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T)
connect s1_req[0].uop.br_mask, _s1_req_0_uop_br_mask_T_1
wire s2_store_failed : UInt<1>
node _s1_valid_T = and(io.lsu.brupdate.b1.mispredict_mask, s0_req[0].uop.br_mask)
node _s1_valid_T_1 = neq(_s1_valid_T, UInt<1>(0h0))
node _s1_valid_T_2 = eq(_s1_valid_T_1, UInt<1>(0h0))
node _s1_valid_T_3 = and(s0_valid[0], _s1_valid_T_2)
node _s1_valid_T_4 = and(io.lsu.exception, s0_req[0].uop.uses_ldq)
node _s1_valid_T_5 = eq(_s1_valid_T_4, UInt<1>(0h0))
node _s1_valid_T_6 = and(_s1_valid_T_3, _s1_valid_T_5)
node _s1_valid_T_7 = and(io.lsu.req.ready, io.lsu.req.valid)
node _s1_valid_T_8 = and(s2_store_failed, _s1_valid_T_7)
node _s1_valid_T_9 = and(_s1_valid_T_8, s0_req[0].uop.uses_stq)
node _s1_valid_T_10 = eq(_s1_valid_T_9, UInt<1>(0h0))
node _s1_valid_T_11 = and(_s1_valid_T_6, _s1_valid_T_10)
regreset s1_valid_REG : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_valid_REG, _s1_valid_T_11
wire s1_valid : UInt<1>[1]
connect s1_valid[0], s1_valid_REG
node _T_7 = and(io.lsu.req.ready, io.lsu.req.valid)
reg REG : UInt<1>, clock
connect REG, _T_7
node _T_8 = eq(REG, UInt<1>(0h0))
node _T_9 = and(io.lsu.s1_kill[0], _T_8)
reg REG_1 : UInt<1>, clock
connect REG_1, io.lsu.req.bits[0].valid
node _T_10 = eq(REG_1, UInt<1>(0h0))
node _T_11 = and(_T_9, _T_10)
node _T_12 = eq(_T_11, UInt<1>(0h0))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:611 assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))\n") : printf_1
assert(clock, _T_12, UInt<1>(0h1), "") : assert_1
node _s1_nack_T = bits(s1_req[0].addr, 9, 6)
node _s1_nack_T_1 = eq(_s1_nack_T, prober.io.meta_write.bits.idx)
node _s1_nack_T_2 = eq(prober.io.req.ready, UInt<1>(0h0))
node s1_nack_0 = and(_s1_nack_T_1, _s1_nack_T_2)
reg s1_send_resp_or_nack : UInt<1>[1], clock
connect s1_send_resp_or_nack, s0_send_resp_or_nack
reg s1_type : UInt, clock
connect s1_type, s0_type
reg s1_mshr_meta_read_way_en : UInt, clock
connect s1_mshr_meta_read_way_en, mshrs.io.meta_read.bits.way_en
reg s1_replay_way_en : UInt, clock
connect s1_replay_way_en, mshrs.io.replay.bits.way_en
reg s1_wb_way_en : UInt, clock
connect s1_wb_way_en, wb.io.data_req.bits.way_en
node _s1_tag_eq_way_T = shr(s1_req[0].addr, 10)
node _s1_tag_eq_way_T_1 = eq(meta_0.io.resp[0].tag, _s1_tag_eq_way_T)
node _s1_tag_eq_way_T_2 = shr(s1_req[0].addr, 10)
node _s1_tag_eq_way_T_3 = eq(meta_0.io.resp[1].tag, _s1_tag_eq_way_T_2)
wire _s1_tag_eq_way_WIRE : UInt<1>[2]
connect _s1_tag_eq_way_WIRE[0], _s1_tag_eq_way_T_1
connect _s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_T_3
node _s1_tag_eq_way_T_4 = cat(_s1_tag_eq_way_WIRE[1], _s1_tag_eq_way_WIRE[0])
wire s1_tag_eq_way : UInt<2>[1]
connect s1_tag_eq_way[0], _s1_tag_eq_way_T_4
node _s1_tag_match_way_T = eq(s1_type, UInt<3>(0h0))
node _s1_tag_match_way_T_1 = eq(s1_type, UInt<3>(0h2))
node _s1_tag_match_way_T_2 = eq(s1_type, UInt<3>(0h3))
node _s1_tag_match_way_T_3 = bits(s1_tag_eq_way[0], 0, 0)
node _s1_tag_match_way_T_4 = gt(meta_0.io.resp[0].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_5 = and(_s1_tag_match_way_T_3, _s1_tag_match_way_T_4)
node _s1_tag_match_way_T_6 = bits(s1_tag_eq_way[0], 1, 1)
node _s1_tag_match_way_T_7 = gt(meta_0.io.resp[1].coh.state, UInt<2>(0h0))
node _s1_tag_match_way_T_8 = and(_s1_tag_match_way_T_6, _s1_tag_match_way_T_7)
wire _s1_tag_match_way_WIRE : UInt<1>[2]
connect _s1_tag_match_way_WIRE[0], _s1_tag_match_way_T_5
connect _s1_tag_match_way_WIRE[1], _s1_tag_match_way_T_8
node _s1_tag_match_way_T_9 = cat(_s1_tag_match_way_WIRE[1], _s1_tag_match_way_WIRE[0])
node _s1_tag_match_way_T_10 = mux(_s1_tag_match_way_T_2, s1_mshr_meta_read_way_en, _s1_tag_match_way_T_9)
node _s1_tag_match_way_T_11 = mux(_s1_tag_match_way_T_1, s1_wb_way_en, _s1_tag_match_way_T_10)
node _s1_tag_match_way_T_12 = mux(_s1_tag_match_way_T, s1_replay_way_en, _s1_tag_match_way_T_11)
wire s1_tag_match_way : UInt[1]
connect s1_tag_match_way[0], _s1_tag_match_way_T_12
node _s1_wb_idx_matches_T = bits(s1_req[0].addr, 9, 6)
node _s1_wb_idx_matches_T_1 = eq(_s1_wb_idx_matches_T, wb.io.idx.bits)
node _s1_wb_idx_matches_T_2 = and(_s1_wb_idx_matches_T_1, wb.io.idx.valid)
wire s1_wb_idx_matches : UInt<1>[1]
connect s1_wb_idx_matches[0], _s1_wb_idx_matches_T_2
reg s2_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}[1], clock
connect s2_req, s1_req
reg s2_type : UInt, clock
connect s2_type, s1_type
node _s2_valid_T = eq(io.lsu.s1_kill[0], UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid[0], _s2_valid_T)
node _s2_valid_T_2 = and(io.lsu.brupdate.b1.mispredict_mask, s1_req[0].uop.br_mask)
node _s2_valid_T_3 = neq(_s2_valid_T_2, UInt<1>(0h0))
node _s2_valid_T_4 = eq(_s2_valid_T_3, UInt<1>(0h0))
node _s2_valid_T_5 = and(_s2_valid_T_1, _s2_valid_T_4)
node _s2_valid_T_6 = and(io.lsu.exception, s1_req[0].uop.uses_ldq)
node _s2_valid_T_7 = eq(_s2_valid_T_6, UInt<1>(0h0))
node _s2_valid_T_8 = and(_s2_valid_T_5, _s2_valid_T_7)
node _s2_valid_T_9 = eq(s1_type, UInt<3>(0h4))
node _s2_valid_T_10 = and(s2_store_failed, _s2_valid_T_9)
node _s2_valid_T_11 = and(_s2_valid_T_10, s1_req[0].uop.uses_stq)
node _s2_valid_T_12 = eq(_s2_valid_T_11, UInt<1>(0h0))
node _s2_valid_T_13 = and(_s2_valid_T_8, _s2_valid_T_12)
reg s2_valid_REG : UInt<1>, clock
connect s2_valid_REG, _s2_valid_T_13
wire s2_valid : UInt<1>[1]
connect s2_valid[0], s2_valid_REG
node _s2_req_0_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _s2_req_0_uop_br_mask_T_1 = and(s1_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T)
connect s2_req[0].uop.br_mask, _s2_req_0_uop_br_mask_T_1
reg s2_tag_match_way : UInt[1], clock
connect s2_tag_match_way, s1_tag_match_way
node s2_tag_match_0 = orr(s2_tag_match_way[0])
reg s2_hit_state_REG : { state : UInt<2>}, clock
connect s2_hit_state_REG, meta_0.io.resp[0].coh
reg s2_hit_state_REG_1 : { state : UInt<2>}, clock
connect s2_hit_state_REG_1, meta_0.io.resp[1].coh
wire _s2_hit_state_WIRE : { state : UInt<2>}[2]
connect _s2_hit_state_WIRE[0], s2_hit_state_REG
connect _s2_hit_state_WIRE[1], s2_hit_state_REG_1
node _s2_hit_state_T = bits(s2_tag_match_way[0], 0, 0)
node _s2_hit_state_T_1 = bits(s2_tag_match_way[0], 1, 1)
wire _s2_hit_state_WIRE_1 : { state : UInt<2>}
node _s2_hit_state_T_2 = mux(_s2_hit_state_T, _s2_hit_state_WIRE[0].state, UInt<1>(0h0))
node _s2_hit_state_T_3 = mux(_s2_hit_state_T_1, _s2_hit_state_WIRE[1].state, UInt<1>(0h0))
node _s2_hit_state_T_4 = or(_s2_hit_state_T_2, _s2_hit_state_T_3)
wire _s2_hit_state_WIRE_2 : UInt<2>
connect _s2_hit_state_WIRE_2, _s2_hit_state_T_4
connect _s2_hit_state_WIRE_1.state, _s2_hit_state_WIRE_2
wire s2_hit_state : { state : UInt<2>}[1]
connect s2_hit_state[0], _s2_hit_state_WIRE_1
node _s2_has_permission_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_has_permission_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_has_permission_r_c_cat_T_2 = or(_s2_has_permission_r_c_cat_T, _s2_has_permission_r_c_cat_T_1)
node _s2_has_permission_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_has_permission_r_c_cat_T_4 = or(_s2_has_permission_r_c_cat_T_2, _s2_has_permission_r_c_cat_T_3)
node _s2_has_permission_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_has_permission_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_has_permission_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_has_permission_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_has_permission_r_c_cat_T_9 = or(_s2_has_permission_r_c_cat_T_5, _s2_has_permission_r_c_cat_T_6)
node _s2_has_permission_r_c_cat_T_10 = or(_s2_has_permission_r_c_cat_T_9, _s2_has_permission_r_c_cat_T_7)
node _s2_has_permission_r_c_cat_T_11 = or(_s2_has_permission_r_c_cat_T_10, _s2_has_permission_r_c_cat_T_8)
node _s2_has_permission_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_has_permission_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_has_permission_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_has_permission_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_has_permission_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_has_permission_r_c_cat_T_17 = or(_s2_has_permission_r_c_cat_T_12, _s2_has_permission_r_c_cat_T_13)
node _s2_has_permission_r_c_cat_T_18 = or(_s2_has_permission_r_c_cat_T_17, _s2_has_permission_r_c_cat_T_14)
node _s2_has_permission_r_c_cat_T_19 = or(_s2_has_permission_r_c_cat_T_18, _s2_has_permission_r_c_cat_T_15)
node _s2_has_permission_r_c_cat_T_20 = or(_s2_has_permission_r_c_cat_T_19, _s2_has_permission_r_c_cat_T_16)
node _s2_has_permission_r_c_cat_T_21 = or(_s2_has_permission_r_c_cat_T_11, _s2_has_permission_r_c_cat_T_20)
node _s2_has_permission_r_c_cat_T_22 = or(_s2_has_permission_r_c_cat_T_4, _s2_has_permission_r_c_cat_T_21)
node _s2_has_permission_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_has_permission_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_has_permission_r_c_cat_T_25 = or(_s2_has_permission_r_c_cat_T_23, _s2_has_permission_r_c_cat_T_24)
node _s2_has_permission_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_has_permission_r_c_cat_T_27 = or(_s2_has_permission_r_c_cat_T_25, _s2_has_permission_r_c_cat_T_26)
node _s2_has_permission_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_has_permission_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_has_permission_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_has_permission_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_has_permission_r_c_cat_T_32 = or(_s2_has_permission_r_c_cat_T_28, _s2_has_permission_r_c_cat_T_29)
node _s2_has_permission_r_c_cat_T_33 = or(_s2_has_permission_r_c_cat_T_32, _s2_has_permission_r_c_cat_T_30)
node _s2_has_permission_r_c_cat_T_34 = or(_s2_has_permission_r_c_cat_T_33, _s2_has_permission_r_c_cat_T_31)
node _s2_has_permission_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_has_permission_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_has_permission_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_has_permission_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_has_permission_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_has_permission_r_c_cat_T_40 = or(_s2_has_permission_r_c_cat_T_35, _s2_has_permission_r_c_cat_T_36)
node _s2_has_permission_r_c_cat_T_41 = or(_s2_has_permission_r_c_cat_T_40, _s2_has_permission_r_c_cat_T_37)
node _s2_has_permission_r_c_cat_T_42 = or(_s2_has_permission_r_c_cat_T_41, _s2_has_permission_r_c_cat_T_38)
node _s2_has_permission_r_c_cat_T_43 = or(_s2_has_permission_r_c_cat_T_42, _s2_has_permission_r_c_cat_T_39)
node _s2_has_permission_r_c_cat_T_44 = or(_s2_has_permission_r_c_cat_T_34, _s2_has_permission_r_c_cat_T_43)
node _s2_has_permission_r_c_cat_T_45 = or(_s2_has_permission_r_c_cat_T_27, _s2_has_permission_r_c_cat_T_44)
node _s2_has_permission_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _s2_has_permission_r_c_cat_T_47 = or(_s2_has_permission_r_c_cat_T_45, _s2_has_permission_r_c_cat_T_46)
node _s2_has_permission_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_has_permission_r_c_cat_T_49 = or(_s2_has_permission_r_c_cat_T_47, _s2_has_permission_r_c_cat_T_48)
node s2_has_permission_r_c = cat(_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49)
node _s2_has_permission_r_T = cat(s2_has_permission_r_c, s2_hit_state[0].state)
node _s2_has_permission_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_2 = cat(_s2_has_permission_r_T_1, UInt<2>(0h3))
node _s2_has_permission_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_4 = cat(_s2_has_permission_r_T_3, UInt<2>(0h2))
node _s2_has_permission_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_6 = cat(_s2_has_permission_r_T_5, UInt<2>(0h1))
node _s2_has_permission_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_8 = cat(_s2_has_permission_r_T_7, UInt<2>(0h3))
node _s2_has_permission_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_10 = cat(_s2_has_permission_r_T_9, UInt<2>(0h2))
node _s2_has_permission_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_12 = cat(_s2_has_permission_r_T_11, UInt<2>(0h3))
node _s2_has_permission_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_14 = cat(_s2_has_permission_r_T_13, UInt<2>(0h2))
node _s2_has_permission_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_16 = cat(_s2_has_permission_r_T_15, UInt<2>(0h0))
node _s2_has_permission_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_18 = cat(_s2_has_permission_r_T_17, UInt<2>(0h1))
node _s2_has_permission_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_has_permission_r_T_20 = cat(_s2_has_permission_r_T_19, UInt<2>(0h0))
node _s2_has_permission_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_22 = cat(_s2_has_permission_r_T_21, UInt<2>(0h1))
node _s2_has_permission_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_has_permission_r_T_24 = cat(_s2_has_permission_r_T_23, UInt<2>(0h0))
node _s2_has_permission_r_T_25 = eq(_s2_has_permission_r_T_24, _s2_has_permission_r_T)
node _s2_has_permission_r_T_26 = mux(_s2_has_permission_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _s2_has_permission_r_T_27 = mux(_s2_has_permission_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _s2_has_permission_r_T_28 = eq(_s2_has_permission_r_T_22, _s2_has_permission_r_T)
node _s2_has_permission_r_T_29 = mux(_s2_has_permission_r_T_28, UInt<1>(0h0), _s2_has_permission_r_T_26)
node _s2_has_permission_r_T_30 = mux(_s2_has_permission_r_T_28, UInt<2>(0h2), _s2_has_permission_r_T_27)
node _s2_has_permission_r_T_31 = eq(_s2_has_permission_r_T_20, _s2_has_permission_r_T)
node _s2_has_permission_r_T_32 = mux(_s2_has_permission_r_T_31, UInt<1>(0h0), _s2_has_permission_r_T_29)
node _s2_has_permission_r_T_33 = mux(_s2_has_permission_r_T_31, UInt<2>(0h1), _s2_has_permission_r_T_30)
node _s2_has_permission_r_T_34 = eq(_s2_has_permission_r_T_18, _s2_has_permission_r_T)
node _s2_has_permission_r_T_35 = mux(_s2_has_permission_r_T_34, UInt<1>(0h0), _s2_has_permission_r_T_32)
node _s2_has_permission_r_T_36 = mux(_s2_has_permission_r_T_34, UInt<2>(0h2), _s2_has_permission_r_T_33)
node _s2_has_permission_r_T_37 = eq(_s2_has_permission_r_T_16, _s2_has_permission_r_T)
node _s2_has_permission_r_T_38 = mux(_s2_has_permission_r_T_37, UInt<1>(0h0), _s2_has_permission_r_T_35)
node _s2_has_permission_r_T_39 = mux(_s2_has_permission_r_T_37, UInt<2>(0h0), _s2_has_permission_r_T_36)
node _s2_has_permission_r_T_40 = eq(_s2_has_permission_r_T_14, _s2_has_permission_r_T)
node _s2_has_permission_r_T_41 = mux(_s2_has_permission_r_T_40, UInt<1>(0h1), _s2_has_permission_r_T_38)
node _s2_has_permission_r_T_42 = mux(_s2_has_permission_r_T_40, UInt<2>(0h3), _s2_has_permission_r_T_39)
node _s2_has_permission_r_T_43 = eq(_s2_has_permission_r_T_12, _s2_has_permission_r_T)
node _s2_has_permission_r_T_44 = mux(_s2_has_permission_r_T_43, UInt<1>(0h1), _s2_has_permission_r_T_41)
node _s2_has_permission_r_T_45 = mux(_s2_has_permission_r_T_43, UInt<2>(0h3), _s2_has_permission_r_T_42)
node _s2_has_permission_r_T_46 = eq(_s2_has_permission_r_T_10, _s2_has_permission_r_T)
node _s2_has_permission_r_T_47 = mux(_s2_has_permission_r_T_46, UInt<1>(0h1), _s2_has_permission_r_T_44)
node _s2_has_permission_r_T_48 = mux(_s2_has_permission_r_T_46, UInt<2>(0h2), _s2_has_permission_r_T_45)
node _s2_has_permission_r_T_49 = eq(_s2_has_permission_r_T_8, _s2_has_permission_r_T)
node _s2_has_permission_r_T_50 = mux(_s2_has_permission_r_T_49, UInt<1>(0h1), _s2_has_permission_r_T_47)
node _s2_has_permission_r_T_51 = mux(_s2_has_permission_r_T_49, UInt<2>(0h3), _s2_has_permission_r_T_48)
node _s2_has_permission_r_T_52 = eq(_s2_has_permission_r_T_6, _s2_has_permission_r_T)
node _s2_has_permission_r_T_53 = mux(_s2_has_permission_r_T_52, UInt<1>(0h1), _s2_has_permission_r_T_50)
node _s2_has_permission_r_T_54 = mux(_s2_has_permission_r_T_52, UInt<2>(0h1), _s2_has_permission_r_T_51)
node _s2_has_permission_r_T_55 = eq(_s2_has_permission_r_T_4, _s2_has_permission_r_T)
node _s2_has_permission_r_T_56 = mux(_s2_has_permission_r_T_55, UInt<1>(0h1), _s2_has_permission_r_T_53)
node _s2_has_permission_r_T_57 = mux(_s2_has_permission_r_T_55, UInt<2>(0h2), _s2_has_permission_r_T_54)
node _s2_has_permission_r_T_58 = eq(_s2_has_permission_r_T_2, _s2_has_permission_r_T)
node s2_has_permission_r_1 = mux(_s2_has_permission_r_T_58, UInt<1>(0h1), _s2_has_permission_r_T_56)
node s2_has_permission_r_2 = mux(_s2_has_permission_r_T_58, UInt<2>(0h3), _s2_has_permission_r_T_57)
wire s2_has_permission_meta : { state : UInt<2>}
connect s2_has_permission_meta.state, s2_has_permission_r_2
wire s2_has_permission : UInt<1>[1]
connect s2_has_permission[0], s2_has_permission_r_1
node _s2_new_hit_state_r_c_cat_T = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_new_hit_state_r_c_cat_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_new_hit_state_r_c_cat_T_2 = or(_s2_new_hit_state_r_c_cat_T, _s2_new_hit_state_r_c_cat_T_1)
node _s2_new_hit_state_r_c_cat_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_new_hit_state_r_c_cat_T_4 = or(_s2_new_hit_state_r_c_cat_T_2, _s2_new_hit_state_r_c_cat_T_3)
node _s2_new_hit_state_r_c_cat_T_5 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_new_hit_state_r_c_cat_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_new_hit_state_r_c_cat_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_new_hit_state_r_c_cat_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_new_hit_state_r_c_cat_T_9 = or(_s2_new_hit_state_r_c_cat_T_5, _s2_new_hit_state_r_c_cat_T_6)
node _s2_new_hit_state_r_c_cat_T_10 = or(_s2_new_hit_state_r_c_cat_T_9, _s2_new_hit_state_r_c_cat_T_7)
node _s2_new_hit_state_r_c_cat_T_11 = or(_s2_new_hit_state_r_c_cat_T_10, _s2_new_hit_state_r_c_cat_T_8)
node _s2_new_hit_state_r_c_cat_T_12 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_new_hit_state_r_c_cat_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_new_hit_state_r_c_cat_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_new_hit_state_r_c_cat_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_new_hit_state_r_c_cat_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_new_hit_state_r_c_cat_T_17 = or(_s2_new_hit_state_r_c_cat_T_12, _s2_new_hit_state_r_c_cat_T_13)
node _s2_new_hit_state_r_c_cat_T_18 = or(_s2_new_hit_state_r_c_cat_T_17, _s2_new_hit_state_r_c_cat_T_14)
node _s2_new_hit_state_r_c_cat_T_19 = or(_s2_new_hit_state_r_c_cat_T_18, _s2_new_hit_state_r_c_cat_T_15)
node _s2_new_hit_state_r_c_cat_T_20 = or(_s2_new_hit_state_r_c_cat_T_19, _s2_new_hit_state_r_c_cat_T_16)
node _s2_new_hit_state_r_c_cat_T_21 = or(_s2_new_hit_state_r_c_cat_T_11, _s2_new_hit_state_r_c_cat_T_20)
node _s2_new_hit_state_r_c_cat_T_22 = or(_s2_new_hit_state_r_c_cat_T_4, _s2_new_hit_state_r_c_cat_T_21)
node _s2_new_hit_state_r_c_cat_T_23 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_new_hit_state_r_c_cat_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_new_hit_state_r_c_cat_T_25 = or(_s2_new_hit_state_r_c_cat_T_23, _s2_new_hit_state_r_c_cat_T_24)
node _s2_new_hit_state_r_c_cat_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_new_hit_state_r_c_cat_T_27 = or(_s2_new_hit_state_r_c_cat_T_25, _s2_new_hit_state_r_c_cat_T_26)
node _s2_new_hit_state_r_c_cat_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_new_hit_state_r_c_cat_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_new_hit_state_r_c_cat_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_new_hit_state_r_c_cat_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_new_hit_state_r_c_cat_T_32 = or(_s2_new_hit_state_r_c_cat_T_28, _s2_new_hit_state_r_c_cat_T_29)
node _s2_new_hit_state_r_c_cat_T_33 = or(_s2_new_hit_state_r_c_cat_T_32, _s2_new_hit_state_r_c_cat_T_30)
node _s2_new_hit_state_r_c_cat_T_34 = or(_s2_new_hit_state_r_c_cat_T_33, _s2_new_hit_state_r_c_cat_T_31)
node _s2_new_hit_state_r_c_cat_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_new_hit_state_r_c_cat_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_new_hit_state_r_c_cat_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_new_hit_state_r_c_cat_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_new_hit_state_r_c_cat_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_new_hit_state_r_c_cat_T_40 = or(_s2_new_hit_state_r_c_cat_T_35, _s2_new_hit_state_r_c_cat_T_36)
node _s2_new_hit_state_r_c_cat_T_41 = or(_s2_new_hit_state_r_c_cat_T_40, _s2_new_hit_state_r_c_cat_T_37)
node _s2_new_hit_state_r_c_cat_T_42 = or(_s2_new_hit_state_r_c_cat_T_41, _s2_new_hit_state_r_c_cat_T_38)
node _s2_new_hit_state_r_c_cat_T_43 = or(_s2_new_hit_state_r_c_cat_T_42, _s2_new_hit_state_r_c_cat_T_39)
node _s2_new_hit_state_r_c_cat_T_44 = or(_s2_new_hit_state_r_c_cat_T_34, _s2_new_hit_state_r_c_cat_T_43)
node _s2_new_hit_state_r_c_cat_T_45 = or(_s2_new_hit_state_r_c_cat_T_27, _s2_new_hit_state_r_c_cat_T_44)
node _s2_new_hit_state_r_c_cat_T_46 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _s2_new_hit_state_r_c_cat_T_47 = or(_s2_new_hit_state_r_c_cat_T_45, _s2_new_hit_state_r_c_cat_T_46)
node _s2_new_hit_state_r_c_cat_T_48 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_new_hit_state_r_c_cat_T_49 = or(_s2_new_hit_state_r_c_cat_T_47, _s2_new_hit_state_r_c_cat_T_48)
node s2_new_hit_state_r_c = cat(_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49)
node _s2_new_hit_state_r_T = cat(s2_new_hit_state_r_c, s2_hit_state[0].state)
node _s2_new_hit_state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_2 = cat(_s2_new_hit_state_r_T_1, UInt<2>(0h3))
node _s2_new_hit_state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_4 = cat(_s2_new_hit_state_r_T_3, UInt<2>(0h2))
node _s2_new_hit_state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_6 = cat(_s2_new_hit_state_r_T_5, UInt<2>(0h1))
node _s2_new_hit_state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_8 = cat(_s2_new_hit_state_r_T_7, UInt<2>(0h3))
node _s2_new_hit_state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_10 = cat(_s2_new_hit_state_r_T_9, UInt<2>(0h2))
node _s2_new_hit_state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_12 = cat(_s2_new_hit_state_r_T_11, UInt<2>(0h3))
node _s2_new_hit_state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_14 = cat(_s2_new_hit_state_r_T_13, UInt<2>(0h2))
node _s2_new_hit_state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_16 = cat(_s2_new_hit_state_r_T_15, UInt<2>(0h0))
node _s2_new_hit_state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_18 = cat(_s2_new_hit_state_r_T_17, UInt<2>(0h1))
node _s2_new_hit_state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _s2_new_hit_state_r_T_20 = cat(_s2_new_hit_state_r_T_19, UInt<2>(0h0))
node _s2_new_hit_state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_22 = cat(_s2_new_hit_state_r_T_21, UInt<2>(0h1))
node _s2_new_hit_state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _s2_new_hit_state_r_T_24 = cat(_s2_new_hit_state_r_T_23, UInt<2>(0h0))
node _s2_new_hit_state_r_T_25 = eq(_s2_new_hit_state_r_T_24, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_26 = mux(_s2_new_hit_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _s2_new_hit_state_r_T_27 = mux(_s2_new_hit_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _s2_new_hit_state_r_T_28 = eq(_s2_new_hit_state_r_T_22, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_29 = mux(_s2_new_hit_state_r_T_28, UInt<1>(0h0), _s2_new_hit_state_r_T_26)
node _s2_new_hit_state_r_T_30 = mux(_s2_new_hit_state_r_T_28, UInt<2>(0h2), _s2_new_hit_state_r_T_27)
node _s2_new_hit_state_r_T_31 = eq(_s2_new_hit_state_r_T_20, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_32 = mux(_s2_new_hit_state_r_T_31, UInt<1>(0h0), _s2_new_hit_state_r_T_29)
node _s2_new_hit_state_r_T_33 = mux(_s2_new_hit_state_r_T_31, UInt<2>(0h1), _s2_new_hit_state_r_T_30)
node _s2_new_hit_state_r_T_34 = eq(_s2_new_hit_state_r_T_18, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_35 = mux(_s2_new_hit_state_r_T_34, UInt<1>(0h0), _s2_new_hit_state_r_T_32)
node _s2_new_hit_state_r_T_36 = mux(_s2_new_hit_state_r_T_34, UInt<2>(0h2), _s2_new_hit_state_r_T_33)
node _s2_new_hit_state_r_T_37 = eq(_s2_new_hit_state_r_T_16, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_38 = mux(_s2_new_hit_state_r_T_37, UInt<1>(0h0), _s2_new_hit_state_r_T_35)
node _s2_new_hit_state_r_T_39 = mux(_s2_new_hit_state_r_T_37, UInt<2>(0h0), _s2_new_hit_state_r_T_36)
node _s2_new_hit_state_r_T_40 = eq(_s2_new_hit_state_r_T_14, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_41 = mux(_s2_new_hit_state_r_T_40, UInt<1>(0h1), _s2_new_hit_state_r_T_38)
node _s2_new_hit_state_r_T_42 = mux(_s2_new_hit_state_r_T_40, UInt<2>(0h3), _s2_new_hit_state_r_T_39)
node _s2_new_hit_state_r_T_43 = eq(_s2_new_hit_state_r_T_12, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_44 = mux(_s2_new_hit_state_r_T_43, UInt<1>(0h1), _s2_new_hit_state_r_T_41)
node _s2_new_hit_state_r_T_45 = mux(_s2_new_hit_state_r_T_43, UInt<2>(0h3), _s2_new_hit_state_r_T_42)
node _s2_new_hit_state_r_T_46 = eq(_s2_new_hit_state_r_T_10, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_47 = mux(_s2_new_hit_state_r_T_46, UInt<1>(0h1), _s2_new_hit_state_r_T_44)
node _s2_new_hit_state_r_T_48 = mux(_s2_new_hit_state_r_T_46, UInt<2>(0h2), _s2_new_hit_state_r_T_45)
node _s2_new_hit_state_r_T_49 = eq(_s2_new_hit_state_r_T_8, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_50 = mux(_s2_new_hit_state_r_T_49, UInt<1>(0h1), _s2_new_hit_state_r_T_47)
node _s2_new_hit_state_r_T_51 = mux(_s2_new_hit_state_r_T_49, UInt<2>(0h3), _s2_new_hit_state_r_T_48)
node _s2_new_hit_state_r_T_52 = eq(_s2_new_hit_state_r_T_6, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_53 = mux(_s2_new_hit_state_r_T_52, UInt<1>(0h1), _s2_new_hit_state_r_T_50)
node _s2_new_hit_state_r_T_54 = mux(_s2_new_hit_state_r_T_52, UInt<2>(0h1), _s2_new_hit_state_r_T_51)
node _s2_new_hit_state_r_T_55 = eq(_s2_new_hit_state_r_T_4, _s2_new_hit_state_r_T)
node _s2_new_hit_state_r_T_56 = mux(_s2_new_hit_state_r_T_55, UInt<1>(0h1), _s2_new_hit_state_r_T_53)
node _s2_new_hit_state_r_T_57 = mux(_s2_new_hit_state_r_T_55, UInt<2>(0h2), _s2_new_hit_state_r_T_54)
node _s2_new_hit_state_r_T_58 = eq(_s2_new_hit_state_r_T_2, _s2_new_hit_state_r_T)
node s2_new_hit_state_r_1 = mux(_s2_new_hit_state_r_T_58, UInt<1>(0h1), _s2_new_hit_state_r_T_56)
node s2_new_hit_state_r_2 = mux(_s2_new_hit_state_r_T_58, UInt<2>(0h3), _s2_new_hit_state_r_T_57)
wire s2_new_hit_state_meta : { state : UInt<2>}
connect s2_new_hit_state_meta.state, s2_new_hit_state_r_2
wire s2_new_hit_state : { state : UInt<2>}[1]
connect s2_new_hit_state[0], s2_new_hit_state_meta
node _s2_hit_T = and(s2_tag_match_0, s2_has_permission[0])
node _s2_hit_T_1 = eq(s2_hit_state[0].state, s2_new_hit_state[0].state)
node _s2_hit_T_2 = and(_s2_hit_T, _s2_hit_T_1)
node _s2_hit_T_3 = eq(mshrs.io.block_hit[0], UInt<1>(0h0))
node _s2_hit_T_4 = and(_s2_hit_T_2, _s2_hit_T_3)
node _s2_hit_T_5 = eq(s2_type, UInt<3>(0h0))
node _s2_hit_T_6 = eq(s2_type, UInt<3>(0h2))
node _s2_hit_T_7 = or(_s2_hit_T_5, _s2_hit_T_6)
node _s2_hit_T_8 = or(_s2_hit_T_4, _s2_hit_T_7)
wire s2_hit : UInt<1>[1]
connect s2_hit[0], _s2_hit_T_8
wire s2_nack : UInt<1>[1]
node _T_16 = eq(s2_type, UInt<3>(0h0))
node _T_17 = eq(s2_hit[0], UInt<1>(0h0))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed: Replays should always hit\n at dcache.scala:651 assert(!(s2_type === t_replay && !s2_hit(0)), \"Replays should always hit\")\n") : printf_2
assert(clock, _T_19, UInt<1>(0h1), "") : assert_2
node _T_23 = eq(s2_type, UInt<3>(0h2))
node _T_24 = eq(s2_hit[0], UInt<1>(0h0))
node _T_25 = and(_T_23, _T_24)
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed: Writeback should always see data hit\n at dcache.scala:652 assert(!(s2_type === t_wb && !s2_hit(0)), \"Writeback should always see data hit\")\n") : printf_3
assert(clock, _T_26, UInt<1>(0h1), "") : assert_3
reg s2_wb_idx_matches : UInt<1>[1], clock
connect s2_wb_idx_matches, s1_wb_idx_matches
regreset debug_sc_fail_addr : UInt, clock, reset, UInt<1>(0h0)
regreset debug_sc_fail_cnt : UInt<8>, clock, reset, UInt<8>(0h0)
regreset lrsc_count : UInt<7>, clock, reset, UInt<7>(0h0)
node lrsc_valid = gt(lrsc_count, UInt<2>(0h3))
reg lrsc_addr : UInt, clock
node _s2_lr_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
reg s2_lr_REG : UInt<1>, clock
connect s2_lr_REG, s1_nack_0
node _s2_lr_T_1 = eq(s2_lr_REG, UInt<1>(0h0))
node _s2_lr_T_2 = eq(s2_type, UInt<3>(0h0))
node _s2_lr_T_3 = or(_s2_lr_T_1, _s2_lr_T_2)
node s2_lr = and(_s2_lr_T, _s2_lr_T_3)
node _s2_sc_T = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
reg s2_sc_REG : UInt<1>, clock
connect s2_sc_REG, s1_nack_0
node _s2_sc_T_1 = eq(s2_sc_REG, UInt<1>(0h0))
node _s2_sc_T_2 = eq(s2_type, UInt<3>(0h0))
node _s2_sc_T_3 = or(_s2_sc_T_1, _s2_sc_T_2)
node s2_sc = and(_s2_sc_T, _s2_sc_T_3)
node _s2_lrsc_addr_match_T = shr(s2_req[0].addr, 6)
node _s2_lrsc_addr_match_T_1 = eq(lrsc_addr, _s2_lrsc_addr_match_T)
node _s2_lrsc_addr_match_T_2 = and(lrsc_valid, _s2_lrsc_addr_match_T_1)
wire s2_lrsc_addr_match : UInt<1>[1]
connect s2_lrsc_addr_match[0], _s2_lrsc_addr_match_T_2
node _s2_sc_fail_T = eq(s2_lrsc_addr_match[0], UInt<1>(0h0))
node s2_sc_fail = and(s2_sc, _s2_sc_fail_T)
node _T_30 = gt(lrsc_count, UInt<1>(0h0))
when _T_30 :
node _lrsc_count_T = sub(lrsc_count, UInt<1>(0h1))
node _lrsc_count_T_1 = tail(_lrsc_count_T, 1)
connect lrsc_count, _lrsc_count_T_1
node _T_31 = eq(s2_type, UInt<3>(0h4))
node _T_32 = and(_T_31, s2_hit[0])
node _T_33 = eq(s2_nack[0], UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(s2_type, UInt<3>(0h0))
node _T_36 = neq(s2_req[0].uop.mem_cmd, UInt<3>(0h5))
node _T_37 = and(_T_35, _T_36)
node _T_38 = or(_T_34, _T_37)
node _T_39 = and(s2_valid[0], _T_38)
when _T_39 :
when s2_lr :
connect lrsc_count, UInt<7>(0h4f)
node _lrsc_addr_T = shr(s2_req[0].addr, 6)
connect lrsc_addr, _lrsc_addr_T
node _T_40 = gt(lrsc_count, UInt<1>(0h0))
when _T_40 :
connect lrsc_count, UInt<1>(0h0)
node _T_41 = eq(s2_type, UInt<3>(0h4))
node _T_42 = and(s2_valid[0], _T_41)
node _T_43 = eq(s2_hit[0], UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = and(s2_has_permission[0], s2_tag_match_0)
node _T_46 = eq(_T_45, UInt<1>(0h0))
node _T_47 = and(_T_44, _T_46)
node _T_48 = and(_T_47, s2_lrsc_addr_match[0])
node _T_49 = eq(s2_nack[0], UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
when _T_50 :
connect lrsc_count, UInt<1>(0h0)
when s2_valid[0] :
node _T_51 = eq(s2_req[0].addr, debug_sc_fail_addr)
when _T_51 :
when s2_sc_fail :
node _debug_sc_fail_cnt_T = add(debug_sc_fail_cnt, UInt<1>(0h1))
node _debug_sc_fail_cnt_T_1 = tail(_debug_sc_fail_cnt_T, 1)
connect debug_sc_fail_cnt, _debug_sc_fail_cnt_T_1
else :
when s2_sc :
connect debug_sc_fail_cnt, UInt<1>(0h0)
else :
when s2_sc_fail :
connect debug_sc_fail_addr, s2_req[0].addr
connect debug_sc_fail_cnt, UInt<1>(0h1)
node _T_52 = lt(debug_sc_fail_cnt, UInt<7>(0h64))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: L1DCache failed too many SCs in a row\n at dcache.scala:703 assert(debug_sc_fail_cnt < 100.U, \"L1DCache failed too many SCs in a row\")\n") : printf_4
assert(clock, _T_52, UInt<1>(0h1), "") : assert_4
wire s2_data : UInt<64>[2][1]
connect s2_data[0][0], data.io.resp[0][0]
connect s2_data[0][1], data.io.resp[0][1]
node _s2_data_muxed_T = bits(s2_tag_match_way[0], 0, 0)
node _s2_data_muxed_T_1 = bits(s2_tag_match_way[0], 1, 1)
node _s2_data_muxed_T_2 = mux(_s2_data_muxed_T, s2_data[0][0], UInt<1>(0h0))
node _s2_data_muxed_T_3 = mux(_s2_data_muxed_T_1, s2_data[0][1], UInt<1>(0h0))
node _s2_data_muxed_T_4 = or(_s2_data_muxed_T_2, _s2_data_muxed_T_3)
wire _s2_data_muxed_WIRE : UInt<64>
connect _s2_data_muxed_WIRE, _s2_data_muxed_T_4
wire s2_data_muxed : UInt<64>[1]
connect s2_data_muxed[0], _s2_data_muxed_WIRE
wire s2_word_idx : UInt<1>[1]
connect s2_word_idx[0], UInt<1>(0h0)
wire replace : UInt<1>
connect replace, UInt<1>(0h0)
inst lfsr_prng of MaxPeriodFibonacciLFSR_2
connect lfsr_prng.clock, clock
connect lfsr_prng.reset, reset
connect lfsr_prng.io.seed.valid, UInt<1>(0h0)
invalidate lfsr_prng.io.seed.bits[0]
invalidate lfsr_prng.io.seed.bits[1]
invalidate lfsr_prng.io.seed.bits[2]
invalidate lfsr_prng.io.seed.bits[3]
invalidate lfsr_prng.io.seed.bits[4]
invalidate lfsr_prng.io.seed.bits[5]
invalidate lfsr_prng.io.seed.bits[6]
invalidate lfsr_prng.io.seed.bits[7]
invalidate lfsr_prng.io.seed.bits[8]
invalidate lfsr_prng.io.seed.bits[9]
invalidate lfsr_prng.io.seed.bits[10]
invalidate lfsr_prng.io.seed.bits[11]
invalidate lfsr_prng.io.seed.bits[12]
invalidate lfsr_prng.io.seed.bits[13]
invalidate lfsr_prng.io.seed.bits[14]
invalidate lfsr_prng.io.seed.bits[15]
connect lfsr_prng.io.increment, replace
node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0])
node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2])
node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo)
node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4])
node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6])
node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo)
node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo)
node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8])
node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10])
node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo)
node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12])
node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14])
node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo)
node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo)
node lfsr = cat(lfsr_hi, lfsr_lo)
node _s1_replaced_way_en_T = bits(lfsr, 0, 0)
node s1_replaced_way_en = dshl(UInt<1>(0h1), _s1_replaced_way_en_T)
node _s2_replaced_way_en_T = bits(lfsr, 0, 0)
reg s2_replaced_way_en_REG : UInt, clock
connect s2_replaced_way_en_REG, _s2_replaced_way_en_T
node s2_replaced_way_en = dshl(UInt<1>(0h1), s2_replaced_way_en_REG)
reg s2_repl_meta_REG : { coh : { state : UInt<2>}, tag : UInt<22>}, clock
connect s2_repl_meta_REG, meta_0.io.resp[0]
reg s2_repl_meta_REG_1 : { coh : { state : UInt<2>}, tag : UInt<22>}, clock
connect s2_repl_meta_REG_1, meta_0.io.resp[1]
wire _s2_repl_meta_WIRE : { coh : { state : UInt<2>}, tag : UInt<22>}[2]
connect _s2_repl_meta_WIRE[0], s2_repl_meta_REG
connect _s2_repl_meta_WIRE[1], s2_repl_meta_REG_1
node _s2_repl_meta_T = bits(s2_replaced_way_en, 0, 0)
node _s2_repl_meta_T_1 = bits(s2_replaced_way_en, 1, 1)
wire _s2_repl_meta_WIRE_1 : { coh : { state : UInt<2>}, tag : UInt<22>}
node _s2_repl_meta_T_2 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].tag, UInt<1>(0h0))
node _s2_repl_meta_T_3 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].tag, UInt<1>(0h0))
node _s2_repl_meta_T_4 = or(_s2_repl_meta_T_2, _s2_repl_meta_T_3)
wire _s2_repl_meta_WIRE_2 : UInt<22>
connect _s2_repl_meta_WIRE_2, _s2_repl_meta_T_4
connect _s2_repl_meta_WIRE_1.tag, _s2_repl_meta_WIRE_2
wire _s2_repl_meta_WIRE_3 : { state : UInt<2>}
node _s2_repl_meta_T_5 = mux(_s2_repl_meta_T, _s2_repl_meta_WIRE[0].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_6 = mux(_s2_repl_meta_T_1, _s2_repl_meta_WIRE[1].coh.state, UInt<1>(0h0))
node _s2_repl_meta_T_7 = or(_s2_repl_meta_T_5, _s2_repl_meta_T_6)
wire _s2_repl_meta_WIRE_4 : UInt<2>
connect _s2_repl_meta_WIRE_4, _s2_repl_meta_T_7
connect _s2_repl_meta_WIRE_3.state, _s2_repl_meta_WIRE_4
connect _s2_repl_meta_WIRE_1.coh, _s2_repl_meta_WIRE_3
wire s2_repl_meta : { coh : { state : UInt<2>}, tag : UInt<22>}[1]
connect s2_repl_meta[0], _s2_repl_meta_WIRE_1
wire _s2_nack_hit_WIRE : UInt<1>[1]
connect _s2_nack_hit_WIRE[0], s1_nack_0
reg s2_nack_hit : UInt<1>[1], clock
connect s2_nack_hit, _s2_nack_hit_WIRE
node _s2_nack_victim_T = and(s2_valid[0], s2_hit[0])
node _s2_nack_victim_T_1 = and(_s2_nack_victim_T, mshrs.io.secondary_miss[0])
wire s2_nack_victim : UInt<1>[1]
connect s2_nack_victim[0], _s2_nack_victim_T_1
node _s2_nack_miss_T = eq(s2_hit[0], UInt<1>(0h0))
node _s2_nack_miss_T_1 = and(s2_valid[0], _s2_nack_miss_T)
node _s2_nack_miss_T_2 = eq(mshrs.io.req[0].ready, UInt<1>(0h0))
node _s2_nack_miss_T_3 = and(_s2_nack_miss_T_1, _s2_nack_miss_T_2)
wire s2_nack_miss : UInt<1>[1]
connect s2_nack_miss[0], _s2_nack_miss_T_3
wire s2_nack_data : UInt<1>[1]
connect s2_nack_data[0], data.io.nacks[0]
node _s2_nack_wb_T = eq(s2_hit[0], UInt<1>(0h0))
node _s2_nack_wb_T_1 = and(s2_valid[0], _s2_nack_wb_T)
node _s2_nack_wb_T_2 = and(_s2_nack_wb_T_1, s2_wb_idx_matches[0])
wire s2_nack_wb : UInt<1>[1]
connect s2_nack_wb[0], _s2_nack_wb_T_2
node _T_56 = or(s2_nack_miss[0], s2_nack_hit[0])
node _T_57 = or(_T_56, s2_nack_victim[0])
node _T_58 = or(_T_57, s2_nack_data[0])
node _T_59 = or(_T_58, s2_nack_wb[0])
node _T_60 = neq(s2_type, UInt<3>(0h0))
node _T_61 = and(_T_59, _T_60)
wire _WIRE_2 : UInt<1>[1]
connect _WIRE_2[0], _T_61
connect s2_nack, _WIRE_2
reg s2_send_resp_REG : UInt<1>, clock
connect s2_send_resp_REG, s1_send_resp_or_nack[0]
node _s2_send_resp_T = eq(s2_nack[0], UInt<1>(0h0))
node _s2_send_resp_T_1 = and(s2_send_resp_REG, _s2_send_resp_T)
node _s2_send_resp_T_2 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid)
node _s2_send_resp_T_3 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s2_send_resp_T_4 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s2_send_resp_T_5 = or(_s2_send_resp_T_3, _s2_send_resp_T_4)
node _s2_send_resp_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_send_resp_T_7 = or(_s2_send_resp_T_5, _s2_send_resp_T_6)
node _s2_send_resp_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_send_resp_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_send_resp_T_10 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_send_resp_T_11 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_send_resp_T_12 = or(_s2_send_resp_T_8, _s2_send_resp_T_9)
node _s2_send_resp_T_13 = or(_s2_send_resp_T_12, _s2_send_resp_T_10)
node _s2_send_resp_T_14 = or(_s2_send_resp_T_13, _s2_send_resp_T_11)
node _s2_send_resp_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_send_resp_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_send_resp_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_send_resp_T_18 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_send_resp_T_19 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_send_resp_T_20 = or(_s2_send_resp_T_15, _s2_send_resp_T_16)
node _s2_send_resp_T_21 = or(_s2_send_resp_T_20, _s2_send_resp_T_17)
node _s2_send_resp_T_22 = or(_s2_send_resp_T_21, _s2_send_resp_T_18)
node _s2_send_resp_T_23 = or(_s2_send_resp_T_22, _s2_send_resp_T_19)
node _s2_send_resp_T_24 = or(_s2_send_resp_T_14, _s2_send_resp_T_23)
node _s2_send_resp_T_25 = or(_s2_send_resp_T_7, _s2_send_resp_T_24)
node _s2_send_resp_T_26 = and(_s2_send_resp_T_2, _s2_send_resp_T_25)
node _s2_send_resp_T_27 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0))
node _s2_send_resp_T_28 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10))
node _s2_send_resp_T_29 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _s2_send_resp_T_30 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s2_send_resp_T_31 = or(_s2_send_resp_T_27, _s2_send_resp_T_28)
node _s2_send_resp_T_32 = or(_s2_send_resp_T_31, _s2_send_resp_T_29)
node _s2_send_resp_T_33 = or(_s2_send_resp_T_32, _s2_send_resp_T_30)
node _s2_send_resp_T_34 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s2_send_resp_T_35 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s2_send_resp_T_36 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s2_send_resp_T_37 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s2_send_resp_T_38 = or(_s2_send_resp_T_34, _s2_send_resp_T_35)
node _s2_send_resp_T_39 = or(_s2_send_resp_T_38, _s2_send_resp_T_36)
node _s2_send_resp_T_40 = or(_s2_send_resp_T_39, _s2_send_resp_T_37)
node _s2_send_resp_T_41 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s2_send_resp_T_42 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s2_send_resp_T_43 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s2_send_resp_T_44 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s2_send_resp_T_45 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s2_send_resp_T_46 = or(_s2_send_resp_T_41, _s2_send_resp_T_42)
node _s2_send_resp_T_47 = or(_s2_send_resp_T_46, _s2_send_resp_T_43)
node _s2_send_resp_T_48 = or(_s2_send_resp_T_47, _s2_send_resp_T_44)
node _s2_send_resp_T_49 = or(_s2_send_resp_T_48, _s2_send_resp_T_45)
node _s2_send_resp_T_50 = or(_s2_send_resp_T_40, _s2_send_resp_T_49)
node _s2_send_resp_T_51 = or(_s2_send_resp_T_33, _s2_send_resp_T_50)
node _s2_send_resp_T_52 = eq(_s2_send_resp_T_51, UInt<1>(0h0))
node _s2_send_resp_T_53 = and(_s2_send_resp_T_26, _s2_send_resp_T_52)
node _s2_send_resp_T_54 = or(s2_hit[0], _s2_send_resp_T_53)
node _s2_send_resp_T_55 = and(_s2_send_resp_T_1, _s2_send_resp_T_54)
wire s2_send_resp : UInt<1>[1]
connect s2_send_resp[0], _s2_send_resp_T_55
reg s2_send_nack_REG : UInt<1>, clock
connect s2_send_nack_REG, s1_send_resp_or_nack[0]
node _s2_send_nack_T = and(s2_send_nack_REG, s2_nack[0])
wire s2_send_nack : UInt<1>[1]
connect s2_send_nack[0], _s2_send_nack_T
node _T_62 = and(s2_send_resp[0], s2_send_nack[0])
node _T_63 = eq(_T_62, UInt<1>(0h0))
node _T_64 = asUInt(reset)
node _T_65 = eq(_T_64, UInt<1>(0h0))
when _T_65 :
node _T_66 = eq(_T_63, UInt<1>(0h0))
when _T_66 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:737 assert(!(s2_send_resp(w) && s2_send_nack(w)))\n") : printf_5
assert(clock, _T_63, UInt<1>(0h1), "") : assert_5
node _s2_store_failed_T = and(s2_valid[0], s2_nack[0])
node _s2_store_failed_T_1 = and(_s2_store_failed_T, s2_send_nack[0])
node _s2_store_failed_T_2 = and(_s2_store_failed_T_1, s2_req[0].uop.uses_stq)
connect s2_store_failed, _s2_store_failed_T_2
node _mshrs_io_req_0_valid_T = eq(s2_hit[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_1 = and(s2_valid[0], _mshrs_io_req_0_valid_T)
node _mshrs_io_req_0_valid_T_2 = eq(s2_nack_hit[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_3 = and(_mshrs_io_req_0_valid_T_1, _mshrs_io_req_0_valid_T_2)
node _mshrs_io_req_0_valid_T_4 = eq(s2_nack_victim[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_5 = and(_mshrs_io_req_0_valid_T_3, _mshrs_io_req_0_valid_T_4)
node _mshrs_io_req_0_valid_T_6 = eq(s2_nack_data[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_7 = and(_mshrs_io_req_0_valid_T_5, _mshrs_io_req_0_valid_T_6)
node _mshrs_io_req_0_valid_T_8 = eq(s2_nack_wb[0], UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_9 = and(_mshrs_io_req_0_valid_T_7, _mshrs_io_req_0_valid_T_8)
node _mshrs_io_req_0_valid_T_10 = eq(s2_type, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_11 = eq(s2_type, UInt<3>(0h5))
node _mshrs_io_req_0_valid_T_12 = or(_mshrs_io_req_0_valid_T_10, _mshrs_io_req_0_valid_T_11)
node _mshrs_io_req_0_valid_T_13 = and(_mshrs_io_req_0_valid_T_9, _mshrs_io_req_0_valid_T_12)
node _mshrs_io_req_0_valid_T_14 = and(io.lsu.brupdate.b1.mispredict_mask, s2_req[0].uop.br_mask)
node _mshrs_io_req_0_valid_T_15 = neq(_mshrs_io_req_0_valid_T_14, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_16 = eq(_mshrs_io_req_0_valid_T_15, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_17 = and(_mshrs_io_req_0_valid_T_13, _mshrs_io_req_0_valid_T_16)
node _mshrs_io_req_0_valid_T_18 = and(io.lsu.exception, s2_req[0].uop.uses_ldq)
node _mshrs_io_req_0_valid_T_19 = eq(_mshrs_io_req_0_valid_T_18, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_20 = and(_mshrs_io_req_0_valid_T_17, _mshrs_io_req_0_valid_T_19)
node _mshrs_io_req_0_valid_T_21 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h2))
node _mshrs_io_req_0_valid_T_22 = eq(s2_req[0].uop.mem_cmd, UInt<2>(0h3))
node _mshrs_io_req_0_valid_T_23 = or(_mshrs_io_req_0_valid_T_21, _mshrs_io_req_0_valid_T_22)
node _mshrs_io_req_0_valid_T_24 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h0))
node _mshrs_io_req_0_valid_T_25 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h10))
node _mshrs_io_req_0_valid_T_26 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h6))
node _mshrs_io_req_0_valid_T_27 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _mshrs_io_req_0_valid_T_28 = or(_mshrs_io_req_0_valid_T_24, _mshrs_io_req_0_valid_T_25)
node _mshrs_io_req_0_valid_T_29 = or(_mshrs_io_req_0_valid_T_28, _mshrs_io_req_0_valid_T_26)
node _mshrs_io_req_0_valid_T_30 = or(_mshrs_io_req_0_valid_T_29, _mshrs_io_req_0_valid_T_27)
node _mshrs_io_req_0_valid_T_31 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_32 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _mshrs_io_req_0_valid_T_33 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _mshrs_io_req_0_valid_T_34 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _mshrs_io_req_0_valid_T_35 = or(_mshrs_io_req_0_valid_T_31, _mshrs_io_req_0_valid_T_32)
node _mshrs_io_req_0_valid_T_36 = or(_mshrs_io_req_0_valid_T_35, _mshrs_io_req_0_valid_T_33)
node _mshrs_io_req_0_valid_T_37 = or(_mshrs_io_req_0_valid_T_36, _mshrs_io_req_0_valid_T_34)
node _mshrs_io_req_0_valid_T_38 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _mshrs_io_req_0_valid_T_39 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _mshrs_io_req_0_valid_T_40 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _mshrs_io_req_0_valid_T_41 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _mshrs_io_req_0_valid_T_42 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _mshrs_io_req_0_valid_T_43 = or(_mshrs_io_req_0_valid_T_38, _mshrs_io_req_0_valid_T_39)
node _mshrs_io_req_0_valid_T_44 = or(_mshrs_io_req_0_valid_T_43, _mshrs_io_req_0_valid_T_40)
node _mshrs_io_req_0_valid_T_45 = or(_mshrs_io_req_0_valid_T_44, _mshrs_io_req_0_valid_T_41)
node _mshrs_io_req_0_valid_T_46 = or(_mshrs_io_req_0_valid_T_45, _mshrs_io_req_0_valid_T_42)
node _mshrs_io_req_0_valid_T_47 = or(_mshrs_io_req_0_valid_T_37, _mshrs_io_req_0_valid_T_46)
node _mshrs_io_req_0_valid_T_48 = or(_mshrs_io_req_0_valid_T_30, _mshrs_io_req_0_valid_T_47)
node _mshrs_io_req_0_valid_T_49 = or(_mshrs_io_req_0_valid_T_23, _mshrs_io_req_0_valid_T_48)
node _mshrs_io_req_0_valid_T_50 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _mshrs_io_req_0_valid_T_51 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _mshrs_io_req_0_valid_T_52 = or(_mshrs_io_req_0_valid_T_50, _mshrs_io_req_0_valid_T_51)
node _mshrs_io_req_0_valid_T_53 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _mshrs_io_req_0_valid_T_54 = or(_mshrs_io_req_0_valid_T_52, _mshrs_io_req_0_valid_T_53)
node _mshrs_io_req_0_valid_T_55 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _mshrs_io_req_0_valid_T_56 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _mshrs_io_req_0_valid_T_57 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _mshrs_io_req_0_valid_T_58 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _mshrs_io_req_0_valid_T_59 = or(_mshrs_io_req_0_valid_T_55, _mshrs_io_req_0_valid_T_56)
node _mshrs_io_req_0_valid_T_60 = or(_mshrs_io_req_0_valid_T_59, _mshrs_io_req_0_valid_T_57)
node _mshrs_io_req_0_valid_T_61 = or(_mshrs_io_req_0_valid_T_60, _mshrs_io_req_0_valid_T_58)
node _mshrs_io_req_0_valid_T_62 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _mshrs_io_req_0_valid_T_63 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _mshrs_io_req_0_valid_T_64 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _mshrs_io_req_0_valid_T_65 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _mshrs_io_req_0_valid_T_66 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _mshrs_io_req_0_valid_T_67 = or(_mshrs_io_req_0_valid_T_62, _mshrs_io_req_0_valid_T_63)
node _mshrs_io_req_0_valid_T_68 = or(_mshrs_io_req_0_valid_T_67, _mshrs_io_req_0_valid_T_64)
node _mshrs_io_req_0_valid_T_69 = or(_mshrs_io_req_0_valid_T_68, _mshrs_io_req_0_valid_T_65)
node _mshrs_io_req_0_valid_T_70 = or(_mshrs_io_req_0_valid_T_69, _mshrs_io_req_0_valid_T_66)
node _mshrs_io_req_0_valid_T_71 = or(_mshrs_io_req_0_valid_T_61, _mshrs_io_req_0_valid_T_70)
node _mshrs_io_req_0_valid_T_72 = or(_mshrs_io_req_0_valid_T_54, _mshrs_io_req_0_valid_T_71)
node _mshrs_io_req_0_valid_T_73 = or(_mshrs_io_req_0_valid_T_49, _mshrs_io_req_0_valid_T_72)
node _mshrs_io_req_0_valid_T_74 = and(_mshrs_io_req_0_valid_T_20, _mshrs_io_req_0_valid_T_73)
connect mshrs.io.req[0].valid, _mshrs_io_req_0_valid_T_74
node _T_67 = eq(s2_type, UInt<3>(0h0))
node _T_68 = and(mshrs.io.req[0].valid, _T_67)
node _T_69 = eq(_T_68, UInt<1>(0h0))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: Replays should not need to go back into MSHRs\n at dcache.scala:758 assert(!(mshrs.io.req(w).valid && s2_type === t_replay), \"Replays should not need to go back into MSHRs\")\n") : printf_6
assert(clock, _T_69, UInt<1>(0h1), "") : assert_6
invalidate mshrs.io.req[0].bits.sdq_id
invalidate mshrs.io.req[0].bits.way_en
invalidate mshrs.io.req[0].bits.old_meta.tag
invalidate mshrs.io.req[0].bits.old_meta.coh.state
invalidate mshrs.io.req[0].bits.tag_match
invalidate mshrs.io.req[0].bits.is_hella
invalidate mshrs.io.req[0].bits.data
invalidate mshrs.io.req[0].bits.addr
invalidate mshrs.io.req[0].bits.uop.debug_tsrc
invalidate mshrs.io.req[0].bits.uop.debug_fsrc
invalidate mshrs.io.req[0].bits.uop.bp_xcpt_if
invalidate mshrs.io.req[0].bits.uop.bp_debug_if
invalidate mshrs.io.req[0].bits.uop.xcpt_ma_if
invalidate mshrs.io.req[0].bits.uop.xcpt_ae_if
invalidate mshrs.io.req[0].bits.uop.xcpt_pf_if
invalidate mshrs.io.req[0].bits.uop.fp_single
invalidate mshrs.io.req[0].bits.uop.fp_val
invalidate mshrs.io.req[0].bits.uop.frs3_en
invalidate mshrs.io.req[0].bits.uop.lrs2_rtype
invalidate mshrs.io.req[0].bits.uop.lrs1_rtype
invalidate mshrs.io.req[0].bits.uop.dst_rtype
invalidate mshrs.io.req[0].bits.uop.ldst_val
invalidate mshrs.io.req[0].bits.uop.lrs3
invalidate mshrs.io.req[0].bits.uop.lrs2
invalidate mshrs.io.req[0].bits.uop.lrs1
invalidate mshrs.io.req[0].bits.uop.ldst
invalidate mshrs.io.req[0].bits.uop.ldst_is_rs1
invalidate mshrs.io.req[0].bits.uop.flush_on_commit
invalidate mshrs.io.req[0].bits.uop.is_unique
invalidate mshrs.io.req[0].bits.uop.is_sys_pc2epc
invalidate mshrs.io.req[0].bits.uop.uses_stq
invalidate mshrs.io.req[0].bits.uop.uses_ldq
invalidate mshrs.io.req[0].bits.uop.is_amo
invalidate mshrs.io.req[0].bits.uop.is_fencei
invalidate mshrs.io.req[0].bits.uop.is_fence
invalidate mshrs.io.req[0].bits.uop.mem_signed
invalidate mshrs.io.req[0].bits.uop.mem_size
invalidate mshrs.io.req[0].bits.uop.mem_cmd
invalidate mshrs.io.req[0].bits.uop.bypassable
invalidate mshrs.io.req[0].bits.uop.exc_cause
invalidate mshrs.io.req[0].bits.uop.exception
invalidate mshrs.io.req[0].bits.uop.stale_pdst
invalidate mshrs.io.req[0].bits.uop.ppred_busy
invalidate mshrs.io.req[0].bits.uop.prs3_busy
invalidate mshrs.io.req[0].bits.uop.prs2_busy
invalidate mshrs.io.req[0].bits.uop.prs1_busy
invalidate mshrs.io.req[0].bits.uop.ppred
invalidate mshrs.io.req[0].bits.uop.prs3
invalidate mshrs.io.req[0].bits.uop.prs2
invalidate mshrs.io.req[0].bits.uop.prs1
invalidate mshrs.io.req[0].bits.uop.pdst
invalidate mshrs.io.req[0].bits.uop.rxq_idx
invalidate mshrs.io.req[0].bits.uop.stq_idx
invalidate mshrs.io.req[0].bits.uop.ldq_idx
invalidate mshrs.io.req[0].bits.uop.rob_idx
invalidate mshrs.io.req[0].bits.uop.csr_addr
invalidate mshrs.io.req[0].bits.uop.imm_packed
invalidate mshrs.io.req[0].bits.uop.taken
invalidate mshrs.io.req[0].bits.uop.pc_lob
invalidate mshrs.io.req[0].bits.uop.edge_inst
invalidate mshrs.io.req[0].bits.uop.ftq_idx
invalidate mshrs.io.req[0].bits.uop.br_tag
invalidate mshrs.io.req[0].bits.uop.br_mask
invalidate mshrs.io.req[0].bits.uop.is_sfb
invalidate mshrs.io.req[0].bits.uop.is_jal
invalidate mshrs.io.req[0].bits.uop.is_jalr
invalidate mshrs.io.req[0].bits.uop.is_br
invalidate mshrs.io.req[0].bits.uop.iw_p2_poisoned
invalidate mshrs.io.req[0].bits.uop.iw_p1_poisoned
invalidate mshrs.io.req[0].bits.uop.iw_state
invalidate mshrs.io.req[0].bits.uop.ctrl.is_std
invalidate mshrs.io.req[0].bits.uop.ctrl.is_sta
invalidate mshrs.io.req[0].bits.uop.ctrl.is_load
invalidate mshrs.io.req[0].bits.uop.ctrl.csr_cmd
invalidate mshrs.io.req[0].bits.uop.ctrl.fcn_dw
invalidate mshrs.io.req[0].bits.uop.ctrl.op_fcn
invalidate mshrs.io.req[0].bits.uop.ctrl.imm_sel
invalidate mshrs.io.req[0].bits.uop.ctrl.op2_sel
invalidate mshrs.io.req[0].bits.uop.ctrl.op1_sel
invalidate mshrs.io.req[0].bits.uop.ctrl.br_type
invalidate mshrs.io.req[0].bits.uop.fu_code
invalidate mshrs.io.req[0].bits.uop.iq_type
invalidate mshrs.io.req[0].bits.uop.debug_pc
invalidate mshrs.io.req[0].bits.uop.is_rvc
invalidate mshrs.io.req[0].bits.uop.debug_inst
invalidate mshrs.io.req[0].bits.uop.inst
invalidate mshrs.io.req[0].bits.uop.uopc
connect mshrs.io.req[0].bits.uop.debug_tsrc, s2_req[0].uop.debug_tsrc
connect mshrs.io.req[0].bits.uop.debug_fsrc, s2_req[0].uop.debug_fsrc
connect mshrs.io.req[0].bits.uop.bp_xcpt_if, s2_req[0].uop.bp_xcpt_if
connect mshrs.io.req[0].bits.uop.bp_debug_if, s2_req[0].uop.bp_debug_if
connect mshrs.io.req[0].bits.uop.xcpt_ma_if, s2_req[0].uop.xcpt_ma_if
connect mshrs.io.req[0].bits.uop.xcpt_ae_if, s2_req[0].uop.xcpt_ae_if
connect mshrs.io.req[0].bits.uop.xcpt_pf_if, s2_req[0].uop.xcpt_pf_if
connect mshrs.io.req[0].bits.uop.fp_single, s2_req[0].uop.fp_single
connect mshrs.io.req[0].bits.uop.fp_val, s2_req[0].uop.fp_val
connect mshrs.io.req[0].bits.uop.frs3_en, s2_req[0].uop.frs3_en
connect mshrs.io.req[0].bits.uop.lrs2_rtype, s2_req[0].uop.lrs2_rtype
connect mshrs.io.req[0].bits.uop.lrs1_rtype, s2_req[0].uop.lrs1_rtype
connect mshrs.io.req[0].bits.uop.dst_rtype, s2_req[0].uop.dst_rtype
connect mshrs.io.req[0].bits.uop.ldst_val, s2_req[0].uop.ldst_val
connect mshrs.io.req[0].bits.uop.lrs3, s2_req[0].uop.lrs3
connect mshrs.io.req[0].bits.uop.lrs2, s2_req[0].uop.lrs2
connect mshrs.io.req[0].bits.uop.lrs1, s2_req[0].uop.lrs1
connect mshrs.io.req[0].bits.uop.ldst, s2_req[0].uop.ldst
connect mshrs.io.req[0].bits.uop.ldst_is_rs1, s2_req[0].uop.ldst_is_rs1
connect mshrs.io.req[0].bits.uop.flush_on_commit, s2_req[0].uop.flush_on_commit
connect mshrs.io.req[0].bits.uop.is_unique, s2_req[0].uop.is_unique
connect mshrs.io.req[0].bits.uop.is_sys_pc2epc, s2_req[0].uop.is_sys_pc2epc
connect mshrs.io.req[0].bits.uop.uses_stq, s2_req[0].uop.uses_stq
connect mshrs.io.req[0].bits.uop.uses_ldq, s2_req[0].uop.uses_ldq
connect mshrs.io.req[0].bits.uop.is_amo, s2_req[0].uop.is_amo
connect mshrs.io.req[0].bits.uop.is_fencei, s2_req[0].uop.is_fencei
connect mshrs.io.req[0].bits.uop.is_fence, s2_req[0].uop.is_fence
connect mshrs.io.req[0].bits.uop.mem_signed, s2_req[0].uop.mem_signed
connect mshrs.io.req[0].bits.uop.mem_size, s2_req[0].uop.mem_size
connect mshrs.io.req[0].bits.uop.mem_cmd, s2_req[0].uop.mem_cmd
connect mshrs.io.req[0].bits.uop.bypassable, s2_req[0].uop.bypassable
connect mshrs.io.req[0].bits.uop.exc_cause, s2_req[0].uop.exc_cause
connect mshrs.io.req[0].bits.uop.exception, s2_req[0].uop.exception
connect mshrs.io.req[0].bits.uop.stale_pdst, s2_req[0].uop.stale_pdst
connect mshrs.io.req[0].bits.uop.ppred_busy, s2_req[0].uop.ppred_busy
connect mshrs.io.req[0].bits.uop.prs3_busy, s2_req[0].uop.prs3_busy
connect mshrs.io.req[0].bits.uop.prs2_busy, s2_req[0].uop.prs2_busy
connect mshrs.io.req[0].bits.uop.prs1_busy, s2_req[0].uop.prs1_busy
connect mshrs.io.req[0].bits.uop.ppred, s2_req[0].uop.ppred
connect mshrs.io.req[0].bits.uop.prs3, s2_req[0].uop.prs3
connect mshrs.io.req[0].bits.uop.prs2, s2_req[0].uop.prs2
connect mshrs.io.req[0].bits.uop.prs1, s2_req[0].uop.prs1
connect mshrs.io.req[0].bits.uop.pdst, s2_req[0].uop.pdst
connect mshrs.io.req[0].bits.uop.rxq_idx, s2_req[0].uop.rxq_idx
connect mshrs.io.req[0].bits.uop.stq_idx, s2_req[0].uop.stq_idx
connect mshrs.io.req[0].bits.uop.ldq_idx, s2_req[0].uop.ldq_idx
connect mshrs.io.req[0].bits.uop.rob_idx, s2_req[0].uop.rob_idx
connect mshrs.io.req[0].bits.uop.csr_addr, s2_req[0].uop.csr_addr
connect mshrs.io.req[0].bits.uop.imm_packed, s2_req[0].uop.imm_packed
connect mshrs.io.req[0].bits.uop.taken, s2_req[0].uop.taken
connect mshrs.io.req[0].bits.uop.pc_lob, s2_req[0].uop.pc_lob
connect mshrs.io.req[0].bits.uop.edge_inst, s2_req[0].uop.edge_inst
connect mshrs.io.req[0].bits.uop.ftq_idx, s2_req[0].uop.ftq_idx
connect mshrs.io.req[0].bits.uop.br_tag, s2_req[0].uop.br_tag
connect mshrs.io.req[0].bits.uop.br_mask, s2_req[0].uop.br_mask
connect mshrs.io.req[0].bits.uop.is_sfb, s2_req[0].uop.is_sfb
connect mshrs.io.req[0].bits.uop.is_jal, s2_req[0].uop.is_jal
connect mshrs.io.req[0].bits.uop.is_jalr, s2_req[0].uop.is_jalr
connect mshrs.io.req[0].bits.uop.is_br, s2_req[0].uop.is_br
connect mshrs.io.req[0].bits.uop.iw_p2_poisoned, s2_req[0].uop.iw_p2_poisoned
connect mshrs.io.req[0].bits.uop.iw_p1_poisoned, s2_req[0].uop.iw_p1_poisoned
connect mshrs.io.req[0].bits.uop.iw_state, s2_req[0].uop.iw_state
connect mshrs.io.req[0].bits.uop.ctrl.is_std, s2_req[0].uop.ctrl.is_std
connect mshrs.io.req[0].bits.uop.ctrl.is_sta, s2_req[0].uop.ctrl.is_sta
connect mshrs.io.req[0].bits.uop.ctrl.is_load, s2_req[0].uop.ctrl.is_load
connect mshrs.io.req[0].bits.uop.ctrl.csr_cmd, s2_req[0].uop.ctrl.csr_cmd
connect mshrs.io.req[0].bits.uop.ctrl.fcn_dw, s2_req[0].uop.ctrl.fcn_dw
connect mshrs.io.req[0].bits.uop.ctrl.op_fcn, s2_req[0].uop.ctrl.op_fcn
connect mshrs.io.req[0].bits.uop.ctrl.imm_sel, s2_req[0].uop.ctrl.imm_sel
connect mshrs.io.req[0].bits.uop.ctrl.op2_sel, s2_req[0].uop.ctrl.op2_sel
connect mshrs.io.req[0].bits.uop.ctrl.op1_sel, s2_req[0].uop.ctrl.op1_sel
connect mshrs.io.req[0].bits.uop.ctrl.br_type, s2_req[0].uop.ctrl.br_type
connect mshrs.io.req[0].bits.uop.fu_code, s2_req[0].uop.fu_code
connect mshrs.io.req[0].bits.uop.iq_type, s2_req[0].uop.iq_type
connect mshrs.io.req[0].bits.uop.debug_pc, s2_req[0].uop.debug_pc
connect mshrs.io.req[0].bits.uop.is_rvc, s2_req[0].uop.is_rvc
connect mshrs.io.req[0].bits.uop.debug_inst, s2_req[0].uop.debug_inst
connect mshrs.io.req[0].bits.uop.inst, s2_req[0].uop.inst
connect mshrs.io.req[0].bits.uop.uopc, s2_req[0].uop.uopc
node _mshrs_io_req_0_bits_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _mshrs_io_req_0_bits_uop_br_mask_T_1 = and(s2_req[0].uop.br_mask, _mshrs_io_req_0_bits_uop_br_mask_T)
connect mshrs.io.req[0].bits.uop.br_mask, _mshrs_io_req_0_bits_uop_br_mask_T_1
connect mshrs.io.req[0].bits.addr, s2_req[0].addr
connect mshrs.io.req[0].bits.tag_match, s2_tag_match_0
wire mshrs_io_req_0_bits_old_meta_meta : { coh : { state : UInt<2>}, tag : UInt<22>}
connect mshrs_io_req_0_bits_old_meta_meta.tag, s2_repl_meta[0].tag
connect mshrs_io_req_0_bits_old_meta_meta.coh, s2_hit_state[0]
node _mshrs_io_req_0_bits_old_meta_T = mux(s2_tag_match_0, mshrs_io_req_0_bits_old_meta_meta, s2_repl_meta[0])
connect mshrs.io.req[0].bits.old_meta.tag, _mshrs_io_req_0_bits_old_meta_T.tag
connect mshrs.io.req[0].bits.old_meta.coh.state, _mshrs_io_req_0_bits_old_meta_T.coh.state
node _mshrs_io_req_0_bits_way_en_T = mux(s2_tag_match_0, s2_tag_match_way[0], s2_replaced_way_en)
connect mshrs.io.req[0].bits.way_en, _mshrs_io_req_0_bits_way_en_T
connect mshrs.io.req[0].bits.data, s2_req[0].data
connect mshrs.io.req[0].bits.is_hella, s2_req[0].is_hella
node _mshrs_io_req_is_probe_0_T = eq(s2_type, UInt<3>(0h1))
node _mshrs_io_req_is_probe_0_T_1 = and(_mshrs_io_req_is_probe_0_T, s2_valid[0])
connect mshrs.io.req_is_probe[0], _mshrs_io_req_is_probe_0_T_1
node _mshrs_io_meta_resp_valid_T = eq(s2_nack_hit[0], UInt<1>(0h0))
node _mshrs_io_meta_resp_valid_T_1 = or(_mshrs_io_meta_resp_valid_T, prober.io.mshr_wb_rdy)
connect mshrs.io.meta_resp.valid, _mshrs_io_meta_resp_valid_T_1
reg mshrs_io_meta_resp_bits_REG : { coh : { state : UInt<2>}, tag : UInt<22>}[2], clock
connect mshrs_io_meta_resp_bits_REG, meta_0.io.resp
node _mshrs_io_meta_resp_bits_T = bits(s2_tag_match_way[0], 0, 0)
node _mshrs_io_meta_resp_bits_T_1 = bits(s2_tag_match_way[0], 1, 1)
wire _mshrs_io_meta_resp_bits_WIRE : { coh : { state : UInt<2>}, tag : UInt<22>}
node _mshrs_io_meta_resp_bits_T_2 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_3 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].tag, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_4 = or(_mshrs_io_meta_resp_bits_T_2, _mshrs_io_meta_resp_bits_T_3)
wire _mshrs_io_meta_resp_bits_WIRE_1 : UInt<22>
connect _mshrs_io_meta_resp_bits_WIRE_1, _mshrs_io_meta_resp_bits_T_4
connect _mshrs_io_meta_resp_bits_WIRE.tag, _mshrs_io_meta_resp_bits_WIRE_1
wire _mshrs_io_meta_resp_bits_WIRE_2 : { state : UInt<2>}
node _mshrs_io_meta_resp_bits_T_5 = mux(_mshrs_io_meta_resp_bits_T, mshrs_io_meta_resp_bits_REG[0].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_6 = mux(_mshrs_io_meta_resp_bits_T_1, mshrs_io_meta_resp_bits_REG[1].coh.state, UInt<1>(0h0))
node _mshrs_io_meta_resp_bits_T_7 = or(_mshrs_io_meta_resp_bits_T_5, _mshrs_io_meta_resp_bits_T_6)
wire _mshrs_io_meta_resp_bits_WIRE_3 : UInt<2>
connect _mshrs_io_meta_resp_bits_WIRE_3, _mshrs_io_meta_resp_bits_T_7
connect _mshrs_io_meta_resp_bits_WIRE_2.state, _mshrs_io_meta_resp_bits_WIRE_3
connect _mshrs_io_meta_resp_bits_WIRE.coh, _mshrs_io_meta_resp_bits_WIRE_2
connect mshrs.io.meta_resp.bits.tag, _mshrs_io_meta_resp_bits_WIRE.tag
connect mshrs.io.meta_resp.bits.coh.state, _mshrs_io_meta_resp_bits_WIRE.coh.state
node _T_73 = and(mshrs.io.req[0].ready, mshrs.io.req[0].valid)
when _T_73 :
connect replace, UInt<1>(0h1)
connect nodeOut.a.bits, mshrs.io.mem_acquire.bits
connect nodeOut.a.valid, mshrs.io.mem_acquire.valid
connect mshrs.io.mem_acquire.ready, nodeOut.a.ready
node _prober_io_req_valid_T = eq(lrsc_valid, UInt<1>(0h0))
node _prober_io_req_valid_T_1 = and(nodeOut.b.valid, _prober_io_req_valid_T)
connect prober.io.req.valid, _prober_io_req_valid_T_1
node _nodeOut_b_ready_T = eq(lrsc_valid, UInt<1>(0h0))
node _nodeOut_b_ready_T_1 = and(prober.io.req.ready, _nodeOut_b_ready_T)
connect nodeOut.b.ready, _nodeOut_b_ready_T_1
connect prober.io.req.bits.corrupt, nodeOut.b.bits.corrupt
connect prober.io.req.bits.data, nodeOut.b.bits.data
connect prober.io.req.bits.mask, nodeOut.b.bits.mask
connect prober.io.req.bits.address, nodeOut.b.bits.address
connect prober.io.req.bits.source, nodeOut.b.bits.source
connect prober.io.req.bits.size, nodeOut.b.bits.size
connect prober.io.req.bits.param, nodeOut.b.bits.param
connect prober.io.req.bits.opcode, nodeOut.b.bits.opcode
connect prober.io.way_en, s2_tag_match_way[0]
connect prober.io.block_state.state, s2_hit_state[0].state
connect metaWriteArb.io.in[1], prober.io.meta_write
connect prober.io.mshr_rdy, mshrs.io.probe_rdy
node _prober_io_wb_rdy_T = neq(prober.io.meta_write.bits.idx, wb.io.idx.bits)
node _prober_io_wb_rdy_T_1 = eq(wb.io.idx.valid, UInt<1>(0h0))
node _prober_io_wb_rdy_T_2 = or(_prober_io_wb_rdy_T, _prober_io_wb_rdy_T_1)
connect prober.io.wb_rdy, _prober_io_wb_rdy_T_2
connect mshrs.io.prober_state.bits, prober.io.state.bits
connect mshrs.io.prober_state.valid, prober.io.state.valid
node _T_74 = eq(nodeOut.d.bits.source, UInt<4>(0h8))
when _T_74 :
connect nodeOut.d.ready, UInt<1>(0h1)
connect mshrs.io.mem_grant.valid, UInt<1>(0h0)
invalidate mshrs.io.mem_grant.bits.corrupt
invalidate mshrs.io.mem_grant.bits.data
invalidate mshrs.io.mem_grant.bits.denied
invalidate mshrs.io.mem_grant.bits.sink
invalidate mshrs.io.mem_grant.bits.source
invalidate mshrs.io.mem_grant.bits.size
invalidate mshrs.io.mem_grant.bits.param
invalidate mshrs.io.mem_grant.bits.opcode
else :
connect mshrs.io.mem_grant, nodeOut.d
connect dataWriteArb.io.in[1], mshrs.io.refill
connect metaWriteArb.io.in[0], mshrs.io.meta_write
connect nodeOut.e.bits, mshrs.io.mem_finish.bits
connect nodeOut.e.valid, mshrs.io.mem_finish.valid
connect mshrs.io.mem_finish.ready, nodeOut.e.ready
inst wbArb of Arbiter2_WritebackReq_1
connect wbArb.clock, clock
connect wbArb.reset, reset
connect wbArb.io.in[0], prober.io.wb_req
connect wbArb.io.in[1], mshrs.io.wb_req
connect wb.io.req, wbArb.io.out
connect wb.io.data_resp, s2_data_muxed[0]
connect mshrs.io.wb_resp, wb.io.resp
node _wb_io_mem_grant_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _wb_io_mem_grant_T_1 = eq(nodeOut.d.bits.source, UInt<4>(0h8))
node _wb_io_mem_grant_T_2 = and(_wb_io_mem_grant_T, _wb_io_mem_grant_T_1)
connect wb.io.mem_grant, _wb_io_mem_grant_T_2
inst lsu_release_arb of Arbiter2_TLBundleC_a32d64s4k3z4c_1
connect lsu_release_arb.clock, clock
connect lsu_release_arb.reset, reset
connect io.lsu.release.bits, lsu_release_arb.io.out.bits
connect io.lsu.release.valid, lsu_release_arb.io.out.valid
connect lsu_release_arb.io.out.ready, io.lsu.release.ready
connect lsu_release_arb.io.in[0], wb.io.lsu_release
connect lsu_release_arb.io.in[1], prober.io.lsu_release
node _decode_T = dshl(UInt<12>(0hfff), wb.io.release.bits.size)
node _decode_T_1 = bits(_decode_T, 11, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node opdata = bits(wb.io.release.bits.opcode, 0, 0)
node _T_75 = mux(opdata, decode, UInt<1>(0h0))
node _decode_T_3 = dshl(UInt<12>(0hfff), prober.io.rep.bits.size)
node _decode_T_4 = bits(_decode_T_3, 11, 0)
node _decode_T_5 = not(_decode_T_4)
node decode_1 = shr(_decode_T_5, 3)
node opdata_1 = bits(prober.io.rep.bits.opcode, 0, 0)
node _T_76 = mux(opdata_1, decode_1, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.c.ready)
node _readys_T = cat(prober.io.rep.valid, wb.io.release.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], wb.io.release.valid)
node _winner_T_1 = and(readys[1], prober.io.rep.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_77 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_78 = eq(winner[0], UInt<1>(0h0))
node _T_79 = or(_T_77, _T_78)
node _T_80 = eq(prefixOR_1, UInt<1>(0h0))
node _T_81 = eq(winner[1], UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
node _T_83 = and(_T_79, _T_82)
node _T_84 = asUInt(reset)
node _T_85 = eq(_T_84, UInt<1>(0h0))
when _T_85 :
node _T_86 = eq(_T_83, UInt<1>(0h0))
when _T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_7
assert(clock, _T_83, UInt<1>(0h1), "") : assert_7
node _T_87 = or(wb.io.release.valid, prober.io.rep.valid)
node _T_88 = eq(_T_87, UInt<1>(0h0))
node _T_89 = or(winner[0], winner[1])
node _T_90 = or(_T_88, _T_89)
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_8
assert(clock, _T_90, UInt<1>(0h1), "") : assert_8
node maskedBeats_0 = mux(winner[0], _T_75, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_76, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _wb_io_release_ready_T = and(nodeOut.c.ready, allowed[0])
connect wb.io.release.ready, _wb_io_release_ready_T
node _prober_io_rep_ready_T = and(nodeOut.c.ready, allowed[1])
connect prober.io.rep.ready, _prober_io_rep_ready_T
node _nodeOut_c_valid_T = or(wb.io.release.valid, prober.io.rep.valid)
node _nodeOut_c_valid_T_1 = mux(state[0], wb.io.release.valid, UInt<1>(0h0))
node _nodeOut_c_valid_T_2 = mux(state[1], prober.io.rep.valid, UInt<1>(0h0))
node _nodeOut_c_valid_T_3 = or(_nodeOut_c_valid_T_1, _nodeOut_c_valid_T_2)
wire _nodeOut_c_valid_WIRE : UInt<1>
connect _nodeOut_c_valid_WIRE, _nodeOut_c_valid_T_3
node _nodeOut_c_valid_T_4 = mux(idle, _nodeOut_c_valid_T, _nodeOut_c_valid_WIRE)
connect nodeOut.c.valid, _nodeOut_c_valid_T_4
wire _nodeOut_c_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_c_bits_T = mux(muxState[0], wb.io.release.bits.corrupt, UInt<1>(0h0))
node _nodeOut_c_bits_T_1 = mux(muxState[1], prober.io.rep.bits.corrupt, UInt<1>(0h0))
node _nodeOut_c_bits_T_2 = or(_nodeOut_c_bits_T, _nodeOut_c_bits_T_1)
wire _nodeOut_c_bits_WIRE_1 : UInt<1>
connect _nodeOut_c_bits_WIRE_1, _nodeOut_c_bits_T_2
connect _nodeOut_c_bits_WIRE.corrupt, _nodeOut_c_bits_WIRE_1
node _nodeOut_c_bits_T_3 = mux(muxState[0], wb.io.release.bits.data, UInt<1>(0h0))
node _nodeOut_c_bits_T_4 = mux(muxState[1], prober.io.rep.bits.data, UInt<1>(0h0))
node _nodeOut_c_bits_T_5 = or(_nodeOut_c_bits_T_3, _nodeOut_c_bits_T_4)
wire _nodeOut_c_bits_WIRE_2 : UInt<64>
connect _nodeOut_c_bits_WIRE_2, _nodeOut_c_bits_T_5
connect _nodeOut_c_bits_WIRE.data, _nodeOut_c_bits_WIRE_2
wire _nodeOut_c_bits_WIRE_3 : { }
connect _nodeOut_c_bits_WIRE.echo, _nodeOut_c_bits_WIRE_3
wire _nodeOut_c_bits_WIRE_4 : { }
connect _nodeOut_c_bits_WIRE.user, _nodeOut_c_bits_WIRE_4
node _nodeOut_c_bits_T_6 = mux(muxState[0], wb.io.release.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_T_7 = mux(muxState[1], prober.io.rep.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_T_8 = or(_nodeOut_c_bits_T_6, _nodeOut_c_bits_T_7)
wire _nodeOut_c_bits_WIRE_5 : UInt<32>
connect _nodeOut_c_bits_WIRE_5, _nodeOut_c_bits_T_8
connect _nodeOut_c_bits_WIRE.address, _nodeOut_c_bits_WIRE_5
node _nodeOut_c_bits_T_9 = mux(muxState[0], wb.io.release.bits.source, UInt<1>(0h0))
node _nodeOut_c_bits_T_10 = mux(muxState[1], prober.io.rep.bits.source, UInt<1>(0h0))
node _nodeOut_c_bits_T_11 = or(_nodeOut_c_bits_T_9, _nodeOut_c_bits_T_10)
wire _nodeOut_c_bits_WIRE_6 : UInt<4>
connect _nodeOut_c_bits_WIRE_6, _nodeOut_c_bits_T_11
connect _nodeOut_c_bits_WIRE.source, _nodeOut_c_bits_WIRE_6
node _nodeOut_c_bits_T_12 = mux(muxState[0], wb.io.release.bits.size, UInt<1>(0h0))
node _nodeOut_c_bits_T_13 = mux(muxState[1], prober.io.rep.bits.size, UInt<1>(0h0))
node _nodeOut_c_bits_T_14 = or(_nodeOut_c_bits_T_12, _nodeOut_c_bits_T_13)
wire _nodeOut_c_bits_WIRE_7 : UInt<4>
connect _nodeOut_c_bits_WIRE_7, _nodeOut_c_bits_T_14
connect _nodeOut_c_bits_WIRE.size, _nodeOut_c_bits_WIRE_7
node _nodeOut_c_bits_T_15 = mux(muxState[0], wb.io.release.bits.param, UInt<1>(0h0))
node _nodeOut_c_bits_T_16 = mux(muxState[1], prober.io.rep.bits.param, UInt<1>(0h0))
node _nodeOut_c_bits_T_17 = or(_nodeOut_c_bits_T_15, _nodeOut_c_bits_T_16)
wire _nodeOut_c_bits_WIRE_8 : UInt<3>
connect _nodeOut_c_bits_WIRE_8, _nodeOut_c_bits_T_17
connect _nodeOut_c_bits_WIRE.param, _nodeOut_c_bits_WIRE_8
node _nodeOut_c_bits_T_18 = mux(muxState[0], wb.io.release.bits.opcode, UInt<1>(0h0))
node _nodeOut_c_bits_T_19 = mux(muxState[1], prober.io.rep.bits.opcode, UInt<1>(0h0))
node _nodeOut_c_bits_T_20 = or(_nodeOut_c_bits_T_18, _nodeOut_c_bits_T_19)
wire _nodeOut_c_bits_WIRE_9 : UInt<3>
connect _nodeOut_c_bits_WIRE_9, _nodeOut_c_bits_T_20
connect _nodeOut_c_bits_WIRE.opcode, _nodeOut_c_bits_WIRE_9
connect nodeOut.c.bits.corrupt, _nodeOut_c_bits_WIRE.corrupt
connect nodeOut.c.bits.data, _nodeOut_c_bits_WIRE.data
connect nodeOut.c.bits.address, _nodeOut_c_bits_WIRE.address
connect nodeOut.c.bits.source, _nodeOut_c_bits_WIRE.source
connect nodeOut.c.bits.size, _nodeOut_c_bits_WIRE.size
connect nodeOut.c.bits.param, _nodeOut_c_bits_WIRE.param
connect nodeOut.c.bits.opcode, _nodeOut_c_bits_WIRE.opcode
node _io_lsu_perf_release_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _io_lsu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.c.bits.size)
node _io_lsu_perf_release_beats1_decode_T_1 = bits(_io_lsu_perf_release_beats1_decode_T, 11, 0)
node _io_lsu_perf_release_beats1_decode_T_2 = not(_io_lsu_perf_release_beats1_decode_T_1)
node io_lsu_perf_release_beats1_decode = shr(_io_lsu_perf_release_beats1_decode_T_2, 3)
node io_lsu_perf_release_beats1_opdata = bits(nodeOut.c.bits.opcode, 0, 0)
node io_lsu_perf_release_beats1 = mux(io_lsu_perf_release_beats1_opdata, io_lsu_perf_release_beats1_decode, UInt<1>(0h0))
regreset io_lsu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_lsu_perf_release_counter1_T = sub(io_lsu_perf_release_counter, UInt<1>(0h1))
node io_lsu_perf_release_counter1 = tail(_io_lsu_perf_release_counter1_T, 1)
node io_lsu_perf_release_first = eq(io_lsu_perf_release_counter, UInt<1>(0h0))
node _io_lsu_perf_release_last_T = eq(io_lsu_perf_release_counter, UInt<1>(0h1))
node _io_lsu_perf_release_last_T_1 = eq(io_lsu_perf_release_beats1, UInt<1>(0h0))
node io_lsu_perf_release_last = or(_io_lsu_perf_release_last_T, _io_lsu_perf_release_last_T_1)
node io_lsu_perf_release_done = and(io_lsu_perf_release_last, _io_lsu_perf_release_T)
node _io_lsu_perf_release_count_T = not(io_lsu_perf_release_counter1)
node io_lsu_perf_release_count = and(io_lsu_perf_release_beats1, _io_lsu_perf_release_count_T)
when _io_lsu_perf_release_T :
node _io_lsu_perf_release_counter_T = mux(io_lsu_perf_release_first, io_lsu_perf_release_beats1, io_lsu_perf_release_counter1)
connect io_lsu_perf_release_counter, _io_lsu_perf_release_counter_T
connect io.lsu.perf.release, io_lsu_perf_release_done
node _io_lsu_perf_acquire_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _io_lsu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.a.bits.size)
node _io_lsu_perf_acquire_beats1_decode_T_1 = bits(_io_lsu_perf_acquire_beats1_decode_T, 11, 0)
node _io_lsu_perf_acquire_beats1_decode_T_2 = not(_io_lsu_perf_acquire_beats1_decode_T_1)
node io_lsu_perf_acquire_beats1_decode = shr(_io_lsu_perf_acquire_beats1_decode_T_2, 3)
node _io_lsu_perf_acquire_beats1_opdata_T = bits(nodeOut.a.bits.opcode, 2, 2)
node io_lsu_perf_acquire_beats1_opdata = eq(_io_lsu_perf_acquire_beats1_opdata_T, UInt<1>(0h0))
node io_lsu_perf_acquire_beats1 = mux(io_lsu_perf_acquire_beats1_opdata, io_lsu_perf_acquire_beats1_decode, UInt<1>(0h0))
regreset io_lsu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_lsu_perf_acquire_counter1_T = sub(io_lsu_perf_acquire_counter, UInt<1>(0h1))
node io_lsu_perf_acquire_counter1 = tail(_io_lsu_perf_acquire_counter1_T, 1)
node io_lsu_perf_acquire_first = eq(io_lsu_perf_acquire_counter, UInt<1>(0h0))
node _io_lsu_perf_acquire_last_T = eq(io_lsu_perf_acquire_counter, UInt<1>(0h1))
node _io_lsu_perf_acquire_last_T_1 = eq(io_lsu_perf_acquire_beats1, UInt<1>(0h0))
node io_lsu_perf_acquire_last = or(_io_lsu_perf_acquire_last_T, _io_lsu_perf_acquire_last_T_1)
node io_lsu_perf_acquire_done = and(io_lsu_perf_acquire_last, _io_lsu_perf_acquire_T)
node _io_lsu_perf_acquire_count_T = not(io_lsu_perf_acquire_counter1)
node io_lsu_perf_acquire_count = and(io_lsu_perf_acquire_beats1, _io_lsu_perf_acquire_count_T)
when _io_lsu_perf_acquire_T :
node _io_lsu_perf_acquire_counter_T = mux(io_lsu_perf_acquire_first, io_lsu_perf_acquire_beats1, io_lsu_perf_acquire_counter1)
connect io_lsu_perf_acquire_counter, _io_lsu_perf_acquire_counter_T
connect io.lsu.perf.acquire, io_lsu_perf_acquire_done
node _s2_data_word_prebypass_T = cat(s2_word_idx[0], UInt<6>(0h0))
node _s2_data_word_prebypass_T_1 = dshr(s2_data_muxed[0], _s2_data_word_prebypass_T)
wire s2_data_word_prebypass : UInt<64>[1]
connect s2_data_word_prebypass[0], _s2_data_word_prebypass_T_1
wire s2_data_word : UInt[1]
node _T_94 = and(s2_sc, UInt<1>(0h1))
wire size : UInt<2>
connect size, s2_req[0].uop.mem_size
node size_dat_padded = pad(s2_data_word[0], 64)
wire cache_resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1]
node _cache_resp_0_valid_T = and(s2_valid[0], s2_send_resp[0])
connect cache_resp[0].valid, _cache_resp_0_valid_T
connect cache_resp[0].bits.uop, s2_req[0].uop
node _cache_resp_0_bits_data_shifted_T = bits(s2_req[0].addr, 2, 2)
node _cache_resp_0_bits_data_shifted_T_1 = bits(s2_data_word[0], 63, 32)
node _cache_resp_0_bits_data_shifted_T_2 = bits(s2_data_word[0], 31, 0)
node cache_resp_0_bits_data_shifted = mux(_cache_resp_0_bits_data_shifted_T, _cache_resp_0_bits_data_shifted_T_1, _cache_resp_0_bits_data_shifted_T_2)
node cache_resp_0_bits_data_doZero = and(UInt<1>(0h0), _T_94)
node cache_resp_0_bits_data_zeroed = mux(cache_resp_0_bits_data_doZero, UInt<1>(0h0), cache_resp_0_bits_data_shifted)
node _cache_resp_0_bits_data_T = eq(size, UInt<2>(0h2))
node _cache_resp_0_bits_data_T_1 = or(_cache_resp_0_bits_data_T, cache_resp_0_bits_data_doZero)
node _cache_resp_0_bits_data_T_2 = bits(cache_resp_0_bits_data_zeroed, 31, 31)
node _cache_resp_0_bits_data_T_3 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_2)
node _cache_resp_0_bits_data_T_4 = mux(_cache_resp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _cache_resp_0_bits_data_T_5 = bits(s2_data_word[0], 63, 32)
node _cache_resp_0_bits_data_T_6 = mux(_cache_resp_0_bits_data_T_1, _cache_resp_0_bits_data_T_4, _cache_resp_0_bits_data_T_5)
node _cache_resp_0_bits_data_T_7 = cat(_cache_resp_0_bits_data_T_6, cache_resp_0_bits_data_zeroed)
node _cache_resp_0_bits_data_shifted_T_3 = bits(s2_req[0].addr, 1, 1)
node _cache_resp_0_bits_data_shifted_T_4 = bits(_cache_resp_0_bits_data_T_7, 31, 16)
node _cache_resp_0_bits_data_shifted_T_5 = bits(_cache_resp_0_bits_data_T_7, 15, 0)
node cache_resp_0_bits_data_shifted_1 = mux(_cache_resp_0_bits_data_shifted_T_3, _cache_resp_0_bits_data_shifted_T_4, _cache_resp_0_bits_data_shifted_T_5)
node cache_resp_0_bits_data_doZero_1 = and(UInt<1>(0h0), _T_94)
node cache_resp_0_bits_data_zeroed_1 = mux(cache_resp_0_bits_data_doZero_1, UInt<1>(0h0), cache_resp_0_bits_data_shifted_1)
node _cache_resp_0_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _cache_resp_0_bits_data_T_9 = or(_cache_resp_0_bits_data_T_8, cache_resp_0_bits_data_doZero_1)
node _cache_resp_0_bits_data_T_10 = bits(cache_resp_0_bits_data_zeroed_1, 15, 15)
node _cache_resp_0_bits_data_T_11 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_10)
node _cache_resp_0_bits_data_T_12 = mux(_cache_resp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _cache_resp_0_bits_data_T_13 = bits(_cache_resp_0_bits_data_T_7, 63, 16)
node _cache_resp_0_bits_data_T_14 = mux(_cache_resp_0_bits_data_T_9, _cache_resp_0_bits_data_T_12, _cache_resp_0_bits_data_T_13)
node _cache_resp_0_bits_data_T_15 = cat(_cache_resp_0_bits_data_T_14, cache_resp_0_bits_data_zeroed_1)
node _cache_resp_0_bits_data_shifted_T_6 = bits(s2_req[0].addr, 0, 0)
node _cache_resp_0_bits_data_shifted_T_7 = bits(_cache_resp_0_bits_data_T_15, 15, 8)
node _cache_resp_0_bits_data_shifted_T_8 = bits(_cache_resp_0_bits_data_T_15, 7, 0)
node cache_resp_0_bits_data_shifted_2 = mux(_cache_resp_0_bits_data_shifted_T_6, _cache_resp_0_bits_data_shifted_T_7, _cache_resp_0_bits_data_shifted_T_8)
node cache_resp_0_bits_data_doZero_2 = and(UInt<1>(0h1), _T_94)
node cache_resp_0_bits_data_zeroed_2 = mux(cache_resp_0_bits_data_doZero_2, UInt<1>(0h0), cache_resp_0_bits_data_shifted_2)
node _cache_resp_0_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _cache_resp_0_bits_data_T_17 = or(_cache_resp_0_bits_data_T_16, cache_resp_0_bits_data_doZero_2)
node _cache_resp_0_bits_data_T_18 = bits(cache_resp_0_bits_data_zeroed_2, 7, 7)
node _cache_resp_0_bits_data_T_19 = and(s2_req[0].uop.mem_signed, _cache_resp_0_bits_data_T_18)
node _cache_resp_0_bits_data_T_20 = mux(_cache_resp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _cache_resp_0_bits_data_T_21 = bits(_cache_resp_0_bits_data_T_15, 63, 8)
node _cache_resp_0_bits_data_T_22 = mux(_cache_resp_0_bits_data_T_17, _cache_resp_0_bits_data_T_20, _cache_resp_0_bits_data_T_21)
node _cache_resp_0_bits_data_T_23 = cat(_cache_resp_0_bits_data_T_22, cache_resp_0_bits_data_zeroed_2)
node _cache_resp_0_bits_data_T_24 = or(_cache_resp_0_bits_data_T_23, s2_sc_fail)
connect cache_resp[0].bits.data, _cache_resp_0_bits_data_T_24
connect cache_resp[0].bits.is_hella, s2_req[0].is_hella
wire uncache_resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}
connect uncache_resp.bits, mshrs.io.resp.bits
connect uncache_resp.valid, mshrs.io.resp.valid
node _mshrs_io_resp_ready_T = eq(cache_resp[0].valid, UInt<1>(0h0))
connect mshrs.io.resp.ready, _mshrs_io_resp_ready_T
wire resp : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}[1]
connect resp, cache_resp
node _uncache_respond_T = eq(cache_resp[0].valid, UInt<1>(0h0))
node _uncache_respond_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node uncache_respond = and(_uncache_respond_T, _uncache_respond_T_1)
when uncache_respond :
connect resp[0], uncache_resp
node _T_95 = or(UInt<1>(0h0), uncache_respond)
node _io_lsu_resp_0_valid_T = and(io.lsu.exception, resp[0].bits.uop.uses_ldq)
node _io_lsu_resp_0_valid_T_1 = eq(_io_lsu_resp_0_valid_T, UInt<1>(0h0))
node _io_lsu_resp_0_valid_T_2 = and(resp[0].valid, _io_lsu_resp_0_valid_T_1)
node _io_lsu_resp_0_valid_T_3 = and(io.lsu.brupdate.b1.mispredict_mask, resp[0].bits.uop.br_mask)
node _io_lsu_resp_0_valid_T_4 = neq(_io_lsu_resp_0_valid_T_3, UInt<1>(0h0))
node _io_lsu_resp_0_valid_T_5 = eq(_io_lsu_resp_0_valid_T_4, UInt<1>(0h0))
node _io_lsu_resp_0_valid_T_6 = and(_io_lsu_resp_0_valid_T_2, _io_lsu_resp_0_valid_T_5)
connect io.lsu.resp[0].valid, _io_lsu_resp_0_valid_T_6
wire io_lsu_resp_0_bits_out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}
connect io_lsu_resp_0_bits_out, resp[0].bits
node _io_lsu_resp_0_bits_out_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _io_lsu_resp_0_bits_out_uop_br_mask_T_1 = and(resp[0].bits.uop.br_mask, _io_lsu_resp_0_bits_out_uop_br_mask_T)
connect io_lsu_resp_0_bits_out.uop.br_mask, _io_lsu_resp_0_bits_out_uop_br_mask_T_1
connect io.lsu.resp[0].bits, io_lsu_resp_0_bits_out
node _io_lsu_nack_0_valid_T = and(s2_valid[0], s2_send_nack[0])
node _io_lsu_nack_0_valid_T_1 = and(io.lsu.exception, s2_req[0].uop.uses_ldq)
node _io_lsu_nack_0_valid_T_2 = eq(_io_lsu_nack_0_valid_T_1, UInt<1>(0h0))
node _io_lsu_nack_0_valid_T_3 = and(_io_lsu_nack_0_valid_T, _io_lsu_nack_0_valid_T_2)
node _io_lsu_nack_0_valid_T_4 = and(io.lsu.brupdate.b1.mispredict_mask, s2_req[0].uop.br_mask)
node _io_lsu_nack_0_valid_T_5 = neq(_io_lsu_nack_0_valid_T_4, UInt<1>(0h0))
node _io_lsu_nack_0_valid_T_6 = eq(_io_lsu_nack_0_valid_T_5, UInt<1>(0h0))
node _io_lsu_nack_0_valid_T_7 = and(_io_lsu_nack_0_valid_T_3, _io_lsu_nack_0_valid_T_6)
connect io.lsu.nack[0].valid, _io_lsu_nack_0_valid_T_7
wire io_lsu_nack_0_bits_out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}
connect io_lsu_nack_0_bits_out, s2_req[0]
node _io_lsu_nack_0_bits_out_uop_br_mask_T = not(io.lsu.brupdate.b1.resolve_mask)
node _io_lsu_nack_0_bits_out_uop_br_mask_T_1 = and(s2_req[0].uop.br_mask, _io_lsu_nack_0_bits_out_uop_br_mask_T)
connect io_lsu_nack_0_bits_out.uop.br_mask, _io_lsu_nack_0_bits_out_uop_br_mask_T_1
connect io.lsu.nack[0].bits, io_lsu_nack_0_bits_out
node _T_96 = neq(s2_type, UInt<3>(0h4))
node _T_97 = and(io.lsu.nack[0].valid, _T_96)
node _T_98 = eq(_T_97, UInt<1>(0h0))
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at dcache.scala:866 assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))\n") : printf_9
assert(clock, _T_98, UInt<1>(0h1), "") : assert_9
reg s3_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s3_req, s2_req[0]
node _s3_valid_T = and(s2_valid[0], s2_hit[0])
node _s3_valid_T_1 = eq(s2_req[0].uop.mem_cmd, UInt<1>(0h1))
node _s3_valid_T_2 = eq(s2_req[0].uop.mem_cmd, UInt<5>(0h11))
node _s3_valid_T_3 = or(_s3_valid_T_1, _s3_valid_T_2)
node _s3_valid_T_4 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h7))
node _s3_valid_T_5 = or(_s3_valid_T_3, _s3_valid_T_4)
node _s3_valid_T_6 = eq(s2_req[0].uop.mem_cmd, UInt<3>(0h4))
node _s3_valid_T_7 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h9))
node _s3_valid_T_8 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0ha))
node _s3_valid_T_9 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hb))
node _s3_valid_T_10 = or(_s3_valid_T_6, _s3_valid_T_7)
node _s3_valid_T_11 = or(_s3_valid_T_10, _s3_valid_T_8)
node _s3_valid_T_12 = or(_s3_valid_T_11, _s3_valid_T_9)
node _s3_valid_T_13 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0h8))
node _s3_valid_T_14 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hc))
node _s3_valid_T_15 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hd))
node _s3_valid_T_16 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0he))
node _s3_valid_T_17 = eq(s2_req[0].uop.mem_cmd, UInt<4>(0hf))
node _s3_valid_T_18 = or(_s3_valid_T_13, _s3_valid_T_14)
node _s3_valid_T_19 = or(_s3_valid_T_18, _s3_valid_T_15)
node _s3_valid_T_20 = or(_s3_valid_T_19, _s3_valid_T_16)
node _s3_valid_T_21 = or(_s3_valid_T_20, _s3_valid_T_17)
node _s3_valid_T_22 = or(_s3_valid_T_12, _s3_valid_T_21)
node _s3_valid_T_23 = or(_s3_valid_T_5, _s3_valid_T_22)
node _s3_valid_T_24 = and(_s3_valid_T, _s3_valid_T_23)
node _s3_valid_T_25 = eq(s2_sc_fail, UInt<1>(0h0))
node _s3_valid_T_26 = and(_s3_valid_T_24, _s3_valid_T_25)
node _s3_valid_T_27 = and(s2_send_nack[0], s2_nack[0])
node _s3_valid_T_28 = eq(_s3_valid_T_27, UInt<1>(0h0))
node _s3_valid_T_29 = and(_s3_valid_T_26, _s3_valid_T_28)
reg s3_valid : UInt<1>, clock
connect s3_valid, _s3_valid_T_29
reg s4_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s4_req, s3_req
reg s4_valid : UInt<1>, clock
connect s4_valid, s3_valid
reg s5_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}, clock
connect s5_req, s4_req
reg s5_valid : UInt<1>, clock
connect s5_valid, s4_valid
node _s3_bypass_T = shr(s2_req[0].addr, 3)
node _s3_bypass_T_1 = shr(s3_req.addr, 3)
node _s3_bypass_T_2 = eq(_s3_bypass_T, _s3_bypass_T_1)
node _s3_bypass_T_3 = and(s3_valid, _s3_bypass_T_2)
wire s3_bypass : UInt<1>[1]
connect s3_bypass[0], _s3_bypass_T_3
node _s4_bypass_T = shr(s2_req[0].addr, 3)
node _s4_bypass_T_1 = shr(s4_req.addr, 3)
node _s4_bypass_T_2 = eq(_s4_bypass_T, _s4_bypass_T_1)
node _s4_bypass_T_3 = and(s4_valid, _s4_bypass_T_2)
wire s4_bypass : UInt<1>[1]
connect s4_bypass[0], _s4_bypass_T_3
node _s5_bypass_T = shr(s2_req[0].addr, 3)
node _s5_bypass_T_1 = shr(s5_req.addr, 3)
node _s5_bypass_T_2 = eq(_s5_bypass_T, _s5_bypass_T_1)
node _s5_bypass_T_3 = and(s5_valid, _s5_bypass_T_2)
wire s5_bypass : UInt<1>[1]
connect s5_bypass[0], _s5_bypass_T_3
node _s2_data_word_0_T = mux(s5_bypass[0], s5_req.data, s2_data_word_prebypass[0])
node _s2_data_word_0_T_1 = mux(s4_bypass[0], s4_req.data, _s2_data_word_0_T)
node _s2_data_word_0_T_2 = mux(s3_bypass[0], s3_req.data, _s2_data_word_0_T_1)
connect s2_data_word[0], _s2_data_word_0_T_2
inst amoalu of AMOALU_1
connect amoalu.clock, clock
connect amoalu.reset, reset
wire amoalu_io_mask_size : UInt<2>
connect amoalu_io_mask_size, s2_req[0].uop.mem_size
node _amoalu_io_mask_upper_T = bits(s2_req[0].addr, 0, 0)
node _amoalu_io_mask_upper_T_1 = mux(_amoalu_io_mask_upper_T, UInt<1>(0h1), UInt<1>(0h0))
node _amoalu_io_mask_upper_T_2 = geq(amoalu_io_mask_size, UInt<1>(0h1))
node _amoalu_io_mask_upper_T_3 = mux(_amoalu_io_mask_upper_T_2, UInt<1>(0h1), UInt<1>(0h0))
node amoalu_io_mask_upper = or(_amoalu_io_mask_upper_T_1, _amoalu_io_mask_upper_T_3)
node _amoalu_io_mask_lower_T = bits(s2_req[0].addr, 0, 0)
node amoalu_io_mask_lower = mux(_amoalu_io_mask_lower_T, UInt<1>(0h0), UInt<1>(0h1))
node _amoalu_io_mask_T = cat(amoalu_io_mask_upper, amoalu_io_mask_lower)
node _amoalu_io_mask_upper_T_4 = bits(s2_req[0].addr, 1, 1)
node _amoalu_io_mask_upper_T_5 = mux(_amoalu_io_mask_upper_T_4, _amoalu_io_mask_T, UInt<1>(0h0))
node _amoalu_io_mask_upper_T_6 = geq(amoalu_io_mask_size, UInt<2>(0h2))
node _amoalu_io_mask_upper_T_7 = mux(_amoalu_io_mask_upper_T_6, UInt<2>(0h3), UInt<1>(0h0))
node amoalu_io_mask_upper_1 = or(_amoalu_io_mask_upper_T_5, _amoalu_io_mask_upper_T_7)
node _amoalu_io_mask_lower_T_1 = bits(s2_req[0].addr, 1, 1)
node amoalu_io_mask_lower_1 = mux(_amoalu_io_mask_lower_T_1, UInt<1>(0h0), _amoalu_io_mask_T)
node _amoalu_io_mask_T_1 = cat(amoalu_io_mask_upper_1, amoalu_io_mask_lower_1)
node _amoalu_io_mask_upper_T_8 = bits(s2_req[0].addr, 2, 2)
node _amoalu_io_mask_upper_T_9 = mux(_amoalu_io_mask_upper_T_8, _amoalu_io_mask_T_1, UInt<1>(0h0))
node _amoalu_io_mask_upper_T_10 = geq(amoalu_io_mask_size, UInt<2>(0h3))
node _amoalu_io_mask_upper_T_11 = mux(_amoalu_io_mask_upper_T_10, UInt<4>(0hf), UInt<1>(0h0))
node amoalu_io_mask_upper_2 = or(_amoalu_io_mask_upper_T_9, _amoalu_io_mask_upper_T_11)
node _amoalu_io_mask_lower_T_2 = bits(s2_req[0].addr, 2, 2)
node amoalu_io_mask_lower_2 = mux(_amoalu_io_mask_lower_T_2, UInt<1>(0h0), _amoalu_io_mask_T_1)
node _amoalu_io_mask_T_2 = cat(amoalu_io_mask_upper_2, amoalu_io_mask_lower_2)
connect amoalu.io.mask, _amoalu_io_mask_T_2
connect amoalu.io.cmd, s2_req[0].uop.mem_cmd
connect amoalu.io.lhs, s2_data_word[0]
connect amoalu.io.rhs, s2_req[0].data
connect s3_req.data, amoalu.io.out
reg s3_way : UInt, clock
connect s3_way, s2_tag_match_way[0]
connect dataWriteArb.io.in[0].valid, s3_valid
connect dataWriteArb.io.in[0].bits.addr, s3_req.addr
node _dataWriteArb_io_in_0_bits_wmask_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect dataWriteArb.io.in[0].bits.wmask, _dataWriteArb_io_in_0_bits_wmask_T
connect dataWriteArb.io.in[0].bits.data, s3_req.data
connect dataWriteArb.io.in[0].bits.way_en, s3_way
node _io_lsu_ordered_T = eq(s1_valid[0], UInt<1>(0h0))
node _io_lsu_ordered_T_1 = and(mshrs.io.fence_rdy, _io_lsu_ordered_T)
node _io_lsu_ordered_T_2 = eq(s2_valid[0], UInt<1>(0h0))
node _io_lsu_ordered_T_3 = and(_io_lsu_ordered_T_1, _io_lsu_ordered_T_2)
connect io.lsu.ordered, _io_lsu_ordered_T_3 | module BoomNonBlockingDCache_1( // @[dcache.scala:413:7]
input clock, // @[dcache.scala:413:7]
input reset, // @[dcache.scala:413:7]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output io_lsu_req_ready, // @[dcache.scala:419:14]
input io_lsu_req_valid, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_valid, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_uopc, // @[dcache.scala:419:14]
input [31:0] io_lsu_req_bits_0_bits_uop_inst, // @[dcache.scala:419:14]
input [31:0] io_lsu_req_bits_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
input [33:0] io_lsu_req_bits_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_iq_type, // @[dcache.scala:419:14]
input [9:0] io_lsu_req_bits_0_bits_uop_fu_code, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_iw_state, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_br, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_jal, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_br_mask, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_br_tag, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_taken, // @[dcache.scala:419:14]
input [19:0] io_lsu_req_bits_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
input [11:0] io_lsu_req_bits_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_pdst, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs1, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs2, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs3, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ppred, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_exception, // @[dcache.scala:419:14]
input [63:0] io_lsu_req_bits_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bypassable, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_mem_size, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_fence, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_amo, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_unique, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_ldst, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs2, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs3, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_fp_val, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_fp_single, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
input [33:0] io_lsu_req_bits_0_bits_addr, // @[dcache.scala:419:14]
input [63:0] io_lsu_req_bits_0_bits_data, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_is_hella, // @[dcache.scala:419:14]
input io_lsu_s1_kill_0, // @[dcache.scala:419:14]
output io_lsu_resp_0_valid, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_uopc, // @[dcache.scala:419:14]
output [31:0] io_lsu_resp_0_bits_uop_inst, // @[dcache.scala:419:14]
output [31:0] io_lsu_resp_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
output [33:0] io_lsu_resp_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_iq_type, // @[dcache.scala:419:14]
output [9:0] io_lsu_resp_0_bits_uop_fu_code, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_iw_state, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_br, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_jal, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_br_mask, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_br_tag, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_taken, // @[dcache.scala:419:14]
output [19:0] io_lsu_resp_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
output [11:0] io_lsu_resp_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_pdst, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_prs1, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_prs2, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_prs3, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ppred, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_exception, // @[dcache.scala:419:14]
output [63:0] io_lsu_resp_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bypassable, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_mem_size, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_fence, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_amo, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_unique, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_ldst, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs3, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_fp_val, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_fp_single, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
output [63:0] io_lsu_resp_0_bits_data, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_is_hella, // @[dcache.scala:419:14]
output io_lsu_nack_0_valid, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_uopc, // @[dcache.scala:419:14]
output [31:0] io_lsu_nack_0_bits_uop_inst, // @[dcache.scala:419:14]
output [31:0] io_lsu_nack_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
output [33:0] io_lsu_nack_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_iq_type, // @[dcache.scala:419:14]
output [9:0] io_lsu_nack_0_bits_uop_fu_code, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_iw_state, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_br, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_jal, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_br_mask, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_br_tag, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_taken, // @[dcache.scala:419:14]
output [19:0] io_lsu_nack_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
output [11:0] io_lsu_nack_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_pdst, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_prs1, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_prs2, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_prs3, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ppred, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_exception, // @[dcache.scala:419:14]
output [63:0] io_lsu_nack_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bypassable, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_mem_size, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_fence, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_amo, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_unique, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_ldst, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs3, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_fp_val, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_fp_single, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
output [33:0] io_lsu_nack_0_bits_addr, // @[dcache.scala:419:14]
output [63:0] io_lsu_nack_0_bits_data, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_is_hella, // @[dcache.scala:419:14]
input [5:0] io_lsu_rob_pnr_idx, // @[dcache.scala:419:14]
input [5:0] io_lsu_rob_head_idx, // @[dcache.scala:419:14]
input io_lsu_release_ready, // @[dcache.scala:419:14]
output io_lsu_release_valid, // @[dcache.scala:419:14]
output [2:0] io_lsu_release_bits_opcode, // @[dcache.scala:419:14]
output [2:0] io_lsu_release_bits_param, // @[dcache.scala:419:14]
output [3:0] io_lsu_release_bits_size, // @[dcache.scala:419:14]
output [3:0] io_lsu_release_bits_source, // @[dcache.scala:419:14]
output [31:0] io_lsu_release_bits_address, // @[dcache.scala:419:14]
output [63:0] io_lsu_release_bits_data, // @[dcache.scala:419:14]
input io_lsu_force_order, // @[dcache.scala:419:14]
output io_lsu_ordered, // @[dcache.scala:419:14]
output io_lsu_perf_acquire, // @[dcache.scala:419:14]
output io_lsu_perf_release // @[dcache.scala:419:14]
);
wire resp_0_valid; // @[dcache.scala:846:22]
wire resp_0_bits_is_hella; // @[dcache.scala:846:22]
wire [63:0] resp_0_bits_data; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_debug_tsrc; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_debug_fsrc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bp_xcpt_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bp_debug_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_ma_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_ae_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_pf_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_fp_single; // @[dcache.scala:846:22]
wire resp_0_bits_uop_fp_val; // @[dcache.scala:846:22]
wire resp_0_bits_uop_frs3_en; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_lrs2_rtype; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_lrs1_rtype; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_dst_rtype; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ldst_val; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs3; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs2; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs1; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_ldst; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ldst_is_rs1; // @[dcache.scala:846:22]
wire resp_0_bits_uop_flush_on_commit; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_unique; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_uses_stq; // @[dcache.scala:846:22]
wire resp_0_bits_uop_uses_ldq; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_amo; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_fencei; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_fence; // @[dcache.scala:846:22]
wire resp_0_bits_uop_mem_signed; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_mem_size; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_mem_cmd; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bypassable; // @[dcache.scala:846:22]
wire [63:0] resp_0_bits_uop_exc_cause; // @[dcache.scala:846:22]
wire resp_0_bits_uop_exception; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_stale_pdst; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ppred_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs3_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs2_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs1_busy; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ppred; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_prs3; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_prs2; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_prs1; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_pdst; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_rxq_idx; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_stq_idx; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ldq_idx; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_rob_idx; // @[dcache.scala:846:22]
wire [11:0] resp_0_bits_uop_csr_addr; // @[dcache.scala:846:22]
wire [19:0] resp_0_bits_uop_imm_packed; // @[dcache.scala:846:22]
wire resp_0_bits_uop_taken; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_pc_lob; // @[dcache.scala:846:22]
wire resp_0_bits_uop_edge_inst; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ftq_idx; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_br_tag; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_br_mask; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_sfb; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_jal; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_jalr; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_br; // @[dcache.scala:846:22]
wire resp_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:846:22]
wire resp_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_iw_state; // @[dcache.scala:846:22]
wire [9:0] resp_0_bits_uop_fu_code; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_iq_type; // @[dcache.scala:846:22]
wire [33:0] resp_0_bits_uop_debug_pc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_rvc; // @[dcache.scala:846:22]
wire [31:0] resp_0_bits_uop_debug_inst; // @[dcache.scala:846:22]
wire [31:0] resp_0_bits_uop_inst; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_uopc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_std; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_sta; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_load; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ctrl_br_type; // @[dcache.scala:846:22]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [21:0] _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire [63:0] _amoalu_io_out; // @[dcache.scala:896:24]
wire _lsu_release_arb_io_in_0_ready; // @[dcache.scala:814:31]
wire _lsu_release_arb_io_in_1_ready; // @[dcache.scala:814:31]
wire _wbArb_io_in_0_ready; // @[dcache.scala:805:21]
wire _wbArb_io_in_1_ready; // @[dcache.scala:805:21]
wire _wbArb_io_out_valid; // @[dcache.scala:805:21]
wire [21:0] _wbArb_io_out_bits_tag; // @[dcache.scala:805:21]
wire [3:0] _wbArb_io_out_bits_idx; // @[dcache.scala:805:21]
wire [3:0] _wbArb_io_out_bits_source; // @[dcache.scala:805:21]
wire [2:0] _wbArb_io_out_bits_param; // @[dcache.scala:805:21]
wire [1:0] _wbArb_io_out_bits_way_en; // @[dcache.scala:805:21]
wire _wbArb_io_out_bits_voluntary; // @[dcache.scala:805:21]
wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22]
wire _dataReadArb_io_in_1_ready; // @[dcache.scala:463:27]
wire _dataReadArb_io_in_2_ready; // @[dcache.scala:463:27]
wire _dataReadArb_io_out_valid; // @[dcache.scala:463:27]
wire [1:0] _dataReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:463:27]
wire [9:0] _dataReadArb_io_out_bits_req_0_addr; // @[dcache.scala:463:27]
wire _dataReadArb_io_out_bits_valid_0; // @[dcache.scala:463:27]
wire _dataWriteArb_io_in_1_ready; // @[dcache.scala:461:28]
wire [1:0] _dataWriteArb_io_out_bits_way_en; // @[dcache.scala:461:28]
wire [9:0] _dataWriteArb_io_out_bits_addr; // @[dcache.scala:461:28]
wire [63:0] _dataWriteArb_io_out_bits_data; // @[dcache.scala:461:28]
wire _metaReadArb_io_in_1_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_2_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_3_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_4_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_5_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_out_valid; // @[dcache.scala:445:27]
wire [3:0] _metaReadArb_io_out_bits_req_0_idx; // @[dcache.scala:445:27]
wire [1:0] _metaReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:445:27]
wire [21:0] _metaReadArb_io_out_bits_req_0_tag; // @[dcache.scala:445:27]
wire _metaWriteArb_io_in_0_ready; // @[dcache.scala:443:28]
wire _metaWriteArb_io_in_1_ready; // @[dcache.scala:443:28]
wire _metaWriteArb_io_out_valid; // @[dcache.scala:443:28]
wire [3:0] _metaWriteArb_io_out_bits_idx; // @[dcache.scala:443:28]
wire [1:0] _metaWriteArb_io_out_bits_way_en; // @[dcache.scala:443:28]
wire [21:0] _metaWriteArb_io_out_bits_tag; // @[dcache.scala:443:28]
wire [1:0] _metaWriteArb_io_out_bits_data_coh_state; // @[dcache.scala:443:28]
wire [21:0] _metaWriteArb_io_out_bits_data_tag; // @[dcache.scala:443:28]
wire _meta_0_io_read_ready; // @[dcache.scala:442:41]
wire _meta_0_io_write_ready; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_0_coh_state; // @[dcache.scala:442:41]
wire [21:0] _meta_0_io_resp_0_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_1_coh_state; // @[dcache.scala:442:41]
wire [21:0] _meta_0_io_resp_1_tag; // @[dcache.scala:442:41]
wire _mshrs_io_req_0_ready; // @[dcache.scala:433:21]
wire _mshrs_io_secondary_miss_0; // @[dcache.scala:433:21]
wire _mshrs_io_block_hit_0; // @[dcache.scala:433:21]
wire _mshrs_io_mem_grant_ready; // @[dcache.scala:433:21]
wire _mshrs_io_refill_valid; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_refill_bits_way_en; // @[dcache.scala:433:21]
wire [9:0] _mshrs_io_refill_bits_addr; // @[dcache.scala:433:21]
wire [63:0] _mshrs_io_refill_bits_data; // @[dcache.scala:433:21]
wire _mshrs_io_meta_write_valid; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_meta_write_bits_idx; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_meta_write_bits_way_en; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_meta_write_bits_data_coh_state; // @[dcache.scala:433:21]
wire [21:0] _mshrs_io_meta_write_bits_data_tag; // @[dcache.scala:433:21]
wire _mshrs_io_meta_read_valid; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_meta_read_bits_idx; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_meta_read_bits_way_en; // @[dcache.scala:433:21]
wire [21:0] _mshrs_io_meta_read_bits_tag; // @[dcache.scala:433:21]
wire _mshrs_io_replay_valid; // @[dcache.scala:433:21]
wire [4:0] _mshrs_io_replay_bits_uop_mem_cmd; // @[dcache.scala:433:21]
wire [33:0] _mshrs_io_replay_bits_addr; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_replay_bits_way_en; // @[dcache.scala:433:21]
wire _mshrs_io_wb_req_valid; // @[dcache.scala:433:21]
wire [21:0] _mshrs_io_wb_req_bits_tag; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_wb_req_bits_idx; // @[dcache.scala:433:21]
wire [3:0] _mshrs_io_wb_req_bits_source; // @[dcache.scala:433:21]
wire [2:0] _mshrs_io_wb_req_bits_param; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_wb_req_bits_way_en; // @[dcache.scala:433:21]
wire _mshrs_io_fence_rdy; // @[dcache.scala:433:21]
wire _mshrs_io_probe_rdy; // @[dcache.scala:433:21]
wire _prober_io_req_ready; // @[dcache.scala:432:22]
wire _prober_io_rep_valid; // @[dcache.scala:432:22]
wire [2:0] _prober_io_rep_bits_param; // @[dcache.scala:432:22]
wire [3:0] _prober_io_rep_bits_size; // @[dcache.scala:432:22]
wire [3:0] _prober_io_rep_bits_source; // @[dcache.scala:432:22]
wire [31:0] _prober_io_rep_bits_address; // @[dcache.scala:432:22]
wire _prober_io_meta_read_valid; // @[dcache.scala:432:22]
wire [3:0] _prober_io_meta_read_bits_idx; // @[dcache.scala:432:22]
wire [21:0] _prober_io_meta_read_bits_tag; // @[dcache.scala:432:22]
wire _prober_io_meta_write_valid; // @[dcache.scala:432:22]
wire [3:0] _prober_io_meta_write_bits_idx; // @[dcache.scala:432:22]
wire [1:0] _prober_io_meta_write_bits_way_en; // @[dcache.scala:432:22]
wire [21:0] _prober_io_meta_write_bits_tag; // @[dcache.scala:432:22]
wire [1:0] _prober_io_meta_write_bits_data_coh_state; // @[dcache.scala:432:22]
wire [21:0] _prober_io_meta_write_bits_data_tag; // @[dcache.scala:432:22]
wire _prober_io_wb_req_valid; // @[dcache.scala:432:22]
wire [21:0] _prober_io_wb_req_bits_tag; // @[dcache.scala:432:22]
wire [3:0] _prober_io_wb_req_bits_idx; // @[dcache.scala:432:22]
wire [3:0] _prober_io_wb_req_bits_source; // @[dcache.scala:432:22]
wire [2:0] _prober_io_wb_req_bits_param; // @[dcache.scala:432:22]
wire [1:0] _prober_io_wb_req_bits_way_en; // @[dcache.scala:432:22]
wire _prober_io_mshr_wb_rdy; // @[dcache.scala:432:22]
wire _prober_io_lsu_release_valid; // @[dcache.scala:432:22]
wire [2:0] _prober_io_lsu_release_bits_param; // @[dcache.scala:432:22]
wire [3:0] _prober_io_lsu_release_bits_size; // @[dcache.scala:432:22]
wire [3:0] _prober_io_lsu_release_bits_source; // @[dcache.scala:432:22]
wire [31:0] _prober_io_lsu_release_bits_address; // @[dcache.scala:432:22]
wire _prober_io_state_valid; // @[dcache.scala:432:22]
wire [33:0] _prober_io_state_bits; // @[dcache.scala:432:22]
wire _wb_io_req_ready; // @[dcache.scala:431:18]
wire _wb_io_meta_read_valid; // @[dcache.scala:431:18]
wire [3:0] _wb_io_meta_read_bits_idx; // @[dcache.scala:431:18]
wire [21:0] _wb_io_meta_read_bits_tag; // @[dcache.scala:431:18]
wire _wb_io_resp; // @[dcache.scala:431:18]
wire _wb_io_idx_valid; // @[dcache.scala:431:18]
wire [3:0] _wb_io_idx_bits; // @[dcache.scala:431:18]
wire _wb_io_data_req_valid; // @[dcache.scala:431:18]
wire [1:0] _wb_io_data_req_bits_way_en; // @[dcache.scala:431:18]
wire [9:0] _wb_io_data_req_bits_addr; // @[dcache.scala:431:18]
wire _wb_io_release_valid; // @[dcache.scala:431:18]
wire [2:0] _wb_io_release_bits_opcode; // @[dcache.scala:431:18]
wire [2:0] _wb_io_release_bits_param; // @[dcache.scala:431:18]
wire [31:0] _wb_io_release_bits_address; // @[dcache.scala:431:18]
wire [63:0] _wb_io_release_bits_data; // @[dcache.scala:431:18]
wire _wb_io_lsu_release_valid; // @[dcache.scala:431:18]
wire [2:0] _wb_io_lsu_release_bits_param; // @[dcache.scala:431:18]
wire [31:0] _wb_io_lsu_release_bits_address; // @[dcache.scala:431:18]
wire [63:0] _wb_io_lsu_release_bits_data; // @[dcache.scala:431:18]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[dcache.scala:413:7]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[dcache.scala:413:7]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[dcache.scala:413:7]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[dcache.scala:413:7]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[dcache.scala:413:7]
wire [3:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[dcache.scala:413:7]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[dcache.scala:413:7]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[dcache.scala:413:7]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[dcache.scala:413:7]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[dcache.scala:413:7]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[dcache.scala:413:7]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[dcache.scala:413:7]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[dcache.scala:413:7]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[dcache.scala:413:7]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[dcache.scala:413:7]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[dcache.scala:413:7]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[dcache.scala:413:7]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[dcache.scala:413:7]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[dcache.scala:413:7]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[dcache.scala:413:7]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[dcache.scala:413:7]
wire io_lsu_req_valid_0 = io_lsu_req_valid; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_valid_0 = io_lsu_req_bits_0_valid; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_uopc_0 = io_lsu_req_bits_0_bits_uop_uopc; // @[dcache.scala:413:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_inst_0 = io_lsu_req_bits_0_bits_uop_inst; // @[dcache.scala:413:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_debug_inst_0 = io_lsu_req_bits_0_bits_uop_debug_inst; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_rvc_0 = io_lsu_req_bits_0_bits_uop_is_rvc; // @[dcache.scala:413:7]
wire [33:0] io_lsu_req_bits_0_bits_uop_debug_pc_0 = io_lsu_req_bits_0_bits_uop_debug_pc; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_iq_type_0 = io_lsu_req_bits_0_bits_uop_iq_type; // @[dcache.scala:413:7]
wire [9:0] io_lsu_req_bits_0_bits_uop_fu_code_0 = io_lsu_req_bits_0_bits_uop_fu_code; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type_0 = io_lsu_req_bits_0_bits_uop_ctrl_br_type; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0 = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_load_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_load; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_sta; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_std_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_std; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_iw_state_0 = io_lsu_req_bits_0_bits_uop_iw_state; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_br_0 = io_lsu_req_bits_0_bits_uop_is_br; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_jalr_0 = io_lsu_req_bits_0_bits_uop_is_jalr; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_jal_0 = io_lsu_req_bits_0_bits_uop_is_jal; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_sfb_0 = io_lsu_req_bits_0_bits_uop_is_sfb; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_br_mask_0 = io_lsu_req_bits_0_bits_uop_br_mask; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_br_tag_0 = io_lsu_req_bits_0_bits_uop_br_tag; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ftq_idx_0 = io_lsu_req_bits_0_bits_uop_ftq_idx; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_edge_inst_0 = io_lsu_req_bits_0_bits_uop_edge_inst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_pc_lob_0 = io_lsu_req_bits_0_bits_uop_pc_lob; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_taken_0 = io_lsu_req_bits_0_bits_uop_taken; // @[dcache.scala:413:7]
wire [19:0] io_lsu_req_bits_0_bits_uop_imm_packed_0 = io_lsu_req_bits_0_bits_uop_imm_packed; // @[dcache.scala:413:7]
wire [11:0] io_lsu_req_bits_0_bits_uop_csr_addr_0 = io_lsu_req_bits_0_bits_uop_csr_addr; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_rob_idx_0 = io_lsu_req_bits_0_bits_uop_rob_idx; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ldq_idx_0 = io_lsu_req_bits_0_bits_uop_ldq_idx; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_stq_idx_0 = io_lsu_req_bits_0_bits_uop_stq_idx; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx_0 = io_lsu_req_bits_0_bits_uop_rxq_idx; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_pdst_0 = io_lsu_req_bits_0_bits_uop_pdst; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs1_0 = io_lsu_req_bits_0_bits_uop_prs1; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs2_0 = io_lsu_req_bits_0_bits_uop_prs2; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs3_0 = io_lsu_req_bits_0_bits_uop_prs3; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ppred_0 = io_lsu_req_bits_0_bits_uop_ppred; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs1_busy_0 = io_lsu_req_bits_0_bits_uop_prs1_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs2_busy_0 = io_lsu_req_bits_0_bits_uop_prs2_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs3_busy_0 = io_lsu_req_bits_0_bits_uop_prs3_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ppred_busy_0 = io_lsu_req_bits_0_bits_uop_ppred_busy; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst_0 = io_lsu_req_bits_0_bits_uop_stale_pdst; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_exception_0 = io_lsu_req_bits_0_bits_uop_exception; // @[dcache.scala:413:7]
wire [63:0] io_lsu_req_bits_0_bits_uop_exc_cause_0 = io_lsu_req_bits_0_bits_uop_exc_cause; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bypassable_0 = io_lsu_req_bits_0_bits_uop_bypassable; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd_0 = io_lsu_req_bits_0_bits_uop_mem_cmd; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_mem_size_0 = io_lsu_req_bits_0_bits_uop_mem_size; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_mem_signed_0 = io_lsu_req_bits_0_bits_uop_mem_signed; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_fence_0 = io_lsu_req_bits_0_bits_uop_is_fence; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_fencei_0 = io_lsu_req_bits_0_bits_uop_is_fencei; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_amo_0 = io_lsu_req_bits_0_bits_uop_is_amo; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_uses_ldq_0 = io_lsu_req_bits_0_bits_uop_uses_ldq; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_uses_stq_0 = io_lsu_req_bits_0_bits_uop_uses_stq; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0 = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_unique_0 = io_lsu_req_bits_0_bits_uop_is_unique; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_flush_on_commit_0 = io_lsu_req_bits_0_bits_uop_flush_on_commit; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_ldst_0 = io_lsu_req_bits_0_bits_uop_ldst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs1_0 = io_lsu_req_bits_0_bits_uop_lrs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs2_0 = io_lsu_req_bits_0_bits_uop_lrs2; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs3_0 = io_lsu_req_bits_0_bits_uop_lrs3; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ldst_val_0 = io_lsu_req_bits_0_bits_uop_ldst_val; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype_0 = io_lsu_req_bits_0_bits_uop_dst_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs1_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs2_rtype; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_frs3_en_0 = io_lsu_req_bits_0_bits_uop_frs3_en; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_fp_val_0 = io_lsu_req_bits_0_bits_uop_fp_val; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_fp_single_0 = io_lsu_req_bits_0_bits_uop_fp_single; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_pf_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ae_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ma_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bp_debug_if_0 = io_lsu_req_bits_0_bits_uop_bp_debug_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0 = io_lsu_req_bits_0_bits_uop_bp_xcpt_if; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc_0 = io_lsu_req_bits_0_bits_uop_debug_fsrc; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc_0 = io_lsu_req_bits_0_bits_uop_debug_tsrc; // @[dcache.scala:413:7]
wire [33:0] io_lsu_req_bits_0_bits_addr_0 = io_lsu_req_bits_0_bits_addr; // @[dcache.scala:413:7]
wire [63:0] io_lsu_req_bits_0_bits_data_0 = io_lsu_req_bits_0_bits_data; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_is_hella_0 = io_lsu_req_bits_0_bits_is_hella; // @[dcache.scala:413:7]
wire io_lsu_s1_kill_0_0 = io_lsu_s1_kill_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_rob_pnr_idx_0 = io_lsu_rob_pnr_idx; // @[dcache.scala:413:7]
wire [5:0] io_lsu_rob_head_idx_0 = io_lsu_rob_head_idx; // @[dcache.scala:413:7]
wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:413:7]
wire io_lsu_force_order_0 = io_lsu_force_order; // @[dcache.scala:413:7]
wire auto_out_a_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire auto_out_c_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_br = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_jalr = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_jal = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_taken = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_exception = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bypassable = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_fence = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_amo = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_unique = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ldst_val = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_fp_val = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_fp_single = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_valid = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_mispredict = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_taken = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_exception = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire mshr_read_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_br = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_jal = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_taken = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_exception = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bypassable = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_fence = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_amo = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_unique = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_fp_val = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_fp_single = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_is_hella = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_br = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_jal = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_taken = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_exception = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bypassable = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_fence = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_amo = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_unique = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_fp_val = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_fp_single = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_is_hella = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_br = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_jal = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_taken = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_exception = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bypassable = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_fence = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_amo = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_unique = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_fp_val = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_fp_single = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_is_hella = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire prefetch_fire = 1'h0; // @[Decoupled.scala:51:35]
wire prefetch_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_br = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_jal = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_taken = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_exception = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bypassable = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_fence = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_amo = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_unique = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_fp_val = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_fp_single = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_is_hella = 1'h0; // @[dcache.scala:568:27]
wire _s0_valid_WIRE_2_0 = 1'h0; // @[dcache.scala:581:82]
wire _s1_valid_T_1 = 1'h0; // @[util.scala:118:59]
wire _s1_valid_T_4 = 1'h0; // @[dcache.scala:607:45]
wire _s2_valid_T_3 = 1'h0; // @[util.scala:118:59]
wire _s2_valid_T_6 = 1'h0; // @[dcache.scala:638:45]
wire _s2_has_permission_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire s2_word_idx_0 = 1'h0; // @[dcache.scala:427:49]
wire s2_nack_data_0 = 1'h0; // @[dcache.scala:427:49]
wire _mshrs_io_req_0_valid_T_15 = 1'h0; // @[util.scala:118:59]
wire _mshrs_io_req_0_valid_T_18 = 1'h0; // @[dcache.scala:754:48]
wire opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _nodeOut_c_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire cache_resp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire cache_resp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire _io_lsu_resp_0_valid_T = 1'h0; // @[dcache.scala:858:48]
wire _io_lsu_resp_0_valid_T_4 = 1'h0; // @[util.scala:118:59]
wire _io_lsu_nack_0_valid_T_1 = 1'h0; // @[dcache.scala:863:48]
wire _io_lsu_nack_0_valid_T_5 = 1'h0; // @[util.scala:118:59]
wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0; // @[dcache.scala:413:7]
wire [3:0] mshr_read_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_br_mask = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_ppred = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_br_mask = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_ldq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_stq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] wb_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_br_mask = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_ppred = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_br_mask = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_ldq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_stq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] prober_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_br_mask = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_ppred = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_br_mask = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_ldq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_stq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] prefetch_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_br_mask = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_ftq_idx = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_ldq_idx = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_stq_idx = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_ppred = 4'h0; // @[dcache.scala:568:27]
wire [3:0] _s1_valid_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _s2_valid_T_2 = 4'h0; // @[util.scala:118:51]
wire [3:0] _s2_has_permission_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _s2_new_hit_state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _mshrs_io_req_0_valid_T_14 = 4'h0; // @[util.scala:118:51]
wire [3:0] _io_lsu_resp_0_valid_T_3 = 4'h0; // @[util.scala:118:51]
wire [3:0] _io_lsu_nack_0_valid_T_4 = 4'h0; // @[util.scala:118:51]
wire [6:0] io_lsu_brupdate_b2_uop_uopc = 7'h0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_pdst = 7'h0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs1 = 7'h0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs2 = 7'h0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs3 = 7'h0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst = 7'h0; // @[dcache.scala:413:7]
wire [6:0] mshr_read_req_0_uop_uopc = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_pdst = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_prs1 = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_prs2 = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_prs3 = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uopc = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_pdst = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_prs1 = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_prs2 = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_prs3 = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uopc = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_pdst = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_prs1 = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_prs2 = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_prs3 = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] prefetch_req_0_uop_uopc = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_pdst = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_prs1 = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_prs2 = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_prs3 = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:568:27]
wire [6:0] _s2_data_word_prebypass_T = 7'h0; // @[dcache.scala:825:69]
wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0; // @[dcache.scala:413:7]
wire [31:0] mshr_read_req_0_uop_inst = 32'h0; // @[dcache.scala:517:27]
wire [31:0] mshr_read_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:517:27]
wire [31:0] mshr_read_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] mshr_read_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] wb_req_0_uop_inst = 32'h0; // @[dcache.scala:532:20]
wire [31:0] wb_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:532:20]
wire [31:0] wb_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] wb_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prober_req_0_uop_inst = 32'h0; // @[dcache.scala:553:26]
wire [31:0] prober_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:553:26]
wire [31:0] prober_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prober_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prefetch_req_0_uop_inst = 32'h0; // @[dcache.scala:568:27]
wire [31:0] prefetch_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:568:27]
wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0; // @[dcache.scala:413:7]
wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0; // @[dcache.scala:413:7]
wire [33:0] mshr_read_req_0_uop_debug_pc = 34'h0; // @[dcache.scala:517:27]
wire [33:0] mshr_read_req_0_uop_uop_debug_pc = 34'h0; // @[consts.scala:269:19]
wire [33:0] wb_req_0_uop_debug_pc = 34'h0; // @[dcache.scala:532:20]
wire [33:0] wb_req_0_uop_uop_debug_pc = 34'h0; // @[consts.scala:269:19]
wire [33:0] prober_req_0_uop_debug_pc = 34'h0; // @[dcache.scala:553:26]
wire [33:0] prober_req_0_uop_uop_debug_pc = 34'h0; // @[consts.scala:269:19]
wire [33:0] prefetch_req_0_uop_debug_pc = 34'h0; // @[dcache.scala:568:27]
wire [33:0] prefetch_req_0_addr = 34'h0; // @[dcache.scala:568:27]
wire [2:0] io_lsu_brupdate_b2_uop_iq_type = 3'h0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0; // @[dcache.scala:413:7]
wire [2:0] mshr_read_req_0_uop_iq_type = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] mshr_read_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] mshr_read_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_iq_type = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_iq_type = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] prefetch_req_0_uop_iq_type = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:568:27]
wire [9:0] io_lsu_brupdate_b2_uop_fu_code = 10'h0; // @[dcache.scala:413:7]
wire [9:0] mshr_read_req_0_uop_fu_code = 10'h0; // @[dcache.scala:517:27]
wire [9:0] mshr_read_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] wb_req_0_uop_fu_code = 10'h0; // @[dcache.scala:532:20]
wire [9:0] wb_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] prober_req_0_uop_fu_code = 10'h0; // @[dcache.scala:553:26]
wire [9:0] prober_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] prefetch_req_0_uop_fu_code = 10'h0; // @[dcache.scala:568:27]
wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_state = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_target_offset = 2'h0; // @[dcache.scala:413:7]
wire [1:0] mshr_read_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_iw_state = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_br_tag = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_mem_size = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_br_tag = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] wb_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_iw_state = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_br_tag = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_mem_size = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_br_tag = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] prober_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_iw_state = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_br_tag = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_mem_size = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_br_tag = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] prefetch_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_iw_state = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_br_tag = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_mem_size = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:568:27]
wire [1:0] _s2_has_permission_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0; // @[dcache.scala:413:7]
wire [4:0] mshr_read_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] wb_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] prober_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] prefetch_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:568:27]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_rob_idx = 6'h0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0; // @[dcache.scala:413:7]
wire [5:0] mshr_read_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_ldst = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_rob_idx = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_ldst = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_rob_idx = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_ldst = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_rob_idx = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prefetch_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_rob_idx = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_ldst = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:568:27]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0; // @[dcache.scala:413:7]
wire [19:0] mshr_read_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:517:27]
wire [19:0] mshr_read_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] wb_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:532:20]
wire [19:0] wb_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] prober_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:553:26]
wire [19:0] prober_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] prefetch_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:568:27]
wire [11:0] io_lsu_brupdate_b2_uop_csr_addr = 12'h0; // @[dcache.scala:413:7]
wire [11:0] mshr_read_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:517:27]
wire [11:0] mshr_read_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] wb_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:532:20]
wire [11:0] wb_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] prober_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:553:26]
wire [11:0] prober_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] prefetch_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:568:27]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0; // @[dcache.scala:413:7]
wire [63:0] mshr_read_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:517:27]
wire [63:0] mshr_read_req_0_data = 64'h0; // @[dcache.scala:517:27]
wire [63:0] mshr_read_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] wb_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:532:20]
wire [63:0] wb_req_0_data = 64'h0; // @[dcache.scala:532:20]
wire [63:0] wb_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] prober_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:553:26]
wire [63:0] prober_req_0_data = 64'h0; // @[dcache.scala:553:26]
wire [63:0] prober_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] prefetch_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:568:27]
wire [63:0] prefetch_req_0_data = 64'h0; // @[dcache.scala:568:27]
wire [63:0] _nodeOut_c_bits_T_4 = 64'h0; // @[Mux.scala:30:73]
wire [3:0] _s1_req_0_uop_br_mask_T = 4'hF; // @[util.scala:85:27]
wire [3:0] _s2_req_0_uop_br_mask_T = 4'hF; // @[util.scala:85:27]
wire [3:0] _s2_has_permission_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _s2_new_hit_state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _mshrs_io_req_0_bits_uop_br_mask_T = 4'hF; // @[util.scala:85:27]
wire [3:0] _io_lsu_resp_0_bits_out_uop_br_mask_T = 4'hF; // @[util.scala:89:23]
wire [3:0] _io_lsu_nack_0_bits_out_uop_br_mask_T = 4'hF; // @[util.scala:89:23]
wire _s0_valid_WIRE_1_0 = 1'h1; // @[dcache.scala:581:48]
wire _s1_valid_T_2 = 1'h1; // @[dcache.scala:606:26]
wire _s1_valid_T_5 = 1'h1; // @[dcache.scala:607:26]
wire _s2_valid_T_4 = 1'h1; // @[dcache.scala:637:26]
wire _s2_valid_T_7 = 1'h1; // @[dcache.scala:638:26]
wire _mshrs_io_req_0_valid_T_6 = 1'h1; // @[dcache.scala:750:29]
wire _mshrs_io_req_0_valid_T_16 = 1'h1; // @[dcache.scala:753:29]
wire _mshrs_io_req_0_valid_T_19 = 1'h1; // @[dcache.scala:754:29]
wire _uncache_respond_T_1 = 1'h1; // @[dcache.scala:849:51]
wire _io_lsu_resp_0_valid_T_1 = 1'h1; // @[dcache.scala:858:29]
wire _io_lsu_resp_0_valid_T_5 = 1'h1; // @[dcache.scala:859:29]
wire _io_lsu_nack_0_valid_T_2 = 1'h1; // @[dcache.scala:863:29]
wire _io_lsu_nack_0_valid_T_6 = 1'h1; // @[dcache.scala:864:29]
wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69]
wire [8:0] decode = 9'h7; // @[Edges.scala:220:59]
wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [3:0] _s2_has_permission_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_new_hit_state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_has_permission_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_new_hit_state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_has_permission_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_new_hit_state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_has_permission_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_new_hit_state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_has_permission_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _s2_new_hit_state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _s2_has_permission_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _s2_new_hit_state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _s2_has_permission_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_new_hit_state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_has_permission_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_new_hit_state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_has_permission_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_new_hit_state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_has_permission_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _s2_new_hit_state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [27:0] _metaReadArb_io_in_5_bits_req_0_idx_T = 28'h0; // @[dcache.scala:573:74]
wire [1:0] mshr_read_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] _s2_has_permission_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _dataWriteArb_io_in_0_bits_wmask_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _dataReadArb_io_in_2_bits_req_0_way_en_T = 2'h3; // @[dcache.scala:491:48]
wire [1:0] _s2_has_permission_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _io_lsu_req_ready_T; // @[dcache.scala:480:50]
wire _s0_valid_WIRE_0 = io_lsu_req_bits_0_valid_0; // @[dcache.scala:413:7, :579:46]
wire [6:0] _s0_req_WIRE_0_uop_uopc = io_lsu_req_bits_0_bits_uop_uopc_0; // @[dcache.scala:413:7, :582:54]
wire [31:0] _s0_req_WIRE_0_uop_inst = io_lsu_req_bits_0_bits_uop_inst_0; // @[dcache.scala:413:7, :582:54]
wire [31:0] _s0_req_WIRE_0_uop_debug_inst = io_lsu_req_bits_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_rvc = io_lsu_req_bits_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7, :582:54]
wire [33:0] _s0_req_WIRE_0_uop_debug_pc = io_lsu_req_bits_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_iq_type = io_lsu_req_bits_0_bits_uop_iq_type_0; // @[dcache.scala:413:7, :582:54]
wire [9:0] _s0_req_WIRE_0_uop_fu_code = io_lsu_req_bits_0_bits_uop_fu_code_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ctrl_br_type = io_lsu_req_bits_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_ctrl_op1_sel = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_op2_sel = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_imm_sel = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_ctrl_op_fcn = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_fcn_dw = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_csr_cmd = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_load = io_lsu_req_bits_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_sta = io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_std = io_lsu_req_bits_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_iw_state = io_lsu_req_bits_0_bits_uop_iw_state_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_iw_p1_poisoned = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_iw_p2_poisoned = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_br = io_lsu_req_bits_0_bits_uop_is_br_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_jalr = io_lsu_req_bits_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_jal = io_lsu_req_bits_0_bits_uop_is_jal_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_sfb = io_lsu_req_bits_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_br_mask = io_lsu_req_bits_0_bits_uop_br_mask_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_br_tag = io_lsu_req_bits_0_bits_uop_br_tag_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ftq_idx = io_lsu_req_bits_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_edge_inst = io_lsu_req_bits_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_pc_lob = io_lsu_req_bits_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_taken = io_lsu_req_bits_0_bits_uop_taken_0; // @[dcache.scala:413:7, :582:54]
wire [19:0] _s0_req_WIRE_0_uop_imm_packed = io_lsu_req_bits_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7, :582:54]
wire [11:0] _s0_req_WIRE_0_uop_csr_addr = io_lsu_req_bits_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_rob_idx = io_lsu_req_bits_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ldq_idx = io_lsu_req_bits_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_stq_idx = io_lsu_req_bits_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_rxq_idx = io_lsu_req_bits_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_pdst = io_lsu_req_bits_0_bits_uop_pdst_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_prs1 = io_lsu_req_bits_0_bits_uop_prs1_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_prs2 = io_lsu_req_bits_0_bits_uop_prs2_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_prs3 = io_lsu_req_bits_0_bits_uop_prs3_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ppred = io_lsu_req_bits_0_bits_uop_ppred_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs1_busy = io_lsu_req_bits_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs2_busy = io_lsu_req_bits_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs3_busy = io_lsu_req_bits_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ppred_busy = io_lsu_req_bits_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_stale_pdst = io_lsu_req_bits_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_exception = io_lsu_req_bits_0_bits_uop_exception_0; // @[dcache.scala:413:7, :582:54]
wire [63:0] _s0_req_WIRE_0_uop_exc_cause = io_lsu_req_bits_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bypassable = io_lsu_req_bits_0_bits_uop_bypassable_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_mem_cmd = io_lsu_req_bits_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_mem_size = io_lsu_req_bits_0_bits_uop_mem_size_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_mem_signed = io_lsu_req_bits_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_fence = io_lsu_req_bits_0_bits_uop_is_fence_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_fencei = io_lsu_req_bits_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_amo = io_lsu_req_bits_0_bits_uop_is_amo_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_uses_ldq = io_lsu_req_bits_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_uses_stq = io_lsu_req_bits_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_sys_pc2epc = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_unique = io_lsu_req_bits_0_bits_uop_is_unique_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_flush_on_commit = io_lsu_req_bits_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ldst_is_rs1 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_ldst = io_lsu_req_bits_0_bits_uop_ldst_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs1 = io_lsu_req_bits_0_bits_uop_lrs1_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs2 = io_lsu_req_bits_0_bits_uop_lrs2_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs3 = io_lsu_req_bits_0_bits_uop_lrs3_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ldst_val = io_lsu_req_bits_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_dst_rtype = io_lsu_req_bits_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_lrs1_rtype = io_lsu_req_bits_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_lrs2_rtype = io_lsu_req_bits_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_frs3_en = io_lsu_req_bits_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_fp_val = io_lsu_req_bits_0_bits_uop_fp_val_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_fp_single = io_lsu_req_bits_0_bits_uop_fp_single_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_pf_if = io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_ae_if = io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_ma_if = io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bp_debug_if = io_lsu_req_bits_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bp_xcpt_if = io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_debug_fsrc = io_lsu_req_bits_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_debug_tsrc = io_lsu_req_bits_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7, :582:54]
wire [33:0] _s0_req_WIRE_0_addr = io_lsu_req_bits_0_bits_addr_0; // @[dcache.scala:413:7, :582:54]
wire [63:0] _s0_req_WIRE_0_data = io_lsu_req_bits_0_bits_data_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_is_hella = io_lsu_req_bits_0_bits_is_hella_0; // @[dcache.scala:413:7, :582:54]
wire _io_lsu_resp_0_valid_T_6; // @[dcache.scala:858:78]
wire [6:0] io_lsu_resp_0_bits_out_uop_uopc; // @[util.scala:101:23]
wire [31:0] io_lsu_resp_0_bits_out_uop_inst; // @[util.scala:101:23]
wire [31:0] io_lsu_resp_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
wire [33:0] io_lsu_resp_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_iq_type; // @[util.scala:101:23]
wire [9:0] io_lsu_resp_0_bits_out_uop_fu_code; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_iw_state; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_br; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_jal; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_br_mask; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_br_tag; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_taken; // @[util.scala:101:23]
wire [19:0] io_lsu_resp_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
wire [11:0] io_lsu_resp_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_pdst; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_prs1; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_prs2; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_prs3; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ppred; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_exception; // @[util.scala:101:23]
wire [63:0] io_lsu_resp_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bypassable; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_mem_size; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_fence; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_amo; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_unique; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_ldst; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs1; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs2; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs3; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_fp_val; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_fp_single; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
wire [63:0] io_lsu_resp_0_bits_out_data; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_is_hella; // @[util.scala:101:23]
wire _io_lsu_nack_0_valid_T_7; // @[dcache.scala:863:75]
wire [6:0] io_lsu_nack_0_bits_out_uop_uopc; // @[util.scala:101:23]
wire [31:0] io_lsu_nack_0_bits_out_uop_inst; // @[util.scala:101:23]
wire [31:0] io_lsu_nack_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
wire [33:0] io_lsu_nack_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_iq_type; // @[util.scala:101:23]
wire [9:0] io_lsu_nack_0_bits_out_uop_fu_code; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_iw_state; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_br; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_jal; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_br_mask; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_br_tag; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_taken; // @[util.scala:101:23]
wire [19:0] io_lsu_nack_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
wire [11:0] io_lsu_nack_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_pdst; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_prs1; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_prs2; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_prs3; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ppred; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_exception; // @[util.scala:101:23]
wire [63:0] io_lsu_nack_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bypassable; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_mem_size; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_fence; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_amo; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_unique; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_ldst; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs1; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs2; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs3; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_fp_val; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_fp_single; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
wire [33:0] io_lsu_nack_0_bits_out_addr; // @[util.scala:101:23]
wire [63:0] io_lsu_nack_0_bits_out_data; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_is_hella; // @[util.scala:101:23]
wire _io_lsu_ordered_T_3; // @[dcache.scala:913:66]
wire io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [2:0] auto_out_a_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_a_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_a_bits_size_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_a_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] auto_out_a_bits_address_0; // @[dcache.scala:413:7]
wire [7:0] auto_out_a_bits_mask_0; // @[dcache.scala:413:7]
wire [63:0] auto_out_a_bits_data_0; // @[dcache.scala:413:7]
wire auto_out_a_valid_0; // @[dcache.scala:413:7]
wire auto_out_b_ready_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_c_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_c_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_c_bits_size_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_c_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] auto_out_c_bits_address_0; // @[dcache.scala:413:7]
wire [63:0] auto_out_c_bits_data_0; // @[dcache.scala:413:7]
wire auto_out_c_valid_0; // @[dcache.scala:413:7]
wire auto_out_d_ready_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_e_bits_sink_0; // @[dcache.scala:413:7]
wire auto_out_e_valid_0; // @[dcache.scala:413:7]
wire io_lsu_req_ready_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_uopc_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_resp_0_bits_uop_inst_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_resp_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7]
wire [33:0] io_lsu_resp_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_iq_type_0; // @[dcache.scala:413:7]
wire [9:0] io_lsu_resp_0_bits_uop_fu_code_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_iw_state_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_br_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_jal_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_br_mask_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_br_tag_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_taken_0; // @[dcache.scala:413:7]
wire [19:0] io_lsu_resp_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7]
wire [11:0] io_lsu_resp_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_pdst_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs1_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs2_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs3_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ppred_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_exception_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_resp_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bypassable_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_mem_size_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_fence_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_amo_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_unique_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_ldst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs3_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_fp_val_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_fp_single_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_resp_0_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_is_hella_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_valid_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_uopc_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_nack_0_bits_uop_inst_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_nack_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7]
wire [33:0] io_lsu_nack_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_iq_type_0; // @[dcache.scala:413:7]
wire [9:0] io_lsu_nack_0_bits_uop_fu_code_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_iw_state_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_br_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_jal_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_br_mask_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_br_tag_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_taken_0; // @[dcache.scala:413:7]
wire [19:0] io_lsu_nack_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7]
wire [11:0] io_lsu_nack_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_pdst_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs1_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs2_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs3_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ppred_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_exception_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_nack_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bypassable_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_mem_size_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_fence_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_amo_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_unique_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_ldst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs3_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_fp_val_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_fp_single_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7]
wire [33:0] io_lsu_nack_0_bits_addr_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_nack_0_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_is_hella_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_valid_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_release_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_release_bits_size_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_release_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_release_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_release_valid_0; // @[dcache.scala:413:7]
wire io_lsu_perf_acquire_0; // @[dcache.scala:413:7]
wire io_lsu_perf_release_0; // @[dcache.scala:413:7]
wire io_lsu_ordered_0; // @[dcache.scala:413:7]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T_1; // @[dcache.scala:779:48]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _meta_0_io_write_valid_T = _meta_0_io_write_ready & _metaWriteArb_io_out_valid; // @[Decoupled.scala:51:35]
wire _data_io_read_0_valid_T = _dataReadArb_io_out_bits_valid_0 & _dataReadArb_io_out_valid; // @[dcache.scala:463:27, :468:63]
assign _io_lsu_req_ready_T = _metaReadArb_io_in_4_ready & _dataReadArb_io_in_2_ready; // @[dcache.scala:445:27, :463:27, :480:50]
assign io_lsu_req_ready_0 = _io_lsu_req_ready_T; // @[dcache.scala:413:7, :480:50]
wire [27:0] _metaReadArb_io_in_4_bits_req_0_idx_T = io_lsu_req_bits_0_bits_addr_0[33:6]; // @[dcache.scala:413:7, :485:77]
wire [3:0] replay_req_0_uop_ctrl_br_type; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_ctrl_op1_sel; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_op2_sel; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_imm_sel; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_ctrl_op_fcn; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_load; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_sta; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_std; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_uopc; // @[dcache.scala:496:24]
wire [31:0] replay_req_0_uop_inst; // @[dcache.scala:496:24]
wire [31:0] replay_req_0_uop_debug_inst; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_rvc; // @[dcache.scala:496:24]
wire [33:0] replay_req_0_uop_debug_pc; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_iq_type; // @[dcache.scala:496:24]
wire [9:0] replay_req_0_uop_fu_code; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_iw_state; // @[dcache.scala:496:24]
wire replay_req_0_uop_iw_p1_poisoned; // @[dcache.scala:496:24]
wire replay_req_0_uop_iw_p2_poisoned; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_br; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_jalr; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_jal; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_sfb; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_br_mask; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_br_tag; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_ftq_idx; // @[dcache.scala:496:24]
wire replay_req_0_uop_edge_inst; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_pc_lob; // @[dcache.scala:496:24]
wire replay_req_0_uop_taken; // @[dcache.scala:496:24]
wire [19:0] replay_req_0_uop_imm_packed; // @[dcache.scala:496:24]
wire [11:0] replay_req_0_uop_csr_addr; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_rob_idx; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_ldq_idx; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_stq_idx; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_rxq_idx; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_pdst; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_prs1; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_prs2; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_prs3; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_ppred; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs1_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs2_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs3_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_ppred_busy; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_stale_pdst; // @[dcache.scala:496:24]
wire replay_req_0_uop_exception; // @[dcache.scala:496:24]
wire [63:0] replay_req_0_uop_exc_cause; // @[dcache.scala:496:24]
wire replay_req_0_uop_bypassable; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_mem_cmd; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_mem_size; // @[dcache.scala:496:24]
wire replay_req_0_uop_mem_signed; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_fence; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_fencei; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_amo; // @[dcache.scala:496:24]
wire replay_req_0_uop_uses_ldq; // @[dcache.scala:496:24]
wire replay_req_0_uop_uses_stq; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_sys_pc2epc; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_unique; // @[dcache.scala:496:24]
wire replay_req_0_uop_flush_on_commit; // @[dcache.scala:496:24]
wire replay_req_0_uop_ldst_is_rs1; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_ldst; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs1; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs2; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs3; // @[dcache.scala:496:24]
wire replay_req_0_uop_ldst_val; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_dst_rtype; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_lrs1_rtype; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_lrs2_rtype; // @[dcache.scala:496:24]
wire replay_req_0_uop_frs3_en; // @[dcache.scala:496:24]
wire replay_req_0_uop_fp_val; // @[dcache.scala:496:24]
wire replay_req_0_uop_fp_single; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_pf_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_ae_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_ma_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_bp_debug_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_bp_xcpt_if; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_debug_fsrc; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_debug_tsrc; // @[dcache.scala:496:24]
wire [33:0] replay_req_0_addr; // @[dcache.scala:496:24]
wire [63:0] replay_req_0_data; // @[dcache.scala:496:24]
wire replay_req_0_is_hella; // @[dcache.scala:496:24]
wire [27:0] _metaReadArb_io_in_0_bits_req_0_idx_T = _mshrs_io_replay_bits_addr[33:6]; // @[dcache.scala:433:21, :506:72]
wire [33:0] mshr_read_req_0_addr; // @[dcache.scala:517:27]
wire [25:0] _mshr_read_req_0_addr_T = {_mshrs_io_meta_read_bits_tag, _mshrs_io_meta_read_bits_idx}; // @[dcache.scala:433:21, :520:35]
wire [31:0] _mshr_read_req_0_addr_T_1 = {_mshr_read_req_0_addr_T, 6'h0}; // @[dcache.scala:520:{35,94}]
assign mshr_read_req_0_addr = {2'h0, _mshr_read_req_0_addr_T_1}; // @[dcache.scala:517:27, :520:{29,94}]
wire _wb_io_meta_read_ready_T; // @[dcache.scala:542:55]
wire _wb_fire_T = _wb_io_meta_read_ready_T & _wb_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _wb_io_data_req_ready_T; // @[dcache.scala:547:55]
wire _wb_fire_T_1 = _wb_io_data_req_ready_T & _wb_io_data_req_valid; // @[Decoupled.scala:51:35]
wire wb_fire = _wb_fire_T & _wb_fire_T_1; // @[Decoupled.scala:51:35]
wire [33:0] wb_req_0_addr; // @[dcache.scala:532:20]
wire [31:0] _wb_req_0_addr_T = {_wb_io_meta_read_bits_tag, _wb_io_data_req_bits_addr}; // @[dcache.scala:431:18, :535:28]
assign wb_req_0_addr = {2'h0, _wb_req_0_addr_T}; // @[dcache.scala:532:20, :535:{22,28}]
wire _GEN = _metaReadArb_io_in_2_ready & _dataReadArb_io_in_1_ready; // @[dcache.scala:445:27, :463:27, :542:55]
assign _wb_io_meta_read_ready_T = _GEN; // @[dcache.scala:542:55]
assign _wb_io_data_req_ready_T = _GEN; // @[dcache.scala:542:55, :547:55]
wire prober_fire = _metaReadArb_io_in_1_ready & _prober_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire [33:0] prober_req_0_addr; // @[dcache.scala:553:26]
wire [25:0] _prober_req_0_addr_T = {_prober_io_meta_read_bits_tag, _prober_io_meta_read_bits_idx}; // @[dcache.scala:432:22, :556:32]
wire [31:0] _prober_req_0_addr_T_1 = {_prober_req_0_addr_T, 6'h0}; // @[dcache.scala:556:{32,93}]
assign prober_req_0_addr = {2'h0, _prober_req_0_addr_T_1}; // @[dcache.scala:553:26, :556:{26,93}]
wire _T_7 = io_lsu_req_ready_0 & io_lsu_req_valid_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T; // @[Decoupled.scala:51:35]
assign _s0_valid_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_req_T; // @[Decoupled.scala:51:35]
assign _s0_req_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_type_T; // @[Decoupled.scala:51:35]
assign _s0_type_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T = _T_7; // @[Decoupled.scala:51:35]
wire _s1_valid_T_7; // @[Decoupled.scala:51:35]
assign _s1_valid_T_7 = _T_7; // @[Decoupled.scala:51:35]
wire _mshrs_io_replay_ready_T; // @[dcache.scala:502:58]
wire _GEN_0 = _mshrs_io_replay_ready_T & _mshrs_io_replay_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_1; // @[Decoupled.scala:51:35]
assign _s0_valid_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_1; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T_2 = _s0_valid_T_1 | wb_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_3 = _s0_valid_T_2 | prober_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_4 = _s0_valid_T_3; // @[dcache.scala:580:{54,69}]
wire _GEN_1 = _metaReadArb_io_in_3_ready & _mshrs_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_5; // @[Decoupled.scala:51:35]
assign _s0_valid_T_5 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_1; // @[Decoupled.scala:51:35]
assign _s0_req_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_type_T_1; // @[Decoupled.scala:51:35]
assign _s0_type_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_valid_T_6 = _s0_valid_T_4 | _s0_valid_T_5; // @[Decoupled.scala:51:35]
wire _s0_valid_T_7_0 = _s0_valid_T_6; // @[dcache.scala:580:{21,86}]
wire s0_valid_0 = _s0_valid_T ? _s0_valid_WIRE_0 : _s0_valid_T_7_0; // @[Decoupled.scala:51:35]
wire _s1_valid_T_3 = s0_valid_0; // @[dcache.scala:579:21, :605:74]
wire [6:0] _s0_req_T_2_0_uop_uopc = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_debug_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_rvc = ~_s0_req_T_1 & replay_req_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [33:0] _s0_req_T_2_0_uop_debug_pc = _s0_req_T_1 ? 34'h0 : replay_req_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_iq_type = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] _s0_req_T_2_0_uop_fu_code = _s0_req_T_1 ? 10'h0 : replay_req_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ctrl_br_type = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_ctrl_op1_sel = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_op2_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_imm_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ctrl_op_fcn = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_fcn_dw = ~_s0_req_T_1 & replay_req_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_csr_cmd = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_load = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_sta = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_std = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_iw_state = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p1_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p2_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_br = ~_s0_req_T_1 & replay_req_0_uop_is_br; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_jalr = ~_s0_req_T_1 & replay_req_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_jal = ~_s0_req_T_1 & replay_req_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sfb = ~_s0_req_T_1 & replay_req_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_br_mask = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_br_tag = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ftq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_edge_inst = ~_s0_req_T_1 & replay_req_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_pc_lob = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_taken = ~_s0_req_T_1 & replay_req_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_2_0_uop_imm_packed = _s0_req_T_1 ? 20'h0 : replay_req_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_2_0_uop_csr_addr = _s0_req_T_1 ? 12'h0 : replay_req_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_rob_idx = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ldq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_stq_idx = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_rxq_idx = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs1 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs2 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs3 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ppred = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs1_busy = ~_s0_req_T_1 & replay_req_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs2_busy = ~_s0_req_T_1 & replay_req_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs3_busy = ~_s0_req_T_1 & replay_req_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ppred_busy = ~_s0_req_T_1 & replay_req_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_stale_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_exception = ~_s0_req_T_1 & replay_req_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_uop_exc_cause = _s0_req_T_1 ? 64'h0 : replay_req_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bypassable = ~_s0_req_T_1 & replay_req_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_mem_cmd = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_mem_size = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_mem_signed = ~_s0_req_T_1 & replay_req_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fence = ~_s0_req_T_1 & replay_req_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fencei = ~_s0_req_T_1 & replay_req_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_amo = ~_s0_req_T_1 & replay_req_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_ldq = ~_s0_req_T_1 & replay_req_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_stq = ~_s0_req_T_1 & replay_req_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sys_pc2epc = ~_s0_req_T_1 & replay_req_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_unique = ~_s0_req_T_1 & replay_req_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_flush_on_commit = ~_s0_req_T_1 & replay_req_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ldst_is_rs1 = ~_s0_req_T_1 & replay_req_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_ldst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs1 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs2 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs3 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ldst_val = ~_s0_req_T_1 & replay_req_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_dst_rtype = _s0_req_T_1 ? 2'h2 : replay_req_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs1_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs2_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_frs3_en = ~_s0_req_T_1 & replay_req_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_val = ~_s0_req_T_1 & replay_req_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_single = ~_s0_req_T_1 & replay_req_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_pf_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ae_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ma_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_debug_if = ~_s0_req_T_1 & replay_req_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_xcpt_if = ~_s0_req_T_1 & replay_req_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_debug_fsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_debug_tsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [33:0] _s0_req_T_2_0_addr = _s0_req_T_1 ? mshr_read_req_0_addr : replay_req_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_data = _s0_req_T_1 ? 64'h0 : replay_req_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_is_hella = ~_s0_req_T_1 & replay_req_0_is_hella; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_3_0_uop_uopc = _s0_req_T_2_0_uop_uopc; // @[dcache.scala:585:21, :586:21]
wire [31:0] _s0_req_T_3_0_uop_inst = _s0_req_T_2_0_uop_inst; // @[dcache.scala:585:21, :586:21]
wire [31:0] _s0_req_T_3_0_uop_debug_inst = _s0_req_T_2_0_uop_debug_inst; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_rvc = _s0_req_T_2_0_uop_is_rvc; // @[dcache.scala:585:21, :586:21]
wire [33:0] _s0_req_T_3_0_uop_debug_pc = _s0_req_T_2_0_uop_debug_pc; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_iq_type = _s0_req_T_2_0_uop_iq_type; // @[dcache.scala:585:21, :586:21]
wire [9:0] _s0_req_T_3_0_uop_fu_code = _s0_req_T_2_0_uop_fu_code; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ctrl_br_type = _s0_req_T_2_0_uop_ctrl_br_type; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_ctrl_op1_sel = _s0_req_T_2_0_uop_ctrl_op1_sel; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_op2_sel = _s0_req_T_2_0_uop_ctrl_op2_sel; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_imm_sel = _s0_req_T_2_0_uop_ctrl_imm_sel; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_ctrl_op_fcn = _s0_req_T_2_0_uop_ctrl_op_fcn; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_fcn_dw = _s0_req_T_2_0_uop_ctrl_fcn_dw; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_csr_cmd = _s0_req_T_2_0_uop_ctrl_csr_cmd; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_load = _s0_req_T_2_0_uop_ctrl_is_load; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_sta = _s0_req_T_2_0_uop_ctrl_is_sta; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_std = _s0_req_T_2_0_uop_ctrl_is_std; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_iw_state = _s0_req_T_2_0_uop_iw_state; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_iw_p1_poisoned = _s0_req_T_2_0_uop_iw_p1_poisoned; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_iw_p2_poisoned = _s0_req_T_2_0_uop_iw_p2_poisoned; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_br = _s0_req_T_2_0_uop_is_br; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_jalr = _s0_req_T_2_0_uop_is_jalr; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_jal = _s0_req_T_2_0_uop_is_jal; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_sfb = _s0_req_T_2_0_uop_is_sfb; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_br_mask = _s0_req_T_2_0_uop_br_mask; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_br_tag = _s0_req_T_2_0_uop_br_tag; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ftq_idx = _s0_req_T_2_0_uop_ftq_idx; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_edge_inst = _s0_req_T_2_0_uop_edge_inst; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_pc_lob = _s0_req_T_2_0_uop_pc_lob; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_taken = _s0_req_T_2_0_uop_taken; // @[dcache.scala:585:21, :586:21]
wire [19:0] _s0_req_T_3_0_uop_imm_packed = _s0_req_T_2_0_uop_imm_packed; // @[dcache.scala:585:21, :586:21]
wire [11:0] _s0_req_T_3_0_uop_csr_addr = _s0_req_T_2_0_uop_csr_addr; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_rob_idx = _s0_req_T_2_0_uop_rob_idx; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ldq_idx = _s0_req_T_2_0_uop_ldq_idx; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_stq_idx = _s0_req_T_2_0_uop_stq_idx; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_rxq_idx = _s0_req_T_2_0_uop_rxq_idx; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_pdst = _s0_req_T_2_0_uop_pdst; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_prs1 = _s0_req_T_2_0_uop_prs1; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_prs2 = _s0_req_T_2_0_uop_prs2; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_prs3 = _s0_req_T_2_0_uop_prs3; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ppred = _s0_req_T_2_0_uop_ppred; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs1_busy = _s0_req_T_2_0_uop_prs1_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs2_busy = _s0_req_T_2_0_uop_prs2_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs3_busy = _s0_req_T_2_0_uop_prs3_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ppred_busy = _s0_req_T_2_0_uop_ppred_busy; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_stale_pdst = _s0_req_T_2_0_uop_stale_pdst; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_exception = _s0_req_T_2_0_uop_exception; // @[dcache.scala:585:21, :586:21]
wire [63:0] _s0_req_T_3_0_uop_exc_cause = _s0_req_T_2_0_uop_exc_cause; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bypassable = _s0_req_T_2_0_uop_bypassable; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_mem_cmd = _s0_req_T_2_0_uop_mem_cmd; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_mem_size = _s0_req_T_2_0_uop_mem_size; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_mem_signed = _s0_req_T_2_0_uop_mem_signed; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_fence = _s0_req_T_2_0_uop_is_fence; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_fencei = _s0_req_T_2_0_uop_is_fencei; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_amo = _s0_req_T_2_0_uop_is_amo; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_uses_ldq = _s0_req_T_2_0_uop_uses_ldq; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_uses_stq = _s0_req_T_2_0_uop_uses_stq; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_sys_pc2epc = _s0_req_T_2_0_uop_is_sys_pc2epc; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_unique = _s0_req_T_2_0_uop_is_unique; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_flush_on_commit = _s0_req_T_2_0_uop_flush_on_commit; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ldst_is_rs1 = _s0_req_T_2_0_uop_ldst_is_rs1; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_ldst = _s0_req_T_2_0_uop_ldst; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs1 = _s0_req_T_2_0_uop_lrs1; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs2 = _s0_req_T_2_0_uop_lrs2; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs3 = _s0_req_T_2_0_uop_lrs3; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ldst_val = _s0_req_T_2_0_uop_ldst_val; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_dst_rtype = _s0_req_T_2_0_uop_dst_rtype; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_lrs1_rtype = _s0_req_T_2_0_uop_lrs1_rtype; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_lrs2_rtype = _s0_req_T_2_0_uop_lrs2_rtype; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_frs3_en = _s0_req_T_2_0_uop_frs3_en; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_fp_val = _s0_req_T_2_0_uop_fp_val; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_fp_single = _s0_req_T_2_0_uop_fp_single; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_pf_if = _s0_req_T_2_0_uop_xcpt_pf_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_ae_if = _s0_req_T_2_0_uop_xcpt_ae_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_ma_if = _s0_req_T_2_0_uop_xcpt_ma_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bp_debug_if = _s0_req_T_2_0_uop_bp_debug_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bp_xcpt_if = _s0_req_T_2_0_uop_bp_xcpt_if; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_debug_fsrc = _s0_req_T_2_0_uop_debug_fsrc; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_debug_tsrc = _s0_req_T_2_0_uop_debug_tsrc; // @[dcache.scala:585:21, :586:21]
wire [33:0] _s0_req_T_3_0_addr = _s0_req_T_2_0_addr; // @[dcache.scala:585:21, :586:21]
wire [63:0] _s0_req_T_3_0_data = _s0_req_T_2_0_data; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_is_hella = _s0_req_T_2_0_is_hella; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_4_0_uop_uopc = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_4_0_uop_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_4_0_uop_debug_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_rvc = ~prober_fire & _s0_req_T_3_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [33:0] _s0_req_T_4_0_uop_debug_pc = prober_fire ? 34'h0 : _s0_req_T_3_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_iq_type = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] _s0_req_T_4_0_uop_fu_code = prober_fire ? 10'h0 : _s0_req_T_3_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ctrl_br_type = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_ctrl_op1_sel = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_op2_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_imm_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ctrl_op_fcn = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_fcn_dw = ~prober_fire & _s0_req_T_3_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_csr_cmd = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_load = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_sta = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_std = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_iw_state = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p1_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p2_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_br = ~prober_fire & _s0_req_T_3_0_uop_is_br; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_jalr = ~prober_fire & _s0_req_T_3_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_jal = ~prober_fire & _s0_req_T_3_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sfb = ~prober_fire & _s0_req_T_3_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_br_mask = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_br_tag = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ftq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_edge_inst = ~prober_fire & _s0_req_T_3_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_pc_lob = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_taken = ~prober_fire & _s0_req_T_3_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_4_0_uop_imm_packed = prober_fire ? 20'h0 : _s0_req_T_3_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_4_0_uop_csr_addr = prober_fire ? 12'h0 : _s0_req_T_3_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_rob_idx = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ldq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_stq_idx = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_rxq_idx = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs1 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs2 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs3 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ppred = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs1_busy = ~prober_fire & _s0_req_T_3_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs2_busy = ~prober_fire & _s0_req_T_3_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs3_busy = ~prober_fire & _s0_req_T_3_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ppred_busy = ~prober_fire & _s0_req_T_3_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_stale_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_exception = ~prober_fire & _s0_req_T_3_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_uop_exc_cause = prober_fire ? 64'h0 : _s0_req_T_3_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bypassable = ~prober_fire & _s0_req_T_3_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_mem_cmd = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_mem_size = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_mem_signed = ~prober_fire & _s0_req_T_3_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fence = ~prober_fire & _s0_req_T_3_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fencei = ~prober_fire & _s0_req_T_3_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_amo = ~prober_fire & _s0_req_T_3_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_ldq = ~prober_fire & _s0_req_T_3_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_stq = ~prober_fire & _s0_req_T_3_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sys_pc2epc = ~prober_fire & _s0_req_T_3_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_unique = ~prober_fire & _s0_req_T_3_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_flush_on_commit = ~prober_fire & _s0_req_T_3_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ldst_is_rs1 = ~prober_fire & _s0_req_T_3_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_ldst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs1 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs2 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs3 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ldst_val = ~prober_fire & _s0_req_T_3_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_dst_rtype = prober_fire ? 2'h2 : _s0_req_T_3_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs1_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs2_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_frs3_en = ~prober_fire & _s0_req_T_3_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_val = ~prober_fire & _s0_req_T_3_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_single = ~prober_fire & _s0_req_T_3_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_pf_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ae_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ma_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_debug_if = ~prober_fire & _s0_req_T_3_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_xcpt_if = ~prober_fire & _s0_req_T_3_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_debug_fsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_debug_tsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [33:0] _s0_req_T_4_0_addr = prober_fire ? prober_req_0_addr : _s0_req_T_3_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_data = prober_fire ? 64'h0 : _s0_req_T_3_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_is_hella = ~prober_fire & _s0_req_T_3_0_is_hella; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_5_0_uop_uopc = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_uopc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [31:0] _s0_req_T_5_0_uop_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [31:0] _s0_req_T_5_0_uop_debug_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_debug_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_rvc = ~wb_fire & _s0_req_T_4_0_uop_is_rvc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [33:0] _s0_req_T_5_0_uop_debug_pc = wb_fire ? 34'h0 : _s0_req_T_4_0_uop_debug_pc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_iq_type = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_iq_type; // @[dcache.scala:531:38, :583:21, :584:21]
wire [9:0] _s0_req_T_5_0_uop_fu_code = wb_fire ? 10'h0 : _s0_req_T_4_0_uop_fu_code; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ctrl_br_type = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ctrl_br_type; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_ctrl_op1_sel = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_ctrl_op1_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_op2_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_op2_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_imm_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_imm_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_ctrl_op_fcn = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ctrl_op_fcn; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_fcn_dw = ~wb_fire & _s0_req_T_4_0_uop_ctrl_fcn_dw; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_csr_cmd = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_csr_cmd; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_load = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_load; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_sta = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_sta; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_std = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_std; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_iw_state = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_iw_state; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_iw_p1_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p1_poisoned; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_iw_p2_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p2_poisoned; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_br = ~wb_fire & _s0_req_T_4_0_uop_is_br; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_jalr = ~wb_fire & _s0_req_T_4_0_uop_is_jalr; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_jal = ~wb_fire & _s0_req_T_4_0_uop_is_jal; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_sfb = ~wb_fire & _s0_req_T_4_0_uop_is_sfb; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_br_mask = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_br_mask; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_br_tag = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_br_tag; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ftq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ftq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_edge_inst = ~wb_fire & _s0_req_T_4_0_uop_edge_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_pc_lob = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_pc_lob; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_taken = ~wb_fire & _s0_req_T_4_0_uop_taken; // @[dcache.scala:531:38, :583:21, :584:21]
wire [19:0] _s0_req_T_5_0_uop_imm_packed = wb_fire ? 20'h0 : _s0_req_T_4_0_uop_imm_packed; // @[dcache.scala:531:38, :583:21, :584:21]
wire [11:0] _s0_req_T_5_0_uop_csr_addr = wb_fire ? 12'h0 : _s0_req_T_4_0_uop_csr_addr; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_rob_idx = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_rob_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ldq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ldq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_stq_idx = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_stq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_rxq_idx = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_rxq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_pdst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_prs1 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_prs2 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs2; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_prs3 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs3; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ppred = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ppred; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs1_busy = ~wb_fire & _s0_req_T_4_0_uop_prs1_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs2_busy = ~wb_fire & _s0_req_T_4_0_uop_prs2_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs3_busy = ~wb_fire & _s0_req_T_4_0_uop_prs3_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ppred_busy = ~wb_fire & _s0_req_T_4_0_uop_ppred_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_stale_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_stale_pdst; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_exception = ~wb_fire & _s0_req_T_4_0_uop_exception; // @[dcache.scala:531:38, :583:21, :584:21]
wire [63:0] _s0_req_T_5_0_uop_exc_cause = wb_fire ? 64'h0 : _s0_req_T_4_0_uop_exc_cause; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bypassable = ~wb_fire & _s0_req_T_4_0_uop_bypassable; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_mem_cmd = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_mem_cmd; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_mem_size = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_mem_size; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_mem_signed = ~wb_fire & _s0_req_T_4_0_uop_mem_signed; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_fence = ~wb_fire & _s0_req_T_4_0_uop_is_fence; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_fencei = ~wb_fire & _s0_req_T_4_0_uop_is_fencei; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_amo = ~wb_fire & _s0_req_T_4_0_uop_is_amo; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_uses_ldq = ~wb_fire & _s0_req_T_4_0_uop_uses_ldq; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_uses_stq = ~wb_fire & _s0_req_T_4_0_uop_uses_stq; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_sys_pc2epc = ~wb_fire & _s0_req_T_4_0_uop_is_sys_pc2epc; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_unique = ~wb_fire & _s0_req_T_4_0_uop_is_unique; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_flush_on_commit = ~wb_fire & _s0_req_T_4_0_uop_flush_on_commit; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ldst_is_rs1 = ~wb_fire & _s0_req_T_4_0_uop_ldst_is_rs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_ldst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_ldst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs1 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs2 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs2; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs3 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs3; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ldst_val = ~wb_fire & _s0_req_T_4_0_uop_ldst_val; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_dst_rtype = wb_fire ? 2'h2 : _s0_req_T_4_0_uop_dst_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_lrs1_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs1_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_lrs2_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs2_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_frs3_en = ~wb_fire & _s0_req_T_4_0_uop_frs3_en; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_fp_val = ~wb_fire & _s0_req_T_4_0_uop_fp_val; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_fp_single = ~wb_fire & _s0_req_T_4_0_uop_fp_single; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_pf_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_pf_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_ae_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ae_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_ma_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ma_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bp_debug_if = ~wb_fire & _s0_req_T_4_0_uop_bp_debug_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bp_xcpt_if = ~wb_fire & _s0_req_T_4_0_uop_bp_xcpt_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_debug_fsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_fsrc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_debug_tsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_tsrc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [33:0] _s0_req_T_5_0_addr = wb_fire ? wb_req_0_addr : _s0_req_T_4_0_addr; // @[dcache.scala:531:38, :532:20, :583:21, :584:21]
wire [63:0] _s0_req_T_5_0_data = wb_fire ? 64'h0 : _s0_req_T_4_0_data; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_is_hella = ~wb_fire & _s0_req_T_4_0_is_hella; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] s0_req_0_uop_uopc = _s0_req_T ? _s0_req_WIRE_0_uop_uopc : _s0_req_T_5_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] s0_req_0_uop_inst = _s0_req_T ? _s0_req_WIRE_0_uop_inst : _s0_req_T_5_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] s0_req_0_uop_debug_inst = _s0_req_T ? _s0_req_WIRE_0_uop_debug_inst : _s0_req_T_5_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_rvc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rvc : _s0_req_T_5_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [33:0] s0_req_0_uop_debug_pc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_pc : _s0_req_T_5_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_iq_type = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type : _s0_req_T_5_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] s0_req_0_uop_fu_code = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code : _s0_req_T_5_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ctrl_br_type = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_br_type : _s0_req_T_5_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_ctrl_op1_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op1_sel : _s0_req_T_5_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_op2_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op2_sel : _s0_req_T_5_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_imm_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_imm_sel : _s0_req_T_5_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ctrl_op_fcn = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op_fcn : _s0_req_T_5_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_fcn_dw = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_fcn_dw : _s0_req_T_5_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_csr_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_csr_cmd : _s0_req_T_5_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_load = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_load : _s0_req_T_5_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_sta = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_sta : _s0_req_T_5_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_std = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_std : _s0_req_T_5_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_iw_state = _s0_req_T ? _s0_req_WIRE_0_uop_iw_state : _s0_req_T_5_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p1_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_poisoned : _s0_req_T_5_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p2_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_poisoned : _s0_req_T_5_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_br = _s0_req_T ? _s0_req_WIRE_0_uop_is_br : _s0_req_T_5_0_uop_is_br; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_jalr = _s0_req_T ? _s0_req_WIRE_0_uop_is_jalr : _s0_req_T_5_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_jal = _s0_req_T ? _s0_req_WIRE_0_uop_is_jal : _s0_req_T_5_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sfb = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfb : _s0_req_T_5_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_br_mask = _s0_req_T ? _s0_req_WIRE_0_uop_br_mask : _s0_req_T_5_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_br_tag = _s0_req_T ? _s0_req_WIRE_0_uop_br_tag : _s0_req_T_5_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ftq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ftq_idx : _s0_req_T_5_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_edge_inst = _s0_req_T ? _s0_req_WIRE_0_uop_edge_inst : _s0_req_T_5_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_pc_lob = _s0_req_T ? _s0_req_WIRE_0_uop_pc_lob : _s0_req_T_5_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_taken = _s0_req_T ? _s0_req_WIRE_0_uop_taken : _s0_req_T_5_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] s0_req_0_uop_imm_packed = _s0_req_T ? _s0_req_WIRE_0_uop_imm_packed : _s0_req_T_5_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] s0_req_0_uop_csr_addr = _s0_req_T ? _s0_req_WIRE_0_uop_csr_addr : _s0_req_T_5_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_rob_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rob_idx : _s0_req_T_5_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ldq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ldq_idx : _s0_req_T_5_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_stq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_stq_idx : _s0_req_T_5_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_rxq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rxq_idx : _s0_req_T_5_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_pdst : _s0_req_T_5_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs1 = _s0_req_T ? _s0_req_WIRE_0_uop_prs1 : _s0_req_T_5_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs2 = _s0_req_T ? _s0_req_WIRE_0_uop_prs2 : _s0_req_T_5_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs3 = _s0_req_T ? _s0_req_WIRE_0_uop_prs3 : _s0_req_T_5_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ppred = _s0_req_T ? _s0_req_WIRE_0_uop_ppred : _s0_req_T_5_0_uop_ppred; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs1_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs1_busy : _s0_req_T_5_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs2_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs2_busy : _s0_req_T_5_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs3_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs3_busy : _s0_req_T_5_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ppred_busy = _s0_req_T ? _s0_req_WIRE_0_uop_ppred_busy : _s0_req_T_5_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_stale_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_stale_pdst : _s0_req_T_5_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_exception = _s0_req_T ? _s0_req_WIRE_0_uop_exception : _s0_req_T_5_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_uop_exc_cause = _s0_req_T ? _s0_req_WIRE_0_uop_exc_cause : _s0_req_T_5_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bypassable = _s0_req_T ? _s0_req_WIRE_0_uop_bypassable : _s0_req_T_5_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_mem_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_mem_cmd : _s0_req_T_5_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_mem_size = _s0_req_T ? _s0_req_WIRE_0_uop_mem_size : _s0_req_T_5_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_mem_signed = _s0_req_T ? _s0_req_WIRE_0_uop_mem_signed : _s0_req_T_5_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fence = _s0_req_T ? _s0_req_WIRE_0_uop_is_fence : _s0_req_T_5_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fencei = _s0_req_T ? _s0_req_WIRE_0_uop_is_fencei : _s0_req_T_5_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_amo = _s0_req_T ? _s0_req_WIRE_0_uop_is_amo : _s0_req_T_5_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_ldq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_ldq : _s0_req_T_5_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_stq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_stq : _s0_req_T_5_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sys_pc2epc = _s0_req_T ? _s0_req_WIRE_0_uop_is_sys_pc2epc : _s0_req_T_5_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_unique = _s0_req_T ? _s0_req_WIRE_0_uop_is_unique : _s0_req_T_5_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_flush_on_commit = _s0_req_T ? _s0_req_WIRE_0_uop_flush_on_commit : _s0_req_T_5_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ldst_is_rs1 = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_is_rs1 : _s0_req_T_5_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_ldst : _s0_req_T_5_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs1 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1 : _s0_req_T_5_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs2 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2 : _s0_req_T_5_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs3 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs3 : _s0_req_T_5_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ldst_val = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_val : _s0_req_T_5_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_dst_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_dst_rtype : _s0_req_T_5_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs1_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1_rtype : _s0_req_T_5_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs2_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2_rtype : _s0_req_T_5_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_frs3_en = _s0_req_T ? _s0_req_WIRE_0_uop_frs3_en : _s0_req_T_5_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_val = _s0_req_T ? _s0_req_WIRE_0_uop_fp_val : _s0_req_T_5_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_single = _s0_req_T ? _s0_req_WIRE_0_uop_fp_single : _s0_req_T_5_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_pf_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_pf_if : _s0_req_T_5_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ae_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ae_if : _s0_req_T_5_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ma_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ma_if : _s0_req_T_5_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_debug_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_debug_if : _s0_req_T_5_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_xcpt_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_xcpt_if : _s0_req_T_5_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_debug_fsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_fsrc : _s0_req_T_5_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_debug_tsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_tsrc : _s0_req_T_5_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [33:0] s0_req_0_addr = _s0_req_T ? _s0_req_WIRE_0_addr : _s0_req_T_5_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_data = _s0_req_T ? _s0_req_WIRE_0_data : _s0_req_T_5_0_data; // @[Decoupled.scala:51:35]
wire s0_req_0_is_hella = _s0_req_T ? _s0_req_WIRE_0_is_hella : _s0_req_T_5_0_is_hella; // @[Decoupled.scala:51:35]
wire [3:0] _s1_req_0_uop_br_mask_T_1 = s0_req_0_uop_br_mask; // @[util.scala:85:25]
wire [2:0] _s0_type_T_2 = _s0_type_T_1 ? 3'h3 : 3'h0; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_3 = _s0_type_T_2; // @[dcache.scala:591:21, :592:21]
wire [2:0] _s0_type_T_4 = prober_fire ? 3'h1 : _s0_type_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_5 = wb_fire ? 3'h2 : _s0_type_T_4; // @[dcache.scala:531:38, :589:21, :590:21]
wire [2:0] s0_type = _s0_type_T ? 3'h4 : _s0_type_T_5; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_2 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_3 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_4 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_5 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_6 = _s0_send_resp_or_nack_T_2 | _s0_send_resp_or_nack_T_3; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_7 = _s0_send_resp_or_nack_T_6 | _s0_send_resp_or_nack_T_4; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_8 = _s0_send_resp_or_nack_T_7 | _s0_send_resp_or_nack_T_5; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_9 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_10 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_11 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_12 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_13 = _s0_send_resp_or_nack_T_9 | _s0_send_resp_or_nack_T_10; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_14 = _s0_send_resp_or_nack_T_13 | _s0_send_resp_or_nack_T_11; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_15 = _s0_send_resp_or_nack_T_14 | _s0_send_resp_or_nack_T_12; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_16 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_17 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_18 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_19 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_20 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_21 = _s0_send_resp_or_nack_T_16 | _s0_send_resp_or_nack_T_17; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_22 = _s0_send_resp_or_nack_T_21 | _s0_send_resp_or_nack_T_18; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_23 = _s0_send_resp_or_nack_T_22 | _s0_send_resp_or_nack_T_19; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_24 = _s0_send_resp_or_nack_T_23 | _s0_send_resp_or_nack_T_20; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_25 = _s0_send_resp_or_nack_T_15 | _s0_send_resp_or_nack_T_24; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_26 = _s0_send_resp_or_nack_T_8 | _s0_send_resp_or_nack_T_25; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_27 = _s0_send_resp_or_nack_T_1 & _s0_send_resp_or_nack_T_26; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_28 = _s0_send_resp_or_nack_T_27; // @[dcache.scala:597:{16,38}]
wire _s0_send_resp_or_nack_T_29 = _s0_send_resp_or_nack_T_28; // @[dcache.scala:597:{16,117}]
wire _s0_send_resp_or_nack_WIRE_0 = _s0_send_resp_or_nack_T_29; // @[dcache.scala:597:{12,117}]
wire s0_send_resp_or_nack_0 = _s0_send_resp_or_nack_T ? s0_valid_0 : _s0_send_resp_or_nack_WIRE_0; // @[Decoupled.scala:51:35]
reg [6:0] s1_req_0_uop_uopc; // @[dcache.scala:600:32]
reg [31:0] s1_req_0_uop_inst; // @[dcache.scala:600:32]
reg [31:0] s1_req_0_uop_debug_inst; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_rvc; // @[dcache.scala:600:32]
reg [33:0] s1_req_0_uop_debug_pc; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_iq_type; // @[dcache.scala:600:32]
reg [9:0] s1_req_0_uop_fu_code; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ctrl_br_type; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_ctrl_op1_sel; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_op2_sel; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_imm_sel; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_ctrl_op_fcn; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_load; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_sta; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_std; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_iw_state; // @[dcache.scala:600:32]
reg s1_req_0_uop_iw_p1_poisoned; // @[dcache.scala:600:32]
reg s1_req_0_uop_iw_p2_poisoned; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_br; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_jalr; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_jal; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_sfb; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_br_mask; // @[dcache.scala:600:32]
wire [3:0] _s2_req_0_uop_br_mask_T_1 = s1_req_0_uop_br_mask; // @[util.scala:85:25]
reg [1:0] s1_req_0_uop_br_tag; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ftq_idx; // @[dcache.scala:600:32]
reg s1_req_0_uop_edge_inst; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_pc_lob; // @[dcache.scala:600:32]
reg s1_req_0_uop_taken; // @[dcache.scala:600:32]
reg [19:0] s1_req_0_uop_imm_packed; // @[dcache.scala:600:32]
reg [11:0] s1_req_0_uop_csr_addr; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_rob_idx; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ldq_idx; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_stq_idx; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_rxq_idx; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_pdst; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_prs1; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_prs2; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_prs3; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ppred; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs1_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs2_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs3_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_ppred_busy; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_stale_pdst; // @[dcache.scala:600:32]
reg s1_req_0_uop_exception; // @[dcache.scala:600:32]
reg [63:0] s1_req_0_uop_exc_cause; // @[dcache.scala:600:32]
reg s1_req_0_uop_bypassable; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_mem_cmd; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_mem_size; // @[dcache.scala:600:32]
reg s1_req_0_uop_mem_signed; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_fence; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_fencei; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_amo; // @[dcache.scala:600:32]
reg s1_req_0_uop_uses_ldq; // @[dcache.scala:600:32]
reg s1_req_0_uop_uses_stq; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_sys_pc2epc; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_unique; // @[dcache.scala:600:32]
reg s1_req_0_uop_flush_on_commit; // @[dcache.scala:600:32]
reg s1_req_0_uop_ldst_is_rs1; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_ldst; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs1; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs2; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs3; // @[dcache.scala:600:32]
reg s1_req_0_uop_ldst_val; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_dst_rtype; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_lrs1_rtype; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_lrs2_rtype; // @[dcache.scala:600:32]
reg s1_req_0_uop_frs3_en; // @[dcache.scala:600:32]
reg s1_req_0_uop_fp_val; // @[dcache.scala:600:32]
reg s1_req_0_uop_fp_single; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_pf_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_ae_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_ma_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_bp_debug_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_bp_xcpt_if; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_debug_fsrc; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_debug_tsrc; // @[dcache.scala:600:32]
reg [33:0] s1_req_0_addr; // @[dcache.scala:600:32]
reg [63:0] s1_req_0_data; // @[dcache.scala:600:32]
reg s1_req_0_is_hella; // @[dcache.scala:600:32]
wire _s2_store_failed_T_2; // @[dcache.scala:742:67]
wire s2_store_failed; // @[dcache.scala:603:29]
wire _s1_valid_T_6 = _s1_valid_T_3; // @[dcache.scala:605:74, :606:76]
wire _s1_valid_T_8 = s2_store_failed & _s1_valid_T_7; // @[Decoupled.scala:51:35]
wire _s1_valid_T_9 = _s1_valid_T_8 & s0_req_0_uop_uses_stq; // @[dcache.scala:582:21, :608:{44,63}]
wire _s1_valid_T_10 = ~_s1_valid_T_9; // @[dcache.scala:608:{26,63}]
wire _s1_valid_T_11 = _s1_valid_T_6 & _s1_valid_T_10; // @[dcache.scala:606:76, :607:74, :608:26]
reg s1_valid_REG; // @[dcache.scala:605:25]
wire s1_valid_0 = s1_valid_REG; // @[dcache.scala:427:49, :605:25]
reg REG; // @[dcache.scala:611:43]
reg REG_1; // @[dcache.scala:611:72]
wire [3:0] _s1_nack_T = s1_req_0_addr[9:6]; // @[dcache.scala:600:32, :613:43]
wire [3:0] _s1_wb_idx_matches_T = s1_req_0_addr[9:6]; // @[dcache.scala:600:32, :613:43, :630:52]
wire _s1_nack_T_1 = _s1_nack_T == _prober_io_meta_write_bits_idx; // @[dcache.scala:432:22, :613:{43,59}]
wire _s1_nack_T_2 = ~_prober_io_req_ready; // @[dcache.scala:432:22, :613:96]
wire s1_nack_0 = _s1_nack_T_1 & _s1_nack_T_2; // @[dcache.scala:613:{59,93,96}]
wire _s2_nack_hit_WIRE_0 = s1_nack_0; // @[dcache.scala:613:93, :722:39]
reg s1_send_resp_or_nack_0; // @[dcache.scala:614:37]
reg [2:0] s1_type; // @[dcache.scala:615:32]
reg [1:0] s1_mshr_meta_read_way_en; // @[dcache.scala:617:41]
reg [1:0] s1_replay_way_en; // @[dcache.scala:618:41]
reg [1:0] s1_wb_way_en; // @[dcache.scala:619:41]
wire [23:0] _s1_tag_eq_way_T = s1_req_0_addr[33:10]; // @[dcache.scala:600:32, :623:95]
wire [23:0] _s1_tag_eq_way_T_2 = s1_req_0_addr[33:10]; // @[dcache.scala:600:32, :623:95]
wire _s1_tag_eq_way_T_1 = {2'h0, _meta_0_io_resp_0_tag} == _s1_tag_eq_way_T; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_0 = _s1_tag_eq_way_T_1; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_3 = {2'h0, _meta_0_io_resp_1_tag} == _s1_tag_eq_way_T_2; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_1 = _s1_tag_eq_way_T_3; // @[dcache.scala:622:47, :623:79]
wire [1:0] _s1_tag_eq_way_T_4 = {_s1_tag_eq_way_WIRE_1, _s1_tag_eq_way_WIRE_0}; // @[dcache.scala:622:47, :623:110]
wire [1:0] s1_tag_eq_way_0 = _s1_tag_eq_way_T_4; // @[dcache.scala:427:49, :623:110]
wire _s1_tag_match_way_T = s1_type == 3'h0; // @[dcache.scala:615:32, :625:38]
wire _s1_tag_match_way_T_1 = s1_type == 3'h2; // @[dcache.scala:615:32, :626:38]
wire _s1_tag_match_way_T_2 = s1_type == 3'h3; // @[dcache.scala:615:32, :627:38]
wire _s1_tag_match_way_T_3 = s1_tag_eq_way_0[0]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_4 = |_meta_0_io_resp_0_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_5 = _s1_tag_match_way_T_3 & _s1_tag_match_way_T_4; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_0 = _s1_tag_match_way_T_5; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_6 = s1_tag_eq_way_0[1]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_7 = |_meta_0_io_resp_1_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_8 = _s1_tag_match_way_T_6 & _s1_tag_match_way_T_7; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_1 = _s1_tag_match_way_T_8; // @[dcache.scala:622:47, :628:67]
wire [1:0] _s1_tag_match_way_T_9 = {_s1_tag_match_way_WIRE_1, _s1_tag_match_way_WIRE_0}; // @[dcache.scala:622:47, :628:104]
wire [1:0] _s1_tag_match_way_T_10 = _s1_tag_match_way_T_2 ? s1_mshr_meta_read_way_en : _s1_tag_match_way_T_9; // @[dcache.scala:617:41, :627:{29,38}, :628:104]
wire [1:0] _s1_tag_match_way_T_11 = _s1_tag_match_way_T_1 ? s1_wb_way_en : _s1_tag_match_way_T_10; // @[dcache.scala:619:41, :626:{29,38}, :627:29]
wire [1:0] _s1_tag_match_way_T_12 = _s1_tag_match_way_T ? s1_replay_way_en : _s1_tag_match_way_T_11; // @[dcache.scala:618:41, :625:{29,38}, :626:29]
wire [1:0] s1_tag_match_way_0 = _s1_tag_match_way_T_12; // @[dcache.scala:427:49, :625:29]
wire _s1_wb_idx_matches_T_1 = _s1_wb_idx_matches_T == _wb_io_idx_bits; // @[dcache.scala:431:18, :630:{52,79}]
wire _s1_wb_idx_matches_T_2 = _s1_wb_idx_matches_T_1 & _wb_io_idx_valid; // @[dcache.scala:431:18, :630:{79,99}]
wire s1_wb_idx_matches_0 = _s1_wb_idx_matches_T_2; // @[dcache.scala:427:49, :630:99]
reg [6:0] s2_req_0_uop_uopc; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_uopc = s2_req_0_uop_uopc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uopc = s2_req_0_uop_uopc; // @[util.scala:101:23]
reg [31:0] s2_req_0_uop_inst; // @[dcache.scala:632:25]
wire [31:0] cache_resp_0_bits_uop_inst = s2_req_0_uop_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_inst = s2_req_0_uop_inst; // @[util.scala:101:23]
reg [31:0] s2_req_0_uop_debug_inst; // @[dcache.scala:632:25]
wire [31:0] cache_resp_0_bits_uop_debug_inst = s2_req_0_uop_debug_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_inst = s2_req_0_uop_debug_inst; // @[util.scala:101:23]
reg s2_req_0_uop_is_rvc; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_rvc = s2_req_0_uop_is_rvc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_rvc = s2_req_0_uop_is_rvc; // @[util.scala:101:23]
reg [33:0] s2_req_0_uop_debug_pc; // @[dcache.scala:632:25]
wire [33:0] cache_resp_0_bits_uop_debug_pc = s2_req_0_uop_debug_pc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_pc = s2_req_0_uop_debug_pc; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_iq_type; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_iq_type = s2_req_0_uop_iq_type; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iq_type = s2_req_0_uop_iq_type; // @[util.scala:101:23]
reg [9:0] s2_req_0_uop_fu_code; // @[dcache.scala:632:25]
wire [9:0] cache_resp_0_bits_uop_fu_code = s2_req_0_uop_fu_code; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fu_code = s2_req_0_uop_fu_code; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ctrl_br_type; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_ctrl_op1_sel; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_op2_sel; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_imm_sel; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_ctrl_op_fcn; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_load; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_sta; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_std; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_iw_state; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_iw_state = s2_req_0_uop_iw_state; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_state = s2_req_0_uop_iw_state; // @[util.scala:101:23]
reg s2_req_0_uop_iw_p1_poisoned; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned; // @[util.scala:101:23]
reg s2_req_0_uop_iw_p2_poisoned; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned; // @[util.scala:101:23]
reg s2_req_0_uop_is_br; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_br = s2_req_0_uop_is_br; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_br = s2_req_0_uop_is_br; // @[util.scala:101:23]
reg s2_req_0_uop_is_jalr; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_jalr = s2_req_0_uop_is_jalr; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_jalr = s2_req_0_uop_is_jalr; // @[util.scala:101:23]
reg s2_req_0_uop_is_jal; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_jal = s2_req_0_uop_is_jal; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_jal = s2_req_0_uop_is_jal; // @[util.scala:101:23]
reg s2_req_0_uop_is_sfb; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_sfb = s2_req_0_uop_is_sfb; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_sfb = s2_req_0_uop_is_sfb; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_br_mask; // @[dcache.scala:632:25]
wire [3:0] _mshrs_io_req_0_bits_uop_br_mask_T_1 = s2_req_0_uop_br_mask; // @[util.scala:85:25]
wire [3:0] cache_resp_0_bits_uop_br_mask = s2_req_0_uop_br_mask; // @[dcache.scala:632:25, :833:26]
wire [3:0] _io_lsu_nack_0_bits_out_uop_br_mask_T_1 = s2_req_0_uop_br_mask; // @[util.scala:89:21]
reg [1:0] s2_req_0_uop_br_tag; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_br_tag = s2_req_0_uop_br_tag; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_br_tag = s2_req_0_uop_br_tag; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ftq_idx; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ftq_idx = s2_req_0_uop_ftq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ftq_idx = s2_req_0_uop_ftq_idx; // @[util.scala:101:23]
reg s2_req_0_uop_edge_inst; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_edge_inst = s2_req_0_uop_edge_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_edge_inst = s2_req_0_uop_edge_inst; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_pc_lob; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_pc_lob = s2_req_0_uop_pc_lob; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_pc_lob = s2_req_0_uop_pc_lob; // @[util.scala:101:23]
reg s2_req_0_uop_taken; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_taken = s2_req_0_uop_taken; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_taken = s2_req_0_uop_taken; // @[util.scala:101:23]
reg [19:0] s2_req_0_uop_imm_packed; // @[dcache.scala:632:25]
wire [19:0] cache_resp_0_bits_uop_imm_packed = s2_req_0_uop_imm_packed; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_imm_packed = s2_req_0_uop_imm_packed; // @[util.scala:101:23]
reg [11:0] s2_req_0_uop_csr_addr; // @[dcache.scala:632:25]
wire [11:0] cache_resp_0_bits_uop_csr_addr = s2_req_0_uop_csr_addr; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_csr_addr = s2_req_0_uop_csr_addr; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_rob_idx; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_rob_idx = s2_req_0_uop_rob_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_rob_idx = s2_req_0_uop_rob_idx; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ldq_idx; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ldq_idx = s2_req_0_uop_ldq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldq_idx = s2_req_0_uop_ldq_idx; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_stq_idx; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_stq_idx = s2_req_0_uop_stq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_stq_idx = s2_req_0_uop_stq_idx; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_rxq_idx; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_rxq_idx = s2_req_0_uop_rxq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_rxq_idx = s2_req_0_uop_rxq_idx; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_pdst; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_pdst = s2_req_0_uop_pdst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_pdst = s2_req_0_uop_pdst; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_prs1; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_prs1 = s2_req_0_uop_prs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs1 = s2_req_0_uop_prs1; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_prs2; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_prs2 = s2_req_0_uop_prs2; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs2 = s2_req_0_uop_prs2; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_prs3; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_prs3 = s2_req_0_uop_prs3; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs3 = s2_req_0_uop_prs3; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ppred; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ppred = s2_req_0_uop_ppred; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ppred = s2_req_0_uop_ppred; // @[util.scala:101:23]
reg s2_req_0_uop_prs1_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs1_busy = s2_req_0_uop_prs1_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs1_busy = s2_req_0_uop_prs1_busy; // @[util.scala:101:23]
reg s2_req_0_uop_prs2_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs2_busy = s2_req_0_uop_prs2_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs2_busy = s2_req_0_uop_prs2_busy; // @[util.scala:101:23]
reg s2_req_0_uop_prs3_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs3_busy = s2_req_0_uop_prs3_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs3_busy = s2_req_0_uop_prs3_busy; // @[util.scala:101:23]
reg s2_req_0_uop_ppred_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ppred_busy = s2_req_0_uop_ppred_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ppred_busy = s2_req_0_uop_ppred_busy; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_stale_pdst; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_stale_pdst = s2_req_0_uop_stale_pdst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_stale_pdst = s2_req_0_uop_stale_pdst; // @[util.scala:101:23]
reg s2_req_0_uop_exception; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_exception = s2_req_0_uop_exception; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_exception = s2_req_0_uop_exception; // @[util.scala:101:23]
reg [63:0] s2_req_0_uop_exc_cause; // @[dcache.scala:632:25]
wire [63:0] cache_resp_0_bits_uop_exc_cause = s2_req_0_uop_exc_cause; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_exc_cause = s2_req_0_uop_exc_cause; // @[util.scala:101:23]
reg s2_req_0_uop_bypassable; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bypassable = s2_req_0_uop_bypassable; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bypassable = s2_req_0_uop_bypassable; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_mem_cmd; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_mem_cmd = s2_req_0_uop_mem_cmd; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_cmd = s2_req_0_uop_mem_cmd; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_mem_size; // @[dcache.scala:632:25]
wire [1:0] size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18]
wire [1:0] cache_resp_0_bits_uop_mem_size = s2_req_0_uop_mem_size; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_size = s2_req_0_uop_mem_size; // @[util.scala:101:23]
wire [1:0] amoalu_io_mask_size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18]
reg s2_req_0_uop_mem_signed; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_mem_signed = s2_req_0_uop_mem_signed; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_signed = s2_req_0_uop_mem_signed; // @[util.scala:101:23]
reg s2_req_0_uop_is_fence; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_fence = s2_req_0_uop_is_fence; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_fence = s2_req_0_uop_is_fence; // @[util.scala:101:23]
reg s2_req_0_uop_is_fencei; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_fencei = s2_req_0_uop_is_fencei; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_fencei = s2_req_0_uop_is_fencei; // @[util.scala:101:23]
reg s2_req_0_uop_is_amo; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_amo = s2_req_0_uop_is_amo; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_amo = s2_req_0_uop_is_amo; // @[util.scala:101:23]
reg s2_req_0_uop_uses_ldq; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_uses_ldq = s2_req_0_uop_uses_ldq; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uses_ldq = s2_req_0_uop_uses_ldq; // @[util.scala:101:23]
reg s2_req_0_uop_uses_stq; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_uses_stq = s2_req_0_uop_uses_stq; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uses_stq = s2_req_0_uop_uses_stq; // @[util.scala:101:23]
reg s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc; // @[util.scala:101:23]
reg s2_req_0_uop_is_unique; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_unique = s2_req_0_uop_is_unique; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_unique = s2_req_0_uop_is_unique; // @[util.scala:101:23]
reg s2_req_0_uop_flush_on_commit; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_flush_on_commit = s2_req_0_uop_flush_on_commit; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_flush_on_commit = s2_req_0_uop_flush_on_commit; // @[util.scala:101:23]
reg s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_ldst; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_ldst = s2_req_0_uop_ldst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst = s2_req_0_uop_ldst; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs1; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs1 = s2_req_0_uop_lrs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs1 = s2_req_0_uop_lrs1; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs2; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs2 = s2_req_0_uop_lrs2; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs2 = s2_req_0_uop_lrs2; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs3; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs3 = s2_req_0_uop_lrs3; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs3 = s2_req_0_uop_lrs3; // @[util.scala:101:23]
reg s2_req_0_uop_ldst_val; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ldst_val = s2_req_0_uop_ldst_val; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst_val = s2_req_0_uop_ldst_val; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_dst_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_dst_rtype = s2_req_0_uop_dst_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_dst_rtype = s2_req_0_uop_dst_rtype; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_lrs1_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_lrs2_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype; // @[util.scala:101:23]
reg s2_req_0_uop_frs3_en; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_frs3_en = s2_req_0_uop_frs3_en; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_frs3_en = s2_req_0_uop_frs3_en; // @[util.scala:101:23]
reg s2_req_0_uop_fp_val; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_fp_val = s2_req_0_uop_fp_val; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fp_val = s2_req_0_uop_fp_val; // @[util.scala:101:23]
reg s2_req_0_uop_fp_single; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_fp_single = s2_req_0_uop_fp_single; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fp_single = s2_req_0_uop_fp_single; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if; // @[util.scala:101:23]
reg s2_req_0_uop_bp_debug_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bp_debug_if = s2_req_0_uop_bp_debug_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bp_debug_if = s2_req_0_uop_bp_debug_if; // @[util.scala:101:23]
reg s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_debug_fsrc; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_debug_fsrc = s2_req_0_uop_debug_fsrc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_fsrc = s2_req_0_uop_debug_fsrc; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_debug_tsrc; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_debug_tsrc = s2_req_0_uop_debug_tsrc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_tsrc = s2_req_0_uop_debug_tsrc; // @[util.scala:101:23]
reg [33:0] s2_req_0_addr; // @[dcache.scala:632:25]
assign io_lsu_nack_0_bits_out_addr = s2_req_0_addr; // @[util.scala:101:23]
reg [63:0] s2_req_0_data; // @[dcache.scala:632:25]
assign io_lsu_nack_0_bits_out_data = s2_req_0_data; // @[util.scala:101:23]
reg s2_req_0_is_hella; // @[dcache.scala:632:25]
wire cache_resp_0_bits_is_hella = s2_req_0_is_hella; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_is_hella = s2_req_0_is_hella; // @[util.scala:101:23]
reg [2:0] s2_type; // @[dcache.scala:633:25]
wire _s2_valid_T = ~io_lsu_s1_kill_0_0; // @[dcache.scala:413:7, :636:26]
wire _s2_valid_T_1 = s1_valid_0 & _s2_valid_T; // @[dcache.scala:427:49, :635:39, :636:26]
wire _s2_valid_T_5 = _s2_valid_T_1; // @[dcache.scala:635:39, :636:45]
wire _s2_valid_T_8 = _s2_valid_T_5; // @[dcache.scala:636:45, :637:76]
wire _s2_valid_T_9 = s1_type == 3'h4; // @[dcache.scala:615:32, :639:56]
wire _s2_valid_T_10 = s2_store_failed & _s2_valid_T_9; // @[dcache.scala:603:29, :639:{44,56}]
wire _s2_valid_T_11 = _s2_valid_T_10 & s1_req_0_uop_uses_stq; // @[dcache.scala:600:32, :639:{44,67}]
wire _s2_valid_T_12 = ~_s2_valid_T_11; // @[dcache.scala:639:{26,67}]
wire _s2_valid_T_13 = _s2_valid_T_8 & _s2_valid_T_12; // @[dcache.scala:637:76, :638:72, :639:26]
reg s2_valid_REG; // @[dcache.scala:635:26]
wire s2_valid_0 = s2_valid_REG; // @[dcache.scala:427:49, :635:26]
reg [1:0] s2_tag_match_way_0; // @[dcache.scala:643:33]
wire s2_tag_match_0 = |s2_tag_match_way_0; // @[dcache.scala:643:33, :644:49]
reg [1:0] s2_hit_state_REG_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_0_state = s2_hit_state_REG_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_1_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_1_state_0 = s2_hit_state_REG_1_state; // @[dcache.scala:622:47, :645:93]
wire _s2_hit_state_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire [1:0] _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_hit_state_0_state = _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_2 = _s2_hit_state_T ? _s2_hit_state_WIRE_0_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_3 = _s2_hit_state_T_1 ? _s2_hit_state_WIRE_1_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_4 = _s2_hit_state_T_2 | _s2_hit_state_T_3; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_2 = _s2_hit_state_T_4; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_1_state = _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] mshrs_io_req_0_bits_old_meta_meta_coh_state = s2_hit_state_0_state; // @[HellaCache.scala:305:20]
wire _GEN_2 = s2_req_0_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_send_resp_T_3; // @[Consts.scala:90:32]
assign _s2_send_resp_T_3 = _GEN_2; // @[Consts.scala:90:32]
wire _mshrs_io_req_0_valid_T_50; // @[Consts.scala:90:32]
assign _mshrs_io_req_0_valid_T_50 = _GEN_2; // @[Consts.scala:90:32]
wire _s3_valid_T_1; // @[Consts.scala:90:32]
assign _s3_valid_T_1 = _GEN_2; // @[Consts.scala:90:32]
wire _GEN_3 = s2_req_0_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_send_resp_T_4; // @[Consts.scala:90:49]
assign _s2_send_resp_T_4 = _GEN_3; // @[Consts.scala:90:49]
wire _mshrs_io_req_0_valid_T_51; // @[Consts.scala:90:49]
assign _mshrs_io_req_0_valid_T_51 = _GEN_3; // @[Consts.scala:90:49]
wire _s3_valid_T_2; // @[Consts.scala:90:49]
assign _s3_valid_T_2 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_2 = _s2_has_permission_r_c_cat_T | _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_4 = s2_req_0_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_sc_T; // @[dcache.scala:664:37]
assign _s2_sc_T = _GEN_4; // @[Consts.scala:90:66]
wire _s2_send_resp_T_6; // @[Consts.scala:90:66]
assign _s2_send_resp_T_6 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_send_resp_T_30; // @[package.scala:16:47]
assign _s2_send_resp_T_30 = _GEN_4; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_27 = _GEN_4; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_53; // @[Consts.scala:90:66]
assign _mshrs_io_req_0_valid_T_53 = _GEN_4; // @[Consts.scala:90:66]
wire _s3_valid_T_4; // @[Consts.scala:90:66]
assign _s3_valid_T_4 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_4 = _s2_has_permission_r_c_cat_T_2 | _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_5 = s2_req_0_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_resp_T_8; // @[package.scala:16:47]
assign _s2_send_resp_T_8 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_resp_T_34; // @[package.scala:16:47]
assign _s2_send_resp_T_34 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_31; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_31 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_55; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_55 = _GEN_5; // @[package.scala:16:47]
wire _s3_valid_T_6; // @[package.scala:16:47]
assign _s3_valid_T_6 = _GEN_5; // @[package.scala:16:47]
wire _GEN_6 = s2_req_0_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_resp_T_9; // @[package.scala:16:47]
assign _s2_send_resp_T_9 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_resp_T_35; // @[package.scala:16:47]
assign _s2_send_resp_T_35 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_32; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_32 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_56; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_56 = _GEN_6; // @[package.scala:16:47]
wire _s3_valid_T_7; // @[package.scala:16:47]
assign _s3_valid_T_7 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = s2_req_0_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_resp_T_10; // @[package.scala:16:47]
assign _s2_send_resp_T_10 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_resp_T_36; // @[package.scala:16:47]
assign _s2_send_resp_T_36 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_33; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_33 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_57; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_57 = _GEN_7; // @[package.scala:16:47]
wire _s3_valid_T_8; // @[package.scala:16:47]
assign _s3_valid_T_8 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = s2_req_0_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_resp_T_11; // @[package.scala:16:47]
assign _s2_send_resp_T_11 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_resp_T_37; // @[package.scala:16:47]
assign _s2_send_resp_T_37 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_34 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_58 = _GEN_8; // @[package.scala:16:47]
wire _s3_valid_T_9; // @[package.scala:16:47]
assign _s3_valid_T_9 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_9 = _s2_has_permission_r_c_cat_T_5 | _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_10 = _s2_has_permission_r_c_cat_T_9 | _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_11 = _s2_has_permission_r_c_cat_T_10 | _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_9 = s2_req_0_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_resp_T_15; // @[package.scala:16:47]
assign _s2_send_resp_T_15 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_resp_T_41; // @[package.scala:16:47]
assign _s2_send_resp_T_41 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_38; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_38 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_62; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_62 = _GEN_9; // @[package.scala:16:47]
wire _s3_valid_T_13; // @[package.scala:16:47]
assign _s3_valid_T_13 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = s2_req_0_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_resp_T_16; // @[package.scala:16:47]
assign _s2_send_resp_T_16 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_resp_T_42; // @[package.scala:16:47]
assign _s2_send_resp_T_42 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_39; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_39 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_63; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_63 = _GEN_10; // @[package.scala:16:47]
wire _s3_valid_T_14; // @[package.scala:16:47]
assign _s3_valid_T_14 = _GEN_10; // @[package.scala:16:47]
wire _GEN_11 = s2_req_0_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_resp_T_17; // @[package.scala:16:47]
assign _s2_send_resp_T_17 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_resp_T_43; // @[package.scala:16:47]
assign _s2_send_resp_T_43 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_40; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_40 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_64; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_64 = _GEN_11; // @[package.scala:16:47]
wire _s3_valid_T_15; // @[package.scala:16:47]
assign _s3_valid_T_15 = _GEN_11; // @[package.scala:16:47]
wire _GEN_12 = s2_req_0_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_resp_T_18; // @[package.scala:16:47]
assign _s2_send_resp_T_18 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_resp_T_44; // @[package.scala:16:47]
assign _s2_send_resp_T_44 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_41; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_41 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_65; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_65 = _GEN_12; // @[package.scala:16:47]
wire _s3_valid_T_16; // @[package.scala:16:47]
assign _s3_valid_T_16 = _GEN_12; // @[package.scala:16:47]
wire _GEN_13 = s2_req_0_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_resp_T_19; // @[package.scala:16:47]
assign _s2_send_resp_T_19 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_resp_T_45; // @[package.scala:16:47]
assign _s2_send_resp_T_45 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_42; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_42 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_66; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_66 = _GEN_13; // @[package.scala:16:47]
wire _s3_valid_T_17; // @[package.scala:16:47]
assign _s3_valid_T_17 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_17 = _s2_has_permission_r_c_cat_T_12 | _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_18 = _s2_has_permission_r_c_cat_T_17 | _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_19 = _s2_has_permission_r_c_cat_T_18 | _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_20 = _s2_has_permission_r_c_cat_T_19 | _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_21 = _s2_has_permission_r_c_cat_T_11 | _s2_has_permission_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_22 = _s2_has_permission_r_c_cat_T_4 | _s2_has_permission_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_has_permission_r_c_cat_T_25 = _s2_has_permission_r_c_cat_T_23 | _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_has_permission_r_c_cat_T_27 = _s2_has_permission_r_c_cat_T_25 | _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_has_permission_r_c_cat_T_32 = _s2_has_permission_r_c_cat_T_28 | _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_33 = _s2_has_permission_r_c_cat_T_32 | _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_34 = _s2_has_permission_r_c_cat_T_33 | _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_40 = _s2_has_permission_r_c_cat_T_35 | _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_41 = _s2_has_permission_r_c_cat_T_40 | _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_42 = _s2_has_permission_r_c_cat_T_41 | _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_43 = _s2_has_permission_r_c_cat_T_42 | _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_44 = _s2_has_permission_r_c_cat_T_34 | _s2_has_permission_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_45 = _s2_has_permission_r_c_cat_T_27 | _s2_has_permission_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_14 = s2_req_0_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_has_permission_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_new_hit_state_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _mshrs_io_req_0_valid_T_22; // @[Consts.scala:88:52]
assign _mshrs_io_req_0_valid_T_22 = _GEN_14; // @[Consts.scala:88:52, :91:54]
wire _s2_has_permission_r_c_cat_T_47 = _s2_has_permission_r_c_cat_T_45 | _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_15 = s2_req_0_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_has_permission_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_new_hit_state_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_lr_T; // @[dcache.scala:663:37]
assign _s2_lr_T = _GEN_15; // @[Consts.scala:91:71]
wire _s2_send_resp_T_29; // @[package.scala:16:47]
assign _s2_send_resp_T_29 = _GEN_15; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_26; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_26 = _GEN_15; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_49 = _s2_has_permission_r_c_cat_T_47 | _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_has_permission_r_c = {_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_has_permission_r_T = {s2_has_permission_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_has_permission_r_T_25 = _s2_has_permission_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_27 = {1'h0, _s2_has_permission_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_28 = _s2_has_permission_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_30 = _s2_has_permission_r_T_28 ? 2'h2 : _s2_has_permission_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_31 = _s2_has_permission_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_33 = _s2_has_permission_r_T_31 ? 2'h1 : _s2_has_permission_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_34 = _s2_has_permission_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_36 = _s2_has_permission_r_T_34 ? 2'h2 : _s2_has_permission_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_37 = _s2_has_permission_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_39 = _s2_has_permission_r_T_37 ? 2'h0 : _s2_has_permission_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_40 = _s2_has_permission_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_41 = _s2_has_permission_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_42 = _s2_has_permission_r_T_40 ? 2'h3 : _s2_has_permission_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_43 = &_s2_has_permission_r_T; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_44 = _s2_has_permission_r_T_43 | _s2_has_permission_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_45 = _s2_has_permission_r_T_43 ? 2'h3 : _s2_has_permission_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_46 = _s2_has_permission_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_47 = _s2_has_permission_r_T_46 | _s2_has_permission_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_48 = _s2_has_permission_r_T_46 ? 2'h2 : _s2_has_permission_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_49 = _s2_has_permission_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_50 = _s2_has_permission_r_T_49 | _s2_has_permission_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_51 = _s2_has_permission_r_T_49 ? 2'h3 : _s2_has_permission_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_52 = _s2_has_permission_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_53 = _s2_has_permission_r_T_52 | _s2_has_permission_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_54 = _s2_has_permission_r_T_52 ? 2'h1 : _s2_has_permission_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_55 = _s2_has_permission_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_56 = _s2_has_permission_r_T_55 | _s2_has_permission_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_57 = _s2_has_permission_r_T_55 ? 2'h2 : _s2_has_permission_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_58 = _s2_has_permission_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_has_permission_r_1 = _s2_has_permission_r_T_58 | _s2_has_permission_r_T_56; // @[Misc.scala:35:9, :49:20]
wire s2_has_permission_0 = s2_has_permission_r_1; // @[Misc.scala:35:9]
wire [1:0] s2_has_permission_r_2 = _s2_has_permission_r_T_58 ? 2'h3 : _s2_has_permission_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_has_permission_meta_state = s2_has_permission_r_2; // @[Misc.scala:35:36]
wire _s2_new_hit_state_r_c_cat_T_2 = _s2_new_hit_state_r_c_cat_T | _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_4 = _s2_new_hit_state_r_c_cat_T_2 | _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_9 = _s2_new_hit_state_r_c_cat_T_5 | _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_10 = _s2_new_hit_state_r_c_cat_T_9 | _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_11 = _s2_new_hit_state_r_c_cat_T_10 | _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_17 = _s2_new_hit_state_r_c_cat_T_12 | _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_18 = _s2_new_hit_state_r_c_cat_T_17 | _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_19 = _s2_new_hit_state_r_c_cat_T_18 | _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_20 = _s2_new_hit_state_r_c_cat_T_19 | _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_21 = _s2_new_hit_state_r_c_cat_T_11 | _s2_new_hit_state_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_22 = _s2_new_hit_state_r_c_cat_T_4 | _s2_new_hit_state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_25 = _s2_new_hit_state_r_c_cat_T_23 | _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_27 = _s2_new_hit_state_r_c_cat_T_25 | _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_32 = _s2_new_hit_state_r_c_cat_T_28 | _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_33 = _s2_new_hit_state_r_c_cat_T_32 | _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_34 = _s2_new_hit_state_r_c_cat_T_33 | _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_40 = _s2_new_hit_state_r_c_cat_T_35 | _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_41 = _s2_new_hit_state_r_c_cat_T_40 | _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_42 = _s2_new_hit_state_r_c_cat_T_41 | _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_43 = _s2_new_hit_state_r_c_cat_T_42 | _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_44 = _s2_new_hit_state_r_c_cat_T_34 | _s2_new_hit_state_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_45 = _s2_new_hit_state_r_c_cat_T_27 | _s2_new_hit_state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_47 = _s2_new_hit_state_r_c_cat_T_45 | _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _s2_new_hit_state_r_c_cat_T_49 = _s2_new_hit_state_r_c_cat_T_47 | _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_new_hit_state_r_c = {_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_new_hit_state_r_T = {s2_new_hit_state_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_new_hit_state_r_T_25 = _s2_new_hit_state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_27 = {1'h0, _s2_new_hit_state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_28 = _s2_new_hit_state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_30 = _s2_new_hit_state_r_T_28 ? 2'h2 : _s2_new_hit_state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_31 = _s2_new_hit_state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_33 = _s2_new_hit_state_r_T_31 ? 2'h1 : _s2_new_hit_state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_34 = _s2_new_hit_state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_36 = _s2_new_hit_state_r_T_34 ? 2'h2 : _s2_new_hit_state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_37 = _s2_new_hit_state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_39 = _s2_new_hit_state_r_T_37 ? 2'h0 : _s2_new_hit_state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_40 = _s2_new_hit_state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_41 = _s2_new_hit_state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_42 = _s2_new_hit_state_r_T_40 ? 2'h3 : _s2_new_hit_state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_43 = &_s2_new_hit_state_r_T; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_44 = _s2_new_hit_state_r_T_43 | _s2_new_hit_state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_45 = _s2_new_hit_state_r_T_43 ? 2'h3 : _s2_new_hit_state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_46 = _s2_new_hit_state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_47 = _s2_new_hit_state_r_T_46 | _s2_new_hit_state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_48 = _s2_new_hit_state_r_T_46 ? 2'h2 : _s2_new_hit_state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_49 = _s2_new_hit_state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_50 = _s2_new_hit_state_r_T_49 | _s2_new_hit_state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_51 = _s2_new_hit_state_r_T_49 ? 2'h3 : _s2_new_hit_state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_52 = _s2_new_hit_state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_53 = _s2_new_hit_state_r_T_52 | _s2_new_hit_state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_54 = _s2_new_hit_state_r_T_52 ? 2'h1 : _s2_new_hit_state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_55 = _s2_new_hit_state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_56 = _s2_new_hit_state_r_T_55 | _s2_new_hit_state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_57 = _s2_new_hit_state_r_T_55 ? 2'h2 : _s2_new_hit_state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_58 = _s2_new_hit_state_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_new_hit_state_r_1 = _s2_new_hit_state_r_T_58 | _s2_new_hit_state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] s2_new_hit_state_r_2 = _s2_new_hit_state_r_T_58 ? 2'h3 : _s2_new_hit_state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_new_hit_state_meta_state = s2_new_hit_state_r_2; // @[Misc.scala:35:36]
wire [1:0] s2_new_hit_state_0_state = s2_new_hit_state_meta_state; // @[Metadata.scala:160:20]
wire _s2_hit_T = s2_tag_match_0 & s2_has_permission_0; // @[dcache.scala:427:49, :644:49, :649:47]
wire _s2_hit_T_1 = s2_hit_state_0_state == s2_new_hit_state_0_state; // @[Metadata.scala:46:46]
wire _s2_hit_T_2 = _s2_hit_T & _s2_hit_T_1; // @[Metadata.scala:46:46]
wire _s2_hit_T_3 = ~_mshrs_io_block_hit_0; // @[dcache.scala:433:21, :649:117]
wire _s2_hit_T_4 = _s2_hit_T_2 & _s2_hit_T_3; // @[dcache.scala:649:{71,114,117}]
wire _T_67 = s2_type == 3'h0; // @[package.scala:16:47]
wire _s2_hit_T_5; // @[package.scala:16:47]
assign _s2_hit_T_5 = _T_67; // @[package.scala:16:47]
wire _s2_lr_T_2; // @[dcache.scala:663:83]
assign _s2_lr_T_2 = _T_67; // @[package.scala:16:47]
wire _s2_sc_T_2; // @[dcache.scala:664:83]
assign _s2_sc_T_2 = _T_67; // @[package.scala:16:47]
wire _s2_hit_T_6 = s2_type == 3'h2; // @[package.scala:16:47]
wire _s2_hit_T_7 = _s2_hit_T_5 | _s2_hit_T_6; // @[package.scala:16:47, :81:59]
wire _s2_hit_T_8 = _s2_hit_T_4 | _s2_hit_T_7; // @[package.scala:81:59]
wire s2_hit_0 = _s2_hit_T_8; // @[dcache.scala:427:49, :649:141]
wire s2_nack_0; // @[dcache.scala:650:21]
reg s2_wb_idx_matches_0; // @[dcache.scala:654:34]
reg [33:0] debug_sc_fail_addr; // @[dcache.scala:657:35]
reg [7:0] debug_sc_fail_cnt; // @[dcache.scala:658:35]
reg [6:0] lrsc_count; // @[dcache.scala:660:27]
wire lrsc_valid = |(lrsc_count[6:2]); // @[dcache.scala:660:27, :661:31]
reg [27:0] lrsc_addr; // @[dcache.scala:662:23]
reg s2_lr_REG; // @[dcache.scala:663:59]
wire _s2_lr_T_1 = ~s2_lr_REG; // @[dcache.scala:663:{51,59}]
wire _s2_lr_T_3 = _s2_lr_T_1 | _s2_lr_T_2; // @[dcache.scala:663:{51,72,83}]
wire s2_lr = _s2_lr_T & _s2_lr_T_3; // @[dcache.scala:663:{37,47,72}]
reg s2_sc_REG; // @[dcache.scala:664:59]
wire _s2_sc_T_1 = ~s2_sc_REG; // @[dcache.scala:664:{51,59}]
wire _s2_sc_T_3 = _s2_sc_T_1 | _s2_sc_T_2; // @[dcache.scala:664:{51,72,83}]
wire s2_sc = _s2_sc_T & _s2_sc_T_3; // @[dcache.scala:664:{37,47,72}]
wire cache_resp_0_bits_data_doZero_2 = s2_sc; // @[AMOALU.scala:43:31]
wire [27:0] _s2_lrsc_addr_match_T = s2_req_0_addr[33:6]; // @[dcache.scala:632:25, :665:86]
wire [27:0] _lrsc_addr_T = s2_req_0_addr[33:6]; // @[dcache.scala:632:25, :665:86, :672:35]
wire _s2_lrsc_addr_match_T_1 = lrsc_addr == _s2_lrsc_addr_match_T; // @[dcache.scala:662:23, :665:{66,86}]
wire _s2_lrsc_addr_match_T_2 = lrsc_valid & _s2_lrsc_addr_match_T_1; // @[dcache.scala:661:31, :665:{53,66}]
wire s2_lrsc_addr_match_0 = _s2_lrsc_addr_match_T_2; // @[dcache.scala:427:49, :665:53]
wire _s2_sc_fail_T = ~s2_lrsc_addr_match_0; // @[dcache.scala:427:49, :666:29]
wire s2_sc_fail = s2_sc & _s2_sc_fail_T; // @[dcache.scala:664:47, :666:{26,29}]
wire [7:0] _lrsc_count_T = {1'h0, lrsc_count} - 8'h1; // @[dcache.scala:660:27, :667:54]
wire [6:0] _lrsc_count_T_1 = _lrsc_count_T[6:0]; // @[dcache.scala:667:54]
wire _mshrs_io_req_0_valid_T_10 = s2_type == 3'h4; // @[package.scala:16:47]
wire [8:0] _debug_sc_fail_cnt_T = {1'h0, debug_sc_fail_cnt} + 9'h1; // @[dcache.scala:658:35, :692:48]
wire [7:0] _debug_sc_fail_cnt_T_1 = _debug_sc_fail_cnt_T[7:0]; // @[dcache.scala:692:48]
wire [63:0] s2_data_0_0; // @[dcache.scala:705:21]
wire [63:0] s2_data_0_1; // @[dcache.scala:705:21]
wire [63:0] _s2_data_muxed_T_2 = _s2_data_muxed_T ? s2_data_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_3 = _s2_data_muxed_T_1 ? s2_data_0_1 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_muxed_T_4 = _s2_data_muxed_T_2 | _s2_data_muxed_T_3; // @[Mux.scala:30:73]
wire [63:0] _s2_data_muxed_WIRE = _s2_data_muxed_T_4; // @[Mux.scala:30:73]
wire [63:0] s2_data_muxed_0 = _s2_data_muxed_WIRE; // @[Mux.scala:30:73]
wire [63:0] _s2_data_word_prebypass_T_1 = s2_data_muxed_0; // @[dcache.scala:427:49, :825:63]
wire replace; // @[Replacement.scala:37:29]
wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17]
wire _s1_replaced_way_en_T = lfsr[0]; // @[PRNG.scala:95:17]
wire _s2_replaced_way_en_T = lfsr[0]; // @[PRNG.scala:95:17]
wire [1:0] s1_replaced_way_en = 2'h1 << _s1_replaced_way_en_T; // @[OneHot.scala:58:35]
reg s2_replaced_way_en_REG; // @[dcache.scala:718:44]
wire [1:0] s2_replaced_way_en = 2'h1 << s2_replaced_way_en_REG; // @[OneHot.scala:58:35]
reg [1:0] s2_repl_meta_REG_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_0_coh_state = s2_repl_meta_REG_coh_state; // @[dcache.scala:622:47, :719:88]
reg [21:0] s2_repl_meta_REG_tag; // @[dcache.scala:719:88]
wire [21:0] _s2_repl_meta_WIRE_0_tag = s2_repl_meta_REG_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_1_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state_0 = s2_repl_meta_REG_1_coh_state; // @[dcache.scala:622:47, :719:88]
reg [21:0] s2_repl_meta_REG_1_tag; // @[dcache.scala:719:88]
wire [21:0] _s2_repl_meta_WIRE_1_tag_0 = s2_repl_meta_REG_1_tag; // @[dcache.scala:622:47, :719:88]
wire _s2_repl_meta_T = s2_replaced_way_en[0]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_1 = s2_replaced_way_en[1]; // @[OneHot.scala:58:35]
wire [1:0] _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [21:0] _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_repl_meta_0_coh_state = _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [21:0] s2_repl_meta_0_tag = _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [21:0] _s2_repl_meta_T_2 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_tag : 22'h0; // @[Mux.scala:30:73, :32:36]
wire [21:0] _s2_repl_meta_T_3 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_tag_0 : 22'h0; // @[Mux.scala:30:73, :32:36]
wire [21:0] _s2_repl_meta_T_4 = _s2_repl_meta_T_2 | _s2_repl_meta_T_3; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_2 = _s2_repl_meta_T_4; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_tag = _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_coh_state = _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_5 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_6 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_coh_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_7 = _s2_repl_meta_T_5 | _s2_repl_meta_T_6; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_4 = _s2_repl_meta_T_7; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_3_state = _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
wire [21:0] mshrs_io_req_0_bits_old_meta_meta_tag = s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
reg s2_nack_hit_0; // @[dcache.scala:722:31]
wire _GEN_16 = s2_valid_0 & s2_hit_0; // @[dcache.scala:427:49, :724:50]
wire _s2_nack_victim_T; // @[dcache.scala:724:50]
assign _s2_nack_victim_T = _GEN_16; // @[dcache.scala:724:50]
wire _s3_valid_T; // @[dcache.scala:871:38]
assign _s3_valid_T = _GEN_16; // @[dcache.scala:724:50, :871:38]
wire _s2_nack_victim_T_1 = _s2_nack_victim_T & _mshrs_io_secondary_miss_0; // @[dcache.scala:433:21, :724:{50,64}]
wire s2_nack_victim_0 = _s2_nack_victim_T_1; // @[dcache.scala:427:49, :724:64]
wire _s2_nack_miss_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :726:53]
wire _s2_nack_miss_T_1 = s2_valid_0 & _s2_nack_miss_T; // @[dcache.scala:427:49, :726:{50,53}]
wire _s2_nack_miss_T_2 = ~_mshrs_io_req_0_ready; // @[dcache.scala:433:21, :726:67]
wire _s2_nack_miss_T_3 = _s2_nack_miss_T_1 & _s2_nack_miss_T_2; // @[dcache.scala:726:{50,64,67}]
wire s2_nack_miss_0 = _s2_nack_miss_T_3; // @[dcache.scala:427:49, :726:64]
wire _s2_nack_wb_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :730:53]
wire _s2_nack_wb_T_1 = s2_valid_0 & _s2_nack_wb_T; // @[dcache.scala:427:49, :730:{50,53}]
wire _s2_nack_wb_T_2 = _s2_nack_wb_T_1 & s2_wb_idx_matches_0; // @[dcache.scala:654:34, :730:{50,64}]
wire s2_nack_wb_0 = _s2_nack_wb_T_2; // @[dcache.scala:427:49, :730:64]
assign s2_nack_0 = (s2_nack_miss_0 | s2_nack_hit_0 | s2_nack_victim_0 | s2_nack_wb_0) & (|s2_type); // @[dcache.scala:427:49, :633:25, :650:21, :722:31, :732:{55,73,113,131,142}]
reg s2_send_resp_REG; // @[dcache.scala:733:44]
wire _s2_send_resp_T = ~s2_nack_0; // @[dcache.scala:650:21, :668:60, :733:73]
wire _s2_send_resp_T_1 = s2_send_resp_REG & _s2_send_resp_T; // @[dcache.scala:733:{44,70,73}]
wire _mshrs_io_req_0_valid_T_74; // @[dcache.scala:754:77]
wire _T_73 = _mshrs_io_req_0_ready & _mshrs_io_req_0_valid_T_74; // @[Decoupled.scala:51:35]
assign replace = _T_73; // @[Decoupled.scala:51:35]
wire _s2_send_resp_T_2; // @[Decoupled.scala:51:35]
assign _s2_send_resp_T_2 = _T_73; // @[Decoupled.scala:51:35]
wire _s2_send_resp_T_5 = _s2_send_resp_T_3 | _s2_send_resp_T_4; // @[Consts.scala:90:{32,42,49}]
wire _s2_send_resp_T_7 = _s2_send_resp_T_5 | _s2_send_resp_T_6; // @[Consts.scala:90:{42,59,66}]
wire _s2_send_resp_T_12 = _s2_send_resp_T_8 | _s2_send_resp_T_9; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_13 = _s2_send_resp_T_12 | _s2_send_resp_T_10; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_14 = _s2_send_resp_T_13 | _s2_send_resp_T_11; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_20 = _s2_send_resp_T_15 | _s2_send_resp_T_16; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_21 = _s2_send_resp_T_20 | _s2_send_resp_T_17; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_22 = _s2_send_resp_T_21 | _s2_send_resp_T_18; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_23 = _s2_send_resp_T_22 | _s2_send_resp_T_19; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_24 = _s2_send_resp_T_14 | _s2_send_resp_T_23; // @[package.scala:81:59]
wire _s2_send_resp_T_25 = _s2_send_resp_T_7 | _s2_send_resp_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_send_resp_T_26 = _s2_send_resp_T_2 & _s2_send_resp_T_25; // @[Decoupled.scala:51:35]
wire _GEN_17 = s2_req_0_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s2_send_resp_T_27; // @[package.scala:16:47]
assign _s2_send_resp_T_27 = _GEN_17; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_24; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_24 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = s2_req_0_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s2_send_resp_T_28; // @[package.scala:16:47]
assign _s2_send_resp_T_28 = _GEN_18; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_25; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_25 = _GEN_18; // @[package.scala:16:47]
wire _s2_send_resp_T_31 = _s2_send_resp_T_27 | _s2_send_resp_T_28; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_32 = _s2_send_resp_T_31 | _s2_send_resp_T_29; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_33 = _s2_send_resp_T_32 | _s2_send_resp_T_30; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_38 = _s2_send_resp_T_34 | _s2_send_resp_T_35; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_39 = _s2_send_resp_T_38 | _s2_send_resp_T_36; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_40 = _s2_send_resp_T_39 | _s2_send_resp_T_37; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_46 = _s2_send_resp_T_41 | _s2_send_resp_T_42; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_47 = _s2_send_resp_T_46 | _s2_send_resp_T_43; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_48 = _s2_send_resp_T_47 | _s2_send_resp_T_44; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_49 = _s2_send_resp_T_48 | _s2_send_resp_T_45; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_50 = _s2_send_resp_T_40 | _s2_send_resp_T_49; // @[package.scala:81:59]
wire _s2_send_resp_T_51 = _s2_send_resp_T_33 | _s2_send_resp_T_50; // @[package.scala:81:59]
wire _s2_send_resp_T_52 = ~_s2_send_resp_T_51; // @[Consts.scala:89:68]
wire _s2_send_resp_T_53 = _s2_send_resp_T_26 & _s2_send_resp_T_52; // @[dcache.scala:734:{59,93,96}]
wire _s2_send_resp_T_54 = s2_hit_0 | _s2_send_resp_T_53; // @[dcache.scala:427:49, :734:{34,93}]
wire _s2_send_resp_T_55 = _s2_send_resp_T_1 & _s2_send_resp_T_54; // @[dcache.scala:733:{70,85}, :734:34]
wire s2_send_resp_0 = _s2_send_resp_T_55; // @[dcache.scala:427:49, :733:85]
reg s2_send_nack_REG; // @[dcache.scala:735:44]
wire _s2_send_nack_T = s2_send_nack_REG & s2_nack_0; // @[dcache.scala:650:21, :735:{44,70}]
wire s2_send_nack_0 = _s2_send_nack_T; // @[dcache.scala:427:49, :735:70]
wire _s2_store_failed_T = s2_valid_0 & s2_nack_0; // @[dcache.scala:427:49, :650:21, :742:34]
wire _s2_store_failed_T_1 = _s2_store_failed_T & s2_send_nack_0; // @[dcache.scala:427:49, :742:{34,48}]
assign _s2_store_failed_T_2 = _s2_store_failed_T_1 & s2_req_0_uop_uses_stq; // @[dcache.scala:632:25, :742:{48,67}]
assign s2_store_failed = _s2_store_failed_T_2; // @[dcache.scala:603:29, :742:67]
wire _mshrs_io_req_0_valid_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :747:29]
wire _mshrs_io_req_0_valid_T_1 = s2_valid_0 & _mshrs_io_req_0_valid_T; // @[dcache.scala:427:49, :746:51, :747:29]
wire _mshrs_io_req_0_valid_T_2 = ~s2_nack_hit_0; // @[dcache.scala:722:31, :748:29]
wire _mshrs_io_req_0_valid_T_3 = _mshrs_io_req_0_valid_T_1 & _mshrs_io_req_0_valid_T_2; // @[dcache.scala:746:51, :747:51, :748:29]
wire _mshrs_io_req_0_valid_T_4 = ~s2_nack_victim_0; // @[dcache.scala:427:49, :749:29]
wire _mshrs_io_req_0_valid_T_5 = _mshrs_io_req_0_valid_T_3 & _mshrs_io_req_0_valid_T_4; // @[dcache.scala:747:51, :748:51, :749:29]
wire _mshrs_io_req_0_valid_T_7 = _mshrs_io_req_0_valid_T_5; // @[dcache.scala:748:51, :749:51]
wire _mshrs_io_req_0_valid_T_8 = ~s2_nack_wb_0; // @[dcache.scala:427:49, :751:29]
wire _mshrs_io_req_0_valid_T_9 = _mshrs_io_req_0_valid_T_7 & _mshrs_io_req_0_valid_T_8; // @[dcache.scala:749:51, :750:51, :751:29]
wire _mshrs_io_req_0_valid_T_11 = s2_type == 3'h5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_12 = _mshrs_io_req_0_valid_T_10 | _mshrs_io_req_0_valid_T_11; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_13 = _mshrs_io_req_0_valid_T_9 & _mshrs_io_req_0_valid_T_12; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_17 = _mshrs_io_req_0_valid_T_13; // @[dcache.scala:751:51, :752:77]
wire _mshrs_io_req_0_valid_T_20 = _mshrs_io_req_0_valid_T_17; // @[dcache.scala:752:77, :753:79]
wire _mshrs_io_req_0_valid_T_21 = s2_req_0_uop_mem_cmd == 5'h2; // @[Consts.scala:88:35]
wire _mshrs_io_req_0_valid_T_23 = _mshrs_io_req_0_valid_T_21 | _mshrs_io_req_0_valid_T_22; // @[Consts.scala:88:{35,45,52}]
wire _mshrs_io_req_0_valid_T_28 = _mshrs_io_req_0_valid_T_24 | _mshrs_io_req_0_valid_T_25; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_29 = _mshrs_io_req_0_valid_T_28 | _mshrs_io_req_0_valid_T_26; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_30 = _mshrs_io_req_0_valid_T_29 | _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_35 = _mshrs_io_req_0_valid_T_31 | _mshrs_io_req_0_valid_T_32; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_36 = _mshrs_io_req_0_valid_T_35 | _mshrs_io_req_0_valid_T_33; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_37 = _mshrs_io_req_0_valid_T_36 | _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_43 = _mshrs_io_req_0_valid_T_38 | _mshrs_io_req_0_valid_T_39; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_44 = _mshrs_io_req_0_valid_T_43 | _mshrs_io_req_0_valid_T_40; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_45 = _mshrs_io_req_0_valid_T_44 | _mshrs_io_req_0_valid_T_41; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_46 = _mshrs_io_req_0_valid_T_45 | _mshrs_io_req_0_valid_T_42; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_47 = _mshrs_io_req_0_valid_T_37 | _mshrs_io_req_0_valid_T_46; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_48 = _mshrs_io_req_0_valid_T_30 | _mshrs_io_req_0_valid_T_47; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_49 = _mshrs_io_req_0_valid_T_23 | _mshrs_io_req_0_valid_T_48; // @[Consts.scala:88:45, :89:68]
wire _mshrs_io_req_0_valid_T_52 = _mshrs_io_req_0_valid_T_50 | _mshrs_io_req_0_valid_T_51; // @[Consts.scala:90:{32,42,49}]
wire _mshrs_io_req_0_valid_T_54 = _mshrs_io_req_0_valid_T_52 | _mshrs_io_req_0_valid_T_53; // @[Consts.scala:90:{42,59,66}]
wire _mshrs_io_req_0_valid_T_59 = _mshrs_io_req_0_valid_T_55 | _mshrs_io_req_0_valid_T_56; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_60 = _mshrs_io_req_0_valid_T_59 | _mshrs_io_req_0_valid_T_57; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_61 = _mshrs_io_req_0_valid_T_60 | _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_67 = _mshrs_io_req_0_valid_T_62 | _mshrs_io_req_0_valid_T_63; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_68 = _mshrs_io_req_0_valid_T_67 | _mshrs_io_req_0_valid_T_64; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_69 = _mshrs_io_req_0_valid_T_68 | _mshrs_io_req_0_valid_T_65; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_70 = _mshrs_io_req_0_valid_T_69 | _mshrs_io_req_0_valid_T_66; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_71 = _mshrs_io_req_0_valid_T_61 | _mshrs_io_req_0_valid_T_70; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_72 = _mshrs_io_req_0_valid_T_54 | _mshrs_io_req_0_valid_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _mshrs_io_req_0_valid_T_73 = _mshrs_io_req_0_valid_T_49 | _mshrs_io_req_0_valid_T_72; // @[Consts.scala:90:76]
assign _mshrs_io_req_0_valid_T_74 = _mshrs_io_req_0_valid_T_20 & _mshrs_io_req_0_valid_T_73; // @[dcache.scala:753:79, :754:77, :756:65]
wire [1:0] _mshrs_io_req_0_bits_old_meta_T_coh_state = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_coh_state : s2_repl_meta_0_coh_state; // @[HellaCache.scala:305:20]
wire [21:0] _mshrs_io_req_0_bits_old_meta_T_tag = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_tag : s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
wire [1:0] _mshrs_io_req_0_bits_way_en_T = s2_tag_match_0 ? s2_tag_match_way_0 : s2_replaced_way_en; // @[OneHot.scala:58:35]
wire _mshrs_io_req_is_probe_0_T = s2_type == 3'h1; // @[dcache.scala:633:25, :769:49]
wire _mshrs_io_req_is_probe_0_T_1 = _mshrs_io_req_is_probe_0_T & s2_valid_0; // @[dcache.scala:427:49, :769:{49,61}]
wire _mshrs_io_meta_resp_valid_T = ~s2_nack_hit_0; // @[dcache.scala:722:31, :748:29, :772:36]
wire _mshrs_io_meta_resp_valid_T_1 = _mshrs_io_meta_resp_valid_T | _prober_io_mshr_wb_rdy; // @[dcache.scala:432:22, :772:{36,52}]
reg [1:0] mshrs_io_meta_resp_bits_REG_0_coh_state; // @[dcache.scala:773:70]
reg [21:0] mshrs_io_meta_resp_bits_REG_0_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_1_coh_state; // @[dcache.scala:773:70]
reg [21:0] mshrs_io_meta_resp_bits_REG_1_tag; // @[dcache.scala:773:70]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [21:0] _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [21:0] _mshrs_io_meta_resp_bits_T_2 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_tag : 22'h0; // @[Mux.scala:30:73, :32:36]
wire [21:0] _mshrs_io_meta_resp_bits_T_3 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_tag : 22'h0; // @[Mux.scala:30:73, :32:36]
wire [21:0] _mshrs_io_meta_resp_bits_T_4 = _mshrs_io_meta_resp_bits_T_2 | _mshrs_io_meta_resp_bits_T_3; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_1 = _mshrs_io_meta_resp_bits_T_4; // @[Mux.scala:30:73]
wire [21:0] _mshrs_io_meta_resp_bits_WIRE_tag = _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_coh_state = _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_5 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_6 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_7 = _mshrs_io_meta_resp_bits_T_5 | _mshrs_io_meta_resp_bits_T_6; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_3 = _mshrs_io_meta_resp_bits_T_7; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_2_state = _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire _prober_io_req_valid_T = ~lrsc_valid; // @[dcache.scala:661:31, :778:46]
wire _prober_io_req_valid_T_1 = nodeOut_b_valid & _prober_io_req_valid_T; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T = ~lrsc_valid; // @[dcache.scala:661:31, :778:46, :779:51]
assign _nodeOut_b_ready_T_1 = _prober_io_req_ready & _nodeOut_b_ready_T; // @[dcache.scala:432:22, :779:{48,51}]
assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[MixedNode.scala:542:17]
wire _prober_io_wb_rdy_T = _prober_io_meta_write_bits_idx != _wb_io_idx_bits; // @[dcache.scala:431:18, :432:22, :785:59]
wire _prober_io_wb_rdy_T_1 = ~_wb_io_idx_valid; // @[dcache.scala:431:18, :785:82]
wire _prober_io_wb_rdy_T_2 = _prober_io_wb_rdy_T | _prober_io_wb_rdy_T_1; // @[dcache.scala:785:{59,79,82}]
wire _wb_io_mem_grant_T_1 = nodeOut_d_bits_source == 4'h8; // @[MixedNode.scala:542:17]
assign nodeOut_d_ready = _wb_io_mem_grant_T_1 | _mshrs_io_mem_grant_ready; // @[MixedNode.scala:542:17]
wire _wb_io_mem_grant_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _wb_io_mem_grant_T_2 = _wb_io_mem_grant_T & _wb_io_mem_grant_T_1; // @[Decoupled.scala:51:35]
wire opdata = _wb_io_release_bits_opcode[0]; // @[Edges.scala:102:36]
wire [26:0] _decode_T_3 = 27'hFFF << _prober_io_rep_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_4 = _decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] decode_1 = _decode_T_5[11:3]; // @[package.scala:243:46]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_c_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {_prober_io_rep_valid, _wb_io_release_valid}; // @[Arbiter.scala:68:51]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & _wb_io_release_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & _prober_io_rep_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_c_valid_T = _wb_io_release_valid | _prober_io_rep_valid; // @[Arbiter.scala:79:31, :96:46]
wire [8:0] maskedBeats_0 = winner_0 & opdata ? 9'h7 : 9'h0; // @[Edges.scala:102:36, :221:14]
wire [8:0] initBeats = maskedBeats_0; // @[Arbiter.scala:82:69, :84:44]
wire _GEN_19 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35]
wire _beatsLeft_T; // @[Decoupled.scala:51:35]
assign _beatsLeft_T = _GEN_19; // @[Decoupled.scala:51:35]
wire _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign _io_lsu_perf_release_T = _GEN_19; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire _wb_io_release_ready_T = nodeOut_c_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31]
wire _prober_io_rep_ready_T = nodeOut_c_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31]
wire _nodeOut_c_valid_T_1 = state_0 & _wb_io_release_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_2 = state_1 & _prober_io_rep_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_3 = _nodeOut_c_valid_T_1 | _nodeOut_c_valid_T_2; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_WIRE = _nodeOut_c_valid_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_valid_T_4 = idle ? _nodeOut_c_valid_T : _nodeOut_c_valid_WIRE; // @[Mux.scala:30:73]
assign nodeOut_c_valid = _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
assign nodeOut_c_bits_opcode = _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
assign nodeOut_c_bits_param = _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
assign nodeOut_c_bits_size = _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
assign nodeOut_c_bits_source = _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
assign nodeOut_c_bits_address = _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
assign nodeOut_c_bits_data = _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_T_3 = muxState_0 ? _wb_io_release_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _nodeOut_c_bits_T_5 = _nodeOut_c_bits_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_2 = _nodeOut_c_bits_T_5; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_data = _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_6 = muxState_0 ? _wb_io_release_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_7 = muxState_1 ? _prober_io_rep_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_8 = _nodeOut_c_bits_T_6 | _nodeOut_c_bits_T_7; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_5 = _nodeOut_c_bits_T_8; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_address = _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_9 = {muxState_0, 3'h0}; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_10 = muxState_1 ? _prober_io_rep_bits_source : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_11 = _nodeOut_c_bits_T_9 | _nodeOut_c_bits_T_10; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_6 = _nodeOut_c_bits_T_11; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_source = _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_12 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_13 = muxState_1 ? _prober_io_rep_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_14 = _nodeOut_c_bits_T_12 | _nodeOut_c_bits_T_13; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_7 = _nodeOut_c_bits_T_14; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_size = _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_15 = muxState_0 ? _wb_io_release_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_16 = muxState_1 ? _prober_io_rep_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_17 = _nodeOut_c_bits_T_15 | _nodeOut_c_bits_T_16; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_8 = _nodeOut_c_bits_T_17; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_param = _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_18 = muxState_0 ? _wb_io_release_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_19 = {muxState_1, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_20 = _nodeOut_c_bits_T_18 | _nodeOut_c_bits_T_19; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_9 = _nodeOut_c_bits_T_20; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_opcode = _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
wire [26:0] _io_lsu_perf_release_beats1_decode_T = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_1 = _io_lsu_perf_release_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_2 = ~_io_lsu_perf_release_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] io_lsu_perf_release_beats1_decode = _io_lsu_perf_release_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire io_lsu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36]
wire [8:0] io_lsu_perf_release_beats1 = io_lsu_perf_release_beats1_opdata ? io_lsu_perf_release_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] io_lsu_perf_release_counter; // @[Edges.scala:229:27]
wire [9:0] _io_lsu_perf_release_counter1_T = {1'h0, io_lsu_perf_release_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] io_lsu_perf_release_counter1 = _io_lsu_perf_release_counter1_T[8:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_release_first = io_lsu_perf_release_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_release_last_T = io_lsu_perf_release_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_release_last_T_1 = io_lsu_perf_release_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_release_last = _io_lsu_perf_release_last_T | _io_lsu_perf_release_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_release_done = io_lsu_perf_release_last & _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_release_0 = io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [8:0] _io_lsu_perf_release_count_T = ~io_lsu_perf_release_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] io_lsu_perf_release_count = io_lsu_perf_release_beats1 & _io_lsu_perf_release_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _io_lsu_perf_release_counter_T = io_lsu_perf_release_first ? io_lsu_perf_release_beats1 : io_lsu_perf_release_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _io_lsu_perf_acquire_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] _io_lsu_perf_acquire_beats1_decode_T = 27'hFFF << nodeOut_a_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_1 = _io_lsu_perf_acquire_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_2 = ~_io_lsu_perf_acquire_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] io_lsu_perf_acquire_beats1_decode = _io_lsu_perf_acquire_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _io_lsu_perf_acquire_beats1_opdata_T = nodeOut_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire io_lsu_perf_acquire_beats1_opdata = ~_io_lsu_perf_acquire_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] io_lsu_perf_acquire_beats1 = io_lsu_perf_acquire_beats1_opdata ? io_lsu_perf_acquire_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] io_lsu_perf_acquire_counter; // @[Edges.scala:229:27]
wire [9:0] _io_lsu_perf_acquire_counter1_T = {1'h0, io_lsu_perf_acquire_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] io_lsu_perf_acquire_counter1 = _io_lsu_perf_acquire_counter1_T[8:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_acquire_first = io_lsu_perf_acquire_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_acquire_last_T = io_lsu_perf_acquire_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_acquire_last_T_1 = io_lsu_perf_acquire_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_acquire_last = _io_lsu_perf_acquire_last_T | _io_lsu_perf_acquire_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_acquire_done = io_lsu_perf_acquire_last & _io_lsu_perf_acquire_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_acquire_0 = io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire [8:0] _io_lsu_perf_acquire_count_T = ~io_lsu_perf_acquire_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] io_lsu_perf_acquire_count = io_lsu_perf_acquire_beats1 & _io_lsu_perf_acquire_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _io_lsu_perf_acquire_counter_T = io_lsu_perf_acquire_first ? io_lsu_perf_acquire_beats1 : io_lsu_perf_acquire_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [63:0] s2_data_word_prebypass_0 = _s2_data_word_prebypass_T_1; // @[dcache.scala:427:49, :825:63]
wire [63:0] _s2_data_word_0_T_2; // @[dcache.scala:891:27]
wire [63:0] s2_data_word_0; // @[dcache.scala:826:26]
wire [63:0] size_dat_padded = s2_data_word_0; // @[AMOALU.scala:13:27]
wire _cache_resp_0_valid_T; // @[dcache.scala:835:48]
wire [63:0] _cache_resp_0_bits_data_T_24; // @[dcache.scala:837:52]
wire [63:0] cache_resp_0_bits_data; // @[dcache.scala:833:26]
wire cache_resp_0_valid; // @[dcache.scala:833:26]
assign _cache_resp_0_valid_T = s2_valid_0 & s2_send_resp_0; // @[dcache.scala:427:49, :835:48]
assign cache_resp_0_valid = _cache_resp_0_valid_T; // @[dcache.scala:833:26, :835:48]
wire _cache_resp_0_bits_data_shifted_T = s2_req_0_addr[2]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T_8 = s2_req_0_addr[2]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T_2 = s2_req_0_addr[2]; // @[AMOALU.scala:21:27, :42:29]
wire [31:0] _cache_resp_0_bits_data_shifted_T_1 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _cache_resp_0_bits_data_T_5 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _cache_resp_0_bits_data_shifted_T_2 = s2_data_word_0[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] cache_resp_0_bits_data_shifted = _cache_resp_0_bits_data_shifted_T ? _cache_resp_0_bits_data_shifted_T_1 : _cache_resp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] cache_resp_0_bits_data_zeroed = cache_resp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _cache_resp_0_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_1 = _cache_resp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _cache_resp_0_bits_data_T_2 = cache_resp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_3 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _cache_resp_0_bits_data_T_4 = {32{_cache_resp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _cache_resp_0_bits_data_T_6 = _cache_resp_0_bits_data_T_1 ? _cache_resp_0_bits_data_T_4 : _cache_resp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_7 = {_cache_resp_0_bits_data_T_6, cache_resp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _cache_resp_0_bits_data_shifted_T_3 = s2_req_0_addr[1]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T_4 = s2_req_0_addr[1]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T_1 = s2_req_0_addr[1]; // @[AMOALU.scala:21:27, :42:29]
wire [15:0] _cache_resp_0_bits_data_shifted_T_4 = _cache_resp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _cache_resp_0_bits_data_shifted_T_5 = _cache_resp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] cache_resp_0_bits_data_shifted_1 = _cache_resp_0_bits_data_shifted_T_3 ? _cache_resp_0_bits_data_shifted_T_4 : _cache_resp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] cache_resp_0_bits_data_zeroed_1 = cache_resp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _cache_resp_0_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_9 = _cache_resp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _cache_resp_0_bits_data_T_10 = cache_resp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_11 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _cache_resp_0_bits_data_T_12 = {48{_cache_resp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _cache_resp_0_bits_data_T_13 = _cache_resp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _cache_resp_0_bits_data_T_14 = _cache_resp_0_bits_data_T_9 ? _cache_resp_0_bits_data_T_12 : _cache_resp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_15 = {_cache_resp_0_bits_data_T_14, cache_resp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _cache_resp_0_bits_data_shifted_T_6 = s2_req_0_addr[0]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T = s2_req_0_addr[0]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T = s2_req_0_addr[0]; // @[AMOALU.scala:21:27, :42:29]
wire [7:0] _cache_resp_0_bits_data_shifted_T_7 = _cache_resp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _cache_resp_0_bits_data_shifted_T_8 = _cache_resp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] cache_resp_0_bits_data_shifted_2 = _cache_resp_0_bits_data_shifted_T_6 ? _cache_resp_0_bits_data_shifted_T_7 : _cache_resp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] cache_resp_0_bits_data_zeroed_2 = cache_resp_0_bits_data_doZero_2 ? 8'h0 : cache_resp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :43:31, :44:23]
wire _cache_resp_0_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_17 = _cache_resp_0_bits_data_T_16 | cache_resp_0_bits_data_doZero_2; // @[AMOALU.scala:43:31, :45:{26,34}]
wire _cache_resp_0_bits_data_T_18 = cache_resp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_19 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _cache_resp_0_bits_data_T_20 = {56{_cache_resp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _cache_resp_0_bits_data_T_21 = _cache_resp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _cache_resp_0_bits_data_T_22 = _cache_resp_0_bits_data_T_17 ? _cache_resp_0_bits_data_T_20 : _cache_resp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_23 = {_cache_resp_0_bits_data_T_22, cache_resp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign _cache_resp_0_bits_data_T_24 = {_cache_resp_0_bits_data_T_23[63:1], _cache_resp_0_bits_data_T_23[0] | s2_sc_fail}; // @[AMOALU.scala:45:16]
assign cache_resp_0_bits_data = _cache_resp_0_bits_data_T_24; // @[dcache.scala:833:26, :837:52]
wire [3:0] uncache_resp_bits_uop_ctrl_br_type; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_ctrl_op1_sel; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_op2_sel; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_imm_sel; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_ctrl_op_fcn; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_fcn_dw; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_csr_cmd; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_load; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_sta; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_std; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_uopc; // @[dcache.scala:841:26]
wire [31:0] uncache_resp_bits_uop_inst; // @[dcache.scala:841:26]
wire [31:0] uncache_resp_bits_uop_debug_inst; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_rvc; // @[dcache.scala:841:26]
wire [33:0] uncache_resp_bits_uop_debug_pc; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_iq_type; // @[dcache.scala:841:26]
wire [9:0] uncache_resp_bits_uop_fu_code; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_iw_state; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_iw_p1_poisoned; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_iw_p2_poisoned; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_br; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_jalr; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_jal; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_sfb; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_br_mask; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_br_tag; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_ftq_idx; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_edge_inst; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_pc_lob; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_taken; // @[dcache.scala:841:26]
wire [19:0] uncache_resp_bits_uop_imm_packed; // @[dcache.scala:841:26]
wire [11:0] uncache_resp_bits_uop_csr_addr; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_rob_idx; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_ldq_idx; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_stq_idx; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_rxq_idx; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_pdst; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_prs1; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_prs2; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_prs3; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_ppred; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs1_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs2_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs3_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ppred_busy; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_stale_pdst; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_exception; // @[dcache.scala:841:26]
wire [63:0] uncache_resp_bits_uop_exc_cause; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bypassable; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_mem_cmd; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_mem_size; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_mem_signed; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_fence; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_fencei; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_amo; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_uses_ldq; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_uses_stq; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_sys_pc2epc; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_unique; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_flush_on_commit; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ldst_is_rs1; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_ldst; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs1; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs2; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs3; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ldst_val; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_dst_rtype; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_lrs1_rtype; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_lrs2_rtype; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_frs3_en; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_fp_val; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_fp_single; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_pf_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_ae_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_ma_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bp_debug_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bp_xcpt_if; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_debug_fsrc; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_debug_tsrc; // @[dcache.scala:841:26]
wire [63:0] uncache_resp_bits_data; // @[dcache.scala:841:26]
wire uncache_resp_bits_is_hella; // @[dcache.scala:841:26]
wire uncache_resp_valid; // @[dcache.scala:841:26]
wire _mshrs_io_resp_ready_T = ~cache_resp_0_valid; // @[dcache.scala:833:26, :844:26]
wire _io_lsu_resp_0_valid_T_2 = resp_0_valid; // @[dcache.scala:846:22, :857:43]
assign io_lsu_resp_0_bits_out_uop_uopc = resp_0_bits_uop_uopc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_inst = resp_0_bits_uop_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_inst = resp_0_bits_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_rvc = resp_0_bits_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_pc = resp_0_bits_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iq_type = resp_0_bits_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fu_code = resp_0_bits_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_br_type = resp_0_bits_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op1_sel = resp_0_bits_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op2_sel = resp_0_bits_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_imm_sel = resp_0_bits_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op_fcn = resp_0_bits_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw = resp_0_bits_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd = resp_0_bits_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_load = resp_0_bits_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_sta = resp_0_bits_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_std = resp_0_bits_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_state = resp_0_bits_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_p1_poisoned = resp_0_bits_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_p2_poisoned = resp_0_bits_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_br = resp_0_bits_uop_is_br; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_jalr = resp_0_bits_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_jal = resp_0_bits_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_sfb = resp_0_bits_uop_is_sfb; // @[util.scala:101:23]
wire [3:0] _io_lsu_resp_0_bits_out_uop_br_mask_T_1 = resp_0_bits_uop_br_mask; // @[util.scala:89:21]
assign io_lsu_resp_0_bits_out_uop_br_tag = resp_0_bits_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ftq_idx = resp_0_bits_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_edge_inst = resp_0_bits_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_pc_lob = resp_0_bits_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_taken = resp_0_bits_uop_taken; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_imm_packed = resp_0_bits_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_csr_addr = resp_0_bits_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_rob_idx = resp_0_bits_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldq_idx = resp_0_bits_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_stq_idx = resp_0_bits_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_rxq_idx = resp_0_bits_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_pdst = resp_0_bits_uop_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs1 = resp_0_bits_uop_prs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs2 = resp_0_bits_uop_prs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs3 = resp_0_bits_uop_prs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ppred = resp_0_bits_uop_ppred; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs1_busy = resp_0_bits_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs2_busy = resp_0_bits_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs3_busy = resp_0_bits_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ppred_busy = resp_0_bits_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_stale_pdst = resp_0_bits_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_exception = resp_0_bits_uop_exception; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_exc_cause = resp_0_bits_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bypassable = resp_0_bits_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_cmd = resp_0_bits_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_size = resp_0_bits_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_signed = resp_0_bits_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_fence = resp_0_bits_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_fencei = resp_0_bits_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_amo = resp_0_bits_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_uses_ldq = resp_0_bits_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_uses_stq = resp_0_bits_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_sys_pc2epc = resp_0_bits_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_unique = resp_0_bits_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_flush_on_commit = resp_0_bits_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst_is_rs1 = resp_0_bits_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst = resp_0_bits_uop_ldst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs1 = resp_0_bits_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs2 = resp_0_bits_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs3 = resp_0_bits_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst_val = resp_0_bits_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_dst_rtype = resp_0_bits_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs1_rtype = resp_0_bits_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs2_rtype = resp_0_bits_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_frs3_en = resp_0_bits_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fp_val = resp_0_bits_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fp_single = resp_0_bits_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_pf_if = resp_0_bits_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_ae_if = resp_0_bits_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_ma_if = resp_0_bits_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bp_debug_if = resp_0_bits_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bp_xcpt_if = resp_0_bits_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_fsrc = resp_0_bits_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_tsrc = resp_0_bits_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_data = resp_0_bits_data; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_is_hella = resp_0_bits_is_hella; // @[util.scala:101:23]
wire _uncache_respond_T = ~cache_resp_0_valid; // @[dcache.scala:833:26, :844:26, :849:27]
wire uncache_respond = _uncache_respond_T; // @[dcache.scala:849:{27,48}]
assign resp_0_valid = uncache_respond ? uncache_resp_valid : cache_resp_0_valid; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uopc = uncache_respond ? uncache_resp_bits_uop_uopc : cache_resp_0_bits_uop_uopc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_inst = uncache_respond ? uncache_resp_bits_uop_inst : cache_resp_0_bits_uop_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_inst = uncache_respond ? uncache_resp_bits_uop_debug_inst : cache_resp_0_bits_uop_debug_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_rvc = uncache_respond ? uncache_resp_bits_uop_is_rvc : cache_resp_0_bits_uop_is_rvc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_pc = uncache_respond ? uncache_resp_bits_uop_debug_pc : cache_resp_0_bits_uop_debug_pc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iq_type = uncache_respond ? uncache_resp_bits_uop_iq_type : cache_resp_0_bits_uop_iq_type; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fu_code = uncache_respond ? uncache_resp_bits_uop_fu_code : cache_resp_0_bits_uop_fu_code; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_br_type = uncache_respond ? uncache_resp_bits_uop_ctrl_br_type : cache_resp_0_bits_uop_ctrl_br_type; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op1_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op1_sel : cache_resp_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op2_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op2_sel : cache_resp_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_imm_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_imm_sel : cache_resp_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op_fcn = uncache_respond ? uncache_resp_bits_uop_ctrl_op_fcn : cache_resp_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_fcn_dw = uncache_respond ? uncache_resp_bits_uop_ctrl_fcn_dw : cache_resp_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_csr_cmd = uncache_respond ? uncache_resp_bits_uop_ctrl_csr_cmd : cache_resp_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_load = uncache_respond ? uncache_resp_bits_uop_ctrl_is_load : cache_resp_0_bits_uop_ctrl_is_load; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_sta = uncache_respond ? uncache_resp_bits_uop_ctrl_is_sta : cache_resp_0_bits_uop_ctrl_is_sta; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_std = uncache_respond ? uncache_resp_bits_uop_ctrl_is_std : cache_resp_0_bits_uop_ctrl_is_std; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_state = uncache_respond ? uncache_resp_bits_uop_iw_state : cache_resp_0_bits_uop_iw_state; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_p1_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p1_poisoned : cache_resp_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_p2_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p2_poisoned : cache_resp_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_br = uncache_respond ? uncache_resp_bits_uop_is_br : cache_resp_0_bits_uop_is_br; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_jalr = uncache_respond ? uncache_resp_bits_uop_is_jalr : cache_resp_0_bits_uop_is_jalr; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_jal = uncache_respond ? uncache_resp_bits_uop_is_jal : cache_resp_0_bits_uop_is_jal; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_sfb = uncache_respond ? uncache_resp_bits_uop_is_sfb : cache_resp_0_bits_uop_is_sfb; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_br_mask = uncache_respond ? uncache_resp_bits_uop_br_mask : cache_resp_0_bits_uop_br_mask; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_br_tag = uncache_respond ? uncache_resp_bits_uop_br_tag : cache_resp_0_bits_uop_br_tag; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ftq_idx = uncache_respond ? uncache_resp_bits_uop_ftq_idx : cache_resp_0_bits_uop_ftq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_edge_inst = uncache_respond ? uncache_resp_bits_uop_edge_inst : cache_resp_0_bits_uop_edge_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_pc_lob = uncache_respond ? uncache_resp_bits_uop_pc_lob : cache_resp_0_bits_uop_pc_lob; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_taken = uncache_respond ? uncache_resp_bits_uop_taken : cache_resp_0_bits_uop_taken; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_imm_packed = uncache_respond ? uncache_resp_bits_uop_imm_packed : cache_resp_0_bits_uop_imm_packed; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_csr_addr = uncache_respond ? uncache_resp_bits_uop_csr_addr : cache_resp_0_bits_uop_csr_addr; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_rob_idx = uncache_respond ? uncache_resp_bits_uop_rob_idx : cache_resp_0_bits_uop_rob_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldq_idx = uncache_respond ? uncache_resp_bits_uop_ldq_idx : cache_resp_0_bits_uop_ldq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_stq_idx = uncache_respond ? uncache_resp_bits_uop_stq_idx : cache_resp_0_bits_uop_stq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_rxq_idx = uncache_respond ? uncache_resp_bits_uop_rxq_idx : cache_resp_0_bits_uop_rxq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_pdst = uncache_respond ? uncache_resp_bits_uop_pdst : cache_resp_0_bits_uop_pdst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs1 = uncache_respond ? uncache_resp_bits_uop_prs1 : cache_resp_0_bits_uop_prs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs2 = uncache_respond ? uncache_resp_bits_uop_prs2 : cache_resp_0_bits_uop_prs2; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs3 = uncache_respond ? uncache_resp_bits_uop_prs3 : cache_resp_0_bits_uop_prs3; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ppred = uncache_respond ? uncache_resp_bits_uop_ppred : cache_resp_0_bits_uop_ppred; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs1_busy = uncache_respond ? uncache_resp_bits_uop_prs1_busy : cache_resp_0_bits_uop_prs1_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs2_busy = uncache_respond ? uncache_resp_bits_uop_prs2_busy : cache_resp_0_bits_uop_prs2_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs3_busy = uncache_respond ? uncache_resp_bits_uop_prs3_busy : cache_resp_0_bits_uop_prs3_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ppred_busy = uncache_respond ? uncache_resp_bits_uop_ppred_busy : cache_resp_0_bits_uop_ppred_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_stale_pdst = uncache_respond ? uncache_resp_bits_uop_stale_pdst : cache_resp_0_bits_uop_stale_pdst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_exception = uncache_respond ? uncache_resp_bits_uop_exception : cache_resp_0_bits_uop_exception; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_exc_cause = uncache_respond ? uncache_resp_bits_uop_exc_cause : cache_resp_0_bits_uop_exc_cause; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bypassable = uncache_respond ? uncache_resp_bits_uop_bypassable : cache_resp_0_bits_uop_bypassable; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_cmd = uncache_respond ? uncache_resp_bits_uop_mem_cmd : cache_resp_0_bits_uop_mem_cmd; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_size = uncache_respond ? uncache_resp_bits_uop_mem_size : cache_resp_0_bits_uop_mem_size; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_signed = uncache_respond ? uncache_resp_bits_uop_mem_signed : cache_resp_0_bits_uop_mem_signed; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_fence = uncache_respond ? uncache_resp_bits_uop_is_fence : cache_resp_0_bits_uop_is_fence; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_fencei = uncache_respond ? uncache_resp_bits_uop_is_fencei : cache_resp_0_bits_uop_is_fencei; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_amo = uncache_respond ? uncache_resp_bits_uop_is_amo : cache_resp_0_bits_uop_is_amo; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uses_ldq = uncache_respond ? uncache_resp_bits_uop_uses_ldq : cache_resp_0_bits_uop_uses_ldq; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uses_stq = uncache_respond ? uncache_resp_bits_uop_uses_stq : cache_resp_0_bits_uop_uses_stq; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_sys_pc2epc = uncache_respond ? uncache_resp_bits_uop_is_sys_pc2epc : cache_resp_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_unique = uncache_respond ? uncache_resp_bits_uop_is_unique : cache_resp_0_bits_uop_is_unique; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_flush_on_commit = uncache_respond ? uncache_resp_bits_uop_flush_on_commit : cache_resp_0_bits_uop_flush_on_commit; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst_is_rs1 = uncache_respond ? uncache_resp_bits_uop_ldst_is_rs1 : cache_resp_0_bits_uop_ldst_is_rs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst = uncache_respond ? uncache_resp_bits_uop_ldst : cache_resp_0_bits_uop_ldst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs1 = uncache_respond ? uncache_resp_bits_uop_lrs1 : cache_resp_0_bits_uop_lrs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs2 = uncache_respond ? uncache_resp_bits_uop_lrs2 : cache_resp_0_bits_uop_lrs2; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs3 = uncache_respond ? uncache_resp_bits_uop_lrs3 : cache_resp_0_bits_uop_lrs3; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst_val = uncache_respond ? uncache_resp_bits_uop_ldst_val : cache_resp_0_bits_uop_ldst_val; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_dst_rtype = uncache_respond ? uncache_resp_bits_uop_dst_rtype : cache_resp_0_bits_uop_dst_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs1_rtype = uncache_respond ? uncache_resp_bits_uop_lrs1_rtype : cache_resp_0_bits_uop_lrs1_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs2_rtype = uncache_respond ? uncache_resp_bits_uop_lrs2_rtype : cache_resp_0_bits_uop_lrs2_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_frs3_en = uncache_respond ? uncache_resp_bits_uop_frs3_en : cache_resp_0_bits_uop_frs3_en; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fp_val = uncache_respond ? uncache_resp_bits_uop_fp_val : cache_resp_0_bits_uop_fp_val; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fp_single = uncache_respond ? uncache_resp_bits_uop_fp_single : cache_resp_0_bits_uop_fp_single; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_pf_if = uncache_respond ? uncache_resp_bits_uop_xcpt_pf_if : cache_resp_0_bits_uop_xcpt_pf_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_ae_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ae_if : cache_resp_0_bits_uop_xcpt_ae_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_ma_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ma_if : cache_resp_0_bits_uop_xcpt_ma_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bp_debug_if = uncache_respond ? uncache_resp_bits_uop_bp_debug_if : cache_resp_0_bits_uop_bp_debug_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bp_xcpt_if = uncache_respond ? uncache_resp_bits_uop_bp_xcpt_if : cache_resp_0_bits_uop_bp_xcpt_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_fsrc = uncache_respond ? uncache_resp_bits_uop_debug_fsrc : cache_resp_0_bits_uop_debug_fsrc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_tsrc = uncache_respond ? uncache_resp_bits_uop_debug_tsrc : cache_resp_0_bits_uop_debug_tsrc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_data = uncache_respond ? uncache_resp_bits_data : cache_resp_0_bits_data; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_is_hella = uncache_respond ? uncache_resp_bits_is_hella : cache_resp_0_bits_is_hella; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign _io_lsu_resp_0_valid_T_6 = _io_lsu_resp_0_valid_T_2; // @[dcache.scala:857:43, :858:78]
assign io_lsu_resp_0_valid_0 = _io_lsu_resp_0_valid_T_6; // @[dcache.scala:413:7, :858:78]
assign io_lsu_resp_0_bits_uop_uopc_0 = io_lsu_resp_0_bits_out_uop_uopc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_inst_0 = io_lsu_resp_0_bits_out_uop_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_inst_0 = io_lsu_resp_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_rvc_0 = io_lsu_resp_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_pc_0 = io_lsu_resp_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iq_type_0 = io_lsu_resp_0_bits_out_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fu_code_0 = io_lsu_resp_0_bits_out_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_br_type_0 = io_lsu_resp_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op1_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op2_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_imm_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op_fcn_0 = io_lsu_resp_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_load_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_sta_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_std_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_state_0 = io_lsu_resp_0_bits_out_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_p1_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_p2_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_br_0 = io_lsu_resp_0_bits_out_uop_is_br; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_jalr_0 = io_lsu_resp_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_jal_0 = io_lsu_resp_0_bits_out_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_sfb_0 = io_lsu_resp_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_br_mask_0 = io_lsu_resp_0_bits_out_uop_br_mask; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_br_tag_0 = io_lsu_resp_0_bits_out_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ftq_idx_0 = io_lsu_resp_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_edge_inst_0 = io_lsu_resp_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_pc_lob_0 = io_lsu_resp_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_taken_0 = io_lsu_resp_0_bits_out_uop_taken; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_imm_packed_0 = io_lsu_resp_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_csr_addr_0 = io_lsu_resp_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_rob_idx_0 = io_lsu_resp_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldq_idx_0 = io_lsu_resp_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_stq_idx_0 = io_lsu_resp_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_rxq_idx_0 = io_lsu_resp_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_pdst_0 = io_lsu_resp_0_bits_out_uop_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs1_0 = io_lsu_resp_0_bits_out_uop_prs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs2_0 = io_lsu_resp_0_bits_out_uop_prs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs3_0 = io_lsu_resp_0_bits_out_uop_prs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ppred_0 = io_lsu_resp_0_bits_out_uop_ppred; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs1_busy_0 = io_lsu_resp_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs2_busy_0 = io_lsu_resp_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs3_busy_0 = io_lsu_resp_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ppred_busy_0 = io_lsu_resp_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_stale_pdst_0 = io_lsu_resp_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_exception_0 = io_lsu_resp_0_bits_out_uop_exception; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_exc_cause_0 = io_lsu_resp_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bypassable_0 = io_lsu_resp_0_bits_out_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_cmd_0 = io_lsu_resp_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_size_0 = io_lsu_resp_0_bits_out_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_signed_0 = io_lsu_resp_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_fence_0 = io_lsu_resp_0_bits_out_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_fencei_0 = io_lsu_resp_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_amo_0 = io_lsu_resp_0_bits_out_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_uses_ldq_0 = io_lsu_resp_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_uses_stq_0 = io_lsu_resp_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_resp_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_unique_0 = io_lsu_resp_0_bits_out_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_flush_on_commit_0 = io_lsu_resp_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_is_rs1_0 = io_lsu_resp_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_0 = io_lsu_resp_0_bits_out_uop_ldst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs1_0 = io_lsu_resp_0_bits_out_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs2_0 = io_lsu_resp_0_bits_out_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs3_0 = io_lsu_resp_0_bits_out_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_val_0 = io_lsu_resp_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_dst_rtype_0 = io_lsu_resp_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs1_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs2_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_frs3_en_0 = io_lsu_resp_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fp_val_0 = io_lsu_resp_0_bits_out_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fp_single_0 = io_lsu_resp_0_bits_out_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_pf_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_ae_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_ma_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bp_debug_if_0 = io_lsu_resp_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bp_xcpt_if_0 = io_lsu_resp_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_fsrc_0 = io_lsu_resp_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_tsrc_0 = io_lsu_resp_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_data_0 = io_lsu_resp_0_bits_out_data; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_is_hella_0 = io_lsu_resp_0_bits_out_is_hella; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_br_mask = _io_lsu_resp_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21, :101:23]
wire _io_lsu_nack_0_valid_T = s2_valid_0 & s2_send_nack_0; // @[dcache.scala:427:49, :862:41]
wire _io_lsu_nack_0_valid_T_3 = _io_lsu_nack_0_valid_T; // @[dcache.scala:862:{41,60}]
assign _io_lsu_nack_0_valid_T_7 = _io_lsu_nack_0_valid_T_3; // @[dcache.scala:862:60, :863:75]
assign io_lsu_nack_0_valid_0 = _io_lsu_nack_0_valid_T_7; // @[dcache.scala:413:7, :863:75]
assign io_lsu_nack_0_bits_uop_uopc_0 = io_lsu_nack_0_bits_out_uop_uopc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_inst_0 = io_lsu_nack_0_bits_out_uop_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_inst_0 = io_lsu_nack_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_rvc_0 = io_lsu_nack_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_pc_0 = io_lsu_nack_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iq_type_0 = io_lsu_nack_0_bits_out_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fu_code_0 = io_lsu_nack_0_bits_out_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_br_type_0 = io_lsu_nack_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op1_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op2_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_imm_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op_fcn_0 = io_lsu_nack_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_load_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_sta_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_std_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_state_0 = io_lsu_nack_0_bits_out_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_p1_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_p2_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_br_0 = io_lsu_nack_0_bits_out_uop_is_br; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_jalr_0 = io_lsu_nack_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_jal_0 = io_lsu_nack_0_bits_out_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_sfb_0 = io_lsu_nack_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_br_mask_0 = io_lsu_nack_0_bits_out_uop_br_mask; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_br_tag_0 = io_lsu_nack_0_bits_out_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ftq_idx_0 = io_lsu_nack_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_edge_inst_0 = io_lsu_nack_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_pc_lob_0 = io_lsu_nack_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_taken_0 = io_lsu_nack_0_bits_out_uop_taken; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_imm_packed_0 = io_lsu_nack_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_csr_addr_0 = io_lsu_nack_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_rob_idx_0 = io_lsu_nack_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldq_idx_0 = io_lsu_nack_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_stq_idx_0 = io_lsu_nack_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_rxq_idx_0 = io_lsu_nack_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_pdst_0 = io_lsu_nack_0_bits_out_uop_pdst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs1_0 = io_lsu_nack_0_bits_out_uop_prs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs2_0 = io_lsu_nack_0_bits_out_uop_prs2; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs3_0 = io_lsu_nack_0_bits_out_uop_prs3; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ppred_0 = io_lsu_nack_0_bits_out_uop_ppred; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs1_busy_0 = io_lsu_nack_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs2_busy_0 = io_lsu_nack_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs3_busy_0 = io_lsu_nack_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ppred_busy_0 = io_lsu_nack_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_stale_pdst_0 = io_lsu_nack_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_exception_0 = io_lsu_nack_0_bits_out_uop_exception; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_exc_cause_0 = io_lsu_nack_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bypassable_0 = io_lsu_nack_0_bits_out_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_cmd_0 = io_lsu_nack_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_size_0 = io_lsu_nack_0_bits_out_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_signed_0 = io_lsu_nack_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_fence_0 = io_lsu_nack_0_bits_out_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_fencei_0 = io_lsu_nack_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_amo_0 = io_lsu_nack_0_bits_out_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_uses_ldq_0 = io_lsu_nack_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_uses_stq_0 = io_lsu_nack_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_sys_pc2epc_0 = io_lsu_nack_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_unique_0 = io_lsu_nack_0_bits_out_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_flush_on_commit_0 = io_lsu_nack_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_is_rs1_0 = io_lsu_nack_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_0 = io_lsu_nack_0_bits_out_uop_ldst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs1_0 = io_lsu_nack_0_bits_out_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs2_0 = io_lsu_nack_0_bits_out_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs3_0 = io_lsu_nack_0_bits_out_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_val_0 = io_lsu_nack_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_dst_rtype_0 = io_lsu_nack_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs1_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs2_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_frs3_en_0 = io_lsu_nack_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fp_val_0 = io_lsu_nack_0_bits_out_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fp_single_0 = io_lsu_nack_0_bits_out_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_pf_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_ae_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_ma_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bp_debug_if_0 = io_lsu_nack_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bp_xcpt_if_0 = io_lsu_nack_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_fsrc_0 = io_lsu_nack_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_tsrc_0 = io_lsu_nack_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_addr_0 = io_lsu_nack_0_bits_out_addr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_data_0 = io_lsu_nack_0_bits_out_data; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_is_hella_0 = io_lsu_nack_0_bits_out_is_hella; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_out_uop_br_mask = _io_lsu_nack_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21, :101:23] |
Generate the Verilog code corresponding to this FIRRTL code module Rob :
input clock : Clock
input reset : Reset
output io : { flip enq_valids : UInt<1>[1], flip enq_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip enq_partial_stall : UInt<1>, flip xcpt_fetch_pc : UInt<40>, rob_tail_idx : UInt<5>, rob_pnr_idx : UInt<5>, rob_head_idx : UInt<5>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip wb_resps : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[4], flip lsu_clr_bsy : { valid : UInt<1>, bits : UInt<5>}[2], flip lsu_clr_unsafe : { valid : UInt<1>, bits : UInt<5>}[1], flip debug_wb_valids : UInt<1>[4], flip debug_wb_wdata : UInt<64>[4], flip fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}[2], flip lxcpt : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<40>}}, flip csr_replay : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<40>}}, commit : { valids : UInt<1>[1], arch_valids : UInt<1>[1], uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[1], rbk_valids : UInt<1>[1], rollback : UInt<1>, debug_wdata : UInt<64>[1]}, com_load_is_at_rob_head : UInt<1>, com_xcpt : { valid : UInt<1>, bits : { ftq_idx : UInt<4>, edge_inst : UInt<1>, is_rvc : UInt<1>, pc_lob : UInt<6>, cause : UInt<64>, badvaddr : UInt<64>, flush_typ : UInt<3>}}, flip csr_stall : UInt<1>, flush : { valid : UInt<1>, bits : { ftq_idx : UInt<4>, edge_inst : UInt<1>, is_rvc : UInt<1>, pc_lob : UInt<6>, cause : UInt<64>, badvaddr : UInt<64>, flush_typ : UInt<3>}}, empty : UInt<1>, ready : UInt<1>, flush_frontend : UInt<1>, flip debug_tsc : UInt<64>}
regreset rob_state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset rob_head : UInt<5>, clock, reset, UInt<5>(0h0)
regreset rob_head_lsb : UInt<1>, clock, reset, UInt<1>(0h0)
regreset rob_tail : UInt<5>, clock, reset, UInt<5>(0h0)
regreset rob_tail_lsb : UInt<1>, clock, reset, UInt<1>(0h0)
regreset rob_pnr : UInt<5>, clock, reset, UInt<5>(0h0)
regreset rob_pnr_lsb : UInt<1>, clock, reset, UInt<1>(0h0)
node _com_idx_T = eq(rob_state, UInt<2>(0h2))
node com_idx = mux(_com_idx_T, rob_tail, rob_head)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
wire full : UInt<1>
wire empty : UInt<1>
wire will_commit : UInt<1>[1]
wire can_commit : UInt<1>[1]
wire can_throw_exception : UInt<1>[1]
wire rob_pnr_unsafe : UInt<1>[1]
wire rob_head_vals : UInt<1>[1]
wire rob_tail_vals : UInt<1>[1]
wire rob_head_uses_stq : UInt<1>[1]
wire rob_head_uses_ldq : UInt<1>[1]
wire rob_head_fflags : UInt<5>[1]
wire exception_thrown : UInt<1>
regreset r_xcpt_val : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_xcpt_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
reg r_xcpt_badvaddr : UInt<40>, clock
connect io.flush_frontend, r_xcpt_val
wire debug_entry : { valid : UInt<1>, busy : UInt<1>, unsafe : UInt<1>, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, exception : UInt<1>}[32]
invalidate debug_entry[0].exception
invalidate debug_entry[0].uop.debug_tsrc
invalidate debug_entry[0].uop.debug_fsrc
invalidate debug_entry[0].uop.bp_xcpt_if
invalidate debug_entry[0].uop.bp_debug_if
invalidate debug_entry[0].uop.xcpt_ma_if
invalidate debug_entry[0].uop.xcpt_ae_if
invalidate debug_entry[0].uop.xcpt_pf_if
invalidate debug_entry[0].uop.fp_single
invalidate debug_entry[0].uop.fp_val
invalidate debug_entry[0].uop.frs3_en
invalidate debug_entry[0].uop.lrs2_rtype
invalidate debug_entry[0].uop.lrs1_rtype
invalidate debug_entry[0].uop.dst_rtype
invalidate debug_entry[0].uop.ldst_val
invalidate debug_entry[0].uop.lrs3
invalidate debug_entry[0].uop.lrs2
invalidate debug_entry[0].uop.lrs1
invalidate debug_entry[0].uop.ldst
invalidate debug_entry[0].uop.ldst_is_rs1
invalidate debug_entry[0].uop.flush_on_commit
invalidate debug_entry[0].uop.is_unique
invalidate debug_entry[0].uop.is_sys_pc2epc
invalidate debug_entry[0].uop.uses_stq
invalidate debug_entry[0].uop.uses_ldq
invalidate debug_entry[0].uop.is_amo
invalidate debug_entry[0].uop.is_fencei
invalidate debug_entry[0].uop.is_fence
invalidate debug_entry[0].uop.mem_signed
invalidate debug_entry[0].uop.mem_size
invalidate debug_entry[0].uop.mem_cmd
invalidate debug_entry[0].uop.bypassable
invalidate debug_entry[0].uop.exc_cause
invalidate debug_entry[0].uop.exception
invalidate debug_entry[0].uop.stale_pdst
invalidate debug_entry[0].uop.ppred_busy
invalidate debug_entry[0].uop.prs3_busy
invalidate debug_entry[0].uop.prs2_busy
invalidate debug_entry[0].uop.prs1_busy
invalidate debug_entry[0].uop.ppred
invalidate debug_entry[0].uop.prs3
invalidate debug_entry[0].uop.prs2
invalidate debug_entry[0].uop.prs1
invalidate debug_entry[0].uop.pdst
invalidate debug_entry[0].uop.rxq_idx
invalidate debug_entry[0].uop.stq_idx
invalidate debug_entry[0].uop.ldq_idx
invalidate debug_entry[0].uop.rob_idx
invalidate debug_entry[0].uop.csr_addr
invalidate debug_entry[0].uop.imm_packed
invalidate debug_entry[0].uop.taken
invalidate debug_entry[0].uop.pc_lob
invalidate debug_entry[0].uop.edge_inst
invalidate debug_entry[0].uop.ftq_idx
invalidate debug_entry[0].uop.br_tag
invalidate debug_entry[0].uop.br_mask
invalidate debug_entry[0].uop.is_sfb
invalidate debug_entry[0].uop.is_jal
invalidate debug_entry[0].uop.is_jalr
invalidate debug_entry[0].uop.is_br
invalidate debug_entry[0].uop.iw_p2_poisoned
invalidate debug_entry[0].uop.iw_p1_poisoned
invalidate debug_entry[0].uop.iw_state
invalidate debug_entry[0].uop.ctrl.is_std
invalidate debug_entry[0].uop.ctrl.is_sta
invalidate debug_entry[0].uop.ctrl.is_load
invalidate debug_entry[0].uop.ctrl.csr_cmd
invalidate debug_entry[0].uop.ctrl.fcn_dw
invalidate debug_entry[0].uop.ctrl.op_fcn
invalidate debug_entry[0].uop.ctrl.imm_sel
invalidate debug_entry[0].uop.ctrl.op2_sel
invalidate debug_entry[0].uop.ctrl.op1_sel
invalidate debug_entry[0].uop.ctrl.br_type
invalidate debug_entry[0].uop.fu_code
invalidate debug_entry[0].uop.iq_type
invalidate debug_entry[0].uop.debug_pc
invalidate debug_entry[0].uop.is_rvc
invalidate debug_entry[0].uop.debug_inst
invalidate debug_entry[0].uop.inst
invalidate debug_entry[0].uop.uopc
invalidate debug_entry[0].unsafe
invalidate debug_entry[0].busy
invalidate debug_entry[0].valid
invalidate debug_entry[1].exception
invalidate debug_entry[1].uop.debug_tsrc
invalidate debug_entry[1].uop.debug_fsrc
invalidate debug_entry[1].uop.bp_xcpt_if
invalidate debug_entry[1].uop.bp_debug_if
invalidate debug_entry[1].uop.xcpt_ma_if
invalidate debug_entry[1].uop.xcpt_ae_if
invalidate debug_entry[1].uop.xcpt_pf_if
invalidate debug_entry[1].uop.fp_single
invalidate debug_entry[1].uop.fp_val
invalidate debug_entry[1].uop.frs3_en
invalidate debug_entry[1].uop.lrs2_rtype
invalidate debug_entry[1].uop.lrs1_rtype
invalidate debug_entry[1].uop.dst_rtype
invalidate debug_entry[1].uop.ldst_val
invalidate debug_entry[1].uop.lrs3
invalidate debug_entry[1].uop.lrs2
invalidate debug_entry[1].uop.lrs1
invalidate debug_entry[1].uop.ldst
invalidate debug_entry[1].uop.ldst_is_rs1
invalidate debug_entry[1].uop.flush_on_commit
invalidate debug_entry[1].uop.is_unique
invalidate debug_entry[1].uop.is_sys_pc2epc
invalidate debug_entry[1].uop.uses_stq
invalidate debug_entry[1].uop.uses_ldq
invalidate debug_entry[1].uop.is_amo
invalidate debug_entry[1].uop.is_fencei
invalidate debug_entry[1].uop.is_fence
invalidate debug_entry[1].uop.mem_signed
invalidate debug_entry[1].uop.mem_size
invalidate debug_entry[1].uop.mem_cmd
invalidate debug_entry[1].uop.bypassable
invalidate debug_entry[1].uop.exc_cause
invalidate debug_entry[1].uop.exception
invalidate debug_entry[1].uop.stale_pdst
invalidate debug_entry[1].uop.ppred_busy
invalidate debug_entry[1].uop.prs3_busy
invalidate debug_entry[1].uop.prs2_busy
invalidate debug_entry[1].uop.prs1_busy
invalidate debug_entry[1].uop.ppred
invalidate debug_entry[1].uop.prs3
invalidate debug_entry[1].uop.prs2
invalidate debug_entry[1].uop.prs1
invalidate debug_entry[1].uop.pdst
invalidate debug_entry[1].uop.rxq_idx
invalidate debug_entry[1].uop.stq_idx
invalidate debug_entry[1].uop.ldq_idx
invalidate debug_entry[1].uop.rob_idx
invalidate debug_entry[1].uop.csr_addr
invalidate debug_entry[1].uop.imm_packed
invalidate debug_entry[1].uop.taken
invalidate debug_entry[1].uop.pc_lob
invalidate debug_entry[1].uop.edge_inst
invalidate debug_entry[1].uop.ftq_idx
invalidate debug_entry[1].uop.br_tag
invalidate debug_entry[1].uop.br_mask
invalidate debug_entry[1].uop.is_sfb
invalidate debug_entry[1].uop.is_jal
invalidate debug_entry[1].uop.is_jalr
invalidate debug_entry[1].uop.is_br
invalidate debug_entry[1].uop.iw_p2_poisoned
invalidate debug_entry[1].uop.iw_p1_poisoned
invalidate debug_entry[1].uop.iw_state
invalidate debug_entry[1].uop.ctrl.is_std
invalidate debug_entry[1].uop.ctrl.is_sta
invalidate debug_entry[1].uop.ctrl.is_load
invalidate debug_entry[1].uop.ctrl.csr_cmd
invalidate debug_entry[1].uop.ctrl.fcn_dw
invalidate debug_entry[1].uop.ctrl.op_fcn
invalidate debug_entry[1].uop.ctrl.imm_sel
invalidate debug_entry[1].uop.ctrl.op2_sel
invalidate debug_entry[1].uop.ctrl.op1_sel
invalidate debug_entry[1].uop.ctrl.br_type
invalidate debug_entry[1].uop.fu_code
invalidate debug_entry[1].uop.iq_type
invalidate debug_entry[1].uop.debug_pc
invalidate debug_entry[1].uop.is_rvc
invalidate debug_entry[1].uop.debug_inst
invalidate debug_entry[1].uop.inst
invalidate debug_entry[1].uop.uopc
invalidate debug_entry[1].unsafe
invalidate debug_entry[1].busy
invalidate debug_entry[1].valid
invalidate debug_entry[2].exception
invalidate debug_entry[2].uop.debug_tsrc
invalidate debug_entry[2].uop.debug_fsrc
invalidate debug_entry[2].uop.bp_xcpt_if
invalidate debug_entry[2].uop.bp_debug_if
invalidate debug_entry[2].uop.xcpt_ma_if
invalidate debug_entry[2].uop.xcpt_ae_if
invalidate debug_entry[2].uop.xcpt_pf_if
invalidate debug_entry[2].uop.fp_single
invalidate debug_entry[2].uop.fp_val
invalidate debug_entry[2].uop.frs3_en
invalidate debug_entry[2].uop.lrs2_rtype
invalidate debug_entry[2].uop.lrs1_rtype
invalidate debug_entry[2].uop.dst_rtype
invalidate debug_entry[2].uop.ldst_val
invalidate debug_entry[2].uop.lrs3
invalidate debug_entry[2].uop.lrs2
invalidate debug_entry[2].uop.lrs1
invalidate debug_entry[2].uop.ldst
invalidate debug_entry[2].uop.ldst_is_rs1
invalidate debug_entry[2].uop.flush_on_commit
invalidate debug_entry[2].uop.is_unique
invalidate debug_entry[2].uop.is_sys_pc2epc
invalidate debug_entry[2].uop.uses_stq
invalidate debug_entry[2].uop.uses_ldq
invalidate debug_entry[2].uop.is_amo
invalidate debug_entry[2].uop.is_fencei
invalidate debug_entry[2].uop.is_fence
invalidate debug_entry[2].uop.mem_signed
invalidate debug_entry[2].uop.mem_size
invalidate debug_entry[2].uop.mem_cmd
invalidate debug_entry[2].uop.bypassable
invalidate debug_entry[2].uop.exc_cause
invalidate debug_entry[2].uop.exception
invalidate debug_entry[2].uop.stale_pdst
invalidate debug_entry[2].uop.ppred_busy
invalidate debug_entry[2].uop.prs3_busy
invalidate debug_entry[2].uop.prs2_busy
invalidate debug_entry[2].uop.prs1_busy
invalidate debug_entry[2].uop.ppred
invalidate debug_entry[2].uop.prs3
invalidate debug_entry[2].uop.prs2
invalidate debug_entry[2].uop.prs1
invalidate debug_entry[2].uop.pdst
invalidate debug_entry[2].uop.rxq_idx
invalidate debug_entry[2].uop.stq_idx
invalidate debug_entry[2].uop.ldq_idx
invalidate debug_entry[2].uop.rob_idx
invalidate debug_entry[2].uop.csr_addr
invalidate debug_entry[2].uop.imm_packed
invalidate debug_entry[2].uop.taken
invalidate debug_entry[2].uop.pc_lob
invalidate debug_entry[2].uop.edge_inst
invalidate debug_entry[2].uop.ftq_idx
invalidate debug_entry[2].uop.br_tag
invalidate debug_entry[2].uop.br_mask
invalidate debug_entry[2].uop.is_sfb
invalidate debug_entry[2].uop.is_jal
invalidate debug_entry[2].uop.is_jalr
invalidate debug_entry[2].uop.is_br
invalidate debug_entry[2].uop.iw_p2_poisoned
invalidate debug_entry[2].uop.iw_p1_poisoned
invalidate debug_entry[2].uop.iw_state
invalidate debug_entry[2].uop.ctrl.is_std
invalidate debug_entry[2].uop.ctrl.is_sta
invalidate debug_entry[2].uop.ctrl.is_load
invalidate debug_entry[2].uop.ctrl.csr_cmd
invalidate debug_entry[2].uop.ctrl.fcn_dw
invalidate debug_entry[2].uop.ctrl.op_fcn
invalidate debug_entry[2].uop.ctrl.imm_sel
invalidate debug_entry[2].uop.ctrl.op2_sel
invalidate debug_entry[2].uop.ctrl.op1_sel
invalidate debug_entry[2].uop.ctrl.br_type
invalidate debug_entry[2].uop.fu_code
invalidate debug_entry[2].uop.iq_type
invalidate debug_entry[2].uop.debug_pc
invalidate debug_entry[2].uop.is_rvc
invalidate debug_entry[2].uop.debug_inst
invalidate debug_entry[2].uop.inst
invalidate debug_entry[2].uop.uopc
invalidate debug_entry[2].unsafe
invalidate debug_entry[2].busy
invalidate debug_entry[2].valid
invalidate debug_entry[3].exception
invalidate debug_entry[3].uop.debug_tsrc
invalidate debug_entry[3].uop.debug_fsrc
invalidate debug_entry[3].uop.bp_xcpt_if
invalidate debug_entry[3].uop.bp_debug_if
invalidate debug_entry[3].uop.xcpt_ma_if
invalidate debug_entry[3].uop.xcpt_ae_if
invalidate debug_entry[3].uop.xcpt_pf_if
invalidate debug_entry[3].uop.fp_single
invalidate debug_entry[3].uop.fp_val
invalidate debug_entry[3].uop.frs3_en
invalidate debug_entry[3].uop.lrs2_rtype
invalidate debug_entry[3].uop.lrs1_rtype
invalidate debug_entry[3].uop.dst_rtype
invalidate debug_entry[3].uop.ldst_val
invalidate debug_entry[3].uop.lrs3
invalidate debug_entry[3].uop.lrs2
invalidate debug_entry[3].uop.lrs1
invalidate debug_entry[3].uop.ldst
invalidate debug_entry[3].uop.ldst_is_rs1
invalidate debug_entry[3].uop.flush_on_commit
invalidate debug_entry[3].uop.is_unique
invalidate debug_entry[3].uop.is_sys_pc2epc
invalidate debug_entry[3].uop.uses_stq
invalidate debug_entry[3].uop.uses_ldq
invalidate debug_entry[3].uop.is_amo
invalidate debug_entry[3].uop.is_fencei
invalidate debug_entry[3].uop.is_fence
invalidate debug_entry[3].uop.mem_signed
invalidate debug_entry[3].uop.mem_size
invalidate debug_entry[3].uop.mem_cmd
invalidate debug_entry[3].uop.bypassable
invalidate debug_entry[3].uop.exc_cause
invalidate debug_entry[3].uop.exception
invalidate debug_entry[3].uop.stale_pdst
invalidate debug_entry[3].uop.ppred_busy
invalidate debug_entry[3].uop.prs3_busy
invalidate debug_entry[3].uop.prs2_busy
invalidate debug_entry[3].uop.prs1_busy
invalidate debug_entry[3].uop.ppred
invalidate debug_entry[3].uop.prs3
invalidate debug_entry[3].uop.prs2
invalidate debug_entry[3].uop.prs1
invalidate debug_entry[3].uop.pdst
invalidate debug_entry[3].uop.rxq_idx
invalidate debug_entry[3].uop.stq_idx
invalidate debug_entry[3].uop.ldq_idx
invalidate debug_entry[3].uop.rob_idx
invalidate debug_entry[3].uop.csr_addr
invalidate debug_entry[3].uop.imm_packed
invalidate debug_entry[3].uop.taken
invalidate debug_entry[3].uop.pc_lob
invalidate debug_entry[3].uop.edge_inst
invalidate debug_entry[3].uop.ftq_idx
invalidate debug_entry[3].uop.br_tag
invalidate debug_entry[3].uop.br_mask
invalidate debug_entry[3].uop.is_sfb
invalidate debug_entry[3].uop.is_jal
invalidate debug_entry[3].uop.is_jalr
invalidate debug_entry[3].uop.is_br
invalidate debug_entry[3].uop.iw_p2_poisoned
invalidate debug_entry[3].uop.iw_p1_poisoned
invalidate debug_entry[3].uop.iw_state
invalidate debug_entry[3].uop.ctrl.is_std
invalidate debug_entry[3].uop.ctrl.is_sta
invalidate debug_entry[3].uop.ctrl.is_load
invalidate debug_entry[3].uop.ctrl.csr_cmd
invalidate debug_entry[3].uop.ctrl.fcn_dw
invalidate debug_entry[3].uop.ctrl.op_fcn
invalidate debug_entry[3].uop.ctrl.imm_sel
invalidate debug_entry[3].uop.ctrl.op2_sel
invalidate debug_entry[3].uop.ctrl.op1_sel
invalidate debug_entry[3].uop.ctrl.br_type
invalidate debug_entry[3].uop.fu_code
invalidate debug_entry[3].uop.iq_type
invalidate debug_entry[3].uop.debug_pc
invalidate debug_entry[3].uop.is_rvc
invalidate debug_entry[3].uop.debug_inst
invalidate debug_entry[3].uop.inst
invalidate debug_entry[3].uop.uopc
invalidate debug_entry[3].unsafe
invalidate debug_entry[3].busy
invalidate debug_entry[3].valid
invalidate debug_entry[4].exception
invalidate debug_entry[4].uop.debug_tsrc
invalidate debug_entry[4].uop.debug_fsrc
invalidate debug_entry[4].uop.bp_xcpt_if
invalidate debug_entry[4].uop.bp_debug_if
invalidate debug_entry[4].uop.xcpt_ma_if
invalidate debug_entry[4].uop.xcpt_ae_if
invalidate debug_entry[4].uop.xcpt_pf_if
invalidate debug_entry[4].uop.fp_single
invalidate debug_entry[4].uop.fp_val
invalidate debug_entry[4].uop.frs3_en
invalidate debug_entry[4].uop.lrs2_rtype
invalidate debug_entry[4].uop.lrs1_rtype
invalidate debug_entry[4].uop.dst_rtype
invalidate debug_entry[4].uop.ldst_val
invalidate debug_entry[4].uop.lrs3
invalidate debug_entry[4].uop.lrs2
invalidate debug_entry[4].uop.lrs1
invalidate debug_entry[4].uop.ldst
invalidate debug_entry[4].uop.ldst_is_rs1
invalidate debug_entry[4].uop.flush_on_commit
invalidate debug_entry[4].uop.is_unique
invalidate debug_entry[4].uop.is_sys_pc2epc
invalidate debug_entry[4].uop.uses_stq
invalidate debug_entry[4].uop.uses_ldq
invalidate debug_entry[4].uop.is_amo
invalidate debug_entry[4].uop.is_fencei
invalidate debug_entry[4].uop.is_fence
invalidate debug_entry[4].uop.mem_signed
invalidate debug_entry[4].uop.mem_size
invalidate debug_entry[4].uop.mem_cmd
invalidate debug_entry[4].uop.bypassable
invalidate debug_entry[4].uop.exc_cause
invalidate debug_entry[4].uop.exception
invalidate debug_entry[4].uop.stale_pdst
invalidate debug_entry[4].uop.ppred_busy
invalidate debug_entry[4].uop.prs3_busy
invalidate debug_entry[4].uop.prs2_busy
invalidate debug_entry[4].uop.prs1_busy
invalidate debug_entry[4].uop.ppred
invalidate debug_entry[4].uop.prs3
invalidate debug_entry[4].uop.prs2
invalidate debug_entry[4].uop.prs1
invalidate debug_entry[4].uop.pdst
invalidate debug_entry[4].uop.rxq_idx
invalidate debug_entry[4].uop.stq_idx
invalidate debug_entry[4].uop.ldq_idx
invalidate debug_entry[4].uop.rob_idx
invalidate debug_entry[4].uop.csr_addr
invalidate debug_entry[4].uop.imm_packed
invalidate debug_entry[4].uop.taken
invalidate debug_entry[4].uop.pc_lob
invalidate debug_entry[4].uop.edge_inst
invalidate debug_entry[4].uop.ftq_idx
invalidate debug_entry[4].uop.br_tag
invalidate debug_entry[4].uop.br_mask
invalidate debug_entry[4].uop.is_sfb
invalidate debug_entry[4].uop.is_jal
invalidate debug_entry[4].uop.is_jalr
invalidate debug_entry[4].uop.is_br
invalidate debug_entry[4].uop.iw_p2_poisoned
invalidate debug_entry[4].uop.iw_p1_poisoned
invalidate debug_entry[4].uop.iw_state
invalidate debug_entry[4].uop.ctrl.is_std
invalidate debug_entry[4].uop.ctrl.is_sta
invalidate debug_entry[4].uop.ctrl.is_load
invalidate debug_entry[4].uop.ctrl.csr_cmd
invalidate debug_entry[4].uop.ctrl.fcn_dw
invalidate debug_entry[4].uop.ctrl.op_fcn
invalidate debug_entry[4].uop.ctrl.imm_sel
invalidate debug_entry[4].uop.ctrl.op2_sel
invalidate debug_entry[4].uop.ctrl.op1_sel
invalidate debug_entry[4].uop.ctrl.br_type
invalidate debug_entry[4].uop.fu_code
invalidate debug_entry[4].uop.iq_type
invalidate debug_entry[4].uop.debug_pc
invalidate debug_entry[4].uop.is_rvc
invalidate debug_entry[4].uop.debug_inst
invalidate debug_entry[4].uop.inst
invalidate debug_entry[4].uop.uopc
invalidate debug_entry[4].unsafe
invalidate debug_entry[4].busy
invalidate debug_entry[4].valid
invalidate debug_entry[5].exception
invalidate debug_entry[5].uop.debug_tsrc
invalidate debug_entry[5].uop.debug_fsrc
invalidate debug_entry[5].uop.bp_xcpt_if
invalidate debug_entry[5].uop.bp_debug_if
invalidate debug_entry[5].uop.xcpt_ma_if
invalidate debug_entry[5].uop.xcpt_ae_if
invalidate debug_entry[5].uop.xcpt_pf_if
invalidate debug_entry[5].uop.fp_single
invalidate debug_entry[5].uop.fp_val
invalidate debug_entry[5].uop.frs3_en
invalidate debug_entry[5].uop.lrs2_rtype
invalidate debug_entry[5].uop.lrs1_rtype
invalidate debug_entry[5].uop.dst_rtype
invalidate debug_entry[5].uop.ldst_val
invalidate debug_entry[5].uop.lrs3
invalidate debug_entry[5].uop.lrs2
invalidate debug_entry[5].uop.lrs1
invalidate debug_entry[5].uop.ldst
invalidate debug_entry[5].uop.ldst_is_rs1
invalidate debug_entry[5].uop.flush_on_commit
invalidate debug_entry[5].uop.is_unique
invalidate debug_entry[5].uop.is_sys_pc2epc
invalidate debug_entry[5].uop.uses_stq
invalidate debug_entry[5].uop.uses_ldq
invalidate debug_entry[5].uop.is_amo
invalidate debug_entry[5].uop.is_fencei
invalidate debug_entry[5].uop.is_fence
invalidate debug_entry[5].uop.mem_signed
invalidate debug_entry[5].uop.mem_size
invalidate debug_entry[5].uop.mem_cmd
invalidate debug_entry[5].uop.bypassable
invalidate debug_entry[5].uop.exc_cause
invalidate debug_entry[5].uop.exception
invalidate debug_entry[5].uop.stale_pdst
invalidate debug_entry[5].uop.ppred_busy
invalidate debug_entry[5].uop.prs3_busy
invalidate debug_entry[5].uop.prs2_busy
invalidate debug_entry[5].uop.prs1_busy
invalidate debug_entry[5].uop.ppred
invalidate debug_entry[5].uop.prs3
invalidate debug_entry[5].uop.prs2
invalidate debug_entry[5].uop.prs1
invalidate debug_entry[5].uop.pdst
invalidate debug_entry[5].uop.rxq_idx
invalidate debug_entry[5].uop.stq_idx
invalidate debug_entry[5].uop.ldq_idx
invalidate debug_entry[5].uop.rob_idx
invalidate debug_entry[5].uop.csr_addr
invalidate debug_entry[5].uop.imm_packed
invalidate debug_entry[5].uop.taken
invalidate debug_entry[5].uop.pc_lob
invalidate debug_entry[5].uop.edge_inst
invalidate debug_entry[5].uop.ftq_idx
invalidate debug_entry[5].uop.br_tag
invalidate debug_entry[5].uop.br_mask
invalidate debug_entry[5].uop.is_sfb
invalidate debug_entry[5].uop.is_jal
invalidate debug_entry[5].uop.is_jalr
invalidate debug_entry[5].uop.is_br
invalidate debug_entry[5].uop.iw_p2_poisoned
invalidate debug_entry[5].uop.iw_p1_poisoned
invalidate debug_entry[5].uop.iw_state
invalidate debug_entry[5].uop.ctrl.is_std
invalidate debug_entry[5].uop.ctrl.is_sta
invalidate debug_entry[5].uop.ctrl.is_load
invalidate debug_entry[5].uop.ctrl.csr_cmd
invalidate debug_entry[5].uop.ctrl.fcn_dw
invalidate debug_entry[5].uop.ctrl.op_fcn
invalidate debug_entry[5].uop.ctrl.imm_sel
invalidate debug_entry[5].uop.ctrl.op2_sel
invalidate debug_entry[5].uop.ctrl.op1_sel
invalidate debug_entry[5].uop.ctrl.br_type
invalidate debug_entry[5].uop.fu_code
invalidate debug_entry[5].uop.iq_type
invalidate debug_entry[5].uop.debug_pc
invalidate debug_entry[5].uop.is_rvc
invalidate debug_entry[5].uop.debug_inst
invalidate debug_entry[5].uop.inst
invalidate debug_entry[5].uop.uopc
invalidate debug_entry[5].unsafe
invalidate debug_entry[5].busy
invalidate debug_entry[5].valid
invalidate debug_entry[6].exception
invalidate debug_entry[6].uop.debug_tsrc
invalidate debug_entry[6].uop.debug_fsrc
invalidate debug_entry[6].uop.bp_xcpt_if
invalidate debug_entry[6].uop.bp_debug_if
invalidate debug_entry[6].uop.xcpt_ma_if
invalidate debug_entry[6].uop.xcpt_ae_if
invalidate debug_entry[6].uop.xcpt_pf_if
invalidate debug_entry[6].uop.fp_single
invalidate debug_entry[6].uop.fp_val
invalidate debug_entry[6].uop.frs3_en
invalidate debug_entry[6].uop.lrs2_rtype
invalidate debug_entry[6].uop.lrs1_rtype
invalidate debug_entry[6].uop.dst_rtype
invalidate debug_entry[6].uop.ldst_val
invalidate debug_entry[6].uop.lrs3
invalidate debug_entry[6].uop.lrs2
invalidate debug_entry[6].uop.lrs1
invalidate debug_entry[6].uop.ldst
invalidate debug_entry[6].uop.ldst_is_rs1
invalidate debug_entry[6].uop.flush_on_commit
invalidate debug_entry[6].uop.is_unique
invalidate debug_entry[6].uop.is_sys_pc2epc
invalidate debug_entry[6].uop.uses_stq
invalidate debug_entry[6].uop.uses_ldq
invalidate debug_entry[6].uop.is_amo
invalidate debug_entry[6].uop.is_fencei
invalidate debug_entry[6].uop.is_fence
invalidate debug_entry[6].uop.mem_signed
invalidate debug_entry[6].uop.mem_size
invalidate debug_entry[6].uop.mem_cmd
invalidate debug_entry[6].uop.bypassable
invalidate debug_entry[6].uop.exc_cause
invalidate debug_entry[6].uop.exception
invalidate debug_entry[6].uop.stale_pdst
invalidate debug_entry[6].uop.ppred_busy
invalidate debug_entry[6].uop.prs3_busy
invalidate debug_entry[6].uop.prs2_busy
invalidate debug_entry[6].uop.prs1_busy
invalidate debug_entry[6].uop.ppred
invalidate debug_entry[6].uop.prs3
invalidate debug_entry[6].uop.prs2
invalidate debug_entry[6].uop.prs1
invalidate debug_entry[6].uop.pdst
invalidate debug_entry[6].uop.rxq_idx
invalidate debug_entry[6].uop.stq_idx
invalidate debug_entry[6].uop.ldq_idx
invalidate debug_entry[6].uop.rob_idx
invalidate debug_entry[6].uop.csr_addr
invalidate debug_entry[6].uop.imm_packed
invalidate debug_entry[6].uop.taken
invalidate debug_entry[6].uop.pc_lob
invalidate debug_entry[6].uop.edge_inst
invalidate debug_entry[6].uop.ftq_idx
invalidate debug_entry[6].uop.br_tag
invalidate debug_entry[6].uop.br_mask
invalidate debug_entry[6].uop.is_sfb
invalidate debug_entry[6].uop.is_jal
invalidate debug_entry[6].uop.is_jalr
invalidate debug_entry[6].uop.is_br
invalidate debug_entry[6].uop.iw_p2_poisoned
invalidate debug_entry[6].uop.iw_p1_poisoned
invalidate debug_entry[6].uop.iw_state
invalidate debug_entry[6].uop.ctrl.is_std
invalidate debug_entry[6].uop.ctrl.is_sta
invalidate debug_entry[6].uop.ctrl.is_load
invalidate debug_entry[6].uop.ctrl.csr_cmd
invalidate debug_entry[6].uop.ctrl.fcn_dw
invalidate debug_entry[6].uop.ctrl.op_fcn
invalidate debug_entry[6].uop.ctrl.imm_sel
invalidate debug_entry[6].uop.ctrl.op2_sel
invalidate debug_entry[6].uop.ctrl.op1_sel
invalidate debug_entry[6].uop.ctrl.br_type
invalidate debug_entry[6].uop.fu_code
invalidate debug_entry[6].uop.iq_type
invalidate debug_entry[6].uop.debug_pc
invalidate debug_entry[6].uop.is_rvc
invalidate debug_entry[6].uop.debug_inst
invalidate debug_entry[6].uop.inst
invalidate debug_entry[6].uop.uopc
invalidate debug_entry[6].unsafe
invalidate debug_entry[6].busy
invalidate debug_entry[6].valid
invalidate debug_entry[7].exception
invalidate debug_entry[7].uop.debug_tsrc
invalidate debug_entry[7].uop.debug_fsrc
invalidate debug_entry[7].uop.bp_xcpt_if
invalidate debug_entry[7].uop.bp_debug_if
invalidate debug_entry[7].uop.xcpt_ma_if
invalidate debug_entry[7].uop.xcpt_ae_if
invalidate debug_entry[7].uop.xcpt_pf_if
invalidate debug_entry[7].uop.fp_single
invalidate debug_entry[7].uop.fp_val
invalidate debug_entry[7].uop.frs3_en
invalidate debug_entry[7].uop.lrs2_rtype
invalidate debug_entry[7].uop.lrs1_rtype
invalidate debug_entry[7].uop.dst_rtype
invalidate debug_entry[7].uop.ldst_val
invalidate debug_entry[7].uop.lrs3
invalidate debug_entry[7].uop.lrs2
invalidate debug_entry[7].uop.lrs1
invalidate debug_entry[7].uop.ldst
invalidate debug_entry[7].uop.ldst_is_rs1
invalidate debug_entry[7].uop.flush_on_commit
invalidate debug_entry[7].uop.is_unique
invalidate debug_entry[7].uop.is_sys_pc2epc
invalidate debug_entry[7].uop.uses_stq
invalidate debug_entry[7].uop.uses_ldq
invalidate debug_entry[7].uop.is_amo
invalidate debug_entry[7].uop.is_fencei
invalidate debug_entry[7].uop.is_fence
invalidate debug_entry[7].uop.mem_signed
invalidate debug_entry[7].uop.mem_size
invalidate debug_entry[7].uop.mem_cmd
invalidate debug_entry[7].uop.bypassable
invalidate debug_entry[7].uop.exc_cause
invalidate debug_entry[7].uop.exception
invalidate debug_entry[7].uop.stale_pdst
invalidate debug_entry[7].uop.ppred_busy
invalidate debug_entry[7].uop.prs3_busy
invalidate debug_entry[7].uop.prs2_busy
invalidate debug_entry[7].uop.prs1_busy
invalidate debug_entry[7].uop.ppred
invalidate debug_entry[7].uop.prs3
invalidate debug_entry[7].uop.prs2
invalidate debug_entry[7].uop.prs1
invalidate debug_entry[7].uop.pdst
invalidate debug_entry[7].uop.rxq_idx
invalidate debug_entry[7].uop.stq_idx
invalidate debug_entry[7].uop.ldq_idx
invalidate debug_entry[7].uop.rob_idx
invalidate debug_entry[7].uop.csr_addr
invalidate debug_entry[7].uop.imm_packed
invalidate debug_entry[7].uop.taken
invalidate debug_entry[7].uop.pc_lob
invalidate debug_entry[7].uop.edge_inst
invalidate debug_entry[7].uop.ftq_idx
invalidate debug_entry[7].uop.br_tag
invalidate debug_entry[7].uop.br_mask
invalidate debug_entry[7].uop.is_sfb
invalidate debug_entry[7].uop.is_jal
invalidate debug_entry[7].uop.is_jalr
invalidate debug_entry[7].uop.is_br
invalidate debug_entry[7].uop.iw_p2_poisoned
invalidate debug_entry[7].uop.iw_p1_poisoned
invalidate debug_entry[7].uop.iw_state
invalidate debug_entry[7].uop.ctrl.is_std
invalidate debug_entry[7].uop.ctrl.is_sta
invalidate debug_entry[7].uop.ctrl.is_load
invalidate debug_entry[7].uop.ctrl.csr_cmd
invalidate debug_entry[7].uop.ctrl.fcn_dw
invalidate debug_entry[7].uop.ctrl.op_fcn
invalidate debug_entry[7].uop.ctrl.imm_sel
invalidate debug_entry[7].uop.ctrl.op2_sel
invalidate debug_entry[7].uop.ctrl.op1_sel
invalidate debug_entry[7].uop.ctrl.br_type
invalidate debug_entry[7].uop.fu_code
invalidate debug_entry[7].uop.iq_type
invalidate debug_entry[7].uop.debug_pc
invalidate debug_entry[7].uop.is_rvc
invalidate debug_entry[7].uop.debug_inst
invalidate debug_entry[7].uop.inst
invalidate debug_entry[7].uop.uopc
invalidate debug_entry[7].unsafe
invalidate debug_entry[7].busy
invalidate debug_entry[7].valid
invalidate debug_entry[8].exception
invalidate debug_entry[8].uop.debug_tsrc
invalidate debug_entry[8].uop.debug_fsrc
invalidate debug_entry[8].uop.bp_xcpt_if
invalidate debug_entry[8].uop.bp_debug_if
invalidate debug_entry[8].uop.xcpt_ma_if
invalidate debug_entry[8].uop.xcpt_ae_if
invalidate debug_entry[8].uop.xcpt_pf_if
invalidate debug_entry[8].uop.fp_single
invalidate debug_entry[8].uop.fp_val
invalidate debug_entry[8].uop.frs3_en
invalidate debug_entry[8].uop.lrs2_rtype
invalidate debug_entry[8].uop.lrs1_rtype
invalidate debug_entry[8].uop.dst_rtype
invalidate debug_entry[8].uop.ldst_val
invalidate debug_entry[8].uop.lrs3
invalidate debug_entry[8].uop.lrs2
invalidate debug_entry[8].uop.lrs1
invalidate debug_entry[8].uop.ldst
invalidate debug_entry[8].uop.ldst_is_rs1
invalidate debug_entry[8].uop.flush_on_commit
invalidate debug_entry[8].uop.is_unique
invalidate debug_entry[8].uop.is_sys_pc2epc
invalidate debug_entry[8].uop.uses_stq
invalidate debug_entry[8].uop.uses_ldq
invalidate debug_entry[8].uop.is_amo
invalidate debug_entry[8].uop.is_fencei
invalidate debug_entry[8].uop.is_fence
invalidate debug_entry[8].uop.mem_signed
invalidate debug_entry[8].uop.mem_size
invalidate debug_entry[8].uop.mem_cmd
invalidate debug_entry[8].uop.bypassable
invalidate debug_entry[8].uop.exc_cause
invalidate debug_entry[8].uop.exception
invalidate debug_entry[8].uop.stale_pdst
invalidate debug_entry[8].uop.ppred_busy
invalidate debug_entry[8].uop.prs3_busy
invalidate debug_entry[8].uop.prs2_busy
invalidate debug_entry[8].uop.prs1_busy
invalidate debug_entry[8].uop.ppred
invalidate debug_entry[8].uop.prs3
invalidate debug_entry[8].uop.prs2
invalidate debug_entry[8].uop.prs1
invalidate debug_entry[8].uop.pdst
invalidate debug_entry[8].uop.rxq_idx
invalidate debug_entry[8].uop.stq_idx
invalidate debug_entry[8].uop.ldq_idx
invalidate debug_entry[8].uop.rob_idx
invalidate debug_entry[8].uop.csr_addr
invalidate debug_entry[8].uop.imm_packed
invalidate debug_entry[8].uop.taken
invalidate debug_entry[8].uop.pc_lob
invalidate debug_entry[8].uop.edge_inst
invalidate debug_entry[8].uop.ftq_idx
invalidate debug_entry[8].uop.br_tag
invalidate debug_entry[8].uop.br_mask
invalidate debug_entry[8].uop.is_sfb
invalidate debug_entry[8].uop.is_jal
invalidate debug_entry[8].uop.is_jalr
invalidate debug_entry[8].uop.is_br
invalidate debug_entry[8].uop.iw_p2_poisoned
invalidate debug_entry[8].uop.iw_p1_poisoned
invalidate debug_entry[8].uop.iw_state
invalidate debug_entry[8].uop.ctrl.is_std
invalidate debug_entry[8].uop.ctrl.is_sta
invalidate debug_entry[8].uop.ctrl.is_load
invalidate debug_entry[8].uop.ctrl.csr_cmd
invalidate debug_entry[8].uop.ctrl.fcn_dw
invalidate debug_entry[8].uop.ctrl.op_fcn
invalidate debug_entry[8].uop.ctrl.imm_sel
invalidate debug_entry[8].uop.ctrl.op2_sel
invalidate debug_entry[8].uop.ctrl.op1_sel
invalidate debug_entry[8].uop.ctrl.br_type
invalidate debug_entry[8].uop.fu_code
invalidate debug_entry[8].uop.iq_type
invalidate debug_entry[8].uop.debug_pc
invalidate debug_entry[8].uop.is_rvc
invalidate debug_entry[8].uop.debug_inst
invalidate debug_entry[8].uop.inst
invalidate debug_entry[8].uop.uopc
invalidate debug_entry[8].unsafe
invalidate debug_entry[8].busy
invalidate debug_entry[8].valid
invalidate debug_entry[9].exception
invalidate debug_entry[9].uop.debug_tsrc
invalidate debug_entry[9].uop.debug_fsrc
invalidate debug_entry[9].uop.bp_xcpt_if
invalidate debug_entry[9].uop.bp_debug_if
invalidate debug_entry[9].uop.xcpt_ma_if
invalidate debug_entry[9].uop.xcpt_ae_if
invalidate debug_entry[9].uop.xcpt_pf_if
invalidate debug_entry[9].uop.fp_single
invalidate debug_entry[9].uop.fp_val
invalidate debug_entry[9].uop.frs3_en
invalidate debug_entry[9].uop.lrs2_rtype
invalidate debug_entry[9].uop.lrs1_rtype
invalidate debug_entry[9].uop.dst_rtype
invalidate debug_entry[9].uop.ldst_val
invalidate debug_entry[9].uop.lrs3
invalidate debug_entry[9].uop.lrs2
invalidate debug_entry[9].uop.lrs1
invalidate debug_entry[9].uop.ldst
invalidate debug_entry[9].uop.ldst_is_rs1
invalidate debug_entry[9].uop.flush_on_commit
invalidate debug_entry[9].uop.is_unique
invalidate debug_entry[9].uop.is_sys_pc2epc
invalidate debug_entry[9].uop.uses_stq
invalidate debug_entry[9].uop.uses_ldq
invalidate debug_entry[9].uop.is_amo
invalidate debug_entry[9].uop.is_fencei
invalidate debug_entry[9].uop.is_fence
invalidate debug_entry[9].uop.mem_signed
invalidate debug_entry[9].uop.mem_size
invalidate debug_entry[9].uop.mem_cmd
invalidate debug_entry[9].uop.bypassable
invalidate debug_entry[9].uop.exc_cause
invalidate debug_entry[9].uop.exception
invalidate debug_entry[9].uop.stale_pdst
invalidate debug_entry[9].uop.ppred_busy
invalidate debug_entry[9].uop.prs3_busy
invalidate debug_entry[9].uop.prs2_busy
invalidate debug_entry[9].uop.prs1_busy
invalidate debug_entry[9].uop.ppred
invalidate debug_entry[9].uop.prs3
invalidate debug_entry[9].uop.prs2
invalidate debug_entry[9].uop.prs1
invalidate debug_entry[9].uop.pdst
invalidate debug_entry[9].uop.rxq_idx
invalidate debug_entry[9].uop.stq_idx
invalidate debug_entry[9].uop.ldq_idx
invalidate debug_entry[9].uop.rob_idx
invalidate debug_entry[9].uop.csr_addr
invalidate debug_entry[9].uop.imm_packed
invalidate debug_entry[9].uop.taken
invalidate debug_entry[9].uop.pc_lob
invalidate debug_entry[9].uop.edge_inst
invalidate debug_entry[9].uop.ftq_idx
invalidate debug_entry[9].uop.br_tag
invalidate debug_entry[9].uop.br_mask
invalidate debug_entry[9].uop.is_sfb
invalidate debug_entry[9].uop.is_jal
invalidate debug_entry[9].uop.is_jalr
invalidate debug_entry[9].uop.is_br
invalidate debug_entry[9].uop.iw_p2_poisoned
invalidate debug_entry[9].uop.iw_p1_poisoned
invalidate debug_entry[9].uop.iw_state
invalidate debug_entry[9].uop.ctrl.is_std
invalidate debug_entry[9].uop.ctrl.is_sta
invalidate debug_entry[9].uop.ctrl.is_load
invalidate debug_entry[9].uop.ctrl.csr_cmd
invalidate debug_entry[9].uop.ctrl.fcn_dw
invalidate debug_entry[9].uop.ctrl.op_fcn
invalidate debug_entry[9].uop.ctrl.imm_sel
invalidate debug_entry[9].uop.ctrl.op2_sel
invalidate debug_entry[9].uop.ctrl.op1_sel
invalidate debug_entry[9].uop.ctrl.br_type
invalidate debug_entry[9].uop.fu_code
invalidate debug_entry[9].uop.iq_type
invalidate debug_entry[9].uop.debug_pc
invalidate debug_entry[9].uop.is_rvc
invalidate debug_entry[9].uop.debug_inst
invalidate debug_entry[9].uop.inst
invalidate debug_entry[9].uop.uopc
invalidate debug_entry[9].unsafe
invalidate debug_entry[9].busy
invalidate debug_entry[9].valid
invalidate debug_entry[10].exception
invalidate debug_entry[10].uop.debug_tsrc
invalidate debug_entry[10].uop.debug_fsrc
invalidate debug_entry[10].uop.bp_xcpt_if
invalidate debug_entry[10].uop.bp_debug_if
invalidate debug_entry[10].uop.xcpt_ma_if
invalidate debug_entry[10].uop.xcpt_ae_if
invalidate debug_entry[10].uop.xcpt_pf_if
invalidate debug_entry[10].uop.fp_single
invalidate debug_entry[10].uop.fp_val
invalidate debug_entry[10].uop.frs3_en
invalidate debug_entry[10].uop.lrs2_rtype
invalidate debug_entry[10].uop.lrs1_rtype
invalidate debug_entry[10].uop.dst_rtype
invalidate debug_entry[10].uop.ldst_val
invalidate debug_entry[10].uop.lrs3
invalidate debug_entry[10].uop.lrs2
invalidate debug_entry[10].uop.lrs1
invalidate debug_entry[10].uop.ldst
invalidate debug_entry[10].uop.ldst_is_rs1
invalidate debug_entry[10].uop.flush_on_commit
invalidate debug_entry[10].uop.is_unique
invalidate debug_entry[10].uop.is_sys_pc2epc
invalidate debug_entry[10].uop.uses_stq
invalidate debug_entry[10].uop.uses_ldq
invalidate debug_entry[10].uop.is_amo
invalidate debug_entry[10].uop.is_fencei
invalidate debug_entry[10].uop.is_fence
invalidate debug_entry[10].uop.mem_signed
invalidate debug_entry[10].uop.mem_size
invalidate debug_entry[10].uop.mem_cmd
invalidate debug_entry[10].uop.bypassable
invalidate debug_entry[10].uop.exc_cause
invalidate debug_entry[10].uop.exception
invalidate debug_entry[10].uop.stale_pdst
invalidate debug_entry[10].uop.ppred_busy
invalidate debug_entry[10].uop.prs3_busy
invalidate debug_entry[10].uop.prs2_busy
invalidate debug_entry[10].uop.prs1_busy
invalidate debug_entry[10].uop.ppred
invalidate debug_entry[10].uop.prs3
invalidate debug_entry[10].uop.prs2
invalidate debug_entry[10].uop.prs1
invalidate debug_entry[10].uop.pdst
invalidate debug_entry[10].uop.rxq_idx
invalidate debug_entry[10].uop.stq_idx
invalidate debug_entry[10].uop.ldq_idx
invalidate debug_entry[10].uop.rob_idx
invalidate debug_entry[10].uop.csr_addr
invalidate debug_entry[10].uop.imm_packed
invalidate debug_entry[10].uop.taken
invalidate debug_entry[10].uop.pc_lob
invalidate debug_entry[10].uop.edge_inst
invalidate debug_entry[10].uop.ftq_idx
invalidate debug_entry[10].uop.br_tag
invalidate debug_entry[10].uop.br_mask
invalidate debug_entry[10].uop.is_sfb
invalidate debug_entry[10].uop.is_jal
invalidate debug_entry[10].uop.is_jalr
invalidate debug_entry[10].uop.is_br
invalidate debug_entry[10].uop.iw_p2_poisoned
invalidate debug_entry[10].uop.iw_p1_poisoned
invalidate debug_entry[10].uop.iw_state
invalidate debug_entry[10].uop.ctrl.is_std
invalidate debug_entry[10].uop.ctrl.is_sta
invalidate debug_entry[10].uop.ctrl.is_load
invalidate debug_entry[10].uop.ctrl.csr_cmd
invalidate debug_entry[10].uop.ctrl.fcn_dw
invalidate debug_entry[10].uop.ctrl.op_fcn
invalidate debug_entry[10].uop.ctrl.imm_sel
invalidate debug_entry[10].uop.ctrl.op2_sel
invalidate debug_entry[10].uop.ctrl.op1_sel
invalidate debug_entry[10].uop.ctrl.br_type
invalidate debug_entry[10].uop.fu_code
invalidate debug_entry[10].uop.iq_type
invalidate debug_entry[10].uop.debug_pc
invalidate debug_entry[10].uop.is_rvc
invalidate debug_entry[10].uop.debug_inst
invalidate debug_entry[10].uop.inst
invalidate debug_entry[10].uop.uopc
invalidate debug_entry[10].unsafe
invalidate debug_entry[10].busy
invalidate debug_entry[10].valid
invalidate debug_entry[11].exception
invalidate debug_entry[11].uop.debug_tsrc
invalidate debug_entry[11].uop.debug_fsrc
invalidate debug_entry[11].uop.bp_xcpt_if
invalidate debug_entry[11].uop.bp_debug_if
invalidate debug_entry[11].uop.xcpt_ma_if
invalidate debug_entry[11].uop.xcpt_ae_if
invalidate debug_entry[11].uop.xcpt_pf_if
invalidate debug_entry[11].uop.fp_single
invalidate debug_entry[11].uop.fp_val
invalidate debug_entry[11].uop.frs3_en
invalidate debug_entry[11].uop.lrs2_rtype
invalidate debug_entry[11].uop.lrs1_rtype
invalidate debug_entry[11].uop.dst_rtype
invalidate debug_entry[11].uop.ldst_val
invalidate debug_entry[11].uop.lrs3
invalidate debug_entry[11].uop.lrs2
invalidate debug_entry[11].uop.lrs1
invalidate debug_entry[11].uop.ldst
invalidate debug_entry[11].uop.ldst_is_rs1
invalidate debug_entry[11].uop.flush_on_commit
invalidate debug_entry[11].uop.is_unique
invalidate debug_entry[11].uop.is_sys_pc2epc
invalidate debug_entry[11].uop.uses_stq
invalidate debug_entry[11].uop.uses_ldq
invalidate debug_entry[11].uop.is_amo
invalidate debug_entry[11].uop.is_fencei
invalidate debug_entry[11].uop.is_fence
invalidate debug_entry[11].uop.mem_signed
invalidate debug_entry[11].uop.mem_size
invalidate debug_entry[11].uop.mem_cmd
invalidate debug_entry[11].uop.bypassable
invalidate debug_entry[11].uop.exc_cause
invalidate debug_entry[11].uop.exception
invalidate debug_entry[11].uop.stale_pdst
invalidate debug_entry[11].uop.ppred_busy
invalidate debug_entry[11].uop.prs3_busy
invalidate debug_entry[11].uop.prs2_busy
invalidate debug_entry[11].uop.prs1_busy
invalidate debug_entry[11].uop.ppred
invalidate debug_entry[11].uop.prs3
invalidate debug_entry[11].uop.prs2
invalidate debug_entry[11].uop.prs1
invalidate debug_entry[11].uop.pdst
invalidate debug_entry[11].uop.rxq_idx
invalidate debug_entry[11].uop.stq_idx
invalidate debug_entry[11].uop.ldq_idx
invalidate debug_entry[11].uop.rob_idx
invalidate debug_entry[11].uop.csr_addr
invalidate debug_entry[11].uop.imm_packed
invalidate debug_entry[11].uop.taken
invalidate debug_entry[11].uop.pc_lob
invalidate debug_entry[11].uop.edge_inst
invalidate debug_entry[11].uop.ftq_idx
invalidate debug_entry[11].uop.br_tag
invalidate debug_entry[11].uop.br_mask
invalidate debug_entry[11].uop.is_sfb
invalidate debug_entry[11].uop.is_jal
invalidate debug_entry[11].uop.is_jalr
invalidate debug_entry[11].uop.is_br
invalidate debug_entry[11].uop.iw_p2_poisoned
invalidate debug_entry[11].uop.iw_p1_poisoned
invalidate debug_entry[11].uop.iw_state
invalidate debug_entry[11].uop.ctrl.is_std
invalidate debug_entry[11].uop.ctrl.is_sta
invalidate debug_entry[11].uop.ctrl.is_load
invalidate debug_entry[11].uop.ctrl.csr_cmd
invalidate debug_entry[11].uop.ctrl.fcn_dw
invalidate debug_entry[11].uop.ctrl.op_fcn
invalidate debug_entry[11].uop.ctrl.imm_sel
invalidate debug_entry[11].uop.ctrl.op2_sel
invalidate debug_entry[11].uop.ctrl.op1_sel
invalidate debug_entry[11].uop.ctrl.br_type
invalidate debug_entry[11].uop.fu_code
invalidate debug_entry[11].uop.iq_type
invalidate debug_entry[11].uop.debug_pc
invalidate debug_entry[11].uop.is_rvc
invalidate debug_entry[11].uop.debug_inst
invalidate debug_entry[11].uop.inst
invalidate debug_entry[11].uop.uopc
invalidate debug_entry[11].unsafe
invalidate debug_entry[11].busy
invalidate debug_entry[11].valid
invalidate debug_entry[12].exception
invalidate debug_entry[12].uop.debug_tsrc
invalidate debug_entry[12].uop.debug_fsrc
invalidate debug_entry[12].uop.bp_xcpt_if
invalidate debug_entry[12].uop.bp_debug_if
invalidate debug_entry[12].uop.xcpt_ma_if
invalidate debug_entry[12].uop.xcpt_ae_if
invalidate debug_entry[12].uop.xcpt_pf_if
invalidate debug_entry[12].uop.fp_single
invalidate debug_entry[12].uop.fp_val
invalidate debug_entry[12].uop.frs3_en
invalidate debug_entry[12].uop.lrs2_rtype
invalidate debug_entry[12].uop.lrs1_rtype
invalidate debug_entry[12].uop.dst_rtype
invalidate debug_entry[12].uop.ldst_val
invalidate debug_entry[12].uop.lrs3
invalidate debug_entry[12].uop.lrs2
invalidate debug_entry[12].uop.lrs1
invalidate debug_entry[12].uop.ldst
invalidate debug_entry[12].uop.ldst_is_rs1
invalidate debug_entry[12].uop.flush_on_commit
invalidate debug_entry[12].uop.is_unique
invalidate debug_entry[12].uop.is_sys_pc2epc
invalidate debug_entry[12].uop.uses_stq
invalidate debug_entry[12].uop.uses_ldq
invalidate debug_entry[12].uop.is_amo
invalidate debug_entry[12].uop.is_fencei
invalidate debug_entry[12].uop.is_fence
invalidate debug_entry[12].uop.mem_signed
invalidate debug_entry[12].uop.mem_size
invalidate debug_entry[12].uop.mem_cmd
invalidate debug_entry[12].uop.bypassable
invalidate debug_entry[12].uop.exc_cause
invalidate debug_entry[12].uop.exception
invalidate debug_entry[12].uop.stale_pdst
invalidate debug_entry[12].uop.ppred_busy
invalidate debug_entry[12].uop.prs3_busy
invalidate debug_entry[12].uop.prs2_busy
invalidate debug_entry[12].uop.prs1_busy
invalidate debug_entry[12].uop.ppred
invalidate debug_entry[12].uop.prs3
invalidate debug_entry[12].uop.prs2
invalidate debug_entry[12].uop.prs1
invalidate debug_entry[12].uop.pdst
invalidate debug_entry[12].uop.rxq_idx
invalidate debug_entry[12].uop.stq_idx
invalidate debug_entry[12].uop.ldq_idx
invalidate debug_entry[12].uop.rob_idx
invalidate debug_entry[12].uop.csr_addr
invalidate debug_entry[12].uop.imm_packed
invalidate debug_entry[12].uop.taken
invalidate debug_entry[12].uop.pc_lob
invalidate debug_entry[12].uop.edge_inst
invalidate debug_entry[12].uop.ftq_idx
invalidate debug_entry[12].uop.br_tag
invalidate debug_entry[12].uop.br_mask
invalidate debug_entry[12].uop.is_sfb
invalidate debug_entry[12].uop.is_jal
invalidate debug_entry[12].uop.is_jalr
invalidate debug_entry[12].uop.is_br
invalidate debug_entry[12].uop.iw_p2_poisoned
invalidate debug_entry[12].uop.iw_p1_poisoned
invalidate debug_entry[12].uop.iw_state
invalidate debug_entry[12].uop.ctrl.is_std
invalidate debug_entry[12].uop.ctrl.is_sta
invalidate debug_entry[12].uop.ctrl.is_load
invalidate debug_entry[12].uop.ctrl.csr_cmd
invalidate debug_entry[12].uop.ctrl.fcn_dw
invalidate debug_entry[12].uop.ctrl.op_fcn
invalidate debug_entry[12].uop.ctrl.imm_sel
invalidate debug_entry[12].uop.ctrl.op2_sel
invalidate debug_entry[12].uop.ctrl.op1_sel
invalidate debug_entry[12].uop.ctrl.br_type
invalidate debug_entry[12].uop.fu_code
invalidate debug_entry[12].uop.iq_type
invalidate debug_entry[12].uop.debug_pc
invalidate debug_entry[12].uop.is_rvc
invalidate debug_entry[12].uop.debug_inst
invalidate debug_entry[12].uop.inst
invalidate debug_entry[12].uop.uopc
invalidate debug_entry[12].unsafe
invalidate debug_entry[12].busy
invalidate debug_entry[12].valid
invalidate debug_entry[13].exception
invalidate debug_entry[13].uop.debug_tsrc
invalidate debug_entry[13].uop.debug_fsrc
invalidate debug_entry[13].uop.bp_xcpt_if
invalidate debug_entry[13].uop.bp_debug_if
invalidate debug_entry[13].uop.xcpt_ma_if
invalidate debug_entry[13].uop.xcpt_ae_if
invalidate debug_entry[13].uop.xcpt_pf_if
invalidate debug_entry[13].uop.fp_single
invalidate debug_entry[13].uop.fp_val
invalidate debug_entry[13].uop.frs3_en
invalidate debug_entry[13].uop.lrs2_rtype
invalidate debug_entry[13].uop.lrs1_rtype
invalidate debug_entry[13].uop.dst_rtype
invalidate debug_entry[13].uop.ldst_val
invalidate debug_entry[13].uop.lrs3
invalidate debug_entry[13].uop.lrs2
invalidate debug_entry[13].uop.lrs1
invalidate debug_entry[13].uop.ldst
invalidate debug_entry[13].uop.ldst_is_rs1
invalidate debug_entry[13].uop.flush_on_commit
invalidate debug_entry[13].uop.is_unique
invalidate debug_entry[13].uop.is_sys_pc2epc
invalidate debug_entry[13].uop.uses_stq
invalidate debug_entry[13].uop.uses_ldq
invalidate debug_entry[13].uop.is_amo
invalidate debug_entry[13].uop.is_fencei
invalidate debug_entry[13].uop.is_fence
invalidate debug_entry[13].uop.mem_signed
invalidate debug_entry[13].uop.mem_size
invalidate debug_entry[13].uop.mem_cmd
invalidate debug_entry[13].uop.bypassable
invalidate debug_entry[13].uop.exc_cause
invalidate debug_entry[13].uop.exception
invalidate debug_entry[13].uop.stale_pdst
invalidate debug_entry[13].uop.ppred_busy
invalidate debug_entry[13].uop.prs3_busy
invalidate debug_entry[13].uop.prs2_busy
invalidate debug_entry[13].uop.prs1_busy
invalidate debug_entry[13].uop.ppred
invalidate debug_entry[13].uop.prs3
invalidate debug_entry[13].uop.prs2
invalidate debug_entry[13].uop.prs1
invalidate debug_entry[13].uop.pdst
invalidate debug_entry[13].uop.rxq_idx
invalidate debug_entry[13].uop.stq_idx
invalidate debug_entry[13].uop.ldq_idx
invalidate debug_entry[13].uop.rob_idx
invalidate debug_entry[13].uop.csr_addr
invalidate debug_entry[13].uop.imm_packed
invalidate debug_entry[13].uop.taken
invalidate debug_entry[13].uop.pc_lob
invalidate debug_entry[13].uop.edge_inst
invalidate debug_entry[13].uop.ftq_idx
invalidate debug_entry[13].uop.br_tag
invalidate debug_entry[13].uop.br_mask
invalidate debug_entry[13].uop.is_sfb
invalidate debug_entry[13].uop.is_jal
invalidate debug_entry[13].uop.is_jalr
invalidate debug_entry[13].uop.is_br
invalidate debug_entry[13].uop.iw_p2_poisoned
invalidate debug_entry[13].uop.iw_p1_poisoned
invalidate debug_entry[13].uop.iw_state
invalidate debug_entry[13].uop.ctrl.is_std
invalidate debug_entry[13].uop.ctrl.is_sta
invalidate debug_entry[13].uop.ctrl.is_load
invalidate debug_entry[13].uop.ctrl.csr_cmd
invalidate debug_entry[13].uop.ctrl.fcn_dw
invalidate debug_entry[13].uop.ctrl.op_fcn
invalidate debug_entry[13].uop.ctrl.imm_sel
invalidate debug_entry[13].uop.ctrl.op2_sel
invalidate debug_entry[13].uop.ctrl.op1_sel
invalidate debug_entry[13].uop.ctrl.br_type
invalidate debug_entry[13].uop.fu_code
invalidate debug_entry[13].uop.iq_type
invalidate debug_entry[13].uop.debug_pc
invalidate debug_entry[13].uop.is_rvc
invalidate debug_entry[13].uop.debug_inst
invalidate debug_entry[13].uop.inst
invalidate debug_entry[13].uop.uopc
invalidate debug_entry[13].unsafe
invalidate debug_entry[13].busy
invalidate debug_entry[13].valid
invalidate debug_entry[14].exception
invalidate debug_entry[14].uop.debug_tsrc
invalidate debug_entry[14].uop.debug_fsrc
invalidate debug_entry[14].uop.bp_xcpt_if
invalidate debug_entry[14].uop.bp_debug_if
invalidate debug_entry[14].uop.xcpt_ma_if
invalidate debug_entry[14].uop.xcpt_ae_if
invalidate debug_entry[14].uop.xcpt_pf_if
invalidate debug_entry[14].uop.fp_single
invalidate debug_entry[14].uop.fp_val
invalidate debug_entry[14].uop.frs3_en
invalidate debug_entry[14].uop.lrs2_rtype
invalidate debug_entry[14].uop.lrs1_rtype
invalidate debug_entry[14].uop.dst_rtype
invalidate debug_entry[14].uop.ldst_val
invalidate debug_entry[14].uop.lrs3
invalidate debug_entry[14].uop.lrs2
invalidate debug_entry[14].uop.lrs1
invalidate debug_entry[14].uop.ldst
invalidate debug_entry[14].uop.ldst_is_rs1
invalidate debug_entry[14].uop.flush_on_commit
invalidate debug_entry[14].uop.is_unique
invalidate debug_entry[14].uop.is_sys_pc2epc
invalidate debug_entry[14].uop.uses_stq
invalidate debug_entry[14].uop.uses_ldq
invalidate debug_entry[14].uop.is_amo
invalidate debug_entry[14].uop.is_fencei
invalidate debug_entry[14].uop.is_fence
invalidate debug_entry[14].uop.mem_signed
invalidate debug_entry[14].uop.mem_size
invalidate debug_entry[14].uop.mem_cmd
invalidate debug_entry[14].uop.bypassable
invalidate debug_entry[14].uop.exc_cause
invalidate debug_entry[14].uop.exception
invalidate debug_entry[14].uop.stale_pdst
invalidate debug_entry[14].uop.ppred_busy
invalidate debug_entry[14].uop.prs3_busy
invalidate debug_entry[14].uop.prs2_busy
invalidate debug_entry[14].uop.prs1_busy
invalidate debug_entry[14].uop.ppred
invalidate debug_entry[14].uop.prs3
invalidate debug_entry[14].uop.prs2
invalidate debug_entry[14].uop.prs1
invalidate debug_entry[14].uop.pdst
invalidate debug_entry[14].uop.rxq_idx
invalidate debug_entry[14].uop.stq_idx
invalidate debug_entry[14].uop.ldq_idx
invalidate debug_entry[14].uop.rob_idx
invalidate debug_entry[14].uop.csr_addr
invalidate debug_entry[14].uop.imm_packed
invalidate debug_entry[14].uop.taken
invalidate debug_entry[14].uop.pc_lob
invalidate debug_entry[14].uop.edge_inst
invalidate debug_entry[14].uop.ftq_idx
invalidate debug_entry[14].uop.br_tag
invalidate debug_entry[14].uop.br_mask
invalidate debug_entry[14].uop.is_sfb
invalidate debug_entry[14].uop.is_jal
invalidate debug_entry[14].uop.is_jalr
invalidate debug_entry[14].uop.is_br
invalidate debug_entry[14].uop.iw_p2_poisoned
invalidate debug_entry[14].uop.iw_p1_poisoned
invalidate debug_entry[14].uop.iw_state
invalidate debug_entry[14].uop.ctrl.is_std
invalidate debug_entry[14].uop.ctrl.is_sta
invalidate debug_entry[14].uop.ctrl.is_load
invalidate debug_entry[14].uop.ctrl.csr_cmd
invalidate debug_entry[14].uop.ctrl.fcn_dw
invalidate debug_entry[14].uop.ctrl.op_fcn
invalidate debug_entry[14].uop.ctrl.imm_sel
invalidate debug_entry[14].uop.ctrl.op2_sel
invalidate debug_entry[14].uop.ctrl.op1_sel
invalidate debug_entry[14].uop.ctrl.br_type
invalidate debug_entry[14].uop.fu_code
invalidate debug_entry[14].uop.iq_type
invalidate debug_entry[14].uop.debug_pc
invalidate debug_entry[14].uop.is_rvc
invalidate debug_entry[14].uop.debug_inst
invalidate debug_entry[14].uop.inst
invalidate debug_entry[14].uop.uopc
invalidate debug_entry[14].unsafe
invalidate debug_entry[14].busy
invalidate debug_entry[14].valid
invalidate debug_entry[15].exception
invalidate debug_entry[15].uop.debug_tsrc
invalidate debug_entry[15].uop.debug_fsrc
invalidate debug_entry[15].uop.bp_xcpt_if
invalidate debug_entry[15].uop.bp_debug_if
invalidate debug_entry[15].uop.xcpt_ma_if
invalidate debug_entry[15].uop.xcpt_ae_if
invalidate debug_entry[15].uop.xcpt_pf_if
invalidate debug_entry[15].uop.fp_single
invalidate debug_entry[15].uop.fp_val
invalidate debug_entry[15].uop.frs3_en
invalidate debug_entry[15].uop.lrs2_rtype
invalidate debug_entry[15].uop.lrs1_rtype
invalidate debug_entry[15].uop.dst_rtype
invalidate debug_entry[15].uop.ldst_val
invalidate debug_entry[15].uop.lrs3
invalidate debug_entry[15].uop.lrs2
invalidate debug_entry[15].uop.lrs1
invalidate debug_entry[15].uop.ldst
invalidate debug_entry[15].uop.ldst_is_rs1
invalidate debug_entry[15].uop.flush_on_commit
invalidate debug_entry[15].uop.is_unique
invalidate debug_entry[15].uop.is_sys_pc2epc
invalidate debug_entry[15].uop.uses_stq
invalidate debug_entry[15].uop.uses_ldq
invalidate debug_entry[15].uop.is_amo
invalidate debug_entry[15].uop.is_fencei
invalidate debug_entry[15].uop.is_fence
invalidate debug_entry[15].uop.mem_signed
invalidate debug_entry[15].uop.mem_size
invalidate debug_entry[15].uop.mem_cmd
invalidate debug_entry[15].uop.bypassable
invalidate debug_entry[15].uop.exc_cause
invalidate debug_entry[15].uop.exception
invalidate debug_entry[15].uop.stale_pdst
invalidate debug_entry[15].uop.ppred_busy
invalidate debug_entry[15].uop.prs3_busy
invalidate debug_entry[15].uop.prs2_busy
invalidate debug_entry[15].uop.prs1_busy
invalidate debug_entry[15].uop.ppred
invalidate debug_entry[15].uop.prs3
invalidate debug_entry[15].uop.prs2
invalidate debug_entry[15].uop.prs1
invalidate debug_entry[15].uop.pdst
invalidate debug_entry[15].uop.rxq_idx
invalidate debug_entry[15].uop.stq_idx
invalidate debug_entry[15].uop.ldq_idx
invalidate debug_entry[15].uop.rob_idx
invalidate debug_entry[15].uop.csr_addr
invalidate debug_entry[15].uop.imm_packed
invalidate debug_entry[15].uop.taken
invalidate debug_entry[15].uop.pc_lob
invalidate debug_entry[15].uop.edge_inst
invalidate debug_entry[15].uop.ftq_idx
invalidate debug_entry[15].uop.br_tag
invalidate debug_entry[15].uop.br_mask
invalidate debug_entry[15].uop.is_sfb
invalidate debug_entry[15].uop.is_jal
invalidate debug_entry[15].uop.is_jalr
invalidate debug_entry[15].uop.is_br
invalidate debug_entry[15].uop.iw_p2_poisoned
invalidate debug_entry[15].uop.iw_p1_poisoned
invalidate debug_entry[15].uop.iw_state
invalidate debug_entry[15].uop.ctrl.is_std
invalidate debug_entry[15].uop.ctrl.is_sta
invalidate debug_entry[15].uop.ctrl.is_load
invalidate debug_entry[15].uop.ctrl.csr_cmd
invalidate debug_entry[15].uop.ctrl.fcn_dw
invalidate debug_entry[15].uop.ctrl.op_fcn
invalidate debug_entry[15].uop.ctrl.imm_sel
invalidate debug_entry[15].uop.ctrl.op2_sel
invalidate debug_entry[15].uop.ctrl.op1_sel
invalidate debug_entry[15].uop.ctrl.br_type
invalidate debug_entry[15].uop.fu_code
invalidate debug_entry[15].uop.iq_type
invalidate debug_entry[15].uop.debug_pc
invalidate debug_entry[15].uop.is_rvc
invalidate debug_entry[15].uop.debug_inst
invalidate debug_entry[15].uop.inst
invalidate debug_entry[15].uop.uopc
invalidate debug_entry[15].unsafe
invalidate debug_entry[15].busy
invalidate debug_entry[15].valid
invalidate debug_entry[16].exception
invalidate debug_entry[16].uop.debug_tsrc
invalidate debug_entry[16].uop.debug_fsrc
invalidate debug_entry[16].uop.bp_xcpt_if
invalidate debug_entry[16].uop.bp_debug_if
invalidate debug_entry[16].uop.xcpt_ma_if
invalidate debug_entry[16].uop.xcpt_ae_if
invalidate debug_entry[16].uop.xcpt_pf_if
invalidate debug_entry[16].uop.fp_single
invalidate debug_entry[16].uop.fp_val
invalidate debug_entry[16].uop.frs3_en
invalidate debug_entry[16].uop.lrs2_rtype
invalidate debug_entry[16].uop.lrs1_rtype
invalidate debug_entry[16].uop.dst_rtype
invalidate debug_entry[16].uop.ldst_val
invalidate debug_entry[16].uop.lrs3
invalidate debug_entry[16].uop.lrs2
invalidate debug_entry[16].uop.lrs1
invalidate debug_entry[16].uop.ldst
invalidate debug_entry[16].uop.ldst_is_rs1
invalidate debug_entry[16].uop.flush_on_commit
invalidate debug_entry[16].uop.is_unique
invalidate debug_entry[16].uop.is_sys_pc2epc
invalidate debug_entry[16].uop.uses_stq
invalidate debug_entry[16].uop.uses_ldq
invalidate debug_entry[16].uop.is_amo
invalidate debug_entry[16].uop.is_fencei
invalidate debug_entry[16].uop.is_fence
invalidate debug_entry[16].uop.mem_signed
invalidate debug_entry[16].uop.mem_size
invalidate debug_entry[16].uop.mem_cmd
invalidate debug_entry[16].uop.bypassable
invalidate debug_entry[16].uop.exc_cause
invalidate debug_entry[16].uop.exception
invalidate debug_entry[16].uop.stale_pdst
invalidate debug_entry[16].uop.ppred_busy
invalidate debug_entry[16].uop.prs3_busy
invalidate debug_entry[16].uop.prs2_busy
invalidate debug_entry[16].uop.prs1_busy
invalidate debug_entry[16].uop.ppred
invalidate debug_entry[16].uop.prs3
invalidate debug_entry[16].uop.prs2
invalidate debug_entry[16].uop.prs1
invalidate debug_entry[16].uop.pdst
invalidate debug_entry[16].uop.rxq_idx
invalidate debug_entry[16].uop.stq_idx
invalidate debug_entry[16].uop.ldq_idx
invalidate debug_entry[16].uop.rob_idx
invalidate debug_entry[16].uop.csr_addr
invalidate debug_entry[16].uop.imm_packed
invalidate debug_entry[16].uop.taken
invalidate debug_entry[16].uop.pc_lob
invalidate debug_entry[16].uop.edge_inst
invalidate debug_entry[16].uop.ftq_idx
invalidate debug_entry[16].uop.br_tag
invalidate debug_entry[16].uop.br_mask
invalidate debug_entry[16].uop.is_sfb
invalidate debug_entry[16].uop.is_jal
invalidate debug_entry[16].uop.is_jalr
invalidate debug_entry[16].uop.is_br
invalidate debug_entry[16].uop.iw_p2_poisoned
invalidate debug_entry[16].uop.iw_p1_poisoned
invalidate debug_entry[16].uop.iw_state
invalidate debug_entry[16].uop.ctrl.is_std
invalidate debug_entry[16].uop.ctrl.is_sta
invalidate debug_entry[16].uop.ctrl.is_load
invalidate debug_entry[16].uop.ctrl.csr_cmd
invalidate debug_entry[16].uop.ctrl.fcn_dw
invalidate debug_entry[16].uop.ctrl.op_fcn
invalidate debug_entry[16].uop.ctrl.imm_sel
invalidate debug_entry[16].uop.ctrl.op2_sel
invalidate debug_entry[16].uop.ctrl.op1_sel
invalidate debug_entry[16].uop.ctrl.br_type
invalidate debug_entry[16].uop.fu_code
invalidate debug_entry[16].uop.iq_type
invalidate debug_entry[16].uop.debug_pc
invalidate debug_entry[16].uop.is_rvc
invalidate debug_entry[16].uop.debug_inst
invalidate debug_entry[16].uop.inst
invalidate debug_entry[16].uop.uopc
invalidate debug_entry[16].unsafe
invalidate debug_entry[16].busy
invalidate debug_entry[16].valid
invalidate debug_entry[17].exception
invalidate debug_entry[17].uop.debug_tsrc
invalidate debug_entry[17].uop.debug_fsrc
invalidate debug_entry[17].uop.bp_xcpt_if
invalidate debug_entry[17].uop.bp_debug_if
invalidate debug_entry[17].uop.xcpt_ma_if
invalidate debug_entry[17].uop.xcpt_ae_if
invalidate debug_entry[17].uop.xcpt_pf_if
invalidate debug_entry[17].uop.fp_single
invalidate debug_entry[17].uop.fp_val
invalidate debug_entry[17].uop.frs3_en
invalidate debug_entry[17].uop.lrs2_rtype
invalidate debug_entry[17].uop.lrs1_rtype
invalidate debug_entry[17].uop.dst_rtype
invalidate debug_entry[17].uop.ldst_val
invalidate debug_entry[17].uop.lrs3
invalidate debug_entry[17].uop.lrs2
invalidate debug_entry[17].uop.lrs1
invalidate debug_entry[17].uop.ldst
invalidate debug_entry[17].uop.ldst_is_rs1
invalidate debug_entry[17].uop.flush_on_commit
invalidate debug_entry[17].uop.is_unique
invalidate debug_entry[17].uop.is_sys_pc2epc
invalidate debug_entry[17].uop.uses_stq
invalidate debug_entry[17].uop.uses_ldq
invalidate debug_entry[17].uop.is_amo
invalidate debug_entry[17].uop.is_fencei
invalidate debug_entry[17].uop.is_fence
invalidate debug_entry[17].uop.mem_signed
invalidate debug_entry[17].uop.mem_size
invalidate debug_entry[17].uop.mem_cmd
invalidate debug_entry[17].uop.bypassable
invalidate debug_entry[17].uop.exc_cause
invalidate debug_entry[17].uop.exception
invalidate debug_entry[17].uop.stale_pdst
invalidate debug_entry[17].uop.ppred_busy
invalidate debug_entry[17].uop.prs3_busy
invalidate debug_entry[17].uop.prs2_busy
invalidate debug_entry[17].uop.prs1_busy
invalidate debug_entry[17].uop.ppred
invalidate debug_entry[17].uop.prs3
invalidate debug_entry[17].uop.prs2
invalidate debug_entry[17].uop.prs1
invalidate debug_entry[17].uop.pdst
invalidate debug_entry[17].uop.rxq_idx
invalidate debug_entry[17].uop.stq_idx
invalidate debug_entry[17].uop.ldq_idx
invalidate debug_entry[17].uop.rob_idx
invalidate debug_entry[17].uop.csr_addr
invalidate debug_entry[17].uop.imm_packed
invalidate debug_entry[17].uop.taken
invalidate debug_entry[17].uop.pc_lob
invalidate debug_entry[17].uop.edge_inst
invalidate debug_entry[17].uop.ftq_idx
invalidate debug_entry[17].uop.br_tag
invalidate debug_entry[17].uop.br_mask
invalidate debug_entry[17].uop.is_sfb
invalidate debug_entry[17].uop.is_jal
invalidate debug_entry[17].uop.is_jalr
invalidate debug_entry[17].uop.is_br
invalidate debug_entry[17].uop.iw_p2_poisoned
invalidate debug_entry[17].uop.iw_p1_poisoned
invalidate debug_entry[17].uop.iw_state
invalidate debug_entry[17].uop.ctrl.is_std
invalidate debug_entry[17].uop.ctrl.is_sta
invalidate debug_entry[17].uop.ctrl.is_load
invalidate debug_entry[17].uop.ctrl.csr_cmd
invalidate debug_entry[17].uop.ctrl.fcn_dw
invalidate debug_entry[17].uop.ctrl.op_fcn
invalidate debug_entry[17].uop.ctrl.imm_sel
invalidate debug_entry[17].uop.ctrl.op2_sel
invalidate debug_entry[17].uop.ctrl.op1_sel
invalidate debug_entry[17].uop.ctrl.br_type
invalidate debug_entry[17].uop.fu_code
invalidate debug_entry[17].uop.iq_type
invalidate debug_entry[17].uop.debug_pc
invalidate debug_entry[17].uop.is_rvc
invalidate debug_entry[17].uop.debug_inst
invalidate debug_entry[17].uop.inst
invalidate debug_entry[17].uop.uopc
invalidate debug_entry[17].unsafe
invalidate debug_entry[17].busy
invalidate debug_entry[17].valid
invalidate debug_entry[18].exception
invalidate debug_entry[18].uop.debug_tsrc
invalidate debug_entry[18].uop.debug_fsrc
invalidate debug_entry[18].uop.bp_xcpt_if
invalidate debug_entry[18].uop.bp_debug_if
invalidate debug_entry[18].uop.xcpt_ma_if
invalidate debug_entry[18].uop.xcpt_ae_if
invalidate debug_entry[18].uop.xcpt_pf_if
invalidate debug_entry[18].uop.fp_single
invalidate debug_entry[18].uop.fp_val
invalidate debug_entry[18].uop.frs3_en
invalidate debug_entry[18].uop.lrs2_rtype
invalidate debug_entry[18].uop.lrs1_rtype
invalidate debug_entry[18].uop.dst_rtype
invalidate debug_entry[18].uop.ldst_val
invalidate debug_entry[18].uop.lrs3
invalidate debug_entry[18].uop.lrs2
invalidate debug_entry[18].uop.lrs1
invalidate debug_entry[18].uop.ldst
invalidate debug_entry[18].uop.ldst_is_rs1
invalidate debug_entry[18].uop.flush_on_commit
invalidate debug_entry[18].uop.is_unique
invalidate debug_entry[18].uop.is_sys_pc2epc
invalidate debug_entry[18].uop.uses_stq
invalidate debug_entry[18].uop.uses_ldq
invalidate debug_entry[18].uop.is_amo
invalidate debug_entry[18].uop.is_fencei
invalidate debug_entry[18].uop.is_fence
invalidate debug_entry[18].uop.mem_signed
invalidate debug_entry[18].uop.mem_size
invalidate debug_entry[18].uop.mem_cmd
invalidate debug_entry[18].uop.bypassable
invalidate debug_entry[18].uop.exc_cause
invalidate debug_entry[18].uop.exception
invalidate debug_entry[18].uop.stale_pdst
invalidate debug_entry[18].uop.ppred_busy
invalidate debug_entry[18].uop.prs3_busy
invalidate debug_entry[18].uop.prs2_busy
invalidate debug_entry[18].uop.prs1_busy
invalidate debug_entry[18].uop.ppred
invalidate debug_entry[18].uop.prs3
invalidate debug_entry[18].uop.prs2
invalidate debug_entry[18].uop.prs1
invalidate debug_entry[18].uop.pdst
invalidate debug_entry[18].uop.rxq_idx
invalidate debug_entry[18].uop.stq_idx
invalidate debug_entry[18].uop.ldq_idx
invalidate debug_entry[18].uop.rob_idx
invalidate debug_entry[18].uop.csr_addr
invalidate debug_entry[18].uop.imm_packed
invalidate debug_entry[18].uop.taken
invalidate debug_entry[18].uop.pc_lob
invalidate debug_entry[18].uop.edge_inst
invalidate debug_entry[18].uop.ftq_idx
invalidate debug_entry[18].uop.br_tag
invalidate debug_entry[18].uop.br_mask
invalidate debug_entry[18].uop.is_sfb
invalidate debug_entry[18].uop.is_jal
invalidate debug_entry[18].uop.is_jalr
invalidate debug_entry[18].uop.is_br
invalidate debug_entry[18].uop.iw_p2_poisoned
invalidate debug_entry[18].uop.iw_p1_poisoned
invalidate debug_entry[18].uop.iw_state
invalidate debug_entry[18].uop.ctrl.is_std
invalidate debug_entry[18].uop.ctrl.is_sta
invalidate debug_entry[18].uop.ctrl.is_load
invalidate debug_entry[18].uop.ctrl.csr_cmd
invalidate debug_entry[18].uop.ctrl.fcn_dw
invalidate debug_entry[18].uop.ctrl.op_fcn
invalidate debug_entry[18].uop.ctrl.imm_sel
invalidate debug_entry[18].uop.ctrl.op2_sel
invalidate debug_entry[18].uop.ctrl.op1_sel
invalidate debug_entry[18].uop.ctrl.br_type
invalidate debug_entry[18].uop.fu_code
invalidate debug_entry[18].uop.iq_type
invalidate debug_entry[18].uop.debug_pc
invalidate debug_entry[18].uop.is_rvc
invalidate debug_entry[18].uop.debug_inst
invalidate debug_entry[18].uop.inst
invalidate debug_entry[18].uop.uopc
invalidate debug_entry[18].unsafe
invalidate debug_entry[18].busy
invalidate debug_entry[18].valid
invalidate debug_entry[19].exception
invalidate debug_entry[19].uop.debug_tsrc
invalidate debug_entry[19].uop.debug_fsrc
invalidate debug_entry[19].uop.bp_xcpt_if
invalidate debug_entry[19].uop.bp_debug_if
invalidate debug_entry[19].uop.xcpt_ma_if
invalidate debug_entry[19].uop.xcpt_ae_if
invalidate debug_entry[19].uop.xcpt_pf_if
invalidate debug_entry[19].uop.fp_single
invalidate debug_entry[19].uop.fp_val
invalidate debug_entry[19].uop.frs3_en
invalidate debug_entry[19].uop.lrs2_rtype
invalidate debug_entry[19].uop.lrs1_rtype
invalidate debug_entry[19].uop.dst_rtype
invalidate debug_entry[19].uop.ldst_val
invalidate debug_entry[19].uop.lrs3
invalidate debug_entry[19].uop.lrs2
invalidate debug_entry[19].uop.lrs1
invalidate debug_entry[19].uop.ldst
invalidate debug_entry[19].uop.ldst_is_rs1
invalidate debug_entry[19].uop.flush_on_commit
invalidate debug_entry[19].uop.is_unique
invalidate debug_entry[19].uop.is_sys_pc2epc
invalidate debug_entry[19].uop.uses_stq
invalidate debug_entry[19].uop.uses_ldq
invalidate debug_entry[19].uop.is_amo
invalidate debug_entry[19].uop.is_fencei
invalidate debug_entry[19].uop.is_fence
invalidate debug_entry[19].uop.mem_signed
invalidate debug_entry[19].uop.mem_size
invalidate debug_entry[19].uop.mem_cmd
invalidate debug_entry[19].uop.bypassable
invalidate debug_entry[19].uop.exc_cause
invalidate debug_entry[19].uop.exception
invalidate debug_entry[19].uop.stale_pdst
invalidate debug_entry[19].uop.ppred_busy
invalidate debug_entry[19].uop.prs3_busy
invalidate debug_entry[19].uop.prs2_busy
invalidate debug_entry[19].uop.prs1_busy
invalidate debug_entry[19].uop.ppred
invalidate debug_entry[19].uop.prs3
invalidate debug_entry[19].uop.prs2
invalidate debug_entry[19].uop.prs1
invalidate debug_entry[19].uop.pdst
invalidate debug_entry[19].uop.rxq_idx
invalidate debug_entry[19].uop.stq_idx
invalidate debug_entry[19].uop.ldq_idx
invalidate debug_entry[19].uop.rob_idx
invalidate debug_entry[19].uop.csr_addr
invalidate debug_entry[19].uop.imm_packed
invalidate debug_entry[19].uop.taken
invalidate debug_entry[19].uop.pc_lob
invalidate debug_entry[19].uop.edge_inst
invalidate debug_entry[19].uop.ftq_idx
invalidate debug_entry[19].uop.br_tag
invalidate debug_entry[19].uop.br_mask
invalidate debug_entry[19].uop.is_sfb
invalidate debug_entry[19].uop.is_jal
invalidate debug_entry[19].uop.is_jalr
invalidate debug_entry[19].uop.is_br
invalidate debug_entry[19].uop.iw_p2_poisoned
invalidate debug_entry[19].uop.iw_p1_poisoned
invalidate debug_entry[19].uop.iw_state
invalidate debug_entry[19].uop.ctrl.is_std
invalidate debug_entry[19].uop.ctrl.is_sta
invalidate debug_entry[19].uop.ctrl.is_load
invalidate debug_entry[19].uop.ctrl.csr_cmd
invalidate debug_entry[19].uop.ctrl.fcn_dw
invalidate debug_entry[19].uop.ctrl.op_fcn
invalidate debug_entry[19].uop.ctrl.imm_sel
invalidate debug_entry[19].uop.ctrl.op2_sel
invalidate debug_entry[19].uop.ctrl.op1_sel
invalidate debug_entry[19].uop.ctrl.br_type
invalidate debug_entry[19].uop.fu_code
invalidate debug_entry[19].uop.iq_type
invalidate debug_entry[19].uop.debug_pc
invalidate debug_entry[19].uop.is_rvc
invalidate debug_entry[19].uop.debug_inst
invalidate debug_entry[19].uop.inst
invalidate debug_entry[19].uop.uopc
invalidate debug_entry[19].unsafe
invalidate debug_entry[19].busy
invalidate debug_entry[19].valid
invalidate debug_entry[20].exception
invalidate debug_entry[20].uop.debug_tsrc
invalidate debug_entry[20].uop.debug_fsrc
invalidate debug_entry[20].uop.bp_xcpt_if
invalidate debug_entry[20].uop.bp_debug_if
invalidate debug_entry[20].uop.xcpt_ma_if
invalidate debug_entry[20].uop.xcpt_ae_if
invalidate debug_entry[20].uop.xcpt_pf_if
invalidate debug_entry[20].uop.fp_single
invalidate debug_entry[20].uop.fp_val
invalidate debug_entry[20].uop.frs3_en
invalidate debug_entry[20].uop.lrs2_rtype
invalidate debug_entry[20].uop.lrs1_rtype
invalidate debug_entry[20].uop.dst_rtype
invalidate debug_entry[20].uop.ldst_val
invalidate debug_entry[20].uop.lrs3
invalidate debug_entry[20].uop.lrs2
invalidate debug_entry[20].uop.lrs1
invalidate debug_entry[20].uop.ldst
invalidate debug_entry[20].uop.ldst_is_rs1
invalidate debug_entry[20].uop.flush_on_commit
invalidate debug_entry[20].uop.is_unique
invalidate debug_entry[20].uop.is_sys_pc2epc
invalidate debug_entry[20].uop.uses_stq
invalidate debug_entry[20].uop.uses_ldq
invalidate debug_entry[20].uop.is_amo
invalidate debug_entry[20].uop.is_fencei
invalidate debug_entry[20].uop.is_fence
invalidate debug_entry[20].uop.mem_signed
invalidate debug_entry[20].uop.mem_size
invalidate debug_entry[20].uop.mem_cmd
invalidate debug_entry[20].uop.bypassable
invalidate debug_entry[20].uop.exc_cause
invalidate debug_entry[20].uop.exception
invalidate debug_entry[20].uop.stale_pdst
invalidate debug_entry[20].uop.ppred_busy
invalidate debug_entry[20].uop.prs3_busy
invalidate debug_entry[20].uop.prs2_busy
invalidate debug_entry[20].uop.prs1_busy
invalidate debug_entry[20].uop.ppred
invalidate debug_entry[20].uop.prs3
invalidate debug_entry[20].uop.prs2
invalidate debug_entry[20].uop.prs1
invalidate debug_entry[20].uop.pdst
invalidate debug_entry[20].uop.rxq_idx
invalidate debug_entry[20].uop.stq_idx
invalidate debug_entry[20].uop.ldq_idx
invalidate debug_entry[20].uop.rob_idx
invalidate debug_entry[20].uop.csr_addr
invalidate debug_entry[20].uop.imm_packed
invalidate debug_entry[20].uop.taken
invalidate debug_entry[20].uop.pc_lob
invalidate debug_entry[20].uop.edge_inst
invalidate debug_entry[20].uop.ftq_idx
invalidate debug_entry[20].uop.br_tag
invalidate debug_entry[20].uop.br_mask
invalidate debug_entry[20].uop.is_sfb
invalidate debug_entry[20].uop.is_jal
invalidate debug_entry[20].uop.is_jalr
invalidate debug_entry[20].uop.is_br
invalidate debug_entry[20].uop.iw_p2_poisoned
invalidate debug_entry[20].uop.iw_p1_poisoned
invalidate debug_entry[20].uop.iw_state
invalidate debug_entry[20].uop.ctrl.is_std
invalidate debug_entry[20].uop.ctrl.is_sta
invalidate debug_entry[20].uop.ctrl.is_load
invalidate debug_entry[20].uop.ctrl.csr_cmd
invalidate debug_entry[20].uop.ctrl.fcn_dw
invalidate debug_entry[20].uop.ctrl.op_fcn
invalidate debug_entry[20].uop.ctrl.imm_sel
invalidate debug_entry[20].uop.ctrl.op2_sel
invalidate debug_entry[20].uop.ctrl.op1_sel
invalidate debug_entry[20].uop.ctrl.br_type
invalidate debug_entry[20].uop.fu_code
invalidate debug_entry[20].uop.iq_type
invalidate debug_entry[20].uop.debug_pc
invalidate debug_entry[20].uop.is_rvc
invalidate debug_entry[20].uop.debug_inst
invalidate debug_entry[20].uop.inst
invalidate debug_entry[20].uop.uopc
invalidate debug_entry[20].unsafe
invalidate debug_entry[20].busy
invalidate debug_entry[20].valid
invalidate debug_entry[21].exception
invalidate debug_entry[21].uop.debug_tsrc
invalidate debug_entry[21].uop.debug_fsrc
invalidate debug_entry[21].uop.bp_xcpt_if
invalidate debug_entry[21].uop.bp_debug_if
invalidate debug_entry[21].uop.xcpt_ma_if
invalidate debug_entry[21].uop.xcpt_ae_if
invalidate debug_entry[21].uop.xcpt_pf_if
invalidate debug_entry[21].uop.fp_single
invalidate debug_entry[21].uop.fp_val
invalidate debug_entry[21].uop.frs3_en
invalidate debug_entry[21].uop.lrs2_rtype
invalidate debug_entry[21].uop.lrs1_rtype
invalidate debug_entry[21].uop.dst_rtype
invalidate debug_entry[21].uop.ldst_val
invalidate debug_entry[21].uop.lrs3
invalidate debug_entry[21].uop.lrs2
invalidate debug_entry[21].uop.lrs1
invalidate debug_entry[21].uop.ldst
invalidate debug_entry[21].uop.ldst_is_rs1
invalidate debug_entry[21].uop.flush_on_commit
invalidate debug_entry[21].uop.is_unique
invalidate debug_entry[21].uop.is_sys_pc2epc
invalidate debug_entry[21].uop.uses_stq
invalidate debug_entry[21].uop.uses_ldq
invalidate debug_entry[21].uop.is_amo
invalidate debug_entry[21].uop.is_fencei
invalidate debug_entry[21].uop.is_fence
invalidate debug_entry[21].uop.mem_signed
invalidate debug_entry[21].uop.mem_size
invalidate debug_entry[21].uop.mem_cmd
invalidate debug_entry[21].uop.bypassable
invalidate debug_entry[21].uop.exc_cause
invalidate debug_entry[21].uop.exception
invalidate debug_entry[21].uop.stale_pdst
invalidate debug_entry[21].uop.ppred_busy
invalidate debug_entry[21].uop.prs3_busy
invalidate debug_entry[21].uop.prs2_busy
invalidate debug_entry[21].uop.prs1_busy
invalidate debug_entry[21].uop.ppred
invalidate debug_entry[21].uop.prs3
invalidate debug_entry[21].uop.prs2
invalidate debug_entry[21].uop.prs1
invalidate debug_entry[21].uop.pdst
invalidate debug_entry[21].uop.rxq_idx
invalidate debug_entry[21].uop.stq_idx
invalidate debug_entry[21].uop.ldq_idx
invalidate debug_entry[21].uop.rob_idx
invalidate debug_entry[21].uop.csr_addr
invalidate debug_entry[21].uop.imm_packed
invalidate debug_entry[21].uop.taken
invalidate debug_entry[21].uop.pc_lob
invalidate debug_entry[21].uop.edge_inst
invalidate debug_entry[21].uop.ftq_idx
invalidate debug_entry[21].uop.br_tag
invalidate debug_entry[21].uop.br_mask
invalidate debug_entry[21].uop.is_sfb
invalidate debug_entry[21].uop.is_jal
invalidate debug_entry[21].uop.is_jalr
invalidate debug_entry[21].uop.is_br
invalidate debug_entry[21].uop.iw_p2_poisoned
invalidate debug_entry[21].uop.iw_p1_poisoned
invalidate debug_entry[21].uop.iw_state
invalidate debug_entry[21].uop.ctrl.is_std
invalidate debug_entry[21].uop.ctrl.is_sta
invalidate debug_entry[21].uop.ctrl.is_load
invalidate debug_entry[21].uop.ctrl.csr_cmd
invalidate debug_entry[21].uop.ctrl.fcn_dw
invalidate debug_entry[21].uop.ctrl.op_fcn
invalidate debug_entry[21].uop.ctrl.imm_sel
invalidate debug_entry[21].uop.ctrl.op2_sel
invalidate debug_entry[21].uop.ctrl.op1_sel
invalidate debug_entry[21].uop.ctrl.br_type
invalidate debug_entry[21].uop.fu_code
invalidate debug_entry[21].uop.iq_type
invalidate debug_entry[21].uop.debug_pc
invalidate debug_entry[21].uop.is_rvc
invalidate debug_entry[21].uop.debug_inst
invalidate debug_entry[21].uop.inst
invalidate debug_entry[21].uop.uopc
invalidate debug_entry[21].unsafe
invalidate debug_entry[21].busy
invalidate debug_entry[21].valid
invalidate debug_entry[22].exception
invalidate debug_entry[22].uop.debug_tsrc
invalidate debug_entry[22].uop.debug_fsrc
invalidate debug_entry[22].uop.bp_xcpt_if
invalidate debug_entry[22].uop.bp_debug_if
invalidate debug_entry[22].uop.xcpt_ma_if
invalidate debug_entry[22].uop.xcpt_ae_if
invalidate debug_entry[22].uop.xcpt_pf_if
invalidate debug_entry[22].uop.fp_single
invalidate debug_entry[22].uop.fp_val
invalidate debug_entry[22].uop.frs3_en
invalidate debug_entry[22].uop.lrs2_rtype
invalidate debug_entry[22].uop.lrs1_rtype
invalidate debug_entry[22].uop.dst_rtype
invalidate debug_entry[22].uop.ldst_val
invalidate debug_entry[22].uop.lrs3
invalidate debug_entry[22].uop.lrs2
invalidate debug_entry[22].uop.lrs1
invalidate debug_entry[22].uop.ldst
invalidate debug_entry[22].uop.ldst_is_rs1
invalidate debug_entry[22].uop.flush_on_commit
invalidate debug_entry[22].uop.is_unique
invalidate debug_entry[22].uop.is_sys_pc2epc
invalidate debug_entry[22].uop.uses_stq
invalidate debug_entry[22].uop.uses_ldq
invalidate debug_entry[22].uop.is_amo
invalidate debug_entry[22].uop.is_fencei
invalidate debug_entry[22].uop.is_fence
invalidate debug_entry[22].uop.mem_signed
invalidate debug_entry[22].uop.mem_size
invalidate debug_entry[22].uop.mem_cmd
invalidate debug_entry[22].uop.bypassable
invalidate debug_entry[22].uop.exc_cause
invalidate debug_entry[22].uop.exception
invalidate debug_entry[22].uop.stale_pdst
invalidate debug_entry[22].uop.ppred_busy
invalidate debug_entry[22].uop.prs3_busy
invalidate debug_entry[22].uop.prs2_busy
invalidate debug_entry[22].uop.prs1_busy
invalidate debug_entry[22].uop.ppred
invalidate debug_entry[22].uop.prs3
invalidate debug_entry[22].uop.prs2
invalidate debug_entry[22].uop.prs1
invalidate debug_entry[22].uop.pdst
invalidate debug_entry[22].uop.rxq_idx
invalidate debug_entry[22].uop.stq_idx
invalidate debug_entry[22].uop.ldq_idx
invalidate debug_entry[22].uop.rob_idx
invalidate debug_entry[22].uop.csr_addr
invalidate debug_entry[22].uop.imm_packed
invalidate debug_entry[22].uop.taken
invalidate debug_entry[22].uop.pc_lob
invalidate debug_entry[22].uop.edge_inst
invalidate debug_entry[22].uop.ftq_idx
invalidate debug_entry[22].uop.br_tag
invalidate debug_entry[22].uop.br_mask
invalidate debug_entry[22].uop.is_sfb
invalidate debug_entry[22].uop.is_jal
invalidate debug_entry[22].uop.is_jalr
invalidate debug_entry[22].uop.is_br
invalidate debug_entry[22].uop.iw_p2_poisoned
invalidate debug_entry[22].uop.iw_p1_poisoned
invalidate debug_entry[22].uop.iw_state
invalidate debug_entry[22].uop.ctrl.is_std
invalidate debug_entry[22].uop.ctrl.is_sta
invalidate debug_entry[22].uop.ctrl.is_load
invalidate debug_entry[22].uop.ctrl.csr_cmd
invalidate debug_entry[22].uop.ctrl.fcn_dw
invalidate debug_entry[22].uop.ctrl.op_fcn
invalidate debug_entry[22].uop.ctrl.imm_sel
invalidate debug_entry[22].uop.ctrl.op2_sel
invalidate debug_entry[22].uop.ctrl.op1_sel
invalidate debug_entry[22].uop.ctrl.br_type
invalidate debug_entry[22].uop.fu_code
invalidate debug_entry[22].uop.iq_type
invalidate debug_entry[22].uop.debug_pc
invalidate debug_entry[22].uop.is_rvc
invalidate debug_entry[22].uop.debug_inst
invalidate debug_entry[22].uop.inst
invalidate debug_entry[22].uop.uopc
invalidate debug_entry[22].unsafe
invalidate debug_entry[22].busy
invalidate debug_entry[22].valid
invalidate debug_entry[23].exception
invalidate debug_entry[23].uop.debug_tsrc
invalidate debug_entry[23].uop.debug_fsrc
invalidate debug_entry[23].uop.bp_xcpt_if
invalidate debug_entry[23].uop.bp_debug_if
invalidate debug_entry[23].uop.xcpt_ma_if
invalidate debug_entry[23].uop.xcpt_ae_if
invalidate debug_entry[23].uop.xcpt_pf_if
invalidate debug_entry[23].uop.fp_single
invalidate debug_entry[23].uop.fp_val
invalidate debug_entry[23].uop.frs3_en
invalidate debug_entry[23].uop.lrs2_rtype
invalidate debug_entry[23].uop.lrs1_rtype
invalidate debug_entry[23].uop.dst_rtype
invalidate debug_entry[23].uop.ldst_val
invalidate debug_entry[23].uop.lrs3
invalidate debug_entry[23].uop.lrs2
invalidate debug_entry[23].uop.lrs1
invalidate debug_entry[23].uop.ldst
invalidate debug_entry[23].uop.ldst_is_rs1
invalidate debug_entry[23].uop.flush_on_commit
invalidate debug_entry[23].uop.is_unique
invalidate debug_entry[23].uop.is_sys_pc2epc
invalidate debug_entry[23].uop.uses_stq
invalidate debug_entry[23].uop.uses_ldq
invalidate debug_entry[23].uop.is_amo
invalidate debug_entry[23].uop.is_fencei
invalidate debug_entry[23].uop.is_fence
invalidate debug_entry[23].uop.mem_signed
invalidate debug_entry[23].uop.mem_size
invalidate debug_entry[23].uop.mem_cmd
invalidate debug_entry[23].uop.bypassable
invalidate debug_entry[23].uop.exc_cause
invalidate debug_entry[23].uop.exception
invalidate debug_entry[23].uop.stale_pdst
invalidate debug_entry[23].uop.ppred_busy
invalidate debug_entry[23].uop.prs3_busy
invalidate debug_entry[23].uop.prs2_busy
invalidate debug_entry[23].uop.prs1_busy
invalidate debug_entry[23].uop.ppred
invalidate debug_entry[23].uop.prs3
invalidate debug_entry[23].uop.prs2
invalidate debug_entry[23].uop.prs1
invalidate debug_entry[23].uop.pdst
invalidate debug_entry[23].uop.rxq_idx
invalidate debug_entry[23].uop.stq_idx
invalidate debug_entry[23].uop.ldq_idx
invalidate debug_entry[23].uop.rob_idx
invalidate debug_entry[23].uop.csr_addr
invalidate debug_entry[23].uop.imm_packed
invalidate debug_entry[23].uop.taken
invalidate debug_entry[23].uop.pc_lob
invalidate debug_entry[23].uop.edge_inst
invalidate debug_entry[23].uop.ftq_idx
invalidate debug_entry[23].uop.br_tag
invalidate debug_entry[23].uop.br_mask
invalidate debug_entry[23].uop.is_sfb
invalidate debug_entry[23].uop.is_jal
invalidate debug_entry[23].uop.is_jalr
invalidate debug_entry[23].uop.is_br
invalidate debug_entry[23].uop.iw_p2_poisoned
invalidate debug_entry[23].uop.iw_p1_poisoned
invalidate debug_entry[23].uop.iw_state
invalidate debug_entry[23].uop.ctrl.is_std
invalidate debug_entry[23].uop.ctrl.is_sta
invalidate debug_entry[23].uop.ctrl.is_load
invalidate debug_entry[23].uop.ctrl.csr_cmd
invalidate debug_entry[23].uop.ctrl.fcn_dw
invalidate debug_entry[23].uop.ctrl.op_fcn
invalidate debug_entry[23].uop.ctrl.imm_sel
invalidate debug_entry[23].uop.ctrl.op2_sel
invalidate debug_entry[23].uop.ctrl.op1_sel
invalidate debug_entry[23].uop.ctrl.br_type
invalidate debug_entry[23].uop.fu_code
invalidate debug_entry[23].uop.iq_type
invalidate debug_entry[23].uop.debug_pc
invalidate debug_entry[23].uop.is_rvc
invalidate debug_entry[23].uop.debug_inst
invalidate debug_entry[23].uop.inst
invalidate debug_entry[23].uop.uopc
invalidate debug_entry[23].unsafe
invalidate debug_entry[23].busy
invalidate debug_entry[23].valid
invalidate debug_entry[24].exception
invalidate debug_entry[24].uop.debug_tsrc
invalidate debug_entry[24].uop.debug_fsrc
invalidate debug_entry[24].uop.bp_xcpt_if
invalidate debug_entry[24].uop.bp_debug_if
invalidate debug_entry[24].uop.xcpt_ma_if
invalidate debug_entry[24].uop.xcpt_ae_if
invalidate debug_entry[24].uop.xcpt_pf_if
invalidate debug_entry[24].uop.fp_single
invalidate debug_entry[24].uop.fp_val
invalidate debug_entry[24].uop.frs3_en
invalidate debug_entry[24].uop.lrs2_rtype
invalidate debug_entry[24].uop.lrs1_rtype
invalidate debug_entry[24].uop.dst_rtype
invalidate debug_entry[24].uop.ldst_val
invalidate debug_entry[24].uop.lrs3
invalidate debug_entry[24].uop.lrs2
invalidate debug_entry[24].uop.lrs1
invalidate debug_entry[24].uop.ldst
invalidate debug_entry[24].uop.ldst_is_rs1
invalidate debug_entry[24].uop.flush_on_commit
invalidate debug_entry[24].uop.is_unique
invalidate debug_entry[24].uop.is_sys_pc2epc
invalidate debug_entry[24].uop.uses_stq
invalidate debug_entry[24].uop.uses_ldq
invalidate debug_entry[24].uop.is_amo
invalidate debug_entry[24].uop.is_fencei
invalidate debug_entry[24].uop.is_fence
invalidate debug_entry[24].uop.mem_signed
invalidate debug_entry[24].uop.mem_size
invalidate debug_entry[24].uop.mem_cmd
invalidate debug_entry[24].uop.bypassable
invalidate debug_entry[24].uop.exc_cause
invalidate debug_entry[24].uop.exception
invalidate debug_entry[24].uop.stale_pdst
invalidate debug_entry[24].uop.ppred_busy
invalidate debug_entry[24].uop.prs3_busy
invalidate debug_entry[24].uop.prs2_busy
invalidate debug_entry[24].uop.prs1_busy
invalidate debug_entry[24].uop.ppred
invalidate debug_entry[24].uop.prs3
invalidate debug_entry[24].uop.prs2
invalidate debug_entry[24].uop.prs1
invalidate debug_entry[24].uop.pdst
invalidate debug_entry[24].uop.rxq_idx
invalidate debug_entry[24].uop.stq_idx
invalidate debug_entry[24].uop.ldq_idx
invalidate debug_entry[24].uop.rob_idx
invalidate debug_entry[24].uop.csr_addr
invalidate debug_entry[24].uop.imm_packed
invalidate debug_entry[24].uop.taken
invalidate debug_entry[24].uop.pc_lob
invalidate debug_entry[24].uop.edge_inst
invalidate debug_entry[24].uop.ftq_idx
invalidate debug_entry[24].uop.br_tag
invalidate debug_entry[24].uop.br_mask
invalidate debug_entry[24].uop.is_sfb
invalidate debug_entry[24].uop.is_jal
invalidate debug_entry[24].uop.is_jalr
invalidate debug_entry[24].uop.is_br
invalidate debug_entry[24].uop.iw_p2_poisoned
invalidate debug_entry[24].uop.iw_p1_poisoned
invalidate debug_entry[24].uop.iw_state
invalidate debug_entry[24].uop.ctrl.is_std
invalidate debug_entry[24].uop.ctrl.is_sta
invalidate debug_entry[24].uop.ctrl.is_load
invalidate debug_entry[24].uop.ctrl.csr_cmd
invalidate debug_entry[24].uop.ctrl.fcn_dw
invalidate debug_entry[24].uop.ctrl.op_fcn
invalidate debug_entry[24].uop.ctrl.imm_sel
invalidate debug_entry[24].uop.ctrl.op2_sel
invalidate debug_entry[24].uop.ctrl.op1_sel
invalidate debug_entry[24].uop.ctrl.br_type
invalidate debug_entry[24].uop.fu_code
invalidate debug_entry[24].uop.iq_type
invalidate debug_entry[24].uop.debug_pc
invalidate debug_entry[24].uop.is_rvc
invalidate debug_entry[24].uop.debug_inst
invalidate debug_entry[24].uop.inst
invalidate debug_entry[24].uop.uopc
invalidate debug_entry[24].unsafe
invalidate debug_entry[24].busy
invalidate debug_entry[24].valid
invalidate debug_entry[25].exception
invalidate debug_entry[25].uop.debug_tsrc
invalidate debug_entry[25].uop.debug_fsrc
invalidate debug_entry[25].uop.bp_xcpt_if
invalidate debug_entry[25].uop.bp_debug_if
invalidate debug_entry[25].uop.xcpt_ma_if
invalidate debug_entry[25].uop.xcpt_ae_if
invalidate debug_entry[25].uop.xcpt_pf_if
invalidate debug_entry[25].uop.fp_single
invalidate debug_entry[25].uop.fp_val
invalidate debug_entry[25].uop.frs3_en
invalidate debug_entry[25].uop.lrs2_rtype
invalidate debug_entry[25].uop.lrs1_rtype
invalidate debug_entry[25].uop.dst_rtype
invalidate debug_entry[25].uop.ldst_val
invalidate debug_entry[25].uop.lrs3
invalidate debug_entry[25].uop.lrs2
invalidate debug_entry[25].uop.lrs1
invalidate debug_entry[25].uop.ldst
invalidate debug_entry[25].uop.ldst_is_rs1
invalidate debug_entry[25].uop.flush_on_commit
invalidate debug_entry[25].uop.is_unique
invalidate debug_entry[25].uop.is_sys_pc2epc
invalidate debug_entry[25].uop.uses_stq
invalidate debug_entry[25].uop.uses_ldq
invalidate debug_entry[25].uop.is_amo
invalidate debug_entry[25].uop.is_fencei
invalidate debug_entry[25].uop.is_fence
invalidate debug_entry[25].uop.mem_signed
invalidate debug_entry[25].uop.mem_size
invalidate debug_entry[25].uop.mem_cmd
invalidate debug_entry[25].uop.bypassable
invalidate debug_entry[25].uop.exc_cause
invalidate debug_entry[25].uop.exception
invalidate debug_entry[25].uop.stale_pdst
invalidate debug_entry[25].uop.ppred_busy
invalidate debug_entry[25].uop.prs3_busy
invalidate debug_entry[25].uop.prs2_busy
invalidate debug_entry[25].uop.prs1_busy
invalidate debug_entry[25].uop.ppred
invalidate debug_entry[25].uop.prs3
invalidate debug_entry[25].uop.prs2
invalidate debug_entry[25].uop.prs1
invalidate debug_entry[25].uop.pdst
invalidate debug_entry[25].uop.rxq_idx
invalidate debug_entry[25].uop.stq_idx
invalidate debug_entry[25].uop.ldq_idx
invalidate debug_entry[25].uop.rob_idx
invalidate debug_entry[25].uop.csr_addr
invalidate debug_entry[25].uop.imm_packed
invalidate debug_entry[25].uop.taken
invalidate debug_entry[25].uop.pc_lob
invalidate debug_entry[25].uop.edge_inst
invalidate debug_entry[25].uop.ftq_idx
invalidate debug_entry[25].uop.br_tag
invalidate debug_entry[25].uop.br_mask
invalidate debug_entry[25].uop.is_sfb
invalidate debug_entry[25].uop.is_jal
invalidate debug_entry[25].uop.is_jalr
invalidate debug_entry[25].uop.is_br
invalidate debug_entry[25].uop.iw_p2_poisoned
invalidate debug_entry[25].uop.iw_p1_poisoned
invalidate debug_entry[25].uop.iw_state
invalidate debug_entry[25].uop.ctrl.is_std
invalidate debug_entry[25].uop.ctrl.is_sta
invalidate debug_entry[25].uop.ctrl.is_load
invalidate debug_entry[25].uop.ctrl.csr_cmd
invalidate debug_entry[25].uop.ctrl.fcn_dw
invalidate debug_entry[25].uop.ctrl.op_fcn
invalidate debug_entry[25].uop.ctrl.imm_sel
invalidate debug_entry[25].uop.ctrl.op2_sel
invalidate debug_entry[25].uop.ctrl.op1_sel
invalidate debug_entry[25].uop.ctrl.br_type
invalidate debug_entry[25].uop.fu_code
invalidate debug_entry[25].uop.iq_type
invalidate debug_entry[25].uop.debug_pc
invalidate debug_entry[25].uop.is_rvc
invalidate debug_entry[25].uop.debug_inst
invalidate debug_entry[25].uop.inst
invalidate debug_entry[25].uop.uopc
invalidate debug_entry[25].unsafe
invalidate debug_entry[25].busy
invalidate debug_entry[25].valid
invalidate debug_entry[26].exception
invalidate debug_entry[26].uop.debug_tsrc
invalidate debug_entry[26].uop.debug_fsrc
invalidate debug_entry[26].uop.bp_xcpt_if
invalidate debug_entry[26].uop.bp_debug_if
invalidate debug_entry[26].uop.xcpt_ma_if
invalidate debug_entry[26].uop.xcpt_ae_if
invalidate debug_entry[26].uop.xcpt_pf_if
invalidate debug_entry[26].uop.fp_single
invalidate debug_entry[26].uop.fp_val
invalidate debug_entry[26].uop.frs3_en
invalidate debug_entry[26].uop.lrs2_rtype
invalidate debug_entry[26].uop.lrs1_rtype
invalidate debug_entry[26].uop.dst_rtype
invalidate debug_entry[26].uop.ldst_val
invalidate debug_entry[26].uop.lrs3
invalidate debug_entry[26].uop.lrs2
invalidate debug_entry[26].uop.lrs1
invalidate debug_entry[26].uop.ldst
invalidate debug_entry[26].uop.ldst_is_rs1
invalidate debug_entry[26].uop.flush_on_commit
invalidate debug_entry[26].uop.is_unique
invalidate debug_entry[26].uop.is_sys_pc2epc
invalidate debug_entry[26].uop.uses_stq
invalidate debug_entry[26].uop.uses_ldq
invalidate debug_entry[26].uop.is_amo
invalidate debug_entry[26].uop.is_fencei
invalidate debug_entry[26].uop.is_fence
invalidate debug_entry[26].uop.mem_signed
invalidate debug_entry[26].uop.mem_size
invalidate debug_entry[26].uop.mem_cmd
invalidate debug_entry[26].uop.bypassable
invalidate debug_entry[26].uop.exc_cause
invalidate debug_entry[26].uop.exception
invalidate debug_entry[26].uop.stale_pdst
invalidate debug_entry[26].uop.ppred_busy
invalidate debug_entry[26].uop.prs3_busy
invalidate debug_entry[26].uop.prs2_busy
invalidate debug_entry[26].uop.prs1_busy
invalidate debug_entry[26].uop.ppred
invalidate debug_entry[26].uop.prs3
invalidate debug_entry[26].uop.prs2
invalidate debug_entry[26].uop.prs1
invalidate debug_entry[26].uop.pdst
invalidate debug_entry[26].uop.rxq_idx
invalidate debug_entry[26].uop.stq_idx
invalidate debug_entry[26].uop.ldq_idx
invalidate debug_entry[26].uop.rob_idx
invalidate debug_entry[26].uop.csr_addr
invalidate debug_entry[26].uop.imm_packed
invalidate debug_entry[26].uop.taken
invalidate debug_entry[26].uop.pc_lob
invalidate debug_entry[26].uop.edge_inst
invalidate debug_entry[26].uop.ftq_idx
invalidate debug_entry[26].uop.br_tag
invalidate debug_entry[26].uop.br_mask
invalidate debug_entry[26].uop.is_sfb
invalidate debug_entry[26].uop.is_jal
invalidate debug_entry[26].uop.is_jalr
invalidate debug_entry[26].uop.is_br
invalidate debug_entry[26].uop.iw_p2_poisoned
invalidate debug_entry[26].uop.iw_p1_poisoned
invalidate debug_entry[26].uop.iw_state
invalidate debug_entry[26].uop.ctrl.is_std
invalidate debug_entry[26].uop.ctrl.is_sta
invalidate debug_entry[26].uop.ctrl.is_load
invalidate debug_entry[26].uop.ctrl.csr_cmd
invalidate debug_entry[26].uop.ctrl.fcn_dw
invalidate debug_entry[26].uop.ctrl.op_fcn
invalidate debug_entry[26].uop.ctrl.imm_sel
invalidate debug_entry[26].uop.ctrl.op2_sel
invalidate debug_entry[26].uop.ctrl.op1_sel
invalidate debug_entry[26].uop.ctrl.br_type
invalidate debug_entry[26].uop.fu_code
invalidate debug_entry[26].uop.iq_type
invalidate debug_entry[26].uop.debug_pc
invalidate debug_entry[26].uop.is_rvc
invalidate debug_entry[26].uop.debug_inst
invalidate debug_entry[26].uop.inst
invalidate debug_entry[26].uop.uopc
invalidate debug_entry[26].unsafe
invalidate debug_entry[26].busy
invalidate debug_entry[26].valid
invalidate debug_entry[27].exception
invalidate debug_entry[27].uop.debug_tsrc
invalidate debug_entry[27].uop.debug_fsrc
invalidate debug_entry[27].uop.bp_xcpt_if
invalidate debug_entry[27].uop.bp_debug_if
invalidate debug_entry[27].uop.xcpt_ma_if
invalidate debug_entry[27].uop.xcpt_ae_if
invalidate debug_entry[27].uop.xcpt_pf_if
invalidate debug_entry[27].uop.fp_single
invalidate debug_entry[27].uop.fp_val
invalidate debug_entry[27].uop.frs3_en
invalidate debug_entry[27].uop.lrs2_rtype
invalidate debug_entry[27].uop.lrs1_rtype
invalidate debug_entry[27].uop.dst_rtype
invalidate debug_entry[27].uop.ldst_val
invalidate debug_entry[27].uop.lrs3
invalidate debug_entry[27].uop.lrs2
invalidate debug_entry[27].uop.lrs1
invalidate debug_entry[27].uop.ldst
invalidate debug_entry[27].uop.ldst_is_rs1
invalidate debug_entry[27].uop.flush_on_commit
invalidate debug_entry[27].uop.is_unique
invalidate debug_entry[27].uop.is_sys_pc2epc
invalidate debug_entry[27].uop.uses_stq
invalidate debug_entry[27].uop.uses_ldq
invalidate debug_entry[27].uop.is_amo
invalidate debug_entry[27].uop.is_fencei
invalidate debug_entry[27].uop.is_fence
invalidate debug_entry[27].uop.mem_signed
invalidate debug_entry[27].uop.mem_size
invalidate debug_entry[27].uop.mem_cmd
invalidate debug_entry[27].uop.bypassable
invalidate debug_entry[27].uop.exc_cause
invalidate debug_entry[27].uop.exception
invalidate debug_entry[27].uop.stale_pdst
invalidate debug_entry[27].uop.ppred_busy
invalidate debug_entry[27].uop.prs3_busy
invalidate debug_entry[27].uop.prs2_busy
invalidate debug_entry[27].uop.prs1_busy
invalidate debug_entry[27].uop.ppred
invalidate debug_entry[27].uop.prs3
invalidate debug_entry[27].uop.prs2
invalidate debug_entry[27].uop.prs1
invalidate debug_entry[27].uop.pdst
invalidate debug_entry[27].uop.rxq_idx
invalidate debug_entry[27].uop.stq_idx
invalidate debug_entry[27].uop.ldq_idx
invalidate debug_entry[27].uop.rob_idx
invalidate debug_entry[27].uop.csr_addr
invalidate debug_entry[27].uop.imm_packed
invalidate debug_entry[27].uop.taken
invalidate debug_entry[27].uop.pc_lob
invalidate debug_entry[27].uop.edge_inst
invalidate debug_entry[27].uop.ftq_idx
invalidate debug_entry[27].uop.br_tag
invalidate debug_entry[27].uop.br_mask
invalidate debug_entry[27].uop.is_sfb
invalidate debug_entry[27].uop.is_jal
invalidate debug_entry[27].uop.is_jalr
invalidate debug_entry[27].uop.is_br
invalidate debug_entry[27].uop.iw_p2_poisoned
invalidate debug_entry[27].uop.iw_p1_poisoned
invalidate debug_entry[27].uop.iw_state
invalidate debug_entry[27].uop.ctrl.is_std
invalidate debug_entry[27].uop.ctrl.is_sta
invalidate debug_entry[27].uop.ctrl.is_load
invalidate debug_entry[27].uop.ctrl.csr_cmd
invalidate debug_entry[27].uop.ctrl.fcn_dw
invalidate debug_entry[27].uop.ctrl.op_fcn
invalidate debug_entry[27].uop.ctrl.imm_sel
invalidate debug_entry[27].uop.ctrl.op2_sel
invalidate debug_entry[27].uop.ctrl.op1_sel
invalidate debug_entry[27].uop.ctrl.br_type
invalidate debug_entry[27].uop.fu_code
invalidate debug_entry[27].uop.iq_type
invalidate debug_entry[27].uop.debug_pc
invalidate debug_entry[27].uop.is_rvc
invalidate debug_entry[27].uop.debug_inst
invalidate debug_entry[27].uop.inst
invalidate debug_entry[27].uop.uopc
invalidate debug_entry[27].unsafe
invalidate debug_entry[27].busy
invalidate debug_entry[27].valid
invalidate debug_entry[28].exception
invalidate debug_entry[28].uop.debug_tsrc
invalidate debug_entry[28].uop.debug_fsrc
invalidate debug_entry[28].uop.bp_xcpt_if
invalidate debug_entry[28].uop.bp_debug_if
invalidate debug_entry[28].uop.xcpt_ma_if
invalidate debug_entry[28].uop.xcpt_ae_if
invalidate debug_entry[28].uop.xcpt_pf_if
invalidate debug_entry[28].uop.fp_single
invalidate debug_entry[28].uop.fp_val
invalidate debug_entry[28].uop.frs3_en
invalidate debug_entry[28].uop.lrs2_rtype
invalidate debug_entry[28].uop.lrs1_rtype
invalidate debug_entry[28].uop.dst_rtype
invalidate debug_entry[28].uop.ldst_val
invalidate debug_entry[28].uop.lrs3
invalidate debug_entry[28].uop.lrs2
invalidate debug_entry[28].uop.lrs1
invalidate debug_entry[28].uop.ldst
invalidate debug_entry[28].uop.ldst_is_rs1
invalidate debug_entry[28].uop.flush_on_commit
invalidate debug_entry[28].uop.is_unique
invalidate debug_entry[28].uop.is_sys_pc2epc
invalidate debug_entry[28].uop.uses_stq
invalidate debug_entry[28].uop.uses_ldq
invalidate debug_entry[28].uop.is_amo
invalidate debug_entry[28].uop.is_fencei
invalidate debug_entry[28].uop.is_fence
invalidate debug_entry[28].uop.mem_signed
invalidate debug_entry[28].uop.mem_size
invalidate debug_entry[28].uop.mem_cmd
invalidate debug_entry[28].uop.bypassable
invalidate debug_entry[28].uop.exc_cause
invalidate debug_entry[28].uop.exception
invalidate debug_entry[28].uop.stale_pdst
invalidate debug_entry[28].uop.ppred_busy
invalidate debug_entry[28].uop.prs3_busy
invalidate debug_entry[28].uop.prs2_busy
invalidate debug_entry[28].uop.prs1_busy
invalidate debug_entry[28].uop.ppred
invalidate debug_entry[28].uop.prs3
invalidate debug_entry[28].uop.prs2
invalidate debug_entry[28].uop.prs1
invalidate debug_entry[28].uop.pdst
invalidate debug_entry[28].uop.rxq_idx
invalidate debug_entry[28].uop.stq_idx
invalidate debug_entry[28].uop.ldq_idx
invalidate debug_entry[28].uop.rob_idx
invalidate debug_entry[28].uop.csr_addr
invalidate debug_entry[28].uop.imm_packed
invalidate debug_entry[28].uop.taken
invalidate debug_entry[28].uop.pc_lob
invalidate debug_entry[28].uop.edge_inst
invalidate debug_entry[28].uop.ftq_idx
invalidate debug_entry[28].uop.br_tag
invalidate debug_entry[28].uop.br_mask
invalidate debug_entry[28].uop.is_sfb
invalidate debug_entry[28].uop.is_jal
invalidate debug_entry[28].uop.is_jalr
invalidate debug_entry[28].uop.is_br
invalidate debug_entry[28].uop.iw_p2_poisoned
invalidate debug_entry[28].uop.iw_p1_poisoned
invalidate debug_entry[28].uop.iw_state
invalidate debug_entry[28].uop.ctrl.is_std
invalidate debug_entry[28].uop.ctrl.is_sta
invalidate debug_entry[28].uop.ctrl.is_load
invalidate debug_entry[28].uop.ctrl.csr_cmd
invalidate debug_entry[28].uop.ctrl.fcn_dw
invalidate debug_entry[28].uop.ctrl.op_fcn
invalidate debug_entry[28].uop.ctrl.imm_sel
invalidate debug_entry[28].uop.ctrl.op2_sel
invalidate debug_entry[28].uop.ctrl.op1_sel
invalidate debug_entry[28].uop.ctrl.br_type
invalidate debug_entry[28].uop.fu_code
invalidate debug_entry[28].uop.iq_type
invalidate debug_entry[28].uop.debug_pc
invalidate debug_entry[28].uop.is_rvc
invalidate debug_entry[28].uop.debug_inst
invalidate debug_entry[28].uop.inst
invalidate debug_entry[28].uop.uopc
invalidate debug_entry[28].unsafe
invalidate debug_entry[28].busy
invalidate debug_entry[28].valid
invalidate debug_entry[29].exception
invalidate debug_entry[29].uop.debug_tsrc
invalidate debug_entry[29].uop.debug_fsrc
invalidate debug_entry[29].uop.bp_xcpt_if
invalidate debug_entry[29].uop.bp_debug_if
invalidate debug_entry[29].uop.xcpt_ma_if
invalidate debug_entry[29].uop.xcpt_ae_if
invalidate debug_entry[29].uop.xcpt_pf_if
invalidate debug_entry[29].uop.fp_single
invalidate debug_entry[29].uop.fp_val
invalidate debug_entry[29].uop.frs3_en
invalidate debug_entry[29].uop.lrs2_rtype
invalidate debug_entry[29].uop.lrs1_rtype
invalidate debug_entry[29].uop.dst_rtype
invalidate debug_entry[29].uop.ldst_val
invalidate debug_entry[29].uop.lrs3
invalidate debug_entry[29].uop.lrs2
invalidate debug_entry[29].uop.lrs1
invalidate debug_entry[29].uop.ldst
invalidate debug_entry[29].uop.ldst_is_rs1
invalidate debug_entry[29].uop.flush_on_commit
invalidate debug_entry[29].uop.is_unique
invalidate debug_entry[29].uop.is_sys_pc2epc
invalidate debug_entry[29].uop.uses_stq
invalidate debug_entry[29].uop.uses_ldq
invalidate debug_entry[29].uop.is_amo
invalidate debug_entry[29].uop.is_fencei
invalidate debug_entry[29].uop.is_fence
invalidate debug_entry[29].uop.mem_signed
invalidate debug_entry[29].uop.mem_size
invalidate debug_entry[29].uop.mem_cmd
invalidate debug_entry[29].uop.bypassable
invalidate debug_entry[29].uop.exc_cause
invalidate debug_entry[29].uop.exception
invalidate debug_entry[29].uop.stale_pdst
invalidate debug_entry[29].uop.ppred_busy
invalidate debug_entry[29].uop.prs3_busy
invalidate debug_entry[29].uop.prs2_busy
invalidate debug_entry[29].uop.prs1_busy
invalidate debug_entry[29].uop.ppred
invalidate debug_entry[29].uop.prs3
invalidate debug_entry[29].uop.prs2
invalidate debug_entry[29].uop.prs1
invalidate debug_entry[29].uop.pdst
invalidate debug_entry[29].uop.rxq_idx
invalidate debug_entry[29].uop.stq_idx
invalidate debug_entry[29].uop.ldq_idx
invalidate debug_entry[29].uop.rob_idx
invalidate debug_entry[29].uop.csr_addr
invalidate debug_entry[29].uop.imm_packed
invalidate debug_entry[29].uop.taken
invalidate debug_entry[29].uop.pc_lob
invalidate debug_entry[29].uop.edge_inst
invalidate debug_entry[29].uop.ftq_idx
invalidate debug_entry[29].uop.br_tag
invalidate debug_entry[29].uop.br_mask
invalidate debug_entry[29].uop.is_sfb
invalidate debug_entry[29].uop.is_jal
invalidate debug_entry[29].uop.is_jalr
invalidate debug_entry[29].uop.is_br
invalidate debug_entry[29].uop.iw_p2_poisoned
invalidate debug_entry[29].uop.iw_p1_poisoned
invalidate debug_entry[29].uop.iw_state
invalidate debug_entry[29].uop.ctrl.is_std
invalidate debug_entry[29].uop.ctrl.is_sta
invalidate debug_entry[29].uop.ctrl.is_load
invalidate debug_entry[29].uop.ctrl.csr_cmd
invalidate debug_entry[29].uop.ctrl.fcn_dw
invalidate debug_entry[29].uop.ctrl.op_fcn
invalidate debug_entry[29].uop.ctrl.imm_sel
invalidate debug_entry[29].uop.ctrl.op2_sel
invalidate debug_entry[29].uop.ctrl.op1_sel
invalidate debug_entry[29].uop.ctrl.br_type
invalidate debug_entry[29].uop.fu_code
invalidate debug_entry[29].uop.iq_type
invalidate debug_entry[29].uop.debug_pc
invalidate debug_entry[29].uop.is_rvc
invalidate debug_entry[29].uop.debug_inst
invalidate debug_entry[29].uop.inst
invalidate debug_entry[29].uop.uopc
invalidate debug_entry[29].unsafe
invalidate debug_entry[29].busy
invalidate debug_entry[29].valid
invalidate debug_entry[30].exception
invalidate debug_entry[30].uop.debug_tsrc
invalidate debug_entry[30].uop.debug_fsrc
invalidate debug_entry[30].uop.bp_xcpt_if
invalidate debug_entry[30].uop.bp_debug_if
invalidate debug_entry[30].uop.xcpt_ma_if
invalidate debug_entry[30].uop.xcpt_ae_if
invalidate debug_entry[30].uop.xcpt_pf_if
invalidate debug_entry[30].uop.fp_single
invalidate debug_entry[30].uop.fp_val
invalidate debug_entry[30].uop.frs3_en
invalidate debug_entry[30].uop.lrs2_rtype
invalidate debug_entry[30].uop.lrs1_rtype
invalidate debug_entry[30].uop.dst_rtype
invalidate debug_entry[30].uop.ldst_val
invalidate debug_entry[30].uop.lrs3
invalidate debug_entry[30].uop.lrs2
invalidate debug_entry[30].uop.lrs1
invalidate debug_entry[30].uop.ldst
invalidate debug_entry[30].uop.ldst_is_rs1
invalidate debug_entry[30].uop.flush_on_commit
invalidate debug_entry[30].uop.is_unique
invalidate debug_entry[30].uop.is_sys_pc2epc
invalidate debug_entry[30].uop.uses_stq
invalidate debug_entry[30].uop.uses_ldq
invalidate debug_entry[30].uop.is_amo
invalidate debug_entry[30].uop.is_fencei
invalidate debug_entry[30].uop.is_fence
invalidate debug_entry[30].uop.mem_signed
invalidate debug_entry[30].uop.mem_size
invalidate debug_entry[30].uop.mem_cmd
invalidate debug_entry[30].uop.bypassable
invalidate debug_entry[30].uop.exc_cause
invalidate debug_entry[30].uop.exception
invalidate debug_entry[30].uop.stale_pdst
invalidate debug_entry[30].uop.ppred_busy
invalidate debug_entry[30].uop.prs3_busy
invalidate debug_entry[30].uop.prs2_busy
invalidate debug_entry[30].uop.prs1_busy
invalidate debug_entry[30].uop.ppred
invalidate debug_entry[30].uop.prs3
invalidate debug_entry[30].uop.prs2
invalidate debug_entry[30].uop.prs1
invalidate debug_entry[30].uop.pdst
invalidate debug_entry[30].uop.rxq_idx
invalidate debug_entry[30].uop.stq_idx
invalidate debug_entry[30].uop.ldq_idx
invalidate debug_entry[30].uop.rob_idx
invalidate debug_entry[30].uop.csr_addr
invalidate debug_entry[30].uop.imm_packed
invalidate debug_entry[30].uop.taken
invalidate debug_entry[30].uop.pc_lob
invalidate debug_entry[30].uop.edge_inst
invalidate debug_entry[30].uop.ftq_idx
invalidate debug_entry[30].uop.br_tag
invalidate debug_entry[30].uop.br_mask
invalidate debug_entry[30].uop.is_sfb
invalidate debug_entry[30].uop.is_jal
invalidate debug_entry[30].uop.is_jalr
invalidate debug_entry[30].uop.is_br
invalidate debug_entry[30].uop.iw_p2_poisoned
invalidate debug_entry[30].uop.iw_p1_poisoned
invalidate debug_entry[30].uop.iw_state
invalidate debug_entry[30].uop.ctrl.is_std
invalidate debug_entry[30].uop.ctrl.is_sta
invalidate debug_entry[30].uop.ctrl.is_load
invalidate debug_entry[30].uop.ctrl.csr_cmd
invalidate debug_entry[30].uop.ctrl.fcn_dw
invalidate debug_entry[30].uop.ctrl.op_fcn
invalidate debug_entry[30].uop.ctrl.imm_sel
invalidate debug_entry[30].uop.ctrl.op2_sel
invalidate debug_entry[30].uop.ctrl.op1_sel
invalidate debug_entry[30].uop.ctrl.br_type
invalidate debug_entry[30].uop.fu_code
invalidate debug_entry[30].uop.iq_type
invalidate debug_entry[30].uop.debug_pc
invalidate debug_entry[30].uop.is_rvc
invalidate debug_entry[30].uop.debug_inst
invalidate debug_entry[30].uop.inst
invalidate debug_entry[30].uop.uopc
invalidate debug_entry[30].unsafe
invalidate debug_entry[30].busy
invalidate debug_entry[30].valid
invalidate debug_entry[31].exception
invalidate debug_entry[31].uop.debug_tsrc
invalidate debug_entry[31].uop.debug_fsrc
invalidate debug_entry[31].uop.bp_xcpt_if
invalidate debug_entry[31].uop.bp_debug_if
invalidate debug_entry[31].uop.xcpt_ma_if
invalidate debug_entry[31].uop.xcpt_ae_if
invalidate debug_entry[31].uop.xcpt_pf_if
invalidate debug_entry[31].uop.fp_single
invalidate debug_entry[31].uop.fp_val
invalidate debug_entry[31].uop.frs3_en
invalidate debug_entry[31].uop.lrs2_rtype
invalidate debug_entry[31].uop.lrs1_rtype
invalidate debug_entry[31].uop.dst_rtype
invalidate debug_entry[31].uop.ldst_val
invalidate debug_entry[31].uop.lrs3
invalidate debug_entry[31].uop.lrs2
invalidate debug_entry[31].uop.lrs1
invalidate debug_entry[31].uop.ldst
invalidate debug_entry[31].uop.ldst_is_rs1
invalidate debug_entry[31].uop.flush_on_commit
invalidate debug_entry[31].uop.is_unique
invalidate debug_entry[31].uop.is_sys_pc2epc
invalidate debug_entry[31].uop.uses_stq
invalidate debug_entry[31].uop.uses_ldq
invalidate debug_entry[31].uop.is_amo
invalidate debug_entry[31].uop.is_fencei
invalidate debug_entry[31].uop.is_fence
invalidate debug_entry[31].uop.mem_signed
invalidate debug_entry[31].uop.mem_size
invalidate debug_entry[31].uop.mem_cmd
invalidate debug_entry[31].uop.bypassable
invalidate debug_entry[31].uop.exc_cause
invalidate debug_entry[31].uop.exception
invalidate debug_entry[31].uop.stale_pdst
invalidate debug_entry[31].uop.ppred_busy
invalidate debug_entry[31].uop.prs3_busy
invalidate debug_entry[31].uop.prs2_busy
invalidate debug_entry[31].uop.prs1_busy
invalidate debug_entry[31].uop.ppred
invalidate debug_entry[31].uop.prs3
invalidate debug_entry[31].uop.prs2
invalidate debug_entry[31].uop.prs1
invalidate debug_entry[31].uop.pdst
invalidate debug_entry[31].uop.rxq_idx
invalidate debug_entry[31].uop.stq_idx
invalidate debug_entry[31].uop.ldq_idx
invalidate debug_entry[31].uop.rob_idx
invalidate debug_entry[31].uop.csr_addr
invalidate debug_entry[31].uop.imm_packed
invalidate debug_entry[31].uop.taken
invalidate debug_entry[31].uop.pc_lob
invalidate debug_entry[31].uop.edge_inst
invalidate debug_entry[31].uop.ftq_idx
invalidate debug_entry[31].uop.br_tag
invalidate debug_entry[31].uop.br_mask
invalidate debug_entry[31].uop.is_sfb
invalidate debug_entry[31].uop.is_jal
invalidate debug_entry[31].uop.is_jalr
invalidate debug_entry[31].uop.is_br
invalidate debug_entry[31].uop.iw_p2_poisoned
invalidate debug_entry[31].uop.iw_p1_poisoned
invalidate debug_entry[31].uop.iw_state
invalidate debug_entry[31].uop.ctrl.is_std
invalidate debug_entry[31].uop.ctrl.is_sta
invalidate debug_entry[31].uop.ctrl.is_load
invalidate debug_entry[31].uop.ctrl.csr_cmd
invalidate debug_entry[31].uop.ctrl.fcn_dw
invalidate debug_entry[31].uop.ctrl.op_fcn
invalidate debug_entry[31].uop.ctrl.imm_sel
invalidate debug_entry[31].uop.ctrl.op2_sel
invalidate debug_entry[31].uop.ctrl.op1_sel
invalidate debug_entry[31].uop.ctrl.br_type
invalidate debug_entry[31].uop.fu_code
invalidate debug_entry[31].uop.iq_type
invalidate debug_entry[31].uop.debug_pc
invalidate debug_entry[31].uop.is_rvc
invalidate debug_entry[31].uop.debug_inst
invalidate debug_entry[31].uop.inst
invalidate debug_entry[31].uop.uopc
invalidate debug_entry[31].unsafe
invalidate debug_entry[31].busy
invalidate debug_entry[31].valid
wire _rob_unsafe_masked_WIRE : UInt<1>[32]
connect _rob_unsafe_masked_WIRE[0], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[1], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[2], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[3], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[4], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[5], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[6], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[7], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[8], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[9], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[10], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[11], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[12], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[13], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[14], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[15], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[16], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[17], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[18], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[19], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[20], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[21], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[22], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[23], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[24], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[25], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[26], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[27], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[28], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[29], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[30], UInt<1>(0h0)
connect _rob_unsafe_masked_WIRE[31], UInt<1>(0h0)
wire rob_unsafe_masked : UInt<1>[32]
connect rob_unsafe_masked, _rob_unsafe_masked_WIRE
smem rob_debug_inst_mem : UInt<32>[1] [32]
wire _rob_debug_inst_wmask_WIRE : UInt<1>[1]
connect _rob_debug_inst_wmask_WIRE[0], UInt<1>(0h0)
wire rob_debug_inst_wmask : UInt<1>[1]
connect rob_debug_inst_wmask, _rob_debug_inst_wmask_WIRE
wire rob_debug_inst_wdata : UInt<32>[1]
write mport MPORT = rob_debug_inst_mem[rob_tail], clock
when rob_debug_inst_wmask[0] :
connect MPORT[0], rob_debug_inst_wdata[0]
wire _rob_debug_inst_rdata_WIRE : UInt<5>
invalidate _rob_debug_inst_rdata_WIRE
when will_commit[0] :
connect _rob_debug_inst_rdata_WIRE, rob_head
read mport rob_debug_inst_rdata = rob_debug_inst_mem[_rob_debug_inst_rdata_WIRE], clock
reg rob_fflags_0 : UInt<5>[32], clock
wire _rob_val_WIRE : UInt<1>[32]
connect _rob_val_WIRE[0], UInt<1>(0h0)
connect _rob_val_WIRE[1], UInt<1>(0h0)
connect _rob_val_WIRE[2], UInt<1>(0h0)
connect _rob_val_WIRE[3], UInt<1>(0h0)
connect _rob_val_WIRE[4], UInt<1>(0h0)
connect _rob_val_WIRE[5], UInt<1>(0h0)
connect _rob_val_WIRE[6], UInt<1>(0h0)
connect _rob_val_WIRE[7], UInt<1>(0h0)
connect _rob_val_WIRE[8], UInt<1>(0h0)
connect _rob_val_WIRE[9], UInt<1>(0h0)
connect _rob_val_WIRE[10], UInt<1>(0h0)
connect _rob_val_WIRE[11], UInt<1>(0h0)
connect _rob_val_WIRE[12], UInt<1>(0h0)
connect _rob_val_WIRE[13], UInt<1>(0h0)
connect _rob_val_WIRE[14], UInt<1>(0h0)
connect _rob_val_WIRE[15], UInt<1>(0h0)
connect _rob_val_WIRE[16], UInt<1>(0h0)
connect _rob_val_WIRE[17], UInt<1>(0h0)
connect _rob_val_WIRE[18], UInt<1>(0h0)
connect _rob_val_WIRE[19], UInt<1>(0h0)
connect _rob_val_WIRE[20], UInt<1>(0h0)
connect _rob_val_WIRE[21], UInt<1>(0h0)
connect _rob_val_WIRE[22], UInt<1>(0h0)
connect _rob_val_WIRE[23], UInt<1>(0h0)
connect _rob_val_WIRE[24], UInt<1>(0h0)
connect _rob_val_WIRE[25], UInt<1>(0h0)
connect _rob_val_WIRE[26], UInt<1>(0h0)
connect _rob_val_WIRE[27], UInt<1>(0h0)
connect _rob_val_WIRE[28], UInt<1>(0h0)
connect _rob_val_WIRE[29], UInt<1>(0h0)
connect _rob_val_WIRE[30], UInt<1>(0h0)
connect _rob_val_WIRE[31], UInt<1>(0h0)
regreset rob_val : UInt<1>[32], clock, reset, _rob_val_WIRE
reg rob_bsy : UInt<1>[32], clock
reg rob_unsafe : UInt<1>[32], clock
reg rob_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[32], clock
reg rob_exception : UInt<1>[32], clock
reg rob_predicated : UInt<1>[32], clock
cmem rob_debug_wdata : UInt<64> [32]
connect rob_debug_inst_wmask[0], io.enq_valids[0]
connect rob_debug_inst_wdata[0], io.enq_uops[0].debug_inst
when io.enq_valids[0] :
connect rob_val[rob_tail], UInt<1>(0h1)
node _rob_bsy_T = or(io.enq_uops[0].is_fence, io.enq_uops[0].is_fencei)
node _rob_bsy_T_1 = eq(_rob_bsy_T, UInt<1>(0h0))
connect rob_bsy[rob_tail], _rob_bsy_T_1
node _rob_unsafe_T = eq(io.enq_uops[0].is_fence, UInt<1>(0h0))
node _rob_unsafe_T_1 = and(io.enq_uops[0].uses_stq, _rob_unsafe_T)
node _rob_unsafe_T_2 = or(io.enq_uops[0].uses_ldq, _rob_unsafe_T_1)
node _rob_unsafe_T_3 = or(_rob_unsafe_T_2, io.enq_uops[0].is_br)
node _rob_unsafe_T_4 = or(_rob_unsafe_T_3, io.enq_uops[0].is_jalr)
connect rob_unsafe[rob_tail], _rob_unsafe_T_4
connect rob_uop[rob_tail], io.enq_uops[0]
connect rob_exception[rob_tail], io.enq_uops[0].exception
connect rob_predicated[rob_tail], UInt<1>(0h0)
connect rob_fflags_0[rob_tail], UInt<1>(0h0)
node _T = eq(rob_val[rob_tail], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] overwriting a valid entry.\n at rob.scala:333 assert (rob_val(rob_tail) === false.B, \"[rob] overwriting a valid entry.\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _T_4 = shr(io.enq_uops[0].rob_idx, 0)
node _T_5 = eq(_T_4, rob_tail)
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at rob.scala:334 assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
else :
node _T_9 = eq(rob_val[rob_tail], UInt<1>(0h0))
node _T_10 = and(io.enq_valids[0], _T_9)
when _T_10 :
connect rob_uop[rob_tail].debug_inst, UInt<32>(0h4033)
node _T_11 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_12 = and(io.wb_resps[0].valid, _T_11)
when _T_12 :
connect rob_bsy[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_unsafe[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_predicated[io.wb_resps[0].bits.uop.rob_idx], io.wb_resps[0].bits.predicated
node _T_13 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_14 = and(io.wb_resps[1].valid, _T_13)
when _T_14 :
connect rob_bsy[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_unsafe[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_predicated[io.wb_resps[1].bits.uop.rob_idx], io.wb_resps[1].bits.predicated
node _T_15 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_16 = and(io.wb_resps[2].valid, _T_15)
when _T_16 :
connect rob_bsy[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_unsafe[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_predicated[io.wb_resps[2].bits.uop.rob_idx], io.wb_resps[2].bits.predicated
node _T_17 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_18 = and(io.wb_resps[3].valid, _T_17)
when _T_18 :
connect rob_bsy[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_unsafe[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0)
connect rob_predicated[io.wb_resps[3].bits.uop.rob_idx], io.wb_resps[3].bits.predicated
node _T_19 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = and(io.lsu_clr_bsy[0].valid, _T_19)
when _T_20 :
connect rob_bsy[io.lsu_clr_bsy[0].bits], UInt<1>(0h0)
connect rob_unsafe[io.lsu_clr_bsy[0].bits], UInt<1>(0h0)
node _T_21 = eq(rob_val[io.lsu_clr_bsy[0].bits], UInt<1>(0h1))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] store writing back to invalid entry.\n at rob.scala:365 assert (rob_val(cidx) === true.B, \"[rob] store writing back to invalid entry.\")\n") : printf_2
assert(clock, _T_21, UInt<1>(0h1), "") : assert_2
node _T_25 = eq(rob_bsy[io.lsu_clr_bsy[0].bits], UInt<1>(0h1))
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] store writing back to a not-busy entry.\n at rob.scala:366 assert (rob_bsy(cidx) === true.B, \"[rob] store writing back to a not-busy entry.\")\n") : printf_3
assert(clock, _T_25, UInt<1>(0h1), "") : assert_3
node _T_29 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_30 = and(io.lsu_clr_bsy[1].valid, _T_29)
when _T_30 :
connect rob_bsy[io.lsu_clr_bsy[1].bits], UInt<1>(0h0)
connect rob_unsafe[io.lsu_clr_bsy[1].bits], UInt<1>(0h0)
node _T_31 = eq(rob_val[io.lsu_clr_bsy[1].bits], UInt<1>(0h1))
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
node _T_34 = eq(_T_31, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] store writing back to invalid entry.\n at rob.scala:365 assert (rob_val(cidx) === true.B, \"[rob] store writing back to invalid entry.\")\n") : printf_4
assert(clock, _T_31, UInt<1>(0h1), "") : assert_4
node _T_35 = eq(rob_bsy[io.lsu_clr_bsy[1].bits], UInt<1>(0h1))
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
node _T_38 = eq(_T_35, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] store writing back to a not-busy entry.\n at rob.scala:366 assert (rob_bsy(cidx) === true.B, \"[rob] store writing back to a not-busy entry.\")\n") : printf_5
assert(clock, _T_35, UInt<1>(0h1), "") : assert_5
node _T_39 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_40 = and(io.lsu_clr_unsafe[0].valid, _T_39)
when _T_40 :
connect rob_unsafe[io.lsu_clr_unsafe[0].bits], UInt<1>(0h0)
node _T_41 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_42 = and(io.fflags[0].valid, _T_41)
when _T_42 :
connect rob_fflags_0[io.fflags[0].bits.uop.rob_idx], io.fflags[0].bits.flags
node _T_43 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_44 = and(io.fflags[1].valid, _T_43)
when _T_44 :
connect rob_fflags_0[io.fflags[1].bits.uop.rob_idx], io.fflags[1].bits.flags
node _T_45 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_46 = and(io.lxcpt.valid, _T_45)
when _T_46 :
connect rob_exception[io.lxcpt.bits.uop.rob_idx], UInt<1>(0h1)
node _T_47 = neq(io.lxcpt.bits.cause, UInt<5>(0h10))
when _T_47 :
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
node _T_50 = eq(rob_unsafe[io.lxcpt.bits.uop.rob_idx], UInt<1>(0h0))
when _T_50 :
printf(clock, UInt<1>(0h1), "Assertion failed: An instruction marked as safe is causing an exception\n at rob.scala:394 assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),\n") : printf_6
assert(clock, rob_unsafe[io.lxcpt.bits.uop.rob_idx], UInt<1>(0h1), "") : assert_6
node _T_51 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_52 = and(io.csr_replay.valid, _T_51)
when _T_52 :
connect rob_exception[io.csr_replay.bits.uop.rob_idx], UInt<1>(0h1)
node _can_throw_exception_0_T = and(rob_val[rob_head], rob_exception[rob_head])
connect can_throw_exception[0], _can_throw_exception_0_T
node _can_commit_0_T = eq(rob_bsy[rob_head], UInt<1>(0h0))
node _can_commit_0_T_1 = and(rob_val[rob_head], _can_commit_0_T)
node _can_commit_0_T_2 = eq(io.csr_stall, UInt<1>(0h0))
node _can_commit_0_T_3 = and(_can_commit_0_T_1, _can_commit_0_T_2)
connect can_commit[0], _can_commit_0_T_3
connect io.commit.valids[0], will_commit[0]
node _io_commit_arch_valids_0_T = eq(rob_predicated[com_idx], UInt<1>(0h0))
node _io_commit_arch_valids_0_T_1 = and(will_commit[0], _io_commit_arch_valids_0_T)
connect io.commit.arch_valids[0], _io_commit_arch_valids_0_T_1
connect io.commit.uops[0], rob_uop[com_idx]
connect io.commit.debug_insts[0], rob_debug_inst_rdata[0]
node _T_53 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_54 = and(io.brupdate.b2.mispredict, _T_53)
node _T_55 = eq(io.brupdate.b2.uop.rob_idx, com_idx)
node _T_56 = and(_T_54, _T_55)
when _T_56 :
connect io.commit.uops[0].debug_fsrc, UInt<2>(0h3)
connect io.commit.uops[0].taken, io.brupdate.b2.taken
node _rbk_row_T = eq(rob_state, UInt<2>(0h2))
node _rbk_row_T_1 = eq(full, UInt<1>(0h0))
node rbk_row = and(_rbk_row_T, _rbk_row_T_1)
node _io_commit_rbk_valids_0_T = and(rbk_row, rob_val[com_idx])
node _io_commit_rbk_valids_0_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _io_commit_rbk_valids_0_T_2 = and(_io_commit_rbk_valids_0_T, _io_commit_rbk_valids_0_T_1)
connect io.commit.rbk_valids[0], _io_commit_rbk_valids_0_T_2
node _io_commit_rollback_T = eq(rob_state, UInt<2>(0h2))
connect io.commit.rollback, _io_commit_rollback_T
node _T_57 = and(io.commit.valids[0], io.commit.rbk_valids[0])
node _T_58 = eq(_T_57, UInt<1>(0h0))
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: com_valids and rbk_valids are mutually exclusive\n at rob.scala:434 assert (!(io.commit.valids.reduce(_||_) && io.commit.rbk_valids.reduce(_||_)),\n") : printf_7
assert(clock, _T_58, UInt<1>(0h1), "") : assert_7
when rbk_row :
connect rob_val[com_idx], UInt<1>(0h0)
connect rob_exception[com_idx], UInt<1>(0h0)
node _T_62 = and(io.brupdate.b1.mispredict_mask, rob_uop[0].br_mask)
node _T_63 = neq(_T_62, UInt<1>(0h0))
when _T_63 :
connect rob_val[0], UInt<1>(0h0)
connect rob_uop[0].debug_inst, UInt<32>(0h4033)
else :
when rob_val[0] :
node _rob_uop_0_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_0_br_mask_T_1 = and(rob_uop[0].br_mask, _rob_uop_0_br_mask_T)
connect rob_uop[0].br_mask, _rob_uop_0_br_mask_T_1
node _T_64 = and(io.brupdate.b1.mispredict_mask, rob_uop[1].br_mask)
node _T_65 = neq(_T_64, UInt<1>(0h0))
when _T_65 :
connect rob_val[1], UInt<1>(0h0)
connect rob_uop[1].debug_inst, UInt<32>(0h4033)
else :
when rob_val[1] :
node _rob_uop_1_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_1_br_mask_T_1 = and(rob_uop[1].br_mask, _rob_uop_1_br_mask_T)
connect rob_uop[1].br_mask, _rob_uop_1_br_mask_T_1
node _T_66 = and(io.brupdate.b1.mispredict_mask, rob_uop[2].br_mask)
node _T_67 = neq(_T_66, UInt<1>(0h0))
when _T_67 :
connect rob_val[2], UInt<1>(0h0)
connect rob_uop[2].debug_inst, UInt<32>(0h4033)
else :
when rob_val[2] :
node _rob_uop_2_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_2_br_mask_T_1 = and(rob_uop[2].br_mask, _rob_uop_2_br_mask_T)
connect rob_uop[2].br_mask, _rob_uop_2_br_mask_T_1
node _T_68 = and(io.brupdate.b1.mispredict_mask, rob_uop[3].br_mask)
node _T_69 = neq(_T_68, UInt<1>(0h0))
when _T_69 :
connect rob_val[3], UInt<1>(0h0)
connect rob_uop[3].debug_inst, UInt<32>(0h4033)
else :
when rob_val[3] :
node _rob_uop_3_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_3_br_mask_T_1 = and(rob_uop[3].br_mask, _rob_uop_3_br_mask_T)
connect rob_uop[3].br_mask, _rob_uop_3_br_mask_T_1
node _T_70 = and(io.brupdate.b1.mispredict_mask, rob_uop[4].br_mask)
node _T_71 = neq(_T_70, UInt<1>(0h0))
when _T_71 :
connect rob_val[4], UInt<1>(0h0)
connect rob_uop[4].debug_inst, UInt<32>(0h4033)
else :
when rob_val[4] :
node _rob_uop_4_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_4_br_mask_T_1 = and(rob_uop[4].br_mask, _rob_uop_4_br_mask_T)
connect rob_uop[4].br_mask, _rob_uop_4_br_mask_T_1
node _T_72 = and(io.brupdate.b1.mispredict_mask, rob_uop[5].br_mask)
node _T_73 = neq(_T_72, UInt<1>(0h0))
when _T_73 :
connect rob_val[5], UInt<1>(0h0)
connect rob_uop[5].debug_inst, UInt<32>(0h4033)
else :
when rob_val[5] :
node _rob_uop_5_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_5_br_mask_T_1 = and(rob_uop[5].br_mask, _rob_uop_5_br_mask_T)
connect rob_uop[5].br_mask, _rob_uop_5_br_mask_T_1
node _T_74 = and(io.brupdate.b1.mispredict_mask, rob_uop[6].br_mask)
node _T_75 = neq(_T_74, UInt<1>(0h0))
when _T_75 :
connect rob_val[6], UInt<1>(0h0)
connect rob_uop[6].debug_inst, UInt<32>(0h4033)
else :
when rob_val[6] :
node _rob_uop_6_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_6_br_mask_T_1 = and(rob_uop[6].br_mask, _rob_uop_6_br_mask_T)
connect rob_uop[6].br_mask, _rob_uop_6_br_mask_T_1
node _T_76 = and(io.brupdate.b1.mispredict_mask, rob_uop[7].br_mask)
node _T_77 = neq(_T_76, UInt<1>(0h0))
when _T_77 :
connect rob_val[7], UInt<1>(0h0)
connect rob_uop[7].debug_inst, UInt<32>(0h4033)
else :
when rob_val[7] :
node _rob_uop_7_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_7_br_mask_T_1 = and(rob_uop[7].br_mask, _rob_uop_7_br_mask_T)
connect rob_uop[7].br_mask, _rob_uop_7_br_mask_T_1
node _T_78 = and(io.brupdate.b1.mispredict_mask, rob_uop[8].br_mask)
node _T_79 = neq(_T_78, UInt<1>(0h0))
when _T_79 :
connect rob_val[8], UInt<1>(0h0)
connect rob_uop[8].debug_inst, UInt<32>(0h4033)
else :
when rob_val[8] :
node _rob_uop_8_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_8_br_mask_T_1 = and(rob_uop[8].br_mask, _rob_uop_8_br_mask_T)
connect rob_uop[8].br_mask, _rob_uop_8_br_mask_T_1
node _T_80 = and(io.brupdate.b1.mispredict_mask, rob_uop[9].br_mask)
node _T_81 = neq(_T_80, UInt<1>(0h0))
when _T_81 :
connect rob_val[9], UInt<1>(0h0)
connect rob_uop[9].debug_inst, UInt<32>(0h4033)
else :
when rob_val[9] :
node _rob_uop_9_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_9_br_mask_T_1 = and(rob_uop[9].br_mask, _rob_uop_9_br_mask_T)
connect rob_uop[9].br_mask, _rob_uop_9_br_mask_T_1
node _T_82 = and(io.brupdate.b1.mispredict_mask, rob_uop[10].br_mask)
node _T_83 = neq(_T_82, UInt<1>(0h0))
when _T_83 :
connect rob_val[10], UInt<1>(0h0)
connect rob_uop[10].debug_inst, UInt<32>(0h4033)
else :
when rob_val[10] :
node _rob_uop_10_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_10_br_mask_T_1 = and(rob_uop[10].br_mask, _rob_uop_10_br_mask_T)
connect rob_uop[10].br_mask, _rob_uop_10_br_mask_T_1
node _T_84 = and(io.brupdate.b1.mispredict_mask, rob_uop[11].br_mask)
node _T_85 = neq(_T_84, UInt<1>(0h0))
when _T_85 :
connect rob_val[11], UInt<1>(0h0)
connect rob_uop[11].debug_inst, UInt<32>(0h4033)
else :
when rob_val[11] :
node _rob_uop_11_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_11_br_mask_T_1 = and(rob_uop[11].br_mask, _rob_uop_11_br_mask_T)
connect rob_uop[11].br_mask, _rob_uop_11_br_mask_T_1
node _T_86 = and(io.brupdate.b1.mispredict_mask, rob_uop[12].br_mask)
node _T_87 = neq(_T_86, UInt<1>(0h0))
when _T_87 :
connect rob_val[12], UInt<1>(0h0)
connect rob_uop[12].debug_inst, UInt<32>(0h4033)
else :
when rob_val[12] :
node _rob_uop_12_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_12_br_mask_T_1 = and(rob_uop[12].br_mask, _rob_uop_12_br_mask_T)
connect rob_uop[12].br_mask, _rob_uop_12_br_mask_T_1
node _T_88 = and(io.brupdate.b1.mispredict_mask, rob_uop[13].br_mask)
node _T_89 = neq(_T_88, UInt<1>(0h0))
when _T_89 :
connect rob_val[13], UInt<1>(0h0)
connect rob_uop[13].debug_inst, UInt<32>(0h4033)
else :
when rob_val[13] :
node _rob_uop_13_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_13_br_mask_T_1 = and(rob_uop[13].br_mask, _rob_uop_13_br_mask_T)
connect rob_uop[13].br_mask, _rob_uop_13_br_mask_T_1
node _T_90 = and(io.brupdate.b1.mispredict_mask, rob_uop[14].br_mask)
node _T_91 = neq(_T_90, UInt<1>(0h0))
when _T_91 :
connect rob_val[14], UInt<1>(0h0)
connect rob_uop[14].debug_inst, UInt<32>(0h4033)
else :
when rob_val[14] :
node _rob_uop_14_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_14_br_mask_T_1 = and(rob_uop[14].br_mask, _rob_uop_14_br_mask_T)
connect rob_uop[14].br_mask, _rob_uop_14_br_mask_T_1
node _T_92 = and(io.brupdate.b1.mispredict_mask, rob_uop[15].br_mask)
node _T_93 = neq(_T_92, UInt<1>(0h0))
when _T_93 :
connect rob_val[15], UInt<1>(0h0)
connect rob_uop[15].debug_inst, UInt<32>(0h4033)
else :
when rob_val[15] :
node _rob_uop_15_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_15_br_mask_T_1 = and(rob_uop[15].br_mask, _rob_uop_15_br_mask_T)
connect rob_uop[15].br_mask, _rob_uop_15_br_mask_T_1
node _T_94 = and(io.brupdate.b1.mispredict_mask, rob_uop[16].br_mask)
node _T_95 = neq(_T_94, UInt<1>(0h0))
when _T_95 :
connect rob_val[16], UInt<1>(0h0)
connect rob_uop[16].debug_inst, UInt<32>(0h4033)
else :
when rob_val[16] :
node _rob_uop_16_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_16_br_mask_T_1 = and(rob_uop[16].br_mask, _rob_uop_16_br_mask_T)
connect rob_uop[16].br_mask, _rob_uop_16_br_mask_T_1
node _T_96 = and(io.brupdate.b1.mispredict_mask, rob_uop[17].br_mask)
node _T_97 = neq(_T_96, UInt<1>(0h0))
when _T_97 :
connect rob_val[17], UInt<1>(0h0)
connect rob_uop[17].debug_inst, UInt<32>(0h4033)
else :
when rob_val[17] :
node _rob_uop_17_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_17_br_mask_T_1 = and(rob_uop[17].br_mask, _rob_uop_17_br_mask_T)
connect rob_uop[17].br_mask, _rob_uop_17_br_mask_T_1
node _T_98 = and(io.brupdate.b1.mispredict_mask, rob_uop[18].br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect rob_val[18], UInt<1>(0h0)
connect rob_uop[18].debug_inst, UInt<32>(0h4033)
else :
when rob_val[18] :
node _rob_uop_18_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_18_br_mask_T_1 = and(rob_uop[18].br_mask, _rob_uop_18_br_mask_T)
connect rob_uop[18].br_mask, _rob_uop_18_br_mask_T_1
node _T_100 = and(io.brupdate.b1.mispredict_mask, rob_uop[19].br_mask)
node _T_101 = neq(_T_100, UInt<1>(0h0))
when _T_101 :
connect rob_val[19], UInt<1>(0h0)
connect rob_uop[19].debug_inst, UInt<32>(0h4033)
else :
when rob_val[19] :
node _rob_uop_19_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_19_br_mask_T_1 = and(rob_uop[19].br_mask, _rob_uop_19_br_mask_T)
connect rob_uop[19].br_mask, _rob_uop_19_br_mask_T_1
node _T_102 = and(io.brupdate.b1.mispredict_mask, rob_uop[20].br_mask)
node _T_103 = neq(_T_102, UInt<1>(0h0))
when _T_103 :
connect rob_val[20], UInt<1>(0h0)
connect rob_uop[20].debug_inst, UInt<32>(0h4033)
else :
when rob_val[20] :
node _rob_uop_20_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_20_br_mask_T_1 = and(rob_uop[20].br_mask, _rob_uop_20_br_mask_T)
connect rob_uop[20].br_mask, _rob_uop_20_br_mask_T_1
node _T_104 = and(io.brupdate.b1.mispredict_mask, rob_uop[21].br_mask)
node _T_105 = neq(_T_104, UInt<1>(0h0))
when _T_105 :
connect rob_val[21], UInt<1>(0h0)
connect rob_uop[21].debug_inst, UInt<32>(0h4033)
else :
when rob_val[21] :
node _rob_uop_21_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_21_br_mask_T_1 = and(rob_uop[21].br_mask, _rob_uop_21_br_mask_T)
connect rob_uop[21].br_mask, _rob_uop_21_br_mask_T_1
node _T_106 = and(io.brupdate.b1.mispredict_mask, rob_uop[22].br_mask)
node _T_107 = neq(_T_106, UInt<1>(0h0))
when _T_107 :
connect rob_val[22], UInt<1>(0h0)
connect rob_uop[22].debug_inst, UInt<32>(0h4033)
else :
when rob_val[22] :
node _rob_uop_22_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_22_br_mask_T_1 = and(rob_uop[22].br_mask, _rob_uop_22_br_mask_T)
connect rob_uop[22].br_mask, _rob_uop_22_br_mask_T_1
node _T_108 = and(io.brupdate.b1.mispredict_mask, rob_uop[23].br_mask)
node _T_109 = neq(_T_108, UInt<1>(0h0))
when _T_109 :
connect rob_val[23], UInt<1>(0h0)
connect rob_uop[23].debug_inst, UInt<32>(0h4033)
else :
when rob_val[23] :
node _rob_uop_23_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_23_br_mask_T_1 = and(rob_uop[23].br_mask, _rob_uop_23_br_mask_T)
connect rob_uop[23].br_mask, _rob_uop_23_br_mask_T_1
node _T_110 = and(io.brupdate.b1.mispredict_mask, rob_uop[24].br_mask)
node _T_111 = neq(_T_110, UInt<1>(0h0))
when _T_111 :
connect rob_val[24], UInt<1>(0h0)
connect rob_uop[24].debug_inst, UInt<32>(0h4033)
else :
when rob_val[24] :
node _rob_uop_24_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_24_br_mask_T_1 = and(rob_uop[24].br_mask, _rob_uop_24_br_mask_T)
connect rob_uop[24].br_mask, _rob_uop_24_br_mask_T_1
node _T_112 = and(io.brupdate.b1.mispredict_mask, rob_uop[25].br_mask)
node _T_113 = neq(_T_112, UInt<1>(0h0))
when _T_113 :
connect rob_val[25], UInt<1>(0h0)
connect rob_uop[25].debug_inst, UInt<32>(0h4033)
else :
when rob_val[25] :
node _rob_uop_25_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_25_br_mask_T_1 = and(rob_uop[25].br_mask, _rob_uop_25_br_mask_T)
connect rob_uop[25].br_mask, _rob_uop_25_br_mask_T_1
node _T_114 = and(io.brupdate.b1.mispredict_mask, rob_uop[26].br_mask)
node _T_115 = neq(_T_114, UInt<1>(0h0))
when _T_115 :
connect rob_val[26], UInt<1>(0h0)
connect rob_uop[26].debug_inst, UInt<32>(0h4033)
else :
when rob_val[26] :
node _rob_uop_26_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_26_br_mask_T_1 = and(rob_uop[26].br_mask, _rob_uop_26_br_mask_T)
connect rob_uop[26].br_mask, _rob_uop_26_br_mask_T_1
node _T_116 = and(io.brupdate.b1.mispredict_mask, rob_uop[27].br_mask)
node _T_117 = neq(_T_116, UInt<1>(0h0))
when _T_117 :
connect rob_val[27], UInt<1>(0h0)
connect rob_uop[27].debug_inst, UInt<32>(0h4033)
else :
when rob_val[27] :
node _rob_uop_27_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_27_br_mask_T_1 = and(rob_uop[27].br_mask, _rob_uop_27_br_mask_T)
connect rob_uop[27].br_mask, _rob_uop_27_br_mask_T_1
node _T_118 = and(io.brupdate.b1.mispredict_mask, rob_uop[28].br_mask)
node _T_119 = neq(_T_118, UInt<1>(0h0))
when _T_119 :
connect rob_val[28], UInt<1>(0h0)
connect rob_uop[28].debug_inst, UInt<32>(0h4033)
else :
when rob_val[28] :
node _rob_uop_28_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_28_br_mask_T_1 = and(rob_uop[28].br_mask, _rob_uop_28_br_mask_T)
connect rob_uop[28].br_mask, _rob_uop_28_br_mask_T_1
node _T_120 = and(io.brupdate.b1.mispredict_mask, rob_uop[29].br_mask)
node _T_121 = neq(_T_120, UInt<1>(0h0))
when _T_121 :
connect rob_val[29], UInt<1>(0h0)
connect rob_uop[29].debug_inst, UInt<32>(0h4033)
else :
when rob_val[29] :
node _rob_uop_29_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_29_br_mask_T_1 = and(rob_uop[29].br_mask, _rob_uop_29_br_mask_T)
connect rob_uop[29].br_mask, _rob_uop_29_br_mask_T_1
node _T_122 = and(io.brupdate.b1.mispredict_mask, rob_uop[30].br_mask)
node _T_123 = neq(_T_122, UInt<1>(0h0))
when _T_123 :
connect rob_val[30], UInt<1>(0h0)
connect rob_uop[30].debug_inst, UInt<32>(0h4033)
else :
when rob_val[30] :
node _rob_uop_30_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_30_br_mask_T_1 = and(rob_uop[30].br_mask, _rob_uop_30_br_mask_T)
connect rob_uop[30].br_mask, _rob_uop_30_br_mask_T_1
node _T_124 = and(io.brupdate.b1.mispredict_mask, rob_uop[31].br_mask)
node _T_125 = neq(_T_124, UInt<1>(0h0))
when _T_125 :
connect rob_val[31], UInt<1>(0h0)
connect rob_uop[31].debug_inst, UInt<32>(0h4033)
else :
when rob_val[31] :
node _rob_uop_31_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _rob_uop_31_br_mask_T_1 = and(rob_uop[31].br_mask, _rob_uop_31_br_mask_T)
connect rob_uop[31].br_mask, _rob_uop_31_br_mask_T_1
node _T_126 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_127 = and(io.brupdate.b2.mispredict, _T_126)
when _T_127 :
connect rob_uop[io.brupdate.b2.uop.rob_idx].debug_fsrc, UInt<2>(0h3)
connect rob_uop[io.brupdate.b2.uop.rob_idx].taken, io.brupdate.b2.taken
when will_commit[0] :
connect rob_val[rob_head], UInt<1>(0h0)
connect rob_head_vals[0], rob_val[rob_head]
connect rob_tail_vals[0], rob_val[rob_tail]
connect rob_head_fflags[0], rob_fflags_0[rob_head]
connect rob_head_uses_stq[0], rob_uop[rob_head].uses_stq
connect rob_head_uses_ldq[0], rob_uop[rob_head].uses_ldq
node _rob_unsafe_masked_0_T = or(rob_unsafe[0], rob_exception[0])
node _rob_unsafe_masked_0_T_1 = and(rob_val[0], _rob_unsafe_masked_0_T)
connect rob_unsafe_masked[0], _rob_unsafe_masked_0_T_1
node _rob_unsafe_masked_1_T = or(rob_unsafe[1], rob_exception[1])
node _rob_unsafe_masked_1_T_1 = and(rob_val[1], _rob_unsafe_masked_1_T)
connect rob_unsafe_masked[1], _rob_unsafe_masked_1_T_1
node _rob_unsafe_masked_2_T = or(rob_unsafe[2], rob_exception[2])
node _rob_unsafe_masked_2_T_1 = and(rob_val[2], _rob_unsafe_masked_2_T)
connect rob_unsafe_masked[2], _rob_unsafe_masked_2_T_1
node _rob_unsafe_masked_3_T = or(rob_unsafe[3], rob_exception[3])
node _rob_unsafe_masked_3_T_1 = and(rob_val[3], _rob_unsafe_masked_3_T)
connect rob_unsafe_masked[3], _rob_unsafe_masked_3_T_1
node _rob_unsafe_masked_4_T = or(rob_unsafe[4], rob_exception[4])
node _rob_unsafe_masked_4_T_1 = and(rob_val[4], _rob_unsafe_masked_4_T)
connect rob_unsafe_masked[4], _rob_unsafe_masked_4_T_1
node _rob_unsafe_masked_5_T = or(rob_unsafe[5], rob_exception[5])
node _rob_unsafe_masked_5_T_1 = and(rob_val[5], _rob_unsafe_masked_5_T)
connect rob_unsafe_masked[5], _rob_unsafe_masked_5_T_1
node _rob_unsafe_masked_6_T = or(rob_unsafe[6], rob_exception[6])
node _rob_unsafe_masked_6_T_1 = and(rob_val[6], _rob_unsafe_masked_6_T)
connect rob_unsafe_masked[6], _rob_unsafe_masked_6_T_1
node _rob_unsafe_masked_7_T = or(rob_unsafe[7], rob_exception[7])
node _rob_unsafe_masked_7_T_1 = and(rob_val[7], _rob_unsafe_masked_7_T)
connect rob_unsafe_masked[7], _rob_unsafe_masked_7_T_1
node _rob_unsafe_masked_8_T = or(rob_unsafe[8], rob_exception[8])
node _rob_unsafe_masked_8_T_1 = and(rob_val[8], _rob_unsafe_masked_8_T)
connect rob_unsafe_masked[8], _rob_unsafe_masked_8_T_1
node _rob_unsafe_masked_9_T = or(rob_unsafe[9], rob_exception[9])
node _rob_unsafe_masked_9_T_1 = and(rob_val[9], _rob_unsafe_masked_9_T)
connect rob_unsafe_masked[9], _rob_unsafe_masked_9_T_1
node _rob_unsafe_masked_10_T = or(rob_unsafe[10], rob_exception[10])
node _rob_unsafe_masked_10_T_1 = and(rob_val[10], _rob_unsafe_masked_10_T)
connect rob_unsafe_masked[10], _rob_unsafe_masked_10_T_1
node _rob_unsafe_masked_11_T = or(rob_unsafe[11], rob_exception[11])
node _rob_unsafe_masked_11_T_1 = and(rob_val[11], _rob_unsafe_masked_11_T)
connect rob_unsafe_masked[11], _rob_unsafe_masked_11_T_1
node _rob_unsafe_masked_12_T = or(rob_unsafe[12], rob_exception[12])
node _rob_unsafe_masked_12_T_1 = and(rob_val[12], _rob_unsafe_masked_12_T)
connect rob_unsafe_masked[12], _rob_unsafe_masked_12_T_1
node _rob_unsafe_masked_13_T = or(rob_unsafe[13], rob_exception[13])
node _rob_unsafe_masked_13_T_1 = and(rob_val[13], _rob_unsafe_masked_13_T)
connect rob_unsafe_masked[13], _rob_unsafe_masked_13_T_1
node _rob_unsafe_masked_14_T = or(rob_unsafe[14], rob_exception[14])
node _rob_unsafe_masked_14_T_1 = and(rob_val[14], _rob_unsafe_masked_14_T)
connect rob_unsafe_masked[14], _rob_unsafe_masked_14_T_1
node _rob_unsafe_masked_15_T = or(rob_unsafe[15], rob_exception[15])
node _rob_unsafe_masked_15_T_1 = and(rob_val[15], _rob_unsafe_masked_15_T)
connect rob_unsafe_masked[15], _rob_unsafe_masked_15_T_1
node _rob_unsafe_masked_16_T = or(rob_unsafe[16], rob_exception[16])
node _rob_unsafe_masked_16_T_1 = and(rob_val[16], _rob_unsafe_masked_16_T)
connect rob_unsafe_masked[16], _rob_unsafe_masked_16_T_1
node _rob_unsafe_masked_17_T = or(rob_unsafe[17], rob_exception[17])
node _rob_unsafe_masked_17_T_1 = and(rob_val[17], _rob_unsafe_masked_17_T)
connect rob_unsafe_masked[17], _rob_unsafe_masked_17_T_1
node _rob_unsafe_masked_18_T = or(rob_unsafe[18], rob_exception[18])
node _rob_unsafe_masked_18_T_1 = and(rob_val[18], _rob_unsafe_masked_18_T)
connect rob_unsafe_masked[18], _rob_unsafe_masked_18_T_1
node _rob_unsafe_masked_19_T = or(rob_unsafe[19], rob_exception[19])
node _rob_unsafe_masked_19_T_1 = and(rob_val[19], _rob_unsafe_masked_19_T)
connect rob_unsafe_masked[19], _rob_unsafe_masked_19_T_1
node _rob_unsafe_masked_20_T = or(rob_unsafe[20], rob_exception[20])
node _rob_unsafe_masked_20_T_1 = and(rob_val[20], _rob_unsafe_masked_20_T)
connect rob_unsafe_masked[20], _rob_unsafe_masked_20_T_1
node _rob_unsafe_masked_21_T = or(rob_unsafe[21], rob_exception[21])
node _rob_unsafe_masked_21_T_1 = and(rob_val[21], _rob_unsafe_masked_21_T)
connect rob_unsafe_masked[21], _rob_unsafe_masked_21_T_1
node _rob_unsafe_masked_22_T = or(rob_unsafe[22], rob_exception[22])
node _rob_unsafe_masked_22_T_1 = and(rob_val[22], _rob_unsafe_masked_22_T)
connect rob_unsafe_masked[22], _rob_unsafe_masked_22_T_1
node _rob_unsafe_masked_23_T = or(rob_unsafe[23], rob_exception[23])
node _rob_unsafe_masked_23_T_1 = and(rob_val[23], _rob_unsafe_masked_23_T)
connect rob_unsafe_masked[23], _rob_unsafe_masked_23_T_1
node _rob_unsafe_masked_24_T = or(rob_unsafe[24], rob_exception[24])
node _rob_unsafe_masked_24_T_1 = and(rob_val[24], _rob_unsafe_masked_24_T)
connect rob_unsafe_masked[24], _rob_unsafe_masked_24_T_1
node _rob_unsafe_masked_25_T = or(rob_unsafe[25], rob_exception[25])
node _rob_unsafe_masked_25_T_1 = and(rob_val[25], _rob_unsafe_masked_25_T)
connect rob_unsafe_masked[25], _rob_unsafe_masked_25_T_1
node _rob_unsafe_masked_26_T = or(rob_unsafe[26], rob_exception[26])
node _rob_unsafe_masked_26_T_1 = and(rob_val[26], _rob_unsafe_masked_26_T)
connect rob_unsafe_masked[26], _rob_unsafe_masked_26_T_1
node _rob_unsafe_masked_27_T = or(rob_unsafe[27], rob_exception[27])
node _rob_unsafe_masked_27_T_1 = and(rob_val[27], _rob_unsafe_masked_27_T)
connect rob_unsafe_masked[27], _rob_unsafe_masked_27_T_1
node _rob_unsafe_masked_28_T = or(rob_unsafe[28], rob_exception[28])
node _rob_unsafe_masked_28_T_1 = and(rob_val[28], _rob_unsafe_masked_28_T)
connect rob_unsafe_masked[28], _rob_unsafe_masked_28_T_1
node _rob_unsafe_masked_29_T = or(rob_unsafe[29], rob_exception[29])
node _rob_unsafe_masked_29_T_1 = and(rob_val[29], _rob_unsafe_masked_29_T)
connect rob_unsafe_masked[29], _rob_unsafe_masked_29_T_1
node _rob_unsafe_masked_30_T = or(rob_unsafe[30], rob_exception[30])
node _rob_unsafe_masked_30_T_1 = and(rob_val[30], _rob_unsafe_masked_30_T)
connect rob_unsafe_masked[30], _rob_unsafe_masked_30_T_1
node _rob_unsafe_masked_31_T = or(rob_unsafe[31], rob_exception[31])
node _rob_unsafe_masked_31_T_1 = and(rob_val[31], _rob_unsafe_masked_31_T)
connect rob_unsafe_masked[31], _rob_unsafe_masked_31_T_1
node _rob_pnr_unsafe_0_T = or(rob_unsafe[rob_pnr], rob_exception[rob_pnr])
node _rob_pnr_unsafe_0_T_1 = and(rob_val[rob_pnr], _rob_pnr_unsafe_0_T)
connect rob_pnr_unsafe[0], _rob_pnr_unsafe_0_T_1
when will_commit[0] :
connect rob_uop[rob_head].debug_inst, UInt<32>(0h4033)
else :
when rbk_row :
connect rob_uop[rob_tail].debug_inst, UInt<32>(0h4033)
node _T_128 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_129 = and(io.debug_wb_valids[0], _T_128)
when _T_129 :
infer mport MPORT_1 = rob_debug_wdata[io.wb_resps[0].bits.uop.rob_idx], clock
connect MPORT_1, io.debug_wb_wdata[0]
node _T_130 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_131 = and(io.wb_resps[0].valid, _T_130)
node _T_132 = eq(rob_val[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (0) occurred to an invalid ROB entry.\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_8
assert(clock, _T_134, UInt<1>(0h1), "") : assert_8
node _T_138 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_139 = and(io.wb_resps[0].valid, _T_138)
node _T_140 = eq(rob_bsy[io.wb_resps[0].bits.uop.rob_idx], UInt<1>(0h0))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(_T_141, UInt<1>(0h0))
node _T_143 = asUInt(reset)
node _T_144 = eq(_T_143, UInt<1>(0h0))
when _T_144 :
node _T_145 = eq(_T_142, UInt<1>(0h0))
when _T_145 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (0) occurred to a not-busy ROB entry.\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_9
assert(clock, _T_142, UInt<1>(0h1), "") : assert_9
node _T_146 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_147 = and(io.wb_resps[0].valid, _T_146)
node _T_148 = and(_T_147, rob_uop[io.wb_resps[0].bits.uop.rob_idx].ldst_val)
node _T_149 = neq(rob_uop[io.wb_resps[0].bits.uop.rob_idx].pdst, io.wb_resps[0].bits.uop.pdst)
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(_T_150, UInt<1>(0h0))
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (0) occurred to the wrong pdst.\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_10
assert(clock, _T_151, UInt<1>(0h1), "") : assert_10
node _T_155 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_156 = and(io.debug_wb_valids[1], _T_155)
when _T_156 :
infer mport MPORT_2 = rob_debug_wdata[io.wb_resps[1].bits.uop.rob_idx], clock
connect MPORT_2, io.debug_wb_wdata[1]
node _T_157 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_158 = and(io.wb_resps[1].valid, _T_157)
node _T_159 = eq(rob_val[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0))
node _T_160 = and(_T_158, _T_159)
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = asUInt(reset)
node _T_163 = eq(_T_162, UInt<1>(0h0))
when _T_163 :
node _T_164 = eq(_T_161, UInt<1>(0h0))
when _T_164 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (1) occurred to an invalid ROB entry.\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_11
assert(clock, _T_161, UInt<1>(0h1), "") : assert_11
node _T_165 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_166 = and(io.wb_resps[1].valid, _T_165)
node _T_167 = eq(rob_bsy[io.wb_resps[1].bits.uop.rob_idx], UInt<1>(0h0))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (1) occurred to a not-busy ROB entry.\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_12
assert(clock, _T_169, UInt<1>(0h1), "") : assert_12
node _T_173 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_174 = and(io.wb_resps[1].valid, _T_173)
node _T_175 = and(_T_174, rob_uop[io.wb_resps[1].bits.uop.rob_idx].ldst_val)
node _T_176 = neq(rob_uop[io.wb_resps[1].bits.uop.rob_idx].pdst, io.wb_resps[1].bits.uop.pdst)
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(_T_177, UInt<1>(0h0))
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_T_178, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (1) occurred to the wrong pdst.\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_13
assert(clock, _T_178, UInt<1>(0h1), "") : assert_13
node _T_182 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_183 = and(io.debug_wb_valids[2], _T_182)
when _T_183 :
infer mport MPORT_3 = rob_debug_wdata[io.wb_resps[2].bits.uop.rob_idx], clock
connect MPORT_3, io.debug_wb_wdata[2]
node _T_184 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_185 = and(io.wb_resps[2].valid, _T_184)
node _T_186 = eq(rob_val[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0))
node _T_187 = and(_T_185, _T_186)
node _T_188 = eq(_T_187, UInt<1>(0h0))
node _T_189 = asUInt(reset)
node _T_190 = eq(_T_189, UInt<1>(0h0))
when _T_190 :
node _T_191 = eq(_T_188, UInt<1>(0h0))
when _T_191 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (2) occurred to an invalid ROB entry.\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_14
assert(clock, _T_188, UInt<1>(0h1), "") : assert_14
node _T_192 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = and(io.wb_resps[2].valid, _T_192)
node _T_194 = eq(rob_bsy[io.wb_resps[2].bits.uop.rob_idx], UInt<1>(0h0))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(_T_195, UInt<1>(0h0))
node _T_197 = asUInt(reset)
node _T_198 = eq(_T_197, UInt<1>(0h0))
when _T_198 :
node _T_199 = eq(_T_196, UInt<1>(0h0))
when _T_199 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (2) occurred to a not-busy ROB entry.\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_15
assert(clock, _T_196, UInt<1>(0h1), "") : assert_15
node _T_200 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_201 = and(io.wb_resps[2].valid, _T_200)
node _T_202 = and(_T_201, rob_uop[io.wb_resps[2].bits.uop.rob_idx].ldst_val)
node _T_203 = neq(rob_uop[io.wb_resps[2].bits.uop.rob_idx].pdst, io.wb_resps[2].bits.uop.pdst)
node _T_204 = and(_T_202, _T_203)
node _T_205 = eq(_T_204, UInt<1>(0h0))
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(_T_205, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (2) occurred to the wrong pdst.\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_16
assert(clock, _T_205, UInt<1>(0h1), "") : assert_16
node _T_209 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = and(io.debug_wb_valids[3], _T_209)
when _T_210 :
infer mport MPORT_4 = rob_debug_wdata[io.wb_resps[3].bits.uop.rob_idx], clock
connect MPORT_4, io.debug_wb_wdata[3]
node _T_211 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = and(io.wb_resps[3].valid, _T_211)
node _T_213 = eq(rob_val[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(_T_214, UInt<1>(0h0))
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (3) occurred to an invalid ROB entry.\n at rob.scala:518 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_17
assert(clock, _T_215, UInt<1>(0h1), "") : assert_17
node _T_219 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_220 = and(io.wb_resps[3].valid, _T_219)
node _T_221 = eq(rob_bsy[io.wb_resps[3].bits.uop.rob_idx], UInt<1>(0h0))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(_T_222, UInt<1>(0h0))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (3) occurred to a not-busy ROB entry.\n at rob.scala:521 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_18
assert(clock, _T_223, UInt<1>(0h1), "") : assert_18
node _T_227 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_228 = and(io.wb_resps[3].valid, _T_227)
node _T_229 = and(_T_228, rob_uop[io.wb_resps[3].bits.uop.rob_idx].ldst_val)
node _T_230 = neq(rob_uop[io.wb_resps[3].bits.uop.rob_idx].pdst, io.wb_resps[3].bits.uop.pdst)
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] writeback (3) occurred to the wrong pdst.\n at rob.scala:524 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") : printf_19
assert(clock, _T_232, UInt<1>(0h1), "") : assert_19
infer mport io_commit_debug_wdata_0_MPORT = rob_debug_wdata[rob_head], clock
connect io.commit.debug_wdata[0], io_commit_debug_wdata_0_MPORT
node _block_commit_T = neq(rob_state, UInt<2>(0h1))
node _block_commit_T_1 = neq(rob_state, UInt<2>(0h3))
node _block_commit_T_2 = and(_block_commit_T, _block_commit_T_1)
reg block_commit_REG : UInt<1>, clock
connect block_commit_REG, exception_thrown
node _block_commit_T_3 = or(_block_commit_T_2, block_commit_REG)
reg block_commit_REG_1 : UInt<1>, clock
connect block_commit_REG_1, exception_thrown
reg block_commit_REG_2 : UInt<1>, clock
connect block_commit_REG_2, block_commit_REG_1
node block_commit = or(_block_commit_T_3, block_commit_REG_2)
node _T_236 = eq(block_commit, UInt<1>(0h0))
node _T_237 = and(can_throw_exception[0], _T_236)
node _T_238 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(_T_239, UInt<1>(0h0))
node _will_commit_0_T = eq(can_throw_exception[0], UInt<1>(0h0))
node _will_commit_0_T_1 = and(can_commit[0], _will_commit_0_T)
node _will_commit_0_T_2 = eq(block_commit, UInt<1>(0h0))
node _will_commit_0_T_3 = and(_will_commit_0_T_1, _will_commit_0_T_2)
connect will_commit[0], _will_commit_0_T_3
node _T_241 = eq(can_commit[0], UInt<1>(0h0))
node _T_242 = or(_T_241, can_throw_exception[0])
node _T_243 = and(rob_head_vals[0], _T_242)
node _T_244 = or(_T_243, block_commit)
connect exception_thrown, _T_240
node _is_mini_exception_T = eq(io.com_xcpt.bits.cause, UInt<5>(0h10))
node _is_mini_exception_T_1 = eq(io.com_xcpt.bits.cause, UInt<5>(0h11))
node is_mini_exception = or(_is_mini_exception_T, _is_mini_exception_T_1)
node _io_com_xcpt_valid_T = eq(is_mini_exception, UInt<1>(0h0))
node _io_com_xcpt_valid_T_1 = and(exception_thrown, _io_com_xcpt_valid_T)
connect io.com_xcpt.valid, _io_com_xcpt_valid_T_1
invalidate io.com_xcpt.bits.flush_typ
invalidate io.com_xcpt.bits.badvaddr
invalidate io.com_xcpt.bits.cause
invalidate io.com_xcpt.bits.pc_lob
invalidate io.com_xcpt.bits.is_rvc
invalidate io.com_xcpt.bits.edge_inst
invalidate io.com_xcpt.bits.ftq_idx
connect io.com_xcpt.bits.cause, r_xcpt_uop.exc_cause
node _io_com_xcpt_bits_badvaddr_T = bits(r_xcpt_badvaddr, 39, 39)
node _io_com_xcpt_bits_badvaddr_T_1 = mux(_io_com_xcpt_bits_badvaddr_T, UInt<24>(0hffffff), UInt<24>(0h0))
node _io_com_xcpt_bits_badvaddr_T_2 = cat(_io_com_xcpt_bits_badvaddr_T_1, r_xcpt_badvaddr)
connect io.com_xcpt.bits.badvaddr, _io_com_xcpt_bits_badvaddr_T_2
node insn_sys_pc2epc = and(rob_head_vals[0], io.commit.uops[0].is_sys_pc2epc)
node refetch_inst = or(exception_thrown, insn_sys_pc2epc)
connect io.com_xcpt.bits.ftq_idx, io.commit.uops[0].ftq_idx
connect io.com_xcpt.bits.edge_inst, io.commit.uops[0].edge_inst
connect io.com_xcpt.bits.is_rvc, io.commit.uops[0].is_rvc
connect io.com_xcpt.bits.pc_lob, io.commit.uops[0].pc_lob
node flush_commit_mask_0 = and(io.commit.valids[0], io.commit.uops[0].flush_on_commit)
node flush_val = or(exception_thrown, flush_commit_mask_0)
node _T_245 = gt(flush_commit_mask_0, UInt<1>(0h1))
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: [rob] Can't commit multiple flush_on_commit instructions on one cycle\n at rob.scala:580 assert(!(PopCount(flush_commit_mask) > 1.U),\n") : printf_20
assert(clock, _T_246, UInt<1>(0h1), "") : assert_20
node flush_uop = mux(exception_thrown, io.commit.uops[0], io.commit.uops[0])
connect io.flush.valid, flush_val
invalidate io.flush.bits.flush_typ
invalidate io.flush.bits.badvaddr
invalidate io.flush.bits.cause
invalidate io.flush.bits.pc_lob
invalidate io.flush.bits.is_rvc
invalidate io.flush.bits.edge_inst
invalidate io.flush.bits.ftq_idx
connect io.flush.bits.ftq_idx, flush_uop.ftq_idx
connect io.flush.bits.pc_lob, flush_uop.pc_lob
connect io.flush.bits.edge_inst, flush_uop.edge_inst
connect io.flush.bits.is_rvc, flush_uop.is_rvc
node _io_flush_bits_flush_typ_T = eq(is_mini_exception, UInt<1>(0h0))
node _io_flush_bits_flush_typ_T_1 = and(exception_thrown, _io_flush_bits_flush_typ_T)
node _io_flush_bits_flush_typ_T_2 = eq(flush_uop.uopc, UInt<7>(0h6a))
node _io_flush_bits_flush_typ_T_3 = and(flush_commit_mask_0, _io_flush_bits_flush_typ_T_2)
node _io_flush_bits_flush_typ_ret_T = eq(flush_val, UInt<1>(0h0))
node _io_flush_bits_flush_typ_ret_T_1 = mux(refetch_inst, UInt<2>(0h2), UInt<3>(0h4))
node _io_flush_bits_flush_typ_ret_T_2 = mux(_io_flush_bits_flush_typ_T_1, UInt<1>(0h1), _io_flush_bits_flush_typ_ret_T_1)
node _io_flush_bits_flush_typ_ret_T_3 = mux(_io_flush_bits_flush_typ_T_3, UInt<2>(0h3), _io_flush_bits_flush_typ_ret_T_2)
node io_flush_bits_flush_typ_ret = mux(_io_flush_bits_flush_typ_ret_T, UInt<1>(0h0), _io_flush_bits_flush_typ_ret_T_3)
connect io.flush.bits.flush_typ, io_flush_bits_flush_typ_ret
wire fflags_val : UInt<1>[1]
wire fflags : UInt<5>[1]
node _fflags_val_0_T = and(io.commit.valids[0], io.commit.uops[0].fp_val)
node _fflags_val_0_T_1 = eq(io.commit.uops[0].uses_stq, UInt<1>(0h0))
node _fflags_val_0_T_2 = and(_fflags_val_0_T, _fflags_val_0_T_1)
connect fflags_val[0], _fflags_val_0_T_2
node _fflags_0_T = mux(fflags_val[0], rob_head_fflags[0], UInt<1>(0h0))
connect fflags[0], _fflags_0_T
node _T_250 = eq(io.commit.uops[0].fp_val, UInt<1>(0h0))
node _T_251 = and(io.commit.valids[0], _T_250)
node _T_252 = neq(rob_head_fflags[0], UInt<1>(0h0))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: Committed non-FP instruction has non-zero fflag bits.\n at rob.scala:613 assert (!(io.commit.valids(w) &&\n") : printf_21
assert(clock, _T_254, UInt<1>(0h1), "") : assert_21
node _T_258 = and(io.commit.valids[0], io.commit.uops[0].fp_val)
node _T_259 = or(io.commit.uops[0].uses_ldq, io.commit.uops[0].uses_stq)
node _T_260 = and(_T_258, _T_259)
node _T_261 = neq(rob_head_fflags[0], UInt<1>(0h0))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(_T_262, UInt<1>(0h0))
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: Committed FP load or store has non-zero fflag bits.\n at rob.scala:617 assert (!(io.commit.valids(w) &&\n") : printf_22
assert(clock, _T_263, UInt<1>(0h1), "") : assert_22
connect io.commit.fflags.valid, fflags_val[0]
connect io.commit.fflags.bits, fflags[0]
wire next_xcpt_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect next_xcpt_uop, r_xcpt_uop
wire enq_xcpts : UInt<1>[1]
node _enq_xcpts_0_T = and(io.enq_valids[0], io.enq_uops[0].exception)
connect enq_xcpts[0], _enq_xcpts_0_T
node _T_267 = or(io.flush.valid, exception_thrown)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = neq(rob_state, UInt<2>(0h2))
node _T_270 = and(_T_268, _T_269)
when _T_270 :
node new_xcpt_valid = or(io.lxcpt.valid, io.csr_replay.valid)
node _lxcpt_older_T = eq(io.csr_replay.valid, UInt<1>(0h0))
node _lxcpt_older_T_1 = lt(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx)
node _lxcpt_older_T_2 = lt(io.lxcpt.bits.uop.rob_idx, rob_head)
node _lxcpt_older_T_3 = xor(_lxcpt_older_T_1, _lxcpt_older_T_2)
node _lxcpt_older_T_4 = lt(io.csr_replay.bits.uop.rob_idx, rob_head)
node _lxcpt_older_T_5 = xor(_lxcpt_older_T_3, _lxcpt_older_T_4)
node _lxcpt_older_T_6 = and(_lxcpt_older_T_5, io.lxcpt.valid)
node lxcpt_older = or(_lxcpt_older_T, _lxcpt_older_T_6)
node new_xcpt = mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)
when new_xcpt_valid :
node _T_271 = eq(r_xcpt_val, UInt<1>(0h0))
node _T_272 = lt(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx)
node _T_273 = lt(new_xcpt.uop.rob_idx, rob_head)
node _T_274 = xor(_T_272, _T_273)
node _T_275 = lt(r_xcpt_uop.rob_idx, rob_head)
node _T_276 = xor(_T_274, _T_275)
node _T_277 = or(_T_271, _T_276)
when _T_277 :
connect r_xcpt_val, UInt<1>(0h1)
connect next_xcpt_uop, new_xcpt.uop
connect next_xcpt_uop.exc_cause, new_xcpt.cause
connect r_xcpt_badvaddr, new_xcpt.badvaddr
else :
node _T_278 = eq(r_xcpt_val, UInt<1>(0h0))
node _T_279 = and(_T_278, enq_xcpts[0])
when _T_279 :
connect r_xcpt_val, UInt<1>(0h1)
connect next_xcpt_uop, io.enq_uops[0]
node _r_xcpt_badvaddr_T = not(io.xcpt_fetch_pc)
node _r_xcpt_badvaddr_T_1 = or(_r_xcpt_badvaddr_T, UInt<6>(0h3f))
node _r_xcpt_badvaddr_T_2 = not(_r_xcpt_badvaddr_T_1)
node _r_xcpt_badvaddr_T_3 = or(_r_xcpt_badvaddr_T_2, io.enq_uops[0].pc_lob)
connect r_xcpt_badvaddr, _r_xcpt_badvaddr_T_3
connect r_xcpt_uop, next_xcpt_uop
node _r_xcpt_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_xcpt_uop_br_mask_T_1 = and(next_xcpt_uop.br_mask, _r_xcpt_uop_br_mask_T)
connect r_xcpt_uop.br_mask, _r_xcpt_uop_br_mask_T_1
node _T_280 = and(io.brupdate.b1.mispredict_mask, next_xcpt_uop.br_mask)
node _T_281 = neq(_T_280, UInt<1>(0h0))
node _T_282 = or(io.flush.valid, _T_281)
when _T_282 :
connect r_xcpt_val, UInt<1>(0h0)
node _T_283 = eq(r_xcpt_val, UInt<1>(0h0))
node _T_284 = and(exception_thrown, _T_283)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: ROB trying to throw an exception, but it doesn't have a valid xcpt_cause\n at rob.scala:667 assert (!(exception_thrown && !r_xcpt_val),\n") : printf_23
assert(clock, _T_285, UInt<1>(0h1), "") : assert_23
node _T_289 = and(empty, r_xcpt_val)
node _T_290 = eq(_T_289, UInt<1>(0h0))
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: ROB is empty, but believes it has an outstanding exception.\n at rob.scala:670 assert (!(empty && r_xcpt_val),\n") : printf_24
assert(clock, _T_290, UInt<1>(0h1), "") : assert_24
node _T_294 = neq(r_xcpt_uop.rob_idx, rob_head)
node _T_295 = and(_T_240, _T_294)
node _T_296 = eq(_T_295, UInt<1>(0h0))
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: ROB is throwing an exception, but the stored exception information's rob_idx does not match the rob_head\n at rob.scala:673 assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),\n") : printf_25
assert(clock, _T_296, UInt<1>(0h1), "") : assert_25
wire rob_deq : UInt<1>
connect rob_deq, UInt<1>(0h0)
regreset r_partial_row : UInt<1>, clock, reset, UInt<1>(0h0)
when io.enq_valids[0] :
connect r_partial_row, io.enq_partial_stall
node _finished_committing_row_T = neq(io.commit.valids[0], UInt<1>(0h0))
node _finished_committing_row_T_1 = xor(will_commit[0], rob_head_vals[0])
node _finished_committing_row_T_2 = eq(_finished_committing_row_T_1, UInt<1>(0h0))
node _finished_committing_row_T_3 = and(_finished_committing_row_T, _finished_committing_row_T_2)
node _finished_committing_row_T_4 = eq(rob_head, rob_tail)
node _finished_committing_row_T_5 = and(r_partial_row, _finished_committing_row_T_4)
node _finished_committing_row_T_6 = eq(maybe_full, UInt<1>(0h0))
node _finished_committing_row_T_7 = and(_finished_committing_row_T_5, _finished_committing_row_T_6)
node _finished_committing_row_T_8 = eq(_finished_committing_row_T_7, UInt<1>(0h0))
node finished_committing_row = and(_finished_committing_row_T_3, _finished_committing_row_T_8)
when finished_committing_row :
node _rob_head_T = add(rob_head, UInt<1>(0h1))
node _rob_head_T_1 = tail(_rob_head_T, 1)
node _rob_head_T_2 = bits(_rob_head_T_1, 4, 0)
connect rob_head, _rob_head_T_2
connect rob_head_lsb, UInt<1>(0h0)
connect rob_deq, UInt<1>(0h1)
else :
node _rob_head_lsb_T = bits(rob_head_vals[0], 0, 0)
node _rob_head_lsb_T_1 = mux(_rob_head_lsb_T, UInt<1>(0h1), UInt<1>(0h0))
connect rob_head_lsb, UInt<1>(0h0)
regreset pnr_maybe_at_tail : UInt<1>, clock, reset, UInt<1>(0h0)
node _safe_to_inc_T = eq(rob_state, UInt<2>(0h1))
node _safe_to_inc_T_1 = eq(rob_state, UInt<2>(0h3))
node safe_to_inc = or(_safe_to_inc_T, _safe_to_inc_T_1)
node _do_inc_row_T = eq(rob_pnr_unsafe[0], UInt<1>(0h0))
node _do_inc_row_T_1 = neq(rob_pnr, rob_tail)
node _do_inc_row_T_2 = eq(pnr_maybe_at_tail, UInt<1>(0h0))
node _do_inc_row_T_3 = and(full, _do_inc_row_T_2)
node _do_inc_row_T_4 = or(_do_inc_row_T_1, _do_inc_row_T_3)
node do_inc_row = and(_do_inc_row_T, _do_inc_row_T_4)
node _T_300 = neq(io.enq_valids[0], UInt<1>(0h0))
node _T_301 = and(empty, _T_300)
when _T_301 :
connect rob_pnr, rob_head
connect rob_pnr_lsb, UInt<1>(0h0)
else :
node _T_302 = and(safe_to_inc, do_inc_row)
when _T_302 :
node _rob_pnr_T = add(rob_pnr, UInt<1>(0h1))
node _rob_pnr_T_1 = tail(_rob_pnr_T, 1)
node _rob_pnr_T_2 = bits(_rob_pnr_T_1, 4, 0)
connect rob_pnr, _rob_pnr_T_2
connect rob_pnr_lsb, UInt<1>(0h0)
else :
node _T_303 = neq(rob_pnr, rob_tail)
node _T_304 = eq(pnr_maybe_at_tail, UInt<1>(0h0))
node _T_305 = and(full, _T_304)
node _T_306 = or(_T_303, _T_305)
node _T_307 = and(safe_to_inc, _T_306)
when _T_307 :
connect rob_pnr_lsb, UInt<1>(0h0)
else :
node _T_308 = eq(full, UInt<1>(0h0))
node _T_309 = and(safe_to_inc, _T_308)
node _T_310 = eq(empty, UInt<1>(0h0))
node _T_311 = and(_T_309, _T_310)
when _T_311 :
node _rob_pnr_lsb_T = dshr(rob_tail_vals[0], UInt<1>(0h0))
node _rob_pnr_lsb_T_1 = not(_rob_pnr_lsb_T)
node _rob_pnr_lsb_T_2 = or(rob_pnr_unsafe[0], _rob_pnr_lsb_T_1)
node _rob_pnr_lsb_T_3 = bits(_rob_pnr_lsb_T_2, 0, 0)
connect rob_pnr_lsb, UInt<1>(0h0)
else :
node _T_312 = and(full, pnr_maybe_at_tail)
when _T_312 :
connect rob_pnr_lsb, UInt<1>(0h0)
node _pnr_maybe_at_tail_T = eq(rob_deq, UInt<1>(0h0))
node _pnr_maybe_at_tail_T_1 = or(do_inc_row, pnr_maybe_at_tail)
node _pnr_maybe_at_tail_T_2 = and(_pnr_maybe_at_tail_T, _pnr_maybe_at_tail_T_1)
connect pnr_maybe_at_tail, _pnr_maybe_at_tail_T_2
node _T_313 = lt(rob_pnr, rob_head)
node _T_314 = lt(rob_pnr, rob_tail)
node _T_315 = xor(_T_313, _T_314)
node _T_316 = lt(rob_head, rob_tail)
node _T_317 = xor(_T_315, _T_316)
node _T_318 = eq(_T_317, UInt<1>(0h0))
node _T_319 = eq(rob_pnr, rob_tail)
node _T_320 = or(_T_318, _T_319)
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_T_320, UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at rob.scala:749 assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)\n") : printf_26
assert(clock, _T_320, UInt<1>(0h1), "") : assert_26
node _T_324 = lt(rob_tail, rob_pnr)
node _T_325 = lt(rob_tail, rob_head)
node _T_326 = xor(_T_324, _T_325)
node _T_327 = lt(rob_pnr, rob_head)
node _T_328 = xor(_T_326, _T_327)
node _T_329 = eq(_T_328, UInt<1>(0h0))
node _T_330 = or(_T_329, full)
node _T_331 = asUInt(reset)
node _T_332 = eq(_T_331, UInt<1>(0h0))
when _T_332 :
node _T_333 = eq(_T_330, UInt<1>(0h0))
when _T_333 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at rob.scala:752 assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)\n") : printf_27
assert(clock, _T_330, UInt<1>(0h1), "") : assert_27
wire rob_enq : UInt<1>
connect rob_enq, UInt<1>(0h0)
node _T_334 = eq(rob_state, UInt<2>(0h2))
node _T_335 = neq(rob_tail, rob_head)
node _T_336 = or(_T_335, maybe_full)
node _T_337 = and(_T_334, _T_336)
when _T_337 :
node _rob_tail_T = sub(rob_tail, UInt<1>(0h1))
node _rob_tail_T_1 = tail(_rob_tail_T, 1)
node _rob_tail_T_2 = bits(_rob_tail_T_1, 4, 0)
connect rob_tail, _rob_tail_T_2
connect rob_tail_lsb, UInt<1>(0h0)
connect rob_deq, UInt<1>(0h1)
else :
node _T_338 = eq(rob_state, UInt<2>(0h2))
node _T_339 = eq(rob_tail, rob_head)
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(maybe_full, UInt<1>(0h0))
node _T_342 = and(_T_340, _T_341)
when _T_342 :
connect rob_tail_lsb, rob_head_lsb
else :
when io.brupdate.b2.mispredict :
node _rob_tail_T_3 = add(io.brupdate.b2.uop.rob_idx, UInt<1>(0h1))
node _rob_tail_T_4 = tail(_rob_tail_T_3, 1)
node _rob_tail_T_5 = bits(_rob_tail_T_4, 4, 0)
connect rob_tail, _rob_tail_T_5
connect rob_tail_lsb, UInt<1>(0h0)
else :
node _T_343 = neq(io.enq_valids[0], UInt<1>(0h0))
node _T_344 = eq(io.enq_partial_stall, UInt<1>(0h0))
node _T_345 = and(_T_343, _T_344)
when _T_345 :
node _rob_tail_T_6 = add(rob_tail, UInt<1>(0h1))
node _rob_tail_T_7 = tail(_rob_tail_T_6, 1)
node _rob_tail_T_8 = bits(_rob_tail_T_7, 4, 0)
connect rob_tail, _rob_tail_T_8
connect rob_tail_lsb, UInt<1>(0h0)
connect rob_enq, UInt<1>(0h1)
else :
node _T_346 = neq(io.enq_valids[0], UInt<1>(0h0))
node _T_347 = and(_T_346, io.enq_partial_stall)
when _T_347 :
node _rob_tail_lsb_T = dshr(io.enq_valids[0], UInt<1>(0h0))
node _rob_tail_lsb_T_1 = not(_rob_tail_lsb_T)
node _rob_tail_lsb_T_2 = bits(_rob_tail_lsb_T_1, 0, 0)
connect rob_tail_lsb, UInt<1>(0h0)
node _maybe_full_T = eq(rob_deq, UInt<1>(0h0))
node _maybe_full_T_1 = or(rob_enq, maybe_full)
node _maybe_full_T_2 = and(_maybe_full_T, _maybe_full_T_1)
node _maybe_full_T_3 = neq(io.brupdate.b1.mispredict_mask, UInt<1>(0h0))
node _maybe_full_T_4 = or(_maybe_full_T_2, _maybe_full_T_3)
connect maybe_full, _maybe_full_T_4
node _full_T = eq(rob_tail, rob_head)
node _full_T_1 = and(_full_T, maybe_full)
connect full, _full_T_1
node _empty_T = eq(rob_head, rob_tail)
node _empty_T_1 = eq(rob_head_vals[0], UInt<1>(0h0))
node _empty_T_2 = and(_empty_T, _empty_T_1)
connect empty, _empty_T_2
connect io.rob_head_idx, rob_head
connect io.rob_tail_idx, rob_tail
connect io.rob_pnr_idx, rob_pnr
connect io.empty, empty
node _io_ready_T = eq(rob_state, UInt<2>(0h1))
node _io_ready_T_1 = eq(full, UInt<1>(0h0))
node _io_ready_T_2 = and(_io_ready_T, _io_ready_T_1)
node _io_ready_T_3 = eq(r_xcpt_val, UInt<1>(0h0))
node _io_ready_T_4 = and(_io_ready_T_2, _io_ready_T_3)
connect io.ready, _io_ready_T_4
node _T_348 = eq(UInt<2>(0h0), rob_state)
when _T_348 :
connect rob_state, UInt<2>(0h1)
else :
node _T_349 = eq(UInt<2>(0h1), rob_state)
when _T_349 :
reg REG : UInt<1>, clock
connect REG, exception_thrown
reg REG_1 : UInt<1>, clock
connect REG_1, REG
when REG_1 :
connect rob_state, UInt<2>(0h2)
else :
node _T_350 = and(io.enq_valids[0], io.enq_uops[0].is_unique)
when _T_350 :
connect rob_state, UInt<2>(0h3)
else :
node _T_351 = eq(UInt<2>(0h2), rob_state)
when _T_351 :
when empty :
connect rob_state, UInt<2>(0h1)
else :
node _T_352 = eq(UInt<2>(0h3), rob_state)
when _T_352 :
reg REG_2 : UInt<1>, clock
connect REG_2, exception_thrown
when REG_2 :
connect rob_state, UInt<2>(0h2)
else :
when empty :
connect rob_state, UInt<2>(0h1)
node _io_com_load_is_at_rob_head_T = bits(rob_head_vals[0], 0, 0)
node _io_com_load_is_at_rob_head_T_1 = eq(will_commit[0], UInt<1>(0h0))
node _io_com_load_is_at_rob_head_T_2 = and(rob_head_uses_ldq[0], _io_com_load_is_at_rob_head_T_1)
reg io_com_load_is_at_rob_head_REG : UInt<1>, clock
connect io_com_load_is_at_rob_head_REG, _io_com_load_is_at_rob_head_T_2
connect io.com_load_is_at_rob_head, io_com_load_is_at_rob_head_REG | module Rob( // @[rob.scala:211:7]
input clock, // @[rob.scala:211:7]
input reset, // @[rob.scala:211:7]
input io_enq_valids_0, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_uopc, // @[rob.scala:216:14]
input [31:0] io_enq_uops_0_inst, // @[rob.scala:216:14]
input [31:0] io_enq_uops_0_debug_inst, // @[rob.scala:216:14]
input io_enq_uops_0_is_rvc, // @[rob.scala:216:14]
input [39:0] io_enq_uops_0_debug_pc, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_iq_type, // @[rob.scala:216:14]
input [9:0] io_enq_uops_0_fu_code, // @[rob.scala:216:14]
input [3:0] io_enq_uops_0_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_ctrl_op_fcn, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_is_load, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_is_sta, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_iw_state, // @[rob.scala:216:14]
input io_enq_uops_0_iw_p1_poisoned, // @[rob.scala:216:14]
input io_enq_uops_0_iw_p2_poisoned, // @[rob.scala:216:14]
input io_enq_uops_0_is_br, // @[rob.scala:216:14]
input io_enq_uops_0_is_jalr, // @[rob.scala:216:14]
input io_enq_uops_0_is_jal, // @[rob.scala:216:14]
input io_enq_uops_0_is_sfb, // @[rob.scala:216:14]
input [7:0] io_enq_uops_0_br_mask, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_br_tag, // @[rob.scala:216:14]
input [3:0] io_enq_uops_0_ftq_idx, // @[rob.scala:216:14]
input io_enq_uops_0_edge_inst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_pc_lob, // @[rob.scala:216:14]
input io_enq_uops_0_taken, // @[rob.scala:216:14]
input [19:0] io_enq_uops_0_imm_packed, // @[rob.scala:216:14]
input [11:0] io_enq_uops_0_csr_addr, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_rob_idx, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_stq_idx, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_pdst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_prs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_prs2, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_prs3, // @[rob.scala:216:14]
input io_enq_uops_0_prs1_busy, // @[rob.scala:216:14]
input io_enq_uops_0_prs2_busy, // @[rob.scala:216:14]
input io_enq_uops_0_prs3_busy, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_stale_pdst, // @[rob.scala:216:14]
input io_enq_uops_0_exception, // @[rob.scala:216:14]
input [63:0] io_enq_uops_0_exc_cause, // @[rob.scala:216:14]
input io_enq_uops_0_bypassable, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_mem_size, // @[rob.scala:216:14]
input io_enq_uops_0_mem_signed, // @[rob.scala:216:14]
input io_enq_uops_0_is_fence, // @[rob.scala:216:14]
input io_enq_uops_0_is_fencei, // @[rob.scala:216:14]
input io_enq_uops_0_is_amo, // @[rob.scala:216:14]
input io_enq_uops_0_uses_ldq, // @[rob.scala:216:14]
input io_enq_uops_0_uses_stq, // @[rob.scala:216:14]
input io_enq_uops_0_is_sys_pc2epc, // @[rob.scala:216:14]
input io_enq_uops_0_is_unique, // @[rob.scala:216:14]
input io_enq_uops_0_flush_on_commit, // @[rob.scala:216:14]
input io_enq_uops_0_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_ldst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_lrs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_lrs2, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_lrs3, // @[rob.scala:216:14]
input io_enq_uops_0_ldst_val, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_lrs2_rtype, // @[rob.scala:216:14]
input io_enq_uops_0_frs3_en, // @[rob.scala:216:14]
input io_enq_uops_0_fp_val, // @[rob.scala:216:14]
input io_enq_uops_0_fp_single, // @[rob.scala:216:14]
input io_enq_uops_0_xcpt_pf_if, // @[rob.scala:216:14]
input io_enq_uops_0_xcpt_ae_if, // @[rob.scala:216:14]
input io_enq_uops_0_xcpt_ma_if, // @[rob.scala:216:14]
input io_enq_uops_0_bp_debug_if, // @[rob.scala:216:14]
input io_enq_uops_0_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_debug_tsrc, // @[rob.scala:216:14]
input io_enq_partial_stall, // @[rob.scala:216:14]
input [39:0] io_xcpt_fetch_pc, // @[rob.scala:216:14]
output [4:0] io_rob_tail_idx, // @[rob.scala:216:14]
output [4:0] io_rob_pnr_idx, // @[rob.scala:216:14]
output [4:0] io_rob_head_idx, // @[rob.scala:216:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[rob.scala:216:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rob.scala:216:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[rob.scala:216:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_br, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_jalr, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_jal, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[rob.scala:216:14]
input io_brupdate_b2_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rob.scala:216:14]
input io_brupdate_b2_uop_taken, // @[rob.scala:216:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[rob.scala:216:14]
input io_brupdate_b2_uop_prs1_busy, // @[rob.scala:216:14]
input io_brupdate_b2_uop_prs2_busy, // @[rob.scala:216:14]
input io_brupdate_b2_uop_prs3_busy, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[rob.scala:216:14]
input io_brupdate_b2_uop_exception, // @[rob.scala:216:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rob.scala:216:14]
input io_brupdate_b2_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rob.scala:216:14]
input io_brupdate_b2_uop_mem_signed, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_fence, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_fencei, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_amo, // @[rob.scala:216:14]
input io_brupdate_b2_uop_uses_ldq, // @[rob.scala:216:14]
input io_brupdate_b2_uop_uses_stq, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_unique, // @[rob.scala:216:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_brupdate_b2_uop_frs3_en, // @[rob.scala:216:14]
input io_brupdate_b2_uop_fp_val, // @[rob.scala:216:14]
input io_brupdate_b2_uop_fp_single, // @[rob.scala:216:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rob.scala:216:14]
input io_brupdate_b2_valid, // @[rob.scala:216:14]
input io_brupdate_b2_mispredict, // @[rob.scala:216:14]
input io_brupdate_b2_taken, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rob.scala:216:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rob.scala:216:14]
input [20:0] io_brupdate_b2_target_offset, // @[rob.scala:216:14]
input io_wb_resps_0_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_0_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_0_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_wb_resps_0_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_0_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_0_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_0_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_0_bits_data, // @[rob.scala:216:14]
input io_wb_resps_0_bits_predicated, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_fflags_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_fflags_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_0_bits_fflags_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_0_bits_fflags_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_wb_resps_0_bits_fflags_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_fflags_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_0_bits_fflags_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_0_bits_fflags_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_fflags_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_0_bits_fflags_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_flags, // @[rob.scala:216:14]
input io_wb_resps_1_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_1_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_1_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_1_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_1_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_1_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_wb_resps_1_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_wb_resps_1_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_1_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_1_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_wb_resps_1_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_1_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_1_bits_data, // @[rob.scala:216:14]
input io_wb_resps_2_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_2_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_2_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_2_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_2_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_wb_resps_2_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_2_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_2_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_2_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_2_bits_data, // @[rob.scala:216:14]
input io_wb_resps_2_bits_predicated, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_fflags_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_2_bits_fflags_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_2_bits_fflags_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_2_bits_fflags_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_fflags_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_2_bits_fflags_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_wb_resps_2_bits_fflags_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_fflags_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_fflags_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_2_bits_fflags_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_2_bits_fflags_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_fflags_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_fflags_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_fflags_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_fflags_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_2_bits_fflags_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_fflags_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_fflags_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_fflags_bits_flags, // @[rob.scala:216:14]
input io_wb_resps_3_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_3_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_3_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_3_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_3_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_wb_resps_3_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_3_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_3_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_3_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_3_bits_data, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_fflags_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_3_bits_fflags_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_3_bits_fflags_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_3_bits_fflags_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_fflags_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_3_bits_fflags_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_wb_resps_3_bits_fflags_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_fflags_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_fflags_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_3_bits_fflags_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_3_bits_fflags_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_fflags_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_fflags_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_fflags_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_fflags_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_3_bits_fflags_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_fflags_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_fflags_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_fflags_bits_flags, // @[rob.scala:216:14]
input io_lsu_clr_bsy_0_valid, // @[rob.scala:216:14]
input [4:0] io_lsu_clr_bsy_0_bits, // @[rob.scala:216:14]
input io_lsu_clr_bsy_1_valid, // @[rob.scala:216:14]
input [4:0] io_lsu_clr_bsy_1_bits, // @[rob.scala:216:14]
input [4:0] io_lsu_clr_unsafe_0_bits, // @[rob.scala:216:14]
input io_debug_wb_valids_0, // @[rob.scala:216:14]
input io_debug_wb_valids_1, // @[rob.scala:216:14]
input io_debug_wb_valids_2, // @[rob.scala:216:14]
input io_debug_wb_valids_3, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_0, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_1, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_2, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_3, // @[rob.scala:216:14]
input io_fflags_0_valid, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_fflags_0_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_fflags_0_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_fflags_0_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_fflags_0_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_fflags_0_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_iw_state, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_br, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_jal, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_fflags_0_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_fflags_0_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_fflags_0_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_fflags_0_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_fflags_0_bits_uop_ppred, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_fflags_0_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_mem_size, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_fence, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_amo, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_unique, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_lrs3, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_fp_val, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_fp_single, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_flags, // @[rob.scala:216:14]
input io_fflags_1_valid, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_fflags_1_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_fflags_1_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_fflags_1_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_fflags_1_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_fflags_1_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_iw_state, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_br, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_jal, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_fflags_1_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_fflags_1_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_fflags_1_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_fflags_1_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_fflags_1_bits_uop_ppred, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_fflags_1_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_mem_size, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_fence, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_amo, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_unique, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_lrs3, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_fp_val, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_fp_single, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_flags, // @[rob.scala:216:14]
input io_lxcpt_valid, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_lxcpt_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_lxcpt_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_lxcpt_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_lxcpt_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_lxcpt_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_iw_state, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_br, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_jal, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_lxcpt_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_lxcpt_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_lxcpt_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_lxcpt_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_lxcpt_bits_uop_ppred, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_lxcpt_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_mem_size, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_fence, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_amo, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_unique, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_lrs3, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_fp_val, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_fp_single, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_cause, // @[rob.scala:216:14]
input [39:0] io_lxcpt_bits_badvaddr, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_csr_replay_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_csr_replay_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_csr_replay_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_csr_replay_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_csr_replay_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_iw_state, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_br, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_jal, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_sfb, // @[rob.scala:216:14]
input [7:0] io_csr_replay_bits_uop_br_mask, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_br_tag, // @[rob.scala:216:14]
input [3:0] io_csr_replay_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_csr_replay_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_csr_replay_bits_uop_csr_addr, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_rob_idx, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_pdst, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_prs1, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_prs2, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_prs3, // @[rob.scala:216:14]
input [3:0] io_csr_replay_bits_uop_ppred, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_csr_replay_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_mem_size, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_fence, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_amo, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_unique, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_lrs3, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_fp_val, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_fp_single, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_debug_tsrc, // @[rob.scala:216:14]
output io_commit_valids_0, // @[rob.scala:216:14]
output io_commit_arch_valids_0, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_uopc, // @[rob.scala:216:14]
output [31:0] io_commit_uops_0_inst, // @[rob.scala:216:14]
output [31:0] io_commit_uops_0_debug_inst, // @[rob.scala:216:14]
output io_commit_uops_0_is_rvc, // @[rob.scala:216:14]
output [39:0] io_commit_uops_0_debug_pc, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_iq_type, // @[rob.scala:216:14]
output [9:0] io_commit_uops_0_fu_code, // @[rob.scala:216:14]
output [3:0] io_commit_uops_0_ctrl_br_type, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_ctrl_op1_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_ctrl_op2_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_ctrl_imm_sel, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_ctrl_op_fcn, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_fcn_dw, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_ctrl_csr_cmd, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_is_load, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_is_sta, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_is_std, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_iw_state, // @[rob.scala:216:14]
output io_commit_uops_0_iw_p1_poisoned, // @[rob.scala:216:14]
output io_commit_uops_0_iw_p2_poisoned, // @[rob.scala:216:14]
output io_commit_uops_0_is_br, // @[rob.scala:216:14]
output io_commit_uops_0_is_jalr, // @[rob.scala:216:14]
output io_commit_uops_0_is_jal, // @[rob.scala:216:14]
output io_commit_uops_0_is_sfb, // @[rob.scala:216:14]
output [7:0] io_commit_uops_0_br_mask, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_br_tag, // @[rob.scala:216:14]
output [3:0] io_commit_uops_0_ftq_idx, // @[rob.scala:216:14]
output io_commit_uops_0_edge_inst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_pc_lob, // @[rob.scala:216:14]
output io_commit_uops_0_taken, // @[rob.scala:216:14]
output [19:0] io_commit_uops_0_imm_packed, // @[rob.scala:216:14]
output [11:0] io_commit_uops_0_csr_addr, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_rob_idx, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_ldq_idx, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_stq_idx, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_rxq_idx, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_pdst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_prs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_prs2, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_prs3, // @[rob.scala:216:14]
output [3:0] io_commit_uops_0_ppred, // @[rob.scala:216:14]
output io_commit_uops_0_prs1_busy, // @[rob.scala:216:14]
output io_commit_uops_0_prs2_busy, // @[rob.scala:216:14]
output io_commit_uops_0_prs3_busy, // @[rob.scala:216:14]
output io_commit_uops_0_ppred_busy, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_stale_pdst, // @[rob.scala:216:14]
output io_commit_uops_0_exception, // @[rob.scala:216:14]
output [63:0] io_commit_uops_0_exc_cause, // @[rob.scala:216:14]
output io_commit_uops_0_bypassable, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_mem_cmd, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_mem_size, // @[rob.scala:216:14]
output io_commit_uops_0_mem_signed, // @[rob.scala:216:14]
output io_commit_uops_0_is_fence, // @[rob.scala:216:14]
output io_commit_uops_0_is_fencei, // @[rob.scala:216:14]
output io_commit_uops_0_is_amo, // @[rob.scala:216:14]
output io_commit_uops_0_uses_ldq, // @[rob.scala:216:14]
output io_commit_uops_0_uses_stq, // @[rob.scala:216:14]
output io_commit_uops_0_is_sys_pc2epc, // @[rob.scala:216:14]
output io_commit_uops_0_is_unique, // @[rob.scala:216:14]
output io_commit_uops_0_flush_on_commit, // @[rob.scala:216:14]
output io_commit_uops_0_ldst_is_rs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_ldst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_lrs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_lrs2, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_lrs3, // @[rob.scala:216:14]
output io_commit_uops_0_ldst_val, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_dst_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_lrs1_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_lrs2_rtype, // @[rob.scala:216:14]
output io_commit_uops_0_frs3_en, // @[rob.scala:216:14]
output io_commit_uops_0_fp_val, // @[rob.scala:216:14]
output io_commit_uops_0_fp_single, // @[rob.scala:216:14]
output io_commit_uops_0_xcpt_pf_if, // @[rob.scala:216:14]
output io_commit_uops_0_xcpt_ae_if, // @[rob.scala:216:14]
output io_commit_uops_0_xcpt_ma_if, // @[rob.scala:216:14]
output io_commit_uops_0_bp_debug_if, // @[rob.scala:216:14]
output io_commit_uops_0_bp_xcpt_if, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_debug_fsrc, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_debug_tsrc, // @[rob.scala:216:14]
output io_commit_fflags_valid, // @[rob.scala:216:14]
output [4:0] io_commit_fflags_bits, // @[rob.scala:216:14]
output [31:0] io_commit_debug_insts_0, // @[rob.scala:216:14]
output io_commit_rbk_valids_0, // @[rob.scala:216:14]
output io_commit_rollback, // @[rob.scala:216:14]
output [63:0] io_commit_debug_wdata_0, // @[rob.scala:216:14]
output io_com_load_is_at_rob_head, // @[rob.scala:216:14]
output io_com_xcpt_valid, // @[rob.scala:216:14]
output [3:0] io_com_xcpt_bits_ftq_idx, // @[rob.scala:216:14]
output io_com_xcpt_bits_edge_inst, // @[rob.scala:216:14]
output [5:0] io_com_xcpt_bits_pc_lob, // @[rob.scala:216:14]
output [63:0] io_com_xcpt_bits_cause, // @[rob.scala:216:14]
output [63:0] io_com_xcpt_bits_badvaddr, // @[rob.scala:216:14]
input io_csr_stall, // @[rob.scala:216:14]
output io_flush_valid, // @[rob.scala:216:14]
output [3:0] io_flush_bits_ftq_idx, // @[rob.scala:216:14]
output io_flush_bits_edge_inst, // @[rob.scala:216:14]
output io_flush_bits_is_rvc, // @[rob.scala:216:14]
output [5:0] io_flush_bits_pc_lob, // @[rob.scala:216:14]
output [2:0] io_flush_bits_flush_typ, // @[rob.scala:216:14]
output io_empty, // @[rob.scala:216:14]
output io_ready, // @[rob.scala:216:14]
output io_flush_frontend, // @[rob.scala:216:14]
input [63:0] io_debug_tsc // @[rob.scala:216:14]
);
wire [1:0] io_commit_uops_0_debug_tsrc_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_debug_fsrc_0; // @[rob.scala:211:7]
wire io_commit_uops_0_bp_xcpt_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_bp_debug_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_xcpt_ma_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_xcpt_ae_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_xcpt_pf_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_fp_single_0; // @[rob.scala:211:7]
wire io_commit_uops_0_fp_val_0; // @[rob.scala:211:7]
wire io_commit_uops_0_frs3_en_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_lrs2_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_lrs1_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_dst_rtype_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ldst_val_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_lrs3_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_lrs2_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_lrs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_ldst_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ldst_is_rs1_0; // @[rob.scala:211:7]
wire io_commit_uops_0_flush_on_commit_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_unique_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_sys_pc2epc_0; // @[rob.scala:211:7]
wire io_commit_uops_0_uses_stq_0; // @[rob.scala:211:7]
wire io_commit_uops_0_uses_ldq_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_amo_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_fencei_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_fence_0; // @[rob.scala:211:7]
wire io_commit_uops_0_mem_signed_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_mem_size_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_mem_cmd_0; // @[rob.scala:211:7]
wire io_commit_uops_0_bypassable_0; // @[rob.scala:211:7]
wire [63:0] io_commit_uops_0_exc_cause_0; // @[rob.scala:211:7]
wire io_commit_uops_0_exception_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_stale_pdst_0; // @[rob.scala:211:7]
wire io_commit_uops_0_prs3_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_0_prs2_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_0_prs1_busy_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_prs3_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_prs2_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_prs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_pdst_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_rxq_idx_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_stq_idx_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_ldq_idx_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_rob_idx_0; // @[rob.scala:211:7]
wire [11:0] io_commit_uops_0_csr_addr_0; // @[rob.scala:211:7]
wire [19:0] io_commit_uops_0_imm_packed_0; // @[rob.scala:211:7]
wire io_commit_uops_0_taken_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_br_tag_0; // @[rob.scala:211:7]
wire [7:0] io_commit_uops_0_br_mask_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_sfb_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_jal_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_jalr_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_br_0; // @[rob.scala:211:7]
wire io_commit_uops_0_iw_p2_poisoned_0; // @[rob.scala:211:7]
wire io_commit_uops_0_iw_p1_poisoned_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_iw_state_0; // @[rob.scala:211:7]
wire [9:0] io_commit_uops_0_fu_code_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_iq_type_0; // @[rob.scala:211:7]
wire [39:0] io_commit_uops_0_debug_pc_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_0_debug_inst_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_0_inst_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_uopc_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_is_std_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_is_sta_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_is_load_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_ctrl_csr_cmd_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_fcn_dw_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_ctrl_op_fcn_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_ctrl_imm_sel_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_ctrl_op2_sel_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_ctrl_op1_sel_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_0_ctrl_br_type_0; // @[rob.scala:211:7]
wire io_commit_valids_0_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_pc_lob_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_rvc_0; // @[rob.scala:211:7]
wire io_commit_uops_0_edge_inst_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_0_ftq_idx_0; // @[rob.scala:211:7]
wire io_enq_valids_0_0 = io_enq_valids_0; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_uopc_0 = io_enq_uops_0_uopc; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_0_inst_0 = io_enq_uops_0_inst; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_0_debug_inst_0 = io_enq_uops_0_debug_inst; // @[rob.scala:211:7]
wire io_enq_uops_0_is_rvc_0 = io_enq_uops_0_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_enq_uops_0_debug_pc_0 = io_enq_uops_0_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_iq_type_0 = io_enq_uops_0_iq_type; // @[rob.scala:211:7]
wire [9:0] io_enq_uops_0_fu_code_0 = io_enq_uops_0_fu_code; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_0_ctrl_br_type_0 = io_enq_uops_0_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_ctrl_op1_sel_0 = io_enq_uops_0_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_ctrl_op2_sel_0 = io_enq_uops_0_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_ctrl_imm_sel_0 = io_enq_uops_0_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_ctrl_op_fcn_0 = io_enq_uops_0_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_fcn_dw_0 = io_enq_uops_0_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_ctrl_csr_cmd_0 = io_enq_uops_0_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_is_load_0 = io_enq_uops_0_ctrl_is_load; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_is_sta_0 = io_enq_uops_0_ctrl_is_sta; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_is_std_0 = io_enq_uops_0_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_iw_state_0 = io_enq_uops_0_iw_state; // @[rob.scala:211:7]
wire io_enq_uops_0_iw_p1_poisoned_0 = io_enq_uops_0_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_0_iw_p2_poisoned_0 = io_enq_uops_0_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_0_is_br_0 = io_enq_uops_0_is_br; // @[rob.scala:211:7]
wire io_enq_uops_0_is_jalr_0 = io_enq_uops_0_is_jalr; // @[rob.scala:211:7]
wire io_enq_uops_0_is_jal_0 = io_enq_uops_0_is_jal; // @[rob.scala:211:7]
wire io_enq_uops_0_is_sfb_0 = io_enq_uops_0_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_enq_uops_0_br_mask_0 = io_enq_uops_0_br_mask; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_br_tag_0 = io_enq_uops_0_br_tag; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_0_ftq_idx_0 = io_enq_uops_0_ftq_idx; // @[rob.scala:211:7]
wire io_enq_uops_0_edge_inst_0 = io_enq_uops_0_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_pc_lob_0 = io_enq_uops_0_pc_lob; // @[rob.scala:211:7]
wire io_enq_uops_0_taken_0 = io_enq_uops_0_taken; // @[rob.scala:211:7]
wire [19:0] io_enq_uops_0_imm_packed_0 = io_enq_uops_0_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_enq_uops_0_csr_addr_0 = io_enq_uops_0_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_rob_idx_0 = io_enq_uops_0_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_ldq_idx_0 = io_enq_uops_0_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_stq_idx_0 = io_enq_uops_0_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_rxq_idx_0 = io_enq_uops_0_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_pdst_0 = io_enq_uops_0_pdst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_prs1_0 = io_enq_uops_0_prs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_prs2_0 = io_enq_uops_0_prs2; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_prs3_0 = io_enq_uops_0_prs3; // @[rob.scala:211:7]
wire io_enq_uops_0_prs1_busy_0 = io_enq_uops_0_prs1_busy; // @[rob.scala:211:7]
wire io_enq_uops_0_prs2_busy_0 = io_enq_uops_0_prs2_busy; // @[rob.scala:211:7]
wire io_enq_uops_0_prs3_busy_0 = io_enq_uops_0_prs3_busy; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_stale_pdst_0 = io_enq_uops_0_stale_pdst; // @[rob.scala:211:7]
wire io_enq_uops_0_exception_0 = io_enq_uops_0_exception; // @[rob.scala:211:7]
wire [63:0] io_enq_uops_0_exc_cause_0 = io_enq_uops_0_exc_cause; // @[rob.scala:211:7]
wire io_enq_uops_0_bypassable_0 = io_enq_uops_0_bypassable; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_mem_cmd_0 = io_enq_uops_0_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_mem_size_0 = io_enq_uops_0_mem_size; // @[rob.scala:211:7]
wire io_enq_uops_0_mem_signed_0 = io_enq_uops_0_mem_signed; // @[rob.scala:211:7]
wire io_enq_uops_0_is_fence_0 = io_enq_uops_0_is_fence; // @[rob.scala:211:7]
wire io_enq_uops_0_is_fencei_0 = io_enq_uops_0_is_fencei; // @[rob.scala:211:7]
wire io_enq_uops_0_is_amo_0 = io_enq_uops_0_is_amo; // @[rob.scala:211:7]
wire io_enq_uops_0_uses_ldq_0 = io_enq_uops_0_uses_ldq; // @[rob.scala:211:7]
wire io_enq_uops_0_uses_stq_0 = io_enq_uops_0_uses_stq; // @[rob.scala:211:7]
wire io_enq_uops_0_is_sys_pc2epc_0 = io_enq_uops_0_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_enq_uops_0_is_unique_0 = io_enq_uops_0_is_unique; // @[rob.scala:211:7]
wire io_enq_uops_0_flush_on_commit_0 = io_enq_uops_0_flush_on_commit; // @[rob.scala:211:7]
wire io_enq_uops_0_ldst_is_rs1_0 = io_enq_uops_0_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_ldst_0 = io_enq_uops_0_ldst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_lrs1_0 = io_enq_uops_0_lrs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_lrs2_0 = io_enq_uops_0_lrs2; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_lrs3_0 = io_enq_uops_0_lrs3; // @[rob.scala:211:7]
wire io_enq_uops_0_ldst_val_0 = io_enq_uops_0_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_dst_rtype_0 = io_enq_uops_0_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_lrs1_rtype_0 = io_enq_uops_0_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_lrs2_rtype_0 = io_enq_uops_0_lrs2_rtype; // @[rob.scala:211:7]
wire io_enq_uops_0_frs3_en_0 = io_enq_uops_0_frs3_en; // @[rob.scala:211:7]
wire io_enq_uops_0_fp_val_0 = io_enq_uops_0_fp_val; // @[rob.scala:211:7]
wire io_enq_uops_0_fp_single_0 = io_enq_uops_0_fp_single; // @[rob.scala:211:7]
wire io_enq_uops_0_xcpt_pf_if_0 = io_enq_uops_0_xcpt_pf_if; // @[rob.scala:211:7]
wire io_enq_uops_0_xcpt_ae_if_0 = io_enq_uops_0_xcpt_ae_if; // @[rob.scala:211:7]
wire io_enq_uops_0_xcpt_ma_if_0 = io_enq_uops_0_xcpt_ma_if; // @[rob.scala:211:7]
wire io_enq_uops_0_bp_debug_if_0 = io_enq_uops_0_bp_debug_if; // @[rob.scala:211:7]
wire io_enq_uops_0_bp_xcpt_if_0 = io_enq_uops_0_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_debug_fsrc_0 = io_enq_uops_0_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_debug_tsrc_0 = io_enq_uops_0_debug_tsrc; // @[rob.scala:211:7]
wire io_enq_partial_stall_0 = io_enq_partial_stall; // @[rob.scala:211:7]
wire [39:0] io_xcpt_fetch_pc_0 = io_xcpt_fetch_pc; // @[rob.scala:211:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rob.scala:211:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rob.scala:211:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rob.scala:211:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rob.scala:211:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rob.scala:211:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rob.scala:211:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rob.scala:211:7]
wire io_wb_resps_0_valid_0 = io_wb_resps_0_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_uopc_0 = io_wb_resps_0_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_uop_inst_0 = io_wb_resps_0_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_uop_debug_inst_0 = io_wb_resps_0_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_rvc_0 = io_wb_resps_0_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_0_bits_uop_debug_pc_0 = io_wb_resps_0_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_iq_type_0 = io_wb_resps_0_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_0_bits_uop_fu_code_0 = io_wb_resps_0_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_uop_ctrl_br_type_0 = io_wb_resps_0_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_ctrl_op1_sel_0 = io_wb_resps_0_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_ctrl_op2_sel_0 = io_wb_resps_0_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_ctrl_imm_sel_0 = io_wb_resps_0_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_ctrl_op_fcn_0 = io_wb_resps_0_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_0_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_0_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_is_load_0 = io_wb_resps_0_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_is_sta_0 = io_wb_resps_0_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_is_std_0 = io_wb_resps_0_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_iw_state_0 = io_wb_resps_0_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_iw_p1_poisoned_0 = io_wb_resps_0_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_iw_p2_poisoned_0 = io_wb_resps_0_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_br_0 = io_wb_resps_0_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_jalr_0 = io_wb_resps_0_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_jal_0 = io_wb_resps_0_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_sfb_0 = io_wb_resps_0_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_wb_resps_0_bits_uop_br_mask_0 = io_wb_resps_0_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_br_tag_0 = io_wb_resps_0_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_uop_ftq_idx_0 = io_wb_resps_0_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_edge_inst_0 = io_wb_resps_0_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_pc_lob_0 = io_wb_resps_0_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_taken_0 = io_wb_resps_0_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_0_bits_uop_imm_packed_0 = io_wb_resps_0_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_0_bits_uop_csr_addr_0 = io_wb_resps_0_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_rob_idx_0 = io_wb_resps_0_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_ldq_idx_0 = io_wb_resps_0_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_stq_idx_0 = io_wb_resps_0_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_rxq_idx_0 = io_wb_resps_0_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_pdst_0 = io_wb_resps_0_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_prs1_0 = io_wb_resps_0_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_prs2_0 = io_wb_resps_0_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_prs3_0 = io_wb_resps_0_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_uop_ppred_0 = io_wb_resps_0_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_prs1_busy_0 = io_wb_resps_0_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_prs2_busy_0 = io_wb_resps_0_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_prs3_busy_0 = io_wb_resps_0_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ppred_busy_0 = io_wb_resps_0_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_stale_pdst_0 = io_wb_resps_0_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_exception_0 = io_wb_resps_0_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_0_bits_uop_exc_cause_0 = io_wb_resps_0_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_bypassable_0 = io_wb_resps_0_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_mem_cmd_0 = io_wb_resps_0_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_mem_size_0 = io_wb_resps_0_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_mem_signed_0 = io_wb_resps_0_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_fence_0 = io_wb_resps_0_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_fencei_0 = io_wb_resps_0_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_amo_0 = io_wb_resps_0_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_uses_ldq_0 = io_wb_resps_0_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_uses_stq_0 = io_wb_resps_0_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_sys_pc2epc_0 = io_wb_resps_0_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_unique_0 = io_wb_resps_0_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_flush_on_commit_0 = io_wb_resps_0_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ldst_is_rs1_0 = io_wb_resps_0_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_ldst_0 = io_wb_resps_0_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs1_0 = io_wb_resps_0_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs2_0 = io_wb_resps_0_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs3_0 = io_wb_resps_0_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ldst_val_0 = io_wb_resps_0_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_dst_rtype_0 = io_wb_resps_0_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_lrs1_rtype_0 = io_wb_resps_0_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_lrs2_rtype_0 = io_wb_resps_0_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_frs3_en_0 = io_wb_resps_0_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_fp_val_0 = io_wb_resps_0_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_fp_single_0 = io_wb_resps_0_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_xcpt_pf_if_0 = io_wb_resps_0_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_xcpt_ae_if_0 = io_wb_resps_0_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_xcpt_ma_if_0 = io_wb_resps_0_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_bp_debug_if_0 = io_wb_resps_0_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_bp_xcpt_if_0 = io_wb_resps_0_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_debug_fsrc_0 = io_wb_resps_0_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_debug_tsrc_0 = io_wb_resps_0_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_0_bits_data_0 = io_wb_resps_0_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_predicated_0 = io_wb_resps_0_bits_predicated; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_valid_0 = io_wb_resps_0_bits_fflags_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_uopc_0 = io_wb_resps_0_bits_fflags_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_fflags_bits_uop_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_0_bits_fflags_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_0_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_0_bits_fflags_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_0_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_0_bits_fflags_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_br_0 = io_wb_resps_0_bits_fflags_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_0_bits_fflags_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_0_bits_fflags_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_0_bits_fflags_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_wb_resps_0_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_0_bits_fflags_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_0_bits_fflags_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_0_bits_fflags_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_taken_0 = io_wb_resps_0_bits_fflags_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_0_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_0_bits_fflags_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_0_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_0_bits_fflags_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_pdst_0 = io_wb_resps_0_bits_fflags_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs1_0 = io_wb_resps_0_bits_fflags_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs2_0 = io_wb_resps_0_bits_fflags_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_prs3_0 = io_wb_resps_0_bits_fflags_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_ppred_0 = io_wb_resps_0_bits_fflags_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_0_bits_fflags_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_exception_0 = io_wb_resps_0_bits_fflags_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_0_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_0_bits_fflags_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_0_bits_fflags_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_0_bits_fflags_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_0_bits_fflags_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_0_bits_fflags_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_0_bits_fflags_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_0_bits_fflags_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_0_bits_fflags_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_ldst_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_0_bits_fflags_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_0_bits_fflags_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_0_bits_fflags_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_flags_0 = io_wb_resps_0_bits_fflags_bits_flags; // @[rob.scala:211:7]
wire io_wb_resps_1_valid_0 = io_wb_resps_1_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_uopc_0 = io_wb_resps_1_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_1_bits_uop_inst_0 = io_wb_resps_1_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_1_bits_uop_debug_inst_0 = io_wb_resps_1_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_rvc_0 = io_wb_resps_1_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_1_bits_uop_debug_pc_0 = io_wb_resps_1_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_iq_type_0 = io_wb_resps_1_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_1_bits_uop_fu_code_0 = io_wb_resps_1_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_uop_ctrl_br_type_0 = io_wb_resps_1_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_ctrl_op1_sel_0 = io_wb_resps_1_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_ctrl_op2_sel_0 = io_wb_resps_1_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_ctrl_imm_sel_0 = io_wb_resps_1_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_ctrl_op_fcn_0 = io_wb_resps_1_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_1_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_1_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_is_load_0 = io_wb_resps_1_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_is_sta_0 = io_wb_resps_1_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_is_std_0 = io_wb_resps_1_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_iw_state_0 = io_wb_resps_1_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_iw_p1_poisoned_0 = io_wb_resps_1_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_iw_p2_poisoned_0 = io_wb_resps_1_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_br_0 = io_wb_resps_1_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_jalr_0 = io_wb_resps_1_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_jal_0 = io_wb_resps_1_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_sfb_0 = io_wb_resps_1_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_wb_resps_1_bits_uop_br_mask_0 = io_wb_resps_1_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_br_tag_0 = io_wb_resps_1_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_uop_ftq_idx_0 = io_wb_resps_1_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_edge_inst_0 = io_wb_resps_1_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_pc_lob_0 = io_wb_resps_1_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_taken_0 = io_wb_resps_1_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_1_bits_uop_imm_packed_0 = io_wb_resps_1_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_1_bits_uop_csr_addr_0 = io_wb_resps_1_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_rob_idx_0 = io_wb_resps_1_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_ldq_idx_0 = io_wb_resps_1_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_stq_idx_0 = io_wb_resps_1_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_rxq_idx_0 = io_wb_resps_1_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_pdst_0 = io_wb_resps_1_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_prs1_0 = io_wb_resps_1_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_prs2_0 = io_wb_resps_1_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_prs3_0 = io_wb_resps_1_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_uop_ppred_0 = io_wb_resps_1_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_prs1_busy_0 = io_wb_resps_1_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_prs2_busy_0 = io_wb_resps_1_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_prs3_busy_0 = io_wb_resps_1_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ppred_busy_0 = io_wb_resps_1_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_stale_pdst_0 = io_wb_resps_1_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_exception_0 = io_wb_resps_1_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_1_bits_uop_exc_cause_0 = io_wb_resps_1_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_bypassable_0 = io_wb_resps_1_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_mem_cmd_0 = io_wb_resps_1_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_mem_size_0 = io_wb_resps_1_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_mem_signed_0 = io_wb_resps_1_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_fence_0 = io_wb_resps_1_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_fencei_0 = io_wb_resps_1_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_amo_0 = io_wb_resps_1_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_uses_ldq_0 = io_wb_resps_1_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_uses_stq_0 = io_wb_resps_1_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_sys_pc2epc_0 = io_wb_resps_1_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_unique_0 = io_wb_resps_1_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_flush_on_commit_0 = io_wb_resps_1_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ldst_is_rs1_0 = io_wb_resps_1_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_ldst_0 = io_wb_resps_1_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs1_0 = io_wb_resps_1_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs2_0 = io_wb_resps_1_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs3_0 = io_wb_resps_1_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ldst_val_0 = io_wb_resps_1_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_dst_rtype_0 = io_wb_resps_1_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_lrs1_rtype_0 = io_wb_resps_1_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_lrs2_rtype_0 = io_wb_resps_1_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_frs3_en_0 = io_wb_resps_1_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_fp_val_0 = io_wb_resps_1_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_fp_single_0 = io_wb_resps_1_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_xcpt_pf_if_0 = io_wb_resps_1_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_xcpt_ae_if_0 = io_wb_resps_1_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_xcpt_ma_if_0 = io_wb_resps_1_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_bp_debug_if_0 = io_wb_resps_1_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_bp_xcpt_if_0 = io_wb_resps_1_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_debug_fsrc_0 = io_wb_resps_1_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_debug_tsrc_0 = io_wb_resps_1_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_1_bits_data_0 = io_wb_resps_1_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_2_valid_0 = io_wb_resps_2_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_uopc_0 = io_wb_resps_2_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_uop_inst_0 = io_wb_resps_2_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_uop_debug_inst_0 = io_wb_resps_2_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_rvc_0 = io_wb_resps_2_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_2_bits_uop_debug_pc_0 = io_wb_resps_2_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_iq_type_0 = io_wb_resps_2_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_2_bits_uop_fu_code_0 = io_wb_resps_2_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_uop_ctrl_br_type_0 = io_wb_resps_2_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_ctrl_op1_sel_0 = io_wb_resps_2_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_ctrl_op2_sel_0 = io_wb_resps_2_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_ctrl_imm_sel_0 = io_wb_resps_2_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_ctrl_op_fcn_0 = io_wb_resps_2_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_2_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_2_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_is_load_0 = io_wb_resps_2_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_is_sta_0 = io_wb_resps_2_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_is_std_0 = io_wb_resps_2_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_iw_state_0 = io_wb_resps_2_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_iw_p1_poisoned_0 = io_wb_resps_2_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_iw_p2_poisoned_0 = io_wb_resps_2_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_br_0 = io_wb_resps_2_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_jalr_0 = io_wb_resps_2_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_jal_0 = io_wb_resps_2_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_sfb_0 = io_wb_resps_2_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_wb_resps_2_bits_uop_br_mask_0 = io_wb_resps_2_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_br_tag_0 = io_wb_resps_2_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_uop_ftq_idx_0 = io_wb_resps_2_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_edge_inst_0 = io_wb_resps_2_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_pc_lob_0 = io_wb_resps_2_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_taken_0 = io_wb_resps_2_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_2_bits_uop_imm_packed_0 = io_wb_resps_2_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_2_bits_uop_csr_addr_0 = io_wb_resps_2_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_rob_idx_0 = io_wb_resps_2_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_ldq_idx_0 = io_wb_resps_2_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_stq_idx_0 = io_wb_resps_2_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_rxq_idx_0 = io_wb_resps_2_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_pdst_0 = io_wb_resps_2_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_prs1_0 = io_wb_resps_2_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_prs2_0 = io_wb_resps_2_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_prs3_0 = io_wb_resps_2_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_uop_ppred_0 = io_wb_resps_2_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_prs1_busy_0 = io_wb_resps_2_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_prs2_busy_0 = io_wb_resps_2_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_prs3_busy_0 = io_wb_resps_2_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ppred_busy_0 = io_wb_resps_2_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_stale_pdst_0 = io_wb_resps_2_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_exception_0 = io_wb_resps_2_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_2_bits_uop_exc_cause_0 = io_wb_resps_2_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_bypassable_0 = io_wb_resps_2_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_mem_cmd_0 = io_wb_resps_2_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_mem_size_0 = io_wb_resps_2_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_mem_signed_0 = io_wb_resps_2_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_fence_0 = io_wb_resps_2_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_fencei_0 = io_wb_resps_2_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_amo_0 = io_wb_resps_2_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_uses_ldq_0 = io_wb_resps_2_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_uses_stq_0 = io_wb_resps_2_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_sys_pc2epc_0 = io_wb_resps_2_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_unique_0 = io_wb_resps_2_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_flush_on_commit_0 = io_wb_resps_2_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ldst_is_rs1_0 = io_wb_resps_2_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_ldst_0 = io_wb_resps_2_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs1_0 = io_wb_resps_2_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs2_0 = io_wb_resps_2_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs3_0 = io_wb_resps_2_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ldst_val_0 = io_wb_resps_2_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_dst_rtype_0 = io_wb_resps_2_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_lrs1_rtype_0 = io_wb_resps_2_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_lrs2_rtype_0 = io_wb_resps_2_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_frs3_en_0 = io_wb_resps_2_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_fp_val_0 = io_wb_resps_2_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_fp_single_0 = io_wb_resps_2_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_xcpt_pf_if_0 = io_wb_resps_2_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_xcpt_ae_if_0 = io_wb_resps_2_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_xcpt_ma_if_0 = io_wb_resps_2_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_bp_debug_if_0 = io_wb_resps_2_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_bp_xcpt_if_0 = io_wb_resps_2_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_debug_fsrc_0 = io_wb_resps_2_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_debug_tsrc_0 = io_wb_resps_2_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_2_bits_data_0 = io_wb_resps_2_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_predicated_0 = io_wb_resps_2_bits_predicated; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_valid_0 = io_wb_resps_2_bits_fflags_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_uopc_0 = io_wb_resps_2_bits_fflags_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_fflags_bits_uop_inst_0 = io_wb_resps_2_bits_fflags_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_2_bits_fflags_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_2_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_2_bits_fflags_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_2_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_2_bits_fflags_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_2_bits_fflags_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_2_bits_fflags_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_2_bits_fflags_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_br_0 = io_wb_resps_2_bits_fflags_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_2_bits_fflags_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_2_bits_fflags_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_2_bits_fflags_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_wb_resps_2_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_2_bits_fflags_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_2_bits_fflags_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_2_bits_fflags_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_2_bits_fflags_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_taken_0 = io_wb_resps_2_bits_fflags_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_2_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_2_bits_fflags_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_2_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_2_bits_fflags_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_2_bits_fflags_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_pdst_0 = io_wb_resps_2_bits_fflags_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs1_0 = io_wb_resps_2_bits_fflags_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs2_0 = io_wb_resps_2_bits_fflags_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_prs3_0 = io_wb_resps_2_bits_fflags_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_ppred_0 = io_wb_resps_2_bits_fflags_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_2_bits_fflags_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_2_bits_fflags_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_exception_0 = io_wb_resps_2_bits_fflags_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_2_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_2_bits_fflags_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_2_bits_fflags_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_2_bits_fflags_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_2_bits_fflags_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_2_bits_fflags_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_2_bits_fflags_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_2_bits_fflags_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_2_bits_fflags_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_2_bits_fflags_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_2_bits_fflags_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_2_bits_fflags_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_2_bits_fflags_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_2_bits_fflags_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_2_bits_fflags_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_ldst_0 = io_wb_resps_2_bits_fflags_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_2_bits_fflags_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_2_bits_fflags_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_2_bits_fflags_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_2_bits_fflags_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_2_bits_fflags_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_2_bits_fflags_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_2_bits_fflags_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_2_bits_fflags_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_2_bits_fflags_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_2_bits_fflags_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_2_bits_fflags_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_2_bits_fflags_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_flags_0 = io_wb_resps_2_bits_fflags_bits_flags; // @[rob.scala:211:7]
wire io_wb_resps_3_valid_0 = io_wb_resps_3_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_uopc_0 = io_wb_resps_3_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_uop_inst_0 = io_wb_resps_3_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_uop_debug_inst_0 = io_wb_resps_3_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_rvc_0 = io_wb_resps_3_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_3_bits_uop_debug_pc_0 = io_wb_resps_3_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_iq_type_0 = io_wb_resps_3_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_3_bits_uop_fu_code_0 = io_wb_resps_3_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_uop_ctrl_br_type_0 = io_wb_resps_3_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_ctrl_op1_sel_0 = io_wb_resps_3_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_ctrl_op2_sel_0 = io_wb_resps_3_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_ctrl_imm_sel_0 = io_wb_resps_3_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_ctrl_op_fcn_0 = io_wb_resps_3_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_3_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_3_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_is_load_0 = io_wb_resps_3_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_is_sta_0 = io_wb_resps_3_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_is_std_0 = io_wb_resps_3_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_iw_state_0 = io_wb_resps_3_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_iw_p1_poisoned_0 = io_wb_resps_3_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_iw_p2_poisoned_0 = io_wb_resps_3_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_br_0 = io_wb_resps_3_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_jalr_0 = io_wb_resps_3_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_jal_0 = io_wb_resps_3_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_sfb_0 = io_wb_resps_3_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_wb_resps_3_bits_uop_br_mask_0 = io_wb_resps_3_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_br_tag_0 = io_wb_resps_3_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_uop_ftq_idx_0 = io_wb_resps_3_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_edge_inst_0 = io_wb_resps_3_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_pc_lob_0 = io_wb_resps_3_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_taken_0 = io_wb_resps_3_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_3_bits_uop_imm_packed_0 = io_wb_resps_3_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_3_bits_uop_csr_addr_0 = io_wb_resps_3_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_rob_idx_0 = io_wb_resps_3_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_ldq_idx_0 = io_wb_resps_3_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_stq_idx_0 = io_wb_resps_3_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_rxq_idx_0 = io_wb_resps_3_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_pdst_0 = io_wb_resps_3_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_prs1_0 = io_wb_resps_3_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_prs2_0 = io_wb_resps_3_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_prs3_0 = io_wb_resps_3_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_uop_ppred_0 = io_wb_resps_3_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_prs1_busy_0 = io_wb_resps_3_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_prs2_busy_0 = io_wb_resps_3_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_prs3_busy_0 = io_wb_resps_3_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ppred_busy_0 = io_wb_resps_3_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_stale_pdst_0 = io_wb_resps_3_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_exception_0 = io_wb_resps_3_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_3_bits_uop_exc_cause_0 = io_wb_resps_3_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_bypassable_0 = io_wb_resps_3_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_mem_cmd_0 = io_wb_resps_3_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_mem_size_0 = io_wb_resps_3_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_mem_signed_0 = io_wb_resps_3_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_fence_0 = io_wb_resps_3_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_fencei_0 = io_wb_resps_3_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_amo_0 = io_wb_resps_3_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_uses_ldq_0 = io_wb_resps_3_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_uses_stq_0 = io_wb_resps_3_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_sys_pc2epc_0 = io_wb_resps_3_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_unique_0 = io_wb_resps_3_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_flush_on_commit_0 = io_wb_resps_3_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ldst_is_rs1_0 = io_wb_resps_3_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_ldst_0 = io_wb_resps_3_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs1_0 = io_wb_resps_3_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs2_0 = io_wb_resps_3_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs3_0 = io_wb_resps_3_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ldst_val_0 = io_wb_resps_3_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_dst_rtype_0 = io_wb_resps_3_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_lrs1_rtype_0 = io_wb_resps_3_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_lrs2_rtype_0 = io_wb_resps_3_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_frs3_en_0 = io_wb_resps_3_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_fp_val_0 = io_wb_resps_3_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_fp_single_0 = io_wb_resps_3_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_xcpt_pf_if_0 = io_wb_resps_3_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_xcpt_ae_if_0 = io_wb_resps_3_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_xcpt_ma_if_0 = io_wb_resps_3_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_bp_debug_if_0 = io_wb_resps_3_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_bp_xcpt_if_0 = io_wb_resps_3_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_debug_fsrc_0 = io_wb_resps_3_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_debug_tsrc_0 = io_wb_resps_3_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_3_bits_data_0 = io_wb_resps_3_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_valid_0 = io_wb_resps_3_bits_fflags_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_uopc_0 = io_wb_resps_3_bits_fflags_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_fflags_bits_uop_inst_0 = io_wb_resps_3_bits_fflags_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_3_bits_fflags_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_3_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_3_bits_fflags_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_3_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_3_bits_fflags_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_3_bits_fflags_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_3_bits_fflags_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_3_bits_fflags_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_br_0 = io_wb_resps_3_bits_fflags_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_3_bits_fflags_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_3_bits_fflags_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_3_bits_fflags_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_wb_resps_3_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_3_bits_fflags_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_3_bits_fflags_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_3_bits_fflags_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_3_bits_fflags_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_taken_0 = io_wb_resps_3_bits_fflags_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_3_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_3_bits_fflags_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_3_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_3_bits_fflags_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_3_bits_fflags_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_pdst_0 = io_wb_resps_3_bits_fflags_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs1_0 = io_wb_resps_3_bits_fflags_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs2_0 = io_wb_resps_3_bits_fflags_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_prs3_0 = io_wb_resps_3_bits_fflags_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_ppred_0 = io_wb_resps_3_bits_fflags_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_3_bits_fflags_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_3_bits_fflags_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_exception_0 = io_wb_resps_3_bits_fflags_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_3_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_3_bits_fflags_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_3_bits_fflags_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_3_bits_fflags_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_3_bits_fflags_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_3_bits_fflags_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_3_bits_fflags_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_3_bits_fflags_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_3_bits_fflags_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_3_bits_fflags_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_3_bits_fflags_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_3_bits_fflags_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_3_bits_fflags_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_3_bits_fflags_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_3_bits_fflags_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_ldst_0 = io_wb_resps_3_bits_fflags_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_3_bits_fflags_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_3_bits_fflags_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_3_bits_fflags_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_3_bits_fflags_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_3_bits_fflags_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_3_bits_fflags_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_3_bits_fflags_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_3_bits_fflags_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_3_bits_fflags_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_3_bits_fflags_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_3_bits_fflags_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_3_bits_fflags_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_flags_0 = io_wb_resps_3_bits_fflags_bits_flags; // @[rob.scala:211:7]
wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[rob.scala:211:7]
wire [4:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[rob.scala:211:7]
wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[rob.scala:211:7]
wire [4:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[rob.scala:211:7]
wire [4:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[rob.scala:211:7]
wire io_debug_wb_valids_0_0 = io_debug_wb_valids_0; // @[rob.scala:211:7]
wire io_debug_wb_valids_1_0 = io_debug_wb_valids_1; // @[rob.scala:211:7]
wire io_debug_wb_valids_2_0 = io_debug_wb_valids_2; // @[rob.scala:211:7]
wire io_debug_wb_valids_3_0 = io_debug_wb_valids_3; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_0_0 = io_debug_wb_wdata_0; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_1_0 = io_debug_wb_wdata_1; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_2_0 = io_debug_wb_wdata_2; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_3_0 = io_debug_wb_wdata_3; // @[rob.scala:211:7]
wire io_fflags_0_valid_0 = io_fflags_0_valid; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_uopc_0 = io_fflags_0_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_fflags_0_bits_uop_inst_0 = io_fflags_0_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_fflags_0_bits_uop_debug_inst_0 = io_fflags_0_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_rvc_0 = io_fflags_0_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_fflags_0_bits_uop_debug_pc_0 = io_fflags_0_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_iq_type_0 = io_fflags_0_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_fflags_0_bits_uop_fu_code_0 = io_fflags_0_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_fflags_0_bits_uop_ctrl_br_type_0 = io_fflags_0_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_ctrl_op1_sel_0 = io_fflags_0_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_ctrl_op2_sel_0 = io_fflags_0_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_ctrl_imm_sel_0 = io_fflags_0_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_ctrl_op_fcn_0 = io_fflags_0_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_fcn_dw_0 = io_fflags_0_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_ctrl_csr_cmd_0 = io_fflags_0_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_is_load_0 = io_fflags_0_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_is_sta_0 = io_fflags_0_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_is_std_0 = io_fflags_0_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_iw_state_0 = io_fflags_0_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_iw_p1_poisoned_0 = io_fflags_0_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_iw_p2_poisoned_0 = io_fflags_0_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_br_0 = io_fflags_0_bits_uop_is_br; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_jalr_0 = io_fflags_0_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_jal_0 = io_fflags_0_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_sfb_0 = io_fflags_0_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_fflags_0_bits_uop_br_mask_0 = io_fflags_0_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_br_tag_0 = io_fflags_0_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_fflags_0_bits_uop_ftq_idx_0 = io_fflags_0_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_edge_inst_0 = io_fflags_0_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_pc_lob_0 = io_fflags_0_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_taken_0 = io_fflags_0_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_fflags_0_bits_uop_imm_packed_0 = io_fflags_0_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_fflags_0_bits_uop_csr_addr_0 = io_fflags_0_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_rob_idx_0 = io_fflags_0_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_ldq_idx_0 = io_fflags_0_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_stq_idx_0 = io_fflags_0_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_rxq_idx_0 = io_fflags_0_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_pdst_0 = io_fflags_0_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_prs1_0 = io_fflags_0_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_prs2_0 = io_fflags_0_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_prs3_0 = io_fflags_0_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_fflags_0_bits_uop_ppred_0 = io_fflags_0_bits_uop_ppred; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_prs1_busy_0 = io_fflags_0_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_prs2_busy_0 = io_fflags_0_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_prs3_busy_0 = io_fflags_0_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ppred_busy_0 = io_fflags_0_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_stale_pdst_0 = io_fflags_0_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_exception_0 = io_fflags_0_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_fflags_0_bits_uop_exc_cause_0 = io_fflags_0_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_bypassable_0 = io_fflags_0_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_mem_cmd_0 = io_fflags_0_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_mem_size_0 = io_fflags_0_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_mem_signed_0 = io_fflags_0_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_fence_0 = io_fflags_0_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_fencei_0 = io_fflags_0_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_amo_0 = io_fflags_0_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_uses_ldq_0 = io_fflags_0_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_uses_stq_0 = io_fflags_0_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_sys_pc2epc_0 = io_fflags_0_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_unique_0 = io_fflags_0_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_flush_on_commit_0 = io_fflags_0_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ldst_is_rs1_0 = io_fflags_0_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_ldst_0 = io_fflags_0_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_lrs1_0 = io_fflags_0_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_lrs2_0 = io_fflags_0_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_lrs3_0 = io_fflags_0_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ldst_val_0 = io_fflags_0_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_dst_rtype_0 = io_fflags_0_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_lrs1_rtype_0 = io_fflags_0_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_lrs2_rtype_0 = io_fflags_0_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_frs3_en_0 = io_fflags_0_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_fp_val_0 = io_fflags_0_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_fp_single_0 = io_fflags_0_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_xcpt_pf_if_0 = io_fflags_0_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_xcpt_ae_if_0 = io_fflags_0_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_xcpt_ma_if_0 = io_fflags_0_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_bp_debug_if_0 = io_fflags_0_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_bp_xcpt_if_0 = io_fflags_0_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_debug_fsrc_0 = io_fflags_0_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_debug_tsrc_0 = io_fflags_0_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_flags_0 = io_fflags_0_bits_flags; // @[rob.scala:211:7]
wire io_fflags_1_valid_0 = io_fflags_1_valid; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_uopc_0 = io_fflags_1_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_fflags_1_bits_uop_inst_0 = io_fflags_1_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_fflags_1_bits_uop_debug_inst_0 = io_fflags_1_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_rvc_0 = io_fflags_1_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_fflags_1_bits_uop_debug_pc_0 = io_fflags_1_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_iq_type_0 = io_fflags_1_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_fflags_1_bits_uop_fu_code_0 = io_fflags_1_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_fflags_1_bits_uop_ctrl_br_type_0 = io_fflags_1_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_ctrl_op1_sel_0 = io_fflags_1_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_ctrl_op2_sel_0 = io_fflags_1_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_ctrl_imm_sel_0 = io_fflags_1_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_ctrl_op_fcn_0 = io_fflags_1_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_fcn_dw_0 = io_fflags_1_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_ctrl_csr_cmd_0 = io_fflags_1_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_is_load_0 = io_fflags_1_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_is_sta_0 = io_fflags_1_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_is_std_0 = io_fflags_1_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_iw_state_0 = io_fflags_1_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_iw_p1_poisoned_0 = io_fflags_1_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_iw_p2_poisoned_0 = io_fflags_1_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_br_0 = io_fflags_1_bits_uop_is_br; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_jalr_0 = io_fflags_1_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_jal_0 = io_fflags_1_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_sfb_0 = io_fflags_1_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_fflags_1_bits_uop_br_mask_0 = io_fflags_1_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_br_tag_0 = io_fflags_1_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_fflags_1_bits_uop_ftq_idx_0 = io_fflags_1_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_edge_inst_0 = io_fflags_1_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_pc_lob_0 = io_fflags_1_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_taken_0 = io_fflags_1_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_fflags_1_bits_uop_imm_packed_0 = io_fflags_1_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_fflags_1_bits_uop_csr_addr_0 = io_fflags_1_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_rob_idx_0 = io_fflags_1_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_ldq_idx_0 = io_fflags_1_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_stq_idx_0 = io_fflags_1_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_rxq_idx_0 = io_fflags_1_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_pdst_0 = io_fflags_1_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_prs1_0 = io_fflags_1_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_prs2_0 = io_fflags_1_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_prs3_0 = io_fflags_1_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_fflags_1_bits_uop_ppred_0 = io_fflags_1_bits_uop_ppred; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_prs1_busy_0 = io_fflags_1_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_prs2_busy_0 = io_fflags_1_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_prs3_busy_0 = io_fflags_1_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ppred_busy_0 = io_fflags_1_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_stale_pdst_0 = io_fflags_1_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_exception_0 = io_fflags_1_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_fflags_1_bits_uop_exc_cause_0 = io_fflags_1_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_bypassable_0 = io_fflags_1_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_mem_cmd_0 = io_fflags_1_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_mem_size_0 = io_fflags_1_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_mem_signed_0 = io_fflags_1_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_fence_0 = io_fflags_1_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_fencei_0 = io_fflags_1_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_amo_0 = io_fflags_1_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_uses_ldq_0 = io_fflags_1_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_uses_stq_0 = io_fflags_1_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_sys_pc2epc_0 = io_fflags_1_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_unique_0 = io_fflags_1_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_flush_on_commit_0 = io_fflags_1_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ldst_is_rs1_0 = io_fflags_1_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_ldst_0 = io_fflags_1_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_lrs1_0 = io_fflags_1_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_lrs2_0 = io_fflags_1_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_lrs3_0 = io_fflags_1_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ldst_val_0 = io_fflags_1_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_dst_rtype_0 = io_fflags_1_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_lrs1_rtype_0 = io_fflags_1_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_lrs2_rtype_0 = io_fflags_1_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_frs3_en_0 = io_fflags_1_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_fp_val_0 = io_fflags_1_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_fp_single_0 = io_fflags_1_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_xcpt_pf_if_0 = io_fflags_1_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_xcpt_ae_if_0 = io_fflags_1_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_xcpt_ma_if_0 = io_fflags_1_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_bp_debug_if_0 = io_fflags_1_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_bp_xcpt_if_0 = io_fflags_1_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_debug_fsrc_0 = io_fflags_1_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_debug_tsrc_0 = io_fflags_1_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_flags_0 = io_fflags_1_bits_flags; // @[rob.scala:211:7]
wire io_lxcpt_valid_0 = io_lxcpt_valid; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_uopc_0 = io_lxcpt_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_lxcpt_bits_uop_inst_0 = io_lxcpt_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_lxcpt_bits_uop_debug_inst_0 = io_lxcpt_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_rvc_0 = io_lxcpt_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_lxcpt_bits_uop_debug_pc_0 = io_lxcpt_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_iq_type_0 = io_lxcpt_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_lxcpt_bits_uop_fu_code_0 = io_lxcpt_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_lxcpt_bits_uop_ctrl_br_type_0 = io_lxcpt_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lxcpt_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lxcpt_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lxcpt_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lxcpt_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lxcpt_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lxcpt_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_is_load_0 = io_lxcpt_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_is_sta_0 = io_lxcpt_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_is_std_0 = io_lxcpt_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_iw_state_0 = io_lxcpt_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lxcpt_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lxcpt_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_br_0 = io_lxcpt_bits_uop_is_br; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_jalr_0 = io_lxcpt_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_jal_0 = io_lxcpt_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_sfb_0 = io_lxcpt_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_lxcpt_bits_uop_br_mask_0 = io_lxcpt_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_br_tag_0 = io_lxcpt_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_lxcpt_bits_uop_ftq_idx_0 = io_lxcpt_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_edge_inst_0 = io_lxcpt_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_pc_lob_0 = io_lxcpt_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_taken_0 = io_lxcpt_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_lxcpt_bits_uop_imm_packed_0 = io_lxcpt_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_lxcpt_bits_uop_csr_addr_0 = io_lxcpt_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_rob_idx_0 = io_lxcpt_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_ldq_idx_0 = io_lxcpt_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_stq_idx_0 = io_lxcpt_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_rxq_idx_0 = io_lxcpt_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_pdst_0 = io_lxcpt_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_prs1_0 = io_lxcpt_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_prs2_0 = io_lxcpt_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_prs3_0 = io_lxcpt_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_lxcpt_bits_uop_ppred_0 = io_lxcpt_bits_uop_ppred; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_prs1_busy_0 = io_lxcpt_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_prs2_busy_0 = io_lxcpt_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_prs3_busy_0 = io_lxcpt_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ppred_busy_0 = io_lxcpt_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_stale_pdst_0 = io_lxcpt_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_exception_0 = io_lxcpt_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_lxcpt_bits_uop_exc_cause_0 = io_lxcpt_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_bypassable_0 = io_lxcpt_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_mem_cmd_0 = io_lxcpt_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_mem_size_0 = io_lxcpt_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_mem_signed_0 = io_lxcpt_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_fence_0 = io_lxcpt_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_fencei_0 = io_lxcpt_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_amo_0 = io_lxcpt_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_uses_ldq_0 = io_lxcpt_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_uses_stq_0 = io_lxcpt_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lxcpt_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_unique_0 = io_lxcpt_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_flush_on_commit_0 = io_lxcpt_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ldst_is_rs1_0 = io_lxcpt_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_ldst_0 = io_lxcpt_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_lrs1_0 = io_lxcpt_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_lrs2_0 = io_lxcpt_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_lrs3_0 = io_lxcpt_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ldst_val_0 = io_lxcpt_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_dst_rtype_0 = io_lxcpt_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_lrs1_rtype_0 = io_lxcpt_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_lrs2_rtype_0 = io_lxcpt_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_frs3_en_0 = io_lxcpt_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_fp_val_0 = io_lxcpt_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_fp_single_0 = io_lxcpt_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_xcpt_pf_if_0 = io_lxcpt_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_xcpt_ae_if_0 = io_lxcpt_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_xcpt_ma_if_0 = io_lxcpt_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_bp_debug_if_0 = io_lxcpt_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_bp_xcpt_if_0 = io_lxcpt_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_debug_fsrc_0 = io_lxcpt_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_debug_tsrc_0 = io_lxcpt_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_cause_0 = io_lxcpt_bits_cause; // @[rob.scala:211:7]
wire [39:0] io_lxcpt_bits_badvaddr_0 = io_lxcpt_bits_badvaddr; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_uopc_0 = io_csr_replay_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_csr_replay_bits_uop_inst_0 = io_csr_replay_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_csr_replay_bits_uop_debug_inst_0 = io_csr_replay_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_rvc_0 = io_csr_replay_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_csr_replay_bits_uop_debug_pc_0 = io_csr_replay_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_iq_type_0 = io_csr_replay_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_csr_replay_bits_uop_fu_code_0 = io_csr_replay_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_csr_replay_bits_uop_ctrl_br_type_0 = io_csr_replay_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_ctrl_op1_sel_0 = io_csr_replay_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_ctrl_op2_sel_0 = io_csr_replay_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_ctrl_imm_sel_0 = io_csr_replay_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_ctrl_op_fcn_0 = io_csr_replay_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_fcn_dw_0 = io_csr_replay_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_ctrl_csr_cmd_0 = io_csr_replay_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_is_load_0 = io_csr_replay_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_is_sta_0 = io_csr_replay_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_is_std_0 = io_csr_replay_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_iw_state_0 = io_csr_replay_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_iw_p1_poisoned_0 = io_csr_replay_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_iw_p2_poisoned_0 = io_csr_replay_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_br_0 = io_csr_replay_bits_uop_is_br; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_jalr_0 = io_csr_replay_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_jal_0 = io_csr_replay_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_sfb_0 = io_csr_replay_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [7:0] io_csr_replay_bits_uop_br_mask_0 = io_csr_replay_bits_uop_br_mask; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_br_tag_0 = io_csr_replay_bits_uop_br_tag; // @[rob.scala:211:7]
wire [3:0] io_csr_replay_bits_uop_ftq_idx_0 = io_csr_replay_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_edge_inst_0 = io_csr_replay_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_pc_lob_0 = io_csr_replay_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_taken_0 = io_csr_replay_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_csr_replay_bits_uop_imm_packed_0 = io_csr_replay_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_csr_replay_bits_uop_csr_addr_0 = io_csr_replay_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_rob_idx_0 = io_csr_replay_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_ldq_idx_0 = io_csr_replay_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_stq_idx_0 = io_csr_replay_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_rxq_idx_0 = io_csr_replay_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_pdst_0 = io_csr_replay_bits_uop_pdst; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_prs1_0 = io_csr_replay_bits_uop_prs1; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_prs2_0 = io_csr_replay_bits_uop_prs2; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_prs3_0 = io_csr_replay_bits_uop_prs3; // @[rob.scala:211:7]
wire [3:0] io_csr_replay_bits_uop_ppred_0 = io_csr_replay_bits_uop_ppred; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_prs1_busy_0 = io_csr_replay_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_prs2_busy_0 = io_csr_replay_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_prs3_busy_0 = io_csr_replay_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ppred_busy_0 = io_csr_replay_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_stale_pdst_0 = io_csr_replay_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_exception_0 = io_csr_replay_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_csr_replay_bits_uop_exc_cause_0 = io_csr_replay_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_bypassable_0 = io_csr_replay_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_mem_cmd_0 = io_csr_replay_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_mem_size_0 = io_csr_replay_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_mem_signed_0 = io_csr_replay_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_fence_0 = io_csr_replay_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_fencei_0 = io_csr_replay_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_amo_0 = io_csr_replay_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_uses_ldq_0 = io_csr_replay_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_uses_stq_0 = io_csr_replay_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_sys_pc2epc_0 = io_csr_replay_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_unique_0 = io_csr_replay_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_flush_on_commit_0 = io_csr_replay_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ldst_is_rs1_0 = io_csr_replay_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_ldst_0 = io_csr_replay_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_lrs1_0 = io_csr_replay_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_lrs2_0 = io_csr_replay_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_lrs3_0 = io_csr_replay_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ldst_val_0 = io_csr_replay_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_dst_rtype_0 = io_csr_replay_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_lrs1_rtype_0 = io_csr_replay_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_lrs2_rtype_0 = io_csr_replay_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_frs3_en_0 = io_csr_replay_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_fp_val_0 = io_csr_replay_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_fp_single_0 = io_csr_replay_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_xcpt_pf_if_0 = io_csr_replay_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_xcpt_ae_if_0 = io_csr_replay_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_xcpt_ma_if_0 = io_csr_replay_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_bp_debug_if_0 = io_csr_replay_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_bp_xcpt_if_0 = io_csr_replay_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_debug_fsrc_0 = io_csr_replay_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_debug_tsrc_0 = io_csr_replay_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire io_csr_stall_0 = io_csr_stall; // @[rob.scala:211:7]
wire [63:0] io_debug_tsc_0 = io_debug_tsc; // @[rob.scala:211:7]
wire _io_commit_rbk_valids_0_T_1 = 1'h1; // @[rob.scala:431:63]
wire _lxcpt_older_T = 1'h1; // @[rob.scala:640:23]
wire lxcpt_older = 1'h1; // @[rob.scala:640:44]
wire io_enq_uops_0_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_predicated = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_valid = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_br = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_taken = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_exception = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_predicated = 1'h0; // @[rob.scala:211:7]
wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[rob.scala:211:7]
wire io_csr_replay_valid = 1'h0; // @[rob.scala:211:7]
wire io_commit_uops_0_ppred_busy_0 = 1'h0; // @[rob.scala:211:7]
wire debug_entry_0_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_exception = 1'h0; // @[rob.scala:285:25]
wire _rob_unsafe_masked_WIRE_0 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_1 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_2 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_3 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_4 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_5 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_6 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_7 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_8 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_9 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_10 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_11 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_12 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_13 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_14 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_15 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_16 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_17 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_18 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_19 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_20 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_21 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_22 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_23 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_24 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_25 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_26 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_27 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_28 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_29 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_30 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_31 = 1'h0; // @[rob.scala:293:43]
wire _rob_debug_inst_wmask_WIRE_0 = 1'h0; // @[rob.scala:297:46]
wire _rob_val_WIRE_0 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_3 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_4 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_5 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_6 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_7 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_8 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_9 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_10 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_11 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_12 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_13 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_14 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_15 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_16 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_17 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_18 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_19 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_20 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_21 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_22 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_23 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_24 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_25 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_26 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_27 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_28 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_29 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_30 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_31 = 1'h0; // @[rob.scala:308:40]
wire [3:0] io_enq_uops_0_ppred = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_ppred = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_0_ppred_0 = 4'h0; // @[rob.scala:211:7]
wire [3:0] debug_entry_0_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_0_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_0_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_1_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_1_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_1_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_2_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_2_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_2_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_3_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_3_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_3_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_4_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_4_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_4_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_5_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_5_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_5_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_6_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_6_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_6_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_7_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_7_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_7_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_8_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_8_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_8_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_9_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_9_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_9_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_10_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_10_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_10_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_11_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_11_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_11_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_12_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_12_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_12_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_13_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_13_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_13_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_14_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_14_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_14_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_15_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_15_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_15_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_16_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_16_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_16_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_17_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_17_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_17_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_18_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_18_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_18_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_19_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_19_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_19_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_20_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_20_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_20_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_21_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_21_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_21_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_22_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_22_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_22_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_23_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_23_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_23_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_24_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_24_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_24_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_25_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_25_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_25_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_26_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_26_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_26_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_27_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_27_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_27_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_28_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_28_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_28_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_29_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_29_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_29_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_30_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_30_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_30_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_31_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_31_uop_ftq_idx = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_31_uop_ppred = 4'h0; // @[rob.scala:285:25]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_uopc = 7'h0; // @[rob.scala:211:7]
wire [6:0] debug_entry_0_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [31:0] io_wb_resps_1_bits_fflags_bits_uop_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] debug_entry_0_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_0_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_1_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_1_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_2_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_2_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_3_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_3_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_4_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_4_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_5_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_5_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_6_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_6_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_7_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_7_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_8_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_8_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_9_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_9_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_10_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_10_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_11_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_11_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_12_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_12_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_13_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_13_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_14_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_14_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_15_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_15_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_16_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_16_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_17_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_17_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_18_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_18_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_19_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_19_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_20_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_20_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_21_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_21_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_22_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_22_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_23_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_23_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_24_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_24_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_25_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_25_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_26_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_26_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_27_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_27_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_28_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_28_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_29_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_29_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_30_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_30_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_31_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_31_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [39:0] io_wb_resps_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rob.scala:211:7]
wire [39:0] io_csr_replay_bits_badvaddr = 40'h0; // @[rob.scala:211:7]
wire [39:0] debug_entry_0_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_1_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_2_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_3_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_4_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_5_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_6_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_7_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_8_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_9_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_10_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_11_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_12_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_13_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_14_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_15_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_16_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_17_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_18_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_19_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_20_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_21_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_22_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_23_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_24_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_25_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_26_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_27_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_28_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_29_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_30_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_31_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_br_tag = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_stq_idx = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_com_xcpt_bits_flush_typ = 3'h0; // @[rob.scala:211:7]
wire [2:0] debug_entry_0_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_br_tag = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_ldq_idx = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_stq_idx = 3'h0; // @[rob.scala:285:25]
wire [9:0] io_wb_resps_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[rob.scala:211:7]
wire [9:0] debug_entry_0_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_1_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_2_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_3_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_4_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_5_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_6_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_7_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_8_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_9_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_10_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_11_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_12_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_13_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_14_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_15_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_16_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_17_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_18_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_19_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_20_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_21_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_22_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_23_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_24_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_25_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_26_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_27_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_28_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_29_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_30_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_31_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] debug_entry_0_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_rob_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_flags = 5'h0; // @[rob.scala:211:7]
wire [4:0] debug_entry_0_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_0_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_0_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_rob_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [7:0] io_wb_resps_1_bits_fflags_bits_uop_br_mask = 8'h0; // @[rob.scala:211:7]
wire [7:0] debug_entry_0_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_1_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_2_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_3_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_4_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_5_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_6_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_7_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_8_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_9_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_10_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_11_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_12_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_13_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_14_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_15_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_16_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_17_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_18_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_19_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_20_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_21_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_22_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_23_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_24_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_25_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_26_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_27_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_28_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_29_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_30_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [7:0] debug_entry_31_uop_br_mask = 8'h0; // @[rob.scala:285:25]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_pdst = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_prs1 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_prs2 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_prs3 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_ldst = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rob.scala:211:7]
wire [5:0] debug_entry_0_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_prs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_prs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_prs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_stale_pdst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [19:0] io_wb_resps_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rob.scala:211:7]
wire [19:0] debug_entry_0_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_1_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_2_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_3_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_4_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_5_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_6_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_7_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_8_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_9_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_10_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_11_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_12_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_13_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_14_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_15_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_16_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_17_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_18_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_19_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_20_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_21_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_22_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_23_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_24_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_25_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_26_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_27_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_28_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_29_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_30_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_31_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [11:0] io_wb_resps_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rob.scala:211:7]
wire [11:0] debug_entry_0_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_1_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_2_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_3_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_4_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_5_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_6_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_7_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_8_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_9_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_10_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_11_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_12_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_13_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_14_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_15_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_16_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_17_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_18_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_19_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_20_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_21_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_22_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_23_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_24_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_25_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_26_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_27_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_28_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_29_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_30_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_31_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [63:0] io_wb_resps_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rob.scala:211:7]
wire [63:0] io_flush_bits_cause = 64'h0; // @[rob.scala:211:7]
wire [63:0] io_flush_bits_badvaddr = 64'h0; // @[rob.scala:211:7]
wire [63:0] debug_entry_0_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_1_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_2_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_3_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_4_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_5_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_6_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_7_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_8_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_9_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_10_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_11_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_12_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_13_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_14_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_15_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_16_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_17_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_18_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_19_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_20_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_21_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_22_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_23_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_24_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_25_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_26_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_27_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_28_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_29_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_30_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_31_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [4:0] io_csr_replay_bits_cause = 5'h11; // @[rob.scala:211:7]
wire rob_debug_inst_wmask_0 = io_enq_valids_0_0; // @[rob.scala:211:7, :297:38]
wire _rob_tail_lsb_T = io_enq_valids_0_0; // @[util.scala:373:29]
wire [31:0] rob_debug_inst_wdata_0 = io_enq_uops_0_debug_inst_0; // @[rob.scala:211:7, :298:34]
wire new_xcpt_valid = io_lxcpt_valid_0; // @[rob.scala:211:7, :639:41]
wire [6:0] new_xcpt_uop_uopc = io_lxcpt_bits_uop_uopc_0; // @[rob.scala:211:7, :641:23]
wire [31:0] new_xcpt_uop_inst = io_lxcpt_bits_uop_inst_0; // @[rob.scala:211:7, :641:23]
wire [31:0] new_xcpt_uop_debug_inst = io_lxcpt_bits_uop_debug_inst_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_rvc = io_lxcpt_bits_uop_is_rvc_0; // @[rob.scala:211:7, :641:23]
wire [39:0] new_xcpt_uop_debug_pc = io_lxcpt_bits_uop_debug_pc_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_iq_type = io_lxcpt_bits_uop_iq_type_0; // @[rob.scala:211:7, :641:23]
wire [9:0] new_xcpt_uop_fu_code = io_lxcpt_bits_uop_fu_code_0; // @[rob.scala:211:7, :641:23]
wire [3:0] new_xcpt_uop_ctrl_br_type = io_lxcpt_bits_uop_ctrl_br_type_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_ctrl_op1_sel = io_lxcpt_bits_uop_ctrl_op1_sel_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_ctrl_op2_sel = io_lxcpt_bits_uop_ctrl_op2_sel_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_ctrl_imm_sel = io_lxcpt_bits_uop_ctrl_imm_sel_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_ctrl_op_fcn = io_lxcpt_bits_uop_ctrl_op_fcn_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_fcn_dw = io_lxcpt_bits_uop_ctrl_fcn_dw_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_ctrl_csr_cmd = io_lxcpt_bits_uop_ctrl_csr_cmd_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_is_load = io_lxcpt_bits_uop_ctrl_is_load_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_is_sta = io_lxcpt_bits_uop_ctrl_is_sta_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_is_std = io_lxcpt_bits_uop_ctrl_is_std_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_iw_state = io_lxcpt_bits_uop_iw_state_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_iw_p1_poisoned = io_lxcpt_bits_uop_iw_p1_poisoned_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_iw_p2_poisoned = io_lxcpt_bits_uop_iw_p2_poisoned_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_br = io_lxcpt_bits_uop_is_br_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_jalr = io_lxcpt_bits_uop_is_jalr_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_jal = io_lxcpt_bits_uop_is_jal_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_sfb = io_lxcpt_bits_uop_is_sfb_0; // @[rob.scala:211:7, :641:23]
wire [7:0] new_xcpt_uop_br_mask = io_lxcpt_bits_uop_br_mask_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_br_tag = io_lxcpt_bits_uop_br_tag_0; // @[rob.scala:211:7, :641:23]
wire [3:0] new_xcpt_uop_ftq_idx = io_lxcpt_bits_uop_ftq_idx_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_edge_inst = io_lxcpt_bits_uop_edge_inst_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_pc_lob = io_lxcpt_bits_uop_pc_lob_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_taken = io_lxcpt_bits_uop_taken_0; // @[rob.scala:211:7, :641:23]
wire [19:0] new_xcpt_uop_imm_packed = io_lxcpt_bits_uop_imm_packed_0; // @[rob.scala:211:7, :641:23]
wire [11:0] new_xcpt_uop_csr_addr = io_lxcpt_bits_uop_csr_addr_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_rob_idx = io_lxcpt_bits_uop_rob_idx_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_ldq_idx = io_lxcpt_bits_uop_ldq_idx_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_stq_idx = io_lxcpt_bits_uop_stq_idx_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_rxq_idx = io_lxcpt_bits_uop_rxq_idx_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_pdst = io_lxcpt_bits_uop_pdst_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_prs1 = io_lxcpt_bits_uop_prs1_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_prs2 = io_lxcpt_bits_uop_prs2_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_prs3 = io_lxcpt_bits_uop_prs3_0; // @[rob.scala:211:7, :641:23]
wire [3:0] new_xcpt_uop_ppred = io_lxcpt_bits_uop_ppred_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_prs1_busy = io_lxcpt_bits_uop_prs1_busy_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_prs2_busy = io_lxcpt_bits_uop_prs2_busy_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_prs3_busy = io_lxcpt_bits_uop_prs3_busy_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ppred_busy = io_lxcpt_bits_uop_ppred_busy_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_stale_pdst = io_lxcpt_bits_uop_stale_pdst_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_exception = io_lxcpt_bits_uop_exception_0; // @[rob.scala:211:7, :641:23]
wire [63:0] new_xcpt_uop_exc_cause = io_lxcpt_bits_uop_exc_cause_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_bypassable = io_lxcpt_bits_uop_bypassable_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_mem_cmd = io_lxcpt_bits_uop_mem_cmd_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_mem_size = io_lxcpt_bits_uop_mem_size_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_mem_signed = io_lxcpt_bits_uop_mem_signed_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_fence = io_lxcpt_bits_uop_is_fence_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_fencei = io_lxcpt_bits_uop_is_fencei_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_amo = io_lxcpt_bits_uop_is_amo_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_uses_ldq = io_lxcpt_bits_uop_uses_ldq_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_uses_stq = io_lxcpt_bits_uop_uses_stq_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_sys_pc2epc = io_lxcpt_bits_uop_is_sys_pc2epc_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_unique = io_lxcpt_bits_uop_is_unique_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_flush_on_commit = io_lxcpt_bits_uop_flush_on_commit_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ldst_is_rs1 = io_lxcpt_bits_uop_ldst_is_rs1_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_ldst = io_lxcpt_bits_uop_ldst_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_lrs1 = io_lxcpt_bits_uop_lrs1_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_lrs2 = io_lxcpt_bits_uop_lrs2_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_lrs3 = io_lxcpt_bits_uop_lrs3_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ldst_val = io_lxcpt_bits_uop_ldst_val_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_dst_rtype = io_lxcpt_bits_uop_dst_rtype_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_lrs1_rtype = io_lxcpt_bits_uop_lrs1_rtype_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_lrs2_rtype = io_lxcpt_bits_uop_lrs2_rtype_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_frs3_en = io_lxcpt_bits_uop_frs3_en_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_fp_val = io_lxcpt_bits_uop_fp_val_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_fp_single = io_lxcpt_bits_uop_fp_single_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_xcpt_pf_if = io_lxcpt_bits_uop_xcpt_pf_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_xcpt_ae_if = io_lxcpt_bits_uop_xcpt_ae_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_xcpt_ma_if = io_lxcpt_bits_uop_xcpt_ma_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_bp_debug_if = io_lxcpt_bits_uop_bp_debug_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_bp_xcpt_if = io_lxcpt_bits_uop_bp_xcpt_if_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_debug_fsrc = io_lxcpt_bits_uop_debug_fsrc_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_debug_tsrc = io_lxcpt_bits_uop_debug_tsrc_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_cause = io_lxcpt_bits_cause_0; // @[rob.scala:211:7, :641:23]
wire [39:0] new_xcpt_badvaddr = io_lxcpt_bits_badvaddr_0; // @[rob.scala:211:7, :641:23]
wire will_commit_0; // @[rob.scala:242:33]
wire _io_commit_arch_valids_0_T_1; // @[rob.scala:414:48]
wire _finished_committing_row_T = io_commit_valids_0_0; // @[rob.scala:211:7, :693:30]
wire [6:0] flush_uop_uopc = io_commit_uops_0_uopc_0; // @[rob.scala:211:7, :583:22]
wire [31:0] flush_uop_inst = io_commit_uops_0_inst_0; // @[rob.scala:211:7, :583:22]
wire [31:0] flush_uop_debug_inst = io_commit_uops_0_debug_inst_0; // @[rob.scala:211:7, :583:22]
wire io_com_xcpt_bits_is_rvc = io_commit_uops_0_is_rvc_0; // @[rob.scala:211:7]
wire flush_uop_is_rvc = io_commit_uops_0_is_rvc_0; // @[rob.scala:211:7, :583:22]
wire [39:0] flush_uop_debug_pc = io_commit_uops_0_debug_pc_0; // @[rob.scala:211:7, :583:22]
wire [2:0] flush_uop_iq_type = io_commit_uops_0_iq_type_0; // @[rob.scala:211:7, :583:22]
wire [9:0] flush_uop_fu_code = io_commit_uops_0_fu_code_0; // @[rob.scala:211:7, :583:22]
wire [3:0] flush_uop_ctrl_br_type = io_commit_uops_0_ctrl_br_type_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_ctrl_op1_sel = io_commit_uops_0_ctrl_op1_sel_0; // @[rob.scala:211:7, :583:22]
wire [2:0] flush_uop_ctrl_op2_sel = io_commit_uops_0_ctrl_op2_sel_0; // @[rob.scala:211:7, :583:22]
wire [2:0] flush_uop_ctrl_imm_sel = io_commit_uops_0_ctrl_imm_sel_0; // @[rob.scala:211:7, :583:22]
wire [4:0] flush_uop_ctrl_op_fcn = io_commit_uops_0_ctrl_op_fcn_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_ctrl_fcn_dw = io_commit_uops_0_ctrl_fcn_dw_0; // @[rob.scala:211:7, :583:22]
wire [2:0] flush_uop_ctrl_csr_cmd = io_commit_uops_0_ctrl_csr_cmd_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_ctrl_is_load = io_commit_uops_0_ctrl_is_load_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_ctrl_is_sta = io_commit_uops_0_ctrl_is_sta_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_ctrl_is_std = io_commit_uops_0_ctrl_is_std_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_iw_state = io_commit_uops_0_iw_state_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_iw_p1_poisoned = io_commit_uops_0_iw_p1_poisoned_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_iw_p2_poisoned = io_commit_uops_0_iw_p2_poisoned_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_br = io_commit_uops_0_is_br_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_jalr = io_commit_uops_0_is_jalr_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_jal = io_commit_uops_0_is_jal_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_sfb = io_commit_uops_0_is_sfb_0; // @[rob.scala:211:7, :583:22]
wire [7:0] flush_uop_br_mask = io_commit_uops_0_br_mask_0; // @[rob.scala:211:7, :583:22]
wire [2:0] flush_uop_br_tag = io_commit_uops_0_br_tag_0; // @[rob.scala:211:7, :583:22]
wire [3:0] io_com_xcpt_bits_ftq_idx_0 = io_commit_uops_0_ftq_idx_0; // @[rob.scala:211:7]
wire [3:0] flush_uop_ftq_idx = io_commit_uops_0_ftq_idx_0; // @[rob.scala:211:7, :583:22]
wire io_com_xcpt_bits_edge_inst_0 = io_commit_uops_0_edge_inst_0; // @[rob.scala:211:7]
wire flush_uop_edge_inst = io_commit_uops_0_edge_inst_0; // @[rob.scala:211:7, :583:22]
wire [5:0] io_com_xcpt_bits_pc_lob_0 = io_commit_uops_0_pc_lob_0; // @[rob.scala:211:7]
wire [5:0] flush_uop_pc_lob = io_commit_uops_0_pc_lob_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_taken = io_commit_uops_0_taken_0; // @[rob.scala:211:7, :583:22]
wire [19:0] flush_uop_imm_packed = io_commit_uops_0_imm_packed_0; // @[rob.scala:211:7, :583:22]
wire [11:0] flush_uop_csr_addr = io_commit_uops_0_csr_addr_0; // @[rob.scala:211:7, :583:22]
wire [4:0] flush_uop_rob_idx = io_commit_uops_0_rob_idx_0; // @[rob.scala:211:7, :583:22]
wire [2:0] flush_uop_ldq_idx = io_commit_uops_0_ldq_idx_0; // @[rob.scala:211:7, :583:22]
wire [2:0] flush_uop_stq_idx = io_commit_uops_0_stq_idx_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_rxq_idx = io_commit_uops_0_rxq_idx_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_pdst = io_commit_uops_0_pdst_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_prs1 = io_commit_uops_0_prs1_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_prs2 = io_commit_uops_0_prs2_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_prs3 = io_commit_uops_0_prs3_0; // @[rob.scala:211:7, :583:22]
wire [3:0] flush_uop_ppred = io_commit_uops_0_ppred_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_prs1_busy = io_commit_uops_0_prs1_busy_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_prs2_busy = io_commit_uops_0_prs2_busy_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_prs3_busy = io_commit_uops_0_prs3_busy_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_ppred_busy = io_commit_uops_0_ppred_busy_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_stale_pdst = io_commit_uops_0_stale_pdst_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_exception = io_commit_uops_0_exception_0; // @[rob.scala:211:7, :583:22]
wire [63:0] flush_uop_exc_cause = io_commit_uops_0_exc_cause_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_bypassable = io_commit_uops_0_bypassable_0; // @[rob.scala:211:7, :583:22]
wire [4:0] flush_uop_mem_cmd = io_commit_uops_0_mem_cmd_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_mem_size = io_commit_uops_0_mem_size_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_mem_signed = io_commit_uops_0_mem_signed_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_fence = io_commit_uops_0_is_fence_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_fencei = io_commit_uops_0_is_fencei_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_amo = io_commit_uops_0_is_amo_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_uses_ldq = io_commit_uops_0_uses_ldq_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_uses_stq = io_commit_uops_0_uses_stq_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_sys_pc2epc = io_commit_uops_0_is_sys_pc2epc_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_is_unique = io_commit_uops_0_is_unique_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_flush_on_commit = io_commit_uops_0_flush_on_commit_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_ldst_is_rs1 = io_commit_uops_0_ldst_is_rs1_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_ldst = io_commit_uops_0_ldst_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_lrs1 = io_commit_uops_0_lrs1_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_lrs2 = io_commit_uops_0_lrs2_0; // @[rob.scala:211:7, :583:22]
wire [5:0] flush_uop_lrs3 = io_commit_uops_0_lrs3_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_ldst_val = io_commit_uops_0_ldst_val_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_dst_rtype = io_commit_uops_0_dst_rtype_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_lrs1_rtype = io_commit_uops_0_lrs1_rtype_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_lrs2_rtype = io_commit_uops_0_lrs2_rtype_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_frs3_en = io_commit_uops_0_frs3_en_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_fp_val = io_commit_uops_0_fp_val_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_fp_single = io_commit_uops_0_fp_single_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_xcpt_pf_if = io_commit_uops_0_xcpt_pf_if_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_xcpt_ae_if = io_commit_uops_0_xcpt_ae_if_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_xcpt_ma_if = io_commit_uops_0_xcpt_ma_if_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_bp_debug_if = io_commit_uops_0_bp_debug_if_0; // @[rob.scala:211:7, :583:22]
wire flush_uop_bp_xcpt_if = io_commit_uops_0_bp_xcpt_if_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_debug_fsrc = io_commit_uops_0_debug_fsrc_0; // @[rob.scala:211:7, :583:22]
wire [1:0] flush_uop_debug_tsrc = io_commit_uops_0_debug_tsrc_0; // @[rob.scala:211:7, :583:22]
wire fflags_val_0; // @[rob.scala:602:24]
wire [4:0] fflags_0; // @[rob.scala:603:24]
wire _io_commit_rbk_valids_0_T_2; // @[rob.scala:431:60]
wire _io_commit_rollback_T; // @[rob.scala:432:38]
wire _io_com_xcpt_valid_T_1; // @[rob.scala:561:41]
wire [63:0] _io_com_xcpt_bits_badvaddr_T_2; // @[util.scala:261:20]
wire flush_val; // @[rob.scala:578:36]
wire [2:0] io_flush_bits_flush_typ_ret; // @[rob.scala:172:10]
wire empty; // @[rob.scala:240:26]
wire _io_ready_T_4; // @[rob.scala:803:56]
wire io_commit_arch_valids_0_0; // @[rob.scala:211:7]
wire io_commit_fflags_valid_0; // @[rob.scala:211:7]
wire [4:0] io_commit_fflags_bits_0; // @[rob.scala:211:7]
wire [31:0] io_commit_debug_insts_0_0; // @[rob.scala:211:7]
wire io_commit_rbk_valids_0_0; // @[rob.scala:211:7]
wire [63:0] io_commit_debug_wdata_0_0; // @[rob.scala:211:7]
wire io_commit_rollback_0; // @[rob.scala:211:7]
wire [63:0] io_com_xcpt_bits_cause_0; // @[rob.scala:211:7]
wire [63:0] io_com_xcpt_bits_badvaddr_0; // @[rob.scala:211:7]
wire io_com_xcpt_valid_0; // @[rob.scala:211:7]
wire [3:0] io_flush_bits_ftq_idx_0; // @[rob.scala:211:7]
wire io_flush_bits_edge_inst_0; // @[rob.scala:211:7]
wire io_flush_bits_is_rvc_0; // @[rob.scala:211:7]
wire [5:0] io_flush_bits_pc_lob_0; // @[rob.scala:211:7]
wire [2:0] io_flush_bits_flush_typ_0; // @[rob.scala:211:7]
wire io_flush_valid_0; // @[rob.scala:211:7]
wire [4:0] io_rob_tail_idx_0; // @[rob.scala:211:7]
wire [4:0] io_rob_pnr_idx_0; // @[rob.scala:211:7]
wire [4:0] io_rob_head_idx_0; // @[rob.scala:211:7]
wire io_com_load_is_at_rob_head_0; // @[rob.scala:211:7]
wire io_empty_0; // @[rob.scala:211:7]
wire io_ready_0; // @[rob.scala:211:7]
wire io_flush_frontend_0; // @[rob.scala:211:7]
reg [1:0] rob_state; // @[rob.scala:220:26]
reg [4:0] rob_head; // @[rob.scala:223:29]
assign io_rob_head_idx_0 = rob_head; // @[rob.scala:211:7, :223:29]
wire [4:0] _rob_debug_inst_rdata_WIRE = rob_head; // @[rob.scala:223:29, :300:53]
reg [4:0] rob_tail; // @[rob.scala:227:29]
assign io_rob_tail_idx_0 = rob_tail; // @[rob.scala:211:7, :227:29]
reg rob_tail_lsb; // @[rob.scala:228:29]
reg [4:0] rob_pnr; // @[rob.scala:231:29]
assign io_rob_pnr_idx_0 = rob_pnr; // @[rob.scala:211:7, :231:29]
wire _T_351 = rob_state == 2'h2; // @[rob.scala:220:26, :235:31]
wire _com_idx_T; // @[rob.scala:235:31]
assign _com_idx_T = _T_351; // @[rob.scala:235:31]
wire _rbk_row_T; // @[rob.scala:429:29]
assign _rbk_row_T = _T_351; // @[rob.scala:235:31, :429:29]
assign _io_commit_rollback_T = _T_351; // @[rob.scala:235:31, :432:38]
wire [4:0] com_idx = _com_idx_T ? rob_tail : rob_head; // @[rob.scala:223:29, :227:29, :235:{20,31}]
reg maybe_full; // @[rob.scala:238:29]
wire _full_T_1; // @[rob.scala:796:39]
wire full; // @[rob.scala:239:26]
wire _empty_T_2; // @[rob.scala:797:41]
assign io_empty_0 = empty; // @[rob.scala:211:7, :240:26]
wire _will_commit_0_T_3; // @[rob.scala:551:70]
assign io_commit_valids_0_0 = will_commit_0; // @[rob.scala:211:7, :242:33]
wire _can_commit_0_T_3; // @[rob.scala:408:64]
wire can_commit_0; // @[rob.scala:243:33]
wire _can_throw_exception_0_T; // @[rob.scala:402:49]
wire can_throw_exception_0; // @[rob.scala:244:33]
wire _rob_pnr_unsafe_0_T_1; // @[rob.scala:497:43]
wire rob_pnr_unsafe_0; // @[rob.scala:246:33]
wire rob_head_vals_0; // @[rob.scala:247:33]
wire _rob_head_lsb_T = rob_head_vals_0; // @[OneHot.scala:85:71]
wire _io_com_load_is_at_rob_head_T = rob_head_vals_0; // @[OneHot.scala:48:45]
wire rob_tail_vals_0; // @[rob.scala:248:33]
wire _rob_pnr_lsb_T = rob_tail_vals_0; // @[util.scala:373:29]
wire rob_head_uses_stq_0; // @[rob.scala:249:33]
wire rob_head_uses_ldq_0; // @[rob.scala:250:33]
wire [4:0] rob_head_fflags_0; // @[rob.scala:251:33]
wire exception_thrown; // @[rob.scala:253:30]
reg r_xcpt_val; // @[rob.scala:257:33]
assign io_flush_frontend_0 = r_xcpt_val; // @[rob.scala:211:7, :257:33]
reg [6:0] r_xcpt_uop_uopc; // @[rob.scala:258:29]
reg [31:0] r_xcpt_uop_inst; // @[rob.scala:258:29]
reg [31:0] r_xcpt_uop_debug_inst; // @[rob.scala:258:29]
reg r_xcpt_uop_is_rvc; // @[rob.scala:258:29]
reg [39:0] r_xcpt_uop_debug_pc; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_iq_type; // @[rob.scala:258:29]
reg [9:0] r_xcpt_uop_fu_code; // @[rob.scala:258:29]
reg [3:0] r_xcpt_uop_ctrl_br_type; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_ctrl_op1_sel; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_ctrl_op2_sel; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_ctrl_imm_sel; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_ctrl_op_fcn; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_fcn_dw; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_ctrl_csr_cmd; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_is_load; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_is_sta; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_is_std; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_iw_state; // @[rob.scala:258:29]
reg r_xcpt_uop_iw_p1_poisoned; // @[rob.scala:258:29]
reg r_xcpt_uop_iw_p2_poisoned; // @[rob.scala:258:29]
reg r_xcpt_uop_is_br; // @[rob.scala:258:29]
reg r_xcpt_uop_is_jalr; // @[rob.scala:258:29]
reg r_xcpt_uop_is_jal; // @[rob.scala:258:29]
reg r_xcpt_uop_is_sfb; // @[rob.scala:258:29]
reg [7:0] r_xcpt_uop_br_mask; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_br_tag; // @[rob.scala:258:29]
reg [3:0] r_xcpt_uop_ftq_idx; // @[rob.scala:258:29]
reg r_xcpt_uop_edge_inst; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_pc_lob; // @[rob.scala:258:29]
reg r_xcpt_uop_taken; // @[rob.scala:258:29]
reg [19:0] r_xcpt_uop_imm_packed; // @[rob.scala:258:29]
reg [11:0] r_xcpt_uop_csr_addr; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_rob_idx; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_ldq_idx; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_stq_idx; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_rxq_idx; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_pdst; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_prs1; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_prs2; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_prs3; // @[rob.scala:258:29]
reg [3:0] r_xcpt_uop_ppred; // @[rob.scala:258:29]
reg r_xcpt_uop_prs1_busy; // @[rob.scala:258:29]
reg r_xcpt_uop_prs2_busy; // @[rob.scala:258:29]
reg r_xcpt_uop_prs3_busy; // @[rob.scala:258:29]
reg r_xcpt_uop_ppred_busy; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_stale_pdst; // @[rob.scala:258:29]
reg r_xcpt_uop_exception; // @[rob.scala:258:29]
reg [63:0] r_xcpt_uop_exc_cause; // @[rob.scala:258:29]
assign io_com_xcpt_bits_cause_0 = r_xcpt_uop_exc_cause; // @[rob.scala:211:7, :258:29]
reg r_xcpt_uop_bypassable; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_mem_cmd; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_mem_size; // @[rob.scala:258:29]
reg r_xcpt_uop_mem_signed; // @[rob.scala:258:29]
reg r_xcpt_uop_is_fence; // @[rob.scala:258:29]
reg r_xcpt_uop_is_fencei; // @[rob.scala:258:29]
reg r_xcpt_uop_is_amo; // @[rob.scala:258:29]
reg r_xcpt_uop_uses_ldq; // @[rob.scala:258:29]
reg r_xcpt_uop_uses_stq; // @[rob.scala:258:29]
reg r_xcpt_uop_is_sys_pc2epc; // @[rob.scala:258:29]
reg r_xcpt_uop_is_unique; // @[rob.scala:258:29]
reg r_xcpt_uop_flush_on_commit; // @[rob.scala:258:29]
reg r_xcpt_uop_ldst_is_rs1; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_ldst; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_lrs1; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_lrs2; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_lrs3; // @[rob.scala:258:29]
reg r_xcpt_uop_ldst_val; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_dst_rtype; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_lrs1_rtype; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_lrs2_rtype; // @[rob.scala:258:29]
reg r_xcpt_uop_frs3_en; // @[rob.scala:258:29]
reg r_xcpt_uop_fp_val; // @[rob.scala:258:29]
reg r_xcpt_uop_fp_single; // @[rob.scala:258:29]
reg r_xcpt_uop_xcpt_pf_if; // @[rob.scala:258:29]
reg r_xcpt_uop_xcpt_ae_if; // @[rob.scala:258:29]
reg r_xcpt_uop_xcpt_ma_if; // @[rob.scala:258:29]
reg r_xcpt_uop_bp_debug_if; // @[rob.scala:258:29]
reg r_xcpt_uop_bp_xcpt_if; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_debug_fsrc; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_debug_tsrc; // @[rob.scala:258:29]
reg [39:0] r_xcpt_badvaddr; // @[rob.scala:259:29]
wire _rob_unsafe_masked_0_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_1_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_2_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_3_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_4_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_5_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_6_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_7_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_8_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_9_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_10_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_11_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_12_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_13_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_14_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_15_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_16_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_17_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_18_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_19_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_20_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_21_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_22_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_23_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_24_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_25_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_26_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_27_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_28_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_29_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_30_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_31_T_1; // @[rob.scala:494:71]
wire rob_unsafe_masked_0; // @[rob.scala:293:35]
wire rob_unsafe_masked_1; // @[rob.scala:293:35]
wire rob_unsafe_masked_2; // @[rob.scala:293:35]
wire rob_unsafe_masked_3; // @[rob.scala:293:35]
wire rob_unsafe_masked_4; // @[rob.scala:293:35]
wire rob_unsafe_masked_5; // @[rob.scala:293:35]
wire rob_unsafe_masked_6; // @[rob.scala:293:35]
wire rob_unsafe_masked_7; // @[rob.scala:293:35]
wire rob_unsafe_masked_8; // @[rob.scala:293:35]
wire rob_unsafe_masked_9; // @[rob.scala:293:35]
wire rob_unsafe_masked_10; // @[rob.scala:293:35]
wire rob_unsafe_masked_11; // @[rob.scala:293:35]
wire rob_unsafe_masked_12; // @[rob.scala:293:35]
wire rob_unsafe_masked_13; // @[rob.scala:293:35]
wire rob_unsafe_masked_14; // @[rob.scala:293:35]
wire rob_unsafe_masked_15; // @[rob.scala:293:35]
wire rob_unsafe_masked_16; // @[rob.scala:293:35]
wire rob_unsafe_masked_17; // @[rob.scala:293:35]
wire rob_unsafe_masked_18; // @[rob.scala:293:35]
wire rob_unsafe_masked_19; // @[rob.scala:293:35]
wire rob_unsafe_masked_20; // @[rob.scala:293:35]
wire rob_unsafe_masked_21; // @[rob.scala:293:35]
wire rob_unsafe_masked_22; // @[rob.scala:293:35]
wire rob_unsafe_masked_23; // @[rob.scala:293:35]
wire rob_unsafe_masked_24; // @[rob.scala:293:35]
wire rob_unsafe_masked_25; // @[rob.scala:293:35]
wire rob_unsafe_masked_26; // @[rob.scala:293:35]
wire rob_unsafe_masked_27; // @[rob.scala:293:35]
wire rob_unsafe_masked_28; // @[rob.scala:293:35]
wire rob_unsafe_masked_29; // @[rob.scala:293:35]
wire rob_unsafe_masked_30; // @[rob.scala:293:35]
wire rob_unsafe_masked_31; // @[rob.scala:293:35]
reg [4:0] rob_fflags_0_0; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_1; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_2; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_3; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_4; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_5; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_6; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_7; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_8; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_9; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_10; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_11; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_12; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_13; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_14; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_15; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_16; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_17; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_18; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_19; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_20; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_21; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_22; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_23; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_24; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_25; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_26; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_27; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_28; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_29; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_30; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_31; // @[rob.scala:302:46]
reg rob_val_0; // @[rob.scala:308:32]
reg rob_val_1; // @[rob.scala:308:32]
reg rob_val_2; // @[rob.scala:308:32]
reg rob_val_3; // @[rob.scala:308:32]
reg rob_val_4; // @[rob.scala:308:32]
reg rob_val_5; // @[rob.scala:308:32]
reg rob_val_6; // @[rob.scala:308:32]
reg rob_val_7; // @[rob.scala:308:32]
reg rob_val_8; // @[rob.scala:308:32]
reg rob_val_9; // @[rob.scala:308:32]
reg rob_val_10; // @[rob.scala:308:32]
reg rob_val_11; // @[rob.scala:308:32]
reg rob_val_12; // @[rob.scala:308:32]
reg rob_val_13; // @[rob.scala:308:32]
reg rob_val_14; // @[rob.scala:308:32]
reg rob_val_15; // @[rob.scala:308:32]
reg rob_val_16; // @[rob.scala:308:32]
reg rob_val_17; // @[rob.scala:308:32]
reg rob_val_18; // @[rob.scala:308:32]
reg rob_val_19; // @[rob.scala:308:32]
reg rob_val_20; // @[rob.scala:308:32]
reg rob_val_21; // @[rob.scala:308:32]
reg rob_val_22; // @[rob.scala:308:32]
reg rob_val_23; // @[rob.scala:308:32]
reg rob_val_24; // @[rob.scala:308:32]
reg rob_val_25; // @[rob.scala:308:32]
reg rob_val_26; // @[rob.scala:308:32]
reg rob_val_27; // @[rob.scala:308:32]
reg rob_val_28; // @[rob.scala:308:32]
reg rob_val_29; // @[rob.scala:308:32]
reg rob_val_30; // @[rob.scala:308:32]
reg rob_val_31; // @[rob.scala:308:32]
reg rob_bsy_0; // @[rob.scala:309:28]
reg rob_bsy_1; // @[rob.scala:309:28]
reg rob_bsy_2; // @[rob.scala:309:28]
reg rob_bsy_3; // @[rob.scala:309:28]
reg rob_bsy_4; // @[rob.scala:309:28]
reg rob_bsy_5; // @[rob.scala:309:28]
reg rob_bsy_6; // @[rob.scala:309:28]
reg rob_bsy_7; // @[rob.scala:309:28]
reg rob_bsy_8; // @[rob.scala:309:28]
reg rob_bsy_9; // @[rob.scala:309:28]
reg rob_bsy_10; // @[rob.scala:309:28]
reg rob_bsy_11; // @[rob.scala:309:28]
reg rob_bsy_12; // @[rob.scala:309:28]
reg rob_bsy_13; // @[rob.scala:309:28]
reg rob_bsy_14; // @[rob.scala:309:28]
reg rob_bsy_15; // @[rob.scala:309:28]
reg rob_bsy_16; // @[rob.scala:309:28]
reg rob_bsy_17; // @[rob.scala:309:28]
reg rob_bsy_18; // @[rob.scala:309:28]
reg rob_bsy_19; // @[rob.scala:309:28]
reg rob_bsy_20; // @[rob.scala:309:28]
reg rob_bsy_21; // @[rob.scala:309:28]
reg rob_bsy_22; // @[rob.scala:309:28]
reg rob_bsy_23; // @[rob.scala:309:28]
reg rob_bsy_24; // @[rob.scala:309:28]
reg rob_bsy_25; // @[rob.scala:309:28]
reg rob_bsy_26; // @[rob.scala:309:28]
reg rob_bsy_27; // @[rob.scala:309:28]
reg rob_bsy_28; // @[rob.scala:309:28]
reg rob_bsy_29; // @[rob.scala:309:28]
reg rob_bsy_30; // @[rob.scala:309:28]
reg rob_bsy_31; // @[rob.scala:309:28]
reg rob_unsafe_0; // @[rob.scala:310:28]
reg rob_unsafe_1; // @[rob.scala:310:28]
reg rob_unsafe_2; // @[rob.scala:310:28]
reg rob_unsafe_3; // @[rob.scala:310:28]
reg rob_unsafe_4; // @[rob.scala:310:28]
reg rob_unsafe_5; // @[rob.scala:310:28]
reg rob_unsafe_6; // @[rob.scala:310:28]
reg rob_unsafe_7; // @[rob.scala:310:28]
reg rob_unsafe_8; // @[rob.scala:310:28]
reg rob_unsafe_9; // @[rob.scala:310:28]
reg rob_unsafe_10; // @[rob.scala:310:28]
reg rob_unsafe_11; // @[rob.scala:310:28]
reg rob_unsafe_12; // @[rob.scala:310:28]
reg rob_unsafe_13; // @[rob.scala:310:28]
reg rob_unsafe_14; // @[rob.scala:310:28]
reg rob_unsafe_15; // @[rob.scala:310:28]
reg rob_unsafe_16; // @[rob.scala:310:28]
reg rob_unsafe_17; // @[rob.scala:310:28]
reg rob_unsafe_18; // @[rob.scala:310:28]
reg rob_unsafe_19; // @[rob.scala:310:28]
reg rob_unsafe_20; // @[rob.scala:310:28]
reg rob_unsafe_21; // @[rob.scala:310:28]
reg rob_unsafe_22; // @[rob.scala:310:28]
reg rob_unsafe_23; // @[rob.scala:310:28]
reg rob_unsafe_24; // @[rob.scala:310:28]
reg rob_unsafe_25; // @[rob.scala:310:28]
reg rob_unsafe_26; // @[rob.scala:310:28]
reg rob_unsafe_27; // @[rob.scala:310:28]
reg rob_unsafe_28; // @[rob.scala:310:28]
reg rob_unsafe_29; // @[rob.scala:310:28]
reg rob_unsafe_30; // @[rob.scala:310:28]
reg rob_unsafe_31; // @[rob.scala:310:28]
reg [6:0] rob_uop_0_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_0_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_0_debug_inst; // @[rob.scala:311:28]
reg rob_uop_0_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_0_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_0_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_0_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_iw_state; // @[rob.scala:311:28]
reg rob_uop_0_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_0_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_0_is_br; // @[rob.scala:311:28]
reg rob_uop_0_is_jalr; // @[rob.scala:311:28]
reg rob_uop_0_is_jal; // @[rob.scala:311:28]
reg rob_uop_0_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_0_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_0_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_0_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_pc_lob; // @[rob.scala:311:28]
reg rob_uop_0_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_0_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_0_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_prs3; // @[rob.scala:311:28]
reg rob_uop_0_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_0_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_0_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_0_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_0_exc_cause; // @[rob.scala:311:28]
reg rob_uop_0_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_mem_size; // @[rob.scala:311:28]
reg rob_uop_0_mem_signed; // @[rob.scala:311:28]
reg rob_uop_0_is_fence; // @[rob.scala:311:28]
reg rob_uop_0_is_fencei; // @[rob.scala:311:28]
reg rob_uop_0_is_amo; // @[rob.scala:311:28]
reg rob_uop_0_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_0_uses_stq; // @[rob.scala:311:28]
reg rob_uop_0_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_0_is_unique; // @[rob.scala:311:28]
reg rob_uop_0_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_0_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_lrs3; // @[rob.scala:311:28]
reg rob_uop_0_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_0_frs3_en; // @[rob.scala:311:28]
reg rob_uop_0_fp_val; // @[rob.scala:311:28]
reg rob_uop_0_fp_single; // @[rob.scala:311:28]
reg rob_uop_0_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_0_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_0_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_0_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_0_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_is_br; // @[rob.scala:311:28]
reg rob_uop_1_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_1_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_prs3; // @[rob.scala:311:28]
reg rob_uop_1_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_is_br; // @[rob.scala:311:28]
reg rob_uop_2_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_2_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_prs3; // @[rob.scala:311:28]
reg rob_uop_2_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_3_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_3_debug_inst; // @[rob.scala:311:28]
reg rob_uop_3_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_3_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_3_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_3_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_iw_state; // @[rob.scala:311:28]
reg rob_uop_3_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_3_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_3_is_br; // @[rob.scala:311:28]
reg rob_uop_3_is_jalr; // @[rob.scala:311:28]
reg rob_uop_3_is_jal; // @[rob.scala:311:28]
reg rob_uop_3_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_3_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_3_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_3_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_pc_lob; // @[rob.scala:311:28]
reg rob_uop_3_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_3_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_3_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_prs3; // @[rob.scala:311:28]
reg rob_uop_3_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_3_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_3_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_3_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_3_exc_cause; // @[rob.scala:311:28]
reg rob_uop_3_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_mem_size; // @[rob.scala:311:28]
reg rob_uop_3_mem_signed; // @[rob.scala:311:28]
reg rob_uop_3_is_fence; // @[rob.scala:311:28]
reg rob_uop_3_is_fencei; // @[rob.scala:311:28]
reg rob_uop_3_is_amo; // @[rob.scala:311:28]
reg rob_uop_3_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_3_uses_stq; // @[rob.scala:311:28]
reg rob_uop_3_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_3_is_unique; // @[rob.scala:311:28]
reg rob_uop_3_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_3_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_lrs3; // @[rob.scala:311:28]
reg rob_uop_3_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_3_frs3_en; // @[rob.scala:311:28]
reg rob_uop_3_fp_val; // @[rob.scala:311:28]
reg rob_uop_3_fp_single; // @[rob.scala:311:28]
reg rob_uop_3_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_3_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_3_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_3_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_3_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_4_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_4_debug_inst; // @[rob.scala:311:28]
reg rob_uop_4_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_4_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_4_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_4_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_iw_state; // @[rob.scala:311:28]
reg rob_uop_4_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_4_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_4_is_br; // @[rob.scala:311:28]
reg rob_uop_4_is_jalr; // @[rob.scala:311:28]
reg rob_uop_4_is_jal; // @[rob.scala:311:28]
reg rob_uop_4_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_4_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_4_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_4_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_pc_lob; // @[rob.scala:311:28]
reg rob_uop_4_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_4_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_4_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_prs3; // @[rob.scala:311:28]
reg rob_uop_4_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_4_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_4_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_4_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_4_exc_cause; // @[rob.scala:311:28]
reg rob_uop_4_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_mem_size; // @[rob.scala:311:28]
reg rob_uop_4_mem_signed; // @[rob.scala:311:28]
reg rob_uop_4_is_fence; // @[rob.scala:311:28]
reg rob_uop_4_is_fencei; // @[rob.scala:311:28]
reg rob_uop_4_is_amo; // @[rob.scala:311:28]
reg rob_uop_4_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_4_uses_stq; // @[rob.scala:311:28]
reg rob_uop_4_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_4_is_unique; // @[rob.scala:311:28]
reg rob_uop_4_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_4_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_lrs3; // @[rob.scala:311:28]
reg rob_uop_4_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_4_frs3_en; // @[rob.scala:311:28]
reg rob_uop_4_fp_val; // @[rob.scala:311:28]
reg rob_uop_4_fp_single; // @[rob.scala:311:28]
reg rob_uop_4_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_4_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_4_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_4_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_4_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_5_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_5_debug_inst; // @[rob.scala:311:28]
reg rob_uop_5_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_5_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_5_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_5_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_iw_state; // @[rob.scala:311:28]
reg rob_uop_5_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_5_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_5_is_br; // @[rob.scala:311:28]
reg rob_uop_5_is_jalr; // @[rob.scala:311:28]
reg rob_uop_5_is_jal; // @[rob.scala:311:28]
reg rob_uop_5_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_5_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_5_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_5_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_pc_lob; // @[rob.scala:311:28]
reg rob_uop_5_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_5_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_5_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_prs3; // @[rob.scala:311:28]
reg rob_uop_5_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_5_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_5_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_5_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_5_exc_cause; // @[rob.scala:311:28]
reg rob_uop_5_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_mem_size; // @[rob.scala:311:28]
reg rob_uop_5_mem_signed; // @[rob.scala:311:28]
reg rob_uop_5_is_fence; // @[rob.scala:311:28]
reg rob_uop_5_is_fencei; // @[rob.scala:311:28]
reg rob_uop_5_is_amo; // @[rob.scala:311:28]
reg rob_uop_5_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_5_uses_stq; // @[rob.scala:311:28]
reg rob_uop_5_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_5_is_unique; // @[rob.scala:311:28]
reg rob_uop_5_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_5_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_lrs3; // @[rob.scala:311:28]
reg rob_uop_5_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_5_frs3_en; // @[rob.scala:311:28]
reg rob_uop_5_fp_val; // @[rob.scala:311:28]
reg rob_uop_5_fp_single; // @[rob.scala:311:28]
reg rob_uop_5_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_5_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_5_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_5_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_5_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_6_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_6_debug_inst; // @[rob.scala:311:28]
reg rob_uop_6_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_6_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_6_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_6_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_iw_state; // @[rob.scala:311:28]
reg rob_uop_6_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_6_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_6_is_br; // @[rob.scala:311:28]
reg rob_uop_6_is_jalr; // @[rob.scala:311:28]
reg rob_uop_6_is_jal; // @[rob.scala:311:28]
reg rob_uop_6_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_6_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_6_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_6_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_pc_lob; // @[rob.scala:311:28]
reg rob_uop_6_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_6_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_6_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_prs3; // @[rob.scala:311:28]
reg rob_uop_6_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_6_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_6_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_6_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_6_exc_cause; // @[rob.scala:311:28]
reg rob_uop_6_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_mem_size; // @[rob.scala:311:28]
reg rob_uop_6_mem_signed; // @[rob.scala:311:28]
reg rob_uop_6_is_fence; // @[rob.scala:311:28]
reg rob_uop_6_is_fencei; // @[rob.scala:311:28]
reg rob_uop_6_is_amo; // @[rob.scala:311:28]
reg rob_uop_6_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_6_uses_stq; // @[rob.scala:311:28]
reg rob_uop_6_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_6_is_unique; // @[rob.scala:311:28]
reg rob_uop_6_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_6_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_lrs3; // @[rob.scala:311:28]
reg rob_uop_6_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_6_frs3_en; // @[rob.scala:311:28]
reg rob_uop_6_fp_val; // @[rob.scala:311:28]
reg rob_uop_6_fp_single; // @[rob.scala:311:28]
reg rob_uop_6_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_6_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_6_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_6_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_6_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_7_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_7_debug_inst; // @[rob.scala:311:28]
reg rob_uop_7_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_7_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_7_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_7_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_iw_state; // @[rob.scala:311:28]
reg rob_uop_7_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_7_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_7_is_br; // @[rob.scala:311:28]
reg rob_uop_7_is_jalr; // @[rob.scala:311:28]
reg rob_uop_7_is_jal; // @[rob.scala:311:28]
reg rob_uop_7_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_7_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_7_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_7_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_pc_lob; // @[rob.scala:311:28]
reg rob_uop_7_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_7_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_7_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_prs3; // @[rob.scala:311:28]
reg rob_uop_7_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_7_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_7_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_7_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_7_exc_cause; // @[rob.scala:311:28]
reg rob_uop_7_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_mem_size; // @[rob.scala:311:28]
reg rob_uop_7_mem_signed; // @[rob.scala:311:28]
reg rob_uop_7_is_fence; // @[rob.scala:311:28]
reg rob_uop_7_is_fencei; // @[rob.scala:311:28]
reg rob_uop_7_is_amo; // @[rob.scala:311:28]
reg rob_uop_7_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_7_uses_stq; // @[rob.scala:311:28]
reg rob_uop_7_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_7_is_unique; // @[rob.scala:311:28]
reg rob_uop_7_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_7_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_lrs3; // @[rob.scala:311:28]
reg rob_uop_7_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_7_frs3_en; // @[rob.scala:311:28]
reg rob_uop_7_fp_val; // @[rob.scala:311:28]
reg rob_uop_7_fp_single; // @[rob.scala:311:28]
reg rob_uop_7_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_7_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_7_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_7_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_7_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_8_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_8_debug_inst; // @[rob.scala:311:28]
reg rob_uop_8_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_8_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_8_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_8_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_iw_state; // @[rob.scala:311:28]
reg rob_uop_8_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_8_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_8_is_br; // @[rob.scala:311:28]
reg rob_uop_8_is_jalr; // @[rob.scala:311:28]
reg rob_uop_8_is_jal; // @[rob.scala:311:28]
reg rob_uop_8_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_8_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_8_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_8_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_pc_lob; // @[rob.scala:311:28]
reg rob_uop_8_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_8_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_8_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_prs3; // @[rob.scala:311:28]
reg rob_uop_8_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_8_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_8_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_8_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_8_exc_cause; // @[rob.scala:311:28]
reg rob_uop_8_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_mem_size; // @[rob.scala:311:28]
reg rob_uop_8_mem_signed; // @[rob.scala:311:28]
reg rob_uop_8_is_fence; // @[rob.scala:311:28]
reg rob_uop_8_is_fencei; // @[rob.scala:311:28]
reg rob_uop_8_is_amo; // @[rob.scala:311:28]
reg rob_uop_8_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_8_uses_stq; // @[rob.scala:311:28]
reg rob_uop_8_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_8_is_unique; // @[rob.scala:311:28]
reg rob_uop_8_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_8_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_lrs3; // @[rob.scala:311:28]
reg rob_uop_8_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_8_frs3_en; // @[rob.scala:311:28]
reg rob_uop_8_fp_val; // @[rob.scala:311:28]
reg rob_uop_8_fp_single; // @[rob.scala:311:28]
reg rob_uop_8_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_8_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_8_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_8_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_8_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_9_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_9_debug_inst; // @[rob.scala:311:28]
reg rob_uop_9_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_9_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_9_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_9_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_iw_state; // @[rob.scala:311:28]
reg rob_uop_9_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_9_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_9_is_br; // @[rob.scala:311:28]
reg rob_uop_9_is_jalr; // @[rob.scala:311:28]
reg rob_uop_9_is_jal; // @[rob.scala:311:28]
reg rob_uop_9_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_9_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_9_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_9_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_pc_lob; // @[rob.scala:311:28]
reg rob_uop_9_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_9_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_9_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_prs3; // @[rob.scala:311:28]
reg rob_uop_9_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_9_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_9_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_9_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_9_exc_cause; // @[rob.scala:311:28]
reg rob_uop_9_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_mem_size; // @[rob.scala:311:28]
reg rob_uop_9_mem_signed; // @[rob.scala:311:28]
reg rob_uop_9_is_fence; // @[rob.scala:311:28]
reg rob_uop_9_is_fencei; // @[rob.scala:311:28]
reg rob_uop_9_is_amo; // @[rob.scala:311:28]
reg rob_uop_9_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_9_uses_stq; // @[rob.scala:311:28]
reg rob_uop_9_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_9_is_unique; // @[rob.scala:311:28]
reg rob_uop_9_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_9_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_lrs3; // @[rob.scala:311:28]
reg rob_uop_9_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_9_frs3_en; // @[rob.scala:311:28]
reg rob_uop_9_fp_val; // @[rob.scala:311:28]
reg rob_uop_9_fp_single; // @[rob.scala:311:28]
reg rob_uop_9_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_9_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_9_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_9_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_9_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_10_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_10_debug_inst; // @[rob.scala:311:28]
reg rob_uop_10_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_10_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_10_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_10_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_iw_state; // @[rob.scala:311:28]
reg rob_uop_10_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_10_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_10_is_br; // @[rob.scala:311:28]
reg rob_uop_10_is_jalr; // @[rob.scala:311:28]
reg rob_uop_10_is_jal; // @[rob.scala:311:28]
reg rob_uop_10_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_10_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_10_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_10_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_pc_lob; // @[rob.scala:311:28]
reg rob_uop_10_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_10_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_10_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_prs3; // @[rob.scala:311:28]
reg rob_uop_10_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_10_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_10_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_10_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_10_exc_cause; // @[rob.scala:311:28]
reg rob_uop_10_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_mem_size; // @[rob.scala:311:28]
reg rob_uop_10_mem_signed; // @[rob.scala:311:28]
reg rob_uop_10_is_fence; // @[rob.scala:311:28]
reg rob_uop_10_is_fencei; // @[rob.scala:311:28]
reg rob_uop_10_is_amo; // @[rob.scala:311:28]
reg rob_uop_10_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_10_uses_stq; // @[rob.scala:311:28]
reg rob_uop_10_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_10_is_unique; // @[rob.scala:311:28]
reg rob_uop_10_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_10_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_lrs3; // @[rob.scala:311:28]
reg rob_uop_10_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_10_frs3_en; // @[rob.scala:311:28]
reg rob_uop_10_fp_val; // @[rob.scala:311:28]
reg rob_uop_10_fp_single; // @[rob.scala:311:28]
reg rob_uop_10_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_10_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_10_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_10_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_10_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_11_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_11_debug_inst; // @[rob.scala:311:28]
reg rob_uop_11_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_11_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_11_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_11_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_iw_state; // @[rob.scala:311:28]
reg rob_uop_11_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_11_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_11_is_br; // @[rob.scala:311:28]
reg rob_uop_11_is_jalr; // @[rob.scala:311:28]
reg rob_uop_11_is_jal; // @[rob.scala:311:28]
reg rob_uop_11_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_11_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_11_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_11_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_pc_lob; // @[rob.scala:311:28]
reg rob_uop_11_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_11_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_11_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_prs3; // @[rob.scala:311:28]
reg rob_uop_11_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_11_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_11_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_11_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_11_exc_cause; // @[rob.scala:311:28]
reg rob_uop_11_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_mem_size; // @[rob.scala:311:28]
reg rob_uop_11_mem_signed; // @[rob.scala:311:28]
reg rob_uop_11_is_fence; // @[rob.scala:311:28]
reg rob_uop_11_is_fencei; // @[rob.scala:311:28]
reg rob_uop_11_is_amo; // @[rob.scala:311:28]
reg rob_uop_11_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_11_uses_stq; // @[rob.scala:311:28]
reg rob_uop_11_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_11_is_unique; // @[rob.scala:311:28]
reg rob_uop_11_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_11_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_lrs3; // @[rob.scala:311:28]
reg rob_uop_11_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_11_frs3_en; // @[rob.scala:311:28]
reg rob_uop_11_fp_val; // @[rob.scala:311:28]
reg rob_uop_11_fp_single; // @[rob.scala:311:28]
reg rob_uop_11_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_11_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_11_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_11_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_11_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_12_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_12_debug_inst; // @[rob.scala:311:28]
reg rob_uop_12_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_12_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_12_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_12_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_iw_state; // @[rob.scala:311:28]
reg rob_uop_12_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_12_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_12_is_br; // @[rob.scala:311:28]
reg rob_uop_12_is_jalr; // @[rob.scala:311:28]
reg rob_uop_12_is_jal; // @[rob.scala:311:28]
reg rob_uop_12_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_12_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_12_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_12_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_pc_lob; // @[rob.scala:311:28]
reg rob_uop_12_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_12_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_12_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_prs3; // @[rob.scala:311:28]
reg rob_uop_12_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_12_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_12_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_12_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_12_exc_cause; // @[rob.scala:311:28]
reg rob_uop_12_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_mem_size; // @[rob.scala:311:28]
reg rob_uop_12_mem_signed; // @[rob.scala:311:28]
reg rob_uop_12_is_fence; // @[rob.scala:311:28]
reg rob_uop_12_is_fencei; // @[rob.scala:311:28]
reg rob_uop_12_is_amo; // @[rob.scala:311:28]
reg rob_uop_12_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_12_uses_stq; // @[rob.scala:311:28]
reg rob_uop_12_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_12_is_unique; // @[rob.scala:311:28]
reg rob_uop_12_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_12_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_lrs3; // @[rob.scala:311:28]
reg rob_uop_12_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_12_frs3_en; // @[rob.scala:311:28]
reg rob_uop_12_fp_val; // @[rob.scala:311:28]
reg rob_uop_12_fp_single; // @[rob.scala:311:28]
reg rob_uop_12_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_12_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_12_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_12_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_12_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_13_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_13_debug_inst; // @[rob.scala:311:28]
reg rob_uop_13_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_13_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_13_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_13_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_iw_state; // @[rob.scala:311:28]
reg rob_uop_13_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_13_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_13_is_br; // @[rob.scala:311:28]
reg rob_uop_13_is_jalr; // @[rob.scala:311:28]
reg rob_uop_13_is_jal; // @[rob.scala:311:28]
reg rob_uop_13_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_13_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_13_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_13_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_pc_lob; // @[rob.scala:311:28]
reg rob_uop_13_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_13_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_13_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_prs3; // @[rob.scala:311:28]
reg rob_uop_13_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_13_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_13_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_13_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_13_exc_cause; // @[rob.scala:311:28]
reg rob_uop_13_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_mem_size; // @[rob.scala:311:28]
reg rob_uop_13_mem_signed; // @[rob.scala:311:28]
reg rob_uop_13_is_fence; // @[rob.scala:311:28]
reg rob_uop_13_is_fencei; // @[rob.scala:311:28]
reg rob_uop_13_is_amo; // @[rob.scala:311:28]
reg rob_uop_13_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_13_uses_stq; // @[rob.scala:311:28]
reg rob_uop_13_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_13_is_unique; // @[rob.scala:311:28]
reg rob_uop_13_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_13_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_lrs3; // @[rob.scala:311:28]
reg rob_uop_13_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_13_frs3_en; // @[rob.scala:311:28]
reg rob_uop_13_fp_val; // @[rob.scala:311:28]
reg rob_uop_13_fp_single; // @[rob.scala:311:28]
reg rob_uop_13_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_13_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_13_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_13_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_13_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_14_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_14_debug_inst; // @[rob.scala:311:28]
reg rob_uop_14_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_14_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_14_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_14_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_iw_state; // @[rob.scala:311:28]
reg rob_uop_14_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_14_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_14_is_br; // @[rob.scala:311:28]
reg rob_uop_14_is_jalr; // @[rob.scala:311:28]
reg rob_uop_14_is_jal; // @[rob.scala:311:28]
reg rob_uop_14_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_14_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_14_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_14_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_pc_lob; // @[rob.scala:311:28]
reg rob_uop_14_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_14_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_14_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_prs3; // @[rob.scala:311:28]
reg rob_uop_14_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_14_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_14_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_14_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_14_exc_cause; // @[rob.scala:311:28]
reg rob_uop_14_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_mem_size; // @[rob.scala:311:28]
reg rob_uop_14_mem_signed; // @[rob.scala:311:28]
reg rob_uop_14_is_fence; // @[rob.scala:311:28]
reg rob_uop_14_is_fencei; // @[rob.scala:311:28]
reg rob_uop_14_is_amo; // @[rob.scala:311:28]
reg rob_uop_14_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_14_uses_stq; // @[rob.scala:311:28]
reg rob_uop_14_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_14_is_unique; // @[rob.scala:311:28]
reg rob_uop_14_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_14_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_lrs3; // @[rob.scala:311:28]
reg rob_uop_14_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_14_frs3_en; // @[rob.scala:311:28]
reg rob_uop_14_fp_val; // @[rob.scala:311:28]
reg rob_uop_14_fp_single; // @[rob.scala:311:28]
reg rob_uop_14_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_14_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_14_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_14_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_14_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_15_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_15_debug_inst; // @[rob.scala:311:28]
reg rob_uop_15_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_15_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_15_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_15_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_iw_state; // @[rob.scala:311:28]
reg rob_uop_15_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_15_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_15_is_br; // @[rob.scala:311:28]
reg rob_uop_15_is_jalr; // @[rob.scala:311:28]
reg rob_uop_15_is_jal; // @[rob.scala:311:28]
reg rob_uop_15_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_15_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_15_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_15_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_pc_lob; // @[rob.scala:311:28]
reg rob_uop_15_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_15_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_15_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_prs3; // @[rob.scala:311:28]
reg rob_uop_15_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_15_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_15_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_15_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_15_exc_cause; // @[rob.scala:311:28]
reg rob_uop_15_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_mem_size; // @[rob.scala:311:28]
reg rob_uop_15_mem_signed; // @[rob.scala:311:28]
reg rob_uop_15_is_fence; // @[rob.scala:311:28]
reg rob_uop_15_is_fencei; // @[rob.scala:311:28]
reg rob_uop_15_is_amo; // @[rob.scala:311:28]
reg rob_uop_15_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_15_uses_stq; // @[rob.scala:311:28]
reg rob_uop_15_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_15_is_unique; // @[rob.scala:311:28]
reg rob_uop_15_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_15_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_lrs3; // @[rob.scala:311:28]
reg rob_uop_15_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_15_frs3_en; // @[rob.scala:311:28]
reg rob_uop_15_fp_val; // @[rob.scala:311:28]
reg rob_uop_15_fp_single; // @[rob.scala:311:28]
reg rob_uop_15_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_15_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_15_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_15_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_15_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_16_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_16_debug_inst; // @[rob.scala:311:28]
reg rob_uop_16_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_16_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_16_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_16_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_iw_state; // @[rob.scala:311:28]
reg rob_uop_16_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_16_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_16_is_br; // @[rob.scala:311:28]
reg rob_uop_16_is_jalr; // @[rob.scala:311:28]
reg rob_uop_16_is_jal; // @[rob.scala:311:28]
reg rob_uop_16_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_16_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_16_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_16_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_pc_lob; // @[rob.scala:311:28]
reg rob_uop_16_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_16_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_16_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_prs3; // @[rob.scala:311:28]
reg rob_uop_16_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_16_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_16_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_16_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_16_exc_cause; // @[rob.scala:311:28]
reg rob_uop_16_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_mem_size; // @[rob.scala:311:28]
reg rob_uop_16_mem_signed; // @[rob.scala:311:28]
reg rob_uop_16_is_fence; // @[rob.scala:311:28]
reg rob_uop_16_is_fencei; // @[rob.scala:311:28]
reg rob_uop_16_is_amo; // @[rob.scala:311:28]
reg rob_uop_16_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_16_uses_stq; // @[rob.scala:311:28]
reg rob_uop_16_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_16_is_unique; // @[rob.scala:311:28]
reg rob_uop_16_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_16_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_lrs3; // @[rob.scala:311:28]
reg rob_uop_16_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_16_frs3_en; // @[rob.scala:311:28]
reg rob_uop_16_fp_val; // @[rob.scala:311:28]
reg rob_uop_16_fp_single; // @[rob.scala:311:28]
reg rob_uop_16_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_16_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_16_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_16_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_16_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_17_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_17_debug_inst; // @[rob.scala:311:28]
reg rob_uop_17_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_17_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_17_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_17_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_iw_state; // @[rob.scala:311:28]
reg rob_uop_17_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_17_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_17_is_br; // @[rob.scala:311:28]
reg rob_uop_17_is_jalr; // @[rob.scala:311:28]
reg rob_uop_17_is_jal; // @[rob.scala:311:28]
reg rob_uop_17_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_17_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_17_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_17_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_pc_lob; // @[rob.scala:311:28]
reg rob_uop_17_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_17_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_17_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_prs3; // @[rob.scala:311:28]
reg rob_uop_17_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_17_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_17_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_17_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_17_exc_cause; // @[rob.scala:311:28]
reg rob_uop_17_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_mem_size; // @[rob.scala:311:28]
reg rob_uop_17_mem_signed; // @[rob.scala:311:28]
reg rob_uop_17_is_fence; // @[rob.scala:311:28]
reg rob_uop_17_is_fencei; // @[rob.scala:311:28]
reg rob_uop_17_is_amo; // @[rob.scala:311:28]
reg rob_uop_17_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_17_uses_stq; // @[rob.scala:311:28]
reg rob_uop_17_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_17_is_unique; // @[rob.scala:311:28]
reg rob_uop_17_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_17_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_lrs3; // @[rob.scala:311:28]
reg rob_uop_17_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_17_frs3_en; // @[rob.scala:311:28]
reg rob_uop_17_fp_val; // @[rob.scala:311:28]
reg rob_uop_17_fp_single; // @[rob.scala:311:28]
reg rob_uop_17_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_17_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_17_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_17_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_17_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_18_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_18_debug_inst; // @[rob.scala:311:28]
reg rob_uop_18_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_18_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_18_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_18_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_iw_state; // @[rob.scala:311:28]
reg rob_uop_18_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_18_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_18_is_br; // @[rob.scala:311:28]
reg rob_uop_18_is_jalr; // @[rob.scala:311:28]
reg rob_uop_18_is_jal; // @[rob.scala:311:28]
reg rob_uop_18_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_18_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_18_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_18_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_pc_lob; // @[rob.scala:311:28]
reg rob_uop_18_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_18_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_18_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_prs3; // @[rob.scala:311:28]
reg rob_uop_18_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_18_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_18_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_18_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_18_exc_cause; // @[rob.scala:311:28]
reg rob_uop_18_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_mem_size; // @[rob.scala:311:28]
reg rob_uop_18_mem_signed; // @[rob.scala:311:28]
reg rob_uop_18_is_fence; // @[rob.scala:311:28]
reg rob_uop_18_is_fencei; // @[rob.scala:311:28]
reg rob_uop_18_is_amo; // @[rob.scala:311:28]
reg rob_uop_18_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_18_uses_stq; // @[rob.scala:311:28]
reg rob_uop_18_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_18_is_unique; // @[rob.scala:311:28]
reg rob_uop_18_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_18_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_lrs3; // @[rob.scala:311:28]
reg rob_uop_18_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_18_frs3_en; // @[rob.scala:311:28]
reg rob_uop_18_fp_val; // @[rob.scala:311:28]
reg rob_uop_18_fp_single; // @[rob.scala:311:28]
reg rob_uop_18_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_18_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_18_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_18_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_18_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_19_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_19_debug_inst; // @[rob.scala:311:28]
reg rob_uop_19_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_19_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_19_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_19_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_iw_state; // @[rob.scala:311:28]
reg rob_uop_19_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_19_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_19_is_br; // @[rob.scala:311:28]
reg rob_uop_19_is_jalr; // @[rob.scala:311:28]
reg rob_uop_19_is_jal; // @[rob.scala:311:28]
reg rob_uop_19_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_19_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_19_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_19_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_pc_lob; // @[rob.scala:311:28]
reg rob_uop_19_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_19_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_19_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_prs3; // @[rob.scala:311:28]
reg rob_uop_19_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_19_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_19_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_19_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_19_exc_cause; // @[rob.scala:311:28]
reg rob_uop_19_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_mem_size; // @[rob.scala:311:28]
reg rob_uop_19_mem_signed; // @[rob.scala:311:28]
reg rob_uop_19_is_fence; // @[rob.scala:311:28]
reg rob_uop_19_is_fencei; // @[rob.scala:311:28]
reg rob_uop_19_is_amo; // @[rob.scala:311:28]
reg rob_uop_19_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_19_uses_stq; // @[rob.scala:311:28]
reg rob_uop_19_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_19_is_unique; // @[rob.scala:311:28]
reg rob_uop_19_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_19_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_lrs3; // @[rob.scala:311:28]
reg rob_uop_19_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_19_frs3_en; // @[rob.scala:311:28]
reg rob_uop_19_fp_val; // @[rob.scala:311:28]
reg rob_uop_19_fp_single; // @[rob.scala:311:28]
reg rob_uop_19_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_19_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_19_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_19_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_19_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_20_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_20_debug_inst; // @[rob.scala:311:28]
reg rob_uop_20_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_20_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_20_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_20_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_iw_state; // @[rob.scala:311:28]
reg rob_uop_20_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_20_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_20_is_br; // @[rob.scala:311:28]
reg rob_uop_20_is_jalr; // @[rob.scala:311:28]
reg rob_uop_20_is_jal; // @[rob.scala:311:28]
reg rob_uop_20_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_20_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_20_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_20_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_pc_lob; // @[rob.scala:311:28]
reg rob_uop_20_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_20_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_20_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_prs3; // @[rob.scala:311:28]
reg rob_uop_20_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_20_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_20_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_20_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_20_exc_cause; // @[rob.scala:311:28]
reg rob_uop_20_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_mem_size; // @[rob.scala:311:28]
reg rob_uop_20_mem_signed; // @[rob.scala:311:28]
reg rob_uop_20_is_fence; // @[rob.scala:311:28]
reg rob_uop_20_is_fencei; // @[rob.scala:311:28]
reg rob_uop_20_is_amo; // @[rob.scala:311:28]
reg rob_uop_20_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_20_uses_stq; // @[rob.scala:311:28]
reg rob_uop_20_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_20_is_unique; // @[rob.scala:311:28]
reg rob_uop_20_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_20_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_lrs3; // @[rob.scala:311:28]
reg rob_uop_20_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_20_frs3_en; // @[rob.scala:311:28]
reg rob_uop_20_fp_val; // @[rob.scala:311:28]
reg rob_uop_20_fp_single; // @[rob.scala:311:28]
reg rob_uop_20_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_20_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_20_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_20_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_20_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_21_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_21_debug_inst; // @[rob.scala:311:28]
reg rob_uop_21_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_21_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_21_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_21_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_iw_state; // @[rob.scala:311:28]
reg rob_uop_21_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_21_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_21_is_br; // @[rob.scala:311:28]
reg rob_uop_21_is_jalr; // @[rob.scala:311:28]
reg rob_uop_21_is_jal; // @[rob.scala:311:28]
reg rob_uop_21_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_21_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_21_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_21_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_pc_lob; // @[rob.scala:311:28]
reg rob_uop_21_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_21_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_21_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_prs3; // @[rob.scala:311:28]
reg rob_uop_21_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_21_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_21_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_21_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_21_exc_cause; // @[rob.scala:311:28]
reg rob_uop_21_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_mem_size; // @[rob.scala:311:28]
reg rob_uop_21_mem_signed; // @[rob.scala:311:28]
reg rob_uop_21_is_fence; // @[rob.scala:311:28]
reg rob_uop_21_is_fencei; // @[rob.scala:311:28]
reg rob_uop_21_is_amo; // @[rob.scala:311:28]
reg rob_uop_21_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_21_uses_stq; // @[rob.scala:311:28]
reg rob_uop_21_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_21_is_unique; // @[rob.scala:311:28]
reg rob_uop_21_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_21_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_lrs3; // @[rob.scala:311:28]
reg rob_uop_21_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_21_frs3_en; // @[rob.scala:311:28]
reg rob_uop_21_fp_val; // @[rob.scala:311:28]
reg rob_uop_21_fp_single; // @[rob.scala:311:28]
reg rob_uop_21_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_21_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_21_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_21_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_21_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_22_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_22_debug_inst; // @[rob.scala:311:28]
reg rob_uop_22_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_22_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_22_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_22_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_iw_state; // @[rob.scala:311:28]
reg rob_uop_22_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_22_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_22_is_br; // @[rob.scala:311:28]
reg rob_uop_22_is_jalr; // @[rob.scala:311:28]
reg rob_uop_22_is_jal; // @[rob.scala:311:28]
reg rob_uop_22_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_22_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_22_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_22_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_pc_lob; // @[rob.scala:311:28]
reg rob_uop_22_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_22_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_22_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_prs3; // @[rob.scala:311:28]
reg rob_uop_22_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_22_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_22_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_22_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_22_exc_cause; // @[rob.scala:311:28]
reg rob_uop_22_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_mem_size; // @[rob.scala:311:28]
reg rob_uop_22_mem_signed; // @[rob.scala:311:28]
reg rob_uop_22_is_fence; // @[rob.scala:311:28]
reg rob_uop_22_is_fencei; // @[rob.scala:311:28]
reg rob_uop_22_is_amo; // @[rob.scala:311:28]
reg rob_uop_22_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_22_uses_stq; // @[rob.scala:311:28]
reg rob_uop_22_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_22_is_unique; // @[rob.scala:311:28]
reg rob_uop_22_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_22_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_lrs3; // @[rob.scala:311:28]
reg rob_uop_22_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_22_frs3_en; // @[rob.scala:311:28]
reg rob_uop_22_fp_val; // @[rob.scala:311:28]
reg rob_uop_22_fp_single; // @[rob.scala:311:28]
reg rob_uop_22_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_22_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_22_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_22_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_22_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_23_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_23_debug_inst; // @[rob.scala:311:28]
reg rob_uop_23_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_23_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_23_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_23_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_iw_state; // @[rob.scala:311:28]
reg rob_uop_23_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_23_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_23_is_br; // @[rob.scala:311:28]
reg rob_uop_23_is_jalr; // @[rob.scala:311:28]
reg rob_uop_23_is_jal; // @[rob.scala:311:28]
reg rob_uop_23_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_23_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_23_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_23_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_pc_lob; // @[rob.scala:311:28]
reg rob_uop_23_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_23_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_23_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_prs3; // @[rob.scala:311:28]
reg rob_uop_23_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_23_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_23_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_23_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_23_exc_cause; // @[rob.scala:311:28]
reg rob_uop_23_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_mem_size; // @[rob.scala:311:28]
reg rob_uop_23_mem_signed; // @[rob.scala:311:28]
reg rob_uop_23_is_fence; // @[rob.scala:311:28]
reg rob_uop_23_is_fencei; // @[rob.scala:311:28]
reg rob_uop_23_is_amo; // @[rob.scala:311:28]
reg rob_uop_23_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_23_uses_stq; // @[rob.scala:311:28]
reg rob_uop_23_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_23_is_unique; // @[rob.scala:311:28]
reg rob_uop_23_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_23_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_lrs3; // @[rob.scala:311:28]
reg rob_uop_23_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_23_frs3_en; // @[rob.scala:311:28]
reg rob_uop_23_fp_val; // @[rob.scala:311:28]
reg rob_uop_23_fp_single; // @[rob.scala:311:28]
reg rob_uop_23_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_23_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_23_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_23_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_23_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_24_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_24_debug_inst; // @[rob.scala:311:28]
reg rob_uop_24_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_24_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_24_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_24_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_iw_state; // @[rob.scala:311:28]
reg rob_uop_24_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_24_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_24_is_br; // @[rob.scala:311:28]
reg rob_uop_24_is_jalr; // @[rob.scala:311:28]
reg rob_uop_24_is_jal; // @[rob.scala:311:28]
reg rob_uop_24_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_24_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_24_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_24_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_pc_lob; // @[rob.scala:311:28]
reg rob_uop_24_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_24_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_24_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_prs3; // @[rob.scala:311:28]
reg rob_uop_24_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_24_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_24_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_24_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_24_exc_cause; // @[rob.scala:311:28]
reg rob_uop_24_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_mem_size; // @[rob.scala:311:28]
reg rob_uop_24_mem_signed; // @[rob.scala:311:28]
reg rob_uop_24_is_fence; // @[rob.scala:311:28]
reg rob_uop_24_is_fencei; // @[rob.scala:311:28]
reg rob_uop_24_is_amo; // @[rob.scala:311:28]
reg rob_uop_24_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_24_uses_stq; // @[rob.scala:311:28]
reg rob_uop_24_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_24_is_unique; // @[rob.scala:311:28]
reg rob_uop_24_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_24_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_lrs3; // @[rob.scala:311:28]
reg rob_uop_24_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_24_frs3_en; // @[rob.scala:311:28]
reg rob_uop_24_fp_val; // @[rob.scala:311:28]
reg rob_uop_24_fp_single; // @[rob.scala:311:28]
reg rob_uop_24_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_24_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_24_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_24_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_24_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_25_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_25_debug_inst; // @[rob.scala:311:28]
reg rob_uop_25_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_25_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_25_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_25_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_iw_state; // @[rob.scala:311:28]
reg rob_uop_25_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_25_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_25_is_br; // @[rob.scala:311:28]
reg rob_uop_25_is_jalr; // @[rob.scala:311:28]
reg rob_uop_25_is_jal; // @[rob.scala:311:28]
reg rob_uop_25_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_25_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_25_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_25_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_pc_lob; // @[rob.scala:311:28]
reg rob_uop_25_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_25_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_25_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_prs3; // @[rob.scala:311:28]
reg rob_uop_25_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_25_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_25_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_25_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_25_exc_cause; // @[rob.scala:311:28]
reg rob_uop_25_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_mem_size; // @[rob.scala:311:28]
reg rob_uop_25_mem_signed; // @[rob.scala:311:28]
reg rob_uop_25_is_fence; // @[rob.scala:311:28]
reg rob_uop_25_is_fencei; // @[rob.scala:311:28]
reg rob_uop_25_is_amo; // @[rob.scala:311:28]
reg rob_uop_25_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_25_uses_stq; // @[rob.scala:311:28]
reg rob_uop_25_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_25_is_unique; // @[rob.scala:311:28]
reg rob_uop_25_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_25_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_lrs3; // @[rob.scala:311:28]
reg rob_uop_25_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_25_frs3_en; // @[rob.scala:311:28]
reg rob_uop_25_fp_val; // @[rob.scala:311:28]
reg rob_uop_25_fp_single; // @[rob.scala:311:28]
reg rob_uop_25_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_25_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_25_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_25_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_25_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_26_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_26_debug_inst; // @[rob.scala:311:28]
reg rob_uop_26_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_26_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_26_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_26_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_iw_state; // @[rob.scala:311:28]
reg rob_uop_26_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_26_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_26_is_br; // @[rob.scala:311:28]
reg rob_uop_26_is_jalr; // @[rob.scala:311:28]
reg rob_uop_26_is_jal; // @[rob.scala:311:28]
reg rob_uop_26_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_26_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_26_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_26_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_pc_lob; // @[rob.scala:311:28]
reg rob_uop_26_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_26_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_26_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_prs3; // @[rob.scala:311:28]
reg rob_uop_26_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_26_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_26_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_26_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_26_exc_cause; // @[rob.scala:311:28]
reg rob_uop_26_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_mem_size; // @[rob.scala:311:28]
reg rob_uop_26_mem_signed; // @[rob.scala:311:28]
reg rob_uop_26_is_fence; // @[rob.scala:311:28]
reg rob_uop_26_is_fencei; // @[rob.scala:311:28]
reg rob_uop_26_is_amo; // @[rob.scala:311:28]
reg rob_uop_26_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_26_uses_stq; // @[rob.scala:311:28]
reg rob_uop_26_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_26_is_unique; // @[rob.scala:311:28]
reg rob_uop_26_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_26_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_lrs3; // @[rob.scala:311:28]
reg rob_uop_26_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_26_frs3_en; // @[rob.scala:311:28]
reg rob_uop_26_fp_val; // @[rob.scala:311:28]
reg rob_uop_26_fp_single; // @[rob.scala:311:28]
reg rob_uop_26_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_26_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_26_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_26_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_26_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_27_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_27_debug_inst; // @[rob.scala:311:28]
reg rob_uop_27_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_27_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_27_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_27_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_iw_state; // @[rob.scala:311:28]
reg rob_uop_27_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_27_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_27_is_br; // @[rob.scala:311:28]
reg rob_uop_27_is_jalr; // @[rob.scala:311:28]
reg rob_uop_27_is_jal; // @[rob.scala:311:28]
reg rob_uop_27_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_27_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_27_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_27_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_pc_lob; // @[rob.scala:311:28]
reg rob_uop_27_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_27_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_27_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_prs3; // @[rob.scala:311:28]
reg rob_uop_27_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_27_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_27_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_27_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_27_exc_cause; // @[rob.scala:311:28]
reg rob_uop_27_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_mem_size; // @[rob.scala:311:28]
reg rob_uop_27_mem_signed; // @[rob.scala:311:28]
reg rob_uop_27_is_fence; // @[rob.scala:311:28]
reg rob_uop_27_is_fencei; // @[rob.scala:311:28]
reg rob_uop_27_is_amo; // @[rob.scala:311:28]
reg rob_uop_27_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_27_uses_stq; // @[rob.scala:311:28]
reg rob_uop_27_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_27_is_unique; // @[rob.scala:311:28]
reg rob_uop_27_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_27_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_lrs3; // @[rob.scala:311:28]
reg rob_uop_27_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_27_frs3_en; // @[rob.scala:311:28]
reg rob_uop_27_fp_val; // @[rob.scala:311:28]
reg rob_uop_27_fp_single; // @[rob.scala:311:28]
reg rob_uop_27_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_27_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_27_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_27_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_27_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_28_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_28_debug_inst; // @[rob.scala:311:28]
reg rob_uop_28_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_28_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_28_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_28_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_iw_state; // @[rob.scala:311:28]
reg rob_uop_28_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_28_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_28_is_br; // @[rob.scala:311:28]
reg rob_uop_28_is_jalr; // @[rob.scala:311:28]
reg rob_uop_28_is_jal; // @[rob.scala:311:28]
reg rob_uop_28_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_28_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_28_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_28_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_pc_lob; // @[rob.scala:311:28]
reg rob_uop_28_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_28_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_28_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_prs3; // @[rob.scala:311:28]
reg rob_uop_28_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_28_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_28_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_28_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_28_exc_cause; // @[rob.scala:311:28]
reg rob_uop_28_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_mem_size; // @[rob.scala:311:28]
reg rob_uop_28_mem_signed; // @[rob.scala:311:28]
reg rob_uop_28_is_fence; // @[rob.scala:311:28]
reg rob_uop_28_is_fencei; // @[rob.scala:311:28]
reg rob_uop_28_is_amo; // @[rob.scala:311:28]
reg rob_uop_28_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_28_uses_stq; // @[rob.scala:311:28]
reg rob_uop_28_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_28_is_unique; // @[rob.scala:311:28]
reg rob_uop_28_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_28_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_lrs3; // @[rob.scala:311:28]
reg rob_uop_28_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_28_frs3_en; // @[rob.scala:311:28]
reg rob_uop_28_fp_val; // @[rob.scala:311:28]
reg rob_uop_28_fp_single; // @[rob.scala:311:28]
reg rob_uop_28_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_28_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_28_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_28_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_28_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_29_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_29_debug_inst; // @[rob.scala:311:28]
reg rob_uop_29_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_29_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_29_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_29_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_iw_state; // @[rob.scala:311:28]
reg rob_uop_29_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_29_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_29_is_br; // @[rob.scala:311:28]
reg rob_uop_29_is_jalr; // @[rob.scala:311:28]
reg rob_uop_29_is_jal; // @[rob.scala:311:28]
reg rob_uop_29_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_29_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_29_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_29_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_pc_lob; // @[rob.scala:311:28]
reg rob_uop_29_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_29_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_29_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_prs3; // @[rob.scala:311:28]
reg rob_uop_29_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_29_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_29_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_29_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_29_exc_cause; // @[rob.scala:311:28]
reg rob_uop_29_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_mem_size; // @[rob.scala:311:28]
reg rob_uop_29_mem_signed; // @[rob.scala:311:28]
reg rob_uop_29_is_fence; // @[rob.scala:311:28]
reg rob_uop_29_is_fencei; // @[rob.scala:311:28]
reg rob_uop_29_is_amo; // @[rob.scala:311:28]
reg rob_uop_29_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_29_uses_stq; // @[rob.scala:311:28]
reg rob_uop_29_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_29_is_unique; // @[rob.scala:311:28]
reg rob_uop_29_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_29_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_lrs3; // @[rob.scala:311:28]
reg rob_uop_29_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_29_frs3_en; // @[rob.scala:311:28]
reg rob_uop_29_fp_val; // @[rob.scala:311:28]
reg rob_uop_29_fp_single; // @[rob.scala:311:28]
reg rob_uop_29_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_29_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_29_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_29_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_29_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_30_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_30_debug_inst; // @[rob.scala:311:28]
reg rob_uop_30_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_30_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_30_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_30_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_iw_state; // @[rob.scala:311:28]
reg rob_uop_30_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_30_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_30_is_br; // @[rob.scala:311:28]
reg rob_uop_30_is_jalr; // @[rob.scala:311:28]
reg rob_uop_30_is_jal; // @[rob.scala:311:28]
reg rob_uop_30_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_30_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_30_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_30_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_pc_lob; // @[rob.scala:311:28]
reg rob_uop_30_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_30_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_30_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_prs3; // @[rob.scala:311:28]
reg rob_uop_30_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_30_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_30_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_30_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_30_exc_cause; // @[rob.scala:311:28]
reg rob_uop_30_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_mem_size; // @[rob.scala:311:28]
reg rob_uop_30_mem_signed; // @[rob.scala:311:28]
reg rob_uop_30_is_fence; // @[rob.scala:311:28]
reg rob_uop_30_is_fencei; // @[rob.scala:311:28]
reg rob_uop_30_is_amo; // @[rob.scala:311:28]
reg rob_uop_30_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_30_uses_stq; // @[rob.scala:311:28]
reg rob_uop_30_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_30_is_unique; // @[rob.scala:311:28]
reg rob_uop_30_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_30_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_lrs3; // @[rob.scala:311:28]
reg rob_uop_30_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_30_frs3_en; // @[rob.scala:311:28]
reg rob_uop_30_fp_val; // @[rob.scala:311:28]
reg rob_uop_30_fp_single; // @[rob.scala:311:28]
reg rob_uop_30_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_30_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_30_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_30_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_30_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_31_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_31_debug_inst; // @[rob.scala:311:28]
reg rob_uop_31_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_31_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_31_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_31_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_iw_state; // @[rob.scala:311:28]
reg rob_uop_31_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_31_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_31_is_br; // @[rob.scala:311:28]
reg rob_uop_31_is_jalr; // @[rob.scala:311:28]
reg rob_uop_31_is_jal; // @[rob.scala:311:28]
reg rob_uop_31_is_sfb; // @[rob.scala:311:28]
reg [7:0] rob_uop_31_br_mask; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_br_tag; // @[rob.scala:311:28]
reg [3:0] rob_uop_31_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_31_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_pc_lob; // @[rob.scala:311:28]
reg rob_uop_31_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_31_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_31_csr_addr; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_rob_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_ldq_idx; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_rxq_idx; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_pdst; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_prs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_prs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_prs3; // @[rob.scala:311:28]
reg rob_uop_31_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_31_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_31_prs3_busy; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_31_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_31_exc_cause; // @[rob.scala:311:28]
reg rob_uop_31_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_mem_size; // @[rob.scala:311:28]
reg rob_uop_31_mem_signed; // @[rob.scala:311:28]
reg rob_uop_31_is_fence; // @[rob.scala:311:28]
reg rob_uop_31_is_fencei; // @[rob.scala:311:28]
reg rob_uop_31_is_amo; // @[rob.scala:311:28]
reg rob_uop_31_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_31_uses_stq; // @[rob.scala:311:28]
reg rob_uop_31_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_31_is_unique; // @[rob.scala:311:28]
reg rob_uop_31_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_31_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_lrs3; // @[rob.scala:311:28]
reg rob_uop_31_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_31_frs3_en; // @[rob.scala:311:28]
reg rob_uop_31_fp_val; // @[rob.scala:311:28]
reg rob_uop_31_fp_single; // @[rob.scala:311:28]
reg rob_uop_31_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_31_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_31_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_31_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_31_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_debug_tsrc; // @[rob.scala:311:28]
reg rob_exception_0; // @[rob.scala:312:28]
reg rob_exception_1; // @[rob.scala:312:28]
reg rob_exception_2; // @[rob.scala:312:28]
reg rob_exception_3; // @[rob.scala:312:28]
reg rob_exception_4; // @[rob.scala:312:28]
reg rob_exception_5; // @[rob.scala:312:28]
reg rob_exception_6; // @[rob.scala:312:28]
reg rob_exception_7; // @[rob.scala:312:28]
reg rob_exception_8; // @[rob.scala:312:28]
reg rob_exception_9; // @[rob.scala:312:28]
reg rob_exception_10; // @[rob.scala:312:28]
reg rob_exception_11; // @[rob.scala:312:28]
reg rob_exception_12; // @[rob.scala:312:28]
reg rob_exception_13; // @[rob.scala:312:28]
reg rob_exception_14; // @[rob.scala:312:28]
reg rob_exception_15; // @[rob.scala:312:28]
reg rob_exception_16; // @[rob.scala:312:28]
reg rob_exception_17; // @[rob.scala:312:28]
reg rob_exception_18; // @[rob.scala:312:28]
reg rob_exception_19; // @[rob.scala:312:28]
reg rob_exception_20; // @[rob.scala:312:28]
reg rob_exception_21; // @[rob.scala:312:28]
reg rob_exception_22; // @[rob.scala:312:28]
reg rob_exception_23; // @[rob.scala:312:28]
reg rob_exception_24; // @[rob.scala:312:28]
reg rob_exception_25; // @[rob.scala:312:28]
reg rob_exception_26; // @[rob.scala:312:28]
reg rob_exception_27; // @[rob.scala:312:28]
reg rob_exception_28; // @[rob.scala:312:28]
reg rob_exception_29; // @[rob.scala:312:28]
reg rob_exception_30; // @[rob.scala:312:28]
reg rob_exception_31; // @[rob.scala:312:28]
reg rob_predicated_0; // @[rob.scala:313:29]
reg rob_predicated_1; // @[rob.scala:313:29]
reg rob_predicated_2; // @[rob.scala:313:29]
reg rob_predicated_3; // @[rob.scala:313:29]
reg rob_predicated_4; // @[rob.scala:313:29]
reg rob_predicated_5; // @[rob.scala:313:29]
reg rob_predicated_6; // @[rob.scala:313:29]
reg rob_predicated_7; // @[rob.scala:313:29]
reg rob_predicated_8; // @[rob.scala:313:29]
reg rob_predicated_9; // @[rob.scala:313:29]
reg rob_predicated_10; // @[rob.scala:313:29]
reg rob_predicated_11; // @[rob.scala:313:29]
reg rob_predicated_12; // @[rob.scala:313:29]
reg rob_predicated_13; // @[rob.scala:313:29]
reg rob_predicated_14; // @[rob.scala:313:29]
reg rob_predicated_15; // @[rob.scala:313:29]
reg rob_predicated_16; // @[rob.scala:313:29]
reg rob_predicated_17; // @[rob.scala:313:29]
reg rob_predicated_18; // @[rob.scala:313:29]
reg rob_predicated_19; // @[rob.scala:313:29]
reg rob_predicated_20; // @[rob.scala:313:29]
reg rob_predicated_21; // @[rob.scala:313:29]
reg rob_predicated_22; // @[rob.scala:313:29]
reg rob_predicated_23; // @[rob.scala:313:29]
reg rob_predicated_24; // @[rob.scala:313:29]
reg rob_predicated_25; // @[rob.scala:313:29]
reg rob_predicated_26; // @[rob.scala:313:29]
reg rob_predicated_27; // @[rob.scala:313:29]
reg rob_predicated_28; // @[rob.scala:313:29]
reg rob_predicated_29; // @[rob.scala:313:29]
reg rob_predicated_30; // @[rob.scala:313:29]
reg rob_predicated_31; // @[rob.scala:313:29]
wire [31:0] _GEN = {{rob_val_31}, {rob_val_30}, {rob_val_29}, {rob_val_28}, {rob_val_27}, {rob_val_26}, {rob_val_25}, {rob_val_24}, {rob_val_23}, {rob_val_22}, {rob_val_21}, {rob_val_20}, {rob_val_19}, {rob_val_18}, {rob_val_17}, {rob_val_16}, {rob_val_15}, {rob_val_14}, {rob_val_13}, {rob_val_12}, {rob_val_11}, {rob_val_10}, {rob_val_9}, {rob_val_8}, {rob_val_7}, {rob_val_6}, {rob_val_5}, {rob_val_4}, {rob_val_3}, {rob_val_2}, {rob_val_1}, {rob_val_0}}; // @[rob.scala:308:32, :324:31]
assign rob_tail_vals_0 = _GEN[rob_tail]; // @[rob.scala:227:29, :248:33, :324:31]
wire _rob_bsy_T = io_enq_uops_0_is_fence_0 | io_enq_uops_0_is_fencei_0; // @[rob.scala:211:7, :325:60]
wire _rob_bsy_T_1 = ~_rob_bsy_T; // @[rob.scala:325:{34,60}]
wire _rob_unsafe_T = ~io_enq_uops_0_is_fence_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_1 = io_enq_uops_0_uses_stq_0 & _rob_unsafe_T; // @[rob.scala:211:7]
wire _rob_unsafe_T_2 = io_enq_uops_0_uses_ldq_0 | _rob_unsafe_T_1; // @[rob.scala:211:7]
wire _rob_unsafe_T_3 = _rob_unsafe_T_2 | io_enq_uops_0_is_br_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_4 = _rob_unsafe_T_3 | io_enq_uops_0_is_jalr_0; // @[rob.scala:211:7]
wire [31:0] _GEN_0 = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[rob.scala:309:28, :363:26]
wire _GEN_1 = io_lxcpt_valid_0 & io_lxcpt_bits_cause_0 != 5'h10 & ~reset; // @[rob.scala:211:7, :392:{33,66}, :394:15]
wire [31:0] _GEN_2 = {{rob_unsafe_31}, {rob_unsafe_30}, {rob_unsafe_29}, {rob_unsafe_28}, {rob_unsafe_27}, {rob_unsafe_26}, {rob_unsafe_25}, {rob_unsafe_24}, {rob_unsafe_23}, {rob_unsafe_22}, {rob_unsafe_21}, {rob_unsafe_20}, {rob_unsafe_19}, {rob_unsafe_18}, {rob_unsafe_17}, {rob_unsafe_16}, {rob_unsafe_15}, {rob_unsafe_14}, {rob_unsafe_13}, {rob_unsafe_12}, {rob_unsafe_11}, {rob_unsafe_10}, {rob_unsafe_9}, {rob_unsafe_8}, {rob_unsafe_7}, {rob_unsafe_6}, {rob_unsafe_5}, {rob_unsafe_4}, {rob_unsafe_3}, {rob_unsafe_2}, {rob_unsafe_1}, {rob_unsafe_0}}; // @[rob.scala:310:28, :394:15]
assign rob_head_vals_0 = _GEN[rob_head]; // @[rob.scala:223:29, :247:33, :324:31, :402:49]
wire [31:0] _GEN_3 = {{rob_exception_31}, {rob_exception_30}, {rob_exception_29}, {rob_exception_28}, {rob_exception_27}, {rob_exception_26}, {rob_exception_25}, {rob_exception_24}, {rob_exception_23}, {rob_exception_22}, {rob_exception_21}, {rob_exception_20}, {rob_exception_19}, {rob_exception_18}, {rob_exception_17}, {rob_exception_16}, {rob_exception_15}, {rob_exception_14}, {rob_exception_13}, {rob_exception_12}, {rob_exception_11}, {rob_exception_10}, {rob_exception_9}, {rob_exception_8}, {rob_exception_7}, {rob_exception_6}, {rob_exception_5}, {rob_exception_4}, {rob_exception_3}, {rob_exception_2}, {rob_exception_1}, {rob_exception_0}}; // @[rob.scala:312:28, :402:49]
assign _can_throw_exception_0_T = rob_head_vals_0 & _GEN_3[rob_head]; // @[rob.scala:223:29, :247:33, :402:49]
assign can_throw_exception_0 = _can_throw_exception_0_T; // @[rob.scala:244:33, :402:49]
wire _can_commit_0_T = ~_GEN_0[rob_head]; // @[rob.scala:223:29, :363:26, :408:43]
wire _can_commit_0_T_1 = rob_head_vals_0 & _can_commit_0_T; // @[rob.scala:247:33, :408:{40,43}]
wire _can_commit_0_T_2 = ~io_csr_stall_0; // @[rob.scala:211:7, :408:67]
assign _can_commit_0_T_3 = _can_commit_0_T_1 & _can_commit_0_T_2; // @[rob.scala:408:{40,64,67}]
assign can_commit_0 = _can_commit_0_T_3; // @[rob.scala:243:33, :408:64]
wire [31:0] _GEN_4 = {{rob_predicated_31}, {rob_predicated_30}, {rob_predicated_29}, {rob_predicated_28}, {rob_predicated_27}, {rob_predicated_26}, {rob_predicated_25}, {rob_predicated_24}, {rob_predicated_23}, {rob_predicated_22}, {rob_predicated_21}, {rob_predicated_20}, {rob_predicated_19}, {rob_predicated_18}, {rob_predicated_17}, {rob_predicated_16}, {rob_predicated_15}, {rob_predicated_14}, {rob_predicated_13}, {rob_predicated_12}, {rob_predicated_11}, {rob_predicated_10}, {rob_predicated_9}, {rob_predicated_8}, {rob_predicated_7}, {rob_predicated_6}, {rob_predicated_5}, {rob_predicated_4}, {rob_predicated_3}, {rob_predicated_2}, {rob_predicated_1}, {rob_predicated_0}}; // @[rob.scala:313:29, :414:51]
wire _io_commit_arch_valids_0_T = ~_GEN_4[com_idx]; // @[rob.scala:235:20, :414:51]
assign _io_commit_arch_valids_0_T_1 = will_commit_0 & _io_commit_arch_valids_0_T; // @[rob.scala:242:33, :414:{48,51}]
assign io_commit_arch_valids_0_0 = _io_commit_arch_valids_0_T_1; // @[rob.scala:211:7, :414:48]
wire [31:0][6:0] _GEN_5 = {{rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_uopc_0 = _GEN_5[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_6 = {{rob_uop_31_inst}, {rob_uop_30_inst}, {rob_uop_29_inst}, {rob_uop_28_inst}, {rob_uop_27_inst}, {rob_uop_26_inst}, {rob_uop_25_inst}, {rob_uop_24_inst}, {rob_uop_23_inst}, {rob_uop_22_inst}, {rob_uop_21_inst}, {rob_uop_20_inst}, {rob_uop_19_inst}, {rob_uop_18_inst}, {rob_uop_17_inst}, {rob_uop_16_inst}, {rob_uop_15_inst}, {rob_uop_14_inst}, {rob_uop_13_inst}, {rob_uop_12_inst}, {rob_uop_11_inst}, {rob_uop_10_inst}, {rob_uop_9_inst}, {rob_uop_8_inst}, {rob_uop_7_inst}, {rob_uop_6_inst}, {rob_uop_5_inst}, {rob_uop_4_inst}, {rob_uop_3_inst}, {rob_uop_2_inst}, {rob_uop_1_inst}, {rob_uop_0_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_inst_0 = _GEN_6[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_7 = {{rob_uop_31_debug_inst}, {rob_uop_30_debug_inst}, {rob_uop_29_debug_inst}, {rob_uop_28_debug_inst}, {rob_uop_27_debug_inst}, {rob_uop_26_debug_inst}, {rob_uop_25_debug_inst}, {rob_uop_24_debug_inst}, {rob_uop_23_debug_inst}, {rob_uop_22_debug_inst}, {rob_uop_21_debug_inst}, {rob_uop_20_debug_inst}, {rob_uop_19_debug_inst}, {rob_uop_18_debug_inst}, {rob_uop_17_debug_inst}, {rob_uop_16_debug_inst}, {rob_uop_15_debug_inst}, {rob_uop_14_debug_inst}, {rob_uop_13_debug_inst}, {rob_uop_12_debug_inst}, {rob_uop_11_debug_inst}, {rob_uop_10_debug_inst}, {rob_uop_9_debug_inst}, {rob_uop_8_debug_inst}, {rob_uop_7_debug_inst}, {rob_uop_6_debug_inst}, {rob_uop_5_debug_inst}, {rob_uop_4_debug_inst}, {rob_uop_3_debug_inst}, {rob_uop_2_debug_inst}, {rob_uop_1_debug_inst}, {rob_uop_0_debug_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_debug_inst_0 = _GEN_7[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_8 = {{rob_uop_31_is_rvc}, {rob_uop_30_is_rvc}, {rob_uop_29_is_rvc}, {rob_uop_28_is_rvc}, {rob_uop_27_is_rvc}, {rob_uop_26_is_rvc}, {rob_uop_25_is_rvc}, {rob_uop_24_is_rvc}, {rob_uop_23_is_rvc}, {rob_uop_22_is_rvc}, {rob_uop_21_is_rvc}, {rob_uop_20_is_rvc}, {rob_uop_19_is_rvc}, {rob_uop_18_is_rvc}, {rob_uop_17_is_rvc}, {rob_uop_16_is_rvc}, {rob_uop_15_is_rvc}, {rob_uop_14_is_rvc}, {rob_uop_13_is_rvc}, {rob_uop_12_is_rvc}, {rob_uop_11_is_rvc}, {rob_uop_10_is_rvc}, {rob_uop_9_is_rvc}, {rob_uop_8_is_rvc}, {rob_uop_7_is_rvc}, {rob_uop_6_is_rvc}, {rob_uop_5_is_rvc}, {rob_uop_4_is_rvc}, {rob_uop_3_is_rvc}, {rob_uop_2_is_rvc}, {rob_uop_1_is_rvc}, {rob_uop_0_is_rvc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_rvc_0 = _GEN_8[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][39:0] _GEN_9 = {{rob_uop_31_debug_pc}, {rob_uop_30_debug_pc}, {rob_uop_29_debug_pc}, {rob_uop_28_debug_pc}, {rob_uop_27_debug_pc}, {rob_uop_26_debug_pc}, {rob_uop_25_debug_pc}, {rob_uop_24_debug_pc}, {rob_uop_23_debug_pc}, {rob_uop_22_debug_pc}, {rob_uop_21_debug_pc}, {rob_uop_20_debug_pc}, {rob_uop_19_debug_pc}, {rob_uop_18_debug_pc}, {rob_uop_17_debug_pc}, {rob_uop_16_debug_pc}, {rob_uop_15_debug_pc}, {rob_uop_14_debug_pc}, {rob_uop_13_debug_pc}, {rob_uop_12_debug_pc}, {rob_uop_11_debug_pc}, {rob_uop_10_debug_pc}, {rob_uop_9_debug_pc}, {rob_uop_8_debug_pc}, {rob_uop_7_debug_pc}, {rob_uop_6_debug_pc}, {rob_uop_5_debug_pc}, {rob_uop_4_debug_pc}, {rob_uop_3_debug_pc}, {rob_uop_2_debug_pc}, {rob_uop_1_debug_pc}, {rob_uop_0_debug_pc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_debug_pc_0 = _GEN_9[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_10 = {{rob_uop_31_iq_type}, {rob_uop_30_iq_type}, {rob_uop_29_iq_type}, {rob_uop_28_iq_type}, {rob_uop_27_iq_type}, {rob_uop_26_iq_type}, {rob_uop_25_iq_type}, {rob_uop_24_iq_type}, {rob_uop_23_iq_type}, {rob_uop_22_iq_type}, {rob_uop_21_iq_type}, {rob_uop_20_iq_type}, {rob_uop_19_iq_type}, {rob_uop_18_iq_type}, {rob_uop_17_iq_type}, {rob_uop_16_iq_type}, {rob_uop_15_iq_type}, {rob_uop_14_iq_type}, {rob_uop_13_iq_type}, {rob_uop_12_iq_type}, {rob_uop_11_iq_type}, {rob_uop_10_iq_type}, {rob_uop_9_iq_type}, {rob_uop_8_iq_type}, {rob_uop_7_iq_type}, {rob_uop_6_iq_type}, {rob_uop_5_iq_type}, {rob_uop_4_iq_type}, {rob_uop_3_iq_type}, {rob_uop_2_iq_type}, {rob_uop_1_iq_type}, {rob_uop_0_iq_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iq_type_0 = _GEN_10[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][9:0] _GEN_11 = {{rob_uop_31_fu_code}, {rob_uop_30_fu_code}, {rob_uop_29_fu_code}, {rob_uop_28_fu_code}, {rob_uop_27_fu_code}, {rob_uop_26_fu_code}, {rob_uop_25_fu_code}, {rob_uop_24_fu_code}, {rob_uop_23_fu_code}, {rob_uop_22_fu_code}, {rob_uop_21_fu_code}, {rob_uop_20_fu_code}, {rob_uop_19_fu_code}, {rob_uop_18_fu_code}, {rob_uop_17_fu_code}, {rob_uop_16_fu_code}, {rob_uop_15_fu_code}, {rob_uop_14_fu_code}, {rob_uop_13_fu_code}, {rob_uop_12_fu_code}, {rob_uop_11_fu_code}, {rob_uop_10_fu_code}, {rob_uop_9_fu_code}, {rob_uop_8_fu_code}, {rob_uop_7_fu_code}, {rob_uop_6_fu_code}, {rob_uop_5_fu_code}, {rob_uop_4_fu_code}, {rob_uop_3_fu_code}, {rob_uop_2_fu_code}, {rob_uop_1_fu_code}, {rob_uop_0_fu_code}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_fu_code_0 = _GEN_11[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_12 = {{rob_uop_31_ctrl_br_type}, {rob_uop_30_ctrl_br_type}, {rob_uop_29_ctrl_br_type}, {rob_uop_28_ctrl_br_type}, {rob_uop_27_ctrl_br_type}, {rob_uop_26_ctrl_br_type}, {rob_uop_25_ctrl_br_type}, {rob_uop_24_ctrl_br_type}, {rob_uop_23_ctrl_br_type}, {rob_uop_22_ctrl_br_type}, {rob_uop_21_ctrl_br_type}, {rob_uop_20_ctrl_br_type}, {rob_uop_19_ctrl_br_type}, {rob_uop_18_ctrl_br_type}, {rob_uop_17_ctrl_br_type}, {rob_uop_16_ctrl_br_type}, {rob_uop_15_ctrl_br_type}, {rob_uop_14_ctrl_br_type}, {rob_uop_13_ctrl_br_type}, {rob_uop_12_ctrl_br_type}, {rob_uop_11_ctrl_br_type}, {rob_uop_10_ctrl_br_type}, {rob_uop_9_ctrl_br_type}, {rob_uop_8_ctrl_br_type}, {rob_uop_7_ctrl_br_type}, {rob_uop_6_ctrl_br_type}, {rob_uop_5_ctrl_br_type}, {rob_uop_4_ctrl_br_type}, {rob_uop_3_ctrl_br_type}, {rob_uop_2_ctrl_br_type}, {rob_uop_1_ctrl_br_type}, {rob_uop_0_ctrl_br_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_br_type_0 = _GEN_12[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_13 = {{rob_uop_31_ctrl_op1_sel}, {rob_uop_30_ctrl_op1_sel}, {rob_uop_29_ctrl_op1_sel}, {rob_uop_28_ctrl_op1_sel}, {rob_uop_27_ctrl_op1_sel}, {rob_uop_26_ctrl_op1_sel}, {rob_uop_25_ctrl_op1_sel}, {rob_uop_24_ctrl_op1_sel}, {rob_uop_23_ctrl_op1_sel}, {rob_uop_22_ctrl_op1_sel}, {rob_uop_21_ctrl_op1_sel}, {rob_uop_20_ctrl_op1_sel}, {rob_uop_19_ctrl_op1_sel}, {rob_uop_18_ctrl_op1_sel}, {rob_uop_17_ctrl_op1_sel}, {rob_uop_16_ctrl_op1_sel}, {rob_uop_15_ctrl_op1_sel}, {rob_uop_14_ctrl_op1_sel}, {rob_uop_13_ctrl_op1_sel}, {rob_uop_12_ctrl_op1_sel}, {rob_uop_11_ctrl_op1_sel}, {rob_uop_10_ctrl_op1_sel}, {rob_uop_9_ctrl_op1_sel}, {rob_uop_8_ctrl_op1_sel}, {rob_uop_7_ctrl_op1_sel}, {rob_uop_6_ctrl_op1_sel}, {rob_uop_5_ctrl_op1_sel}, {rob_uop_4_ctrl_op1_sel}, {rob_uop_3_ctrl_op1_sel}, {rob_uop_2_ctrl_op1_sel}, {rob_uop_1_ctrl_op1_sel}, {rob_uop_0_ctrl_op1_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_op1_sel_0 = _GEN_13[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_14 = {{rob_uop_31_ctrl_op2_sel}, {rob_uop_30_ctrl_op2_sel}, {rob_uop_29_ctrl_op2_sel}, {rob_uop_28_ctrl_op2_sel}, {rob_uop_27_ctrl_op2_sel}, {rob_uop_26_ctrl_op2_sel}, {rob_uop_25_ctrl_op2_sel}, {rob_uop_24_ctrl_op2_sel}, {rob_uop_23_ctrl_op2_sel}, {rob_uop_22_ctrl_op2_sel}, {rob_uop_21_ctrl_op2_sel}, {rob_uop_20_ctrl_op2_sel}, {rob_uop_19_ctrl_op2_sel}, {rob_uop_18_ctrl_op2_sel}, {rob_uop_17_ctrl_op2_sel}, {rob_uop_16_ctrl_op2_sel}, {rob_uop_15_ctrl_op2_sel}, {rob_uop_14_ctrl_op2_sel}, {rob_uop_13_ctrl_op2_sel}, {rob_uop_12_ctrl_op2_sel}, {rob_uop_11_ctrl_op2_sel}, {rob_uop_10_ctrl_op2_sel}, {rob_uop_9_ctrl_op2_sel}, {rob_uop_8_ctrl_op2_sel}, {rob_uop_7_ctrl_op2_sel}, {rob_uop_6_ctrl_op2_sel}, {rob_uop_5_ctrl_op2_sel}, {rob_uop_4_ctrl_op2_sel}, {rob_uop_3_ctrl_op2_sel}, {rob_uop_2_ctrl_op2_sel}, {rob_uop_1_ctrl_op2_sel}, {rob_uop_0_ctrl_op2_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_op2_sel_0 = _GEN_14[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_15 = {{rob_uop_31_ctrl_imm_sel}, {rob_uop_30_ctrl_imm_sel}, {rob_uop_29_ctrl_imm_sel}, {rob_uop_28_ctrl_imm_sel}, {rob_uop_27_ctrl_imm_sel}, {rob_uop_26_ctrl_imm_sel}, {rob_uop_25_ctrl_imm_sel}, {rob_uop_24_ctrl_imm_sel}, {rob_uop_23_ctrl_imm_sel}, {rob_uop_22_ctrl_imm_sel}, {rob_uop_21_ctrl_imm_sel}, {rob_uop_20_ctrl_imm_sel}, {rob_uop_19_ctrl_imm_sel}, {rob_uop_18_ctrl_imm_sel}, {rob_uop_17_ctrl_imm_sel}, {rob_uop_16_ctrl_imm_sel}, {rob_uop_15_ctrl_imm_sel}, {rob_uop_14_ctrl_imm_sel}, {rob_uop_13_ctrl_imm_sel}, {rob_uop_12_ctrl_imm_sel}, {rob_uop_11_ctrl_imm_sel}, {rob_uop_10_ctrl_imm_sel}, {rob_uop_9_ctrl_imm_sel}, {rob_uop_8_ctrl_imm_sel}, {rob_uop_7_ctrl_imm_sel}, {rob_uop_6_ctrl_imm_sel}, {rob_uop_5_ctrl_imm_sel}, {rob_uop_4_ctrl_imm_sel}, {rob_uop_3_ctrl_imm_sel}, {rob_uop_2_ctrl_imm_sel}, {rob_uop_1_ctrl_imm_sel}, {rob_uop_0_ctrl_imm_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_imm_sel_0 = _GEN_15[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_16 = {{rob_uop_31_ctrl_op_fcn}, {rob_uop_30_ctrl_op_fcn}, {rob_uop_29_ctrl_op_fcn}, {rob_uop_28_ctrl_op_fcn}, {rob_uop_27_ctrl_op_fcn}, {rob_uop_26_ctrl_op_fcn}, {rob_uop_25_ctrl_op_fcn}, {rob_uop_24_ctrl_op_fcn}, {rob_uop_23_ctrl_op_fcn}, {rob_uop_22_ctrl_op_fcn}, {rob_uop_21_ctrl_op_fcn}, {rob_uop_20_ctrl_op_fcn}, {rob_uop_19_ctrl_op_fcn}, {rob_uop_18_ctrl_op_fcn}, {rob_uop_17_ctrl_op_fcn}, {rob_uop_16_ctrl_op_fcn}, {rob_uop_15_ctrl_op_fcn}, {rob_uop_14_ctrl_op_fcn}, {rob_uop_13_ctrl_op_fcn}, {rob_uop_12_ctrl_op_fcn}, {rob_uop_11_ctrl_op_fcn}, {rob_uop_10_ctrl_op_fcn}, {rob_uop_9_ctrl_op_fcn}, {rob_uop_8_ctrl_op_fcn}, {rob_uop_7_ctrl_op_fcn}, {rob_uop_6_ctrl_op_fcn}, {rob_uop_5_ctrl_op_fcn}, {rob_uop_4_ctrl_op_fcn}, {rob_uop_3_ctrl_op_fcn}, {rob_uop_2_ctrl_op_fcn}, {rob_uop_1_ctrl_op_fcn}, {rob_uop_0_ctrl_op_fcn}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_op_fcn_0 = _GEN_16[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_17 = {{rob_uop_31_ctrl_fcn_dw}, {rob_uop_30_ctrl_fcn_dw}, {rob_uop_29_ctrl_fcn_dw}, {rob_uop_28_ctrl_fcn_dw}, {rob_uop_27_ctrl_fcn_dw}, {rob_uop_26_ctrl_fcn_dw}, {rob_uop_25_ctrl_fcn_dw}, {rob_uop_24_ctrl_fcn_dw}, {rob_uop_23_ctrl_fcn_dw}, {rob_uop_22_ctrl_fcn_dw}, {rob_uop_21_ctrl_fcn_dw}, {rob_uop_20_ctrl_fcn_dw}, {rob_uop_19_ctrl_fcn_dw}, {rob_uop_18_ctrl_fcn_dw}, {rob_uop_17_ctrl_fcn_dw}, {rob_uop_16_ctrl_fcn_dw}, {rob_uop_15_ctrl_fcn_dw}, {rob_uop_14_ctrl_fcn_dw}, {rob_uop_13_ctrl_fcn_dw}, {rob_uop_12_ctrl_fcn_dw}, {rob_uop_11_ctrl_fcn_dw}, {rob_uop_10_ctrl_fcn_dw}, {rob_uop_9_ctrl_fcn_dw}, {rob_uop_8_ctrl_fcn_dw}, {rob_uop_7_ctrl_fcn_dw}, {rob_uop_6_ctrl_fcn_dw}, {rob_uop_5_ctrl_fcn_dw}, {rob_uop_4_ctrl_fcn_dw}, {rob_uop_3_ctrl_fcn_dw}, {rob_uop_2_ctrl_fcn_dw}, {rob_uop_1_ctrl_fcn_dw}, {rob_uop_0_ctrl_fcn_dw}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_fcn_dw_0 = _GEN_17[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_18 = {{rob_uop_31_ctrl_csr_cmd}, {rob_uop_30_ctrl_csr_cmd}, {rob_uop_29_ctrl_csr_cmd}, {rob_uop_28_ctrl_csr_cmd}, {rob_uop_27_ctrl_csr_cmd}, {rob_uop_26_ctrl_csr_cmd}, {rob_uop_25_ctrl_csr_cmd}, {rob_uop_24_ctrl_csr_cmd}, {rob_uop_23_ctrl_csr_cmd}, {rob_uop_22_ctrl_csr_cmd}, {rob_uop_21_ctrl_csr_cmd}, {rob_uop_20_ctrl_csr_cmd}, {rob_uop_19_ctrl_csr_cmd}, {rob_uop_18_ctrl_csr_cmd}, {rob_uop_17_ctrl_csr_cmd}, {rob_uop_16_ctrl_csr_cmd}, {rob_uop_15_ctrl_csr_cmd}, {rob_uop_14_ctrl_csr_cmd}, {rob_uop_13_ctrl_csr_cmd}, {rob_uop_12_ctrl_csr_cmd}, {rob_uop_11_ctrl_csr_cmd}, {rob_uop_10_ctrl_csr_cmd}, {rob_uop_9_ctrl_csr_cmd}, {rob_uop_8_ctrl_csr_cmd}, {rob_uop_7_ctrl_csr_cmd}, {rob_uop_6_ctrl_csr_cmd}, {rob_uop_5_ctrl_csr_cmd}, {rob_uop_4_ctrl_csr_cmd}, {rob_uop_3_ctrl_csr_cmd}, {rob_uop_2_ctrl_csr_cmd}, {rob_uop_1_ctrl_csr_cmd}, {rob_uop_0_ctrl_csr_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_csr_cmd_0 = _GEN_18[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_19 = {{rob_uop_31_ctrl_is_load}, {rob_uop_30_ctrl_is_load}, {rob_uop_29_ctrl_is_load}, {rob_uop_28_ctrl_is_load}, {rob_uop_27_ctrl_is_load}, {rob_uop_26_ctrl_is_load}, {rob_uop_25_ctrl_is_load}, {rob_uop_24_ctrl_is_load}, {rob_uop_23_ctrl_is_load}, {rob_uop_22_ctrl_is_load}, {rob_uop_21_ctrl_is_load}, {rob_uop_20_ctrl_is_load}, {rob_uop_19_ctrl_is_load}, {rob_uop_18_ctrl_is_load}, {rob_uop_17_ctrl_is_load}, {rob_uop_16_ctrl_is_load}, {rob_uop_15_ctrl_is_load}, {rob_uop_14_ctrl_is_load}, {rob_uop_13_ctrl_is_load}, {rob_uop_12_ctrl_is_load}, {rob_uop_11_ctrl_is_load}, {rob_uop_10_ctrl_is_load}, {rob_uop_9_ctrl_is_load}, {rob_uop_8_ctrl_is_load}, {rob_uop_7_ctrl_is_load}, {rob_uop_6_ctrl_is_load}, {rob_uop_5_ctrl_is_load}, {rob_uop_4_ctrl_is_load}, {rob_uop_3_ctrl_is_load}, {rob_uop_2_ctrl_is_load}, {rob_uop_1_ctrl_is_load}, {rob_uop_0_ctrl_is_load}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_is_load_0 = _GEN_19[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_20 = {{rob_uop_31_ctrl_is_sta}, {rob_uop_30_ctrl_is_sta}, {rob_uop_29_ctrl_is_sta}, {rob_uop_28_ctrl_is_sta}, {rob_uop_27_ctrl_is_sta}, {rob_uop_26_ctrl_is_sta}, {rob_uop_25_ctrl_is_sta}, {rob_uop_24_ctrl_is_sta}, {rob_uop_23_ctrl_is_sta}, {rob_uop_22_ctrl_is_sta}, {rob_uop_21_ctrl_is_sta}, {rob_uop_20_ctrl_is_sta}, {rob_uop_19_ctrl_is_sta}, {rob_uop_18_ctrl_is_sta}, {rob_uop_17_ctrl_is_sta}, {rob_uop_16_ctrl_is_sta}, {rob_uop_15_ctrl_is_sta}, {rob_uop_14_ctrl_is_sta}, {rob_uop_13_ctrl_is_sta}, {rob_uop_12_ctrl_is_sta}, {rob_uop_11_ctrl_is_sta}, {rob_uop_10_ctrl_is_sta}, {rob_uop_9_ctrl_is_sta}, {rob_uop_8_ctrl_is_sta}, {rob_uop_7_ctrl_is_sta}, {rob_uop_6_ctrl_is_sta}, {rob_uop_5_ctrl_is_sta}, {rob_uop_4_ctrl_is_sta}, {rob_uop_3_ctrl_is_sta}, {rob_uop_2_ctrl_is_sta}, {rob_uop_1_ctrl_is_sta}, {rob_uop_0_ctrl_is_sta}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_is_sta_0 = _GEN_20[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_21 = {{rob_uop_31_ctrl_is_std}, {rob_uop_30_ctrl_is_std}, {rob_uop_29_ctrl_is_std}, {rob_uop_28_ctrl_is_std}, {rob_uop_27_ctrl_is_std}, {rob_uop_26_ctrl_is_std}, {rob_uop_25_ctrl_is_std}, {rob_uop_24_ctrl_is_std}, {rob_uop_23_ctrl_is_std}, {rob_uop_22_ctrl_is_std}, {rob_uop_21_ctrl_is_std}, {rob_uop_20_ctrl_is_std}, {rob_uop_19_ctrl_is_std}, {rob_uop_18_ctrl_is_std}, {rob_uop_17_ctrl_is_std}, {rob_uop_16_ctrl_is_std}, {rob_uop_15_ctrl_is_std}, {rob_uop_14_ctrl_is_std}, {rob_uop_13_ctrl_is_std}, {rob_uop_12_ctrl_is_std}, {rob_uop_11_ctrl_is_std}, {rob_uop_10_ctrl_is_std}, {rob_uop_9_ctrl_is_std}, {rob_uop_8_ctrl_is_std}, {rob_uop_7_ctrl_is_std}, {rob_uop_6_ctrl_is_std}, {rob_uop_5_ctrl_is_std}, {rob_uop_4_ctrl_is_std}, {rob_uop_3_ctrl_is_std}, {rob_uop_2_ctrl_is_std}, {rob_uop_1_ctrl_is_std}, {rob_uop_0_ctrl_is_std}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_is_std_0 = _GEN_21[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_22 = {{rob_uop_31_iw_state}, {rob_uop_30_iw_state}, {rob_uop_29_iw_state}, {rob_uop_28_iw_state}, {rob_uop_27_iw_state}, {rob_uop_26_iw_state}, {rob_uop_25_iw_state}, {rob_uop_24_iw_state}, {rob_uop_23_iw_state}, {rob_uop_22_iw_state}, {rob_uop_21_iw_state}, {rob_uop_20_iw_state}, {rob_uop_19_iw_state}, {rob_uop_18_iw_state}, {rob_uop_17_iw_state}, {rob_uop_16_iw_state}, {rob_uop_15_iw_state}, {rob_uop_14_iw_state}, {rob_uop_13_iw_state}, {rob_uop_12_iw_state}, {rob_uop_11_iw_state}, {rob_uop_10_iw_state}, {rob_uop_9_iw_state}, {rob_uop_8_iw_state}, {rob_uop_7_iw_state}, {rob_uop_6_iw_state}, {rob_uop_5_iw_state}, {rob_uop_4_iw_state}, {rob_uop_3_iw_state}, {rob_uop_2_iw_state}, {rob_uop_1_iw_state}, {rob_uop_0_iw_state}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iw_state_0 = _GEN_22[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_23 = {{rob_uop_31_iw_p1_poisoned}, {rob_uop_30_iw_p1_poisoned}, {rob_uop_29_iw_p1_poisoned}, {rob_uop_28_iw_p1_poisoned}, {rob_uop_27_iw_p1_poisoned}, {rob_uop_26_iw_p1_poisoned}, {rob_uop_25_iw_p1_poisoned}, {rob_uop_24_iw_p1_poisoned}, {rob_uop_23_iw_p1_poisoned}, {rob_uop_22_iw_p1_poisoned}, {rob_uop_21_iw_p1_poisoned}, {rob_uop_20_iw_p1_poisoned}, {rob_uop_19_iw_p1_poisoned}, {rob_uop_18_iw_p1_poisoned}, {rob_uop_17_iw_p1_poisoned}, {rob_uop_16_iw_p1_poisoned}, {rob_uop_15_iw_p1_poisoned}, {rob_uop_14_iw_p1_poisoned}, {rob_uop_13_iw_p1_poisoned}, {rob_uop_12_iw_p1_poisoned}, {rob_uop_11_iw_p1_poisoned}, {rob_uop_10_iw_p1_poisoned}, {rob_uop_9_iw_p1_poisoned}, {rob_uop_8_iw_p1_poisoned}, {rob_uop_7_iw_p1_poisoned}, {rob_uop_6_iw_p1_poisoned}, {rob_uop_5_iw_p1_poisoned}, {rob_uop_4_iw_p1_poisoned}, {rob_uop_3_iw_p1_poisoned}, {rob_uop_2_iw_p1_poisoned}, {rob_uop_1_iw_p1_poisoned}, {rob_uop_0_iw_p1_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iw_p1_poisoned_0 = _GEN_23[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_24 = {{rob_uop_31_iw_p2_poisoned}, {rob_uop_30_iw_p2_poisoned}, {rob_uop_29_iw_p2_poisoned}, {rob_uop_28_iw_p2_poisoned}, {rob_uop_27_iw_p2_poisoned}, {rob_uop_26_iw_p2_poisoned}, {rob_uop_25_iw_p2_poisoned}, {rob_uop_24_iw_p2_poisoned}, {rob_uop_23_iw_p2_poisoned}, {rob_uop_22_iw_p2_poisoned}, {rob_uop_21_iw_p2_poisoned}, {rob_uop_20_iw_p2_poisoned}, {rob_uop_19_iw_p2_poisoned}, {rob_uop_18_iw_p2_poisoned}, {rob_uop_17_iw_p2_poisoned}, {rob_uop_16_iw_p2_poisoned}, {rob_uop_15_iw_p2_poisoned}, {rob_uop_14_iw_p2_poisoned}, {rob_uop_13_iw_p2_poisoned}, {rob_uop_12_iw_p2_poisoned}, {rob_uop_11_iw_p2_poisoned}, {rob_uop_10_iw_p2_poisoned}, {rob_uop_9_iw_p2_poisoned}, {rob_uop_8_iw_p2_poisoned}, {rob_uop_7_iw_p2_poisoned}, {rob_uop_6_iw_p2_poisoned}, {rob_uop_5_iw_p2_poisoned}, {rob_uop_4_iw_p2_poisoned}, {rob_uop_3_iw_p2_poisoned}, {rob_uop_2_iw_p2_poisoned}, {rob_uop_1_iw_p2_poisoned}, {rob_uop_0_iw_p2_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iw_p2_poisoned_0 = _GEN_24[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_25 = {{rob_uop_31_is_br}, {rob_uop_30_is_br}, {rob_uop_29_is_br}, {rob_uop_28_is_br}, {rob_uop_27_is_br}, {rob_uop_26_is_br}, {rob_uop_25_is_br}, {rob_uop_24_is_br}, {rob_uop_23_is_br}, {rob_uop_22_is_br}, {rob_uop_21_is_br}, {rob_uop_20_is_br}, {rob_uop_19_is_br}, {rob_uop_18_is_br}, {rob_uop_17_is_br}, {rob_uop_16_is_br}, {rob_uop_15_is_br}, {rob_uop_14_is_br}, {rob_uop_13_is_br}, {rob_uop_12_is_br}, {rob_uop_11_is_br}, {rob_uop_10_is_br}, {rob_uop_9_is_br}, {rob_uop_8_is_br}, {rob_uop_7_is_br}, {rob_uop_6_is_br}, {rob_uop_5_is_br}, {rob_uop_4_is_br}, {rob_uop_3_is_br}, {rob_uop_2_is_br}, {rob_uop_1_is_br}, {rob_uop_0_is_br}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_br_0 = _GEN_25[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_26 = {{rob_uop_31_is_jalr}, {rob_uop_30_is_jalr}, {rob_uop_29_is_jalr}, {rob_uop_28_is_jalr}, {rob_uop_27_is_jalr}, {rob_uop_26_is_jalr}, {rob_uop_25_is_jalr}, {rob_uop_24_is_jalr}, {rob_uop_23_is_jalr}, {rob_uop_22_is_jalr}, {rob_uop_21_is_jalr}, {rob_uop_20_is_jalr}, {rob_uop_19_is_jalr}, {rob_uop_18_is_jalr}, {rob_uop_17_is_jalr}, {rob_uop_16_is_jalr}, {rob_uop_15_is_jalr}, {rob_uop_14_is_jalr}, {rob_uop_13_is_jalr}, {rob_uop_12_is_jalr}, {rob_uop_11_is_jalr}, {rob_uop_10_is_jalr}, {rob_uop_9_is_jalr}, {rob_uop_8_is_jalr}, {rob_uop_7_is_jalr}, {rob_uop_6_is_jalr}, {rob_uop_5_is_jalr}, {rob_uop_4_is_jalr}, {rob_uop_3_is_jalr}, {rob_uop_2_is_jalr}, {rob_uop_1_is_jalr}, {rob_uop_0_is_jalr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_jalr_0 = _GEN_26[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_27 = {{rob_uop_31_is_jal}, {rob_uop_30_is_jal}, {rob_uop_29_is_jal}, {rob_uop_28_is_jal}, {rob_uop_27_is_jal}, {rob_uop_26_is_jal}, {rob_uop_25_is_jal}, {rob_uop_24_is_jal}, {rob_uop_23_is_jal}, {rob_uop_22_is_jal}, {rob_uop_21_is_jal}, {rob_uop_20_is_jal}, {rob_uop_19_is_jal}, {rob_uop_18_is_jal}, {rob_uop_17_is_jal}, {rob_uop_16_is_jal}, {rob_uop_15_is_jal}, {rob_uop_14_is_jal}, {rob_uop_13_is_jal}, {rob_uop_12_is_jal}, {rob_uop_11_is_jal}, {rob_uop_10_is_jal}, {rob_uop_9_is_jal}, {rob_uop_8_is_jal}, {rob_uop_7_is_jal}, {rob_uop_6_is_jal}, {rob_uop_5_is_jal}, {rob_uop_4_is_jal}, {rob_uop_3_is_jal}, {rob_uop_2_is_jal}, {rob_uop_1_is_jal}, {rob_uop_0_is_jal}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_jal_0 = _GEN_27[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_28 = {{rob_uop_31_is_sfb}, {rob_uop_30_is_sfb}, {rob_uop_29_is_sfb}, {rob_uop_28_is_sfb}, {rob_uop_27_is_sfb}, {rob_uop_26_is_sfb}, {rob_uop_25_is_sfb}, {rob_uop_24_is_sfb}, {rob_uop_23_is_sfb}, {rob_uop_22_is_sfb}, {rob_uop_21_is_sfb}, {rob_uop_20_is_sfb}, {rob_uop_19_is_sfb}, {rob_uop_18_is_sfb}, {rob_uop_17_is_sfb}, {rob_uop_16_is_sfb}, {rob_uop_15_is_sfb}, {rob_uop_14_is_sfb}, {rob_uop_13_is_sfb}, {rob_uop_12_is_sfb}, {rob_uop_11_is_sfb}, {rob_uop_10_is_sfb}, {rob_uop_9_is_sfb}, {rob_uop_8_is_sfb}, {rob_uop_7_is_sfb}, {rob_uop_6_is_sfb}, {rob_uop_5_is_sfb}, {rob_uop_4_is_sfb}, {rob_uop_3_is_sfb}, {rob_uop_2_is_sfb}, {rob_uop_1_is_sfb}, {rob_uop_0_is_sfb}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_sfb_0 = _GEN_28[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][7:0] _GEN_29 = {{rob_uop_31_br_mask}, {rob_uop_30_br_mask}, {rob_uop_29_br_mask}, {rob_uop_28_br_mask}, {rob_uop_27_br_mask}, {rob_uop_26_br_mask}, {rob_uop_25_br_mask}, {rob_uop_24_br_mask}, {rob_uop_23_br_mask}, {rob_uop_22_br_mask}, {rob_uop_21_br_mask}, {rob_uop_20_br_mask}, {rob_uop_19_br_mask}, {rob_uop_18_br_mask}, {rob_uop_17_br_mask}, {rob_uop_16_br_mask}, {rob_uop_15_br_mask}, {rob_uop_14_br_mask}, {rob_uop_13_br_mask}, {rob_uop_12_br_mask}, {rob_uop_11_br_mask}, {rob_uop_10_br_mask}, {rob_uop_9_br_mask}, {rob_uop_8_br_mask}, {rob_uop_7_br_mask}, {rob_uop_6_br_mask}, {rob_uop_5_br_mask}, {rob_uop_4_br_mask}, {rob_uop_3_br_mask}, {rob_uop_2_br_mask}, {rob_uop_1_br_mask}, {rob_uop_0_br_mask}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_br_mask_0 = _GEN_29[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_30 = {{rob_uop_31_br_tag}, {rob_uop_30_br_tag}, {rob_uop_29_br_tag}, {rob_uop_28_br_tag}, {rob_uop_27_br_tag}, {rob_uop_26_br_tag}, {rob_uop_25_br_tag}, {rob_uop_24_br_tag}, {rob_uop_23_br_tag}, {rob_uop_22_br_tag}, {rob_uop_21_br_tag}, {rob_uop_20_br_tag}, {rob_uop_19_br_tag}, {rob_uop_18_br_tag}, {rob_uop_17_br_tag}, {rob_uop_16_br_tag}, {rob_uop_15_br_tag}, {rob_uop_14_br_tag}, {rob_uop_13_br_tag}, {rob_uop_12_br_tag}, {rob_uop_11_br_tag}, {rob_uop_10_br_tag}, {rob_uop_9_br_tag}, {rob_uop_8_br_tag}, {rob_uop_7_br_tag}, {rob_uop_6_br_tag}, {rob_uop_5_br_tag}, {rob_uop_4_br_tag}, {rob_uop_3_br_tag}, {rob_uop_2_br_tag}, {rob_uop_1_br_tag}, {rob_uop_0_br_tag}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_br_tag_0 = _GEN_30[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_31 = {{rob_uop_31_ftq_idx}, {rob_uop_30_ftq_idx}, {rob_uop_29_ftq_idx}, {rob_uop_28_ftq_idx}, {rob_uop_27_ftq_idx}, {rob_uop_26_ftq_idx}, {rob_uop_25_ftq_idx}, {rob_uop_24_ftq_idx}, {rob_uop_23_ftq_idx}, {rob_uop_22_ftq_idx}, {rob_uop_21_ftq_idx}, {rob_uop_20_ftq_idx}, {rob_uop_19_ftq_idx}, {rob_uop_18_ftq_idx}, {rob_uop_17_ftq_idx}, {rob_uop_16_ftq_idx}, {rob_uop_15_ftq_idx}, {rob_uop_14_ftq_idx}, {rob_uop_13_ftq_idx}, {rob_uop_12_ftq_idx}, {rob_uop_11_ftq_idx}, {rob_uop_10_ftq_idx}, {rob_uop_9_ftq_idx}, {rob_uop_8_ftq_idx}, {rob_uop_7_ftq_idx}, {rob_uop_6_ftq_idx}, {rob_uop_5_ftq_idx}, {rob_uop_4_ftq_idx}, {rob_uop_3_ftq_idx}, {rob_uop_2_ftq_idx}, {rob_uop_1_ftq_idx}, {rob_uop_0_ftq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ftq_idx_0 = _GEN_31[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_32 = {{rob_uop_31_edge_inst}, {rob_uop_30_edge_inst}, {rob_uop_29_edge_inst}, {rob_uop_28_edge_inst}, {rob_uop_27_edge_inst}, {rob_uop_26_edge_inst}, {rob_uop_25_edge_inst}, {rob_uop_24_edge_inst}, {rob_uop_23_edge_inst}, {rob_uop_22_edge_inst}, {rob_uop_21_edge_inst}, {rob_uop_20_edge_inst}, {rob_uop_19_edge_inst}, {rob_uop_18_edge_inst}, {rob_uop_17_edge_inst}, {rob_uop_16_edge_inst}, {rob_uop_15_edge_inst}, {rob_uop_14_edge_inst}, {rob_uop_13_edge_inst}, {rob_uop_12_edge_inst}, {rob_uop_11_edge_inst}, {rob_uop_10_edge_inst}, {rob_uop_9_edge_inst}, {rob_uop_8_edge_inst}, {rob_uop_7_edge_inst}, {rob_uop_6_edge_inst}, {rob_uop_5_edge_inst}, {rob_uop_4_edge_inst}, {rob_uop_3_edge_inst}, {rob_uop_2_edge_inst}, {rob_uop_1_edge_inst}, {rob_uop_0_edge_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_edge_inst_0 = _GEN_32[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_33 = {{rob_uop_31_pc_lob}, {rob_uop_30_pc_lob}, {rob_uop_29_pc_lob}, {rob_uop_28_pc_lob}, {rob_uop_27_pc_lob}, {rob_uop_26_pc_lob}, {rob_uop_25_pc_lob}, {rob_uop_24_pc_lob}, {rob_uop_23_pc_lob}, {rob_uop_22_pc_lob}, {rob_uop_21_pc_lob}, {rob_uop_20_pc_lob}, {rob_uop_19_pc_lob}, {rob_uop_18_pc_lob}, {rob_uop_17_pc_lob}, {rob_uop_16_pc_lob}, {rob_uop_15_pc_lob}, {rob_uop_14_pc_lob}, {rob_uop_13_pc_lob}, {rob_uop_12_pc_lob}, {rob_uop_11_pc_lob}, {rob_uop_10_pc_lob}, {rob_uop_9_pc_lob}, {rob_uop_8_pc_lob}, {rob_uop_7_pc_lob}, {rob_uop_6_pc_lob}, {rob_uop_5_pc_lob}, {rob_uop_4_pc_lob}, {rob_uop_3_pc_lob}, {rob_uop_2_pc_lob}, {rob_uop_1_pc_lob}, {rob_uop_0_pc_lob}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_pc_lob_0 = _GEN_33[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_34 = {{rob_uop_31_taken}, {rob_uop_30_taken}, {rob_uop_29_taken}, {rob_uop_28_taken}, {rob_uop_27_taken}, {rob_uop_26_taken}, {rob_uop_25_taken}, {rob_uop_24_taken}, {rob_uop_23_taken}, {rob_uop_22_taken}, {rob_uop_21_taken}, {rob_uop_20_taken}, {rob_uop_19_taken}, {rob_uop_18_taken}, {rob_uop_17_taken}, {rob_uop_16_taken}, {rob_uop_15_taken}, {rob_uop_14_taken}, {rob_uop_13_taken}, {rob_uop_12_taken}, {rob_uop_11_taken}, {rob_uop_10_taken}, {rob_uop_9_taken}, {rob_uop_8_taken}, {rob_uop_7_taken}, {rob_uop_6_taken}, {rob_uop_5_taken}, {rob_uop_4_taken}, {rob_uop_3_taken}, {rob_uop_2_taken}, {rob_uop_1_taken}, {rob_uop_0_taken}}; // @[rob.scala:311:28, :415:25]
wire [31:0][19:0] _GEN_35 = {{rob_uop_31_imm_packed}, {rob_uop_30_imm_packed}, {rob_uop_29_imm_packed}, {rob_uop_28_imm_packed}, {rob_uop_27_imm_packed}, {rob_uop_26_imm_packed}, {rob_uop_25_imm_packed}, {rob_uop_24_imm_packed}, {rob_uop_23_imm_packed}, {rob_uop_22_imm_packed}, {rob_uop_21_imm_packed}, {rob_uop_20_imm_packed}, {rob_uop_19_imm_packed}, {rob_uop_18_imm_packed}, {rob_uop_17_imm_packed}, {rob_uop_16_imm_packed}, {rob_uop_15_imm_packed}, {rob_uop_14_imm_packed}, {rob_uop_13_imm_packed}, {rob_uop_12_imm_packed}, {rob_uop_11_imm_packed}, {rob_uop_10_imm_packed}, {rob_uop_9_imm_packed}, {rob_uop_8_imm_packed}, {rob_uop_7_imm_packed}, {rob_uop_6_imm_packed}, {rob_uop_5_imm_packed}, {rob_uop_4_imm_packed}, {rob_uop_3_imm_packed}, {rob_uop_2_imm_packed}, {rob_uop_1_imm_packed}, {rob_uop_0_imm_packed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_imm_packed_0 = _GEN_35[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][11:0] _GEN_36 = {{rob_uop_31_csr_addr}, {rob_uop_30_csr_addr}, {rob_uop_29_csr_addr}, {rob_uop_28_csr_addr}, {rob_uop_27_csr_addr}, {rob_uop_26_csr_addr}, {rob_uop_25_csr_addr}, {rob_uop_24_csr_addr}, {rob_uop_23_csr_addr}, {rob_uop_22_csr_addr}, {rob_uop_21_csr_addr}, {rob_uop_20_csr_addr}, {rob_uop_19_csr_addr}, {rob_uop_18_csr_addr}, {rob_uop_17_csr_addr}, {rob_uop_16_csr_addr}, {rob_uop_15_csr_addr}, {rob_uop_14_csr_addr}, {rob_uop_13_csr_addr}, {rob_uop_12_csr_addr}, {rob_uop_11_csr_addr}, {rob_uop_10_csr_addr}, {rob_uop_9_csr_addr}, {rob_uop_8_csr_addr}, {rob_uop_7_csr_addr}, {rob_uop_6_csr_addr}, {rob_uop_5_csr_addr}, {rob_uop_4_csr_addr}, {rob_uop_3_csr_addr}, {rob_uop_2_csr_addr}, {rob_uop_1_csr_addr}, {rob_uop_0_csr_addr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_csr_addr_0 = _GEN_36[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_37 = {{rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_rob_idx_0 = _GEN_37[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_38 = {{rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldq_idx_0 = _GEN_38[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_39 = {{rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_stq_idx_0 = _GEN_39[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_40 = {{rob_uop_31_rxq_idx}, {rob_uop_30_rxq_idx}, {rob_uop_29_rxq_idx}, {rob_uop_28_rxq_idx}, {rob_uop_27_rxq_idx}, {rob_uop_26_rxq_idx}, {rob_uop_25_rxq_idx}, {rob_uop_24_rxq_idx}, {rob_uop_23_rxq_idx}, {rob_uop_22_rxq_idx}, {rob_uop_21_rxq_idx}, {rob_uop_20_rxq_idx}, {rob_uop_19_rxq_idx}, {rob_uop_18_rxq_idx}, {rob_uop_17_rxq_idx}, {rob_uop_16_rxq_idx}, {rob_uop_15_rxq_idx}, {rob_uop_14_rxq_idx}, {rob_uop_13_rxq_idx}, {rob_uop_12_rxq_idx}, {rob_uop_11_rxq_idx}, {rob_uop_10_rxq_idx}, {rob_uop_9_rxq_idx}, {rob_uop_8_rxq_idx}, {rob_uop_7_rxq_idx}, {rob_uop_6_rxq_idx}, {rob_uop_5_rxq_idx}, {rob_uop_4_rxq_idx}, {rob_uop_3_rxq_idx}, {rob_uop_2_rxq_idx}, {rob_uop_1_rxq_idx}, {rob_uop_0_rxq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_rxq_idx_0 = _GEN_40[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_41 = {{rob_uop_31_pdst}, {rob_uop_30_pdst}, {rob_uop_29_pdst}, {rob_uop_28_pdst}, {rob_uop_27_pdst}, {rob_uop_26_pdst}, {rob_uop_25_pdst}, {rob_uop_24_pdst}, {rob_uop_23_pdst}, {rob_uop_22_pdst}, {rob_uop_21_pdst}, {rob_uop_20_pdst}, {rob_uop_19_pdst}, {rob_uop_18_pdst}, {rob_uop_17_pdst}, {rob_uop_16_pdst}, {rob_uop_15_pdst}, {rob_uop_14_pdst}, {rob_uop_13_pdst}, {rob_uop_12_pdst}, {rob_uop_11_pdst}, {rob_uop_10_pdst}, {rob_uop_9_pdst}, {rob_uop_8_pdst}, {rob_uop_7_pdst}, {rob_uop_6_pdst}, {rob_uop_5_pdst}, {rob_uop_4_pdst}, {rob_uop_3_pdst}, {rob_uop_2_pdst}, {rob_uop_1_pdst}, {rob_uop_0_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_pdst_0 = _GEN_41[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_42 = {{rob_uop_31_prs1}, {rob_uop_30_prs1}, {rob_uop_29_prs1}, {rob_uop_28_prs1}, {rob_uop_27_prs1}, {rob_uop_26_prs1}, {rob_uop_25_prs1}, {rob_uop_24_prs1}, {rob_uop_23_prs1}, {rob_uop_22_prs1}, {rob_uop_21_prs1}, {rob_uop_20_prs1}, {rob_uop_19_prs1}, {rob_uop_18_prs1}, {rob_uop_17_prs1}, {rob_uop_16_prs1}, {rob_uop_15_prs1}, {rob_uop_14_prs1}, {rob_uop_13_prs1}, {rob_uop_12_prs1}, {rob_uop_11_prs1}, {rob_uop_10_prs1}, {rob_uop_9_prs1}, {rob_uop_8_prs1}, {rob_uop_7_prs1}, {rob_uop_6_prs1}, {rob_uop_5_prs1}, {rob_uop_4_prs1}, {rob_uop_3_prs1}, {rob_uop_2_prs1}, {rob_uop_1_prs1}, {rob_uop_0_prs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs1_0 = _GEN_42[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_43 = {{rob_uop_31_prs2}, {rob_uop_30_prs2}, {rob_uop_29_prs2}, {rob_uop_28_prs2}, {rob_uop_27_prs2}, {rob_uop_26_prs2}, {rob_uop_25_prs2}, {rob_uop_24_prs2}, {rob_uop_23_prs2}, {rob_uop_22_prs2}, {rob_uop_21_prs2}, {rob_uop_20_prs2}, {rob_uop_19_prs2}, {rob_uop_18_prs2}, {rob_uop_17_prs2}, {rob_uop_16_prs2}, {rob_uop_15_prs2}, {rob_uop_14_prs2}, {rob_uop_13_prs2}, {rob_uop_12_prs2}, {rob_uop_11_prs2}, {rob_uop_10_prs2}, {rob_uop_9_prs2}, {rob_uop_8_prs2}, {rob_uop_7_prs2}, {rob_uop_6_prs2}, {rob_uop_5_prs2}, {rob_uop_4_prs2}, {rob_uop_3_prs2}, {rob_uop_2_prs2}, {rob_uop_1_prs2}, {rob_uop_0_prs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs2_0 = _GEN_43[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_44 = {{rob_uop_31_prs3}, {rob_uop_30_prs3}, {rob_uop_29_prs3}, {rob_uop_28_prs3}, {rob_uop_27_prs3}, {rob_uop_26_prs3}, {rob_uop_25_prs3}, {rob_uop_24_prs3}, {rob_uop_23_prs3}, {rob_uop_22_prs3}, {rob_uop_21_prs3}, {rob_uop_20_prs3}, {rob_uop_19_prs3}, {rob_uop_18_prs3}, {rob_uop_17_prs3}, {rob_uop_16_prs3}, {rob_uop_15_prs3}, {rob_uop_14_prs3}, {rob_uop_13_prs3}, {rob_uop_12_prs3}, {rob_uop_11_prs3}, {rob_uop_10_prs3}, {rob_uop_9_prs3}, {rob_uop_8_prs3}, {rob_uop_7_prs3}, {rob_uop_6_prs3}, {rob_uop_5_prs3}, {rob_uop_4_prs3}, {rob_uop_3_prs3}, {rob_uop_2_prs3}, {rob_uop_1_prs3}, {rob_uop_0_prs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs3_0 = _GEN_44[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_45 = {{rob_uop_31_prs1_busy}, {rob_uop_30_prs1_busy}, {rob_uop_29_prs1_busy}, {rob_uop_28_prs1_busy}, {rob_uop_27_prs1_busy}, {rob_uop_26_prs1_busy}, {rob_uop_25_prs1_busy}, {rob_uop_24_prs1_busy}, {rob_uop_23_prs1_busy}, {rob_uop_22_prs1_busy}, {rob_uop_21_prs1_busy}, {rob_uop_20_prs1_busy}, {rob_uop_19_prs1_busy}, {rob_uop_18_prs1_busy}, {rob_uop_17_prs1_busy}, {rob_uop_16_prs1_busy}, {rob_uop_15_prs1_busy}, {rob_uop_14_prs1_busy}, {rob_uop_13_prs1_busy}, {rob_uop_12_prs1_busy}, {rob_uop_11_prs1_busy}, {rob_uop_10_prs1_busy}, {rob_uop_9_prs1_busy}, {rob_uop_8_prs1_busy}, {rob_uop_7_prs1_busy}, {rob_uop_6_prs1_busy}, {rob_uop_5_prs1_busy}, {rob_uop_4_prs1_busy}, {rob_uop_3_prs1_busy}, {rob_uop_2_prs1_busy}, {rob_uop_1_prs1_busy}, {rob_uop_0_prs1_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs1_busy_0 = _GEN_45[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_46 = {{rob_uop_31_prs2_busy}, {rob_uop_30_prs2_busy}, {rob_uop_29_prs2_busy}, {rob_uop_28_prs2_busy}, {rob_uop_27_prs2_busy}, {rob_uop_26_prs2_busy}, {rob_uop_25_prs2_busy}, {rob_uop_24_prs2_busy}, {rob_uop_23_prs2_busy}, {rob_uop_22_prs2_busy}, {rob_uop_21_prs2_busy}, {rob_uop_20_prs2_busy}, {rob_uop_19_prs2_busy}, {rob_uop_18_prs2_busy}, {rob_uop_17_prs2_busy}, {rob_uop_16_prs2_busy}, {rob_uop_15_prs2_busy}, {rob_uop_14_prs2_busy}, {rob_uop_13_prs2_busy}, {rob_uop_12_prs2_busy}, {rob_uop_11_prs2_busy}, {rob_uop_10_prs2_busy}, {rob_uop_9_prs2_busy}, {rob_uop_8_prs2_busy}, {rob_uop_7_prs2_busy}, {rob_uop_6_prs2_busy}, {rob_uop_5_prs2_busy}, {rob_uop_4_prs2_busy}, {rob_uop_3_prs2_busy}, {rob_uop_2_prs2_busy}, {rob_uop_1_prs2_busy}, {rob_uop_0_prs2_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs2_busy_0 = _GEN_46[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_47 = {{rob_uop_31_prs3_busy}, {rob_uop_30_prs3_busy}, {rob_uop_29_prs3_busy}, {rob_uop_28_prs3_busy}, {rob_uop_27_prs3_busy}, {rob_uop_26_prs3_busy}, {rob_uop_25_prs3_busy}, {rob_uop_24_prs3_busy}, {rob_uop_23_prs3_busy}, {rob_uop_22_prs3_busy}, {rob_uop_21_prs3_busy}, {rob_uop_20_prs3_busy}, {rob_uop_19_prs3_busy}, {rob_uop_18_prs3_busy}, {rob_uop_17_prs3_busy}, {rob_uop_16_prs3_busy}, {rob_uop_15_prs3_busy}, {rob_uop_14_prs3_busy}, {rob_uop_13_prs3_busy}, {rob_uop_12_prs3_busy}, {rob_uop_11_prs3_busy}, {rob_uop_10_prs3_busy}, {rob_uop_9_prs3_busy}, {rob_uop_8_prs3_busy}, {rob_uop_7_prs3_busy}, {rob_uop_6_prs3_busy}, {rob_uop_5_prs3_busy}, {rob_uop_4_prs3_busy}, {rob_uop_3_prs3_busy}, {rob_uop_2_prs3_busy}, {rob_uop_1_prs3_busy}, {rob_uop_0_prs3_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs3_busy_0 = _GEN_47[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_48 = {{rob_uop_31_stale_pdst}, {rob_uop_30_stale_pdst}, {rob_uop_29_stale_pdst}, {rob_uop_28_stale_pdst}, {rob_uop_27_stale_pdst}, {rob_uop_26_stale_pdst}, {rob_uop_25_stale_pdst}, {rob_uop_24_stale_pdst}, {rob_uop_23_stale_pdst}, {rob_uop_22_stale_pdst}, {rob_uop_21_stale_pdst}, {rob_uop_20_stale_pdst}, {rob_uop_19_stale_pdst}, {rob_uop_18_stale_pdst}, {rob_uop_17_stale_pdst}, {rob_uop_16_stale_pdst}, {rob_uop_15_stale_pdst}, {rob_uop_14_stale_pdst}, {rob_uop_13_stale_pdst}, {rob_uop_12_stale_pdst}, {rob_uop_11_stale_pdst}, {rob_uop_10_stale_pdst}, {rob_uop_9_stale_pdst}, {rob_uop_8_stale_pdst}, {rob_uop_7_stale_pdst}, {rob_uop_6_stale_pdst}, {rob_uop_5_stale_pdst}, {rob_uop_4_stale_pdst}, {rob_uop_3_stale_pdst}, {rob_uop_2_stale_pdst}, {rob_uop_1_stale_pdst}, {rob_uop_0_stale_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_stale_pdst_0 = _GEN_48[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_49 = {{rob_uop_31_exception}, {rob_uop_30_exception}, {rob_uop_29_exception}, {rob_uop_28_exception}, {rob_uop_27_exception}, {rob_uop_26_exception}, {rob_uop_25_exception}, {rob_uop_24_exception}, {rob_uop_23_exception}, {rob_uop_22_exception}, {rob_uop_21_exception}, {rob_uop_20_exception}, {rob_uop_19_exception}, {rob_uop_18_exception}, {rob_uop_17_exception}, {rob_uop_16_exception}, {rob_uop_15_exception}, {rob_uop_14_exception}, {rob_uop_13_exception}, {rob_uop_12_exception}, {rob_uop_11_exception}, {rob_uop_10_exception}, {rob_uop_9_exception}, {rob_uop_8_exception}, {rob_uop_7_exception}, {rob_uop_6_exception}, {rob_uop_5_exception}, {rob_uop_4_exception}, {rob_uop_3_exception}, {rob_uop_2_exception}, {rob_uop_1_exception}, {rob_uop_0_exception}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_exception_0 = _GEN_49[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][63:0] _GEN_50 = {{rob_uop_31_exc_cause}, {rob_uop_30_exc_cause}, {rob_uop_29_exc_cause}, {rob_uop_28_exc_cause}, {rob_uop_27_exc_cause}, {rob_uop_26_exc_cause}, {rob_uop_25_exc_cause}, {rob_uop_24_exc_cause}, {rob_uop_23_exc_cause}, {rob_uop_22_exc_cause}, {rob_uop_21_exc_cause}, {rob_uop_20_exc_cause}, {rob_uop_19_exc_cause}, {rob_uop_18_exc_cause}, {rob_uop_17_exc_cause}, {rob_uop_16_exc_cause}, {rob_uop_15_exc_cause}, {rob_uop_14_exc_cause}, {rob_uop_13_exc_cause}, {rob_uop_12_exc_cause}, {rob_uop_11_exc_cause}, {rob_uop_10_exc_cause}, {rob_uop_9_exc_cause}, {rob_uop_8_exc_cause}, {rob_uop_7_exc_cause}, {rob_uop_6_exc_cause}, {rob_uop_5_exc_cause}, {rob_uop_4_exc_cause}, {rob_uop_3_exc_cause}, {rob_uop_2_exc_cause}, {rob_uop_1_exc_cause}, {rob_uop_0_exc_cause}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_exc_cause_0 = _GEN_50[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_51 = {{rob_uop_31_bypassable}, {rob_uop_30_bypassable}, {rob_uop_29_bypassable}, {rob_uop_28_bypassable}, {rob_uop_27_bypassable}, {rob_uop_26_bypassable}, {rob_uop_25_bypassable}, {rob_uop_24_bypassable}, {rob_uop_23_bypassable}, {rob_uop_22_bypassable}, {rob_uop_21_bypassable}, {rob_uop_20_bypassable}, {rob_uop_19_bypassable}, {rob_uop_18_bypassable}, {rob_uop_17_bypassable}, {rob_uop_16_bypassable}, {rob_uop_15_bypassable}, {rob_uop_14_bypassable}, {rob_uop_13_bypassable}, {rob_uop_12_bypassable}, {rob_uop_11_bypassable}, {rob_uop_10_bypassable}, {rob_uop_9_bypassable}, {rob_uop_8_bypassable}, {rob_uop_7_bypassable}, {rob_uop_6_bypassable}, {rob_uop_5_bypassable}, {rob_uop_4_bypassable}, {rob_uop_3_bypassable}, {rob_uop_2_bypassable}, {rob_uop_1_bypassable}, {rob_uop_0_bypassable}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_bypassable_0 = _GEN_51[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_52 = {{rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_mem_cmd_0 = _GEN_52[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_53 = {{rob_uop_31_mem_size}, {rob_uop_30_mem_size}, {rob_uop_29_mem_size}, {rob_uop_28_mem_size}, {rob_uop_27_mem_size}, {rob_uop_26_mem_size}, {rob_uop_25_mem_size}, {rob_uop_24_mem_size}, {rob_uop_23_mem_size}, {rob_uop_22_mem_size}, {rob_uop_21_mem_size}, {rob_uop_20_mem_size}, {rob_uop_19_mem_size}, {rob_uop_18_mem_size}, {rob_uop_17_mem_size}, {rob_uop_16_mem_size}, {rob_uop_15_mem_size}, {rob_uop_14_mem_size}, {rob_uop_13_mem_size}, {rob_uop_12_mem_size}, {rob_uop_11_mem_size}, {rob_uop_10_mem_size}, {rob_uop_9_mem_size}, {rob_uop_8_mem_size}, {rob_uop_7_mem_size}, {rob_uop_6_mem_size}, {rob_uop_5_mem_size}, {rob_uop_4_mem_size}, {rob_uop_3_mem_size}, {rob_uop_2_mem_size}, {rob_uop_1_mem_size}, {rob_uop_0_mem_size}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_mem_size_0 = _GEN_53[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_54 = {{rob_uop_31_mem_signed}, {rob_uop_30_mem_signed}, {rob_uop_29_mem_signed}, {rob_uop_28_mem_signed}, {rob_uop_27_mem_signed}, {rob_uop_26_mem_signed}, {rob_uop_25_mem_signed}, {rob_uop_24_mem_signed}, {rob_uop_23_mem_signed}, {rob_uop_22_mem_signed}, {rob_uop_21_mem_signed}, {rob_uop_20_mem_signed}, {rob_uop_19_mem_signed}, {rob_uop_18_mem_signed}, {rob_uop_17_mem_signed}, {rob_uop_16_mem_signed}, {rob_uop_15_mem_signed}, {rob_uop_14_mem_signed}, {rob_uop_13_mem_signed}, {rob_uop_12_mem_signed}, {rob_uop_11_mem_signed}, {rob_uop_10_mem_signed}, {rob_uop_9_mem_signed}, {rob_uop_8_mem_signed}, {rob_uop_7_mem_signed}, {rob_uop_6_mem_signed}, {rob_uop_5_mem_signed}, {rob_uop_4_mem_signed}, {rob_uop_3_mem_signed}, {rob_uop_2_mem_signed}, {rob_uop_1_mem_signed}, {rob_uop_0_mem_signed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_mem_signed_0 = _GEN_54[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_55 = {{rob_uop_31_is_fence}, {rob_uop_30_is_fence}, {rob_uop_29_is_fence}, {rob_uop_28_is_fence}, {rob_uop_27_is_fence}, {rob_uop_26_is_fence}, {rob_uop_25_is_fence}, {rob_uop_24_is_fence}, {rob_uop_23_is_fence}, {rob_uop_22_is_fence}, {rob_uop_21_is_fence}, {rob_uop_20_is_fence}, {rob_uop_19_is_fence}, {rob_uop_18_is_fence}, {rob_uop_17_is_fence}, {rob_uop_16_is_fence}, {rob_uop_15_is_fence}, {rob_uop_14_is_fence}, {rob_uop_13_is_fence}, {rob_uop_12_is_fence}, {rob_uop_11_is_fence}, {rob_uop_10_is_fence}, {rob_uop_9_is_fence}, {rob_uop_8_is_fence}, {rob_uop_7_is_fence}, {rob_uop_6_is_fence}, {rob_uop_5_is_fence}, {rob_uop_4_is_fence}, {rob_uop_3_is_fence}, {rob_uop_2_is_fence}, {rob_uop_1_is_fence}, {rob_uop_0_is_fence}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_fence_0 = _GEN_55[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_56 = {{rob_uop_31_is_fencei}, {rob_uop_30_is_fencei}, {rob_uop_29_is_fencei}, {rob_uop_28_is_fencei}, {rob_uop_27_is_fencei}, {rob_uop_26_is_fencei}, {rob_uop_25_is_fencei}, {rob_uop_24_is_fencei}, {rob_uop_23_is_fencei}, {rob_uop_22_is_fencei}, {rob_uop_21_is_fencei}, {rob_uop_20_is_fencei}, {rob_uop_19_is_fencei}, {rob_uop_18_is_fencei}, {rob_uop_17_is_fencei}, {rob_uop_16_is_fencei}, {rob_uop_15_is_fencei}, {rob_uop_14_is_fencei}, {rob_uop_13_is_fencei}, {rob_uop_12_is_fencei}, {rob_uop_11_is_fencei}, {rob_uop_10_is_fencei}, {rob_uop_9_is_fencei}, {rob_uop_8_is_fencei}, {rob_uop_7_is_fencei}, {rob_uop_6_is_fencei}, {rob_uop_5_is_fencei}, {rob_uop_4_is_fencei}, {rob_uop_3_is_fencei}, {rob_uop_2_is_fencei}, {rob_uop_1_is_fencei}, {rob_uop_0_is_fencei}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_fencei_0 = _GEN_56[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_57 = {{rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_amo_0 = _GEN_57[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_58 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_uses_ldq_0 = _GEN_58[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_59 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_uses_stq_0 = _GEN_59[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_60 = {{rob_uop_31_is_sys_pc2epc}, {rob_uop_30_is_sys_pc2epc}, {rob_uop_29_is_sys_pc2epc}, {rob_uop_28_is_sys_pc2epc}, {rob_uop_27_is_sys_pc2epc}, {rob_uop_26_is_sys_pc2epc}, {rob_uop_25_is_sys_pc2epc}, {rob_uop_24_is_sys_pc2epc}, {rob_uop_23_is_sys_pc2epc}, {rob_uop_22_is_sys_pc2epc}, {rob_uop_21_is_sys_pc2epc}, {rob_uop_20_is_sys_pc2epc}, {rob_uop_19_is_sys_pc2epc}, {rob_uop_18_is_sys_pc2epc}, {rob_uop_17_is_sys_pc2epc}, {rob_uop_16_is_sys_pc2epc}, {rob_uop_15_is_sys_pc2epc}, {rob_uop_14_is_sys_pc2epc}, {rob_uop_13_is_sys_pc2epc}, {rob_uop_12_is_sys_pc2epc}, {rob_uop_11_is_sys_pc2epc}, {rob_uop_10_is_sys_pc2epc}, {rob_uop_9_is_sys_pc2epc}, {rob_uop_8_is_sys_pc2epc}, {rob_uop_7_is_sys_pc2epc}, {rob_uop_6_is_sys_pc2epc}, {rob_uop_5_is_sys_pc2epc}, {rob_uop_4_is_sys_pc2epc}, {rob_uop_3_is_sys_pc2epc}, {rob_uop_2_is_sys_pc2epc}, {rob_uop_1_is_sys_pc2epc}, {rob_uop_0_is_sys_pc2epc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_sys_pc2epc_0 = _GEN_60[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_61 = {{rob_uop_31_is_unique}, {rob_uop_30_is_unique}, {rob_uop_29_is_unique}, {rob_uop_28_is_unique}, {rob_uop_27_is_unique}, {rob_uop_26_is_unique}, {rob_uop_25_is_unique}, {rob_uop_24_is_unique}, {rob_uop_23_is_unique}, {rob_uop_22_is_unique}, {rob_uop_21_is_unique}, {rob_uop_20_is_unique}, {rob_uop_19_is_unique}, {rob_uop_18_is_unique}, {rob_uop_17_is_unique}, {rob_uop_16_is_unique}, {rob_uop_15_is_unique}, {rob_uop_14_is_unique}, {rob_uop_13_is_unique}, {rob_uop_12_is_unique}, {rob_uop_11_is_unique}, {rob_uop_10_is_unique}, {rob_uop_9_is_unique}, {rob_uop_8_is_unique}, {rob_uop_7_is_unique}, {rob_uop_6_is_unique}, {rob_uop_5_is_unique}, {rob_uop_4_is_unique}, {rob_uop_3_is_unique}, {rob_uop_2_is_unique}, {rob_uop_1_is_unique}, {rob_uop_0_is_unique}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_unique_0 = _GEN_61[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_62 = {{rob_uop_31_flush_on_commit}, {rob_uop_30_flush_on_commit}, {rob_uop_29_flush_on_commit}, {rob_uop_28_flush_on_commit}, {rob_uop_27_flush_on_commit}, {rob_uop_26_flush_on_commit}, {rob_uop_25_flush_on_commit}, {rob_uop_24_flush_on_commit}, {rob_uop_23_flush_on_commit}, {rob_uop_22_flush_on_commit}, {rob_uop_21_flush_on_commit}, {rob_uop_20_flush_on_commit}, {rob_uop_19_flush_on_commit}, {rob_uop_18_flush_on_commit}, {rob_uop_17_flush_on_commit}, {rob_uop_16_flush_on_commit}, {rob_uop_15_flush_on_commit}, {rob_uop_14_flush_on_commit}, {rob_uop_13_flush_on_commit}, {rob_uop_12_flush_on_commit}, {rob_uop_11_flush_on_commit}, {rob_uop_10_flush_on_commit}, {rob_uop_9_flush_on_commit}, {rob_uop_8_flush_on_commit}, {rob_uop_7_flush_on_commit}, {rob_uop_6_flush_on_commit}, {rob_uop_5_flush_on_commit}, {rob_uop_4_flush_on_commit}, {rob_uop_3_flush_on_commit}, {rob_uop_2_flush_on_commit}, {rob_uop_1_flush_on_commit}, {rob_uop_0_flush_on_commit}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_flush_on_commit_0 = _GEN_62[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_63 = {{rob_uop_31_ldst_is_rs1}, {rob_uop_30_ldst_is_rs1}, {rob_uop_29_ldst_is_rs1}, {rob_uop_28_ldst_is_rs1}, {rob_uop_27_ldst_is_rs1}, {rob_uop_26_ldst_is_rs1}, {rob_uop_25_ldst_is_rs1}, {rob_uop_24_ldst_is_rs1}, {rob_uop_23_ldst_is_rs1}, {rob_uop_22_ldst_is_rs1}, {rob_uop_21_ldst_is_rs1}, {rob_uop_20_ldst_is_rs1}, {rob_uop_19_ldst_is_rs1}, {rob_uop_18_ldst_is_rs1}, {rob_uop_17_ldst_is_rs1}, {rob_uop_16_ldst_is_rs1}, {rob_uop_15_ldst_is_rs1}, {rob_uop_14_ldst_is_rs1}, {rob_uop_13_ldst_is_rs1}, {rob_uop_12_ldst_is_rs1}, {rob_uop_11_ldst_is_rs1}, {rob_uop_10_ldst_is_rs1}, {rob_uop_9_ldst_is_rs1}, {rob_uop_8_ldst_is_rs1}, {rob_uop_7_ldst_is_rs1}, {rob_uop_6_ldst_is_rs1}, {rob_uop_5_ldst_is_rs1}, {rob_uop_4_ldst_is_rs1}, {rob_uop_3_ldst_is_rs1}, {rob_uop_2_ldst_is_rs1}, {rob_uop_1_ldst_is_rs1}, {rob_uop_0_ldst_is_rs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldst_is_rs1_0 = _GEN_63[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_64 = {{rob_uop_31_ldst}, {rob_uop_30_ldst}, {rob_uop_29_ldst}, {rob_uop_28_ldst}, {rob_uop_27_ldst}, {rob_uop_26_ldst}, {rob_uop_25_ldst}, {rob_uop_24_ldst}, {rob_uop_23_ldst}, {rob_uop_22_ldst}, {rob_uop_21_ldst}, {rob_uop_20_ldst}, {rob_uop_19_ldst}, {rob_uop_18_ldst}, {rob_uop_17_ldst}, {rob_uop_16_ldst}, {rob_uop_15_ldst}, {rob_uop_14_ldst}, {rob_uop_13_ldst}, {rob_uop_12_ldst}, {rob_uop_11_ldst}, {rob_uop_10_ldst}, {rob_uop_9_ldst}, {rob_uop_8_ldst}, {rob_uop_7_ldst}, {rob_uop_6_ldst}, {rob_uop_5_ldst}, {rob_uop_4_ldst}, {rob_uop_3_ldst}, {rob_uop_2_ldst}, {rob_uop_1_ldst}, {rob_uop_0_ldst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldst_0 = _GEN_64[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_65 = {{rob_uop_31_lrs1}, {rob_uop_30_lrs1}, {rob_uop_29_lrs1}, {rob_uop_28_lrs1}, {rob_uop_27_lrs1}, {rob_uop_26_lrs1}, {rob_uop_25_lrs1}, {rob_uop_24_lrs1}, {rob_uop_23_lrs1}, {rob_uop_22_lrs1}, {rob_uop_21_lrs1}, {rob_uop_20_lrs1}, {rob_uop_19_lrs1}, {rob_uop_18_lrs1}, {rob_uop_17_lrs1}, {rob_uop_16_lrs1}, {rob_uop_15_lrs1}, {rob_uop_14_lrs1}, {rob_uop_13_lrs1}, {rob_uop_12_lrs1}, {rob_uop_11_lrs1}, {rob_uop_10_lrs1}, {rob_uop_9_lrs1}, {rob_uop_8_lrs1}, {rob_uop_7_lrs1}, {rob_uop_6_lrs1}, {rob_uop_5_lrs1}, {rob_uop_4_lrs1}, {rob_uop_3_lrs1}, {rob_uop_2_lrs1}, {rob_uop_1_lrs1}, {rob_uop_0_lrs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs1_0 = _GEN_65[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_66 = {{rob_uop_31_lrs2}, {rob_uop_30_lrs2}, {rob_uop_29_lrs2}, {rob_uop_28_lrs2}, {rob_uop_27_lrs2}, {rob_uop_26_lrs2}, {rob_uop_25_lrs2}, {rob_uop_24_lrs2}, {rob_uop_23_lrs2}, {rob_uop_22_lrs2}, {rob_uop_21_lrs2}, {rob_uop_20_lrs2}, {rob_uop_19_lrs2}, {rob_uop_18_lrs2}, {rob_uop_17_lrs2}, {rob_uop_16_lrs2}, {rob_uop_15_lrs2}, {rob_uop_14_lrs2}, {rob_uop_13_lrs2}, {rob_uop_12_lrs2}, {rob_uop_11_lrs2}, {rob_uop_10_lrs2}, {rob_uop_9_lrs2}, {rob_uop_8_lrs2}, {rob_uop_7_lrs2}, {rob_uop_6_lrs2}, {rob_uop_5_lrs2}, {rob_uop_4_lrs2}, {rob_uop_3_lrs2}, {rob_uop_2_lrs2}, {rob_uop_1_lrs2}, {rob_uop_0_lrs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs2_0 = _GEN_66[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_67 = {{rob_uop_31_lrs3}, {rob_uop_30_lrs3}, {rob_uop_29_lrs3}, {rob_uop_28_lrs3}, {rob_uop_27_lrs3}, {rob_uop_26_lrs3}, {rob_uop_25_lrs3}, {rob_uop_24_lrs3}, {rob_uop_23_lrs3}, {rob_uop_22_lrs3}, {rob_uop_21_lrs3}, {rob_uop_20_lrs3}, {rob_uop_19_lrs3}, {rob_uop_18_lrs3}, {rob_uop_17_lrs3}, {rob_uop_16_lrs3}, {rob_uop_15_lrs3}, {rob_uop_14_lrs3}, {rob_uop_13_lrs3}, {rob_uop_12_lrs3}, {rob_uop_11_lrs3}, {rob_uop_10_lrs3}, {rob_uop_9_lrs3}, {rob_uop_8_lrs3}, {rob_uop_7_lrs3}, {rob_uop_6_lrs3}, {rob_uop_5_lrs3}, {rob_uop_4_lrs3}, {rob_uop_3_lrs3}, {rob_uop_2_lrs3}, {rob_uop_1_lrs3}, {rob_uop_0_lrs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs3_0 = _GEN_67[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_68 = {{rob_uop_31_ldst_val}, {rob_uop_30_ldst_val}, {rob_uop_29_ldst_val}, {rob_uop_28_ldst_val}, {rob_uop_27_ldst_val}, {rob_uop_26_ldst_val}, {rob_uop_25_ldst_val}, {rob_uop_24_ldst_val}, {rob_uop_23_ldst_val}, {rob_uop_22_ldst_val}, {rob_uop_21_ldst_val}, {rob_uop_20_ldst_val}, {rob_uop_19_ldst_val}, {rob_uop_18_ldst_val}, {rob_uop_17_ldst_val}, {rob_uop_16_ldst_val}, {rob_uop_15_ldst_val}, {rob_uop_14_ldst_val}, {rob_uop_13_ldst_val}, {rob_uop_12_ldst_val}, {rob_uop_11_ldst_val}, {rob_uop_10_ldst_val}, {rob_uop_9_ldst_val}, {rob_uop_8_ldst_val}, {rob_uop_7_ldst_val}, {rob_uop_6_ldst_val}, {rob_uop_5_ldst_val}, {rob_uop_4_ldst_val}, {rob_uop_3_ldst_val}, {rob_uop_2_ldst_val}, {rob_uop_1_ldst_val}, {rob_uop_0_ldst_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldst_val_0 = _GEN_68[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_69 = {{rob_uop_31_dst_rtype}, {rob_uop_30_dst_rtype}, {rob_uop_29_dst_rtype}, {rob_uop_28_dst_rtype}, {rob_uop_27_dst_rtype}, {rob_uop_26_dst_rtype}, {rob_uop_25_dst_rtype}, {rob_uop_24_dst_rtype}, {rob_uop_23_dst_rtype}, {rob_uop_22_dst_rtype}, {rob_uop_21_dst_rtype}, {rob_uop_20_dst_rtype}, {rob_uop_19_dst_rtype}, {rob_uop_18_dst_rtype}, {rob_uop_17_dst_rtype}, {rob_uop_16_dst_rtype}, {rob_uop_15_dst_rtype}, {rob_uop_14_dst_rtype}, {rob_uop_13_dst_rtype}, {rob_uop_12_dst_rtype}, {rob_uop_11_dst_rtype}, {rob_uop_10_dst_rtype}, {rob_uop_9_dst_rtype}, {rob_uop_8_dst_rtype}, {rob_uop_7_dst_rtype}, {rob_uop_6_dst_rtype}, {rob_uop_5_dst_rtype}, {rob_uop_4_dst_rtype}, {rob_uop_3_dst_rtype}, {rob_uop_2_dst_rtype}, {rob_uop_1_dst_rtype}, {rob_uop_0_dst_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_dst_rtype_0 = _GEN_69[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_70 = {{rob_uop_31_lrs1_rtype}, {rob_uop_30_lrs1_rtype}, {rob_uop_29_lrs1_rtype}, {rob_uop_28_lrs1_rtype}, {rob_uop_27_lrs1_rtype}, {rob_uop_26_lrs1_rtype}, {rob_uop_25_lrs1_rtype}, {rob_uop_24_lrs1_rtype}, {rob_uop_23_lrs1_rtype}, {rob_uop_22_lrs1_rtype}, {rob_uop_21_lrs1_rtype}, {rob_uop_20_lrs1_rtype}, {rob_uop_19_lrs1_rtype}, {rob_uop_18_lrs1_rtype}, {rob_uop_17_lrs1_rtype}, {rob_uop_16_lrs1_rtype}, {rob_uop_15_lrs1_rtype}, {rob_uop_14_lrs1_rtype}, {rob_uop_13_lrs1_rtype}, {rob_uop_12_lrs1_rtype}, {rob_uop_11_lrs1_rtype}, {rob_uop_10_lrs1_rtype}, {rob_uop_9_lrs1_rtype}, {rob_uop_8_lrs1_rtype}, {rob_uop_7_lrs1_rtype}, {rob_uop_6_lrs1_rtype}, {rob_uop_5_lrs1_rtype}, {rob_uop_4_lrs1_rtype}, {rob_uop_3_lrs1_rtype}, {rob_uop_2_lrs1_rtype}, {rob_uop_1_lrs1_rtype}, {rob_uop_0_lrs1_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs1_rtype_0 = _GEN_70[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_71 = {{rob_uop_31_lrs2_rtype}, {rob_uop_30_lrs2_rtype}, {rob_uop_29_lrs2_rtype}, {rob_uop_28_lrs2_rtype}, {rob_uop_27_lrs2_rtype}, {rob_uop_26_lrs2_rtype}, {rob_uop_25_lrs2_rtype}, {rob_uop_24_lrs2_rtype}, {rob_uop_23_lrs2_rtype}, {rob_uop_22_lrs2_rtype}, {rob_uop_21_lrs2_rtype}, {rob_uop_20_lrs2_rtype}, {rob_uop_19_lrs2_rtype}, {rob_uop_18_lrs2_rtype}, {rob_uop_17_lrs2_rtype}, {rob_uop_16_lrs2_rtype}, {rob_uop_15_lrs2_rtype}, {rob_uop_14_lrs2_rtype}, {rob_uop_13_lrs2_rtype}, {rob_uop_12_lrs2_rtype}, {rob_uop_11_lrs2_rtype}, {rob_uop_10_lrs2_rtype}, {rob_uop_9_lrs2_rtype}, {rob_uop_8_lrs2_rtype}, {rob_uop_7_lrs2_rtype}, {rob_uop_6_lrs2_rtype}, {rob_uop_5_lrs2_rtype}, {rob_uop_4_lrs2_rtype}, {rob_uop_3_lrs2_rtype}, {rob_uop_2_lrs2_rtype}, {rob_uop_1_lrs2_rtype}, {rob_uop_0_lrs2_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs2_rtype_0 = _GEN_71[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_72 = {{rob_uop_31_frs3_en}, {rob_uop_30_frs3_en}, {rob_uop_29_frs3_en}, {rob_uop_28_frs3_en}, {rob_uop_27_frs3_en}, {rob_uop_26_frs3_en}, {rob_uop_25_frs3_en}, {rob_uop_24_frs3_en}, {rob_uop_23_frs3_en}, {rob_uop_22_frs3_en}, {rob_uop_21_frs3_en}, {rob_uop_20_frs3_en}, {rob_uop_19_frs3_en}, {rob_uop_18_frs3_en}, {rob_uop_17_frs3_en}, {rob_uop_16_frs3_en}, {rob_uop_15_frs3_en}, {rob_uop_14_frs3_en}, {rob_uop_13_frs3_en}, {rob_uop_12_frs3_en}, {rob_uop_11_frs3_en}, {rob_uop_10_frs3_en}, {rob_uop_9_frs3_en}, {rob_uop_8_frs3_en}, {rob_uop_7_frs3_en}, {rob_uop_6_frs3_en}, {rob_uop_5_frs3_en}, {rob_uop_4_frs3_en}, {rob_uop_3_frs3_en}, {rob_uop_2_frs3_en}, {rob_uop_1_frs3_en}, {rob_uop_0_frs3_en}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_frs3_en_0 = _GEN_72[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_73 = {{rob_uop_31_fp_val}, {rob_uop_30_fp_val}, {rob_uop_29_fp_val}, {rob_uop_28_fp_val}, {rob_uop_27_fp_val}, {rob_uop_26_fp_val}, {rob_uop_25_fp_val}, {rob_uop_24_fp_val}, {rob_uop_23_fp_val}, {rob_uop_22_fp_val}, {rob_uop_21_fp_val}, {rob_uop_20_fp_val}, {rob_uop_19_fp_val}, {rob_uop_18_fp_val}, {rob_uop_17_fp_val}, {rob_uop_16_fp_val}, {rob_uop_15_fp_val}, {rob_uop_14_fp_val}, {rob_uop_13_fp_val}, {rob_uop_12_fp_val}, {rob_uop_11_fp_val}, {rob_uop_10_fp_val}, {rob_uop_9_fp_val}, {rob_uop_8_fp_val}, {rob_uop_7_fp_val}, {rob_uop_6_fp_val}, {rob_uop_5_fp_val}, {rob_uop_4_fp_val}, {rob_uop_3_fp_val}, {rob_uop_2_fp_val}, {rob_uop_1_fp_val}, {rob_uop_0_fp_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_fp_val_0 = _GEN_73[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_74 = {{rob_uop_31_fp_single}, {rob_uop_30_fp_single}, {rob_uop_29_fp_single}, {rob_uop_28_fp_single}, {rob_uop_27_fp_single}, {rob_uop_26_fp_single}, {rob_uop_25_fp_single}, {rob_uop_24_fp_single}, {rob_uop_23_fp_single}, {rob_uop_22_fp_single}, {rob_uop_21_fp_single}, {rob_uop_20_fp_single}, {rob_uop_19_fp_single}, {rob_uop_18_fp_single}, {rob_uop_17_fp_single}, {rob_uop_16_fp_single}, {rob_uop_15_fp_single}, {rob_uop_14_fp_single}, {rob_uop_13_fp_single}, {rob_uop_12_fp_single}, {rob_uop_11_fp_single}, {rob_uop_10_fp_single}, {rob_uop_9_fp_single}, {rob_uop_8_fp_single}, {rob_uop_7_fp_single}, {rob_uop_6_fp_single}, {rob_uop_5_fp_single}, {rob_uop_4_fp_single}, {rob_uop_3_fp_single}, {rob_uop_2_fp_single}, {rob_uop_1_fp_single}, {rob_uop_0_fp_single}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_fp_single_0 = _GEN_74[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_75 = {{rob_uop_31_xcpt_pf_if}, {rob_uop_30_xcpt_pf_if}, {rob_uop_29_xcpt_pf_if}, {rob_uop_28_xcpt_pf_if}, {rob_uop_27_xcpt_pf_if}, {rob_uop_26_xcpt_pf_if}, {rob_uop_25_xcpt_pf_if}, {rob_uop_24_xcpt_pf_if}, {rob_uop_23_xcpt_pf_if}, {rob_uop_22_xcpt_pf_if}, {rob_uop_21_xcpt_pf_if}, {rob_uop_20_xcpt_pf_if}, {rob_uop_19_xcpt_pf_if}, {rob_uop_18_xcpt_pf_if}, {rob_uop_17_xcpt_pf_if}, {rob_uop_16_xcpt_pf_if}, {rob_uop_15_xcpt_pf_if}, {rob_uop_14_xcpt_pf_if}, {rob_uop_13_xcpt_pf_if}, {rob_uop_12_xcpt_pf_if}, {rob_uop_11_xcpt_pf_if}, {rob_uop_10_xcpt_pf_if}, {rob_uop_9_xcpt_pf_if}, {rob_uop_8_xcpt_pf_if}, {rob_uop_7_xcpt_pf_if}, {rob_uop_6_xcpt_pf_if}, {rob_uop_5_xcpt_pf_if}, {rob_uop_4_xcpt_pf_if}, {rob_uop_3_xcpt_pf_if}, {rob_uop_2_xcpt_pf_if}, {rob_uop_1_xcpt_pf_if}, {rob_uop_0_xcpt_pf_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_xcpt_pf_if_0 = _GEN_75[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_76 = {{rob_uop_31_xcpt_ae_if}, {rob_uop_30_xcpt_ae_if}, {rob_uop_29_xcpt_ae_if}, {rob_uop_28_xcpt_ae_if}, {rob_uop_27_xcpt_ae_if}, {rob_uop_26_xcpt_ae_if}, {rob_uop_25_xcpt_ae_if}, {rob_uop_24_xcpt_ae_if}, {rob_uop_23_xcpt_ae_if}, {rob_uop_22_xcpt_ae_if}, {rob_uop_21_xcpt_ae_if}, {rob_uop_20_xcpt_ae_if}, {rob_uop_19_xcpt_ae_if}, {rob_uop_18_xcpt_ae_if}, {rob_uop_17_xcpt_ae_if}, {rob_uop_16_xcpt_ae_if}, {rob_uop_15_xcpt_ae_if}, {rob_uop_14_xcpt_ae_if}, {rob_uop_13_xcpt_ae_if}, {rob_uop_12_xcpt_ae_if}, {rob_uop_11_xcpt_ae_if}, {rob_uop_10_xcpt_ae_if}, {rob_uop_9_xcpt_ae_if}, {rob_uop_8_xcpt_ae_if}, {rob_uop_7_xcpt_ae_if}, {rob_uop_6_xcpt_ae_if}, {rob_uop_5_xcpt_ae_if}, {rob_uop_4_xcpt_ae_if}, {rob_uop_3_xcpt_ae_if}, {rob_uop_2_xcpt_ae_if}, {rob_uop_1_xcpt_ae_if}, {rob_uop_0_xcpt_ae_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_xcpt_ae_if_0 = _GEN_76[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_77 = {{rob_uop_31_xcpt_ma_if}, {rob_uop_30_xcpt_ma_if}, {rob_uop_29_xcpt_ma_if}, {rob_uop_28_xcpt_ma_if}, {rob_uop_27_xcpt_ma_if}, {rob_uop_26_xcpt_ma_if}, {rob_uop_25_xcpt_ma_if}, {rob_uop_24_xcpt_ma_if}, {rob_uop_23_xcpt_ma_if}, {rob_uop_22_xcpt_ma_if}, {rob_uop_21_xcpt_ma_if}, {rob_uop_20_xcpt_ma_if}, {rob_uop_19_xcpt_ma_if}, {rob_uop_18_xcpt_ma_if}, {rob_uop_17_xcpt_ma_if}, {rob_uop_16_xcpt_ma_if}, {rob_uop_15_xcpt_ma_if}, {rob_uop_14_xcpt_ma_if}, {rob_uop_13_xcpt_ma_if}, {rob_uop_12_xcpt_ma_if}, {rob_uop_11_xcpt_ma_if}, {rob_uop_10_xcpt_ma_if}, {rob_uop_9_xcpt_ma_if}, {rob_uop_8_xcpt_ma_if}, {rob_uop_7_xcpt_ma_if}, {rob_uop_6_xcpt_ma_if}, {rob_uop_5_xcpt_ma_if}, {rob_uop_4_xcpt_ma_if}, {rob_uop_3_xcpt_ma_if}, {rob_uop_2_xcpt_ma_if}, {rob_uop_1_xcpt_ma_if}, {rob_uop_0_xcpt_ma_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_xcpt_ma_if_0 = _GEN_77[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_78 = {{rob_uop_31_bp_debug_if}, {rob_uop_30_bp_debug_if}, {rob_uop_29_bp_debug_if}, {rob_uop_28_bp_debug_if}, {rob_uop_27_bp_debug_if}, {rob_uop_26_bp_debug_if}, {rob_uop_25_bp_debug_if}, {rob_uop_24_bp_debug_if}, {rob_uop_23_bp_debug_if}, {rob_uop_22_bp_debug_if}, {rob_uop_21_bp_debug_if}, {rob_uop_20_bp_debug_if}, {rob_uop_19_bp_debug_if}, {rob_uop_18_bp_debug_if}, {rob_uop_17_bp_debug_if}, {rob_uop_16_bp_debug_if}, {rob_uop_15_bp_debug_if}, {rob_uop_14_bp_debug_if}, {rob_uop_13_bp_debug_if}, {rob_uop_12_bp_debug_if}, {rob_uop_11_bp_debug_if}, {rob_uop_10_bp_debug_if}, {rob_uop_9_bp_debug_if}, {rob_uop_8_bp_debug_if}, {rob_uop_7_bp_debug_if}, {rob_uop_6_bp_debug_if}, {rob_uop_5_bp_debug_if}, {rob_uop_4_bp_debug_if}, {rob_uop_3_bp_debug_if}, {rob_uop_2_bp_debug_if}, {rob_uop_1_bp_debug_if}, {rob_uop_0_bp_debug_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_bp_debug_if_0 = _GEN_78[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_79 = {{rob_uop_31_bp_xcpt_if}, {rob_uop_30_bp_xcpt_if}, {rob_uop_29_bp_xcpt_if}, {rob_uop_28_bp_xcpt_if}, {rob_uop_27_bp_xcpt_if}, {rob_uop_26_bp_xcpt_if}, {rob_uop_25_bp_xcpt_if}, {rob_uop_24_bp_xcpt_if}, {rob_uop_23_bp_xcpt_if}, {rob_uop_22_bp_xcpt_if}, {rob_uop_21_bp_xcpt_if}, {rob_uop_20_bp_xcpt_if}, {rob_uop_19_bp_xcpt_if}, {rob_uop_18_bp_xcpt_if}, {rob_uop_17_bp_xcpt_if}, {rob_uop_16_bp_xcpt_if}, {rob_uop_15_bp_xcpt_if}, {rob_uop_14_bp_xcpt_if}, {rob_uop_13_bp_xcpt_if}, {rob_uop_12_bp_xcpt_if}, {rob_uop_11_bp_xcpt_if}, {rob_uop_10_bp_xcpt_if}, {rob_uop_9_bp_xcpt_if}, {rob_uop_8_bp_xcpt_if}, {rob_uop_7_bp_xcpt_if}, {rob_uop_6_bp_xcpt_if}, {rob_uop_5_bp_xcpt_if}, {rob_uop_4_bp_xcpt_if}, {rob_uop_3_bp_xcpt_if}, {rob_uop_2_bp_xcpt_if}, {rob_uop_1_bp_xcpt_if}, {rob_uop_0_bp_xcpt_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_bp_xcpt_if_0 = _GEN_79[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_80 = {{rob_uop_31_debug_fsrc}, {rob_uop_30_debug_fsrc}, {rob_uop_29_debug_fsrc}, {rob_uop_28_debug_fsrc}, {rob_uop_27_debug_fsrc}, {rob_uop_26_debug_fsrc}, {rob_uop_25_debug_fsrc}, {rob_uop_24_debug_fsrc}, {rob_uop_23_debug_fsrc}, {rob_uop_22_debug_fsrc}, {rob_uop_21_debug_fsrc}, {rob_uop_20_debug_fsrc}, {rob_uop_19_debug_fsrc}, {rob_uop_18_debug_fsrc}, {rob_uop_17_debug_fsrc}, {rob_uop_16_debug_fsrc}, {rob_uop_15_debug_fsrc}, {rob_uop_14_debug_fsrc}, {rob_uop_13_debug_fsrc}, {rob_uop_12_debug_fsrc}, {rob_uop_11_debug_fsrc}, {rob_uop_10_debug_fsrc}, {rob_uop_9_debug_fsrc}, {rob_uop_8_debug_fsrc}, {rob_uop_7_debug_fsrc}, {rob_uop_6_debug_fsrc}, {rob_uop_5_debug_fsrc}, {rob_uop_4_debug_fsrc}, {rob_uop_3_debug_fsrc}, {rob_uop_2_debug_fsrc}, {rob_uop_1_debug_fsrc}, {rob_uop_0_debug_fsrc}}; // @[rob.scala:311:28, :415:25]
wire [31:0][1:0] _GEN_81 = {{rob_uop_31_debug_tsrc}, {rob_uop_30_debug_tsrc}, {rob_uop_29_debug_tsrc}, {rob_uop_28_debug_tsrc}, {rob_uop_27_debug_tsrc}, {rob_uop_26_debug_tsrc}, {rob_uop_25_debug_tsrc}, {rob_uop_24_debug_tsrc}, {rob_uop_23_debug_tsrc}, {rob_uop_22_debug_tsrc}, {rob_uop_21_debug_tsrc}, {rob_uop_20_debug_tsrc}, {rob_uop_19_debug_tsrc}, {rob_uop_18_debug_tsrc}, {rob_uop_17_debug_tsrc}, {rob_uop_16_debug_tsrc}, {rob_uop_15_debug_tsrc}, {rob_uop_14_debug_tsrc}, {rob_uop_13_debug_tsrc}, {rob_uop_12_debug_tsrc}, {rob_uop_11_debug_tsrc}, {rob_uop_10_debug_tsrc}, {rob_uop_9_debug_tsrc}, {rob_uop_8_debug_tsrc}, {rob_uop_7_debug_tsrc}, {rob_uop_6_debug_tsrc}, {rob_uop_5_debug_tsrc}, {rob_uop_4_debug_tsrc}, {rob_uop_3_debug_tsrc}, {rob_uop_2_debug_tsrc}, {rob_uop_1_debug_tsrc}, {rob_uop_0_debug_tsrc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_debug_tsrc_0 = _GEN_81[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire _T_56 = io_brupdate_b2_mispredict_0 & io_brupdate_b2_uop_rob_idx_0 == com_idx; // @[rob.scala:211:7, :235:20, :421:57, :422:45]
assign io_commit_uops_0_debug_fsrc_0 = _T_56 ? 2'h3 : _GEN_80[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :421:57, :422:58, :423:36]
assign io_commit_uops_0_taken_0 = _T_56 ? io_brupdate_b2_taken_0 : _GEN_34[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :421:57, :422:58, :424:36]
wire _rbk_row_T_1 = ~full; // @[rob.scala:239:26, :429:47]
wire rbk_row = _rbk_row_T & _rbk_row_T_1; // @[rob.scala:429:{29,44,47}]
wire _io_commit_rbk_valids_0_T = rbk_row & _GEN[com_idx]; // @[rob.scala:235:20, :324:31, :429:44, :431:40]
assign _io_commit_rbk_valids_0_T_2 = _io_commit_rbk_valids_0_T; // @[rob.scala:431:{40,60}]
assign io_commit_rbk_valids_0_0 = _io_commit_rbk_valids_0_T_2; // @[rob.scala:211:7, :431:60]
assign io_commit_rollback_0 = _io_commit_rollback_T; // @[rob.scala:211:7, :432:38]
wire [7:0] _rob_uop_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_0_br_mask_T_1 = rob_uop_0_br_mask & _rob_uop_0_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_1_br_mask_T_1 = rob_uop_1_br_mask & _rob_uop_1_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_2_br_mask_T_1 = rob_uop_2_br_mask & _rob_uop_2_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_3_br_mask_T_1 = rob_uop_3_br_mask & _rob_uop_3_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_4_br_mask_T_1 = rob_uop_4_br_mask & _rob_uop_4_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_5_br_mask_T_1 = rob_uop_5_br_mask & _rob_uop_5_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_6_br_mask_T_1 = rob_uop_6_br_mask & _rob_uop_6_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_7_br_mask_T_1 = rob_uop_7_br_mask & _rob_uop_7_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_8_br_mask_T_1 = rob_uop_8_br_mask & _rob_uop_8_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_9_br_mask_T_1 = rob_uop_9_br_mask & _rob_uop_9_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_10_br_mask_T_1 = rob_uop_10_br_mask & _rob_uop_10_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_11_br_mask_T_1 = rob_uop_11_br_mask & _rob_uop_11_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_12_br_mask_T_1 = rob_uop_12_br_mask & _rob_uop_12_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_13_br_mask_T_1 = rob_uop_13_br_mask & _rob_uop_13_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_14_br_mask_T_1 = rob_uop_14_br_mask & _rob_uop_14_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_15_br_mask_T_1 = rob_uop_15_br_mask & _rob_uop_15_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_16_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_16_br_mask_T_1 = rob_uop_16_br_mask & _rob_uop_16_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_17_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_17_br_mask_T_1 = rob_uop_17_br_mask & _rob_uop_17_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_18_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_18_br_mask_T_1 = rob_uop_18_br_mask & _rob_uop_18_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_19_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_19_br_mask_T_1 = rob_uop_19_br_mask & _rob_uop_19_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_20_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_20_br_mask_T_1 = rob_uop_20_br_mask & _rob_uop_20_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_21_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_21_br_mask_T_1 = rob_uop_21_br_mask & _rob_uop_21_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_22_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_22_br_mask_T_1 = rob_uop_22_br_mask & _rob_uop_22_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_23_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_23_br_mask_T_1 = rob_uop_23_br_mask & _rob_uop_23_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_24_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_24_br_mask_T_1 = rob_uop_24_br_mask & _rob_uop_24_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_25_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_25_br_mask_T_1 = rob_uop_25_br_mask & _rob_uop_25_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_26_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_26_br_mask_T_1 = rob_uop_26_br_mask & _rob_uop_26_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_27_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_27_br_mask_T_1 = rob_uop_27_br_mask & _rob_uop_27_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_28_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_28_br_mask_T_1 = rob_uop_28_br_mask & _rob_uop_28_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_29_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_29_br_mask_T_1 = rob_uop_29_br_mask & _rob_uop_29_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_30_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_30_br_mask_T_1 = rob_uop_30_br_mask & _rob_uop_30_br_mask_T; // @[util.scala:89:{21,23}]
wire [7:0] _rob_uop_31_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [7:0] _rob_uop_31_br_mask_T_1 = rob_uop_31_br_mask & _rob_uop_31_br_mask_T; // @[util.scala:89:{21,23}]
wire [31:0][4:0] _GEN_82 = {{rob_fflags_0_31}, {rob_fflags_0_30}, {rob_fflags_0_29}, {rob_fflags_0_28}, {rob_fflags_0_27}, {rob_fflags_0_26}, {rob_fflags_0_25}, {rob_fflags_0_24}, {rob_fflags_0_23}, {rob_fflags_0_22}, {rob_fflags_0_21}, {rob_fflags_0_20}, {rob_fflags_0_19}, {rob_fflags_0_18}, {rob_fflags_0_17}, {rob_fflags_0_16}, {rob_fflags_0_15}, {rob_fflags_0_14}, {rob_fflags_0_13}, {rob_fflags_0_12}, {rob_fflags_0_11}, {rob_fflags_0_10}, {rob_fflags_0_9}, {rob_fflags_0_8}, {rob_fflags_0_7}, {rob_fflags_0_6}, {rob_fflags_0_5}, {rob_fflags_0_4}, {rob_fflags_0_3}, {rob_fflags_0_2}, {rob_fflags_0_1}, {rob_fflags_0_0}}; // @[rob.scala:302:46, :487:26]
assign rob_head_fflags_0 = _GEN_82[rob_head]; // @[rob.scala:223:29, :251:33, :487:26]
assign rob_head_uses_ldq_0 = _GEN_58[rob_head]; // @[rob.scala:223:29, :250:33, :415:25, :488:26]
assign rob_head_uses_stq_0 = _GEN_59[rob_head]; // @[rob.scala:223:29, :249:33, :415:25, :488:26]
wire _rob_unsafe_masked_0_T = rob_unsafe_0 | rob_exception_0; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_0_T_1 = rob_val_0 & _rob_unsafe_masked_0_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_0 = _rob_unsafe_masked_0_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_1_T = rob_unsafe_1 | rob_exception_1; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_1_T_1 = rob_val_1 & _rob_unsafe_masked_1_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_1 = _rob_unsafe_masked_1_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_2_T = rob_unsafe_2 | rob_exception_2; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_2_T_1 = rob_val_2 & _rob_unsafe_masked_2_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_2 = _rob_unsafe_masked_2_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_3_T = rob_unsafe_3 | rob_exception_3; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_3_T_1 = rob_val_3 & _rob_unsafe_masked_3_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_3 = _rob_unsafe_masked_3_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_4_T = rob_unsafe_4 | rob_exception_4; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_4_T_1 = rob_val_4 & _rob_unsafe_masked_4_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_4 = _rob_unsafe_masked_4_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_5_T = rob_unsafe_5 | rob_exception_5; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_5_T_1 = rob_val_5 & _rob_unsafe_masked_5_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_5 = _rob_unsafe_masked_5_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_6_T = rob_unsafe_6 | rob_exception_6; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_6_T_1 = rob_val_6 & _rob_unsafe_masked_6_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_6 = _rob_unsafe_masked_6_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_7_T = rob_unsafe_7 | rob_exception_7; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_7_T_1 = rob_val_7 & _rob_unsafe_masked_7_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_7 = _rob_unsafe_masked_7_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_8_T = rob_unsafe_8 | rob_exception_8; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_8_T_1 = rob_val_8 & _rob_unsafe_masked_8_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_8 = _rob_unsafe_masked_8_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_9_T = rob_unsafe_9 | rob_exception_9; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_9_T_1 = rob_val_9 & _rob_unsafe_masked_9_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_9 = _rob_unsafe_masked_9_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_10_T = rob_unsafe_10 | rob_exception_10; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_10_T_1 = rob_val_10 & _rob_unsafe_masked_10_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_10 = _rob_unsafe_masked_10_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_11_T = rob_unsafe_11 | rob_exception_11; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_11_T_1 = rob_val_11 & _rob_unsafe_masked_11_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_11 = _rob_unsafe_masked_11_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_12_T = rob_unsafe_12 | rob_exception_12; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_12_T_1 = rob_val_12 & _rob_unsafe_masked_12_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_12 = _rob_unsafe_masked_12_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_13_T = rob_unsafe_13 | rob_exception_13; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_13_T_1 = rob_val_13 & _rob_unsafe_masked_13_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_13 = _rob_unsafe_masked_13_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_14_T = rob_unsafe_14 | rob_exception_14; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_14_T_1 = rob_val_14 & _rob_unsafe_masked_14_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_14 = _rob_unsafe_masked_14_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_15_T = rob_unsafe_15 | rob_exception_15; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_15_T_1 = rob_val_15 & _rob_unsafe_masked_15_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_15 = _rob_unsafe_masked_15_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_16_T = rob_unsafe_16 | rob_exception_16; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_16_T_1 = rob_val_16 & _rob_unsafe_masked_16_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_16 = _rob_unsafe_masked_16_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_17_T = rob_unsafe_17 | rob_exception_17; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_17_T_1 = rob_val_17 & _rob_unsafe_masked_17_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_17 = _rob_unsafe_masked_17_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_18_T = rob_unsafe_18 | rob_exception_18; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_18_T_1 = rob_val_18 & _rob_unsafe_masked_18_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_18 = _rob_unsafe_masked_18_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_19_T = rob_unsafe_19 | rob_exception_19; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_19_T_1 = rob_val_19 & _rob_unsafe_masked_19_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_19 = _rob_unsafe_masked_19_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_20_T = rob_unsafe_20 | rob_exception_20; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_20_T_1 = rob_val_20 & _rob_unsafe_masked_20_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_20 = _rob_unsafe_masked_20_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_21_T = rob_unsafe_21 | rob_exception_21; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_21_T_1 = rob_val_21 & _rob_unsafe_masked_21_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_21 = _rob_unsafe_masked_21_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_22_T = rob_unsafe_22 | rob_exception_22; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_22_T_1 = rob_val_22 & _rob_unsafe_masked_22_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_22 = _rob_unsafe_masked_22_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_23_T = rob_unsafe_23 | rob_exception_23; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_23_T_1 = rob_val_23 & _rob_unsafe_masked_23_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_23 = _rob_unsafe_masked_23_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_24_T = rob_unsafe_24 | rob_exception_24; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_24_T_1 = rob_val_24 & _rob_unsafe_masked_24_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_24 = _rob_unsafe_masked_24_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_25_T = rob_unsafe_25 | rob_exception_25; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_25_T_1 = rob_val_25 & _rob_unsafe_masked_25_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_25 = _rob_unsafe_masked_25_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_26_T = rob_unsafe_26 | rob_exception_26; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_26_T_1 = rob_val_26 & _rob_unsafe_masked_26_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_26 = _rob_unsafe_masked_26_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_27_T = rob_unsafe_27 | rob_exception_27; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_27_T_1 = rob_val_27 & _rob_unsafe_masked_27_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_27 = _rob_unsafe_masked_27_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_28_T = rob_unsafe_28 | rob_exception_28; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_28_T_1 = rob_val_28 & _rob_unsafe_masked_28_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_28 = _rob_unsafe_masked_28_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_29_T = rob_unsafe_29 | rob_exception_29; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_29_T_1 = rob_val_29 & _rob_unsafe_masked_29_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_29 = _rob_unsafe_masked_29_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_30_T = rob_unsafe_30 | rob_exception_30; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_30_T_1 = rob_val_30 & _rob_unsafe_masked_30_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_30 = _rob_unsafe_masked_30_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_31_T = rob_unsafe_31 | rob_exception_31; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_31_T_1 = rob_val_31 & _rob_unsafe_masked_31_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_31 = _rob_unsafe_masked_31_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_pnr_unsafe_0_T = _GEN_2[rob_pnr] | _GEN_3[rob_pnr]; // @[rob.scala:231:29, :394:15, :402:49, :497:67]
assign _rob_pnr_unsafe_0_T_1 = _GEN[rob_pnr] & _rob_pnr_unsafe_0_T; // @[rob.scala:231:29, :324:31, :497:{43,67}]
assign rob_pnr_unsafe_0 = _rob_pnr_unsafe_0_T_1; // @[rob.scala:246:33, :497:43]
wire _block_commit_T = rob_state != 2'h1; // @[rob.scala:220:26, :544:33]
wire _block_commit_T_1 = rob_state != 2'h3; // @[rob.scala:220:26, :544:61]
wire _block_commit_T_2 = _block_commit_T & _block_commit_T_1; // @[rob.scala:544:{33,47,61}]
reg block_commit_REG; // @[rob.scala:544:94]
wire _block_commit_T_3 = _block_commit_T_2 | block_commit_REG; // @[rob.scala:544:{47,84,94}]
reg block_commit_REG_1; // @[rob.scala:544:131]
reg block_commit_REG_2; // @[rob.scala:544:123]
wire block_commit = _block_commit_T_3 | block_commit_REG_2; // @[rob.scala:544:{84,113,123}]
assign exception_thrown = can_throw_exception_0 & ~block_commit; // @[rob.scala:244:33, :253:30, :544:113, :549:{52,55}]
wire _will_commit_0_T = ~can_throw_exception_0; // @[rob.scala:244:33, :551:46]
wire _will_commit_0_T_1 = can_commit_0 & _will_commit_0_T; // @[rob.scala:243:33, :551:{43,46}]
wire _will_commit_0_T_2 = ~block_commit; // @[rob.scala:544:113, :549:55, :551:73]
assign _will_commit_0_T_3 = _will_commit_0_T_1 & _will_commit_0_T_2; // @[rob.scala:551:{43,70,73}]
assign will_commit_0 = _will_commit_0_T_3; // @[rob.scala:242:33, :551:70]
wire _is_mini_exception_T = io_com_xcpt_bits_cause_0 == 64'h10; // @[package.scala:16:47]
wire _is_mini_exception_T_1 = io_com_xcpt_bits_cause_0 == 64'h11; // @[package.scala:16:47]
wire is_mini_exception = _is_mini_exception_T | _is_mini_exception_T_1; // @[package.scala:16:47, :81:59]
wire _io_com_xcpt_valid_T = ~is_mini_exception; // @[package.scala:81:59]
assign _io_com_xcpt_valid_T_1 = exception_thrown & _io_com_xcpt_valid_T; // @[rob.scala:253:30, :561:{41,44}]
assign io_com_xcpt_valid_0 = _io_com_xcpt_valid_T_1; // @[rob.scala:211:7, :561:41]
wire _io_com_xcpt_bits_badvaddr_T = r_xcpt_badvaddr[39]; // @[util.scala:261:46]
wire [23:0] _io_com_xcpt_bits_badvaddr_T_1 = {24{_io_com_xcpt_bits_badvaddr_T}}; // @[util.scala:261:{25,46}]
assign _io_com_xcpt_bits_badvaddr_T_2 = {_io_com_xcpt_bits_badvaddr_T_1, r_xcpt_badvaddr}; // @[util.scala:261:{20,25}]
assign io_com_xcpt_bits_badvaddr_0 = _io_com_xcpt_bits_badvaddr_T_2; // @[util.scala:261:20]
wire insn_sys_pc2epc = rob_head_vals_0 & io_commit_uops_0_is_sys_pc2epc_0; // @[rob.scala:211:7, :247:33, :567:31]
wire refetch_inst = exception_thrown | insn_sys_pc2epc; // @[rob.scala:253:30, :567:31, :569:39]
wire flush_commit_mask_0 = io_commit_valids_0_0 & io_commit_uops_0_flush_on_commit_0; // @[rob.scala:211:7, :576:75]
assign flush_val = exception_thrown | flush_commit_mask_0; // @[rob.scala:253:30, :576:75, :578:36]
assign io_flush_valid_0 = flush_val; // @[rob.scala:211:7, :578:36]
assign io_flush_bits_is_rvc_0 = flush_uop_is_rvc; // @[rob.scala:211:7, :583:22]
assign io_flush_bits_ftq_idx_0 = flush_uop_ftq_idx; // @[rob.scala:211:7, :583:22]
assign io_flush_bits_edge_inst_0 = flush_uop_edge_inst; // @[rob.scala:211:7, :583:22]
assign io_flush_bits_pc_lob_0 = flush_uop_pc_lob; // @[rob.scala:211:7, :583:22]
wire _io_flush_bits_flush_typ_T = ~is_mini_exception; // @[package.scala:81:59]
wire _io_flush_bits_flush_typ_T_1 = exception_thrown & _io_flush_bits_flush_typ_T; // @[rob.scala:253:30, :593:{66,69}]
wire _io_flush_bits_flush_typ_T_2 = flush_uop_uopc == 7'h6A; // @[rob.scala:583:22, :594:80]
wire _io_flush_bits_flush_typ_T_3 = flush_commit_mask_0 & _io_flush_bits_flush_typ_T_2; // @[rob.scala:576:75, :594:{62,80}]
wire _io_flush_bits_flush_typ_ret_T = ~flush_val; // @[rob.scala:172:11, :578:36]
wire [2:0] _io_flush_bits_flush_typ_ret_T_1 = refetch_inst ? 3'h2 : 3'h4; // @[rob.scala:175:10, :569:39]
wire [2:0] _io_flush_bits_flush_typ_ret_T_2 = _io_flush_bits_flush_typ_T_1 ? 3'h1 : _io_flush_bits_flush_typ_ret_T_1; // @[rob.scala:174:10, :175:10, :593:66]
wire [2:0] _io_flush_bits_flush_typ_ret_T_3 = _io_flush_bits_flush_typ_T_3 ? 3'h3 : _io_flush_bits_flush_typ_ret_T_2; // @[rob.scala:173:10, :174:10, :594:62]
assign io_flush_bits_flush_typ_ret = _io_flush_bits_flush_typ_ret_T ? 3'h0 : _io_flush_bits_flush_typ_ret_T_3; // @[rob.scala:172:{10,11}, :173:10]
assign io_flush_bits_flush_typ_0 = io_flush_bits_flush_typ_ret; // @[rob.scala:172:10, :211:7]
wire _fflags_val_0_T_2; // @[rob.scala:608:32]
assign io_commit_fflags_valid_0 = fflags_val_0; // @[rob.scala:211:7, :602:24]
wire [4:0] _fflags_0_T; // @[rob.scala:611:21]
assign io_commit_fflags_bits_0 = fflags_0; // @[rob.scala:211:7, :603:24]
wire _fflags_val_0_T = io_commit_valids_0_0 & io_commit_uops_0_fp_val_0; // @[rob.scala:211:7, :607:27]
wire _fflags_val_0_T_1 = ~io_commit_uops_0_uses_stq_0; // @[rob.scala:211:7, :609:7]
assign _fflags_val_0_T_2 = _fflags_val_0_T & _fflags_val_0_T_1; // @[rob.scala:607:27, :608:32, :609:7]
assign fflags_val_0 = _fflags_val_0_T_2; // @[rob.scala:602:24, :608:32]
assign _fflags_0_T = fflags_val_0 ? rob_head_fflags_0 : 5'h0; // @[rob.scala:251:33, :602:24, :611:21]
assign fflags_0 = _fflags_0_T; // @[rob.scala:603:24, :611:21]
wire [3:0] next_xcpt_uop_ctrl_br_type; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_ctrl_op1_sel; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_ctrl_op2_sel; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_ctrl_imm_sel; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_ctrl_op_fcn; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_fcn_dw; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_ctrl_csr_cmd; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_is_load; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_is_sta; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_is_std; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_uopc; // @[rob.scala:630:27]
wire [31:0] next_xcpt_uop_inst; // @[rob.scala:630:27]
wire [31:0] next_xcpt_uop_debug_inst; // @[rob.scala:630:27]
wire next_xcpt_uop_is_rvc; // @[rob.scala:630:27]
wire [39:0] next_xcpt_uop_debug_pc; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_iq_type; // @[rob.scala:630:27]
wire [9:0] next_xcpt_uop_fu_code; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_iw_state; // @[rob.scala:630:27]
wire next_xcpt_uop_iw_p1_poisoned; // @[rob.scala:630:27]
wire next_xcpt_uop_iw_p2_poisoned; // @[rob.scala:630:27]
wire next_xcpt_uop_is_br; // @[rob.scala:630:27]
wire next_xcpt_uop_is_jalr; // @[rob.scala:630:27]
wire next_xcpt_uop_is_jal; // @[rob.scala:630:27]
wire next_xcpt_uop_is_sfb; // @[rob.scala:630:27]
wire [7:0] next_xcpt_uop_br_mask; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_br_tag; // @[rob.scala:630:27]
wire [3:0] next_xcpt_uop_ftq_idx; // @[rob.scala:630:27]
wire next_xcpt_uop_edge_inst; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_pc_lob; // @[rob.scala:630:27]
wire next_xcpt_uop_taken; // @[rob.scala:630:27]
wire [19:0] next_xcpt_uop_imm_packed; // @[rob.scala:630:27]
wire [11:0] next_xcpt_uop_csr_addr; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_rob_idx; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_ldq_idx; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_stq_idx; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_rxq_idx; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_pdst; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_prs1; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_prs2; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_prs3; // @[rob.scala:630:27]
wire [3:0] next_xcpt_uop_ppred; // @[rob.scala:630:27]
wire next_xcpt_uop_prs1_busy; // @[rob.scala:630:27]
wire next_xcpt_uop_prs2_busy; // @[rob.scala:630:27]
wire next_xcpt_uop_prs3_busy; // @[rob.scala:630:27]
wire next_xcpt_uop_ppred_busy; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_stale_pdst; // @[rob.scala:630:27]
wire next_xcpt_uop_exception; // @[rob.scala:630:27]
wire [63:0] next_xcpt_uop_exc_cause; // @[rob.scala:630:27]
wire next_xcpt_uop_bypassable; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_mem_cmd; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_mem_size; // @[rob.scala:630:27]
wire next_xcpt_uop_mem_signed; // @[rob.scala:630:27]
wire next_xcpt_uop_is_fence; // @[rob.scala:630:27]
wire next_xcpt_uop_is_fencei; // @[rob.scala:630:27]
wire next_xcpt_uop_is_amo; // @[rob.scala:630:27]
wire next_xcpt_uop_uses_ldq; // @[rob.scala:630:27]
wire next_xcpt_uop_uses_stq; // @[rob.scala:630:27]
wire next_xcpt_uop_is_sys_pc2epc; // @[rob.scala:630:27]
wire next_xcpt_uop_is_unique; // @[rob.scala:630:27]
wire next_xcpt_uop_flush_on_commit; // @[rob.scala:630:27]
wire next_xcpt_uop_ldst_is_rs1; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_ldst; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_lrs1; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_lrs2; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_lrs3; // @[rob.scala:630:27]
wire next_xcpt_uop_ldst_val; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_dst_rtype; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_lrs1_rtype; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_lrs2_rtype; // @[rob.scala:630:27]
wire next_xcpt_uop_frs3_en; // @[rob.scala:630:27]
wire next_xcpt_uop_fp_val; // @[rob.scala:630:27]
wire next_xcpt_uop_fp_single; // @[rob.scala:630:27]
wire next_xcpt_uop_xcpt_pf_if; // @[rob.scala:630:27]
wire next_xcpt_uop_xcpt_ae_if; // @[rob.scala:630:27]
wire next_xcpt_uop_xcpt_ma_if; // @[rob.scala:630:27]
wire next_xcpt_uop_bp_debug_if; // @[rob.scala:630:27]
wire next_xcpt_uop_bp_xcpt_if; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_debug_fsrc; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_debug_tsrc; // @[rob.scala:630:27]
wire _enq_xcpts_0_T; // @[rob.scala:634:38]
wire enq_xcpts_0; // @[rob.scala:632:23]
assign _enq_xcpts_0_T = io_enq_valids_0_0 & io_enq_uops_0_exception_0; // @[rob.scala:211:7, :634:38]
assign enq_xcpts_0 = _enq_xcpts_0_T; // @[rob.scala:632:23, :634:38]
wire _T_270 = ~(io_flush_valid_0 | exception_thrown) & rob_state != 2'h2; // @[rob.scala:211:7, :220:26, :253:30, :637:{9,26,47,60}]
wire _lxcpt_older_T_1 = io_lxcpt_bits_uop_rob_idx_0 < io_csr_replay_bits_uop_rob_idx_0; // @[util.scala:363:52]
wire _lxcpt_older_T_2 = io_lxcpt_bits_uop_rob_idx_0 < rob_head; // @[util.scala:363:64]
wire _lxcpt_older_T_3 = _lxcpt_older_T_1 ^ _lxcpt_older_T_2; // @[util.scala:363:{52,58,64}]
wire _lxcpt_older_T_4 = io_csr_replay_bits_uop_rob_idx_0 < rob_head; // @[util.scala:363:78]
wire _lxcpt_older_T_5 = _lxcpt_older_T_3 ^ _lxcpt_older_T_4; // @[util.scala:363:{58,72,78}]
wire _lxcpt_older_T_6 = _lxcpt_older_T_5 & io_lxcpt_valid_0; // @[util.scala:363:72]
wire _T_277 = ~r_xcpt_val | new_xcpt_uop_rob_idx < r_xcpt_uop_rob_idx ^ new_xcpt_uop_rob_idx < rob_head ^ r_xcpt_uop_rob_idx < rob_head; // @[util.scala:363:{52,58,64,72,78}]
wire _T_279 = ~r_xcpt_val & enq_xcpts_0; // @[rob.scala:257:33, :632:23, :650:{18,30}]
assign next_xcpt_uop_uopc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_uopc : r_xcpt_uop_uopc) : _T_279 ? io_enq_uops_0_uopc_0 : r_xcpt_uop_uopc) : r_xcpt_uop_uopc; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_inst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_inst : r_xcpt_uop_inst) : _T_279 ? io_enq_uops_0_inst_0 : r_xcpt_uop_inst) : r_xcpt_uop_inst; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_debug_inst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_inst : r_xcpt_uop_debug_inst) : _T_279 ? io_enq_uops_0_debug_inst_0 : r_xcpt_uop_debug_inst) : r_xcpt_uop_debug_inst; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_rvc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_rvc : r_xcpt_uop_is_rvc) : _T_279 ? io_enq_uops_0_is_rvc_0 : r_xcpt_uop_is_rvc) : r_xcpt_uop_is_rvc; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_debug_pc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_pc : r_xcpt_uop_debug_pc) : _T_279 ? io_enq_uops_0_debug_pc_0 : r_xcpt_uop_debug_pc) : r_xcpt_uop_debug_pc; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_iq_type = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iq_type : r_xcpt_uop_iq_type) : _T_279 ? io_enq_uops_0_iq_type_0 : r_xcpt_uop_iq_type) : r_xcpt_uop_iq_type; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_fu_code = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_fu_code : r_xcpt_uop_fu_code) : _T_279 ? io_enq_uops_0_fu_code_0 : r_xcpt_uop_fu_code) : r_xcpt_uop_fu_code; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_br_type = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_br_type : r_xcpt_uop_ctrl_br_type) : _T_279 ? io_enq_uops_0_ctrl_br_type_0 : r_xcpt_uop_ctrl_br_type) : r_xcpt_uop_ctrl_br_type; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_op1_sel = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_op1_sel : r_xcpt_uop_ctrl_op1_sel) : _T_279 ? io_enq_uops_0_ctrl_op1_sel_0 : r_xcpt_uop_ctrl_op1_sel) : r_xcpt_uop_ctrl_op1_sel; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_op2_sel = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_op2_sel : r_xcpt_uop_ctrl_op2_sel) : _T_279 ? io_enq_uops_0_ctrl_op2_sel_0 : r_xcpt_uop_ctrl_op2_sel) : r_xcpt_uop_ctrl_op2_sel; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_imm_sel = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_imm_sel : r_xcpt_uop_ctrl_imm_sel) : _T_279 ? io_enq_uops_0_ctrl_imm_sel_0 : r_xcpt_uop_ctrl_imm_sel) : r_xcpt_uop_ctrl_imm_sel; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_op_fcn = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_op_fcn : r_xcpt_uop_ctrl_op_fcn) : _T_279 ? io_enq_uops_0_ctrl_op_fcn_0 : r_xcpt_uop_ctrl_op_fcn) : r_xcpt_uop_ctrl_op_fcn; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_fcn_dw = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_fcn_dw : r_xcpt_uop_ctrl_fcn_dw) : _T_279 ? io_enq_uops_0_ctrl_fcn_dw_0 : r_xcpt_uop_ctrl_fcn_dw) : r_xcpt_uop_ctrl_fcn_dw; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_csr_cmd = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_csr_cmd : r_xcpt_uop_ctrl_csr_cmd) : _T_279 ? io_enq_uops_0_ctrl_csr_cmd_0 : r_xcpt_uop_ctrl_csr_cmd) : r_xcpt_uop_ctrl_csr_cmd; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_is_load = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_is_load : r_xcpt_uop_ctrl_is_load) : _T_279 ? io_enq_uops_0_ctrl_is_load_0 : r_xcpt_uop_ctrl_is_load) : r_xcpt_uop_ctrl_is_load; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_is_sta = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_is_sta : r_xcpt_uop_ctrl_is_sta) : _T_279 ? io_enq_uops_0_ctrl_is_sta_0 : r_xcpt_uop_ctrl_is_sta) : r_xcpt_uop_ctrl_is_sta; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ctrl_is_std = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ctrl_is_std : r_xcpt_uop_ctrl_is_std) : _T_279 ? io_enq_uops_0_ctrl_is_std_0 : r_xcpt_uop_ctrl_is_std) : r_xcpt_uop_ctrl_is_std; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_iw_state = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iw_state : r_xcpt_uop_iw_state) : _T_279 ? io_enq_uops_0_iw_state_0 : r_xcpt_uop_iw_state) : r_xcpt_uop_iw_state; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_iw_p1_poisoned = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iw_p1_poisoned : r_xcpt_uop_iw_p1_poisoned) : _T_279 ? io_enq_uops_0_iw_p1_poisoned_0 : r_xcpt_uop_iw_p1_poisoned) : r_xcpt_uop_iw_p1_poisoned; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_iw_p2_poisoned = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_iw_p2_poisoned : r_xcpt_uop_iw_p2_poisoned) : _T_279 ? io_enq_uops_0_iw_p2_poisoned_0 : r_xcpt_uop_iw_p2_poisoned) : r_xcpt_uop_iw_p2_poisoned; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_br = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_br : r_xcpt_uop_is_br) : _T_279 ? io_enq_uops_0_is_br_0 : r_xcpt_uop_is_br) : r_xcpt_uop_is_br; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_jalr = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_jalr : r_xcpt_uop_is_jalr) : _T_279 ? io_enq_uops_0_is_jalr_0 : r_xcpt_uop_is_jalr) : r_xcpt_uop_is_jalr; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_jal = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_jal : r_xcpt_uop_is_jal) : _T_279 ? io_enq_uops_0_is_jal_0 : r_xcpt_uop_is_jal) : r_xcpt_uop_is_jal; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_sfb = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_sfb : r_xcpt_uop_is_sfb) : _T_279 ? io_enq_uops_0_is_sfb_0 : r_xcpt_uop_is_sfb) : r_xcpt_uop_is_sfb; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_br_mask = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_br_mask : r_xcpt_uop_br_mask) : _T_279 ? io_enq_uops_0_br_mask_0 : r_xcpt_uop_br_mask) : r_xcpt_uop_br_mask; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_br_tag = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_br_tag : r_xcpt_uop_br_tag) : _T_279 ? io_enq_uops_0_br_tag_0 : r_xcpt_uop_br_tag) : r_xcpt_uop_br_tag; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ftq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ftq_idx : r_xcpt_uop_ftq_idx) : _T_279 ? io_enq_uops_0_ftq_idx_0 : r_xcpt_uop_ftq_idx) : r_xcpt_uop_ftq_idx; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_edge_inst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_edge_inst : r_xcpt_uop_edge_inst) : _T_279 ? io_enq_uops_0_edge_inst_0 : r_xcpt_uop_edge_inst) : r_xcpt_uop_edge_inst; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_pc_lob = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_pc_lob : r_xcpt_uop_pc_lob) : _T_279 ? io_enq_uops_0_pc_lob_0 : r_xcpt_uop_pc_lob) : r_xcpt_uop_pc_lob; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_taken = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_taken : r_xcpt_uop_taken) : _T_279 ? io_enq_uops_0_taken_0 : r_xcpt_uop_taken) : r_xcpt_uop_taken; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_imm_packed = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_imm_packed : r_xcpt_uop_imm_packed) : _T_279 ? io_enq_uops_0_imm_packed_0 : r_xcpt_uop_imm_packed) : r_xcpt_uop_imm_packed; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_csr_addr = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_csr_addr : r_xcpt_uop_csr_addr) : _T_279 ? io_enq_uops_0_csr_addr_0 : r_xcpt_uop_csr_addr) : r_xcpt_uop_csr_addr; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_rob_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_rob_idx : r_xcpt_uop_rob_idx) : _T_279 ? io_enq_uops_0_rob_idx_0 : r_xcpt_uop_rob_idx) : r_xcpt_uop_rob_idx; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ldq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldq_idx : r_xcpt_uop_ldq_idx) : _T_279 ? io_enq_uops_0_ldq_idx_0 : r_xcpt_uop_ldq_idx) : r_xcpt_uop_ldq_idx; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_stq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_stq_idx : r_xcpt_uop_stq_idx) : _T_279 ? io_enq_uops_0_stq_idx_0 : r_xcpt_uop_stq_idx) : r_xcpt_uop_stq_idx; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_rxq_idx = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_rxq_idx : r_xcpt_uop_rxq_idx) : _T_279 ? io_enq_uops_0_rxq_idx_0 : r_xcpt_uop_rxq_idx) : r_xcpt_uop_rxq_idx; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_pdst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_pdst : r_xcpt_uop_pdst) : _T_279 ? io_enq_uops_0_pdst_0 : r_xcpt_uop_pdst) : r_xcpt_uop_pdst; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_prs1 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs1 : r_xcpt_uop_prs1) : _T_279 ? io_enq_uops_0_prs1_0 : r_xcpt_uop_prs1) : r_xcpt_uop_prs1; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_prs2 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs2 : r_xcpt_uop_prs2) : _T_279 ? io_enq_uops_0_prs2_0 : r_xcpt_uop_prs2) : r_xcpt_uop_prs2; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_prs3 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs3 : r_xcpt_uop_prs3) : _T_279 ? io_enq_uops_0_prs3_0 : r_xcpt_uop_prs3) : r_xcpt_uop_prs3; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ppred = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ppred : r_xcpt_uop_ppred) : _T_279 ? 4'h0 : r_xcpt_uop_ppred) : r_xcpt_uop_ppred; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_prs1_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs1_busy : r_xcpt_uop_prs1_busy) : _T_279 ? io_enq_uops_0_prs1_busy_0 : r_xcpt_uop_prs1_busy) : r_xcpt_uop_prs1_busy; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_prs2_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs2_busy : r_xcpt_uop_prs2_busy) : _T_279 ? io_enq_uops_0_prs2_busy_0 : r_xcpt_uop_prs2_busy) : r_xcpt_uop_prs2_busy; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_prs3_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_prs3_busy : r_xcpt_uop_prs3_busy) : _T_279 ? io_enq_uops_0_prs3_busy_0 : r_xcpt_uop_prs3_busy) : r_xcpt_uop_prs3_busy; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ppred_busy = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ppred_busy : r_xcpt_uop_ppred_busy) : ~_T_279 & r_xcpt_uop_ppred_busy) : r_xcpt_uop_ppred_busy; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_stale_pdst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_stale_pdst : r_xcpt_uop_stale_pdst) : _T_279 ? io_enq_uops_0_stale_pdst_0 : r_xcpt_uop_stale_pdst) : r_xcpt_uop_stale_pdst; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_exception = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_exception : r_xcpt_uop_exception) : _T_279 ? io_enq_uops_0_exception_0 : r_xcpt_uop_exception) : r_xcpt_uop_exception; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_exc_cause = _T_270 ? (new_xcpt_valid ? (_T_277 ? {59'h0, new_xcpt_cause} : r_xcpt_uop_exc_cause) : _T_279 ? io_enq_uops_0_exc_cause_0 : r_xcpt_uop_exc_cause) : r_xcpt_uop_exc_cause; // @[package.scala:16:47]
assign next_xcpt_uop_bypassable = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_bypassable : r_xcpt_uop_bypassable) : _T_279 ? io_enq_uops_0_bypassable_0 : r_xcpt_uop_bypassable) : r_xcpt_uop_bypassable; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_mem_cmd = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_mem_cmd : r_xcpt_uop_mem_cmd) : _T_279 ? io_enq_uops_0_mem_cmd_0 : r_xcpt_uop_mem_cmd) : r_xcpt_uop_mem_cmd; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_mem_size = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_mem_size : r_xcpt_uop_mem_size) : _T_279 ? io_enq_uops_0_mem_size_0 : r_xcpt_uop_mem_size) : r_xcpt_uop_mem_size; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_mem_signed = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_mem_signed : r_xcpt_uop_mem_signed) : _T_279 ? io_enq_uops_0_mem_signed_0 : r_xcpt_uop_mem_signed) : r_xcpt_uop_mem_signed; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_fence = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_fence : r_xcpt_uop_is_fence) : _T_279 ? io_enq_uops_0_is_fence_0 : r_xcpt_uop_is_fence) : r_xcpt_uop_is_fence; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_fencei = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_fencei : r_xcpt_uop_is_fencei) : _T_279 ? io_enq_uops_0_is_fencei_0 : r_xcpt_uop_is_fencei) : r_xcpt_uop_is_fencei; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_amo = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_amo : r_xcpt_uop_is_amo) : _T_279 ? io_enq_uops_0_is_amo_0 : r_xcpt_uop_is_amo) : r_xcpt_uop_is_amo; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_uses_ldq = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_uses_ldq : r_xcpt_uop_uses_ldq) : _T_279 ? io_enq_uops_0_uses_ldq_0 : r_xcpt_uop_uses_ldq) : r_xcpt_uop_uses_ldq; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_uses_stq = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_uses_stq : r_xcpt_uop_uses_stq) : _T_279 ? io_enq_uops_0_uses_stq_0 : r_xcpt_uop_uses_stq) : r_xcpt_uop_uses_stq; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_sys_pc2epc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_sys_pc2epc : r_xcpt_uop_is_sys_pc2epc) : _T_279 ? io_enq_uops_0_is_sys_pc2epc_0 : r_xcpt_uop_is_sys_pc2epc) : r_xcpt_uop_is_sys_pc2epc; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_is_unique = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_is_unique : r_xcpt_uop_is_unique) : _T_279 ? io_enq_uops_0_is_unique_0 : r_xcpt_uop_is_unique) : r_xcpt_uop_is_unique; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_flush_on_commit = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_flush_on_commit : r_xcpt_uop_flush_on_commit) : _T_279 ? io_enq_uops_0_flush_on_commit_0 : r_xcpt_uop_flush_on_commit) : r_xcpt_uop_flush_on_commit; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ldst_is_rs1 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldst_is_rs1 : r_xcpt_uop_ldst_is_rs1) : _T_279 ? io_enq_uops_0_ldst_is_rs1_0 : r_xcpt_uop_ldst_is_rs1) : r_xcpt_uop_ldst_is_rs1; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ldst = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldst : r_xcpt_uop_ldst) : _T_279 ? io_enq_uops_0_ldst_0 : r_xcpt_uop_ldst) : r_xcpt_uop_ldst; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_lrs1 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs1 : r_xcpt_uop_lrs1) : _T_279 ? io_enq_uops_0_lrs1_0 : r_xcpt_uop_lrs1) : r_xcpt_uop_lrs1; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_lrs2 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs2 : r_xcpt_uop_lrs2) : _T_279 ? io_enq_uops_0_lrs2_0 : r_xcpt_uop_lrs2) : r_xcpt_uop_lrs2; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_lrs3 = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs3 : r_xcpt_uop_lrs3) : _T_279 ? io_enq_uops_0_lrs3_0 : r_xcpt_uop_lrs3) : r_xcpt_uop_lrs3; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_ldst_val = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_ldst_val : r_xcpt_uop_ldst_val) : _T_279 ? io_enq_uops_0_ldst_val_0 : r_xcpt_uop_ldst_val) : r_xcpt_uop_ldst_val; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_dst_rtype = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_dst_rtype : r_xcpt_uop_dst_rtype) : _T_279 ? io_enq_uops_0_dst_rtype_0 : r_xcpt_uop_dst_rtype) : r_xcpt_uop_dst_rtype; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_lrs1_rtype = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs1_rtype : r_xcpt_uop_lrs1_rtype) : _T_279 ? io_enq_uops_0_lrs1_rtype_0 : r_xcpt_uop_lrs1_rtype) : r_xcpt_uop_lrs1_rtype; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_lrs2_rtype = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_lrs2_rtype : r_xcpt_uop_lrs2_rtype) : _T_279 ? io_enq_uops_0_lrs2_rtype_0 : r_xcpt_uop_lrs2_rtype) : r_xcpt_uop_lrs2_rtype; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_frs3_en = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_frs3_en : r_xcpt_uop_frs3_en) : _T_279 ? io_enq_uops_0_frs3_en_0 : r_xcpt_uop_frs3_en) : r_xcpt_uop_frs3_en; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_fp_val = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_fp_val : r_xcpt_uop_fp_val) : _T_279 ? io_enq_uops_0_fp_val_0 : r_xcpt_uop_fp_val) : r_xcpt_uop_fp_val; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_fp_single = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_fp_single : r_xcpt_uop_fp_single) : _T_279 ? io_enq_uops_0_fp_single_0 : r_xcpt_uop_fp_single) : r_xcpt_uop_fp_single; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_xcpt_pf_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_xcpt_pf_if : r_xcpt_uop_xcpt_pf_if) : _T_279 ? io_enq_uops_0_xcpt_pf_if_0 : r_xcpt_uop_xcpt_pf_if) : r_xcpt_uop_xcpt_pf_if; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_xcpt_ae_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_xcpt_ae_if : r_xcpt_uop_xcpt_ae_if) : _T_279 ? io_enq_uops_0_xcpt_ae_if_0 : r_xcpt_uop_xcpt_ae_if) : r_xcpt_uop_xcpt_ae_if; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_xcpt_ma_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_xcpt_ma_if : r_xcpt_uop_xcpt_ma_if) : _T_279 ? io_enq_uops_0_xcpt_ma_if_0 : r_xcpt_uop_xcpt_ma_if) : r_xcpt_uop_xcpt_ma_if; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_bp_debug_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_bp_debug_if : r_xcpt_uop_bp_debug_if) : _T_279 ? io_enq_uops_0_bp_debug_if_0 : r_xcpt_uop_bp_debug_if) : r_xcpt_uop_bp_debug_if; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_bp_xcpt_if = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_bp_xcpt_if : r_xcpt_uop_bp_xcpt_if) : _T_279 ? io_enq_uops_0_bp_xcpt_if_0 : r_xcpt_uop_bp_xcpt_if) : r_xcpt_uop_bp_xcpt_if; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_debug_fsrc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_fsrc : r_xcpt_uop_debug_fsrc) : _T_279 ? io_enq_uops_0_debug_fsrc_0 : r_xcpt_uop_debug_fsrc) : r_xcpt_uop_debug_fsrc; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_debug_tsrc = _T_270 ? (new_xcpt_valid ? (_T_277 ? new_xcpt_uop_debug_tsrc : r_xcpt_uop_debug_tsrc) : _T_279 ? io_enq_uops_0_debug_tsrc_0 : r_xcpt_uop_debug_tsrc) : r_xcpt_uop_debug_tsrc; // @[rob.scala:211:7, :258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
wire [39:0] _r_xcpt_badvaddr_T = ~io_xcpt_fetch_pc_0; // @[util.scala:237:7]
wire [39:0] _r_xcpt_badvaddr_T_1 = {_r_xcpt_badvaddr_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] _r_xcpt_badvaddr_T_2 = ~_r_xcpt_badvaddr_T_1; // @[util.scala:237:{5,11}]
wire [39:0] _r_xcpt_badvaddr_T_3 = {_r_xcpt_badvaddr_T_2[39:6], _r_xcpt_badvaddr_T_2[5:0] | io_enq_uops_0_pc_lob_0}; // @[util.scala:237:5]
wire [7:0] _r_xcpt_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [7:0] _r_xcpt_uop_br_mask_T_1 = next_xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire rob_deq; // @[rob.scala:685:25]
reg r_partial_row; // @[rob.scala:686:30]
wire _finished_committing_row_T_1 = will_commit_0 ^ rob_head_vals_0; // @[rob.scala:242:33, :247:33, :694:26]
wire _finished_committing_row_T_2 = ~_finished_committing_row_T_1; // @[rob.scala:694:{26,50}]
wire _finished_committing_row_T_3 = _finished_committing_row_T & _finished_committing_row_T_2; // @[rob.scala:693:{30,39}, :694:50]
wire _T_339 = rob_head == rob_tail; // @[rob.scala:223:29, :227:29, :695:33]
wire _finished_committing_row_T_4; // @[rob.scala:695:33]
assign _finished_committing_row_T_4 = _T_339; // @[rob.scala:695:33]
wire _full_T; // @[rob.scala:796:26]
assign _full_T = _T_339; // @[rob.scala:695:33, :796:26]
wire _empty_T; // @[rob.scala:797:27]
assign _empty_T = _T_339; // @[rob.scala:695:33, :797:27]
wire _finished_committing_row_T_5 = r_partial_row & _finished_committing_row_T_4; // @[rob.scala:686:30, :695:{21,33}]
wire _finished_committing_row_T_6 = ~maybe_full; // @[rob.scala:238:29, :695:49]
wire _finished_committing_row_T_7 = _finished_committing_row_T_5 & _finished_committing_row_T_6; // @[rob.scala:695:{21,46,49}]
wire _finished_committing_row_T_8 = ~_finished_committing_row_T_7; // @[rob.scala:695:{5,46}]
wire finished_committing_row = _finished_committing_row_T_3 & _finished_committing_row_T_8; // @[rob.scala:693:39, :694:59, :695:5]
wire [5:0] _rob_head_T = {1'h0, rob_head} + 6'h1; // @[util.scala:203:14]
wire [4:0] _rob_head_T_1 = _rob_head_T[4:0]; // @[util.scala:203:14]
wire [4:0] _rob_head_T_2 = _rob_head_T_1; // @[util.scala:203:{14,20}]
wire _rob_head_lsb_T_1 = _rob_head_lsb_T; // @[OneHot.scala:85:71]
reg pnr_maybe_at_tail; // @[rob.scala:723:36]
wire _T_349 = rob_state == 2'h1; // @[rob.scala:220:26, :725:33]
wire _safe_to_inc_T; // @[rob.scala:725:33]
assign _safe_to_inc_T = _T_349; // @[rob.scala:725:33]
wire _io_ready_T; // @[rob.scala:803:33]
assign _io_ready_T = _T_349; // @[rob.scala:725:33, :803:33]
wire _safe_to_inc_T_1 = &rob_state; // @[rob.scala:220:26, :725:59]
wire safe_to_inc = _safe_to_inc_T | _safe_to_inc_T_1; // @[rob.scala:725:{33,46,59}]
wire _do_inc_row_T = ~rob_pnr_unsafe_0; // @[rob.scala:246:33, :726:23]
wire _do_inc_row_T_1 = rob_pnr != rob_tail; // @[rob.scala:227:29, :231:29, :726:64]
wire _do_inc_row_T_2 = ~pnr_maybe_at_tail; // @[rob.scala:723:36, :726:89]
wire _do_inc_row_T_3 = full & _do_inc_row_T_2; // @[rob.scala:239:26, :726:{86,89}]
wire _do_inc_row_T_4 = _do_inc_row_T_1 | _do_inc_row_T_3; // @[rob.scala:726:{64,77,86}]
wire do_inc_row = _do_inc_row_T & _do_inc_row_T_4; // @[rob.scala:726:{23,52,77}]
wire [5:0] _rob_pnr_T = {1'h0, rob_pnr} + 6'h1; // @[util.scala:203:14]
wire [4:0] _rob_pnr_T_1 = _rob_pnr_T[4:0]; // @[util.scala:203:14]
wire [4:0] _rob_pnr_T_2 = _rob_pnr_T_1; // @[util.scala:203:{14,20}]
wire _rob_pnr_lsb_T_1 = ~_rob_pnr_lsb_T; // @[util.scala:373:29]
wire _rob_pnr_lsb_T_2 = rob_pnr_unsafe_0 | _rob_pnr_lsb_T_1; // @[rob.scala:246:33, :740:{60,62}]
wire _rob_pnr_lsb_T_3 = _rob_pnr_lsb_T_2; // @[OneHot.scala:48:45]
wire _pnr_maybe_at_tail_T = ~rob_deq; // @[rob.scala:685:25, :745:26]
wire _pnr_maybe_at_tail_T_1 = do_inc_row | pnr_maybe_at_tail; // @[rob.scala:723:36, :726:52, :745:50]
wire _pnr_maybe_at_tail_T_2 = _pnr_maybe_at_tail_T & _pnr_maybe_at_tail_T_1; // @[rob.scala:745:{26,35,50}] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_38 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_38( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ALU_2 :
input clock : Clock
input reset : Reset
output io : { flip dw : UInt<1>, flip fn : UInt<5>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>}
node _in2_inv_T = bits(io.fn, 3, 3)
node _in2_inv_T_1 = not(io.in2)
node in2_inv = mux(_in2_inv_T, _in2_inv_T_1, io.in2)
node in1_xor_in2 = xor(io.in1, in2_inv)
node in1_and_in2 = and(io.in1, in2_inv)
node _io_adder_out_T = add(io.in1, in2_inv)
node _io_adder_out_T_1 = tail(_io_adder_out_T, 1)
node _io_adder_out_T_2 = bits(io.fn, 3, 3)
node _io_adder_out_T_3 = add(_io_adder_out_T_1, _io_adder_out_T_2)
node _io_adder_out_T_4 = tail(_io_adder_out_T_3, 1)
connect io.adder_out, _io_adder_out_T_4
node _slt_T = bits(io.in1, 63, 63)
node _slt_T_1 = bits(io.in2, 63, 63)
node _slt_T_2 = eq(_slt_T, _slt_T_1)
node _slt_T_3 = bits(io.adder_out, 63, 63)
node _slt_T_4 = bits(io.fn, 1, 1)
node _slt_T_5 = bits(io.in2, 63, 63)
node _slt_T_6 = bits(io.in1, 63, 63)
node _slt_T_7 = mux(_slt_T_4, _slt_T_5, _slt_T_6)
node slt = mux(_slt_T_2, _slt_T_3, _slt_T_7)
node _io_cmp_out_T = bits(io.fn, 0, 0)
node _io_cmp_out_T_1 = bits(io.fn, 3, 3)
node _io_cmp_out_T_2 = eq(_io_cmp_out_T_1, UInt<1>(0h0))
node _io_cmp_out_T_3 = eq(in1_xor_in2, UInt<1>(0h0))
node _io_cmp_out_T_4 = mux(_io_cmp_out_T_2, _io_cmp_out_T_3, slt)
node _io_cmp_out_T_5 = xor(_io_cmp_out_T, _io_cmp_out_T_4)
connect io.cmp_out, _io_cmp_out_T_5
node _shin_hi_32_T = bits(io.fn, 3, 3)
node _shin_hi_32_T_1 = bits(io.in1, 31, 31)
node _shin_hi_32_T_2 = and(_shin_hi_32_T, _shin_hi_32_T_1)
node shin_hi_32 = mux(_shin_hi_32_T_2, UInt<32>(0hffffffff), UInt<32>(0h0))
node _shin_hi_T = eq(io.dw, UInt<1>(0h1))
node _shin_hi_T_1 = bits(io.in1, 63, 32)
node shin_hi = mux(_shin_hi_T, _shin_hi_T_1, shin_hi_32)
node _shamt_T = bits(io.in2, 5, 5)
node _shamt_T_1 = eq(io.dw, UInt<1>(0h1))
node _shamt_T_2 = and(_shamt_T, _shamt_T_1)
node _shamt_T_3 = bits(io.in2, 4, 0)
node shamt = cat(_shamt_T_2, _shamt_T_3)
node _T = bits(io.in1, 31, 0)
node shin_r = cat(shin_hi, _T)
node _shin_T = eq(io.fn, UInt<3>(0h5))
node _shin_T_1 = eq(io.fn, UInt<4>(0hb))
node _shin_T_2 = eq(io.fn, UInt<5>(0h12))
node _shin_T_3 = eq(io.fn, UInt<5>(0h13))
node _shin_T_4 = or(_shin_T, _shin_T_1)
node _shin_T_5 = or(_shin_T_4, _shin_T_2)
node _shin_T_6 = or(_shin_T_5, _shin_T_3)
node _shin_T_7 = eq(_shin_T_6, UInt<1>(0h0))
node _shin_T_8 = shl(UInt<32>(0hffffffff), 32)
node _shin_T_9 = xor(UInt<64>(0hffffffffffffffff), _shin_T_8)
node _shin_T_10 = shr(shin_r, 32)
node _shin_T_11 = and(_shin_T_10, _shin_T_9)
node _shin_T_12 = bits(shin_r, 31, 0)
node _shin_T_13 = shl(_shin_T_12, 32)
node _shin_T_14 = not(_shin_T_9)
node _shin_T_15 = and(_shin_T_13, _shin_T_14)
node _shin_T_16 = or(_shin_T_11, _shin_T_15)
node _shin_T_17 = bits(_shin_T_9, 47, 0)
node _shin_T_18 = shl(_shin_T_17, 16)
node _shin_T_19 = xor(_shin_T_9, _shin_T_18)
node _shin_T_20 = shr(_shin_T_16, 16)
node _shin_T_21 = and(_shin_T_20, _shin_T_19)
node _shin_T_22 = bits(_shin_T_16, 47, 0)
node _shin_T_23 = shl(_shin_T_22, 16)
node _shin_T_24 = not(_shin_T_19)
node _shin_T_25 = and(_shin_T_23, _shin_T_24)
node _shin_T_26 = or(_shin_T_21, _shin_T_25)
node _shin_T_27 = bits(_shin_T_19, 55, 0)
node _shin_T_28 = shl(_shin_T_27, 8)
node _shin_T_29 = xor(_shin_T_19, _shin_T_28)
node _shin_T_30 = shr(_shin_T_26, 8)
node _shin_T_31 = and(_shin_T_30, _shin_T_29)
node _shin_T_32 = bits(_shin_T_26, 55, 0)
node _shin_T_33 = shl(_shin_T_32, 8)
node _shin_T_34 = not(_shin_T_29)
node _shin_T_35 = and(_shin_T_33, _shin_T_34)
node _shin_T_36 = or(_shin_T_31, _shin_T_35)
node _shin_T_37 = bits(_shin_T_29, 59, 0)
node _shin_T_38 = shl(_shin_T_37, 4)
node _shin_T_39 = xor(_shin_T_29, _shin_T_38)
node _shin_T_40 = shr(_shin_T_36, 4)
node _shin_T_41 = and(_shin_T_40, _shin_T_39)
node _shin_T_42 = bits(_shin_T_36, 59, 0)
node _shin_T_43 = shl(_shin_T_42, 4)
node _shin_T_44 = not(_shin_T_39)
node _shin_T_45 = and(_shin_T_43, _shin_T_44)
node _shin_T_46 = or(_shin_T_41, _shin_T_45)
node _shin_T_47 = bits(_shin_T_39, 61, 0)
node _shin_T_48 = shl(_shin_T_47, 2)
node _shin_T_49 = xor(_shin_T_39, _shin_T_48)
node _shin_T_50 = shr(_shin_T_46, 2)
node _shin_T_51 = and(_shin_T_50, _shin_T_49)
node _shin_T_52 = bits(_shin_T_46, 61, 0)
node _shin_T_53 = shl(_shin_T_52, 2)
node _shin_T_54 = not(_shin_T_49)
node _shin_T_55 = and(_shin_T_53, _shin_T_54)
node _shin_T_56 = or(_shin_T_51, _shin_T_55)
node _shin_T_57 = bits(_shin_T_49, 62, 0)
node _shin_T_58 = shl(_shin_T_57, 1)
node _shin_T_59 = xor(_shin_T_49, _shin_T_58)
node _shin_T_60 = shr(_shin_T_56, 1)
node _shin_T_61 = and(_shin_T_60, _shin_T_59)
node _shin_T_62 = bits(_shin_T_56, 62, 0)
node _shin_T_63 = shl(_shin_T_62, 1)
node _shin_T_64 = not(_shin_T_59)
node _shin_T_65 = and(_shin_T_63, _shin_T_64)
node _shin_T_66 = or(_shin_T_61, _shin_T_65)
node shin = mux(_shin_T_7, _shin_T_66, shin_r)
node _shout_r_T = bits(io.fn, 3, 3)
node _shout_r_T_1 = bits(shin, 63, 63)
node _shout_r_T_2 = and(_shout_r_T, _shout_r_T_1)
node _shout_r_T_3 = cat(_shout_r_T_2, shin)
node _shout_r_T_4 = asSInt(_shout_r_T_3)
node _shout_r_T_5 = dshr(_shout_r_T_4, shamt)
node shout_r = bits(_shout_r_T_5, 63, 0)
node _shout_l_T = shl(UInt<32>(0hffffffff), 32)
node _shout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _shout_l_T)
node _shout_l_T_2 = shr(shout_r, 32)
node _shout_l_T_3 = and(_shout_l_T_2, _shout_l_T_1)
node _shout_l_T_4 = bits(shout_r, 31, 0)
node _shout_l_T_5 = shl(_shout_l_T_4, 32)
node _shout_l_T_6 = not(_shout_l_T_1)
node _shout_l_T_7 = and(_shout_l_T_5, _shout_l_T_6)
node _shout_l_T_8 = or(_shout_l_T_3, _shout_l_T_7)
node _shout_l_T_9 = bits(_shout_l_T_1, 47, 0)
node _shout_l_T_10 = shl(_shout_l_T_9, 16)
node _shout_l_T_11 = xor(_shout_l_T_1, _shout_l_T_10)
node _shout_l_T_12 = shr(_shout_l_T_8, 16)
node _shout_l_T_13 = and(_shout_l_T_12, _shout_l_T_11)
node _shout_l_T_14 = bits(_shout_l_T_8, 47, 0)
node _shout_l_T_15 = shl(_shout_l_T_14, 16)
node _shout_l_T_16 = not(_shout_l_T_11)
node _shout_l_T_17 = and(_shout_l_T_15, _shout_l_T_16)
node _shout_l_T_18 = or(_shout_l_T_13, _shout_l_T_17)
node _shout_l_T_19 = bits(_shout_l_T_11, 55, 0)
node _shout_l_T_20 = shl(_shout_l_T_19, 8)
node _shout_l_T_21 = xor(_shout_l_T_11, _shout_l_T_20)
node _shout_l_T_22 = shr(_shout_l_T_18, 8)
node _shout_l_T_23 = and(_shout_l_T_22, _shout_l_T_21)
node _shout_l_T_24 = bits(_shout_l_T_18, 55, 0)
node _shout_l_T_25 = shl(_shout_l_T_24, 8)
node _shout_l_T_26 = not(_shout_l_T_21)
node _shout_l_T_27 = and(_shout_l_T_25, _shout_l_T_26)
node _shout_l_T_28 = or(_shout_l_T_23, _shout_l_T_27)
node _shout_l_T_29 = bits(_shout_l_T_21, 59, 0)
node _shout_l_T_30 = shl(_shout_l_T_29, 4)
node _shout_l_T_31 = xor(_shout_l_T_21, _shout_l_T_30)
node _shout_l_T_32 = shr(_shout_l_T_28, 4)
node _shout_l_T_33 = and(_shout_l_T_32, _shout_l_T_31)
node _shout_l_T_34 = bits(_shout_l_T_28, 59, 0)
node _shout_l_T_35 = shl(_shout_l_T_34, 4)
node _shout_l_T_36 = not(_shout_l_T_31)
node _shout_l_T_37 = and(_shout_l_T_35, _shout_l_T_36)
node _shout_l_T_38 = or(_shout_l_T_33, _shout_l_T_37)
node _shout_l_T_39 = bits(_shout_l_T_31, 61, 0)
node _shout_l_T_40 = shl(_shout_l_T_39, 2)
node _shout_l_T_41 = xor(_shout_l_T_31, _shout_l_T_40)
node _shout_l_T_42 = shr(_shout_l_T_38, 2)
node _shout_l_T_43 = and(_shout_l_T_42, _shout_l_T_41)
node _shout_l_T_44 = bits(_shout_l_T_38, 61, 0)
node _shout_l_T_45 = shl(_shout_l_T_44, 2)
node _shout_l_T_46 = not(_shout_l_T_41)
node _shout_l_T_47 = and(_shout_l_T_45, _shout_l_T_46)
node _shout_l_T_48 = or(_shout_l_T_43, _shout_l_T_47)
node _shout_l_T_49 = bits(_shout_l_T_41, 62, 0)
node _shout_l_T_50 = shl(_shout_l_T_49, 1)
node _shout_l_T_51 = xor(_shout_l_T_41, _shout_l_T_50)
node _shout_l_T_52 = shr(_shout_l_T_48, 1)
node _shout_l_T_53 = and(_shout_l_T_52, _shout_l_T_51)
node _shout_l_T_54 = bits(_shout_l_T_48, 62, 0)
node _shout_l_T_55 = shl(_shout_l_T_54, 1)
node _shout_l_T_56 = not(_shout_l_T_51)
node _shout_l_T_57 = and(_shout_l_T_55, _shout_l_T_56)
node shout_l = or(_shout_l_T_53, _shout_l_T_57)
node _shout_T = eq(io.fn, UInt<3>(0h5))
node _shout_T_1 = eq(io.fn, UInt<4>(0hb))
node _shout_T_2 = or(_shout_T, _shout_T_1)
node _shout_T_3 = eq(io.fn, UInt<5>(0h13))
node _shout_T_4 = or(_shout_T_2, _shout_T_3)
node _shout_T_5 = mux(_shout_T_4, shout_r, UInt<1>(0h0))
node _shout_T_6 = eq(io.fn, UInt<1>(0h1))
node _shout_T_7 = mux(_shout_T_6, shout_l, UInt<1>(0h0))
node shout = or(_shout_T_5, _shout_T_7)
node in2_not_zero = orr(io.in2)
node _logic_T = eq(io.fn, UInt<3>(0h4))
node _logic_T_1 = eq(io.fn, UInt<3>(0h6))
node _logic_T_2 = or(_logic_T, _logic_T_1)
node _logic_T_3 = eq(io.fn, UInt<5>(0h19))
node _logic_T_4 = or(_logic_T_2, _logic_T_3)
node _logic_T_5 = eq(io.fn, UInt<5>(0h1a))
node _logic_T_6 = or(_logic_T_4, _logic_T_5)
node _logic_T_7 = mux(_logic_T_6, in1_xor_in2, UInt<1>(0h0))
node _logic_T_8 = eq(io.fn, UInt<3>(0h6))
node _logic_T_9 = eq(io.fn, UInt<3>(0h7))
node _logic_T_10 = or(_logic_T_8, _logic_T_9)
node _logic_T_11 = eq(io.fn, UInt<5>(0h19))
node _logic_T_12 = or(_logic_T_10, _logic_T_11)
node _logic_T_13 = eq(io.fn, UInt<5>(0h18))
node _logic_T_14 = or(_logic_T_12, _logic_T_13)
node _logic_T_15 = mux(_logic_T_14, in1_and_in2, UInt<1>(0h0))
node logic = or(_logic_T_7, _logic_T_15)
node _bext_mask_T = eq(io.fn, UInt<5>(0h13))
node _bext_mask_T_1 = and(UInt<1>(0h1), _bext_mask_T)
node _bext_mask_T_2 = not(UInt<64>(0h0))
node bext_mask = mux(_bext_mask_T_1, UInt<1>(0h1), _bext_mask_T_2)
node _shift_logic_T = geq(io.fn, UInt<4>(0hc))
node _shift_logic_T_1 = leq(io.fn, UInt<4>(0hf))
node _shift_logic_T_2 = and(_shift_logic_T, _shift_logic_T_1)
node _shift_logic_T_3 = and(_shift_logic_T_2, slt)
node _shift_logic_T_4 = or(_shift_logic_T_3, logic)
node _shift_logic_T_5 = and(shout, bext_mask)
node shift_logic = or(_shift_logic_T_4, _shift_logic_T_5)
node _tz_in_T = eq(io.dw, UInt<1>(0h0))
node _tz_in_T_1 = bits(io.in2, 0, 0)
node _tz_in_T_2 = eq(_tz_in_T_1, UInt<1>(0h0))
node _tz_in_T_3 = cat(_tz_in_T, _tz_in_T_2)
node _tz_in_T_4 = shl(UInt<32>(0hffffffff), 32)
node _tz_in_T_5 = xor(UInt<64>(0hffffffffffffffff), _tz_in_T_4)
node _tz_in_T_6 = shr(io.in1, 32)
node _tz_in_T_7 = and(_tz_in_T_6, _tz_in_T_5)
node _tz_in_T_8 = bits(io.in1, 31, 0)
node _tz_in_T_9 = shl(_tz_in_T_8, 32)
node _tz_in_T_10 = not(_tz_in_T_5)
node _tz_in_T_11 = and(_tz_in_T_9, _tz_in_T_10)
node _tz_in_T_12 = or(_tz_in_T_7, _tz_in_T_11)
node _tz_in_T_13 = bits(_tz_in_T_5, 47, 0)
node _tz_in_T_14 = shl(_tz_in_T_13, 16)
node _tz_in_T_15 = xor(_tz_in_T_5, _tz_in_T_14)
node _tz_in_T_16 = shr(_tz_in_T_12, 16)
node _tz_in_T_17 = and(_tz_in_T_16, _tz_in_T_15)
node _tz_in_T_18 = bits(_tz_in_T_12, 47, 0)
node _tz_in_T_19 = shl(_tz_in_T_18, 16)
node _tz_in_T_20 = not(_tz_in_T_15)
node _tz_in_T_21 = and(_tz_in_T_19, _tz_in_T_20)
node _tz_in_T_22 = or(_tz_in_T_17, _tz_in_T_21)
node _tz_in_T_23 = bits(_tz_in_T_15, 55, 0)
node _tz_in_T_24 = shl(_tz_in_T_23, 8)
node _tz_in_T_25 = xor(_tz_in_T_15, _tz_in_T_24)
node _tz_in_T_26 = shr(_tz_in_T_22, 8)
node _tz_in_T_27 = and(_tz_in_T_26, _tz_in_T_25)
node _tz_in_T_28 = bits(_tz_in_T_22, 55, 0)
node _tz_in_T_29 = shl(_tz_in_T_28, 8)
node _tz_in_T_30 = not(_tz_in_T_25)
node _tz_in_T_31 = and(_tz_in_T_29, _tz_in_T_30)
node _tz_in_T_32 = or(_tz_in_T_27, _tz_in_T_31)
node _tz_in_T_33 = bits(_tz_in_T_25, 59, 0)
node _tz_in_T_34 = shl(_tz_in_T_33, 4)
node _tz_in_T_35 = xor(_tz_in_T_25, _tz_in_T_34)
node _tz_in_T_36 = shr(_tz_in_T_32, 4)
node _tz_in_T_37 = and(_tz_in_T_36, _tz_in_T_35)
node _tz_in_T_38 = bits(_tz_in_T_32, 59, 0)
node _tz_in_T_39 = shl(_tz_in_T_38, 4)
node _tz_in_T_40 = not(_tz_in_T_35)
node _tz_in_T_41 = and(_tz_in_T_39, _tz_in_T_40)
node _tz_in_T_42 = or(_tz_in_T_37, _tz_in_T_41)
node _tz_in_T_43 = bits(_tz_in_T_35, 61, 0)
node _tz_in_T_44 = shl(_tz_in_T_43, 2)
node _tz_in_T_45 = xor(_tz_in_T_35, _tz_in_T_44)
node _tz_in_T_46 = shr(_tz_in_T_42, 2)
node _tz_in_T_47 = and(_tz_in_T_46, _tz_in_T_45)
node _tz_in_T_48 = bits(_tz_in_T_42, 61, 0)
node _tz_in_T_49 = shl(_tz_in_T_48, 2)
node _tz_in_T_50 = not(_tz_in_T_45)
node _tz_in_T_51 = and(_tz_in_T_49, _tz_in_T_50)
node _tz_in_T_52 = or(_tz_in_T_47, _tz_in_T_51)
node _tz_in_T_53 = bits(_tz_in_T_45, 62, 0)
node _tz_in_T_54 = shl(_tz_in_T_53, 1)
node _tz_in_T_55 = xor(_tz_in_T_45, _tz_in_T_54)
node _tz_in_T_56 = shr(_tz_in_T_52, 1)
node _tz_in_T_57 = and(_tz_in_T_56, _tz_in_T_55)
node _tz_in_T_58 = bits(_tz_in_T_52, 62, 0)
node _tz_in_T_59 = shl(_tz_in_T_58, 1)
node _tz_in_T_60 = not(_tz_in_T_55)
node _tz_in_T_61 = and(_tz_in_T_59, _tz_in_T_60)
node _tz_in_T_62 = or(_tz_in_T_57, _tz_in_T_61)
node _tz_in_T_63 = bits(io.in1, 31, 0)
node _tz_in_T_64 = cat(UInt<1>(0h1), _tz_in_T_63)
node _tz_in_T_65 = bits(io.in1, 31, 0)
node _tz_in_T_66 = shl(UInt<16>(0hffff), 16)
node _tz_in_T_67 = xor(UInt<32>(0hffffffff), _tz_in_T_66)
node _tz_in_T_68 = shr(_tz_in_T_65, 16)
node _tz_in_T_69 = and(_tz_in_T_68, _tz_in_T_67)
node _tz_in_T_70 = bits(_tz_in_T_65, 15, 0)
node _tz_in_T_71 = shl(_tz_in_T_70, 16)
node _tz_in_T_72 = not(_tz_in_T_67)
node _tz_in_T_73 = and(_tz_in_T_71, _tz_in_T_72)
node _tz_in_T_74 = or(_tz_in_T_69, _tz_in_T_73)
node _tz_in_T_75 = bits(_tz_in_T_67, 23, 0)
node _tz_in_T_76 = shl(_tz_in_T_75, 8)
node _tz_in_T_77 = xor(_tz_in_T_67, _tz_in_T_76)
node _tz_in_T_78 = shr(_tz_in_T_74, 8)
node _tz_in_T_79 = and(_tz_in_T_78, _tz_in_T_77)
node _tz_in_T_80 = bits(_tz_in_T_74, 23, 0)
node _tz_in_T_81 = shl(_tz_in_T_80, 8)
node _tz_in_T_82 = not(_tz_in_T_77)
node _tz_in_T_83 = and(_tz_in_T_81, _tz_in_T_82)
node _tz_in_T_84 = or(_tz_in_T_79, _tz_in_T_83)
node _tz_in_T_85 = bits(_tz_in_T_77, 27, 0)
node _tz_in_T_86 = shl(_tz_in_T_85, 4)
node _tz_in_T_87 = xor(_tz_in_T_77, _tz_in_T_86)
node _tz_in_T_88 = shr(_tz_in_T_84, 4)
node _tz_in_T_89 = and(_tz_in_T_88, _tz_in_T_87)
node _tz_in_T_90 = bits(_tz_in_T_84, 27, 0)
node _tz_in_T_91 = shl(_tz_in_T_90, 4)
node _tz_in_T_92 = not(_tz_in_T_87)
node _tz_in_T_93 = and(_tz_in_T_91, _tz_in_T_92)
node _tz_in_T_94 = or(_tz_in_T_89, _tz_in_T_93)
node _tz_in_T_95 = bits(_tz_in_T_87, 29, 0)
node _tz_in_T_96 = shl(_tz_in_T_95, 2)
node _tz_in_T_97 = xor(_tz_in_T_87, _tz_in_T_96)
node _tz_in_T_98 = shr(_tz_in_T_94, 2)
node _tz_in_T_99 = and(_tz_in_T_98, _tz_in_T_97)
node _tz_in_T_100 = bits(_tz_in_T_94, 29, 0)
node _tz_in_T_101 = shl(_tz_in_T_100, 2)
node _tz_in_T_102 = not(_tz_in_T_97)
node _tz_in_T_103 = and(_tz_in_T_101, _tz_in_T_102)
node _tz_in_T_104 = or(_tz_in_T_99, _tz_in_T_103)
node _tz_in_T_105 = bits(_tz_in_T_97, 30, 0)
node _tz_in_T_106 = shl(_tz_in_T_105, 1)
node _tz_in_T_107 = xor(_tz_in_T_97, _tz_in_T_106)
node _tz_in_T_108 = shr(_tz_in_T_104, 1)
node _tz_in_T_109 = and(_tz_in_T_108, _tz_in_T_107)
node _tz_in_T_110 = bits(_tz_in_T_104, 30, 0)
node _tz_in_T_111 = shl(_tz_in_T_110, 1)
node _tz_in_T_112 = not(_tz_in_T_107)
node _tz_in_T_113 = and(_tz_in_T_111, _tz_in_T_112)
node _tz_in_T_114 = or(_tz_in_T_109, _tz_in_T_113)
node _tz_in_T_115 = cat(UInt<1>(0h1), _tz_in_T_114)
node _tz_in_T_116 = eq(UInt<1>(0h1), _tz_in_T_3)
node _tz_in_T_117 = mux(_tz_in_T_116, _tz_in_T_62, io.in1)
node _tz_in_T_118 = eq(UInt<2>(0h2), _tz_in_T_3)
node _tz_in_T_119 = mux(_tz_in_T_118, _tz_in_T_64, _tz_in_T_117)
node _tz_in_T_120 = eq(UInt<2>(0h3), _tz_in_T_3)
node tz_in = mux(_tz_in_T_120, _tz_in_T_115, _tz_in_T_119)
node _popc_in_T = bits(io.in2, 1, 1)
node _popc_in_T_1 = eq(io.dw, UInt<1>(0h0))
node _popc_in_T_2 = bits(io.in1, 31, 0)
node _popc_in_T_3 = mux(_popc_in_T_1, _popc_in_T_2, io.in1)
node _popc_in_T_4 = cat(UInt<1>(0h1), tz_in)
node _popc_in_T_5 = bits(_popc_in_T_4, 0, 0)
node _popc_in_T_6 = bits(_popc_in_T_4, 1, 1)
node _popc_in_T_7 = bits(_popc_in_T_4, 2, 2)
node _popc_in_T_8 = bits(_popc_in_T_4, 3, 3)
node _popc_in_T_9 = bits(_popc_in_T_4, 4, 4)
node _popc_in_T_10 = bits(_popc_in_T_4, 5, 5)
node _popc_in_T_11 = bits(_popc_in_T_4, 6, 6)
node _popc_in_T_12 = bits(_popc_in_T_4, 7, 7)
node _popc_in_T_13 = bits(_popc_in_T_4, 8, 8)
node _popc_in_T_14 = bits(_popc_in_T_4, 9, 9)
node _popc_in_T_15 = bits(_popc_in_T_4, 10, 10)
node _popc_in_T_16 = bits(_popc_in_T_4, 11, 11)
node _popc_in_T_17 = bits(_popc_in_T_4, 12, 12)
node _popc_in_T_18 = bits(_popc_in_T_4, 13, 13)
node _popc_in_T_19 = bits(_popc_in_T_4, 14, 14)
node _popc_in_T_20 = bits(_popc_in_T_4, 15, 15)
node _popc_in_T_21 = bits(_popc_in_T_4, 16, 16)
node _popc_in_T_22 = bits(_popc_in_T_4, 17, 17)
node _popc_in_T_23 = bits(_popc_in_T_4, 18, 18)
node _popc_in_T_24 = bits(_popc_in_T_4, 19, 19)
node _popc_in_T_25 = bits(_popc_in_T_4, 20, 20)
node _popc_in_T_26 = bits(_popc_in_T_4, 21, 21)
node _popc_in_T_27 = bits(_popc_in_T_4, 22, 22)
node _popc_in_T_28 = bits(_popc_in_T_4, 23, 23)
node _popc_in_T_29 = bits(_popc_in_T_4, 24, 24)
node _popc_in_T_30 = bits(_popc_in_T_4, 25, 25)
node _popc_in_T_31 = bits(_popc_in_T_4, 26, 26)
node _popc_in_T_32 = bits(_popc_in_T_4, 27, 27)
node _popc_in_T_33 = bits(_popc_in_T_4, 28, 28)
node _popc_in_T_34 = bits(_popc_in_T_4, 29, 29)
node _popc_in_T_35 = bits(_popc_in_T_4, 30, 30)
node _popc_in_T_36 = bits(_popc_in_T_4, 31, 31)
node _popc_in_T_37 = bits(_popc_in_T_4, 32, 32)
node _popc_in_T_38 = bits(_popc_in_T_4, 33, 33)
node _popc_in_T_39 = bits(_popc_in_T_4, 34, 34)
node _popc_in_T_40 = bits(_popc_in_T_4, 35, 35)
node _popc_in_T_41 = bits(_popc_in_T_4, 36, 36)
node _popc_in_T_42 = bits(_popc_in_T_4, 37, 37)
node _popc_in_T_43 = bits(_popc_in_T_4, 38, 38)
node _popc_in_T_44 = bits(_popc_in_T_4, 39, 39)
node _popc_in_T_45 = bits(_popc_in_T_4, 40, 40)
node _popc_in_T_46 = bits(_popc_in_T_4, 41, 41)
node _popc_in_T_47 = bits(_popc_in_T_4, 42, 42)
node _popc_in_T_48 = bits(_popc_in_T_4, 43, 43)
node _popc_in_T_49 = bits(_popc_in_T_4, 44, 44)
node _popc_in_T_50 = bits(_popc_in_T_4, 45, 45)
node _popc_in_T_51 = bits(_popc_in_T_4, 46, 46)
node _popc_in_T_52 = bits(_popc_in_T_4, 47, 47)
node _popc_in_T_53 = bits(_popc_in_T_4, 48, 48)
node _popc_in_T_54 = bits(_popc_in_T_4, 49, 49)
node _popc_in_T_55 = bits(_popc_in_T_4, 50, 50)
node _popc_in_T_56 = bits(_popc_in_T_4, 51, 51)
node _popc_in_T_57 = bits(_popc_in_T_4, 52, 52)
node _popc_in_T_58 = bits(_popc_in_T_4, 53, 53)
node _popc_in_T_59 = bits(_popc_in_T_4, 54, 54)
node _popc_in_T_60 = bits(_popc_in_T_4, 55, 55)
node _popc_in_T_61 = bits(_popc_in_T_4, 56, 56)
node _popc_in_T_62 = bits(_popc_in_T_4, 57, 57)
node _popc_in_T_63 = bits(_popc_in_T_4, 58, 58)
node _popc_in_T_64 = bits(_popc_in_T_4, 59, 59)
node _popc_in_T_65 = bits(_popc_in_T_4, 60, 60)
node _popc_in_T_66 = bits(_popc_in_T_4, 61, 61)
node _popc_in_T_67 = bits(_popc_in_T_4, 62, 62)
node _popc_in_T_68 = bits(_popc_in_T_4, 63, 63)
node _popc_in_T_69 = bits(_popc_in_T_4, 64, 64)
node _popc_in_T_70 = mux(_popc_in_T_69, UInt<65>(0h10000000000000000), UInt<65>(0h0))
node _popc_in_T_71 = mux(_popc_in_T_68, UInt<65>(0h8000000000000000), _popc_in_T_70)
node _popc_in_T_72 = mux(_popc_in_T_67, UInt<65>(0h4000000000000000), _popc_in_T_71)
node _popc_in_T_73 = mux(_popc_in_T_66, UInt<65>(0h2000000000000000), _popc_in_T_72)
node _popc_in_T_74 = mux(_popc_in_T_65, UInt<65>(0h1000000000000000), _popc_in_T_73)
node _popc_in_T_75 = mux(_popc_in_T_64, UInt<65>(0h800000000000000), _popc_in_T_74)
node _popc_in_T_76 = mux(_popc_in_T_63, UInt<65>(0h400000000000000), _popc_in_T_75)
node _popc_in_T_77 = mux(_popc_in_T_62, UInt<65>(0h200000000000000), _popc_in_T_76)
node _popc_in_T_78 = mux(_popc_in_T_61, UInt<65>(0h100000000000000), _popc_in_T_77)
node _popc_in_T_79 = mux(_popc_in_T_60, UInt<65>(0h80000000000000), _popc_in_T_78)
node _popc_in_T_80 = mux(_popc_in_T_59, UInt<65>(0h40000000000000), _popc_in_T_79)
node _popc_in_T_81 = mux(_popc_in_T_58, UInt<65>(0h20000000000000), _popc_in_T_80)
node _popc_in_T_82 = mux(_popc_in_T_57, UInt<65>(0h10000000000000), _popc_in_T_81)
node _popc_in_T_83 = mux(_popc_in_T_56, UInt<65>(0h8000000000000), _popc_in_T_82)
node _popc_in_T_84 = mux(_popc_in_T_55, UInt<65>(0h4000000000000), _popc_in_T_83)
node _popc_in_T_85 = mux(_popc_in_T_54, UInt<65>(0h2000000000000), _popc_in_T_84)
node _popc_in_T_86 = mux(_popc_in_T_53, UInt<65>(0h1000000000000), _popc_in_T_85)
node _popc_in_T_87 = mux(_popc_in_T_52, UInt<65>(0h800000000000), _popc_in_T_86)
node _popc_in_T_88 = mux(_popc_in_T_51, UInt<65>(0h400000000000), _popc_in_T_87)
node _popc_in_T_89 = mux(_popc_in_T_50, UInt<65>(0h200000000000), _popc_in_T_88)
node _popc_in_T_90 = mux(_popc_in_T_49, UInt<65>(0h100000000000), _popc_in_T_89)
node _popc_in_T_91 = mux(_popc_in_T_48, UInt<65>(0h80000000000), _popc_in_T_90)
node _popc_in_T_92 = mux(_popc_in_T_47, UInt<65>(0h40000000000), _popc_in_T_91)
node _popc_in_T_93 = mux(_popc_in_T_46, UInt<65>(0h20000000000), _popc_in_T_92)
node _popc_in_T_94 = mux(_popc_in_T_45, UInt<65>(0h10000000000), _popc_in_T_93)
node _popc_in_T_95 = mux(_popc_in_T_44, UInt<65>(0h8000000000), _popc_in_T_94)
node _popc_in_T_96 = mux(_popc_in_T_43, UInt<65>(0h4000000000), _popc_in_T_95)
node _popc_in_T_97 = mux(_popc_in_T_42, UInt<65>(0h2000000000), _popc_in_T_96)
node _popc_in_T_98 = mux(_popc_in_T_41, UInt<65>(0h1000000000), _popc_in_T_97)
node _popc_in_T_99 = mux(_popc_in_T_40, UInt<65>(0h800000000), _popc_in_T_98)
node _popc_in_T_100 = mux(_popc_in_T_39, UInt<65>(0h400000000), _popc_in_T_99)
node _popc_in_T_101 = mux(_popc_in_T_38, UInt<65>(0h200000000), _popc_in_T_100)
node _popc_in_T_102 = mux(_popc_in_T_37, UInt<65>(0h100000000), _popc_in_T_101)
node _popc_in_T_103 = mux(_popc_in_T_36, UInt<65>(0h80000000), _popc_in_T_102)
node _popc_in_T_104 = mux(_popc_in_T_35, UInt<65>(0h40000000), _popc_in_T_103)
node _popc_in_T_105 = mux(_popc_in_T_34, UInt<65>(0h20000000), _popc_in_T_104)
node _popc_in_T_106 = mux(_popc_in_T_33, UInt<65>(0h10000000), _popc_in_T_105)
node _popc_in_T_107 = mux(_popc_in_T_32, UInt<65>(0h8000000), _popc_in_T_106)
node _popc_in_T_108 = mux(_popc_in_T_31, UInt<65>(0h4000000), _popc_in_T_107)
node _popc_in_T_109 = mux(_popc_in_T_30, UInt<65>(0h2000000), _popc_in_T_108)
node _popc_in_T_110 = mux(_popc_in_T_29, UInt<65>(0h1000000), _popc_in_T_109)
node _popc_in_T_111 = mux(_popc_in_T_28, UInt<65>(0h800000), _popc_in_T_110)
node _popc_in_T_112 = mux(_popc_in_T_27, UInt<65>(0h400000), _popc_in_T_111)
node _popc_in_T_113 = mux(_popc_in_T_26, UInt<65>(0h200000), _popc_in_T_112)
node _popc_in_T_114 = mux(_popc_in_T_25, UInt<65>(0h100000), _popc_in_T_113)
node _popc_in_T_115 = mux(_popc_in_T_24, UInt<65>(0h80000), _popc_in_T_114)
node _popc_in_T_116 = mux(_popc_in_T_23, UInt<65>(0h40000), _popc_in_T_115)
node _popc_in_T_117 = mux(_popc_in_T_22, UInt<65>(0h20000), _popc_in_T_116)
node _popc_in_T_118 = mux(_popc_in_T_21, UInt<65>(0h10000), _popc_in_T_117)
node _popc_in_T_119 = mux(_popc_in_T_20, UInt<65>(0h8000), _popc_in_T_118)
node _popc_in_T_120 = mux(_popc_in_T_19, UInt<65>(0h4000), _popc_in_T_119)
node _popc_in_T_121 = mux(_popc_in_T_18, UInt<65>(0h2000), _popc_in_T_120)
node _popc_in_T_122 = mux(_popc_in_T_17, UInt<65>(0h1000), _popc_in_T_121)
node _popc_in_T_123 = mux(_popc_in_T_16, UInt<65>(0h800), _popc_in_T_122)
node _popc_in_T_124 = mux(_popc_in_T_15, UInt<65>(0h400), _popc_in_T_123)
node _popc_in_T_125 = mux(_popc_in_T_14, UInt<65>(0h200), _popc_in_T_124)
node _popc_in_T_126 = mux(_popc_in_T_13, UInt<65>(0h100), _popc_in_T_125)
node _popc_in_T_127 = mux(_popc_in_T_12, UInt<65>(0h80), _popc_in_T_126)
node _popc_in_T_128 = mux(_popc_in_T_11, UInt<65>(0h40), _popc_in_T_127)
node _popc_in_T_129 = mux(_popc_in_T_10, UInt<65>(0h20), _popc_in_T_128)
node _popc_in_T_130 = mux(_popc_in_T_9, UInt<65>(0h10), _popc_in_T_129)
node _popc_in_T_131 = mux(_popc_in_T_8, UInt<65>(0h8), _popc_in_T_130)
node _popc_in_T_132 = mux(_popc_in_T_7, UInt<65>(0h4), _popc_in_T_131)
node _popc_in_T_133 = mux(_popc_in_T_6, UInt<65>(0h2), _popc_in_T_132)
node _popc_in_T_134 = mux(_popc_in_T_5, UInt<65>(0h1), _popc_in_T_133)
node _popc_in_T_135 = sub(_popc_in_T_134, UInt<1>(0h1))
node _popc_in_T_136 = tail(_popc_in_T_135, 1)
node _popc_in_T_137 = mux(_popc_in_T, _popc_in_T_3, _popc_in_T_136)
node popc_in = bits(_popc_in_T_137, 63, 0)
node _count_T = bits(popc_in, 0, 0)
node _count_T_1 = bits(popc_in, 1, 1)
node _count_T_2 = bits(popc_in, 2, 2)
node _count_T_3 = bits(popc_in, 3, 3)
node _count_T_4 = bits(popc_in, 4, 4)
node _count_T_5 = bits(popc_in, 5, 5)
node _count_T_6 = bits(popc_in, 6, 6)
node _count_T_7 = bits(popc_in, 7, 7)
node _count_T_8 = bits(popc_in, 8, 8)
node _count_T_9 = bits(popc_in, 9, 9)
node _count_T_10 = bits(popc_in, 10, 10)
node _count_T_11 = bits(popc_in, 11, 11)
node _count_T_12 = bits(popc_in, 12, 12)
node _count_T_13 = bits(popc_in, 13, 13)
node _count_T_14 = bits(popc_in, 14, 14)
node _count_T_15 = bits(popc_in, 15, 15)
node _count_T_16 = bits(popc_in, 16, 16)
node _count_T_17 = bits(popc_in, 17, 17)
node _count_T_18 = bits(popc_in, 18, 18)
node _count_T_19 = bits(popc_in, 19, 19)
node _count_T_20 = bits(popc_in, 20, 20)
node _count_T_21 = bits(popc_in, 21, 21)
node _count_T_22 = bits(popc_in, 22, 22)
node _count_T_23 = bits(popc_in, 23, 23)
node _count_T_24 = bits(popc_in, 24, 24)
node _count_T_25 = bits(popc_in, 25, 25)
node _count_T_26 = bits(popc_in, 26, 26)
node _count_T_27 = bits(popc_in, 27, 27)
node _count_T_28 = bits(popc_in, 28, 28)
node _count_T_29 = bits(popc_in, 29, 29)
node _count_T_30 = bits(popc_in, 30, 30)
node _count_T_31 = bits(popc_in, 31, 31)
node _count_T_32 = bits(popc_in, 32, 32)
node _count_T_33 = bits(popc_in, 33, 33)
node _count_T_34 = bits(popc_in, 34, 34)
node _count_T_35 = bits(popc_in, 35, 35)
node _count_T_36 = bits(popc_in, 36, 36)
node _count_T_37 = bits(popc_in, 37, 37)
node _count_T_38 = bits(popc_in, 38, 38)
node _count_T_39 = bits(popc_in, 39, 39)
node _count_T_40 = bits(popc_in, 40, 40)
node _count_T_41 = bits(popc_in, 41, 41)
node _count_T_42 = bits(popc_in, 42, 42)
node _count_T_43 = bits(popc_in, 43, 43)
node _count_T_44 = bits(popc_in, 44, 44)
node _count_T_45 = bits(popc_in, 45, 45)
node _count_T_46 = bits(popc_in, 46, 46)
node _count_T_47 = bits(popc_in, 47, 47)
node _count_T_48 = bits(popc_in, 48, 48)
node _count_T_49 = bits(popc_in, 49, 49)
node _count_T_50 = bits(popc_in, 50, 50)
node _count_T_51 = bits(popc_in, 51, 51)
node _count_T_52 = bits(popc_in, 52, 52)
node _count_T_53 = bits(popc_in, 53, 53)
node _count_T_54 = bits(popc_in, 54, 54)
node _count_T_55 = bits(popc_in, 55, 55)
node _count_T_56 = bits(popc_in, 56, 56)
node _count_T_57 = bits(popc_in, 57, 57)
node _count_T_58 = bits(popc_in, 58, 58)
node _count_T_59 = bits(popc_in, 59, 59)
node _count_T_60 = bits(popc_in, 60, 60)
node _count_T_61 = bits(popc_in, 61, 61)
node _count_T_62 = bits(popc_in, 62, 62)
node _count_T_63 = bits(popc_in, 63, 63)
node _count_T_64 = add(_count_T, _count_T_1)
node _count_T_65 = bits(_count_T_64, 1, 0)
node _count_T_66 = add(_count_T_2, _count_T_3)
node _count_T_67 = bits(_count_T_66, 1, 0)
node _count_T_68 = add(_count_T_65, _count_T_67)
node _count_T_69 = bits(_count_T_68, 2, 0)
node _count_T_70 = add(_count_T_4, _count_T_5)
node _count_T_71 = bits(_count_T_70, 1, 0)
node _count_T_72 = add(_count_T_6, _count_T_7)
node _count_T_73 = bits(_count_T_72, 1, 0)
node _count_T_74 = add(_count_T_71, _count_T_73)
node _count_T_75 = bits(_count_T_74, 2, 0)
node _count_T_76 = add(_count_T_69, _count_T_75)
node _count_T_77 = bits(_count_T_76, 3, 0)
node _count_T_78 = add(_count_T_8, _count_T_9)
node _count_T_79 = bits(_count_T_78, 1, 0)
node _count_T_80 = add(_count_T_10, _count_T_11)
node _count_T_81 = bits(_count_T_80, 1, 0)
node _count_T_82 = add(_count_T_79, _count_T_81)
node _count_T_83 = bits(_count_T_82, 2, 0)
node _count_T_84 = add(_count_T_12, _count_T_13)
node _count_T_85 = bits(_count_T_84, 1, 0)
node _count_T_86 = add(_count_T_14, _count_T_15)
node _count_T_87 = bits(_count_T_86, 1, 0)
node _count_T_88 = add(_count_T_85, _count_T_87)
node _count_T_89 = bits(_count_T_88, 2, 0)
node _count_T_90 = add(_count_T_83, _count_T_89)
node _count_T_91 = bits(_count_T_90, 3, 0)
node _count_T_92 = add(_count_T_77, _count_T_91)
node _count_T_93 = bits(_count_T_92, 4, 0)
node _count_T_94 = add(_count_T_16, _count_T_17)
node _count_T_95 = bits(_count_T_94, 1, 0)
node _count_T_96 = add(_count_T_18, _count_T_19)
node _count_T_97 = bits(_count_T_96, 1, 0)
node _count_T_98 = add(_count_T_95, _count_T_97)
node _count_T_99 = bits(_count_T_98, 2, 0)
node _count_T_100 = add(_count_T_20, _count_T_21)
node _count_T_101 = bits(_count_T_100, 1, 0)
node _count_T_102 = add(_count_T_22, _count_T_23)
node _count_T_103 = bits(_count_T_102, 1, 0)
node _count_T_104 = add(_count_T_101, _count_T_103)
node _count_T_105 = bits(_count_T_104, 2, 0)
node _count_T_106 = add(_count_T_99, _count_T_105)
node _count_T_107 = bits(_count_T_106, 3, 0)
node _count_T_108 = add(_count_T_24, _count_T_25)
node _count_T_109 = bits(_count_T_108, 1, 0)
node _count_T_110 = add(_count_T_26, _count_T_27)
node _count_T_111 = bits(_count_T_110, 1, 0)
node _count_T_112 = add(_count_T_109, _count_T_111)
node _count_T_113 = bits(_count_T_112, 2, 0)
node _count_T_114 = add(_count_T_28, _count_T_29)
node _count_T_115 = bits(_count_T_114, 1, 0)
node _count_T_116 = add(_count_T_30, _count_T_31)
node _count_T_117 = bits(_count_T_116, 1, 0)
node _count_T_118 = add(_count_T_115, _count_T_117)
node _count_T_119 = bits(_count_T_118, 2, 0)
node _count_T_120 = add(_count_T_113, _count_T_119)
node _count_T_121 = bits(_count_T_120, 3, 0)
node _count_T_122 = add(_count_T_107, _count_T_121)
node _count_T_123 = bits(_count_T_122, 4, 0)
node _count_T_124 = add(_count_T_93, _count_T_123)
node _count_T_125 = bits(_count_T_124, 5, 0)
node _count_T_126 = add(_count_T_32, _count_T_33)
node _count_T_127 = bits(_count_T_126, 1, 0)
node _count_T_128 = add(_count_T_34, _count_T_35)
node _count_T_129 = bits(_count_T_128, 1, 0)
node _count_T_130 = add(_count_T_127, _count_T_129)
node _count_T_131 = bits(_count_T_130, 2, 0)
node _count_T_132 = add(_count_T_36, _count_T_37)
node _count_T_133 = bits(_count_T_132, 1, 0)
node _count_T_134 = add(_count_T_38, _count_T_39)
node _count_T_135 = bits(_count_T_134, 1, 0)
node _count_T_136 = add(_count_T_133, _count_T_135)
node _count_T_137 = bits(_count_T_136, 2, 0)
node _count_T_138 = add(_count_T_131, _count_T_137)
node _count_T_139 = bits(_count_T_138, 3, 0)
node _count_T_140 = add(_count_T_40, _count_T_41)
node _count_T_141 = bits(_count_T_140, 1, 0)
node _count_T_142 = add(_count_T_42, _count_T_43)
node _count_T_143 = bits(_count_T_142, 1, 0)
node _count_T_144 = add(_count_T_141, _count_T_143)
node _count_T_145 = bits(_count_T_144, 2, 0)
node _count_T_146 = add(_count_T_44, _count_T_45)
node _count_T_147 = bits(_count_T_146, 1, 0)
node _count_T_148 = add(_count_T_46, _count_T_47)
node _count_T_149 = bits(_count_T_148, 1, 0)
node _count_T_150 = add(_count_T_147, _count_T_149)
node _count_T_151 = bits(_count_T_150, 2, 0)
node _count_T_152 = add(_count_T_145, _count_T_151)
node _count_T_153 = bits(_count_T_152, 3, 0)
node _count_T_154 = add(_count_T_139, _count_T_153)
node _count_T_155 = bits(_count_T_154, 4, 0)
node _count_T_156 = add(_count_T_48, _count_T_49)
node _count_T_157 = bits(_count_T_156, 1, 0)
node _count_T_158 = add(_count_T_50, _count_T_51)
node _count_T_159 = bits(_count_T_158, 1, 0)
node _count_T_160 = add(_count_T_157, _count_T_159)
node _count_T_161 = bits(_count_T_160, 2, 0)
node _count_T_162 = add(_count_T_52, _count_T_53)
node _count_T_163 = bits(_count_T_162, 1, 0)
node _count_T_164 = add(_count_T_54, _count_T_55)
node _count_T_165 = bits(_count_T_164, 1, 0)
node _count_T_166 = add(_count_T_163, _count_T_165)
node _count_T_167 = bits(_count_T_166, 2, 0)
node _count_T_168 = add(_count_T_161, _count_T_167)
node _count_T_169 = bits(_count_T_168, 3, 0)
node _count_T_170 = add(_count_T_56, _count_T_57)
node _count_T_171 = bits(_count_T_170, 1, 0)
node _count_T_172 = add(_count_T_58, _count_T_59)
node _count_T_173 = bits(_count_T_172, 1, 0)
node _count_T_174 = add(_count_T_171, _count_T_173)
node _count_T_175 = bits(_count_T_174, 2, 0)
node _count_T_176 = add(_count_T_60, _count_T_61)
node _count_T_177 = bits(_count_T_176, 1, 0)
node _count_T_178 = add(_count_T_62, _count_T_63)
node _count_T_179 = bits(_count_T_178, 1, 0)
node _count_T_180 = add(_count_T_177, _count_T_179)
node _count_T_181 = bits(_count_T_180, 2, 0)
node _count_T_182 = add(_count_T_175, _count_T_181)
node _count_T_183 = bits(_count_T_182, 3, 0)
node _count_T_184 = add(_count_T_169, _count_T_183)
node _count_T_185 = bits(_count_T_184, 4, 0)
node _count_T_186 = add(_count_T_155, _count_T_185)
node _count_T_187 = bits(_count_T_186, 5, 0)
node _count_T_188 = add(_count_T_125, _count_T_187)
node count = bits(_count_T_188, 6, 0)
wire in1_bytes : UInt<8>[8]
wire _in1_bytes_WIRE : UInt<64>
connect _in1_bytes_WIRE, io.in1
node _in1_bytes_T = bits(_in1_bytes_WIRE, 7, 0)
connect in1_bytes[0], _in1_bytes_T
node _in1_bytes_T_1 = bits(_in1_bytes_WIRE, 15, 8)
connect in1_bytes[1], _in1_bytes_T_1
node _in1_bytes_T_2 = bits(_in1_bytes_WIRE, 23, 16)
connect in1_bytes[2], _in1_bytes_T_2
node _in1_bytes_T_3 = bits(_in1_bytes_WIRE, 31, 24)
connect in1_bytes[3], _in1_bytes_T_3
node _in1_bytes_T_4 = bits(_in1_bytes_WIRE, 39, 32)
connect in1_bytes[4], _in1_bytes_T_4
node _in1_bytes_T_5 = bits(_in1_bytes_WIRE, 47, 40)
connect in1_bytes[5], _in1_bytes_T_5
node _in1_bytes_T_6 = bits(_in1_bytes_WIRE, 55, 48)
connect in1_bytes[6], _in1_bytes_T_6
node _in1_bytes_T_7 = bits(_in1_bytes_WIRE, 63, 56)
connect in1_bytes[7], _in1_bytes_T_7
node _orcb_T = neq(in1_bytes[0], UInt<1>(0h0))
node _orcb_T_1 = mux(_orcb_T, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_2 = neq(in1_bytes[1], UInt<1>(0h0))
node _orcb_T_3 = mux(_orcb_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_4 = neq(in1_bytes[2], UInt<1>(0h0))
node _orcb_T_5 = mux(_orcb_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_6 = neq(in1_bytes[3], UInt<1>(0h0))
node _orcb_T_7 = mux(_orcb_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_8 = neq(in1_bytes[4], UInt<1>(0h0))
node _orcb_T_9 = mux(_orcb_T_8, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_10 = neq(in1_bytes[5], UInt<1>(0h0))
node _orcb_T_11 = mux(_orcb_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_12 = neq(in1_bytes[6], UInt<1>(0h0))
node _orcb_T_13 = mux(_orcb_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _orcb_T_14 = neq(in1_bytes[7], UInt<1>(0h0))
node _orcb_T_15 = mux(_orcb_T_14, UInt<8>(0hff), UInt<8>(0h0))
wire _orcb_WIRE : UInt<8>[8]
connect _orcb_WIRE[0], _orcb_T_1
connect _orcb_WIRE[1], _orcb_T_3
connect _orcb_WIRE[2], _orcb_T_5
connect _orcb_WIRE[3], _orcb_T_7
connect _orcb_WIRE[4], _orcb_T_9
connect _orcb_WIRE[5], _orcb_T_11
connect _orcb_WIRE[6], _orcb_T_13
connect _orcb_WIRE[7], _orcb_T_15
node orcb_lo_lo = cat(_orcb_WIRE[1], _orcb_WIRE[0])
node orcb_lo_hi = cat(_orcb_WIRE[3], _orcb_WIRE[2])
node orcb_lo = cat(orcb_lo_hi, orcb_lo_lo)
node orcb_hi_lo = cat(_orcb_WIRE[5], _orcb_WIRE[4])
node orcb_hi_hi = cat(_orcb_WIRE[7], _orcb_WIRE[6])
node orcb_hi = cat(orcb_hi_hi, orcb_hi_lo)
node orcb = cat(orcb_hi, orcb_lo)
wire _rev8_WIRE : UInt<8>[8]
connect _rev8_WIRE[0], in1_bytes[7]
connect _rev8_WIRE[1], in1_bytes[6]
connect _rev8_WIRE[2], in1_bytes[5]
connect _rev8_WIRE[3], in1_bytes[4]
connect _rev8_WIRE[4], in1_bytes[3]
connect _rev8_WIRE[5], in1_bytes[2]
connect _rev8_WIRE[6], in1_bytes[1]
connect _rev8_WIRE[7], in1_bytes[0]
node rev8_lo_lo = cat(_rev8_WIRE[1], _rev8_WIRE[0])
node rev8_lo_hi = cat(_rev8_WIRE[3], _rev8_WIRE[2])
node rev8_lo = cat(rev8_lo_hi, rev8_lo_lo)
node rev8_hi_lo = cat(_rev8_WIRE[5], _rev8_WIRE[4])
node rev8_hi_hi = cat(_rev8_WIRE[7], _rev8_WIRE[6])
node rev8_hi = cat(rev8_hi_hi, rev8_hi_lo)
node rev8 = cat(rev8_hi, rev8_lo)
node _unary_T = bits(io.in2, 11, 0)
node _unary_T_1 = bits(io.in1, 15, 0)
node _unary_T_2 = bits(io.in1, 7, 7)
node _unary_T_3 = mux(_unary_T_2, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _unary_T_4 = bits(io.in1, 7, 0)
node _unary_T_5 = cat(_unary_T_3, _unary_T_4)
node _unary_T_6 = bits(io.in1, 15, 15)
node _unary_T_7 = mux(_unary_T_6, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _unary_T_8 = bits(io.in1, 15, 0)
node _unary_T_9 = cat(_unary_T_7, _unary_T_8)
node _unary_T_10 = eq(UInt<10>(0h287), _unary_T)
node _unary_T_11 = mux(_unary_T_10, orcb, count)
node _unary_T_12 = eq(UInt<11>(0h6b8), _unary_T)
node _unary_T_13 = mux(_unary_T_12, rev8, _unary_T_11)
node _unary_T_14 = eq(UInt<8>(0h80), _unary_T)
node _unary_T_15 = mux(_unary_T_14, _unary_T_1, _unary_T_13)
node _unary_T_16 = eq(UInt<11>(0h604), _unary_T)
node _unary_T_17 = mux(_unary_T_16, _unary_T_5, _unary_T_15)
node _unary_T_18 = eq(UInt<11>(0h605), _unary_T)
node unary = mux(_unary_T_18, _unary_T_9, _unary_T_17)
node maxmin_out = mux(io.cmp_out, io.in2, io.in1)
node _rot_shamt_T = eq(io.dw, UInt<1>(0h0))
node _rot_shamt_T_1 = mux(_rot_shamt_T, UInt<6>(0h20), UInt<7>(0h40))
node _rot_shamt_T_2 = sub(_rot_shamt_T_1, shamt)
node rot_shamt = tail(_rot_shamt_T_2, 1)
node _rotin_T = bits(io.fn, 0, 0)
node _rotin_T_1 = shl(UInt<32>(0hffffffff), 32)
node _rotin_T_2 = xor(UInt<64>(0hffffffffffffffff), _rotin_T_1)
node _rotin_T_3 = shr(shin_r, 32)
node _rotin_T_4 = and(_rotin_T_3, _rotin_T_2)
node _rotin_T_5 = bits(shin_r, 31, 0)
node _rotin_T_6 = shl(_rotin_T_5, 32)
node _rotin_T_7 = not(_rotin_T_2)
node _rotin_T_8 = and(_rotin_T_6, _rotin_T_7)
node _rotin_T_9 = or(_rotin_T_4, _rotin_T_8)
node _rotin_T_10 = bits(_rotin_T_2, 47, 0)
node _rotin_T_11 = shl(_rotin_T_10, 16)
node _rotin_T_12 = xor(_rotin_T_2, _rotin_T_11)
node _rotin_T_13 = shr(_rotin_T_9, 16)
node _rotin_T_14 = and(_rotin_T_13, _rotin_T_12)
node _rotin_T_15 = bits(_rotin_T_9, 47, 0)
node _rotin_T_16 = shl(_rotin_T_15, 16)
node _rotin_T_17 = not(_rotin_T_12)
node _rotin_T_18 = and(_rotin_T_16, _rotin_T_17)
node _rotin_T_19 = or(_rotin_T_14, _rotin_T_18)
node _rotin_T_20 = bits(_rotin_T_12, 55, 0)
node _rotin_T_21 = shl(_rotin_T_20, 8)
node _rotin_T_22 = xor(_rotin_T_12, _rotin_T_21)
node _rotin_T_23 = shr(_rotin_T_19, 8)
node _rotin_T_24 = and(_rotin_T_23, _rotin_T_22)
node _rotin_T_25 = bits(_rotin_T_19, 55, 0)
node _rotin_T_26 = shl(_rotin_T_25, 8)
node _rotin_T_27 = not(_rotin_T_22)
node _rotin_T_28 = and(_rotin_T_26, _rotin_T_27)
node _rotin_T_29 = or(_rotin_T_24, _rotin_T_28)
node _rotin_T_30 = bits(_rotin_T_22, 59, 0)
node _rotin_T_31 = shl(_rotin_T_30, 4)
node _rotin_T_32 = xor(_rotin_T_22, _rotin_T_31)
node _rotin_T_33 = shr(_rotin_T_29, 4)
node _rotin_T_34 = and(_rotin_T_33, _rotin_T_32)
node _rotin_T_35 = bits(_rotin_T_29, 59, 0)
node _rotin_T_36 = shl(_rotin_T_35, 4)
node _rotin_T_37 = not(_rotin_T_32)
node _rotin_T_38 = and(_rotin_T_36, _rotin_T_37)
node _rotin_T_39 = or(_rotin_T_34, _rotin_T_38)
node _rotin_T_40 = bits(_rotin_T_32, 61, 0)
node _rotin_T_41 = shl(_rotin_T_40, 2)
node _rotin_T_42 = xor(_rotin_T_32, _rotin_T_41)
node _rotin_T_43 = shr(_rotin_T_39, 2)
node _rotin_T_44 = and(_rotin_T_43, _rotin_T_42)
node _rotin_T_45 = bits(_rotin_T_39, 61, 0)
node _rotin_T_46 = shl(_rotin_T_45, 2)
node _rotin_T_47 = not(_rotin_T_42)
node _rotin_T_48 = and(_rotin_T_46, _rotin_T_47)
node _rotin_T_49 = or(_rotin_T_44, _rotin_T_48)
node _rotin_T_50 = bits(_rotin_T_42, 62, 0)
node _rotin_T_51 = shl(_rotin_T_50, 1)
node _rotin_T_52 = xor(_rotin_T_42, _rotin_T_51)
node _rotin_T_53 = shr(_rotin_T_49, 1)
node _rotin_T_54 = and(_rotin_T_53, _rotin_T_52)
node _rotin_T_55 = bits(_rotin_T_49, 62, 0)
node _rotin_T_56 = shl(_rotin_T_55, 1)
node _rotin_T_57 = not(_rotin_T_52)
node _rotin_T_58 = and(_rotin_T_56, _rotin_T_57)
node _rotin_T_59 = or(_rotin_T_54, _rotin_T_58)
node rotin = mux(_rotin_T, shin_r, _rotin_T_59)
node _rotout_r_T = dshr(rotin, rot_shamt)
node rotout_r = bits(_rotout_r_T, 63, 0)
node _rotout_l_T = shl(UInt<32>(0hffffffff), 32)
node _rotout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _rotout_l_T)
node _rotout_l_T_2 = shr(rotout_r, 32)
node _rotout_l_T_3 = and(_rotout_l_T_2, _rotout_l_T_1)
node _rotout_l_T_4 = bits(rotout_r, 31, 0)
node _rotout_l_T_5 = shl(_rotout_l_T_4, 32)
node _rotout_l_T_6 = not(_rotout_l_T_1)
node _rotout_l_T_7 = and(_rotout_l_T_5, _rotout_l_T_6)
node _rotout_l_T_8 = or(_rotout_l_T_3, _rotout_l_T_7)
node _rotout_l_T_9 = bits(_rotout_l_T_1, 47, 0)
node _rotout_l_T_10 = shl(_rotout_l_T_9, 16)
node _rotout_l_T_11 = xor(_rotout_l_T_1, _rotout_l_T_10)
node _rotout_l_T_12 = shr(_rotout_l_T_8, 16)
node _rotout_l_T_13 = and(_rotout_l_T_12, _rotout_l_T_11)
node _rotout_l_T_14 = bits(_rotout_l_T_8, 47, 0)
node _rotout_l_T_15 = shl(_rotout_l_T_14, 16)
node _rotout_l_T_16 = not(_rotout_l_T_11)
node _rotout_l_T_17 = and(_rotout_l_T_15, _rotout_l_T_16)
node _rotout_l_T_18 = or(_rotout_l_T_13, _rotout_l_T_17)
node _rotout_l_T_19 = bits(_rotout_l_T_11, 55, 0)
node _rotout_l_T_20 = shl(_rotout_l_T_19, 8)
node _rotout_l_T_21 = xor(_rotout_l_T_11, _rotout_l_T_20)
node _rotout_l_T_22 = shr(_rotout_l_T_18, 8)
node _rotout_l_T_23 = and(_rotout_l_T_22, _rotout_l_T_21)
node _rotout_l_T_24 = bits(_rotout_l_T_18, 55, 0)
node _rotout_l_T_25 = shl(_rotout_l_T_24, 8)
node _rotout_l_T_26 = not(_rotout_l_T_21)
node _rotout_l_T_27 = and(_rotout_l_T_25, _rotout_l_T_26)
node _rotout_l_T_28 = or(_rotout_l_T_23, _rotout_l_T_27)
node _rotout_l_T_29 = bits(_rotout_l_T_21, 59, 0)
node _rotout_l_T_30 = shl(_rotout_l_T_29, 4)
node _rotout_l_T_31 = xor(_rotout_l_T_21, _rotout_l_T_30)
node _rotout_l_T_32 = shr(_rotout_l_T_28, 4)
node _rotout_l_T_33 = and(_rotout_l_T_32, _rotout_l_T_31)
node _rotout_l_T_34 = bits(_rotout_l_T_28, 59, 0)
node _rotout_l_T_35 = shl(_rotout_l_T_34, 4)
node _rotout_l_T_36 = not(_rotout_l_T_31)
node _rotout_l_T_37 = and(_rotout_l_T_35, _rotout_l_T_36)
node _rotout_l_T_38 = or(_rotout_l_T_33, _rotout_l_T_37)
node _rotout_l_T_39 = bits(_rotout_l_T_31, 61, 0)
node _rotout_l_T_40 = shl(_rotout_l_T_39, 2)
node _rotout_l_T_41 = xor(_rotout_l_T_31, _rotout_l_T_40)
node _rotout_l_T_42 = shr(_rotout_l_T_38, 2)
node _rotout_l_T_43 = and(_rotout_l_T_42, _rotout_l_T_41)
node _rotout_l_T_44 = bits(_rotout_l_T_38, 61, 0)
node _rotout_l_T_45 = shl(_rotout_l_T_44, 2)
node _rotout_l_T_46 = not(_rotout_l_T_41)
node _rotout_l_T_47 = and(_rotout_l_T_45, _rotout_l_T_46)
node _rotout_l_T_48 = or(_rotout_l_T_43, _rotout_l_T_47)
node _rotout_l_T_49 = bits(_rotout_l_T_41, 62, 0)
node _rotout_l_T_50 = shl(_rotout_l_T_49, 1)
node _rotout_l_T_51 = xor(_rotout_l_T_41, _rotout_l_T_50)
node _rotout_l_T_52 = shr(_rotout_l_T_48, 1)
node _rotout_l_T_53 = and(_rotout_l_T_52, _rotout_l_T_51)
node _rotout_l_T_54 = bits(_rotout_l_T_48, 62, 0)
node _rotout_l_T_55 = shl(_rotout_l_T_54, 1)
node _rotout_l_T_56 = not(_rotout_l_T_51)
node _rotout_l_T_57 = and(_rotout_l_T_55, _rotout_l_T_56)
node rotout_l = or(_rotout_l_T_53, _rotout_l_T_57)
node _rotout_T = bits(io.fn, 0, 0)
node _rotout_T_1 = mux(_rotout_T, rotout_r, rotout_l)
node _rotout_T_2 = bits(io.fn, 0, 0)
node _rotout_T_3 = mux(_rotout_T_2, shout_l, shout_r)
node rotout = or(_rotout_T_1, _rotout_T_3)
node _out_T = eq(UInt<1>(0h0), io.fn)
node _out_T_1 = mux(_out_T, io.adder_out, shift_logic)
node _out_T_2 = eq(UInt<4>(0ha), io.fn)
node _out_T_3 = mux(_out_T_2, io.adder_out, _out_T_1)
node _out_T_4 = eq(UInt<5>(0h10), io.fn)
node _out_T_5 = mux(_out_T_4, unary, _out_T_3)
node _out_T_6 = eq(UInt<5>(0h1c), io.fn)
node _out_T_7 = mux(_out_T_6, maxmin_out, _out_T_5)
node _out_T_8 = eq(UInt<5>(0h1d), io.fn)
node _out_T_9 = mux(_out_T_8, maxmin_out, _out_T_7)
node _out_T_10 = eq(UInt<5>(0h1e), io.fn)
node _out_T_11 = mux(_out_T_10, maxmin_out, _out_T_9)
node _out_T_12 = eq(UInt<5>(0h1f), io.fn)
node _out_T_13 = mux(_out_T_12, maxmin_out, _out_T_11)
node _out_T_14 = eq(UInt<5>(0h11), io.fn)
node _out_T_15 = mux(_out_T_14, rotout, _out_T_13)
node _out_T_16 = eq(UInt<5>(0h12), io.fn)
node out = mux(_out_T_16, rotout, _out_T_15)
connect io.out, out
node _T_1 = eq(io.dw, UInt<1>(0h0))
when _T_1 :
node _io_out_T = bits(out, 31, 31)
node _io_out_T_1 = mux(_io_out_T, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_out_T_2 = bits(out, 31, 0)
node _io_out_T_3 = cat(_io_out_T_1, _io_out_T_2)
connect io.out, _io_out_T_3 | module ALU_2( // @[ALU.scala:83:7]
input clock, // @[ALU.scala:83:7]
input reset, // @[ALU.scala:83:7]
input io_dw, // @[ALU.scala:72:14]
input [4:0] io_fn, // @[ALU.scala:72:14]
input [63:0] io_in2, // @[ALU.scala:72:14]
input [63:0] io_in1, // @[ALU.scala:72:14]
output [63:0] io_out, // @[ALU.scala:72:14]
output [63:0] io_adder_out, // @[ALU.scala:72:14]
output io_cmp_out // @[ALU.scala:72:14]
);
wire [7:0] in1_bytes_6; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_5; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_4; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_3; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_2; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_1; // @[ALU.scala:140:34]
wire [7:0] in1_bytes_0; // @[ALU.scala:140:34]
wire io_dw_0 = io_dw; // @[ALU.scala:83:7]
wire [4:0] io_fn_0 = io_fn; // @[ALU.scala:83:7]
wire [63:0] io_in2_0 = io_in2; // @[ALU.scala:83:7]
wire [63:0] io_in1_0 = io_in1; // @[ALU.scala:83:7]
wire [63:0] _bext_mask_T_2 = 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:70]
wire [31:0] _tz_in_T_67 = 32'hFFFF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_66 = 32'hFFFF0000; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_72 = 32'hFFFF0000; // @[ALU.scala:134:26]
wire [23:0] _tz_in_T_75 = 24'hFFFF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_76 = 32'hFFFF00; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_77 = 32'hFF00FF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_82 = 32'hFF00FF00; // @[ALU.scala:134:26]
wire [27:0] _tz_in_T_85 = 28'hFF00FF; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_86 = 32'hFF00FF0; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_87 = 32'hF0F0F0F; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_92 = 32'hF0F0F0F0; // @[ALU.scala:134:26]
wire [29:0] _tz_in_T_95 = 30'hF0F0F0F; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_96 = 32'h3C3C3C3C; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_97 = 32'h33333333; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_102 = 32'hCCCCCCCC; // @[ALU.scala:134:26]
wire [30:0] _tz_in_T_105 = 31'h33333333; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_106 = 32'h66666666; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_107 = 32'h55555555; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_112 = 32'hAAAAAAAA; // @[ALU.scala:134:26]
wire [63:0] _shin_T_9 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_5 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_2 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_8 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46]
wire [63:0] _shin_T_14 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46]
wire [63:0] _shout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24]
wire [63:0] _tz_in_T_4 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_10 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19]
wire [63:0] _rotin_T_1 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_7 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44]
wire [63:0] _rotout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25]
wire [47:0] _shin_T_17 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _shout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _tz_in_T_13 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotin_T_10 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_18 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_14 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_11 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_19 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_15 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_12 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_24 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_20 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_17 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shin_T_27 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _tz_in_T_23 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotin_T_20 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_28 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_24 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_21 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_29 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_25 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_22 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_34 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_30 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_27 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shin_T_37 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _tz_in_T_33 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotin_T_30 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_38 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_34 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_31 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_39 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_35 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_32 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_44 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_40 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_37 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _shin_T_47 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _shout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _tz_in_T_43 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _rotin_T_40 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [61:0] _rotout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_48 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_44 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_41 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_49 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_45 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_42 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_54 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_50 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_47 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shin_T_57 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _tz_in_T_53 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotin_T_50 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_58 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_54 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_51 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_59 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_55 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_52 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_64 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_60 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_57 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire _shin_hi_T = io_dw_0; // @[ALU.scala:83:7, :102:31]
wire _shamt_T_1 = io_dw_0; // @[ALU.scala:83:7, :103:42]
wire [63:0] _in1_bytes_WIRE = io_in1_0; // @[ALU.scala:83:7, :140:34]
wire [63:0] _io_adder_out_T_4; // @[ALU.scala:88:36]
wire _io_cmp_out_T_5; // @[ALU.scala:94:36]
wire [63:0] io_out_0; // @[ALU.scala:83:7]
wire [63:0] io_adder_out_0; // @[ALU.scala:83:7]
wire io_cmp_out_0; // @[ALU.scala:83:7]
wire _in2_inv_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire _io_adder_out_T_2 = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire _io_cmp_out_T_1 = io_fn_0[3]; // @[ALU.scala:58:29, :63:30, :83:7]
wire _shin_hi_32_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire _shout_r_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7]
wire [63:0] _in2_inv_T_1 = ~io_in2_0; // @[ALU.scala:83:7, :85:35]
wire [63:0] in2_inv = _in2_inv_T ? _in2_inv_T_1 : io_in2_0; // @[ALU.scala:58:29, :83:7, :85:{20,35}]
wire [63:0] in1_xor_in2 = io_in1_0 ^ in2_inv; // @[ALU.scala:83:7, :85:20, :86:28]
wire [63:0] in1_and_in2 = io_in1_0 & in2_inv; // @[ALU.scala:83:7, :85:20, :87:28]
wire [64:0] _io_adder_out_T = {1'h0, io_in1_0} + {1'h0, in2_inv}; // @[ALU.scala:83:7, :85:20, :88:26]
wire [63:0] _io_adder_out_T_1 = _io_adder_out_T[63:0]; // @[ALU.scala:88:26]
wire [64:0] _io_adder_out_T_3 = {1'h0, _io_adder_out_T_1} + {64'h0, _io_adder_out_T_2}; // @[ALU.scala:58:29, :88:{26,36}]
assign _io_adder_out_T_4 = _io_adder_out_T_3[63:0]; // @[ALU.scala:88:36]
assign io_adder_out_0 = _io_adder_out_T_4; // @[ALU.scala:83:7, :88:36]
wire _slt_T = io_in1_0[63]; // @[ALU.scala:83:7, :92:15]
wire _slt_T_6 = io_in1_0[63]; // @[ALU.scala:83:7, :92:15, :93:51]
wire _slt_T_1 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34]
wire _slt_T_5 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34, :93:35]
wire _slt_T_2 = _slt_T == _slt_T_1; // @[ALU.scala:92:{15,24,34}]
wire _slt_T_3 = io_adder_out_0[63]; // @[ALU.scala:83:7, :92:56]
wire _slt_T_4 = io_fn_0[1]; // @[ALU.scala:61:35, :83:7]
wire _slt_T_7 = _slt_T_4 ? _slt_T_5 : _slt_T_6; // @[ALU.scala:61:35, :93:{8,35,51}]
wire slt = _slt_T_2 ? _slt_T_3 : _slt_T_7; // @[ALU.scala:92:{8,24,56}, :93:8]
wire _io_cmp_out_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7]
wire _rotin_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :156:24]
wire _rotout_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:25]
wire _rotout_T_2 = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:61]
wire _io_cmp_out_T_2 = ~_io_cmp_out_T_1; // @[ALU.scala:63:{26,30}]
wire _io_cmp_out_T_3 = in1_xor_in2 == 64'h0; // @[ALU.scala:86:28, :94:68]
wire _io_cmp_out_T_4 = _io_cmp_out_T_2 ? _io_cmp_out_T_3 : slt; // @[ALU.scala:63:26, :92:8, :94:{41,68}]
assign _io_cmp_out_T_5 = _io_cmp_out_T ^ _io_cmp_out_T_4; // @[ALU.scala:62:35, :94:{36,41}]
assign io_cmp_out_0 = _io_cmp_out_T_5; // @[ALU.scala:83:7, :94:36]
wire _shin_hi_32_T_1 = io_in1_0[31]; // @[ALU.scala:83:7, :101:55]
wire _shin_hi_32_T_2 = _shin_hi_32_T & _shin_hi_32_T_1; // @[ALU.scala:58:29, :101:{46,55}]
wire [31:0] shin_hi_32 = {32{_shin_hi_32_T_2}}; // @[ALU.scala:101:{28,46}]
wire [31:0] _shin_hi_T_1 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48]
wire [31:0] _tz_in_T_6 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48, :132:19]
wire [31:0] shin_hi = _shin_hi_T ? _shin_hi_T_1 : shin_hi_32; // @[ALU.scala:101:28, :102:{24,31,48}]
wire _shamt_T = io_in2_0[5]; // @[ALU.scala:83:7, :103:29]
wire _shamt_T_2 = _shamt_T & _shamt_T_1; // @[ALU.scala:103:{29,33,42}]
wire [4:0] _shamt_T_3 = io_in2_0[4:0]; // @[ALU.scala:83:7, :103:60]
wire [5:0] shamt = {_shamt_T_2, _shamt_T_3}; // @[ALU.scala:103:{22,33,60}]
wire [31:0] _tz_in_T_8 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :132:19]
wire [31:0] _tz_in_T_63 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :133:25]
wire [31:0] _tz_in_T_65 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :134:33]
wire [31:0] _popc_in_T_2 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :137:32]
wire [63:0] shin_r = {shin_hi, io_in1_0[31:0]}; // @[ALU.scala:83:7, :102:24, :104:{18,34}]
wire _GEN = io_fn_0 == 5'h5; // @[package.scala:16:47]
wire _shin_T; // @[package.scala:16:47]
assign _shin_T = _GEN; // @[package.scala:16:47]
wire _shout_T; // @[ALU.scala:109:25]
assign _shout_T = _GEN; // @[package.scala:16:47]
wire _GEN_0 = io_fn_0 == 5'hB; // @[package.scala:16:47]
wire _shin_T_1; // @[package.scala:16:47]
assign _shin_T_1 = _GEN_0; // @[package.scala:16:47]
wire _shout_T_1; // @[ALU.scala:109:44]
assign _shout_T_1 = _GEN_0; // @[package.scala:16:47]
wire _GEN_1 = io_fn_0 == 5'h12; // @[package.scala:16:47]
wire _shin_T_2; // @[package.scala:16:47]
assign _shin_T_2 = _GEN_1; // @[package.scala:16:47]
wire _out_T_16; // @[ALU.scala:161:47]
assign _out_T_16 = _GEN_1; // @[package.scala:16:47]
wire _GEN_2 = io_fn_0 == 5'h13; // @[package.scala:16:47]
wire _shin_T_3; // @[package.scala:16:47]
assign _shin_T_3 = _GEN_2; // @[package.scala:16:47]
wire _shout_T_3; // @[ALU.scala:109:64]
assign _shout_T_3 = _GEN_2; // @[package.scala:16:47]
wire _bext_mask_T; // @[ALU.scala:122:52]
assign _bext_mask_T = _GEN_2; // @[package.scala:16:47]
wire _shin_T_4 = _shin_T | _shin_T_1; // @[package.scala:16:47, :81:59]
wire _shin_T_5 = _shin_T_4 | _shin_T_2; // @[package.scala:16:47, :81:59]
wire _shin_T_6 = _shin_T_5 | _shin_T_3; // @[package.scala:16:47, :81:59]
wire _shin_T_7 = ~_shin_T_6; // @[package.scala:81:59]
wire [31:0] _shin_T_10 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46]
wire [31:0] _rotin_T_3 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46, :156:44]
wire [63:0] _shin_T_11 = {32'h0, _shin_T_10}; // @[ALU.scala:106:46]
wire [31:0] _shin_T_12 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46]
wire [31:0] _rotin_T_5 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46, :156:44]
wire [63:0] _shin_T_13 = {_shin_T_12, 32'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_15 = _shin_T_13 & 64'hFFFFFFFF00000000; // @[ALU.scala:106:46]
wire [63:0] _shin_T_16 = _shin_T_11 | _shin_T_15; // @[ALU.scala:106:46]
wire [47:0] _shin_T_20 = _shin_T_16[63:16]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_21 = {16'h0, _shin_T_20 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _shin_T_22 = _shin_T_16[47:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_23 = {_shin_T_22, 16'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_25 = _shin_T_23 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_26 = _shin_T_21 | _shin_T_25; // @[ALU.scala:106:46]
wire [55:0] _shin_T_30 = _shin_T_26[63:8]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_31 = {8'h0, _shin_T_30 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shin_T_32 = _shin_T_26[55:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_33 = {_shin_T_32, 8'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_35 = _shin_T_33 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_36 = _shin_T_31 | _shin_T_35; // @[ALU.scala:106:46]
wire [59:0] _shin_T_40 = _shin_T_36[63:4]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_41 = {4'h0, _shin_T_40 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shin_T_42 = _shin_T_36[59:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_43 = {_shin_T_42, 4'h0}; // @[ALU.scala:106:46]
wire [63:0] _shin_T_45 = _shin_T_43 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_46 = _shin_T_41 | _shin_T_45; // @[ALU.scala:106:46]
wire [61:0] _shin_T_50 = _shin_T_46[63:2]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_51 = {2'h0, _shin_T_50 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _shin_T_52 = _shin_T_46[61:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_53 = {_shin_T_52, 2'h0}; // @[package.scala:16:47]
wire [63:0] _shin_T_55 = _shin_T_53 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_56 = _shin_T_51 | _shin_T_55; // @[ALU.scala:106:46]
wire [62:0] _shin_T_60 = _shin_T_56[63:1]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_61 = {1'h0, _shin_T_60 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shin_T_62 = _shin_T_56[62:0]; // @[ALU.scala:106:46]
wire [63:0] _shin_T_63 = {_shin_T_62, 1'h0}; // @[ALU.scala:88:26, :106:46]
wire [63:0] _shin_T_65 = _shin_T_63 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shin_T_66 = _shin_T_61 | _shin_T_65; // @[ALU.scala:106:46]
wire [63:0] shin = _shin_T_7 ? _shin_T_66 : shin_r; // @[ALU.scala:64:33, :104:18, :106:{17,46}]
wire _shout_r_T_1 = shin[63]; // @[ALU.scala:106:17, :107:41]
wire _shout_r_T_2 = _shout_r_T & _shout_r_T_1; // @[ALU.scala:58:29, :107:{35,41}]
wire [64:0] _shout_r_T_3 = {_shout_r_T_2, shin}; // @[ALU.scala:106:17, :107:{21,35}]
wire [64:0] _shout_r_T_4 = _shout_r_T_3; // @[ALU.scala:107:{21,57}]
wire [64:0] _shout_r_T_5 = $signed($signed(_shout_r_T_4) >>> shamt); // @[ALU.scala:103:22, :107:{57,64}]
wire [63:0] shout_r = _shout_r_T_5[63:0]; // @[ALU.scala:107:{64,73}]
wire [31:0] _shout_l_T_2 = shout_r[63:32]; // @[ALU.scala:107:73, :108:24]
wire [63:0] _shout_l_T_3 = {32'h0, _shout_l_T_2}; // @[ALU.scala:108:24]
wire [31:0] _shout_l_T_4 = shout_r[31:0]; // @[ALU.scala:107:73, :108:24]
wire [63:0] _shout_l_T_5 = {_shout_l_T_4, 32'h0}; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_7 = _shout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_8 = _shout_l_T_3 | _shout_l_T_7; // @[ALU.scala:108:24]
wire [47:0] _shout_l_T_12 = _shout_l_T_8[63:16]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_13 = {16'h0, _shout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _shout_l_T_14 = _shout_l_T_8[47:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_15 = {_shout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :108:24]
wire [63:0] _shout_l_T_17 = _shout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_18 = _shout_l_T_13 | _shout_l_T_17; // @[ALU.scala:108:24]
wire [55:0] _shout_l_T_22 = _shout_l_T_18[63:8]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_23 = {8'h0, _shout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _shout_l_T_24 = _shout_l_T_18[55:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_25 = {_shout_l_T_24, 8'h0}; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_27 = _shout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_28 = _shout_l_T_23 | _shout_l_T_27; // @[ALU.scala:108:24]
wire [59:0] _shout_l_T_32 = _shout_l_T_28[63:4]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_33 = {4'h0, _shout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _shout_l_T_34 = _shout_l_T_28[59:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_35 = {_shout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :108:24]
wire [63:0] _shout_l_T_37 = _shout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_38 = _shout_l_T_33 | _shout_l_T_37; // @[ALU.scala:108:24]
wire [61:0] _shout_l_T_42 = _shout_l_T_38[63:2]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_43 = {2'h0, _shout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _shout_l_T_44 = _shout_l_T_38[61:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_45 = {_shout_l_T_44, 2'h0}; // @[package.scala:16:47]
wire [63:0] _shout_l_T_47 = _shout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _shout_l_T_48 = _shout_l_T_43 | _shout_l_T_47; // @[ALU.scala:108:24]
wire [62:0] _shout_l_T_52 = _shout_l_T_48[63:1]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_53 = {1'h0, _shout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _shout_l_T_54 = _shout_l_T_48[62:0]; // @[ALU.scala:108:24]
wire [63:0] _shout_l_T_55 = {_shout_l_T_54, 1'h0}; // @[ALU.scala:88:26, :108:24]
wire [63:0] _shout_l_T_57 = _shout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] shout_l = _shout_l_T_53 | _shout_l_T_57; // @[ALU.scala:108:24]
wire _shout_T_2 = _shout_T | _shout_T_1; // @[ALU.scala:109:{25,35,44}]
wire _shout_T_4 = _shout_T_2 | _shout_T_3; // @[ALU.scala:109:{35,55,64}]
wire [63:0] _shout_T_5 = _shout_T_4 ? shout_r : 64'h0; // @[ALU.scala:107:73, :109:{18,55}]
wire _shout_T_6 = io_fn_0 == 5'h1; // @[ALU.scala:83:7, :110:25]
wire [63:0] _shout_T_7 = _shout_T_6 ? shout_l : 64'h0; // @[ALU.scala:108:24, :110:{18,25}]
wire [63:0] shout = _shout_T_5 | _shout_T_7; // @[ALU.scala:109:{18,91}, :110:18]
wire in2_not_zero = |io_in2_0; // @[ALU.scala:83:7, :113:29]
wire _logic_T = io_fn_0 == 5'h4; // @[ALU.scala:83:7, :119:25]
wire _GEN_3 = io_fn_0 == 5'h6; // @[ALU.scala:83:7, :119:45]
wire _logic_T_1; // @[ALU.scala:119:45]
assign _logic_T_1 = _GEN_3; // @[ALU.scala:119:45]
wire _logic_T_8; // @[ALU.scala:120:25]
assign _logic_T_8 = _GEN_3; // @[ALU.scala:119:45, :120:25]
wire _logic_T_2 = _logic_T | _logic_T_1; // @[ALU.scala:119:{25,36,45}]
wire _GEN_4 = io_fn_0 == 5'h19; // @[ALU.scala:83:7, :119:64]
wire _logic_T_3; // @[ALU.scala:119:64]
assign _logic_T_3 = _GEN_4; // @[ALU.scala:119:64]
wire _logic_T_11; // @[ALU.scala:120:64]
assign _logic_T_11 = _GEN_4; // @[ALU.scala:119:64, :120:64]
wire _logic_T_4 = _logic_T_2 | _logic_T_3; // @[ALU.scala:119:{36,55,64}]
wire _logic_T_5 = io_fn_0 == 5'h1A; // @[ALU.scala:83:7, :119:84]
wire _logic_T_6 = _logic_T_4 | _logic_T_5; // @[ALU.scala:119:{55,75,84}]
wire [63:0] _logic_T_7 = _logic_T_6 ? in1_xor_in2 : 64'h0; // @[ALU.scala:86:28, :119:{18,75}]
wire _logic_T_9 = io_fn_0 == 5'h7; // @[ALU.scala:83:7, :120:44]
wire _logic_T_10 = _logic_T_8 | _logic_T_9; // @[ALU.scala:120:{25,35,44}]
wire _logic_T_12 = _logic_T_10 | _logic_T_11; // @[ALU.scala:120:{35,55,64}]
wire _logic_T_13 = io_fn_0 == 5'h18; // @[ALU.scala:83:7, :120:84]
wire _logic_T_14 = _logic_T_12 | _logic_T_13; // @[ALU.scala:120:{55,75,84}]
wire [63:0] _logic_T_15 = _logic_T_14 ? in1_and_in2 : 64'h0; // @[ALU.scala:87:28, :120:{18,75}]
wire [63:0] logic_0 = _logic_T_7 | _logic_T_15; // @[ALU.scala:119:{18,115}, :120:18]
wire _bext_mask_T_1 = _bext_mask_T; // @[ALU.scala:122:{43,52}]
wire [63:0] bext_mask = _bext_mask_T_1 ? 64'h1 : 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:{22,43}]
wire _shift_logic_T = io_fn_0 > 5'hB; // @[ALU.scala:59:31, :83:7]
wire _shift_logic_T_1 = ~(io_fn_0[4]); // @[ALU.scala:59:48, :83:7]
wire _shift_logic_T_2 = _shift_logic_T & _shift_logic_T_1; // @[ALU.scala:59:{31,41,48}]
wire _shift_logic_T_3 = _shift_logic_T_2 & slt; // @[ALU.scala:59:41, :92:8, :123:36]
wire [63:0] _shift_logic_T_4 = {63'h0, _shift_logic_T_3} | logic_0; // @[ALU.scala:119:115, :123:{36,44}]
wire [63:0] _shift_logic_T_5 = shout & bext_mask; // @[ALU.scala:109:91, :122:22, :123:61]
wire [63:0] shift_logic = _shift_logic_T_4 | _shift_logic_T_5; // @[ALU.scala:123:{44,52,61}]
wire _tz_in_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32]
wire _tz_in_T_1 = io_in2_0[0]; // @[ALU.scala:83:7, :130:53]
wire _tz_in_T_2 = ~_tz_in_T_1; // @[ALU.scala:130:{46,53}]
wire [1:0] _tz_in_T_3 = {_tz_in_T, _tz_in_T_2}; // @[ALU.scala:130:{32,43,46}]
wire [63:0] _tz_in_T_7 = {32'h0, _tz_in_T_6}; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_9 = {_tz_in_T_8, 32'h0}; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_11 = _tz_in_T_9 & 64'hFFFFFFFF00000000; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_12 = _tz_in_T_7 | _tz_in_T_11; // @[ALU.scala:132:19]
wire [47:0] _tz_in_T_16 = _tz_in_T_12[63:16]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_17 = {16'h0, _tz_in_T_16 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _tz_in_T_18 = _tz_in_T_12[47:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_19 = {_tz_in_T_18, 16'h0}; // @[ALU.scala:106:46, :132:19]
wire [63:0] _tz_in_T_21 = _tz_in_T_19 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_22 = _tz_in_T_17 | _tz_in_T_21; // @[ALU.scala:132:19]
wire [55:0] _tz_in_T_26 = _tz_in_T_22[63:8]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_27 = {8'h0, _tz_in_T_26 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _tz_in_T_28 = _tz_in_T_22[55:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_29 = {_tz_in_T_28, 8'h0}; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_31 = _tz_in_T_29 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_32 = _tz_in_T_27 | _tz_in_T_31; // @[ALU.scala:132:19]
wire [59:0] _tz_in_T_36 = _tz_in_T_32[63:4]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_37 = {4'h0, _tz_in_T_36 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _tz_in_T_38 = _tz_in_T_32[59:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_39 = {_tz_in_T_38, 4'h0}; // @[ALU.scala:106:46, :132:19]
wire [63:0] _tz_in_T_41 = _tz_in_T_39 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_42 = _tz_in_T_37 | _tz_in_T_41; // @[ALU.scala:132:19]
wire [61:0] _tz_in_T_46 = _tz_in_T_42[63:2]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_47 = {2'h0, _tz_in_T_46 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _tz_in_T_48 = _tz_in_T_42[61:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_49 = {_tz_in_T_48, 2'h0}; // @[package.scala:16:47]
wire [63:0] _tz_in_T_51 = _tz_in_T_49 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_52 = _tz_in_T_47 | _tz_in_T_51; // @[ALU.scala:132:19]
wire [62:0] _tz_in_T_56 = _tz_in_T_52[63:1]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_57 = {1'h0, _tz_in_T_56 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _tz_in_T_58 = _tz_in_T_52[62:0]; // @[ALU.scala:132:19]
wire [63:0] _tz_in_T_59 = {_tz_in_T_58, 1'h0}; // @[ALU.scala:88:26, :132:19]
wire [63:0] _tz_in_T_61 = _tz_in_T_59 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _tz_in_T_62 = _tz_in_T_57 | _tz_in_T_61; // @[ALU.scala:132:19]
wire [32:0] _tz_in_T_64 = {1'h1, _tz_in_T_63}; // @[ALU.scala:133:{16,25}]
wire [15:0] _tz_in_T_68 = _tz_in_T_65[31:16]; // @[ALU.scala:134:{26,33}]
wire [31:0] _tz_in_T_69 = {16'h0, _tz_in_T_68}; // @[ALU.scala:106:46, :134:26]
wire [15:0] _tz_in_T_70 = _tz_in_T_65[15:0]; // @[ALU.scala:134:{26,33}]
wire [31:0] _tz_in_T_71 = {_tz_in_T_70, 16'h0}; // @[ALU.scala:106:46, :134:26]
wire [31:0] _tz_in_T_73 = _tz_in_T_71 & 32'hFFFF0000; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_74 = _tz_in_T_69 | _tz_in_T_73; // @[ALU.scala:134:26]
wire [23:0] _tz_in_T_78 = _tz_in_T_74[31:8]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_79 = {8'h0, _tz_in_T_78 & 24'hFF00FF}; // @[ALU.scala:134:26]
wire [23:0] _tz_in_T_80 = _tz_in_T_74[23:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_81 = {_tz_in_T_80, 8'h0}; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_83 = _tz_in_T_81 & 32'hFF00FF00; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_84 = _tz_in_T_79 | _tz_in_T_83; // @[ALU.scala:134:26]
wire [27:0] _tz_in_T_88 = _tz_in_T_84[31:4]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_89 = {4'h0, _tz_in_T_88 & 28'hF0F0F0F}; // @[ALU.scala:106:46, :134:26]
wire [27:0] _tz_in_T_90 = _tz_in_T_84[27:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_91 = {_tz_in_T_90, 4'h0}; // @[ALU.scala:106:46, :134:26]
wire [31:0] _tz_in_T_93 = _tz_in_T_91 & 32'hF0F0F0F0; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_94 = _tz_in_T_89 | _tz_in_T_93; // @[ALU.scala:134:26]
wire [29:0] _tz_in_T_98 = _tz_in_T_94[31:2]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_99 = {2'h0, _tz_in_T_98 & 30'h33333333}; // @[package.scala:16:47]
wire [29:0] _tz_in_T_100 = _tz_in_T_94[29:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_101 = {_tz_in_T_100, 2'h0}; // @[package.scala:16:47]
wire [31:0] _tz_in_T_103 = _tz_in_T_101 & 32'hCCCCCCCC; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_104 = _tz_in_T_99 | _tz_in_T_103; // @[ALU.scala:134:26]
wire [30:0] _tz_in_T_108 = _tz_in_T_104[31:1]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_109 = {1'h0, _tz_in_T_108 & 31'h55555555}; // @[ALU.scala:88:26, :134:26]
wire [30:0] _tz_in_T_110 = _tz_in_T_104[30:0]; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_111 = {_tz_in_T_110, 1'h0}; // @[ALU.scala:88:26, :134:26]
wire [31:0] _tz_in_T_113 = _tz_in_T_111 & 32'hAAAAAAAA; // @[ALU.scala:134:26]
wire [31:0] _tz_in_T_114 = _tz_in_T_109 | _tz_in_T_113; // @[ALU.scala:134:26]
wire [32:0] _tz_in_T_115 = {1'h1, _tz_in_T_114}; // @[ALU.scala:134:{16,26}]
wire _tz_in_T_116 = _tz_in_T_3 == 2'h1; // @[ALU.scala:130:{43,62}]
wire [63:0] _tz_in_T_117 = _tz_in_T_116 ? _tz_in_T_62 : io_in1_0; // @[ALU.scala:83:7, :130:62, :132:19]
wire _tz_in_T_118 = _tz_in_T_3 == 2'h2; // @[ALU.scala:130:{43,62}]
wire [63:0] _tz_in_T_119 = _tz_in_T_118 ? {31'h0, _tz_in_T_64} : _tz_in_T_117; // @[ALU.scala:130:62, :133:16]
wire _tz_in_T_120 = &_tz_in_T_3; // @[ALU.scala:130:{43,62}]
wire [63:0] tz_in = _tz_in_T_120 ? {31'h0, _tz_in_T_115} : _tz_in_T_119; // @[ALU.scala:130:62, :134:16]
wire _popc_in_T = io_in2_0[1]; // @[ALU.scala:83:7, :136:27]
wire _popc_in_T_1 = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :137:15]
wire [63:0] _popc_in_T_3 = _popc_in_T_1 ? {32'h0, _popc_in_T_2} : io_in1_0; // @[ALU.scala:83:7, :137:{8,15,32}]
wire [64:0] _popc_in_T_4 = {1'h1, tz_in}; // @[ALU.scala:130:62, :138:27]
wire _popc_in_T_5 = _popc_in_T_4[0]; // @[OneHot.scala:85:71]
wire _popc_in_T_6 = _popc_in_T_4[1]; // @[OneHot.scala:85:71]
wire _popc_in_T_7 = _popc_in_T_4[2]; // @[OneHot.scala:85:71]
wire _popc_in_T_8 = _popc_in_T_4[3]; // @[OneHot.scala:85:71]
wire _popc_in_T_9 = _popc_in_T_4[4]; // @[OneHot.scala:85:71]
wire _popc_in_T_10 = _popc_in_T_4[5]; // @[OneHot.scala:85:71]
wire _popc_in_T_11 = _popc_in_T_4[6]; // @[OneHot.scala:85:71]
wire _popc_in_T_12 = _popc_in_T_4[7]; // @[OneHot.scala:85:71]
wire _popc_in_T_13 = _popc_in_T_4[8]; // @[OneHot.scala:85:71]
wire _popc_in_T_14 = _popc_in_T_4[9]; // @[OneHot.scala:85:71]
wire _popc_in_T_15 = _popc_in_T_4[10]; // @[OneHot.scala:85:71]
wire _popc_in_T_16 = _popc_in_T_4[11]; // @[OneHot.scala:85:71]
wire _popc_in_T_17 = _popc_in_T_4[12]; // @[OneHot.scala:85:71]
wire _popc_in_T_18 = _popc_in_T_4[13]; // @[OneHot.scala:85:71]
wire _popc_in_T_19 = _popc_in_T_4[14]; // @[OneHot.scala:85:71]
wire _popc_in_T_20 = _popc_in_T_4[15]; // @[OneHot.scala:85:71]
wire _popc_in_T_21 = _popc_in_T_4[16]; // @[OneHot.scala:85:71]
wire _popc_in_T_22 = _popc_in_T_4[17]; // @[OneHot.scala:85:71]
wire _popc_in_T_23 = _popc_in_T_4[18]; // @[OneHot.scala:85:71]
wire _popc_in_T_24 = _popc_in_T_4[19]; // @[OneHot.scala:85:71]
wire _popc_in_T_25 = _popc_in_T_4[20]; // @[OneHot.scala:85:71]
wire _popc_in_T_26 = _popc_in_T_4[21]; // @[OneHot.scala:85:71]
wire _popc_in_T_27 = _popc_in_T_4[22]; // @[OneHot.scala:85:71]
wire _popc_in_T_28 = _popc_in_T_4[23]; // @[OneHot.scala:85:71]
wire _popc_in_T_29 = _popc_in_T_4[24]; // @[OneHot.scala:85:71]
wire _popc_in_T_30 = _popc_in_T_4[25]; // @[OneHot.scala:85:71]
wire _popc_in_T_31 = _popc_in_T_4[26]; // @[OneHot.scala:85:71]
wire _popc_in_T_32 = _popc_in_T_4[27]; // @[OneHot.scala:85:71]
wire _popc_in_T_33 = _popc_in_T_4[28]; // @[OneHot.scala:85:71]
wire _popc_in_T_34 = _popc_in_T_4[29]; // @[OneHot.scala:85:71]
wire _popc_in_T_35 = _popc_in_T_4[30]; // @[OneHot.scala:85:71]
wire _popc_in_T_36 = _popc_in_T_4[31]; // @[OneHot.scala:85:71]
wire _popc_in_T_37 = _popc_in_T_4[32]; // @[OneHot.scala:85:71]
wire _popc_in_T_38 = _popc_in_T_4[33]; // @[OneHot.scala:85:71]
wire _popc_in_T_39 = _popc_in_T_4[34]; // @[OneHot.scala:85:71]
wire _popc_in_T_40 = _popc_in_T_4[35]; // @[OneHot.scala:85:71]
wire _popc_in_T_41 = _popc_in_T_4[36]; // @[OneHot.scala:85:71]
wire _popc_in_T_42 = _popc_in_T_4[37]; // @[OneHot.scala:85:71]
wire _popc_in_T_43 = _popc_in_T_4[38]; // @[OneHot.scala:85:71]
wire _popc_in_T_44 = _popc_in_T_4[39]; // @[OneHot.scala:85:71]
wire _popc_in_T_45 = _popc_in_T_4[40]; // @[OneHot.scala:85:71]
wire _popc_in_T_46 = _popc_in_T_4[41]; // @[OneHot.scala:85:71]
wire _popc_in_T_47 = _popc_in_T_4[42]; // @[OneHot.scala:85:71]
wire _popc_in_T_48 = _popc_in_T_4[43]; // @[OneHot.scala:85:71]
wire _popc_in_T_49 = _popc_in_T_4[44]; // @[OneHot.scala:85:71]
wire _popc_in_T_50 = _popc_in_T_4[45]; // @[OneHot.scala:85:71]
wire _popc_in_T_51 = _popc_in_T_4[46]; // @[OneHot.scala:85:71]
wire _popc_in_T_52 = _popc_in_T_4[47]; // @[OneHot.scala:85:71]
wire _popc_in_T_53 = _popc_in_T_4[48]; // @[OneHot.scala:85:71]
wire _popc_in_T_54 = _popc_in_T_4[49]; // @[OneHot.scala:85:71]
wire _popc_in_T_55 = _popc_in_T_4[50]; // @[OneHot.scala:85:71]
wire _popc_in_T_56 = _popc_in_T_4[51]; // @[OneHot.scala:85:71]
wire _popc_in_T_57 = _popc_in_T_4[52]; // @[OneHot.scala:85:71]
wire _popc_in_T_58 = _popc_in_T_4[53]; // @[OneHot.scala:85:71]
wire _popc_in_T_59 = _popc_in_T_4[54]; // @[OneHot.scala:85:71]
wire _popc_in_T_60 = _popc_in_T_4[55]; // @[OneHot.scala:85:71]
wire _popc_in_T_61 = _popc_in_T_4[56]; // @[OneHot.scala:85:71]
wire _popc_in_T_62 = _popc_in_T_4[57]; // @[OneHot.scala:85:71]
wire _popc_in_T_63 = _popc_in_T_4[58]; // @[OneHot.scala:85:71]
wire _popc_in_T_64 = _popc_in_T_4[59]; // @[OneHot.scala:85:71]
wire _popc_in_T_65 = _popc_in_T_4[60]; // @[OneHot.scala:85:71]
wire _popc_in_T_66 = _popc_in_T_4[61]; // @[OneHot.scala:85:71]
wire _popc_in_T_67 = _popc_in_T_4[62]; // @[OneHot.scala:85:71]
wire _popc_in_T_68 = _popc_in_T_4[63]; // @[OneHot.scala:85:71]
wire _popc_in_T_69 = _popc_in_T_4[64]; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_70 = {_popc_in_T_69, 64'h0}; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_71 = _popc_in_T_68 ? 65'h8000000000000000 : _popc_in_T_70; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_72 = _popc_in_T_67 ? 65'h4000000000000000 : _popc_in_T_71; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_73 = _popc_in_T_66 ? 65'h2000000000000000 : _popc_in_T_72; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_74 = _popc_in_T_65 ? 65'h1000000000000000 : _popc_in_T_73; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_75 = _popc_in_T_64 ? 65'h800000000000000 : _popc_in_T_74; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_76 = _popc_in_T_63 ? 65'h400000000000000 : _popc_in_T_75; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_77 = _popc_in_T_62 ? 65'h200000000000000 : _popc_in_T_76; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_78 = _popc_in_T_61 ? 65'h100000000000000 : _popc_in_T_77; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_79 = _popc_in_T_60 ? 65'h80000000000000 : _popc_in_T_78; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_80 = _popc_in_T_59 ? 65'h40000000000000 : _popc_in_T_79; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_81 = _popc_in_T_58 ? 65'h20000000000000 : _popc_in_T_80; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_82 = _popc_in_T_57 ? 65'h10000000000000 : _popc_in_T_81; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_83 = _popc_in_T_56 ? 65'h8000000000000 : _popc_in_T_82; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_84 = _popc_in_T_55 ? 65'h4000000000000 : _popc_in_T_83; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_85 = _popc_in_T_54 ? 65'h2000000000000 : _popc_in_T_84; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_86 = _popc_in_T_53 ? 65'h1000000000000 : _popc_in_T_85; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_87 = _popc_in_T_52 ? 65'h800000000000 : _popc_in_T_86; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_88 = _popc_in_T_51 ? 65'h400000000000 : _popc_in_T_87; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_89 = _popc_in_T_50 ? 65'h200000000000 : _popc_in_T_88; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_90 = _popc_in_T_49 ? 65'h100000000000 : _popc_in_T_89; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_91 = _popc_in_T_48 ? 65'h80000000000 : _popc_in_T_90; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_92 = _popc_in_T_47 ? 65'h40000000000 : _popc_in_T_91; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_93 = _popc_in_T_46 ? 65'h20000000000 : _popc_in_T_92; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_94 = _popc_in_T_45 ? 65'h10000000000 : _popc_in_T_93; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_95 = _popc_in_T_44 ? 65'h8000000000 : _popc_in_T_94; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_96 = _popc_in_T_43 ? 65'h4000000000 : _popc_in_T_95; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_97 = _popc_in_T_42 ? 65'h2000000000 : _popc_in_T_96; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_98 = _popc_in_T_41 ? 65'h1000000000 : _popc_in_T_97; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_99 = _popc_in_T_40 ? 65'h800000000 : _popc_in_T_98; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_100 = _popc_in_T_39 ? 65'h400000000 : _popc_in_T_99; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_101 = _popc_in_T_38 ? 65'h200000000 : _popc_in_T_100; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_102 = _popc_in_T_37 ? 65'h100000000 : _popc_in_T_101; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_103 = _popc_in_T_36 ? 65'h80000000 : _popc_in_T_102; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_104 = _popc_in_T_35 ? 65'h40000000 : _popc_in_T_103; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_105 = _popc_in_T_34 ? 65'h20000000 : _popc_in_T_104; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_106 = _popc_in_T_33 ? 65'h10000000 : _popc_in_T_105; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_107 = _popc_in_T_32 ? 65'h8000000 : _popc_in_T_106; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_108 = _popc_in_T_31 ? 65'h4000000 : _popc_in_T_107; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_109 = _popc_in_T_30 ? 65'h2000000 : _popc_in_T_108; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_110 = _popc_in_T_29 ? 65'h1000000 : _popc_in_T_109; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_111 = _popc_in_T_28 ? 65'h800000 : _popc_in_T_110; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_112 = _popc_in_T_27 ? 65'h400000 : _popc_in_T_111; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_113 = _popc_in_T_26 ? 65'h200000 : _popc_in_T_112; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_114 = _popc_in_T_25 ? 65'h100000 : _popc_in_T_113; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_115 = _popc_in_T_24 ? 65'h80000 : _popc_in_T_114; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_116 = _popc_in_T_23 ? 65'h40000 : _popc_in_T_115; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_117 = _popc_in_T_22 ? 65'h20000 : _popc_in_T_116; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_118 = _popc_in_T_21 ? 65'h10000 : _popc_in_T_117; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_119 = _popc_in_T_20 ? 65'h8000 : _popc_in_T_118; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_120 = _popc_in_T_19 ? 65'h4000 : _popc_in_T_119; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_121 = _popc_in_T_18 ? 65'h2000 : _popc_in_T_120; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_122 = _popc_in_T_17 ? 65'h1000 : _popc_in_T_121; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_123 = _popc_in_T_16 ? 65'h800 : _popc_in_T_122; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_124 = _popc_in_T_15 ? 65'h400 : _popc_in_T_123; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_125 = _popc_in_T_14 ? 65'h200 : _popc_in_T_124; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_126 = _popc_in_T_13 ? 65'h100 : _popc_in_T_125; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_127 = _popc_in_T_12 ? 65'h80 : _popc_in_T_126; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_128 = _popc_in_T_11 ? 65'h40 : _popc_in_T_127; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_129 = _popc_in_T_10 ? 65'h20 : _popc_in_T_128; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_130 = _popc_in_T_9 ? 65'h10 : _popc_in_T_129; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_131 = _popc_in_T_8 ? 65'h8 : _popc_in_T_130; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_132 = _popc_in_T_7 ? 65'h4 : _popc_in_T_131; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_133 = _popc_in_T_6 ? 65'h2 : _popc_in_T_132; // @[OneHot.scala:85:71]
wire [64:0] _popc_in_T_134 = _popc_in_T_5 ? 65'h1 : _popc_in_T_133; // @[OneHot.scala:85:71]
wire [65:0] _popc_in_T_135 = {1'h0, _popc_in_T_134} - 66'h1; // @[Mux.scala:50:70]
wire [64:0] _popc_in_T_136 = _popc_in_T_135[64:0]; // @[ALU.scala:138:37]
wire [64:0] _popc_in_T_137 = _popc_in_T ? {1'h0, _popc_in_T_3} : _popc_in_T_136; // @[ALU.scala:88:26, :136:{20,27}, :137:8, :138:37]
wire [63:0] popc_in = _popc_in_T_137[63:0]; // @[ALU.scala:136:20, :138:43]
wire _count_T = popc_in[0]; // @[ALU.scala:138:43, :139:23]
wire _count_T_1 = popc_in[1]; // @[ALU.scala:138:43, :139:23]
wire _count_T_2 = popc_in[2]; // @[ALU.scala:138:43, :139:23]
wire _count_T_3 = popc_in[3]; // @[ALU.scala:138:43, :139:23]
wire _count_T_4 = popc_in[4]; // @[ALU.scala:138:43, :139:23]
wire _count_T_5 = popc_in[5]; // @[ALU.scala:138:43, :139:23]
wire _count_T_6 = popc_in[6]; // @[ALU.scala:138:43, :139:23]
wire _count_T_7 = popc_in[7]; // @[ALU.scala:138:43, :139:23]
wire _count_T_8 = popc_in[8]; // @[ALU.scala:138:43, :139:23]
wire _count_T_9 = popc_in[9]; // @[ALU.scala:138:43, :139:23]
wire _count_T_10 = popc_in[10]; // @[ALU.scala:138:43, :139:23]
wire _count_T_11 = popc_in[11]; // @[ALU.scala:138:43, :139:23]
wire _count_T_12 = popc_in[12]; // @[ALU.scala:138:43, :139:23]
wire _count_T_13 = popc_in[13]; // @[ALU.scala:138:43, :139:23]
wire _count_T_14 = popc_in[14]; // @[ALU.scala:138:43, :139:23]
wire _count_T_15 = popc_in[15]; // @[ALU.scala:138:43, :139:23]
wire _count_T_16 = popc_in[16]; // @[ALU.scala:138:43, :139:23]
wire _count_T_17 = popc_in[17]; // @[ALU.scala:138:43, :139:23]
wire _count_T_18 = popc_in[18]; // @[ALU.scala:138:43, :139:23]
wire _count_T_19 = popc_in[19]; // @[ALU.scala:138:43, :139:23]
wire _count_T_20 = popc_in[20]; // @[ALU.scala:138:43, :139:23]
wire _count_T_21 = popc_in[21]; // @[ALU.scala:138:43, :139:23]
wire _count_T_22 = popc_in[22]; // @[ALU.scala:138:43, :139:23]
wire _count_T_23 = popc_in[23]; // @[ALU.scala:138:43, :139:23]
wire _count_T_24 = popc_in[24]; // @[ALU.scala:138:43, :139:23]
wire _count_T_25 = popc_in[25]; // @[ALU.scala:138:43, :139:23]
wire _count_T_26 = popc_in[26]; // @[ALU.scala:138:43, :139:23]
wire _count_T_27 = popc_in[27]; // @[ALU.scala:138:43, :139:23]
wire _count_T_28 = popc_in[28]; // @[ALU.scala:138:43, :139:23]
wire _count_T_29 = popc_in[29]; // @[ALU.scala:138:43, :139:23]
wire _count_T_30 = popc_in[30]; // @[ALU.scala:138:43, :139:23]
wire _count_T_31 = popc_in[31]; // @[ALU.scala:138:43, :139:23]
wire _count_T_32 = popc_in[32]; // @[ALU.scala:138:43, :139:23]
wire _count_T_33 = popc_in[33]; // @[ALU.scala:138:43, :139:23]
wire _count_T_34 = popc_in[34]; // @[ALU.scala:138:43, :139:23]
wire _count_T_35 = popc_in[35]; // @[ALU.scala:138:43, :139:23]
wire _count_T_36 = popc_in[36]; // @[ALU.scala:138:43, :139:23]
wire _count_T_37 = popc_in[37]; // @[ALU.scala:138:43, :139:23]
wire _count_T_38 = popc_in[38]; // @[ALU.scala:138:43, :139:23]
wire _count_T_39 = popc_in[39]; // @[ALU.scala:138:43, :139:23]
wire _count_T_40 = popc_in[40]; // @[ALU.scala:138:43, :139:23]
wire _count_T_41 = popc_in[41]; // @[ALU.scala:138:43, :139:23]
wire _count_T_42 = popc_in[42]; // @[ALU.scala:138:43, :139:23]
wire _count_T_43 = popc_in[43]; // @[ALU.scala:138:43, :139:23]
wire _count_T_44 = popc_in[44]; // @[ALU.scala:138:43, :139:23]
wire _count_T_45 = popc_in[45]; // @[ALU.scala:138:43, :139:23]
wire _count_T_46 = popc_in[46]; // @[ALU.scala:138:43, :139:23]
wire _count_T_47 = popc_in[47]; // @[ALU.scala:138:43, :139:23]
wire _count_T_48 = popc_in[48]; // @[ALU.scala:138:43, :139:23]
wire _count_T_49 = popc_in[49]; // @[ALU.scala:138:43, :139:23]
wire _count_T_50 = popc_in[50]; // @[ALU.scala:138:43, :139:23]
wire _count_T_51 = popc_in[51]; // @[ALU.scala:138:43, :139:23]
wire _count_T_52 = popc_in[52]; // @[ALU.scala:138:43, :139:23]
wire _count_T_53 = popc_in[53]; // @[ALU.scala:138:43, :139:23]
wire _count_T_54 = popc_in[54]; // @[ALU.scala:138:43, :139:23]
wire _count_T_55 = popc_in[55]; // @[ALU.scala:138:43, :139:23]
wire _count_T_56 = popc_in[56]; // @[ALU.scala:138:43, :139:23]
wire _count_T_57 = popc_in[57]; // @[ALU.scala:138:43, :139:23]
wire _count_T_58 = popc_in[58]; // @[ALU.scala:138:43, :139:23]
wire _count_T_59 = popc_in[59]; // @[ALU.scala:138:43, :139:23]
wire _count_T_60 = popc_in[60]; // @[ALU.scala:138:43, :139:23]
wire _count_T_61 = popc_in[61]; // @[ALU.scala:138:43, :139:23]
wire _count_T_62 = popc_in[62]; // @[ALU.scala:138:43, :139:23]
wire _count_T_63 = popc_in[63]; // @[ALU.scala:138:43, :139:23]
wire [1:0] _count_T_64 = {1'h0, _count_T} + {1'h0, _count_T_1}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_65 = _count_T_64; // @[ALU.scala:139:23]
wire [1:0] _count_T_66 = {1'h0, _count_T_2} + {1'h0, _count_T_3}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_67 = _count_T_66; // @[ALU.scala:139:23]
wire [2:0] _count_T_68 = {1'h0, _count_T_65} + {1'h0, _count_T_67}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_69 = _count_T_68; // @[ALU.scala:139:23]
wire [1:0] _count_T_70 = {1'h0, _count_T_4} + {1'h0, _count_T_5}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_71 = _count_T_70; // @[ALU.scala:139:23]
wire [1:0] _count_T_72 = {1'h0, _count_T_6} + {1'h0, _count_T_7}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_73 = _count_T_72; // @[ALU.scala:139:23]
wire [2:0] _count_T_74 = {1'h0, _count_T_71} + {1'h0, _count_T_73}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_75 = _count_T_74; // @[ALU.scala:139:23]
wire [3:0] _count_T_76 = {1'h0, _count_T_69} + {1'h0, _count_T_75}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_77 = _count_T_76; // @[ALU.scala:139:23]
wire [1:0] _count_T_78 = {1'h0, _count_T_8} + {1'h0, _count_T_9}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_79 = _count_T_78; // @[ALU.scala:139:23]
wire [1:0] _count_T_80 = {1'h0, _count_T_10} + {1'h0, _count_T_11}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_81 = _count_T_80; // @[ALU.scala:139:23]
wire [2:0] _count_T_82 = {1'h0, _count_T_79} + {1'h0, _count_T_81}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_83 = _count_T_82; // @[ALU.scala:139:23]
wire [1:0] _count_T_84 = {1'h0, _count_T_12} + {1'h0, _count_T_13}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_85 = _count_T_84; // @[ALU.scala:139:23]
wire [1:0] _count_T_86 = {1'h0, _count_T_14} + {1'h0, _count_T_15}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_87 = _count_T_86; // @[ALU.scala:139:23]
wire [2:0] _count_T_88 = {1'h0, _count_T_85} + {1'h0, _count_T_87}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_89 = _count_T_88; // @[ALU.scala:139:23]
wire [3:0] _count_T_90 = {1'h0, _count_T_83} + {1'h0, _count_T_89}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_91 = _count_T_90; // @[ALU.scala:139:23]
wire [4:0] _count_T_92 = {1'h0, _count_T_77} + {1'h0, _count_T_91}; // @[ALU.scala:88:26, :139:23]
wire [4:0] _count_T_93 = _count_T_92; // @[ALU.scala:139:23]
wire [1:0] _count_T_94 = {1'h0, _count_T_16} + {1'h0, _count_T_17}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_95 = _count_T_94; // @[ALU.scala:139:23]
wire [1:0] _count_T_96 = {1'h0, _count_T_18} + {1'h0, _count_T_19}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_97 = _count_T_96; // @[ALU.scala:139:23]
wire [2:0] _count_T_98 = {1'h0, _count_T_95} + {1'h0, _count_T_97}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_99 = _count_T_98; // @[ALU.scala:139:23]
wire [1:0] _count_T_100 = {1'h0, _count_T_20} + {1'h0, _count_T_21}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_101 = _count_T_100; // @[ALU.scala:139:23]
wire [1:0] _count_T_102 = {1'h0, _count_T_22} + {1'h0, _count_T_23}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_103 = _count_T_102; // @[ALU.scala:139:23]
wire [2:0] _count_T_104 = {1'h0, _count_T_101} + {1'h0, _count_T_103}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_105 = _count_T_104; // @[ALU.scala:139:23]
wire [3:0] _count_T_106 = {1'h0, _count_T_99} + {1'h0, _count_T_105}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_107 = _count_T_106; // @[ALU.scala:139:23]
wire [1:0] _count_T_108 = {1'h0, _count_T_24} + {1'h0, _count_T_25}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_109 = _count_T_108; // @[ALU.scala:139:23]
wire [1:0] _count_T_110 = {1'h0, _count_T_26} + {1'h0, _count_T_27}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_111 = _count_T_110; // @[ALU.scala:139:23]
wire [2:0] _count_T_112 = {1'h0, _count_T_109} + {1'h0, _count_T_111}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_113 = _count_T_112; // @[ALU.scala:139:23]
wire [1:0] _count_T_114 = {1'h0, _count_T_28} + {1'h0, _count_T_29}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_115 = _count_T_114; // @[ALU.scala:139:23]
wire [1:0] _count_T_116 = {1'h0, _count_T_30} + {1'h0, _count_T_31}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_117 = _count_T_116; // @[ALU.scala:139:23]
wire [2:0] _count_T_118 = {1'h0, _count_T_115} + {1'h0, _count_T_117}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_119 = _count_T_118; // @[ALU.scala:139:23]
wire [3:0] _count_T_120 = {1'h0, _count_T_113} + {1'h0, _count_T_119}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_121 = _count_T_120; // @[ALU.scala:139:23]
wire [4:0] _count_T_122 = {1'h0, _count_T_107} + {1'h0, _count_T_121}; // @[ALU.scala:88:26, :139:23]
wire [4:0] _count_T_123 = _count_T_122; // @[ALU.scala:139:23]
wire [5:0] _count_T_124 = {1'h0, _count_T_93} + {1'h0, _count_T_123}; // @[ALU.scala:88:26, :139:23]
wire [5:0] _count_T_125 = _count_T_124; // @[ALU.scala:139:23]
wire [1:0] _count_T_126 = {1'h0, _count_T_32} + {1'h0, _count_T_33}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_127 = _count_T_126; // @[ALU.scala:139:23]
wire [1:0] _count_T_128 = {1'h0, _count_T_34} + {1'h0, _count_T_35}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_129 = _count_T_128; // @[ALU.scala:139:23]
wire [2:0] _count_T_130 = {1'h0, _count_T_127} + {1'h0, _count_T_129}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_131 = _count_T_130; // @[ALU.scala:139:23]
wire [1:0] _count_T_132 = {1'h0, _count_T_36} + {1'h0, _count_T_37}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_133 = _count_T_132; // @[ALU.scala:139:23]
wire [1:0] _count_T_134 = {1'h0, _count_T_38} + {1'h0, _count_T_39}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_135 = _count_T_134; // @[ALU.scala:139:23]
wire [2:0] _count_T_136 = {1'h0, _count_T_133} + {1'h0, _count_T_135}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_137 = _count_T_136; // @[ALU.scala:139:23]
wire [3:0] _count_T_138 = {1'h0, _count_T_131} + {1'h0, _count_T_137}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_139 = _count_T_138; // @[ALU.scala:139:23]
wire [1:0] _count_T_140 = {1'h0, _count_T_40} + {1'h0, _count_T_41}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_141 = _count_T_140; // @[ALU.scala:139:23]
wire [1:0] _count_T_142 = {1'h0, _count_T_42} + {1'h0, _count_T_43}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_143 = _count_T_142; // @[ALU.scala:139:23]
wire [2:0] _count_T_144 = {1'h0, _count_T_141} + {1'h0, _count_T_143}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_145 = _count_T_144; // @[ALU.scala:139:23]
wire [1:0] _count_T_146 = {1'h0, _count_T_44} + {1'h0, _count_T_45}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_147 = _count_T_146; // @[ALU.scala:139:23]
wire [1:0] _count_T_148 = {1'h0, _count_T_46} + {1'h0, _count_T_47}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_149 = _count_T_148; // @[ALU.scala:139:23]
wire [2:0] _count_T_150 = {1'h0, _count_T_147} + {1'h0, _count_T_149}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_151 = _count_T_150; // @[ALU.scala:139:23]
wire [3:0] _count_T_152 = {1'h0, _count_T_145} + {1'h0, _count_T_151}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_153 = _count_T_152; // @[ALU.scala:139:23]
wire [4:0] _count_T_154 = {1'h0, _count_T_139} + {1'h0, _count_T_153}; // @[ALU.scala:88:26, :139:23]
wire [4:0] _count_T_155 = _count_T_154; // @[ALU.scala:139:23]
wire [1:0] _count_T_156 = {1'h0, _count_T_48} + {1'h0, _count_T_49}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_157 = _count_T_156; // @[ALU.scala:139:23]
wire [1:0] _count_T_158 = {1'h0, _count_T_50} + {1'h0, _count_T_51}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_159 = _count_T_158; // @[ALU.scala:139:23]
wire [2:0] _count_T_160 = {1'h0, _count_T_157} + {1'h0, _count_T_159}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_161 = _count_T_160; // @[ALU.scala:139:23]
wire [1:0] _count_T_162 = {1'h0, _count_T_52} + {1'h0, _count_T_53}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_163 = _count_T_162; // @[ALU.scala:139:23]
wire [1:0] _count_T_164 = {1'h0, _count_T_54} + {1'h0, _count_T_55}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_165 = _count_T_164; // @[ALU.scala:139:23]
wire [2:0] _count_T_166 = {1'h0, _count_T_163} + {1'h0, _count_T_165}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_167 = _count_T_166; // @[ALU.scala:139:23]
wire [3:0] _count_T_168 = {1'h0, _count_T_161} + {1'h0, _count_T_167}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_169 = _count_T_168; // @[ALU.scala:139:23]
wire [1:0] _count_T_170 = {1'h0, _count_T_56} + {1'h0, _count_T_57}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_171 = _count_T_170; // @[ALU.scala:139:23]
wire [1:0] _count_T_172 = {1'h0, _count_T_58} + {1'h0, _count_T_59}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_173 = _count_T_172; // @[ALU.scala:139:23]
wire [2:0] _count_T_174 = {1'h0, _count_T_171} + {1'h0, _count_T_173}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_175 = _count_T_174; // @[ALU.scala:139:23]
wire [1:0] _count_T_176 = {1'h0, _count_T_60} + {1'h0, _count_T_61}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_177 = _count_T_176; // @[ALU.scala:139:23]
wire [1:0] _count_T_178 = {1'h0, _count_T_62} + {1'h0, _count_T_63}; // @[ALU.scala:88:26, :139:23]
wire [1:0] _count_T_179 = _count_T_178; // @[ALU.scala:139:23]
wire [2:0] _count_T_180 = {1'h0, _count_T_177} + {1'h0, _count_T_179}; // @[ALU.scala:88:26, :139:23]
wire [2:0] _count_T_181 = _count_T_180; // @[ALU.scala:139:23]
wire [3:0] _count_T_182 = {1'h0, _count_T_175} + {1'h0, _count_T_181}; // @[ALU.scala:88:26, :139:23]
wire [3:0] _count_T_183 = _count_T_182; // @[ALU.scala:139:23]
wire [4:0] _count_T_184 = {1'h0, _count_T_169} + {1'h0, _count_T_183}; // @[ALU.scala:88:26, :139:23]
wire [4:0] _count_T_185 = _count_T_184; // @[ALU.scala:139:23]
wire [5:0] _count_T_186 = {1'h0, _count_T_155} + {1'h0, _count_T_185}; // @[ALU.scala:88:26, :139:23]
wire [5:0] _count_T_187 = _count_T_186; // @[ALU.scala:139:23]
wire [6:0] _count_T_188 = {1'h0, _count_T_125} + {1'h0, _count_T_187}; // @[ALU.scala:88:26, :139:23]
wire [6:0] count = _count_T_188; // @[ALU.scala:139:23]
wire [7:0] _in1_bytes_T; // @[ALU.scala:140:34]
wire [7:0] _in1_bytes_T_1; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_7 = in1_bytes_0; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_2; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_6 = in1_bytes_1; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_3; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_5 = in1_bytes_2; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_4; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_4 = in1_bytes_3; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_5; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_3 = in1_bytes_4; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_6; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_2 = in1_bytes_5; // @[ALU.scala:140:34, :142:21]
wire [7:0] _in1_bytes_T_7; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_1 = in1_bytes_6; // @[ALU.scala:140:34, :142:21]
wire [7:0] in1_bytes_7; // @[ALU.scala:140:34]
wire [7:0] _rev8_WIRE_0 = in1_bytes_7; // @[ALU.scala:140:34, :142:21]
assign _in1_bytes_T = _in1_bytes_WIRE[7:0]; // @[ALU.scala:140:34]
assign in1_bytes_0 = _in1_bytes_T; // @[ALU.scala:140:34]
assign _in1_bytes_T_1 = _in1_bytes_WIRE[15:8]; // @[ALU.scala:140:34]
assign in1_bytes_1 = _in1_bytes_T_1; // @[ALU.scala:140:34]
assign _in1_bytes_T_2 = _in1_bytes_WIRE[23:16]; // @[ALU.scala:140:34]
assign in1_bytes_2 = _in1_bytes_T_2; // @[ALU.scala:140:34]
assign _in1_bytes_T_3 = _in1_bytes_WIRE[31:24]; // @[ALU.scala:140:34]
assign in1_bytes_3 = _in1_bytes_T_3; // @[ALU.scala:140:34]
assign _in1_bytes_T_4 = _in1_bytes_WIRE[39:32]; // @[ALU.scala:140:34]
assign in1_bytes_4 = _in1_bytes_T_4; // @[ALU.scala:140:34]
assign _in1_bytes_T_5 = _in1_bytes_WIRE[47:40]; // @[ALU.scala:140:34]
assign in1_bytes_5 = _in1_bytes_T_5; // @[ALU.scala:140:34]
assign _in1_bytes_T_6 = _in1_bytes_WIRE[55:48]; // @[ALU.scala:140:34]
assign in1_bytes_6 = _in1_bytes_T_6; // @[ALU.scala:140:34]
assign _in1_bytes_T_7 = _in1_bytes_WIRE[63:56]; // @[ALU.scala:140:34]
assign in1_bytes_7 = _in1_bytes_T_7; // @[ALU.scala:140:34]
wire _orcb_T = |in1_bytes_0; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_1 = {8{_orcb_T}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_0 = _orcb_T_1; // @[ALU.scala:141:{21,45}]
wire _orcb_T_2 = |in1_bytes_1; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_3 = {8{_orcb_T_2}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_1 = _orcb_T_3; // @[ALU.scala:141:{21,45}]
wire _orcb_T_4 = |in1_bytes_2; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_5 = {8{_orcb_T_4}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_2 = _orcb_T_5; // @[ALU.scala:141:{21,45}]
wire _orcb_T_6 = |in1_bytes_3; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_7 = {8{_orcb_T_6}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_3 = _orcb_T_7; // @[ALU.scala:141:{21,45}]
wire _orcb_T_8 = |in1_bytes_4; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_9 = {8{_orcb_T_8}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_4 = _orcb_T_9; // @[ALU.scala:141:{21,45}]
wire _orcb_T_10 = |in1_bytes_5; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_11 = {8{_orcb_T_10}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_5 = _orcb_T_11; // @[ALU.scala:141:{21,45}]
wire _orcb_T_12 = |in1_bytes_6; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_13 = {8{_orcb_T_12}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_6 = _orcb_T_13; // @[ALU.scala:141:{21,45}]
wire _orcb_T_14 = |in1_bytes_7; // @[ALU.scala:140:34, :141:51]
wire [7:0] _orcb_T_15 = {8{_orcb_T_14}}; // @[ALU.scala:141:{45,51}]
wire [7:0] _orcb_WIRE_7 = _orcb_T_15; // @[ALU.scala:141:{21,45}]
wire [15:0] orcb_lo_lo = {_orcb_WIRE_1, _orcb_WIRE_0}; // @[ALU.scala:141:{21,62}]
wire [15:0] orcb_lo_hi = {_orcb_WIRE_3, _orcb_WIRE_2}; // @[ALU.scala:141:{21,62}]
wire [31:0] orcb_lo = {orcb_lo_hi, orcb_lo_lo}; // @[ALU.scala:141:62]
wire [15:0] orcb_hi_lo = {_orcb_WIRE_5, _orcb_WIRE_4}; // @[ALU.scala:141:{21,62}]
wire [15:0] orcb_hi_hi = {_orcb_WIRE_7, _orcb_WIRE_6}; // @[ALU.scala:141:{21,62}]
wire [31:0] orcb_hi = {orcb_hi_hi, orcb_hi_lo}; // @[ALU.scala:141:62]
wire [63:0] orcb = {orcb_hi, orcb_lo}; // @[ALU.scala:141:62]
wire [15:0] rev8_lo_lo = {_rev8_WIRE_1, _rev8_WIRE_0}; // @[ALU.scala:142:{21,41}]
wire [15:0] rev8_lo_hi = {_rev8_WIRE_3, _rev8_WIRE_2}; // @[ALU.scala:142:{21,41}]
wire [31:0] rev8_lo = {rev8_lo_hi, rev8_lo_lo}; // @[ALU.scala:142:41]
wire [15:0] rev8_hi_lo = {_rev8_WIRE_5, _rev8_WIRE_4}; // @[ALU.scala:142:{21,41}]
wire [15:0] rev8_hi_hi = {_rev8_WIRE_7, _rev8_WIRE_6}; // @[ALU.scala:142:{21,41}]
wire [31:0] rev8_hi = {rev8_hi_hi, rev8_hi_lo}; // @[ALU.scala:142:41]
wire [63:0] rev8 = {rev8_hi, rev8_lo}; // @[ALU.scala:142:41]
wire [11:0] _unary_T = io_in2_0[11:0]; // @[ALU.scala:83:7, :143:31]
wire [15:0] _unary_T_1 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22]
wire [15:0] _unary_T_8 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22, :148:51]
wire _unary_T_2 = io_in1_0[7]; // @[ALU.scala:83:7, :147:35]
wire [55:0] _unary_T_3 = {56{_unary_T_2}}; // @[ALU.scala:147:{20,35}]
wire [7:0] _unary_T_4 = io_in1_0[7:0]; // @[ALU.scala:83:7, :147:49]
wire [63:0] _unary_T_5 = {_unary_T_3, _unary_T_4}; // @[ALU.scala:147:{20,40,49}]
wire _unary_T_6 = io_in1_0[15]; // @[ALU.scala:83:7, :148:36]
wire [47:0] _unary_T_7 = {48{_unary_T_6}}; // @[ALU.scala:148:{20,36}]
wire [63:0] _unary_T_9 = {_unary_T_7, _unary_T_8}; // @[ALU.scala:148:{20,42,51}]
wire _unary_T_10 = _unary_T == 12'h287; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_11 = _unary_T_10 ? orcb : {57'h0, count}; // @[ALU.scala:139:23, :141:62, :143:45]
wire _unary_T_12 = _unary_T == 12'h6B8; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_13 = _unary_T_12 ? rev8 : _unary_T_11; // @[ALU.scala:142:41, :143:45]
wire _unary_T_14 = _unary_T == 12'h80; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_15 = _unary_T_14 ? {48'h0, _unary_T_1} : _unary_T_13; // @[ALU.scala:143:45, :146:22]
wire _unary_T_16 = _unary_T == 12'h604; // @[ALU.scala:143:{31,45}]
wire [63:0] _unary_T_17 = _unary_T_16 ? _unary_T_5 : _unary_T_15; // @[ALU.scala:143:45, :147:40]
wire _unary_T_18 = _unary_T == 12'h605; // @[ALU.scala:143:{31,45}]
wire [63:0] unary = _unary_T_18 ? _unary_T_9 : _unary_T_17; // @[ALU.scala:143:45, :148:42]
wire [63:0] maxmin_out = io_cmp_out_0 ? io_in2_0 : io_in1_0; // @[ALU.scala:83:7, :152:23]
wire _rot_shamt_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :155:29]
wire [6:0] _rot_shamt_T_1 = _rot_shamt_T ? 7'h20 : 7'h40; // @[ALU.scala:155:{22,29}]
wire [7:0] _rot_shamt_T_2 = {1'h0, _rot_shamt_T_1} - {2'h0, shamt}; // @[package.scala:16:47]
wire [6:0] rot_shamt = _rot_shamt_T_2[6:0]; // @[ALU.scala:155:54]
wire [63:0] _rotin_T_4 = {32'h0, _rotin_T_3}; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_6 = {_rotin_T_5, 32'h0}; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_8 = _rotin_T_6 & 64'hFFFFFFFF00000000; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_9 = _rotin_T_4 | _rotin_T_8; // @[ALU.scala:156:44]
wire [47:0] _rotin_T_13 = _rotin_T_9[63:16]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_14 = {16'h0, _rotin_T_13 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotin_T_15 = _rotin_T_9[47:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_16 = {_rotin_T_15, 16'h0}; // @[ALU.scala:106:46, :156:44]
wire [63:0] _rotin_T_18 = _rotin_T_16 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_19 = _rotin_T_14 | _rotin_T_18; // @[ALU.scala:156:44]
wire [55:0] _rotin_T_23 = _rotin_T_19[63:8]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_24 = {8'h0, _rotin_T_23 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotin_T_25 = _rotin_T_19[55:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_26 = {_rotin_T_25, 8'h0}; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_28 = _rotin_T_26 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_29 = _rotin_T_24 | _rotin_T_28; // @[ALU.scala:156:44]
wire [59:0] _rotin_T_33 = _rotin_T_29[63:4]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_34 = {4'h0, _rotin_T_33 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotin_T_35 = _rotin_T_29[59:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_36 = {_rotin_T_35, 4'h0}; // @[ALU.scala:106:46, :156:44]
wire [63:0] _rotin_T_38 = _rotin_T_36 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_39 = _rotin_T_34 | _rotin_T_38; // @[ALU.scala:156:44]
wire [61:0] _rotin_T_43 = _rotin_T_39[63:2]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_44 = {2'h0, _rotin_T_43 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _rotin_T_45 = _rotin_T_39[61:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_46 = {_rotin_T_45, 2'h0}; // @[package.scala:16:47]
wire [63:0] _rotin_T_48 = _rotin_T_46 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_49 = _rotin_T_44 | _rotin_T_48; // @[ALU.scala:156:44]
wire [62:0] _rotin_T_53 = _rotin_T_49[63:1]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_54 = {1'h0, _rotin_T_53 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotin_T_55 = _rotin_T_49[62:0]; // @[ALU.scala:156:44]
wire [63:0] _rotin_T_56 = {_rotin_T_55, 1'h0}; // @[ALU.scala:88:26, :156:44]
wire [63:0] _rotin_T_58 = _rotin_T_56 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotin_T_59 = _rotin_T_54 | _rotin_T_58; // @[ALU.scala:156:44]
wire [63:0] rotin = _rotin_T ? shin_r : _rotin_T_59; // @[ALU.scala:104:18, :156:{18,24,44}]
wire [63:0] _rotout_r_T = rotin >> rot_shamt; // @[ALU.scala:155:54, :156:18, :157:25]
wire [63:0] rotout_r = _rotout_r_T; // @[ALU.scala:157:{25,38}]
wire [31:0] _rotout_l_T_2 = rotout_r[63:32]; // @[ALU.scala:157:38, :158:25]
wire [63:0] _rotout_l_T_3 = {32'h0, _rotout_l_T_2}; // @[ALU.scala:158:25]
wire [31:0] _rotout_l_T_4 = rotout_r[31:0]; // @[ALU.scala:157:38, :158:25]
wire [63:0] _rotout_l_T_5 = {_rotout_l_T_4, 32'h0}; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_7 = _rotout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_8 = _rotout_l_T_3 | _rotout_l_T_7; // @[ALU.scala:158:25]
wire [47:0] _rotout_l_T_12 = _rotout_l_T_8[63:16]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_13 = {16'h0, _rotout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [47:0] _rotout_l_T_14 = _rotout_l_T_8[47:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_15 = {_rotout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :158:25]
wire [63:0] _rotout_l_T_17 = _rotout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_18 = _rotout_l_T_13 | _rotout_l_T_17; // @[ALU.scala:158:25]
wire [55:0] _rotout_l_T_22 = _rotout_l_T_18[63:8]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_23 = {8'h0, _rotout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [55:0] _rotout_l_T_24 = _rotout_l_T_18[55:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_25 = {_rotout_l_T_24, 8'h0}; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_27 = _rotout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_28 = _rotout_l_T_23 | _rotout_l_T_27; // @[ALU.scala:158:25]
wire [59:0] _rotout_l_T_32 = _rotout_l_T_28[63:4]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_33 = {4'h0, _rotout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [59:0] _rotout_l_T_34 = _rotout_l_T_28[59:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_35 = {_rotout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :158:25]
wire [63:0] _rotout_l_T_37 = _rotout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_38 = _rotout_l_T_33 | _rotout_l_T_37; // @[ALU.scala:158:25]
wire [61:0] _rotout_l_T_42 = _rotout_l_T_38[63:2]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_43 = {2'h0, _rotout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47]
wire [61:0] _rotout_l_T_44 = _rotout_l_T_38[61:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_45 = {_rotout_l_T_44, 2'h0}; // @[package.scala:16:47]
wire [63:0] _rotout_l_T_47 = _rotout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] _rotout_l_T_48 = _rotout_l_T_43 | _rotout_l_T_47; // @[ALU.scala:158:25]
wire [62:0] _rotout_l_T_52 = _rotout_l_T_48[63:1]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_53 = {1'h0, _rotout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25]
wire [62:0] _rotout_l_T_54 = _rotout_l_T_48[62:0]; // @[ALU.scala:158:25]
wire [63:0] _rotout_l_T_55 = {_rotout_l_T_54, 1'h0}; // @[ALU.scala:88:26, :158:25]
wire [63:0] _rotout_l_T_57 = _rotout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25]
wire [63:0] rotout_l = _rotout_l_T_53 | _rotout_l_T_57; // @[ALU.scala:158:25]
wire [63:0] _rotout_T_1 = _rotout_T ? rotout_r : rotout_l; // @[ALU.scala:157:38, :158:25, :159:{19,25}]
wire [63:0] _rotout_T_3 = _rotout_T_2 ? shout_l : shout_r; // @[ALU.scala:107:73, :108:24, :159:{55,61}]
wire [63:0] rotout = _rotout_T_1 | _rotout_T_3; // @[ALU.scala:159:{19,50,55}]
wire _out_T = io_fn_0 == 5'h0; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_1 = _out_T ? io_adder_out_0 : shift_logic; // @[ALU.scala:83:7, :123:52, :161:47]
wire _out_T_2 = io_fn_0 == 5'hA; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_3 = _out_T_2 ? io_adder_out_0 : _out_T_1; // @[ALU.scala:83:7, :161:47]
wire _out_T_4 = io_fn_0 == 5'h10; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_5 = _out_T_4 ? unary : _out_T_3; // @[ALU.scala:143:45, :161:47]
wire _out_T_6 = io_fn_0 == 5'h1C; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_7 = _out_T_6 ? maxmin_out : _out_T_5; // @[ALU.scala:152:23, :161:47]
wire _out_T_8 = io_fn_0 == 5'h1D; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_9 = _out_T_8 ? maxmin_out : _out_T_7; // @[ALU.scala:152:23, :161:47]
wire _out_T_10 = io_fn_0 == 5'h1E; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_11 = _out_T_10 ? maxmin_out : _out_T_9; // @[ALU.scala:152:23, :161:47]
wire _out_T_12 = &io_fn_0; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_13 = _out_T_12 ? maxmin_out : _out_T_11; // @[ALU.scala:152:23, :161:47]
wire _out_T_14 = io_fn_0 == 5'h11; // @[ALU.scala:83:7, :161:47]
wire [63:0] _out_T_15 = _out_T_14 ? rotout : _out_T_13; // @[ALU.scala:159:50, :161:47]
wire [63:0] out = _out_T_16 ? rotout : _out_T_15; // @[ALU.scala:159:50, :161:47]
wire _io_out_T = out[31]; // @[ALU.scala:161:47, :178:56]
wire [31:0] _io_out_T_1 = {32{_io_out_T}}; // @[ALU.scala:178:{48,56}]
wire [31:0] _io_out_T_2 = out[31:0]; // @[ALU.scala:161:47, :178:66]
wire [63:0] _io_out_T_3 = {_io_out_T_1, _io_out_T_2}; // @[ALU.scala:178:{43,48,66}]
assign io_out_0 = io_dw_0 ? out : _io_out_T_3; // @[ALU.scala:83:7, :161:47, :175:10, :178:{28,37,43}]
assign io_out = io_out_0; // @[ALU.scala:83:7]
assign io_adder_out = io_adder_out_0; // @[ALU.scala:83:7]
assign io_cmp_out = io_cmp_out_0; // @[ALU.scala:83:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_7 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_7
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_7( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_7 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_18 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}}
node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero)
node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf)
node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1)
node notNaN_isInfOut = or(io.a.isInf, io.b.isInf)
node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero)
node notNaN_signOut = xor(io.a.sign, io.b.sign)
node _common_sExpOut_T = add(io.a.sExp, io.b.sExp)
node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1)
node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1)
node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100)))
node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1)
node common_sExpOut = asSInt(_common_sExpOut_T_4)
node _common_sigOut_T = mul(io.a.sig, io.b.sig)
node common_sigOut = bits(_common_sigOut_T, 47, 0)
node _io_invalidExc_T = bits(io.a.sig, 22, 22)
node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0))
node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1)
node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22)
node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0))
node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4)
node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc)
connect io.invalidExc, _io_invalidExc_T_7
connect io.rawOut.isInf, notNaN_isInfOut
connect io.rawOut.isZero, notNaN_isZeroOut
connect io.rawOut.sExp, common_sExpOut
node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.sign, notNaN_signOut
connect io.rawOut.sig, common_sigOut | module MulFullRawFN_18( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_490 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_234
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_490( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_234 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_5 :
input clock : Clock
input reset : Reset
output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}}
node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31)
node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23)
node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0)
node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0)
node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1)
node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2)
node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3)
node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4)
node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5)
node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6)
node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7)
node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8)
node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9)
node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10)
node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11)
node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12)
node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13)
node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14)
node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15)
node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16)
node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17)
node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18)
node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19)
node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20)
node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21)
node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22)
node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23)
node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24)
node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25)
node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26)
node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27)
node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28)
node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29)
node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30)
node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31)
node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32)
node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33)
node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34)
node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35)
node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36)
node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37)
node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38)
node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39)
node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40)
node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41)
node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42)
node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43)
node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist)
node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn)
node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2)
node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3)
node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn)
node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T)
connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1
node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn)
connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T
connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero
connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign
node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T)
connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1
node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T)
node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn)
node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2)
connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3
node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6)
node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T)
node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2)
node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3)
node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0)
node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5)
node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0)
node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7)
node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31)
node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23)
node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0)
node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0)
node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1)
node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2)
node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3)
node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4)
node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5)
node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6)
node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7)
node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8)
node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9)
node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10)
node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11)
node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12)
node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13)
node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14)
node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15)
node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16)
node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17)
node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18)
node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19)
node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20)
node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21)
node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22)
node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23)
node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24)
node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25)
node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26)
node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27)
node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28)
node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29)
node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30)
node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31)
node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32)
node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33)
node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34)
node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35)
node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36)
node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37)
node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38)
node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39)
node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40)
node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41)
node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42)
node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43)
node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist)
node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn)
node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2)
node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3)
node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn)
node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T)
connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1
node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn)
connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T
connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero
connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign
node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T)
connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1
node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T)
node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn)
node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2)
connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3
node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6)
node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T)
node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2)
node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3)
node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0)
node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5)
node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0)
node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7)
node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31)
node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23)
node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0)
node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0)
node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1)
node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2)
node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3)
node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4)
node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5)
node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6)
node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7)
node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8)
node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9)
node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10)
node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11)
node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12)
node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13)
node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14)
node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15)
node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16)
node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17)
node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18)
node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19)
node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20)
node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21)
node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22)
node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23)
node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24)
node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25)
node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26)
node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27)
node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28)
node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29)
node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30)
node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31)
node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32)
node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33)
node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34)
node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35)
node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36)
node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37)
node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38)
node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39)
node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40)
node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41)
node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42)
node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43)
node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist)
node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn)
node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2)
node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3)
node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn)
node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T)
connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1
node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn)
connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T
connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero
connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign
node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T)
connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1
node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T)
node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn)
node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2)
connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3
node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6)
node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T)
node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2)
node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3)
node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0)
node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5)
node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0)
node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7)
inst io_out_d_m1_resizer of RecFNToRecFN_174
connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec
connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0)
connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1)
inst io_out_d_m2_resizer of RecFNToRecFN_175
connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec
connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0)
connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1)
inst io_out_d_muladder of MulAddRecFN_e8_s24_69
connect io_out_d_muladder.io.op, UInt<1>(0h0)
connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0)
connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1)
connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out
connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out
connect io_out_d_muladder.io.c, io_out_d_self_rec
wire io_out_d_out : { bits : UInt<32>}
node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23)
node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6)
node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7)
node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6)
node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T)
connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1
node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6)
node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1)
connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2
connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero
node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32)
connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T
node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp)
connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T
node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T)
node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0)
node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2)
connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3
node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0)
node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T)
node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1)
node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1)
node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist)
node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0)
node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0)
node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81))
node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1)
node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2)
node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf)
node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5)
node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0)
node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T)
node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1)
node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut)
node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut)
connect io_out_d_out.bits, _io_out_d_out_bits_T
connect io.out_d, io_out_d_out | module MacUnit_5( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [31:0] io_in_a_bits, // @[PE.scala:16:14]
input [31:0] io_in_b_bits, // @[PE.scala:16:14]
input [31:0] io_in_c_bits, // @[PE.scala:16:14]
output [31:0] io_out_d_bits // @[PE.scala:16:14]
);
wire io_out_d_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_d_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_d_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [32:0] _io_out_d_muladder_io_out; // @[Arithmetic.scala:376:30]
wire [32:0] _io_out_d_m2_resizer_io_out; // @[Arithmetic.scala:369:32]
wire [32:0] _io_out_d_m1_resizer_io_out; // @[Arithmetic.scala:362:32]
wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:14:7]
wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:14:7]
wire [31:0] io_in_c_bits_0 = io_in_c_bits; // @[PE.scala:14:7]
wire [31:0] io_out_d_out_bits; // @[Arithmetic.scala:387:23]
wire [31:0] io_out_d_bits_0; // @[PE.scala:14:7]
wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] | _io_out_d_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] | _io_out_d_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] | _io_out_d_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12]
assign io_out_d_bits_0 = io_out_d_out_bits; // @[PE.scala:14:7]
wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_d_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_d_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_d_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_d_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN | io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 | _io_out_d_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_out_d_out_bits = _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12]
RecFNToRecFN_174 io_out_d_m1_resizer ( // @[Arithmetic.scala:362:32]
.io_in (io_out_d_m1_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_m1_resizer_io_out)
); // @[Arithmetic.scala:362:32]
RecFNToRecFN_175 io_out_d_m2_resizer ( // @[Arithmetic.scala:369:32]
.io_in (io_out_d_m2_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_m2_resizer_io_out)
); // @[Arithmetic.scala:369:32]
MulAddRecFN_e8_s24_69 io_out_d_muladder ( // @[Arithmetic.scala:376:30]
.io_a (_io_out_d_m1_resizer_io_out), // @[Arithmetic.scala:362:32]
.io_b (_io_out_d_m2_resizer_io_out), // @[Arithmetic.scala:369:32]
.io_c (io_out_d_self_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_muladder_io_out)
); // @[Arithmetic.scala:376:30]
assign io_out_d_bits = io_out_d_bits_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = and(_T_11, _T_24)
node _T_105 = and(_T_104, _T_37)
node _T_106 = and(_T_105, _T_50)
node _T_107 = and(_T_106, _T_63)
node _T_108 = and(_T_107, _T_71)
node _T_109 = and(_T_108, _T_79)
node _T_110 = and(_T_109, _T_87)
node _T_111 = and(_T_110, _T_95)
node _T_112 = and(_T_111, _T_103)
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(_T_112, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_112, UInt<1>(0h1), "") : assert_1
node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_116 :
node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_121 = shr(io.in.a.bits.source, 2)
node _T_122 = eq(_T_121, UInt<1>(0h0))
node _T_123 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_124 = and(_T_122, _T_123)
node _T_125 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_126 = and(_T_124, _T_125)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<1>(0h1))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<2>(0h2))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<2>(0h3))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_120, _T_126)
node _T_151 = or(_T_150, _T_132)
node _T_152 = or(_T_151, _T_138)
node _T_153 = or(_T_152, _T_144)
node _T_154 = or(_T_153, _T_145)
node _T_155 = or(_T_154, _T_146)
node _T_156 = or(_T_155, _T_147)
node _T_157 = or(_T_156, _T_148)
node _T_158 = or(_T_157, _T_149)
node _T_159 = and(_T_119, _T_158)
node _T_160 = or(UInt<1>(0h0), _T_159)
node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<13>(0h1000)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = and(_T_161, _T_166)
node _T_168 = or(UInt<1>(0h0), _T_167)
node _T_169 = and(_T_160, _T_168)
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_169, UInt<1>(0h1), "") : assert_2
node _T_173 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_174 = shr(io.in.a.bits.source, 2)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_177 = and(_T_175, _T_176)
node _T_178 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_179 = and(_T_177, _T_178)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_180 = shr(io.in.a.bits.source, 2)
node _T_181 = eq(_T_180, UInt<1>(0h1))
node _T_182 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_183 = and(_T_181, _T_182)
node _T_184 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_185 = and(_T_183, _T_184)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_186 = shr(io.in.a.bits.source, 2)
node _T_187 = eq(_T_186, UInt<2>(0h2))
node _T_188 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_189 = and(_T_187, _T_188)
node _T_190 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_191 = and(_T_189, _T_190)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_192 = shr(io.in.a.bits.source, 2)
node _T_193 = eq(_T_192, UInt<2>(0h3))
node _T_194 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_195 = and(_T_193, _T_194)
node _T_196 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_201 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_202 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[10]
connect _WIRE[0], _T_173
connect _WIRE[1], _T_179
connect _WIRE[2], _T_185
connect _WIRE[3], _T_191
connect _WIRE[4], _T_197
connect _WIRE[5], _T_198
connect _WIRE[6], _T_199
connect _WIRE[7], _T_200
connect _WIRE[8], _T_201
connect _WIRE[9], _T_202
node _T_203 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_204 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_205 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_207 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[6], _T_203, UInt<1>(0h0))
node _T_211 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_213 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_214 = or(_T_204, _T_205)
node _T_215 = or(_T_214, _T_206)
node _T_216 = or(_T_215, _T_207)
node _T_217 = or(_T_216, _T_208)
node _T_218 = or(_T_217, _T_209)
node _T_219 = or(_T_218, _T_210)
node _T_220 = or(_T_219, _T_211)
node _T_221 = or(_T_220, _T_212)
node _T_222 = or(_T_221, _T_213)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_222
node _T_223 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_224 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_225 = and(_T_223, _T_224)
node _T_226 = or(UInt<1>(0h0), _T_225)
node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_228 = cvt(_T_227)
node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000)))
node _T_230 = asSInt(_T_229)
node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0)))
node _T_232 = and(_T_226, _T_231)
node _T_233 = or(UInt<1>(0h0), _T_232)
node _T_234 = and(_WIRE_1, _T_233)
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_234, UInt<1>(0h1), "") : assert_3
node _T_238 = asUInt(reset)
node _T_239 = eq(_T_238, UInt<1>(0h0))
when _T_239 :
node _T_240 = eq(source_ok, UInt<1>(0h0))
when _T_240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_242 = asUInt(reset)
node _T_243 = eq(_T_242, UInt<1>(0h0))
when _T_243 :
node _T_244 = eq(_T_241, UInt<1>(0h0))
when _T_244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_241, UInt<1>(0h1), "") : assert_5
node _T_245 = asUInt(reset)
node _T_246 = eq(_T_245, UInt<1>(0h0))
when _T_246 :
node _T_247 = eq(is_aligned, UInt<1>(0h0))
when _T_247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_248, UInt<1>(0h1), "") : assert_7
node _T_252 = not(io.in.a.bits.mask)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_253, UInt<1>(0h1), "") : assert_8
node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_T_257, UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_257, UInt<1>(0h1), "") : assert_9
node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_261 :
node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<1>(0h1))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h2))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<2>(0h3))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_295 = or(_T_265, _T_271)
node _T_296 = or(_T_295, _T_277)
node _T_297 = or(_T_296, _T_283)
node _T_298 = or(_T_297, _T_289)
node _T_299 = or(_T_298, _T_290)
node _T_300 = or(_T_299, _T_291)
node _T_301 = or(_T_300, _T_292)
node _T_302 = or(_T_301, _T_293)
node _T_303 = or(_T_302, _T_294)
node _T_304 = and(_T_264, _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_307 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = and(_T_306, _T_311)
node _T_313 = or(UInt<1>(0h0), _T_312)
node _T_314 = and(_T_305, _T_313)
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(_T_314, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_314, UInt<1>(0h1), "") : assert_10
node _T_318 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_319 = shr(io.in.a.bits.source, 2)
node _T_320 = eq(_T_319, UInt<1>(0h0))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_325 = shr(io.in.a.bits.source, 2)
node _T_326 = eq(_T_325, UInt<1>(0h1))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_330 = and(_T_328, _T_329)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<2>(0h2))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<2>(0h3))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[10]
connect _WIRE_2[0], _T_318
connect _WIRE_2[1], _T_324
connect _WIRE_2[2], _T_330
connect _WIRE_2[3], _T_336
connect _WIRE_2[4], _T_342
connect _WIRE_2[5], _T_343
connect _WIRE_2[6], _T_344
connect _WIRE_2[7], _T_345
connect _WIRE_2[8], _T_346
connect _WIRE_2[9], _T_347
node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_349 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_350 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_352 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_353 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_354 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_355 = mux(_WIRE_2[6], _T_348, UInt<1>(0h0))
node _T_356 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_357 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = or(_T_349, _T_350)
node _T_360 = or(_T_359, _T_351)
node _T_361 = or(_T_360, _T_352)
node _T_362 = or(_T_361, _T_353)
node _T_363 = or(_T_362, _T_354)
node _T_364 = or(_T_363, _T_355)
node _T_365 = or(_T_364, _T_356)
node _T_366 = or(_T_365, _T_357)
node _T_367 = or(_T_366, _T_358)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_367
node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_370 = and(_T_368, _T_369)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = and(_T_371, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = and(_WIRE_3, _T_378)
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_379, UInt<1>(0h1), "") : assert_11
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(source_ok, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_386, UInt<1>(0h1), "") : assert_13
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(is_aligned, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_393, UInt<1>(0h1), "") : assert_15
node _T_397 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_397, UInt<1>(0h1), "") : assert_16
node _T_401 = not(io.in.a.bits.mask)
node _T_402 = eq(_T_401, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_402, UInt<1>(0h1), "") : assert_17
node _T_406 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_406, UInt<1>(0h1), "") : assert_18
node _T_410 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_410 :
node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_413 = and(_T_411, _T_412)
node _T_414 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_415 = shr(io.in.a.bits.source, 2)
node _T_416 = eq(_T_415, UInt<1>(0h0))
node _T_417 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_418 = and(_T_416, _T_417)
node _T_419 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h1))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<2>(0h2))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h3))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_444 = or(_T_414, _T_420)
node _T_445 = or(_T_444, _T_426)
node _T_446 = or(_T_445, _T_432)
node _T_447 = or(_T_446, _T_438)
node _T_448 = or(_T_447, _T_439)
node _T_449 = or(_T_448, _T_440)
node _T_450 = or(_T_449, _T_441)
node _T_451 = or(_T_450, _T_442)
node _T_452 = or(_T_451, _T_443)
node _T_453 = and(_T_413, _T_452)
node _T_454 = or(UInt<1>(0h0), _T_453)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_454, UInt<1>(0h1), "") : assert_19
node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_459 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_460 = and(_T_458, _T_459)
node _T_461 = or(UInt<1>(0h0), _T_460)
node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = and(_T_461, _T_466)
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_468, UInt<1>(0h1), "") : assert_20
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(source_ok, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(is_aligned, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_478 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_478, UInt<1>(0h1), "") : assert_23
node _T_482 = eq(io.in.a.bits.mask, mask)
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_482, UInt<1>(0h1), "") : assert_24
node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_486, UInt<1>(0h1), "") : assert_25
node _T_490 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_490 :
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_495 = shr(io.in.a.bits.source, 2)
node _T_496 = eq(_T_495, UInt<1>(0h0))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<1>(0h1))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<2>(0h2))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<2>(0h3))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_524 = or(_T_494, _T_500)
node _T_525 = or(_T_524, _T_506)
node _T_526 = or(_T_525, _T_512)
node _T_527 = or(_T_526, _T_518)
node _T_528 = or(_T_527, _T_519)
node _T_529 = or(_T_528, _T_520)
node _T_530 = or(_T_529, _T_521)
node _T_531 = or(_T_530, _T_522)
node _T_532 = or(_T_531, _T_523)
node _T_533 = and(_T_493, _T_532)
node _T_534 = or(UInt<1>(0h0), _T_533)
node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_536 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_537 = and(_T_535, _T_536)
node _T_538 = or(UInt<1>(0h0), _T_537)
node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = and(_T_538, _T_543)
node _T_545 = or(UInt<1>(0h0), _T_544)
node _T_546 = and(_T_534, _T_545)
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_546, UInt<1>(0h1), "") : assert_26
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(source_ok, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(is_aligned, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_556 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_556, UInt<1>(0h1), "") : assert_29
node _T_560 = eq(io.in.a.bits.mask, mask)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_560, UInt<1>(0h1), "") : assert_30
node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_564 :
node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_567 = and(_T_565, _T_566)
node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_569 = shr(io.in.a.bits.source, 2)
node _T_570 = eq(_T_569, UInt<1>(0h0))
node _T_571 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_572 = and(_T_570, _T_571)
node _T_573 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_574 = and(_T_572, _T_573)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_575 = shr(io.in.a.bits.source, 2)
node _T_576 = eq(_T_575, UInt<1>(0h1))
node _T_577 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_578 = and(_T_576, _T_577)
node _T_579 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_580 = and(_T_578, _T_579)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<2>(0h2))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<2>(0h3))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_598 = or(_T_568, _T_574)
node _T_599 = or(_T_598, _T_580)
node _T_600 = or(_T_599, _T_586)
node _T_601 = or(_T_600, _T_592)
node _T_602 = or(_T_601, _T_593)
node _T_603 = or(_T_602, _T_594)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_596)
node _T_606 = or(_T_605, _T_597)
node _T_607 = and(_T_567, _T_606)
node _T_608 = or(UInt<1>(0h0), _T_607)
node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_611 = and(_T_609, _T_610)
node _T_612 = or(UInt<1>(0h0), _T_611)
node _T_613 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<13>(0h1000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = and(_T_612, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_618)
node _T_620 = and(_T_608, _T_619)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_620, UInt<1>(0h1), "") : assert_31
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(source_ok, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(is_aligned, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_630 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_630, UInt<1>(0h1), "") : assert_34
node _T_634 = not(mask)
node _T_635 = and(io.in.a.bits.mask, _T_634)
node _T_636 = eq(_T_635, UInt<1>(0h0))
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_636, UInt<1>(0h1), "") : assert_35
node _T_640 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_640 :
node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_645 = shr(io.in.a.bits.source, 2)
node _T_646 = eq(_T_645, UInt<1>(0h0))
node _T_647 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_648 = and(_T_646, _T_647)
node _T_649 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_650 = and(_T_648, _T_649)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_651 = shr(io.in.a.bits.source, 2)
node _T_652 = eq(_T_651, UInt<1>(0h1))
node _T_653 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_654 = and(_T_652, _T_653)
node _T_655 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_656 = and(_T_654, _T_655)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_657 = shr(io.in.a.bits.source, 2)
node _T_658 = eq(_T_657, UInt<2>(0h2))
node _T_659 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_660 = and(_T_658, _T_659)
node _T_661 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_662 = and(_T_660, _T_661)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_663 = shr(io.in.a.bits.source, 2)
node _T_664 = eq(_T_663, UInt<2>(0h3))
node _T_665 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_666 = and(_T_664, _T_665)
node _T_667 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_668 = and(_T_666, _T_667)
node _T_669 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_673 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_674 = or(_T_644, _T_650)
node _T_675 = or(_T_674, _T_656)
node _T_676 = or(_T_675, _T_662)
node _T_677 = or(_T_676, _T_668)
node _T_678 = or(_T_677, _T_669)
node _T_679 = or(_T_678, _T_670)
node _T_680 = or(_T_679, _T_671)
node _T_681 = or(_T_680, _T_672)
node _T_682 = or(_T_681, _T_673)
node _T_683 = and(_T_643, _T_682)
node _T_684 = or(UInt<1>(0h0), _T_683)
node _T_685 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_686 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_687 = cvt(_T_686)
node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000)))
node _T_689 = asSInt(_T_688)
node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0)))
node _T_691 = and(_T_685, _T_690)
node _T_692 = or(UInt<1>(0h0), _T_691)
node _T_693 = and(_T_684, _T_692)
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_693, UInt<1>(0h1), "") : assert_36
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(source_ok, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(is_aligned, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_703 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_703, UInt<1>(0h1), "") : assert_39
node _T_707 = eq(io.in.a.bits.mask, mask)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_707, UInt<1>(0h1), "") : assert_40
node _T_711 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_711 :
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_714 = and(_T_712, _T_713)
node _T_715 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_716 = shr(io.in.a.bits.source, 2)
node _T_717 = eq(_T_716, UInt<1>(0h0))
node _T_718 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_719 = and(_T_717, _T_718)
node _T_720 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_722 = shr(io.in.a.bits.source, 2)
node _T_723 = eq(_T_722, UInt<1>(0h1))
node _T_724 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_725 = and(_T_723, _T_724)
node _T_726 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_727 = and(_T_725, _T_726)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_728 = shr(io.in.a.bits.source, 2)
node _T_729 = eq(_T_728, UInt<2>(0h2))
node _T_730 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_731 = and(_T_729, _T_730)
node _T_732 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_733 = and(_T_731, _T_732)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<2>(0h3))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _T_740 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_744 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_745 = or(_T_715, _T_721)
node _T_746 = or(_T_745, _T_727)
node _T_747 = or(_T_746, _T_733)
node _T_748 = or(_T_747, _T_739)
node _T_749 = or(_T_748, _T_740)
node _T_750 = or(_T_749, _T_741)
node _T_751 = or(_T_750, _T_742)
node _T_752 = or(_T_751, _T_743)
node _T_753 = or(_T_752, _T_744)
node _T_754 = and(_T_714, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_757 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_758 = cvt(_T_757)
node _T_759 = and(_T_758, asSInt(UInt<13>(0h1000)))
node _T_760 = asSInt(_T_759)
node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0)))
node _T_762 = and(_T_756, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_762)
node _T_764 = and(_T_755, _T_763)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_764, UInt<1>(0h1), "") : assert_41
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(source_ok, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(is_aligned, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_774 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_774, UInt<1>(0h1), "") : assert_44
node _T_778 = eq(io.in.a.bits.mask, mask)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_778, UInt<1>(0h1), "") : assert_45
node _T_782 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_782 :
node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_787 = shr(io.in.a.bits.source, 2)
node _T_788 = eq(_T_787, UInt<1>(0h0))
node _T_789 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_790 = and(_T_788, _T_789)
node _T_791 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_792 = and(_T_790, _T_791)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_793 = shr(io.in.a.bits.source, 2)
node _T_794 = eq(_T_793, UInt<1>(0h1))
node _T_795 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_796 = and(_T_794, _T_795)
node _T_797 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_798 = and(_T_796, _T_797)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_799 = shr(io.in.a.bits.source, 2)
node _T_800 = eq(_T_799, UInt<2>(0h2))
node _T_801 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_802 = and(_T_800, _T_801)
node _T_803 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_804 = and(_T_802, _T_803)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_805 = shr(io.in.a.bits.source, 2)
node _T_806 = eq(_T_805, UInt<2>(0h3))
node _T_807 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_808 = and(_T_806, _T_807)
node _T_809 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_810 = and(_T_808, _T_809)
node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_816 = or(_T_786, _T_792)
node _T_817 = or(_T_816, _T_798)
node _T_818 = or(_T_817, _T_804)
node _T_819 = or(_T_818, _T_810)
node _T_820 = or(_T_819, _T_811)
node _T_821 = or(_T_820, _T_812)
node _T_822 = or(_T_821, _T_813)
node _T_823 = or(_T_822, _T_814)
node _T_824 = or(_T_823, _T_815)
node _T_825 = and(_T_785, _T_824)
node _T_826 = or(UInt<1>(0h0), _T_825)
node _T_827 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_828 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<13>(0h1000)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = and(_T_827, _T_832)
node _T_834 = or(UInt<1>(0h0), _T_833)
node _T_835 = and(_T_826, _T_834)
node _T_836 = asUInt(reset)
node _T_837 = eq(_T_836, UInt<1>(0h0))
when _T_837 :
node _T_838 = eq(_T_835, UInt<1>(0h0))
when _T_838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_835, UInt<1>(0h1), "") : assert_46
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(source_ok, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(is_aligned, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_845 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_845, UInt<1>(0h1), "") : assert_49
node _T_849 = eq(io.in.a.bits.mask, mask)
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_849, UInt<1>(0h1), "") : assert_50
node _T_853 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_853, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_857 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(_T_857, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_857, UInt<1>(0h1), "") : assert_52
node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_38
connect _source_ok_WIRE_1[1], _source_ok_T_44
connect _source_ok_WIRE_1[2], _source_ok_T_50
connect _source_ok_WIRE_1[3], _source_ok_T_56
connect _source_ok_WIRE_1[4], _source_ok_T_62
connect _source_ok_WIRE_1[5], _source_ok_T_63
connect _source_ok_WIRE_1[6], _source_ok_T_64
connect _source_ok_WIRE_1[7], _source_ok_T_65
connect _source_ok_WIRE_1[8], _source_ok_T_66
connect _source_ok_WIRE_1[9], _source_ok_T_67
node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_861 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_861 :
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(source_ok_1, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_865, UInt<1>(0h1), "") : assert_54
node _T_869 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_869, UInt<1>(0h1), "") : assert_55
node _T_873 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_873, UInt<1>(0h1), "") : assert_56
node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_877, UInt<1>(0h1), "") : assert_57
node _T_881 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_881 :
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(source_ok_1, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(sink_ok, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_888 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(_T_888, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_888, UInt<1>(0h1), "") : assert_60
node _T_892 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_892, UInt<1>(0h1), "") : assert_61
node _T_896 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_896, UInt<1>(0h1), "") : assert_62
node _T_900 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_900, UInt<1>(0h1), "") : assert_63
node _T_904 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_905 = or(UInt<1>(0h0), _T_904)
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(_T_905, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_905, UInt<1>(0h1), "") : assert_64
node _T_909 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_909 :
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(source_ok_1, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(sink_ok, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_916 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_916, UInt<1>(0h1), "") : assert_67
node _T_920 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_920, UInt<1>(0h1), "") : assert_68
node _T_924 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_924, UInt<1>(0h1), "") : assert_69
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(_T_928, io.in.d.bits.corrupt)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_929, UInt<1>(0h1), "") : assert_70
node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_934 = or(UInt<1>(0h0), _T_933)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_934, UInt<1>(0h1), "") : assert_71
node _T_938 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_938 :
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(source_ok_1, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_942 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_942, UInt<1>(0h1), "") : assert_73
node _T_946 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_946, UInt<1>(0h1), "") : assert_74
node _T_950 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_951 = or(UInt<1>(0h0), _T_950)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_951, UInt<1>(0h1), "") : assert_75
node _T_955 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_955 :
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(source_ok_1, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_959, UInt<1>(0h1), "") : assert_77
node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_964 = or(_T_963, io.in.d.bits.corrupt)
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_964, UInt<1>(0h1), "") : assert_78
node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_969, UInt<1>(0h1), "") : assert_79
node _T_973 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_973 :
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(source_ok_1, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_978 = asUInt(reset)
node _T_979 = eq(_T_978, UInt<1>(0h0))
when _T_979 :
node _T_980 = eq(_T_977, UInt<1>(0h0))
when _T_980 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_977, UInt<1>(0h1), "") : assert_81
node _T_981 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(_T_981, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_981, UInt<1>(0h1), "") : assert_82
node _T_985 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_986 = or(UInt<1>(0h0), _T_985)
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_986, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_990 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_990, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_994 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_994, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_998 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_998, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1002 = eq(a_first, UInt<1>(0h0))
node _T_1003 = and(io.in.a.valid, _T_1002)
when _T_1003 :
node _T_1004 = eq(io.in.a.bits.opcode, opcode)
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_87
node _T_1008 = eq(io.in.a.bits.param, param)
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(_T_1008, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1008, UInt<1>(0h1), "") : assert_88
node _T_1012 = eq(io.in.a.bits.size, size)
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_89
node _T_1016 = eq(io.in.a.bits.source, source)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_90
node _T_1020 = eq(io.in.a.bits.address, address)
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_91
node _T_1024 = and(io.in.a.ready, io.in.a.valid)
node _T_1025 = and(_T_1024, a_first)
when _T_1025 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1026 = eq(d_first, UInt<1>(0h0))
node _T_1027 = and(io.in.d.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_92
node _T_1032 = eq(io.in.d.bits.param, param_1)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_93
node _T_1036 = eq(io.in.d.bits.size, size_1)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_94
node _T_1040 = eq(io.in.d.bits.source, source_1)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_95
node _T_1044 = eq(io.in.d.bits.sink, sink)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_96
node _T_1048 = eq(io.in.d.bits.denied, denied)
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_97
node _T_1052 = and(io.in.d.ready, io.in.d.valid)
node _T_1053 = and(_T_1052, d_first)
when _T_1053 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1054 = and(io.in.a.valid, a_first_1)
node _T_1055 = and(_T_1054, UInt<1>(0h1))
when _T_1055 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1056 = and(io.in.a.ready, io.in.a.valid)
node _T_1057 = and(_T_1056, a_first_1)
node _T_1058 = and(_T_1057, UInt<1>(0h1))
when _T_1058 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1059 = dshr(inflight, io.in.a.bits.source)
node _T_1060 = bits(_T_1059, 0, 0)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1065 = and(io.in.d.valid, d_first_1)
node _T_1066 = and(_T_1065, UInt<1>(0h1))
node _T_1067 = eq(d_release_ack, UInt<1>(0h0))
node _T_1068 = and(_T_1066, _T_1067)
when _T_1068 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1069 = and(io.in.d.ready, io.in.d.valid)
node _T_1070 = and(_T_1069, d_first_1)
node _T_1071 = and(_T_1070, UInt<1>(0h1))
node _T_1072 = eq(d_release_ack, UInt<1>(0h0))
node _T_1073 = and(_T_1071, _T_1072)
when _T_1073 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1074 = and(io.in.d.valid, d_first_1)
node _T_1075 = and(_T_1074, UInt<1>(0h1))
node _T_1076 = eq(d_release_ack, UInt<1>(0h0))
node _T_1077 = and(_T_1075, _T_1076)
when _T_1077 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1078 = dshr(inflight, io.in.d.bits.source)
node _T_1079 = bits(_T_1078, 0, 0)
node _T_1080 = or(_T_1079, same_cycle_resp)
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1084 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1085 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1086 = or(_T_1084, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_100
node _T_1090 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_101
else :
node _T_1094 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1095 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1096 = or(_T_1094, _T_1095)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_102
node _T_1100 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_103
node _T_1104 = and(io.in.d.valid, d_first_1)
node _T_1105 = and(_T_1104, a_first_1)
node _T_1106 = and(_T_1105, io.in.a.valid)
node _T_1107 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = eq(d_release_ack, UInt<1>(0h0))
node _T_1110 = and(_T_1108, _T_1109)
when _T_1110 :
node _T_1111 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1112 = or(_T_1111, io.in.a.ready)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_14
node _T_1116 = orr(inflight)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
node _T_1118 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1119 = or(_T_1117, _T_1118)
node _T_1120 = lt(watchdog, plusarg_reader.out)
node _T_1121 = or(_T_1119, _T_1120)
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1125 = and(io.in.a.ready, io.in.a.valid)
node _T_1126 = and(io.in.d.ready, io.in.d.valid)
node _T_1127 = or(_T_1125, _T_1126)
when _T_1127 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1128 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1129 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1130 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1131 = and(_T_1129, _T_1130)
node _T_1132 = and(_T_1128, _T_1131)
when _T_1132 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1133 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1134 = and(_T_1133, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1135 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1136 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1137 = and(_T_1135, _T_1136)
node _T_1138 = and(_T_1134, _T_1137)
when _T_1138 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1139 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1145 = and(io.in.d.valid, d_first_2)
node _T_1146 = and(_T_1145, UInt<1>(0h1))
node _T_1147 = and(_T_1146, d_release_ack_1)
when _T_1147 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1148 = and(io.in.d.ready, io.in.d.valid)
node _T_1149 = and(_T_1148, d_first_2)
node _T_1150 = and(_T_1149, UInt<1>(0h1))
node _T_1151 = and(_T_1150, d_release_ack_1)
when _T_1151 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1152 = and(io.in.d.valid, d_first_2)
node _T_1153 = and(_T_1152, UInt<1>(0h1))
node _T_1154 = and(_T_1153, d_release_ack_1)
when _T_1154 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1155 = dshr(inflight_1, io.in.d.bits.source)
node _T_1156 = bits(_T_1155, 0, 0)
node _T_1157 = or(_T_1156, same_cycle_resp_1)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1161 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_108
else :
node _T_1165 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_109
node _T_1169 = and(io.in.d.valid, d_first_2)
node _T_1170 = and(_T_1169, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1171 = and(_T_1170, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1172 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1173 = and(_T_1171, _T_1172)
node _T_1174 = and(_T_1173, d_release_ack_1)
node _T_1175 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1176 = and(_T_1174, _T_1175)
when _T_1176 :
node _T_1177 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1178 = or(_T_1177, _WIRE_27.ready)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_15
node _T_1182 = orr(inflight_1)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
node _T_1184 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1185 = or(_T_1183, _T_1184)
node _T_1186 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1187 = or(_T_1185, _T_1186)
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1191 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1192 = and(io.in.d.ready, io.in.d.valid)
node _T_1193 = or(_T_1191, _T_1192)
when _T_1193 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLBFromNoC_9 :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<45>, clock
node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0))
node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T)
node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready)
connect io.flit.ready, _io_flit_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_address_WIRE : UInt<29>
connect _protocol_bits_address_WIRE, const
connect protocol.bits.address, _protocol_bits_address_WIRE
node _T = shr(const, 29)
wire _protocol_bits_source_WIRE : UInt<7>
connect _protocol_bits_source_WIRE, _T
connect protocol.bits.source, _protocol_bits_source_WIRE
node _T_1 = shr(_T, 7)
wire _protocol_bits_size_WIRE : UInt<4>
connect _protocol_bits_size_WIRE, _T_1
connect protocol.bits.size, _protocol_bits_size_WIRE
node _T_2 = shr(_T_1, 4)
wire _protocol_bits_param_WIRE : UInt<2>
connect _protocol_bits_param_WIRE, _T_2
connect protocol.bits.param, _protocol_bits_param_WIRE
node _T_3 = shr(_T_2, 2)
wire _protocol_bits_opcode_WIRE : UInt<3>
connect _protocol_bits_opcode_WIRE, _T_3
connect protocol.bits.opcode, _protocol_bits_opcode_WIRE
node _T_4 = shr(_T_3, 3)
wire _protocol_bits_corrupt_WIRE : UInt<1>
connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload
connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE
node _T_5 = shr(io.flit.bits.payload, 1)
wire _protocol_bits_data_WIRE : UInt<64>
connect _protocol_bits_data_WIRE, _T_5
connect protocol.bits.data, _protocol_bits_data_WIRE
node _T_6 = shr(_T_5, 64)
wire _protocol_bits_mask_WIRE : UInt<8>
connect _protocol_bits_mask_WIRE, _T_6
connect protocol.bits.mask, _protocol_bits_mask_WIRE
node _T_7 = shr(_T_6, 8)
node _T_8 = and(io.flit.ready, io.flit.valid)
node _T_9 = and(_T_8, io.flit.bits.head)
when _T_9 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.flit.bits.payload
node _T_10 = and(io.flit.ready, io.flit.valid)
node _T_11 = and(_T_10, io.flit.bits.tail)
when _T_11 :
connect is_const, UInt<1>(0h1)
connect io.protocol, protocol
node _io_protocol_bits_source_T = bits(protocol.bits.source, 6, 0)
connect io.protocol.bits.source, _io_protocol_bits_source_T
when io.flit.bits.head :
node _io_protocol_bits_mask_T = not(UInt<8>(0h0))
connect io.protocol.bits.mask, _io_protocol_bits_mask_T | module TLBFromNoC_9( // @[TilelinkAdapters.scala:145:7]
input clock, // @[TilelinkAdapters.scala:145:7]
input reset, // @[TilelinkAdapters.scala:145:7]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail; // @[TilelinkAdapters.scala:68:25, :71:{30,33}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:145:7]
if (reset) // @[TilelinkAdapters.scala:145:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :145:7]
else // @[TilelinkAdapters.scala:145:7]
is_const <= _GEN & io_flit_bits_tail | ~(_GEN & io_flit_bits_head) & is_const; // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RegisterFileSynthesizable :
input clock : Clock
input reset : Reset
output io : { read_ports : { flip addr : UInt<7>, data : UInt<65>}[3], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<65>}}[2]}
cmem regfile : UInt<65> [96]
wire read_data : UInt<65>[3]
reg read_addrs_0 : UInt, clock
connect read_addrs_0, io.read_ports[0].addr
reg read_addrs_1 : UInt, clock
connect read_addrs_1, io.read_ports[1].addr
reg read_addrs_2 : UInt, clock
connect read_addrs_2, io.read_ports[2].addr
node _read_data_0_T = or(read_addrs_0, UInt<7>(0h0))
node _read_data_0_T_1 = bits(_read_data_0_T, 6, 0)
infer mport read_data_0_MPORT = regfile[_read_data_0_T_1], clock
connect read_data[0], read_data_0_MPORT
node _read_data_1_T = or(read_addrs_1, UInt<7>(0h0))
node _read_data_1_T_1 = bits(_read_data_1_T, 6, 0)
infer mport read_data_1_MPORT = regfile[_read_data_1_T_1], clock
connect read_data[1], read_data_1_MPORT
node _read_data_2_T = or(read_addrs_2, UInt<7>(0h0))
node _read_data_2_T_1 = bits(_read_data_2_T, 6, 0)
infer mport read_data_2_MPORT = regfile[_read_data_2_T_1], clock
connect read_data[2], read_data_2_MPORT
connect io.read_ports[0].data, read_data[0]
connect io.read_ports[1].data, read_data[1]
connect io.read_ports[2].data, read_data[2]
when io.write_ports[0].valid :
infer mport MPORT = regfile[io.write_ports[0].bits.addr], clock
connect MPORT, io.write_ports[0].bits.data
when io.write_ports[1].valid :
infer mport MPORT_1 = regfile[io.write_ports[1].bits.addr], clock
connect MPORT_1, io.write_ports[1].bits.data
node _T = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr)
node _T_4 = or(_T_2, _T_3)
node _T_5 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0))
node _T_6 = or(_T_4, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert | module RegisterFileSynthesizable( // @[regfile.scala:106:7]
input clock, // @[regfile.scala:106:7]
input reset, // @[regfile.scala:106:7]
input [6:0] io_read_ports_0_addr, // @[regfile.scala:82:14]
output [64:0] io_read_ports_0_data, // @[regfile.scala:82:14]
input [6:0] io_read_ports_1_addr, // @[regfile.scala:82:14]
output [64:0] io_read_ports_1_data, // @[regfile.scala:82:14]
input [6:0] io_read_ports_2_addr, // @[regfile.scala:82:14]
output [64:0] io_read_ports_2_data, // @[regfile.scala:82:14]
input io_write_ports_0_valid, // @[regfile.scala:82:14]
input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:82:14]
input [64:0] io_write_ports_0_bits_data, // @[regfile.scala:82:14]
input io_write_ports_1_valid, // @[regfile.scala:82:14]
input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:82:14]
input [64:0] io_write_ports_1_bits_data // @[regfile.scala:82:14]
);
wire [6:0] io_read_ports_0_addr_0 = io_read_ports_0_addr; // @[regfile.scala:106:7]
wire [6:0] io_read_ports_1_addr_0 = io_read_ports_1_addr; // @[regfile.scala:106:7]
wire [6:0] io_read_ports_2_addr_0 = io_read_ports_2_addr; // @[regfile.scala:106:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:106:7]
wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:106:7]
wire [64:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:106:7]
wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:106:7]
wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:106:7]
wire [64:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:106:7]
wire [64:0] read_data_0; // @[regfile.scala:122:23]
wire [64:0] read_data_1; // @[regfile.scala:122:23]
wire [64:0] read_data_2; // @[regfile.scala:122:23]
wire [64:0] io_read_ports_0_data_0; // @[regfile.scala:106:7]
wire [64:0] io_read_ports_1_data_0; // @[regfile.scala:106:7]
wire [64:0] io_read_ports_2_data_0; // @[regfile.scala:106:7]
assign io_read_ports_0_data_0 = read_data_0; // @[regfile.scala:106:7, :122:23]
assign io_read_ports_1_data_0 = read_data_1; // @[regfile.scala:106:7, :122:23]
assign io_read_ports_2_data_0 = read_data_2; // @[regfile.scala:106:7, :122:23]
reg [6:0] read_addrs_0; // @[regfile.scala:125:50]
wire [6:0] _read_data_0_T = read_addrs_0; // @[regfile.scala:125:50, :128:28]
reg [6:0] read_addrs_1; // @[regfile.scala:125:50]
wire [6:0] _read_data_1_T = read_addrs_1; // @[regfile.scala:125:50, :128:28]
reg [6:0] read_addrs_2; // @[regfile.scala:125:50]
wire [6:0] _read_data_2_T = read_addrs_2; // @[regfile.scala:125:50, :128:28]
wire [6:0] _read_data_0_T_1 = _read_data_0_T; // @[regfile.scala:128:28]
wire [6:0] _read_data_1_T_1 = _read_data_1_T; // @[regfile.scala:128:28]
wire [6:0] _read_data_2_T_1 = _read_data_2_T; // @[regfile.scala:128:28] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_67 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0)
node _source_ok_T_27 = shr(io.in.a.bits.source, 4)
node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1))
node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf))
node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0)
node _source_ok_T_33 = shr(io.in.a.bits.source, 4)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<5>(0h10))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<5>(0h11))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<5>(0h12))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<5>(0h13))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_80 = shr(io.in.a.bits.source, 4)
node _T_81 = eq(_T_80, UInt<1>(0h1))
node _T_82 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_83 = and(_T_81, _T_82)
node _T_84 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_93 = shr(io.in.a.bits.source, 4)
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_96 = and(_T_94, _T_95)
node _T_97 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_98 = and(_T_96, _T_97)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_71)
node _T_127 = and(_T_126, _T_79)
node _T_128 = and(_T_127, _T_92)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<5>(0h10))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<5>(0h11))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<5>(0h12))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<5>(0h13))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_166 = shr(io.in.a.bits.source, 4)
node _T_167 = eq(_T_166, UInt<1>(0h1))
node _T_168 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_169 = and(_T_167, _T_168)
node _T_170 = leq(uncommonBits_10, UInt<4>(0hf))
node _T_171 = and(_T_169, _T_170)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_172 = shr(io.in.a.bits.source, 4)
node _T_173 = eq(_T_172, UInt<1>(0h0))
node _T_174 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_175 = and(_T_173, _T_174)
node _T_176 = leq(uncommonBits_11, UInt<4>(0hf))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_164)
node _T_185 = or(_T_184, _T_165)
node _T_186 = or(_T_185, _T_171)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = and(_T_192, _T_197)
node _T_199 = or(UInt<1>(0h0), _T_198)
node _T_200 = and(_T_191, _T_199)
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_200, UInt<1>(0h1), "") : assert_2
node _T_204 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<5>(0h10))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<5>(0h11))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<5>(0h12))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<5>(0h13))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_231 = shr(io.in.a.bits.source, 4)
node _T_232 = eq(_T_231, UInt<1>(0h1))
node _T_233 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_234 = and(_T_232, _T_233)
node _T_235 = leq(uncommonBits_16, UInt<4>(0hf))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_237 = shr(io.in.a.bits.source, 4)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_17, UInt<4>(0hf))
node _T_242 = and(_T_240, _T_241)
node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_204
connect _WIRE[1], _T_210
connect _WIRE[2], _T_216
connect _WIRE[3], _T_222
connect _WIRE[4], _T_228
connect _WIRE[5], _T_229
connect _WIRE[6], _T_230
connect _WIRE[7], _T_236
connect _WIRE[8], _T_242
connect _WIRE[9], _T_243
connect _WIRE[10], _T_244
node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[5], _T_245, UInt<1>(0h0))
node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = or(_T_246, _T_247)
node _T_258 = or(_T_257, _T_248)
node _T_259 = or(_T_258, _T_249)
node _T_260 = or(_T_259, _T_250)
node _T_261 = or(_T_260, _T_251)
node _T_262 = or(_T_261, _T_252)
node _T_263 = or(_T_262, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_266
node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_269 = and(_T_267, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_WIRE_1, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_278, UInt<1>(0h1), "") : assert_3
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_285, UInt<1>(0h1), "") : assert_5
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(is_aligned, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_292, UInt<1>(0h1), "") : assert_7
node _T_296 = not(io.in.a.bits.mask)
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_297, UInt<1>(0h1), "") : assert_8
node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_301, UInt<1>(0h1), "") : assert_9
node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_305 :
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<5>(0h10))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_316 = shr(io.in.a.bits.source, 2)
node _T_317 = eq(_T_316, UInt<5>(0h11))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<5>(0h12))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<5>(0h13))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0)
node _T_336 = shr(io.in.a.bits.source, 4)
node _T_337 = eq(_T_336, UInt<1>(0h1))
node _T_338 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_339 = and(_T_337, _T_338)
node _T_340 = leq(uncommonBits_22, UInt<4>(0hf))
node _T_341 = and(_T_339, _T_340)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0)
node _T_342 = shr(io.in.a.bits.source, 4)
node _T_343 = eq(_T_342, UInt<1>(0h0))
node _T_344 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_345 = and(_T_343, _T_344)
node _T_346 = leq(uncommonBits_23, UInt<4>(0hf))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_350 = or(_T_309, _T_315)
node _T_351 = or(_T_350, _T_321)
node _T_352 = or(_T_351, _T_327)
node _T_353 = or(_T_352, _T_333)
node _T_354 = or(_T_353, _T_334)
node _T_355 = or(_T_354, _T_335)
node _T_356 = or(_T_355, _T_341)
node _T_357 = or(_T_356, _T_347)
node _T_358 = or(_T_357, _T_348)
node _T_359 = or(_T_358, _T_349)
node _T_360 = and(_T_308, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = and(_T_362, _T_367)
node _T_369 = or(UInt<1>(0h0), _T_368)
node _T_370 = and(_T_361, _T_369)
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_370, UInt<1>(0h1), "") : assert_10
node _T_374 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<5>(0h10))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<5>(0h11))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<5>(0h12))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<5>(0h13))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0)
node _T_401 = shr(io.in.a.bits.source, 4)
node _T_402 = eq(_T_401, UInt<1>(0h1))
node _T_403 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_404 = and(_T_402, _T_403)
node _T_405 = leq(uncommonBits_28, UInt<4>(0hf))
node _T_406 = and(_T_404, _T_405)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0)
node _T_407 = shr(io.in.a.bits.source, 4)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_410 = and(_T_408, _T_409)
node _T_411 = leq(uncommonBits_29, UInt<4>(0hf))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_374
connect _WIRE_2[1], _T_380
connect _WIRE_2[2], _T_386
connect _WIRE_2[3], _T_392
connect _WIRE_2[4], _T_398
connect _WIRE_2[5], _T_399
connect _WIRE_2[6], _T_400
connect _WIRE_2[7], _T_406
connect _WIRE_2[8], _T_412
connect _WIRE_2[9], _T_413
connect _WIRE_2[10], _T_414
node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE_2[5], _T_415, UInt<1>(0h0))
node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = or(_T_416, _T_417)
node _T_428 = or(_T_427, _T_418)
node _T_429 = or(_T_428, _T_419)
node _T_430 = or(_T_429, _T_420)
node _T_431 = or(_T_430, _T_421)
node _T_432 = or(_T_431, _T_422)
node _T_433 = or(_T_432, _T_423)
node _T_434 = or(_T_433, _T_424)
node _T_435 = or(_T_434, _T_425)
node _T_436 = or(_T_435, _T_426)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_436
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = and(_WIRE_3, _T_447)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_448, UInt<1>(0h1), "") : assert_11
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(source_ok, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_T_455, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_455, UInt<1>(0h1), "") : assert_13
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(is_aligned, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_462, UInt<1>(0h1), "") : assert_15
node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_466, UInt<1>(0h1), "") : assert_16
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_471, UInt<1>(0h1), "") : assert_17
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_475, UInt<1>(0h1), "") : assert_18
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<5>(0h10))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<5>(0h11))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<5>(0h12))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<5>(0h13))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0)
node _T_510 = shr(io.in.a.bits.source, 4)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_34, UInt<4>(0hf))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0)
node _T_516 = shr(io.in.a.bits.source, 4)
node _T_517 = eq(_T_516, UInt<1>(0h0))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_35, UInt<4>(0hf))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_524 = or(_T_483, _T_489)
node _T_525 = or(_T_524, _T_495)
node _T_526 = or(_T_525, _T_501)
node _T_527 = or(_T_526, _T_507)
node _T_528 = or(_T_527, _T_508)
node _T_529 = or(_T_528, _T_509)
node _T_530 = or(_T_529, _T_515)
node _T_531 = or(_T_530, _T_521)
node _T_532 = or(_T_531, _T_522)
node _T_533 = or(_T_532, _T_523)
node _T_534 = and(_T_482, _T_533)
node _T_535 = or(UInt<1>(0h0), _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_535, UInt<1>(0h1), "") : assert_19
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<13>(0h1000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = and(_T_542, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_549, UInt<1>(0h1), "") : assert_20
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(source_ok, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(is_aligned, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_559, UInt<1>(0h1), "") : assert_23
node _T_563 = eq(io.in.a.bits.mask, mask)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_563, UInt<1>(0h1), "") : assert_24
node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_567, UInt<1>(0h1), "") : assert_25
node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_571 :
node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<5>(0h10))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<5>(0h11))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_588 = shr(io.in.a.bits.source, 2)
node _T_589 = eq(_T_588, UInt<5>(0h12))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<5>(0h13))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0)
node _T_602 = shr(io.in.a.bits.source, 4)
node _T_603 = eq(_T_602, UInt<1>(0h1))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_40, UInt<4>(0hf))
node _T_607 = and(_T_605, _T_606)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0)
node _T_608 = shr(io.in.a.bits.source, 4)
node _T_609 = eq(_T_608, UInt<1>(0h0))
node _T_610 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_611 = and(_T_609, _T_610)
node _T_612 = leq(uncommonBits_41, UInt<4>(0hf))
node _T_613 = and(_T_611, _T_612)
node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_616 = or(_T_575, _T_581)
node _T_617 = or(_T_616, _T_587)
node _T_618 = or(_T_617, _T_593)
node _T_619 = or(_T_618, _T_599)
node _T_620 = or(_T_619, _T_600)
node _T_621 = or(_T_620, _T_601)
node _T_622 = or(_T_621, _T_607)
node _T_623 = or(_T_622, _T_613)
node _T_624 = or(_T_623, _T_614)
node _T_625 = or(_T_624, _T_615)
node _T_626 = and(_T_574, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_630 = and(_T_628, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_633 = cvt(_T_632)
node _T_634 = and(_T_633, asSInt(UInt<13>(0h1000)))
node _T_635 = asSInt(_T_634)
node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0)))
node _T_637 = and(_T_631, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = and(_T_627, _T_638)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_639, UInt<1>(0h1), "") : assert_26
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(source_ok, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(is_aligned, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_649, UInt<1>(0h1), "") : assert_29
node _T_653 = eq(io.in.a.bits.mask, mask)
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_653, UInt<1>(0h1), "") : assert_30
node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_657 :
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<5>(0h10))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<5>(0h11))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_674 = shr(io.in.a.bits.source, 2)
node _T_675 = eq(_T_674, UInt<5>(0h12))
node _T_676 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_677 = and(_T_675, _T_676)
node _T_678 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_679 = and(_T_677, _T_678)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_680 = shr(io.in.a.bits.source, 2)
node _T_681 = eq(_T_680, UInt<5>(0h13))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_685 = and(_T_683, _T_684)
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0)
node _T_688 = shr(io.in.a.bits.source, 4)
node _T_689 = eq(_T_688, UInt<1>(0h1))
node _T_690 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_691 = and(_T_689, _T_690)
node _T_692 = leq(uncommonBits_46, UInt<4>(0hf))
node _T_693 = and(_T_691, _T_692)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0)
node _T_694 = shr(io.in.a.bits.source, 4)
node _T_695 = eq(_T_694, UInt<1>(0h0))
node _T_696 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_697 = and(_T_695, _T_696)
node _T_698 = leq(uncommonBits_47, UInt<4>(0hf))
node _T_699 = and(_T_697, _T_698)
node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_701 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_702 = or(_T_661, _T_667)
node _T_703 = or(_T_702, _T_673)
node _T_704 = or(_T_703, _T_679)
node _T_705 = or(_T_704, _T_685)
node _T_706 = or(_T_705, _T_686)
node _T_707 = or(_T_706, _T_687)
node _T_708 = or(_T_707, _T_693)
node _T_709 = or(_T_708, _T_699)
node _T_710 = or(_T_709, _T_700)
node _T_711 = or(_T_710, _T_701)
node _T_712 = and(_T_660, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_716 = and(_T_714, _T_715)
node _T_717 = or(UInt<1>(0h0), _T_716)
node _T_718 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = and(_T_713, _T_724)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_725, UInt<1>(0h1), "") : assert_31
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(source_ok, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(is_aligned, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_735, UInt<1>(0h1), "") : assert_34
node _T_739 = not(mask)
node _T_740 = and(io.in.a.bits.mask, _T_739)
node _T_741 = eq(_T_740, UInt<1>(0h0))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_741, UInt<1>(0h1), "") : assert_35
node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_745 :
node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<5>(0h10))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<5>(0h11))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<5>(0h12))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_768 = shr(io.in.a.bits.source, 2)
node _T_769 = eq(_T_768, UInt<5>(0h13))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_773 = and(_T_771, _T_772)
node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0)
node _T_776 = shr(io.in.a.bits.source, 4)
node _T_777 = eq(_T_776, UInt<1>(0h1))
node _T_778 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_779 = and(_T_777, _T_778)
node _T_780 = leq(uncommonBits_52, UInt<4>(0hf))
node _T_781 = and(_T_779, _T_780)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0)
node _T_782 = shr(io.in.a.bits.source, 4)
node _T_783 = eq(_T_782, UInt<1>(0h0))
node _T_784 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_785 = and(_T_783, _T_784)
node _T_786 = leq(uncommonBits_53, UInt<4>(0hf))
node _T_787 = and(_T_785, _T_786)
node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_789 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_790 = or(_T_749, _T_755)
node _T_791 = or(_T_790, _T_761)
node _T_792 = or(_T_791, _T_767)
node _T_793 = or(_T_792, _T_773)
node _T_794 = or(_T_793, _T_774)
node _T_795 = or(_T_794, _T_775)
node _T_796 = or(_T_795, _T_781)
node _T_797 = or(_T_796, _T_787)
node _T_798 = or(_T_797, _T_788)
node _T_799 = or(_T_798, _T_789)
node _T_800 = and(_T_748, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = or(UInt<1>(0h0), _T_808)
node _T_810 = and(_T_801, _T_809)
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(_T_810, UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_810, UInt<1>(0h1), "") : assert_36
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(source_ok, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(is_aligned, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_820, UInt<1>(0h1), "") : assert_39
node _T_824 = eq(io.in.a.bits.mask, mask)
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(_T_824, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_824, UInt<1>(0h1), "") : assert_40
node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_828 :
node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_831 = and(_T_829, _T_830)
node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<5>(0h10))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<5>(0h11))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<5>(0h12))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<5>(0h13))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0)
node _T_859 = shr(io.in.a.bits.source, 4)
node _T_860 = eq(_T_859, UInt<1>(0h1))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_58, UInt<4>(0hf))
node _T_864 = and(_T_862, _T_863)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0)
node _T_865 = shr(io.in.a.bits.source, 4)
node _T_866 = eq(_T_865, UInt<1>(0h0))
node _T_867 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_868 = and(_T_866, _T_867)
node _T_869 = leq(uncommonBits_59, UInt<4>(0hf))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_872 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_873 = or(_T_832, _T_838)
node _T_874 = or(_T_873, _T_844)
node _T_875 = or(_T_874, _T_850)
node _T_876 = or(_T_875, _T_856)
node _T_877 = or(_T_876, _T_857)
node _T_878 = or(_T_877, _T_858)
node _T_879 = or(_T_878, _T_864)
node _T_880 = or(_T_879, _T_870)
node _T_881 = or(_T_880, _T_871)
node _T_882 = or(_T_881, _T_872)
node _T_883 = and(_T_831, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_883)
node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_886 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = and(_T_885, _T_890)
node _T_892 = or(UInt<1>(0h0), _T_891)
node _T_893 = and(_T_884, _T_892)
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_893, UInt<1>(0h1), "") : assert_41
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(source_ok, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(is_aligned, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_903, UInt<1>(0h1), "") : assert_44
node _T_907 = eq(io.in.a.bits.mask, mask)
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_907, UInt<1>(0h1), "") : assert_45
node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_911 :
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_916 = shr(io.in.a.bits.source, 2)
node _T_917 = eq(_T_916, UInt<5>(0h10))
node _T_918 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_919 = and(_T_917, _T_918)
node _T_920 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_921 = and(_T_919, _T_920)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_922 = shr(io.in.a.bits.source, 2)
node _T_923 = eq(_T_922, UInt<5>(0h11))
node _T_924 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_925 = and(_T_923, _T_924)
node _T_926 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_927 = and(_T_925, _T_926)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_928 = shr(io.in.a.bits.source, 2)
node _T_929 = eq(_T_928, UInt<5>(0h12))
node _T_930 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_931 = and(_T_929, _T_930)
node _T_932 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_933 = and(_T_931, _T_932)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_934 = shr(io.in.a.bits.source, 2)
node _T_935 = eq(_T_934, UInt<5>(0h13))
node _T_936 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_937 = and(_T_935, _T_936)
node _T_938 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_939 = and(_T_937, _T_938)
node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0)
node _T_942 = shr(io.in.a.bits.source, 4)
node _T_943 = eq(_T_942, UInt<1>(0h1))
node _T_944 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_945 = and(_T_943, _T_944)
node _T_946 = leq(uncommonBits_64, UInt<4>(0hf))
node _T_947 = and(_T_945, _T_946)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0)
node _T_948 = shr(io.in.a.bits.source, 4)
node _T_949 = eq(_T_948, UInt<1>(0h0))
node _T_950 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_951 = and(_T_949, _T_950)
node _T_952 = leq(uncommonBits_65, UInt<4>(0hf))
node _T_953 = and(_T_951, _T_952)
node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_955 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_956 = or(_T_915, _T_921)
node _T_957 = or(_T_956, _T_927)
node _T_958 = or(_T_957, _T_933)
node _T_959 = or(_T_958, _T_939)
node _T_960 = or(_T_959, _T_940)
node _T_961 = or(_T_960, _T_941)
node _T_962 = or(_T_961, _T_947)
node _T_963 = or(_T_962, _T_953)
node _T_964 = or(_T_963, _T_954)
node _T_965 = or(_T_964, _T_955)
node _T_966 = and(_T_914, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_969 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_970 = cvt(_T_969)
node _T_971 = and(_T_970, asSInt(UInt<13>(0h1000)))
node _T_972 = asSInt(_T_971)
node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0)))
node _T_974 = and(_T_968, _T_973)
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = and(_T_967, _T_975)
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_976, UInt<1>(0h1), "") : assert_46
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(is_aligned, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_986, UInt<1>(0h1), "") : assert_49
node _T_990 = eq(io.in.a.bits.mask, mask)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_990, UInt<1>(0h1), "") : assert_50
node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_994, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_998, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 4)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0)
node _source_ok_T_83 = shr(io.in.d.bits.source, 4)
node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0))
node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf))
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_75
connect _source_ok_WIRE_1[6], _source_ok_T_76
connect _source_ok_WIRE_1[7], _source_ok_T_82
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_54
node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_55
node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_56
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_57
node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1022 :
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(source_ok_1, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(sink_ok, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(_T_1029, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1029, UInt<1>(0h1), "") : assert_60
node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_61
node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_62
node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_63
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_64
node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1050 :
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(source_ok_1, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(sink_ok, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_67
node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_68
node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_69
node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1070 = or(_T_1069, io.in.d.bits.corrupt)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_70
node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1075 = or(UInt<1>(0h0), _T_1074)
node _T_1076 = asUInt(reset)
node _T_1077 = eq(_T_1076, UInt<1>(0h0))
when _T_1077 :
node _T_1078 = eq(_T_1075, UInt<1>(0h0))
when _T_1078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1075, UInt<1>(0h1), "") : assert_71
node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(source_ok_1, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1084 = asUInt(reset)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(_T_1083, UInt<1>(0h0))
when _T_1086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1083, UInt<1>(0h1), "") : assert_73
node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(_T_1087, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1087, UInt<1>(0h1), "") : assert_74
node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1092 = or(UInt<1>(0h0), _T_1091)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_75
node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1096 :
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(source_ok_1, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_77
node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1105 = or(_T_1104, io.in.d.bits.corrupt)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_78
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h0), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_79
node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_81
node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_82
node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1127 = or(UInt<1>(0h0), _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(_T_1135, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1143 = eq(a_first, UInt<1>(0h0))
node _T_1144 = and(io.in.a.valid, _T_1143)
when _T_1144 :
node _T_1145 = eq(io.in.a.bits.opcode, opcode)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_87
node _T_1149 = eq(io.in.a.bits.param, param)
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_88
node _T_1153 = eq(io.in.a.bits.size, size)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_89
node _T_1157 = eq(io.in.a.bits.source, source)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_90
node _T_1161 = eq(io.in.a.bits.address, address)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_91
node _T_1165 = and(io.in.a.ready, io.in.a.valid)
node _T_1166 = and(_T_1165, a_first)
when _T_1166 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1167 = eq(d_first, UInt<1>(0h0))
node _T_1168 = and(io.in.d.valid, _T_1167)
when _T_1168 :
node _T_1169 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_92
node _T_1173 = eq(io.in.d.bits.param, param_1)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_93
node _T_1177 = eq(io.in.d.bits.size, size_1)
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_94
node _T_1181 = eq(io.in.d.bits.source, source_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_95
node _T_1185 = eq(io.in.d.bits.sink, sink)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_96
node _T_1189 = eq(io.in.d.bits.denied, denied)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_97
node _T_1193 = and(io.in.d.ready, io.in.d.valid)
node _T_1194 = and(_T_1193, d_first)
when _T_1194 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1195 = and(io.in.a.valid, a_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
when _T_1196 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1197 = and(io.in.a.ready, io.in.a.valid)
node _T_1198 = and(_T_1197, a_first_1)
node _T_1199 = and(_T_1198, UInt<1>(0h1))
when _T_1199 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1200 = dshr(inflight, io.in.a.bits.source)
node _T_1201 = bits(_T_1200, 0, 0)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1206 = and(io.in.d.valid, d_first_1)
node _T_1207 = and(_T_1206, UInt<1>(0h1))
node _T_1208 = eq(d_release_ack, UInt<1>(0h0))
node _T_1209 = and(_T_1207, _T_1208)
when _T_1209 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1210 = and(io.in.d.ready, io.in.d.valid)
node _T_1211 = and(_T_1210, d_first_1)
node _T_1212 = and(_T_1211, UInt<1>(0h1))
node _T_1213 = eq(d_release_ack, UInt<1>(0h0))
node _T_1214 = and(_T_1212, _T_1213)
when _T_1214 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1215 = and(io.in.d.valid, d_first_1)
node _T_1216 = and(_T_1215, UInt<1>(0h1))
node _T_1217 = eq(d_release_ack, UInt<1>(0h0))
node _T_1218 = and(_T_1216, _T_1217)
when _T_1218 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1219 = dshr(inflight, io.in.d.bits.source)
node _T_1220 = bits(_T_1219, 0, 0)
node _T_1221 = or(_T_1220, same_cycle_resp)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1227 = or(_T_1225, _T_1226)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_100
node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_101
else :
node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1237 = or(_T_1235, _T_1236)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_102
node _T_1241 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_103
node _T_1245 = and(io.in.d.valid, d_first_1)
node _T_1246 = and(_T_1245, a_first_1)
node _T_1247 = and(_T_1246, io.in.a.valid)
node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1249 = and(_T_1247, _T_1248)
node _T_1250 = eq(d_release_ack, UInt<1>(0h0))
node _T_1251 = and(_T_1249, _T_1250)
when _T_1251 :
node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1253 = or(_T_1252, io.in.a.ready)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_138
node _T_1257 = orr(inflight)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
node _T_1259 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1260 = or(_T_1258, _T_1259)
node _T_1261 = lt(watchdog, plusarg_reader.out)
node _T_1262 = or(_T_1260, _T_1261)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1266 = and(io.in.a.ready, io.in.a.valid)
node _T_1267 = and(io.in.d.ready, io.in.d.valid)
node _T_1268 = or(_T_1266, _T_1267)
when _T_1268 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1269 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1270 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1271 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1272 = and(_T_1270, _T_1271)
node _T_1273 = and(_T_1269, _T_1272)
when _T_1273 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1274 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1275 = and(_T_1274, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1276 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1277 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1278 = and(_T_1276, _T_1277)
node _T_1279 = and(_T_1275, _T_1278)
when _T_1279 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1280 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1281 = bits(_T_1280, 0, 0)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1286 = and(io.in.d.valid, d_first_2)
node _T_1287 = and(_T_1286, UInt<1>(0h1))
node _T_1288 = and(_T_1287, d_release_ack_1)
when _T_1288 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1289 = and(io.in.d.ready, io.in.d.valid)
node _T_1290 = and(_T_1289, d_first_2)
node _T_1291 = and(_T_1290, UInt<1>(0h1))
node _T_1292 = and(_T_1291, d_release_ack_1)
when _T_1292 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1293 = and(io.in.d.valid, d_first_2)
node _T_1294 = and(_T_1293, UInt<1>(0h1))
node _T_1295 = and(_T_1294, d_release_ack_1)
when _T_1295 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1296 = dshr(inflight_1, io.in.d.bits.source)
node _T_1297 = bits(_T_1296, 0, 0)
node _T_1298 = or(_T_1297, same_cycle_resp_1)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1302 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_108
else :
node _T_1306 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_109
node _T_1310 = and(io.in.d.valid, d_first_2)
node _T_1311 = and(_T_1310, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1312 = and(_T_1311, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1313 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1314 = and(_T_1312, _T_1313)
node _T_1315 = and(_T_1314, d_release_ack_1)
node _T_1316 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1317 = and(_T_1315, _T_1316)
when _T_1317 :
node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1319 = or(_T_1318, _WIRE_27.ready)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_139
node _T_1323 = orr(inflight_1)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
node _T_1325 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1326 = or(_T_1324, _T_1325)
node _T_1327 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1328 = or(_T_1326, _T_1327)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1332 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1333 = and(io.in.d.ready, io.in.d.valid)
node _T_1334 = or(_T_1332, _T_1333)
when _T_1334 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_67( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1292 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_123
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_124
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_125 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 1
parameter FORMAT = "uart_tx=%d"
parameter WIDTH = 32
extmodule plusarg_reader_126 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "uart_tx_printf=%d"
parameter WIDTH = 32 | module TLMonitor_61( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ScratchpadBank :
output auto : { flip xbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst xbar of TLXbar_i1_o1_a28d64s3k1z3u
connect xbar.clock, childClock
connect xbar.reset, childReset
inst ram of TLRAM_ScratchpadBank
connect ram.clock, childClock
connect ram.reset, childReset
inst fragmenter of TLFragmenter_ScratchpadBank
connect fragmenter.clock, childClock
connect fragmenter.reset, childReset
inst buffer of TLBuffer_a28d64s3k1z3u_1
connect buffer.clock, childClock
connect buffer.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect buffer.auto.in, xbar.auto.anon_out
connect ram.auto.in, fragmenter.auto.anon_out
connect fragmenter.auto.anon_in, buffer.auto.out
connect clockNodeIn, auto.clock_in
connect xbar.auto.anon_in, auto.xbar_anon_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module ScratchpadBank( // @[ClockDomain.scala:14:9]
output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_xbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] xbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [27:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [6:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [27:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _ram_auto_in_a_ready; // @[Scratchpad.scala:33:25]
wire _ram_auto_in_d_valid; // @[Scratchpad.scala:33:25]
wire [2:0] _ram_auto_in_d_bits_opcode; // @[Scratchpad.scala:33:25]
wire [1:0] _ram_auto_in_d_bits_size; // @[Scratchpad.scala:33:25]
wire [6:0] _ram_auto_in_d_bits_source; // @[Scratchpad.scala:33:25]
wire [63:0] _ram_auto_in_d_bits_data; // @[Scratchpad.scala:33:25]
wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [27:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire [1:0] xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__addressC_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__addressC_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__requestCIO_T = 28'h0; // @[Parameters.scala:137:31]
wire [27:0] xbar__requestBOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__requestBOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsBO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__beatsBO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsCI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__beatsCI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__portsBIO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__portsBIO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar_portsBIO_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__portsCOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__portsCOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar_portsCOI_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__requestBOI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__requestBOI_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] xbar_requestBOI_uncommonBits = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__portsBIO_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsBIO_filtered_0_bits_source = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_source = 3'h0; // @[Xbar.scala:352:24]
wire [7:0] xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [5:0] xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire [28:0] xbar__requestAIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestAIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_1 = 29'h0; // @[Parameters.scala:137:41]
wire [28:0] xbar__requestCIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire xbar_auto_anon_in_a_valid = auto_xbar_anon_in_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_opcode = auto_xbar_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_param = auto_xbar_anon_in_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_size = auto_xbar_anon_in_a_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_source = auto_xbar_anon_in_a_bits_source_0; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_in_a_bits_address = auto_xbar_anon_in_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_a_bits_mask = auto_xbar_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_a_bits_data = auto_xbar_anon_in_a_bits_data_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_a_bits_corrupt = auto_xbar_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_ready = auto_xbar_anon_in_d_ready_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_a_ready_0 = xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_bits_corrupt = xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_valid_0 = xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_opcode_0 = xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_param_0 = xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_size_0 = xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_source_0 = xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_sink_0 = xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_denied_0 = xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_data_0 = xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_corrupt_0 = xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_corrupt = xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire xbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9]
wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [2:0] xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [27:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire xbar_in_0_a_bits_corrupt = xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire xbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [27:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [27:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsAOI_filtered_0_bits_corrupt = xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_corrupt = xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [2:0] xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [28:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [2:0] xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] xbar__beatsAI_decode_T = 13'h3F << xbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] xbar__beatsDO_decode_T = 13'h3F << xbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_corrupt = xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLRAM_ScratchpadBank ram ( // @[Scratchpad.scala:33:25]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_ram_auto_in_a_ready),
.auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_in_d_valid (_ram_auto_in_d_valid),
.auto_in_d_bits_opcode (_ram_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_ram_auto_in_d_bits_size),
.auto_in_d_bits_source (_ram_auto_in_d_bits_source),
.auto_in_d_bits_data (_ram_auto_in_d_bits_data)
); // @[Scratchpad.scala:33:25]
TLFragmenter_ScratchpadBank fragmenter ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (_ram_auto_in_a_ready), // @[Scratchpad.scala:33:25]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_ram_auto_in_d_valid), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_opcode (_ram_auto_in_d_bits_opcode), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_size (_ram_auto_in_d_bits_size), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_source (_ram_auto_in_d_bits_source), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_data (_ram_auto_in_d_bits_data) // @[Scratchpad.scala:33:25]
); // @[Fragmenter.scala:345:34]
TLBuffer_a28d64s3k1z3u_1 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (xbar_auto_anon_out_a_ready),
.auto_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9]
.auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9]
.auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9]
.auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9]
.auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9]
.auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9]
.auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9]
.auto_in_a_bits_corrupt (xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9]
.auto_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9]
.auto_in_d_valid (xbar_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt),
.auto_out_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34]
); // @[Buffer.scala:75:28]
assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_param = auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_sink = auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_denied = auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_corrupt = auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_8 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}}
wire _in_flight_WIRE : UInt<1>[10]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
connect _in_flight_WIRE[8], UInt<1>(0h0)
connect _in_flight_WIRE[9], UInt<1>(0h0)
regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(_T_12, _T_19)
node _T_35 = or(_T_34, _T_26)
node _T_36 = or(_T_35, _T_33)
node _T_37 = or(_T_5, _T_36)
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_37, UInt<1>(0h1), "") : assert_1
node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_43 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_46 = and(_T_44, _T_45)
node _T_47 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_50 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_55 = and(_T_53, _T_54)
node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_57 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_62 = and(_T_60, _T_61)
node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_64 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_65 = and(_T_63, _T_64)
node _T_66 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = or(_T_48, _T_55)
node _T_71 = or(_T_70, _T_62)
node _T_72 = or(_T_71, _T_69)
node _T_73 = or(_T_41, _T_72)
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_73, UInt<1>(0h1), "") : assert_2
node _T_77 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_78 = or(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_89 = and(_T_87, _T_88)
node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_126 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_133 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_140 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_173 = and(_T_171, _T_172)
node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_178 = and(_T_176, _T_177)
node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_180 = and(_T_178, _T_179)
node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_185 = and(_T_183, _T_184)
node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_187 = and(_T_185, _T_186)
node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_192 = and(_T_190, _T_191)
node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_194 = and(_T_192, _T_193)
node _T_195 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_196 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4))
node _T_199 = and(_T_197, _T_198)
node _T_200 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_201 = and(_T_199, _T_200)
node _T_202 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_203 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_204 = and(_T_202, _T_203)
node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_206 = and(_T_204, _T_205)
node _T_207 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_208 = and(_T_206, _T_207)
node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_210 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_211 = and(_T_209, _T_210)
node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_213 = and(_T_211, _T_212)
node _T_214 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_215 = and(_T_213, _T_214)
node _T_216 = or(_T_89, _T_96)
node _T_217 = or(_T_216, _T_103)
node _T_218 = or(_T_217, _T_110)
node _T_219 = or(_T_218, _T_117)
node _T_220 = or(_T_219, _T_124)
node _T_221 = or(_T_220, _T_131)
node _T_222 = or(_T_221, _T_138)
node _T_223 = or(_T_222, _T_145)
node _T_224 = or(_T_223, _T_152)
node _T_225 = or(_T_224, _T_159)
node _T_226 = or(_T_225, _T_166)
node _T_227 = or(_T_226, _T_173)
node _T_228 = or(_T_227, _T_180)
node _T_229 = or(_T_228, _T_187)
node _T_230 = or(_T_229, _T_194)
node _T_231 = or(_T_230, _T_201)
node _T_232 = or(_T_231, _T_208)
node _T_233 = or(_T_232, _T_215)
node _T_234 = or(_T_82, _T_233)
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_234, UInt<1>(0h1), "") : assert_4
node _T_238 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_239 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_240 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_241 = and(_T_239, _T_240)
node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_243 = and(_T_241, _T_242)
node _T_244 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_247 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_254 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_261 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_266 = and(_T_264, _T_265)
node _T_267 = or(_T_245, _T_252)
node _T_268 = or(_T_267, _T_259)
node _T_269 = or(_T_268, _T_266)
node _T_270 = or(_T_238, _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_270, UInt<1>(0h1), "") : assert_5
node _T_274 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_276 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_277 = and(_T_275, _T_276)
node _T_278 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_279 = and(_T_277, _T_278)
node _T_280 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_283 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_284 = and(_T_282, _T_283)
node _T_285 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_286 = and(_T_284, _T_285)
node _T_287 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_290 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_291 = and(_T_289, _T_290)
node _T_292 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_297 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_298 = and(_T_296, _T_297)
node _T_299 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_302 = and(_T_300, _T_301)
node _T_303 = or(_T_281, _T_288)
node _T_304 = or(_T_303, _T_295)
node _T_305 = or(_T_304, _T_302)
node _T_306 = or(_T_274, _T_305)
node _T_307 = asUInt(reset)
node _T_308 = eq(_T_307, UInt<1>(0h0))
when _T_308 :
node _T_309 = eq(_T_306, UInt<1>(0h0))
when _T_309 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_306, UInt<1>(0h1), "") : assert_6
node _T_310 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_311 = or(_T_310, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_311, UInt<1>(0h1), "") : assert_7
node _T_315 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_316 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_317 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_322 = and(_T_320, _T_321)
node _T_323 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_324 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_329 = and(_T_327, _T_328)
node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_331 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_332 = and(_T_330, _T_331)
node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_336 = and(_T_334, _T_335)
node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_338 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_339 = and(_T_337, _T_338)
node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_341 = and(_T_339, _T_340)
node _T_342 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_345 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_346 = and(_T_344, _T_345)
node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_348 = and(_T_346, _T_347)
node _T_349 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_352 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_353 = and(_T_351, _T_352)
node _T_354 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_355 = and(_T_353, _T_354)
node _T_356 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_359 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_364 = and(_T_362, _T_363)
node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_366 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_369 = and(_T_367, _T_368)
node _T_370 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_371 = and(_T_369, _T_370)
node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_373 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_374 = and(_T_372, _T_373)
node _T_375 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_376 = and(_T_374, _T_375)
node _T_377 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_380 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_381 = and(_T_379, _T_380)
node _T_382 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_383 = and(_T_381, _T_382)
node _T_384 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_385 = and(_T_383, _T_384)
node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_387 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_388 = and(_T_386, _T_387)
node _T_389 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_390 = and(_T_388, _T_389)
node _T_391 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_392 = and(_T_390, _T_391)
node _T_393 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_394 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_395 = and(_T_393, _T_394)
node _T_396 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_397 = and(_T_395, _T_396)
node _T_398 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_399 = and(_T_397, _T_398)
node _T_400 = or(_T_322, _T_329)
node _T_401 = or(_T_400, _T_336)
node _T_402 = or(_T_401, _T_343)
node _T_403 = or(_T_402, _T_350)
node _T_404 = or(_T_403, _T_357)
node _T_405 = or(_T_404, _T_364)
node _T_406 = or(_T_405, _T_371)
node _T_407 = or(_T_406, _T_378)
node _T_408 = or(_T_407, _T_385)
node _T_409 = or(_T_408, _T_392)
node _T_410 = or(_T_409, _T_399)
node _T_411 = or(_T_315, _T_410)
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_411, UInt<1>(0h1), "") : assert_8
node _T_415 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_417 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_418 = and(_T_416, _T_417)
node _T_419 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_420 = and(_T_418, _T_419)
node _T_421 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_424 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_425 = and(_T_423, _T_424)
node _T_426 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_427 = and(_T_425, _T_426)
node _T_428 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_431 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_432 = and(_T_430, _T_431)
node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_438 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_439 = and(_T_437, _T_438)
node _T_440 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_445 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_446 = and(_T_444, _T_445)
node _T_447 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_448 = and(_T_446, _T_447)
node _T_449 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_450 = and(_T_448, _T_449)
node _T_451 = or(_T_422, _T_429)
node _T_452 = or(_T_451, _T_436)
node _T_453 = or(_T_452, _T_443)
node _T_454 = or(_T_453, _T_450)
node _T_455 = or(_T_415, _T_454)
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_T_455, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9
assert(clock, _T_455, UInt<1>(0h1), "") : assert_9
node _T_459 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9))
node _T_460 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_461 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_462 = and(_T_460, _T_461)
node _T_463 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_464 = and(_T_462, _T_463)
node _T_465 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_466 = and(_T_464, _T_465)
node _T_467 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_468 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_469 = and(_T_467, _T_468)
node _T_470 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_475 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_476 = and(_T_474, _T_475)
node _T_477 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_482 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_483 = and(_T_481, _T_482)
node _T_484 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_485 = and(_T_483, _T_484)
node _T_486 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_489 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_490 = and(_T_488, _T_489)
node _T_491 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_492 = and(_T_490, _T_491)
node _T_493 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = or(_T_466, _T_473)
node _T_496 = or(_T_495, _T_480)
node _T_497 = or(_T_496, _T_487)
node _T_498 = or(_T_497, _T_494)
node _T_499 = or(_T_459, _T_498)
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10
assert(clock, _T_499, UInt<1>(0h1), "") : assert_10 | module NoCMonitor_8( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_10 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue2_EgressFlit_10
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19)
node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22)
node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25)
node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28)
node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31)
node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34)
node _q_io_enq_bits_ingress_id_T_36 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_37 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_38 = and(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37)
node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h14), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h10), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0ha), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h0), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0hc), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h16), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h12), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h4), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h6), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_48 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0he), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_49 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0h18), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_50 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0h8), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_51 = mux(_q_io_enq_bits_ingress_id_T_38, UInt<5>(0h2), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_39, _q_io_enq_bits_ingress_id_T_40)
node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_41)
node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_42)
node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_43)
node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_44)
node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_45)
node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_46)
node _q_io_enq_bits_ingress_id_T_59 = or(_q_io_enq_bits_ingress_id_T_58, _q_io_enq_bits_ingress_id_T_47)
node _q_io_enq_bits_ingress_id_T_60 = or(_q_io_enq_bits_ingress_id_T_59, _q_io_enq_bits_ingress_id_T_48)
node _q_io_enq_bits_ingress_id_T_61 = or(_q_io_enq_bits_ingress_id_T_60, _q_io_enq_bits_ingress_id_T_49)
node _q_io_enq_bits_ingress_id_T_62 = or(_q_io_enq_bits_ingress_id_T_61, _q_io_enq_bits_ingress_id_T_50)
node _q_io_enq_bits_ingress_id_T_63 = or(_q_io_enq_bits_ingress_id_T_62, _q_io_enq_bits_ingress_id_T_51)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_63
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_10( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_21 :
input clock : Clock
input reset : Reset
output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1]}, credit_alloc : { `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[4]}, switch_sel : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}}
inst arbs_0 of SwitchArbiter_70
connect arbs_0.clock, clock
connect arbs_0.reset, reset
inst arbs_1 of SwitchArbiter_71
connect arbs_1.clock, clock
connect arbs_1.reset, reset
inst arbs_2 of SwitchArbiter_72
connect arbs_2.clock, clock
connect arbs_2.reset, reset
connect arbs_0.io.out[0].ready, UInt<1>(0h1)
connect arbs_1.io.out[0].ready, UInt<1>(0h1)
connect arbs_2.io.out[0].ready, UInt<1>(0h1)
wire fires : UInt<1>[3]
node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_0_valid_T_3 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_2)
connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_3
connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid)
connect fires[0], _fires_0_T
node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0])
connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T
connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid)
connect fires[1], _fires_1_T
node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0])
connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T
connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid)
connect fires[2], _fires_2_T
node _io_req_0_0_ready_T = or(fires[0], fires[1])
node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2])
connect io.req.`0`[0].ready, _io_req_0_0_ready_T_1
wire fires_1 : UInt<1>[3]
node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_1_valid_T_3 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_2)
connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_3
connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid)
connect fires_1[0], _fires_0_T_1
node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0])
connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T
connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid)
connect fires_1[1], _fires_1_T_1
node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0])
connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T
connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid)
connect fires_1[2], _fires_2_T_1
node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1])
node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2])
connect io.req.`1`[0].ready, _io_req_1_0_ready_T_1
wire fires_2 : UInt<1>[3]
node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_2_valid_T_3 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_2)
connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_3
connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid)
connect fires_2[0], _fires_0_T_2
node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0])
connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T
connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid)
connect fires_2[1], _fires_1_T_2
node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0])
connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T
connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid)
connect fires_2[2], _fires_2_T_2
node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1])
node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2])
connect io.req.`2`[0].ready, _io_req_2_0_ready_T_1
node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0)
node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T)
node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2
node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1)
node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T)
node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2
node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2)
node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T)
node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2
node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0)
node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T)
node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2
node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1)
node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T)
node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2
node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2)
node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T)
node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2
node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0)
node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T)
node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2
node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1)
node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T)
node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2
node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2)
node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T)
node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0)
node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0])
when _T :
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail
node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1])
when _T_1 :
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail
node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2])
when _T_2 :
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail
node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3])
when _T_3 :
connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail
node _T_4 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0])
when _T_4 :
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail
node _T_5 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0])
when _T_5 :
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail | module SwitchAllocator_21( // @[SwitchAllocator.scala:64:7]
input clock, // @[SwitchAllocator.scala:64:7]
input reset, // @[SwitchAllocator.scala:64:7]
output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14]
);
wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45]
wire [2:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45]
wire [2:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45]
wire [2:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_0 | io_req_0_0_bits_vc_sel_0_1); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33]
wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33]
SwitchArbiter_70 arbs_0 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_0_io_in_0_ready),
.io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_out_0_valid (_arbs_0_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (_arbs_0_io_out_0_bits_vc_sel_0_0),
.io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1),
.io_out_0_bits_tail (/* unused */),
.io_chosen_oh_0 (_arbs_0_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_70 arbs_1 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_1_io_in_0_ready),
.io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_out_0_valid (_arbs_1_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail),
.io_chosen_oh_0 (_arbs_1_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_70 arbs_2 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_2_io_in_0_ready),
.io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_out_0_valid (_arbs_2_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail),
.io_chosen_oh_0 (_arbs_2_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid; // @[Decoupled.scala:51:35]
assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33]
assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]
assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33]
assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]
assign io_credit_alloc_0_0_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_96 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_96( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_12 :
input clock : Clock
input reset : Reset
output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]}
connect io.xcpt_if, UInt<1>(0h0)
connect io.xcpt_ld, UInt<1>(0h0)
connect io.xcpt_st, UInt<1>(0h0)
connect io.debug_if, UInt<1>(0h0)
connect io.debug_ld, UInt<1>(0h0)
connect io.debug_st, UInt<1>(0h0) | module BreakpointUnit_12( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_54 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h1), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h1), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h1), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h1), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h1), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_110
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_111
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_54( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_898; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_898 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_98 = shr(io.in.a.bits.source, 5)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_176 = shr(io.in.a.bits.source, 5)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_229 = shr(io.in.a.bits.source, 5)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_276 = shr(io.in.a.bits.source, 5)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_325 = shr(io.in.a.bits.source, 5)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_369 = shr(io.in.a.bits.source, 5)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_413 = shr(io.in.a.bits.source, 5)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<20>
connect a_set, UInt<20>(0h0)
wire a_set_wo_ready : UInt<20>
connect a_set_wo_ready, UInt<20>(0h0)
wire a_opcodes_set : UInt<80>
connect a_opcodes_set, UInt<80>(0h0)
wire a_sizes_set : UInt<80>
connect a_sizes_set, UInt<80>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<20>
connect d_clr, UInt<20>(0h0)
wire d_clr_wo_ready : UInt<20>
connect d_clr_wo_ready, UInt<20>(0h0)
wire d_opcodes_clr : UInt<80>
connect d_opcodes_clr, UInt<80>(0h0)
wire d_sizes_clr : UInt<80>
connect d_sizes_clr, UInt<80>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_80
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<20>
connect c_set, UInt<20>(0h0)
wire c_set_wo_ready : UInt<20>
connect c_set_wo_ready, UInt<20>(0h0)
wire c_opcodes_set : UInt<80>
connect c_opcodes_set, UInt<80>(0h0)
wire c_sizes_set : UInt<80>
connect c_sizes_set, UInt<80>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<20>
connect d_clr_1, UInt<20>(0h0)
wire d_clr_wo_ready_1 : UInt<20>
connect d_clr_wo_ready_1, UInt<20>(0h0)
wire d_opcodes_clr_1 : UInt<80>
connect d_opcodes_clr_1, UInt<80>(0h0)
wire d_sizes_clr_1 : UInt<80>
connect d_sizes_clr_1, UInt<80>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_81
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_40( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<10>(0h200)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = and(_T_19, _T_24)
node _T_26 = or(UInt<1>(0h0), _T_25)
node _T_27 = and(_T_18, _T_26)
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_27, UInt<1>(0h1), "") : assert_2
node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(UInt<1>(0h0), _T_33)
node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<10>(0h200)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = and(_T_34, _T_39)
node _T_41 = or(UInt<1>(0h0), _T_40)
node _T_42 = and(UInt<1>(0h0), _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_42, UInt<1>(0h1), "") : assert_3
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_49, UInt<1>(0h1), "") : assert_5
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(is_aligned, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_56, UInt<1>(0h1), "") : assert_7
node _T_60 = not(io.in.a.bits.mask)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_61, UInt<1>(0h1), "") : assert_8
node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_69 :
node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_71 = and(UInt<1>(0h0), _T_70)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<10>(0h200)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = and(_T_73, _T_78)
node _T_80 = or(UInt<1>(0h0), _T_79)
node _T_81 = and(_T_72, _T_80)
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_81, UInt<1>(0h1), "") : assert_10
node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_87 = and(_T_85, _T_86)
node _T_88 = or(UInt<1>(0h0), _T_87)
node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<10>(0h200)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = and(_T_88, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_94)
node _T_96 = and(UInt<1>(0h0), _T_95)
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_96, UInt<1>(0h1), "") : assert_11
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_103, UInt<1>(0h1), "") : assert_13
node _T_107 = asUInt(reset)
node _T_108 = eq(_T_107, UInt<1>(0h0))
when _T_108 :
node _T_109 = eq(is_aligned, UInt<1>(0h0))
when _T_109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_110, UInt<1>(0h1), "") : assert_15
node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_114, UInt<1>(0h1), "") : assert_16
node _T_118 = not(io.in.a.bits.mask)
node _T_119 = eq(_T_118, UInt<1>(0h0))
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_119, UInt<1>(0h1), "") : assert_17
node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_T_123, UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_123, UInt<1>(0h1), "") : assert_18
node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_127 :
node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_130 = and(_T_128, _T_129)
node _T_131 = or(UInt<1>(0h0), _T_130)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_131, UInt<1>(0h1), "") : assert_19
node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_137 = and(_T_135, _T_136)
node _T_138 = or(UInt<1>(0h0), _T_137)
node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<10>(0h200)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = and(_T_138, _T_143)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = asUInt(reset)
node _T_147 = eq(_T_146, UInt<1>(0h0))
when _T_147 :
node _T_148 = eq(_T_145, UInt<1>(0h0))
when _T_148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_145, UInt<1>(0h1), "") : assert_20
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_155, UInt<1>(0h1), "") : assert_23
node _T_159 = eq(io.in.a.bits.mask, mask)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_159, UInt<1>(0h1), "") : assert_24
node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_163, UInt<1>(0h1), "") : assert_25
node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_170 = and(_T_168, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_174 = and(_T_172, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<10>(0h200)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = and(_T_175, _T_180)
node _T_182 = or(UInt<1>(0h0), _T_181)
node _T_183 = and(_T_171, _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_183, UInt<1>(0h1), "") : assert_26
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(is_aligned, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_193, UInt<1>(0h1), "") : assert_29
node _T_197 = eq(io.in.a.bits.mask, mask)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_197, UInt<1>(0h1), "") : assert_30
node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_201 :
node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_203 = and(UInt<1>(0h0), _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_207 = and(_T_205, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_210 = cvt(_T_209)
node _T_211 = and(_T_210, asSInt(UInt<10>(0h200)))
node _T_212 = asSInt(_T_211)
node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0)))
node _T_214 = and(_T_208, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(_T_204, _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_216, UInt<1>(0h1), "") : assert_31
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(is_aligned, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_226, UInt<1>(0h1), "") : assert_34
node _T_230 = not(mask)
node _T_231 = and(io.in.a.bits.mask, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_232, UInt<1>(0h1), "") : assert_35
node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_236 :
node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_238 = and(UInt<1>(0h0), _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<10>(0h200)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = and(_T_240, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = and(_T_239, _T_247)
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_248, UInt<1>(0h1), "") : assert_36
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(is_aligned, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_258, UInt<1>(0h1), "") : assert_39
node _T_262 = eq(io.in.a.bits.mask, mask)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_262, UInt<1>(0h1), "") : assert_40
node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_266 :
node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_268 = and(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<10>(0h200)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_T_269, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_278, UInt<1>(0h1), "") : assert_41
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(is_aligned, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_288, UInt<1>(0h1), "") : assert_44
node _T_292 = eq(io.in.a.bits.mask, mask)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_292, UInt<1>(0h1), "") : assert_45
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_296 :
node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_298 = and(UInt<1>(0h0), _T_297)
node _T_299 = or(UInt<1>(0h0), _T_298)
node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<10>(0h200)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = and(_T_300, _T_305)
node _T_307 = or(UInt<1>(0h0), _T_306)
node _T_308 = and(_T_299, _T_307)
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_308, UInt<1>(0h1), "") : assert_46
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(is_aligned, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_318, UInt<1>(0h1), "") : assert_49
node _T_322 = eq(io.in.a.bits.mask, mask)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_322, UInt<1>(0h1), "") : assert_50
node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_326, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_331 = asUInt(reset)
node _T_332 = eq(_T_331, UInt<1>(0h0))
when _T_332 :
node _T_333 = eq(_T_330, UInt<1>(0h0))
when _T_333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_330, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_334 :
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_338, UInt<1>(0h1), "") : assert_54
node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_342, UInt<1>(0h1), "") : assert_55
node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_346, UInt<1>(0h1), "") : assert_56
node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_T_350, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_350, UInt<1>(0h1), "") : assert_57
node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_354 :
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(sink_ok, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_361, UInt<1>(0h1), "") : assert_60
node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_365, UInt<1>(0h1), "") : assert_61
node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_369, UInt<1>(0h1), "") : assert_62
node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_373, UInt<1>(0h1), "") : assert_63
node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_378 = or(UInt<1>(0h1), _T_377)
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_378, UInt<1>(0h1), "") : assert_64
node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_382 :
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(sink_ok, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_389, UInt<1>(0h1), "") : assert_67
node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_393, UInt<1>(0h1), "") : assert_68
node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_397, UInt<1>(0h1), "") : assert_69
node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_402 = or(_T_401, io.in.d.bits.corrupt)
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_402, UInt<1>(0h1), "") : assert_70
node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_407 = or(UInt<1>(0h1), _T_406)
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_407, UInt<1>(0h1), "") : assert_71
node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_411 :
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_415, UInt<1>(0h1), "") : assert_73
node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_419, UInt<1>(0h1), "") : assert_74
node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_424 = or(UInt<1>(0h1), _T_423)
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_424, UInt<1>(0h1), "") : assert_75
node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_428 :
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_432, UInt<1>(0h1), "") : assert_77
node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_437 = or(_T_436, io.in.d.bits.corrupt)
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_437, UInt<1>(0h1), "") : assert_78
node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_442 = or(UInt<1>(0h1), _T_441)
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_442, UInt<1>(0h1), "") : assert_79
node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_450, UInt<1>(0h1), "") : assert_81
node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_454, UInt<1>(0h1), "") : assert_82
node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_459 = or(UInt<1>(0h1), _T_458)
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_459, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_463, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_467, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_471, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_475 = eq(a_first, UInt<1>(0h0))
node _T_476 = and(io.in.a.valid, _T_475)
when _T_476 :
node _T_477 = eq(io.in.a.bits.opcode, opcode)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_477, UInt<1>(0h1), "") : assert_87
node _T_481 = eq(io.in.a.bits.param, param)
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_481, UInt<1>(0h1), "") : assert_88
node _T_485 = eq(io.in.a.bits.size, size)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_485, UInt<1>(0h1), "") : assert_89
node _T_489 = eq(io.in.a.bits.source, source)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_489, UInt<1>(0h1), "") : assert_90
node _T_493 = eq(io.in.a.bits.address, address)
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_493, UInt<1>(0h1), "") : assert_91
node _T_497 = and(io.in.a.ready, io.in.a.valid)
node _T_498 = and(_T_497, a_first)
when _T_498 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_499 = eq(d_first, UInt<1>(0h0))
node _T_500 = and(io.in.d.valid, _T_499)
when _T_500 :
node _T_501 = eq(io.in.d.bits.opcode, opcode_1)
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_501, UInt<1>(0h1), "") : assert_92
node _T_505 = eq(io.in.d.bits.param, param_1)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_505, UInt<1>(0h1), "") : assert_93
node _T_509 = eq(io.in.d.bits.size, size_1)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_509, UInt<1>(0h1), "") : assert_94
node _T_513 = eq(io.in.d.bits.source, source_1)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_513, UInt<1>(0h1), "") : assert_95
node _T_517 = eq(io.in.d.bits.sink, sink)
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_517, UInt<1>(0h1), "") : assert_96
node _T_521 = eq(io.in.d.bits.denied, denied)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_521, UInt<1>(0h1), "") : assert_97
node _T_525 = and(io.in.d.ready, io.in.d.valid)
node _T_526 = and(_T_525, d_first)
when _T_526 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_527 = and(io.in.a.valid, a_first_1)
node _T_528 = and(_T_527, UInt<1>(0h1))
when _T_528 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_529 = and(io.in.a.ready, io.in.a.valid)
node _T_530 = and(_T_529, a_first_1)
node _T_531 = and(_T_530, UInt<1>(0h1))
when _T_531 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_532 = dshr(inflight, io.in.a.bits.source)
node _T_533 = bits(_T_532, 0, 0)
node _T_534 = eq(_T_533, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_534, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_538 = and(io.in.d.valid, d_first_1)
node _T_539 = and(_T_538, UInt<1>(0h1))
node _T_540 = eq(d_release_ack, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
when _T_541 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_542 = and(io.in.d.ready, io.in.d.valid)
node _T_543 = and(_T_542, d_first_1)
node _T_544 = and(_T_543, UInt<1>(0h1))
node _T_545 = eq(d_release_ack, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
when _T_546 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_551 = dshr(inflight, io.in.d.bits.source)
node _T_552 = bits(_T_551, 0, 0)
node _T_553 = or(_T_552, same_cycle_resp)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_553, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_559 = or(_T_557, _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_559, UInt<1>(0h1), "") : assert_100
node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_563, UInt<1>(0h1), "") : assert_101
else :
node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_569 = or(_T_567, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_569, UInt<1>(0h1), "") : assert_102
node _T_573 = eq(io.in.d.bits.size, a_size_lookup)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_573, UInt<1>(0h1), "") : assert_103
node _T_577 = and(io.in.d.valid, d_first_1)
node _T_578 = and(_T_577, a_first_1)
node _T_579 = and(_T_578, io.in.a.valid)
node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_581 = and(_T_579, _T_580)
node _T_582 = eq(d_release_ack, UInt<1>(0h0))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
node _T_584 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_585 = or(_T_584, io.in.a.ready)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_585, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_104
node _T_589 = orr(inflight)
node _T_590 = eq(_T_589, UInt<1>(0h0))
node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_592 = or(_T_590, _T_591)
node _T_593 = lt(watchdog, plusarg_reader.out)
node _T_594 = or(_T_592, _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_594, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_598 = and(io.in.a.ready, io.in.a.valid)
node _T_599 = and(io.in.d.ready, io.in.d.valid)
node _T_600 = or(_T_598, _T_599)
when _T_600 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_601 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_604 = and(_T_602, _T_603)
node _T_605 = and(_T_601, _T_604)
when _T_605 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_607 = and(_T_606, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_610 = and(_T_608, _T_609)
node _T_611 = and(_T_607, _T_610)
when _T_611 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_612 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = eq(_T_613, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_614, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_618 = and(io.in.d.valid, d_first_2)
node _T_619 = and(_T_618, UInt<1>(0h1))
node _T_620 = and(_T_619, d_release_ack_1)
when _T_620 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_621 = and(io.in.d.ready, io.in.d.valid)
node _T_622 = and(_T_621, d_first_2)
node _T_623 = and(_T_622, UInt<1>(0h1))
node _T_624 = and(_T_623, d_release_ack_1)
when _T_624 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_625 = and(io.in.d.valid, d_first_2)
node _T_626 = and(_T_625, UInt<1>(0h1))
node _T_627 = and(_T_626, d_release_ack_1)
when _T_627 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_628 = dshr(inflight_1, io.in.d.bits.source)
node _T_629 = bits(_T_628, 0, 0)
node _T_630 = or(_T_629, same_cycle_resp_1)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_630, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_634, UInt<1>(0h1), "") : assert_108
else :
node _T_638 = eq(io.in.d.bits.size, c_size_lookup)
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_638, UInt<1>(0h1), "") : assert_109
node _T_642 = and(io.in.d.valid, d_first_2)
node _T_643 = and(_T_642, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_644 = and(_T_643, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_646 = and(_T_644, _T_645)
node _T_647 = and(_T_646, d_release_ack_1)
node _T_648 = eq(c_probe_ack, UInt<1>(0h0))
node _T_649 = and(_T_647, _T_648)
when _T_649 :
node _T_650 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_651 = or(_T_650, _WIRE_23.ready)
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_651, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_105
node _T_655 = orr(inflight_1)
node _T_656 = eq(_T_655, UInt<1>(0h0))
node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_658 = or(_T_656, _T_657)
node _T_659 = lt(watchdog_1, plusarg_reader_1.out)
node _T_660 = or(_T_658, _T_659)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_660, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_665 = and(io.in.d.ready, io.in.d.valid)
node _T_666 = or(_T_664, _T_665)
when _T_666 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_51( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_598; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_240 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_240( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e11_s53 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}}
inst divSqrtRawFN of DivSqrtRawFN_small_e11_s53
connect divSqrtRawFN.clock, clock
connect divSqrtRawFN.reset, reset
connect io.inReady, divSqrtRawFN.io.inReady
connect divSqrtRawFN.io.inValid, io.inValid
connect divSqrtRawFN.io.sqrtOp, io.sqrtOp
node divSqrtRawFN_io_a_exp = bits(io.a, 63, 52)
node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 11, 9)
node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 11, 10)
node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 9, 9)
node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T)
connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1
node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 9, 9)
node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1)
connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2
connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero
node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 64, 64)
connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T
node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp)
connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T
node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T)
node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 51, 0)
node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2)
connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3
connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig
connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp
connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign
connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero
connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf
connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN
node divSqrtRawFN_io_b_exp = bits(io.b, 63, 52)
node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 11, 9)
node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 11, 10)
node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 9, 9)
node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T)
connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1
node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 9, 9)
node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1)
connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2
connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero
node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 64, 64)
connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T
node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp)
connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T
node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T)
node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 51, 0)
node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2)
connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3
connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig
connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp
connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign
connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero
connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf
connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN
connect divSqrtRawFN.io.roundingMode, io.roundingMode
connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div
connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt
connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut
connect io.invalidExc, divSqrtRawFN.io.invalidExc
connect io.infiniteExc, divSqrtRawFN.io.infiniteExc
connect io.rawOut, divSqrtRawFN.io.rawOut | module DivSqrtRecFMToRaw_small_e11_s53( // @[DivSqrtRecFN_small.scala:422:5]
input clock, // @[DivSqrtRecFN_small.scala:422:5]
input reset, // @[DivSqrtRecFN_small.scala:422:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:426:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:426:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16]
input [64:0] io_a, // @[DivSqrtRecFN_small.scala:426:16]
input [64:0] io_b, // @[DivSqrtRecFN_small.scala:426:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16]
output [12:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16]
output [55:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5]
wire [64:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5]
wire [64:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [11:0] divSqrtRawFN_io_a_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] divSqrtRawFN_io_b_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
DivSqrtRawFN_small_e11_s53 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_rawOutValid_div (io_rawOutValid_div_0),
.io_rawOutValid_sqrt (io_rawOutValid_sqrt_0),
.io_roundingModeOut (io_roundingModeOut_0),
.io_invalidExc (io_invalidExc_0),
.io_infiniteExc (io_infiniteExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (io_rawOut_sig_0)
); // @[DivSqrtRecFN_small.scala:446:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<3>(0h6))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_4, UInt<3>(0h4))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_39 = shr(io.in.a.bits.source, 3)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<3>(0h4))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<3>(0h4))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[18]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_36
connect _source_ok_WIRE[12], _source_ok_T_37
connect _source_ok_WIRE[13], _source_ok_T_38
connect _source_ok_WIRE[14], _source_ok_T_44
connect _source_ok_WIRE[15], _source_ok_T_45
connect _source_ok_WIRE[16], _source_ok_T_46
connect _source_ok_WIRE[17], _source_ok_T_47
node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[7])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[8])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[9])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[10])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[11])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[12])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[13])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[14])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[15])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[16])
node source_ok = or(_source_ok_T_63, _source_ok_WIRE[17])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_112 = shr(io.in.a.bits.source, 3)
node _T_113 = eq(_T_112, UInt<3>(0h6))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<3>(0h4))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_120 = cvt(_T_119)
node _T_121 = and(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = asSInt(_T_121)
node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = or(_T_118, _T_123)
node _T_125 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_126 = eq(_T_125, UInt<1>(0h0))
node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = or(_T_126, _T_131)
node _T_133 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = or(_T_134, _T_139)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_141 = shr(io.in.a.bits.source, 3)
node _T_142 = eq(_T_141, UInt<3>(0h4))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_5, UInt<3>(0h4))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(_T_146, UInt<1>(0h0))
node _T_148 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_149 = cvt(_T_148)
node _T_150 = and(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = asSInt(_T_150)
node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0)))
node _T_153 = or(_T_147, _T_152)
node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = or(_T_155, _T_160)
node _T_162 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_163 = eq(_T_162, UInt<1>(0h0))
node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = or(_T_163, _T_168)
node _T_170 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = or(_T_171, _T_176)
node _T_178 = and(_T_11, _T_24)
node _T_179 = and(_T_178, _T_37)
node _T_180 = and(_T_179, _T_50)
node _T_181 = and(_T_180, _T_63)
node _T_182 = and(_T_181, _T_71)
node _T_183 = and(_T_182, _T_79)
node _T_184 = and(_T_183, _T_87)
node _T_185 = and(_T_184, _T_95)
node _T_186 = and(_T_185, _T_103)
node _T_187 = and(_T_186, _T_111)
node _T_188 = and(_T_187, _T_124)
node _T_189 = and(_T_188, _T_132)
node _T_190 = and(_T_189, _T_140)
node _T_191 = and(_T_190, _T_153)
node _T_192 = and(_T_191, _T_161)
node _T_193 = and(_T_192, _T_169)
node _T_194 = and(_T_193, _T_177)
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_194, UInt<1>(0h1), "") : assert_1
node _T_198 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_198 :
node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_201 = and(_T_199, _T_200)
node _T_202 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_203 = shr(io.in.a.bits.source, 2)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_206 = and(_T_204, _T_205)
node _T_207 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_208 = and(_T_206, _T_207)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_209 = shr(io.in.a.bits.source, 2)
node _T_210 = eq(_T_209, UInt<1>(0h1))
node _T_211 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_212 = and(_T_210, _T_211)
node _T_213 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_214 = and(_T_212, _T_213)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_215 = shr(io.in.a.bits.source, 2)
node _T_216 = eq(_T_215, UInt<2>(0h2))
node _T_217 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_218 = and(_T_216, _T_217)
node _T_219 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_220 = and(_T_218, _T_219)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_221 = shr(io.in.a.bits.source, 2)
node _T_222 = eq(_T_221, UInt<2>(0h3))
node _T_223 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_224 = and(_T_222, _T_223)
node _T_225 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_228 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_230 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_231 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0)
node _T_233 = shr(io.in.a.bits.source, 3)
node _T_234 = eq(_T_233, UInt<3>(0h6))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_10, UInt<3>(0h4))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_241 = shr(io.in.a.bits.source, 3)
node _T_242 = eq(_T_241, UInt<3>(0h4))
node _T_243 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_244 = and(_T_242, _T_243)
node _T_245 = leq(uncommonBits_11, UInt<3>(0h4))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_249 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_250 = or(_T_202, _T_208)
node _T_251 = or(_T_250, _T_214)
node _T_252 = or(_T_251, _T_220)
node _T_253 = or(_T_252, _T_226)
node _T_254 = or(_T_253, _T_227)
node _T_255 = or(_T_254, _T_228)
node _T_256 = or(_T_255, _T_229)
node _T_257 = or(_T_256, _T_230)
node _T_258 = or(_T_257, _T_231)
node _T_259 = or(_T_258, _T_232)
node _T_260 = or(_T_259, _T_238)
node _T_261 = or(_T_260, _T_239)
node _T_262 = or(_T_261, _T_240)
node _T_263 = or(_T_262, _T_246)
node _T_264 = or(_T_263, _T_247)
node _T_265 = or(_T_264, _T_248)
node _T_266 = or(_T_265, _T_249)
node _T_267 = and(_T_201, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_271 = cvt(_T_270)
node _T_272 = and(_T_271, asSInt(UInt<14>(0h2000)))
node _T_273 = asSInt(_T_272)
node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0)))
node _T_275 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_276 = cvt(_T_275)
node _T_277 = and(_T_276, asSInt(UInt<13>(0h1000)))
node _T_278 = asSInt(_T_277)
node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0)))
node _T_280 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_281 = cvt(_T_280)
node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000)))
node _T_283 = asSInt(_T_282)
node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0)))
node _T_285 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_286 = cvt(_T_285)
node _T_287 = and(_T_286, asSInt(UInt<18>(0h2f000)))
node _T_288 = asSInt(_T_287)
node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0)))
node _T_290 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<17>(0h10000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = or(_T_274, _T_279)
node _T_311 = or(_T_310, _T_284)
node _T_312 = or(_T_311, _T_289)
node _T_313 = or(_T_312, _T_294)
node _T_314 = or(_T_313, _T_299)
node _T_315 = or(_T_314, _T_304)
node _T_316 = or(_T_315, _T_309)
node _T_317 = and(_T_269, _T_316)
node _T_318 = or(UInt<1>(0h0), _T_317)
node _T_319 = and(_T_268, _T_318)
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(_T_319, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_319, UInt<1>(0h1), "") : assert_2
node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_324 = shr(io.in.a.bits.source, 2)
node _T_325 = eq(_T_324, UInt<1>(0h0))
node _T_326 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_327 = and(_T_325, _T_326)
node _T_328 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_329 = and(_T_327, _T_328)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_330 = shr(io.in.a.bits.source, 2)
node _T_331 = eq(_T_330, UInt<1>(0h1))
node _T_332 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_333 = and(_T_331, _T_332)
node _T_334 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_335 = and(_T_333, _T_334)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_336 = shr(io.in.a.bits.source, 2)
node _T_337 = eq(_T_336, UInt<2>(0h2))
node _T_338 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_339 = and(_T_337, _T_338)
node _T_340 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_341 = and(_T_339, _T_340)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_342 = shr(io.in.a.bits.source, 2)
node _T_343 = eq(_T_342, UInt<2>(0h3))
node _T_344 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_345 = and(_T_343, _T_344)
node _T_346 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_350 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_351 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_352 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_353 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0)
node _T_354 = shr(io.in.a.bits.source, 3)
node _T_355 = eq(_T_354, UInt<3>(0h6))
node _T_356 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_357 = and(_T_355, _T_356)
node _T_358 = leq(uncommonBits_16, UInt<3>(0h4))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_361 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0)
node _T_362 = shr(io.in.a.bits.source, 3)
node _T_363 = eq(_T_362, UInt<3>(0h4))
node _T_364 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_365 = and(_T_363, _T_364)
node _T_366 = leq(uncommonBits_17, UInt<3>(0h4))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_370 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[18]
connect _WIRE[0], _T_323
connect _WIRE[1], _T_329
connect _WIRE[2], _T_335
connect _WIRE[3], _T_341
connect _WIRE[4], _T_347
connect _WIRE[5], _T_348
connect _WIRE[6], _T_349
connect _WIRE[7], _T_350
connect _WIRE[8], _T_351
connect _WIRE[9], _T_352
connect _WIRE[10], _T_353
connect _WIRE[11], _T_359
connect _WIRE[12], _T_360
connect _WIRE[13], _T_361
connect _WIRE[14], _T_367
connect _WIRE[15], _T_368
connect _WIRE[16], _T_369
connect _WIRE[17], _T_370
node _T_371 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_372 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_373 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_375 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_376 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_377 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_379 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_380 = mux(_WIRE[5], _T_371, UInt<1>(0h0))
node _T_381 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_382 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_383 = mux(_WIRE[8], _T_372, UInt<1>(0h0))
node _T_384 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_385 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_386 = mux(_WIRE[11], _T_373, UInt<1>(0h0))
node _T_387 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_388 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_389 = mux(_WIRE[14], _T_374, UInt<1>(0h0))
node _T_390 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_391 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_392 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_393 = or(_T_375, _T_376)
node _T_394 = or(_T_393, _T_377)
node _T_395 = or(_T_394, _T_378)
node _T_396 = or(_T_395, _T_379)
node _T_397 = or(_T_396, _T_380)
node _T_398 = or(_T_397, _T_381)
node _T_399 = or(_T_398, _T_382)
node _T_400 = or(_T_399, _T_383)
node _T_401 = or(_T_400, _T_384)
node _T_402 = or(_T_401, _T_385)
node _T_403 = or(_T_402, _T_386)
node _T_404 = or(_T_403, _T_387)
node _T_405 = or(_T_404, _T_388)
node _T_406 = or(_T_405, _T_389)
node _T_407 = or(_T_406, _T_390)
node _T_408 = or(_T_407, _T_391)
node _T_409 = or(_T_408, _T_392)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_409
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _T_413 = or(UInt<1>(0h0), _T_412)
node _T_414 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<14>(0h2000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<18>(0h2f000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_445 = cvt(_T_444)
node _T_446 = and(_T_445, asSInt(UInt<27>(0h4000000)))
node _T_447 = asSInt(_T_446)
node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0)))
node _T_449 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_450 = cvt(_T_449)
node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000)))
node _T_452 = asSInt(_T_451)
node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0)))
node _T_454 = or(_T_418, _T_423)
node _T_455 = or(_T_454, _T_428)
node _T_456 = or(_T_455, _T_433)
node _T_457 = or(_T_456, _T_438)
node _T_458 = or(_T_457, _T_443)
node _T_459 = or(_T_458, _T_448)
node _T_460 = or(_T_459, _T_453)
node _T_461 = and(_T_413, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = and(_WIRE_1, _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_463, UInt<1>(0h1), "") : assert_3
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(source_ok, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_470 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_471 = asUInt(reset)
node _T_472 = eq(_T_471, UInt<1>(0h0))
when _T_472 :
node _T_473 = eq(_T_470, UInt<1>(0h0))
when _T_473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_470, UInt<1>(0h1), "") : assert_5
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(is_aligned, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_477 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_477, UInt<1>(0h1), "") : assert_7
node _T_481 = not(io.in.a.bits.mask)
node _T_482 = eq(_T_481, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_482, UInt<1>(0h1), "") : assert_8
node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_486, UInt<1>(0h1), "") : assert_9
node _T_490 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_490 :
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_495 = shr(io.in.a.bits.source, 2)
node _T_496 = eq(_T_495, UInt<1>(0h0))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<1>(0h1))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<2>(0h2))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<2>(0h3))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_520 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_521 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_524 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0)
node _T_525 = shr(io.in.a.bits.source, 3)
node _T_526 = eq(_T_525, UInt<3>(0h6))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_22, UInt<3>(0h4))
node _T_530 = and(_T_528, _T_529)
node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0)
node _T_533 = shr(io.in.a.bits.source, 3)
node _T_534 = eq(_T_533, UInt<3>(0h4))
node _T_535 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_536 = and(_T_534, _T_535)
node _T_537 = leq(uncommonBits_23, UInt<3>(0h4))
node _T_538 = and(_T_536, _T_537)
node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_540 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_541 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_542 = or(_T_494, _T_500)
node _T_543 = or(_T_542, _T_506)
node _T_544 = or(_T_543, _T_512)
node _T_545 = or(_T_544, _T_518)
node _T_546 = or(_T_545, _T_519)
node _T_547 = or(_T_546, _T_520)
node _T_548 = or(_T_547, _T_521)
node _T_549 = or(_T_548, _T_522)
node _T_550 = or(_T_549, _T_523)
node _T_551 = or(_T_550, _T_524)
node _T_552 = or(_T_551, _T_530)
node _T_553 = or(_T_552, _T_531)
node _T_554 = or(_T_553, _T_532)
node _T_555 = or(_T_554, _T_538)
node _T_556 = or(_T_555, _T_539)
node _T_557 = or(_T_556, _T_540)
node _T_558 = or(_T_557, _T_541)
node _T_559 = and(_T_493, _T_558)
node _T_560 = or(UInt<1>(0h0), _T_559)
node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_562 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_563 = cvt(_T_562)
node _T_564 = and(_T_563, asSInt(UInt<14>(0h2000)))
node _T_565 = asSInt(_T_564)
node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0)))
node _T_567 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<13>(0h1000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<17>(0h10000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_578 = cvt(_T_577)
node _T_579 = and(_T_578, asSInt(UInt<18>(0h2f000)))
node _T_580 = asSInt(_T_579)
node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0)))
node _T_582 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<17>(0h10000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_588 = cvt(_T_587)
node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000)))
node _T_590 = asSInt(_T_589)
node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0)))
node _T_592 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_593 = cvt(_T_592)
node _T_594 = and(_T_593, asSInt(UInt<27>(0h4000000)))
node _T_595 = asSInt(_T_594)
node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0)))
node _T_597 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_598 = cvt(_T_597)
node _T_599 = and(_T_598, asSInt(UInt<13>(0h1000)))
node _T_600 = asSInt(_T_599)
node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0)))
node _T_602 = or(_T_566, _T_571)
node _T_603 = or(_T_602, _T_576)
node _T_604 = or(_T_603, _T_581)
node _T_605 = or(_T_604, _T_586)
node _T_606 = or(_T_605, _T_591)
node _T_607 = or(_T_606, _T_596)
node _T_608 = or(_T_607, _T_601)
node _T_609 = and(_T_561, _T_608)
node _T_610 = or(UInt<1>(0h0), _T_609)
node _T_611 = and(_T_560, _T_610)
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_T_611, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_611, UInt<1>(0h1), "") : assert_10
node _T_615 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_616 = shr(io.in.a.bits.source, 2)
node _T_617 = eq(_T_616, UInt<1>(0h0))
node _T_618 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_619 = and(_T_617, _T_618)
node _T_620 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_621 = and(_T_619, _T_620)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_622 = shr(io.in.a.bits.source, 2)
node _T_623 = eq(_T_622, UInt<1>(0h1))
node _T_624 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_625 = and(_T_623, _T_624)
node _T_626 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_627 = and(_T_625, _T_626)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_628 = shr(io.in.a.bits.source, 2)
node _T_629 = eq(_T_628, UInt<2>(0h2))
node _T_630 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_631 = and(_T_629, _T_630)
node _T_632 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_633 = and(_T_631, _T_632)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_634 = shr(io.in.a.bits.source, 2)
node _T_635 = eq(_T_634, UInt<2>(0h3))
node _T_636 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_637 = and(_T_635, _T_636)
node _T_638 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_639 = and(_T_637, _T_638)
node _T_640 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_642 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_643 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_644 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_645 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0)
node _T_646 = shr(io.in.a.bits.source, 3)
node _T_647 = eq(_T_646, UInt<3>(0h6))
node _T_648 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_649 = and(_T_647, _T_648)
node _T_650 = leq(uncommonBits_28, UInt<3>(0h4))
node _T_651 = and(_T_649, _T_650)
node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_653 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0)
node _T_654 = shr(io.in.a.bits.source, 3)
node _T_655 = eq(_T_654, UInt<3>(0h4))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_29, UInt<3>(0h4))
node _T_659 = and(_T_657, _T_658)
node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_662 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[18]
connect _WIRE_2[0], _T_615
connect _WIRE_2[1], _T_621
connect _WIRE_2[2], _T_627
connect _WIRE_2[3], _T_633
connect _WIRE_2[4], _T_639
connect _WIRE_2[5], _T_640
connect _WIRE_2[6], _T_641
connect _WIRE_2[7], _T_642
connect _WIRE_2[8], _T_643
connect _WIRE_2[9], _T_644
connect _WIRE_2[10], _T_645
connect _WIRE_2[11], _T_651
connect _WIRE_2[12], _T_652
connect _WIRE_2[13], _T_653
connect _WIRE_2[14], _T_659
connect _WIRE_2[15], _T_660
connect _WIRE_2[16], _T_661
connect _WIRE_2[17], _T_662
node _T_663 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_664 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_665 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_666 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_667 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_668 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_669 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_670 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_671 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_672 = mux(_WIRE_2[5], _T_663, UInt<1>(0h0))
node _T_673 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_674 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_675 = mux(_WIRE_2[8], _T_664, UInt<1>(0h0))
node _T_676 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_677 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_678 = mux(_WIRE_2[11], _T_665, UInt<1>(0h0))
node _T_679 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_680 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_681 = mux(_WIRE_2[14], _T_666, UInt<1>(0h0))
node _T_682 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_683 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_684 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_685 = or(_T_667, _T_668)
node _T_686 = or(_T_685, _T_669)
node _T_687 = or(_T_686, _T_670)
node _T_688 = or(_T_687, _T_671)
node _T_689 = or(_T_688, _T_672)
node _T_690 = or(_T_689, _T_673)
node _T_691 = or(_T_690, _T_674)
node _T_692 = or(_T_691, _T_675)
node _T_693 = or(_T_692, _T_676)
node _T_694 = or(_T_693, _T_677)
node _T_695 = or(_T_694, _T_678)
node _T_696 = or(_T_695, _T_679)
node _T_697 = or(_T_696, _T_680)
node _T_698 = or(_T_697, _T_681)
node _T_699 = or(_T_698, _T_682)
node _T_700 = or(_T_699, _T_683)
node _T_701 = or(_T_700, _T_684)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_701
node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_703 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_704 = and(_T_702, _T_703)
node _T_705 = or(UInt<1>(0h0), _T_704)
node _T_706 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<14>(0h2000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<18>(0h2f000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<27>(0h4000000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = or(_T_710, _T_715)
node _T_747 = or(_T_746, _T_720)
node _T_748 = or(_T_747, _T_725)
node _T_749 = or(_T_748, _T_730)
node _T_750 = or(_T_749, _T_735)
node _T_751 = or(_T_750, _T_740)
node _T_752 = or(_T_751, _T_745)
node _T_753 = and(_T_705, _T_752)
node _T_754 = or(UInt<1>(0h0), _T_753)
node _T_755 = and(_WIRE_3, _T_754)
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(_T_755, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_755, UInt<1>(0h1), "") : assert_11
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(source_ok, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_762 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_762, UInt<1>(0h1), "") : assert_13
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(is_aligned, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_769 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_770 = asUInt(reset)
node _T_771 = eq(_T_770, UInt<1>(0h0))
when _T_771 :
node _T_772 = eq(_T_769, UInt<1>(0h0))
when _T_772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_769, UInt<1>(0h1), "") : assert_15
node _T_773 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_773, UInt<1>(0h1), "") : assert_16
node _T_777 = not(io.in.a.bits.mask)
node _T_778 = eq(_T_777, UInt<1>(0h0))
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_778, UInt<1>(0h1), "") : assert_17
node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_782, UInt<1>(0h1), "") : assert_18
node _T_786 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_786 :
node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_789 = and(_T_787, _T_788)
node _T_790 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<1>(0h0))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_797 = shr(io.in.a.bits.source, 2)
node _T_798 = eq(_T_797, UInt<1>(0h1))
node _T_799 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_800 = and(_T_798, _T_799)
node _T_801 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_802 = and(_T_800, _T_801)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_803 = shr(io.in.a.bits.source, 2)
node _T_804 = eq(_T_803, UInt<2>(0h2))
node _T_805 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_806 = and(_T_804, _T_805)
node _T_807 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_808 = and(_T_806, _T_807)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<2>(0h3))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_816 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_817 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_818 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_819 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_821 = shr(io.in.a.bits.source, 3)
node _T_822 = eq(_T_821, UInt<3>(0h6))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_34, UInt<3>(0h4))
node _T_826 = and(_T_824, _T_825)
node _T_827 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_828 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0)
node _T_829 = shr(io.in.a.bits.source, 3)
node _T_830 = eq(_T_829, UInt<3>(0h4))
node _T_831 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_832 = and(_T_830, _T_831)
node _T_833 = leq(uncommonBits_35, UInt<3>(0h4))
node _T_834 = and(_T_832, _T_833)
node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_837 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_838 = or(_T_790, _T_796)
node _T_839 = or(_T_838, _T_802)
node _T_840 = or(_T_839, _T_808)
node _T_841 = or(_T_840, _T_814)
node _T_842 = or(_T_841, _T_815)
node _T_843 = or(_T_842, _T_816)
node _T_844 = or(_T_843, _T_817)
node _T_845 = or(_T_844, _T_818)
node _T_846 = or(_T_845, _T_819)
node _T_847 = or(_T_846, _T_820)
node _T_848 = or(_T_847, _T_826)
node _T_849 = or(_T_848, _T_827)
node _T_850 = or(_T_849, _T_828)
node _T_851 = or(_T_850, _T_834)
node _T_852 = or(_T_851, _T_835)
node _T_853 = or(_T_852, _T_836)
node _T_854 = or(_T_853, _T_837)
node _T_855 = and(_T_789, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = asUInt(reset)
node _T_858 = eq(_T_857, UInt<1>(0h0))
when _T_858 :
node _T_859 = eq(_T_856, UInt<1>(0h0))
when _T_859 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_856, UInt<1>(0h1), "") : assert_19
node _T_860 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_861 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_862 = and(_T_860, _T_861)
node _T_863 = or(UInt<1>(0h0), _T_862)
node _T_864 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<13>(0h1000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = and(_T_863, _T_868)
node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_871 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_872 = and(_T_870, _T_871)
node _T_873 = or(UInt<1>(0h0), _T_872)
node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = or(_T_878, _T_883)
node _T_910 = or(_T_909, _T_888)
node _T_911 = or(_T_910, _T_893)
node _T_912 = or(_T_911, _T_898)
node _T_913 = or(_T_912, _T_903)
node _T_914 = or(_T_913, _T_908)
node _T_915 = and(_T_873, _T_914)
node _T_916 = or(UInt<1>(0h0), _T_869)
node _T_917 = or(_T_916, _T_915)
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_917, UInt<1>(0h1), "") : assert_20
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(source_ok, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_924 = asUInt(reset)
node _T_925 = eq(_T_924, UInt<1>(0h0))
when _T_925 :
node _T_926 = eq(is_aligned, UInt<1>(0h0))
when _T_926 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_927 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_928 = asUInt(reset)
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(_T_927, UInt<1>(0h0))
when _T_930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_927, UInt<1>(0h1), "") : assert_23
node _T_931 = eq(io.in.a.bits.mask, mask)
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(_T_931, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_931, UInt<1>(0h1), "") : assert_24
node _T_935 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_935, UInt<1>(0h1), "") : assert_25
node _T_939 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_939 :
node _T_940 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_941 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_942 = and(_T_940, _T_941)
node _T_943 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_944 = shr(io.in.a.bits.source, 2)
node _T_945 = eq(_T_944, UInt<1>(0h0))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_950 = shr(io.in.a.bits.source, 2)
node _T_951 = eq(_T_950, UInt<1>(0h1))
node _T_952 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_953 = and(_T_951, _T_952)
node _T_954 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_955 = and(_T_953, _T_954)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_956 = shr(io.in.a.bits.source, 2)
node _T_957 = eq(_T_956, UInt<2>(0h2))
node _T_958 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_959 = and(_T_957, _T_958)
node _T_960 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_961 = and(_T_959, _T_960)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_962 = shr(io.in.a.bits.source, 2)
node _T_963 = eq(_T_962, UInt<2>(0h3))
node _T_964 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_965 = and(_T_963, _T_964)
node _T_966 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_967 = and(_T_965, _T_966)
node _T_968 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_969 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_970 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_971 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_972 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_973 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_974 = shr(io.in.a.bits.source, 3)
node _T_975 = eq(_T_974, UInt<3>(0h6))
node _T_976 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_977 = and(_T_975, _T_976)
node _T_978 = leq(uncommonBits_40, UInt<3>(0h4))
node _T_979 = and(_T_977, _T_978)
node _T_980 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_981 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_982 = shr(io.in.a.bits.source, 3)
node _T_983 = eq(_T_982, UInt<3>(0h4))
node _T_984 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_985 = and(_T_983, _T_984)
node _T_986 = leq(uncommonBits_41, UInt<3>(0h4))
node _T_987 = and(_T_985, _T_986)
node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_990 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_991 = or(_T_943, _T_949)
node _T_992 = or(_T_991, _T_955)
node _T_993 = or(_T_992, _T_961)
node _T_994 = or(_T_993, _T_967)
node _T_995 = or(_T_994, _T_968)
node _T_996 = or(_T_995, _T_969)
node _T_997 = or(_T_996, _T_970)
node _T_998 = or(_T_997, _T_971)
node _T_999 = or(_T_998, _T_972)
node _T_1000 = or(_T_999, _T_973)
node _T_1001 = or(_T_1000, _T_979)
node _T_1002 = or(_T_1001, _T_980)
node _T_1003 = or(_T_1002, _T_981)
node _T_1004 = or(_T_1003, _T_987)
node _T_1005 = or(_T_1004, _T_988)
node _T_1006 = or(_T_1005, _T_989)
node _T_1007 = or(_T_1006, _T_990)
node _T_1008 = and(_T_942, _T_1007)
node _T_1009 = or(UInt<1>(0h0), _T_1008)
node _T_1010 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1011 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1012 = and(_T_1010, _T_1011)
node _T_1013 = or(UInt<1>(0h0), _T_1012)
node _T_1014 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1015 = cvt(_T_1014)
node _T_1016 = and(_T_1015, asSInt(UInt<13>(0h1000)))
node _T_1017 = asSInt(_T_1016)
node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0)))
node _T_1019 = and(_T_1013, _T_1018)
node _T_1020 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1021 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1022 = and(_T_1020, _T_1021)
node _T_1023 = or(UInt<1>(0h0), _T_1022)
node _T_1024 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1025 = cvt(_T_1024)
node _T_1026 = and(_T_1025, asSInt(UInt<14>(0h2000)))
node _T_1027 = asSInt(_T_1026)
node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0)))
node _T_1029 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1030 = cvt(_T_1029)
node _T_1031 = and(_T_1030, asSInt(UInt<18>(0h2f000)))
node _T_1032 = asSInt(_T_1031)
node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0)))
node _T_1034 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1035 = cvt(_T_1034)
node _T_1036 = and(_T_1035, asSInt(UInt<17>(0h10000)))
node _T_1037 = asSInt(_T_1036)
node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0)))
node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1040 = cvt(_T_1039)
node _T_1041 = and(_T_1040, asSInt(UInt<13>(0h1000)))
node _T_1042 = asSInt(_T_1041)
node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0)))
node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1045 = cvt(_T_1044)
node _T_1046 = and(_T_1045, asSInt(UInt<27>(0h4000000)))
node _T_1047 = asSInt(_T_1046)
node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0)))
node _T_1049 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1050 = cvt(_T_1049)
node _T_1051 = and(_T_1050, asSInt(UInt<13>(0h1000)))
node _T_1052 = asSInt(_T_1051)
node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0)))
node _T_1054 = or(_T_1028, _T_1033)
node _T_1055 = or(_T_1054, _T_1038)
node _T_1056 = or(_T_1055, _T_1043)
node _T_1057 = or(_T_1056, _T_1048)
node _T_1058 = or(_T_1057, _T_1053)
node _T_1059 = and(_T_1023, _T_1058)
node _T_1060 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1061 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1062 = cvt(_T_1061)
node _T_1063 = and(_T_1062, asSInt(UInt<17>(0h10000)))
node _T_1064 = asSInt(_T_1063)
node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0)))
node _T_1066 = and(_T_1060, _T_1065)
node _T_1067 = or(UInt<1>(0h0), _T_1019)
node _T_1068 = or(_T_1067, _T_1059)
node _T_1069 = or(_T_1068, _T_1066)
node _T_1070 = and(_T_1009, _T_1069)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_26
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(source_ok, UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(is_aligned, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1080 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_29
node _T_1084 = eq(io.in.a.bits.mask, mask)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_30
node _T_1088 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1088 :
node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1090 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1091 = and(_T_1089, _T_1090)
node _T_1092 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1093 = shr(io.in.a.bits.source, 2)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
node _T_1095 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1096 = and(_T_1094, _T_1095)
node _T_1097 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1098 = and(_T_1096, _T_1097)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1099 = shr(io.in.a.bits.source, 2)
node _T_1100 = eq(_T_1099, UInt<1>(0h1))
node _T_1101 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1102 = and(_T_1100, _T_1101)
node _T_1103 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1104 = and(_T_1102, _T_1103)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_1105 = shr(io.in.a.bits.source, 2)
node _T_1106 = eq(_T_1105, UInt<2>(0h2))
node _T_1107 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_1110 = and(_T_1108, _T_1109)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_1111 = shr(io.in.a.bits.source, 2)
node _T_1112 = eq(_T_1111, UInt<2>(0h3))
node _T_1113 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_1114 = and(_T_1112, _T_1113)
node _T_1115 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_1116 = and(_T_1114, _T_1115)
node _T_1117 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1118 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1119 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1120 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1121 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1122 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_1123 = shr(io.in.a.bits.source, 3)
node _T_1124 = eq(_T_1123, UInt<3>(0h6))
node _T_1125 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_1126 = and(_T_1124, _T_1125)
node _T_1127 = leq(uncommonBits_46, UInt<3>(0h4))
node _T_1128 = and(_T_1126, _T_1127)
node _T_1129 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1130 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_1131 = shr(io.in.a.bits.source, 3)
node _T_1132 = eq(_T_1131, UInt<3>(0h4))
node _T_1133 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_1134 = and(_T_1132, _T_1133)
node _T_1135 = leq(uncommonBits_47, UInt<3>(0h4))
node _T_1136 = and(_T_1134, _T_1135)
node _T_1137 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1138 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1139 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1140 = or(_T_1092, _T_1098)
node _T_1141 = or(_T_1140, _T_1104)
node _T_1142 = or(_T_1141, _T_1110)
node _T_1143 = or(_T_1142, _T_1116)
node _T_1144 = or(_T_1143, _T_1117)
node _T_1145 = or(_T_1144, _T_1118)
node _T_1146 = or(_T_1145, _T_1119)
node _T_1147 = or(_T_1146, _T_1120)
node _T_1148 = or(_T_1147, _T_1121)
node _T_1149 = or(_T_1148, _T_1122)
node _T_1150 = or(_T_1149, _T_1128)
node _T_1151 = or(_T_1150, _T_1129)
node _T_1152 = or(_T_1151, _T_1130)
node _T_1153 = or(_T_1152, _T_1136)
node _T_1154 = or(_T_1153, _T_1137)
node _T_1155 = or(_T_1154, _T_1138)
node _T_1156 = or(_T_1155, _T_1139)
node _T_1157 = and(_T_1091, _T_1156)
node _T_1158 = or(UInt<1>(0h0), _T_1157)
node _T_1159 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1160 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1161 = and(_T_1159, _T_1160)
node _T_1162 = or(UInt<1>(0h0), _T_1161)
node _T_1163 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1164 = cvt(_T_1163)
node _T_1165 = and(_T_1164, asSInt(UInt<13>(0h1000)))
node _T_1166 = asSInt(_T_1165)
node _T_1167 = eq(_T_1166, asSInt(UInt<1>(0h0)))
node _T_1168 = and(_T_1162, _T_1167)
node _T_1169 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1170 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1171 = and(_T_1169, _T_1170)
node _T_1172 = or(UInt<1>(0h0), _T_1171)
node _T_1173 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1174 = cvt(_T_1173)
node _T_1175 = and(_T_1174, asSInt(UInt<14>(0h2000)))
node _T_1176 = asSInt(_T_1175)
node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0)))
node _T_1178 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1179 = cvt(_T_1178)
node _T_1180 = and(_T_1179, asSInt(UInt<18>(0h2f000)))
node _T_1181 = asSInt(_T_1180)
node _T_1182 = eq(_T_1181, asSInt(UInt<1>(0h0)))
node _T_1183 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1184 = cvt(_T_1183)
node _T_1185 = and(_T_1184, asSInt(UInt<17>(0h10000)))
node _T_1186 = asSInt(_T_1185)
node _T_1187 = eq(_T_1186, asSInt(UInt<1>(0h0)))
node _T_1188 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1189 = cvt(_T_1188)
node _T_1190 = and(_T_1189, asSInt(UInt<13>(0h1000)))
node _T_1191 = asSInt(_T_1190)
node _T_1192 = eq(_T_1191, asSInt(UInt<1>(0h0)))
node _T_1193 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1194 = cvt(_T_1193)
node _T_1195 = and(_T_1194, asSInt(UInt<27>(0h4000000)))
node _T_1196 = asSInt(_T_1195)
node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0)))
node _T_1198 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1199 = cvt(_T_1198)
node _T_1200 = and(_T_1199, asSInt(UInt<13>(0h1000)))
node _T_1201 = asSInt(_T_1200)
node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0)))
node _T_1203 = or(_T_1177, _T_1182)
node _T_1204 = or(_T_1203, _T_1187)
node _T_1205 = or(_T_1204, _T_1192)
node _T_1206 = or(_T_1205, _T_1197)
node _T_1207 = or(_T_1206, _T_1202)
node _T_1208 = and(_T_1172, _T_1207)
node _T_1209 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1210 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1211 = cvt(_T_1210)
node _T_1212 = and(_T_1211, asSInt(UInt<17>(0h10000)))
node _T_1213 = asSInt(_T_1212)
node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = and(_T_1209, _T_1214)
node _T_1216 = or(UInt<1>(0h0), _T_1168)
node _T_1217 = or(_T_1216, _T_1208)
node _T_1218 = or(_T_1217, _T_1215)
node _T_1219 = and(_T_1158, _T_1218)
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_31
node _T_1223 = asUInt(reset)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
when _T_1224 :
node _T_1225 = eq(source_ok, UInt<1>(0h0))
when _T_1225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(is_aligned, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1229 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_34
node _T_1233 = not(mask)
node _T_1234 = and(io.in.a.bits.mask, _T_1233)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_35
node _T_1239 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1239 :
node _T_1240 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1241 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1242 = and(_T_1240, _T_1241)
node _T_1243 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1244 = shr(io.in.a.bits.source, 2)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
node _T_1246 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1247 = and(_T_1245, _T_1246)
node _T_1248 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1249 = and(_T_1247, _T_1248)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_1250 = shr(io.in.a.bits.source, 2)
node _T_1251 = eq(_T_1250, UInt<1>(0h1))
node _T_1252 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1253 = and(_T_1251, _T_1252)
node _T_1254 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_1255 = and(_T_1253, _T_1254)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1256 = shr(io.in.a.bits.source, 2)
node _T_1257 = eq(_T_1256, UInt<2>(0h2))
node _T_1258 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1259 = and(_T_1257, _T_1258)
node _T_1260 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1261 = and(_T_1259, _T_1260)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1262 = shr(io.in.a.bits.source, 2)
node _T_1263 = eq(_T_1262, UInt<2>(0h3))
node _T_1264 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1265 = and(_T_1263, _T_1264)
node _T_1266 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1267 = and(_T_1265, _T_1266)
node _T_1268 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1269 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1270 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1271 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1272 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1273 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0)
node _T_1274 = shr(io.in.a.bits.source, 3)
node _T_1275 = eq(_T_1274, UInt<3>(0h6))
node _T_1276 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1277 = and(_T_1275, _T_1276)
node _T_1278 = leq(uncommonBits_52, UInt<3>(0h4))
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1281 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_1282 = shr(io.in.a.bits.source, 3)
node _T_1283 = eq(_T_1282, UInt<3>(0h4))
node _T_1284 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = leq(uncommonBits_53, UInt<3>(0h4))
node _T_1287 = and(_T_1285, _T_1286)
node _T_1288 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1289 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1290 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1291 = or(_T_1243, _T_1249)
node _T_1292 = or(_T_1291, _T_1255)
node _T_1293 = or(_T_1292, _T_1261)
node _T_1294 = or(_T_1293, _T_1267)
node _T_1295 = or(_T_1294, _T_1268)
node _T_1296 = or(_T_1295, _T_1269)
node _T_1297 = or(_T_1296, _T_1270)
node _T_1298 = or(_T_1297, _T_1271)
node _T_1299 = or(_T_1298, _T_1272)
node _T_1300 = or(_T_1299, _T_1273)
node _T_1301 = or(_T_1300, _T_1279)
node _T_1302 = or(_T_1301, _T_1280)
node _T_1303 = or(_T_1302, _T_1281)
node _T_1304 = or(_T_1303, _T_1287)
node _T_1305 = or(_T_1304, _T_1288)
node _T_1306 = or(_T_1305, _T_1289)
node _T_1307 = or(_T_1306, _T_1290)
node _T_1308 = and(_T_1242, _T_1307)
node _T_1309 = or(UInt<1>(0h0), _T_1308)
node _T_1310 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1311 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1312 = and(_T_1310, _T_1311)
node _T_1313 = or(UInt<1>(0h0), _T_1312)
node _T_1314 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1315 = cvt(_T_1314)
node _T_1316 = and(_T_1315, asSInt(UInt<15>(0h5000)))
node _T_1317 = asSInt(_T_1316)
node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0)))
node _T_1319 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1320 = cvt(_T_1319)
node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000)))
node _T_1322 = asSInt(_T_1321)
node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0)))
node _T_1324 = or(_T_1318, _T_1323)
node _T_1325 = and(_T_1313, _T_1324)
node _T_1326 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1327 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1328 = cvt(_T_1327)
node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000)))
node _T_1330 = asSInt(_T_1329)
node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0)))
node _T_1332 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1333 = cvt(_T_1332)
node _T_1334 = and(_T_1333, asSInt(UInt<17>(0h10000)))
node _T_1335 = asSInt(_T_1334)
node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0)))
node _T_1337 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1338 = cvt(_T_1337)
node _T_1339 = and(_T_1338, asSInt(UInt<18>(0h2f000)))
node _T_1340 = asSInt(_T_1339)
node _T_1341 = eq(_T_1340, asSInt(UInt<1>(0h0)))
node _T_1342 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1343 = cvt(_T_1342)
node _T_1344 = and(_T_1343, asSInt(UInt<17>(0h10000)))
node _T_1345 = asSInt(_T_1344)
node _T_1346 = eq(_T_1345, asSInt(UInt<1>(0h0)))
node _T_1347 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1348 = cvt(_T_1347)
node _T_1349 = and(_T_1348, asSInt(UInt<13>(0h1000)))
node _T_1350 = asSInt(_T_1349)
node _T_1351 = eq(_T_1350, asSInt(UInt<1>(0h0)))
node _T_1352 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1353 = cvt(_T_1352)
node _T_1354 = and(_T_1353, asSInt(UInt<27>(0h4000000)))
node _T_1355 = asSInt(_T_1354)
node _T_1356 = eq(_T_1355, asSInt(UInt<1>(0h0)))
node _T_1357 = or(_T_1331, _T_1336)
node _T_1358 = or(_T_1357, _T_1341)
node _T_1359 = or(_T_1358, _T_1346)
node _T_1360 = or(_T_1359, _T_1351)
node _T_1361 = or(_T_1360, _T_1356)
node _T_1362 = and(_T_1326, _T_1361)
node _T_1363 = or(UInt<1>(0h0), _T_1325)
node _T_1364 = or(_T_1363, _T_1362)
node _T_1365 = and(_T_1309, _T_1364)
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_36
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(source_ok, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(is_aligned, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1375 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_39
node _T_1379 = eq(io.in.a.bits.mask, mask)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_40
node _T_1383 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1383 :
node _T_1384 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1385 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1386 = and(_T_1384, _T_1385)
node _T_1387 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_1388 = shr(io.in.a.bits.source, 2)
node _T_1389 = eq(_T_1388, UInt<1>(0h0))
node _T_1390 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1391 = and(_T_1389, _T_1390)
node _T_1392 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_1393 = and(_T_1391, _T_1392)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1394 = shr(io.in.a.bits.source, 2)
node _T_1395 = eq(_T_1394, UInt<1>(0h1))
node _T_1396 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1397 = and(_T_1395, _T_1396)
node _T_1398 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1399 = and(_T_1397, _T_1398)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1400 = shr(io.in.a.bits.source, 2)
node _T_1401 = eq(_T_1400, UInt<2>(0h2))
node _T_1402 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1403 = and(_T_1401, _T_1402)
node _T_1404 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1405 = and(_T_1403, _T_1404)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1406 = shr(io.in.a.bits.source, 2)
node _T_1407 = eq(_T_1406, UInt<2>(0h3))
node _T_1408 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1409 = and(_T_1407, _T_1408)
node _T_1410 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1411 = and(_T_1409, _T_1410)
node _T_1412 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1413 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1414 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1415 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1416 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1417 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 2, 0)
node _T_1418 = shr(io.in.a.bits.source, 3)
node _T_1419 = eq(_T_1418, UInt<3>(0h6))
node _T_1420 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1421 = and(_T_1419, _T_1420)
node _T_1422 = leq(uncommonBits_58, UInt<3>(0h4))
node _T_1423 = and(_T_1421, _T_1422)
node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0)
node _T_1426 = shr(io.in.a.bits.source, 3)
node _T_1427 = eq(_T_1426, UInt<3>(0h4))
node _T_1428 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1429 = and(_T_1427, _T_1428)
node _T_1430 = leq(uncommonBits_59, UInt<3>(0h4))
node _T_1431 = and(_T_1429, _T_1430)
node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1434 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1435 = or(_T_1387, _T_1393)
node _T_1436 = or(_T_1435, _T_1399)
node _T_1437 = or(_T_1436, _T_1405)
node _T_1438 = or(_T_1437, _T_1411)
node _T_1439 = or(_T_1438, _T_1412)
node _T_1440 = or(_T_1439, _T_1413)
node _T_1441 = or(_T_1440, _T_1414)
node _T_1442 = or(_T_1441, _T_1415)
node _T_1443 = or(_T_1442, _T_1416)
node _T_1444 = or(_T_1443, _T_1417)
node _T_1445 = or(_T_1444, _T_1423)
node _T_1446 = or(_T_1445, _T_1424)
node _T_1447 = or(_T_1446, _T_1425)
node _T_1448 = or(_T_1447, _T_1431)
node _T_1449 = or(_T_1448, _T_1432)
node _T_1450 = or(_T_1449, _T_1433)
node _T_1451 = or(_T_1450, _T_1434)
node _T_1452 = and(_T_1386, _T_1451)
node _T_1453 = or(UInt<1>(0h0), _T_1452)
node _T_1454 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1455 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1456 = and(_T_1454, _T_1455)
node _T_1457 = or(UInt<1>(0h0), _T_1456)
node _T_1458 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1459 = cvt(_T_1458)
node _T_1460 = and(_T_1459, asSInt(UInt<15>(0h5000)))
node _T_1461 = asSInt(_T_1460)
node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0)))
node _T_1463 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1464 = cvt(_T_1463)
node _T_1465 = and(_T_1464, asSInt(UInt<13>(0h1000)))
node _T_1466 = asSInt(_T_1465)
node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0)))
node _T_1468 = or(_T_1462, _T_1467)
node _T_1469 = and(_T_1457, _T_1468)
node _T_1470 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1471 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1472 = cvt(_T_1471)
node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000)))
node _T_1474 = asSInt(_T_1473)
node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0)))
node _T_1476 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1477 = cvt(_T_1476)
node _T_1478 = and(_T_1477, asSInt(UInt<17>(0h10000)))
node _T_1479 = asSInt(_T_1478)
node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0)))
node _T_1481 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1482 = cvt(_T_1481)
node _T_1483 = and(_T_1482, asSInt(UInt<18>(0h2f000)))
node _T_1484 = asSInt(_T_1483)
node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0)))
node _T_1486 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1487 = cvt(_T_1486)
node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000)))
node _T_1489 = asSInt(_T_1488)
node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0)))
node _T_1491 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1492 = cvt(_T_1491)
node _T_1493 = and(_T_1492, asSInt(UInt<13>(0h1000)))
node _T_1494 = asSInt(_T_1493)
node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0)))
node _T_1496 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1497 = cvt(_T_1496)
node _T_1498 = and(_T_1497, asSInt(UInt<27>(0h4000000)))
node _T_1499 = asSInt(_T_1498)
node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0)))
node _T_1501 = or(_T_1475, _T_1480)
node _T_1502 = or(_T_1501, _T_1485)
node _T_1503 = or(_T_1502, _T_1490)
node _T_1504 = or(_T_1503, _T_1495)
node _T_1505 = or(_T_1504, _T_1500)
node _T_1506 = and(_T_1470, _T_1505)
node _T_1507 = or(UInt<1>(0h0), _T_1469)
node _T_1508 = or(_T_1507, _T_1506)
node _T_1509 = and(_T_1453, _T_1508)
node _T_1510 = asUInt(reset)
node _T_1511 = eq(_T_1510, UInt<1>(0h0))
when _T_1511 :
node _T_1512 = eq(_T_1509, UInt<1>(0h0))
when _T_1512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1509, UInt<1>(0h1), "") : assert_41
node _T_1513 = asUInt(reset)
node _T_1514 = eq(_T_1513, UInt<1>(0h0))
when _T_1514 :
node _T_1515 = eq(source_ok, UInt<1>(0h0))
when _T_1515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(is_aligned, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1519 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_44
node _T_1523 = eq(io.in.a.bits.mask, mask)
node _T_1524 = asUInt(reset)
node _T_1525 = eq(_T_1524, UInt<1>(0h0))
when _T_1525 :
node _T_1526 = eq(_T_1523, UInt<1>(0h0))
when _T_1526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1523, UInt<1>(0h1), "") : assert_45
node _T_1527 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1527 :
node _T_1528 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1529 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1530 = and(_T_1528, _T_1529)
node _T_1531 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1532 = shr(io.in.a.bits.source, 2)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
node _T_1534 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1535 = and(_T_1533, _T_1534)
node _T_1536 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1537 = and(_T_1535, _T_1536)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1538 = shr(io.in.a.bits.source, 2)
node _T_1539 = eq(_T_1538, UInt<1>(0h1))
node _T_1540 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1541 = and(_T_1539, _T_1540)
node _T_1542 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1543 = and(_T_1541, _T_1542)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1544 = shr(io.in.a.bits.source, 2)
node _T_1545 = eq(_T_1544, UInt<2>(0h2))
node _T_1546 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1547 = and(_T_1545, _T_1546)
node _T_1548 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1549 = and(_T_1547, _T_1548)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1550 = shr(io.in.a.bits.source, 2)
node _T_1551 = eq(_T_1550, UInt<2>(0h3))
node _T_1552 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1553 = and(_T_1551, _T_1552)
node _T_1554 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1555 = and(_T_1553, _T_1554)
node _T_1556 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1557 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1558 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1559 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1560 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1561 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0)
node _T_1562 = shr(io.in.a.bits.source, 3)
node _T_1563 = eq(_T_1562, UInt<3>(0h6))
node _T_1564 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1565 = and(_T_1563, _T_1564)
node _T_1566 = leq(uncommonBits_64, UInt<3>(0h4))
node _T_1567 = and(_T_1565, _T_1566)
node _T_1568 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1569 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 2, 0)
node _T_1570 = shr(io.in.a.bits.source, 3)
node _T_1571 = eq(_T_1570, UInt<3>(0h4))
node _T_1572 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1573 = and(_T_1571, _T_1572)
node _T_1574 = leq(uncommonBits_65, UInt<3>(0h4))
node _T_1575 = and(_T_1573, _T_1574)
node _T_1576 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1577 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1578 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1579 = or(_T_1531, _T_1537)
node _T_1580 = or(_T_1579, _T_1543)
node _T_1581 = or(_T_1580, _T_1549)
node _T_1582 = or(_T_1581, _T_1555)
node _T_1583 = or(_T_1582, _T_1556)
node _T_1584 = or(_T_1583, _T_1557)
node _T_1585 = or(_T_1584, _T_1558)
node _T_1586 = or(_T_1585, _T_1559)
node _T_1587 = or(_T_1586, _T_1560)
node _T_1588 = or(_T_1587, _T_1561)
node _T_1589 = or(_T_1588, _T_1567)
node _T_1590 = or(_T_1589, _T_1568)
node _T_1591 = or(_T_1590, _T_1569)
node _T_1592 = or(_T_1591, _T_1575)
node _T_1593 = or(_T_1592, _T_1576)
node _T_1594 = or(_T_1593, _T_1577)
node _T_1595 = or(_T_1594, _T_1578)
node _T_1596 = and(_T_1530, _T_1595)
node _T_1597 = or(UInt<1>(0h0), _T_1596)
node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1600 = and(_T_1598, _T_1599)
node _T_1601 = or(UInt<1>(0h0), _T_1600)
node _T_1602 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1603 = cvt(_T_1602)
node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000)))
node _T_1605 = asSInt(_T_1604)
node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0)))
node _T_1607 = and(_T_1601, _T_1606)
node _T_1608 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1609 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1610 = cvt(_T_1609)
node _T_1611 = and(_T_1610, asSInt(UInt<14>(0h2000)))
node _T_1612 = asSInt(_T_1611)
node _T_1613 = eq(_T_1612, asSInt(UInt<1>(0h0)))
node _T_1614 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1615 = cvt(_T_1614)
node _T_1616 = and(_T_1615, asSInt(UInt<17>(0h10000)))
node _T_1617 = asSInt(_T_1616)
node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0)))
node _T_1619 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1620 = cvt(_T_1619)
node _T_1621 = and(_T_1620, asSInt(UInt<18>(0h2f000)))
node _T_1622 = asSInt(_T_1621)
node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0)))
node _T_1624 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1625 = cvt(_T_1624)
node _T_1626 = and(_T_1625, asSInt(UInt<17>(0h10000)))
node _T_1627 = asSInt(_T_1626)
node _T_1628 = eq(_T_1627, asSInt(UInt<1>(0h0)))
node _T_1629 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1630 = cvt(_T_1629)
node _T_1631 = and(_T_1630, asSInt(UInt<13>(0h1000)))
node _T_1632 = asSInt(_T_1631)
node _T_1633 = eq(_T_1632, asSInt(UInt<1>(0h0)))
node _T_1634 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1635 = cvt(_T_1634)
node _T_1636 = and(_T_1635, asSInt(UInt<27>(0h4000000)))
node _T_1637 = asSInt(_T_1636)
node _T_1638 = eq(_T_1637, asSInt(UInt<1>(0h0)))
node _T_1639 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1640 = cvt(_T_1639)
node _T_1641 = and(_T_1640, asSInt(UInt<13>(0h1000)))
node _T_1642 = asSInt(_T_1641)
node _T_1643 = eq(_T_1642, asSInt(UInt<1>(0h0)))
node _T_1644 = or(_T_1613, _T_1618)
node _T_1645 = or(_T_1644, _T_1623)
node _T_1646 = or(_T_1645, _T_1628)
node _T_1647 = or(_T_1646, _T_1633)
node _T_1648 = or(_T_1647, _T_1638)
node _T_1649 = or(_T_1648, _T_1643)
node _T_1650 = and(_T_1608, _T_1649)
node _T_1651 = or(UInt<1>(0h0), _T_1607)
node _T_1652 = or(_T_1651, _T_1650)
node _T_1653 = and(_T_1597, _T_1652)
node _T_1654 = asUInt(reset)
node _T_1655 = eq(_T_1654, UInt<1>(0h0))
when _T_1655 :
node _T_1656 = eq(_T_1653, UInt<1>(0h0))
when _T_1656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1653, UInt<1>(0h1), "") : assert_46
node _T_1657 = asUInt(reset)
node _T_1658 = eq(_T_1657, UInt<1>(0h0))
when _T_1658 :
node _T_1659 = eq(source_ok, UInt<1>(0h0))
when _T_1659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1660 = asUInt(reset)
node _T_1661 = eq(_T_1660, UInt<1>(0h0))
when _T_1661 :
node _T_1662 = eq(is_aligned, UInt<1>(0h0))
when _T_1662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1663 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1664 = asUInt(reset)
node _T_1665 = eq(_T_1664, UInt<1>(0h0))
when _T_1665 :
node _T_1666 = eq(_T_1663, UInt<1>(0h0))
when _T_1666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1663, UInt<1>(0h1), "") : assert_49
node _T_1667 = eq(io.in.a.bits.mask, mask)
node _T_1668 = asUInt(reset)
node _T_1669 = eq(_T_1668, UInt<1>(0h0))
when _T_1669 :
node _T_1670 = eq(_T_1667, UInt<1>(0h0))
when _T_1670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1667, UInt<1>(0h1), "") : assert_50
node _T_1671 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1672 = asUInt(reset)
node _T_1673 = eq(_T_1672, UInt<1>(0h0))
when _T_1673 :
node _T_1674 = eq(_T_1671, UInt<1>(0h0))
when _T_1674 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1671, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1675 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(_T_1675, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1675, UInt<1>(0h1), "") : assert_52
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h0))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h2))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_83 = shr(io.in.d.bits.source, 2)
node _source_ok_T_84 = eq(_source_ok_T_83, UInt<2>(0h3))
node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h44))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<7>(0h45))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h46))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 2, 0)
node _source_ok_T_95 = shr(io.in.d.bits.source, 3)
node _source_ok_T_96 = eq(_source_ok_T_95, UInt<3>(0h6))
node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_T_99 = leq(source_ok_uncommonBits_10, UInt<3>(0h4))
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_103 = shr(io.in.d.bits.source, 3)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_11, UInt<3>(0h4))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[18]
connect _source_ok_WIRE_1[0], _source_ok_T_64
connect _source_ok_WIRE_1[1], _source_ok_T_70
connect _source_ok_WIRE_1[2], _source_ok_T_76
connect _source_ok_WIRE_1[3], _source_ok_T_82
connect _source_ok_WIRE_1[4], _source_ok_T_88
connect _source_ok_WIRE_1[5], _source_ok_T_89
connect _source_ok_WIRE_1[6], _source_ok_T_90
connect _source_ok_WIRE_1[7], _source_ok_T_91
connect _source_ok_WIRE_1[8], _source_ok_T_92
connect _source_ok_WIRE_1[9], _source_ok_T_93
connect _source_ok_WIRE_1[10], _source_ok_T_94
connect _source_ok_WIRE_1[11], _source_ok_T_100
connect _source_ok_WIRE_1[12], _source_ok_T_101
connect _source_ok_WIRE_1[13], _source_ok_T_102
connect _source_ok_WIRE_1[14], _source_ok_T_108
connect _source_ok_WIRE_1[15], _source_ok_T_109
connect _source_ok_WIRE_1[16], _source_ok_T_110
connect _source_ok_WIRE_1[17], _source_ok_T_111
node _source_ok_T_112 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[2])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[3])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[4])
node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[5])
node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[6])
node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[7])
node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[8])
node _source_ok_T_120 = or(_source_ok_T_119, _source_ok_WIRE_1[9])
node _source_ok_T_121 = or(_source_ok_T_120, _source_ok_WIRE_1[10])
node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_1[11])
node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_1[12])
node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_1[13])
node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_1[14])
node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[15])
node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[16])
node source_ok_1 = or(_source_ok_T_127, _source_ok_WIRE_1[17])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1679 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1679 :
node _T_1680 = asUInt(reset)
node _T_1681 = eq(_T_1680, UInt<1>(0h0))
when _T_1681 :
node _T_1682 = eq(source_ok_1, UInt<1>(0h0))
when _T_1682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1683 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1684 = asUInt(reset)
node _T_1685 = eq(_T_1684, UInt<1>(0h0))
when _T_1685 :
node _T_1686 = eq(_T_1683, UInt<1>(0h0))
when _T_1686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1683, UInt<1>(0h1), "") : assert_54
node _T_1687 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1688 = asUInt(reset)
node _T_1689 = eq(_T_1688, UInt<1>(0h0))
when _T_1689 :
node _T_1690 = eq(_T_1687, UInt<1>(0h0))
when _T_1690 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1687, UInt<1>(0h1), "") : assert_55
node _T_1691 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_56
node _T_1695 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_57
node _T_1699 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1699 :
node _T_1700 = asUInt(reset)
node _T_1701 = eq(_T_1700, UInt<1>(0h0))
when _T_1701 :
node _T_1702 = eq(source_ok_1, UInt<1>(0h0))
when _T_1702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1703 = asUInt(reset)
node _T_1704 = eq(_T_1703, UInt<1>(0h0))
when _T_1704 :
node _T_1705 = eq(sink_ok, UInt<1>(0h0))
when _T_1705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1706 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1707 = asUInt(reset)
node _T_1708 = eq(_T_1707, UInt<1>(0h0))
when _T_1708 :
node _T_1709 = eq(_T_1706, UInt<1>(0h0))
when _T_1709 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1706, UInt<1>(0h1), "") : assert_60
node _T_1710 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1711 = asUInt(reset)
node _T_1712 = eq(_T_1711, UInt<1>(0h0))
when _T_1712 :
node _T_1713 = eq(_T_1710, UInt<1>(0h0))
when _T_1713 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1710, UInt<1>(0h1), "") : assert_61
node _T_1714 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(_T_1714, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1714, UInt<1>(0h1), "") : assert_62
node _T_1718 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1719 = asUInt(reset)
node _T_1720 = eq(_T_1719, UInt<1>(0h0))
when _T_1720 :
node _T_1721 = eq(_T_1718, UInt<1>(0h0))
when _T_1721 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1718, UInt<1>(0h1), "") : assert_63
node _T_1722 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1723 = or(UInt<1>(0h1), _T_1722)
node _T_1724 = asUInt(reset)
node _T_1725 = eq(_T_1724, UInt<1>(0h0))
when _T_1725 :
node _T_1726 = eq(_T_1723, UInt<1>(0h0))
when _T_1726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1723, UInt<1>(0h1), "") : assert_64
node _T_1727 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1727 :
node _T_1728 = asUInt(reset)
node _T_1729 = eq(_T_1728, UInt<1>(0h0))
when _T_1729 :
node _T_1730 = eq(source_ok_1, UInt<1>(0h0))
when _T_1730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1731 = asUInt(reset)
node _T_1732 = eq(_T_1731, UInt<1>(0h0))
when _T_1732 :
node _T_1733 = eq(sink_ok, UInt<1>(0h0))
when _T_1733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1734 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1735 = asUInt(reset)
node _T_1736 = eq(_T_1735, UInt<1>(0h0))
when _T_1736 :
node _T_1737 = eq(_T_1734, UInt<1>(0h0))
when _T_1737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1734, UInt<1>(0h1), "") : assert_67
node _T_1738 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1739 = asUInt(reset)
node _T_1740 = eq(_T_1739, UInt<1>(0h0))
when _T_1740 :
node _T_1741 = eq(_T_1738, UInt<1>(0h0))
when _T_1741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1738, UInt<1>(0h1), "") : assert_68
node _T_1742 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1743 = asUInt(reset)
node _T_1744 = eq(_T_1743, UInt<1>(0h0))
when _T_1744 :
node _T_1745 = eq(_T_1742, UInt<1>(0h0))
when _T_1745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1742, UInt<1>(0h1), "") : assert_69
node _T_1746 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1747 = or(_T_1746, io.in.d.bits.corrupt)
node _T_1748 = asUInt(reset)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
when _T_1749 :
node _T_1750 = eq(_T_1747, UInt<1>(0h0))
when _T_1750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1747, UInt<1>(0h1), "") : assert_70
node _T_1751 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1752 = or(UInt<1>(0h1), _T_1751)
node _T_1753 = asUInt(reset)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
when _T_1754 :
node _T_1755 = eq(_T_1752, UInt<1>(0h0))
when _T_1755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1752, UInt<1>(0h1), "") : assert_71
node _T_1756 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1756 :
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(source_ok_1, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1760 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1761 = asUInt(reset)
node _T_1762 = eq(_T_1761, UInt<1>(0h0))
when _T_1762 :
node _T_1763 = eq(_T_1760, UInt<1>(0h0))
when _T_1763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1760, UInt<1>(0h1), "") : assert_73
node _T_1764 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1765 = asUInt(reset)
node _T_1766 = eq(_T_1765, UInt<1>(0h0))
when _T_1766 :
node _T_1767 = eq(_T_1764, UInt<1>(0h0))
when _T_1767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1764, UInt<1>(0h1), "") : assert_74
node _T_1768 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1769 = or(UInt<1>(0h1), _T_1768)
node _T_1770 = asUInt(reset)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
when _T_1771 :
node _T_1772 = eq(_T_1769, UInt<1>(0h0))
when _T_1772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1769, UInt<1>(0h1), "") : assert_75
node _T_1773 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1773 :
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(source_ok_1, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1777 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1778 = asUInt(reset)
node _T_1779 = eq(_T_1778, UInt<1>(0h0))
when _T_1779 :
node _T_1780 = eq(_T_1777, UInt<1>(0h0))
when _T_1780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1777, UInt<1>(0h1), "") : assert_77
node _T_1781 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1782 = or(_T_1781, io.in.d.bits.corrupt)
node _T_1783 = asUInt(reset)
node _T_1784 = eq(_T_1783, UInt<1>(0h0))
when _T_1784 :
node _T_1785 = eq(_T_1782, UInt<1>(0h0))
when _T_1785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1782, UInt<1>(0h1), "") : assert_78
node _T_1786 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1787 = or(UInt<1>(0h1), _T_1786)
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(_T_1787, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1787, UInt<1>(0h1), "") : assert_79
node _T_1791 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1791 :
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(source_ok_1, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1795 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_81
node _T_1799 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_82
node _T_1803 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1804 = or(UInt<1>(0h1), _T_1803)
node _T_1805 = asUInt(reset)
node _T_1806 = eq(_T_1805, UInt<1>(0h0))
when _T_1806 :
node _T_1807 = eq(_T_1804, UInt<1>(0h0))
when _T_1807 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1804, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1808 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1809 = asUInt(reset)
node _T_1810 = eq(_T_1809, UInt<1>(0h0))
when _T_1810 :
node _T_1811 = eq(_T_1808, UInt<1>(0h0))
when _T_1811 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1808, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1812 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1813 = asUInt(reset)
node _T_1814 = eq(_T_1813, UInt<1>(0h0))
when _T_1814 :
node _T_1815 = eq(_T_1812, UInt<1>(0h0))
when _T_1815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1812, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1816 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1817 = asUInt(reset)
node _T_1818 = eq(_T_1817, UInt<1>(0h0))
when _T_1818 :
node _T_1819 = eq(_T_1816, UInt<1>(0h0))
when _T_1819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1816, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1820 = eq(a_first, UInt<1>(0h0))
node _T_1821 = and(io.in.a.valid, _T_1820)
when _T_1821 :
node _T_1822 = eq(io.in.a.bits.opcode, opcode)
node _T_1823 = asUInt(reset)
node _T_1824 = eq(_T_1823, UInt<1>(0h0))
when _T_1824 :
node _T_1825 = eq(_T_1822, UInt<1>(0h0))
when _T_1825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1822, UInt<1>(0h1), "") : assert_87
node _T_1826 = eq(io.in.a.bits.param, param)
node _T_1827 = asUInt(reset)
node _T_1828 = eq(_T_1827, UInt<1>(0h0))
when _T_1828 :
node _T_1829 = eq(_T_1826, UInt<1>(0h0))
when _T_1829 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1826, UInt<1>(0h1), "") : assert_88
node _T_1830 = eq(io.in.a.bits.size, size)
node _T_1831 = asUInt(reset)
node _T_1832 = eq(_T_1831, UInt<1>(0h0))
when _T_1832 :
node _T_1833 = eq(_T_1830, UInt<1>(0h0))
when _T_1833 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1830, UInt<1>(0h1), "") : assert_89
node _T_1834 = eq(io.in.a.bits.source, source)
node _T_1835 = asUInt(reset)
node _T_1836 = eq(_T_1835, UInt<1>(0h0))
when _T_1836 :
node _T_1837 = eq(_T_1834, UInt<1>(0h0))
when _T_1837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1834, UInt<1>(0h1), "") : assert_90
node _T_1838 = eq(io.in.a.bits.address, address)
node _T_1839 = asUInt(reset)
node _T_1840 = eq(_T_1839, UInt<1>(0h0))
when _T_1840 :
node _T_1841 = eq(_T_1838, UInt<1>(0h0))
when _T_1841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1838, UInt<1>(0h1), "") : assert_91
node _T_1842 = and(io.in.a.ready, io.in.a.valid)
node _T_1843 = and(_T_1842, a_first)
when _T_1843 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1844 = eq(d_first, UInt<1>(0h0))
node _T_1845 = and(io.in.d.valid, _T_1844)
when _T_1845 :
node _T_1846 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(_T_1846, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1846, UInt<1>(0h1), "") : assert_92
node _T_1850 = eq(io.in.d.bits.param, param_1)
node _T_1851 = asUInt(reset)
node _T_1852 = eq(_T_1851, UInt<1>(0h0))
when _T_1852 :
node _T_1853 = eq(_T_1850, UInt<1>(0h0))
when _T_1853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1850, UInt<1>(0h1), "") : assert_93
node _T_1854 = eq(io.in.d.bits.size, size_1)
node _T_1855 = asUInt(reset)
node _T_1856 = eq(_T_1855, UInt<1>(0h0))
when _T_1856 :
node _T_1857 = eq(_T_1854, UInt<1>(0h0))
when _T_1857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1854, UInt<1>(0h1), "") : assert_94
node _T_1858 = eq(io.in.d.bits.source, source_1)
node _T_1859 = asUInt(reset)
node _T_1860 = eq(_T_1859, UInt<1>(0h0))
when _T_1860 :
node _T_1861 = eq(_T_1858, UInt<1>(0h0))
when _T_1861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1858, UInt<1>(0h1), "") : assert_95
node _T_1862 = eq(io.in.d.bits.sink, sink)
node _T_1863 = asUInt(reset)
node _T_1864 = eq(_T_1863, UInt<1>(0h0))
when _T_1864 :
node _T_1865 = eq(_T_1862, UInt<1>(0h0))
when _T_1865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1862, UInt<1>(0h1), "") : assert_96
node _T_1866 = eq(io.in.d.bits.denied, denied)
node _T_1867 = asUInt(reset)
node _T_1868 = eq(_T_1867, UInt<1>(0h0))
when _T_1868 :
node _T_1869 = eq(_T_1866, UInt<1>(0h0))
when _T_1869 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1866, UInt<1>(0h1), "") : assert_97
node _T_1870 = and(io.in.d.ready, io.in.d.valid)
node _T_1871 = and(_T_1870, d_first)
when _T_1871 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<1032>
connect a_sizes_set, UInt<1032>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1872 = and(io.in.a.valid, a_first_1)
node _T_1873 = and(_T_1872, UInt<1>(0h1))
when _T_1873 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1874 = and(io.in.a.ready, io.in.a.valid)
node _T_1875 = and(_T_1874, a_first_1)
node _T_1876 = and(_T_1875, UInt<1>(0h1))
when _T_1876 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1877 = dshr(inflight, io.in.a.bits.source)
node _T_1878 = bits(_T_1877, 0, 0)
node _T_1879 = eq(_T_1878, UInt<1>(0h0))
node _T_1880 = asUInt(reset)
node _T_1881 = eq(_T_1880, UInt<1>(0h0))
when _T_1881 :
node _T_1882 = eq(_T_1879, UInt<1>(0h0))
when _T_1882 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1879, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<1032>
connect d_sizes_clr, UInt<1032>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1883 = and(io.in.d.valid, d_first_1)
node _T_1884 = and(_T_1883, UInt<1>(0h1))
node _T_1885 = eq(d_release_ack, UInt<1>(0h0))
node _T_1886 = and(_T_1884, _T_1885)
when _T_1886 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1887 = and(io.in.d.ready, io.in.d.valid)
node _T_1888 = and(_T_1887, d_first_1)
node _T_1889 = and(_T_1888, UInt<1>(0h1))
node _T_1890 = eq(d_release_ack, UInt<1>(0h0))
node _T_1891 = and(_T_1889, _T_1890)
when _T_1891 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1892 = and(io.in.d.valid, d_first_1)
node _T_1893 = and(_T_1892, UInt<1>(0h1))
node _T_1894 = eq(d_release_ack, UInt<1>(0h0))
node _T_1895 = and(_T_1893, _T_1894)
when _T_1895 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1896 = dshr(inflight, io.in.d.bits.source)
node _T_1897 = bits(_T_1896, 0, 0)
node _T_1898 = or(_T_1897, same_cycle_resp)
node _T_1899 = asUInt(reset)
node _T_1900 = eq(_T_1899, UInt<1>(0h0))
when _T_1900 :
node _T_1901 = eq(_T_1898, UInt<1>(0h0))
when _T_1901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1898, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1902 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1903 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1904 = or(_T_1902, _T_1903)
node _T_1905 = asUInt(reset)
node _T_1906 = eq(_T_1905, UInt<1>(0h0))
when _T_1906 :
node _T_1907 = eq(_T_1904, UInt<1>(0h0))
when _T_1907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1904, UInt<1>(0h1), "") : assert_100
node _T_1908 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1909 = asUInt(reset)
node _T_1910 = eq(_T_1909, UInt<1>(0h0))
when _T_1910 :
node _T_1911 = eq(_T_1908, UInt<1>(0h0))
when _T_1911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1908, UInt<1>(0h1), "") : assert_101
else :
node _T_1912 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1913 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1914 = or(_T_1912, _T_1913)
node _T_1915 = asUInt(reset)
node _T_1916 = eq(_T_1915, UInt<1>(0h0))
when _T_1916 :
node _T_1917 = eq(_T_1914, UInt<1>(0h0))
when _T_1917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1914, UInt<1>(0h1), "") : assert_102
node _T_1918 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1919 = asUInt(reset)
node _T_1920 = eq(_T_1919, UInt<1>(0h0))
when _T_1920 :
node _T_1921 = eq(_T_1918, UInt<1>(0h0))
when _T_1921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1918, UInt<1>(0h1), "") : assert_103
node _T_1922 = and(io.in.d.valid, d_first_1)
node _T_1923 = and(_T_1922, a_first_1)
node _T_1924 = and(_T_1923, io.in.a.valid)
node _T_1925 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1926 = and(_T_1924, _T_1925)
node _T_1927 = eq(d_release_ack, UInt<1>(0h0))
node _T_1928 = and(_T_1926, _T_1927)
when _T_1928 :
node _T_1929 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1930 = or(_T_1929, io.in.a.ready)
node _T_1931 = asUInt(reset)
node _T_1932 = eq(_T_1931, UInt<1>(0h0))
when _T_1932 :
node _T_1933 = eq(_T_1930, UInt<1>(0h0))
when _T_1933 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1930, UInt<1>(0h1), "") : assert_104
node _T_1934 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1935 = orr(a_set_wo_ready)
node _T_1936 = eq(_T_1935, UInt<1>(0h0))
node _T_1937 = or(_T_1934, _T_1936)
node _T_1938 = asUInt(reset)
node _T_1939 = eq(_T_1938, UInt<1>(0h0))
when _T_1939 :
node _T_1940 = eq(_T_1937, UInt<1>(0h0))
when _T_1940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1937, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_44
node _T_1941 = orr(inflight)
node _T_1942 = eq(_T_1941, UInt<1>(0h0))
node _T_1943 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1944 = or(_T_1942, _T_1943)
node _T_1945 = lt(watchdog, plusarg_reader.out)
node _T_1946 = or(_T_1944, _T_1945)
node _T_1947 = asUInt(reset)
node _T_1948 = eq(_T_1947, UInt<1>(0h0))
when _T_1948 :
node _T_1949 = eq(_T_1946, UInt<1>(0h0))
when _T_1949 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1946, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1950 = and(io.in.a.ready, io.in.a.valid)
node _T_1951 = and(io.in.d.ready, io.in.d.valid)
node _T_1952 = or(_T_1950, _T_1951)
when _T_1952 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<1032>
connect c_sizes_set, UInt<1032>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1953 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1954 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1955 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1956 = and(_T_1954, _T_1955)
node _T_1957 = and(_T_1953, _T_1956)
when _T_1957 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1958 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1959 = and(_T_1958, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1960 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1961 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1962 = and(_T_1960, _T_1961)
node _T_1963 = and(_T_1959, _T_1962)
when _T_1963 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1964 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1965 = bits(_T_1964, 0, 0)
node _T_1966 = eq(_T_1965, UInt<1>(0h0))
node _T_1967 = asUInt(reset)
node _T_1968 = eq(_T_1967, UInt<1>(0h0))
when _T_1968 :
node _T_1969 = eq(_T_1966, UInt<1>(0h0))
when _T_1969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1966, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<1032>
connect d_sizes_clr_1, UInt<1032>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1970 = and(io.in.d.valid, d_first_2)
node _T_1971 = and(_T_1970, UInt<1>(0h1))
node _T_1972 = and(_T_1971, d_release_ack_1)
when _T_1972 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1973 = and(io.in.d.ready, io.in.d.valid)
node _T_1974 = and(_T_1973, d_first_2)
node _T_1975 = and(_T_1974, UInt<1>(0h1))
node _T_1976 = and(_T_1975, d_release_ack_1)
when _T_1976 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1977 = and(io.in.d.valid, d_first_2)
node _T_1978 = and(_T_1977, UInt<1>(0h1))
node _T_1979 = and(_T_1978, d_release_ack_1)
when _T_1979 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1980 = dshr(inflight_1, io.in.d.bits.source)
node _T_1981 = bits(_T_1980, 0, 0)
node _T_1982 = or(_T_1981, same_cycle_resp_1)
node _T_1983 = asUInt(reset)
node _T_1984 = eq(_T_1983, UInt<1>(0h0))
when _T_1984 :
node _T_1985 = eq(_T_1982, UInt<1>(0h0))
when _T_1985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1982, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1986 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1987 = asUInt(reset)
node _T_1988 = eq(_T_1987, UInt<1>(0h0))
when _T_1988 :
node _T_1989 = eq(_T_1986, UInt<1>(0h0))
when _T_1989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1986, UInt<1>(0h1), "") : assert_109
else :
node _T_1990 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1991 = asUInt(reset)
node _T_1992 = eq(_T_1991, UInt<1>(0h0))
when _T_1992 :
node _T_1993 = eq(_T_1990, UInt<1>(0h0))
when _T_1993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1990, UInt<1>(0h1), "") : assert_110
node _T_1994 = and(io.in.d.valid, d_first_2)
node _T_1995 = and(_T_1994, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1996 = and(_T_1995, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1997 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1998 = and(_T_1996, _T_1997)
node _T_1999 = and(_T_1998, d_release_ack_1)
node _T_2000 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2001 = and(_T_1999, _T_2000)
when _T_2001 :
node _T_2002 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_2003 = or(_T_2002, _WIRE_27.ready)
node _T_2004 = asUInt(reset)
node _T_2005 = eq(_T_2004, UInt<1>(0h0))
when _T_2005 :
node _T_2006 = eq(_T_2003, UInt<1>(0h0))
when _T_2006 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_2003, UInt<1>(0h1), "") : assert_111
node _T_2007 = orr(c_set_wo_ready)
when _T_2007 :
node _T_2008 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2009 = asUInt(reset)
node _T_2010 = eq(_T_2009, UInt<1>(0h0))
when _T_2010 :
node _T_2011 = eq(_T_2008, UInt<1>(0h0))
when _T_2011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_2008, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_45
node _T_2012 = orr(inflight_1)
node _T_2013 = eq(_T_2012, UInt<1>(0h0))
node _T_2014 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2015 = or(_T_2013, _T_2014)
node _T_2016 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2017 = or(_T_2015, _T_2016)
node _T_2018 = asUInt(reset)
node _T_2019 = eq(_T_2018, UInt<1>(0h0))
when _T_2019 :
node _T_2020 = eq(_T_2017, UInt<1>(0h0))
when _T_2020 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_2017, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_2021 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_2022 = and(io.in.d.ready, io.in.d.valid)
node _T_2023 = or(_T_2021, _T_2022)
when _T_2023 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_22( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31]
wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31]
wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1950 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1950; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1950; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_2023 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2023; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2023; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2023; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1876 = _T_1950 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1876 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1876 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1876 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1876 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1876 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1922 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1922 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1891 = _T_2023 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1891 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1891 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1891 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1994 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1994 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1976 = _T_2023 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1976 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1976 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1976 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_415 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_159
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_415( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_159 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_2 :
input clock : Clock
input reset : Reset
output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>}
node default = gt(io.prv, UInt<1>(0h1))
wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmp0_WIRE.mask, UInt<32>(0h0)
connect _pmp0_WIRE.addr, UInt<30>(0h0)
connect _pmp0_WIRE.cfg.r, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.w, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.x, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.a, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.res, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.l, UInt<1>(0h0)
wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp0, _pmp0_WIRE
connect pmp0.cfg.r, default
connect pmp0.cfg.w, default
connect pmp0.cfg.x, default
node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1)
node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0)
node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1)
node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2)
node _res_hit_msbMatch_T = shr(io.addr, 3)
node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1)
node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3))
node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3)
node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3)
node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3)
node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5)
node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6)
node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8)
node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0))
node _res_hit_lsbMatch_T = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1)
node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3))
node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3)
node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0)
node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0)
node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5)
node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6)
node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8)
node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0))
node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch)
node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0)
node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0)
node _res_hit_T_5 = not(_res_hit_T_4)
node _res_hit_msbsLess_T = shr(io.addr, 3)
node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1)
node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3))
node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3)
node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3)
node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5)
node _res_hit_msbsEqual_T = shr(io.addr, 3)
node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1)
node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3))
node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3)
node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3)
node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5)
node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0))
node _res_hit_lsbsLess_T = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5)
node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2)
node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3))
node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4)
node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0)
node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6)
node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess)
node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6)
node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0))
node _res_hit_msbsLess_T_6 = shr(io.addr, 3)
node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7)
node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3))
node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9)
node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3)
node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11)
node _res_hit_msbsEqual_T_7 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8)
node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3))
node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10)
node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3)
node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12)
node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0))
node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0))
node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9)
node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3))
node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11)
node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0)
node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13)
node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1)
node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9)
node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10)
node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11)
node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12)
node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0))
node res_ignore = and(default, _res_ignore_T)
node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0)
node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1)
node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1)
node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3)
node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3)
node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5)
node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8)
node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10)
node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0)
node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13)
node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14)
node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16)
node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1)
node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3)
node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3)
node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5)
node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8)
node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10)
node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0)
node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask)
node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14)
node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16)
node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound)
node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0)
node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T)
node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1)
node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0))
node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1)
node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned)
node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0))
node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1))
node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r)
node _res_T_6 = eq(_res_T_5, UInt<1>(0h0))
node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r)
node _res_T_8 = eq(_res_T_7, UInt<1>(0h1))
node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r)
node _res_T_10 = eq(_res_T_9, UInt<2>(0h3))
node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r)
node _res_T_12 = eq(_res_T_11, UInt<3>(0h4))
node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r)
node _res_T_14 = eq(_res_T_13, UInt<3>(0h5))
node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r)
node _res_T_16 = eq(_res_T_15, UInt<3>(0h7))
node _res_T_17 = eq(res_ignore, UInt<1>(0h0))
node _res_T_18 = and(_res_T_17, res_hit)
node _res_T_19 = and(_res_T_18, res_aligned)
node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_21 = and(_res_T_19, _res_T_20)
node _res_T_22 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_23 = and(_res_T_22, res_aligned)
node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_25 = and(_res_T_23, _res_T_24)
node _res_T_26 = eq(res_ignore, UInt<1>(0h0))
node _res_T_27 = and(_res_T_26, res_hit)
node _res_T_28 = and(_res_T_27, res_aligned)
node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_30 = and(_res_T_28, _res_T_29)
node _res_T_31 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_32 = and(_res_T_31, res_aligned)
node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_34 = and(_res_T_32, _res_T_33)
node _res_T_35 = eq(res_ignore, UInt<1>(0h0))
node _res_T_36 = and(_res_T_35, res_hit)
node _res_T_37 = and(_res_T_36, res_aligned)
node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_39 = and(_res_T_37, _res_T_38)
node _res_T_40 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_41 = and(_res_T_40, res_aligned)
node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_43 = and(_res_T_41, _res_T_42)
wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur, io.pmp[7]
node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore)
node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T)
connect res_cur.cfg.r, _res_cur_cfg_r_T_1
node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore)
node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T)
connect res_cur.cfg.w, _res_cur_cfg_w_T_1
node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore)
node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T)
connect res_cur.cfg.x, _res_cur_cfg_x_T_1
node _res_T_44 = mux(res_hit, res_cur, pmp0)
node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1)
node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0)
node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4)
node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5)
node _res_hit_msbMatch_T_10 = shr(io.addr, 3)
node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11)
node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3))
node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13)
node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3)
node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3)
node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15)
node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16)
node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18)
node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0))
node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11)
node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3))
node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13)
node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0)
node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0)
node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15)
node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16)
node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18)
node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0))
node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1)
node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0)
node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0)
node _res_hit_T_18 = not(_res_hit_T_17)
node _res_hit_msbsLess_T_12 = shr(io.addr, 3)
node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13)
node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3))
node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15)
node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3)
node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17)
node _res_hit_msbsEqual_T_14 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15)
node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3))
node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17)
node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3)
node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19)
node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0))
node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18)
node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16)
node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3))
node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18)
node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0)
node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20)
node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2)
node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19)
node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0))
node _res_hit_msbsLess_T_18 = shr(io.addr, 3)
node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19)
node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3))
node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21)
node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3)
node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23)
node _res_hit_msbsEqual_T_21 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22)
node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3))
node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24)
node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3)
node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26)
node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0))
node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0))
node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23)
node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3))
node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25)
node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0)
node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27)
node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3)
node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22)
node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23)
node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24)
node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25)
node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0))
node res_ignore_1 = and(default, _res_ignore_T_1)
node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0)
node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3)
node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18)
node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20)
node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3)
node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22)
node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25)
node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27)
node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0)
node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30)
node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31)
node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33)
node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18)
node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20)
node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3)
node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22)
node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25)
node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27)
node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0)
node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1)
node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31)
node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33)
node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1)
node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0)
node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3)
node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4)
node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0))
node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1)
node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1)
node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0))
node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1))
node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r)
node _res_T_51 = eq(_res_T_50, UInt<1>(0h0))
node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r)
node _res_T_53 = eq(_res_T_52, UInt<1>(0h1))
node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r)
node _res_T_55 = eq(_res_T_54, UInt<2>(0h3))
node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r)
node _res_T_57 = eq(_res_T_56, UInt<3>(0h4))
node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r)
node _res_T_59 = eq(_res_T_58, UInt<3>(0h5))
node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r)
node _res_T_61 = eq(_res_T_60, UInt<3>(0h7))
node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_63 = and(_res_T_62, res_hit_1)
node _res_T_64 = and(_res_T_63, res_aligned_1)
node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_66 = and(_res_T_64, _res_T_65)
node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_68 = and(_res_T_67, res_aligned_1)
node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_70 = and(_res_T_68, _res_T_69)
node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_72 = and(_res_T_71, res_hit_1)
node _res_T_73 = and(_res_T_72, res_aligned_1)
node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_75 = and(_res_T_73, _res_T_74)
node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_77 = and(_res_T_76, res_aligned_1)
node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_79 = and(_res_T_77, _res_T_78)
node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_81 = and(_res_T_80, res_hit_1)
node _res_T_82 = and(_res_T_81, res_aligned_1)
node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_84 = and(_res_T_82, _res_T_83)
node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_86 = and(_res_T_85, res_aligned_1)
node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_88 = and(_res_T_86, _res_T_87)
wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_1, io.pmp[6]
node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1)
node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2)
connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3
node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1)
node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2)
connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3
node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1)
node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2)
connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3
node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44)
node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1)
node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0)
node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7)
node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8)
node _res_hit_msbMatch_T_20 = shr(io.addr, 3)
node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21)
node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3))
node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23)
node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3)
node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3)
node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25)
node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26)
node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28)
node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0))
node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21)
node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3))
node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23)
node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0)
node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0)
node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25)
node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26)
node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28)
node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0))
node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2)
node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0)
node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0)
node _res_hit_T_31 = not(_res_hit_T_30)
node _res_hit_msbsLess_T_24 = shr(io.addr, 3)
node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25)
node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3))
node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27)
node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3)
node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29)
node _res_hit_msbsEqual_T_28 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29)
node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3))
node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31)
node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3)
node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33)
node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0))
node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31)
node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30)
node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3))
node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32)
node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0)
node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34)
node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4)
node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32)
node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0))
node _res_hit_msbsLess_T_30 = shr(io.addr, 3)
node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31)
node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3))
node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33)
node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3)
node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35)
node _res_hit_msbsEqual_T_35 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36)
node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3))
node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38)
node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3)
node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40)
node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0))
node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0))
node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37)
node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3))
node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39)
node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0)
node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41)
node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5)
node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35)
node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36)
node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37)
node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38)
node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0))
node res_ignore_2 = and(default, _res_ignore_T_2)
node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0)
node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5)
node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35)
node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37)
node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3)
node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39)
node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42)
node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44)
node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0)
node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47)
node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48)
node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50)
node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35)
node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37)
node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3)
node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39)
node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42)
node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44)
node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0)
node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2)
node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48)
node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50)
node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2)
node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0)
node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6)
node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7)
node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0))
node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1)
node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2)
node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0))
node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1))
node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r)
node _res_T_96 = eq(_res_T_95, UInt<1>(0h0))
node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r)
node _res_T_98 = eq(_res_T_97, UInt<1>(0h1))
node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r)
node _res_T_100 = eq(_res_T_99, UInt<2>(0h3))
node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r)
node _res_T_102 = eq(_res_T_101, UInt<3>(0h4))
node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r)
node _res_T_104 = eq(_res_T_103, UInt<3>(0h5))
node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r)
node _res_T_106 = eq(_res_T_105, UInt<3>(0h7))
node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_108 = and(_res_T_107, res_hit_2)
node _res_T_109 = and(_res_T_108, res_aligned_2)
node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_111 = and(_res_T_109, _res_T_110)
node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_113 = and(_res_T_112, res_aligned_2)
node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_115 = and(_res_T_113, _res_T_114)
node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_117 = and(_res_T_116, res_hit_2)
node _res_T_118 = and(_res_T_117, res_aligned_2)
node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_120 = and(_res_T_118, _res_T_119)
node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_122 = and(_res_T_121, res_aligned_2)
node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_124 = and(_res_T_122, _res_T_123)
node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_126 = and(_res_T_125, res_hit_2)
node _res_T_127 = and(_res_T_126, res_aligned_2)
node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_129 = and(_res_T_127, _res_T_128)
node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_131 = and(_res_T_130, res_aligned_2)
node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_133 = and(_res_T_131, _res_T_132)
wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_2, io.pmp[5]
node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2)
node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4)
connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5
node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2)
node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4)
connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5
node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2)
node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4)
connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5
node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89)
node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1)
node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0)
node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10)
node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11)
node _res_hit_msbMatch_T_30 = shr(io.addr, 3)
node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31)
node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3))
node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33)
node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3)
node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3)
node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35)
node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36)
node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38)
node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0))
node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31)
node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3))
node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33)
node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0)
node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0)
node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35)
node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36)
node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38)
node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0))
node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3)
node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0)
node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0)
node _res_hit_T_44 = not(_res_hit_T_43)
node _res_hit_msbsLess_T_36 = shr(io.addr, 3)
node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37)
node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3))
node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39)
node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3)
node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41)
node _res_hit_msbsEqual_T_42 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43)
node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3))
node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45)
node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3)
node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47)
node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0))
node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44)
node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44)
node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3))
node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46)
node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0)
node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48)
node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6)
node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45)
node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0))
node _res_hit_msbsLess_T_42 = shr(io.addr, 3)
node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43)
node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3))
node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45)
node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3)
node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47)
node _res_hit_msbsEqual_T_49 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50)
node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3))
node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52)
node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3)
node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54)
node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0))
node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0))
node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51)
node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3))
node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53)
node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0)
node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55)
node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7)
node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48)
node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49)
node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50)
node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51)
node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0))
node res_ignore_3 = and(default, _res_ignore_T_3)
node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0)
node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7)
node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52)
node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54)
node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3)
node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56)
node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59)
node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61)
node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0)
node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64)
node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65)
node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67)
node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52)
node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54)
node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3)
node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56)
node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59)
node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61)
node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0)
node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3)
node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65)
node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67)
node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3)
node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0)
node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9)
node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10)
node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0))
node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1)
node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3)
node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0))
node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1))
node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r)
node _res_T_141 = eq(_res_T_140, UInt<1>(0h0))
node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r)
node _res_T_143 = eq(_res_T_142, UInt<1>(0h1))
node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r)
node _res_T_145 = eq(_res_T_144, UInt<2>(0h3))
node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r)
node _res_T_147 = eq(_res_T_146, UInt<3>(0h4))
node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r)
node _res_T_149 = eq(_res_T_148, UInt<3>(0h5))
node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r)
node _res_T_151 = eq(_res_T_150, UInt<3>(0h7))
node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_153 = and(_res_T_152, res_hit_3)
node _res_T_154 = and(_res_T_153, res_aligned_3)
node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_156 = and(_res_T_154, _res_T_155)
node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_158 = and(_res_T_157, res_aligned_3)
node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_160 = and(_res_T_158, _res_T_159)
node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_162 = and(_res_T_161, res_hit_3)
node _res_T_163 = and(_res_T_162, res_aligned_3)
node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_165 = and(_res_T_163, _res_T_164)
node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_167 = and(_res_T_166, res_aligned_3)
node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_169 = and(_res_T_167, _res_T_168)
node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_171 = and(_res_T_170, res_hit_3)
node _res_T_172 = and(_res_T_171, res_aligned_3)
node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_174 = and(_res_T_172, _res_T_173)
node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_176 = and(_res_T_175, res_aligned_3)
node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_178 = and(_res_T_176, _res_T_177)
wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_3, io.pmp[4]
node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3)
node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6)
connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7
node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3)
node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6)
connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7
node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3)
node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6)
connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7
node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134)
node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1)
node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0)
node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13)
node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14)
node _res_hit_msbMatch_T_40 = shr(io.addr, 3)
node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41)
node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3))
node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43)
node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3)
node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3)
node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45)
node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46)
node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48)
node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0))
node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41)
node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3))
node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43)
node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0)
node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0)
node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45)
node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46)
node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48)
node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0))
node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4)
node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0)
node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0)
node _res_hit_T_57 = not(_res_hit_T_56)
node _res_hit_msbsLess_T_48 = shr(io.addr, 3)
node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49)
node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3))
node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51)
node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3)
node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53)
node _res_hit_msbsEqual_T_56 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57)
node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3))
node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59)
node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3)
node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61)
node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0))
node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57)
node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58)
node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3))
node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60)
node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0)
node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62)
node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8)
node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58)
node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0))
node _res_hit_msbsLess_T_54 = shr(io.addr, 3)
node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55)
node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3))
node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57)
node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3)
node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59)
node _res_hit_msbsEqual_T_63 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64)
node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3))
node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66)
node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3)
node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68)
node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0))
node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0))
node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65)
node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3))
node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67)
node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0)
node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69)
node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9)
node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61)
node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62)
node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63)
node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64)
node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0))
node res_ignore_4 = and(default, _res_ignore_T_4)
node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0)
node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9)
node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69)
node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71)
node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3)
node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73)
node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76)
node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78)
node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0)
node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81)
node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82)
node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84)
node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69)
node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71)
node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3)
node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73)
node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76)
node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78)
node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0)
node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4)
node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82)
node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84)
node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4)
node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0)
node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12)
node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13)
node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0))
node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1)
node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4)
node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0))
node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1))
node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r)
node _res_T_186 = eq(_res_T_185, UInt<1>(0h0))
node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r)
node _res_T_188 = eq(_res_T_187, UInt<1>(0h1))
node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r)
node _res_T_190 = eq(_res_T_189, UInt<2>(0h3))
node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r)
node _res_T_192 = eq(_res_T_191, UInt<3>(0h4))
node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r)
node _res_T_194 = eq(_res_T_193, UInt<3>(0h5))
node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r)
node _res_T_196 = eq(_res_T_195, UInt<3>(0h7))
node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_198 = and(_res_T_197, res_hit_4)
node _res_T_199 = and(_res_T_198, res_aligned_4)
node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_201 = and(_res_T_199, _res_T_200)
node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_203 = and(_res_T_202, res_aligned_4)
node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_205 = and(_res_T_203, _res_T_204)
node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_207 = and(_res_T_206, res_hit_4)
node _res_T_208 = and(_res_T_207, res_aligned_4)
node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_210 = and(_res_T_208, _res_T_209)
node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_212 = and(_res_T_211, res_aligned_4)
node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_214 = and(_res_T_212, _res_T_213)
node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_216 = and(_res_T_215, res_hit_4)
node _res_T_217 = and(_res_T_216, res_aligned_4)
node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_219 = and(_res_T_217, _res_T_218)
node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_221 = and(_res_T_220, res_aligned_4)
node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_223 = and(_res_T_221, _res_T_222)
wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_4, io.pmp[3]
node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4)
node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8)
connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9
node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4)
node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8)
connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9
node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4)
node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8)
connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9
node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179)
node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1)
node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0)
node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16)
node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17)
node _res_hit_msbMatch_T_50 = shr(io.addr, 3)
node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51)
node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3))
node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53)
node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3)
node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3)
node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55)
node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56)
node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58)
node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0))
node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51)
node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3))
node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53)
node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0)
node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0)
node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55)
node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56)
node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58)
node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0))
node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5)
node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0)
node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0)
node _res_hit_T_70 = not(_res_hit_T_69)
node _res_hit_msbsLess_T_60 = shr(io.addr, 3)
node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61)
node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3))
node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63)
node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3)
node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65)
node _res_hit_msbsEqual_T_70 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71)
node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3))
node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73)
node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3)
node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75)
node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0))
node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70)
node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72)
node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3))
node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74)
node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0)
node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76)
node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10)
node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71)
node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0))
node _res_hit_msbsLess_T_66 = shr(io.addr, 3)
node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67)
node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3))
node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69)
node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3)
node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71)
node _res_hit_msbsEqual_T_77 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78)
node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3))
node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80)
node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3)
node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82)
node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0))
node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0))
node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79)
node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3))
node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81)
node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0)
node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83)
node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11)
node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74)
node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75)
node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76)
node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77)
node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0))
node res_ignore_5 = and(default, _res_ignore_T_5)
node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0)
node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11)
node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86)
node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88)
node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3)
node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90)
node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93)
node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95)
node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0)
node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98)
node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99)
node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101)
node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86)
node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88)
node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3)
node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90)
node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93)
node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95)
node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0)
node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5)
node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99)
node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101)
node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5)
node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0)
node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15)
node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16)
node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0))
node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1)
node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5)
node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0))
node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1))
node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r)
node _res_T_231 = eq(_res_T_230, UInt<1>(0h0))
node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r)
node _res_T_233 = eq(_res_T_232, UInt<1>(0h1))
node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r)
node _res_T_235 = eq(_res_T_234, UInt<2>(0h3))
node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r)
node _res_T_237 = eq(_res_T_236, UInt<3>(0h4))
node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r)
node _res_T_239 = eq(_res_T_238, UInt<3>(0h5))
node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r)
node _res_T_241 = eq(_res_T_240, UInt<3>(0h7))
node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_243 = and(_res_T_242, res_hit_5)
node _res_T_244 = and(_res_T_243, res_aligned_5)
node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_246 = and(_res_T_244, _res_T_245)
node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_248 = and(_res_T_247, res_aligned_5)
node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_250 = and(_res_T_248, _res_T_249)
node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_252 = and(_res_T_251, res_hit_5)
node _res_T_253 = and(_res_T_252, res_aligned_5)
node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_255 = and(_res_T_253, _res_T_254)
node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_257 = and(_res_T_256, res_aligned_5)
node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_259 = and(_res_T_257, _res_T_258)
node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_261 = and(_res_T_260, res_hit_5)
node _res_T_262 = and(_res_T_261, res_aligned_5)
node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_264 = and(_res_T_262, _res_T_263)
node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_266 = and(_res_T_265, res_aligned_5)
node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_268 = and(_res_T_266, _res_T_267)
wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_5, io.pmp[2]
node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5)
node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10)
connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11
node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5)
node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10)
connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11
node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5)
node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10)
connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11
node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224)
node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1)
node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0)
node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19)
node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20)
node _res_hit_msbMatch_T_60 = shr(io.addr, 3)
node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61)
node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3))
node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63)
node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3)
node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3)
node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65)
node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66)
node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68)
node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0))
node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61)
node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3))
node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63)
node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0)
node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0)
node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65)
node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66)
node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68)
node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0))
node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6)
node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0)
node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0)
node _res_hit_T_83 = not(_res_hit_T_82)
node _res_hit_msbsLess_T_72 = shr(io.addr, 3)
node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73)
node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3))
node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75)
node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3)
node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77)
node _res_hit_msbsEqual_T_84 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85)
node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3))
node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87)
node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3)
node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89)
node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0))
node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83)
node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86)
node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3))
node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88)
node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0)
node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90)
node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12)
node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84)
node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0))
node _res_hit_msbsLess_T_78 = shr(io.addr, 3)
node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79)
node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3))
node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81)
node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3)
node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83)
node _res_hit_msbsEqual_T_91 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92)
node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3))
node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94)
node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3)
node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96)
node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0))
node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0))
node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93)
node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3))
node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95)
node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0)
node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97)
node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13)
node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87)
node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88)
node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89)
node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90)
node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0))
node res_ignore_6 = and(default, _res_ignore_T_6)
node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0)
node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13)
node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103)
node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105)
node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3)
node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107)
node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110)
node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112)
node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0)
node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115)
node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116)
node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118)
node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103)
node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105)
node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3)
node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107)
node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110)
node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112)
node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0)
node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6)
node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116)
node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118)
node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6)
node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0)
node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18)
node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19)
node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0))
node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1)
node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6)
node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0))
node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1))
node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r)
node _res_T_276 = eq(_res_T_275, UInt<1>(0h0))
node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r)
node _res_T_278 = eq(_res_T_277, UInt<1>(0h1))
node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r)
node _res_T_280 = eq(_res_T_279, UInt<2>(0h3))
node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r)
node _res_T_282 = eq(_res_T_281, UInt<3>(0h4))
node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r)
node _res_T_284 = eq(_res_T_283, UInt<3>(0h5))
node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r)
node _res_T_286 = eq(_res_T_285, UInt<3>(0h7))
node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_288 = and(_res_T_287, res_hit_6)
node _res_T_289 = and(_res_T_288, res_aligned_6)
node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_291 = and(_res_T_289, _res_T_290)
node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_293 = and(_res_T_292, res_aligned_6)
node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_295 = and(_res_T_293, _res_T_294)
node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_297 = and(_res_T_296, res_hit_6)
node _res_T_298 = and(_res_T_297, res_aligned_6)
node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_300 = and(_res_T_298, _res_T_299)
node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_302 = and(_res_T_301, res_aligned_6)
node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_304 = and(_res_T_302, _res_T_303)
node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_306 = and(_res_T_305, res_hit_6)
node _res_T_307 = and(_res_T_306, res_aligned_6)
node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_309 = and(_res_T_307, _res_T_308)
node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_311 = and(_res_T_310, res_aligned_6)
node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_313 = and(_res_T_311, _res_T_312)
wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_6, io.pmp[1]
node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6)
node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12)
connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13
node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6)
node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12)
connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13
node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6)
node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12)
connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13
node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269)
node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1)
node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0)
node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22)
node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23)
node _res_hit_msbMatch_T_70 = shr(io.addr, 3)
node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71)
node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3))
node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73)
node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3)
node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3)
node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75)
node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76)
node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78)
node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0))
node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71)
node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3))
node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73)
node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0)
node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0)
node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75)
node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76)
node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78)
node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0))
node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7)
node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0)
node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0)
node _res_hit_T_96 = not(_res_hit_T_95)
node _res_hit_msbsLess_T_84 = shr(io.addr, 3)
node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2)
node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85)
node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3))
node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87)
node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3)
node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89)
node _res_hit_msbsEqual_T_98 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2)
node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99)
node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3))
node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101)
node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3)
node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103)
node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0))
node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96)
node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2)
node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100)
node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3))
node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102)
node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0)
node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104)
node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14)
node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97)
node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0))
node _res_hit_msbsLess_T_90 = shr(io.addr, 3)
node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91)
node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3))
node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93)
node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3)
node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95)
node _res_hit_msbsEqual_T_105 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106)
node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3))
node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108)
node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3)
node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110)
node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0))
node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0))
node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107)
node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3))
node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109)
node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0)
node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111)
node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15)
node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100)
node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101)
node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102)
node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103)
node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0))
node res_ignore_7 = and(default, _res_ignore_T_7)
node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0)
node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15)
node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120)
node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122)
node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3)
node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124)
node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127)
node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129)
node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0)
node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132)
node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133)
node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135)
node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120)
node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122)
node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3)
node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124)
node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127)
node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129)
node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0)
node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7)
node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133)
node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135)
node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7)
node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0)
node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21)
node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22)
node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0))
node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1)
node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7)
node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0))
node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1))
node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r)
node _res_T_321 = eq(_res_T_320, UInt<1>(0h0))
node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r)
node _res_T_323 = eq(_res_T_322, UInt<1>(0h1))
node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r)
node _res_T_325 = eq(_res_T_324, UInt<2>(0h3))
node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r)
node _res_T_327 = eq(_res_T_326, UInt<3>(0h4))
node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r)
node _res_T_329 = eq(_res_T_328, UInt<3>(0h5))
node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r)
node _res_T_331 = eq(_res_T_330, UInt<3>(0h7))
node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_333 = and(_res_T_332, res_hit_7)
node _res_T_334 = and(_res_T_333, res_aligned_7)
node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_336 = and(_res_T_334, _res_T_335)
node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_338 = and(_res_T_337, res_aligned_7)
node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_340 = and(_res_T_338, _res_T_339)
node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_342 = and(_res_T_341, res_hit_7)
node _res_T_343 = and(_res_T_342, res_aligned_7)
node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_345 = and(_res_T_343, _res_T_344)
node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_347 = and(_res_T_346, res_aligned_7)
node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_349 = and(_res_T_347, _res_T_348)
node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_351 = and(_res_T_350, res_hit_7)
node _res_T_352 = and(_res_T_351, res_aligned_7)
node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_354 = and(_res_T_352, _res_T_353)
node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_356 = and(_res_T_355, res_aligned_7)
node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_358 = and(_res_T_356, _res_T_357)
wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_7, io.pmp[0]
node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7)
node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14)
connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15
node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7)
node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14)
connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15
node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7)
node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14)
connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15
node res = mux(res_hit_7, res_cur_7, _res_T_314)
connect io.r, res.cfg.r
connect io.w, res.cfg.w
connect io.x, res.cfg.x | module PMPChecker_s3_2( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5]
wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27]
wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39]
wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53]
wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30]
wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16]
wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147]
wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71]
assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_3; // @[package.scala:243:71]
assign _res_hit_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_16; // @[package.scala:243:71]
assign _res_hit_T_16 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_29; // @[package.scala:243:71]
assign _res_hit_T_29 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_42; // @[package.scala:243:71]
assign _res_hit_T_42 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_55; // @[package.scala:243:71]
assign _res_hit_T_55 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_68; // @[package.scala:243:71]
assign _res_hit_T_68 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_81; // @[package.scala:243:71]
assign _res_hit_T_81 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_94; // @[package.scala:243:71]
assign _res_hit_T_94 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71]
wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46]
wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46]
wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}]
wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46]
wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48]
wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}]
wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}]
wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}]
wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46]
wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k5z4c_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_58
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k5z4c
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k5z4c
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k5z4c
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k5z4c
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k5z4c
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s2k5z4c_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [31:0] _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
wire [7:0] _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21]
wire _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [4:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_58 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_b_ready (auto_in_b_ready),
.io_in_b_valid (_nodeIn_b_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_b_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_b_bits_param (_nodeIn_b_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_b_bits_size (_nodeIn_b_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_b_bits_source (_nodeIn_b_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_b_bits_address (_nodeIn_b_q_io_deq_bits_address), // @[Decoupled.scala:362:21]
.io_in_b_bits_mask (_nodeIn_b_q_io_deq_bits_mask), // @[Decoupled.scala:362:21]
.io_in_b_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21]
.io_in_c_ready (_nodeOut_c_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_c_valid (auto_in_c_valid),
.io_in_c_bits_opcode (auto_in_c_bits_opcode),
.io_in_c_bits_param (auto_in_c_bits_param),
.io_in_c_bits_size (auto_in_c_bits_size),
.io_in_c_bits_source (auto_in_c_bits_source),
.io_in_c_bits_address (auto_in_c_bits_address),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21]
.io_in_e_ready (_nodeOut_e_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_e_valid (auto_in_e_valid),
.io_in_e_bits_sink (auto_in_e_bits_sink)
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s2k5z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s2k5z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (auto_out_d_bits_param),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (auto_out_d_bits_sink),
.io_enq_bits_denied (auto_out_d_bits_denied),
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s2k5z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_b_ready),
.io_enq_valid (auto_out_b_valid),
.io_enq_bits_opcode (auto_out_b_bits_opcode),
.io_enq_bits_param (auto_out_b_bits_param),
.io_enq_bits_size (auto_out_b_bits_size),
.io_enq_bits_source (auto_out_b_bits_source),
.io_enq_bits_address (auto_out_b_bits_address),
.io_enq_bits_mask (auto_out_b_bits_mask),
.io_enq_bits_data (auto_out_b_bits_data),
.io_enq_bits_corrupt (auto_out_b_bits_corrupt),
.io_deq_ready (auto_in_b_ready),
.io_deq_valid (_nodeIn_b_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_b_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_b_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_b_q_io_deq_bits_source),
.io_deq_bits_address (_nodeIn_b_q_io_deq_bits_address),
.io_deq_bits_mask (_nodeIn_b_q_io_deq_bits_mask),
.io_deq_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s2k5z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_c_q_io_enq_ready),
.io_enq_valid (auto_in_c_valid),
.io_enq_bits_opcode (auto_in_c_bits_opcode),
.io_enq_bits_param (auto_in_c_bits_param),
.io_enq_bits_size (auto_in_c_bits_size),
.io_enq_bits_source (auto_in_c_bits_source),
.io_enq_bits_address (auto_in_c_bits_address),
.io_enq_bits_data (auto_in_c_bits_data),
.io_deq_ready (auto_out_c_ready),
.io_deq_valid (auto_out_c_valid),
.io_deq_bits_opcode (auto_out_c_bits_opcode),
.io_deq_bits_param (auto_out_c_bits_param),
.io_deq_bits_size (auto_out_c_bits_size),
.io_deq_bits_source (auto_out_c_bits_source),
.io_deq_bits_address (auto_out_c_bits_address),
.io_deq_bits_data (auto_out_c_bits_data),
.io_deq_bits_corrupt (auto_out_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s2k5z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_e_q_io_enq_ready),
.io_enq_valid (auto_in_e_valid),
.io_enq_bits_sink (auto_in_e_bits_sink),
.io_deq_ready (auto_out_e_ready),
.io_deq_valid (auto_out_e_valid),
.io_deq_bits_sink (auto_out_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_b_valid = _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_opcode = _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_param = _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_size = _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_source = _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_address = _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_mask = _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_corrupt = _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign auto_in_c_ready = _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign auto_in_e_ready = _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_41
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s2k3z4c_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [31:0] _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
wire [7:0] _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21]
wire _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_41 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_b_ready (auto_in_b_ready),
.io_in_b_valid (_nodeIn_b_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_b_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_b_bits_param (_nodeIn_b_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_b_bits_size (_nodeIn_b_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_b_bits_source (_nodeIn_b_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_b_bits_address (_nodeIn_b_q_io_deq_bits_address), // @[Decoupled.scala:362:21]
.io_in_b_bits_mask (_nodeIn_b_q_io_deq_bits_mask), // @[Decoupled.scala:362:21]
.io_in_b_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21]
.io_in_c_ready (_nodeOut_c_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_c_valid (auto_in_c_valid),
.io_in_c_bits_opcode (auto_in_c_bits_opcode),
.io_in_c_bits_param (auto_in_c_bits_param),
.io_in_c_bits_size (auto_in_c_bits_size),
.io_in_c_bits_source (auto_in_c_bits_source),
.io_in_c_bits_address (auto_in_c_bits_address),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21]
.io_in_e_ready (_nodeOut_e_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_e_valid (auto_in_e_valid),
.io_in_e_bits_sink (auto_in_e_bits_sink)
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (auto_out_d_bits_param),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (auto_out_d_bits_sink),
.io_enq_bits_denied (auto_out_d_bits_denied),
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_b_ready),
.io_enq_valid (auto_out_b_valid),
.io_enq_bits_param (auto_out_b_bits_param),
.io_enq_bits_address (auto_out_b_bits_address),
.io_deq_ready (auto_in_b_ready),
.io_deq_valid (_nodeIn_b_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_b_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_b_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_b_q_io_deq_bits_source),
.io_deq_bits_address (_nodeIn_b_q_io_deq_bits_address),
.io_deq_bits_mask (_nodeIn_b_q_io_deq_bits_mask),
.io_deq_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_c_q_io_enq_ready),
.io_enq_valid (auto_in_c_valid),
.io_enq_bits_opcode (auto_in_c_bits_opcode),
.io_enq_bits_param (auto_in_c_bits_param),
.io_enq_bits_size (auto_in_c_bits_size),
.io_enq_bits_source (auto_in_c_bits_source),
.io_enq_bits_address (auto_in_c_bits_address),
.io_enq_bits_data (auto_in_c_bits_data),
.io_deq_ready (auto_out_c_ready),
.io_deq_valid (auto_out_c_valid),
.io_deq_bits_opcode (auto_out_c_bits_opcode),
.io_deq_bits_param (auto_out_c_bits_param),
.io_deq_bits_size (auto_out_c_bits_size),
.io_deq_bits_source (auto_out_c_bits_source),
.io_deq_bits_address (auto_out_c_bits_address),
.io_deq_bits_data (auto_out_c_bits_data),
.io_deq_bits_corrupt (auto_out_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_e_q_io_enq_ready),
.io_enq_valid (auto_in_e_valid),
.io_enq_bits_sink (auto_in_e_bits_sink),
.io_deq_valid (auto_out_e_valid),
.io_deq_bits_sink (auto_out_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_b_valid = _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_opcode = _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_param = _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_size = _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_source = _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_address = _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_mask = _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_corrupt = _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign auto_in_c_ready = _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign auto_in_e_ready = _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_27 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_27( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_111 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_111( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module CLINTClockSinkDomain :
output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_11 : { sync : UInt<1>[2]}, int_in_clock_xing_out_10 : { sync : UInt<1>[2]}, int_in_clock_xing_out_9 : { sync : UInt<1>[2]}, int_in_clock_xing_out_8 : { sync : UInt<1>[2]}, int_in_clock_xing_out_7 : { sync : UInt<1>[2]}, int_in_clock_xing_out_6 : { sync : UInt<1>[2]}, int_in_clock_xing_out_5 : { sync : UInt<1>[2]}, int_in_clock_xing_out_4 : { sync : UInt<1>[2]}, int_in_clock_xing_out_3 : { sync : UInt<1>[2]}, int_in_clock_xing_out_2 : { sync : UInt<1>[2]}, int_in_clock_xing_out_1 : { sync : UInt<1>[2]}, int_in_clock_xing_out_0 : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}}
input tick : UInt<1>
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst clint of CLINT
connect clint.clock, childClock
connect clint.reset, childReset
inst intsource of IntSyncCrossingSource_n1x2
connect intsource.clock, childClock
connect intsource.reset, childReset
inst intsource_1 of IntSyncCrossingSource_n1x2_1
connect intsource_1.clock, childClock
connect intsource_1.reset, childReset
inst intsource_2 of IntSyncCrossingSource_n1x2_2
connect intsource_2.clock, childClock
connect intsource_2.reset, childReset
inst intsource_3 of IntSyncCrossingSource_n1x2_3
connect intsource_3.clock, childClock
connect intsource_3.reset, childReset
inst intsource_4 of IntSyncCrossingSource_n1x2_4
connect intsource_4.clock, childClock
connect intsource_4.reset, childReset
inst intsource_5 of IntSyncCrossingSource_n1x2_5
connect intsource_5.clock, childClock
connect intsource_5.reset, childReset
inst intsource_6 of IntSyncCrossingSource_n1x2_6
connect intsource_6.clock, childClock
connect intsource_6.reset, childReset
inst intsource_7 of IntSyncCrossingSource_n1x2_7
connect intsource_7.clock, childClock
connect intsource_7.reset, childReset
inst intsource_8 of IntSyncCrossingSource_n1x2_8
connect intsource_8.clock, childClock
connect intsource_8.reset, childReset
inst intsource_9 of IntSyncCrossingSource_n1x2_9
connect intsource_9.clock, childClock
connect intsource_9.reset, childReset
inst intsource_10 of IntSyncCrossingSource_n1x2_10
connect intsource_10.clock, childClock
connect intsource_10.reset, childReset
inst intsource_11 of IntSyncCrossingSource_n1x2_11
connect intsource_11.clock, childClock
connect intsource_11.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
wire intInClockXingOut : { sync : UInt<1>[2]}
invalidate intInClockXingOut.sync[0]
invalidate intInClockXingOut.sync[1]
wire intInClockXingIn : { sync : UInt<1>[2]}
invalidate intInClockXingIn.sync[0]
invalidate intInClockXingIn.sync[1]
connect intInClockXingOut, intInClockXingIn
wire intInClockXingOut_1 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_1.sync[0]
invalidate intInClockXingOut_1.sync[1]
wire intInClockXingIn_1 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_1.sync[0]
invalidate intInClockXingIn_1.sync[1]
connect intInClockXingOut_1, intInClockXingIn_1
wire intInClockXingOut_2 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_2.sync[0]
invalidate intInClockXingOut_2.sync[1]
wire intInClockXingIn_2 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_2.sync[0]
invalidate intInClockXingIn_2.sync[1]
connect intInClockXingOut_2, intInClockXingIn_2
wire intInClockXingOut_3 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_3.sync[0]
invalidate intInClockXingOut_3.sync[1]
wire intInClockXingIn_3 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_3.sync[0]
invalidate intInClockXingIn_3.sync[1]
connect intInClockXingOut_3, intInClockXingIn_3
wire intInClockXingOut_4 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_4.sync[0]
invalidate intInClockXingOut_4.sync[1]
wire intInClockXingIn_4 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_4.sync[0]
invalidate intInClockXingIn_4.sync[1]
connect intInClockXingOut_4, intInClockXingIn_4
wire intInClockXingOut_5 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_5.sync[0]
invalidate intInClockXingOut_5.sync[1]
wire intInClockXingIn_5 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_5.sync[0]
invalidate intInClockXingIn_5.sync[1]
connect intInClockXingOut_5, intInClockXingIn_5
wire intInClockXingOut_6 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_6.sync[0]
invalidate intInClockXingOut_6.sync[1]
wire intInClockXingIn_6 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_6.sync[0]
invalidate intInClockXingIn_6.sync[1]
connect intInClockXingOut_6, intInClockXingIn_6
wire intInClockXingOut_7 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_7.sync[0]
invalidate intInClockXingOut_7.sync[1]
wire intInClockXingIn_7 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_7.sync[0]
invalidate intInClockXingIn_7.sync[1]
connect intInClockXingOut_7, intInClockXingIn_7
wire intInClockXingOut_8 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_8.sync[0]
invalidate intInClockXingOut_8.sync[1]
wire intInClockXingIn_8 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_8.sync[0]
invalidate intInClockXingIn_8.sync[1]
connect intInClockXingOut_8, intInClockXingIn_8
wire intInClockXingOut_9 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_9.sync[0]
invalidate intInClockXingOut_9.sync[1]
wire intInClockXingIn_9 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_9.sync[0]
invalidate intInClockXingIn_9.sync[1]
connect intInClockXingOut_9, intInClockXingIn_9
wire intInClockXingOut_10 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_10.sync[0]
invalidate intInClockXingOut_10.sync[1]
wire intInClockXingIn_10 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_10.sync[0]
invalidate intInClockXingIn_10.sync[1]
connect intInClockXingOut_10, intInClockXingIn_10
wire intInClockXingOut_11 : { sync : UInt<1>[2]}
invalidate intInClockXingOut_11.sync[0]
invalidate intInClockXingOut_11.sync[1]
wire intInClockXingIn_11 : { sync : UInt<1>[2]}
invalidate intInClockXingIn_11.sync[0]
invalidate intInClockXingIn_11.sync[1]
connect intInClockXingOut_11, intInClockXingIn_11
connect intsource.auto.in[0], clint.auto.int_out_0[0]
connect intsource.auto.in[1], clint.auto.int_out_0[1]
connect intsource_1.auto.in[0], clint.auto.int_out_1[0]
connect intsource_1.auto.in[1], clint.auto.int_out_1[1]
connect intsource_2.auto.in[0], clint.auto.int_out_2[0]
connect intsource_2.auto.in[1], clint.auto.int_out_2[1]
connect intsource_3.auto.in[0], clint.auto.int_out_3[0]
connect intsource_3.auto.in[1], clint.auto.int_out_3[1]
connect intsource_4.auto.in[0], clint.auto.int_out_4[0]
connect intsource_4.auto.in[1], clint.auto.int_out_4[1]
connect intsource_5.auto.in[0], clint.auto.int_out_5[0]
connect intsource_5.auto.in[1], clint.auto.int_out_5[1]
connect intsource_6.auto.in[0], clint.auto.int_out_6[0]
connect intsource_6.auto.in[1], clint.auto.int_out_6[1]
connect intsource_7.auto.in[0], clint.auto.int_out_7[0]
connect intsource_7.auto.in[1], clint.auto.int_out_7[1]
connect intsource_8.auto.in[0], clint.auto.int_out_8[0]
connect intsource_8.auto.in[1], clint.auto.int_out_8[1]
connect intsource_9.auto.in[0], clint.auto.int_out_9[0]
connect intsource_9.auto.in[1], clint.auto.int_out_9[1]
connect intsource_10.auto.in[0], clint.auto.int_out_10[0]
connect intsource_10.auto.in[1], clint.auto.int_out_10[1]
connect intsource_11.auto.in[0], clint.auto.int_out_11[0]
connect intsource_11.auto.in[1], clint.auto.int_out_11[1]
connect intInClockXingIn, intsource.auto.out
connect intInClockXingIn_1, intsource_1.auto.out
connect intInClockXingIn_2, intsource_2.auto.out
connect intInClockXingIn_3, intsource_3.auto.out
connect intInClockXingIn_4, intsource_4.auto.out
connect intInClockXingIn_5, intsource_5.auto.out
connect intInClockXingIn_6, intsource_6.auto.out
connect intInClockXingIn_7, intsource_7.auto.out
connect intInClockXingIn_8, intsource_8.auto.out
connect intInClockXingIn_9, intsource_9.auto.out
connect intInClockXingIn_10, intsource_10.auto.out
connect intInClockXingIn_11, intsource_11.auto.out
connect clockNodeIn, auto.clock_in
connect auto.int_in_clock_xing_out_0, intInClockXingOut
connect auto.int_in_clock_xing_out_1, intInClockXingOut_1
connect auto.int_in_clock_xing_out_2, intInClockXingOut_2
connect auto.int_in_clock_xing_out_3, intInClockXingOut_3
connect auto.int_in_clock_xing_out_4, intInClockXingOut_4
connect auto.int_in_clock_xing_out_5, intInClockXingOut_5
connect auto.int_in_clock_xing_out_6, intInClockXingOut_6
connect auto.int_in_clock_xing_out_7, intInClockXingOut_7
connect auto.int_in_clock_xing_out_8, intInClockXingOut_8
connect auto.int_in_clock_xing_out_9, intInClockXingOut_9
connect auto.int_in_clock_xing_out_10, intInClockXingOut_10
connect auto.int_in_clock_xing_out_11, intInClockXingOut_11
connect clint.auto.in, auto.clint_in
connect clint.io.rtcTick, tick
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset
extmodule plusarg_reader_250 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_251 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9]
output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_11_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_11_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_10_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_10_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_9_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_9_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_8_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_8_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_7_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_7_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_6_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_6_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_5_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_5_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_4_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_4_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_3_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_3_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_2_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_2_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_1_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25]
input tick, // @[CLINT.scala:115:20]
output clock, // @[ClockDomain.scala:21:19]
output reset // @[ClockDomain.scala:22:19]
);
wire _clint_auto_int_out_11_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_11_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_10_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_10_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_9_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_9_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_8_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_8_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_7_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_7_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_6_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_6_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_5_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_5_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_4_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_4_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_3_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_3_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_2_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_2_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_1_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_1_1; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_0_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_0_1; // @[CLINT.scala:112:48]
CLINT clint ( // @[CLINT.scala:112:48]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_int_out_11_0 (_clint_auto_int_out_11_0),
.auto_int_out_11_1 (_clint_auto_int_out_11_1),
.auto_int_out_10_0 (_clint_auto_int_out_10_0),
.auto_int_out_10_1 (_clint_auto_int_out_10_1),
.auto_int_out_9_0 (_clint_auto_int_out_9_0),
.auto_int_out_9_1 (_clint_auto_int_out_9_1),
.auto_int_out_8_0 (_clint_auto_int_out_8_0),
.auto_int_out_8_1 (_clint_auto_int_out_8_1),
.auto_int_out_7_0 (_clint_auto_int_out_7_0),
.auto_int_out_7_1 (_clint_auto_int_out_7_1),
.auto_int_out_6_0 (_clint_auto_int_out_6_0),
.auto_int_out_6_1 (_clint_auto_int_out_6_1),
.auto_int_out_5_0 (_clint_auto_int_out_5_0),
.auto_int_out_5_1 (_clint_auto_int_out_5_1),
.auto_int_out_4_0 (_clint_auto_int_out_4_0),
.auto_int_out_4_1 (_clint_auto_int_out_4_1),
.auto_int_out_3_0 (_clint_auto_int_out_3_0),
.auto_int_out_3_1 (_clint_auto_int_out_3_1),
.auto_int_out_2_0 (_clint_auto_int_out_2_0),
.auto_int_out_2_1 (_clint_auto_int_out_2_1),
.auto_int_out_1_0 (_clint_auto_int_out_1_0),
.auto_int_out_1_1 (_clint_auto_int_out_1_1),
.auto_int_out_0_0 (_clint_auto_int_out_0_0),
.auto_int_out_0_1 (_clint_auto_int_out_0_1),
.auto_in_a_ready (auto_clint_in_a_ready),
.auto_in_a_valid (auto_clint_in_a_valid),
.auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode),
.auto_in_a_bits_param (auto_clint_in_a_bits_param),
.auto_in_a_bits_size (auto_clint_in_a_bits_size),
.auto_in_a_bits_source (auto_clint_in_a_bits_source),
.auto_in_a_bits_address (auto_clint_in_a_bits_address),
.auto_in_a_bits_mask (auto_clint_in_a_bits_mask),
.auto_in_a_bits_data (auto_clint_in_a_bits_data),
.auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt),
.auto_in_d_ready (auto_clint_in_d_ready),
.auto_in_d_valid (auto_clint_in_d_valid),
.auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode),
.auto_in_d_bits_size (auto_clint_in_d_bits_size),
.auto_in_d_bits_source (auto_clint_in_d_bits_source),
.auto_in_d_bits_data (auto_clint_in_d_bits_data),
.io_rtcTick (tick)
); // @[CLINT.scala:112:48]
IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_0_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_0_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_0_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_0_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_1 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_1_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_1_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_1_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_1_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_2 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_2_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_2_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_2_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_2_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_3 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_3_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_3_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_3_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_3_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_4 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_4_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_4_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_4_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_4_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_5 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_5_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_5_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_5_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_5_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_6 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_6_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_6_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_6_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_6_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_7 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_7_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_7_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_7_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_7_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_8 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_8_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_8_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_8_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_8_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_9 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_9_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_9_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_9_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_9_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_10 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_10_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_10_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_10_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_10_sync_1)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x2 intsource_11 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_11_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_11_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (auto_int_in_clock_xing_out_11_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_11_sync_1)
); // @[Crossing.scala:29:31]
assign clock = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
assign reset = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter_4 :
input clock : Clock
input reset : Reset
output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}}
reg s1_id : UInt, clock
reg s2_id : UInt, clock
connect s2_id, s1_id
node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled)
connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T
node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid)
connect io.mem.req.valid, _io_mem_req_valid_T
connect io.requestor[0].req.ready, io.mem.req.ready
node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0))
node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T)
connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1
connect io.mem.req.bits, io.requestor[1].req.bits
node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1))
connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T
connect s1_id, UInt<1>(0h1)
connect io.mem.s1_kill, io.requestor[1].s1_kill
connect io.mem.s1_data, io.requestor[1].s1_data
connect io.mem.s2_kill, io.requestor[1].s2_kill
when io.requestor[0].req.valid :
connect io.mem.req.bits, io.requestor[0].req.bits
node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0))
connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1
connect s1_id, UInt<1>(0h0)
node _T = eq(s1_id, UInt<1>(0h0))
when _T :
connect io.mem.s1_kill, io.requestor[0].s1_kill
connect io.mem.s1_data, io.requestor[0].s1_data
node _T_1 = eq(s2_id, UInt<1>(0h0))
when _T_1 :
connect io.mem.s2_kill, io.requestor[0].s2_kill
node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0)
node tag_hit = eq(_tag_hit_T, UInt<1>(0h0))
node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit)
connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T
connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt
connect io.requestor[0].s2_gpa, io.mem.s2_gpa
connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte
connect io.requestor[0].ordered, io.mem.ordered
connect io.requestor[0].store_pending, io.mem.store_pending
connect io.requestor[0].perf, io.mem.perf
node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0))
node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T)
connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1
connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw
connect io.requestor[0].s2_uncached, io.mem.s2_uncached
connect io.requestor[0].s2_paddr, io.mem.s2_paddr
connect io.requestor[0].clock_enabled, io.mem.clock_enabled
connect io.requestor[0].resp.bits, io.mem.resp.bits
node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1)
connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T
connect io.requestor[0].replay_next, io.mem.replay_next
node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0)
node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1))
node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1)
connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T
connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt
connect io.requestor[1].s2_gpa, io.mem.s2_gpa
connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte
connect io.requestor[1].ordered, io.mem.ordered
connect io.requestor[1].store_pending, io.mem.store_pending
connect io.requestor[1].perf, io.mem.perf
node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1))
node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T)
connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1
connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw
connect io.requestor[1].s2_uncached, io.mem.s2_uncached
connect io.requestor[1].s2_paddr, io.mem.s2_paddr
connect io.requestor[1].clock_enabled, io.mem.clock_enabled
connect io.requestor[1].resp.bits, io.mem.resp.bits
node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1)
connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T
connect io.requestor[1].replay_next, io.mem.replay_next | module HellaCacheArbiter_4( // @[HellaCacheArbiter.scala:10:7]
input clock, // @[HellaCacheArbiter.scala:10:7]
input reset, // @[HellaCacheArbiter.scala:10:7]
output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14]
output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14]
output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_release, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input [7:0] io_requestor_1_req_bits_tag, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_requestor_1_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14]
input [7:0] io_requestor_1_s1_data_mask, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14]
output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14]
output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_release, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14]
input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14]
output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14]
input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input [7:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14]
input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14]
input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14]
input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14]
input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_release, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_storeBufferEmptyAfterStore // @[HellaCacheArbiter.scala:12:14]
);
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_req_bits_dprv_0 = io_requestor_1_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_dv_0 = io_requestor_1_req_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_1_s1_data_mask_0 = io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7]
wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_release_0 = io_mem_perf_release; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7]
wire [8:0] _io_mem_req_bits_tag_T_1 = 9'h0; // @[HellaCacheArbiter.scala:34:35]
wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [7:0] io_requestor_0_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_1_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s1_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire _io_mem_keep_clock_enabled_T = 1'h0; // @[HellaCacheArbiter.scala:23:81]
wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49]
wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39]
wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64]
wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49]
wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39]
wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
wire _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:25:63]
wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7]
reg s1_id; // @[HellaCacheArbiter.scala:20:20]
reg s2_id; // @[HellaCacheArbiter.scala:21:24]
wire _io_requestor_1_s2_nack_T = s2_id; // @[HellaCacheArbiter.scala:21:24, :68:58]
assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63]
assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:10:7, :25:63]
wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67]
assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}]
assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64]
wire [8:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1}; // @[HellaCacheArbiter.scala:10:7, :34:35]
assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]
assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : io_requestor_1_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]
assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 8'h0 : _io_mem_req_bits_tag_T[7:0]; // @[HellaCacheArbiter.scala:10:7, :34:{29,35}, :50:26]
assign io_mem_s1_kill_0 = ~s1_id & io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:{21,30}]
assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30]
assign io_mem_s1_data_mask_0 = s1_id ? io_requestor_1_s1_data_mask_0 : 8'h0; // @[HellaCacheArbiter.scala:10:7, :20:20, :39:24, :51:30]
wire _io_requestor_0_s2_nack_T = ~s2_id; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58]
wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41]
wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41]
wire tag_hit = ~_tag_hit_T; // @[HellaCacheArbiter.scala:60:{41,57}]
assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39]
assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39]
assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}]
assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49]
wire [6:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1]; // @[HellaCacheArbiter.scala:10:7, :74:45]
wire [6:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:1]; // @[HellaCacheArbiter.scala:10:7, :74:45]
assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}]
wire tag_hit_1 = _tag_hit_T_1; // @[HellaCacheArbiter.scala:60:{41,57}]
assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39]
assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39]
assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}]
assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49]
assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}]
always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7]
s1_id <= ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :28:67]
s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24]
always @(posedge)
assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_12 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_138
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_139
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_140
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_12( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_138 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_139 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_140 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_196 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_196( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_43 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_53
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_43( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_53 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64_mulAddZ31 :
input clock : Clock
input reset : Reset
output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
inst divSqrtRecF64ToRaw of DivSqrtRecF64ToRaw_mulAddZ31
connect divSqrtRecF64ToRaw.clock, clock
connect divSqrtRecF64ToRaw.reset, reset
connect io.inReady_div, divSqrtRecF64ToRaw.io.inReady_div
connect io.inReady_sqrt, divSqrtRecF64ToRaw.io.inReady_sqrt
connect divSqrtRecF64ToRaw.io.inValid, io.inValid
connect divSqrtRecF64ToRaw.io.sqrtOp, io.sqrtOp
connect divSqrtRecF64ToRaw.io.a, io.a
connect divSqrtRecF64ToRaw.io.b, io.b
connect divSqrtRecF64ToRaw.io.roundingMode, io.roundingMode
connect io.usingMulAdd, divSqrtRecF64ToRaw.io.usingMulAdd
connect io.latchMulAddA_0, divSqrtRecF64ToRaw.io.latchMulAddA_0
connect io.mulAddA_0, divSqrtRecF64ToRaw.io.mulAddA_0
connect io.latchMulAddB_0, divSqrtRecF64ToRaw.io.latchMulAddB_0
connect io.mulAddB_0, divSqrtRecF64ToRaw.io.mulAddB_0
connect io.mulAddC_2, divSqrtRecF64ToRaw.io.mulAddC_2
connect divSqrtRecF64ToRaw.io.mulAddResult_3, io.mulAddResult_3
connect io.outValid_div, divSqrtRecF64ToRaw.io.rawOutValid_div
connect io.outValid_sqrt, divSqrtRecF64ToRaw.io.rawOutValid_sqrt
inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_1
connect roundRawFNToRecFN.io.invalidExc, divSqrtRecF64ToRaw.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecF64ToRaw.io.infiniteExc
connect roundRawFNToRecFN.io.in.sig, divSqrtRecF64ToRaw.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, divSqrtRecF64ToRaw.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, divSqrtRecF64ToRaw.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, divSqrtRecF64ToRaw.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, divSqrtRecF64ToRaw.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecF64ToRaw.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, divSqrtRecF64ToRaw.io.roundingModeOut
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module DivSqrtRecF64_mulAddZ31( // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
input clock, // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
input reset, // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_outValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_outValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [64:0] io_out, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [4:0] io_exceptionFlags // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
);
wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_invalidExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_infiniteExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_isNaN; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_isInf; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_isZero; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_sign; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_detectTininess = 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7, :721:16, :775:15]
wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [64:0] io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
DivSqrtRecF64ToRaw_mulAddZ31 divSqrtRecF64ToRaw ( // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.clock (clock),
.reset (reset),
.io_inReady_div (io_inReady_div_0),
.io_inReady_sqrt (io_inReady_sqrt_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_a (io_a_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_b (io_b_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_usingMulAdd (io_usingMulAdd_0),
.io_latchMulAddA_0 (io_latchMulAddA_0_0),
.io_mulAddA_0 (io_mulAddA_0_0),
.io_latchMulAddB_0 (io_latchMulAddB_0_0),
.io_mulAddB_0 (io_mulAddB_0_0),
.io_mulAddC_2 (io_mulAddC_2_0),
.io_mulAddResult_3 (io_mulAddResult_3_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_rawOutValid_div (io_outValid_div_0),
.io_rawOutValid_sqrt (io_outValid_sqrt_0),
.io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig)
); // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
RoundRawFNToRecFN_e11_s53_1 roundRawFNToRecFN ( // @[DivSqrtRecF64_mulAddZ31.scala:775:15]
.io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[DivSqrtRecF64_mulAddZ31.scala:775:15]
assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_out = io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = and(_T_207, _T_212)
node _T_214 = or(UInt<1>(0h0), _T_213)
node _T_215 = and(_T_206, _T_214)
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_215, UInt<1>(0h1), "") : assert_26
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(is_aligned, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(io.in.a.bits.mask, mask)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_229, UInt<1>(0h1), "") : assert_30
node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_233 :
node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_237 = shr(io.in.a.bits.source, 11)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_242 = and(_T_240, _T_241)
node _T_243 = and(_T_236, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = and(_T_245, _T_250)
node _T_252 = or(UInt<1>(0h0), _T_251)
node _T_253 = and(_T_244, _T_252)
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_253, UInt<1>(0h1), "") : assert_31
node _T_257 = asUInt(reset)
node _T_258 = eq(_T_257, UInt<1>(0h0))
when _T_258 :
node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(is_aligned, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_263, UInt<1>(0h1), "") : assert_34
node _T_267 = not(mask)
node _T_268 = and(io.in.a.bits.mask, _T_267)
node _T_269 = eq(_T_268, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_269, UInt<1>(0h1), "") : assert_35
node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_273 :
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_277 = shr(io.in.a.bits.source, 11)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_280 = and(_T_278, _T_279)
node _T_281 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_282 = and(_T_280, _T_281)
node _T_283 = and(_T_276, _T_282)
node _T_284 = or(UInt<1>(0h0), _T_283)
node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = and(_T_285, _T_290)
node _T_292 = or(UInt<1>(0h0), _T_291)
node _T_293 = and(_T_284, _T_292)
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_293, UInt<1>(0h1), "") : assert_36
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(is_aligned, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_304 = asUInt(reset)
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(_T_303, UInt<1>(0h0))
when _T_306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_303, UInt<1>(0h1), "") : assert_39
node _T_307 = eq(io.in.a.bits.mask, mask)
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_307, UInt<1>(0h1), "") : assert_40
node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_311 :
node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_315 = shr(io.in.a.bits.source, 11)
node _T_316 = eq(_T_315, UInt<1>(0h0))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_320 = and(_T_318, _T_319)
node _T_321 = and(_T_314, _T_320)
node _T_322 = or(UInt<1>(0h0), _T_321)
node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = and(_T_323, _T_328)
node _T_330 = or(UInt<1>(0h0), _T_329)
node _T_331 = and(_T_322, _T_330)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_331, UInt<1>(0h1), "") : assert_41
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(is_aligned, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_341, UInt<1>(0h1), "") : assert_44
node _T_345 = eq(io.in.a.bits.mask, mask)
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_345, UInt<1>(0h1), "") : assert_45
node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_349 :
node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_352 = and(_T_350, _T_351)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_353 = shr(io.in.a.bits.source, 11)
node _T_354 = eq(_T_353, UInt<1>(0h0))
node _T_355 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_356 = and(_T_354, _T_355)
node _T_357 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_358 = and(_T_356, _T_357)
node _T_359 = and(_T_352, _T_358)
node _T_360 = or(UInt<1>(0h0), _T_359)
node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = and(_T_361, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = and(_T_360, _T_368)
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_369, UInt<1>(0h1), "") : assert_46
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(is_aligned, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_379, UInt<1>(0h1), "") : assert_49
node _T_383 = eq(io.in.a.bits.mask, mask)
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_383, UInt<1>(0h1), "") : assert_50
node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_387, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_391, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_395 :
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_399, UInt<1>(0h1), "") : assert_54
node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_403, UInt<1>(0h1), "") : assert_55
node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_407, UInt<1>(0h1), "") : assert_56
node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_411, UInt<1>(0h1), "") : assert_57
node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_415 :
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(sink_ok, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_422, UInt<1>(0h1), "") : assert_60
node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_426, UInt<1>(0h1), "") : assert_61
node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_430, UInt<1>(0h1), "") : assert_62
node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_434, UInt<1>(0h1), "") : assert_63
node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_439 = or(UInt<1>(0h0), _T_438)
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_439, UInt<1>(0h1), "") : assert_64
node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_443 :
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(sink_ok, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_450, UInt<1>(0h1), "") : assert_67
node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_454, UInt<1>(0h1), "") : assert_68
node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(_T_458, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_458, UInt<1>(0h1), "") : assert_69
node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_463 = or(_T_462, io.in.d.bits.corrupt)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_463, UInt<1>(0h1), "") : assert_70
node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_468, UInt<1>(0h1), "") : assert_71
node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_472 :
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_476, UInt<1>(0h1), "") : assert_73
node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_480, UInt<1>(0h1), "") : assert_74
node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_485 = or(UInt<1>(0h0), _T_484)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_485, UInt<1>(0h1), "") : assert_75
node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_489 :
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_493, UInt<1>(0h1), "") : assert_77
node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_498 = or(_T_497, io.in.d.bits.corrupt)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_498, UInt<1>(0h1), "") : assert_78
node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(_T_503, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_503, UInt<1>(0h1), "") : assert_79
node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_507 :
node _T_508 = asUInt(reset)
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_512 = asUInt(reset)
node _T_513 = eq(_T_512, UInt<1>(0h0))
when _T_513 :
node _T_514 = eq(_T_511, UInt<1>(0h0))
when _T_514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_511, UInt<1>(0h1), "") : assert_81
node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(_T_515, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_515, UInt<1>(0h1), "") : assert_82
node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_520 = or(UInt<1>(0h0), _T_519)
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_520, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_524, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_528, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_532, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_536 = eq(a_first, UInt<1>(0h0))
node _T_537 = and(io.in.a.valid, _T_536)
when _T_537 :
node _T_538 = eq(io.in.a.bits.opcode, opcode)
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_538, UInt<1>(0h1), "") : assert_87
node _T_542 = eq(io.in.a.bits.param, param)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_542, UInt<1>(0h1), "") : assert_88
node _T_546 = eq(io.in.a.bits.size, size)
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_546, UInt<1>(0h1), "") : assert_89
node _T_550 = eq(io.in.a.bits.source, source)
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_550, UInt<1>(0h1), "") : assert_90
node _T_554 = eq(io.in.a.bits.address, address)
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_554, UInt<1>(0h1), "") : assert_91
node _T_558 = and(io.in.a.ready, io.in.a.valid)
node _T_559 = and(_T_558, a_first)
when _T_559 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_560 = eq(d_first, UInt<1>(0h0))
node _T_561 = and(io.in.d.valid, _T_560)
when _T_561 :
node _T_562 = eq(io.in.d.bits.opcode, opcode_1)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_562, UInt<1>(0h1), "") : assert_92
node _T_566 = eq(io.in.d.bits.param, param_1)
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(_T_566, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_566, UInt<1>(0h1), "") : assert_93
node _T_570 = eq(io.in.d.bits.size, size_1)
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_570, UInt<1>(0h1), "") : assert_94
node _T_574 = eq(io.in.d.bits.source, source_1)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_574, UInt<1>(0h1), "") : assert_95
node _T_578 = eq(io.in.d.bits.sink, sink)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_578, UInt<1>(0h1), "") : assert_96
node _T_582 = eq(io.in.d.bits.denied, denied)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_582, UInt<1>(0h1), "") : assert_97
node _T_586 = and(io.in.d.ready, io.in.d.valid)
node _T_587 = and(_T_586, d_first)
when _T_587 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_588 = and(io.in.a.valid, a_first_1)
node _T_589 = and(_T_588, UInt<1>(0h1))
when _T_589 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_590 = and(io.in.a.ready, io.in.a.valid)
node _T_591 = and(_T_590, a_first_1)
node _T_592 = and(_T_591, UInt<1>(0h1))
when _T_592 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_593 = dshr(inflight, io.in.a.bits.source)
node _T_594 = bits(_T_593, 0, 0)
node _T_595 = eq(_T_594, UInt<1>(0h0))
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_595, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_599 = and(io.in.d.valid, d_first_1)
node _T_600 = and(_T_599, UInt<1>(0h1))
node _T_601 = eq(d_release_ack, UInt<1>(0h0))
node _T_602 = and(_T_600, _T_601)
when _T_602 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_603 = and(io.in.d.ready, io.in.d.valid)
node _T_604 = and(_T_603, d_first_1)
node _T_605 = and(_T_604, UInt<1>(0h1))
node _T_606 = eq(d_release_ack, UInt<1>(0h0))
node _T_607 = and(_T_605, _T_606)
when _T_607 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_608 = and(io.in.d.valid, d_first_1)
node _T_609 = and(_T_608, UInt<1>(0h1))
node _T_610 = eq(d_release_ack, UInt<1>(0h0))
node _T_611 = and(_T_609, _T_610)
when _T_611 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_612 = dshr(inflight, io.in.d.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = or(_T_613, same_cycle_resp)
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_614, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_620 = or(_T_618, _T_619)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_620, UInt<1>(0h1), "") : assert_100
node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(_T_624, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_624, UInt<1>(0h1), "") : assert_101
else :
node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_630 = or(_T_628, _T_629)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_630, UInt<1>(0h1), "") : assert_102
node _T_634 = eq(io.in.d.bits.size, a_size_lookup)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_634, UInt<1>(0h1), "") : assert_103
node _T_638 = and(io.in.d.valid, d_first_1)
node _T_639 = and(_T_638, a_first_1)
node _T_640 = and(_T_639, io.in.a.valid)
node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_642 = and(_T_640, _T_641)
node _T_643 = eq(d_release_ack, UInt<1>(0h0))
node _T_644 = and(_T_642, _T_643)
when _T_644 :
node _T_645 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_646 = or(_T_645, io.in.a.ready)
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_646, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_111
node _T_650 = orr(inflight)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_653 = or(_T_651, _T_652)
node _T_654 = lt(watchdog, plusarg_reader.out)
node _T_655 = or(_T_653, _T_654)
node _T_656 = asUInt(reset)
node _T_657 = eq(_T_656, UInt<1>(0h0))
when _T_657 :
node _T_658 = eq(_T_655, UInt<1>(0h0))
when _T_658 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_655, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_659 = and(io.in.a.ready, io.in.a.valid)
node _T_660 = and(io.in.d.ready, io.in.d.valid)
node _T_661 = or(_T_659, _T_660)
when _T_661 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<17>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<17>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_662 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<17>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_665 = and(_T_663, _T_664)
node _T_666 = and(_T_662, _T_665)
when _T_666 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<17>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_668 = and(_T_667, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<17>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<17>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_673 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_674 = bits(_T_673, 0, 0)
node _T_675 = eq(_T_674, UInt<1>(0h0))
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(_T_675, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_675, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_679 = and(io.in.d.valid, d_first_2)
node _T_680 = and(_T_679, UInt<1>(0h1))
node _T_681 = and(_T_680, d_release_ack_1)
when _T_681 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_682 = and(io.in.d.ready, io.in.d.valid)
node _T_683 = and(_T_682, d_first_2)
node _T_684 = and(_T_683, UInt<1>(0h1))
node _T_685 = and(_T_684, d_release_ack_1)
when _T_685 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_686 = and(io.in.d.valid, d_first_2)
node _T_687 = and(_T_686, UInt<1>(0h1))
node _T_688 = and(_T_687, d_release_ack_1)
when _T_688 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_689 = dshr(inflight_1, io.in.d.bits.source)
node _T_690 = bits(_T_689, 0, 0)
node _T_691 = or(_T_690, same_cycle_resp_1)
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(_T_691, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_691, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<17>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_696 = asUInt(reset)
node _T_697 = eq(_T_696, UInt<1>(0h0))
when _T_697 :
node _T_698 = eq(_T_695, UInt<1>(0h0))
when _T_698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_695, UInt<1>(0h1), "") : assert_108
else :
node _T_699 = eq(io.in.d.bits.size, c_size_lookup)
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(_T_699, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_699, UInt<1>(0h1), "") : assert_109
node _T_703 = and(io.in.d.valid, d_first_2)
node _T_704 = and(_T_703, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<17>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_705 = and(_T_704, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<17>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_707 = and(_T_705, _T_706)
node _T_708 = and(_T_707, d_release_ack_1)
node _T_709 = eq(c_probe_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<17>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_712 = or(_T_711, _WIRE_23.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_112
node _T_716 = orr(inflight_1)
node _T_717 = eq(_T_716, UInt<1>(0h0))
node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_719 = or(_T_717, _T_718)
node _T_720 = lt(watchdog_1, plusarg_reader_1.out)
node _T_721 = or(_T_719, _T_720)
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_721, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<17>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_726 = and(io.in.d.ready, io.in.d.valid)
node _T_727 = or(_T_725, _T_726)
when _T_727 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_55( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_659; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35]
assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_112 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_200
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_112( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_200 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c_5 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonIn.e.bits.sink
invalidate anonIn.e.valid
invalidate anonIn.e.ready
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.c.bits.corrupt
invalidate anonIn.c.bits.data
invalidate anonIn.c.bits.address
invalidate anonIn.c.bits.source
invalidate anonIn.c.bits.size
invalidate anonIn.c.bits.param
invalidate anonIn.c.bits.opcode
invalidate anonIn.c.valid
invalidate anonIn.c.ready
invalidate anonIn.b.bits.corrupt
invalidate anonIn.b.bits.data
invalidate anonIn.b.bits.mask
invalidate anonIn.b.bits.address
invalidate anonIn.b.bits.source
invalidate anonIn.b.bits.size
invalidate anonIn.b.bits.param
invalidate anonIn.b.bits.opcode
invalidate anonIn.b.valid
invalidate anonIn.b.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor_63
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, anonIn.e.bits.sink
connect monitor.io.in.e.valid, anonIn.e.valid
connect monitor.io.in.e.ready, anonIn.e.ready
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.c.bits.corrupt, anonIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, anonIn.c.bits.data
connect monitor.io.in.c.bits.address, anonIn.c.bits.address
connect monitor.io.in.c.bits.source, anonIn.c.bits.source
connect monitor.io.in.c.bits.size, anonIn.c.bits.size
connect monitor.io.in.c.bits.param, anonIn.c.bits.param
connect monitor.io.in.c.bits.opcode, anonIn.c.bits.opcode
connect monitor.io.in.c.valid, anonIn.c.valid
connect monitor.io.in.c.ready, anonIn.c.ready
connect monitor.io.in.b.bits.corrupt, anonIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, anonIn.b.bits.data
connect monitor.io.in.b.bits.mask, anonIn.b.bits.mask
connect monitor.io.in.b.bits.address, anonIn.b.bits.address
connect monitor.io.in.b.bits.source, anonIn.b.bits.source
connect monitor.io.in.b.bits.size, anonIn.b.bits.size
connect monitor.io.in.b.bits.param, anonIn.b.bits.param
connect monitor.io.in.b.bits.opcode, anonIn.b.bits.opcode
connect monitor.io.in.b.valid, anonIn.b.valid
connect monitor.io.in.b.ready, anonIn.b.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_64
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonOut.e.bits.sink
invalidate anonOut.e.valid
invalidate anonOut.e.ready
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.c.bits.corrupt
invalidate anonOut.c.bits.data
invalidate anonOut.c.bits.address
invalidate anonOut.c.bits.source
invalidate anonOut.c.bits.size
invalidate anonOut.c.bits.param
invalidate anonOut.c.bits.opcode
invalidate anonOut.c.valid
invalidate anonOut.c.ready
invalidate anonOut.b.bits.corrupt
invalidate anonOut.b.bits.data
invalidate anonOut.b.bits.mask
invalidate anonOut.b.bits.address
invalidate anonOut.b.bits.source
invalidate anonOut.b.bits.size
invalidate anonOut.b.bits.param
invalidate anonOut.b.bits.opcode
invalidate anonOut.b.valid
invalidate anonOut.b.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
connect anonIn.b.bits.corrupt, in[0].b.bits.corrupt
connect anonIn.b.bits.data, in[0].b.bits.data
connect anonIn.b.bits.mask, in[0].b.bits.mask
connect anonIn.b.bits.address, in[0].b.bits.address
connect anonIn.b.bits.source, in[0].b.bits.source
connect anonIn.b.bits.size, in[0].b.bits.size
connect anonIn.b.bits.param, in[0].b.bits.param
connect anonIn.b.bits.opcode, in[0].b.bits.opcode
connect anonIn.b.valid, in[0].b.valid
connect in[0].b.ready, anonIn.b.ready
node _anonIn_b_bits_source_T = bits(in[0].b.bits.source, 0, 0)
connect anonIn.b.bits.source, _anonIn_b_bits_source_T
connect in[0].c.bits.corrupt, anonIn.c.bits.corrupt
connect in[0].c.bits.data, anonIn.c.bits.data
connect in[0].c.bits.address, anonIn.c.bits.address
connect in[0].c.bits.source, anonIn.c.bits.source
connect in[0].c.bits.size, anonIn.c.bits.size
connect in[0].c.bits.param, anonIn.c.bits.param
connect in[0].c.bits.opcode, anonIn.c.bits.opcode
connect in[0].c.valid, anonIn.c.valid
connect anonIn.c.ready, in[0].c.ready
node _in_0_c_bits_source_T = or(anonIn.c.bits.source, UInt<1>(0h0))
connect in[0].c.bits.source, _in_0_c_bits_source_T
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 0, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
connect in[0].e.bits.sink, anonIn.e.bits.sink
connect in[0].e.valid, anonIn.e.valid
connect anonIn.e.ready, in[0].e.ready
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<2>(0h2))
connect in[1].a.bits.source, _in_1_a_bits_source_T
invalidate in[1].b.bits.corrupt
invalidate in[1].b.bits.data
invalidate in[1].b.bits.mask
invalidate in[1].b.bits.address
invalidate in[1].b.bits.source
invalidate in[1].b.bits.size
invalidate in[1].b.bits.param
invalidate in[1].b.bits.opcode
invalidate in[1].b.valid
invalidate in[1].b.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
connect in[1].b.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
invalidate in[1].c.bits.corrupt
invalidate in[1].c.bits.data
invalidate in[1].c.bits.address
invalidate in[1].c.bits.source
invalidate in[1].c.bits.size
invalidate in[1].c.bits.param
invalidate in[1].c.bits.opcode
invalidate in[1].c.valid
invalidate in[1].c.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<1>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
invalidate _WIRE_5.bits.corrupt
invalidate _WIRE_5.bits.data
invalidate _WIRE_5.bits.address
invalidate _WIRE_5.bits.source
invalidate _WIRE_5.bits.size
invalidate _WIRE_5.bits.param
invalidate _WIRE_5.bits.opcode
invalidate _WIRE_5.valid
invalidate _WIRE_5.ready
connect in[1].c.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
connect anonIn_1.d.bits.source, UInt<1>(0h0)
invalidate in[1].e.bits.sink
invalidate in[1].e.valid
invalidate in[1].e.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits.sink, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.sink
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
connect in[1].e.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
connect out[0].b.bits.corrupt, anonOut.b.bits.corrupt
connect out[0].b.bits.data, anonOut.b.bits.data
connect out[0].b.bits.mask, anonOut.b.bits.mask
connect out[0].b.bits.address, anonOut.b.bits.address
connect out[0].b.bits.source, anonOut.b.bits.source
connect out[0].b.bits.size, anonOut.b.bits.size
connect out[0].b.bits.param, anonOut.b.bits.param
connect out[0].b.bits.opcode, anonOut.b.bits.opcode
connect out[0].b.valid, anonOut.b.valid
connect anonOut.b.ready, out[0].b.ready
connect anonOut.c.bits.corrupt, out[0].c.bits.corrupt
connect anonOut.c.bits.data, out[0].c.bits.data
connect anonOut.c.bits.address, out[0].c.bits.address
connect anonOut.c.bits.source, out[0].c.bits.source
connect anonOut.c.bits.size, out[0].c.bits.size
connect anonOut.c.bits.param, out[0].c.bits.param
connect anonOut.c.bits.opcode, out[0].c.bits.opcode
connect anonOut.c.valid, out[0].c.valid
connect out[0].c.ready, anonOut.c.ready
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
connect anonOut.e.bits.sink, out[0].e.bits.sink
connect anonOut.e.valid, out[0].e.valid
connect out[0].e.ready, anonOut.e.ready
node _anonOut_e_bits_sink_T = bits(out[0].e.bits.sink, 2, 0)
connect anonOut.e.bits.sink, _anonOut_e_bits_sink_T
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<1>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 0, 0)
node _requestBOI_T = shr(out[0].b.bits.source, 1)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<1>(0h1))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
node requestBOI_0_1 = eq(out[0].b.bits.source, UInt<2>(0h2))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<1>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 0, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 1)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<1>(0h1))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<2>(0h2))
node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0)
node _requestEIO_T = shr(in[0].e.bits.sink, 3)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7))
node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4)
node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0)
node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7))
node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[0].bits.data, out[0].b.bits.data
connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[0].bits.address, out[0].b.bits.address
connect portsBIO_filtered[0].bits.source, out[0].b.bits.source
connect portsBIO_filtered[0].bits.size, out[0].b.bits.size
connect portsBIO_filtered[0].bits.param, out[0].b.bits.param
connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[1].bits.data, out[0].b.bits.data
connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[1].bits.address, out[0].b.bits.address
connect portsBIO_filtered[1].bits.source, out[0].b.bits.source
connect portsBIO_filtered[1].bits.size, out[0].b.bits.size
connect portsBIO_filtered[1].bits.param, out[0].b.bits.param
connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1)
wire _portsBIO_out_0_b_ready_WIRE : UInt<1>
connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2
connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, in[0].c.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect in[0].c.ready, portsCOI_filtered[0].ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, in[1].c.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect in[1].c.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1]
connect portsEOI_filtered[0].bits, in[0].e.bits
node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect in[0].e.ready, portsEOI_filtered[0].ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1]
connect portsEOI_filtered_1[0].bits, in[1].e.bits
node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect in[1].e.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<2>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
connect out[0].c, portsCOI_filtered[0]
connect out[0].e, portsEOI_filtered[0]
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
connect in[0].b, portsBIO_filtered[0]
connect in[0].d, portsDIO_filtered[0]
invalidate in[1].b.bits.corrupt
invalidate in[1].b.bits.data
invalidate in[1].b.bits.mask
invalidate in[1].b.bits.address
invalidate in[1].b.bits.source
invalidate in[1].b.bits.size
invalidate in[1].b.bits.param
invalidate in[1].b.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0) | module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c_5( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire [2:0] out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [1:0] in_0_c_bits_source; // @[Xbar.scala:159:18]
wire [1:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17]
wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17]
wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24]
wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73]
wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18]
wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:159:18]
wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [63:0] auto_anon_in_1_a_bits_data = 64'h0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] in_1_a_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_1_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _out_0_a_bits_T_4 = 64'h0; // @[Mux.scala:30:73]
wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69]
wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_1_b_bits_source = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_1_c_bits_source = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] portsCOI_filtered_1_0_bits_source = 2'h0; // @[Xbar.scala:352:24]
wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [1:0] in_1_a_bits_source = 2'h2; // @[Xbar.scala:159:18]
wire [1:0] _in_1_a_bits_source_T = 2'h2; // @[Xbar.scala:166:55]
wire [1:0] portsAOI_filtered_1_0_bits_source = 2'h2; // @[Xbar.scala:352:24]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [8:0] beatsAI_decode_1 = 9'h7; // @[Edges.scala:220:59]
wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [7:0] in_1_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9]
wire anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_c_ready; // @[MixedNode.scala:551:17]
wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9]
wire anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_e_ready; // @[MixedNode.scala:551:17]
wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_b_ready; // @[MixedNode.scala:542:17]
wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9]
wire anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9]
wire anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18]
wire in_0_b_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9]
wire _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_0_b_bits_mask; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_0_b_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9]
wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9]
wire in_0_c_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9]
wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_0_e_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9]
wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [1:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_b_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9]
wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19]
wire [1:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19]
wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire [7:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19]
wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19]
wire out_0_c_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9]
wire [1:0] out_0_c_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] out_0_c_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19]
wire out_0_e_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9]
wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [1:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18]
wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18]
wire [1:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18]
wire [7:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24]
assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18]
wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18]
wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [1:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [2:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18]
wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire [2:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [1:0] in_0_b_bits_source; // @[Xbar.scala:159:18]
wire [1:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [1:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_b_bits_source_T = in_0_b_bits_source[0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [1:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19]
assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [1:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19]
assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
wire [7:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19]
assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19]
assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19]
assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19]
assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19]
assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [1:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24]
wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19]
assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire requestBOI_uncommonBits = _requestBOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}]
wire _requestBOI_T = out_0_b_bits_source[1]; // @[Xbar.scala:216:19]
wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54]
wire requestBOI_0_1 = out_0_b_bits_source == 2'h2; // @[Xbar.scala:216:19]
wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54]
wire requestDOI_uncommonBits = _requestDOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[1]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire requestDOI_0_1 = out_0_d_bits_source == 2'h2; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73]
wire [2:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsBO_decode = _beatsBO_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19]
wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}]
wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsCI_decode = _beatsCI_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [8:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73]
assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73]
assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
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